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-rw-r--r--drivers/ata/pata_pdc2027x.c869
1 files changed, 869 insertions, 0 deletions
diff --git a/drivers/ata/pata_pdc2027x.c b/drivers/ata/pata_pdc2027x.c
new file mode 100644
index 000000000000..56b8c1ee2937
--- /dev/null
+++ b/drivers/ata/pata_pdc2027x.c
@@ -0,0 +1,869 @@
1/*
2 * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Ported to libata by:
10 * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
11 *
12 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 *
15 * Author: Frank Tiernan (frankt@promise.com)
16 * Released under terms of General Public License
17 *
18 *
19 * libata documentation is available via 'make {ps|pdf}docs',
20 * as Documentation/DocBook/libata.*
21 *
22 * Hardware information only available under NDA.
23 *
24 */
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/blkdev.h>
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <scsi/scsi.h>
33#include <scsi/scsi_host.h>
34#include <scsi/scsi_cmnd.h>
35#include <linux/libata.h>
36#include <asm/io.h>
37
38#define DRV_NAME "pata_pdc2027x"
39#define DRV_VERSION "0.74-ac3"
40#undef PDC_DEBUG
41
42#ifdef PDC_DEBUG
43#define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
44#else
45#define PDPRINTK(fmt, args...)
46#endif
47
48enum {
49 PDC_UDMA_100 = 0,
50 PDC_UDMA_133 = 1,
51
52 PDC_100_MHZ = 100000000,
53 PDC_133_MHZ = 133333333,
54
55 PDC_SYS_CTL = 0x1100,
56 PDC_ATA_CTL = 0x1104,
57 PDC_GLOBAL_CTL = 0x1108,
58 PDC_CTCR0 = 0x110C,
59 PDC_CTCR1 = 0x1110,
60 PDC_BYTE_COUNT = 0x1120,
61 PDC_PLL_CTL = 0x1202,
62};
63
64static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
65static void pdc2027x_remove_one(struct pci_dev *pdev);
66static void pdc2027x_error_handler(struct ata_port *ap);
67static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
68static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
69static void pdc2027x_post_set_mode(struct ata_port *ap);
70static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
71
72/*
73 * ATA Timing Tables based on 133MHz controller clock.
74 * These tables are only used when the controller is in 133MHz clock.
75 * If the controller is in 100MHz clock, the ASIC hardware will
76 * set the timing registers automatically when "set feature" command
77 * is issued to the device. However, if the controller clock is 133MHz,
78 * the following tables must be used.
79 */
80static struct pdc2027x_pio_timing {
81 u8 value0, value1, value2;
82} pdc2027x_pio_timing_tbl [] = {
83 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
84 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
85 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
86 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
87 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
88};
89
90static struct pdc2027x_mdma_timing {
91 u8 value0, value1;
92} pdc2027x_mdma_timing_tbl [] = {
93 { 0xdf, 0x5f }, /* MDMA mode 0 */
94 { 0x6b, 0x27 }, /* MDMA mode 1 */
95 { 0x69, 0x25 }, /* MDMA mode 2 */
96};
97
98static struct pdc2027x_udma_timing {
99 u8 value0, value1, value2;
100} pdc2027x_udma_timing_tbl [] = {
101 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
102 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
103 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
104 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
105 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
106 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
107 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
108};
109
110static const struct pci_device_id pdc2027x_pci_tbl[] = {
111 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_100 },
112 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
113 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_100 },
114 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
115 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
116 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
117 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
118 { } /* terminate list */
119};
120
121static struct pci_driver pdc2027x_pci_driver = {
122 .name = DRV_NAME,
123 .id_table = pdc2027x_pci_tbl,
124 .probe = pdc2027x_init_one,
125 .remove = __devexit_p(pdc2027x_remove_one),
126};
127
128static struct scsi_host_template pdc2027x_sht = {
129 .module = THIS_MODULE,
130 .name = DRV_NAME,
131 .ioctl = ata_scsi_ioctl,
132 .queuecommand = ata_scsi_queuecmd,
133 .can_queue = ATA_DEF_QUEUE,
134 .this_id = ATA_SHT_THIS_ID,
135 .sg_tablesize = LIBATA_MAX_PRD,
136 .max_sectors = ATA_MAX_SECTORS,
137 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
138 .emulated = ATA_SHT_EMULATED,
139 .use_clustering = ATA_SHT_USE_CLUSTERING,
140 .proc_name = DRV_NAME,
141 .dma_boundary = ATA_DMA_BOUNDARY,
142 .slave_configure = ata_scsi_slave_config,
143 .bios_param = ata_std_bios_param,
144};
145
146static struct ata_port_operations pdc2027x_pata100_ops = {
147 .port_disable = ata_port_disable,
148
149 .tf_load = ata_tf_load,
150 .tf_read = ata_tf_read,
151 .check_status = ata_check_status,
152 .exec_command = ata_exec_command,
153 .dev_select = ata_std_dev_select,
154
155 .check_atapi_dma = pdc2027x_check_atapi_dma,
156 .bmdma_setup = ata_bmdma_setup,
157 .bmdma_start = ata_bmdma_start,
158 .bmdma_stop = ata_bmdma_stop,
159 .bmdma_status = ata_bmdma_status,
160 .qc_prep = ata_qc_prep,
161 .qc_issue = ata_qc_issue_prot,
162 .data_xfer = ata_mmio_data_xfer,
163
164 .freeze = ata_bmdma_freeze,
165 .thaw = ata_bmdma_thaw,
166 .error_handler = pdc2027x_error_handler,
167 .post_internal_cmd = ata_bmdma_post_internal_cmd,
168
169 .irq_handler = ata_interrupt,
170 .irq_clear = ata_bmdma_irq_clear,
171
172 .port_start = ata_port_start,
173 .port_stop = ata_port_stop,
174 .host_stop = ata_pci_host_stop,
175};
176
177static struct ata_port_operations pdc2027x_pata133_ops = {
178 .port_disable = ata_port_disable,
179 .set_piomode = pdc2027x_set_piomode,
180 .set_dmamode = pdc2027x_set_dmamode,
181 .post_set_mode = pdc2027x_post_set_mode,
182
183 .tf_load = ata_tf_load,
184 .tf_read = ata_tf_read,
185 .check_status = ata_check_status,
186 .exec_command = ata_exec_command,
187 .dev_select = ata_std_dev_select,
188
189 .check_atapi_dma = pdc2027x_check_atapi_dma,
190 .bmdma_setup = ata_bmdma_setup,
191 .bmdma_start = ata_bmdma_start,
192 .bmdma_stop = ata_bmdma_stop,
193 .bmdma_status = ata_bmdma_status,
194 .qc_prep = ata_qc_prep,
195 .qc_issue = ata_qc_issue_prot,
196 .data_xfer = ata_mmio_data_xfer,
197
198 .freeze = ata_bmdma_freeze,
199 .thaw = ata_bmdma_thaw,
200 .error_handler = pdc2027x_error_handler,
201 .post_internal_cmd = ata_bmdma_post_internal_cmd,
202
203 .irq_handler = ata_interrupt,
204 .irq_clear = ata_bmdma_irq_clear,
205
206 .port_start = ata_port_start,
207 .port_stop = ata_port_stop,
208 .host_stop = ata_pci_host_stop,
209};
210
211static struct ata_port_info pdc2027x_port_info[] = {
212 /* PDC_UDMA_100 */
213 {
214 .sht = &pdc2027x_sht,
215 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
216 ATA_FLAG_MMIO,
217 .pio_mask = 0x1f, /* pio0-4 */
218 .mwdma_mask = 0x07, /* mwdma0-2 */
219 .udma_mask = ATA_UDMA5, /* udma0-5 */
220 .port_ops = &pdc2027x_pata100_ops,
221 },
222 /* PDC_UDMA_133 */
223 {
224 .sht = &pdc2027x_sht,
225 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
226 ATA_FLAG_MMIO,
227 .pio_mask = 0x1f, /* pio0-4 */
228 .mwdma_mask = 0x07, /* mwdma0-2 */
229 .udma_mask = ATA_UDMA6, /* udma0-6 */
230 .port_ops = &pdc2027x_pata133_ops,
231 },
232};
233
234MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
235MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
236MODULE_LICENSE("GPL");
237MODULE_VERSION(DRV_VERSION);
238MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
239
240/**
241 * port_mmio - Get the MMIO address of PDC2027x extended registers
242 * @ap: Port
243 * @offset: offset from mmio base
244 */
245static inline void* port_mmio(struct ata_port *ap, unsigned int offset)
246{
247 return ap->host->mmio_base + ap->port_no * 0x100 + offset;
248}
249
250/**
251 * dev_mmio - Get the MMIO address of PDC2027x extended registers
252 * @ap: Port
253 * @adev: device
254 * @offset: offset from mmio base
255 */
256static inline void* dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
257{
258 u8 adj = (adev->devno) ? 0x08 : 0x00;
259 return port_mmio(ap, offset) + adj;
260}
261
262/**
263 * pdc2027x_pata_cbl_detect - Probe host controller cable detect info
264 * @ap: Port for which cable detect info is desired
265 *
266 * Read 80c cable indicator from Promise extended register.
267 * This register is latched when the system is reset.
268 *
269 * LOCKING:
270 * None (inherited from caller).
271 */
272static void pdc2027x_cbl_detect(struct ata_port *ap)
273{
274 u32 cgcr;
275
276 /* check cable detect results */
277 cgcr = readl(port_mmio(ap, PDC_GLOBAL_CTL));
278 if (cgcr & (1 << 26))
279 goto cbl40;
280
281 PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
282
283 ap->cbl = ATA_CBL_PATA80;
284 return;
285
286cbl40:
287 printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
288 ap->cbl = ATA_CBL_PATA40;
289 ap->udma_mask &= ATA_UDMA_MASK_40C;
290}
291
292/**
293 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
294 * @ap: Port to check
295 */
296static inline int pdc2027x_port_enabled(struct ata_port *ap)
297{
298 return readb(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
299}
300
301/**
302 * pdc2027x_prereset - prereset for PATA host controller
303 * @ap: Target port
304 *
305 * Probeinit including cable detection.
306 *
307 * LOCKING:
308 * None (inherited from caller).
309 */
310
311static int pdc2027x_prereset(struct ata_port *ap)
312{
313 /* Check whether port enabled */
314 if (!pdc2027x_port_enabled(ap)) {
315 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
316 return 0;
317 }
318 pdc2027x_cbl_detect(ap);
319 return ata_std_prereset(ap);
320}
321
322/**
323 * pdc2027x_error_handler - Perform reset on PATA port and classify
324 * @ap: Port to reset
325 *
326 * Reset PATA phy and classify attached devices.
327 *
328 * LOCKING:
329 * None (inherited from caller).
330 */
331
332static void pdc2027x_error_handler(struct ata_port *ap)
333{
334 ata_bmdma_drive_eh(ap, pdc2027x_prereset, ata_std_softreset, NULL, ata_std_postreset);
335}
336
337/**
338 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
339 * @ap: Port to configure
340 * @adev: um
341 * @pio: PIO mode, 0 - 4
342 *
343 * Set PIO mode for device.
344 *
345 * LOCKING:
346 * None (inherited from caller).
347 */
348
349static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
350{
351 unsigned int pio = adev->pio_mode - XFER_PIO_0;
352 u32 ctcr0, ctcr1;
353
354 PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
355
356 /* Sanity check */
357 if (pio > 4) {
358 printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
359 return;
360
361 }
362
363 /* Set the PIO timing registers using value table for 133MHz */
364 PDPRINTK("Set pio regs... \n");
365
366 ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0));
367 ctcr0 &= 0xffff0000;
368 ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
369 (pdc2027x_pio_timing_tbl[pio].value1 << 8);
370 writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
371
372 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
373 ctcr1 &= 0x00ffffff;
374 ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
375 writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
376
377 PDPRINTK("Set pio regs done\n");
378
379 PDPRINTK("Set to pio mode[%u] \n", pio);
380}
381
382/**
383 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
384 * @ap: Port to configure
385 * @adev: um
386 * @udma: udma mode, XFER_UDMA_0 to XFER_UDMA_6
387 *
388 * Set UDMA mode for device.
389 *
390 * LOCKING:
391 * None (inherited from caller).
392 */
393static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
394{
395 unsigned int dma_mode = adev->dma_mode;
396 u32 ctcr0, ctcr1;
397
398 if ((dma_mode >= XFER_UDMA_0) &&
399 (dma_mode <= XFER_UDMA_6)) {
400 /* Set the UDMA timing registers with value table for 133MHz */
401 unsigned int udma_mode = dma_mode & 0x07;
402
403 if (dma_mode == XFER_UDMA_2) {
404 /*
405 * Turn off tHOLD.
406 * If tHOLD is '1', the hardware will add half clock for data hold time.
407 * This code segment seems to be no effect. tHOLD will be overwritten below.
408 */
409 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
410 writel(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
411 }
412
413 PDPRINTK("Set udma regs... \n");
414
415 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
416 ctcr1 &= 0xff000000;
417 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
418 (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
419 (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
420 writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
421
422 PDPRINTK("Set udma regs done\n");
423
424 PDPRINTK("Set to udma mode[%u] \n", udma_mode);
425
426 } else if ((dma_mode >= XFER_MW_DMA_0) &&
427 (dma_mode <= XFER_MW_DMA_2)) {
428 /* Set the MDMA timing registers with value table for 133MHz */
429 unsigned int mdma_mode = dma_mode & 0x07;
430
431 PDPRINTK("Set mdma regs... \n");
432 ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0));
433
434 ctcr0 &= 0x0000ffff;
435 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
436 (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
437
438 writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
439 PDPRINTK("Set mdma regs done\n");
440
441 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
442 } else {
443 printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
444 }
445}
446
447/**
448 * pdc2027x_post_set_mode - Set the timing registers back to correct values.
449 * @ap: Port to configure
450 *
451 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
452 * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
453 * This function overwrites the possibly incorrect values set by the hardware to be correct.
454 */
455static void pdc2027x_post_set_mode(struct ata_port *ap)
456{
457 int i;
458
459 for (i = 0; i < ATA_MAX_DEVICES; i++) {
460 struct ata_device *dev = &ap->device[i];
461
462 if (ata_dev_enabled(dev)) {
463
464 pdc2027x_set_piomode(ap, dev);
465
466 /*
467 * Enable prefetch if the device support PIO only.
468 */
469 if (dev->xfer_shift == ATA_SHIFT_PIO) {
470 u32 ctcr1 = readl(dev_mmio(ap, dev, PDC_CTCR1));
471 ctcr1 |= (1 << 25);
472 writel(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
473
474 PDPRINTK("Turn on prefetch\n");
475 } else {
476 pdc2027x_set_dmamode(ap, dev);
477 }
478 }
479 }
480}
481
482/**
483 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
484 * @qc: Metadata associated with taskfile to check
485 *
486 * LOCKING:
487 * None (inherited from caller).
488 *
489 * RETURNS: 0 when ATAPI DMA can be used
490 * 1 otherwise
491 */
492static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
493{
494 struct scsi_cmnd *cmd = qc->scsicmd;
495 u8 *scsicmd = cmd->cmnd;
496 int rc = 1; /* atapi dma off by default */
497
498 /*
499 * This workaround is from Promise's GPL driver.
500 * If ATAPI DMA is used for commands not in the
501 * following white list, say MODE_SENSE and REQUEST_SENSE,
502 * pdc2027x might hit the irq lost problem.
503 */
504 switch (scsicmd[0]) {
505 case READ_10:
506 case WRITE_10:
507 case READ_12:
508 case WRITE_12:
509 case READ_6:
510 case WRITE_6:
511 case 0xad: /* READ_DVD_STRUCTURE */
512 case 0xbe: /* READ_CD */
513 /* ATAPI DMA is ok */
514 rc = 0;
515 break;
516 default:
517 ;
518 }
519
520 return rc;
521}
522
523/**
524 * pdc_read_counter - Read the ctr counter
525 * @probe_ent: for the port address
526 */
527
528static long pdc_read_counter(struct ata_probe_ent *probe_ent)
529{
530 long counter;
531 int retry = 1;
532 u32 bccrl, bccrh, bccrlv, bccrhv;
533
534retry:
535 bccrl = readl(probe_ent->mmio_base + PDC_BYTE_COUNT) & 0xffff;
536 bccrh = readl(probe_ent->mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff;
537 rmb();
538
539 /* Read the counter values again for verification */
540 bccrlv = readl(probe_ent->mmio_base + PDC_BYTE_COUNT) & 0xffff;
541 bccrhv = readl(probe_ent->mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff;
542 rmb();
543
544 counter = (bccrh << 15) | bccrl;
545
546 PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl);
547 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
548
549 /*
550 * The 30-bit decreasing counter are read by 2 pieces.
551 * Incorrect value may be read when both bccrh and bccrl are changing.
552 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
553 */
554 if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
555 retry--;
556 PDPRINTK("rereading counter\n");
557 goto retry;
558 }
559
560 return counter;
561}
562
563/**
564 * adjust_pll - Adjust the PLL input clock in Hz.
565 *
566 * @pdc_controller: controller specific information
567 * @probe_ent: For the port address
568 * @pll_clock: The input of PLL in HZ
569 */
570static void pdc_adjust_pll(struct ata_probe_ent *probe_ent, long pll_clock, unsigned int board_idx)
571{
572
573 u16 pll_ctl;
574 long pll_clock_khz = pll_clock / 1000;
575 long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
576 long ratio = pout_required / pll_clock_khz;
577 int F, R;
578
579 /* Sanity check */
580 if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
581 printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
582 return;
583 }
584
585#ifdef PDC_DEBUG
586 PDPRINTK("pout_required is %ld\n", pout_required);
587
588 /* Show the current clock value of PLL control register
589 * (maybe already configured by the firmware)
590 */
591 pll_ctl = readw(probe_ent->mmio_base + PDC_PLL_CTL);
592
593 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
594#endif
595
596 /*
597 * Calculate the ratio of F, R and OD
598 * POUT = (F + 2) / (( R + 2) * NO)
599 */
600 if (ratio < 8600L) { /* 8.6x */
601 /* Using NO = 0x01, R = 0x0D */
602 R = 0x0d;
603 } else if (ratio < 12900L) { /* 12.9x */
604 /* Using NO = 0x01, R = 0x08 */
605 R = 0x08;
606 } else if (ratio < 16100L) { /* 16.1x */
607 /* Using NO = 0x01, R = 0x06 */
608 R = 0x06;
609 } else if (ratio < 64000L) { /* 64x */
610 R = 0x00;
611 } else {
612 /* Invalid ratio */
613 printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
614 return;
615 }
616
617 F = (ratio * (R+2)) / 1000 - 2;
618
619 if (unlikely(F < 0 || F > 127)) {
620 /* Invalid F */
621 printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
622 return;
623 }
624
625 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
626
627 pll_ctl = (R << 8) | F;
628
629 PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
630
631 writew(pll_ctl, probe_ent->mmio_base + PDC_PLL_CTL);
632 readw(probe_ent->mmio_base + PDC_PLL_CTL); /* flush */
633
634 /* Wait the PLL circuit to be stable */
635 mdelay(30);
636
637#ifdef PDC_DEBUG
638 /*
639 * Show the current clock value of PLL control register
640 * (maybe configured by the firmware)
641 */
642 pll_ctl = readw(probe_ent->mmio_base + PDC_PLL_CTL);
643
644 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
645#endif
646
647 return;
648}
649
650/**
651 * detect_pll_input_clock - Detect the PLL input clock in Hz.
652 * @probe_ent: for the port address
653 * Ex. 16949000 on 33MHz PCI bus for pdc20275.
654 * Half of the PCI clock.
655 */
656static long pdc_detect_pll_input_clock(struct ata_probe_ent *probe_ent)
657{
658 u32 scr;
659 long start_count, end_count;
660 long pll_clock;
661
662 /* Read current counter value */
663 start_count = pdc_read_counter(probe_ent);
664
665 /* Start the test mode */
666 scr = readl(probe_ent->mmio_base + PDC_SYS_CTL);
667 PDPRINTK("scr[%X]\n", scr);
668 writel(scr | (0x01 << 14), probe_ent->mmio_base + PDC_SYS_CTL);
669 readl(probe_ent->mmio_base + PDC_SYS_CTL); /* flush */
670
671 /* Let the counter run for 100 ms. */
672 mdelay(100);
673
674 /* Read the counter values again */
675 end_count = pdc_read_counter(probe_ent);
676
677 /* Stop the test mode */
678 scr = readl(probe_ent->mmio_base + PDC_SYS_CTL);
679 PDPRINTK("scr[%X]\n", scr);
680 writel(scr & ~(0x01 << 14), probe_ent->mmio_base + PDC_SYS_CTL);
681 readl(probe_ent->mmio_base + PDC_SYS_CTL); /* flush */
682
683 /* calculate the input clock in Hz */
684 pll_clock = (start_count - end_count) * 10;
685
686 PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
687 PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
688
689 return pll_clock;
690}
691
692/**
693 * pdc_hardware_init - Initialize the hardware.
694 * @pdev: instance of pci_dev found
695 * @pdc_controller: controller specific information
696 * @pe: for the port address
697 */
698static int pdc_hardware_init(struct pci_dev *pdev, struct ata_probe_ent *pe, unsigned int board_idx)
699{
700 long pll_clock;
701
702 /*
703 * Detect PLL input clock rate.
704 * On some system, where PCI bus is running at non-standard clock rate.
705 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
706 * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
707 */
708 pll_clock = pdc_detect_pll_input_clock(pe);
709
710 if (pll_clock < 0) /* counter overflow? Try again. */
711 pll_clock = pdc_detect_pll_input_clock(pe);
712
713 dev_printk(KERN_INFO, &pdev->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
714
715 /* Adjust PLL control register */
716 pdc_adjust_pll(pe, pll_clock, board_idx);
717
718 return 0;
719}
720
721/**
722 * pdc_ata_setup_port - setup the mmio address
723 * @port: ata ioports to setup
724 * @base: base address
725 */
726static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
727{
728 port->cmd_addr =
729 port->data_addr = base;
730 port->feature_addr =
731 port->error_addr = base + 0x05;
732 port->nsect_addr = base + 0x0a;
733 port->lbal_addr = base + 0x0f;
734 port->lbam_addr = base + 0x10;
735 port->lbah_addr = base + 0x15;
736 port->device_addr = base + 0x1a;
737 port->command_addr =
738 port->status_addr = base + 0x1f;
739 port->altstatus_addr =
740 port->ctl_addr = base + 0x81a;
741}
742
743/**
744 * pdc2027x_init_one - PCI probe function
745 * Called when an instance of PCI adapter is inserted.
746 * This function checks whether the hardware is supported,
747 * initialize hardware and register an instance of ata_host to
748 * libata by providing struct ata_probe_ent and ata_device_add().
749 * (implements struct pci_driver.probe() )
750 *
751 * @pdev: instance of pci_dev found
752 * @ent: matching entry in the id_tbl[]
753 */
754static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
755{
756 static int printed_version;
757 unsigned int board_idx = (unsigned int) ent->driver_data;
758
759 struct ata_probe_ent *probe_ent = NULL;
760 unsigned long base;
761 void *mmio_base;
762 int rc;
763
764 if (!printed_version++)
765 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
766
767 rc = pci_enable_device(pdev);
768 if (rc)
769 return rc;
770
771 rc = pci_request_regions(pdev, DRV_NAME);
772 if (rc)
773 goto err_out;
774
775 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
776 if (rc)
777 goto err_out_regions;
778
779 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
780 if (rc)
781 goto err_out_regions;
782
783 /* Prepare the probe entry */
784 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
785 if (probe_ent == NULL) {
786 rc = -ENOMEM;
787 goto err_out_regions;
788 }
789
790 probe_ent->dev = pci_dev_to_dev(pdev);
791 INIT_LIST_HEAD(&probe_ent->node);
792
793 mmio_base = pci_iomap(pdev, 5, 0);
794 if (!mmio_base) {
795 rc = -ENOMEM;
796 goto err_out_free_ent;
797 }
798
799 base = (unsigned long) mmio_base;
800
801 probe_ent->sht = pdc2027x_port_info[board_idx].sht;
802 probe_ent->port_flags = pdc2027x_port_info[board_idx].flags;
803 probe_ent->pio_mask = pdc2027x_port_info[board_idx].pio_mask;
804 probe_ent->mwdma_mask = pdc2027x_port_info[board_idx].mwdma_mask;
805 probe_ent->udma_mask = pdc2027x_port_info[board_idx].udma_mask;
806 probe_ent->port_ops = pdc2027x_port_info[board_idx].port_ops;
807
808 probe_ent->irq = pdev->irq;
809 probe_ent->irq_flags = SA_SHIRQ;
810 probe_ent->mmio_base = mmio_base;
811
812 pdc_ata_setup_port(&probe_ent->port[0], base + 0x17c0);
813 probe_ent->port[0].bmdma_addr = base + 0x1000;
814 pdc_ata_setup_port(&probe_ent->port[1], base + 0x15c0);
815 probe_ent->port[1].bmdma_addr = base + 0x1008;
816
817 probe_ent->n_ports = 2;
818
819 pci_set_master(pdev);
820 //pci_enable_intx(pdev);
821
822 /* initialize adapter */
823 if (pdc_hardware_init(pdev, probe_ent, board_idx) != 0)
824 goto err_out_free_ent;
825
826 ata_device_add(probe_ent);
827 kfree(probe_ent);
828
829 return 0;
830
831err_out_free_ent:
832 kfree(probe_ent);
833err_out_regions:
834 pci_release_regions(pdev);
835err_out:
836 pci_disable_device(pdev);
837 return rc;
838}
839
840/**
841 * pdc2027x_remove_one - Called to remove a single instance of the
842 * adapter.
843 *
844 * @dev: The PCI device to remove.
845 * FIXME: module load/unload not working yet
846 */
847static void __devexit pdc2027x_remove_one(struct pci_dev *pdev)
848{
849 ata_pci_remove_one(pdev);
850}
851
852/**
853 * pdc2027x_init - Called after this module is loaded into the kernel.
854 */
855static int __init pdc2027x_init(void)
856{
857 return pci_module_init(&pdc2027x_pci_driver);
858}
859
860/**
861 * pdc2027x_exit - Called before this module unloaded from the kernel
862 */
863static void __exit pdc2027x_exit(void)
864{
865 pci_unregister_driver(&pdc2027x_pci_driver);
866}
867
868module_init(pdc2027x_init);
869module_exit(pdc2027x_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 05:08:32 -0500