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-rw-r--r--drivers/ata/pata_oldpiix.c339
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diff --git a/drivers/ata/pata_oldpiix.c b/drivers/ata/pata_oldpiix.c
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1/*
2 * pata_oldpiix.c - Intel PATA/SATA controllers
3 *
4 * (C) 2005 Red Hat <alan@redhat.com>
5 *
6 * Some parts based on ata_piix.c by Jeff Garzik and others.
7 *
8 * Early PIIX differs significantly from the later PIIX as it lacks
9 * SITRE and the slave timing registers. This means that you have to
10 * set timing per channel, or be clever. Libata tells us whenever it
11 * does drive selection and we use this to reload the timings.
12 *
13 * Because of these behaviour differences PIIX gets its own driver module.
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/blkdev.h>
21#include <linux/delay.h>
22#include <linux/device.h>
23#include <scsi/scsi_host.h>
24#include <linux/libata.h>
25#include <linux/ata.h>
26
27#define DRV_NAME "pata_oldpiix"
28#define DRV_VERSION "0.5.1"
29
30/**
31 * oldpiix_pre_reset - probe begin
32 * @ap: ATA port
33 *
34 * Set up cable type and use generic probe init
35 */
36
37static int oldpiix_pre_reset(struct ata_port *ap)
38{
39 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
40 static const struct pci_bits oldpiix_enable_bits[] = {
41 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
42 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
43 };
44
45 if (!pci_test_config_bits(pdev, &oldpiix_enable_bits[ap->port_no])) {
46 ata_port_disable(ap);
47 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
48 return 0;
49 }
50 ap->cbl = ATA_CBL_PATA40;
51 return ata_std_prereset(ap);
52}
53
54/**
55 * oldpiix_pata_error_handler - Probe specified port on PATA host controller
56 * @ap: Port to probe
57 * @classes:
58 *
59 * LOCKING:
60 * None (inherited from caller).
61 */
62
63static void oldpiix_pata_error_handler(struct ata_port *ap)
64{
65 ata_bmdma_drive_eh(ap, oldpiix_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
66}
67
68/**
69 * oldpiix_set_piomode - Initialize host controller PATA PIO timings
70 * @ap: Port whose timings we are configuring
71 * @adev: um
72 *
73 * Set PIO mode for device, in host controller PCI config space.
74 *
75 * LOCKING:
76 * None (inherited from caller).
77 */
78
79static void oldpiix_set_piomode (struct ata_port *ap, struct ata_device *adev)
80{
81 unsigned int pio = adev->pio_mode - XFER_PIO_0;
82 struct pci_dev *dev = to_pci_dev(ap->host->dev);
83 unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
84 u16 idetm_data;
85 int control = 0;
86
87 /*
88 * See Intel Document 298600-004 for the timing programing rules
89 * for PIIX/ICH. Note that the early PIIX does not have the slave
90 * timing port at 0x44.
91 */
92
93 static const /* ISP RTC */
94 u8 timings[][2] = { { 0, 0 },
95 { 0, 0 },
96 { 1, 0 },
97 { 2, 1 },
98 { 2, 3 }, };
99
100 if (pio > 2)
101 control |= 1; /* TIME1 enable */
102 if (ata_pio_need_iordy(adev))
103 control |= 2; /* IE IORDY */
104
105 /* Intel specifies that the PPE functionality is for disk only */
106 if (adev->class == ATA_DEV_ATA)
107 control |= 4; /* PPE enable */
108
109 pci_read_config_word(dev, idetm_port, &idetm_data);
110
111 /* Enable PPE, IE and TIME as appropriate. Clear the other
112 drive timing bits */
113 if (adev->devno == 0) {
114 idetm_data &= 0xCCE0;
115 idetm_data |= control;
116 } else {
117 idetm_data &= 0xCC0E;
118 idetm_data |= (control << 4);
119 }
120 idetm_data |= (timings[pio][0] << 12) |
121 (timings[pio][1] << 8);
122 pci_write_config_word(dev, idetm_port, idetm_data);
123
124 /* Track which port is configured */
125 ap->private_data = adev;
126}
127
128/**
129 * oldpiix_set_dmamode - Initialize host controller PATA DMA timings
130 * @ap: Port whose timings we are configuring
131 * @adev: Device to program
132 * @isich: True if the device is an ICH and has IOCFG registers
133 *
134 * Set MWDMA mode for device, in host controller PCI config space.
135 *
136 * LOCKING:
137 * None (inherited from caller).
138 */
139
140static void oldpiix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
141{
142 struct pci_dev *dev = to_pci_dev(ap->host->dev);
143 u8 idetm_port = ap->port_no ? 0x42 : 0x40;
144 u16 idetm_data;
145
146 static const /* ISP RTC */
147 u8 timings[][2] = { { 0, 0 },
148 { 0, 0 },
149 { 1, 0 },
150 { 2, 1 },
151 { 2, 3 }, };
152
153 /*
154 * MWDMA is driven by the PIO timings. We must also enable
155 * IORDY unconditionally along with TIME1. PPE has already
156 * been set when the PIO timing was set.
157 */
158
159 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
160 unsigned int control;
161 const unsigned int needed_pio[3] = {
162 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
163 };
164 int pio = needed_pio[mwdma] - XFER_PIO_0;
165
166 pci_read_config_word(dev, idetm_port, &idetm_data);
167
168 control = 3; /* IORDY|TIME0 */
169 /* Intel specifies that the PPE functionality is for disk only */
170 if (adev->class == ATA_DEV_ATA)
171 control |= 4; /* PPE enable */
172
173 /* If the drive MWDMA is faster than it can do PIO then
174 we must force PIO into PIO0 */
175
176 if (adev->pio_mode < needed_pio[mwdma])
177 /* Enable DMA timing only */
178 control |= 8; /* PIO cycles in PIO0 */
179
180 /* Mask out the relevant control and timing bits we will load. Also
181 clear the other drive TIME register as a precaution */
182 if (adev->devno == 0) {
183 idetm_data &= 0xCCE0;
184 idetm_data |= control;
185 } else {
186 idetm_data &= 0xCC0E;
187 idetm_data |= (control << 4);
188 }
189 idetm_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
190 pci_write_config_word(dev, idetm_port, idetm_data);
191
192 /* Track which port is configured */
193 ap->private_data = adev;
194}
195
196/**
197 * oldpiix_qc_issue_prot - command issue
198 * @qc: command pending
199 *
200 * Called when the libata layer is about to issue a command. We wrap
201 * this interface so that we can load the correct ATA timings if
202 * neccessary. Our logic also clears TIME0/TIME1 for the other device so
203 * that, even if we get this wrong, cycles to the other device will
204 * be made PIO0.
205 */
206
207static unsigned int oldpiix_qc_issue_prot(struct ata_queued_cmd *qc)
208{
209 struct ata_port *ap = qc->ap;
210 struct ata_device *adev = qc->dev;
211
212 if (adev != ap->private_data) {
213 if (adev->dma_mode)
214 oldpiix_set_dmamode(ap, adev);
215 else if (adev->pio_mode)
216 oldpiix_set_piomode(ap, adev);
217 }
218 return ata_qc_issue_prot(qc);
219}
220
221
222static struct scsi_host_template oldpiix_sht = {
223 .module = THIS_MODULE,
224 .name = DRV_NAME,
225 .ioctl = ata_scsi_ioctl,
226 .queuecommand = ata_scsi_queuecmd,
227 .can_queue = ATA_DEF_QUEUE,
228 .this_id = ATA_SHT_THIS_ID,
229 .sg_tablesize = LIBATA_MAX_PRD,
230 .max_sectors = ATA_MAX_SECTORS,
231 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
232 .emulated = ATA_SHT_EMULATED,
233 .use_clustering = ATA_SHT_USE_CLUSTERING,
234 .proc_name = DRV_NAME,
235 .dma_boundary = ATA_DMA_BOUNDARY,
236 .slave_configure = ata_scsi_slave_config,
237 .bios_param = ata_std_bios_param,
238};
239
240static const struct ata_port_operations oldpiix_pata_ops = {
241 .port_disable = ata_port_disable,
242 .set_piomode = oldpiix_set_piomode,
243 .set_dmamode = oldpiix_set_dmamode,
244 .mode_filter = ata_pci_default_filter,
245
246 .tf_load = ata_tf_load,
247 .tf_read = ata_tf_read,
248 .check_status = ata_check_status,
249 .exec_command = ata_exec_command,
250 .dev_select = ata_std_dev_select,
251
252 .freeze = ata_bmdma_freeze,
253 .thaw = ata_bmdma_thaw,
254 .error_handler = oldpiix_pata_error_handler,
255 .post_internal_cmd = ata_bmdma_post_internal_cmd,
256
257 .bmdma_setup = ata_bmdma_setup,
258 .bmdma_start = ata_bmdma_start,
259 .bmdma_stop = ata_bmdma_stop,
260 .bmdma_status = ata_bmdma_status,
261 .qc_prep = ata_qc_prep,
262 .qc_issue = oldpiix_qc_issue_prot,
263 .data_xfer = ata_pio_data_xfer,
264
265 .irq_handler = ata_interrupt,
266 .irq_clear = ata_bmdma_irq_clear,
267
268 .port_start = ata_port_start,
269 .port_stop = ata_port_stop,
270 .host_stop = ata_host_stop,
271};
272
273
274/**
275 * oldpiix_init_one - Register PIIX ATA PCI device with kernel services
276 * @pdev: PCI device to register
277 * @ent: Entry in oldpiix_pci_tbl matching with @pdev
278 *
279 * Called from kernel PCI layer. We probe for combined mode (sigh),
280 * and then hand over control to libata, for it to do the rest.
281 *
282 * LOCKING:
283 * Inherited from PCI layer (may sleep).
284 *
285 * RETURNS:
286 * Zero on success, or -ERRNO value.
287 */
288
289static int oldpiix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
290{
291 static int printed_version;
292 static struct ata_port_info info = {
293 .sht = &oldpiix_sht,
294 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
295 .pio_mask = 0x1f, /* pio0-4 */
296 .mwdma_mask = 0x07, /* mwdma1-2 */
297 .port_ops = &oldpiix_pata_ops,
298 };
299 static struct ata_port_info *port_info[2] = { &info, &info };
300
301 if (!printed_version++)
302 dev_printk(KERN_DEBUG, &pdev->dev,
303 "version " DRV_VERSION "\n");
304
305 return ata_pci_init_one(pdev, port_info, 2);
306}
307
308static const struct pci_device_id oldpiix_pci_tbl[] = {
309 { PCI_DEVICE(0x8086, 0x1230), },
310 { } /* terminate list */
311};
312
313static struct pci_driver oldpiix_pci_driver = {
314 .name = DRV_NAME,
315 .id_table = oldpiix_pci_tbl,
316 .probe = oldpiix_init_one,
317 .remove = ata_pci_remove_one,
318};
319
320static int __init oldpiix_init(void)
321{
322 return pci_register_driver(&oldpiix_pci_driver);
323}
324
325static void __exit oldpiix_exit(void)
326{
327 pci_unregister_driver(&oldpiix_pci_driver);
328}
329
330
331module_init(oldpiix_init);
332module_exit(oldpiix_exit);
333
334MODULE_AUTHOR("Alan Cox");
335MODULE_DESCRIPTION("SCSI low-level driver for early PIIX series controllers");
336MODULE_LICENSE("GPL");
337MODULE_DEVICE_TABLE(pci, oldpiix_pci_tbl);
338MODULE_VERSION(DRV_VERSION);
339