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-rw-r--r--drivers/ata/pata_macio.c1427
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diff --git a/drivers/ata/pata_macio.c b/drivers/ata/pata_macio.c
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1/*
2 * Libata based driver for Apple "macio" family of PATA controllers
3 *
4 * Copyright 2008/2009 Benjamin Herrenschmidt, IBM Corp
5 * <benh@kernel.crashing.org>
6 *
7 * Some bits and pieces from drivers/ide/ppc/pmac.c
8 *
9 */
10
11#undef DEBUG
12#undef DEBUG_DMA
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/blkdev.h>
18#include <linux/ata.h>
19#include <linux/libata.h>
20#include <linux/adb.h>
21#include <linux/pmu.h>
22#include <linux/scatterlist.h>
23#include <linux/of.h>
24
25#include <scsi/scsi.h>
26#include <scsi/scsi_host.h>
27#include <scsi/scsi_device.h>
28
29#include <asm/macio.h>
30#include <asm/io.h>
31#include <asm/dbdma.h>
32#include <asm/pci-bridge.h>
33#include <asm/machdep.h>
34#include <asm/pmac_feature.h>
35#include <asm/mediabay.h>
36
37#ifdef DEBUG_DMA
38#define dev_dbgdma(dev, format, arg...) \
39 dev_printk(KERN_DEBUG , dev , format , ## arg)
40#else
41#define dev_dbgdma(dev, format, arg...) \
42 ({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })
43#endif
44
45#define DRV_NAME "pata_macio"
46#define DRV_VERSION "0.9"
47
48/* Models of macio ATA controller */
49enum {
50 controller_ohare, /* OHare based */
51 controller_heathrow, /* Heathrow/Paddington */
52 controller_kl_ata3, /* KeyLargo ATA-3 */
53 controller_kl_ata4, /* KeyLargo ATA-4 */
54 controller_un_ata6, /* UniNorth2 ATA-6 */
55 controller_k2_ata6, /* K2 ATA-6 */
56 controller_sh_ata6, /* Shasta ATA-6 */
57};
58
59static const char* macio_ata_names[] = {
60 "OHare ATA", /* OHare based */
61 "Heathrow ATA", /* Heathrow/Paddington */
62 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
63 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
64 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
65 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
66 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
67};
68
69/*
70 * Extra registers, both 32-bit little-endian
71 */
72#define IDE_TIMING_CONFIG 0x200
73#define IDE_INTERRUPT 0x300
74
75/* Kauai (U2) ATA has different register setup */
76#define IDE_KAUAI_PIO_CONFIG 0x200
77#define IDE_KAUAI_ULTRA_CONFIG 0x210
78#define IDE_KAUAI_POLL_CONFIG 0x220
79
80/*
81 * Timing configuration register definitions
82 */
83
84/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
85#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
86#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
87#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
88#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
89
90/* 133Mhz cell, found in shasta.
91 * See comments about 100 Mhz Uninorth 2...
92 * Note that PIO_MASK and MDMA_MASK seem to overlap, that's just
93 * weird and I don't now why .. at this stage
94 */
95#define TR_133_PIOREG_PIO_MASK 0xff000fff
96#define TR_133_PIOREG_MDMA_MASK 0x00fff800
97#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
98#define TR_133_UDMAREG_UDMA_EN 0x00000001
99
100/* 100Mhz cell, found in Uninorth 2 and K2. It appears as a pci device
101 * (106b/0033) on uninorth or K2 internal PCI bus and it's clock is
102 * controlled like gem or fw. It appears to be an evolution of keylargo
103 * ATA4 with a timing register extended to 2x32bits registers (one
104 * for PIO & MWDMA and one for UDMA, and a similar DBDMA channel.
105 * It has it's own local feature control register as well.
106 *
107 * After scratching my mind over the timing values, at least for PIO
108 * and MDMA, I think I've figured the format of the timing register,
109 * though I use pre-calculated tables for UDMA as usual...
110 */
111#define TR_100_PIO_ADDRSETUP_MASK 0xff000000 /* Size of field unknown */
112#define TR_100_PIO_ADDRSETUP_SHIFT 24
113#define TR_100_MDMA_MASK 0x00fff000
114#define TR_100_MDMA_RECOVERY_MASK 0x00fc0000
115#define TR_100_MDMA_RECOVERY_SHIFT 18
116#define TR_100_MDMA_ACCESS_MASK 0x0003f000
117#define TR_100_MDMA_ACCESS_SHIFT 12
118#define TR_100_PIO_MASK 0xff000fff
119#define TR_100_PIO_RECOVERY_MASK 0x00000fc0
120#define TR_100_PIO_RECOVERY_SHIFT 6
121#define TR_100_PIO_ACCESS_MASK 0x0000003f
122#define TR_100_PIO_ACCESS_SHIFT 0
123
124#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
125#define TR_100_UDMAREG_UDMA_EN 0x00000001
126
127
128/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
129 * 40 connector cable and to 4 on 80 connector one.
130 * Clock unit is 15ns (66Mhz)
131 *
132 * 3 Values can be programmed:
133 * - Write data setup, which appears to match the cycle time. They
134 * also call it DIOW setup.
135 * - Ready to pause time (from spec)
136 * - Address setup. That one is weird. I don't see where exactly
137 * it fits in UDMA cycles, I got it's name from an obscure piece
138 * of commented out code in Darwin. They leave it to 0, we do as
139 * well, despite a comment that would lead to think it has a
140 * min value of 45ns.
141 * Apple also add 60ns to the write data setup (or cycle time ?) on
142 * reads.
143 */
144#define TR_66_UDMA_MASK 0xfff00000
145#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
146#define TR_66_PIO_ADDRSETUP_MASK 0xe0000000 /* Address setup */
147#define TR_66_PIO_ADDRSETUP_SHIFT 29
148#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
149#define TR_66_UDMA_RDY2PAUS_SHIFT 25
150#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
151#define TR_66_UDMA_WRDATASETUP_SHIFT 21
152#define TR_66_MDMA_MASK 0x000ffc00
153#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
154#define TR_66_MDMA_RECOVERY_SHIFT 15
155#define TR_66_MDMA_ACCESS_MASK 0x00007c00
156#define TR_66_MDMA_ACCESS_SHIFT 10
157#define TR_66_PIO_MASK 0xe00003ff
158#define TR_66_PIO_RECOVERY_MASK 0x000003e0
159#define TR_66_PIO_RECOVERY_SHIFT 5
160#define TR_66_PIO_ACCESS_MASK 0x0000001f
161#define TR_66_PIO_ACCESS_SHIFT 0
162
163/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
164 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
165 *
166 * The access time and recovery time can be programmed. Some older
167 * Darwin code base limit OHare to 150ns cycle time. I decided to do
168 * the same here fore safety against broken old hardware ;)
169 * The HalfTick bit, when set, adds half a clock (15ns) to the access
170 * time and removes one from recovery. It's not supported on KeyLargo
171 * implementation afaik. The E bit appears to be set for PIO mode 0 and
172 * is used to reach long timings used in this mode.
173 */
174#define TR_33_MDMA_MASK 0x003ff800
175#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
176#define TR_33_MDMA_RECOVERY_SHIFT 16
177#define TR_33_MDMA_ACCESS_MASK 0x0000f800
178#define TR_33_MDMA_ACCESS_SHIFT 11
179#define TR_33_MDMA_HALFTICK 0x00200000
180#define TR_33_PIO_MASK 0x000007ff
181#define TR_33_PIO_E 0x00000400
182#define TR_33_PIO_RECOVERY_MASK 0x000003e0
183#define TR_33_PIO_RECOVERY_SHIFT 5
184#define TR_33_PIO_ACCESS_MASK 0x0000001f
185#define TR_33_PIO_ACCESS_SHIFT 0
186
187/*
188 * Interrupt register definitions. Only present on newer cells
189 * (Keylargo and later afaik) so we don't use it.
190 */
191#define IDE_INTR_DMA 0x80000000
192#define IDE_INTR_DEVICE 0x40000000
193
194/*
195 * FCR Register on Kauai. Not sure what bit 0x4 is ...
196 */
197#define KAUAI_FCR_UATA_MAGIC 0x00000004
198#define KAUAI_FCR_UATA_RESET_N 0x00000002
199#define KAUAI_FCR_UATA_ENABLE 0x00000001
200
201
202/* Allow up to 256 DBDMA commands per xfer */
203#define MAX_DCMDS 256
204
205/* Don't let a DMA segment go all the way to 64K */
206#define MAX_DBDMA_SEG 0xff00
207
208
209/*
210 * Wait 1s for disk to answer on IDE bus after a hard reset
211 * of the device (via GPIO/FCR).
212 *
213 * Some devices seem to "pollute" the bus even after dropping
214 * the BSY bit (typically some combo drives slave on the UDMA
215 * bus) after a hard reset. Since we hard reset all drives on
216 * KeyLargo ATA66, we have to keep that delay around. I may end
217 * up not hard resetting anymore on these and keep the delay only
218 * for older interfaces instead (we have to reset when coming
219 * from MacOS...) --BenH.
220 */
221#define IDE_WAKEUP_DELAY_MS 1000
222
223struct pata_macio_timing;
224
225struct pata_macio_priv {
226 int kind;
227 int aapl_bus_id;
228 int mediabay : 1;
229 struct device_node *node;
230 struct macio_dev *mdev;
231 struct pci_dev *pdev;
232 struct device *dev;
233 int irq;
234 u32 treg[2][2];
235 void __iomem *tfregs;
236 void __iomem *kauai_fcr;
237 struct dbdma_cmd * dma_table_cpu;
238 dma_addr_t dma_table_dma;
239 struct ata_host *host;
240 const struct pata_macio_timing *timings;
241};
242
243/* Previous variants of this driver used to calculate timings
244 * for various variants of the chip and use tables for others.
245 *
246 * Not only was this confusing, but in addition, it isn't clear
247 * whether our calculation code was correct. It didn't entirely
248 * match the darwin code and whatever documentation I could find
249 * on these cells
250 *
251 * I decided to entirely rely on a table instead for this version
252 * of the driver. Also, because I don't really care about derated
253 * modes and really old HW other than making it work, I'm not going
254 * to calculate / snoop timing values for something else than the
255 * standard modes.
256 */
257struct pata_macio_timing {
258 int mode;
259 u32 reg1; /* Bits to set in first timing reg */
260 u32 reg2; /* Bits to set in second timing reg */
261};
262
263static const struct pata_macio_timing pata_macio_ohare_timings[] = {
264 { XFER_PIO_0, 0x00000526, 0, },
265 { XFER_PIO_1, 0x00000085, 0, },
266 { XFER_PIO_2, 0x00000025, 0, },
267 { XFER_PIO_3, 0x00000025, 0, },
268 { XFER_PIO_4, 0x00000025, 0, },
269 { XFER_MW_DMA_0, 0x00074000, 0, },
270 { XFER_MW_DMA_1, 0x00221000, 0, },
271 { XFER_MW_DMA_2, 0x00211000, 0, },
272 { -1, 0, 0 }
273};
274
275static const struct pata_macio_timing pata_macio_heathrow_timings[] = {
276 { XFER_PIO_0, 0x00000526, 0, },
277 { XFER_PIO_1, 0x00000085, 0, },
278 { XFER_PIO_2, 0x00000025, 0, },
279 { XFER_PIO_3, 0x00000025, 0, },
280 { XFER_PIO_4, 0x00000025, 0, },
281 { XFER_MW_DMA_0, 0x00074000, 0, },
282 { XFER_MW_DMA_1, 0x00221000, 0, },
283 { XFER_MW_DMA_2, 0x00211000, 0, },
284 { -1, 0, 0 }
285};
286
287static const struct pata_macio_timing pata_macio_kl33_timings[] = {
288 { XFER_PIO_0, 0x00000526, 0, },
289 { XFER_PIO_1, 0x00000085, 0, },
290 { XFER_PIO_2, 0x00000025, 0, },
291 { XFER_PIO_3, 0x00000025, 0, },
292 { XFER_PIO_4, 0x00000025, 0, },
293 { XFER_MW_DMA_0, 0x00084000, 0, },
294 { XFER_MW_DMA_1, 0x00021800, 0, },
295 { XFER_MW_DMA_2, 0x00011800, 0, },
296 { -1, 0, 0 }
297};
298
299static const struct pata_macio_timing pata_macio_kl66_timings[] = {
300 { XFER_PIO_0, 0x0000038c, 0, },
301 { XFER_PIO_1, 0x0000020a, 0, },
302 { XFER_PIO_2, 0x00000127, 0, },
303 { XFER_PIO_3, 0x000000c6, 0, },
304 { XFER_PIO_4, 0x00000065, 0, },
305 { XFER_MW_DMA_0, 0x00084000, 0, },
306 { XFER_MW_DMA_1, 0x00029800, 0, },
307 { XFER_MW_DMA_2, 0x00019400, 0, },
308 { XFER_UDMA_0, 0x19100000, 0, },
309 { XFER_UDMA_1, 0x14d00000, 0, },
310 { XFER_UDMA_2, 0x10900000, 0, },
311 { XFER_UDMA_3, 0x0c700000, 0, },
312 { XFER_UDMA_4, 0x0c500000, 0, },
313 { -1, 0, 0 }
314};
315
316static const struct pata_macio_timing pata_macio_kauai_timings[] = {
317 { XFER_PIO_0, 0x08000a92, 0, },
318 { XFER_PIO_1, 0x0800060f, 0, },
319 { XFER_PIO_2, 0x0800038b, 0, },
320 { XFER_PIO_3, 0x05000249, 0, },
321 { XFER_PIO_4, 0x04000148, 0, },
322 { XFER_MW_DMA_0, 0x00618000, 0, },
323 { XFER_MW_DMA_1, 0x00209000, 0, },
324 { XFER_MW_DMA_2, 0x00148000, 0, },
325 { XFER_UDMA_0, 0, 0x000070c1, },
326 { XFER_UDMA_1, 0, 0x00005d81, },
327 { XFER_UDMA_2, 0, 0x00004a61, },
328 { XFER_UDMA_3, 0, 0x00003a51, },
329 { XFER_UDMA_4, 0, 0x00002a31, },
330 { XFER_UDMA_5, 0, 0x00002921, },
331 { -1, 0, 0 }
332};
333
334static const struct pata_macio_timing pata_macio_shasta_timings[] = {
335 { XFER_PIO_0, 0x0a000c97, 0, },
336 { XFER_PIO_1, 0x07000712, 0, },
337 { XFER_PIO_2, 0x040003cd, 0, },
338 { XFER_PIO_3, 0x0500028b, 0, },
339 { XFER_PIO_4, 0x0400010a, 0, },
340 { XFER_MW_DMA_0, 0x00820800, 0, },
341 { XFER_MW_DMA_1, 0x0028b000, 0, },
342 { XFER_MW_DMA_2, 0x001ca000, 0, },
343 { XFER_UDMA_0, 0, 0x00035901, },
344 { XFER_UDMA_1, 0, 0x000348b1, },
345 { XFER_UDMA_2, 0, 0x00033881, },
346 { XFER_UDMA_3, 0, 0x00033861, },
347 { XFER_UDMA_4, 0, 0x00033841, },
348 { XFER_UDMA_5, 0, 0x00033031, },
349 { XFER_UDMA_6, 0, 0x00033021, },
350 { -1, 0, 0 }
351};
352
353static const struct pata_macio_timing *pata_macio_find_timing(
354 struct pata_macio_priv *priv,
355 int mode)
356{
357 int i;
358
359 for (i = 0; priv->timings[i].mode > 0; i++) {
360 if (priv->timings[i].mode == mode)
361 return &priv->timings[i];
362 }
363 return NULL;
364}
365
366
367static void pata_macio_apply_timings(struct ata_port *ap, unsigned int device)
368{
369 struct pata_macio_priv *priv = ap->private_data;
370 void __iomem *rbase = ap->ioaddr.cmd_addr;
371
372 if (priv->kind == controller_sh_ata6 ||
373 priv->kind == controller_un_ata6 ||
374 priv->kind == controller_k2_ata6) {
375 writel(priv->treg[device][0], rbase + IDE_KAUAI_PIO_CONFIG);
376 writel(priv->treg[device][1], rbase + IDE_KAUAI_ULTRA_CONFIG);
377 } else
378 writel(priv->treg[device][0], rbase + IDE_TIMING_CONFIG);
379}
380
381static void pata_macio_dev_select(struct ata_port *ap, unsigned int device)
382{
383 ata_sff_dev_select(ap, device);
384
385 /* Apply timings */
386 pata_macio_apply_timings(ap, device);
387}
388
389static void pata_macio_set_timings(struct ata_port *ap,
390 struct ata_device *adev)
391{
392 struct pata_macio_priv *priv = ap->private_data;
393 const struct pata_macio_timing *t;
394
395 dev_dbg(priv->dev, "Set timings: DEV=%d,PIO=0x%x (%s),DMA=0x%x (%s)\n",
396 adev->devno,
397 adev->pio_mode,
398 ata_mode_string(ata_xfer_mode2mask(adev->pio_mode)),
399 adev->dma_mode,
400 ata_mode_string(ata_xfer_mode2mask(adev->dma_mode)));
401
402 /* First clear timings */
403 priv->treg[adev->devno][0] = priv->treg[adev->devno][1] = 0;
404
405 /* Now get the PIO timings */
406 t = pata_macio_find_timing(priv, adev->pio_mode);
407 if (t == NULL) {
408 dev_warn(priv->dev, "Invalid PIO timing requested: 0x%x\n",
409 adev->pio_mode);
410 t = pata_macio_find_timing(priv, XFER_PIO_0);
411 }
412 BUG_ON(t == NULL);
413
414 /* PIO timings only ever use the first treg */
415 priv->treg[adev->devno][0] |= t->reg1;
416
417 /* Now get DMA timings */
418 t = pata_macio_find_timing(priv, adev->dma_mode);
419 if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) {
420 dev_dbg(priv->dev, "DMA timing not set yet, using MW_DMA_0\n");
421 t = pata_macio_find_timing(priv, XFER_MW_DMA_0);
422 }
423 BUG_ON(t == NULL);
424
425 /* DMA timings can use both tregs */
426 priv->treg[adev->devno][0] |= t->reg1;
427 priv->treg[adev->devno][1] |= t->reg2;
428
429 dev_dbg(priv->dev, " -> %08x %08x\n",
430 priv->treg[adev->devno][0],
431 priv->treg[adev->devno][1]);
432
433 /* Apply to hardware */
434 pata_macio_apply_timings(ap, adev->devno);
435}
436
437/*
438 * Blast some well known "safe" values to the timing registers at init or
439 * wakeup from sleep time, before we do real calculation
440 */
441static void pata_macio_default_timings(struct pata_macio_priv *priv)
442{
443 unsigned int value, value2 = 0;
444
445 switch(priv->kind) {
446 case controller_sh_ata6:
447 value = 0x0a820c97;
448 value2 = 0x00033031;
449 break;
450 case controller_un_ata6:
451 case controller_k2_ata6:
452 value = 0x08618a92;
453 value2 = 0x00002921;
454 break;
455 case controller_kl_ata4:
456 value = 0x0008438c;
457 break;
458 case controller_kl_ata3:
459 value = 0x00084526;
460 break;
461 case controller_heathrow:
462 case controller_ohare:
463 default:
464 value = 0x00074526;
465 break;
466 }
467 priv->treg[0][0] = priv->treg[1][0] = value;
468 priv->treg[0][1] = priv->treg[1][1] = value2;
469}
470
471static int pata_macio_cable_detect(struct ata_port *ap)
472{
473 struct pata_macio_priv *priv = ap->private_data;
474
475 /* Get cable type from device-tree */
476 if (priv->kind == controller_kl_ata4 ||
477 priv->kind == controller_un_ata6 ||
478 priv->kind == controller_k2_ata6 ||
479 priv->kind == controller_sh_ata6) {
480 const char* cable = of_get_property(priv->node, "cable-type",
481 NULL);
482 struct device_node *root = of_find_node_by_path("/");
483 const char *model = of_get_property(root, "model", NULL);
484
485 if (cable && !strncmp(cable, "80-", 3)) {
486 /* Some drives fail to detect 80c cable in PowerBook
487 * These machine use proprietary short IDE cable
488 * anyway
489 */
490 if (!strncmp(model, "PowerBook", 9))
491 return ATA_CBL_PATA40_SHORT;
492 else
493 return ATA_CBL_PATA80;
494 }
495 }
496
497 /* G5's seem to have incorrect cable type in device-tree.
498 * Let's assume they always have a 80 conductor cable, this seem to
499 * be always the case unless the user mucked around
500 */
501 if (of_device_is_compatible(priv->node, "K2-UATA") ||
502 of_device_is_compatible(priv->node, "shasta-ata"))
503 return ATA_CBL_PATA80;
504
505 /* Anything else is 40 connectors */
506 return ATA_CBL_PATA40;
507}
508
509static void pata_macio_qc_prep(struct ata_queued_cmd *qc)
510{
511 unsigned int write = (qc->tf.flags & ATA_TFLAG_WRITE);
512 struct ata_port *ap = qc->ap;
513 struct pata_macio_priv *priv = ap->private_data;
514 struct scatterlist *sg;
515 struct dbdma_cmd *table;
516 unsigned int si, pi;
517
518 dev_dbgdma(priv->dev, "%s: qc %p flags %lx, write %d dev %d\n",
519 __func__, qc, qc->flags, write, qc->dev->devno);
520
521 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
522 return;
523
524 table = (struct dbdma_cmd *) priv->dma_table_cpu;
525
526 pi = 0;
527 for_each_sg(qc->sg, sg, qc->n_elem, si) {
528 u32 addr, sg_len, len;
529
530 /* determine if physical DMA addr spans 64K boundary.
531 * Note h/w doesn't support 64-bit, so we unconditionally
532 * truncate dma_addr_t to u32.
533 */
534 addr = (u32) sg_dma_address(sg);
535 sg_len = sg_dma_len(sg);
536
537 while (sg_len) {
538 /* table overflow should never happen */
539 BUG_ON (pi++ >= MAX_DCMDS);
540
541 len = (sg_len < MAX_DBDMA_SEG) ? sg_len : MAX_DBDMA_SEG;
542 st_le16(&table->command, write ? OUTPUT_MORE: INPUT_MORE);
543 st_le16(&table->req_count, len);
544 st_le32(&table->phy_addr, addr);
545 table->cmd_dep = 0;
546 table->xfer_status = 0;
547 table->res_count = 0;
548 addr += len;
549 sg_len -= len;
550 ++table;
551 }
552 }
553
554 /* Should never happen according to Tejun */
555 BUG_ON(!pi);
556
557 /* Convert the last command to an input/output */
558 table--;
559 st_le16(&table->command, write ? OUTPUT_LAST: INPUT_LAST);
560 table++;
561
562 /* Add the stop command to the end of the list */
563 memset(table, 0, sizeof(struct dbdma_cmd));
564 st_le16(&table->command, DBDMA_STOP);
565
566 dev_dbgdma(priv->dev, "%s: %d DMA list entries\n", __func__, pi);
567}
568
569
570static void pata_macio_freeze(struct ata_port *ap)
571{
572 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
573
574 if (dma_regs) {
575 unsigned int timeout = 1000000;
576
577 /* Make sure DMA controller is stopped */
578 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control);
579 while (--timeout && (readl(&dma_regs->status) & RUN))
580 udelay(1);
581 }
582
583 ata_sff_freeze(ap);
584}
585
586
587static void pata_macio_bmdma_setup(struct ata_queued_cmd *qc)
588{
589 struct ata_port *ap = qc->ap;
590 struct pata_macio_priv *priv = ap->private_data;
591 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
592 int dev = qc->dev->devno;
593
594 dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
595
596 /* Make sure DMA commands updates are visible */
597 writel(priv->dma_table_dma, &dma_regs->cmdptr);
598
599 /* On KeyLargo 66Mhz cell, we need to add 60ns to wrDataSetup on
600 * UDMA reads
601 */
602 if (priv->kind == controller_kl_ata4 &&
603 (priv->treg[dev][0] & TR_66_UDMA_EN)) {
604 void __iomem *rbase = ap->ioaddr.cmd_addr;
605 u32 reg = priv->treg[dev][0];
606
607 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
608 reg += 0x00800000;
609 writel(reg, rbase + IDE_TIMING_CONFIG);
610 }
611
612 /* issue r/w command */
613 ap->ops->sff_exec_command(ap, &qc->tf);
614}
615
616static void pata_macio_bmdma_start(struct ata_queued_cmd *qc)
617{
618 struct ata_port *ap = qc->ap;
619 struct pata_macio_priv *priv = ap->private_data;
620 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
621
622 dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
623
624 writel((RUN << 16) | RUN, &dma_regs->control);
625 /* Make sure it gets to the controller right now */
626 (void)readl(&dma_regs->control);
627}
628
629static void pata_macio_bmdma_stop(struct ata_queued_cmd *qc)
630{
631 struct ata_port *ap = qc->ap;
632 struct pata_macio_priv *priv = ap->private_data;
633 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
634 unsigned int timeout = 1000000;
635
636 dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
637
638 /* Stop the DMA engine and wait for it to full halt */
639 writel (((RUN|WAKE|DEAD) << 16), &dma_regs->control);
640 while (--timeout && (readl(&dma_regs->status) & RUN))
641 udelay(1);
642}
643
644static u8 pata_macio_bmdma_status(struct ata_port *ap)
645{
646 struct pata_macio_priv *priv = ap->private_data;
647 struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
648 u32 dstat, rstat = ATA_DMA_INTR;
649 unsigned long timeout = 0;
650
651 dstat = readl(&dma_regs->status);
652
653 dev_dbgdma(priv->dev, "%s: dstat=%x\n", __func__, dstat);
654
655 /* We have two things to deal with here:
656 *
657 * - The dbdma won't stop if the command was started
658 * but completed with an error without transferring all
659 * datas. This happens when bad blocks are met during
660 * a multi-block transfer.
661 *
662 * - The dbdma fifo hasn't yet finished flushing to
663 * to system memory when the disk interrupt occurs.
664 *
665 */
666
667 /* First check for errors */
668 if ((dstat & (RUN|DEAD)) != RUN)
669 rstat |= ATA_DMA_ERR;
670
671 /* If ACTIVE is cleared, the STOP command has been hit and
672 * the transfer is complete. If not, we have to flush the
673 * channel.
674 */
675 if ((dstat & ACTIVE) == 0)
676 return rstat;
677
678 dev_dbgdma(priv->dev, "%s: DMA still active, flushing...\n", __func__);
679
680 /* If dbdma didn't execute the STOP command yet, the
681 * active bit is still set. We consider that we aren't
682 * sharing interrupts (which is hopefully the case with
683 * those controllers) and so we just try to flush the
684 * channel for pending data in the fifo
685 */
686 udelay(1);
687 writel((FLUSH << 16) | FLUSH, &dma_regs->control);
688 for (;;) {
689 udelay(1);
690 dstat = readl(&dma_regs->status);
691 if ((dstat & FLUSH) == 0)
692 break;
693 if (++timeout > 1000) {
694 dev_warn(priv->dev, "timeout flushing DMA\n");
695 rstat |= ATA_DMA_ERR;
696 break;
697 }
698 }
699 return rstat;
700}
701
702/* port_start is when we allocate the DMA command list */
703static int pata_macio_port_start(struct ata_port *ap)
704{
705 struct pata_macio_priv *priv = ap->private_data;
706
707 if (ap->ioaddr.bmdma_addr == NULL)
708 return 0;
709
710 /* Allocate space for the DBDMA commands.
711 *
712 * The +2 is +1 for the stop command and +1 to allow for
713 * aligning the start address to a multiple of 16 bytes.
714 */
715 priv->dma_table_cpu =
716 dmam_alloc_coherent(priv->dev,
717 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
718 &priv->dma_table_dma, GFP_KERNEL);
719 if (priv->dma_table_cpu == NULL) {
720 dev_err(priv->dev, "Unable to allocate DMA command list\n");
721 ap->ioaddr.bmdma_addr = NULL;
722 }
723 return 0;
724}
725
726static void pata_macio_irq_clear(struct ata_port *ap)
727{
728 struct pata_macio_priv *priv = ap->private_data;
729
730 /* Nothing to do here */
731
732 dev_dbgdma(priv->dev, "%s\n", __func__);
733}
734
735static void pata_macio_reset_hw(struct pata_macio_priv *priv, int resume)
736{
737 dev_dbg(priv->dev, "Enabling & resetting... \n");
738
739 if (priv->mediabay)
740 return;
741
742 if (priv->kind == controller_ohare && !resume) {
743 /* The code below is having trouble on some ohare machines
744 * (timing related ?). Until I can put my hand on one of these
745 * units, I keep the old way
746 */
747 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, 0, 1);
748 } else {
749 int rc;
750
751 /* Reset and enable controller */
752 rc = ppc_md.feature_call(PMAC_FTR_IDE_RESET,
753 priv->node, priv->aapl_bus_id, 1);
754 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE,
755 priv->node, priv->aapl_bus_id, 1);
756 msleep(10);
757 /* Only bother waiting if there's a reset control */
758 if (rc == 0) {
759 ppc_md.feature_call(PMAC_FTR_IDE_RESET,
760 priv->node, priv->aapl_bus_id, 0);
761 msleep(IDE_WAKEUP_DELAY_MS);
762 }
763 }
764
765 /* If resuming a PCI device, restore the config space here */
766 if (priv->pdev && resume) {
767 int rc;
768
769 pci_restore_state(priv->pdev);
770 rc = pcim_enable_device(priv->pdev);
771 if (rc)
772 dev_printk(KERN_ERR, &priv->pdev->dev,
773 "Failed to enable device after resume (%d)\n", rc);
774 else
775 pci_set_master(priv->pdev);
776 }
777
778 /* On Kauai, initialize the FCR. We don't perform a reset, doesn't really
779 * seem necessary and speeds up the boot process
780 */
781 if (priv->kauai_fcr)
782 writel(KAUAI_FCR_UATA_MAGIC |
783 KAUAI_FCR_UATA_RESET_N |
784 KAUAI_FCR_UATA_ENABLE, priv->kauai_fcr);
785}
786
787/* Hook the standard slave config to fixup some HW related alignment
788 * restrictions
789 */
790static int pata_macio_slave_config(struct scsi_device *sdev)
791{
792 struct ata_port *ap = ata_shost_to_port(sdev->host);
793 struct pata_macio_priv *priv = ap->private_data;
794 struct ata_device *dev;
795 u16 cmd;
796 int rc;
797
798 /* First call original */
799 rc = ata_scsi_slave_config(sdev);
800 if (rc)
801 return rc;
802
803 /* This is lifted from sata_nv */
804 dev = &ap->link.device[sdev->id];
805
806 /* OHare has issues with non cache aligned DMA on some chipsets */
807 if (priv->kind == controller_ohare) {
808 blk_queue_update_dma_alignment(sdev->request_queue, 31);
809 blk_queue_update_dma_pad(sdev->request_queue, 31);
810
811 /* Tell the world about it */
812 ata_dev_printk(dev, KERN_INFO, "OHare alignment limits applied\n");
813 return 0;
814 }
815
816 /* We only have issues with ATAPI */
817 if (dev->class != ATA_DEV_ATAPI)
818 return 0;
819
820 /* Shasta and K2 seem to have "issues" with reads ... */
821 if (priv->kind == controller_sh_ata6 || priv->kind == controller_k2_ata6) {
822 /* Allright these are bad, apply restrictions */
823 blk_queue_update_dma_alignment(sdev->request_queue, 15);
824 blk_queue_update_dma_pad(sdev->request_queue, 15);
825
826 /* We enable MWI and hack cache line size directly here, this
827 * is specific to this chipset and not normal values, we happen
828 * to somewhat know what we are doing here (which is basically
829 * to do the same Apple does and pray they did not get it wrong :-)
830 */
831 BUG_ON(!priv->pdev);
832 pci_write_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, 0x08);
833 pci_read_config_word(priv->pdev, PCI_COMMAND, &cmd);
834 pci_write_config_word(priv->pdev, PCI_COMMAND,
835 cmd | PCI_COMMAND_INVALIDATE);
836
837 /* Tell the world about it */
838 ata_dev_printk(dev, KERN_INFO,
839 "K2/Shasta alignment limits applied\n");
840 }
841
842 return 0;
843}
844
845#ifdef CONFIG_PM
846
847static int pata_macio_do_suspend(struct pata_macio_priv *priv, pm_message_t mesg)
848{
849 int rc;
850
851 /* First, core libata suspend to do most of the work */
852 rc = ata_host_suspend(priv->host, mesg);
853 if (rc)
854 return rc;
855
856 /* Restore to default timings */
857 pata_macio_default_timings(priv);
858
859 /* Mask interrupt. Not strictly necessary but old driver did
860 * it and I'd rather not change that here */
861 disable_irq(priv->irq);
862
863 /* The media bay will handle itself just fine */
864 if (priv->mediabay)
865 return 0;
866
867 /* Kauai has bus control FCRs directly here */
868 if (priv->kauai_fcr) {
869 u32 fcr = readl(priv->kauai_fcr);
870 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
871 writel(fcr, priv->kauai_fcr);
872 }
873
874 /* For PCI, save state and disable DMA. No need to call
875 * pci_set_power_state(), the HW doesn't do D states that
876 * way, the platform code will take care of suspending the
877 * ASIC properly
878 */
879 if (priv->pdev) {
880 pci_save_state(priv->pdev);
881 pci_disable_device(priv->pdev);
882 }
883
884 /* Disable the bus on older machines and the cell on kauai */
885 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node,
886 priv->aapl_bus_id, 0);
887
888 return 0;
889}
890
891static int pata_macio_do_resume(struct pata_macio_priv *priv)
892{
893 /* Reset and re-enable the HW */
894 pata_macio_reset_hw(priv, 1);
895
896 /* Sanitize drive timings */
897 pata_macio_apply_timings(priv->host->ports[0], 0);
898
899 /* We want our IRQ back ! */
900 enable_irq(priv->irq);
901
902 /* Let the libata core take it from there */
903 ata_host_resume(priv->host);
904
905 return 0;
906}
907
908#endif /* CONFIG_PM */
909
910static struct scsi_host_template pata_macio_sht = {
911 ATA_BASE_SHT(DRV_NAME),
912 .sg_tablesize = MAX_DCMDS,
913 /* We may not need that strict one */
914 .dma_boundary = ATA_DMA_BOUNDARY,
915 .slave_configure = pata_macio_slave_config,
916};
917
918static struct ata_port_operations pata_macio_ops = {
919 .inherits = &ata_sff_port_ops,
920
921 .freeze = pata_macio_freeze,
922 .set_piomode = pata_macio_set_timings,
923 .set_dmamode = pata_macio_set_timings,
924 .cable_detect = pata_macio_cable_detect,
925 .sff_dev_select = pata_macio_dev_select,
926 .qc_prep = pata_macio_qc_prep,
927 .mode_filter = ata_bmdma_mode_filter,
928 .bmdma_setup = pata_macio_bmdma_setup,
929 .bmdma_start = pata_macio_bmdma_start,
930 .bmdma_stop = pata_macio_bmdma_stop,
931 .bmdma_status = pata_macio_bmdma_status,
932 .port_start = pata_macio_port_start,
933 .sff_irq_clear = pata_macio_irq_clear,
934};
935
936static void __devinit pata_macio_invariants(struct pata_macio_priv *priv)
937{
938 const int *bidp;
939
940 /* Identify the type of controller */
941 if (of_device_is_compatible(priv->node, "shasta-ata")) {
942 priv->kind = controller_sh_ata6;
943 priv->timings = pata_macio_shasta_timings;
944 } else if (of_device_is_compatible(priv->node, "kauai-ata")) {
945 priv->kind = controller_un_ata6;
946 priv->timings = pata_macio_kauai_timings;
947 } else if (of_device_is_compatible(priv->node, "K2-UATA")) {
948 priv->kind = controller_k2_ata6;
949 priv->timings = pata_macio_kauai_timings;
950 } else if (of_device_is_compatible(priv->node, "keylargo-ata")) {
951 if (strcmp(priv->node->name, "ata-4") == 0) {
952 priv->kind = controller_kl_ata4;
953 priv->timings = pata_macio_kl66_timings;
954 } else {
955 priv->kind = controller_kl_ata3;
956 priv->timings = pata_macio_kl33_timings;
957 }
958 } else if (of_device_is_compatible(priv->node, "heathrow-ata")) {
959 priv->kind = controller_heathrow;
960 priv->timings = pata_macio_heathrow_timings;
961 } else {
962 priv->kind = controller_ohare;
963 priv->timings = pata_macio_ohare_timings;
964 }
965
966 /* XXX FIXME --- setup priv->mediabay here */
967
968 /* Get Apple bus ID (for clock and ASIC control) */
969 bidp = of_get_property(priv->node, "AAPL,bus-id", NULL);
970 priv->aapl_bus_id = bidp ? *bidp : 0;
971
972 /* Fixup missing Apple bus ID in case of media-bay */
973 if (priv->mediabay && bidp == 0)
974 priv->aapl_bus_id = 1;
975}
976
977static void __devinit pata_macio_setup_ios(struct ata_ioports *ioaddr,
978 void __iomem * base,
979 void __iomem * dma)
980{
981 /* cmd_addr is the base of regs for that port */
982 ioaddr->cmd_addr = base;
983
984 /* taskfile registers */
985 ioaddr->data_addr = base + (ATA_REG_DATA << 4);
986 ioaddr->error_addr = base + (ATA_REG_ERR << 4);
987 ioaddr->feature_addr = base + (ATA_REG_FEATURE << 4);
988 ioaddr->nsect_addr = base + (ATA_REG_NSECT << 4);
989 ioaddr->lbal_addr = base + (ATA_REG_LBAL << 4);
990 ioaddr->lbam_addr = base + (ATA_REG_LBAM << 4);
991 ioaddr->lbah_addr = base + (ATA_REG_LBAH << 4);
992 ioaddr->device_addr = base + (ATA_REG_DEVICE << 4);
993 ioaddr->status_addr = base + (ATA_REG_STATUS << 4);
994 ioaddr->command_addr = base + (ATA_REG_CMD << 4);
995 ioaddr->altstatus_addr = base + 0x160;
996 ioaddr->ctl_addr = base + 0x160;
997 ioaddr->bmdma_addr = dma;
998}
999
1000static void __devinit pmac_macio_calc_timing_masks(struct pata_macio_priv *priv,
1001 struct ata_port_info *pinfo)
1002{
1003 int i = 0;
1004
1005 pinfo->pio_mask = 0;
1006 pinfo->mwdma_mask = 0;
1007 pinfo->udma_mask = 0;
1008
1009 while (priv->timings[i].mode > 0) {
1010 unsigned int mask = 1U << (priv->timings[i].mode & 0x0f);
1011 switch(priv->timings[i].mode & 0xf0) {
1012 case 0x00: /* PIO */
1013 pinfo->pio_mask |= (mask >> 8);
1014 break;
1015 case 0x20: /* MWDMA */
1016 pinfo->mwdma_mask |= mask;
1017 break;
1018 case 0x40: /* UDMA */
1019 pinfo->udma_mask |= mask;
1020 break;
1021 }
1022 i++;
1023 }
1024 dev_dbg(priv->dev, "Supported masks: PIO=%lx, MWDMA=%lx, UDMA=%lx\n",
1025 pinfo->pio_mask, pinfo->mwdma_mask, pinfo->udma_mask);
1026}
1027
1028static int __devinit pata_macio_common_init(struct pata_macio_priv *priv,
1029 resource_size_t tfregs,
1030 resource_size_t dmaregs,
1031 resource_size_t fcregs,
1032 unsigned long irq)
1033{
1034 struct ata_port_info pinfo;
1035 const struct ata_port_info *ppi[] = { &pinfo, NULL };
1036 void __iomem *dma_regs = NULL;
1037
1038 /* Fill up privates with various invariants collected from the
1039 * device-tree
1040 */
1041 pata_macio_invariants(priv);
1042
1043 /* Make sure we have sane initial timings in the cache */
1044 pata_macio_default_timings(priv);
1045
1046 /* Not sure what the real max is but we know it's less than 64K, let's
1047 * use 64K minus 256
1048 */
1049 dma_set_max_seg_size(priv->dev, MAX_DBDMA_SEG);
1050
1051 /* Allocate libata host for 1 port */
1052 memset(&pinfo, 0, sizeof(struct ata_port_info));
1053 pmac_macio_calc_timing_masks(priv, &pinfo);
1054 pinfo.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_MMIO |
1055 ATA_FLAG_NO_LEGACY;
1056 pinfo.port_ops = &pata_macio_ops;
1057 pinfo.private_data = priv;
1058
1059 priv->host = ata_host_alloc_pinfo(priv->dev, ppi, 1);
1060 if (priv->host == NULL) {
1061 dev_err(priv->dev, "Failed to allocate ATA port structure\n");
1062 return -ENOMEM;
1063 }
1064
1065 /* Setup the private data in host too */
1066 priv->host->private_data = priv;
1067
1068 /* Map base registers */
1069 priv->tfregs = devm_ioremap(priv->dev, tfregs, 0x100);
1070 if (priv->tfregs == NULL) {
1071 dev_err(priv->dev, "Failed to map ATA ports\n");
1072 return -ENOMEM;
1073 }
1074 priv->host->iomap = &priv->tfregs;
1075
1076 /* Map DMA regs */
1077 if (dmaregs != 0) {
1078 dma_regs = devm_ioremap(priv->dev, dmaregs,
1079 sizeof(struct dbdma_regs));
1080 if (dma_regs == NULL)
1081 dev_warn(priv->dev, "Failed to map ATA DMA registers\n");
1082 }
1083
1084 /* If chip has local feature control, map those regs too */
1085 if (fcregs != 0) {
1086 priv->kauai_fcr = devm_ioremap(priv->dev, fcregs, 4);
1087 if (priv->kauai_fcr == NULL) {
1088 dev_err(priv->dev, "Failed to map ATA FCR register\n");
1089 return -ENOMEM;
1090 }
1091 }
1092
1093 /* Setup port data structure */
1094 pata_macio_setup_ios(&priv->host->ports[0]->ioaddr,
1095 priv->tfregs, dma_regs);
1096 priv->host->ports[0]->private_data = priv;
1097
1098 /* hard-reset the controller */
1099 pata_macio_reset_hw(priv, 0);
1100 pata_macio_apply_timings(priv->host->ports[0], 0);
1101
1102 /* Enable bus master if necessary */
1103 if (priv->pdev && dma_regs)
1104 pci_set_master(priv->pdev);
1105
1106 dev_info(priv->dev, "Activating pata-macio chipset %s, Apple bus ID %d\n",
1107 macio_ata_names[priv->kind], priv->aapl_bus_id);
1108
1109 /* Start it up */
1110 priv->irq = irq;
1111 return ata_host_activate(priv->host, irq, ata_sff_interrupt, 0,
1112 &pata_macio_sht);
1113}
1114
1115static int __devinit pata_macio_attach(struct macio_dev *mdev,
1116 const struct of_device_id *match)
1117{
1118 struct pata_macio_priv *priv;
1119 resource_size_t tfregs, dmaregs = 0;
1120 unsigned long irq;
1121 int rc;
1122
1123 /* Check for broken device-trees */
1124 if (macio_resource_count(mdev) == 0) {
1125 dev_err(&mdev->ofdev.dev,
1126 "No addresses for controller\n");
1127 return -ENXIO;
1128 }
1129
1130 /* Enable managed resources */
1131 macio_enable_devres(mdev);
1132
1133 /* Allocate and init private data structure */
1134 priv = devm_kzalloc(&mdev->ofdev.dev,
1135 sizeof(struct pata_macio_priv), GFP_KERNEL);
1136 if (priv == NULL) {
1137 dev_err(&mdev->ofdev.dev,
1138 "Failed to allocate private memory\n");
1139 return -ENOMEM;
1140 }
1141 priv->node = of_node_get(mdev->ofdev.node);
1142 priv->mdev = mdev;
1143 priv->dev = &mdev->ofdev.dev;
1144
1145 /* Request memory resource for taskfile registers */
1146 if (macio_request_resource(mdev, 0, "pata-macio")) {
1147 dev_err(&mdev->ofdev.dev,
1148 "Cannot obtain taskfile resource\n");
1149 return -EBUSY;
1150 }
1151 tfregs = macio_resource_start(mdev, 0);
1152
1153 /* Request resources for DMA registers if any */
1154 if (macio_resource_count(mdev) >= 2) {
1155 if (macio_request_resource(mdev, 1, "pata-macio-dma"))
1156 dev_err(&mdev->ofdev.dev,
1157 "Cannot obtain DMA resource\n");
1158 else
1159 dmaregs = macio_resource_start(mdev, 1);
1160 }
1161
1162 /*
1163 * Fixup missing IRQ for some old implementations with broken
1164 * device-trees.
1165 *
1166 * This is a bit bogus, it should be fixed in the device-tree itself,
1167 * via the existing macio fixups, based on the type of interrupt
1168 * controller in the machine. However, I have no test HW for this case,
1169 * and this trick works well enough on those old machines...
1170 */
1171 if (macio_irq_count(mdev) == 0) {
1172 dev_warn(&mdev->ofdev.dev,
1173 "No interrupts for controller, using 13\n");
1174 irq = irq_create_mapping(NULL, 13);
1175 } else
1176 irq = macio_irq(mdev, 0);
1177
1178 /* Prevvent media bay callbacks until fully registered */
1179 lock_media_bay(priv->mdev->media_bay);
1180
1181 /* Get register addresses and call common initialization */
1182 rc = pata_macio_common_init(priv,
1183 tfregs, /* Taskfile regs */
1184 dmaregs, /* DBDMA regs */
1185 0, /* Feature control */
1186 irq);
1187 unlock_media_bay(priv->mdev->media_bay);
1188
1189 return rc;
1190}
1191
1192static int __devexit pata_macio_detach(struct macio_dev *mdev)
1193{
1194 struct ata_host *host = macio_get_drvdata(mdev);
1195 struct pata_macio_priv *priv = host->private_data;
1196
1197 lock_media_bay(priv->mdev->media_bay);
1198
1199 /* Make sure the mediabay callback doesn't try to access
1200 * dead stuff
1201 */
1202 priv->host->private_data = NULL;
1203
1204 ata_host_detach(host);
1205
1206 unlock_media_bay(priv->mdev->media_bay);
1207
1208 return 0;
1209}
1210
1211#ifdef CONFIG_PM
1212
1213static int pata_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
1214{
1215 struct ata_host *host = macio_get_drvdata(mdev);
1216
1217 return pata_macio_do_suspend(host->private_data, mesg);
1218}
1219
1220static int pata_macio_resume(struct macio_dev *mdev)
1221{
1222 struct ata_host *host = macio_get_drvdata(mdev);
1223
1224 return pata_macio_do_resume(host->private_data);
1225}
1226
1227#endif /* CONFIG_PM */
1228
1229#ifdef CONFIG_PMAC_MEDIABAY
1230static void pata_macio_mb_event(struct macio_dev* mdev, int mb_state)
1231{
1232 struct ata_host *host = macio_get_drvdata(mdev);
1233 struct ata_port *ap;
1234 struct ata_eh_info *ehi;
1235 struct ata_device *dev;
1236 unsigned long flags;
1237
1238 if (!host || !host->private_data)
1239 return;
1240 ap = host->ports[0];
1241 spin_lock_irqsave(ap->lock, flags);
1242 ehi = &ap->link.eh_info;
1243 if (mb_state == MB_CD) {
1244 ata_ehi_push_desc(ehi, "mediabay plug");
1245 ata_ehi_hotplugged(ehi);
1246 ata_port_freeze(ap);
1247 } else {
1248 ata_ehi_push_desc(ehi, "mediabay unplug");
1249 ata_for_each_dev(dev, &ap->link, ALL)
1250 dev->flags |= ATA_DFLAG_DETACH;
1251 ata_port_abort(ap);
1252 }
1253 spin_unlock_irqrestore(ap->lock, flags);
1254
1255}
1256#endif /* CONFIG_PMAC_MEDIABAY */
1257
1258
1259static int __devinit pata_macio_pci_attach(struct pci_dev *pdev,
1260 const struct pci_device_id *id)
1261{
1262 struct pata_macio_priv *priv;
1263 struct device_node *np;
1264 resource_size_t rbase;
1265
1266 /* We cannot use a MacIO controller without its OF device node */
1267 np = pci_device_to_OF_node(pdev);
1268 if (np == NULL) {
1269 dev_err(&pdev->dev,
1270 "Cannot find OF device node for controller\n");
1271 return -ENODEV;
1272 }
1273
1274 /* Check that it can be enabled */
1275 if (pcim_enable_device(pdev)) {
1276 dev_err(&pdev->dev,
1277 "Cannot enable controller PCI device\n");
1278 return -ENXIO;
1279 }
1280
1281 /* Allocate and init private data structure */
1282 priv = devm_kzalloc(&pdev->dev,
1283 sizeof(struct pata_macio_priv), GFP_KERNEL);
1284 if (priv == NULL) {
1285 dev_err(&pdev->dev,
1286 "Failed to allocate private memory\n");
1287 return -ENOMEM;
1288 }
1289 priv->node = of_node_get(np);
1290 priv->pdev = pdev;
1291 priv->dev = &pdev->dev;
1292
1293 /* Get MMIO regions */
1294 if (pci_request_regions(pdev, "pata-macio")) {
1295 dev_err(&pdev->dev,
1296 "Cannot obtain PCI resources\n");
1297 return -EBUSY;
1298 }
1299
1300 /* Get register addresses and call common initialization */
1301 rbase = pci_resource_start(pdev, 0);
1302 if (pata_macio_common_init(priv,
1303 rbase + 0x2000, /* Taskfile regs */
1304 rbase + 0x1000, /* DBDMA regs */
1305 rbase, /* Feature control */
1306 pdev->irq))
1307 return -ENXIO;
1308
1309 return 0;
1310}
1311
1312static void __devexit pata_macio_pci_detach(struct pci_dev *pdev)
1313{
1314 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1315
1316 ata_host_detach(host);
1317}
1318
1319#ifdef CONFIG_PM
1320
1321static int pata_macio_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
1322{
1323 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1324
1325 return pata_macio_do_suspend(host->private_data, mesg);
1326}
1327
1328static int pata_macio_pci_resume(struct pci_dev *pdev)
1329{
1330 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1331
1332 return pata_macio_do_resume(host->private_data);
1333}
1334
1335#endif /* CONFIG_PM */
1336
1337static struct of_device_id pata_macio_match[] =
1338{
1339 {
1340 .name = "IDE",
1341 },
1342 {
1343 .name = "ATA",
1344 },
1345 {
1346 .type = "ide",
1347 },
1348 {
1349 .type = "ata",
1350 },
1351 {},
1352};
1353
1354static struct macio_driver pata_macio_driver =
1355{
1356 .name = "pata-macio",
1357 .match_table = pata_macio_match,
1358 .probe = pata_macio_attach,
1359 .remove = pata_macio_detach,
1360#ifdef CONFIG_PM
1361 .suspend = pata_macio_suspend,
1362 .resume = pata_macio_resume,
1363#endif
1364#ifdef CONFIG_PMAC_MEDIABAY
1365 .mediabay_event = pata_macio_mb_event,
1366#endif
1367 .driver = {
1368 .owner = THIS_MODULE,
1369 },
1370};
1371
1372static const struct pci_device_id pata_macio_pci_match[] = {
1373 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
1374 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
1375 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
1376 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
1377 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
1378 {},
1379};
1380
1381static struct pci_driver pata_macio_pci_driver = {
1382 .name = "pata-pci-macio",
1383 .id_table = pata_macio_pci_match,
1384 .probe = pata_macio_pci_attach,
1385 .remove = pata_macio_pci_detach,
1386#ifdef CONFIG_PM
1387 .suspend = pata_macio_pci_suspend,
1388 .resume = pata_macio_pci_resume,
1389#endif
1390 .driver = {
1391 .owner = THIS_MODULE,
1392 },
1393};
1394MODULE_DEVICE_TABLE(pci, pata_macio_pci_match);
1395
1396
1397static int __init pata_macio_init(void)
1398{
1399 int rc;
1400
1401 if (!machine_is(powermac))
1402 return -ENODEV;
1403
1404 rc = pci_register_driver(&pata_macio_pci_driver);
1405 if (rc)
1406 return rc;
1407 rc = macio_register_driver(&pata_macio_driver);
1408 if (rc) {
1409 pci_unregister_driver(&pata_macio_pci_driver);
1410 return rc;
1411 }
1412 return 0;
1413}
1414
1415static void __exit pata_macio_exit(void)
1416{
1417 macio_unregister_driver(&pata_macio_driver);
1418 pci_unregister_driver(&pata_macio_pci_driver);
1419}
1420
1421module_init(pata_macio_init);
1422module_exit(pata_macio_exit);
1423
1424MODULE_AUTHOR("Benjamin Herrenschmidt");
1425MODULE_DESCRIPTION("Apple MacIO PATA driver");
1426MODULE_LICENSE("GPL");
1427MODULE_VERSION(DRV_VERSION);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 23:29:04 -0500