1 files changed, 336 insertions, 0 deletions
diff --git a/drivers/ata/pata_cs5520.c b/drivers/ata/pata_cs5520.c
new file mode 100644
index 000000000000..792ce4828510
--- /dev/null
+++ b/drivers/ata/pata_cs5520.c
@@ -0,0 +1,336 @@
+/*
+ *      IDE tuning and bus mastering support for the CS5510/CS5520
+ *      chipsets
+ *
+ *      The CS5510/CS5520 are slightly unusual devices. Unlike the
+ *      typical IDE controllers they do bus mastering with the drive in
+ *      PIO mode and smarter silicon.
+ *
+ *      The practical upshot of this is that we must always tune the
+ *      drive for the right PIO mode. We must also ignore all the blacklists
+ *      and the drive bus mastering DMA information. Also to confuse matters
+ *      further we can do DMA on PIO only drives.
+ *
+ *      DMA on the 5510 also requires we disable_hlt() during DMA on early
+ *      revisions.
+ *
+ *      *** This driver is strictly experimental ***
+ *
+ *      (c) Copyright Red Hat Inc 2002
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2, or (at your option) any
+ * later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * Documentation:
+ *      Not publically available.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/blkdev.h>
+#include <linux/delay.h>
+#include <scsi/scsi_host.h>
+#include <linux/libata.h>
+#define DRV_NAME        "pata_cs5520"
+#define DRV_VERSION     "0.6.2"
+struct pio_clocks
+{
+        int address;
+        int assert;
+        int recovery;
+};
+static const struct pio_clocks cs5520_pio_clocks[]={
+        {3, 6, 11},
+        {2, 5, 6},
+        {1, 4, 3},
+        {1, 3, 2},
+        {1, 2, 1}
+};
+/**
+ *      cs5520_set_timings      -       program PIO timings
+ *      @ap: ATA port
+ *      @adev: ATA device
+ *
+ *      Program the PIO mode timings for the controller according to the pio
+ *      clocking table.
+ */
+static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int pio)
+{
+        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
+        int slave = adev->devno;
+        pio -= XFER_PIO_0;
+        /* Channel command timing */
+        pci_write_config_byte(pdev, 0x62 + ap->port_no,
+                                (cs5520_pio_clocks[pio].recovery << 4) |
+                                (cs5520_pio_clocks[pio].assert));
+        /* FIXME: should these use address ? */
+        /* Read command timing */
+        pci_write_config_byte(pdev, 0x64 +  4*ap->port_no + slave,
+                                (cs5520_pio_clocks[pio].recovery << 4) |
+                                (cs5520_pio_clocks[pio].assert));
+        /* Write command timing */
+        pci_write_config_byte(pdev, 0x66 +  4*ap->port_no + slave,
+                                (cs5520_pio_clocks[pio].recovery << 4) |
+                                (cs5520_pio_clocks[pio].assert));
+}
+/**
+ *      cs5520_enable_dma       -       turn on DMA bits
+ *
+ *      Turn on the DMA bits for this disk. Needed because the BIOS probably
+ *      has not done the work for us. Belongs in the core SATA code.
+ */
+static void cs5520_enable_dma(struct ata_port *ap, struct ata_device *adev)
+{
+        /* Set the DMA enable/disable flag */
+        u8 reg = inb(ap->ioaddr.bmdma_addr + 0x02);
+        reg |= 1<<(adev->devno + 5);
+        outb(reg, ap->ioaddr.bmdma_addr + 0x02);
+}
+/**
+ *      cs5520_set_dmamode      -       program DMA timings
+ *      @ap: ATA port
+ *      @adev: ATA device
+ *
+ *      Program the DMA mode timings for the controller according to the pio
+ *      clocking table. Note that this device sets the DMA timings to PIO
+ *      mode values. This may seem bizarre but the 5520 architecture talks
+ *      PIO mode to the disk and DMA mode to the controller so the underlying
+ *      transfers are PIO timed.
+ */
+static void cs5520_set_dmamode(struct ata_port *ap, struct ata_device *adev)
+{
+        static const int dma_xlate[3] = { XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 };
+        cs5520_set_timings(ap, adev, dma_xlate[adev->dma_mode]);
+        cs5520_enable_dma(ap, adev);
+}
+/**
+ *      cs5520_set_piomode      -       program PIO timings
+ *      @ap: ATA port
+ *      @adev: ATA device
+ *
+ *      Program the PIO mode timings for the controller according to the pio
+ *      clocking table. We know pio_mode will equal dma_mode because of the
+ *      CS5520 architecture. At least once we turned DMA on and wrote a
+ *      mode setter.
+ */
+static void cs5520_set_piomode(struct ata_port *ap, struct ata_device *adev)
+{
+        cs5520_set_timings(ap, adev, adev->pio_mode);
+}
+static int cs5520_pre_reset(struct ata_port *ap)
+{
+        ap->cbl = ATA_CBL_PATA40;
+        return ata_std_prereset(ap);
+}
+static void cs5520_error_handler(struct ata_port *ap)
+{
+        return ata_bmdma_drive_eh(ap, cs5520_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
+}
+static struct scsi_host_template cs5520_sht = {
+        .module                 = THIS_MODULE,
+        .name                   = DRV_NAME,
+        .ioctl                  = ata_scsi_ioctl,
+        .queuecommand           = ata_scsi_queuecmd,
+        .can_queue              = ATA_DEF_QUEUE,
+        .this_id                = ATA_SHT_THIS_ID,
+        .sg_tablesize           = LIBATA_MAX_PRD,
+        .max_sectors            = ATA_MAX_SECTORS,
+        .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
+        .emulated               = ATA_SHT_EMULATED,
+        .use_clustering         = ATA_SHT_USE_CLUSTERING,
+        .proc_name              = DRV_NAME,
+        .dma_boundary           = ATA_DMA_BOUNDARY,
+        .slave_configure        = ata_scsi_slave_config,
+        .bios_param             = ata_std_bios_param,
+};
+static struct ata_port_operations cs5520_port_ops = {
+        .port_disable           = ata_port_disable,
+        .set_piomode            = cs5520_set_piomode,
+        .set_dmamode            = cs5520_set_dmamode,
+        .tf_load                = ata_tf_load,
+        .tf_read                = ata_tf_read,
+        .check_status           = ata_check_status,
+        .exec_command           = ata_exec_command,
+        .dev_select             = ata_std_dev_select,
+        .freeze                 = ata_bmdma_freeze,
+        .thaw                   = ata_bmdma_thaw,
+        .error_handler          = cs5520_error_handler,
+        .post_internal_cmd      = ata_bmdma_post_internal_cmd,
+        .bmdma_setup            = ata_bmdma_setup,
+        .bmdma_start            = ata_bmdma_start,
+        .bmdma_stop             = ata_bmdma_stop,
+        .bmdma_status           = ata_bmdma_status,
+        .qc_prep                = ata_qc_prep,
+        .qc_issue               = ata_qc_issue_prot,
+        .data_xfer              = ata_pio_data_xfer,
+        .eng_timeout            = ata_eng_timeout,
+        .irq_handler            = ata_interrupt,
+        .irq_clear              = ata_bmdma_irq_clear,
+        .port_start             = ata_port_start,
+        .port_stop              = ata_port_stop,
+        .host_stop              = ata_host_stop,
+};
+static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
+{
+        u8 pcicfg;
+        static struct ata_probe_ent probe[2];
+        int ports = 0;
+        /* IDE port enable bits */
+        pci_read_config_byte(dev, 0x60, &pcicfg);
+        /* Check if the ATA ports are enabled */
+        if ((pcicfg & 3) == 0)
+                return -ENODEV;
+        if ((pcicfg & 0x40) == 0) {
+                printk(KERN_WARNING DRV_NAME ": DMA mode disabled. Enabling.\n");
+                pci_write_config_byte(dev, 0x60, pcicfg | 0x40);
+        }
+        /* Perform set up for DMA */
+        if (pci_enable_device_bars(dev, 1<<2)) {
+                printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n");
+                return -ENODEV;
+        }
+        pci_set_master(dev);
+        if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
+                printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n");
+                return -ENODEV;
+        }
+        if (pci_set_consistent_dma_mask(dev, DMA_32BIT_MASK)) {
+                printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n");
+                return -ENODEV;
+        }
+        /* We have to do our own plumbing as the PCI setup for this
+           chipset is non-standard so we can't punt to the libata code */
+        INIT_LIST_HEAD(&probe[0].node);
+        probe[0].dev = pci_dev_to_dev(dev);
+        probe[0].port_ops = &cs5520_port_ops;
+        probe[0].sht = &cs5520_sht;
+        probe[0].pio_mask = 0x1F;
+        probe[0].mwdma_mask = id->driver_data;
+        probe[0].irq = 14;
+        probe[0].irq_flags = 0;
+        probe[0].port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST;
+        probe[0].n_ports = 1;
+        probe[0].port[0].cmd_addr = 0x1F0;
+        probe[0].port[0].ctl_addr = 0x3F6;
+        probe[0].port[0].altstatus_addr = 0x3F6;
+        probe[0].port[0].bmdma_addr = pci_resource_start(dev, 2);
+        /* The secondary lurks at different addresses but is otherwise
+           the same beastie */
+        probe[1] = probe[0];
+        INIT_LIST_HEAD(&probe[1].node);
+        probe[1].irq = 15;
+        probe[1].port[0].cmd_addr = 0x170;
+        probe[1].port[0].ctl_addr = 0x376;
+        probe[1].port[0].altstatus_addr = 0x376;
+        probe[1].port[0].bmdma_addr = pci_resource_start(dev, 2) + 8;
+        /* Let libata fill in the port details */
+        ata_std_ports(&probe[0].port[0]);
+        ata_std_ports(&probe[1].port[0]);
+        /* Now add the ports that are active */
+        if (pcicfg & 1)
+                ports += ata_device_add(&probe[0]);
+        if (pcicfg & 2)
+                ports += ata_device_add(&probe[1]);
+        if (ports)
+                return 0;
+        return -ENODEV;
+}
+/**
+ *      cs5520_remove_one       -       device unload
+ *      @pdev: PCI device being removed
+ *
+ *      Handle an unplug/unload event for a PCI device. Unload the
+ *      PCI driver but do not use the default handler as we manage
+ *      resources ourself and *MUST NOT* disable the device as it has
+ *      other functions.
+ */
+static void __devexit cs5520_remove_one(struct pci_dev *pdev)
+{
+        struct device *dev = pci_dev_to_dev(pdev);
+        struct ata_host *host = dev_get_drvdata(dev);
+        ata_host_remove(host);
+        dev_set_drvdata(dev, NULL);
+}
+/* For now keep DMA off. We can set it for all but A rev CS5510 once the
+   core ATA code can handle it */
+static struct pci_device_id pata_cs5520[] = {
+        { PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510), },
+        { PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520), },
+        { 0, },
+};
+static struct pci_driver cs5520_pci_driver = {
+        .name           = DRV_NAME,
+        .id_table       = pata_cs5520,
+        .probe          = cs5520_init_one,
+        .remove         = cs5520_remove_one
+};
+static int __init cs5520_init(void)
+{
+        return pci_register_driver(&cs5520_pci_driver);
+}
+static void __exit cs5520_exit(void)
+{
+        pci_unregister_driver(&cs5520_pci_driver);
+}
+MODULE_AUTHOR("Alan Cox");
+MODULE_DESCRIPTION("low-level driver for Cyrix CS5510/5520");
+MODULE_LICENSE("GPL");
+MODULE_DEVICE_TABLE(pci, pata_cs5520);
+MODULE_VERSION(DRV_VERSION);
+module_init(cs5520_init);
+module_exit(cs5520_exit);

diff --git a/drivers/ata/pata_cs5520.c b/drivers/ata/pata_cs5520.c new file mode 100644 index 000000000000..792ce4828510 --- /dev/null +++ b/drivers/ata/pata_cs5520.c
@@ -0,0 +1,336 @@
	1	/*
	2	* IDE tuning and bus mastering support for the CS5510/CS5520
	3	* chipsets
	4	*
	5	* The CS5510/CS5520 are slightly unusual devices. Unlike the
	6	* typical IDE controllers they do bus mastering with the drive in
	7	* PIO mode and smarter silicon.
	8	*
	9	* The practical upshot of this is that we must always tune the
	10	* drive for the right PIO mode. We must also ignore all the blacklists
	11	* and the drive bus mastering DMA information. Also to confuse matters
	12	* further we can do DMA on PIO only drives.
	13	*
	14	* DMA on the 5510 also requires we disable_hlt() during DMA on early
	15	* revisions.
	16	*
	17	* * This driver is strictly experimental *
	18	*
	19	* (c) Copyright Red Hat Inc 2002
	20	*
	21	* This program is free software; you can redistribute it and/or modify it
	22	* under the terms of the GNU General Public License as published by the
	23	* Free Software Foundation; either version 2, or (at your option) any
	24	* later version.
	25	*
	26	* This program is distributed in the hope that it will be useful, but
	27	* WITHOUT ANY WARRANTY; without even the implied warranty of
	28	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	29	* General Public License for more details.
	30	*
	31	* Documentation:
	32	* Not publically available.
	33	*/
	34	#include <linux/kernel.h>
	35	#include <linux/module.h>
	36	#include <linux/pci.h>
	37	#include <linux/init.h>
	38	#include <linux/blkdev.h>
	39	#include <linux/delay.h>
	40	#include <scsi/scsi_host.h>
	41	#include <linux/libata.h>
	42
	43	#define DRV_NAME "pata_cs5520"
	44	#define DRV_VERSION "0.6.2"
	45
	46	struct pio_clocks
	47	{
	48	int address;
	49	int assert;
	50	int recovery;
	51	};
	52
	53	static const struct pio_clocks cs5520_pio_clocks[]={
	54	{3, 6, 11},
	55	{2, 5, 6},
	56	{1, 4, 3},
	57	{1, 3, 2},
	58	{1, 2, 1}
	59	};
	60
	61	/**
	62	* cs5520_set_timings - program PIO timings
	63	* @ap: ATA port
	64	* @adev: ATA device
	65	*
	66	* Program the PIO mode timings for the controller according to the pio
	67	* clocking table.
	68	*/
	69
	70	static void cs5520_set_timings(struct ata_port ap, struct ata_device adev, int pio)
	71	{
	72	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	73	int slave = adev->devno;
	74
	75	pio -= XFER_PIO_0;
	76
	77	/* Channel command timing */
	78	pci_write_config_byte(pdev, 0x62 + ap->port_no,
	79	(cs5520_pio_clocks[pio].recovery << 4) \|
	80	(cs5520_pio_clocks[pio].assert));
	81	/* FIXME: should these use address ? */
	82	/* Read command timing */
	83	pci_write_config_byte(pdev, 0x64 + 4*ap->port_no + slave,
	84	(cs5520_pio_clocks[pio].recovery << 4) \|
	85	(cs5520_pio_clocks[pio].assert));
	86	/* Write command timing */
	87	pci_write_config_byte(pdev, 0x66 + 4*ap->port_no + slave,
	88	(cs5520_pio_clocks[pio].recovery << 4) \|
	89	(cs5520_pio_clocks[pio].assert));
	90	}
	91
	92	/**
	93	* cs5520_enable_dma - turn on DMA bits
	94	*
	95	* Turn on the DMA bits for this disk. Needed because the BIOS probably
	96	* has not done the work for us. Belongs in the core SATA code.
	97	*/
	98
	99	static void cs5520_enable_dma(struct ata_port ap, struct ata_device adev)
	100	{
	101	/* Set the DMA enable/disable flag */
	102	u8 reg = inb(ap->ioaddr.bmdma_addr + 0x02);
	103	reg \|= 1<<(adev->devno + 5);
	104	outb(reg, ap->ioaddr.bmdma_addr + 0x02);
	105	}
	106
	107	/**
	108	* cs5520_set_dmamode - program DMA timings
	109	* @ap: ATA port
	110	* @adev: ATA device
	111	*
	112	* Program the DMA mode timings for the controller according to the pio
	113	* clocking table. Note that this device sets the DMA timings to PIO
	114	* mode values. This may seem bizarre but the 5520 architecture talks
	115	* PIO mode to the disk and DMA mode to the controller so the underlying
	116	* transfers are PIO timed.
	117	*/
	118
	119	static void cs5520_set_dmamode(struct ata_port ap, struct ata_device adev)
	120	{
	121	static const int dma_xlate[3] = { XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 };
	122	cs5520_set_timings(ap, adev, dma_xlate[adev->dma_mode]);
	123	cs5520_enable_dma(ap, adev);
	124	}
	125
	126	/**
	127	* cs5520_set_piomode - program PIO timings
	128	* @ap: ATA port
	129	* @adev: ATA device
	130	*
	131	* Program the PIO mode timings for the controller according to the pio
	132	* clocking table. We know pio_mode will equal dma_mode because of the
	133	* CS5520 architecture. At least once we turned DMA on and wrote a
	134	* mode setter.
	135	*/
	136
	137	static void cs5520_set_piomode(struct ata_port ap, struct ata_device adev)
	138	{
	139	cs5520_set_timings(ap, adev, adev->pio_mode);
	140	}
	141
	142
	143	static int cs5520_pre_reset(struct ata_port *ap)
	144	{
	145	ap->cbl = ATA_CBL_PATA40;
	146	return ata_std_prereset(ap);
	147	}
	148
	149	static void cs5520_error_handler(struct ata_port *ap)
	150	{
	151	return ata_bmdma_drive_eh(ap, cs5520_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
	152	}
	153
	154	static struct scsi_host_template cs5520_sht = {
	155	.module = THIS_MODULE,
	156	.name = DRV_NAME,
	157	.ioctl = ata_scsi_ioctl,
	158	.queuecommand = ata_scsi_queuecmd,
	159	.can_queue = ATA_DEF_QUEUE,
	160	.this_id = ATA_SHT_THIS_ID,
	161	.sg_tablesize = LIBATA_MAX_PRD,
	162	.max_sectors = ATA_MAX_SECTORS,
	163	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	164	.emulated = ATA_SHT_EMULATED,
	165	.use_clustering = ATA_SHT_USE_CLUSTERING,
	166	.proc_name = DRV_NAME,
	167	.dma_boundary = ATA_DMA_BOUNDARY,
	168	.slave_configure = ata_scsi_slave_config,
	169	.bios_param = ata_std_bios_param,
	170	};
	171
	172	static struct ata_port_operations cs5520_port_ops = {
	173	.port_disable = ata_port_disable,
	174	.set_piomode = cs5520_set_piomode,
	175	.set_dmamode = cs5520_set_dmamode,
	176
	177	.tf_load = ata_tf_load,
	178	.tf_read = ata_tf_read,
	179	.check_status = ata_check_status,
	180	.exec_command = ata_exec_command,
	181	.dev_select = ata_std_dev_select,
	182
	183	.freeze = ata_bmdma_freeze,
	184	.thaw = ata_bmdma_thaw,
	185	.error_handler = cs5520_error_handler,
	186	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	187
	188	.bmdma_setup = ata_bmdma_setup,
	189	.bmdma_start = ata_bmdma_start,
	190	.bmdma_stop = ata_bmdma_stop,
	191	.bmdma_status = ata_bmdma_status,
	192	.qc_prep = ata_qc_prep,
	193	.qc_issue = ata_qc_issue_prot,
	194	.data_xfer = ata_pio_data_xfer,
	195
	196	.eng_timeout = ata_eng_timeout,
	197
	198	.irq_handler = ata_interrupt,
	199	.irq_clear = ata_bmdma_irq_clear,
	200
	201	.port_start = ata_port_start,
	202	.port_stop = ata_port_stop,
	203	.host_stop = ata_host_stop,
	204	};
	205
	206	static int __devinit cs5520_init_one(struct pci_dev dev, const struct pci_device_id id)
	207	{
	208	u8 pcicfg;
	209	static struct ata_probe_ent probe[2];
	210	int ports = 0;
	211
	212	/* IDE port enable bits */
	213	pci_read_config_byte(dev, 0x60, &pcicfg);
	214
	215	/* Check if the ATA ports are enabled */
	216	if ((pcicfg & 3) == 0)
	217	return -ENODEV;
	218
	219	if ((pcicfg & 0x40) == 0) {
	220	printk(KERN_WARNING DRV_NAME ": DMA mode disabled. Enabling.\n");
	221	pci_write_config_byte(dev, 0x60, pcicfg \| 0x40);
	222	}
	223
	224	/* Perform set up for DMA */
	225	if (pci_enable_device_bars(dev, 1<<2)) {
	226	printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n");
	227	return -ENODEV;
	228	}
	229	pci_set_master(dev);
	230	if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
	231	printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n");
	232	return -ENODEV;
	233	}
	234	if (pci_set_consistent_dma_mask(dev, DMA_32BIT_MASK)) {
	235	printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n");
	236	return -ENODEV;
	237	}
	238
	239	/* We have to do our own plumbing as the PCI setup for this
	240	chipset is non-standard so we can't punt to the libata code */
	241
	242	INIT_LIST_HEAD(&probe[0].node);
	243	probe[0].dev = pci_dev_to_dev(dev);
	244	probe[0].port_ops = &cs5520_port_ops;
	245	probe[0].sht = &cs5520_sht;
	246	probe[0].pio_mask = 0x1F;
	247	probe[0].mwdma_mask = id->driver_data;
	248	probe[0].irq = 14;
	249	probe[0].irq_flags = 0;
	250	probe[0].port_flags = ATA_FLAG_SLAVE_POSS\|ATA_FLAG_SRST;
	251	probe[0].n_ports = 1;
	252	probe[0].port[0].cmd_addr = 0x1F0;
	253	probe[0].port[0].ctl_addr = 0x3F6;
	254	probe[0].port[0].altstatus_addr = 0x3F6;
	255	probe[0].port[0].bmdma_addr = pci_resource_start(dev, 2);
	256
	257	/* The secondary lurks at different addresses but is otherwise
	258	the same beastie */
	259
	260	probe[1] = probe[0];
	261	INIT_LIST_HEAD(&probe[1].node);
	262	probe[1].irq = 15;
	263	probe[1].port[0].cmd_addr = 0x170;
	264	probe[1].port[0].ctl_addr = 0x376;
	265	probe[1].port[0].altstatus_addr = 0x376;
	266	probe[1].port[0].bmdma_addr = pci_resource_start(dev, 2) + 8;
	267
	268	/* Let libata fill in the port details */
	269	ata_std_ports(&probe[0].port[0]);
	270	ata_std_ports(&probe[1].port[0]);
	271
	272	/* Now add the ports that are active */
	273	if (pcicfg & 1)
	274	ports += ata_device_add(&probe[0]);
	275	if (pcicfg & 2)
	276	ports += ata_device_add(&probe[1]);
	277	if (ports)
	278	return 0;
	279	return -ENODEV;
	280	}
	281
	282	/**
	283	* cs5520_remove_one - device unload
	284	* @pdev: PCI device being removed
	285	*
	286	* Handle an unplug/unload event for a PCI device. Unload the
	287	* PCI driver but do not use the default handler as we manage
	288	* resources ourself and MUST NOT disable the device as it has
	289	* other functions.
	290	*/
	291
	292	static void __devexit cs5520_remove_one(struct pci_dev *pdev)
	293	{
	294	struct device *dev = pci_dev_to_dev(pdev);
	295	struct ata_host *host = dev_get_drvdata(dev);
	296
	297	ata_host_remove(host);
	298	dev_set_drvdata(dev, NULL);
	299	}
	300
	301	/* For now keep DMA off. We can set it for all but A rev CS5510 once the
	302	core ATA code can handle it */
	303
	304	static struct pci_device_id pata_cs5520[] = {
	305	{ PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510), },
	306	{ PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520), },
	307	{ 0, },
	308	};
	309
	310	static struct pci_driver cs5520_pci_driver = {
	311	.name = DRV_NAME,
	312	.id_table = pata_cs5520,
	313	.probe = cs5520_init_one,
	314	.remove = cs5520_remove_one
	315	};
	316
	317
	318	static int __init cs5520_init(void)
	319	{
	320	return pci_register_driver(&cs5520_pci_driver);
	321	}
	322
	323	static void __exit cs5520_exit(void)
	324	{
	325	pci_unregister_driver(&cs5520_pci_driver);
	326	}
	327
	328	MODULE_AUTHOR("Alan Cox");
	329	MODULE_DESCRIPTION("low-level driver for Cyrix CS5510/5520");
	330	MODULE_LICENSE("GPL");
	331	MODULE_DEVICE_TABLE(pci, pata_cs5520);
	332	MODULE_VERSION(DRV_VERSION);
	333
	334	module_init(cs5520_init);
	335	module_exit(cs5520_exit);
	336