diff options
Diffstat (limited to 'drivers/ata/pata_cmd64x.c')
-rw-r--r-- | drivers/ata/pata_cmd64x.c | 88 |
1 files changed, 44 insertions, 44 deletions
diff --git a/drivers/ata/pata_cmd64x.c b/drivers/ata/pata_cmd64x.c index 03284611a727..abf1bb7bd322 100644 --- a/drivers/ata/pata_cmd64x.c +++ b/drivers/ata/pata_cmd64x.c | |||
@@ -20,7 +20,7 @@ | |||
20 | * TODO | 20 | * TODO |
21 | * Testing work | 21 | * Testing work |
22 | */ | 22 | */ |
23 | 23 | ||
24 | #include <linux/kernel.h> | 24 | #include <linux/kernel.h> |
25 | #include <linux/module.h> | 25 | #include <linux/module.h> |
26 | #include <linux/pci.h> | 26 | #include <linux/pci.h> |
@@ -36,7 +36,7 @@ | |||
36 | /* | 36 | /* |
37 | * CMD64x specific registers definition. | 37 | * CMD64x specific registers definition. |
38 | */ | 38 | */ |
39 | 39 | ||
40 | enum { | 40 | enum { |
41 | CFR = 0x50, | 41 | CFR = 0x50, |
42 | CFR_INTR_CH0 = 0x02, | 42 | CFR_INTR_CH0 = 0x02, |
@@ -90,9 +90,9 @@ static int cmd648_pre_reset(struct ata_port *ap) | |||
90 | pci_read_config_byte(pdev, BMIDECSR, &r); | 90 | pci_read_config_byte(pdev, BMIDECSR, &r); |
91 | if (r & (1 << ap->port_no)) | 91 | if (r & (1 << ap->port_no)) |
92 | ap->cbl = ATA_CBL_PATA80; | 92 | ap->cbl = ATA_CBL_PATA80; |
93 | else | 93 | else |
94 | ap->cbl = ATA_CBL_PATA40; | 94 | ap->cbl = ATA_CBL_PATA40; |
95 | 95 | ||
96 | return ata_std_prereset(ap); | 96 | return ata_std_prereset(ap); |
97 | } | 97 | } |
98 | 98 | ||
@@ -113,18 +113,18 @@ static void cmd648_error_handler(struct ata_port *ap) | |||
113 | * | 113 | * |
114 | * Called to do the PIO mode setup. | 114 | * Called to do the PIO mode setup. |
115 | */ | 115 | */ |
116 | 116 | ||
117 | static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev) | 117 | static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev) |
118 | { | 118 | { |
119 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | 119 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
120 | struct ata_timing t; | 120 | struct ata_timing t; |
121 | const unsigned long T = 1000000 / 33; | 121 | const unsigned long T = 1000000 / 33; |
122 | const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 }; | 122 | const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 }; |
123 | 123 | ||
124 | u8 reg; | 124 | u8 reg; |
125 | 125 | ||
126 | /* Port layout is not logical so use a table */ | 126 | /* Port layout is not logical so use a table */ |
127 | const u8 arttim_port[2][2] = { | 127 | const u8 arttim_port[2][2] = { |
128 | { ARTTIM0, ARTTIM1 }, | 128 | { ARTTIM0, ARTTIM1 }, |
129 | { ARTTIM23, ARTTIM23 } | 129 | { ARTTIM23, ARTTIM23 } |
130 | }; | 130 | }; |
@@ -132,11 +132,11 @@ static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev) | |||
132 | { DRWTIM0, DRWTIM1 }, | 132 | { DRWTIM0, DRWTIM1 }, |
133 | { DRWTIM2, DRWTIM3 } | 133 | { DRWTIM2, DRWTIM3 } |
134 | }; | 134 | }; |
135 | 135 | ||
136 | int arttim = arttim_port[ap->port_no][adev->devno]; | 136 | int arttim = arttim_port[ap->port_no][adev->devno]; |
137 | int drwtim = drwtim_port[ap->port_no][adev->devno]; | 137 | int drwtim = drwtim_port[ap->port_no][adev->devno]; |
138 | 138 | ||
139 | 139 | ||
140 | if (ata_timing_compute(adev, adev->pio_mode, &t, T, 0) < 0) { | 140 | if (ata_timing_compute(adev, adev->pio_mode, &t, T, 0) < 0) { |
141 | printk(KERN_ERR DRV_NAME ": mode computation failed.\n"); | 141 | printk(KERN_ERR DRV_NAME ": mode computation failed.\n"); |
142 | return; | 142 | return; |
@@ -144,14 +144,14 @@ static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev) | |||
144 | if (ap->port_no) { | 144 | if (ap->port_no) { |
145 | /* Slave has shared address setup */ | 145 | /* Slave has shared address setup */ |
146 | struct ata_device *pair = ata_dev_pair(adev); | 146 | struct ata_device *pair = ata_dev_pair(adev); |
147 | 147 | ||
148 | if (pair) { | 148 | if (pair) { |
149 | struct ata_timing tp; | 149 | struct ata_timing tp; |
150 | ata_timing_compute(pair, pair->pio_mode, &tp, T, 0); | 150 | ata_timing_compute(pair, pair->pio_mode, &tp, T, 0); |
151 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); | 151 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); |
152 | } | 152 | } |
153 | } | 153 | } |
154 | 154 | ||
155 | printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n", | 155 | printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n", |
156 | t.active, t.recover, t.setup); | 156 | t.active, t.recover, t.setup); |
157 | if (t.recover > 16) { | 157 | if (t.recover > 16) { |
@@ -160,30 +160,30 @@ static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev) | |||
160 | } | 160 | } |
161 | if (t.active > 16) | 161 | if (t.active > 16) |
162 | t.active = 16; | 162 | t.active = 16; |
163 | 163 | ||
164 | /* Now convert the clocks into values we can actually stuff into | 164 | /* Now convert the clocks into values we can actually stuff into |
165 | the chip */ | 165 | the chip */ |
166 | 166 | ||
167 | if (t.recover > 1) | 167 | if (t.recover > 1) |
168 | t.recover--; | 168 | t.recover--; |
169 | else | 169 | else |
170 | t.recover = 15; | 170 | t.recover = 15; |
171 | 171 | ||
172 | if (t.setup > 4) | 172 | if (t.setup > 4) |
173 | t.setup = 0xC0; | 173 | t.setup = 0xC0; |
174 | else | 174 | else |
175 | t.setup = setup_data[t.setup]; | 175 | t.setup = setup_data[t.setup]; |
176 | 176 | ||
177 | t.active &= 0x0F; /* 0 = 16 */ | 177 | t.active &= 0x0F; /* 0 = 16 */ |
178 | 178 | ||
179 | /* Load setup timing */ | 179 | /* Load setup timing */ |
180 | pci_read_config_byte(pdev, arttim, ®); | 180 | pci_read_config_byte(pdev, arttim, ®); |
181 | reg &= 0x3F; | 181 | reg &= 0x3F; |
182 | reg |= t.setup; | 182 | reg |= t.setup; |
183 | pci_write_config_byte(pdev, arttim, reg); | 183 | pci_write_config_byte(pdev, arttim, reg); |
184 | 184 | ||
185 | /* Load active/recovery */ | 185 | /* Load active/recovery */ |
186 | pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover); | 186 | pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover); |
187 | } | 187 | } |
188 | 188 | ||
189 | /** | 189 | /** |
@@ -193,29 +193,29 @@ static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev) | |||
193 | * | 193 | * |
194 | * Called to do the DMA mode setup. | 194 | * Called to do the DMA mode setup. |
195 | */ | 195 | */ |
196 | 196 | ||
197 | static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev) | 197 | static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
198 | { | 198 | { |
199 | static const u8 udma_data[] = { | 199 | static const u8 udma_data[] = { |
200 | 0x31, 0x21, 0x11, 0x25, 0x15, 0x05 | 200 | 0x31, 0x21, 0x11, 0x25, 0x15, 0x05 |
201 | }; | 201 | }; |
202 | static const u8 mwdma_data[] = { | 202 | static const u8 mwdma_data[] = { |
203 | 0x30, 0x20, 0x10 | 203 | 0x30, 0x20, 0x10 |
204 | }; | 204 | }; |
205 | 205 | ||
206 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | 206 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
207 | u8 regU, regD; | 207 | u8 regU, regD; |
208 | 208 | ||
209 | int pciU = UDIDETCR0 + 8 * ap->port_no; | 209 | int pciU = UDIDETCR0 + 8 * ap->port_no; |
210 | int pciD = BMIDESR0 + 8 * ap->port_no; | 210 | int pciD = BMIDESR0 + 8 * ap->port_no; |
211 | int shift = 2 * adev->devno; | 211 | int shift = 2 * adev->devno; |
212 | 212 | ||
213 | pci_read_config_byte(pdev, pciD, ®D); | 213 | pci_read_config_byte(pdev, pciD, ®D); |
214 | pci_read_config_byte(pdev, pciU, ®U); | 214 | pci_read_config_byte(pdev, pciU, ®U); |
215 | 215 | ||
216 | regD &= ~(0x20 << shift); | 216 | regD &= ~(0x20 << shift); |
217 | regU &= ~(0x35 << shift); | 217 | regU &= ~(0x35 << shift); |
218 | 218 | ||
219 | if (adev->dma_mode >= XFER_UDMA_0) | 219 | if (adev->dma_mode >= XFER_UDMA_0) |
220 | regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift; | 220 | regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift; |
221 | else | 221 | else |
@@ -241,13 +241,13 @@ static void cmd648_bmdma_stop(struct ata_queued_cmd *qc) | |||
241 | u8 dma_intr; | 241 | u8 dma_intr; |
242 | int dma_reg = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0; | 242 | int dma_reg = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0; |
243 | int dma_mask = ap->port_no ? ARTTIM2 : CFR; | 243 | int dma_mask = ap->port_no ? ARTTIM2 : CFR; |
244 | 244 | ||
245 | ata_bmdma_stop(qc); | 245 | ata_bmdma_stop(qc); |
246 | 246 | ||
247 | pci_read_config_byte(pdev, dma_reg, &dma_intr); | 247 | pci_read_config_byte(pdev, dma_reg, &dma_intr); |
248 | pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask); | 248 | pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask); |
249 | } | 249 | } |
250 | 250 | ||
251 | /** | 251 | /** |
252 | * cmd646r1_dma_stop - DMA stop callback | 252 | * cmd646r1_dma_stop - DMA stop callback |
253 | * @qc: Command in progress | 253 | * @qc: Command in progress |
@@ -259,7 +259,7 @@ static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc) | |||
259 | { | 259 | { |
260 | ata_bmdma_stop(qc); | 260 | ata_bmdma_stop(qc); |
261 | } | 261 | } |
262 | 262 | ||
263 | static struct scsi_host_template cmd64x_sht = { | 263 | static struct scsi_host_template cmd64x_sht = { |
264 | .module = THIS_MODULE, | 264 | .module = THIS_MODULE, |
265 | .name = DRV_NAME, | 265 | .name = DRV_NAME, |
@@ -306,11 +306,11 @@ static struct ata_port_operations cmd64x_port_ops = { | |||
306 | 306 | ||
307 | .irq_handler = ata_interrupt, | 307 | .irq_handler = ata_interrupt, |
308 | .irq_clear = ata_bmdma_irq_clear, | 308 | .irq_clear = ata_bmdma_irq_clear, |
309 | 309 | ||
310 | .port_start = ata_port_start, | 310 | .port_start = ata_port_start, |
311 | .port_stop = ata_port_stop, | 311 | .port_stop = ata_port_stop, |
312 | .host_stop = ata_host_stop | 312 | .host_stop = ata_host_stop |
313 | }; | 313 | }; |
314 | 314 | ||
315 | static struct ata_port_operations cmd646r1_port_ops = { | 315 | static struct ata_port_operations cmd646r1_port_ops = { |
316 | .port_disable = ata_port_disable, | 316 | .port_disable = ata_port_disable, |
@@ -340,11 +340,11 @@ static struct ata_port_operations cmd646r1_port_ops = { | |||
340 | 340 | ||
341 | .irq_handler = ata_interrupt, | 341 | .irq_handler = ata_interrupt, |
342 | .irq_clear = ata_bmdma_irq_clear, | 342 | .irq_clear = ata_bmdma_irq_clear, |
343 | 343 | ||
344 | .port_start = ata_port_start, | 344 | .port_start = ata_port_start, |
345 | .port_stop = ata_port_stop, | 345 | .port_stop = ata_port_stop, |
346 | .host_stop = ata_host_stop | 346 | .host_stop = ata_host_stop |
347 | }; | 347 | }; |
348 | 348 | ||
349 | static struct ata_port_operations cmd648_port_ops = { | 349 | static struct ata_port_operations cmd648_port_ops = { |
350 | .port_disable = ata_port_disable, | 350 | .port_disable = ata_port_disable, |
@@ -374,16 +374,16 @@ static struct ata_port_operations cmd648_port_ops = { | |||
374 | 374 | ||
375 | .irq_handler = ata_interrupt, | 375 | .irq_handler = ata_interrupt, |
376 | .irq_clear = ata_bmdma_irq_clear, | 376 | .irq_clear = ata_bmdma_irq_clear, |
377 | 377 | ||
378 | .port_start = ata_port_start, | 378 | .port_start = ata_port_start, |
379 | .port_stop = ata_port_stop, | 379 | .port_stop = ata_port_stop, |
380 | .host_stop = ata_host_stop | 380 | .host_stop = ata_host_stop |
381 | }; | 381 | }; |
382 | 382 | ||
383 | static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) | 383 | static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
384 | { | 384 | { |
385 | u32 class_rev; | 385 | u32 class_rev; |
386 | 386 | ||
387 | static struct ata_port_info cmd_info[6] = { | 387 | static struct ata_port_info cmd_info[6] = { |
388 | { /* CMD 643 - no UDMA */ | 388 | { /* CMD 643 - no UDMA */ |
389 | .sht = &cmd64x_sht, | 389 | .sht = &cmd64x_sht, |
@@ -433,15 +433,15 @@ static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) | |||
433 | }; | 433 | }; |
434 | static struct ata_port_info *port_info[2], *info; | 434 | static struct ata_port_info *port_info[2], *info; |
435 | u8 mrdmode; | 435 | u8 mrdmode; |
436 | 436 | ||
437 | info = &cmd_info[id->driver_data]; | 437 | info = &cmd_info[id->driver_data]; |
438 | 438 | ||
439 | pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev); | 439 | pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev); |
440 | class_rev &= 0xFF; | 440 | class_rev &= 0xFF; |
441 | 441 | ||
442 | if (id->driver_data == 0) /* 643 */ | 442 | if (id->driver_data == 0) /* 643 */ |
443 | ata_pci_clear_simplex(pdev); | 443 | ata_pci_clear_simplex(pdev); |
444 | 444 | ||
445 | if (pdev->device == PCI_DEVICE_ID_CMD_646) { | 445 | if (pdev->device == PCI_DEVICE_ID_CMD_646) { |
446 | /* Does UDMA work ? */ | 446 | /* Does UDMA work ? */ |
447 | if (class_rev > 4) | 447 | if (class_rev > 4) |
@@ -456,14 +456,14 @@ static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) | |||
456 | mrdmode &= ~ 0x30; /* IRQ set up */ | 456 | mrdmode &= ~ 0x30; /* IRQ set up */ |
457 | mrdmode |= 0x02; /* Memory read line enable */ | 457 | mrdmode |= 0x02; /* Memory read line enable */ |
458 | pci_write_config_byte(pdev, MRDMODE, mrdmode); | 458 | pci_write_config_byte(pdev, MRDMODE, mrdmode); |
459 | 459 | ||
460 | /* Force PIO 0 here.. */ | 460 | /* Force PIO 0 here.. */ |
461 | 461 | ||
462 | /* PPC specific fixup copied from old driver */ | 462 | /* PPC specific fixup copied from old driver */ |
463 | #ifdef CONFIG_PPC | 463 | #ifdef CONFIG_PPC |
464 | pci_write_config_byte(pdev, UDIDETCR0, 0xF0); | 464 | pci_write_config_byte(pdev, UDIDETCR0, 0xF0); |
465 | #endif | 465 | #endif |
466 | 466 | ||
467 | port_info[0] = port_info[1] = info; | 467 | port_info[0] = port_info[1] = info; |
468 | return ata_pci_init_one(pdev, port_info, 2); | 468 | return ata_pci_init_one(pdev, port_info, 2); |
469 | } | 469 | } |