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-rw-r--r--drivers/ata/pata_artop.c518
1 files changed, 518 insertions, 0 deletions
diff --git a/drivers/ata/pata_artop.c b/drivers/ata/pata_artop.c
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1/*
2 * pata_artop.c - ARTOP ATA controller driver
3 *
4 * (C) 2006 Red Hat <alan@redhat.com>
5 *
6 * Based in part on drivers/ide/pci/aec62xx.c
7 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
8 * 865/865R fixes for Macintosh card version from a patch to the old
9 * driver by Thibaut VARENE <varenet@parisc-linux.org>
10 * When setting the PCI latency we must set 0x80 or higher for burst
11 * performance Alessandro Zummo <alessandro.zummo@towertech.it>
12 *
13 * TODO
14 * 850 serialization once the core supports it
15 * Investigate no_dsc on 850R
16 * Clock detect
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/init.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <linux/device.h>
26#include <scsi/scsi_host.h>
27#include <linux/libata.h>
28#include <linux/ata.h>
29
30#define DRV_NAME "pata_artop"
31#define DRV_VERSION "0.4.1"
32
33/*
34 * The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
35 * get PCI bus speed functionality we leave this as 0. Its a variable
36 * for when we get the functionality and also for folks wanting to
37 * test stuff.
38 */
39
40static int clock = 0;
41
42static int artop6210_pre_reset(struct ata_port *ap)
43{
44 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
45 const struct pci_bits artop_enable_bits[] = {
46 { 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
47 { 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
48 };
49
50 if (!pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no])) {
51 ata_port_disable(ap);
52 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
53 return 0;
54 }
55 ap->cbl = ATA_CBL_PATA40;
56 return ata_std_prereset(ap);
57}
58
59/**
60 * artop6210_error_handler - Probe specified port on PATA host controller
61 * @ap: Port to probe
62 *
63 * LOCKING:
64 * None (inherited from caller).
65 */
66
67static void artop6210_error_handler(struct ata_port *ap)
68{
69 ata_bmdma_drive_eh(ap, artop6210_pre_reset,
70 ata_std_softreset, NULL,
71 ata_std_postreset);
72}
73
74/**
75 * artop6260_pre_reset - check for 40/80 pin
76 * @ap: Port
77 *
78 * The ARTOP hardware reports the cable detect bits in register 0x49.
79 * Nothing complicated needed here.
80 */
81
82static int artop6260_pre_reset(struct ata_port *ap)
83{
84 static const struct pci_bits artop_enable_bits[] = {
85 { 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
86 { 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
87 };
88
89 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
90 u8 tmp;
91
92 /* Odd numbered device ids are the units with enable bits (the -R cards) */
93 if (pdev->device % 1 && !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no])) {
94 ata_port_disable(ap);
95 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
96 return 0;
97 }
98 pci_read_config_byte(pdev, 0x49, &tmp);
99 if (tmp & (1 >> ap->port_no))
100 ap->cbl = ATA_CBL_PATA40;
101 else
102 ap->cbl = ATA_CBL_PATA80;
103 return ata_std_prereset(ap);
104}
105
106/**
107 * artop6260_error_handler - Probe specified port on PATA host controller
108 * @ap: Port to probe
109 *
110 * LOCKING:
111 * None (inherited from caller).
112 */
113
114static void artop6260_error_handler(struct ata_port *ap)
115{
116 ata_bmdma_drive_eh(ap, artop6260_pre_reset,
117 ata_std_softreset, NULL,
118 ata_std_postreset);
119}
120
121/**
122 * artop6210_load_piomode - Load a set of PATA PIO timings
123 * @ap: Port whose timings we are configuring
124 * @adev: Device
125 * @pio: PIO mode
126 *
127 * Set PIO mode for device, in host controller PCI config space. This
128 * is used both to set PIO timings in PIO mode and also to set the
129 * matching PIO clocking for UDMA, as well as the MWDMA timings.
130 *
131 * LOCKING:
132 * None (inherited from caller).
133 */
134
135static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio)
136{
137 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
138 int dn = adev->devno + 2 * ap->port_no;
139 const u16 timing[2][5] = {
140 { 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
141 { 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }
142
143 };
144 /* Load the PIO timing active/recovery bits */
145 pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
146}
147
148/**
149 * artop6210_set_piomode - Initialize host controller PATA PIO timings
150 * @ap: Port whose timings we are configuring
151 * @adev: Device we are configuring
152 *
153 * Set PIO mode for device, in host controller PCI config space. For
154 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
155 * the event UDMA is used the later call to set_dmamode will set the
156 * bits as required.
157 *
158 * LOCKING:
159 * None (inherited from caller).
160 */
161
162static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev)
163{
164 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
165 int dn = adev->devno + 2 * ap->port_no;
166 u8 ultra;
167
168 artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
169
170 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
171 pci_read_config_byte(pdev, 0x54, &ultra);
172 ultra &= ~(3 << (2 * dn));
173 pci_write_config_byte(pdev, 0x54, ultra);
174}
175
176/**
177 * artop6260_load_piomode - Initialize host controller PATA PIO timings
178 * @ap: Port whose timings we are configuring
179 * @adev: Device we are configuring
180 * @pio: PIO mode
181 *
182 * Set PIO mode for device, in host controller PCI config space. The
183 * ARTOP6260 and relatives store the timing data differently.
184 *
185 * LOCKING:
186 * None (inherited from caller).
187 */
188
189static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio)
190{
191 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
192 int dn = adev->devno + 2 * ap->port_no;
193 const u8 timing[2][5] = {
194 { 0x00, 0x0A, 0x08, 0x33, 0x31 },
195 { 0x70, 0x7A, 0x78, 0x43, 0x41 }
196
197 };
198 /* Load the PIO timing active/recovery bits */
199 pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
200}
201
202/**
203 * artop6260_set_piomode - Initialize host controller PATA PIO timings
204 * @ap: Port whose timings we are configuring
205 * @adev: Device we are configuring
206 *
207 * Set PIO mode for device, in host controller PCI config space. For
208 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
209 * the event UDMA is used the later call to set_dmamode will set the
210 * bits as required.
211 *
212 * LOCKING:
213 * None (inherited from caller).
214 */
215
216static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev)
217{
218 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
219 u8 ultra;
220
221 artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
222
223 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
224 pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
225 ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
226 pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
227}
228
229/**
230 * artop6210_set_dmamode - Initialize host controller PATA PIO timings
231 * @ap: Port whose timings we are configuring
232 * @adev: um
233 *
234 * Set DMA mode for device, in host controller PCI config space.
235 *
236 * LOCKING:
237 * None (inherited from caller).
238 */
239
240static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev)
241{
242 unsigned int pio;
243 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
244 int dn = adev->devno + 2 * ap->port_no;
245 u8 ultra;
246
247 if (adev->dma_mode == XFER_MW_DMA_0)
248 pio = 1;
249 else
250 pio = 4;
251
252 /* Load the PIO timing active/recovery bits */
253 artop6210_load_piomode(ap, adev, pio);
254
255 pci_read_config_byte(pdev, 0x54, &ultra);
256 ultra &= ~(3 << (2 * dn));
257
258 /* Add ultra DMA bits if in UDMA mode */
259 if (adev->dma_mode >= XFER_UDMA_0) {
260 u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
261 if (mode == 0)
262 mode = 1;
263 ultra |= (mode << (2 * dn));
264 }
265 pci_write_config_byte(pdev, 0x54, ultra);
266}
267
268/**
269 * artop6260_set_dmamode - Initialize host controller PATA PIO timings
270 * @ap: Port whose timings we are configuring
271 * @adev: Device we are configuring
272 *
273 * Set DMA mode for device, in host controller PCI config space. The
274 * ARTOP6260 and relatives store the timing data differently.
275 *
276 * LOCKING:
277 * None (inherited from caller).
278 */
279
280static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev)
281{
282 unsigned int pio = adev->pio_mode - XFER_PIO_0;
283 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
284 u8 ultra;
285
286 if (adev->dma_mode == XFER_MW_DMA_0)
287 pio = 1;
288 else
289 pio = 4;
290
291 /* Load the PIO timing active/recovery bits */
292 artop6260_load_piomode(ap, adev, pio);
293
294 /* Add ultra DMA bits if in UDMA mode */
295 pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
296 ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
297 if (adev->dma_mode >= XFER_UDMA_0) {
298 u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
299 if (mode == 0)
300 mode = 1;
301 ultra |= (mode << (4 * adev->devno));
302 }
303 pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
304}
305
306static struct scsi_host_template artop_sht = {
307 .module = THIS_MODULE,
308 .name = DRV_NAME,
309 .ioctl = ata_scsi_ioctl,
310 .queuecommand = ata_scsi_queuecmd,
311 .can_queue = ATA_DEF_QUEUE,
312 .this_id = ATA_SHT_THIS_ID,
313 .sg_tablesize = LIBATA_MAX_PRD,
314 .max_sectors = ATA_MAX_SECTORS,
315 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
316 .emulated = ATA_SHT_EMULATED,
317 .use_clustering = ATA_SHT_USE_CLUSTERING,
318 .proc_name = DRV_NAME,
319 .dma_boundary = ATA_DMA_BOUNDARY,
320 .slave_configure = ata_scsi_slave_config,
321 .bios_param = ata_std_bios_param,
322};
323
324static const struct ata_port_operations artop6210_ops = {
325 .port_disable = ata_port_disable,
326 .set_piomode = artop6210_set_piomode,
327 .set_dmamode = artop6210_set_dmamode,
328 .mode_filter = ata_pci_default_filter,
329
330 .tf_load = ata_tf_load,
331 .tf_read = ata_tf_read,
332 .check_status = ata_check_status,
333 .exec_command = ata_exec_command,
334 .dev_select = ata_std_dev_select,
335
336 .freeze = ata_bmdma_freeze,
337 .thaw = ata_bmdma_thaw,
338 .error_handler = artop6210_error_handler,
339 .post_internal_cmd = ata_bmdma_post_internal_cmd,
340
341 .bmdma_setup = ata_bmdma_setup,
342 .bmdma_start = ata_bmdma_start,
343 .bmdma_stop = ata_bmdma_stop,
344 .bmdma_status = ata_bmdma_status,
345 .qc_prep = ata_qc_prep,
346 .qc_issue = ata_qc_issue_prot,
347 .eng_timeout = ata_eng_timeout,
348 .data_xfer = ata_pio_data_xfer,
349
350 .irq_handler = ata_interrupt,
351 .irq_clear = ata_bmdma_irq_clear,
352
353 .port_start = ata_port_start,
354 .port_stop = ata_port_stop,
355 .host_stop = ata_host_stop,
356};
357
358static const struct ata_port_operations artop6260_ops = {
359 .port_disable = ata_port_disable,
360 .set_piomode = artop6260_set_piomode,
361 .set_dmamode = artop6260_set_dmamode,
362
363 .tf_load = ata_tf_load,
364 .tf_read = ata_tf_read,
365 .check_status = ata_check_status,
366 .exec_command = ata_exec_command,
367 .dev_select = ata_std_dev_select,
368
369 .freeze = ata_bmdma_freeze,
370 .thaw = ata_bmdma_thaw,
371 .error_handler = artop6260_error_handler,
372 .post_internal_cmd = ata_bmdma_post_internal_cmd,
373
374 .bmdma_setup = ata_bmdma_setup,
375 .bmdma_start = ata_bmdma_start,
376 .bmdma_stop = ata_bmdma_stop,
377 .bmdma_status = ata_bmdma_status,
378 .qc_prep = ata_qc_prep,
379 .qc_issue = ata_qc_issue_prot,
380 .data_xfer = ata_pio_data_xfer,
381
382 .eng_timeout = ata_eng_timeout,
383
384 .irq_handler = ata_interrupt,
385 .irq_clear = ata_bmdma_irq_clear,
386
387 .port_start = ata_port_start,
388 .port_stop = ata_port_stop,
389 .host_stop = ata_host_stop,
390};
391
392
393/**
394 * artop_init_one - Register ARTOP ATA PCI device with kernel services
395 * @pdev: PCI device to register
396 * @ent: Entry in artop_pci_tbl matching with @pdev
397 *
398 * Called from kernel PCI layer.
399 *
400 * LOCKING:
401 * Inherited from PCI layer (may sleep).
402 *
403 * RETURNS:
404 * Zero on success, or -ERRNO value.
405 */
406
407static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
408{
409 static int printed_version;
410 static struct ata_port_info info_6210 = {
411 .sht = &artop_sht,
412 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
413 .pio_mask = 0x1f, /* pio0-4 */
414 .mwdma_mask = 0x07, /* mwdma0-2 */
415 .udma_mask = ATA_UDMA2,
416 .port_ops = &artop6210_ops,
417 };
418 static struct ata_port_info info_626x = {
419 .sht = &artop_sht,
420 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
421 .pio_mask = 0x1f, /* pio0-4 */
422 .mwdma_mask = 0x07, /* mwdma0-2 */
423 .udma_mask = ATA_UDMA4,
424 .port_ops = &artop6260_ops,
425 };
426 static struct ata_port_info info_626x_fast = {
427 .sht = &artop_sht,
428 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
429 .pio_mask = 0x1f, /* pio0-4 */
430 .mwdma_mask = 0x07, /* mwdma0-2 */
431 .udma_mask = ATA_UDMA5,
432 .port_ops = &artop6260_ops,
433 };
434 struct ata_port_info *port_info[2];
435 struct ata_port_info *info;
436 int ports = 2;
437
438 if (!printed_version++)
439 dev_printk(KERN_DEBUG, &pdev->dev,
440 "version " DRV_VERSION "\n");
441
442 if (id->driver_data == 0) { /* 6210 variant */
443 info = &info_6210;
444 /* BIOS may have left us in UDMA, clear it before libata probe */
445 pci_write_config_byte(pdev, 0x54, 0);
446 /* For the moment (also lacks dsc) */
447 printk(KERN_WARNING "ARTOP 6210 requires serialize functionality not yet supported by libata.\n");
448 printk(KERN_WARNING "Secondary ATA ports will not be activated.\n");
449 ports = 1;
450 }
451 else if (id->driver_data == 1) /* 6260 */
452 info = &info_626x;
453 else if (id->driver_data == 2) { /* 6260 or 6260 + fast */
454 unsigned long io = pci_resource_start(pdev, 4);
455 u8 reg;
456
457 info = &info_626x;
458 if (inb(io) & 0x10)
459 info = &info_626x_fast;
460 /* Mac systems come up with some registers not set as we
461 will need them */
462
463 /* Clear reset & test bits */
464 pci_read_config_byte(pdev, 0x49, &reg);
465 pci_write_config_byte(pdev, 0x49, reg & ~ 0x30);
466
467 /* PCI latency must be > 0x80 for burst mode, tweak it
468 * if required.
469 */
470 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &reg);
471 if (reg <= 0x80)
472 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);
473
474 /* Enable IRQ output and burst mode */
475 pci_read_config_byte(pdev, 0x4a, &reg);
476 pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);
477
478 }
479 port_info[0] = port_info[1] = info;
480 return ata_pci_init_one(pdev, port_info, ports);
481}
482
483static const struct pci_device_id artop_pci_tbl[] = {
484 { 0x1191, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
485 { 0x1191, 0x0006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
486 { 0x1191, 0x0007, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
487 { 0x1191, 0x0008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
488 { 0x1191, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
489 { } /* terminate list */
490};
491
492static struct pci_driver artop_pci_driver = {
493 .name = DRV_NAME,
494 .id_table = artop_pci_tbl,
495 .probe = artop_init_one,
496 .remove = ata_pci_remove_one,
497};
498
499static int __init artop_init(void)
500{
501 return pci_register_driver(&artop_pci_driver);
502}
503
504static void __exit artop_exit(void)
505{
506 pci_unregister_driver(&artop_pci_driver);
507}
508
509
510module_init(artop_init);
511module_exit(artop_exit);
512
513MODULE_AUTHOR("Alan Cox");
514MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
515MODULE_LICENSE("GPL");
516MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
517MODULE_VERSION(DRV_VERSION);
518