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-rw-r--r--drivers/ata/pata_amd.c707
1 files changed, 707 insertions, 0 deletions
diff --git a/drivers/ata/pata_amd.c b/drivers/ata/pata_amd.c
new file mode 100644
index 000000000000..6ab568428a14
--- /dev/null
+++ b/drivers/ata/pata_amd.c
@@ -0,0 +1,707 @@
1/*
2 * pata_amd.c - AMD PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based on pata-sil680. Errata information is taken from data sheets
7 * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
8 * claimed by sata-nv.c.
9 *
10 * TODO:
11 * Variable system clock when/if it makes sense
12 * Power management on ports
13 *
14 *
15 * Documentation publically available.
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26
27#define DRV_NAME "pata_amd"
28#define DRV_VERSION "0.2.2"
29
30/**
31 * timing_setup - shared timing computation and load
32 * @ap: ATA port being set up
33 * @adev: drive being configured
34 * @offset: port offset
35 * @speed: target speed
36 * @clock: clock multiplier (number of times 33MHz for this part)
37 *
38 * Perform the actual timing set up for Nvidia or AMD PATA devices.
39 * The actual devices vary so they all call into this helper function
40 * providing the clock multipler and offset (because AMD and Nvidia put
41 * the ports at different locations).
42 */
43
44static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
45{
46 static const unsigned char amd_cyc2udma[] = {
47 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
48 };
49
50 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
51 struct ata_device *peer = ata_dev_pair(adev);
52 int dn = ap->port_no * 2 + adev->devno;
53 struct ata_timing at, apeer;
54 int T, UT;
55 const int amd_clock = 33333; /* KHz. */
56 u8 t;
57
58 T = 1000000000 / amd_clock;
59 UT = T / min_t(int, max_t(int, clock, 1), 2);
60
61 if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
62 dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed);
63 return;
64 }
65
66 if (peer) {
67 /* This may be over conservative */
68 if (peer->dma_mode) {
69 ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
70 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
71 }
72 ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
73 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
74 }
75
76 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
77 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
78
79 /*
80 * Now do the setup work
81 */
82
83 /* Configure the address set up timing */
84 pci_read_config_byte(pdev, offset + 0x0C, &t);
85 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
86 pci_write_config_byte(pdev, offset + 0x0C , t);
87
88 /* Configure the 8bit I/O timing */
89 pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
90 ((FIT(at.act8b, 1, 16) - 1) << 4) | (FIT(at.rec8b, 1, 16) - 1));
91
92 /* Drive timing */
93 pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
94 ((FIT(at.active, 1, 16) - 1) << 4) | (FIT(at.recover, 1, 16) - 1));
95
96 switch (clock) {
97 case 1:
98 t = at.udma ? (0xc0 | (FIT(at.udma, 2, 5) - 2)) : 0x03;
99 break;
100
101 case 2:
102 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 2, 10)]) : 0x03;
103 break;
104
105 case 3:
106 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 10)]) : 0x03;
107 break;
108
109 case 4:
110 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 15)]) : 0x03;
111 break;
112
113 default:
114 return;
115 }
116
117 /* UDMA timing */
118 pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
119}
120
121/**
122 * amd_probe_init - cable detection
123 * @ap: ATA port
124 *
125 * Perform cable detection. The BIOS stores this in PCI config
126 * space for us.
127 */
128
129static int amd_pre_reset(struct ata_port *ap)
130{
131 static const u32 bitmask[2] = {0x03, 0xC0};
132 static const struct pci_bits amd_enable_bits[] = {
133 { 0x40, 1, 0x02, 0x02 },
134 { 0x40, 1, 0x01, 0x01 }
135 };
136
137 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
138 u8 ata66;
139
140 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no])) {
141 ata_port_disable(ap);
142 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
143 return 0;
144 }
145
146 pci_read_config_byte(pdev, 0x42, &ata66);
147 if (ata66 & bitmask[ap->port_no])
148 ap->cbl = ATA_CBL_PATA80;
149 else
150 ap->cbl = ATA_CBL_PATA40;
151 return ata_std_prereset(ap);
152
153}
154
155static void amd_error_handler(struct ata_port *ap)
156{
157 return ata_bmdma_drive_eh(ap, amd_pre_reset,
158 ata_std_softreset, NULL,
159 ata_std_postreset);
160}
161
162static int amd_early_pre_reset(struct ata_port *ap)
163{
164 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
165 static struct pci_bits amd_enable_bits[] = {
166 { 0x40, 1, 0x02, 0x02 },
167 { 0x40, 1, 0x01, 0x01 }
168 };
169
170 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no])) {
171 ata_port_disable(ap);
172 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
173 return 0;
174 }
175 /* No host side cable detection */
176 ap->cbl = ATA_CBL_PATA80;
177 return ata_std_prereset(ap);
178
179}
180
181static void amd_early_error_handler(struct ata_port *ap)
182{
183 ata_bmdma_drive_eh(ap, amd_early_pre_reset,
184 ata_std_softreset, NULL,
185 ata_std_postreset);
186}
187
188/**
189 * amd33_set_piomode - set initial PIO mode data
190 * @ap: ATA interface
191 * @adev: ATA device
192 *
193 * Program the AMD registers for PIO mode.
194 */
195
196static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
197{
198 timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
199}
200
201static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
202{
203 timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
204}
205
206static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
207{
208 timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
209}
210
211static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
212{
213 timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
214}
215
216/**
217 * amd33_set_dmamode - set initial DMA mode data
218 * @ap: ATA interface
219 * @adev: ATA device
220 *
221 * Program the MWDMA/UDMA modes for the AMD and Nvidia
222 * chipset.
223 */
224
225static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
226{
227 timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
228}
229
230static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
231{
232 timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
233}
234
235static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
236{
237 timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
238}
239
240static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
241{
242 timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
243}
244
245
246/**
247 * nv_probe_init - cable detection
248 * @ap: ATA port
249 *
250 * Perform cable detection. The BIOS stores this in PCI config
251 * space for us.
252 */
253
254static int nv_pre_reset(struct ata_port *ap) {
255 static const u8 bitmask[2] = {0x03, 0xC0};
256
257 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
258 u8 ata66;
259 u16 udma;
260
261 pci_read_config_byte(pdev, 0x52, &ata66);
262 if (ata66 & bitmask[ap->port_no])
263 ap->cbl = ATA_CBL_PATA80;
264 else
265 ap->cbl = ATA_CBL_PATA40;
266
267 /* We now have to double check because the Nvidia boxes BIOS
268 doesn't always set the cable bits but does set mode bits */
269
270 pci_read_config_word(pdev, 0x62 - 2 * ap->port_no, &udma);
271 if ((udma & 0xC4) == 0xC4 || (udma & 0xC400) == 0xC400)
272 ap->cbl = ATA_CBL_PATA80;
273 return ata_std_prereset(ap);
274}
275
276static void nv_error_handler(struct ata_port *ap)
277{
278 ata_bmdma_drive_eh(ap, nv_pre_reset,
279 ata_std_softreset, NULL,
280 ata_std_postreset);
281}
282/**
283 * nv100_set_piomode - set initial PIO mode data
284 * @ap: ATA interface
285 * @adev: ATA device
286 *
287 * Program the AMD registers for PIO mode.
288 */
289
290static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
291{
292 timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
293}
294
295static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
296{
297 timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
298}
299
300/**
301 * nv100_set_dmamode - set initial DMA mode data
302 * @ap: ATA interface
303 * @adev: ATA device
304 *
305 * Program the MWDMA/UDMA modes for the AMD and Nvidia
306 * chipset.
307 */
308
309static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
310{
311 timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
312}
313
314static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
315{
316 timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
317}
318
319static struct scsi_host_template amd_sht = {
320 .module = THIS_MODULE,
321 .name = DRV_NAME,
322 .ioctl = ata_scsi_ioctl,
323 .queuecommand = ata_scsi_queuecmd,
324 .can_queue = ATA_DEF_QUEUE,
325 .this_id = ATA_SHT_THIS_ID,
326 .sg_tablesize = LIBATA_MAX_PRD,
327 .max_sectors = ATA_MAX_SECTORS,
328 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
329 .emulated = ATA_SHT_EMULATED,
330 .use_clustering = ATA_SHT_USE_CLUSTERING,
331 .proc_name = DRV_NAME,
332 .dma_boundary = ATA_DMA_BOUNDARY,
333 .slave_configure = ata_scsi_slave_config,
334 .bios_param = ata_std_bios_param,
335};
336
337static struct ata_port_operations amd33_port_ops = {
338 .port_disable = ata_port_disable,
339 .set_piomode = amd33_set_piomode,
340 .set_dmamode = amd33_set_dmamode,
341 .mode_filter = ata_pci_default_filter,
342 .tf_load = ata_tf_load,
343 .tf_read = ata_tf_read,
344 .check_status = ata_check_status,
345 .exec_command = ata_exec_command,
346 .dev_select = ata_std_dev_select,
347
348 .freeze = ata_bmdma_freeze,
349 .thaw = ata_bmdma_thaw,
350 .error_handler = amd_early_error_handler,
351 .post_internal_cmd = ata_bmdma_post_internal_cmd,
352
353 .bmdma_setup = ata_bmdma_setup,
354 .bmdma_start = ata_bmdma_start,
355 .bmdma_stop = ata_bmdma_stop,
356 .bmdma_status = ata_bmdma_status,
357
358 .qc_prep = ata_qc_prep,
359 .qc_issue = ata_qc_issue_prot,
360 .eng_timeout = ata_eng_timeout,
361 .data_xfer = ata_pio_data_xfer,
362
363 .irq_handler = ata_interrupt,
364 .irq_clear = ata_bmdma_irq_clear,
365
366 .port_start = ata_port_start,
367 .port_stop = ata_port_stop,
368 .host_stop = ata_host_stop
369};
370
371static struct ata_port_operations amd66_port_ops = {
372 .port_disable = ata_port_disable,
373 .set_piomode = amd66_set_piomode,
374 .set_dmamode = amd66_set_dmamode,
375 .mode_filter = ata_pci_default_filter,
376 .tf_load = ata_tf_load,
377 .tf_read = ata_tf_read,
378 .check_status = ata_check_status,
379 .exec_command = ata_exec_command,
380 .dev_select = ata_std_dev_select,
381
382 .freeze = ata_bmdma_freeze,
383 .thaw = ata_bmdma_thaw,
384 .error_handler = amd_early_error_handler,
385 .post_internal_cmd = ata_bmdma_post_internal_cmd,
386
387 .bmdma_setup = ata_bmdma_setup,
388 .bmdma_start = ata_bmdma_start,
389 .bmdma_stop = ata_bmdma_stop,
390 .bmdma_status = ata_bmdma_status,
391
392 .qc_prep = ata_qc_prep,
393 .qc_issue = ata_qc_issue_prot,
394 .eng_timeout = ata_eng_timeout,
395 .data_xfer = ata_pio_data_xfer,
396
397 .irq_handler = ata_interrupt,
398 .irq_clear = ata_bmdma_irq_clear,
399
400 .port_start = ata_port_start,
401 .port_stop = ata_port_stop,
402 .host_stop = ata_host_stop
403};
404
405static struct ata_port_operations amd100_port_ops = {
406 .port_disable = ata_port_disable,
407 .set_piomode = amd100_set_piomode,
408 .set_dmamode = amd100_set_dmamode,
409 .mode_filter = ata_pci_default_filter,
410 .tf_load = ata_tf_load,
411 .tf_read = ata_tf_read,
412 .check_status = ata_check_status,
413 .exec_command = ata_exec_command,
414 .dev_select = ata_std_dev_select,
415
416 .freeze = ata_bmdma_freeze,
417 .thaw = ata_bmdma_thaw,
418 .error_handler = amd_error_handler,
419 .post_internal_cmd = ata_bmdma_post_internal_cmd,
420
421 .bmdma_setup = ata_bmdma_setup,
422 .bmdma_start = ata_bmdma_start,
423 .bmdma_stop = ata_bmdma_stop,
424 .bmdma_status = ata_bmdma_status,
425
426 .qc_prep = ata_qc_prep,
427 .qc_issue = ata_qc_issue_prot,
428 .eng_timeout = ata_eng_timeout,
429 .data_xfer = ata_pio_data_xfer,
430
431 .irq_handler = ata_interrupt,
432 .irq_clear = ata_bmdma_irq_clear,
433
434 .port_start = ata_port_start,
435 .port_stop = ata_port_stop,
436 .host_stop = ata_host_stop
437};
438
439static struct ata_port_operations amd133_port_ops = {
440 .port_disable = ata_port_disable,
441 .set_piomode = amd133_set_piomode,
442 .set_dmamode = amd133_set_dmamode,
443 .mode_filter = ata_pci_default_filter,
444 .tf_load = ata_tf_load,
445 .tf_read = ata_tf_read,
446 .check_status = ata_check_status,
447 .exec_command = ata_exec_command,
448 .dev_select = ata_std_dev_select,
449
450 .freeze = ata_bmdma_freeze,
451 .thaw = ata_bmdma_thaw,
452 .error_handler = amd_error_handler,
453 .post_internal_cmd = ata_bmdma_post_internal_cmd,
454
455 .bmdma_setup = ata_bmdma_setup,
456 .bmdma_start = ata_bmdma_start,
457 .bmdma_stop = ata_bmdma_stop,
458 .bmdma_status = ata_bmdma_status,
459
460 .qc_prep = ata_qc_prep,
461 .qc_issue = ata_qc_issue_prot,
462 .eng_timeout = ata_eng_timeout,
463 .data_xfer = ata_pio_data_xfer,
464
465 .irq_handler = ata_interrupt,
466 .irq_clear = ata_bmdma_irq_clear,
467
468 .port_start = ata_port_start,
469 .port_stop = ata_port_stop,
470 .host_stop = ata_host_stop
471};
472
473static struct ata_port_operations nv100_port_ops = {
474 .port_disable = ata_port_disable,
475 .set_piomode = nv100_set_piomode,
476 .set_dmamode = nv100_set_dmamode,
477 .mode_filter = ata_pci_default_filter,
478 .tf_load = ata_tf_load,
479 .tf_read = ata_tf_read,
480 .check_status = ata_check_status,
481 .exec_command = ata_exec_command,
482 .dev_select = ata_std_dev_select,
483
484 .freeze = ata_bmdma_freeze,
485 .thaw = ata_bmdma_thaw,
486 .error_handler = nv_error_handler,
487 .post_internal_cmd = ata_bmdma_post_internal_cmd,
488
489 .bmdma_setup = ata_bmdma_setup,
490 .bmdma_start = ata_bmdma_start,
491 .bmdma_stop = ata_bmdma_stop,
492 .bmdma_status = ata_bmdma_status,
493
494 .qc_prep = ata_qc_prep,
495 .qc_issue = ata_qc_issue_prot,
496 .eng_timeout = ata_eng_timeout,
497 .data_xfer = ata_pio_data_xfer,
498
499 .irq_handler = ata_interrupt,
500 .irq_clear = ata_bmdma_irq_clear,
501
502 .port_start = ata_port_start,
503 .port_stop = ata_port_stop,
504 .host_stop = ata_host_stop
505};
506
507static struct ata_port_operations nv133_port_ops = {
508 .port_disable = ata_port_disable,
509 .set_piomode = nv133_set_piomode,
510 .set_dmamode = nv133_set_dmamode,
511 .mode_filter = ata_pci_default_filter,
512 .tf_load = ata_tf_load,
513 .tf_read = ata_tf_read,
514 .check_status = ata_check_status,
515 .exec_command = ata_exec_command,
516 .dev_select = ata_std_dev_select,
517
518 .freeze = ata_bmdma_freeze,
519 .thaw = ata_bmdma_thaw,
520 .error_handler = nv_error_handler,
521 .post_internal_cmd = ata_bmdma_post_internal_cmd,
522
523 .bmdma_setup = ata_bmdma_setup,
524 .bmdma_start = ata_bmdma_start,
525 .bmdma_stop = ata_bmdma_stop,
526 .bmdma_status = ata_bmdma_status,
527
528 .qc_prep = ata_qc_prep,
529 .qc_issue = ata_qc_issue_prot,
530 .eng_timeout = ata_eng_timeout,
531 .data_xfer = ata_pio_data_xfer,
532
533 .irq_handler = ata_interrupt,
534 .irq_clear = ata_bmdma_irq_clear,
535
536 .port_start = ata_port_start,
537 .port_stop = ata_port_stop,
538 .host_stop = ata_host_stop
539};
540
541static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
542{
543 static struct ata_port_info info[10] = {
544 { /* 0: AMD 7401 */
545 .sht = &amd_sht,
546 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
547 .pio_mask = 0x1f,
548 .mwdma_mask = 0x07, /* No SWDMA */
549 .udma_mask = 0x07, /* UDMA 33 */
550 .port_ops = &amd33_port_ops
551 },
552 { /* 1: Early AMD7409 - no swdma */
553 .sht = &amd_sht,
554 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
555 .pio_mask = 0x1f,
556 .mwdma_mask = 0x07,
557 .udma_mask = 0x1f, /* UDMA 66 */
558 .port_ops = &amd66_port_ops
559 },
560 { /* 2: AMD 7409, no swdma errata */
561 .sht = &amd_sht,
562 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
563 .pio_mask = 0x1f,
564 .mwdma_mask = 0x07,
565 .udma_mask = 0x1f, /* UDMA 66 */
566 .port_ops = &amd66_port_ops
567 },
568 { /* 3: AMD 7411 */
569 .sht = &amd_sht,
570 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
571 .pio_mask = 0x1f,
572 .mwdma_mask = 0x07,
573 .udma_mask = 0x3f, /* UDMA 100 */
574 .port_ops = &amd100_port_ops
575 },
576 { /* 4: AMD 7441 */
577 .sht = &amd_sht,
578 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
579 .pio_mask = 0x1f,
580 .mwdma_mask = 0x07,
581 .udma_mask = 0x3f, /* UDMA 100 */
582 .port_ops = &amd100_port_ops
583 },
584 { /* 5: AMD 8111*/
585 .sht = &amd_sht,
586 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
587 .pio_mask = 0x1f,
588 .mwdma_mask = 0x07,
589 .udma_mask = 0x7f, /* UDMA 133, no swdma */
590 .port_ops = &amd133_port_ops
591 },
592 { /* 6: AMD 8111 UDMA 100 (Serenade) */
593 .sht = &amd_sht,
594 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
595 .pio_mask = 0x1f,
596 .mwdma_mask = 0x07,
597 .udma_mask = 0x3f, /* UDMA 100, no swdma */
598 .port_ops = &amd133_port_ops
599 },
600 { /* 7: Nvidia Nforce */
601 .sht = &amd_sht,
602 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
603 .pio_mask = 0x1f,
604 .mwdma_mask = 0x07,
605 .udma_mask = 0x3f, /* UDMA 100 */
606 .port_ops = &nv100_port_ops
607 },
608 { /* 8: Nvidia Nforce2 and later */
609 .sht = &amd_sht,
610 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
611 .pio_mask = 0x1f,
612 .mwdma_mask = 0x07,
613 .udma_mask = 0x7f, /* UDMA 133, no swdma */
614 .port_ops = &nv133_port_ops
615 },
616 { /* 9: AMD CS5536 (Geode companion) */
617 .sht = &amd_sht,
618 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
619 .pio_mask = 0x1f,
620 .mwdma_mask = 0x07,
621 .udma_mask = 0x3f, /* UDMA 100 */
622 .port_ops = &amd100_port_ops
623 }
624 };
625 static struct ata_port_info *port_info[2];
626 static int printed_version;
627 int type = id->driver_data;
628 u8 rev;
629 u8 fifo;
630
631 if (!printed_version++)
632 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
633
634 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
635 pci_read_config_byte(pdev, 0x41, &fifo);
636
637 /* Check for AMD7409 without swdma errata and if found adjust type */
638 if (type == 1 && rev > 0x7)
639 type = 2;
640
641 /* Check for AMD7411 */
642 if (type == 3)
643 /* FIFO is broken */
644 pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
645 else
646 pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
647
648 /* Serenade ? */
649 if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
650 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
651 type = 6; /* UDMA 100 only */
652
653 if (type < 3)
654 ata_pci_clear_simplex(pdev);
655
656 /* And fire it up */
657
658 port_info[0] = port_info[1] = &info[type];
659 return ata_pci_init_one(pdev, port_info, 2);
660}
661
662static const struct pci_device_id amd[] = {
663 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_COBRA_7401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
664 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7409, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
665 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
666 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
667 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
668 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7 },
669 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
670 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
671 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
672 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
673 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
674 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
675 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
676 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
677 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
678 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9 },
679 { 0, },
680};
681
682static struct pci_driver amd_pci_driver = {
683 .name = DRV_NAME,
684 .id_table = amd,
685 .probe = amd_init_one,
686 .remove = ata_pci_remove_one
687};
688
689static int __init amd_init(void)
690{
691 return pci_register_driver(&amd_pci_driver);
692}
693
694static void __exit amd_exit(void)
695{
696 pci_unregister_driver(&amd_pci_driver);
697}
698
699
700MODULE_AUTHOR("Alan Cox");
701MODULE_DESCRIPTION("low-level driver for AMD PATA IDE");
702MODULE_LICENSE("GPL");
703MODULE_DEVICE_TABLE(pci, amd);
704MODULE_VERSION(DRV_VERSION);
705
706module_init(amd_init);
707module_exit(amd_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 21:30:51 -0500