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-rw-r--r--drivers/ata/pata_amd.c718
1 files changed, 718 insertions, 0 deletions
diff --git a/drivers/ata/pata_amd.c b/drivers/ata/pata_amd.c
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index 000000000000..3293cf9a7eb5
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+++ b/drivers/ata/pata_amd.c
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1/*
2 * pata_amd.c - AMD PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based on pata-sil680. Errata information is taken from data sheets
7 * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
8 * claimed by sata-nv.c.
9 *
10 * TODO:
11 * Variable system clock when/if it makes sense
12 * Power management on ports
13 *
14 *
15 * Documentation publically available.
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26
27#define DRV_NAME "pata_amd"
28#define DRV_VERSION "0.2.3"
29
30/**
31 * timing_setup - shared timing computation and load
32 * @ap: ATA port being set up
33 * @adev: drive being configured
34 * @offset: port offset
35 * @speed: target speed
36 * @clock: clock multiplier (number of times 33MHz for this part)
37 *
38 * Perform the actual timing set up for Nvidia or AMD PATA devices.
39 * The actual devices vary so they all call into this helper function
40 * providing the clock multipler and offset (because AMD and Nvidia put
41 * the ports at different locations).
42 */
43
44static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
45{
46 static const unsigned char amd_cyc2udma[] = {
47 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
48 };
49
50 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
51 struct ata_device *peer = ata_dev_pair(adev);
52 int dn = ap->port_no * 2 + adev->devno;
53 struct ata_timing at, apeer;
54 int T, UT;
55 const int amd_clock = 33333; /* KHz. */
56 u8 t;
57
58 T = 1000000000 / amd_clock;
59 UT = T / min_t(int, max_t(int, clock, 1), 2);
60
61 if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
62 dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed);
63 return;
64 }
65
66 if (peer) {
67 /* This may be over conservative */
68 if (peer->dma_mode) {
69 ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
70 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
71 }
72 ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
73 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
74 }
75
76 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
77 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
78
79 /*
80 * Now do the setup work
81 */
82
83 /* Configure the address set up timing */
84 pci_read_config_byte(pdev, offset + 0x0C, &t);
85 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
86 pci_write_config_byte(pdev, offset + 0x0C , t);
87
88 /* Configure the 8bit I/O timing */
89 pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
90 ((FIT(at.act8b, 1, 16) - 1) << 4) | (FIT(at.rec8b, 1, 16) - 1));
91
92 /* Drive timing */
93 pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
94 ((FIT(at.active, 1, 16) - 1) << 4) | (FIT(at.recover, 1, 16) - 1));
95
96 switch (clock) {
97 case 1:
98 t = at.udma ? (0xc0 | (FIT(at.udma, 2, 5) - 2)) : 0x03;
99 break;
100
101 case 2:
102 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 2, 10)]) : 0x03;
103 break;
104
105 case 3:
106 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 10)]) : 0x03;
107 break;
108
109 case 4:
110 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 15)]) : 0x03;
111 break;
112
113 default:
114 return;
115 }
116
117 /* UDMA timing */
118 pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
119}
120
121/**
122 * amd_probe_init - cable detection
123 * @ap: ATA port
124 *
125 * Perform cable detection. The BIOS stores this in PCI config
126 * space for us.
127 */
128
129static int amd_pre_reset(struct ata_port *ap)
130{
131 static const u32 bitmask[2] = {0x03, 0xC0};
132 static const struct pci_bits amd_enable_bits[] = {
133 { 0x40, 1, 0x02, 0x02 },
134 { 0x40, 1, 0x01, 0x01 }
135 };
136
137 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
138 u8 ata66;
139
140 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no])) {
141 ata_port_disable(ap);
142 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
143 return 0;
144 }
145
146 pci_read_config_byte(pdev, 0x42, &ata66);
147 if (ata66 & bitmask[ap->port_no])
148 ap->cbl = ATA_CBL_PATA80;
149 else
150 ap->cbl = ATA_CBL_PATA40;
151 return ata_std_prereset(ap);
152
153}
154
155static void amd_error_handler(struct ata_port *ap)
156{
157 return ata_bmdma_drive_eh(ap, amd_pre_reset,
158 ata_std_softreset, NULL,
159 ata_std_postreset);
160}
161
162static int amd_early_pre_reset(struct ata_port *ap)
163{
164 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
165 static struct pci_bits amd_enable_bits[] = {
166 { 0x40, 1, 0x02, 0x02 },
167 { 0x40, 1, 0x01, 0x01 }
168 };
169
170 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no])) {
171 ata_port_disable(ap);
172 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
173 return 0;
174 }
175 /* No host side cable detection */
176 ap->cbl = ATA_CBL_PATA80;
177 return ata_std_prereset(ap);
178
179}
180
181static void amd_early_error_handler(struct ata_port *ap)
182{
183 ata_bmdma_drive_eh(ap, amd_early_pre_reset,
184 ata_std_softreset, NULL,
185 ata_std_postreset);
186}
187
188/**
189 * amd33_set_piomode - set initial PIO mode data
190 * @ap: ATA interface
191 * @adev: ATA device
192 *
193 * Program the AMD registers for PIO mode.
194 */
195
196static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
197{
198 timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
199}
200
201static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
202{
203 timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
204}
205
206static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
207{
208 timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
209}
210
211static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
212{
213 timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
214}
215
216/**
217 * amd33_set_dmamode - set initial DMA mode data
218 * @ap: ATA interface
219 * @adev: ATA device
220 *
221 * Program the MWDMA/UDMA modes for the AMD and Nvidia
222 * chipset.
223 */
224
225static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
226{
227 timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
228}
229
230static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
231{
232 timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
233}
234
235static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
236{
237 timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
238}
239
240static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
241{
242 timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
243}
244
245
246/**
247 * nv_probe_init - cable detection
248 * @ap: ATA port
249 *
250 * Perform cable detection. The BIOS stores this in PCI config
251 * space for us.
252 */
253
254static int nv_pre_reset(struct ata_port *ap) {
255 static const u8 bitmask[2] = {0x03, 0xC0};
256 static const struct pci_bits nv_enable_bits[] = {
257 { 0x50, 1, 0x02, 0x02 },
258 { 0x50, 1, 0x01, 0x01 }
259 };
260
261 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
262 u8 ata66;
263 u16 udma;
264
265 if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no])) {
266 ata_port_disable(ap);
267 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
268 return 0;
269 }
270
271
272 pci_read_config_byte(pdev, 0x52, &ata66);
273 if (ata66 & bitmask[ap->port_no])
274 ap->cbl = ATA_CBL_PATA80;
275 else
276 ap->cbl = ATA_CBL_PATA40;
277
278 /* We now have to double check because the Nvidia boxes BIOS
279 doesn't always set the cable bits but does set mode bits */
280
281 pci_read_config_word(pdev, 0x62 - 2 * ap->port_no, &udma);
282 if ((udma & 0xC4) == 0xC4 || (udma & 0xC400) == 0xC400)
283 ap->cbl = ATA_CBL_PATA80;
284 return ata_std_prereset(ap);
285}
286
287static void nv_error_handler(struct ata_port *ap)
288{
289 ata_bmdma_drive_eh(ap, nv_pre_reset,
290 ata_std_softreset, NULL,
291 ata_std_postreset);
292}
293/**
294 * nv100_set_piomode - set initial PIO mode data
295 * @ap: ATA interface
296 * @adev: ATA device
297 *
298 * Program the AMD registers for PIO mode.
299 */
300
301static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
302{
303 timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
304}
305
306static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
307{
308 timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
309}
310
311/**
312 * nv100_set_dmamode - set initial DMA mode data
313 * @ap: ATA interface
314 * @adev: ATA device
315 *
316 * Program the MWDMA/UDMA modes for the AMD and Nvidia
317 * chipset.
318 */
319
320static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
321{
322 timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
323}
324
325static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
326{
327 timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
328}
329
330static struct scsi_host_template amd_sht = {
331 .module = THIS_MODULE,
332 .name = DRV_NAME,
333 .ioctl = ata_scsi_ioctl,
334 .queuecommand = ata_scsi_queuecmd,
335 .can_queue = ATA_DEF_QUEUE,
336 .this_id = ATA_SHT_THIS_ID,
337 .sg_tablesize = LIBATA_MAX_PRD,
338 .max_sectors = ATA_MAX_SECTORS,
339 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
340 .emulated = ATA_SHT_EMULATED,
341 .use_clustering = ATA_SHT_USE_CLUSTERING,
342 .proc_name = DRV_NAME,
343 .dma_boundary = ATA_DMA_BOUNDARY,
344 .slave_configure = ata_scsi_slave_config,
345 .bios_param = ata_std_bios_param,
346};
347
348static struct ata_port_operations amd33_port_ops = {
349 .port_disable = ata_port_disable,
350 .set_piomode = amd33_set_piomode,
351 .set_dmamode = amd33_set_dmamode,
352 .mode_filter = ata_pci_default_filter,
353 .tf_load = ata_tf_load,
354 .tf_read = ata_tf_read,
355 .check_status = ata_check_status,
356 .exec_command = ata_exec_command,
357 .dev_select = ata_std_dev_select,
358
359 .freeze = ata_bmdma_freeze,
360 .thaw = ata_bmdma_thaw,
361 .error_handler = amd_early_error_handler,
362 .post_internal_cmd = ata_bmdma_post_internal_cmd,
363
364 .bmdma_setup = ata_bmdma_setup,
365 .bmdma_start = ata_bmdma_start,
366 .bmdma_stop = ata_bmdma_stop,
367 .bmdma_status = ata_bmdma_status,
368
369 .qc_prep = ata_qc_prep,
370 .qc_issue = ata_qc_issue_prot,
371 .eng_timeout = ata_eng_timeout,
372 .data_xfer = ata_pio_data_xfer,
373
374 .irq_handler = ata_interrupt,
375 .irq_clear = ata_bmdma_irq_clear,
376
377 .port_start = ata_port_start,
378 .port_stop = ata_port_stop,
379 .host_stop = ata_host_stop
380};
381
382static struct ata_port_operations amd66_port_ops = {
383 .port_disable = ata_port_disable,
384 .set_piomode = amd66_set_piomode,
385 .set_dmamode = amd66_set_dmamode,
386 .mode_filter = ata_pci_default_filter,
387 .tf_load = ata_tf_load,
388 .tf_read = ata_tf_read,
389 .check_status = ata_check_status,
390 .exec_command = ata_exec_command,
391 .dev_select = ata_std_dev_select,
392
393 .freeze = ata_bmdma_freeze,
394 .thaw = ata_bmdma_thaw,
395 .error_handler = amd_early_error_handler,
396 .post_internal_cmd = ata_bmdma_post_internal_cmd,
397
398 .bmdma_setup = ata_bmdma_setup,
399 .bmdma_start = ata_bmdma_start,
400 .bmdma_stop = ata_bmdma_stop,
401 .bmdma_status = ata_bmdma_status,
402
403 .qc_prep = ata_qc_prep,
404 .qc_issue = ata_qc_issue_prot,
405 .eng_timeout = ata_eng_timeout,
406 .data_xfer = ata_pio_data_xfer,
407
408 .irq_handler = ata_interrupt,
409 .irq_clear = ata_bmdma_irq_clear,
410
411 .port_start = ata_port_start,
412 .port_stop = ata_port_stop,
413 .host_stop = ata_host_stop
414};
415
416static struct ata_port_operations amd100_port_ops = {
417 .port_disable = ata_port_disable,
418 .set_piomode = amd100_set_piomode,
419 .set_dmamode = amd100_set_dmamode,
420 .mode_filter = ata_pci_default_filter,
421 .tf_load = ata_tf_load,
422 .tf_read = ata_tf_read,
423 .check_status = ata_check_status,
424 .exec_command = ata_exec_command,
425 .dev_select = ata_std_dev_select,
426
427 .freeze = ata_bmdma_freeze,
428 .thaw = ata_bmdma_thaw,
429 .error_handler = amd_error_handler,
430 .post_internal_cmd = ata_bmdma_post_internal_cmd,
431
432 .bmdma_setup = ata_bmdma_setup,
433 .bmdma_start = ata_bmdma_start,
434 .bmdma_stop = ata_bmdma_stop,
435 .bmdma_status = ata_bmdma_status,
436
437 .qc_prep = ata_qc_prep,
438 .qc_issue = ata_qc_issue_prot,
439 .eng_timeout = ata_eng_timeout,
440 .data_xfer = ata_pio_data_xfer,
441
442 .irq_handler = ata_interrupt,
443 .irq_clear = ata_bmdma_irq_clear,
444
445 .port_start = ata_port_start,
446 .port_stop = ata_port_stop,
447 .host_stop = ata_host_stop
448};
449
450static struct ata_port_operations amd133_port_ops = {
451 .port_disable = ata_port_disable,
452 .set_piomode = amd133_set_piomode,
453 .set_dmamode = amd133_set_dmamode,
454 .mode_filter = ata_pci_default_filter,
455 .tf_load = ata_tf_load,
456 .tf_read = ata_tf_read,
457 .check_status = ata_check_status,
458 .exec_command = ata_exec_command,
459 .dev_select = ata_std_dev_select,
460
461 .freeze = ata_bmdma_freeze,
462 .thaw = ata_bmdma_thaw,
463 .error_handler = amd_error_handler,
464 .post_internal_cmd = ata_bmdma_post_internal_cmd,
465
466 .bmdma_setup = ata_bmdma_setup,
467 .bmdma_start = ata_bmdma_start,
468 .bmdma_stop = ata_bmdma_stop,
469 .bmdma_status = ata_bmdma_status,
470
471 .qc_prep = ata_qc_prep,
472 .qc_issue = ata_qc_issue_prot,
473 .eng_timeout = ata_eng_timeout,
474 .data_xfer = ata_pio_data_xfer,
475
476 .irq_handler = ata_interrupt,
477 .irq_clear = ata_bmdma_irq_clear,
478
479 .port_start = ata_port_start,
480 .port_stop = ata_port_stop,
481 .host_stop = ata_host_stop
482};
483
484static struct ata_port_operations nv100_port_ops = {
485 .port_disable = ata_port_disable,
486 .set_piomode = nv100_set_piomode,
487 .set_dmamode = nv100_set_dmamode,
488 .mode_filter = ata_pci_default_filter,
489 .tf_load = ata_tf_load,
490 .tf_read = ata_tf_read,
491 .check_status = ata_check_status,
492 .exec_command = ata_exec_command,
493 .dev_select = ata_std_dev_select,
494
495 .freeze = ata_bmdma_freeze,
496 .thaw = ata_bmdma_thaw,
497 .error_handler = nv_error_handler,
498 .post_internal_cmd = ata_bmdma_post_internal_cmd,
499
500 .bmdma_setup = ata_bmdma_setup,
501 .bmdma_start = ata_bmdma_start,
502 .bmdma_stop = ata_bmdma_stop,
503 .bmdma_status = ata_bmdma_status,
504
505 .qc_prep = ata_qc_prep,
506 .qc_issue = ata_qc_issue_prot,
507 .eng_timeout = ata_eng_timeout,
508 .data_xfer = ata_pio_data_xfer,
509
510 .irq_handler = ata_interrupt,
511 .irq_clear = ata_bmdma_irq_clear,
512
513 .port_start = ata_port_start,
514 .port_stop = ata_port_stop,
515 .host_stop = ata_host_stop
516};
517
518static struct ata_port_operations nv133_port_ops = {
519 .port_disable = ata_port_disable,
520 .set_piomode = nv133_set_piomode,
521 .set_dmamode = nv133_set_dmamode,
522 .mode_filter = ata_pci_default_filter,
523 .tf_load = ata_tf_load,
524 .tf_read = ata_tf_read,
525 .check_status = ata_check_status,
526 .exec_command = ata_exec_command,
527 .dev_select = ata_std_dev_select,
528
529 .freeze = ata_bmdma_freeze,
530 .thaw = ata_bmdma_thaw,
531 .error_handler = nv_error_handler,
532 .post_internal_cmd = ata_bmdma_post_internal_cmd,
533
534 .bmdma_setup = ata_bmdma_setup,
535 .bmdma_start = ata_bmdma_start,
536 .bmdma_stop = ata_bmdma_stop,
537 .bmdma_status = ata_bmdma_status,
538
539 .qc_prep = ata_qc_prep,
540 .qc_issue = ata_qc_issue_prot,
541 .eng_timeout = ata_eng_timeout,
542 .data_xfer = ata_pio_data_xfer,
543
544 .irq_handler = ata_interrupt,
545 .irq_clear = ata_bmdma_irq_clear,
546
547 .port_start = ata_port_start,
548 .port_stop = ata_port_stop,
549 .host_stop = ata_host_stop
550};
551
552static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
553{
554 static struct ata_port_info info[10] = {
555 { /* 0: AMD 7401 */
556 .sht = &amd_sht,
557 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
558 .pio_mask = 0x1f,
559 .mwdma_mask = 0x07, /* No SWDMA */
560 .udma_mask = 0x07, /* UDMA 33 */
561 .port_ops = &amd33_port_ops
562 },
563 { /* 1: Early AMD7409 - no swdma */
564 .sht = &amd_sht,
565 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
566 .pio_mask = 0x1f,
567 .mwdma_mask = 0x07,
568 .udma_mask = 0x1f, /* UDMA 66 */
569 .port_ops = &amd66_port_ops
570 },
571 { /* 2: AMD 7409, no swdma errata */
572 .sht = &amd_sht,
573 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
574 .pio_mask = 0x1f,
575 .mwdma_mask = 0x07,
576 .udma_mask = 0x1f, /* UDMA 66 */
577 .port_ops = &amd66_port_ops
578 },
579 { /* 3: AMD 7411 */
580 .sht = &amd_sht,
581 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
582 .pio_mask = 0x1f,
583 .mwdma_mask = 0x07,
584 .udma_mask = 0x3f, /* UDMA 100 */
585 .port_ops = &amd100_port_ops
586 },
587 { /* 4: AMD 7441 */
588 .sht = &amd_sht,
589 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
590 .pio_mask = 0x1f,
591 .mwdma_mask = 0x07,
592 .udma_mask = 0x3f, /* UDMA 100 */
593 .port_ops = &amd100_port_ops
594 },
595 { /* 5: AMD 8111*/
596 .sht = &amd_sht,
597 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
598 .pio_mask = 0x1f,
599 .mwdma_mask = 0x07,
600 .udma_mask = 0x7f, /* UDMA 133, no swdma */
601 .port_ops = &amd133_port_ops
602 },
603 { /* 6: AMD 8111 UDMA 100 (Serenade) */
604 .sht = &amd_sht,
605 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
606 .pio_mask = 0x1f,
607 .mwdma_mask = 0x07,
608 .udma_mask = 0x3f, /* UDMA 100, no swdma */
609 .port_ops = &amd133_port_ops
610 },
611 { /* 7: Nvidia Nforce */
612 .sht = &amd_sht,
613 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
614 .pio_mask = 0x1f,
615 .mwdma_mask = 0x07,
616 .udma_mask = 0x3f, /* UDMA 100 */
617 .port_ops = &nv100_port_ops
618 },
619 { /* 8: Nvidia Nforce2 and later */
620 .sht = &amd_sht,
621 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
622 .pio_mask = 0x1f,
623 .mwdma_mask = 0x07,
624 .udma_mask = 0x7f, /* UDMA 133, no swdma */
625 .port_ops = &nv133_port_ops
626 },
627 { /* 9: AMD CS5536 (Geode companion) */
628 .sht = &amd_sht,
629 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
630 .pio_mask = 0x1f,
631 .mwdma_mask = 0x07,
632 .udma_mask = 0x3f, /* UDMA 100 */
633 .port_ops = &amd100_port_ops
634 }
635 };
636 static struct ata_port_info *port_info[2];
637 static int printed_version;
638 int type = id->driver_data;
639 u8 rev;
640 u8 fifo;
641
642 if (!printed_version++)
643 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
644
645 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
646 pci_read_config_byte(pdev, 0x41, &fifo);
647
648 /* Check for AMD7409 without swdma errata and if found adjust type */
649 if (type == 1 && rev > 0x7)
650 type = 2;
651
652 /* Check for AMD7411 */
653 if (type == 3)
654 /* FIFO is broken */
655 pci_write_config_byte(pdev, 0x41, fifo & 0x0F);
656 else
657 pci_write_config_byte(pdev, 0x41, fifo | 0xF0);
658
659 /* Serenade ? */
660 if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
661 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
662 type = 6; /* UDMA 100 only */
663
664 if (type < 3)
665 ata_pci_clear_simplex(pdev);
666
667 /* And fire it up */
668
669 port_info[0] = port_info[1] = &info[type];
670 return ata_pci_init_one(pdev, port_info, 2);
671}
672
673static const struct pci_device_id amd[] = {
674 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_COBRA_7401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
675 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7409, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
676 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
677 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
678 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
679 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7 },
680 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
681 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
682 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
683 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
684 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
685 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
686 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
687 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
688 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
689 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9 },
690 { 0, },
691};
692
693static struct pci_driver amd_pci_driver = {
694 .name = DRV_NAME,
695 .id_table = amd,
696 .probe = amd_init_one,
697 .remove = ata_pci_remove_one
698};
699
700static int __init amd_init(void)
701{
702 return pci_register_driver(&amd_pci_driver);
703}
704
705static void __exit amd_exit(void)
706{
707 pci_unregister_driver(&amd_pci_driver);
708}
709
710
711MODULE_AUTHOR("Alan Cox");
712MODULE_DESCRIPTION("low-level driver for AMD PATA IDE");
713MODULE_LICENSE("GPL");
714MODULE_DEVICE_TABLE(pci, amd);
715MODULE_VERSION(DRV_VERSION);
716
717module_init(amd_init);
718module_exit(amd_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 06:48:21 -0500