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-rw-r--r--drivers/ata/libata-sff.c2296
1 files changed, 2070 insertions, 226 deletions
diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c
index 20dc572fb45a..15499522e642 100644
--- a/drivers/ata/libata-sff.c
+++ b/drivers/ata/libata-sff.c
@@ -35,11 +35,377 @@
35#include <linux/kernel.h> 35#include <linux/kernel.h>
36#include <linux/pci.h> 36#include <linux/pci.h>
37#include <linux/libata.h> 37#include <linux/libata.h>
38#include <linux/highmem.h>
38 39
39#include "libata.h" 40#include "libata.h"
40 41
42const struct ata_port_operations ata_sff_port_ops = {
43 .inherits = &ata_base_port_ops,
44
45 .qc_prep = ata_sff_qc_prep,
46 .qc_issue = ata_sff_qc_issue,
47 .qc_fill_rtf = ata_sff_qc_fill_rtf,
48
49 .freeze = ata_sff_freeze,
50 .thaw = ata_sff_thaw,
51 .prereset = ata_sff_prereset,
52 .softreset = ata_sff_softreset,
53 .hardreset = sata_sff_hardreset,
54 .postreset = ata_sff_postreset,
55 .error_handler = ata_sff_error_handler,
56 .post_internal_cmd = ata_sff_post_internal_cmd,
57
58 .sff_dev_select = ata_sff_dev_select,
59 .sff_check_status = ata_sff_check_status,
60 .sff_tf_load = ata_sff_tf_load,
61 .sff_tf_read = ata_sff_tf_read,
62 .sff_exec_command = ata_sff_exec_command,
63 .sff_data_xfer = ata_sff_data_xfer,
64 .sff_irq_on = ata_sff_irq_on,
65 .sff_irq_clear = ata_sff_irq_clear,
66
67 .port_start = ata_sff_port_start,
68};
69
70const struct ata_port_operations ata_bmdma_port_ops = {
71 .inherits = &ata_sff_port_ops,
72
73 .mode_filter = ata_bmdma_mode_filter,
74
75 .bmdma_setup = ata_bmdma_setup,
76 .bmdma_start = ata_bmdma_start,
77 .bmdma_stop = ata_bmdma_stop,
78 .bmdma_status = ata_bmdma_status,
79};
80
81/**
82 * ata_fill_sg - Fill PCI IDE PRD table
83 * @qc: Metadata associated with taskfile to be transferred
84 *
85 * Fill PCI IDE PRD (scatter-gather) table with segments
86 * associated with the current disk command.
87 *
88 * LOCKING:
89 * spin_lock_irqsave(host lock)
90 *
91 */
92static void ata_fill_sg(struct ata_queued_cmd *qc)
93{
94 struct ata_port *ap = qc->ap;
95 struct scatterlist *sg;
96 unsigned int si, pi;
97
98 pi = 0;
99 for_each_sg(qc->sg, sg, qc->n_elem, si) {
100 u32 addr, offset;
101 u32 sg_len, len;
102
103 /* determine if physical DMA addr spans 64K boundary.
104 * Note h/w doesn't support 64-bit, so we unconditionally
105 * truncate dma_addr_t to u32.
106 */
107 addr = (u32) sg_dma_address(sg);
108 sg_len = sg_dma_len(sg);
109
110 while (sg_len) {
111 offset = addr & 0xffff;
112 len = sg_len;
113 if ((offset + sg_len) > 0x10000)
114 len = 0x10000 - offset;
115
116 ap->prd[pi].addr = cpu_to_le32(addr);
117 ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff);
118 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
119
120 pi++;
121 sg_len -= len;
122 addr += len;
123 }
124 }
125
126 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
127}
128
129/**
130 * ata_fill_sg_dumb - Fill PCI IDE PRD table
131 * @qc: Metadata associated with taskfile to be transferred
132 *
133 * Fill PCI IDE PRD (scatter-gather) table with segments
134 * associated with the current disk command. Perform the fill
135 * so that we avoid writing any length 64K records for
136 * controllers that don't follow the spec.
137 *
138 * LOCKING:
139 * spin_lock_irqsave(host lock)
140 *
141 */
142static void ata_fill_sg_dumb(struct ata_queued_cmd *qc)
143{
144 struct ata_port *ap = qc->ap;
145 struct scatterlist *sg;
146 unsigned int si, pi;
147
148 pi = 0;
149 for_each_sg(qc->sg, sg, qc->n_elem, si) {
150 u32 addr, offset;
151 u32 sg_len, len, blen;
152
153 /* determine if physical DMA addr spans 64K boundary.
154 * Note h/w doesn't support 64-bit, so we unconditionally
155 * truncate dma_addr_t to u32.
156 */
157 addr = (u32) sg_dma_address(sg);
158 sg_len = sg_dma_len(sg);
159
160 while (sg_len) {
161 offset = addr & 0xffff;
162 len = sg_len;
163 if ((offset + sg_len) > 0x10000)
164 len = 0x10000 - offset;
165
166 blen = len & 0xffff;
167 ap->prd[pi].addr = cpu_to_le32(addr);
168 if (blen == 0) {
169 /* Some PATA chipsets like the CS5530 can't
170 cope with 0x0000 meaning 64K as the spec says */
171 ap->prd[pi].flags_len = cpu_to_le32(0x8000);
172 blen = 0x8000;
173 ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000);
174 }
175 ap->prd[pi].flags_len = cpu_to_le32(blen);
176 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
177
178 pi++;
179 sg_len -= len;
180 addr += len;
181 }
182 }
183
184 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
185}
186
187/**
188 * ata_sff_qc_prep - Prepare taskfile for submission
189 * @qc: Metadata associated with taskfile to be prepared
190 *
191 * Prepare ATA taskfile for submission.
192 *
193 * LOCKING:
194 * spin_lock_irqsave(host lock)
195 */
196void ata_sff_qc_prep(struct ata_queued_cmd *qc)
197{
198 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
199 return;
200
201 ata_fill_sg(qc);
202}
203
204/**
205 * ata_sff_dumb_qc_prep - Prepare taskfile for submission
206 * @qc: Metadata associated with taskfile to be prepared
207 *
208 * Prepare ATA taskfile for submission.
209 *
210 * LOCKING:
211 * spin_lock_irqsave(host lock)
212 */
213void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc)
214{
215 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
216 return;
217
218 ata_fill_sg_dumb(qc);
219}
220
221/**
222 * ata_sff_check_status - Read device status reg & clear interrupt
223 * @ap: port where the device is
224 *
225 * Reads ATA taskfile status register for currently-selected device
226 * and return its value. This also clears pending interrupts
227 * from this device
228 *
229 * LOCKING:
230 * Inherited from caller.
231 */
232u8 ata_sff_check_status(struct ata_port *ap)
233{
234 return ioread8(ap->ioaddr.status_addr);
235}
236
237/**
238 * ata_sff_altstatus - Read device alternate status reg
239 * @ap: port where the device is
240 *
241 * Reads ATA taskfile alternate status register for
242 * currently-selected device and return its value.
243 *
244 * Note: may NOT be used as the check_altstatus() entry in
245 * ata_port_operations.
246 *
247 * LOCKING:
248 * Inherited from caller.
249 */
250u8 ata_sff_altstatus(struct ata_port *ap)
251{
252 if (ap->ops->sff_check_altstatus)
253 return ap->ops->sff_check_altstatus(ap);
254
255 return ioread8(ap->ioaddr.altstatus_addr);
256}
257
258/**
259 * ata_sff_busy_sleep - sleep until BSY clears, or timeout
260 * @ap: port containing status register to be polled
261 * @tmout_pat: impatience timeout
262 * @tmout: overall timeout
263 *
264 * Sleep until ATA Status register bit BSY clears,
265 * or a timeout occurs.
266 *
267 * LOCKING:
268 * Kernel thread context (may sleep).
269 *
270 * RETURNS:
271 * 0 on success, -errno otherwise.
272 */
273int ata_sff_busy_sleep(struct ata_port *ap,
274 unsigned long tmout_pat, unsigned long tmout)
275{
276 unsigned long timer_start, timeout;
277 u8 status;
278
279 status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
280 timer_start = jiffies;
281 timeout = timer_start + tmout_pat;
282 while (status != 0xff && (status & ATA_BUSY) &&
283 time_before(jiffies, timeout)) {
284 msleep(50);
285 status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
286 }
287
288 if (status != 0xff && (status & ATA_BUSY))
289 ata_port_printk(ap, KERN_WARNING,
290 "port is slow to respond, please be patient "
291 "(Status 0x%x)\n", status);
292
293 timeout = timer_start + tmout;
294 while (status != 0xff && (status & ATA_BUSY) &&
295 time_before(jiffies, timeout)) {
296 msleep(50);
297 status = ap->ops->sff_check_status(ap);
298 }
299
300 if (status == 0xff)
301 return -ENODEV;
302
303 if (status & ATA_BUSY) {
304 ata_port_printk(ap, KERN_ERR, "port failed to respond "
305 "(%lu secs, Status 0x%x)\n",
306 tmout / HZ, status);
307 return -EBUSY;
308 }
309
310 return 0;
311}
312
313static int ata_sff_check_ready(struct ata_link *link)
314{
315 u8 status = link->ap->ops->sff_check_status(link->ap);
316
317 if (!(status & ATA_BUSY))
318 return 1;
319 if (status == 0xff)
320 return -ENODEV;
321 return 0;
322}
323
324/**
325 * ata_sff_wait_ready - sleep until BSY clears, or timeout
326 * @link: SFF link to wait ready status for
327 * @deadline: deadline jiffies for the operation
328 *
329 * Sleep until ATA Status register bit BSY clears, or timeout
330 * occurs.
331 *
332 * LOCKING:
333 * Kernel thread context (may sleep).
334 *
335 * RETURNS:
336 * 0 on success, -errno otherwise.
337 */
338int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
339{
340 return ata_wait_ready(link, deadline, ata_sff_check_ready);
341}
342
343/**
344 * ata_sff_dev_select - Select device 0/1 on ATA bus
345 * @ap: ATA channel to manipulate
346 * @device: ATA device (numbered from zero) to select
347 *
348 * Use the method defined in the ATA specification to
349 * make either device 0, or device 1, active on the
350 * ATA channel. Works with both PIO and MMIO.
351 *
352 * May be used as the dev_select() entry in ata_port_operations.
353 *
354 * LOCKING:
355 * caller.
356 */
357void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
358{
359 u8 tmp;
360
361 if (device == 0)
362 tmp = ATA_DEVICE_OBS;
363 else
364 tmp = ATA_DEVICE_OBS | ATA_DEV1;
365
366 iowrite8(tmp, ap->ioaddr.device_addr);
367 ata_sff_pause(ap); /* needed; also flushes, for mmio */
368}
369
370/**
371 * ata_dev_select - Select device 0/1 on ATA bus
372 * @ap: ATA channel to manipulate
373 * @device: ATA device (numbered from zero) to select
374 * @wait: non-zero to wait for Status register BSY bit to clear
375 * @can_sleep: non-zero if context allows sleeping
376 *
377 * Use the method defined in the ATA specification to
378 * make either device 0, or device 1, active on the
379 * ATA channel.
380 *
381 * This is a high-level version of ata_sff_dev_select(), which
382 * additionally provides the services of inserting the proper
383 * pauses and status polling, where needed.
384 *
385 * LOCKING:
386 * caller.
387 */
388void ata_dev_select(struct ata_port *ap, unsigned int device,
389 unsigned int wait, unsigned int can_sleep)
390{
391 if (ata_msg_probe(ap))
392 ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, "
393 "device %u, wait %u\n", device, wait);
394
395 if (wait)
396 ata_wait_idle(ap);
397
398 ap->ops->sff_dev_select(ap, device);
399
400 if (wait) {
401 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
402 msleep(150);
403 ata_wait_idle(ap);
404 }
405}
406
41/** 407/**
42 * ata_irq_on - Enable interrupts on a port. 408 * ata_sff_irq_on - Enable interrupts on a port.
43 * @ap: Port on which interrupts are enabled. 409 * @ap: Port on which interrupts are enabled.
44 * 410 *
45 * Enable interrupts on a legacy IDE device using MMIO or PIO, 411 * Enable interrupts on a legacy IDE device using MMIO or PIO,
@@ -48,7 +414,7 @@
48 * LOCKING: 414 * LOCKING:
49 * Inherited from caller. 415 * Inherited from caller.
50 */ 416 */
51u8 ata_irq_on(struct ata_port *ap) 417u8 ata_sff_irq_on(struct ata_port *ap)
52{ 418{
53 struct ata_ioports *ioaddr = &ap->ioaddr; 419 struct ata_ioports *ioaddr = &ap->ioaddr;
54 u8 tmp; 420 u8 tmp;
@@ -60,13 +426,34 @@ u8 ata_irq_on(struct ata_port *ap)
60 iowrite8(ap->ctl, ioaddr->ctl_addr); 426 iowrite8(ap->ctl, ioaddr->ctl_addr);
61 tmp = ata_wait_idle(ap); 427 tmp = ata_wait_idle(ap);
62 428
63 ap->ops->irq_clear(ap); 429 ap->ops->sff_irq_clear(ap);
64 430
65 return tmp; 431 return tmp;
66} 432}
67 433
68/** 434/**
69 * ata_tf_load - send taskfile registers to host controller 435 * ata_sff_irq_clear - Clear PCI IDE BMDMA interrupt.
436 * @ap: Port associated with this ATA transaction.
437 *
438 * Clear interrupt and error flags in DMA status register.
439 *
440 * May be used as the irq_clear() entry in ata_port_operations.
441 *
442 * LOCKING:
443 * spin_lock_irqsave(host lock)
444 */
445void ata_sff_irq_clear(struct ata_port *ap)
446{
447 void __iomem *mmio = ap->ioaddr.bmdma_addr;
448
449 if (!mmio)
450 return;
451
452 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
453}
454
455/**
456 * ata_sff_tf_load - send taskfile registers to host controller
70 * @ap: Port to which output is sent 457 * @ap: Port to which output is sent
71 * @tf: ATA taskfile register set 458 * @tf: ATA taskfile register set
72 * 459 *
@@ -75,8 +462,7 @@ u8 ata_irq_on(struct ata_port *ap)
75 * LOCKING: 462 * LOCKING:
76 * Inherited from caller. 463 * Inherited from caller.
77 */ 464 */
78 465void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
79void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
80{ 466{
81 struct ata_ioports *ioaddr = &ap->ioaddr; 467 struct ata_ioports *ioaddr = &ap->ioaddr;
82 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 468 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
@@ -126,26 +512,7 @@ void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
126} 512}
127 513
128/** 514/**
129 * ata_exec_command - issue ATA command to host controller 515 * ata_sff_tf_read - input device's ATA taskfile shadow registers
130 * @ap: port to which command is being issued
131 * @tf: ATA taskfile register set
132 *
133 * Issues ATA command, with proper synchronization with interrupt
134 * handler / other threads.
135 *
136 * LOCKING:
137 * spin_lock_irqsave(host lock)
138 */
139void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
140{
141 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
142
143 iowrite8(tf->command, ap->ioaddr.command_addr);
144 ata_pause(ap);
145}
146
147/**
148 * ata_tf_read - input device's ATA taskfile shadow registers
149 * @ap: Port from which input is read 516 * @ap: Port from which input is read
150 * @tf: ATA taskfile register set for storing input 517 * @tf: ATA taskfile register set for storing input
151 * 518 *
@@ -157,11 +524,11 @@ void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
157 * LOCKING: 524 * LOCKING:
158 * Inherited from caller. 525 * Inherited from caller.
159 */ 526 */
160void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 527void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
161{ 528{
162 struct ata_ioports *ioaddr = &ap->ioaddr; 529 struct ata_ioports *ioaddr = &ap->ioaddr;
163 530
164 tf->command = ata_check_status(ap); 531 tf->command = ata_sff_check_status(ap);
165 tf->feature = ioread8(ioaddr->error_addr); 532 tf->feature = ioread8(ioaddr->error_addr);
166 tf->nsect = ioread8(ioaddr->nsect_addr); 533 tf->nsect = ioread8(ioaddr->nsect_addr);
167 tf->lbal = ioread8(ioaddr->lbal_addr); 534 tf->lbal = ioread8(ioaddr->lbal_addr);
@@ -185,165 +552,1028 @@ void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
185} 552}
186 553
187/** 554/**
188 * ata_check_status - Read device status reg & clear interrupt 555 * ata_sff_exec_command - issue ATA command to host controller
189 * @ap: port where the device is 556 * @ap: port to which command is being issued
557 * @tf: ATA taskfile register set
190 * 558 *
191 * Reads ATA taskfile status register for currently-selected device 559 * Issues ATA command, with proper synchronization with interrupt
192 * and return its value. This also clears pending interrupts 560 * handler / other threads.
193 * from this device
194 * 561 *
195 * LOCKING: 562 * LOCKING:
196 * Inherited from caller. 563 * spin_lock_irqsave(host lock)
197 */ 564 */
198u8 ata_check_status(struct ata_port *ap) 565void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
199{ 566{
200 return ioread8(ap->ioaddr.status_addr); 567 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
568
569 iowrite8(tf->command, ap->ioaddr.command_addr);
570 ata_sff_pause(ap);
201} 571}
202 572
203/** 573/**
204 * ata_altstatus - Read device alternate status reg 574 * ata_tf_to_host - issue ATA taskfile to host controller
205 * @ap: port where the device is 575 * @ap: port to which command is being issued
576 * @tf: ATA taskfile register set
206 * 577 *
207 * Reads ATA taskfile alternate status register for 578 * Issues ATA taskfile register set to ATA host controller,
208 * currently-selected device and return its value. 579 * with proper synchronization with interrupt handler and
580 * other threads.
209 * 581 *
210 * Note: may NOT be used as the check_altstatus() entry in 582 * LOCKING:
211 * ata_port_operations. 583 * spin_lock_irqsave(host lock)
584 */
585static inline void ata_tf_to_host(struct ata_port *ap,
586 const struct ata_taskfile *tf)
587{
588 ap->ops->sff_tf_load(ap, tf);
589 ap->ops->sff_exec_command(ap, tf);
590}
591
592/**
593 * ata_sff_data_xfer - Transfer data by PIO
594 * @dev: device to target
595 * @buf: data buffer
596 * @buflen: buffer length
597 * @rw: read/write
598 *
599 * Transfer data from/to the device data register by PIO.
212 * 600 *
213 * LOCKING: 601 * LOCKING:
214 * Inherited from caller. 602 * Inherited from caller.
603 *
604 * RETURNS:
605 * Bytes consumed.
215 */ 606 */
216u8 ata_altstatus(struct ata_port *ap) 607unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf,
608 unsigned int buflen, int rw)
217{ 609{
218 if (ap->ops->check_altstatus) 610 struct ata_port *ap = dev->link->ap;
219 return ap->ops->check_altstatus(ap); 611 void __iomem *data_addr = ap->ioaddr.data_addr;
612 unsigned int words = buflen >> 1;
220 613
221 return ioread8(ap->ioaddr.altstatus_addr); 614 /* Transfer multiple of 2 bytes */
615 if (rw == READ)
616 ioread16_rep(data_addr, buf, words);
617 else
618 iowrite16_rep(data_addr, buf, words);
619
620 /* Transfer trailing 1 byte, if any. */
621 if (unlikely(buflen & 0x01)) {
622 __le16 align_buf[1] = { 0 };
623 unsigned char *trailing_buf = buf + buflen - 1;
624
625 if (rw == READ) {
626 align_buf[0] = cpu_to_le16(ioread16(data_addr));
627 memcpy(trailing_buf, align_buf, 1);
628 } else {
629 memcpy(align_buf, trailing_buf, 1);
630 iowrite16(le16_to_cpu(align_buf[0]), data_addr);
631 }
632 words++;
633 }
634
635 return words << 1;
222} 636}
223 637
224/** 638/**
225 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction 639 * ata_sff_data_xfer_noirq - Transfer data by PIO
226 * @qc: Info associated with this ATA transaction. 640 * @dev: device to target
641 * @buf: data buffer
642 * @buflen: buffer length
643 * @rw: read/write
644 *
645 * Transfer data from/to the device data register by PIO. Do the
646 * transfer with interrupts disabled.
227 * 647 *
228 * LOCKING: 648 * LOCKING:
229 * spin_lock_irqsave(host lock) 649 * Inherited from caller.
650 *
651 * RETURNS:
652 * Bytes consumed.
230 */ 653 */
231void ata_bmdma_setup(struct ata_queued_cmd *qc) 654unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
655 unsigned int buflen, int rw)
656{
657 unsigned long flags;
658 unsigned int consumed;
659
660 local_irq_save(flags);
661 consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
662 local_irq_restore(flags);
663
664 return consumed;
665}
666
667/**
668 * ata_pio_sector - Transfer a sector of data.
669 * @qc: Command on going
670 *
671 * Transfer qc->sect_size bytes of data from/to the ATA device.
672 *
673 * LOCKING:
674 * Inherited from caller.
675 */
676static void ata_pio_sector(struct ata_queued_cmd *qc)
232{ 677{
678 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
233 struct ata_port *ap = qc->ap; 679 struct ata_port *ap = qc->ap;
234 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 680 struct page *page;
235 u8 dmactl; 681 unsigned int offset;
682 unsigned char *buf;
236 683
237 /* load PRD table addr. */ 684 if (qc->curbytes == qc->nbytes - qc->sect_size)
238 mb(); /* make sure PRD table writes are visible to controller */ 685 ap->hsm_task_state = HSM_ST_LAST;
239 iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
240 686
241 /* specify data direction, triple-check start bit is clear */ 687 page = sg_page(qc->cursg);
242 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 688 offset = qc->cursg->offset + qc->cursg_ofs;
243 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
244 if (!rw)
245 dmactl |= ATA_DMA_WR;
246 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
247 689
248 /* issue r/w command */ 690 /* get the current page and offset */
249 ap->ops->exec_command(ap, &qc->tf); 691 page = nth_page(page, (offset >> PAGE_SHIFT));
692 offset %= PAGE_SIZE;
693
694 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
695
696 if (PageHighMem(page)) {
697 unsigned long flags;
698
699 /* FIXME: use a bounce buffer */
700 local_irq_save(flags);
701 buf = kmap_atomic(page, KM_IRQ0);
702
703 /* do the actual data transfer */
704 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
705 do_write);
706
707 kunmap_atomic(buf, KM_IRQ0);
708 local_irq_restore(flags);
709 } else {
710 buf = page_address(page);
711 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
712 do_write);
713 }
714
715 qc->curbytes += qc->sect_size;
716 qc->cursg_ofs += qc->sect_size;
717
718 if (qc->cursg_ofs == qc->cursg->length) {
719 qc->cursg = sg_next(qc->cursg);
720 qc->cursg_ofs = 0;
721 }
250} 722}
251 723
252/** 724/**
253 * ata_bmdma_start - Start a PCI IDE BMDMA transaction 725 * ata_pio_sectors - Transfer one or many sectors.
254 * @qc: Info associated with this ATA transaction. 726 * @qc: Command on going
727 *
728 * Transfer one or many sectors of data from/to the
729 * ATA device for the DRQ request.
255 * 730 *
256 * LOCKING: 731 * LOCKING:
257 * spin_lock_irqsave(host lock) 732 * Inherited from caller.
258 */ 733 */
259void ata_bmdma_start(struct ata_queued_cmd *qc) 734static void ata_pio_sectors(struct ata_queued_cmd *qc)
735{
736 if (is_multi_taskfile(&qc->tf)) {
737 /* READ/WRITE MULTIPLE */
738 unsigned int nsect;
739
740 WARN_ON(qc->dev->multi_count == 0);
741
742 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
743 qc->dev->multi_count);
744 while (nsect--)
745 ata_pio_sector(qc);
746 } else
747 ata_pio_sector(qc);
748
749 ata_sff_altstatus(qc->ap); /* flush */
750}
751
752/**
753 * atapi_send_cdb - Write CDB bytes to hardware
754 * @ap: Port to which ATAPI device is attached.
755 * @qc: Taskfile currently active
756 *
757 * When device has indicated its readiness to accept
758 * a CDB, this function is called. Send the CDB.
759 *
760 * LOCKING:
761 * caller.
762 */
763static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
764{
765 /* send SCSI cdb */
766 DPRINTK("send cdb\n");
767 WARN_ON(qc->dev->cdb_len < 12);
768
769 ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
770 ata_sff_altstatus(ap); /* flush */
771
772 switch (qc->tf.protocol) {
773 case ATAPI_PROT_PIO:
774 ap->hsm_task_state = HSM_ST;
775 break;
776 case ATAPI_PROT_NODATA:
777 ap->hsm_task_state = HSM_ST_LAST;
778 break;
779 case ATAPI_PROT_DMA:
780 ap->hsm_task_state = HSM_ST_LAST;
781 /* initiate bmdma */
782 ap->ops->bmdma_start(qc);
783 break;
784 }
785}
786
787/**
788 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
789 * @qc: Command on going
790 * @bytes: number of bytes
791 *
792 * Transfer Transfer data from/to the ATAPI device.
793 *
794 * LOCKING:
795 * Inherited from caller.
796 *
797 */
798static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
260{ 799{
800 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
261 struct ata_port *ap = qc->ap; 801 struct ata_port *ap = qc->ap;
262 u8 dmactl; 802 struct ata_device *dev = qc->dev;
803 struct ata_eh_info *ehi = &dev->link->eh_info;
804 struct scatterlist *sg;
805 struct page *page;
806 unsigned char *buf;
807 unsigned int offset, count, consumed;
808
809next_sg:
810 sg = qc->cursg;
811 if (unlikely(!sg)) {
812 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
813 "buf=%u cur=%u bytes=%u",
814 qc->nbytes, qc->curbytes, bytes);
815 return -1;
816 }
263 817
264 /* start host DMA transaction */ 818 page = sg_page(sg);
265 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 819 offset = sg->offset + qc->cursg_ofs;
266 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
267 820
268 /* Strictly, one may wish to issue an ioread8() here, to 821 /* get the current page and offset */
269 * flush the mmio write. However, control also passes 822 page = nth_page(page, (offset >> PAGE_SHIFT));
270 * to the hardware at this point, and it will interrupt 823 offset %= PAGE_SIZE;
271 * us when we are to resume control. So, in effect, 824
272 * we don't care when the mmio write flushes. 825 /* don't overrun current sg */
273 * Further, a read of the DMA status register _immediately_ 826 count = min(sg->length - qc->cursg_ofs, bytes);
274 * following the write may not be what certain flaky hardware 827
275 * is expected, so I think it is best to not add a readb() 828 /* don't cross page boundaries */
276 * without first all the MMIO ATA cards/mobos. 829 count = min(count, (unsigned int)PAGE_SIZE - offset);
277 * Or maybe I'm just being paranoid. 830
278 * 831 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
279 * FIXME: The posting of this write means I/O starts are 832
280 * unneccessarily delayed for MMIO 833 if (PageHighMem(page)) {
834 unsigned long flags;
835
836 /* FIXME: use bounce buffer */
837 local_irq_save(flags);
838 buf = kmap_atomic(page, KM_IRQ0);
839
840 /* do the actual data transfer */
841 consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw);
842
843 kunmap_atomic(buf, KM_IRQ0);
844 local_irq_restore(flags);
845 } else {
846 buf = page_address(page);
847 consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw);
848 }
849
850 bytes -= min(bytes, consumed);
851 qc->curbytes += count;
852 qc->cursg_ofs += count;
853
854 if (qc->cursg_ofs == sg->length) {
855 qc->cursg = sg_next(qc->cursg);
856 qc->cursg_ofs = 0;
857 }
858
859 /* consumed can be larger than count only for the last transfer */
860 WARN_ON(qc->cursg && count != consumed);
861
862 if (bytes)
863 goto next_sg;
864 return 0;
865}
866
867/**
868 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
869 * @qc: Command on going
870 *
871 * Transfer Transfer data from/to the ATAPI device.
872 *
873 * LOCKING:
874 * Inherited from caller.
875 */
876static void atapi_pio_bytes(struct ata_queued_cmd *qc)
877{
878 struct ata_port *ap = qc->ap;
879 struct ata_device *dev = qc->dev;
880 struct ata_eh_info *ehi = &dev->link->eh_info;
881 unsigned int ireason, bc_lo, bc_hi, bytes;
882 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
883
884 /* Abuse qc->result_tf for temp storage of intermediate TF
885 * here to save some kernel stack usage.
886 * For normal completion, qc->result_tf is not relevant. For
887 * error, qc->result_tf is later overwritten by ata_qc_complete().
888 * So, the correctness of qc->result_tf is not affected.
281 */ 889 */
890 ap->ops->sff_tf_read(ap, &qc->result_tf);
891 ireason = qc->result_tf.nsect;
892 bc_lo = qc->result_tf.lbam;
893 bc_hi = qc->result_tf.lbah;
894 bytes = (bc_hi << 8) | bc_lo;
895
896 /* shall be cleared to zero, indicating xfer of data */
897 if (unlikely(ireason & (1 << 0)))
898 goto atapi_check;
899
900 /* make sure transfer direction matches expected */
901 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
902 if (unlikely(do_write != i_write))
903 goto atapi_check;
904
905 if (unlikely(!bytes))
906 goto atapi_check;
907
908 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
909
910 if (unlikely(__atapi_pio_bytes(qc, bytes)))
911 goto err_out;
912 ata_sff_altstatus(ap); /* flush */
913
914 return;
915
916 atapi_check:
917 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
918 ireason, bytes);
919 err_out:
920 qc->err_mask |= AC_ERR_HSM;
921 ap->hsm_task_state = HSM_ST_ERR;
282} 922}
283 923
284/** 924/**
285 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt. 925 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
286 * @ap: Port associated with this ATA transaction. 926 * @ap: the target ata_port
927 * @qc: qc on going
287 * 928 *
288 * Clear interrupt and error flags in DMA status register. 929 * RETURNS:
930 * 1 if ok in workqueue, 0 otherwise.
931 */
932static inline int ata_hsm_ok_in_wq(struct ata_port *ap, struct ata_queued_cmd *qc)
933{
934 if (qc->tf.flags & ATA_TFLAG_POLLING)
935 return 1;
936
937 if (ap->hsm_task_state == HSM_ST_FIRST) {
938 if (qc->tf.protocol == ATA_PROT_PIO &&
939 (qc->tf.flags & ATA_TFLAG_WRITE))
940 return 1;
941
942 if (ata_is_atapi(qc->tf.protocol) &&
943 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
944 return 1;
945 }
946
947 return 0;
948}
949
950/**
951 * ata_hsm_qc_complete - finish a qc running on standard HSM
952 * @qc: Command to complete
953 * @in_wq: 1 if called from workqueue, 0 otherwise
289 * 954 *
290 * May be used as the irq_clear() entry in ata_port_operations. 955 * Finish @qc which is running on standard HSM.
291 * 956 *
292 * LOCKING: 957 * LOCKING:
293 * spin_lock_irqsave(host lock) 958 * If @in_wq is zero, spin_lock_irqsave(host lock).
959 * Otherwise, none on entry and grabs host lock.
294 */ 960 */
295void ata_bmdma_irq_clear(struct ata_port *ap) 961static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
296{ 962{
297 void __iomem *mmio = ap->ioaddr.bmdma_addr; 963 struct ata_port *ap = qc->ap;
964 unsigned long flags;
298 965
299 if (!mmio) 966 if (ap->ops->error_handler) {
300 return; 967 if (in_wq) {
968 spin_lock_irqsave(ap->lock, flags);
969
970 /* EH might have kicked in while host lock is
971 * released.
972 */
973 qc = ata_qc_from_tag(ap, qc->tag);
974 if (qc) {
975 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
976 ap->ops->sff_irq_on(ap);
977 ata_qc_complete(qc);
978 } else
979 ata_port_freeze(ap);
980 }
981
982 spin_unlock_irqrestore(ap->lock, flags);
983 } else {
984 if (likely(!(qc->err_mask & AC_ERR_HSM)))
985 ata_qc_complete(qc);
986 else
987 ata_port_freeze(ap);
988 }
989 } else {
990 if (in_wq) {
991 spin_lock_irqsave(ap->lock, flags);
992 ap->ops->sff_irq_on(ap);
993 ata_qc_complete(qc);
994 spin_unlock_irqrestore(ap->lock, flags);
995 } else
996 ata_qc_complete(qc);
997 }
998}
301 999
302 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); 1000/**
1001 * ata_sff_hsm_move - move the HSM to the next state.
1002 * @ap: the target ata_port
1003 * @qc: qc on going
1004 * @status: current device status
1005 * @in_wq: 1 if called from workqueue, 0 otherwise
1006 *
1007 * RETURNS:
1008 * 1 when poll next status needed, 0 otherwise.
1009 */
1010int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1011 u8 status, int in_wq)
1012{
1013 unsigned long flags = 0;
1014 int poll_next;
1015
1016 WARN_ON((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
1017
1018 /* Make sure ata_sff_qc_issue() does not throw things
1019 * like DMA polling into the workqueue. Notice that
1020 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1021 */
1022 WARN_ON(in_wq != ata_hsm_ok_in_wq(ap, qc));
1023
1024fsm_start:
1025 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1026 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1027
1028 switch (ap->hsm_task_state) {
1029 case HSM_ST_FIRST:
1030 /* Send first data block or PACKET CDB */
1031
1032 /* If polling, we will stay in the work queue after
1033 * sending the data. Otherwise, interrupt handler
1034 * takes over after sending the data.
1035 */
1036 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1037
1038 /* check device status */
1039 if (unlikely((status & ATA_DRQ) == 0)) {
1040 /* handle BSY=0, DRQ=0 as error */
1041 if (likely(status & (ATA_ERR | ATA_DF)))
1042 /* device stops HSM for abort/error */
1043 qc->err_mask |= AC_ERR_DEV;
1044 else
1045 /* HSM violation. Let EH handle this */
1046 qc->err_mask |= AC_ERR_HSM;
1047
1048 ap->hsm_task_state = HSM_ST_ERR;
1049 goto fsm_start;
1050 }
1051
1052 /* Device should not ask for data transfer (DRQ=1)
1053 * when it finds something wrong.
1054 * We ignore DRQ here and stop the HSM by
1055 * changing hsm_task_state to HSM_ST_ERR and
1056 * let the EH abort the command or reset the device.
1057 */
1058 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1059 /* Some ATAPI tape drives forget to clear the ERR bit
1060 * when doing the next command (mostly request sense).
1061 * We ignore ERR here to workaround and proceed sending
1062 * the CDB.
1063 */
1064 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1065 ata_port_printk(ap, KERN_WARNING,
1066 "DRQ=1 with device error, "
1067 "dev_stat 0x%X\n", status);
1068 qc->err_mask |= AC_ERR_HSM;
1069 ap->hsm_task_state = HSM_ST_ERR;
1070 goto fsm_start;
1071 }
1072 }
1073
1074 /* Send the CDB (atapi) or the first data block (ata pio out).
1075 * During the state transition, interrupt handler shouldn't
1076 * be invoked before the data transfer is complete and
1077 * hsm_task_state is changed. Hence, the following locking.
1078 */
1079 if (in_wq)
1080 spin_lock_irqsave(ap->lock, flags);
1081
1082 if (qc->tf.protocol == ATA_PROT_PIO) {
1083 /* PIO data out protocol.
1084 * send first data block.
1085 */
1086
1087 /* ata_pio_sectors() might change the state
1088 * to HSM_ST_LAST. so, the state is changed here
1089 * before ata_pio_sectors().
1090 */
1091 ap->hsm_task_state = HSM_ST;
1092 ata_pio_sectors(qc);
1093 } else
1094 /* send CDB */
1095 atapi_send_cdb(ap, qc);
1096
1097 if (in_wq)
1098 spin_unlock_irqrestore(ap->lock, flags);
1099
1100 /* if polling, ata_pio_task() handles the rest.
1101 * otherwise, interrupt handler takes over from here.
1102 */
1103 break;
1104
1105 case HSM_ST:
1106 /* complete command or read/write the data register */
1107 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1108 /* ATAPI PIO protocol */
1109 if ((status & ATA_DRQ) == 0) {
1110 /* No more data to transfer or device error.
1111 * Device error will be tagged in HSM_ST_LAST.
1112 */
1113 ap->hsm_task_state = HSM_ST_LAST;
1114 goto fsm_start;
1115 }
1116
1117 /* Device should not ask for data transfer (DRQ=1)
1118 * when it finds something wrong.
1119 * We ignore DRQ here and stop the HSM by
1120 * changing hsm_task_state to HSM_ST_ERR and
1121 * let the EH abort the command or reset the device.
1122 */
1123 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1124 ata_port_printk(ap, KERN_WARNING, "DRQ=1 with "
1125 "device error, dev_stat 0x%X\n",
1126 status);
1127 qc->err_mask |= AC_ERR_HSM;
1128 ap->hsm_task_state = HSM_ST_ERR;
1129 goto fsm_start;
1130 }
1131
1132 atapi_pio_bytes(qc);
1133
1134 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1135 /* bad ireason reported by device */
1136 goto fsm_start;
1137
1138 } else {
1139 /* ATA PIO protocol */
1140 if (unlikely((status & ATA_DRQ) == 0)) {
1141 /* handle BSY=0, DRQ=0 as error */
1142 if (likely(status & (ATA_ERR | ATA_DF)))
1143 /* device stops HSM for abort/error */
1144 qc->err_mask |= AC_ERR_DEV;
1145 else
1146 /* HSM violation. Let EH handle this.
1147 * Phantom devices also trigger this
1148 * condition. Mark hint.
1149 */
1150 qc->err_mask |= AC_ERR_HSM |
1151 AC_ERR_NODEV_HINT;
1152
1153 ap->hsm_task_state = HSM_ST_ERR;
1154 goto fsm_start;
1155 }
1156
1157 /* For PIO reads, some devices may ask for
1158 * data transfer (DRQ=1) alone with ERR=1.
1159 * We respect DRQ here and transfer one
1160 * block of junk data before changing the
1161 * hsm_task_state to HSM_ST_ERR.
1162 *
1163 * For PIO writes, ERR=1 DRQ=1 doesn't make
1164 * sense since the data block has been
1165 * transferred to the device.
1166 */
1167 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1168 /* data might be corrputed */
1169 qc->err_mask |= AC_ERR_DEV;
1170
1171 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1172 ata_pio_sectors(qc);
1173 status = ata_wait_idle(ap);
1174 }
1175
1176 if (status & (ATA_BUSY | ATA_DRQ))
1177 qc->err_mask |= AC_ERR_HSM;
1178
1179 /* ata_pio_sectors() might change the
1180 * state to HSM_ST_LAST. so, the state
1181 * is changed after ata_pio_sectors().
1182 */
1183 ap->hsm_task_state = HSM_ST_ERR;
1184 goto fsm_start;
1185 }
1186
1187 ata_pio_sectors(qc);
1188
1189 if (ap->hsm_task_state == HSM_ST_LAST &&
1190 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1191 /* all data read */
1192 status = ata_wait_idle(ap);
1193 goto fsm_start;
1194 }
1195 }
1196
1197 poll_next = 1;
1198 break;
1199
1200 case HSM_ST_LAST:
1201 if (unlikely(!ata_ok(status))) {
1202 qc->err_mask |= __ac_err_mask(status);
1203 ap->hsm_task_state = HSM_ST_ERR;
1204 goto fsm_start;
1205 }
1206
1207 /* no more data to transfer */
1208 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1209 ap->print_id, qc->dev->devno, status);
1210
1211 WARN_ON(qc->err_mask);
1212
1213 ap->hsm_task_state = HSM_ST_IDLE;
1214
1215 /* complete taskfile transaction */
1216 ata_hsm_qc_complete(qc, in_wq);
1217
1218 poll_next = 0;
1219 break;
1220
1221 case HSM_ST_ERR:
1222 /* make sure qc->err_mask is available to
1223 * know what's wrong and recover
1224 */
1225 WARN_ON(qc->err_mask == 0);
1226
1227 ap->hsm_task_state = HSM_ST_IDLE;
1228
1229 /* complete taskfile transaction */
1230 ata_hsm_qc_complete(qc, in_wq);
1231
1232 poll_next = 0;
1233 break;
1234 default:
1235 poll_next = 0;
1236 BUG();
1237 }
1238
1239 return poll_next;
1240}
1241
1242void ata_pio_task(struct work_struct *work)
1243{
1244 struct ata_port *ap =
1245 container_of(work, struct ata_port, port_task.work);
1246 struct ata_queued_cmd *qc = ap->port_task_data;
1247 u8 status;
1248 int poll_next;
1249
1250fsm_start:
1251 WARN_ON(ap->hsm_task_state == HSM_ST_IDLE);
1252
1253 /*
1254 * This is purely heuristic. This is a fast path.
1255 * Sometimes when we enter, BSY will be cleared in
1256 * a chk-status or two. If not, the drive is probably seeking
1257 * or something. Snooze for a couple msecs, then
1258 * chk-status again. If still busy, queue delayed work.
1259 */
1260 status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
1261 if (status & ATA_BUSY) {
1262 msleep(2);
1263 status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
1264 if (status & ATA_BUSY) {
1265 ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
1266 return;
1267 }
1268 }
1269
1270 /* move the HSM */
1271 poll_next = ata_sff_hsm_move(ap, qc, status, 1);
1272
1273 /* another command or interrupt handler
1274 * may be running at this point.
1275 */
1276 if (poll_next)
1277 goto fsm_start;
303} 1278}
304 1279
305/** 1280/**
306 * ata_bmdma_status - Read PCI IDE BMDMA status 1281 * ata_sff_qc_issue - issue taskfile to device in proto-dependent manner
307 * @ap: Port associated with this ATA transaction. 1282 * @qc: command to issue to device
308 * 1283 *
309 * Read and return BMDMA status register. 1284 * Using various libata functions and hooks, this function
1285 * starts an ATA command. ATA commands are grouped into
1286 * classes called "protocols", and issuing each type of protocol
1287 * is slightly different.
310 * 1288 *
311 * May be used as the bmdma_status() entry in ata_port_operations. 1289 * May be used as the qc_issue() entry in ata_port_operations.
312 * 1290 *
313 * LOCKING: 1291 * LOCKING:
314 * spin_lock_irqsave(host lock) 1292 * spin_lock_irqsave(host lock)
1293 *
1294 * RETURNS:
1295 * Zero on success, AC_ERR_* mask on failure
315 */ 1296 */
316u8 ata_bmdma_status(struct ata_port *ap) 1297unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
317{ 1298{
318 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); 1299 struct ata_port *ap = qc->ap;
1300
1301 /* Use polling pio if the LLD doesn't handle
1302 * interrupt driven pio and atapi CDB interrupt.
1303 */
1304 if (ap->flags & ATA_FLAG_PIO_POLLING) {
1305 switch (qc->tf.protocol) {
1306 case ATA_PROT_PIO:
1307 case ATA_PROT_NODATA:
1308 case ATAPI_PROT_PIO:
1309 case ATAPI_PROT_NODATA:
1310 qc->tf.flags |= ATA_TFLAG_POLLING;
1311 break;
1312 case ATAPI_PROT_DMA:
1313 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1314 /* see ata_dma_blacklisted() */
1315 BUG();
1316 break;
1317 default:
1318 break;
1319 }
1320 }
1321
1322 /* select the device */
1323 ata_dev_select(ap, qc->dev->devno, 1, 0);
1324
1325 /* start the command */
1326 switch (qc->tf.protocol) {
1327 case ATA_PROT_NODATA:
1328 if (qc->tf.flags & ATA_TFLAG_POLLING)
1329 ata_qc_set_polling(qc);
1330
1331 ata_tf_to_host(ap, &qc->tf);
1332 ap->hsm_task_state = HSM_ST_LAST;
1333
1334 if (qc->tf.flags & ATA_TFLAG_POLLING)
1335 ata_pio_queue_task(ap, qc, 0);
1336
1337 break;
1338
1339 case ATA_PROT_DMA:
1340 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
1341
1342 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
1343 ap->ops->bmdma_setup(qc); /* set up bmdma */
1344 ap->ops->bmdma_start(qc); /* initiate bmdma */
1345 ap->hsm_task_state = HSM_ST_LAST;
1346 break;
1347
1348 case ATA_PROT_PIO:
1349 if (qc->tf.flags & ATA_TFLAG_POLLING)
1350 ata_qc_set_polling(qc);
1351
1352 ata_tf_to_host(ap, &qc->tf);
1353
1354 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1355 /* PIO data out protocol */
1356 ap->hsm_task_state = HSM_ST_FIRST;
1357 ata_pio_queue_task(ap, qc, 0);
1358
1359 /* always send first data block using
1360 * the ata_pio_task() codepath.
1361 */
1362 } else {
1363 /* PIO data in protocol */
1364 ap->hsm_task_state = HSM_ST;
1365
1366 if (qc->tf.flags & ATA_TFLAG_POLLING)
1367 ata_pio_queue_task(ap, qc, 0);
1368
1369 /* if polling, ata_pio_task() handles the rest.
1370 * otherwise, interrupt handler takes over from here.
1371 */
1372 }
1373
1374 break;
1375
1376 case ATAPI_PROT_PIO:
1377 case ATAPI_PROT_NODATA:
1378 if (qc->tf.flags & ATA_TFLAG_POLLING)
1379 ata_qc_set_polling(qc);
1380
1381 ata_tf_to_host(ap, &qc->tf);
1382
1383 ap->hsm_task_state = HSM_ST_FIRST;
1384
1385 /* send cdb by polling if no cdb interrupt */
1386 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1387 (qc->tf.flags & ATA_TFLAG_POLLING))
1388 ata_pio_queue_task(ap, qc, 0);
1389 break;
1390
1391 case ATAPI_PROT_DMA:
1392 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
1393
1394 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
1395 ap->ops->bmdma_setup(qc); /* set up bmdma */
1396 ap->hsm_task_state = HSM_ST_FIRST;
1397
1398 /* send cdb by polling if no cdb interrupt */
1399 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1400 ata_pio_queue_task(ap, qc, 0);
1401 break;
1402
1403 default:
1404 WARN_ON(1);
1405 return AC_ERR_SYSTEM;
1406 }
1407
1408 return 0;
319} 1409}
320 1410
321/** 1411/**
322 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer 1412 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
323 * @qc: Command we are ending DMA for 1413 * @qc: qc to fill result TF for
324 * 1414 *
325 * Clears the ATA_DMA_START flag in the dma control register 1415 * @qc is finished and result TF needs to be filled. Fill it
1416 * using ->sff_tf_read.
326 * 1417 *
327 * May be used as the bmdma_stop() entry in ata_port_operations. 1418 * LOCKING:
1419 * spin_lock_irqsave(host lock)
1420 *
1421 * RETURNS:
1422 * true indicating that result TF is successfully filled.
1423 */
1424bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
1425{
1426 qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
1427 return true;
1428}
1429
1430/**
1431 * ata_sff_host_intr - Handle host interrupt for given (port, task)
1432 * @ap: Port on which interrupt arrived (possibly...)
1433 * @qc: Taskfile currently active in engine
1434 *
1435 * Handle host interrupt for given queued command. Currently,
1436 * only DMA interrupts are handled. All other commands are
1437 * handled via polling with interrupts disabled (nIEN bit).
328 * 1438 *
329 * LOCKING: 1439 * LOCKING:
330 * spin_lock_irqsave(host lock) 1440 * spin_lock_irqsave(host lock)
1441 *
1442 * RETURNS:
1443 * One if interrupt was handled, zero if not (shared irq).
331 */ 1444 */
332void ata_bmdma_stop(struct ata_queued_cmd *qc) 1445inline unsigned int ata_sff_host_intr(struct ata_port *ap,
1446 struct ata_queued_cmd *qc)
333{ 1447{
334 struct ata_port *ap = qc->ap; 1448 struct ata_eh_info *ehi = &ap->link.eh_info;
335 void __iomem *mmio = ap->ioaddr.bmdma_addr; 1449 u8 status, host_stat = 0;
336 1450
337 /* clear start/stop bit */ 1451 VPRINTK("ata%u: protocol %d task_state %d\n",
338 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, 1452 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
339 mmio + ATA_DMA_CMD);
340 1453
341 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 1454 /* Check whether we are expecting interrupt in this state */
342 ata_altstatus(ap); /* dummy read */ 1455 switch (ap->hsm_task_state) {
1456 case HSM_ST_FIRST:
1457 /* Some pre-ATAPI-4 devices assert INTRQ
1458 * at this state when ready to receive CDB.
1459 */
1460
1461 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1462 * The flag was turned on only for atapi devices. No
1463 * need to check ata_is_atapi(qc->tf.protocol) again.
1464 */
1465 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1466 goto idle_irq;
1467 break;
1468 case HSM_ST_LAST:
1469 if (qc->tf.protocol == ATA_PROT_DMA ||
1470 qc->tf.protocol == ATAPI_PROT_DMA) {
1471 /* check status of DMA engine */
1472 host_stat = ap->ops->bmdma_status(ap);
1473 VPRINTK("ata%u: host_stat 0x%X\n",
1474 ap->print_id, host_stat);
1475
1476 /* if it's not our irq... */
1477 if (!(host_stat & ATA_DMA_INTR))
1478 goto idle_irq;
1479
1480 /* before we do anything else, clear DMA-Start bit */
1481 ap->ops->bmdma_stop(qc);
1482
1483 if (unlikely(host_stat & ATA_DMA_ERR)) {
1484 /* error when transfering data to/from memory */
1485 qc->err_mask |= AC_ERR_HOST_BUS;
1486 ap->hsm_task_state = HSM_ST_ERR;
1487 }
1488 }
1489 break;
1490 case HSM_ST:
1491 break;
1492 default:
1493 goto idle_irq;
1494 }
1495
1496 /* check altstatus */
1497 status = ata_sff_altstatus(ap);
1498 if (status & ATA_BUSY)
1499 goto idle_irq;
1500
1501 /* check main status, clearing INTRQ */
1502 status = ap->ops->sff_check_status(ap);
1503 if (unlikely(status & ATA_BUSY))
1504 goto idle_irq;
1505
1506 /* ack bmdma irq events */
1507 ap->ops->sff_irq_clear(ap);
1508
1509 ata_sff_hsm_move(ap, qc, status, 0);
1510
1511 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
1512 qc->tf.protocol == ATAPI_PROT_DMA))
1513 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
1514
1515 return 1; /* irq handled */
1516
1517idle_irq:
1518 ap->stats.idle_irq++;
1519
1520#ifdef ATA_IRQ_TRAP
1521 if ((ap->stats.idle_irq % 1000) == 0) {
1522 ap->ops->sff_check_status(ap);
1523 ap->ops->sff_irq_clear(ap);
1524 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
1525 return 1;
1526 }
1527#endif
1528 return 0; /* irq not handled */
1529}
1530
1531/**
1532 * ata_sff_interrupt - Default ATA host interrupt handler
1533 * @irq: irq line (unused)
1534 * @dev_instance: pointer to our ata_host information structure
1535 *
1536 * Default interrupt handler for PCI IDE devices. Calls
1537 * ata_sff_host_intr() for each port that is not disabled.
1538 *
1539 * LOCKING:
1540 * Obtains host lock during operation.
1541 *
1542 * RETURNS:
1543 * IRQ_NONE or IRQ_HANDLED.
1544 */
1545irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
1546{
1547 struct ata_host *host = dev_instance;
1548 unsigned int i;
1549 unsigned int handled = 0;
1550 unsigned long flags;
1551
1552 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1553 spin_lock_irqsave(&host->lock, flags);
1554
1555 for (i = 0; i < host->n_ports; i++) {
1556 struct ata_port *ap;
1557
1558 ap = host->ports[i];
1559 if (ap &&
1560 !(ap->flags & ATA_FLAG_DISABLED)) {
1561 struct ata_queued_cmd *qc;
1562
1563 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1564 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
1565 (qc->flags & ATA_QCFLAG_ACTIVE))
1566 handled |= ata_sff_host_intr(ap, qc);
1567 }
1568 }
1569
1570 spin_unlock_irqrestore(&host->lock, flags);
1571
1572 return IRQ_RETVAL(handled);
343} 1573}
344 1574
345/** 1575/**
346 * ata_bmdma_freeze - Freeze BMDMA controller port 1576 * ata_sff_freeze - Freeze SFF controller port
347 * @ap: port to freeze 1577 * @ap: port to freeze
348 * 1578 *
349 * Freeze BMDMA controller port. 1579 * Freeze BMDMA controller port.
@@ -351,7 +1581,7 @@ void ata_bmdma_stop(struct ata_queued_cmd *qc)
351 * LOCKING: 1581 * LOCKING:
352 * Inherited from caller. 1582 * Inherited from caller.
353 */ 1583 */
354void ata_bmdma_freeze(struct ata_port *ap) 1584void ata_sff_freeze(struct ata_port *ap)
355{ 1585{
356 struct ata_ioports *ioaddr = &ap->ioaddr; 1586 struct ata_ioports *ioaddr = &ap->ioaddr;
357 1587
@@ -365,51 +1595,412 @@ void ata_bmdma_freeze(struct ata_port *ap)
365 * ATA_NIEN manipulation. Also, many controllers fail to mask 1595 * ATA_NIEN manipulation. Also, many controllers fail to mask
366 * previously pending IRQ on ATA_NIEN assertion. Clear it. 1596 * previously pending IRQ on ATA_NIEN assertion. Clear it.
367 */ 1597 */
368 ata_chk_status(ap); 1598 ap->ops->sff_check_status(ap);
369 1599
370 ap->ops->irq_clear(ap); 1600 ap->ops->sff_irq_clear(ap);
371} 1601}
372 1602
373/** 1603/**
374 * ata_bmdma_thaw - Thaw BMDMA controller port 1604 * ata_sff_thaw - Thaw SFF controller port
375 * @ap: port to thaw 1605 * @ap: port to thaw
376 * 1606 *
377 * Thaw BMDMA controller port. 1607 * Thaw SFF controller port.
378 * 1608 *
379 * LOCKING: 1609 * LOCKING:
380 * Inherited from caller. 1610 * Inherited from caller.
381 */ 1611 */
382void ata_bmdma_thaw(struct ata_port *ap) 1612void ata_sff_thaw(struct ata_port *ap)
383{ 1613{
384 /* clear & re-enable interrupts */ 1614 /* clear & re-enable interrupts */
385 ata_chk_status(ap); 1615 ap->ops->sff_check_status(ap);
386 ap->ops->irq_clear(ap); 1616 ap->ops->sff_irq_clear(ap);
387 ap->ops->irq_on(ap); 1617 ap->ops->sff_irq_on(ap);
1618}
1619
1620/**
1621 * ata_sff_prereset - prepare SFF link for reset
1622 * @link: SFF link to be reset
1623 * @deadline: deadline jiffies for the operation
1624 *
1625 * SFF link @link is about to be reset. Initialize it. It first
1626 * calls ata_std_prereset() and wait for !BSY if the port is
1627 * being softreset.
1628 *
1629 * LOCKING:
1630 * Kernel thread context (may sleep)
1631 *
1632 * RETURNS:
1633 * 0 on success, -errno otherwise.
1634 */
1635int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
1636{
1637 struct ata_eh_context *ehc = &link->eh_context;
1638 int rc;
1639
1640 rc = ata_std_prereset(link, deadline);
1641 if (rc)
1642 return rc;
1643
1644 /* if we're about to do hardreset, nothing more to do */
1645 if (ehc->i.action & ATA_EH_HARDRESET)
1646 return 0;
1647
1648 /* wait for !BSY if we don't know that no device is attached */
1649 if (!ata_link_offline(link)) {
1650 rc = ata_sff_wait_ready(link, deadline);
1651 if (rc && rc != -ENODEV) {
1652 ata_link_printk(link, KERN_WARNING, "device not ready "
1653 "(errno=%d), forcing hardreset\n", rc);
1654 ehc->i.action |= ATA_EH_HARDRESET;
1655 }
1656 }
1657
1658 return 0;
1659}
1660
1661/**
1662 * ata_devchk - PATA device presence detection
1663 * @ap: ATA channel to examine
1664 * @device: Device to examine (starting at zero)
1665 *
1666 * This technique was originally described in
1667 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1668 * later found its way into the ATA/ATAPI spec.
1669 *
1670 * Write a pattern to the ATA shadow registers,
1671 * and if a device is present, it will respond by
1672 * correctly storing and echoing back the
1673 * ATA shadow register contents.
1674 *
1675 * LOCKING:
1676 * caller.
1677 */
1678static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
1679{
1680 struct ata_ioports *ioaddr = &ap->ioaddr;
1681 u8 nsect, lbal;
1682
1683 ap->ops->sff_dev_select(ap, device);
1684
1685 iowrite8(0x55, ioaddr->nsect_addr);
1686 iowrite8(0xaa, ioaddr->lbal_addr);
1687
1688 iowrite8(0xaa, ioaddr->nsect_addr);
1689 iowrite8(0x55, ioaddr->lbal_addr);
1690
1691 iowrite8(0x55, ioaddr->nsect_addr);
1692 iowrite8(0xaa, ioaddr->lbal_addr);
1693
1694 nsect = ioread8(ioaddr->nsect_addr);
1695 lbal = ioread8(ioaddr->lbal_addr);
1696
1697 if ((nsect == 0x55) && (lbal == 0xaa))
1698 return 1; /* we found a device */
1699
1700 return 0; /* nothing found */
1701}
1702
1703/**
1704 * ata_sff_dev_classify - Parse returned ATA device signature
1705 * @dev: ATA device to classify (starting at zero)
1706 * @present: device seems present
1707 * @r_err: Value of error register on completion
1708 *
1709 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1710 * an ATA/ATAPI-defined set of values is placed in the ATA
1711 * shadow registers, indicating the results of device detection
1712 * and diagnostics.
1713 *
1714 * Select the ATA device, and read the values from the ATA shadow
1715 * registers. Then parse according to the Error register value,
1716 * and the spec-defined values examined by ata_dev_classify().
1717 *
1718 * LOCKING:
1719 * caller.
1720 *
1721 * RETURNS:
1722 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1723 */
1724unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
1725 u8 *r_err)
1726{
1727 struct ata_port *ap = dev->link->ap;
1728 struct ata_taskfile tf;
1729 unsigned int class;
1730 u8 err;
1731
1732 ap->ops->sff_dev_select(ap, dev->devno);
1733
1734 memset(&tf, 0, sizeof(tf));
1735
1736 ap->ops->sff_tf_read(ap, &tf);
1737 err = tf.feature;
1738 if (r_err)
1739 *r_err = err;
1740
1741 /* see if device passed diags: continue and warn later */
1742 if (err == 0)
1743 /* diagnostic fail : do nothing _YET_ */
1744 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1745 else if (err == 1)
1746 /* do nothing */ ;
1747 else if ((dev->devno == 0) && (err == 0x81))
1748 /* do nothing */ ;
1749 else
1750 return ATA_DEV_NONE;
1751
1752 /* determine if device is ATA or ATAPI */
1753 class = ata_dev_classify(&tf);
1754
1755 if (class == ATA_DEV_UNKNOWN) {
1756 /* If the device failed diagnostic, it's likely to
1757 * have reported incorrect device signature too.
1758 * Assume ATA device if the device seems present but
1759 * device signature is invalid with diagnostic
1760 * failure.
1761 */
1762 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1763 class = ATA_DEV_ATA;
1764 else
1765 class = ATA_DEV_NONE;
1766 } else if ((class == ATA_DEV_ATA) &&
1767 (ap->ops->sff_check_status(ap) == 0))
1768 class = ATA_DEV_NONE;
1769
1770 return class;
1771}
1772
1773/**
1774 * ata_sff_wait_after_reset - wait for devices to become ready after reset
1775 * @link: SFF link which is just reset
1776 * @devmask: mask of present devices
1777 * @deadline: deadline jiffies for the operation
1778 *
1779 * Wait devices attached to SFF @link to become ready after
1780 * reset. It contains preceding 150ms wait to avoid accessing TF
1781 * status register too early.
1782 *
1783 * LOCKING:
1784 * Kernel thread context (may sleep).
1785 *
1786 * RETURNS:
1787 * 0 on success, -ENODEV if some or all of devices in @devmask
1788 * don't seem to exist. -errno on other errors.
1789 */
1790int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
1791 unsigned long deadline)
1792{
1793 struct ata_port *ap = link->ap;
1794 struct ata_ioports *ioaddr = &ap->ioaddr;
1795 unsigned int dev0 = devmask & (1 << 0);
1796 unsigned int dev1 = devmask & (1 << 1);
1797 int rc, ret = 0;
1798
1799 msleep(ATA_WAIT_AFTER_RESET_MSECS);
1800
1801 /* always check readiness of the master device */
1802 rc = ata_sff_wait_ready(link, deadline);
1803 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
1804 * and TF status is 0xff, bail out on it too.
1805 */
1806 if (rc)
1807 return rc;
1808
1809 /* if device 1 was found in ata_devchk, wait for register
1810 * access briefly, then wait for BSY to clear.
1811 */
1812 if (dev1) {
1813 int i;
1814
1815 ap->ops->sff_dev_select(ap, 1);
1816
1817 /* Wait for register access. Some ATAPI devices fail
1818 * to set nsect/lbal after reset, so don't waste too
1819 * much time on it. We're gonna wait for !BSY anyway.
1820 */
1821 for (i = 0; i < 2; i++) {
1822 u8 nsect, lbal;
1823
1824 nsect = ioread8(ioaddr->nsect_addr);
1825 lbal = ioread8(ioaddr->lbal_addr);
1826 if ((nsect == 1) && (lbal == 1))
1827 break;
1828 msleep(50); /* give drive a breather */
1829 }
1830
1831 rc = ata_sff_wait_ready(link, deadline);
1832 if (rc) {
1833 if (rc != -ENODEV)
1834 return rc;
1835 ret = rc;
1836 }
1837 }
1838
1839 /* is all this really necessary? */
1840 ap->ops->sff_dev_select(ap, 0);
1841 if (dev1)
1842 ap->ops->sff_dev_select(ap, 1);
1843 if (dev0)
1844 ap->ops->sff_dev_select(ap, 0);
1845
1846 return ret;
1847}
1848
1849static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
1850 unsigned long deadline)
1851{
1852 struct ata_ioports *ioaddr = &ap->ioaddr;
1853
1854 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
1855
1856 /* software reset. causes dev0 to be selected */
1857 iowrite8(ap->ctl, ioaddr->ctl_addr);
1858 udelay(20); /* FIXME: flush */
1859 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1860 udelay(20); /* FIXME: flush */
1861 iowrite8(ap->ctl, ioaddr->ctl_addr);
1862
1863 /* wait the port to become ready */
1864 return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
1865}
1866
1867/**
1868 * ata_sff_softreset - reset host port via ATA SRST
1869 * @link: ATA link to reset
1870 * @classes: resulting classes of attached devices
1871 * @deadline: deadline jiffies for the operation
1872 *
1873 * Reset host port using ATA SRST.
1874 *
1875 * LOCKING:
1876 * Kernel thread context (may sleep)
1877 *
1878 * RETURNS:
1879 * 0 on success, -errno otherwise.
1880 */
1881int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
1882 unsigned long deadline)
1883{
1884 struct ata_port *ap = link->ap;
1885 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1886 unsigned int devmask = 0;
1887 int rc;
1888 u8 err;
1889
1890 DPRINTK("ENTER\n");
1891
1892 /* determine if device 0/1 are present */
1893 if (ata_devchk(ap, 0))
1894 devmask |= (1 << 0);
1895 if (slave_possible && ata_devchk(ap, 1))
1896 devmask |= (1 << 1);
1897
1898 /* select device 0 again */
1899 ap->ops->sff_dev_select(ap, 0);
1900
1901 /* issue bus reset */
1902 DPRINTK("about to softreset, devmask=%x\n", devmask);
1903 rc = ata_bus_softreset(ap, devmask, deadline);
1904 /* if link is occupied, -ENODEV too is an error */
1905 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
1906 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
1907 return rc;
1908 }
1909
1910 /* determine by signature whether we have ATA or ATAPI devices */
1911 classes[0] = ata_sff_dev_classify(&link->device[0],
1912 devmask & (1 << 0), &err);
1913 if (slave_possible && err != 0x81)
1914 classes[1] = ata_sff_dev_classify(&link->device[1],
1915 devmask & (1 << 1), &err);
1916
1917 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
1918 return 0;
1919}
1920
1921/**
1922 * sata_sff_hardreset - reset host port via SATA phy reset
1923 * @link: link to reset
1924 * @class: resulting class of attached device
1925 * @deadline: deadline jiffies for the operation
1926 *
1927 * SATA phy-reset host port using DET bits of SControl register,
1928 * wait for !BSY and classify the attached device.
1929 *
1930 * LOCKING:
1931 * Kernel thread context (may sleep)
1932 *
1933 * RETURNS:
1934 * 0 on success, -errno otherwise.
1935 */
1936int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
1937 unsigned long deadline)
1938{
1939 struct ata_eh_context *ehc = &link->eh_context;
1940 const unsigned long *timing = sata_ehc_deb_timing(ehc);
1941 bool online;
1942 int rc;
1943
1944 rc = sata_link_hardreset(link, timing, deadline, &online,
1945 ata_sff_check_ready);
1946 if (online)
1947 *class = ata_sff_dev_classify(link->device, 1, NULL);
1948
1949 DPRINTK("EXIT, class=%u\n", *class);
1950 return rc;
388} 1951}
389 1952
390/** 1953/**
391 * ata_bmdma_drive_eh - Perform EH with given methods for BMDMA controller 1954 * ata_sff_postreset - SFF postreset callback
1955 * @link: the target SFF ata_link
1956 * @classes: classes of attached devices
1957 *
1958 * This function is invoked after a successful reset. It first
1959 * calls ata_std_postreset() and performs SFF specific postreset
1960 * processing.
1961 *
1962 * LOCKING:
1963 * Kernel thread context (may sleep)
1964 */
1965void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
1966{
1967 struct ata_port *ap = link->ap;
1968
1969 ata_std_postreset(link, classes);
1970
1971 /* is double-select really necessary? */
1972 if (classes[0] != ATA_DEV_NONE)
1973 ap->ops->sff_dev_select(ap, 1);
1974 if (classes[1] != ATA_DEV_NONE)
1975 ap->ops->sff_dev_select(ap, 0);
1976
1977 /* bail out if no device is present */
1978 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
1979 DPRINTK("EXIT, no device\n");
1980 return;
1981 }
1982
1983 /* set up device control */
1984 if (ap->ioaddr.ctl_addr)
1985 iowrite8(ap->ctl, ap->ioaddr.ctl_addr);
1986}
1987
1988/**
1989 * ata_sff_error_handler - Stock error handler for BMDMA controller
392 * @ap: port to handle error for 1990 * @ap: port to handle error for
393 * @prereset: prereset method (can be NULL)
394 * @softreset: softreset method (can be NULL)
395 * @hardreset: hardreset method (can be NULL)
396 * @postreset: postreset method (can be NULL)
397 * 1991 *
398 * Handle error for ATA BMDMA controller. It can handle both 1992 * Stock error handler for SFF controller. It can handle both
399 * PATA and SATA controllers. Many controllers should be able to 1993 * PATA and SATA controllers. Many controllers should be able to
400 * use this EH as-is or with some added handling before and 1994 * use this EH as-is or with some added handling before and
401 * after. 1995 * after.
402 * 1996 *
403 * This function is intended to be used for constructing
404 * ->error_handler callback by low level drivers.
405 *
406 * LOCKING: 1997 * LOCKING:
407 * Kernel thread context (may sleep) 1998 * Kernel thread context (may sleep)
408 */ 1999 */
409void ata_bmdma_drive_eh(struct ata_port *ap, ata_prereset_fn_t prereset, 2000void ata_sff_error_handler(struct ata_port *ap)
410 ata_reset_fn_t softreset, ata_reset_fn_t hardreset,
411 ata_postreset_fn_t postreset)
412{ 2001{
2002 ata_reset_fn_t softreset = ap->ops->softreset;
2003 ata_reset_fn_t hardreset = ap->ops->hardreset;
413 struct ata_queued_cmd *qc; 2004 struct ata_queued_cmd *qc;
414 unsigned long flags; 2005 unsigned long flags;
415 int thaw = 0; 2006 int thaw = 0;
@@ -423,7 +2014,8 @@ void ata_bmdma_drive_eh(struct ata_port *ap, ata_prereset_fn_t prereset,
423 2014
424 ap->hsm_task_state = HSM_ST_IDLE; 2015 ap->hsm_task_state = HSM_ST_IDLE;
425 2016
426 if (qc && (qc->tf.protocol == ATA_PROT_DMA || 2017 if (ap->ioaddr.bmdma_addr &&
2018 qc && (qc->tf.protocol == ATA_PROT_DMA ||
427 qc->tf.protocol == ATAPI_PROT_DMA)) { 2019 qc->tf.protocol == ATAPI_PROT_DMA)) {
428 u8 host_stat; 2020 u8 host_stat;
429 2021
@@ -442,9 +2034,9 @@ void ata_bmdma_drive_eh(struct ata_port *ap, ata_prereset_fn_t prereset,
442 ap->ops->bmdma_stop(qc); 2034 ap->ops->bmdma_stop(qc);
443 } 2035 }
444 2036
445 ata_altstatus(ap); 2037 ata_sff_altstatus(ap);
446 ata_chk_status(ap); 2038 ap->ops->sff_check_status(ap);
447 ap->ops->irq_clear(ap); 2039 ap->ops->sff_irq_clear(ap);
448 2040
449 spin_unlock_irqrestore(ap->lock, flags); 2041 spin_unlock_irqrestore(ap->lock, flags);
450 2042
@@ -452,40 +2044,27 @@ void ata_bmdma_drive_eh(struct ata_port *ap, ata_prereset_fn_t prereset,
452 ata_eh_thaw_port(ap); 2044 ata_eh_thaw_port(ap);
453 2045
454 /* PIO and DMA engines have been stopped, perform recovery */ 2046 /* PIO and DMA engines have been stopped, perform recovery */
455 ata_do_eh(ap, prereset, softreset, hardreset, postreset);
456}
457
458/**
459 * ata_bmdma_error_handler - Stock error handler for BMDMA controller
460 * @ap: port to handle error for
461 *
462 * Stock error handler for BMDMA controller.
463 *
464 * LOCKING:
465 * Kernel thread context (may sleep)
466 */
467void ata_bmdma_error_handler(struct ata_port *ap)
468{
469 ata_reset_fn_t softreset = NULL, hardreset = NULL;
470 2047
471 if (ap->ioaddr.ctl_addr) 2048 /* Ignore ata_sff_softreset if ctl isn't accessible and
472 softreset = ata_std_softreset; 2049 * built-in hardresets if SCR access isn't available.
473 if (sata_scr_valid(&ap->link)) 2050 */
474 hardreset = sata_std_hardreset; 2051 if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr)
2052 softreset = NULL;
2053 if (ata_is_builtin_hardreset(hardreset) && !sata_scr_valid(&ap->link))
2054 hardreset = NULL;
475 2055
476 ata_bmdma_drive_eh(ap, ata_std_prereset, softreset, hardreset, 2056 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
477 ata_std_postreset); 2057 ap->ops->postreset);
478} 2058}
479 2059
480/** 2060/**
481 * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for 2061 * ata_sff_post_internal_cmd - Stock post_internal_cmd for SFF controller
482 * BMDMA controller
483 * @qc: internal command to clean up 2062 * @qc: internal command to clean up
484 * 2063 *
485 * LOCKING: 2064 * LOCKING:
486 * Kernel thread context (may sleep) 2065 * Kernel thread context (may sleep)
487 */ 2066 */
488void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc) 2067void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc)
489{ 2068{
490 if (qc->ap->ioaddr.bmdma_addr) 2069 if (qc->ap->ioaddr.bmdma_addr)
491 ata_bmdma_stop(qc); 2070 ata_bmdma_stop(qc);
@@ -504,7 +2083,6 @@ void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
504 * LOCKING: 2083 * LOCKING:
505 * Inherited from caller. 2084 * Inherited from caller.
506 */ 2085 */
507
508int ata_sff_port_start(struct ata_port *ap) 2086int ata_sff_port_start(struct ata_port *ap)
509{ 2087{
510 if (ap->ioaddr.bmdma_addr) 2088 if (ap->ioaddr.bmdma_addr)
@@ -512,24 +2090,262 @@ int ata_sff_port_start(struct ata_port *ap)
512 return 0; 2090 return 0;
513} 2091}
514 2092
515#ifdef CONFIG_PCI 2093/**
2094 * ata_sff_std_ports - initialize ioaddr with standard port offsets.
2095 * @ioaddr: IO address structure to be initialized
2096 *
2097 * Utility function which initializes data_addr, error_addr,
2098 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2099 * device_addr, status_addr, and command_addr to standard offsets
2100 * relative to cmd_addr.
2101 *
2102 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2103 */
2104void ata_sff_std_ports(struct ata_ioports *ioaddr)
2105{
2106 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2107 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2108 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2109 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2110 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2111 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2112 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2113 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2114 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2115 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2116}
516 2117
517static int ata_resources_present(struct pci_dev *pdev, int port) 2118unsigned long ata_bmdma_mode_filter(struct ata_device *adev,
2119 unsigned long xfer_mask)
518{ 2120{
519 int i; 2121 /* Filter out DMA modes if the device has been configured by
2122 the BIOS as PIO only */
520 2123
521 /* Check the PCI resources for this channel are enabled */ 2124 if (adev->link->ap->ioaddr.bmdma_addr == NULL)
522 port = port * 2; 2125 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
523 for (i = 0; i < 2; i ++) { 2126 return xfer_mask;
524 if (pci_resource_start(pdev, port + i) == 0 || 2127}
525 pci_resource_len(pdev, port + i) == 0) 2128
526 return 0; 2129/**
2130 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
2131 * @qc: Info associated with this ATA transaction.
2132 *
2133 * LOCKING:
2134 * spin_lock_irqsave(host lock)
2135 */
2136void ata_bmdma_setup(struct ata_queued_cmd *qc)
2137{
2138 struct ata_port *ap = qc->ap;
2139 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
2140 u8 dmactl;
2141
2142 /* load PRD table addr. */
2143 mb(); /* make sure PRD table writes are visible to controller */
2144 iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2145
2146 /* specify data direction, triple-check start bit is clear */
2147 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2148 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
2149 if (!rw)
2150 dmactl |= ATA_DMA_WR;
2151 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2152
2153 /* issue r/w command */
2154 ap->ops->sff_exec_command(ap, &qc->tf);
2155}
2156
2157/**
2158 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
2159 * @qc: Info associated with this ATA transaction.
2160 *
2161 * LOCKING:
2162 * spin_lock_irqsave(host lock)
2163 */
2164void ata_bmdma_start(struct ata_queued_cmd *qc)
2165{
2166 struct ata_port *ap = qc->ap;
2167 u8 dmactl;
2168
2169 /* start host DMA transaction */
2170 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2171 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2172
2173 /* Strictly, one may wish to issue an ioread8() here, to
2174 * flush the mmio write. However, control also passes
2175 * to the hardware at this point, and it will interrupt
2176 * us when we are to resume control. So, in effect,
2177 * we don't care when the mmio write flushes.
2178 * Further, a read of the DMA status register _immediately_
2179 * following the write may not be what certain flaky hardware
2180 * is expected, so I think it is best to not add a readb()
2181 * without first all the MMIO ATA cards/mobos.
2182 * Or maybe I'm just being paranoid.
2183 *
2184 * FIXME: The posting of this write means I/O starts are
2185 * unneccessarily delayed for MMIO
2186 */
2187}
2188
2189/**
2190 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
2191 * @qc: Command we are ending DMA for
2192 *
2193 * Clears the ATA_DMA_START flag in the dma control register
2194 *
2195 * May be used as the bmdma_stop() entry in ata_port_operations.
2196 *
2197 * LOCKING:
2198 * spin_lock_irqsave(host lock)
2199 */
2200void ata_bmdma_stop(struct ata_queued_cmd *qc)
2201{
2202 struct ata_port *ap = qc->ap;
2203 void __iomem *mmio = ap->ioaddr.bmdma_addr;
2204
2205 /* clear start/stop bit */
2206 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
2207 mmio + ATA_DMA_CMD);
2208
2209 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
2210 ata_sff_altstatus(ap); /* dummy read */
2211}
2212
2213/**
2214 * ata_bmdma_status - Read PCI IDE BMDMA status
2215 * @ap: Port associated with this ATA transaction.
2216 *
2217 * Read and return BMDMA status register.
2218 *
2219 * May be used as the bmdma_status() entry in ata_port_operations.
2220 *
2221 * LOCKING:
2222 * spin_lock_irqsave(host lock)
2223 */
2224u8 ata_bmdma_status(struct ata_port *ap)
2225{
2226 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
2227}
2228
2229/**
2230 * ata_bus_reset - reset host port and associated ATA channel
2231 * @ap: port to reset
2232 *
2233 * This is typically the first time we actually start issuing
2234 * commands to the ATA channel. We wait for BSY to clear, then
2235 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
2236 * result. Determine what devices, if any, are on the channel
2237 * by looking at the device 0/1 error register. Look at the signature
2238 * stored in each device's taskfile registers, to determine if
2239 * the device is ATA or ATAPI.
2240 *
2241 * LOCKING:
2242 * PCI/etc. bus probe sem.
2243 * Obtains host lock.
2244 *
2245 * SIDE EFFECTS:
2246 * Sets ATA_FLAG_DISABLED if bus reset fails.
2247 *
2248 * DEPRECATED:
2249 * This function is only for drivers which still use old EH and
2250 * will be removed soon.
2251 */
2252void ata_bus_reset(struct ata_port *ap)
2253{
2254 struct ata_device *device = ap->link.device;
2255 struct ata_ioports *ioaddr = &ap->ioaddr;
2256 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2257 u8 err;
2258 unsigned int dev0, dev1 = 0, devmask = 0;
2259 int rc;
2260
2261 DPRINTK("ENTER, host %u, port %u\n", ap->print_id, ap->port_no);
2262
2263 /* determine if device 0/1 are present */
2264 if (ap->flags & ATA_FLAG_SATA_RESET)
2265 dev0 = 1;
2266 else {
2267 dev0 = ata_devchk(ap, 0);
2268 if (slave_possible)
2269 dev1 = ata_devchk(ap, 1);
527 } 2270 }
528 return 1; 2271
2272 if (dev0)
2273 devmask |= (1 << 0);
2274 if (dev1)
2275 devmask |= (1 << 1);
2276
2277 /* select device 0 again */
2278 ap->ops->sff_dev_select(ap, 0);
2279
2280 /* issue bus reset */
2281 if (ap->flags & ATA_FLAG_SRST) {
2282 rc = ata_bus_softreset(ap, devmask, jiffies + 40 * HZ);
2283 if (rc && rc != -ENODEV)
2284 goto err_out;
2285 }
2286
2287 /*
2288 * determine by signature whether we have ATA or ATAPI devices
2289 */
2290 device[0].class = ata_sff_dev_classify(&device[0], dev0, &err);
2291 if ((slave_possible) && (err != 0x81))
2292 device[1].class = ata_sff_dev_classify(&device[1], dev1, &err);
2293
2294 /* is double-select really necessary? */
2295 if (device[1].class != ATA_DEV_NONE)
2296 ap->ops->sff_dev_select(ap, 1);
2297 if (device[0].class != ATA_DEV_NONE)
2298 ap->ops->sff_dev_select(ap, 0);
2299
2300 /* if no devices were detected, disable this port */
2301 if ((device[0].class == ATA_DEV_NONE) &&
2302 (device[1].class == ATA_DEV_NONE))
2303 goto err_out;
2304
2305 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2306 /* set up device control for ATA_FLAG_SATA_RESET */
2307 iowrite8(ap->ctl, ioaddr->ctl_addr);
2308 }
2309
2310 DPRINTK("EXIT\n");
2311 return;
2312
2313err_out:
2314 ata_port_printk(ap, KERN_ERR, "disabling port\n");
2315 ata_port_disable(ap);
2316
2317 DPRINTK("EXIT\n");
529} 2318}
530 2319
2320#ifdef CONFIG_PCI
2321
531/** 2322/**
532 * ata_pci_init_bmdma - acquire PCI BMDMA resources and init ATA host 2323 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
2324 * @pdev: PCI device
2325 *
2326 * Some PCI ATA devices report simplex mode but in fact can be told to
2327 * enter non simplex mode. This implements the necessary logic to
2328 * perform the task on such devices. Calling it on other devices will
2329 * have -undefined- behaviour.
2330 */
2331int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
2332{
2333 unsigned long bmdma = pci_resource_start(pdev, 4);
2334 u8 simplex;
2335
2336 if (bmdma == 0)
2337 return -ENOENT;
2338
2339 simplex = inb(bmdma + 0x02);
2340 outb(simplex & 0x60, bmdma + 0x02);
2341 simplex = inb(bmdma + 0x02);
2342 if (simplex & 0x80)
2343 return -EOPNOTSUPP;
2344 return 0;
2345}
2346
2347/**
2348 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
533 * @host: target ATA host 2349 * @host: target ATA host
534 * 2350 *
535 * Acquire PCI BMDMA resources and initialize @host accordingly. 2351 * Acquire PCI BMDMA resources and initialize @host accordingly.
@@ -540,7 +2356,7 @@ static int ata_resources_present(struct pci_dev *pdev, int port)
540 * RETURNS: 2356 * RETURNS:
541 * 0 on success, -errno otherwise. 2357 * 0 on success, -errno otherwise.
542 */ 2358 */
543int ata_pci_init_bmdma(struct ata_host *host) 2359int ata_pci_bmdma_init(struct ata_host *host)
544{ 2360{
545 struct device *gdev = host->dev; 2361 struct device *gdev = host->dev;
546 struct pci_dev *pdev = to_pci_dev(gdev); 2362 struct pci_dev *pdev = to_pci_dev(gdev);
@@ -585,8 +2401,22 @@ int ata_pci_init_bmdma(struct ata_host *host)
585 return 0; 2401 return 0;
586} 2402}
587 2403
2404static int ata_resources_present(struct pci_dev *pdev, int port)
2405{
2406 int i;
2407
2408 /* Check the PCI resources for this channel are enabled */
2409 port = port * 2;
2410 for (i = 0; i < 2; i ++) {
2411 if (pci_resource_start(pdev, port + i) == 0 ||
2412 pci_resource_len(pdev, port + i) == 0)
2413 return 0;
2414 }
2415 return 1;
2416}
2417
588/** 2418/**
589 * ata_pci_init_sff_host - acquire native PCI ATA resources and init host 2419 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
590 * @host: target ATA host 2420 * @host: target ATA host
591 * 2421 *
592 * Acquire native PCI ATA resources for @host and initialize the 2422 * Acquire native PCI ATA resources for @host and initialize the
@@ -604,7 +2434,7 @@ int ata_pci_init_bmdma(struct ata_host *host)
604 * 0 if at least one port is initialized, -ENODEV if no port is 2434 * 0 if at least one port is initialized, -ENODEV if no port is
605 * available. 2435 * available.
606 */ 2436 */
607int ata_pci_init_sff_host(struct ata_host *host) 2437int ata_pci_sff_init_host(struct ata_host *host)
608{ 2438{
609 struct device *gdev = host->dev; 2439 struct device *gdev = host->dev;
610 struct pci_dev *pdev = to_pci_dev(gdev); 2440 struct pci_dev *pdev = to_pci_dev(gdev);
@@ -646,7 +2476,7 @@ int ata_pci_init_sff_host(struct ata_host *host)
646 ap->ioaddr.altstatus_addr = 2476 ap->ioaddr.altstatus_addr =
647 ap->ioaddr.ctl_addr = (void __iomem *) 2477 ap->ioaddr.ctl_addr = (void __iomem *)
648 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS); 2478 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
649 ata_std_ports(&ap->ioaddr); 2479 ata_sff_std_ports(&ap->ioaddr);
650 2480
651 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", 2481 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
652 (unsigned long long)pci_resource_start(pdev, base), 2482 (unsigned long long)pci_resource_start(pdev, base),
@@ -664,7 +2494,7 @@ int ata_pci_init_sff_host(struct ata_host *host)
664} 2494}
665 2495
666/** 2496/**
667 * ata_pci_prepare_sff_host - helper to prepare native PCI ATA host 2497 * ata_pci_sff_prepare_host - helper to prepare native PCI ATA host
668 * @pdev: target PCI device 2498 * @pdev: target PCI device
669 * @ppi: array of port_info, must be enough for two ports 2499 * @ppi: array of port_info, must be enough for two ports
670 * @r_host: out argument for the initialized ATA host 2500 * @r_host: out argument for the initialized ATA host
@@ -678,7 +2508,7 @@ int ata_pci_init_sff_host(struct ata_host *host)
678 * RETURNS: 2508 * RETURNS:
679 * 0 on success, -errno otherwise. 2509 * 0 on success, -errno otherwise.
680 */ 2510 */
681int ata_pci_prepare_sff_host(struct pci_dev *pdev, 2511int ata_pci_sff_prepare_host(struct pci_dev *pdev,
682 const struct ata_port_info * const * ppi, 2512 const struct ata_port_info * const * ppi,
683 struct ata_host **r_host) 2513 struct ata_host **r_host)
684{ 2514{
@@ -696,12 +2526,12 @@ int ata_pci_prepare_sff_host(struct pci_dev *pdev,
696 goto err_out; 2526 goto err_out;
697 } 2527 }
698 2528
699 rc = ata_pci_init_sff_host(host); 2529 rc = ata_pci_sff_init_host(host);
700 if (rc) 2530 if (rc)
701 goto err_out; 2531 goto err_out;
702 2532
703 /* init DMA related stuff */ 2533 /* init DMA related stuff */
704 rc = ata_pci_init_bmdma(host); 2534 rc = ata_pci_bmdma_init(host);
705 if (rc) 2535 if (rc)
706 goto err_bmdma; 2536 goto err_bmdma;
707 2537
@@ -722,7 +2552,7 @@ int ata_pci_prepare_sff_host(struct pci_dev *pdev,
722} 2552}
723 2553
724/** 2554/**
725 * ata_pci_activate_sff_host - start SFF host, request IRQ and register it 2555 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
726 * @host: target SFF ATA host 2556 * @host: target SFF ATA host
727 * @irq_handler: irq_handler used when requesting IRQ(s) 2557 * @irq_handler: irq_handler used when requesting IRQ(s)
728 * @sht: scsi_host_template to use when registering the host 2558 * @sht: scsi_host_template to use when registering the host
@@ -737,7 +2567,7 @@ int ata_pci_prepare_sff_host(struct pci_dev *pdev,
737 * RETURNS: 2567 * RETURNS:
738 * 0 on success, -errno otherwise. 2568 * 0 on success, -errno otherwise.
739 */ 2569 */
740int ata_pci_activate_sff_host(struct ata_host *host, 2570int ata_pci_sff_activate_host(struct ata_host *host,
741 irq_handler_t irq_handler, 2571 irq_handler_t irq_handler,
742 struct scsi_host_template *sht) 2572 struct scsi_host_template *sht)
743{ 2573{
@@ -815,9 +2645,11 @@ int ata_pci_activate_sff_host(struct ata_host *host,
815} 2645}
816 2646
817/** 2647/**
818 * ata_pci_init_one - Initialize/register PCI IDE host controller 2648 * ata_pci_sff_init_one - Initialize/register PCI IDE host controller
819 * @pdev: Controller to be initialized 2649 * @pdev: Controller to be initialized
820 * @ppi: array of port_info, must be enough for two ports 2650 * @ppi: array of port_info, must be enough for two ports
2651 * @sht: scsi_host_template to use when registering the host
2652 * @host_priv: host private_data
821 * 2653 *
822 * This is a helper function which can be called from a driver's 2654 * This is a helper function which can be called from a driver's
823 * xxx_init_one() probe function if the hardware uses traditional 2655 * xxx_init_one() probe function if the hardware uses traditional
@@ -837,8 +2669,9 @@ int ata_pci_activate_sff_host(struct ata_host *host,
837 * RETURNS: 2669 * RETURNS:
838 * Zero on success, negative on errno-based value on error. 2670 * Zero on success, negative on errno-based value on error.
839 */ 2671 */
840int ata_pci_init_one(struct pci_dev *pdev, 2672int ata_pci_sff_init_one(struct pci_dev *pdev,
841 const struct ata_port_info * const * ppi) 2673 const struct ata_port_info * const * ppi,
2674 struct scsi_host_template *sht, void *host_priv)
842{ 2675{
843 struct device *dev = &pdev->dev; 2676 struct device *dev = &pdev->dev;
844 const struct ata_port_info *pi = NULL; 2677 const struct ata_port_info *pi = NULL;
@@ -869,13 +2702,13 @@ int ata_pci_init_one(struct pci_dev *pdev,
869 goto out; 2702 goto out;
870 2703
871 /* prepare and activate SFF host */ 2704 /* prepare and activate SFF host */
872 rc = ata_pci_prepare_sff_host(pdev, ppi, &host); 2705 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
873 if (rc) 2706 if (rc)
874 goto out; 2707 goto out;
2708 host->private_data = host_priv;
875 2709
876 pci_set_master(pdev); 2710 pci_set_master(pdev);
877 rc = ata_pci_activate_sff_host(host, pi->port_ops->irq_handler, 2711 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
878 pi->sht);
879 out: 2712 out:
880 if (rc == 0) 2713 if (rc == 0)
881 devres_remove_group(&pdev->dev, NULL); 2714 devres_remove_group(&pdev->dev, NULL);
@@ -885,41 +2718,52 @@ int ata_pci_init_one(struct pci_dev *pdev,
885 return rc; 2718 return rc;
886} 2719}
887 2720
888/**
889 * ata_pci_clear_simplex - attempt to kick device out of simplex
890 * @pdev: PCI device
891 *
892 * Some PCI ATA devices report simplex mode but in fact can be told to
893 * enter non simplex mode. This implements the necessary logic to
894 * perform the task on such devices. Calling it on other devices will
895 * have -undefined- behaviour.
896 */
897
898int ata_pci_clear_simplex(struct pci_dev *pdev)
899{
900 unsigned long bmdma = pci_resource_start(pdev, 4);
901 u8 simplex;
902
903 if (bmdma == 0)
904 return -ENOENT;
905
906 simplex = inb(bmdma + 0x02);
907 outb(simplex & 0x60, bmdma + 0x02);
908 simplex = inb(bmdma + 0x02);
909 if (simplex & 0x80)
910 return -EOPNOTSUPP;
911 return 0;
912}
913
914unsigned long ata_pci_default_filter(struct ata_device *adev, unsigned long xfer_mask)
915{
916 /* Filter out DMA modes if the device has been configured by
917 the BIOS as PIO only */
918
919 if (adev->link->ap->ioaddr.bmdma_addr == NULL)
920 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
921 return xfer_mask;
922}
923
924#endif /* CONFIG_PCI */ 2721#endif /* CONFIG_PCI */
925 2722
2723EXPORT_SYMBOL_GPL(ata_sff_port_ops);
2724EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
2725EXPORT_SYMBOL_GPL(ata_sff_qc_prep);
2726EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep);
2727EXPORT_SYMBOL_GPL(ata_sff_dev_select);
2728EXPORT_SYMBOL_GPL(ata_sff_check_status);
2729EXPORT_SYMBOL_GPL(ata_sff_altstatus);
2730EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
2731EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
2732EXPORT_SYMBOL_GPL(ata_sff_tf_load);
2733EXPORT_SYMBOL_GPL(ata_sff_tf_read);
2734EXPORT_SYMBOL_GPL(ata_sff_exec_command);
2735EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
2736EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq);
2737EXPORT_SYMBOL_GPL(ata_sff_irq_on);
2738EXPORT_SYMBOL_GPL(ata_sff_irq_clear);
2739EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
2740EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
2741EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
2742EXPORT_SYMBOL_GPL(ata_sff_host_intr);
2743EXPORT_SYMBOL_GPL(ata_sff_interrupt);
2744EXPORT_SYMBOL_GPL(ata_sff_freeze);
2745EXPORT_SYMBOL_GPL(ata_sff_thaw);
2746EXPORT_SYMBOL_GPL(ata_sff_prereset);
2747EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
2748EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
2749EXPORT_SYMBOL_GPL(ata_sff_softreset);
2750EXPORT_SYMBOL_GPL(sata_sff_hardreset);
2751EXPORT_SYMBOL_GPL(ata_sff_postreset);
2752EXPORT_SYMBOL_GPL(ata_sff_error_handler);
2753EXPORT_SYMBOL_GPL(ata_sff_post_internal_cmd);
2754EXPORT_SYMBOL_GPL(ata_sff_port_start);
2755EXPORT_SYMBOL_GPL(ata_sff_std_ports);
2756EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter);
2757EXPORT_SYMBOL_GPL(ata_bmdma_setup);
2758EXPORT_SYMBOL_GPL(ata_bmdma_start);
2759EXPORT_SYMBOL_GPL(ata_bmdma_stop);
2760EXPORT_SYMBOL_GPL(ata_bmdma_status);
2761EXPORT_SYMBOL_GPL(ata_bus_reset);
2762#ifdef CONFIG_PCI
2763EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
2764EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
2765EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
2766EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
2767EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
2768EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
2769#endif /* CONFIG_PCI */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 15:36:07 -0500