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-rw-r--r--drivers/ata/libata-sff.c1859
1 files changed, 1856 insertions, 3 deletions
diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c
index 40645ed125b1..840ae6da59bc 100644
--- a/drivers/ata/libata-sff.c
+++ b/drivers/ata/libata-sff.c
@@ -35,9 +35,185 @@
35#include <linux/kernel.h> 35#include <linux/kernel.h>
36#include <linux/pci.h> 36#include <linux/pci.h>
37#include <linux/libata.h> 37#include <linux/libata.h>
38#include <linux/highmem.h>
38 39
39#include "libata.h" 40#include "libata.h"
40 41
42const struct ata_port_operations ata_sff_port_ops = {
43 .inherits = &ata_base_port_ops,
44
45 .qc_prep = ata_qc_prep,
46 .qc_issue = ata_qc_issue_prot,
47
48 .freeze = ata_bmdma_freeze,
49 .thaw = ata_bmdma_thaw,
50 .softreset = ata_std_softreset,
51 .error_handler = ata_bmdma_error_handler,
52 .post_internal_cmd = ata_bmdma_post_internal_cmd,
53
54 .dev_select = ata_std_dev_select,
55 .check_status = ata_check_status,
56 .tf_load = ata_tf_load,
57 .tf_read = ata_tf_read,
58 .exec_command = ata_exec_command,
59 .data_xfer = ata_data_xfer,
60 .irq_on = ata_irq_on,
61
62 .port_start = ata_sff_port_start,
63};
64
65const struct ata_port_operations ata_bmdma_port_ops = {
66 .inherits = &ata_sff_port_ops,
67
68 .mode_filter = ata_pci_default_filter,
69
70 .bmdma_setup = ata_bmdma_setup,
71 .bmdma_start = ata_bmdma_start,
72 .bmdma_stop = ata_bmdma_stop,
73 .bmdma_status = ata_bmdma_status,
74 .irq_clear = ata_bmdma_irq_clear,
75};
76
77/**
78 * ata_fill_sg - Fill PCI IDE PRD table
79 * @qc: Metadata associated with taskfile to be transferred
80 *
81 * Fill PCI IDE PRD (scatter-gather) table with segments
82 * associated with the current disk command.
83 *
84 * LOCKING:
85 * spin_lock_irqsave(host lock)
86 *
87 */
88static void ata_fill_sg(struct ata_queued_cmd *qc)
89{
90 struct ata_port *ap = qc->ap;
91 struct scatterlist *sg;
92 unsigned int si, pi;
93
94 pi = 0;
95 for_each_sg(qc->sg, sg, qc->n_elem, si) {
96 u32 addr, offset;
97 u32 sg_len, len;
98
99 /* determine if physical DMA addr spans 64K boundary.
100 * Note h/w doesn't support 64-bit, so we unconditionally
101 * truncate dma_addr_t to u32.
102 */
103 addr = (u32) sg_dma_address(sg);
104 sg_len = sg_dma_len(sg);
105
106 while (sg_len) {
107 offset = addr & 0xffff;
108 len = sg_len;
109 if ((offset + sg_len) > 0x10000)
110 len = 0x10000 - offset;
111
112 ap->prd[pi].addr = cpu_to_le32(addr);
113 ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff);
114 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
115
116 pi++;
117 sg_len -= len;
118 addr += len;
119 }
120 }
121
122 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
123}
124
125/**
126 * ata_fill_sg_dumb - Fill PCI IDE PRD table
127 * @qc: Metadata associated with taskfile to be transferred
128 *
129 * Fill PCI IDE PRD (scatter-gather) table with segments
130 * associated with the current disk command. Perform the fill
131 * so that we avoid writing any length 64K records for
132 * controllers that don't follow the spec.
133 *
134 * LOCKING:
135 * spin_lock_irqsave(host lock)
136 *
137 */
138static void ata_fill_sg_dumb(struct ata_queued_cmd *qc)
139{
140 struct ata_port *ap = qc->ap;
141 struct scatterlist *sg;
142 unsigned int si, pi;
143
144 pi = 0;
145 for_each_sg(qc->sg, sg, qc->n_elem, si) {
146 u32 addr, offset;
147 u32 sg_len, len, blen;
148
149 /* determine if physical DMA addr spans 64K boundary.
150 * Note h/w doesn't support 64-bit, so we unconditionally
151 * truncate dma_addr_t to u32.
152 */
153 addr = (u32) sg_dma_address(sg);
154 sg_len = sg_dma_len(sg);
155
156 while (sg_len) {
157 offset = addr & 0xffff;
158 len = sg_len;
159 if ((offset + sg_len) > 0x10000)
160 len = 0x10000 - offset;
161
162 blen = len & 0xffff;
163 ap->prd[pi].addr = cpu_to_le32(addr);
164 if (blen == 0) {
165 /* Some PATA chipsets like the CS5530 can't
166 cope with 0x0000 meaning 64K as the spec says */
167 ap->prd[pi].flags_len = cpu_to_le32(0x8000);
168 blen = 0x8000;
169 ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000);
170 }
171 ap->prd[pi].flags_len = cpu_to_le32(blen);
172 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
173
174 pi++;
175 sg_len -= len;
176 addr += len;
177 }
178 }
179
180 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
181}
182
183/**
184 * ata_qc_prep - Prepare taskfile for submission
185 * @qc: Metadata associated with taskfile to be prepared
186 *
187 * Prepare ATA taskfile for submission.
188 *
189 * LOCKING:
190 * spin_lock_irqsave(host lock)
191 */
192void ata_qc_prep(struct ata_queued_cmd *qc)
193{
194 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
195 return;
196
197 ata_fill_sg(qc);
198}
199
200/**
201 * ata_dumb_qc_prep - Prepare taskfile for submission
202 * @qc: Metadata associated with taskfile to be prepared
203 *
204 * Prepare ATA taskfile for submission.
205 *
206 * LOCKING:
207 * spin_lock_irqsave(host lock)
208 */
209void ata_dumb_qc_prep(struct ata_queued_cmd *qc)
210{
211 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
212 return;
213
214 ata_fill_sg_dumb(qc);
215}
216
41/** 217/**
42 * ata_check_status - Read device status reg & clear interrupt 218 * ata_check_status - Read device status reg & clear interrupt
43 * @ap: port where the device is 219 * @ap: port where the device is
@@ -76,6 +252,167 @@ u8 ata_altstatus(struct ata_port *ap)
76} 252}
77 253
78/** 254/**
255 * ata_busy_sleep - sleep until BSY clears, or timeout
256 * @ap: port containing status register to be polled
257 * @tmout_pat: impatience timeout
258 * @tmout: overall timeout
259 *
260 * Sleep until ATA Status register bit BSY clears,
261 * or a timeout occurs.
262 *
263 * LOCKING:
264 * Kernel thread context (may sleep).
265 *
266 * RETURNS:
267 * 0 on success, -errno otherwise.
268 */
269int ata_busy_sleep(struct ata_port *ap,
270 unsigned long tmout_pat, unsigned long tmout)
271{
272 unsigned long timer_start, timeout;
273 u8 status;
274
275 status = ata_busy_wait(ap, ATA_BUSY, 300);
276 timer_start = jiffies;
277 timeout = timer_start + tmout_pat;
278 while (status != 0xff && (status & ATA_BUSY) &&
279 time_before(jiffies, timeout)) {
280 msleep(50);
281 status = ata_busy_wait(ap, ATA_BUSY, 3);
282 }
283
284 if (status != 0xff && (status & ATA_BUSY))
285 ata_port_printk(ap, KERN_WARNING,
286 "port is slow to respond, please be patient "
287 "(Status 0x%x)\n", status);
288
289 timeout = timer_start + tmout;
290 while (status != 0xff && (status & ATA_BUSY) &&
291 time_before(jiffies, timeout)) {
292 msleep(50);
293 status = ata_chk_status(ap);
294 }
295
296 if (status == 0xff)
297 return -ENODEV;
298
299 if (status & ATA_BUSY) {
300 ata_port_printk(ap, KERN_ERR, "port failed to respond "
301 "(%lu secs, Status 0x%x)\n",
302 tmout / HZ, status);
303 return -EBUSY;
304 }
305
306 return 0;
307}
308
309/**
310 * ata_wait_ready - sleep until BSY clears, or timeout
311 * @ap: port containing status register to be polled
312 * @deadline: deadline jiffies for the operation
313 *
314 * Sleep until ATA Status register bit BSY clears, or timeout
315 * occurs.
316 *
317 * LOCKING:
318 * Kernel thread context (may sleep).
319 *
320 * RETURNS:
321 * 0 on success, -errno otherwise.
322 */
323int ata_wait_ready(struct ata_port *ap, unsigned long deadline)
324{
325 unsigned long start = jiffies;
326 int warned = 0;
327
328 while (1) {
329 u8 status = ata_chk_status(ap);
330 unsigned long now = jiffies;
331
332 if (!(status & ATA_BUSY))
333 return 0;
334 if (!ata_link_online(&ap->link) && status == 0xff)
335 return -ENODEV;
336 if (time_after(now, deadline))
337 return -EBUSY;
338
339 if (!warned && time_after(now, start + 5 * HZ) &&
340 (deadline - now > 3 * HZ)) {
341 ata_port_printk(ap, KERN_WARNING,
342 "port is slow to respond, please be patient "
343 "(Status 0x%x)\n", status);
344 warned = 1;
345 }
346
347 msleep(50);
348 }
349}
350
351/**
352 * ata_std_dev_select - Select device 0/1 on ATA bus
353 * @ap: ATA channel to manipulate
354 * @device: ATA device (numbered from zero) to select
355 *
356 * Use the method defined in the ATA specification to
357 * make either device 0, or device 1, active on the
358 * ATA channel. Works with both PIO and MMIO.
359 *
360 * May be used as the dev_select() entry in ata_port_operations.
361 *
362 * LOCKING:
363 * caller.
364 */
365void ata_std_dev_select(struct ata_port *ap, unsigned int device)
366{
367 u8 tmp;
368
369 if (device == 0)
370 tmp = ATA_DEVICE_OBS;
371 else
372 tmp = ATA_DEVICE_OBS | ATA_DEV1;
373
374 iowrite8(tmp, ap->ioaddr.device_addr);
375 ata_pause(ap); /* needed; also flushes, for mmio */
376}
377
378/**
379 * ata_dev_select - Select device 0/1 on ATA bus
380 * @ap: ATA channel to manipulate
381 * @device: ATA device (numbered from zero) to select
382 * @wait: non-zero to wait for Status register BSY bit to clear
383 * @can_sleep: non-zero if context allows sleeping
384 *
385 * Use the method defined in the ATA specification to
386 * make either device 0, or device 1, active on the
387 * ATA channel.
388 *
389 * This is a high-level version of ata_std_dev_select(),
390 * which additionally provides the services of inserting
391 * the proper pauses and status polling, where needed.
392 *
393 * LOCKING:
394 * caller.
395 */
396void ata_dev_select(struct ata_port *ap, unsigned int device,
397 unsigned int wait, unsigned int can_sleep)
398{
399 if (ata_msg_probe(ap))
400 ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, "
401 "device %u, wait %u\n", device, wait);
402
403 if (wait)
404 ata_wait_idle(ap);
405
406 ap->ops->dev_select(ap, device);
407
408 if (wait) {
409 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
410 msleep(150);
411 ata_wait_idle(ap);
412 }
413}
414
415/**
79 * ata_irq_on - Enable interrupts on a port. 416 * ata_irq_on - Enable interrupts on a port.
80 * @ap: Port on which interrupts are enabled. 417 * @ap: Port on which interrupts are enabled.
81 * 418 *
@@ -242,6 +579,987 @@ void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
242} 579}
243 580
244/** 581/**
582 * ata_tf_to_host - issue ATA taskfile to host controller
583 * @ap: port to which command is being issued
584 * @tf: ATA taskfile register set
585 *
586 * Issues ATA taskfile register set to ATA host controller,
587 * with proper synchronization with interrupt handler and
588 * other threads.
589 *
590 * LOCKING:
591 * spin_lock_irqsave(host lock)
592 */
593static inline void ata_tf_to_host(struct ata_port *ap,
594 const struct ata_taskfile *tf)
595{
596 ap->ops->tf_load(ap, tf);
597 ap->ops->exec_command(ap, tf);
598}
599
600/**
601 * ata_data_xfer - Transfer data by PIO
602 * @dev: device to target
603 * @buf: data buffer
604 * @buflen: buffer length
605 * @rw: read/write
606 *
607 * Transfer data from/to the device data register by PIO.
608 *
609 * LOCKING:
610 * Inherited from caller.
611 *
612 * RETURNS:
613 * Bytes consumed.
614 */
615unsigned int ata_data_xfer(struct ata_device *dev, unsigned char *buf,
616 unsigned int buflen, int rw)
617{
618 struct ata_port *ap = dev->link->ap;
619 void __iomem *data_addr = ap->ioaddr.data_addr;
620 unsigned int words = buflen >> 1;
621
622 /* Transfer multiple of 2 bytes */
623 if (rw == READ)
624 ioread16_rep(data_addr, buf, words);
625 else
626 iowrite16_rep(data_addr, buf, words);
627
628 /* Transfer trailing 1 byte, if any. */
629 if (unlikely(buflen & 0x01)) {
630 __le16 align_buf[1] = { 0 };
631 unsigned char *trailing_buf = buf + buflen - 1;
632
633 if (rw == READ) {
634 align_buf[0] = cpu_to_le16(ioread16(data_addr));
635 memcpy(trailing_buf, align_buf, 1);
636 } else {
637 memcpy(align_buf, trailing_buf, 1);
638 iowrite16(le16_to_cpu(align_buf[0]), data_addr);
639 }
640 words++;
641 }
642
643 return words << 1;
644}
645
646/**
647 * ata_data_xfer_noirq - Transfer data by PIO
648 * @dev: device to target
649 * @buf: data buffer
650 * @buflen: buffer length
651 * @rw: read/write
652 *
653 * Transfer data from/to the device data register by PIO. Do the
654 * transfer with interrupts disabled.
655 *
656 * LOCKING:
657 * Inherited from caller.
658 *
659 * RETURNS:
660 * Bytes consumed.
661 */
662unsigned int ata_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
663 unsigned int buflen, int rw)
664{
665 unsigned long flags;
666 unsigned int consumed;
667
668 local_irq_save(flags);
669 consumed = ata_data_xfer(dev, buf, buflen, rw);
670 local_irq_restore(flags);
671
672 return consumed;
673}
674
675/**
676 * ata_pio_sector - Transfer a sector of data.
677 * @qc: Command on going
678 *
679 * Transfer qc->sect_size bytes of data from/to the ATA device.
680 *
681 * LOCKING:
682 * Inherited from caller.
683 */
684static void ata_pio_sector(struct ata_queued_cmd *qc)
685{
686 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
687 struct ata_port *ap = qc->ap;
688 struct page *page;
689 unsigned int offset;
690 unsigned char *buf;
691
692 if (qc->curbytes == qc->nbytes - qc->sect_size)
693 ap->hsm_task_state = HSM_ST_LAST;
694
695 page = sg_page(qc->cursg);
696 offset = qc->cursg->offset + qc->cursg_ofs;
697
698 /* get the current page and offset */
699 page = nth_page(page, (offset >> PAGE_SHIFT));
700 offset %= PAGE_SIZE;
701
702 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
703
704 if (PageHighMem(page)) {
705 unsigned long flags;
706
707 /* FIXME: use a bounce buffer */
708 local_irq_save(flags);
709 buf = kmap_atomic(page, KM_IRQ0);
710
711 /* do the actual data transfer */
712 ap->ops->data_xfer(qc->dev, buf + offset, qc->sect_size, do_write);
713
714 kunmap_atomic(buf, KM_IRQ0);
715 local_irq_restore(flags);
716 } else {
717 buf = page_address(page);
718 ap->ops->data_xfer(qc->dev, buf + offset, qc->sect_size, do_write);
719 }
720
721 qc->curbytes += qc->sect_size;
722 qc->cursg_ofs += qc->sect_size;
723
724 if (qc->cursg_ofs == qc->cursg->length) {
725 qc->cursg = sg_next(qc->cursg);
726 qc->cursg_ofs = 0;
727 }
728}
729
730/**
731 * ata_pio_sectors - Transfer one or many sectors.
732 * @qc: Command on going
733 *
734 * Transfer one or many sectors of data from/to the
735 * ATA device for the DRQ request.
736 *
737 * LOCKING:
738 * Inherited from caller.
739 */
740static void ata_pio_sectors(struct ata_queued_cmd *qc)
741{
742 if (is_multi_taskfile(&qc->tf)) {
743 /* READ/WRITE MULTIPLE */
744 unsigned int nsect;
745
746 WARN_ON(qc->dev->multi_count == 0);
747
748 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
749 qc->dev->multi_count);
750 while (nsect--)
751 ata_pio_sector(qc);
752 } else
753 ata_pio_sector(qc);
754
755 ata_altstatus(qc->ap); /* flush */
756}
757
758/**
759 * atapi_send_cdb - Write CDB bytes to hardware
760 * @ap: Port to which ATAPI device is attached.
761 * @qc: Taskfile currently active
762 *
763 * When device has indicated its readiness to accept
764 * a CDB, this function is called. Send the CDB.
765 *
766 * LOCKING:
767 * caller.
768 */
769static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
770{
771 /* send SCSI cdb */
772 DPRINTK("send cdb\n");
773 WARN_ON(qc->dev->cdb_len < 12);
774
775 ap->ops->data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
776 ata_altstatus(ap); /* flush */
777
778 switch (qc->tf.protocol) {
779 case ATAPI_PROT_PIO:
780 ap->hsm_task_state = HSM_ST;
781 break;
782 case ATAPI_PROT_NODATA:
783 ap->hsm_task_state = HSM_ST_LAST;
784 break;
785 case ATAPI_PROT_DMA:
786 ap->hsm_task_state = HSM_ST_LAST;
787 /* initiate bmdma */
788 ap->ops->bmdma_start(qc);
789 break;
790 }
791}
792
793/**
794 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
795 * @qc: Command on going
796 * @bytes: number of bytes
797 *
798 * Transfer Transfer data from/to the ATAPI device.
799 *
800 * LOCKING:
801 * Inherited from caller.
802 *
803 */
804static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
805{
806 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
807 struct ata_port *ap = qc->ap;
808 struct ata_device *dev = qc->dev;
809 struct ata_eh_info *ehi = &dev->link->eh_info;
810 struct scatterlist *sg;
811 struct page *page;
812 unsigned char *buf;
813 unsigned int offset, count, consumed;
814
815next_sg:
816 sg = qc->cursg;
817 if (unlikely(!sg)) {
818 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
819 "buf=%u cur=%u bytes=%u",
820 qc->nbytes, qc->curbytes, bytes);
821 return -1;
822 }
823
824 page = sg_page(sg);
825 offset = sg->offset + qc->cursg_ofs;
826
827 /* get the current page and offset */
828 page = nth_page(page, (offset >> PAGE_SHIFT));
829 offset %= PAGE_SIZE;
830
831 /* don't overrun current sg */
832 count = min(sg->length - qc->cursg_ofs, bytes);
833
834 /* don't cross page boundaries */
835 count = min(count, (unsigned int)PAGE_SIZE - offset);
836
837 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
838
839 if (PageHighMem(page)) {
840 unsigned long flags;
841
842 /* FIXME: use bounce buffer */
843 local_irq_save(flags);
844 buf = kmap_atomic(page, KM_IRQ0);
845
846 /* do the actual data transfer */
847 consumed = ap->ops->data_xfer(dev, buf + offset, count, rw);
848
849 kunmap_atomic(buf, KM_IRQ0);
850 local_irq_restore(flags);
851 } else {
852 buf = page_address(page);
853 consumed = ap->ops->data_xfer(dev, buf + offset, count, rw);
854 }
855
856 bytes -= min(bytes, consumed);
857 qc->curbytes += count;
858 qc->cursg_ofs += count;
859
860 if (qc->cursg_ofs == sg->length) {
861 qc->cursg = sg_next(qc->cursg);
862 qc->cursg_ofs = 0;
863 }
864
865 /* consumed can be larger than count only for the last transfer */
866 WARN_ON(qc->cursg && count != consumed);
867
868 if (bytes)
869 goto next_sg;
870 return 0;
871}
872
873/**
874 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
875 * @qc: Command on going
876 *
877 * Transfer Transfer data from/to the ATAPI device.
878 *
879 * LOCKING:
880 * Inherited from caller.
881 */
882static void atapi_pio_bytes(struct ata_queued_cmd *qc)
883{
884 struct ata_port *ap = qc->ap;
885 struct ata_device *dev = qc->dev;
886 struct ata_eh_info *ehi = &dev->link->eh_info;
887 unsigned int ireason, bc_lo, bc_hi, bytes;
888 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
889
890 /* Abuse qc->result_tf for temp storage of intermediate TF
891 * here to save some kernel stack usage.
892 * For normal completion, qc->result_tf is not relevant. For
893 * error, qc->result_tf is later overwritten by ata_qc_complete().
894 * So, the correctness of qc->result_tf is not affected.
895 */
896 ap->ops->tf_read(ap, &qc->result_tf);
897 ireason = qc->result_tf.nsect;
898 bc_lo = qc->result_tf.lbam;
899 bc_hi = qc->result_tf.lbah;
900 bytes = (bc_hi << 8) | bc_lo;
901
902 /* shall be cleared to zero, indicating xfer of data */
903 if (unlikely(ireason & (1 << 0)))
904 goto atapi_check;
905
906 /* make sure transfer direction matches expected */
907 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
908 if (unlikely(do_write != i_write))
909 goto atapi_check;
910
911 if (unlikely(!bytes))
912 goto atapi_check;
913
914 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
915
916 if (unlikely(__atapi_pio_bytes(qc, bytes)))
917 goto err_out;
918 ata_altstatus(ap); /* flush */
919
920 return;
921
922 atapi_check:
923 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
924 ireason, bytes);
925 err_out:
926 qc->err_mask |= AC_ERR_HSM;
927 ap->hsm_task_state = HSM_ST_ERR;
928}
929
930/**
931 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
932 * @ap: the target ata_port
933 * @qc: qc on going
934 *
935 * RETURNS:
936 * 1 if ok in workqueue, 0 otherwise.
937 */
938static inline int ata_hsm_ok_in_wq(struct ata_port *ap, struct ata_queued_cmd *qc)
939{
940 if (qc->tf.flags & ATA_TFLAG_POLLING)
941 return 1;
942
943 if (ap->hsm_task_state == HSM_ST_FIRST) {
944 if (qc->tf.protocol == ATA_PROT_PIO &&
945 (qc->tf.flags & ATA_TFLAG_WRITE))
946 return 1;
947
948 if (ata_is_atapi(qc->tf.protocol) &&
949 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
950 return 1;
951 }
952
953 return 0;
954}
955
956/**
957 * ata_hsm_qc_complete - finish a qc running on standard HSM
958 * @qc: Command to complete
959 * @in_wq: 1 if called from workqueue, 0 otherwise
960 *
961 * Finish @qc which is running on standard HSM.
962 *
963 * LOCKING:
964 * If @in_wq is zero, spin_lock_irqsave(host lock).
965 * Otherwise, none on entry and grabs host lock.
966 */
967static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
968{
969 struct ata_port *ap = qc->ap;
970 unsigned long flags;
971
972 if (ap->ops->error_handler) {
973 if (in_wq) {
974 spin_lock_irqsave(ap->lock, flags);
975
976 /* EH might have kicked in while host lock is
977 * released.
978 */
979 qc = ata_qc_from_tag(ap, qc->tag);
980 if (qc) {
981 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
982 ap->ops->irq_on(ap);
983 ata_qc_complete(qc);
984 } else
985 ata_port_freeze(ap);
986 }
987
988 spin_unlock_irqrestore(ap->lock, flags);
989 } else {
990 if (likely(!(qc->err_mask & AC_ERR_HSM)))
991 ata_qc_complete(qc);
992 else
993 ata_port_freeze(ap);
994 }
995 } else {
996 if (in_wq) {
997 spin_lock_irqsave(ap->lock, flags);
998 ap->ops->irq_on(ap);
999 ata_qc_complete(qc);
1000 spin_unlock_irqrestore(ap->lock, flags);
1001 } else
1002 ata_qc_complete(qc);
1003 }
1004}
1005
1006/**
1007 * ata_hsm_move - move the HSM to the next state.
1008 * @ap: the target ata_port
1009 * @qc: qc on going
1010 * @status: current device status
1011 * @in_wq: 1 if called from workqueue, 0 otherwise
1012 *
1013 * RETURNS:
1014 * 1 when poll next status needed, 0 otherwise.
1015 */
1016int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1017 u8 status, int in_wq)
1018{
1019 unsigned long flags = 0;
1020 int poll_next;
1021
1022 WARN_ON((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
1023
1024 /* Make sure ata_qc_issue_prot() does not throw things
1025 * like DMA polling into the workqueue. Notice that
1026 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1027 */
1028 WARN_ON(in_wq != ata_hsm_ok_in_wq(ap, qc));
1029
1030fsm_start:
1031 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1032 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1033
1034 switch (ap->hsm_task_state) {
1035 case HSM_ST_FIRST:
1036 /* Send first data block or PACKET CDB */
1037
1038 /* If polling, we will stay in the work queue after
1039 * sending the data. Otherwise, interrupt handler
1040 * takes over after sending the data.
1041 */
1042 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1043
1044 /* check device status */
1045 if (unlikely((status & ATA_DRQ) == 0)) {
1046 /* handle BSY=0, DRQ=0 as error */
1047 if (likely(status & (ATA_ERR | ATA_DF)))
1048 /* device stops HSM for abort/error */
1049 qc->err_mask |= AC_ERR_DEV;
1050 else
1051 /* HSM violation. Let EH handle this */
1052 qc->err_mask |= AC_ERR_HSM;
1053
1054 ap->hsm_task_state = HSM_ST_ERR;
1055 goto fsm_start;
1056 }
1057
1058 /* Device should not ask for data transfer (DRQ=1)
1059 * when it finds something wrong.
1060 * We ignore DRQ here and stop the HSM by
1061 * changing hsm_task_state to HSM_ST_ERR and
1062 * let the EH abort the command or reset the device.
1063 */
1064 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1065 /* Some ATAPI tape drives forget to clear the ERR bit
1066 * when doing the next command (mostly request sense).
1067 * We ignore ERR here to workaround and proceed sending
1068 * the CDB.
1069 */
1070 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1071 ata_port_printk(ap, KERN_WARNING,
1072 "DRQ=1 with device error, "
1073 "dev_stat 0x%X\n", status);
1074 qc->err_mask |= AC_ERR_HSM;
1075 ap->hsm_task_state = HSM_ST_ERR;
1076 goto fsm_start;
1077 }
1078 }
1079
1080 /* Send the CDB (atapi) or the first data block (ata pio out).
1081 * During the state transition, interrupt handler shouldn't
1082 * be invoked before the data transfer is complete and
1083 * hsm_task_state is changed. Hence, the following locking.
1084 */
1085 if (in_wq)
1086 spin_lock_irqsave(ap->lock, flags);
1087
1088 if (qc->tf.protocol == ATA_PROT_PIO) {
1089 /* PIO data out protocol.
1090 * send first data block.
1091 */
1092
1093 /* ata_pio_sectors() might change the state
1094 * to HSM_ST_LAST. so, the state is changed here
1095 * before ata_pio_sectors().
1096 */
1097 ap->hsm_task_state = HSM_ST;
1098 ata_pio_sectors(qc);
1099 } else
1100 /* send CDB */
1101 atapi_send_cdb(ap, qc);
1102
1103 if (in_wq)
1104 spin_unlock_irqrestore(ap->lock, flags);
1105
1106 /* if polling, ata_pio_task() handles the rest.
1107 * otherwise, interrupt handler takes over from here.
1108 */
1109 break;
1110
1111 case HSM_ST:
1112 /* complete command or read/write the data register */
1113 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1114 /* ATAPI PIO protocol */
1115 if ((status & ATA_DRQ) == 0) {
1116 /* No more data to transfer or device error.
1117 * Device error will be tagged in HSM_ST_LAST.
1118 */
1119 ap->hsm_task_state = HSM_ST_LAST;
1120 goto fsm_start;
1121 }
1122
1123 /* Device should not ask for data transfer (DRQ=1)
1124 * when it finds something wrong.
1125 * We ignore DRQ here and stop the HSM by
1126 * changing hsm_task_state to HSM_ST_ERR and
1127 * let the EH abort the command or reset the device.
1128 */
1129 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1130 ata_port_printk(ap, KERN_WARNING, "DRQ=1 with "
1131 "device error, dev_stat 0x%X\n",
1132 status);
1133 qc->err_mask |= AC_ERR_HSM;
1134 ap->hsm_task_state = HSM_ST_ERR;
1135 goto fsm_start;
1136 }
1137
1138 atapi_pio_bytes(qc);
1139
1140 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1141 /* bad ireason reported by device */
1142 goto fsm_start;
1143
1144 } else {
1145 /* ATA PIO protocol */
1146 if (unlikely((status & ATA_DRQ) == 0)) {
1147 /* handle BSY=0, DRQ=0 as error */
1148 if (likely(status & (ATA_ERR | ATA_DF)))
1149 /* device stops HSM for abort/error */
1150 qc->err_mask |= AC_ERR_DEV;
1151 else
1152 /* HSM violation. Let EH handle this.
1153 * Phantom devices also trigger this
1154 * condition. Mark hint.
1155 */
1156 qc->err_mask |= AC_ERR_HSM |
1157 AC_ERR_NODEV_HINT;
1158
1159 ap->hsm_task_state = HSM_ST_ERR;
1160 goto fsm_start;
1161 }
1162
1163 /* For PIO reads, some devices may ask for
1164 * data transfer (DRQ=1) alone with ERR=1.
1165 * We respect DRQ here and transfer one
1166 * block of junk data before changing the
1167 * hsm_task_state to HSM_ST_ERR.
1168 *
1169 * For PIO writes, ERR=1 DRQ=1 doesn't make
1170 * sense since the data block has been
1171 * transferred to the device.
1172 */
1173 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1174 /* data might be corrputed */
1175 qc->err_mask |= AC_ERR_DEV;
1176
1177 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1178 ata_pio_sectors(qc);
1179 status = ata_wait_idle(ap);
1180 }
1181
1182 if (status & (ATA_BUSY | ATA_DRQ))
1183 qc->err_mask |= AC_ERR_HSM;
1184
1185 /* ata_pio_sectors() might change the
1186 * state to HSM_ST_LAST. so, the state
1187 * is changed after ata_pio_sectors().
1188 */
1189 ap->hsm_task_state = HSM_ST_ERR;
1190 goto fsm_start;
1191 }
1192
1193 ata_pio_sectors(qc);
1194
1195 if (ap->hsm_task_state == HSM_ST_LAST &&
1196 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1197 /* all data read */
1198 status = ata_wait_idle(ap);
1199 goto fsm_start;
1200 }
1201 }
1202
1203 poll_next = 1;
1204 break;
1205
1206 case HSM_ST_LAST:
1207 if (unlikely(!ata_ok(status))) {
1208 qc->err_mask |= __ac_err_mask(status);
1209 ap->hsm_task_state = HSM_ST_ERR;
1210 goto fsm_start;
1211 }
1212
1213 /* no more data to transfer */
1214 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1215 ap->print_id, qc->dev->devno, status);
1216
1217 WARN_ON(qc->err_mask);
1218
1219 ap->hsm_task_state = HSM_ST_IDLE;
1220
1221 /* complete taskfile transaction */
1222 ata_hsm_qc_complete(qc, in_wq);
1223
1224 poll_next = 0;
1225 break;
1226
1227 case HSM_ST_ERR:
1228 /* make sure qc->err_mask is available to
1229 * know what's wrong and recover
1230 */
1231 WARN_ON(qc->err_mask == 0);
1232
1233 ap->hsm_task_state = HSM_ST_IDLE;
1234
1235 /* complete taskfile transaction */
1236 ata_hsm_qc_complete(qc, in_wq);
1237
1238 poll_next = 0;
1239 break;
1240 default:
1241 poll_next = 0;
1242 BUG();
1243 }
1244
1245 return poll_next;
1246}
1247
1248void ata_pio_task(struct work_struct *work)
1249{
1250 struct ata_port *ap =
1251 container_of(work, struct ata_port, port_task.work);
1252 struct ata_queued_cmd *qc = ap->port_task_data;
1253 u8 status;
1254 int poll_next;
1255
1256fsm_start:
1257 WARN_ON(ap->hsm_task_state == HSM_ST_IDLE);
1258
1259 /*
1260 * This is purely heuristic. This is a fast path.
1261 * Sometimes when we enter, BSY will be cleared in
1262 * a chk-status or two. If not, the drive is probably seeking
1263 * or something. Snooze for a couple msecs, then
1264 * chk-status again. If still busy, queue delayed work.
1265 */
1266 status = ata_busy_wait(ap, ATA_BUSY, 5);
1267 if (status & ATA_BUSY) {
1268 msleep(2);
1269 status = ata_busy_wait(ap, ATA_BUSY, 10);
1270 if (status & ATA_BUSY) {
1271 ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
1272 return;
1273 }
1274 }
1275
1276 /* move the HSM */
1277 poll_next = ata_hsm_move(ap, qc, status, 1);
1278
1279 /* another command or interrupt handler
1280 * may be running at this point.
1281 */
1282 if (poll_next)
1283 goto fsm_start;
1284}
1285
1286/**
1287 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
1288 * @qc: command to issue to device
1289 *
1290 * Using various libata functions and hooks, this function
1291 * starts an ATA command. ATA commands are grouped into
1292 * classes called "protocols", and issuing each type of protocol
1293 * is slightly different.
1294 *
1295 * May be used as the qc_issue() entry in ata_port_operations.
1296 *
1297 * LOCKING:
1298 * spin_lock_irqsave(host lock)
1299 *
1300 * RETURNS:
1301 * Zero on success, AC_ERR_* mask on failure
1302 */
1303unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
1304{
1305 struct ata_port *ap = qc->ap;
1306
1307 /* Use polling pio if the LLD doesn't handle
1308 * interrupt driven pio and atapi CDB interrupt.
1309 */
1310 if (ap->flags & ATA_FLAG_PIO_POLLING) {
1311 switch (qc->tf.protocol) {
1312 case ATA_PROT_PIO:
1313 case ATA_PROT_NODATA:
1314 case ATAPI_PROT_PIO:
1315 case ATAPI_PROT_NODATA:
1316 qc->tf.flags |= ATA_TFLAG_POLLING;
1317 break;
1318 case ATAPI_PROT_DMA:
1319 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1320 /* see ata_dma_blacklisted() */
1321 BUG();
1322 break;
1323 default:
1324 break;
1325 }
1326 }
1327
1328 /* select the device */
1329 ata_dev_select(ap, qc->dev->devno, 1, 0);
1330
1331 /* start the command */
1332 switch (qc->tf.protocol) {
1333 case ATA_PROT_NODATA:
1334 if (qc->tf.flags & ATA_TFLAG_POLLING)
1335 ata_qc_set_polling(qc);
1336
1337 ata_tf_to_host(ap, &qc->tf);
1338 ap->hsm_task_state = HSM_ST_LAST;
1339
1340 if (qc->tf.flags & ATA_TFLAG_POLLING)
1341 ata_pio_queue_task(ap, qc, 0);
1342
1343 break;
1344
1345 case ATA_PROT_DMA:
1346 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
1347
1348 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
1349 ap->ops->bmdma_setup(qc); /* set up bmdma */
1350 ap->ops->bmdma_start(qc); /* initiate bmdma */
1351 ap->hsm_task_state = HSM_ST_LAST;
1352 break;
1353
1354 case ATA_PROT_PIO:
1355 if (qc->tf.flags & ATA_TFLAG_POLLING)
1356 ata_qc_set_polling(qc);
1357
1358 ata_tf_to_host(ap, &qc->tf);
1359
1360 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1361 /* PIO data out protocol */
1362 ap->hsm_task_state = HSM_ST_FIRST;
1363 ata_pio_queue_task(ap, qc, 0);
1364
1365 /* always send first data block using
1366 * the ata_pio_task() codepath.
1367 */
1368 } else {
1369 /* PIO data in protocol */
1370 ap->hsm_task_state = HSM_ST;
1371
1372 if (qc->tf.flags & ATA_TFLAG_POLLING)
1373 ata_pio_queue_task(ap, qc, 0);
1374
1375 /* if polling, ata_pio_task() handles the rest.
1376 * otherwise, interrupt handler takes over from here.
1377 */
1378 }
1379
1380 break;
1381
1382 case ATAPI_PROT_PIO:
1383 case ATAPI_PROT_NODATA:
1384 if (qc->tf.flags & ATA_TFLAG_POLLING)
1385 ata_qc_set_polling(qc);
1386
1387 ata_tf_to_host(ap, &qc->tf);
1388
1389 ap->hsm_task_state = HSM_ST_FIRST;
1390
1391 /* send cdb by polling if no cdb interrupt */
1392 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1393 (qc->tf.flags & ATA_TFLAG_POLLING))
1394 ata_pio_queue_task(ap, qc, 0);
1395 break;
1396
1397 case ATAPI_PROT_DMA:
1398 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
1399
1400 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
1401 ap->ops->bmdma_setup(qc); /* set up bmdma */
1402 ap->hsm_task_state = HSM_ST_FIRST;
1403
1404 /* send cdb by polling if no cdb interrupt */
1405 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1406 ata_pio_queue_task(ap, qc, 0);
1407 break;
1408
1409 default:
1410 WARN_ON(1);
1411 return AC_ERR_SYSTEM;
1412 }
1413
1414 return 0;
1415}
1416
1417/**
1418 * ata_host_intr - Handle host interrupt for given (port, task)
1419 * @ap: Port on which interrupt arrived (possibly...)
1420 * @qc: Taskfile currently active in engine
1421 *
1422 * Handle host interrupt for given queued command. Currently,
1423 * only DMA interrupts are handled. All other commands are
1424 * handled via polling with interrupts disabled (nIEN bit).
1425 *
1426 * LOCKING:
1427 * spin_lock_irqsave(host lock)
1428 *
1429 * RETURNS:
1430 * One if interrupt was handled, zero if not (shared irq).
1431 */
1432inline unsigned int ata_host_intr(struct ata_port *ap,
1433 struct ata_queued_cmd *qc)
1434{
1435 struct ata_eh_info *ehi = &ap->link.eh_info;
1436 u8 status, host_stat = 0;
1437
1438 VPRINTK("ata%u: protocol %d task_state %d\n",
1439 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1440
1441 /* Check whether we are expecting interrupt in this state */
1442 switch (ap->hsm_task_state) {
1443 case HSM_ST_FIRST:
1444 /* Some pre-ATAPI-4 devices assert INTRQ
1445 * at this state when ready to receive CDB.
1446 */
1447
1448 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1449 * The flag was turned on only for atapi devices. No
1450 * need to check ata_is_atapi(qc->tf.protocol) again.
1451 */
1452 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1453 goto idle_irq;
1454 break;
1455 case HSM_ST_LAST:
1456 if (qc->tf.protocol == ATA_PROT_DMA ||
1457 qc->tf.protocol == ATAPI_PROT_DMA) {
1458 /* check status of DMA engine */
1459 host_stat = ap->ops->bmdma_status(ap);
1460 VPRINTK("ata%u: host_stat 0x%X\n",
1461 ap->print_id, host_stat);
1462
1463 /* if it's not our irq... */
1464 if (!(host_stat & ATA_DMA_INTR))
1465 goto idle_irq;
1466
1467 /* before we do anything else, clear DMA-Start bit */
1468 ap->ops->bmdma_stop(qc);
1469
1470 if (unlikely(host_stat & ATA_DMA_ERR)) {
1471 /* error when transfering data to/from memory */
1472 qc->err_mask |= AC_ERR_HOST_BUS;
1473 ap->hsm_task_state = HSM_ST_ERR;
1474 }
1475 }
1476 break;
1477 case HSM_ST:
1478 break;
1479 default:
1480 goto idle_irq;
1481 }
1482
1483 /* check altstatus */
1484 status = ata_altstatus(ap);
1485 if (status & ATA_BUSY)
1486 goto idle_irq;
1487
1488 /* check main status, clearing INTRQ */
1489 status = ata_chk_status(ap);
1490 if (unlikely(status & ATA_BUSY))
1491 goto idle_irq;
1492
1493 /* ack bmdma irq events */
1494 ap->ops->irq_clear(ap);
1495
1496 ata_hsm_move(ap, qc, status, 0);
1497
1498 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
1499 qc->tf.protocol == ATAPI_PROT_DMA))
1500 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
1501
1502 return 1; /* irq handled */
1503
1504idle_irq:
1505 ap->stats.idle_irq++;
1506
1507#ifdef ATA_IRQ_TRAP
1508 if ((ap->stats.idle_irq % 1000) == 0) {
1509 ata_chk_status(ap);
1510 ap->ops->irq_clear(ap);
1511 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
1512 return 1;
1513 }
1514#endif
1515 return 0; /* irq not handled */
1516}
1517
1518/**
1519 * ata_interrupt - Default ATA host interrupt handler
1520 * @irq: irq line (unused)
1521 * @dev_instance: pointer to our ata_host information structure
1522 *
1523 * Default interrupt handler for PCI IDE devices. Calls
1524 * ata_host_intr() for each port that is not disabled.
1525 *
1526 * LOCKING:
1527 * Obtains host lock during operation.
1528 *
1529 * RETURNS:
1530 * IRQ_NONE or IRQ_HANDLED.
1531 */
1532irqreturn_t ata_interrupt(int irq, void *dev_instance)
1533{
1534 struct ata_host *host = dev_instance;
1535 unsigned int i;
1536 unsigned int handled = 0;
1537 unsigned long flags;
1538
1539 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1540 spin_lock_irqsave(&host->lock, flags);
1541
1542 for (i = 0; i < host->n_ports; i++) {
1543 struct ata_port *ap;
1544
1545 ap = host->ports[i];
1546 if (ap &&
1547 !(ap->flags & ATA_FLAG_DISABLED)) {
1548 struct ata_queued_cmd *qc;
1549
1550 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1551 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
1552 (qc->flags & ATA_QCFLAG_ACTIVE))
1553 handled |= ata_host_intr(ap, qc);
1554 }
1555 }
1556
1557 spin_unlock_irqrestore(&host->lock, flags);
1558
1559 return IRQ_RETVAL(handled);
1560}
1561
1562/**
245 * ata_bmdma_freeze - Freeze BMDMA controller port 1563 * ata_bmdma_freeze - Freeze BMDMA controller port
246 * @ap: port to freeze 1564 * @ap: port to freeze
247 * 1565 *
@@ -287,6 +1605,387 @@ void ata_bmdma_thaw(struct ata_port *ap)
287} 1605}
288 1606
289/** 1607/**
1608 * ata_devchk - PATA device presence detection
1609 * @ap: ATA channel to examine
1610 * @device: Device to examine (starting at zero)
1611 *
1612 * This technique was originally described in
1613 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1614 * later found its way into the ATA/ATAPI spec.
1615 *
1616 * Write a pattern to the ATA shadow registers,
1617 * and if a device is present, it will respond by
1618 * correctly storing and echoing back the
1619 * ATA shadow register contents.
1620 *
1621 * LOCKING:
1622 * caller.
1623 */
1624static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
1625{
1626 struct ata_ioports *ioaddr = &ap->ioaddr;
1627 u8 nsect, lbal;
1628
1629 ap->ops->dev_select(ap, device);
1630
1631 iowrite8(0x55, ioaddr->nsect_addr);
1632 iowrite8(0xaa, ioaddr->lbal_addr);
1633
1634 iowrite8(0xaa, ioaddr->nsect_addr);
1635 iowrite8(0x55, ioaddr->lbal_addr);
1636
1637 iowrite8(0x55, ioaddr->nsect_addr);
1638 iowrite8(0xaa, ioaddr->lbal_addr);
1639
1640 nsect = ioread8(ioaddr->nsect_addr);
1641 lbal = ioread8(ioaddr->lbal_addr);
1642
1643 if ((nsect == 0x55) && (lbal == 0xaa))
1644 return 1; /* we found a device */
1645
1646 return 0; /* nothing found */
1647}
1648
1649/**
1650 * ata_dev_try_classify - Parse returned ATA device signature
1651 * @dev: ATA device to classify (starting at zero)
1652 * @present: device seems present
1653 * @r_err: Value of error register on completion
1654 *
1655 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1656 * an ATA/ATAPI-defined set of values is placed in the ATA
1657 * shadow registers, indicating the results of device detection
1658 * and diagnostics.
1659 *
1660 * Select the ATA device, and read the values from the ATA shadow
1661 * registers. Then parse according to the Error register value,
1662 * and the spec-defined values examined by ata_dev_classify().
1663 *
1664 * LOCKING:
1665 * caller.
1666 *
1667 * RETURNS:
1668 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1669 */
1670unsigned int ata_dev_try_classify(struct ata_device *dev, int present,
1671 u8 *r_err)
1672{
1673 struct ata_port *ap = dev->link->ap;
1674 struct ata_taskfile tf;
1675 unsigned int class;
1676 u8 err;
1677
1678 ap->ops->dev_select(ap, dev->devno);
1679
1680 memset(&tf, 0, sizeof(tf));
1681
1682 ap->ops->tf_read(ap, &tf);
1683 err = tf.feature;
1684 if (r_err)
1685 *r_err = err;
1686
1687 /* see if device passed diags: continue and warn later */
1688 if (err == 0)
1689 /* diagnostic fail : do nothing _YET_ */
1690 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1691 else if (err == 1)
1692 /* do nothing */ ;
1693 else if ((dev->devno == 0) && (err == 0x81))
1694 /* do nothing */ ;
1695 else
1696 return ATA_DEV_NONE;
1697
1698 /* determine if device is ATA or ATAPI */
1699 class = ata_dev_classify(&tf);
1700
1701 if (class == ATA_DEV_UNKNOWN) {
1702 /* If the device failed diagnostic, it's likely to
1703 * have reported incorrect device signature too.
1704 * Assume ATA device if the device seems present but
1705 * device signature is invalid with diagnostic
1706 * failure.
1707 */
1708 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1709 class = ATA_DEV_ATA;
1710 else
1711 class = ATA_DEV_NONE;
1712 } else if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0))
1713 class = ATA_DEV_NONE;
1714
1715 return class;
1716}
1717
1718static int ata_bus_post_reset(struct ata_port *ap, unsigned int devmask,
1719 unsigned long deadline)
1720{
1721 struct ata_ioports *ioaddr = &ap->ioaddr;
1722 unsigned int dev0 = devmask & (1 << 0);
1723 unsigned int dev1 = devmask & (1 << 1);
1724 int rc, ret = 0;
1725
1726 /* if device 0 was found in ata_devchk, wait for its
1727 * BSY bit to clear
1728 */
1729 if (dev0) {
1730 rc = ata_wait_ready(ap, deadline);
1731 if (rc) {
1732 if (rc != -ENODEV)
1733 return rc;
1734 ret = rc;
1735 }
1736 }
1737
1738 /* if device 1 was found in ata_devchk, wait for register
1739 * access briefly, then wait for BSY to clear.
1740 */
1741 if (dev1) {
1742 int i;
1743
1744 ap->ops->dev_select(ap, 1);
1745
1746 /* Wait for register access. Some ATAPI devices fail
1747 * to set nsect/lbal after reset, so don't waste too
1748 * much time on it. We're gonna wait for !BSY anyway.
1749 */
1750 for (i = 0; i < 2; i++) {
1751 u8 nsect, lbal;
1752
1753 nsect = ioread8(ioaddr->nsect_addr);
1754 lbal = ioread8(ioaddr->lbal_addr);
1755 if ((nsect == 1) && (lbal == 1))
1756 break;
1757 msleep(50); /* give drive a breather */
1758 }
1759
1760 rc = ata_wait_ready(ap, deadline);
1761 if (rc) {
1762 if (rc != -ENODEV)
1763 return rc;
1764 ret = rc;
1765 }
1766 }
1767
1768 /* is all this really necessary? */
1769 ap->ops->dev_select(ap, 0);
1770 if (dev1)
1771 ap->ops->dev_select(ap, 1);
1772 if (dev0)
1773 ap->ops->dev_select(ap, 0);
1774
1775 return ret;
1776}
1777
1778/**
1779 * ata_wait_after_reset - wait before checking status after reset
1780 * @ap: port containing status register to be polled
1781 * @deadline: deadline jiffies for the operation
1782 *
1783 * After reset, we need to pause a while before reading status.
1784 * Also, certain combination of controller and device report 0xff
1785 * for some duration (e.g. until SATA PHY is up and running)
1786 * which is interpreted as empty port in ATA world. This
1787 * function also waits for such devices to get out of 0xff
1788 * status.
1789 *
1790 * LOCKING:
1791 * Kernel thread context (may sleep).
1792 */
1793void ata_wait_after_reset(struct ata_port *ap, unsigned long deadline)
1794{
1795 unsigned long until = jiffies + ATA_TMOUT_FF_WAIT;
1796
1797 if (time_before(until, deadline))
1798 deadline = until;
1799
1800 /* Spec mandates ">= 2ms" before checking status. We wait
1801 * 150ms, because that was the magic delay used for ATAPI
1802 * devices in Hale Landis's ATADRVR, for the period of time
1803 * between when the ATA command register is written, and then
1804 * status is checked. Because waiting for "a while" before
1805 * checking status is fine, post SRST, we perform this magic
1806 * delay here as well.
1807 *
1808 * Old drivers/ide uses the 2mS rule and then waits for ready.
1809 */
1810 msleep(150);
1811
1812 /* Wait for 0xff to clear. Some SATA devices take a long time
1813 * to clear 0xff after reset. For example, HHD424020F7SV00
1814 * iVDR needs >= 800ms while. Quantum GoVault needs even more
1815 * than that.
1816 *
1817 * Note that some PATA controllers (pata_ali) explode if
1818 * status register is read more than once when there's no
1819 * device attached.
1820 */
1821 if (ap->flags & ATA_FLAG_SATA) {
1822 while (1) {
1823 u8 status = ata_chk_status(ap);
1824
1825 if (status != 0xff || time_after(jiffies, deadline))
1826 return;
1827
1828 msleep(50);
1829 }
1830 }
1831}
1832
1833static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
1834 unsigned long deadline)
1835{
1836 struct ata_ioports *ioaddr = &ap->ioaddr;
1837
1838 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
1839
1840 /* software reset. causes dev0 to be selected */
1841 iowrite8(ap->ctl, ioaddr->ctl_addr);
1842 udelay(20); /* FIXME: flush */
1843 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1844 udelay(20); /* FIXME: flush */
1845 iowrite8(ap->ctl, ioaddr->ctl_addr);
1846
1847 /* wait a while before checking status */
1848 ata_wait_after_reset(ap, deadline);
1849
1850 /* Before we perform post reset processing we want to see if
1851 * the bus shows 0xFF because the odd clown forgets the D7
1852 * pulldown resistor.
1853 */
1854 if (ata_chk_status(ap) == 0xFF)
1855 return -ENODEV;
1856
1857 return ata_bus_post_reset(ap, devmask, deadline);
1858}
1859
1860/**
1861 * ata_std_softreset - reset host port via ATA SRST
1862 * @link: ATA link to reset
1863 * @classes: resulting classes of attached devices
1864 * @deadline: deadline jiffies for the operation
1865 *
1866 * Reset host port using ATA SRST.
1867 *
1868 * LOCKING:
1869 * Kernel thread context (may sleep)
1870 *
1871 * RETURNS:
1872 * 0 on success, -errno otherwise.
1873 */
1874int ata_std_softreset(struct ata_link *link, unsigned int *classes,
1875 unsigned long deadline)
1876{
1877 struct ata_port *ap = link->ap;
1878 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1879 unsigned int devmask = 0;
1880 int rc;
1881 u8 err;
1882
1883 DPRINTK("ENTER\n");
1884
1885 if (ata_link_offline(link)) {
1886 classes[0] = ATA_DEV_NONE;
1887 goto out;
1888 }
1889
1890 /* determine if device 0/1 are present */
1891 if (ata_devchk(ap, 0))
1892 devmask |= (1 << 0);
1893 if (slave_possible && ata_devchk(ap, 1))
1894 devmask |= (1 << 1);
1895
1896 /* select device 0 again */
1897 ap->ops->dev_select(ap, 0);
1898
1899 /* issue bus reset */
1900 DPRINTK("about to softreset, devmask=%x\n", devmask);
1901 rc = ata_bus_softreset(ap, devmask, deadline);
1902 /* if link is occupied, -ENODEV too is an error */
1903 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
1904 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
1905 return rc;
1906 }
1907
1908 /* determine by signature whether we have ATA or ATAPI devices */
1909 classes[0] = ata_dev_try_classify(&link->device[0],
1910 devmask & (1 << 0), &err);
1911 if (slave_possible && err != 0x81)
1912 classes[1] = ata_dev_try_classify(&link->device[1],
1913 devmask & (1 << 1), &err);
1914
1915 out:
1916 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
1917 return 0;
1918}
1919
1920/**
1921 * sata_std_hardreset - reset host port via SATA phy reset
1922 * @link: link to reset
1923 * @class: resulting class of attached device
1924 * @deadline: deadline jiffies for the operation
1925 *
1926 * SATA phy-reset host port using DET bits of SControl register,
1927 * wait for !BSY and classify the attached device.
1928 *
1929 * LOCKING:
1930 * Kernel thread context (may sleep)
1931 *
1932 * RETURNS:
1933 * 0 on success, -errno otherwise.
1934 */
1935int sata_std_hardreset(struct ata_link *link, unsigned int *class,
1936 unsigned long deadline)
1937{
1938 struct ata_port *ap = link->ap;
1939 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1940 int rc;
1941
1942 DPRINTK("ENTER\n");
1943
1944 /* do hardreset */
1945 rc = sata_link_hardreset(link, timing, deadline);
1946 if (rc) {
1947 ata_link_printk(link, KERN_ERR,
1948 "COMRESET failed (errno=%d)\n", rc);
1949 return rc;
1950 }
1951
1952 /* TODO: phy layer with polling, timeouts, etc. */
1953 if (ata_link_offline(link)) {
1954 *class = ATA_DEV_NONE;
1955 DPRINTK("EXIT, link offline\n");
1956 return 0;
1957 }
1958
1959 /* wait a while before checking status */
1960 ata_wait_after_reset(ap, deadline);
1961
1962 /* If PMP is supported, we have to do follow-up SRST. Note
1963 * that some PMPs don't send D2H Reg FIS after hardreset at
1964 * all if the first port is empty. Wait for it just for a
1965 * second and request follow-up SRST.
1966 */
1967 if (ap->flags & ATA_FLAG_PMP) {
1968 ata_wait_ready(ap, jiffies + HZ);
1969 return -EAGAIN;
1970 }
1971
1972 rc = ata_wait_ready(ap, deadline);
1973 /* link occupied, -ENODEV too is an error */
1974 if (rc) {
1975 ata_link_printk(link, KERN_ERR,
1976 "COMRESET failed (errno=%d)\n", rc);
1977 return rc;
1978 }
1979
1980 ap->ops->dev_select(ap, 0); /* probably unnecessary */
1981
1982 *class = ata_dev_try_classify(link->device, 1, NULL);
1983
1984 DPRINTK("EXIT, class=%u\n", *class);
1985 return 0;
1986}
1987
1988/**
290 * ata_bmdma_error_handler - Stock error handler for BMDMA controller 1989 * ata_bmdma_error_handler - Stock error handler for BMDMA controller
291 * @ap: port to handle error for 1990 * @ap: port to handle error for
292 * 1991 *
@@ -394,6 +2093,31 @@ int ata_sff_port_start(struct ata_port *ap)
394} 2093}
395 2094
396/** 2095/**
2096 * ata_std_ports - initialize ioaddr with standard port offsets.
2097 * @ioaddr: IO address structure to be initialized
2098 *
2099 * Utility function which initializes data_addr, error_addr,
2100 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2101 * device_addr, status_addr, and command_addr to standard offsets
2102 * relative to cmd_addr.
2103 *
2104 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2105 */
2106void ata_std_ports(struct ata_ioports *ioaddr)
2107{
2108 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2109 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2110 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2111 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2112 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2113 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2114 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2115 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2116 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2117 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2118}
2119
2120/**
397 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction 2121 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
398 * @qc: Info associated with this ATA transaction. 2122 * @qc: Info associated with this ATA transaction.
399 * 2123 *
@@ -494,11 +2218,94 @@ u8 ata_bmdma_status(struct ata_port *ap)
494} 2218}
495 2219
496/** 2220/**
497 * ata_noop_irq_clear - Noop placeholder for irq_clear 2221 * ata_bus_reset - reset host port and associated ATA channel
498 * @ap: Port associated with this ATA transaction. 2222 * @ap: port to reset
2223 *
2224 * This is typically the first time we actually start issuing
2225 * commands to the ATA channel. We wait for BSY to clear, then
2226 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
2227 * result. Determine what devices, if any, are on the channel
2228 * by looking at the device 0/1 error register. Look at the signature
2229 * stored in each device's taskfile registers, to determine if
2230 * the device is ATA or ATAPI.
2231 *
2232 * LOCKING:
2233 * PCI/etc. bus probe sem.
2234 * Obtains host lock.
2235 *
2236 * SIDE EFFECTS:
2237 * Sets ATA_FLAG_DISABLED if bus reset fails.
2238 *
2239 * DEPRECATED:
2240 * This function is only for drivers which still use old EH and
2241 * will be removed soon.
499 */ 2242 */
500void ata_noop_irq_clear(struct ata_port *ap) 2243void ata_bus_reset(struct ata_port *ap)
501{ 2244{
2245 struct ata_device *device = ap->link.device;
2246 struct ata_ioports *ioaddr = &ap->ioaddr;
2247 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2248 u8 err;
2249 unsigned int dev0, dev1 = 0, devmask = 0;
2250 int rc;
2251
2252 DPRINTK("ENTER, host %u, port %u\n", ap->print_id, ap->port_no);
2253
2254 /* determine if device 0/1 are present */
2255 if (ap->flags & ATA_FLAG_SATA_RESET)
2256 dev0 = 1;
2257 else {
2258 dev0 = ata_devchk(ap, 0);
2259 if (slave_possible)
2260 dev1 = ata_devchk(ap, 1);
2261 }
2262
2263 if (dev0)
2264 devmask |= (1 << 0);
2265 if (dev1)
2266 devmask |= (1 << 1);
2267
2268 /* select device 0 again */
2269 ap->ops->dev_select(ap, 0);
2270
2271 /* issue bus reset */
2272 if (ap->flags & ATA_FLAG_SRST) {
2273 rc = ata_bus_softreset(ap, devmask, jiffies + 40 * HZ);
2274 if (rc && rc != -ENODEV)
2275 goto err_out;
2276 }
2277
2278 /*
2279 * determine by signature whether we have ATA or ATAPI devices
2280 */
2281 device[0].class = ata_dev_try_classify(&device[0], dev0, &err);
2282 if ((slave_possible) && (err != 0x81))
2283 device[1].class = ata_dev_try_classify(&device[1], dev1, &err);
2284
2285 /* is double-select really necessary? */
2286 if (device[1].class != ATA_DEV_NONE)
2287 ap->ops->dev_select(ap, 1);
2288 if (device[0].class != ATA_DEV_NONE)
2289 ap->ops->dev_select(ap, 0);
2290
2291 /* if no devices were detected, disable this port */
2292 if ((device[0].class == ATA_DEV_NONE) &&
2293 (device[1].class == ATA_DEV_NONE))
2294 goto err_out;
2295
2296 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2297 /* set up device control for ATA_FLAG_SATA_RESET */
2298 iowrite8(ap->ctl, ioaddr->ctl_addr);
2299 }
2300
2301 DPRINTK("EXIT\n");
2302 return;
2303
2304err_out:
2305 ata_port_printk(ap, KERN_ERR, "disabling port\n");
2306 ata_port_disable(ap);
2307
2308 DPRINTK("EXIT\n");
502} 2309}
503 2310
504#ifdef CONFIG_PCI 2311#ifdef CONFIG_PCI
@@ -914,3 +2721,49 @@ int ata_pci_init_one(struct pci_dev *pdev,
914 2721
915#endif /* CONFIG_PCI */ 2722#endif /* CONFIG_PCI */
916 2723
2724EXPORT_SYMBOL_GPL(ata_sff_port_ops);
2725EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
2726EXPORT_SYMBOL_GPL(ata_qc_prep);
2727EXPORT_SYMBOL_GPL(ata_dumb_qc_prep);
2728EXPORT_SYMBOL_GPL(ata_std_dev_select);
2729EXPORT_SYMBOL_GPL(ata_check_status);
2730EXPORT_SYMBOL_GPL(ata_altstatus);
2731EXPORT_SYMBOL_GPL(ata_busy_sleep);
2732EXPORT_SYMBOL_GPL(ata_wait_ready);
2733EXPORT_SYMBOL_GPL(ata_tf_load);
2734EXPORT_SYMBOL_GPL(ata_tf_read);
2735EXPORT_SYMBOL_GPL(ata_exec_command);
2736EXPORT_SYMBOL_GPL(ata_data_xfer);
2737EXPORT_SYMBOL_GPL(ata_data_xfer_noirq);
2738EXPORT_SYMBOL_GPL(ata_irq_on);
2739EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
2740EXPORT_SYMBOL_GPL(ata_hsm_move);
2741EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
2742EXPORT_SYMBOL_GPL(ata_host_intr);
2743EXPORT_SYMBOL_GPL(ata_interrupt);
2744EXPORT_SYMBOL_GPL(ata_bmdma_freeze);
2745EXPORT_SYMBOL_GPL(ata_bmdma_thaw);
2746EXPORT_SYMBOL_GPL(ata_std_prereset);
2747EXPORT_SYMBOL_GPL(ata_dev_try_classify);
2748EXPORT_SYMBOL_GPL(ata_wait_after_reset);
2749EXPORT_SYMBOL_GPL(ata_std_softreset);
2750EXPORT_SYMBOL_GPL(sata_std_hardreset);
2751EXPORT_SYMBOL_GPL(ata_std_postreset);
2752EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
2753EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
2754EXPORT_SYMBOL_GPL(ata_sff_port_start);
2755EXPORT_SYMBOL_GPL(ata_std_ports);
2756EXPORT_SYMBOL_GPL(ata_bmdma_setup);
2757EXPORT_SYMBOL_GPL(ata_bmdma_start);
2758EXPORT_SYMBOL_GPL(ata_bmdma_stop);
2759EXPORT_SYMBOL_GPL(ata_bmdma_status);
2760EXPORT_SYMBOL_GPL(ata_bus_reset);
2761#ifdef CONFIG_PCI
2762EXPORT_SYMBOL_GPL(ata_pci_clear_simplex);
2763EXPORT_SYMBOL_GPL(ata_pci_default_filter);
2764EXPORT_SYMBOL_GPL(ata_pci_init_bmdma);
2765EXPORT_SYMBOL_GPL(ata_pci_init_sff_host);
2766EXPORT_SYMBOL_GPL(ata_pci_prepare_sff_host);
2767EXPORT_SYMBOL_GPL(ata_pci_activate_sff_host);
2768EXPORT_SYMBOL_GPL(ata_pci_init_one);
2769#endif /* CONFIG_PCI */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 23:08:04 -0500