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path: root/drivers/ata/ata_piix.c
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Diffstat (limited to 'drivers/ata/ata_piix.c')
-rw-r--r--drivers/ata/ata_piix.c41
1 files changed, 38 insertions, 3 deletions
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
index ea2c7649d399..a90ae03f56b2 100644
--- a/drivers/ata/ata_piix.c
+++ b/drivers/ata/ata_piix.c
@@ -247,10 +247,11 @@ static const struct pci_device_id piix_pci_tbl[] = {
247 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 247 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
248 /* SATA Controller 2 IDE (ICH8) */ 248 /* SATA Controller 2 IDE (ICH8) */
249 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 249 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
250 /* Mobile SATA Controller IDE (ICH8M) */
251 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
252 /* Mobile SATA Controller IDE (ICH8M), Apple */ 250 /* Mobile SATA Controller IDE (ICH8M), Apple */
253 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata }, 251 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
252 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
253 /* Mobile SATA Controller IDE (ICH8M) */
254 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
254 /* SATA Controller IDE (ICH9) */ 255 /* SATA Controller IDE (ICH9) */
255 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 256 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
256 /* SATA Controller IDE (ICH9) */ 257 /* SATA Controller IDE (ICH9) */
@@ -526,7 +527,7 @@ static struct ata_port_info piix_port_info[] = {
526 527
527 [ich8m_apple_sata] = 528 [ich8m_apple_sata] =
528 { 529 {
529 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 530 .flags = PIIX_SATA_FLAGS,
530 .pio_mask = 0x1f, /* pio0-4 */ 531 .pio_mask = 0x1f, /* pio0-4 */
531 .mwdma_mask = 0x07, /* mwdma0-2 */ 532 .mwdma_mask = 0x07, /* mwdma0-2 */
532 .udma_mask = ATA_UDMA6, 533 .udma_mask = ATA_UDMA6,
@@ -573,6 +574,8 @@ static const struct ich_laptop ich_laptop[] = {
573 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ 574 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
574 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ 575 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
575 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ 576 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
577 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
578 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
576 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */ 579 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
577 /* end marker */ 580 /* end marker */
578 { 0, } 581 { 0, }
@@ -1040,6 +1043,13 @@ static int piix_broken_suspend(void)
1040 }, 1043 },
1041 }, 1044 },
1042 { 1045 {
1046 .ident = "TECRA M4",
1047 .matches = {
1048 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1049 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
1050 },
1051 },
1052 {
1043 .ident = "TECRA M5", 1053 .ident = "TECRA M5",
1044 .matches = { 1054 .matches = {
1045 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1055 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
@@ -1348,6 +1358,8 @@ static void __devinit piix_init_sidpr(struct ata_host *host)
1348{ 1358{
1349 struct pci_dev *pdev = to_pci_dev(host->dev); 1359 struct pci_dev *pdev = to_pci_dev(host->dev);
1350 struct piix_host_priv *hpriv = host->private_data; 1360 struct piix_host_priv *hpriv = host->private_data;
1361 struct ata_device *dev0 = &host->ports[0]->link.device[0];
1362 u32 scontrol;
1351 int i; 1363 int i;
1352 1364
1353 /* check for availability */ 1365 /* check for availability */
@@ -1366,6 +1378,29 @@ static void __devinit piix_init_sidpr(struct ata_host *host)
1366 return; 1378 return;
1367 1379
1368 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR]; 1380 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1381
1382 /* SCR access via SIDPR doesn't work on some configurations.
1383 * Give it a test drive by inhibiting power save modes which
1384 * we'll do anyway.
1385 */
1386 scontrol = piix_sidpr_read(dev0, SCR_CONTROL);
1387
1388 /* if IPM is already 3, SCR access is probably working. Don't
1389 * un-inhibit power save modes as BIOS might have inhibited
1390 * them for a reason.
1391 */
1392 if ((scontrol & 0xf00) != 0x300) {
1393 scontrol |= 0x300;
1394 piix_sidpr_write(dev0, SCR_CONTROL, scontrol);
1395 scontrol = piix_sidpr_read(dev0, SCR_CONTROL);
1396
1397 if ((scontrol & 0xf00) != 0x300) {
1398 dev_printk(KERN_INFO, host->dev, "SCR access via "
1399 "SIDPR is available but doesn't work\n");
1400 return;
1401 }
1402 }
1403
1369 host->ports[0]->ops = &piix_sidpr_sata_ops; 1404 host->ports[0]->ops = &piix_sidpr_sata_ops;
1370 host->ports[1]->ops = &piix_sidpr_sata_ops; 1405 host->ports[1]->ops = &piix_sidpr_sata_ops;
1371} 1406}