1 files changed, 157 insertions, 85 deletions

diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c
index 3e23e9941dad..dd4d6f74d7bd 100644
--- a/drivers/ata/ahci_imx.c
+++ b/drivers/ata/ahci_imx.c
@@ -34,10 +34,21 @@ enum {
         HOST_TIMER1MS = 0xe0,                   /* Timer 1-ms */
 };
 
+enum ahci_imx_type {
+        AHCI_IMX53,
+        AHCI_IMX6Q,
+};
+
 struct imx_ahci_priv {
         struct platform_device *ahci_pdev;
+        enum ahci_imx_type type;
+
+        /* i.MX53 clock */
+        struct clk *sata_gate_clk;
+        /* Common clock */
         struct clk *sata_ref_clk;
         struct clk *ahb_clk;
+
         struct regmap *gpr;
         bool no_device;
         bool first_time;
@@ -47,6 +58,59 @@ static int ahci_imx_hotplug;
 module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
 MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
 
+static int imx_sata_clock_enable(struct device *dev)
+{
+        struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
+        int ret;
+
+        if (imxpriv->type == AHCI_IMX53) {
+                ret = clk_prepare_enable(imxpriv->sata_gate_clk);
+                if (ret < 0) {
+                        dev_err(dev, "prepare-enable sata_gate clock err:%d\n",
+                                ret);
+                        return ret;
+                }
+        }
+
+        ret = clk_prepare_enable(imxpriv->sata_ref_clk);
+        if (ret < 0) {
+                dev_err(dev, "prepare-enable sata_ref clock err:%d\n",
+                        ret);
+                goto clk_err;
+        }
+
+        if (imxpriv->type == AHCI_IMX6Q) {
+                regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
+                                   IMX6Q_GPR13_SATA_MPLL_CLK_EN,
+                                   IMX6Q_GPR13_SATA_MPLL_CLK_EN);
+        }
+
+        usleep_range(1000, 2000);
+
+        return 0;
+
+clk_err:
+        if (imxpriv->type == AHCI_IMX53)
+                clk_disable_unprepare(imxpriv->sata_gate_clk);
+        return ret;
+}
+
+static void imx_sata_clock_disable(struct device *dev)
+{
+        struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
+
+        if (imxpriv->type == AHCI_IMX6Q) {
+                regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
+                                   IMX6Q_GPR13_SATA_MPLL_CLK_EN,
+                                   !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
+        }
+
+        clk_disable_unprepare(imxpriv->sata_ref_clk);
+
+        if (imxpriv->type == AHCI_IMX53)
+                clk_disable_unprepare(imxpriv->sata_gate_clk);
+}
+
 static void ahci_imx_error_handler(struct ata_port *ap)
 {
         u32 reg_val;
@@ -72,16 +136,29 @@ static void ahci_imx_error_handler(struct ata_port *ap)
          */
         reg_val = readl(mmio + PORT_PHY_CTL);
         writel(reg_val | PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL);
-        regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
-                        IMX6Q_GPR13_SATA_MPLL_CLK_EN,
-                        !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
-        clk_disable_unprepare(imxpriv->sata_ref_clk);
+        imx_sata_clock_disable(ap->dev);
         imxpriv->no_device = true;
 }
 
+static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
+                       unsigned long deadline)
+{
+        struct ata_port *ap = link->ap;
+        struct imx_ahci_priv *imxpriv = dev_get_drvdata(ap->dev->parent);
+        int ret = -EIO;
+
+        if (imxpriv->type == AHCI_IMX53)
+                ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
+        else if (imxpriv->type == AHCI_IMX6Q)
+                ret = ahci_ops.softreset(link, class, deadline);
+
+        return ret;
+}
+
 static struct ata_port_operations ahci_imx_ops = {
         .inherits       = &ahci_platform_ops,
         .error_handler  = ahci_imx_error_handler,
+        .softreset      = ahci_imx_softreset,
 };
 
 static const struct ata_port_info ahci_imx_port_info = {
@@ -91,52 +168,15 @@ static const struct ata_port_info ahci_imx_port_info = {
         .port_ops       = &ahci_imx_ops,
 };
 
-static int imx6q_sata_init(struct device *dev, void __iomem *mmio)
+static int imx_sata_init(struct device *dev, void __iomem *mmio)
 {
         int ret = 0;
         unsigned int reg_val;
         struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
 
-        imxpriv->gpr =
-                syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
-        if (IS_ERR(imxpriv->gpr)) {
-                dev_err(dev, "failed to find fsl,imx6q-iomux-gpr regmap\n");
-                return PTR_ERR(imxpriv->gpr);
-        }
-
-        ret = clk_prepare_enable(imxpriv->sata_ref_clk);
-        if (ret < 0) {
-                dev_err(dev, "prepare-enable sata_ref clock err:%d\n", ret);
+        ret = imx_sata_clock_enable(dev);
+        if (ret < 0)
                 return ret;
-        }
-
-        /*
-         * set PHY Paremeters, two steps to configure the GPR13,
-         * one write for rest of parameters, mask of first write
-         * is 0x07ffffff, and the other one write for setting
-         * the mpll_clk_en.
-         */
-        regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK
-                        | IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK
-                        | IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK
-                        | IMX6Q_GPR13_SATA_SPD_MODE_MASK
-                        | IMX6Q_GPR13_SATA_MPLL_SS_EN
-                        | IMX6Q_GPR13_SATA_TX_ATTEN_MASK
-                        | IMX6Q_GPR13_SATA_TX_BOOST_MASK
-                        | IMX6Q_GPR13_SATA_TX_LVL_MASK
-                        | IMX6Q_GPR13_SATA_MPLL_CLK_EN
-                        | IMX6Q_GPR13_SATA_TX_EDGE_RATE
-                        , IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB
-                        | IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M
-                        | IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F
-                        | IMX6Q_GPR13_SATA_SPD_MODE_3P0G
-                        | IMX6Q_GPR13_SATA_MPLL_SS_EN
-                        | IMX6Q_GPR13_SATA_TX_ATTEN_9_16
-                        | IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB
-                        | IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
-        regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
-                        IMX6Q_GPR13_SATA_MPLL_CLK_EN);
-        usleep_range(100, 200);
 
         /*
          * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
@@ -162,13 +202,9 @@ static int imx6q_sata_init(struct device *dev, void __iomem *mmio)
         return 0;
 }
 
-static void imx6q_sata_exit(struct device *dev)
+static void imx_sata_exit(struct device *dev)
 {
-        struct imx_ahci_priv *imxpriv =  dev_get_drvdata(dev->parent);
-
-        regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
-                        !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
-        clk_disable_unprepare(imxpriv->sata_ref_clk);
+        imx_sata_clock_disable(dev);
 }
 
 static int imx_ahci_suspend(struct device *dev)
@@ -179,12 +215,8 @@ static int imx_ahci_suspend(struct device *dev)
          * If no_device is set, The CLKs had been gated off in the
          * initialization so don't do it again here.
          */
-        if (!imxpriv->no_device) {
-                regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
-                                IMX6Q_GPR13_SATA_MPLL_CLK_EN,
-                                !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
-                clk_disable_unprepare(imxpriv->sata_ref_clk);
-        }
+        if (!imxpriv->no_device)
+                imx_sata_clock_disable(dev);
 
         return 0;
 }
@@ -192,34 +224,26 @@ static int imx_ahci_suspend(struct device *dev)
 static int imx_ahci_resume(struct device *dev)
 {
         struct imx_ahci_priv *imxpriv =  dev_get_drvdata(dev->parent);
-        int ret;
-
-        if (!imxpriv->no_device) {
-                ret = clk_prepare_enable(imxpriv->sata_ref_clk);
-                if (ret < 0) {
-                        dev_err(dev, "pre-enable sata_ref clock err:%d\n", ret);
-                        return ret;
-                }
+        int ret = 0;
 
-                regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
-                                IMX6Q_GPR13_SATA_MPLL_CLK_EN,
-                                IMX6Q_GPR13_SATA_MPLL_CLK_EN);
-                usleep_range(1000, 2000);
-        }
+        if (!imxpriv->no_device)
+                ret = imx_sata_clock_enable(dev);
 
-        return 0;
+        return ret;
 }
 
-static struct ahci_platform_data imx6q_sata_pdata = {
-        .init = imx6q_sata_init,
-        .exit = imx6q_sata_exit,
-        .ata_port_info = &ahci_imx_port_info,
-        .suspend = imx_ahci_suspend,
-        .resume = imx_ahci_resume,
+static struct ahci_platform_data imx_sata_pdata = {
+        .init           = imx_sata_init,
+        .exit           = imx_sata_exit,
+        .ata_port_info  = &ahci_imx_port_info,
+        .suspend        = imx_ahci_suspend,
+        .resume         = imx_ahci_resume,
+
 };
 
 static const struct of_device_id imx_ahci_of_match[] = {
-        { .compatible = "fsl,imx6q-ahci", .data = &imx6q_sata_pdata},
+        { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
+        { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
         {},
 };
 MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
@@ -229,12 +253,20 @@ static int imx_ahci_probe(struct platform_device *pdev)
         struct device *dev = &pdev->dev;
         struct resource *mem, *irq, res[2];
         const struct of_device_id *of_id;
+        enum ahci_imx_type type;
         const struct ahci_platform_data *pdata = NULL;
         struct imx_ahci_priv *imxpriv;
         struct device *ahci_dev;
         struct platform_device *ahci_pdev;
         int ret;
 
+        of_id = of_match_device(imx_ahci_of_match, dev);
+        if (!of_id)
+                return -EINVAL;
+
+        type = (enum ahci_imx_type)of_id->data;
+        pdata = &imx_sata_pdata;
+
         imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
         if (!imxpriv) {
                 dev_err(dev, "can't alloc ahci_host_priv\n");
@@ -250,6 +282,8 @@ static int imx_ahci_probe(struct platform_device *pdev)
 
         imxpriv->no_device = false;
         imxpriv->first_time = true;
+        imxpriv->type = type;
+
         imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
         if (IS_ERR(imxpriv->ahb_clk)) {
                 dev_err(dev, "can't get ahb clock.\n");
@@ -257,6 +291,15 @@ static int imx_ahci_probe(struct platform_device *pdev)
                 goto err_out;
         }
 
+        if (type == AHCI_IMX53) {
+                imxpriv->sata_gate_clk = devm_clk_get(dev, "sata_gate");
+                if (IS_ERR(imxpriv->sata_gate_clk)) {
+                        dev_err(dev, "can't get sata_gate clock.\n");
+                        ret = PTR_ERR(imxpriv->sata_gate_clk);
+                        goto err_out;
+                }
+        }
+
         imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
         if (IS_ERR(imxpriv->sata_ref_clk)) {
                 dev_err(dev, "can't get sata_ref clock.\n");
@@ -267,14 +310,6 @@ static int imx_ahci_probe(struct platform_device *pdev)
         imxpriv->ahci_pdev = ahci_pdev;
         platform_set_drvdata(pdev, imxpriv);
 
-        of_id = of_match_device(imx_ahci_of_match, dev);
-        if (of_id) {
-                pdata = of_id->data;
-        } else {
-                ret = -EINVAL;
-                goto err_out;
-        }
-
         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
         if (!mem || !irq) {
@@ -290,6 +325,43 @@ static int imx_ahci_probe(struct platform_device *pdev)
         ahci_dev->dma_mask = &ahci_dev->coherent_dma_mask;
         ahci_dev->of_node = dev->of_node;
 
+        if (type == AHCI_IMX6Q) {
+                imxpriv->gpr = syscon_regmap_lookup_by_compatible(
+                                                        "fsl,imx6q-iomuxc-gpr");
+                if (IS_ERR(imxpriv->gpr)) {
+                        dev_err(dev,
+                                "failed to find fsl,imx6q-iomux-gpr regmap\n");
+                        ret = PTR_ERR(imxpriv->gpr);
+                        goto err_out;
+                }
+
+                /*
+                 * Set PHY Paremeters, two steps to configure the GPR13,
+                 * one write for rest of parameters, mask of first write
+                 * is 0x07fffffe, and the other one write for setting
+                 * the mpll_clk_en happens in imx_sata_clock_enable().
+                 */
+                regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
+                                   IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
+                                   IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
+                                   IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
+                                   IMX6Q_GPR13_SATA_SPD_MODE_MASK |
+                                   IMX6Q_GPR13_SATA_MPLL_SS_EN |
+                                   IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
+                                   IMX6Q_GPR13_SATA_TX_BOOST_MASK |
+                                   IMX6Q_GPR13_SATA_TX_LVL_MASK |
+                                   IMX6Q_GPR13_SATA_MPLL_CLK_EN |
+                                   IMX6Q_GPR13_SATA_TX_EDGE_RATE,
+                                   IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB |
+                                   IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
+                                   IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
+                                   IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
+                                   IMX6Q_GPR13_SATA_MPLL_SS_EN |
+                                   IMX6Q_GPR13_SATA_TX_ATTEN_9_16 |
+                                   IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB |
+                                   IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
+        }
+
         ret = platform_device_add_resources(ahci_pdev, res, 2);
         if (ret)
                 goto err_out;