diff options
Diffstat (limited to 'drivers/ata/ahci.c')
| -rw-r--r-- | drivers/ata/ahci.c | 473 |
1 files changed, 228 insertions, 245 deletions
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index fd27227771b4..34c5534ed64c 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c | |||
| @@ -170,6 +170,10 @@ enum { | |||
| 170 | AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */ | 170 | AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */ |
| 171 | AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */ | 171 | AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */ |
| 172 | AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */ | 172 | AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */ |
| 173 | |||
| 174 | AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | ||
| 175 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | ||
| 176 | ATA_FLAG_SKIP_D2H_BSY, | ||
| 173 | }; | 177 | }; |
| 174 | 178 | ||
| 175 | struct ahci_cmd_hdr { | 179 | struct ahci_cmd_hdr { |
| @@ -188,8 +192,10 @@ struct ahci_sg { | |||
| 188 | }; | 192 | }; |
| 189 | 193 | ||
| 190 | struct ahci_host_priv { | 194 | struct ahci_host_priv { |
| 191 | u32 cap; /* cache of HOST_CAP register */ | 195 | u32 cap; /* cap to use */ |
| 192 | u32 port_map; /* cache of HOST_PORTS_IMPL reg */ | 196 | u32 port_map; /* port map to use */ |
| 197 | u32 saved_cap; /* saved initial cap */ | ||
| 198 | u32 saved_port_map; /* saved initial port_map */ | ||
| 193 | }; | 199 | }; |
| 194 | 200 | ||
| 195 | struct ahci_port_priv { | 201 | struct ahci_port_priv { |
| @@ -209,7 +215,6 @@ static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg); | |||
| 209 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | 215 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); |
| 210 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | 216 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); |
| 211 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); | 217 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
| 212 | static irqreturn_t ahci_interrupt (int irq, void *dev_instance); | ||
| 213 | static void ahci_irq_clear(struct ata_port *ap); | 218 | static void ahci_irq_clear(struct ata_port *ap); |
| 214 | static int ahci_port_start(struct ata_port *ap); | 219 | static int ahci_port_start(struct ata_port *ap); |
| 215 | static void ahci_port_stop(struct ata_port *ap); | 220 | static void ahci_port_stop(struct ata_port *ap); |
| @@ -263,7 +268,6 @@ static const struct ata_port_operations ahci_ops = { | |||
| 263 | .qc_prep = ahci_qc_prep, | 268 | .qc_prep = ahci_qc_prep, |
| 264 | .qc_issue = ahci_qc_issue, | 269 | .qc_issue = ahci_qc_issue, |
| 265 | 270 | ||
| 266 | .irq_handler = ahci_interrupt, | ||
| 267 | .irq_clear = ahci_irq_clear, | 271 | .irq_clear = ahci_irq_clear, |
| 268 | .irq_on = ata_dummy_irq_on, | 272 | .irq_on = ata_dummy_irq_on, |
| 269 | .irq_ack = ata_dummy_irq_ack, | 273 | .irq_ack = ata_dummy_irq_ack, |
| @@ -298,7 +302,6 @@ static const struct ata_port_operations ahci_vt8251_ops = { | |||
| 298 | .qc_prep = ahci_qc_prep, | 302 | .qc_prep = ahci_qc_prep, |
| 299 | .qc_issue = ahci_qc_issue, | 303 | .qc_issue = ahci_qc_issue, |
| 300 | 304 | ||
| 301 | .irq_handler = ahci_interrupt, | ||
| 302 | .irq_clear = ahci_irq_clear, | 305 | .irq_clear = ahci_irq_clear, |
| 303 | .irq_on = ata_dummy_irq_on, | 306 | .irq_on = ata_dummy_irq_on, |
| 304 | .irq_ack = ata_dummy_irq_ack, | 307 | .irq_ack = ata_dummy_irq_ack, |
| @@ -324,58 +327,41 @@ static const struct ata_port_operations ahci_vt8251_ops = { | |||
| 324 | static const struct ata_port_info ahci_port_info[] = { | 327 | static const struct ata_port_info ahci_port_info[] = { |
| 325 | /* board_ahci */ | 328 | /* board_ahci */ |
| 326 | { | 329 | { |
| 327 | .sht = &ahci_sht, | 330 | .flags = AHCI_FLAG_COMMON, |
| 328 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | ||
| 329 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | ||
| 330 | ATA_FLAG_SKIP_D2H_BSY, | ||
| 331 | .pio_mask = 0x1f, /* pio0-4 */ | 331 | .pio_mask = 0x1f, /* pio0-4 */ |
| 332 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | 332 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
| 333 | .port_ops = &ahci_ops, | 333 | .port_ops = &ahci_ops, |
| 334 | }, | 334 | }, |
| 335 | /* board_ahci_pi */ | 335 | /* board_ahci_pi */ |
| 336 | { | 336 | { |
| 337 | .sht = &ahci_sht, | 337 | .flags = AHCI_FLAG_COMMON | AHCI_FLAG_HONOR_PI, |
| 338 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | ||
| 339 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | ||
| 340 | ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI, | ||
| 341 | .pio_mask = 0x1f, /* pio0-4 */ | 338 | .pio_mask = 0x1f, /* pio0-4 */ |
| 342 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | 339 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
| 343 | .port_ops = &ahci_ops, | 340 | .port_ops = &ahci_ops, |
| 344 | }, | 341 | }, |
| 345 | /* board_ahci_vt8251 */ | 342 | /* board_ahci_vt8251 */ |
| 346 | { | 343 | { |
| 347 | .sht = &ahci_sht, | 344 | .flags = AHCI_FLAG_COMMON | ATA_FLAG_HRST_TO_RESUME | |
| 348 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | 345 | AHCI_FLAG_NO_NCQ, |
| 349 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | ||
| 350 | ATA_FLAG_SKIP_D2H_BSY | | ||
| 351 | ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ, | ||
| 352 | .pio_mask = 0x1f, /* pio0-4 */ | 346 | .pio_mask = 0x1f, /* pio0-4 */ |
| 353 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | 347 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
| 354 | .port_ops = &ahci_vt8251_ops, | 348 | .port_ops = &ahci_vt8251_ops, |
| 355 | }, | 349 | }, |
| 356 | /* board_ahci_ign_iferr */ | 350 | /* board_ahci_ign_iferr */ |
| 357 | { | 351 | { |
| 358 | .sht = &ahci_sht, | 352 | .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR, |
| 359 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | ||
| 360 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | ||
| 361 | ATA_FLAG_SKIP_D2H_BSY | | ||
| 362 | AHCI_FLAG_IGN_IRQ_IF_ERR, | ||
| 363 | .pio_mask = 0x1f, /* pio0-4 */ | 353 | .pio_mask = 0x1f, /* pio0-4 */ |
| 364 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | 354 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
| 365 | .port_ops = &ahci_ops, | 355 | .port_ops = &ahci_ops, |
| 366 | }, | 356 | }, |
| 367 | /* board_ahci_sb600 */ | 357 | /* board_ahci_sb600 */ |
| 368 | { | 358 | { |
| 369 | .sht = &ahci_sht, | 359 | .flags = AHCI_FLAG_COMMON | |
| 370 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | ||
| 371 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | ||
| 372 | ATA_FLAG_SKIP_D2H_BSY | | ||
| 373 | AHCI_FLAG_IGN_SERR_INTERNAL, | 360 | AHCI_FLAG_IGN_SERR_INTERNAL, |
| 374 | .pio_mask = 0x1f, /* pio0-4 */ | 361 | .pio_mask = 0x1f, /* pio0-4 */ |
| 375 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | 362 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
| 376 | .port_ops = &ahci_ops, | 363 | .port_ops = &ahci_ops, |
| 377 | }, | 364 | }, |
| 378 | |||
| 379 | }; | 365 | }; |
| 380 | 366 | ||
| 381 | static const struct pci_device_id ahci_pci_tbl[] = { | 367 | static const struct pci_device_id ahci_pci_tbl[] = { |
| @@ -413,11 +399,11 @@ static const struct pci_device_id ahci_pci_tbl[] = { | |||
| 413 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, | 399 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, |
| 414 | 400 | ||
| 415 | /* ATI */ | 401 | /* ATI */ |
| 416 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 non-raid */ | 402 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
| 417 | { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */ | ||
| 418 | 403 | ||
| 419 | /* VIA */ | 404 | /* VIA */ |
| 420 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ | 405 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
| 406 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ | ||
| 421 | 407 | ||
| 422 | /* NVIDIA */ | 408 | /* NVIDIA */ |
| 423 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ | 409 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ |
| @@ -471,10 +457,100 @@ static inline int ahci_nr_ports(u32 cap) | |||
| 471 | return (cap & 0x1f) + 1; | 457 | return (cap & 0x1f) + 1; |
| 472 | } | 458 | } |
| 473 | 459 | ||
| 474 | static inline void __iomem *ahci_port_base(void __iomem *base, | 460 | static inline void __iomem *ahci_port_base(struct ata_port *ap) |
| 475 | unsigned int port) | 461 | { |
| 462 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; | ||
| 463 | |||
| 464 | return mmio + 0x100 + (ap->port_no * 0x80); | ||
| 465 | } | ||
| 466 | |||
| 467 | /** | ||
| 468 | * ahci_save_initial_config - Save and fixup initial config values | ||
| 469 | * @pdev: target PCI device | ||
| 470 | * @pi: associated ATA port info | ||
| 471 | * @hpriv: host private area to store config values | ||
| 472 | * | ||
| 473 | * Some registers containing configuration info might be setup by | ||
| 474 | * BIOS and might be cleared on reset. This function saves the | ||
| 475 | * initial values of those registers into @hpriv such that they | ||
| 476 | * can be restored after controller reset. | ||
| 477 | * | ||
| 478 | * If inconsistent, config values are fixed up by this function. | ||
| 479 | * | ||
| 480 | * LOCKING: | ||
| 481 | * None. | ||
| 482 | */ | ||
| 483 | static void ahci_save_initial_config(struct pci_dev *pdev, | ||
| 484 | const struct ata_port_info *pi, | ||
| 485 | struct ahci_host_priv *hpriv) | ||
| 476 | { | 486 | { |
| 477 | return base + 0x100 + (port * 0x80); | 487 | void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; |
| 488 | u32 cap, port_map; | ||
| 489 | int i; | ||
| 490 | |||
| 491 | /* Values prefixed with saved_ are written back to host after | ||
| 492 | * reset. Values without are used for driver operation. | ||
| 493 | */ | ||
| 494 | hpriv->saved_cap = cap = readl(mmio + HOST_CAP); | ||
| 495 | hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); | ||
| 496 | |||
| 497 | /* fixup zero port_map */ | ||
| 498 | if (!port_map) { | ||
| 499 | port_map = (1 << ahci_nr_ports(hpriv->cap)) - 1; | ||
| 500 | dev_printk(KERN_WARNING, &pdev->dev, | ||
| 501 | "PORTS_IMPL is zero, forcing 0x%x\n", port_map); | ||
| 502 | |||
| 503 | /* write the fixed up value to the PI register */ | ||
| 504 | hpriv->saved_port_map = port_map; | ||
| 505 | } | ||
| 506 | |||
| 507 | /* cross check port_map and cap.n_ports */ | ||
| 508 | if (pi->flags & AHCI_FLAG_HONOR_PI) { | ||
| 509 | u32 tmp_port_map = port_map; | ||
| 510 | int n_ports = ahci_nr_ports(cap); | ||
| 511 | |||
| 512 | for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) { | ||
| 513 | if (tmp_port_map & (1 << i)) { | ||
| 514 | n_ports--; | ||
| 515 | tmp_port_map &= ~(1 << i); | ||
| 516 | } | ||
| 517 | } | ||
| 518 | |||
| 519 | /* Whine if inconsistent. No need to update cap. | ||
| 520 | * port_map is used to determine number of ports. | ||
| 521 | */ | ||
| 522 | if (n_ports || tmp_port_map) | ||
| 523 | dev_printk(KERN_WARNING, &pdev->dev, | ||
| 524 | "nr_ports (%u) and implemented port map " | ||
| 525 | "(0x%x) don't match\n", | ||
| 526 | ahci_nr_ports(cap), port_map); | ||
| 527 | } else { | ||
| 528 | /* fabricate port_map from cap.nr_ports */ | ||
| 529 | port_map = (1 << ahci_nr_ports(cap)) - 1; | ||
| 530 | } | ||
| 531 | |||
| 532 | /* record values to use during operation */ | ||
| 533 | hpriv->cap = cap; | ||
| 534 | hpriv->port_map = port_map; | ||
| 535 | } | ||
| 536 | |||
| 537 | /** | ||
| 538 | * ahci_restore_initial_config - Restore initial config | ||
| 539 | * @host: target ATA host | ||
| 540 | * | ||
| 541 | * Restore initial config stored by ahci_save_initial_config(). | ||
| 542 | * | ||
| 543 | * LOCKING: | ||
| 544 | * None. | ||
| 545 | */ | ||
| 546 | static void ahci_restore_initial_config(struct ata_host *host) | ||
| 547 | { | ||
| 548 | struct ahci_host_priv *hpriv = host->private_data; | ||
| 549 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | ||
| 550 | |||
| 551 | writel(hpriv->saved_cap, mmio + HOST_CAP); | ||
| 552 | writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); | ||
| 553 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ | ||
| 478 | } | 554 | } |
| 479 | 555 | ||
| 480 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in) | 556 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in) |
| @@ -511,8 +587,9 @@ static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in, | |||
| 511 | writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); | 587 | writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
| 512 | } | 588 | } |
| 513 | 589 | ||
| 514 | static void ahci_start_engine(void __iomem *port_mmio) | 590 | static void ahci_start_engine(struct ata_port *ap) |
| 515 | { | 591 | { |
| 592 | void __iomem *port_mmio = ahci_port_base(ap); | ||
| 516 | u32 tmp; | 593 | u32 tmp; |
| 517 | 594 | ||
| 518 | /* start DMA */ | 595 | /* start DMA */ |
| @@ -522,8 +599,9 @@ static void ahci_start_engine(void __iomem *port_mmio) | |||
| 522 | readl(port_mmio + PORT_CMD); /* flush */ | 599 | readl(port_mmio + PORT_CMD); /* flush */ |
| 523 | } | 600 | } |
| 524 | 601 | ||
| 525 | static int ahci_stop_engine(void __iomem *port_mmio) | 602 | static int ahci_stop_engine(struct ata_port *ap) |
| 526 | { | 603 | { |
| 604 | void __iomem *port_mmio = ahci_port_base(ap); | ||
| 527 | u32 tmp; | 605 | u32 tmp; |
| 528 | 606 | ||
| 529 | tmp = readl(port_mmio + PORT_CMD); | 607 | tmp = readl(port_mmio + PORT_CMD); |
| @@ -545,19 +623,23 @@ static int ahci_stop_engine(void __iomem *port_mmio) | |||
| 545 | return 0; | 623 | return 0; |
| 546 | } | 624 | } |
| 547 | 625 | ||
| 548 | static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap, | 626 | static void ahci_start_fis_rx(struct ata_port *ap) |
| 549 | dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma) | ||
| 550 | { | 627 | { |
| 628 | void __iomem *port_mmio = ahci_port_base(ap); | ||
| 629 | struct ahci_host_priv *hpriv = ap->host->private_data; | ||
| 630 | struct ahci_port_priv *pp = ap->private_data; | ||
| 551 | u32 tmp; | 631 | u32 tmp; |
| 552 | 632 | ||
| 553 | /* set FIS registers */ | 633 | /* set FIS registers */ |
| 554 | if (cap & HOST_CAP_64) | 634 | if (hpriv->cap & HOST_CAP_64) |
| 555 | writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI); | 635 | writel((pp->cmd_slot_dma >> 16) >> 16, |
| 556 | writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); | 636 | port_mmio + PORT_LST_ADDR_HI); |
| 637 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); | ||
| 557 | 638 | ||
| 558 | if (cap & HOST_CAP_64) | 639 | if (hpriv->cap & HOST_CAP_64) |
| 559 | writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI); | 640 | writel((pp->rx_fis_dma >> 16) >> 16, |
| 560 | writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); | 641 | port_mmio + PORT_FIS_ADDR_HI); |
| 642 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); | ||
| 561 | 643 | ||
| 562 | /* enable FIS reception */ | 644 | /* enable FIS reception */ |
| 563 | tmp = readl(port_mmio + PORT_CMD); | 645 | tmp = readl(port_mmio + PORT_CMD); |
| @@ -568,8 +650,9 @@ static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap, | |||
| 568 | readl(port_mmio + PORT_CMD); | 650 | readl(port_mmio + PORT_CMD); |
| 569 | } | 651 | } |
| 570 | 652 | ||
| 571 | static int ahci_stop_fis_rx(void __iomem *port_mmio) | 653 | static int ahci_stop_fis_rx(struct ata_port *ap) |
| 572 | { | 654 | { |
| 655 | void __iomem *port_mmio = ahci_port_base(ap); | ||
| 573 | u32 tmp; | 656 | u32 tmp; |
| 574 | 657 | ||
| 575 | /* disable FIS reception */ | 658 | /* disable FIS reception */ |
| @@ -586,14 +669,16 @@ static int ahci_stop_fis_rx(void __iomem *port_mmio) | |||
| 586 | return 0; | 669 | return 0; |
| 587 | } | 670 | } |
| 588 | 671 | ||
| 589 | static void ahci_power_up(void __iomem *port_mmio, u32 cap) | 672 | static void ahci_power_up(struct ata_port *ap) |
| 590 | { | 673 | { |
| 674 | struct ahci_host_priv *hpriv = ap->host->private_data; | ||
| 675 | void __iomem *port_mmio = ahci_port_base(ap); | ||
| 591 | u32 cmd; | 676 | u32 cmd; |
| 592 | 677 | ||
| 593 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | 678 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; |
| 594 | 679 | ||
| 595 | /* spin up device */ | 680 | /* spin up device */ |
| 596 | if (cap & HOST_CAP_SSS) { | 681 | if (hpriv->cap & HOST_CAP_SSS) { |
| 597 | cmd |= PORT_CMD_SPIN_UP; | 682 | cmd |= PORT_CMD_SPIN_UP; |
| 598 | writel(cmd, port_mmio + PORT_CMD); | 683 | writel(cmd, port_mmio + PORT_CMD); |
| 599 | } | 684 | } |
| @@ -603,11 +688,13 @@ static void ahci_power_up(void __iomem *port_mmio, u32 cap) | |||
| 603 | } | 688 | } |
| 604 | 689 | ||
| 605 | #ifdef CONFIG_PM | 690 | #ifdef CONFIG_PM |
| 606 | static void ahci_power_down(void __iomem *port_mmio, u32 cap) | 691 | static void ahci_power_down(struct ata_port *ap) |
| 607 | { | 692 | { |
| 693 | struct ahci_host_priv *hpriv = ap->host->private_data; | ||
| 694 | void __iomem *port_mmio = ahci_port_base(ap); | ||
| 608 | u32 cmd, scontrol; | 695 | u32 cmd, scontrol; |
| 609 | 696 | ||
| 610 | if (!(cap & HOST_CAP_SSS)) | 697 | if (!(hpriv->cap & HOST_CAP_SSS)) |
| 611 | return; | 698 | return; |
| 612 | 699 | ||
| 613 | /* put device into listen mode, first set PxSCTL.DET to 0 */ | 700 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
| @@ -622,29 +709,28 @@ static void ahci_power_down(void __iomem *port_mmio, u32 cap) | |||
| 622 | } | 709 | } |
| 623 | #endif | 710 | #endif |
| 624 | 711 | ||
| 625 | static void ahci_init_port(void __iomem *port_mmio, u32 cap, | 712 | static void ahci_init_port(struct ata_port *ap) |
| 626 | dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma) | ||
| 627 | { | 713 | { |
| 628 | /* enable FIS reception */ | 714 | /* enable FIS reception */ |
| 629 | ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma); | 715 | ahci_start_fis_rx(ap); |
| 630 | 716 | ||
| 631 | /* enable DMA */ | 717 | /* enable DMA */ |
| 632 | ahci_start_engine(port_mmio); | 718 | ahci_start_engine(ap); |
| 633 | } | 719 | } |
| 634 | 720 | ||
| 635 | static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg) | 721 | static int ahci_deinit_port(struct ata_port *ap, const char **emsg) |
| 636 | { | 722 | { |
| 637 | int rc; | 723 | int rc; |
| 638 | 724 | ||
| 639 | /* disable DMA */ | 725 | /* disable DMA */ |
| 640 | rc = ahci_stop_engine(port_mmio); | 726 | rc = ahci_stop_engine(ap); |
| 641 | if (rc) { | 727 | if (rc) { |
| 642 | *emsg = "failed to stop engine"; | 728 | *emsg = "failed to stop engine"; |
| 643 | return rc; | 729 | return rc; |
| 644 | } | 730 | } |
| 645 | 731 | ||
| 646 | /* disable FIS reception */ | 732 | /* disable FIS reception */ |
| 647 | rc = ahci_stop_fis_rx(port_mmio); | 733 | rc = ahci_stop_fis_rx(ap); |
| 648 | if (rc) { | 734 | if (rc) { |
| 649 | *emsg = "failed stop FIS RX"; | 735 | *emsg = "failed stop FIS RX"; |
| 650 | return rc; | 736 | return rc; |
| @@ -653,12 +739,11 @@ static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg) | |||
| 653 | return 0; | 739 | return 0; |
| 654 | } | 740 | } |
| 655 | 741 | ||
| 656 | static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev) | 742 | static int ahci_reset_controller(struct ata_host *host) |
| 657 | { | 743 | { |
| 658 | u32 cap_save, impl_save, tmp; | 744 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 659 | 745 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | |
| 660 | cap_save = readl(mmio + HOST_CAP); | 746 | u32 tmp; |
| 661 | impl_save = readl(mmio + HOST_PORTS_IMPL); | ||
| 662 | 747 | ||
| 663 | /* global controller reset */ | 748 | /* global controller reset */ |
| 664 | tmp = readl(mmio + HOST_CTL); | 749 | tmp = readl(mmio + HOST_CTL); |
| @@ -674,7 +759,7 @@ static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev) | |||
| 674 | 759 | ||
| 675 | tmp = readl(mmio + HOST_CTL); | 760 | tmp = readl(mmio + HOST_CTL); |
| 676 | if (tmp & HOST_RESET) { | 761 | if (tmp & HOST_RESET) { |
| 677 | dev_printk(KERN_ERR, &pdev->dev, | 762 | dev_printk(KERN_ERR, host->dev, |
| 678 | "controller reset failed (0x%x)\n", tmp); | 763 | "controller reset failed (0x%x)\n", tmp); |
| 679 | return -EIO; | 764 | return -EIO; |
| 680 | } | 765 | } |
| @@ -683,18 +768,8 @@ static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev) | |||
| 683 | writel(HOST_AHCI_EN, mmio + HOST_CTL); | 768 | writel(HOST_AHCI_EN, mmio + HOST_CTL); |
| 684 | (void) readl(mmio + HOST_CTL); /* flush */ | 769 | (void) readl(mmio + HOST_CTL); /* flush */ |
| 685 | 770 | ||
| 686 | /* These write-once registers are normally cleared on reset. | 771 | /* some registers might be cleared on reset. restore initial values */ |
| 687 | * Restore BIOS values... which we HOPE were present before | 772 | ahci_restore_initial_config(host); |
| 688 | * reset. | ||
| 689 | */ | ||
| 690 | if (!impl_save) { | ||
| 691 | impl_save = (1 << ahci_nr_ports(cap_save)) - 1; | ||
| 692 | dev_printk(KERN_WARNING, &pdev->dev, | ||
| 693 | "PORTS_IMPL is zero, forcing 0x%x\n", impl_save); | ||
| 694 | } | ||
| 695 | writel(cap_save, mmio + HOST_CAP); | ||
| 696 | writel(impl_save, mmio + HOST_PORTS_IMPL); | ||
| 697 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ | ||
| 698 | 773 | ||
| 699 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { | 774 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
| 700 | u16 tmp16; | 775 | u16 tmp16; |
| @@ -708,23 +783,23 @@ static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev) | |||
| 708 | return 0; | 783 | return 0; |
| 709 | } | 784 | } |
| 710 | 785 | ||
| 711 | static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev, | 786 | static void ahci_init_controller(struct ata_host *host) |
| 712 | int n_ports, unsigned int port_flags, | ||
| 713 | struct ahci_host_priv *hpriv) | ||
| 714 | { | 787 | { |
| 788 | struct pci_dev *pdev = to_pci_dev(host->dev); | ||
| 789 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | ||
| 715 | int i, rc; | 790 | int i, rc; |
| 716 | u32 tmp; | 791 | u32 tmp; |
| 717 | 792 | ||
| 718 | for (i = 0; i < n_ports; i++) { | 793 | for (i = 0; i < host->n_ports; i++) { |
| 719 | void __iomem *port_mmio = ahci_port_base(mmio, i); | 794 | struct ata_port *ap = host->ports[i]; |
| 795 | void __iomem *port_mmio = ahci_port_base(ap); | ||
| 720 | const char *emsg = NULL; | 796 | const char *emsg = NULL; |
| 721 | 797 | ||
| 722 | if ((port_flags & AHCI_FLAG_HONOR_PI) && | 798 | if (ata_port_is_dummy(ap)) |
| 723 | !(hpriv->port_map & (1 << i))) | ||
| 724 | continue; | 799 | continue; |
| 725 | 800 | ||
| 726 | /* make sure port is not active */ | 801 | /* make sure port is not active */ |
| 727 | rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg); | 802 | rc = ahci_deinit_port(ap, &emsg); |
| 728 | if (rc) | 803 | if (rc) |
| 729 | dev_printk(KERN_WARNING, &pdev->dev, | 804 | dev_printk(KERN_WARNING, &pdev->dev, |
| 730 | "%s (%d)\n", emsg, rc); | 805 | "%s (%d)\n", emsg, rc); |
| @@ -752,7 +827,7 @@ static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev, | |||
| 752 | 827 | ||
| 753 | static unsigned int ahci_dev_classify(struct ata_port *ap) | 828 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
| 754 | { | 829 | { |
| 755 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; | 830 | void __iomem *port_mmio = ahci_port_base(ap); |
| 756 | struct ata_taskfile tf; | 831 | struct ata_taskfile tf; |
| 757 | u32 tmp; | 832 | u32 tmp; |
| 758 | 833 | ||
| @@ -802,8 +877,7 @@ static int ahci_clo(struct ata_port *ap) | |||
| 802 | static int ahci_softreset(struct ata_port *ap, unsigned int *class) | 877 | static int ahci_softreset(struct ata_port *ap, unsigned int *class) |
| 803 | { | 878 | { |
| 804 | struct ahci_port_priv *pp = ap->private_data; | 879 | struct ahci_port_priv *pp = ap->private_data; |
| 805 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; | 880 | void __iomem *port_mmio = ahci_port_base(ap); |
| 806 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | ||
| 807 | const u32 cmd_fis_len = 5; /* five dwords */ | 881 | const u32 cmd_fis_len = 5; /* five dwords */ |
| 808 | const char *reason = NULL; | 882 | const char *reason = NULL; |
| 809 | struct ata_taskfile tf; | 883 | struct ata_taskfile tf; |
| @@ -820,7 +894,7 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class) | |||
| 820 | } | 894 | } |
| 821 | 895 | ||
| 822 | /* prepare for SRST (AHCI-1.1 10.4.1) */ | 896 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
| 823 | rc = ahci_stop_engine(port_mmio); | 897 | rc = ahci_stop_engine(ap); |
| 824 | if (rc) { | 898 | if (rc) { |
| 825 | reason = "failed to stop engine"; | 899 | reason = "failed to stop engine"; |
| 826 | goto fail_restart; | 900 | goto fail_restart; |
| @@ -840,7 +914,7 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class) | |||
| 840 | } | 914 | } |
| 841 | 915 | ||
| 842 | /* restart engine */ | 916 | /* restart engine */ |
| 843 | ahci_start_engine(port_mmio); | 917 | ahci_start_engine(ap); |
| 844 | 918 | ||
| 845 | ata_tf_init(ap->device, &tf); | 919 | ata_tf_init(ap->device, &tf); |
| 846 | fis = pp->cmd_tbl; | 920 | fis = pp->cmd_tbl; |
| @@ -899,7 +973,7 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class) | |||
| 899 | return 0; | 973 | return 0; |
| 900 | 974 | ||
| 901 | fail_restart: | 975 | fail_restart: |
| 902 | ahci_start_engine(port_mmio); | 976 | ahci_start_engine(ap); |
| 903 | fail: | 977 | fail: |
| 904 | ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); | 978 | ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); |
| 905 | return rc; | 979 | return rc; |
| @@ -910,13 +984,11 @@ static int ahci_hardreset(struct ata_port *ap, unsigned int *class) | |||
| 910 | struct ahci_port_priv *pp = ap->private_data; | 984 | struct ahci_port_priv *pp = ap->private_data; |
| 911 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | 985 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
| 912 | struct ata_taskfile tf; | 986 | struct ata_taskfile tf; |
| 913 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; | ||
| 914 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | ||
| 915 | int rc; | 987 | int rc; |
| 916 | 988 | ||
| 917 | DPRINTK("ENTER\n"); | 989 | DPRINTK("ENTER\n"); |
| 918 | 990 | ||
| 919 | ahci_stop_engine(port_mmio); | 991 | ahci_stop_engine(ap); |
| 920 | 992 | ||
| 921 | /* clear D2H reception area to properly wait for D2H FIS */ | 993 | /* clear D2H reception area to properly wait for D2H FIS */ |
| 922 | ata_tf_init(ap->device, &tf); | 994 | ata_tf_init(ap->device, &tf); |
| @@ -925,7 +997,7 @@ static int ahci_hardreset(struct ata_port *ap, unsigned int *class) | |||
| 925 | 997 | ||
| 926 | rc = sata_std_hardreset(ap, class); | 998 | rc = sata_std_hardreset(ap, class); |
| 927 | 999 | ||
| 928 | ahci_start_engine(port_mmio); | 1000 | ahci_start_engine(ap); |
| 929 | 1001 | ||
| 930 | if (rc == 0 && ata_port_online(ap)) | 1002 | if (rc == 0 && ata_port_online(ap)) |
| 931 | *class = ahci_dev_classify(ap); | 1003 | *class = ahci_dev_classify(ap); |
| @@ -938,20 +1010,18 @@ static int ahci_hardreset(struct ata_port *ap, unsigned int *class) | |||
| 938 | 1010 | ||
| 939 | static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class) | 1011 | static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class) |
| 940 | { | 1012 | { |
| 941 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; | ||
| 942 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | ||
| 943 | int rc; | 1013 | int rc; |
| 944 | 1014 | ||
| 945 | DPRINTK("ENTER\n"); | 1015 | DPRINTK("ENTER\n"); |
| 946 | 1016 | ||
| 947 | ahci_stop_engine(port_mmio); | 1017 | ahci_stop_engine(ap); |
| 948 | 1018 | ||
| 949 | rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context)); | 1019 | rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context)); |
| 950 | 1020 | ||
| 951 | /* vt8251 needs SError cleared for the port to operate */ | 1021 | /* vt8251 needs SError cleared for the port to operate */ |
| 952 | ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR)); | 1022 | ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR)); |
| 953 | 1023 | ||
| 954 | ahci_start_engine(port_mmio); | 1024 | ahci_start_engine(ap); |
| 955 | 1025 | ||
| 956 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | 1026 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
| 957 | 1027 | ||
| @@ -963,7 +1033,7 @@ static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class) | |||
| 963 | 1033 | ||
| 964 | static void ahci_postreset(struct ata_port *ap, unsigned int *class) | 1034 | static void ahci_postreset(struct ata_port *ap, unsigned int *class) |
| 965 | { | 1035 | { |
| 966 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; | 1036 | void __iomem *port_mmio = ahci_port_base(ap); |
| 967 | u32 new_tmp, tmp; | 1037 | u32 new_tmp, tmp; |
| 968 | 1038 | ||
| 969 | ata_std_postreset(ap, class); | 1039 | ata_std_postreset(ap, class); |
| @@ -1131,8 +1201,7 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) | |||
| 1131 | 1201 | ||
| 1132 | static void ahci_host_intr(struct ata_port *ap) | 1202 | static void ahci_host_intr(struct ata_port *ap) |
| 1133 | { | 1203 | { |
| 1134 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; | 1204 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
| 1135 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | ||
| 1136 | struct ata_eh_info *ehi = &ap->eh_info; | 1205 | struct ata_eh_info *ehi = &ap->eh_info; |
| 1137 | struct ahci_port_priv *pp = ap->private_data; | 1206 | struct ahci_port_priv *pp = ap->private_data; |
| 1138 | u32 status, qc_active; | 1207 | u32 status, qc_active; |
| @@ -1283,7 +1352,7 @@ static irqreturn_t ahci_interrupt(int irq, void *dev_instance) | |||
| 1283 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) | 1352 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
| 1284 | { | 1353 | { |
| 1285 | struct ata_port *ap = qc->ap; | 1354 | struct ata_port *ap = qc->ap; |
| 1286 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; | 1355 | void __iomem *port_mmio = ahci_port_base(ap); |
| 1287 | 1356 | ||
| 1288 | if (qc->tf.protocol == ATA_PROT_NCQ) | 1357 | if (qc->tf.protocol == ATA_PROT_NCQ) |
| 1289 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); | 1358 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); |
| @@ -1295,8 +1364,7 @@ static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) | |||
| 1295 | 1364 | ||
| 1296 | static void ahci_freeze(struct ata_port *ap) | 1365 | static void ahci_freeze(struct ata_port *ap) |
| 1297 | { | 1366 | { |
| 1298 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; | 1367 | void __iomem *port_mmio = ahci_port_base(ap); |
| 1299 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | ||
| 1300 | 1368 | ||
| 1301 | /* turn IRQ off */ | 1369 | /* turn IRQ off */ |
| 1302 | writel(0, port_mmio + PORT_IRQ_MASK); | 1370 | writel(0, port_mmio + PORT_IRQ_MASK); |
| @@ -1305,7 +1373,7 @@ static void ahci_freeze(struct ata_port *ap) | |||
| 1305 | static void ahci_thaw(struct ata_port *ap) | 1373 | static void ahci_thaw(struct ata_port *ap) |
| 1306 | { | 1374 | { |
| 1307 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; | 1375 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; |
| 1308 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | 1376 | void __iomem *port_mmio = ahci_port_base(ap); |
| 1309 | u32 tmp; | 1377 | u32 tmp; |
| 1310 | 1378 | ||
| 1311 | /* clear IRQ */ | 1379 | /* clear IRQ */ |
| @@ -1319,13 +1387,10 @@ static void ahci_thaw(struct ata_port *ap) | |||
| 1319 | 1387 | ||
| 1320 | static void ahci_error_handler(struct ata_port *ap) | 1388 | static void ahci_error_handler(struct ata_port *ap) |
| 1321 | { | 1389 | { |
| 1322 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; | ||
| 1323 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | ||
| 1324 | |||
| 1325 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { | 1390 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
| 1326 | /* restart engine */ | 1391 | /* restart engine */ |
| 1327 | ahci_stop_engine(port_mmio); | 1392 | ahci_stop_engine(ap); |
| 1328 | ahci_start_engine(port_mmio); | 1393 | ahci_start_engine(ap); |
| 1329 | } | 1394 | } |
| 1330 | 1395 | ||
| 1331 | /* perform recovery */ | 1396 | /* perform recovery */ |
| @@ -1335,13 +1400,10 @@ static void ahci_error_handler(struct ata_port *ap) | |||
| 1335 | 1400 | ||
| 1336 | static void ahci_vt8251_error_handler(struct ata_port *ap) | 1401 | static void ahci_vt8251_error_handler(struct ata_port *ap) |
| 1337 | { | 1402 | { |
| 1338 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; | ||
| 1339 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | ||
| 1340 | |||
| 1341 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { | 1403 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
| 1342 | /* restart engine */ | 1404 | /* restart engine */ |
| 1343 | ahci_stop_engine(port_mmio); | 1405 | ahci_stop_engine(ap); |
| 1344 | ahci_start_engine(port_mmio); | 1406 | ahci_start_engine(ap); |
| 1345 | } | 1407 | } |
| 1346 | 1408 | ||
| 1347 | /* perform recovery */ | 1409 | /* perform recovery */ |
| @@ -1352,36 +1414,26 @@ static void ahci_vt8251_error_handler(struct ata_port *ap) | |||
| 1352 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) | 1414 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
| 1353 | { | 1415 | { |
| 1354 | struct ata_port *ap = qc->ap; | 1416 | struct ata_port *ap = qc->ap; |
| 1355 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; | ||
| 1356 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | ||
| 1357 | 1417 | ||
| 1358 | if (qc->flags & ATA_QCFLAG_FAILED) | 1418 | if (qc->flags & ATA_QCFLAG_FAILED) { |
| 1359 | qc->err_mask |= AC_ERR_OTHER; | ||
| 1360 | |||
| 1361 | if (qc->err_mask) { | ||
| 1362 | /* make DMA engine forget about the failed command */ | 1419 | /* make DMA engine forget about the failed command */ |
| 1363 | ahci_stop_engine(port_mmio); | 1420 | ahci_stop_engine(ap); |
| 1364 | ahci_start_engine(port_mmio); | 1421 | ahci_start_engine(ap); |
| 1365 | } | 1422 | } |
| 1366 | } | 1423 | } |
| 1367 | 1424 | ||
| 1368 | #ifdef CONFIG_PM | 1425 | #ifdef CONFIG_PM |
| 1369 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) | 1426 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
| 1370 | { | 1427 | { |
| 1371 | struct ahci_host_priv *hpriv = ap->host->private_data; | ||
| 1372 | struct ahci_port_priv *pp = ap->private_data; | ||
| 1373 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; | ||
| 1374 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | ||
| 1375 | const char *emsg = NULL; | 1428 | const char *emsg = NULL; |
| 1376 | int rc; | 1429 | int rc; |
| 1377 | 1430 | ||
| 1378 | rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg); | 1431 | rc = ahci_deinit_port(ap, &emsg); |
| 1379 | if (rc == 0) | 1432 | if (rc == 0) |
| 1380 | ahci_power_down(port_mmio, hpriv->cap); | 1433 | ahci_power_down(ap); |
| 1381 | else { | 1434 | else { |
| 1382 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); | 1435 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
| 1383 | ahci_init_port(port_mmio, hpriv->cap, | 1436 | ahci_init_port(ap); |
| 1384 | pp->cmd_slot_dma, pp->rx_fis_dma); | ||
| 1385 | } | 1437 | } |
| 1386 | 1438 | ||
| 1387 | return rc; | 1439 | return rc; |
| @@ -1389,13 +1441,8 @@ static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) | |||
| 1389 | 1441 | ||
| 1390 | static int ahci_port_resume(struct ata_port *ap) | 1442 | static int ahci_port_resume(struct ata_port *ap) |
| 1391 | { | 1443 | { |
| 1392 | struct ahci_port_priv *pp = ap->private_data; | 1444 | ahci_power_up(ap); |
| 1393 | struct ahci_host_priv *hpriv = ap->host->private_data; | 1445 | ahci_init_port(ap); |
| 1394 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; | ||
| 1395 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | ||
| 1396 | |||
| 1397 | ahci_power_up(port_mmio, hpriv->cap); | ||
| 1398 | ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma); | ||
| 1399 | 1446 | ||
| 1400 | return 0; | 1447 | return 0; |
| 1401 | } | 1448 | } |
| @@ -1423,8 +1470,6 @@ static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) | |||
| 1423 | static int ahci_pci_device_resume(struct pci_dev *pdev) | 1470 | static int ahci_pci_device_resume(struct pci_dev *pdev) |
| 1424 | { | 1471 | { |
| 1425 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | 1472 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
| 1426 | struct ahci_host_priv *hpriv = host->private_data; | ||
| 1427 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; | ||
| 1428 | int rc; | 1473 | int rc; |
| 1429 | 1474 | ||
| 1430 | rc = ata_pci_device_do_resume(pdev); | 1475 | rc = ata_pci_device_do_resume(pdev); |
| @@ -1432,12 +1477,11 @@ static int ahci_pci_device_resume(struct pci_dev *pdev) | |||
| 1432 | return rc; | 1477 | return rc; |
| 1433 | 1478 | ||
| 1434 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | 1479 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { |
| 1435 | rc = ahci_reset_controller(mmio, pdev); | 1480 | rc = ahci_reset_controller(host); |
| 1436 | if (rc) | 1481 | if (rc) |
| 1437 | return rc; | 1482 | return rc; |
| 1438 | 1483 | ||
| 1439 | ahci_init_controller(mmio, pdev, host->n_ports, | 1484 | ahci_init_controller(host); |
| 1440 | host->ports[0]->flags, hpriv); | ||
| 1441 | } | 1485 | } |
| 1442 | 1486 | ||
| 1443 | ata_host_resume(host); | 1487 | ata_host_resume(host); |
| @@ -1449,10 +1493,7 @@ static int ahci_pci_device_resume(struct pci_dev *pdev) | |||
| 1449 | static int ahci_port_start(struct ata_port *ap) | 1493 | static int ahci_port_start(struct ata_port *ap) |
| 1450 | { | 1494 | { |
| 1451 | struct device *dev = ap->host->dev; | 1495 | struct device *dev = ap->host->dev; |
| 1452 | struct ahci_host_priv *hpriv = ap->host->private_data; | ||
| 1453 | struct ahci_port_priv *pp; | 1496 | struct ahci_port_priv *pp; |
| 1454 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; | ||
| 1455 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | ||
| 1456 | void *mem; | 1497 | void *mem; |
| 1457 | dma_addr_t mem_dma; | 1498 | dma_addr_t mem_dma; |
| 1458 | int rc; | 1499 | int rc; |
| @@ -1500,85 +1541,29 @@ static int ahci_port_start(struct ata_port *ap) | |||
| 1500 | ap->private_data = pp; | 1541 | ap->private_data = pp; |
| 1501 | 1542 | ||
| 1502 | /* power up port */ | 1543 | /* power up port */ |
| 1503 | ahci_power_up(port_mmio, hpriv->cap); | 1544 | ahci_power_up(ap); |
| 1504 | 1545 | ||
| 1505 | /* initialize port */ | 1546 | /* initialize port */ |
| 1506 | ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma); | 1547 | ahci_init_port(ap); |
| 1507 | 1548 | ||
| 1508 | return 0; | 1549 | return 0; |
| 1509 | } | 1550 | } |
| 1510 | 1551 | ||
| 1511 | static void ahci_port_stop(struct ata_port *ap) | 1552 | static void ahci_port_stop(struct ata_port *ap) |
| 1512 | { | 1553 | { |
| 1513 | struct ahci_host_priv *hpriv = ap->host->private_data; | ||
| 1514 | void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; | ||
| 1515 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | ||
| 1516 | const char *emsg = NULL; | 1554 | const char *emsg = NULL; |
| 1517 | int rc; | 1555 | int rc; |
| 1518 | 1556 | ||
| 1519 | /* de-initialize port */ | 1557 | /* de-initialize port */ |
| 1520 | rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg); | 1558 | rc = ahci_deinit_port(ap, &emsg); |
| 1521 | if (rc) | 1559 | if (rc) |
| 1522 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); | 1560 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); |
| 1523 | } | 1561 | } |
| 1524 | 1562 | ||
| 1525 | static void ahci_setup_port(struct ata_ioports *port, void __iomem *base, | 1563 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
| 1526 | unsigned int port_idx) | ||
| 1527 | { | 1564 | { |
| 1528 | VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx); | ||
| 1529 | base = ahci_port_base(base, port_idx); | ||
| 1530 | VPRINTK("base now==0x%lx\n", base); | ||
| 1531 | |||
| 1532 | port->cmd_addr = base; | ||
| 1533 | port->scr_addr = base + PORT_SCR; | ||
| 1534 | |||
| 1535 | VPRINTK("EXIT\n"); | ||
| 1536 | } | ||
| 1537 | |||
| 1538 | static int ahci_host_init(struct ata_probe_ent *probe_ent) | ||
| 1539 | { | ||
| 1540 | struct ahci_host_priv *hpriv = probe_ent->private_data; | ||
| 1541 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | ||
| 1542 | void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR]; | ||
| 1543 | unsigned int i, cap_n_ports, using_dac; | ||
| 1544 | int rc; | 1565 | int rc; |
| 1545 | 1566 | ||
| 1546 | rc = ahci_reset_controller(mmio, pdev); | ||
| 1547 | if (rc) | ||
| 1548 | return rc; | ||
| 1549 | |||
| 1550 | hpriv->cap = readl(mmio + HOST_CAP); | ||
| 1551 | hpriv->port_map = readl(mmio + HOST_PORTS_IMPL); | ||
| 1552 | cap_n_ports = ahci_nr_ports(hpriv->cap); | ||
| 1553 | |||
| 1554 | VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n", | ||
| 1555 | hpriv->cap, hpriv->port_map, cap_n_ports); | ||
| 1556 | |||
| 1557 | if (probe_ent->port_flags & AHCI_FLAG_HONOR_PI) { | ||
| 1558 | unsigned int n_ports = cap_n_ports; | ||
| 1559 | u32 port_map = hpriv->port_map; | ||
| 1560 | int max_port = 0; | ||
| 1561 | |||
| 1562 | for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) { | ||
| 1563 | if (port_map & (1 << i)) { | ||
| 1564 | n_ports--; | ||
| 1565 | port_map &= ~(1 << i); | ||
| 1566 | max_port = i; | ||
| 1567 | } else | ||
| 1568 | probe_ent->dummy_port_mask |= 1 << i; | ||
| 1569 | } | ||
| 1570 | |||
| 1571 | if (n_ports || port_map) | ||
| 1572 | dev_printk(KERN_WARNING, &pdev->dev, | ||
| 1573 | "nr_ports (%u) and implemented port map " | ||
| 1574 | "(0x%x) don't match\n", | ||
| 1575 | cap_n_ports, hpriv->port_map); | ||
| 1576 | |||
| 1577 | probe_ent->n_ports = max_port + 1; | ||
| 1578 | } else | ||
| 1579 | probe_ent->n_ports = cap_n_ports; | ||
| 1580 | |||
| 1581 | using_dac = hpriv->cap & HOST_CAP_64; | ||
| 1582 | if (using_dac && | 1567 | if (using_dac && |
| 1583 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | 1568 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
| 1584 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | 1569 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); |
| @@ -1604,23 +1589,14 @@ static int ahci_host_init(struct ata_probe_ent *probe_ent) | |||
| 1604 | return rc; | 1589 | return rc; |
| 1605 | } | 1590 | } |
| 1606 | } | 1591 | } |
| 1607 | |||
| 1608 | for (i = 0; i < probe_ent->n_ports; i++) | ||
| 1609 | ahci_setup_port(&probe_ent->port[i], mmio, i); | ||
| 1610 | |||
| 1611 | ahci_init_controller(mmio, pdev, probe_ent->n_ports, | ||
| 1612 | probe_ent->port_flags, hpriv); | ||
| 1613 | |||
| 1614 | pci_set_master(pdev); | ||
| 1615 | |||
| 1616 | return 0; | 1592 | return 0; |
| 1617 | } | 1593 | } |
| 1618 | 1594 | ||
| 1619 | static void ahci_print_info(struct ata_probe_ent *probe_ent) | 1595 | static void ahci_print_info(struct ata_host *host) |
| 1620 | { | 1596 | { |
| 1621 | struct ahci_host_priv *hpriv = probe_ent->private_data; | 1597 | struct ahci_host_priv *hpriv = host->private_data; |
| 1622 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | 1598 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 1623 | void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR]; | 1599 | void __iomem *mmio = host->iomap[AHCI_PCI_BAR]; |
| 1624 | u32 vers, cap, impl, speed; | 1600 | u32 vers, cap, impl, speed; |
| 1625 | const char *speed_s; | 1601 | const char *speed_s; |
| 1626 | u16 cc; | 1602 | u16 cc; |
| @@ -1690,11 +1666,12 @@ static void ahci_print_info(struct ata_probe_ent *probe_ent) | |||
| 1690 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | 1666 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 1691 | { | 1667 | { |
| 1692 | static int printed_version; | 1668 | static int printed_version; |
| 1693 | unsigned int board_idx = (unsigned int) ent->driver_data; | 1669 | struct ata_port_info pi = ahci_port_info[ent->driver_data]; |
| 1670 | const struct ata_port_info *ppi[] = { &pi, NULL }; | ||
| 1694 | struct device *dev = &pdev->dev; | 1671 | struct device *dev = &pdev->dev; |
| 1695 | struct ata_probe_ent *probe_ent; | ||
| 1696 | struct ahci_host_priv *hpriv; | 1672 | struct ahci_host_priv *hpriv; |
| 1697 | int rc; | 1673 | struct ata_host *host; |
| 1674 | int i, rc; | ||
| 1698 | 1675 | ||
| 1699 | VPRINTK("ENTER\n"); | 1676 | VPRINTK("ENTER\n"); |
| 1700 | 1677 | ||
| @@ -1703,6 +1680,7 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
| 1703 | if (!printed_version++) | 1680 | if (!printed_version++) |
| 1704 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); | 1681 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
| 1705 | 1682 | ||
| 1683 | /* acquire resources */ | ||
| 1706 | rc = pcim_enable_device(pdev); | 1684 | rc = pcim_enable_device(pdev); |
| 1707 | if (rc) | 1685 | if (rc) |
| 1708 | return rc; | 1686 | return rc; |
| @@ -1716,44 +1694,49 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
| 1716 | if (pci_enable_msi(pdev)) | 1694 | if (pci_enable_msi(pdev)) |
| 1717 | pci_intx(pdev, 1); | 1695 | pci_intx(pdev, 1); |
| 1718 | 1696 | ||
| 1719 | probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL); | ||
| 1720 | if (probe_ent == NULL) | ||
| 1721 | return -ENOMEM; | ||
| 1722 | |||
| 1723 | probe_ent->dev = pci_dev_to_dev(pdev); | ||
| 1724 | INIT_LIST_HEAD(&probe_ent->node); | ||
| 1725 | |||
| 1726 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); | 1697 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
| 1727 | if (!hpriv) | 1698 | if (!hpriv) |
| 1728 | return -ENOMEM; | 1699 | return -ENOMEM; |
| 1729 | 1700 | ||
| 1730 | probe_ent->sht = ahci_port_info[board_idx].sht; | 1701 | /* save initial config */ |
| 1731 | probe_ent->port_flags = ahci_port_info[board_idx].flags; | 1702 | ahci_save_initial_config(pdev, &pi, hpriv); |
| 1732 | probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask; | ||
| 1733 | probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask; | ||
| 1734 | probe_ent->port_ops = ahci_port_info[board_idx].port_ops; | ||
| 1735 | 1703 | ||
| 1736 | probe_ent->irq = pdev->irq; | 1704 | /* prepare host */ |
| 1737 | probe_ent->irq_flags = IRQF_SHARED; | 1705 | if (!(pi.flags & AHCI_FLAG_NO_NCQ) && (hpriv->cap & HOST_CAP_NCQ)) |
| 1738 | probe_ent->iomap = pcim_iomap_table(pdev); | 1706 | pi.flags |= ATA_FLAG_NCQ; |
| 1739 | probe_ent->private_data = hpriv; | 1707 | |
| 1708 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map)); | ||
| 1709 | if (!host) | ||
| 1710 | return -ENOMEM; | ||
| 1711 | host->iomap = pcim_iomap_table(pdev); | ||
| 1712 | host->private_data = hpriv; | ||
| 1713 | |||
| 1714 | for (i = 0; i < host->n_ports; i++) { | ||
| 1715 | if (hpriv->port_map & (1 << i)) { | ||
| 1716 | struct ata_port *ap = host->ports[i]; | ||
| 1717 | void __iomem *port_mmio = ahci_port_base(ap); | ||
| 1718 | |||
| 1719 | ap->ioaddr.cmd_addr = port_mmio; | ||
| 1720 | ap->ioaddr.scr_addr = port_mmio + PORT_SCR; | ||
| 1721 | } else | ||
| 1722 | host->ports[i]->ops = &ata_dummy_port_ops; | ||
| 1723 | } | ||
| 1740 | 1724 | ||
| 1741 | /* initialize adapter */ | 1725 | /* initialize adapter */ |
| 1742 | rc = ahci_host_init(probe_ent); | 1726 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); |
| 1743 | if (rc) | 1727 | if (rc) |
| 1744 | return rc; | 1728 | return rc; |
| 1745 | 1729 | ||
| 1746 | if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) && | 1730 | rc = ahci_reset_controller(host); |
| 1747 | (hpriv->cap & HOST_CAP_NCQ)) | 1731 | if (rc) |
| 1748 | probe_ent->port_flags |= ATA_FLAG_NCQ; | 1732 | return rc; |
| 1749 | |||
| 1750 | ahci_print_info(probe_ent); | ||
| 1751 | 1733 | ||
| 1752 | if (!ata_device_add(probe_ent)) | 1734 | ahci_init_controller(host); |
| 1753 | return -ENODEV; | 1735 | ahci_print_info(host); |
| 1754 | 1736 | ||
| 1755 | devm_kfree(dev, probe_ent); | 1737 | pci_set_master(pdev); |
| 1756 | return 0; | 1738 | return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED, |
| 1739 | &ahci_sht); | ||
| 1757 | } | 1740 | } |
| 1758 | 1741 | ||
| 1759 | static int __init ahci_init(void) | 1742 | static int __init ahci_init(void) |
