1 files changed, 149 insertions, 106 deletions

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 11e4eb9f304e..06f212ff2b4f 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -99,6 +99,7 @@ enum {
         HOST_CAP_SSC            = (1 << 14), /* Slumber capable */
         HOST_CAP_CLO            = (1 << 24), /* Command List Override support */
         HOST_CAP_SSS            = (1 << 27), /* Staggered Spin-up */
+        HOST_CAP_SNTF           = (1 << 29), /* SNotification register */
         HOST_CAP_NCQ            = (1 << 30), /* Native Command Queueing */
         HOST_CAP_64             = (1 << 31), /* PCI DAC (64-bit DMA) support */
 
@@ -113,11 +114,11 @@ enum {
         PORT_TFDATA             = 0x20, /* taskfile data */
         PORT_SIG                = 0x24, /* device TF signature */
         PORT_CMD_ISSUE          = 0x38, /* command issue */
-        PORT_SCR                = 0x28, /* SATA phy register block */
         PORT_SCR_STAT           = 0x28, /* SATA phy register: SStatus */
         PORT_SCR_CTL            = 0x2c, /* SATA phy register: SControl */
         PORT_SCR_ERR            = 0x30, /* SATA phy register: SError */
         PORT_SCR_ACT            = 0x34, /* SATA phy register: SActive */
+        PORT_SCR_NTF            = 0x3c, /* SATA phy register: SNotification */
 
         /* PORT_IRQ_{STAT,MASK} bits */
         PORT_IRQ_COLD_PRES      = (1 << 31), /* cold presence detect */
@@ -216,8 +217,8 @@ struct ahci_port_priv {
         unsigned int            ncq_saw_sdb:1;
 };
 
-static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
-static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
+static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
+static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
 static void ahci_irq_clear(struct ata_port *ap);
@@ -417,7 +418,10 @@ static const struct pci_device_id ahci_pci_tbl[] = {
 
         /* ATI */
         { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
-        { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700 */
+        { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700 IDE */
+        { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700 AHCI */
+        { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700 nraid5 */
+        { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700 raid5 */
 
         /* VIA */
         { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
@@ -545,13 +549,19 @@ static void ahci_save_initial_config(struct pci_dev *pdev,
         hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
         hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
 
-        /* some chips lie about 64bit support */
+        /* some chips have errata preventing 64bit use */
         if ((cap & HOST_CAP_64) && (pi->flags & AHCI_FLAG_32BIT_ONLY)) {
                 dev_printk(KERN_INFO, &pdev->dev,
                            "controller can't do 64bit DMA, forcing 32bit\n");
                 cap &= ~HOST_CAP_64;
         }
 
+        if ((cap & HOST_CAP_NCQ) && (pi->flags & AHCI_FLAG_NO_NCQ)) {
+                dev_printk(KERN_INFO, &pdev->dev,
+                           "controller can't do NCQ, turning off CAP_NCQ\n");
+                cap &= ~HOST_CAP_NCQ;
+        }
+
         /* fixup zero port_map */
         if (!port_map) {
                 port_map = (1 << ahci_nr_ports(cap)) - 1;
@@ -625,38 +635,45 @@ static void ahci_restore_initial_config(struct ata_host *host)
         (void) readl(mmio + HOST_PORTS_IMPL);   /* flush */
 }
 
-static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
+static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
 {
-        unsigned int sc_reg;
-
-        switch (sc_reg_in) {
-        case SCR_STATUS:        sc_reg = 0; break;
-        case SCR_CONTROL:       sc_reg = 1; break;
-        case SCR_ERROR:         sc_reg = 2; break;
-        case SCR_ACTIVE:        sc_reg = 3; break;
-        default:
-                return 0xffffffffU;
-        }
+        static const int offset[] = {
+                [SCR_STATUS]            = PORT_SCR_STAT,
+                [SCR_CONTROL]           = PORT_SCR_CTL,
+                [SCR_ERROR]             = PORT_SCR_ERR,
+                [SCR_ACTIVE]            = PORT_SCR_ACT,
+                [SCR_NOTIFICATION]      = PORT_SCR_NTF,
+        };
+        struct ahci_host_priv *hpriv = ap->host->private_data;
 
-        return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
+        if (sc_reg < ARRAY_SIZE(offset) &&
+            (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
+                return offset[sc_reg];
+        return 0;
 }
 
-
-static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
-                               u32 val)
+static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
 {
-        unsigned int sc_reg;
-
-        switch (sc_reg_in) {
-        case SCR_STATUS:        sc_reg = 0; break;
-        case SCR_CONTROL:       sc_reg = 1; break;
-        case SCR_ERROR:         sc_reg = 2; break;
-        case SCR_ACTIVE:        sc_reg = 3; break;
-        default:
-                return;
+        void __iomem *port_mmio = ahci_port_base(ap);
+        int offset = ahci_scr_offset(ap, sc_reg);
+
+        if (offset) {
+                *val = readl(port_mmio + offset);
+                return 0;
         }
+        return -EINVAL;
+}
 
-        writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
+static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
+{
+        void __iomem *port_mmio = ahci_port_base(ap);
+        int offset = ahci_scr_offset(ap, sc_reg);
+
+        if (offset) {
+                writel(val, port_mmio + offset);
+                return 0;
+        }
+        return -EINVAL;
 }
 
 static void ahci_start_engine(struct ata_port *ap)
@@ -948,37 +965,87 @@ static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
         pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
 }
 
-static int ahci_clo(struct ata_port *ap)
+static int ahci_kick_engine(struct ata_port *ap, int force_restart)
 {
         void __iomem *port_mmio = ap->ioaddr.cmd_addr;
         struct ahci_host_priv *hpriv = ap->host->private_data;
         u32 tmp;
+        int busy, rc;
+
+        /* do we need to kick the port? */
+        busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
+        if (!busy && !force_restart)
+                return 0;
+
+        /* stop engine */
+        rc = ahci_stop_engine(ap);
+        if (rc)
+                goto out_restart;
 
-        if (!(hpriv->cap & HOST_CAP_CLO))
-                return -EOPNOTSUPP;
+        /* need to do CLO? */
+        if (!busy) {
+                rc = 0;
+                goto out_restart;
+        }
 
+        if (!(hpriv->cap & HOST_CAP_CLO)) {
+                rc = -EOPNOTSUPP;
+                goto out_restart;
+        }
+
+        /* perform CLO */
         tmp = readl(port_mmio + PORT_CMD);
         tmp |= PORT_CMD_CLO;
         writel(tmp, port_mmio + PORT_CMD);
 
+        rc = 0;
         tmp = ata_wait_register(port_mmio + PORT_CMD,
                                 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
         if (tmp & PORT_CMD_CLO)
-                return -EIO;
+                rc = -EIO;
 
-        return 0;
+        /* restart engine */
+ out_restart:
+        ahci_start_engine(ap);
+        return rc;
 }
 
-static int ahci_softreset(struct ata_port *ap, unsigned int *class,
-                          unsigned long deadline)
+static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
+                                struct ata_taskfile *tf, int is_cmd, u16 flags,
+                                unsigned long timeout_msec)
 {
+        const u32 cmd_fis_len = 5; /* five dwords */
         struct ahci_port_priv *pp = ap->private_data;
         void __iomem *port_mmio = ahci_port_base(ap);
-        const u32 cmd_fis_len = 5; /* five dwords */
+        u8 *fis = pp->cmd_tbl;
+        u32 tmp;
+
+        /* prep the command */
+        ata_tf_to_fis(tf, pmp, is_cmd, fis);
+        ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
+
+        /* issue & wait */
+        writel(1, port_mmio + PORT_CMD_ISSUE);
+
+        if (timeout_msec) {
+                tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
+                                        1, timeout_msec);
+                if (tmp & 0x1) {
+                        ahci_kick_engine(ap, 1);
+                        return -EBUSY;
+                }
+        } else
+                readl(port_mmio + PORT_CMD_ISSUE);      /* flush */
+
+        return 0;
+}
+
+static int ahci_do_softreset(struct ata_port *ap, unsigned int *class,
+                             int pmp, unsigned long deadline)
+{
         const char *reason = NULL;
+        unsigned long now, msecs;
         struct ata_taskfile tf;
-        u32 tmp;
-        u8 *fis;
         int rc;
 
         DPRINTK("ENTER\n");
@@ -990,43 +1057,22 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class,
         }
 
         /* prepare for SRST (AHCI-1.1 10.4.1) */
-        rc = ahci_stop_engine(ap);
-        if (rc) {
-                reason = "failed to stop engine";
-                goto fail_restart;
-        }
-
-        /* check BUSY/DRQ, perform Command List Override if necessary */
-        if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
-                rc = ahci_clo(ap);
-
-                if (rc == -EOPNOTSUPP) {
-                        reason = "port busy but CLO unavailable";
-                        goto fail_restart;
-                } else if (rc) {
-                        reason = "port busy but CLO failed";
-                        goto fail_restart;
-                }
-        }
-
-        /* restart engine */
-        ahci_start_engine(ap);
+        rc = ahci_kick_engine(ap, 1);
+        if (rc)
+                ata_port_printk(ap, KERN_WARNING,
+                                "failed to reset engine (errno=%d)", rc);
 
         ata_tf_init(ap->device, &tf);
-        fis = pp->cmd_tbl;
 
         /* issue the first D2H Register FIS */
-        ahci_fill_cmd_slot(pp, 0,
-                           cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
+        msecs = 0;
+        now = jiffies;
+        if (time_after(now, deadline))
+                msecs = jiffies_to_msecs(deadline - now);
 
         tf.ctl |= ATA_SRST;
-        ata_tf_to_fis(&tf, fis, 0);
-        fis[1] &= ~(1 << 7);    /* turn off Command FIS bit */
-
-        writel(1, port_mmio + PORT_CMD_ISSUE);
-
-        tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
-        if (tmp & 0x1) {
+        if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
+                                 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
                 rc = -EIO;
                 reason = "1st FIS failed";
                 goto fail;
@@ -1036,14 +1082,8 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class,
         msleep(1);
 
         /* issue the second D2H Register FIS */
-        ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
-
         tf.ctl &= ~ATA_SRST;
-        ata_tf_to_fis(&tf, fis, 0);
-        fis[1] &= ~(1 << 7);    /* turn off Command FIS bit */
-
-        writel(1, port_mmio + PORT_CMD_ISSUE);
-        readl(port_mmio + PORT_CMD_ISSUE);      /* flush */
+        ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
 
         /* spec mandates ">= 2ms" before checking status.
          * We wait 150ms, because that was the magic delay used for
@@ -1066,13 +1106,17 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class,
         DPRINTK("EXIT, class=%u\n", *class);
         return 0;
 
- fail_restart:
-        ahci_start_engine(ap);
  fail:
         ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
         return rc;
 }
 
+static int ahci_softreset(struct ata_port *ap, unsigned int *class,
+                          unsigned long deadline)
+{
+        return ahci_do_softreset(ap, class, 0, deadline);
+}
+
 static int ahci_hardreset(struct ata_port *ap, unsigned int *class,
                           unsigned long deadline)
 {
@@ -1088,7 +1132,7 @@ static int ahci_hardreset(struct ata_port *ap, unsigned int *class,
         /* clear D2H reception area to properly wait for D2H FIS */
         ata_tf_init(ap->device, &tf);
         tf.command = 0x80;
-        ata_tf_to_fis(&tf, d2h_fis, 0);
+        ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 
         rc = sata_std_hardreset(ap, class, deadline);
 
@@ -1106,6 +1150,7 @@ static int ahci_hardreset(struct ata_port *ap, unsigned int *class,
 static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class,
                                  unsigned long deadline)
 {
+        u32 serror;
         int rc;
 
         DPRINTK("ENTER\n");
@@ -1116,7 +1161,8 @@ static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class,
                                  deadline);
 
         /* vt8251 needs SError cleared for the port to operate */
-        ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
+        ahci_scr_read(ap, SCR_ERROR, &serror);
+        ahci_scr_write(ap, SCR_ERROR, serror);
 
         ahci_start_engine(ap);
 
@@ -1205,7 +1251,7 @@ static void ahci_qc_prep(struct ata_queued_cmd *qc)
          */
         cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
 
-        ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
+        ata_tf_to_fis(&qc->tf, 0, 1, cmd_tbl);
         if (is_atapi) {
                 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
                 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
@@ -1238,7 +1284,7 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
         ata_ehi_clear_desc(ehi);
 
         /* AHCI needs SError cleared; otherwise, it might lock up */
-        serror = ahci_scr_read(ap, SCR_ERROR);
+        ahci_scr_read(ap, SCR_ERROR, &serror);
         ahci_scr_write(ap, SCR_ERROR, serror);
 
         /* analyze @irq_stat */
@@ -1262,12 +1308,12 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
         if (irq_stat & PORT_IRQ_IF_ERR) {
                 err_mask |= AC_ERR_ATA_BUS;
                 action |= ATA_EH_SOFTRESET;
-                ata_ehi_push_desc(ehi, ", interface fatal error");
+                ata_ehi_push_desc(ehi, "interface fatal error");
         }
 
         if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
                 ata_ehi_hotplugged(ehi);
-                ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
+                ata_ehi_push_desc(ehi, "%s", irq_stat & PORT_IRQ_CONNECT ?
                         "connection status changed" : "PHY RDY changed");
         }
 
@@ -1276,7 +1322,7 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
 
                 err_mask |= AC_ERR_HSM;
                 action |= ATA_EH_SOFTRESET;
-                ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
+                ata_ehi_push_desc(ehi, "unknown FIS %08x %08x %08x %08x",
                                   unk[0], unk[1], unk[2], unk[3]);
         }
 
@@ -1512,11 +1558,17 @@ static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
 {
         struct ata_port *ap = qc->ap;
 
-        if (qc->flags & ATA_QCFLAG_FAILED) {
-                /* make DMA engine forget about the failed command */
-                ahci_stop_engine(ap);
-                ahci_start_engine(ap);
-        }
+        /* make DMA engine forget about the failed command */
+        if (qc->flags & ATA_QCFLAG_FAILED)
+                ahci_kick_engine(ap, 1);
+}
+
+static int ahci_port_resume(struct ata_port *ap)
+{
+        ahci_power_up(ap);
+        ahci_start_port(ap);
+
+        return 0;
 }
 
 #ifdef CONFIG_PM
@@ -1536,14 +1588,6 @@ static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
         return rc;
 }
 
-static int ahci_port_resume(struct ata_port *ap)
-{
-        ahci_power_up(ap);
-        ahci_start_port(ap);
-
-        return 0;
-}
-
 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
 {
         struct ata_host *host = dev_get_drvdata(&pdev->dev);
@@ -1734,12 +1778,13 @@ static void ahci_print_info(struct ata_host *host)
 
         dev_printk(KERN_INFO, &pdev->dev,
                 "flags: "
-                "%s%s%s%s%s%s"
-                "%s%s%s%s%s%s%s\n"
+                "%s%s%s%s%s%s%s"
+                "%s%s%s%s%s%s%s\n"
                 ,
 
                 cap & (1 << 31) ? "64bit " : "",
                 cap & (1 << 30) ? "ncq " : "",
+                cap & (1 << 29) ? "sntf " : "",
                 cap & (1 << 28) ? "ilck " : "",
                 cap & (1 << 27) ? "stag " : "",
                 cap & (1 << 26) ? "pm " : "",
@@ -1794,7 +1839,7 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
         ahci_save_initial_config(pdev, &pi, hpriv);
 
         /* prepare host */
-        if (!(pi.flags & AHCI_FLAG_NO_NCQ) && (hpriv->cap & HOST_CAP_NCQ))
+        if (hpriv->cap & HOST_CAP_NCQ)
                 pi.flags |= ATA_FLAG_NCQ;
 
         host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
@@ -1808,10 +1853,8 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
                 void __iomem *port_mmio = ahci_port_base(ap);
 
                 /* standard SATA port setup */
-                if (hpriv->port_map & (1 << i)) {
+                if (hpriv->port_map & (1 << i))
                         ap->ioaddr.cmd_addr = port_mmio;
-                        ap->ioaddr.scr_addr = port_mmio + PORT_SCR;
-                }
 
                 /* disabled/not-implemented port */
                 else