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Diffstat (limited to 'drivers/ata/ahci.c')
-rw-r--r--drivers/ata/ahci.c13
1 files changed, 10 insertions, 3 deletions
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 25929123ffff..234197e57e9e 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -334,6 +334,14 @@ static const struct pci_device_id ahci_pci_tbl[] = {
334 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */ 334 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
335 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */ 335 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
336 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */ 336 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
337 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
338 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
339 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
340 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
341 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
342 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
343 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
344 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
337 345
338 /* SiS */ 346 /* SiS */
339 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ 347 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
@@ -736,8 +744,7 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class)
736 } 744 }
737 745
738 /* check BUSY/DRQ, perform Command List Override if necessary */ 746 /* check BUSY/DRQ, perform Command List Override if necessary */
739 ahci_tf_read(ap, &tf); 747 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
740 if (tf.command & (ATA_BUSY | ATA_DRQ)) {
741 rc = ahci_clo(ap); 748 rc = ahci_clo(ap);
742 749
743 if (rc == -EOPNOTSUPP) { 750 if (rc == -EOPNOTSUPP) {
@@ -1041,7 +1048,7 @@ static void ahci_host_intr(struct ata_port *ap)
1041 /* hmmm... a spurious interupt */ 1048 /* hmmm... a spurious interupt */
1042 1049
1043 /* some devices send D2H reg with I bit set during NCQ command phase */ 1050 /* some devices send D2H reg with I bit set during NCQ command phase */
1044 if (ap->sactive && status & PORT_IRQ_D2H_REG_FIS) 1051 if (ap->sactive && (status & PORT_IRQ_D2H_REG_FIS))
1045 return; 1052 return;
1046 1053
1047 /* ignore interim PIO setup fis interrupts */ 1054 /* ignore interim PIO setup fis interrupts */