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path: root/drivers/acpi/executer/exmutex.c
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Diffstat (limited to 'drivers/acpi/executer/exmutex.c')
-rw-r--r--drivers/acpi/executer/exmutex.c26
1 files changed, 20 insertions, 6 deletions
diff --git a/drivers/acpi/executer/exmutex.c b/drivers/acpi/executer/exmutex.c
index 89b8ab79410b..f843b22e20b9 100644
--- a/drivers/acpi/executer/exmutex.c
+++ b/drivers/acpi/executer/exmutex.c
@@ -153,7 +153,9 @@ acpi_ex_acquire_mutex(union acpi_operand_object *time_desc,
153 /* Sanity check -- we must have a valid thread ID */ 153 /* Sanity check -- we must have a valid thread ID */
154 154
155 if (!walk_state->thread) { 155 if (!walk_state->thread) {
156 ACPI_REPORT_ERROR(("Cannot acquire Mutex [%4.4s], null thread info\n", acpi_ut_get_node_name(obj_desc->mutex.node))); 156 ACPI_ERROR((AE_INFO,
157 "Cannot acquire Mutex [%4.4s], null thread info",
158 acpi_ut_get_node_name(obj_desc->mutex.node)));
157 return_ACPI_STATUS(AE_AML_INTERNAL); 159 return_ACPI_STATUS(AE_AML_INTERNAL);
158 } 160 }
159 161
@@ -162,7 +164,9 @@ acpi_ex_acquire_mutex(union acpi_operand_object *time_desc,
162 * mutex. This mechanism provides some deadlock prevention 164 * mutex. This mechanism provides some deadlock prevention
163 */ 165 */
164 if (walk_state->thread->current_sync_level > obj_desc->mutex.sync_level) { 166 if (walk_state->thread->current_sync_level > obj_desc->mutex.sync_level) {
165 ACPI_REPORT_ERROR(("Cannot acquire Mutex [%4.4s], incorrect sync_level\n", acpi_ut_get_node_name(obj_desc->mutex.node))); 167 ACPI_ERROR((AE_INFO,
168 "Cannot acquire Mutex [%4.4s], incorrect sync_level",
169 acpi_ut_get_node_name(obj_desc->mutex.node)));
166 return_ACPI_STATUS(AE_AML_MUTEX_ORDER); 170 return_ACPI_STATUS(AE_AML_MUTEX_ORDER);
167 } 171 }
168 172
@@ -237,14 +241,18 @@ acpi_ex_release_mutex(union acpi_operand_object *obj_desc,
237 /* The mutex must have been previously acquired in order to release it */ 241 /* The mutex must have been previously acquired in order to release it */
238 242
239 if (!obj_desc->mutex.owner_thread) { 243 if (!obj_desc->mutex.owner_thread) {
240 ACPI_REPORT_ERROR(("Cannot release Mutex [%4.4s], not acquired\n", acpi_ut_get_node_name(obj_desc->mutex.node))); 244 ACPI_ERROR((AE_INFO,
245 "Cannot release Mutex [%4.4s], not acquired",
246 acpi_ut_get_node_name(obj_desc->mutex.node)));
241 return_ACPI_STATUS(AE_AML_MUTEX_NOT_ACQUIRED); 247 return_ACPI_STATUS(AE_AML_MUTEX_NOT_ACQUIRED);
242 } 248 }
243 249
244 /* Sanity check -- we must have a valid thread ID */ 250 /* Sanity check -- we must have a valid thread ID */
245 251
246 if (!walk_state->thread) { 252 if (!walk_state->thread) {
247 ACPI_REPORT_ERROR(("Cannot release Mutex [%4.4s], null thread info\n", acpi_ut_get_node_name(obj_desc->mutex.node))); 253 ACPI_ERROR((AE_INFO,
254 "Cannot release Mutex [%4.4s], null thread info",
255 acpi_ut_get_node_name(obj_desc->mutex.node)));
248 return_ACPI_STATUS(AE_AML_INTERNAL); 256 return_ACPI_STATUS(AE_AML_INTERNAL);
249 } 257 }
250 258
@@ -255,7 +263,11 @@ acpi_ex_release_mutex(union acpi_operand_object *obj_desc,
255 if ((obj_desc->mutex.owner_thread->thread_id != 263 if ((obj_desc->mutex.owner_thread->thread_id !=
256 walk_state->thread->thread_id) 264 walk_state->thread->thread_id)
257 && (obj_desc->mutex.semaphore != acpi_gbl_global_lock_semaphore)) { 265 && (obj_desc->mutex.semaphore != acpi_gbl_global_lock_semaphore)) {
258 ACPI_REPORT_ERROR(("Thread %X cannot release Mutex [%4.4s] acquired by thread %X\n", walk_state->thread->thread_id, acpi_ut_get_node_name(obj_desc->mutex.node), obj_desc->mutex.owner_thread->thread_id)); 266 ACPI_ERROR((AE_INFO,
267 "Thread %X cannot release Mutex [%4.4s] acquired by thread %X",
268 walk_state->thread->thread_id,
269 acpi_ut_get_node_name(obj_desc->mutex.node),
270 obj_desc->mutex.owner_thread->thread_id));
259 return_ACPI_STATUS(AE_AML_NOT_OWNER); 271 return_ACPI_STATUS(AE_AML_NOT_OWNER);
260 } 272 }
261 273
@@ -264,7 +276,9 @@ acpi_ex_release_mutex(union acpi_operand_object *obj_desc,
264 * equal to the current sync level 276 * equal to the current sync level
265 */ 277 */
266 if (obj_desc->mutex.sync_level > walk_state->thread->current_sync_level) { 278 if (obj_desc->mutex.sync_level > walk_state->thread->current_sync_level) {
267 ACPI_REPORT_ERROR(("Cannot release Mutex [%4.4s], incorrect sync_level\n", acpi_ut_get_node_name(obj_desc->mutex.node))); 279 ACPI_ERROR((AE_INFO,
280 "Cannot release Mutex [%4.4s], incorrect sync_level",
281 acpi_ut_get_node_name(obj_desc->mutex.node)));
268 return_ACPI_STATUS(AE_AML_MUTEX_ORDER); 282 return_ACPI_STATUS(AE_AML_MUTEX_ORDER);
269 } 283 }
270 284
an>,0x10}, // TV Output Control Register {0x0062,0x00}, // CRT/TV Display Start Address Register 0 {0x0063,0x00}, // CRT/TV Display Start Address Register 1 {0x0064,0x00}, // CRT/TV Display Start Address Register 2 {0x0068,0x00}, // CRT/TV Pixel Panning Register {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register {0x0070,0x00}, // LCD Ink/Cursor Control Register {0x0071,0x01}, // LCD Ink/Cursor Start Address Register {0x0072,0x00}, // LCD Cursor X Position Register 0 {0x0073,0x00}, // LCD Cursor X Position Register 1 {0x0074,0x00}, // LCD Cursor Y Position Register 0 {0x0075,0x00}, // LCD Cursor Y Position Register 1 {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register {0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register {0x0082,0x00}, // CRT/TV Cursor X Position Register 0 {0x0083,0x00}, // CRT/TV Cursor X Position Register 1 {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0 {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1 {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register {0x0100,0x00}, // BitBlt Control Register 0 {0x0101,0x00}, // BitBlt Control Register 1 {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register {0x0103,0x00}, // BitBlt Operation Register {0x0104,0x00}, // BitBlt Source Start Address Register 0 {0x0105,0x00}, // BitBlt Source Start Address Register 1 {0x0106,0x00}, // BitBlt Source Start Address Register 2 {0x0108,0x00}, // BitBlt Destination Start Address Register 0 {0x0109,0x00}, // BitBlt Destination Start Address Register 1 {0x010A,0x00}, // BitBlt Destination Start Address Register 2 {0x010C,0x00}, // BitBlt Memory Address Offset Register 0 {0x010D,0x00}, // BitBlt Memory Address Offset Register 1 {0x0110,0x00}, // BitBlt Width Register 0 {0x0111,0x00}, // BitBlt Width Register 1 {0x0112,0x00}, // BitBlt Height Register 0 {0x0113,0x00}, // BitBlt Height Register 1 {0x0114,0x00}, // BitBlt Background Color Register 0 {0x0115,0x00}, // BitBlt Background Color Register 1 {0x0118,0x00}, // BitBlt Foreground Color Register 0 {0x0119,0x00}, // BitBlt Foreground Color Register 1 {0x01E0,0x00}, // Look-Up Table Mode Register {0x01E2,0x00}, // Look-Up Table Address Register {0x01F0,0x10}, // Power Save Configuration Register {0x01F1,0x00}, // Power Save Status Register {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register #if (SWIVEL_VIEW == 0) {0x01FC,0x01}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT) #elif (SWIVEL_VIEW == 1) {0x01FC,0x41}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT) #else #error unsupported SWIVEL_VIEW mode #endif /* SWIVEL_VIEW */ #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3) {0x0008,0x07}, // LCD panel Vdd & Vg on #endif {0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp) #if defined(CONFIG_PLAT_MAPPI) {0x0046,0x80}, // LCD Memory Address Offset Register 0 {0x0047,0x02}, // LCD Memory Address Offset Register 1 #elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3) {0x0046,0xf0}, // LCD Memory Address Offset Register 0 {0x0047,0x00}, // LCD Memory Address Offset Register 1 #endif {0x0060,0x05}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp) {0x0066,0x80}, // CRT/TV Memory Address Offset Register 0 // takeo {0x0067,0x02}, // CRT/TV Memory Address Offset Register 1 };