367 files changed, 5201 insertions, 5004 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e25419817791..ae5d6152d977 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -306,9 +306,12 @@ choice
 config ARCH_MULTIPLATFORM
         bool "Allow multiple platforms to be selected"
         depends on MMU
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARM_HAS_SG_CHAIN
         select ARM_PATCH_PHYS_VIRT
         select AUTO_ZRELADDR
         select COMMON_CLK
+        select GENERIC_CLOCKEVENTS
         select MULTI_IRQ_HANDLER
         select SPARSE_IRQ
         select USE_OF
@@ -388,8 +391,6 @@ config ARCH_CLPS711X
         select CPU_ARM720T
         select GENERIC_CLOCKEVENTS
         select MFD_SYSCON
-        select MULTI_IRQ_HANDLER
-        select SPARSE_IRQ
         help
           Support for Cirrus Logic 711x/721x/731x based boards.
 
@@ -657,9 +658,8 @@ config ARCH_PXA
         help
           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 
-config ARCH_MSM_NODT
-        bool "Qualcomm MSM"
-        select ARCH_MSM
+config ARCH_MSM
+        bool "Qualcomm MSM (non-multiplatform)"
         select ARCH_REQUIRE_GPIOLIB
         select COMMON_CLK
         select GENERIC_CLOCKEVENTS
@@ -898,7 +898,7 @@ config ARCH_MULTI_V5
         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
         depends on !ARCH_MULTI_V6_V7
         select ARCH_MULTI_V4_V5
-        select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
+        select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 
@@ -908,16 +908,18 @@ config ARCH_MULTI_V4_V5
 config ARCH_MULTI_V6
         bool "ARMv6 based platforms (ARM11)"
         select ARCH_MULTI_V6_V7
-        select CPU_V6
+        select CPU_V6K
 
 config ARCH_MULTI_V7
         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
         default y
         select ARCH_MULTI_V6_V7
         select CPU_V7
+        select HAVE_SMP
 
 config ARCH_MULTI_V6_V7
         bool
+        select MIGHT_HAVE_CACHE_L2X0
 
 config ARCH_MULTI_CPU_AUTO
         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
@@ -925,6 +927,13 @@ config ARCH_MULTI_CPU_AUTO
 
 endmenu
 
+config ARCH_VIRT
+        bool "Dummy Virtual Machine" if ARCH_MULTI_V7
+        select ARM_AMBA
+        select ARM_GIC
+        select ARM_PSCI
+        select HAVE_ARM_ARCH_TIMER
+
 #
 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 # Kconfigs may be included either alphabetically (according to the
@@ -1005,6 +1014,8 @@ source "arch/arm/plat-pxa/Kconfig"
 
 source "arch/arm/mach-mmp/Kconfig"
 
+source "arch/arm/mach-qcom/Kconfig"
+
 source "arch/arm/mach-realview/Kconfig"
 
 source "arch/arm/mach-rockchip/Kconfig"
@@ -1048,8 +1059,6 @@ source "arch/arm/mach-versatile/Kconfig"
 source "arch/arm/mach-vexpress/Kconfig"
 source "arch/arm/plat-versatile/Kconfig"
 
-source "arch/arm/mach-virt/Kconfig"
-
 source "arch/arm/mach-vt8500/Kconfig"
 
 source "arch/arm/mach-w90x900/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 0531da8e5216..ceecb66cb1e3 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -106,9 +106,14 @@ choice
                 depends on ARCH_BCM2835
                 select DEBUG_UART_PL01X
 
+        config DEBUG_BCM_5301X
+                bool "Kernel low-level debugging on BCM5301X UART1"
+                depends on ARCH_BCM_5301X
+                select DEBUG_UART_PL01X
+
         config DEBUG_BCM_KONA_UART
                 bool "Kernel low-level debugging messages via BCM KONA UART"
-                depends on ARCH_BCM
+                depends on ARCH_BCM_MOBILE
                 select DEBUG_UART_8250
                 help
                   Say Y here if you want kernel low-level debugging support
@@ -171,15 +176,6 @@ choice
                   Say Y here if you want the debug print routines to direct
                   their output to UART0 serial port on DaVinci DMx devices.
 
-        config DEBUG_DAVINCI_TNETV107X_UART1
-                bool "Kernel low-level debugging on DaVinci TNETV107x using UART1"
-                depends on ARCH_DAVINCI_TNETV107X
-                select DEBUG_UART_8250
-                help
-                  Say Y here if you want the debug print routines to direct
-                  their output to UART1 serial port on DaVinci TNETV107X
-                  devices.
-
         config DEBUG_ZYNQ_UART0
                 bool "Kernel low-level debugging on Xilinx Zynq using UART0"
                 depends on ARCH_ZYNQ
@@ -956,7 +952,7 @@ config DEBUG_STI_UART
 
 config DEBUG_MSM_UART
         bool
-        depends on ARCH_MSM
+        depends on ARCH_MSM || ARCH_QCOM
 
 config DEBUG_LL_INCLUDE
         string
@@ -1014,7 +1010,6 @@ config DEBUG_UART_PHYS
         default 0x02530c00 if DEBUG_KEYSTONE_UART0
         default 0x02531000 if DEBUG_KEYSTONE_UART1
         default 0x03010fe0 if ARCH_RPC
-        default 0x08108300 if DEBUG_DAVINCI_TNETV107X_UART1
         default 0x10009000 if DEBUG_REALVIEW_STD_PORT || DEBUG_CNS3XXX || \
                                 DEBUG_VEXPRESS_UART0_CA9
         default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT
@@ -1023,6 +1018,7 @@ config DEBUG_UART_PHYS
         default 0x101f1000 if ARCH_VERSATILE
         default 0x101fb000 if DEBUG_NOMADIK_UART
         default 0x16000000 if ARCH_INTEGRATOR
+        default 0x18000300 if DEBUG_BCM_5301X
         default 0x1c090000 if DEBUG_VEXPRESS_UART0_RS1
         default 0x20060000 if DEBUG_RK29_UART0
         default 0x20064000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
@@ -1071,6 +1067,7 @@ config DEBUG_UART_VIRT
         default 0xf0009000 if DEBUG_CNS3XXX
         default 0xf01fb000 if DEBUG_NOMADIK_UART
         default 0xf0201000 if DEBUG_BCM2835
+        default 0xf1000300 if DEBUG_BCM_5301X
         default 0xf11f1000 if ARCH_VERSATILE
         default 0xf1600000 if ARCH_INTEGRATOR
         default 0xf1c28000 if DEBUG_SUNXI_UART0
@@ -1110,7 +1107,6 @@ config DEBUG_UART_VIRT
         default 0xfed12000 if ARCH_KIRKWOOD
         default 0xfedc0000 if ARCH_EP93XX
         default 0xfee003f8 if FOOTBRIDGE
-        default 0xfee08300 if DEBUG_DAVINCI_TNETV107X_UART1
         default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
         default 0xfef36000 if DEBUG_HIGHBANK_UART
         default 0xfee82340 if ARCH_IOP13XX
@@ -1135,7 +1131,7 @@ config DEBUG_UART_8250_WORD
         default y if DEBUG_PICOXCELL_UART || DEBUG_SOCFPGA_UART || \
                 ARCH_KEYSTONE || \
                 DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
-                DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_DAVINCI_TNETV107X_UART1 || \
+                DEBUG_DAVINCI_DA8XX_UART2 || \
                 DEBUG_BCM_KONA_UART
 
 config DEBUG_UART_8250_FLOW_CONTROL
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 08a9ef58d9c3..dd1bd7ed77be 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -180,6 +180,7 @@ machine-$(CONFIG_ARCH_OMAP2PLUS)	+= omap2
 machine-$(CONFIG_ARCH_ORION5X)          += orion5x
 machine-$(CONFIG_ARCH_PICOXCELL)        += picoxcell
 machine-$(CONFIG_ARCH_PXA)              += pxa
+machine-$(CONFIG_ARCH_QCOM)             += qcom
 machine-$(CONFIG_ARCH_REALVIEW)         += realview
 machine-$(CONFIG_ARCH_ROCKCHIP)         += rockchip
 machine-$(CONFIG_ARCH_RPC)              += rpc
@@ -199,7 +200,6 @@ machine-$(CONFIG_ARCH_U300)		+= u300
 machine-$(CONFIG_ARCH_U8500)            += ux500
 machine-$(CONFIG_ARCH_VERSATILE)        += versatile
 machine-$(CONFIG_ARCH_VEXPRESS)         += vexpress
-machine-$(CONFIG_ARCH_VIRT)             += virt
 machine-$(CONFIG_ARCH_VT8500)           += vt8500
 machine-$(CONFIG_ARCH_W90X900)          += w90x900
 machine-$(CONFIG_ARCH_ZYNQ)             += zynq
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9d6a8b485e0..f8581e49982c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -38,6 +38,7 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
 # sama5d3
+dtb-$(CONFIG_ARCH_AT91) += at91-sama5d3_xplained.dtb
 dtb-$(CONFIG_ARCH_AT91) += sama5d31ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
@@ -54,7 +55,7 @@ dtb-$(CONFIG_ARCH_BERLIN) += \
         berlin2cd-google-chromecast.dtb
 dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
         da850-evm.dtb
-dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
+dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
         dove-cubox.dtb \
         dove-d2plug.dtb \
         dove-d3plug.dtb \
@@ -81,8 +82,8 @@ dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
         ecx-2000.dtb
 dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
         integratorcp.dtb
-dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
-dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
+kirkwood := \
+        kirkwood-cloudbox.dtb \
         kirkwood-db-88f6281.dtb \
         kirkwood-db-88f6282.dtb \
         kirkwood-dns320.dtb \
@@ -116,11 +117,11 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
         kirkwood-topkick.dtb \
         kirkwood-ts219-6281.dtb \
         kirkwood-ts219-6282.dtb
+dtb-$(CONFIG_ARCH_KIRKWOOD) += $(kirkwood)
+dtb-$(CONFIG_MACH_KIRKWOOD) += $(kirkwood)
+dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
 dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
 dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
-dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \
-        qcom-msm8960-cdp.dtb \
-        qcom-apq8074-dragonboard.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
         armada-370-mirabox.dtb \
         armada-370-netgear-rn102.dtb \
@@ -208,7 +209,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
         omap3-n900.dtb \
         omap3-n9.dtb \
         omap3-n950.dtb \
-        omap3-tobi.dtb \
+        omap3-overo-tobi.dtb \
+        omap3-overo-storm-tobi.dtb \
         omap3-gta04.dtb \
         omap3-igep0020.dtb \
         omap3-igep0030.dtb \
@@ -232,6 +234,9 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
         dra7-evm.dtb
 dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
+        qcom-msm8960-cdp.dtb \
+        qcom-apq8074-dragonboard.dtb
 dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
         ste-hrefprev60-stuib.dtb \
         ste-hrefprev60-tvk.dtb \
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 4718ec4a4dbf..486880b74831 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -121,7 +121,7 @@
                 ti,model = "AM335x-EVMSK";
                 ti,audio-codec = <&tlv320aic3106>;
                 ti,mcasp-controller = <&mcasp1>;
-                ti,codec-clock-rate = <24576000>;
+                ti,codec-clock-rate = <24000000>;
                 ti,audio-routing =
                         "Headphone Jack",       "HPLOUT",
                         "Headphone Jack",       "HPROUT";
@@ -256,6 +256,12 @@
                 >;
         };
 
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+                >;
+        };
+
         mcasp1_pins: mcasp1_pins {
                 pinctrl-single,pins = <
                         0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
@@ -456,6 +462,9 @@
         status = "okay";
         vmmc-supply = <&vmmc_reg>;
         bus-width = <4>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
 };
 
 &sham {
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 66609684d41b..9480cf891f8c 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -23,6 +23,7 @@
                 gpio0 = &gpio0;
                 gpio1 = &gpio1;
                 gpio2 = &gpio2;
+                eth3 = &eth3;
         };
 
         cpus {
@@ -291,7 +292,7 @@
                                 interrupts = <91>;
                         };
 
-                        ethernet@34000 {
+                        eth3: ethernet@34000 {
                                 compatible = "marvell,armada-370-neta";
                                 reg = <0x34000 0x4000>;
                                 interrupts = <14>;
diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
new file mode 100644
index 000000000000..ce1375595e5f
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
@@ -0,0 +1,229 @@
+/*
+ * at91-sama5d3_xplained.dts - Device Tree file for the SAMA5D3 Xplained board
+ *
+ *  Copyright (C) 2014 Atmel,
+ *                2014 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+#include "sama5d36.dtsi"
+
+/ {
+        model = "SAMA5D3 Xplained";
+        compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5";
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+
+        memory {
+                reg = <0x20000000 0x10000000>;
+        };
+
+        ahb {
+                apb {
+                        mmc0: mmc@f0000000 {
+                                pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <8>;
+                                        cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>;
+                                };
+                        };
+
+                        spi0: spi@f0004000 {
+                                cs-gpios = <&pioD 13 0>;
+                                status = "okay";
+                        };
+
+                        can0: can@f000c000 {
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@f0014000 {
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@f0018000 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@f0028000 {
+                                phy-mode = "rgmii";
+                                status = "okay";
+                        };
+
+                        usart0: serial@f001c000 {
+                                status = "okay";
+                        };
+
+                        usart1: serial@f0020000 {
+                                pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
+                                status = "okay";
+                        };
+
+                        uart0: serial@f0024000 {
+                                status = "okay";
+                        };
+
+                        mmc1: mmc@f8000000 {
+                                pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioE 1 GPIO_ACTIVE_HIGH>;
+                                };
+                        };
+
+                        spi1: spi@f8008000 {
+                                cs-gpios = <&pioC 25 0>, <0>, <0>, <&pioD 16 0>;
+                                status = "okay";
+                        };
+
+                        adc0: adc@f8018000 {
+                                pinctrl-0 = <
+                                        &pinctrl_adc0_adtrg
+                                        &pinctrl_adc0_ad0
+                                        &pinctrl_adc0_ad1
+                                        &pinctrl_adc0_ad2
+                                        &pinctrl_adc0_ad3
+                                        &pinctrl_adc0_ad4
+                                        &pinctrl_adc0_ad5
+                                        &pinctrl_adc0_ad6
+                                        &pinctrl_adc0_ad7
+                                        &pinctrl_adc0_ad8
+                                        &pinctrl_adc0_ad9
+                                        >;
+                                status = "okay";
+                        };
+
+                        i2c2: i2c@f801c000 {
+                                dmas = <0>, <0>;        /* Do not use DMA for i2c2 */
+                                status = "okay";
+                        };
+
+                        macb1: ethernet@f802c000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        dbgu: serial@ffffee00 {
+                                status = "okay";
+                        };
+
+                        pinctrl@fffff200 {
+                                board {
+                                        pinctrl_mmc0_cd: mmc0_cd {
+                                                atmel,pins =
+                                                        <AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+                                        };
+
+                                        pinctrl_mmc1_cd: mmc1_cd {
+                                                atmel,pins =
+                                                        <AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+                                        };
+
+                                        pinctrl_usba_vbus: usba_vbus {
+                                                atmel,pins =
+                                                        <AT91_PIOE 9 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;   /* PE9, conflicts with A9 */
+                                        };
+                                };
+                        };
+
+                        pmc: pmc@fffffc00 {
+                                main: mainck {
+                                        clock-frequency = <12000000>;
+                                };
+                        };
+                };
+
+                nand0: nand@60000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "hw";
+                        atmel,has-pmecc;
+                        atmel,pmecc-cap = <4>;
+                        atmel,pmecc-sector-size = <512>;
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x40000>;
+                        };
+
+                        bootloader@40000 {
+                                label = "bootloader";
+                                reg = <0x40000 0x80000>;
+                        };
+
+                        bootloaderenv@c0000 {
+                                label = "bootloader env";
+                                reg = <0xc0000 0xc0000>;
+                        };
+
+                        dtb@180000 {
+                                label = "device tree";
+                                reg = <0x180000 0x80000>;
+                        };
+
+                        kernel@200000 {
+                                label = "kernel";
+                                reg = <0x200000 0x600000>;
+                        };
+
+                        rootfs@800000 {
+                                label = "rootfs";
+                                reg = <0x800000 0x0f800000>;
+                        };
+                };
+
+                usb0: gadget@00500000 {
+                        atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>;   /* PE9, conflicts with A9 */
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usba_vbus>;
+                        status = "okay";
+                };
+
+                usb1: ohci@00600000 {
+                        num-ports = <3>;
+                        atmel,vbus-gpio = <0
+                                           &pioE 3 GPIO_ACTIVE_LOW
+                                           &pioE 4 GPIO_ACTIVE_LOW
+                                          >;
+                        status = "okay";
+                };
+
+                usb2: ehci@00700000 {
+                        status = "okay";
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+
+                bp3 {
+                        label = "PB_USER";
+                        gpios = <&pioE 29 GPIO_ACTIVE_LOW>;
+                        linux,code = <0x104>;
+                        gpio-key,wakeup;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                d2 {
+                        label = "d2";
+                        gpios = <&pioE 23 GPIO_ACTIVE_LOW>;     /* PE23, conflicts with A23, CTS2 */
+                        linux,default-trigger = "heartbeat";
+                };
+
+                d3 {
+                        label = "d3";
+                        gpios = <&pioE 24 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 0042f73068b0..fece8665fb63 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -523,7 +523,7 @@
                         };
 
                         i2c0: i2c@fff88000 {
-                                compatible = "atmel,at91sam9263-i2c";
+                                compatible = "atmel,at91sam9260-i2c";
                                 reg = <0xfff88000 0x100>;
                                 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
                                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index e9487f6f0166..924a6a6ffd0f 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -124,6 +124,10 @@
                         nand-on-flash-bbt;
                         status = "okay";
                 };
+
+                usb0: ohci@00500000 {
+                        status = "okay";
+                };
         };
 
         leds {
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 2b76524f4aa7..187fd46b7b5e 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -379,15 +379,6 @@
                                 #clock-cells = <1>;
                         };
 
-                        pmu_intc: pmu-interrupt-ctrl@d0050 {
-                                compatible = "marvell,dove-pmu-intc";
-                                interrupt-controller;
-                                #interrupt-cells = <1>;
-                                reg = <0xd0050 0x8>;
-                                interrupts = <33>;
-                                marvell,#interrupts = <7>;
-                        };
-
                         pinctrl: pin-ctrl@d0200 {
                                 compatible = "marvell,dove-pinctrl";
                                 reg = <0xd0200 0x10>;
@@ -610,8 +601,6 @@
                         rtc: real-time-clock@d8500 {
                                 compatible = "marvell,orion-rtc";
                                 reg = <0xd8500 0x20>;
-                                interrupt-parent = <&pmu_intc>;
-                                interrupts = <5>;
                         };
 
                         gpio2: gpio-ctrl@e8400 {
diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts
index fd8fc7cd53f3..5bfae54fb780 100644
--- a/arch/arm/boot/dts/imx6dl-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts
@@ -52,12 +52,6 @@
                 };
         };
 
-        codec: spdif-transmitter {
-                compatible = "linux,spdif-dit";
-                pinctrl-names = "default";
-                pinctrl-0 = <&pinctrl_hummingboard_spdif>;
-        };
-
         sound-spdif {
                 compatible = "fsl,imx-audio-spdif";
                 model = "imx-spdif";
@@ -111,7 +105,7 @@
                 };
 
                 pinctrl_hummingboard_spdif: hummingboard-spdif {
-                        fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0>;
+                        fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
                 };
 
                 pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
@@ -142,6 +136,8 @@
 };
 
 &spdif {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hummingboard_spdif>;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
index 64daa3b311f6..c2a24888a276 100644
--- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
@@ -46,12 +46,6 @@
                 };
         };
 
-        codec: spdif-transmitter {
-                compatible = "linux,spdif-dit";
-                pinctrl-names = "default";
-                pinctrl-0 = <&pinctrl_cubox_i_spdif>;
-        };
-
         sound-spdif {
                 compatible = "fsl,imx-audio-spdif";
                 model = "imx-spdif";
@@ -89,7 +83,7 @@
                 };
 
                 pinctrl_cubox_i_spdif: cubox-i-spdif {
-                        fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0>;
+                        fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
                 };
 
                 pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus {
@@ -121,6 +115,8 @@
 };
 
 &spdif {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_cubox_i_spdif>;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
index dc86429756d7..2cb0dc529165 100644
--- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
+++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
@@ -122,4 +122,66 @@
                         gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
                 };
         };
+
+        dsa@0 {
+                compatible = "marvell,dsa";
+                #address-cells = <2>;
+                #size-cells = <0>;
+
+                dsa,ethernet = <&eth0>;
+                dsa,mii-bus = <&ethphy0>;
+
+                switch@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0 0>;    /* MDIO address 0, switch 0 in tree */
+
+                        port@0 {
+                                reg = <0>;
+                                label = "lan1";
+                        };
+
+                        port@1 {
+                                reg = <1>;
+                                label = "lan2";
+                        };
+
+                        port@2 {
+                                reg = <2>;
+                                label = "lan3";
+                        };
+
+                        port@3 {
+                                reg = <3>;
+                                label = "lan4";
+                        };
+
+                        port@4 {
+                                reg = <4>;
+                                label = "wan";
+                        };
+
+                        port@5 {
+                                reg = <5>;
+                                label = "cpu";
+                        };
+                };
+        };
+};
+
+&mdio {
+        status = "okay";
+
+        ethphy0: ethernet-phy@ff {
+                reg = <0xff>;   /* No phy attached */
+                speed = <1000>;
+                duplex = <1>;
+        };
+};
+
+&eth0 {
+        status = "okay";
+        ethernet0-port@0 {
+                phy-handle = <&ethphy0>;
+        };
 };
diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts
index b9b55c95a566..c551e4af4d83 100644
--- a/arch/arm/boot/dts/omap3-gta04.dts
+++ b/arch/arm/boot/dts/omap3-gta04.dts
@@ -32,7 +32,7 @@
                 aux-button {
                         label = "aux";
                         linux,code = <169>;
-                        gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
                         gpio-key,wakeup;
                 };
         };
@@ -92,6 +92,8 @@
         bmp085@77 {
                 compatible = "bosch,bmp085";
                 reg = <0x77>;
+                interrupt-parent = <&gpio4>;
+                interrupts = <17 IRQ_TYPE_EDGE_RISING>;
         };
 
         /* leds */
@@ -141,8 +143,8 @@
         pinctrl-names = "default";
         pinctrl-0 = <&mmc1_pins>;
         vmmc-supply = <&vmmc1>;
-        vmmc_aux-supply = <&vsim>;
         bus-width = <4>;
+        ti,non-removable;
 };
 
 &mmc2 {
diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts
index 39828ce464ee..9938b5dc1909 100644
--- a/arch/arm/boot/dts/omap3-n9.dts
+++ b/arch/arm/boot/dts/omap3-n9.dts
@@ -14,5 +14,5 @@
 
 / {
         model = "Nokia N9";
-        compatible = "nokia,omap3-n9", "ti,omap3";
+        compatible = "nokia,omap3-n9", "ti,omap36xx", "ti,omap3";
 };
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 6fc85f963530..0bf40c90faba 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2013 Pavel Machek <pavel@ucw.cz>
- * Copyright 2013 Aaro Koskinen <aaro.koskinen@iki.fi>
+ * Copyright (C) 2013-2014 Aaro Koskinen <aaro.koskinen@iki.fi>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 (or later) as
@@ -13,7 +13,7 @@
 
 / {
         model = "Nokia N900";
-        compatible = "nokia,omap3-n900", "ti,omap3";
+        compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
 
         cpus {
                 cpu@0 {
diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts
index b076a526b999..261c5589bfa3 100644
--- a/arch/arm/boot/dts/omap3-n950.dts
+++ b/arch/arm/boot/dts/omap3-n950.dts
@@ -14,5 +14,5 @@
 
 / {
         model = "Nokia N950";
-        compatible = "nokia,omap3-n950", "ti,omap3";
+        compatible = "nokia,omap3-n950", "ti,omap36xx", "ti,omap3";
 };
diff --git a/arch/arm/boot/dts/omap3-overo-storm-tobi.dts b/arch/arm/boot/dts/omap3-overo-storm-tobi.dts
new file mode 100644
index 000000000000..966b5c9cd96a
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-storm-tobi.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Tobi expansion board is manufactured by Gumstix Inc.
+ */
+
+/dts-v1/;
+
+#include "omap36xx.dtsi"
+#include "omap3-overo-tobi-common.dtsi"
+
+/ {
+        model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Tobi";
+        compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap36xx", "ti,omap3";
+};
+
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi
index 7e4ad2aec37a..4edc013a91c1 100644
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ b/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi
@@ -13,9 +13,6 @@
 #include "omap3-overo.dtsi"
 
 / {
-        model = "TI OMAP3 Gumstix Overo on Tobi";
-        compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3";
-
         leds {
                 compatible = "gpio-leds";
                 heartbeat {
diff --git a/arch/arm/boot/dts/omap3-overo-tobi.dts b/arch/arm/boot/dts/omap3-overo-tobi.dts
new file mode 100644
index 000000000000..de5653e1b5ca
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo-tobi.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Tobi expansion board is manufactured by Gumstix Inc.
+ */
+
+/dts-v1/;
+
+#include "omap34xx.dtsi"
+#include "omap3-overo-tobi-common.dtsi"
+
+/ {
+        model = "OMAP35xx Gumstix Overo on Tobi";
+        compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3";
+};
+
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
index a461d2fd1fb0..597099907f8e 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -9,9 +9,6 @@
 /*
  * The Gumstix Overo must be combined with an expansion board.
  */
-/dts-v1/;
-
-#include "omap34xx.dtsi"
 
 / {
         pwmleds {
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index 68a72f5507b9..169bad90dac9 100644
--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
@@ -1,63 +1,6 @@
-/dts-v1/;
-
-/include/ "skeleton.dtsi"
-
-#include <dt-bindings/clock/qcom,gcc-msm8660.h>
+#include "qcom-msm8660.dtsi"
 
 / {
         model = "Qualcomm MSM8660 SURF";
         compatible = "qcom,msm8660-surf", "qcom,msm8660";
-        interrupt-parent = <&intc>;
-
-        intc: interrupt-controller@2080000 {
-                compatible = "qcom,msm-8660-qgic";
-                interrupt-controller;
-                #interrupt-cells = <3>;
-                reg = < 0x02080000 0x1000 >,
-                      < 0x02081000 0x1000 >;
-        };
-
-        timer@2000000 {
-                compatible = "qcom,scss-timer", "qcom,msm-timer";
-                interrupts = <1 0 0x301>,
-                             <1 1 0x301>,
-                             <1 2 0x301>;
-                reg = <0x02000000 0x100>;
-                clock-frequency = <27000000>,
-                                  <32768>;
-                cpu-offset = <0x40000>;
-        };
-
-        msmgpio: gpio@800000 {
-                compatible = "qcom,msm-gpio";
-                reg = <0x00800000 0x4000>;
-                gpio-controller;
-                #gpio-cells = <2>;
-                ngpio = <173>;
-                interrupts = <0 16 0x4>;
-                interrupt-controller;
-                #interrupt-cells = <2>;
-        };
-
-        gcc: clock-controller@900000 {
-                compatible = "qcom,gcc-msm8660";
-                #clock-cells = <1>;
-                #reset-cells = <1>;
-                reg = <0x900000 0x4000>;
-        };
-
-        serial@19c40000 {
-                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
-                reg = <0x19c40000 0x1000>,
-                      <0x19c00000 0x1000>;
-                interrupts = <0 195 0x0>;
-                clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
-                clock-names = "core", "iface";
-        };
-
-        qcom,ssbi@500000 {
-                compatible = "qcom,ssbi";
-                reg = <0x500000 0x1000>;
-                qcom,controller-type = "pmic-arbiter";
-        };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
new file mode 100644
index 000000000000..69d6c4edea30
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -0,0 +1,63 @@
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+#include <dt-bindings/clock/qcom,gcc-msm8660.h>
+
+/ {
+        model = "Qualcomm MSM8660";
+        compatible = "qcom,msm8660";
+        interrupt-parent = <&intc>;
+
+        intc: interrupt-controller@2080000 {
+                compatible = "qcom,msm-8660-qgic";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = < 0x02080000 0x1000 >,
+                      < 0x02081000 0x1000 >;
+        };
+
+        timer@2000000 {
+                compatible = "qcom,scss-timer", "qcom,msm-timer";
+                interrupts = <1 0 0x301>,
+                             <1 1 0x301>,
+                             <1 2 0x301>;
+                reg = <0x02000000 0x100>;
+                clock-frequency = <27000000>,
+                                  <32768>;
+                cpu-offset = <0x40000>;
+        };
+
+        msmgpio: gpio@800000 {
+                compatible = "qcom,msm-gpio";
+                reg = <0x00800000 0x4000>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                ngpio = <173>;
+                interrupts = <0 16 0x4>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gcc: clock-controller@900000 {
+                compatible = "qcom,gcc-msm8660";
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+                reg = <0x900000 0x4000>;
+        };
+
+        serial@19c40000 {
+                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+                reg = <0x19c40000 0x1000>,
+                      <0x19c00000 0x1000>;
+                interrupts = <0 195 0x0>;
+                clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
+                clock-names = "core", "iface";
+        };
+
+        qcom,ssbi@500000 {
+                compatible = "qcom,ssbi";
+                reg = <0x500000 0x1000>;
+                qcom,controller-type = "pmic-arbiter";
+        };
+};
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index 7c30de4fa302..a58fb88315f6 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -1,70 +1,6 @@
-/dts-v1/;
-
-/include/ "skeleton.dtsi"
-
-#include <dt-bindings/clock/qcom,gcc-msm8960.h>
+#include "qcom-msm8960.dtsi"
 
 / {
         model = "Qualcomm MSM8960 CDP";
         compatible = "qcom,msm8960-cdp", "qcom,msm8960";
-        interrupt-parent = <&intc>;
-
-        intc: interrupt-controller@2000000 {
-                compatible = "qcom,msm-qgic2";
-                interrupt-controller;
-                #interrupt-cells = <3>;
-                reg = < 0x02000000 0x1000 >,
-                      < 0x02002000 0x1000 >;
-        };
-
-        timer@200a000 {
-                compatible = "qcom,kpss-timer", "qcom,msm-timer";
-                interrupts = <1 1 0x301>,
-                             <1 2 0x301>,
-                             <1 3 0x301>;
-                reg = <0x0200a000 0x100>;
-                clock-frequency = <27000000>,
-                                  <32768>;
-                cpu-offset = <0x80000>;
-        };
-
-        msmgpio: gpio@800000 {
-                compatible = "qcom,msm-gpio";
-                gpio-controller;
-                #gpio-cells = <2>;
-                ngpio = <150>;
-                interrupts = <0 16 0x4>;
-                interrupt-controller;
-                #interrupt-cells = <2>;
-                reg = <0x800000 0x4000>;
-        };
-
-        gcc: clock-controller@900000 {
-                compatible = "qcom,gcc-msm8960";
-                #clock-cells = <1>;
-                #reset-cells = <1>;
-                reg = <0x900000 0x4000>;
-        };
-
-        clock-controller@4000000 {
-                compatible = "qcom,mmcc-msm8960";
-                reg = <0x4000000 0x1000>;
-                #clock-cells = <1>;
-                #reset-cells = <1>;
-        };
-
-        serial@16440000 {
-                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
-                reg = <0x16440000 0x1000>,
-                      <0x16400000 0x1000>;
-                interrupts = <0 154 0x0>;
-                clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
-                clock-names = "core", "iface";
-        };
-
-        qcom,ssbi@500000 {
-                compatible = "qcom,ssbi";
-                reg = <0x500000 0x1000>;
-                qcom,controller-type = "pmic-arbiter";
-        };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
new file mode 100644
index 000000000000..3a9c3caa9aad
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -0,0 +1,76 @@
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+#include <dt-bindings/clock/qcom,gcc-msm8960.h>
+
+/ {
+        model = "Qualcomm MSM8960";
+        compatible = "qcom,msm8960";
+        interrupt-parent = <&intc>;
+
+        cpu-pmu {
+                compatible = "qcom,krait-pmu";
+                interrupts = <1 10 0x304>;
+                qcom,no-pc-write;
+        };
+
+        intc: interrupt-controller@2000000 {
+                compatible = "qcom,msm-qgic2";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = < 0x02000000 0x1000 >,
+                      < 0x02002000 0x1000 >;
+        };
+
+        timer@200a000 {
+                compatible = "qcom,kpss-timer", "qcom,msm-timer";
+                interrupts = <1 1 0x301>,
+                             <1 2 0x301>,
+                             <1 3 0x301>;
+                reg = <0x0200a000 0x100>;
+                clock-frequency = <27000000>,
+                                  <32768>;
+                cpu-offset = <0x80000>;
+        };
+
+        msmgpio: gpio@800000 {
+                compatible = "qcom,msm-gpio";
+                gpio-controller;
+                #gpio-cells = <2>;
+                ngpio = <150>;
+                interrupts = <0 16 0x4>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                reg = <0x800000 0x4000>;
+        };
+
+        gcc: clock-controller@900000 {
+                compatible = "qcom,gcc-msm8960";
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+                reg = <0x900000 0x4000>;
+        };
+
+        clock-controller@4000000 {
+                compatible = "qcom,mmcc-msm8960";
+                reg = <0x4000000 0x1000>;
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+        };
+
+        serial@16440000 {
+                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+                reg = <0x16440000 0x1000>,
+                      <0x16400000 0x1000>;
+                interrupts = <0 154 0x0>;
+                clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
+                clock-names = "core", "iface";
+        };
+
+        qcom,ssbi@500000 {
+                compatible = "qcom,ssbi";
+                reg = <0x500000 0x1000>;
+                qcom,controller-type = "pmic-arbiter";
+        };
+};
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 9e5dadb101eb..1eff4130cde0 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -9,6 +9,11 @@
         compatible = "qcom,msm8974";
         interrupt-parent = <&intc>;
 
+        cpu-pmu {
+                compatible = "qcom,krait-pmu";
+                interrupts = <1 7 0xf04>;
+        };
+
         soc: soc {
                 #address-cells = <1>;
                 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index be5d2b09a363..4d4dfbb59f4b 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -64,6 +64,19 @@
                         clock-names = "timer", "pclk";
                 };
 
+                sram: sram@10080000 {
+                        compatible = "mmio-sram";
+                        reg = <0x10080000 0x10000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x10080000 0x10000>;
+
+                        smp-sram@0 {
+                                compatible = "rockchip,rk3066-smp-sram";
+                                reg = <0x0 0x50>;
+                        };
+                };
+
                 pinctrl@20008000 {
                         compatible = "rockchip,rk3066a-pinctrl";
                         reg = <0x20008000 0x150>;
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 1a26b03b3649..bb36596ea205 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -60,6 +60,19 @@
                         interrupts = <GIC_PPI 13 0xf04>;
                 };
 
+                sram: sram@10080000 {
+                        compatible = "mmio-sram";
+                        reg = <0x10080000 0x8000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x10080000 0x8000>;
+
+                        smp-sram@0 {
+                                compatible = "rockchip,rk3066-smp-sram";
+                                reg = <0x0 0x50>;
+                        };
+                };
+
                 pinctrl@20008000 {
                         compatible = "rockchip,rk3188-pinctrl";
                         reg = <0x20008000 0xa0>,
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 0fcbcfd67de2..26e5a968d49d 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -26,6 +26,16 @@
                 compatible = "simple-bus";
                 ranges;
 
+                scu@1013c000 {
+                        compatible = "arm,cortex-a9-scu";
+                        reg = <0x1013c000 0x100>;
+                };
+
+                pmu@20004000 {
+                        compatible = "rockchip,rk3066-pmu";
+                        reg = <0x20004000 0x100>;
+                };
+
                 gic: interrupt-controller@1013d000 {
                         compatible = "arm,cortex-a9-gic";
                         interrupt-controller;
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 52447c17537a..3d5faf85f51b 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -1228,7 +1228,7 @@
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00600000 0x100000>;
                         interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
-                        clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,
+                        clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
                                  <&uhpck>;
                         clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
                         status = "disabled";
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index 0c1e8d871ed1..6cb9b68e2188 100644
--- a/arch/arm/boot/dts/ste-href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -188,7 +188,6 @@
                 msp2: msp@80117000 {
                         pinctrl-names = "default";
                         pinctrl-0 = <&msp2_default_mode>;
-                        status = "okay";
                 };
 
                 msp3: msp@80125000 {
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 040bb0eba152..10666ca8aee1 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -315,7 +315,7 @@
                 ranges;
 
                 emac: ethernet@01c0b000 {
-                        compatible = "allwinner,sun4i-emac";
+                        compatible = "allwinner,sun4i-a10-emac";
                         reg = <0x01c0b000 0x1000>;
                         interrupts = <55>;
                         clocks = <&ahb_gates 17>;
@@ -323,7 +323,7 @@
                 };
 
                 mdio@01c0b080 {
-                        compatible = "allwinner,sun4i-mdio";
+                        compatible = "allwinner,sun4i-a10-mdio";
                         reg = <0x01c0b080 0x14>;
                         status = "disabled";
                         #address-cells = <1>;
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index ea16054857a4..64961595e8d6 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -278,7 +278,7 @@
                 ranges;
 
                 emac: ethernet@01c0b000 {
-                        compatible = "allwinner,sun4i-emac";
+                        compatible = "allwinner,sun4i-a10-emac";
                         reg = <0x01c0b000 0x1000>;
                         interrupts = <55>;
                         clocks = <&ahb_gates 17>;
@@ -286,7 +286,7 @@
                 };
 
                 mdio@01c0b080 {
-                        compatible = "allwinner,sun4i-mdio";
+                        compatible = "allwinner,sun4i-a10-mdio";
                         reg = <0x01c0b080 0x14>;
                         status = "disabled";
                         #address-cells = <1>;
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 119f066f0d98..9ff09484847b 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -340,7 +340,7 @@
                 ranges;
 
                 emac: ethernet@01c0b000 {
-                        compatible = "allwinner,sun4i-emac";
+                        compatible = "allwinner,sun4i-a10-emac";
                         reg = <0x01c0b000 0x1000>;
                         interrupts = <0 55 4>;
                         clocks = <&ahb_gates 17>;
@@ -348,7 +348,7 @@
                 };
 
                 mdio@01c0b080 {
-                        compatible = "allwinner,sun4i-mdio";
+                        compatible = "allwinner,sun4i-a10-mdio";
                         reg = <0x01c0b080 0x14>;
                         status = "disabled";
                         #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 389e987ec281..44ec401ec366 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -57,6 +57,8 @@
                         resets = <&tegra_car 27>;
                         reset-names = "dc";
 
+                        nvidia,head = <0>;
+
                         rgb {
                                 status = "disabled";
                         };
@@ -72,6 +74,8 @@
                         resets = <&tegra_car 26>;
                         reset-names = "dc";
 
+                        nvidia,head = <1>;
+
                         rgb {
                                 status = "disabled";
                         };
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 480ecda3416b..48d2a7f4d0c0 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -94,6 +94,8 @@
                         resets = <&tegra_car 27>;
                         reset-names = "dc";
 
+                        nvidia,head = <0>;
+
                         rgb {
                                 status = "disabled";
                         };
@@ -109,6 +111,8 @@
                         resets = <&tegra_car 26>;
                         reset-names = "dc";
 
+                        nvidia,head = <1>;
+
                         rgb {
                                 status = "disabled";
                         };
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 9104224124ee..1e156d9d0506 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -28,7 +28,7 @@
         compatible = "nvidia,cardhu", "nvidia,tegra30";
 
         aliases {
-                rtc0 = "/i2c@7000d000/tps6586x@34";
+                rtc0 = "/i2c@7000d000/tps65911@2d";
                 rtc1 = "/rtc@7000e000";
         };
 
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index ed8e7700b46d..19a84e933f4e 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -170,6 +170,8 @@
                         resets = <&tegra_car 27>;
                         reset-names = "dc";
 
+                        nvidia,head = <0>;
+
                         rgb {
                                 status = "disabled";
                         };
@@ -185,6 +187,8 @@
                         resets = <&tegra_car 26>;
                         reset-names = "dc";
 
+                        nvidia,head = <1>;
+
                         rgb {
                                 status = "disabled";
                         };
diff --git a/arch/arm/boot/dts/testcases/tests-interrupts.dtsi b/arch/arm/boot/dts/testcases/tests-interrupts.dtsi
deleted file mode 100644
index c843720bd3e5..000000000000
--- a/arch/arm/boot/dts/testcases/tests-interrupts.dtsi
+++ /dev/null
@@ -1,58 +0,0 @@
-
-/ {
-        testcase-data {
-                interrupts {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        test_intc0: intc0 {
-                                interrupt-controller;
-                                #interrupt-cells = <1>;
-                        };
-
-                        test_intc1: intc1 {
-                                interrupt-controller;
-                                #interrupt-cells = <3>;
-                        };
-
-                        test_intc2: intc2 {
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                        };
-
-                        test_intmap0: intmap0 {
-                                #interrupt-cells = <1>;
-                                #address-cells = <0>;
-                                interrupt-map = <1 &test_intc0 9>,
-                                                <2 &test_intc1 10 11 12>,
-                                                <3 &test_intc2 13 14>,
-                                                <4 &test_intc2 15 16>;
-                        };
-
-                        test_intmap1: intmap1 {
-                                #interrupt-cells = <2>;
-                                interrupt-map = <0x5000 1 2 &test_intc0 15>;
-                        };
-
-                        interrupts0 {
-                                interrupt-parent = <&test_intc0>;
-                                interrupts = <1>, <2>, <3>, <4>;
-                        };
-
-                        interrupts1 {
-                                interrupt-parent = <&test_intmap0>;
-                                interrupts = <1>, <2>, <3>, <4>;
-                        };
-
-                        interrupts-extended0 {
-                                reg = <0x5000 0x100>;
-                                interrupts-extended = <&test_intc0 1>,
-                                                      <&test_intc1 2 3 4>,
-                                                      <&test_intc2 5 6>,
-                                                      <&test_intmap0 1>,
-                                                      <&test_intmap0 2>,
-                                                      <&test_intmap0 3>,
-                                                      <&test_intmap1 1 2>;
-                        };
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/testcases/tests-phandle.dtsi b/arch/arm/boot/dts/testcases/tests-phandle.dtsi
deleted file mode 100644
index 0007d3cd7dc2..000000000000
--- a/arch/arm/boot/dts/testcases/tests-phandle.dtsi
+++ /dev/null
@@ -1,39 +0,0 @@
-
-/ {
-        testcase-data {
-                phandle-tests {
-                        provider0: provider0 {
-                                #phandle-cells = <0>;
-                        };
-
-                        provider1: provider1 {
-                                #phandle-cells = <1>;
-                        };
-
-                        provider2: provider2 {
-                                #phandle-cells = <2>;
-                        };
-
-                        provider3: provider3 {
-                                #phandle-cells = <3>;
-                        };
-
-                        consumer-a {
-                                phandle-list =  <&provider1 1>,
-                                                <&provider2 2 0>,
-                                                <0>,
-                                                <&provider3 4 4 3>,
-                                                <&provider2 5 100>,
-                                                <&provider0>,
-                                                <&provider1 7>;
-                                phandle-list-names = "first", "second", "third";
-
-                                phandle-list-bad-phandle = <12345678 0 0>;
-                                phandle-list-bad-args = <&provider2 1 0>,
-                                                        <&provider3 0>;
-                                empty-property;
-                                unterminated-string = [40 41 42 43];
-                        };
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/testcases/tests.dtsi b/arch/arm/boot/dts/testcases/tests.dtsi
deleted file mode 100644
index 3f123ecc9dd7..000000000000
--- a/arch/arm/boot/dts/testcases/tests.dtsi
+++ /dev/null
@@ -1,2 +0,0 @@
-/include/ "tests-phandle.dtsi"
-/include/ "tests-interrupts.dtsi"
diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts
index f43907c40c93..65f657711323 100644
--- a/arch/arm/boot/dts/versatile-pb.dts
+++ b/arch/arm/boot/dts/versatile-pb.dts
@@ -1,4 +1,4 @@
-/include/ "versatile-ab.dts"
+#include <versatile-ab.dts>
 
 / {
         model = "ARM Versatile PB";
@@ -47,4 +47,4 @@
         };
 };
 
-/include/ "testcases/tests.dtsi"
+#include <testcases.dtsi>
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index 2519d6de0640..01004640ee4d 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -79,6 +79,13 @@ CONFIG_HW_RANDOM=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 # CONFIG_HWMON is not set
+CONFIG_MFD_BCM590XX=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
+CONFIG_REGULATOR_USERSPACE_CONSUMER=y
+CONFIG_REGULATOR_BCM590XX=y
+
 CONFIG_VIDEO_OUTPUT_CONTROL=y
 CONFIG_FB=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig
deleted file mode 100644
index 1571bea48bed..000000000000
--- a/arch/arm/configs/da8xx_omapl_defconfig
+++ /dev/null
@@ -1,139 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CGROUPS=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_DAVINCI=y
-CONFIG_ARCH_DAVINCI_DA830=y
-CONFIG_ARCH_DAVINCI_DA850=y
-CONFIG_MACH_DA8XX_DT=y
-CONFIG_MACH_MITYOMAPL138=y
-CONFIG_MACH_OMAPL138_HAWKBOARD=y
-CONFIG_DAVINCI_RESET_CLOCKS=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_LEDS=y
-CONFIG_USE_OF=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=m
-CONFIG_CPU_FREQ_GOV_POWERSAVE=m
-CONFIG_CPU_FREQ_GOV_ONDEMAND=m
-CONFIG_CPU_IDLE=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_INET_LRO is not set
-CONFIG_NETFILTER=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FW_LOADER is not set
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=1
-CONFIG_BLK_DEV_RAM_SIZE=32768
-CONFIG_EEPROM_AT24=y
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_NETDEVICES=y
-CONFIG_TUN=m
-CONFIG_LXT_PHY=y
-CONFIG_LSI_ET1011C_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_TI_DAVINCI_EMAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_NETCONSOLE=y
-CONFIG_NETPOLL_TRAP=y
-CONFIG_INPUT_MOUSEDEV=m
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=m
-CONFIG_KEYBOARD_ATKBD=m
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KEYBOARD_XTKBD=m
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_VT_CONSOLE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_DAVINCI=y
-CONFIG_PINCTRL_SINGLE=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_DUMMY=y
-CONFIG_REGULATOR_TPS6507X=y
-CONFIG_FB=y
-CONFIG_FB_DA8XX=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_SOC=m
-CONFIG_SND_DAVINCI_SOC=m
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_DMADEVICES=y
-CONFIG_TI_EDMA=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_XFS_FS=m
-CONFIG_INOTIFY=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_MINIX_FS=m
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-CONFIG_SMB_FS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_TIMER_STATS=y
-CONFIG_DEBUG_RT_MUTEXES=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_T10DIF=m
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index ab2f7378352c..fff4eb6f62c2 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -20,9 +20,14 @@ CONFIG_ARCH_DAVINCI_DM644x=y
 CONFIG_ARCH_DAVINCI_DM355=y
 CONFIG_ARCH_DAVINCI_DM646x=y
 CONFIG_ARCH_DAVINCI_DM365=y
+CONFIG_ARCH_DAVINCI_DA830=y
+CONFIG_ARCH_DAVINCI_DA850=y
+CONFIG_MACH_DA8XX_DT=y
 CONFIG_MACH_SFFSDR=y
 CONFIG_MACH_NEUROS_OSD2=y
 CONFIG_MACH_DM355_LEOPARD=y
+CONFIG_MACH_MITYOMAPL138=y
+CONFIG_MACH_OMAPL138_HAWKBOARD=y
 CONFIG_DAVINCI_MUX_DEBUG=y
 CONFIG_DAVINCI_MUX_WARNINGS=y
 CONFIG_DAVINCI_RESET_CLOCKS=y
@@ -32,8 +37,16 @@ CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
 CONFIG_LEDS=y
+CONFIG_USE_OF=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=m
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_ONDEMAND=m
+CONFIG_CPU_IDLE=y
 CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -71,6 +84,7 @@ CONFIG_TUN=m
 CONFIG_LXT_PHY=y
 CONFIG_LSI_ET1011C_PHY=y
 CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
 CONFIG_TI_DAVINCI_EMAC=y
 CONFIG_DM9000=y
 # CONFIG_NETDEV_1000 is not set
@@ -97,15 +111,21 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_NR_UARTS=3
 # CONFIG_HW_RANDOM is not set
+CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_DAVINCI=y
+CONFIG_PINCTRL_SINGLE=y
 CONFIG_GPIO_PCF857X=y
 CONFIG_WATCHDOG=y
 CONFIG_DAVINCI_WATCHDOG=m
 CONFIG_MFD_DM355EVM_MSP=y
+CONFIG_TPS6507X=y
 CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_TPS6507X=y
 CONFIG_FB=y
+CONFIG_FB_DA8XX=y
 CONFIG_FIRMWARE_EDID=y
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_FRAMEBUFFER_CONSOLE=y
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index 6309ee52ccfc..f1aeb7d72712 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -154,6 +154,7 @@ CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
 CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_ESDHC_IMX=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 53e82c2523eb..09e974392fa1 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -39,6 +39,8 @@ CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
 CONFIG_SOC_IMX6SL=y
 CONFIG_SOC_VF610=y
+CONFIG_PCI=y
+CONFIG_PCI_IMX6=y
 CONFIG_SMP=y
 CONFIG_VMSPLIT_2G=y
 CONFIG_PREEMPT_VOLUNTARY=y
@@ -165,6 +167,7 @@ CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_ANATOP=y
 CONFIG_REGULATOR_DA9052=y
+CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_MC13783=y
 CONFIG_REGULATOR_MC13892=y
 CONFIG_REGULATOR_PFUZE100=y
@@ -186,6 +189,7 @@ CONFIG_LCD_L4F00242T03=y
 CONFIG_LCD_PLATFORM=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_PWM=y
+CONFIG_BACKLIGHT_GPIO=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
 CONFIG_SOUND=y
@@ -211,6 +215,7 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_ETH=m
 CONFIG_USB_MASS_STORAGE=m
 CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_ESDHC_IMX=y
@@ -225,6 +230,7 @@ CONFIG_LEDS_TRIGGER_BACKLIGHT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_PCF8563=y
 CONFIG_RTC_DRV_MC13XXX=y
 CONFIG_RTC_DRV_MXC=y
 CONFIG_RTC_DRV_SNVS=y
@@ -277,6 +283,7 @@ CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_UTF8=y
+CONFIG_DEBUG_FS=y
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_SCHED_DEBUG is not set
 CONFIG_PROVE_LOCKING=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 845bc745706b..1b4821bc5c7a 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -11,6 +11,7 @@ CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCM_5301X=y
 CONFIG_ARCH_BCM_MOBILE=y
 CONFIG_ARCH_BERLIN=y
 CONFIG_MACH_BERLIN_BG2=y
@@ -29,6 +30,7 @@ CONFIG_ARCH_OMAP3=y
 CONFIG_ARCH_OMAP4=y
 CONFIG_SOC_OMAP5=y
 CONFIG_SOC_AM33XX=y
+CONFIG_SOC_DRA7XX=y
 CONFIG_SOC_AM43XX=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_ARCH_SOCFPGA=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 3a0b53d225e7..364ba38e40f3 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -28,6 +28,7 @@ CONFIG_ARCH_OMAP3=y
 CONFIG_ARCH_OMAP4=y
 CONFIG_SOC_OMAP5=y
 CONFIG_SOC_AM33XX=y
+CONFIG_SOC_AM43XX=y
 CONFIG_SOC_DRA7XX=y
 CONFIG_ARM_THUMBEE=y
 CONFIG_ARM_ERRATA_411920=y
diff --git a/arch/arm/firmware/Kconfig b/arch/arm/firmware/Kconfig
index bb00ccf00d66..ad396af68e47 100644
--- a/arch/arm/firmware/Kconfig
+++ b/arch/arm/firmware/Kconfig
@@ -11,6 +11,7 @@ menu "Firmware options"
 config TRUSTED_FOUNDATIONS
         bool "Trusted Foundations secure monitor support"
         depends on ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
+        default y
         help
           Some devices (including most Tegra-based consumer devices on the
           market) are booted with the Trusted Foundations secure monitor
@@ -20,7 +21,7 @@ config TRUSTED_FOUNDATIONS
           This option allows the kernel to invoke the secure monitor whenever
           required on devices using Trusted Foundations. See
           arch/arm/include/asm/trusted_foundations.h or the
-          tl,trusted-foundations device tree binding documentation for details
+          tlm,trusted-foundations device tree binding documentation for details
           on how to use it.
 
           Say n if you don't know what this is about.
diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c
index ef1e3d8f4af0..3fb1b5a1dce9 100644
--- a/arch/arm/firmware/trusted_foundations.c
+++ b/arch/arm/firmware/trusted_foundations.c
@@ -22,6 +22,15 @@
 
 #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
 
+#define TF_CPU_PM               0xfffffffc
+#define TF_CPU_PM_S3            0xffffffe3
+#define TF_CPU_PM_S2            0xffffffe6
+#define TF_CPU_PM_S2_NO_MC_CLK  0xffffffe5
+#define TF_CPU_PM_S1            0xffffffe4
+#define TF_CPU_PM_S1_NOFLUSH_L2 0xffffffe7
+
+static unsigned long cpu_boot_addr;
+
 static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2)
 {
         asm volatile(
@@ -41,13 +50,22 @@ static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2)
 
 static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
 {
-        tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, boot_addr, 0);
+        cpu_boot_addr = boot_addr;
+        tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, cpu_boot_addr, 0);
+
+        return 0;
+}
+
+static int tf_prepare_idle(void)
+{
+        tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2, cpu_boot_addr);
 
         return 0;
 }
 
 static const struct firmware_ops trusted_foundations_ops = {
         .set_cpu_boot_addr = tf_set_cpu_boot_addr,
+        .prepare_idle = tf_prepare_idle,
 };
 
 void register_trusted_foundations(struct trusted_foundations_platform_data *pd)
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index e9a49fe0284e..8b8b61685a34 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -212,6 +212,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
 static inline void __flush_icache_all(void)
 {
         __flush_icache_preferred();
+        dsb();
 }
 
 /*
diff --git a/arch/arm/include/asm/firmware.h b/arch/arm/include/asm/firmware.h
index 15631300c238..2c9f10df7568 100644
--- a/arch/arm/include/asm/firmware.h
+++ b/arch/arm/include/asm/firmware.h
@@ -22,6 +22,10 @@
  */
 struct firmware_ops {
         /*
+         * Inform the firmware we intend to enter CPU idle mode
+         */
+        int (*prepare_idle)(void);
+        /*
          * Enters CPU idle mode
          */
         int (*do_idle)(void);
diff --git a/arch/arm/plat-orion/include/plat/cache-feroceon-l2.h b/arch/arm/include/asm/hardware/cache-feroceon-l2.h
index 06f982d55697..12e1588dc4f1 100644
--- a/arch/arm/plat-orion/include/plat/cache-feroceon-l2.h
+++ b/arch/arm/include/asm/hardware/cache-feroceon-l2.h
@@ -1,5 +1,5 @@
 /*
- * arch/arm/plat-orion/include/plat/cache-feroceon-l2.h
+ * arch/arm/include/asm/hardware/cache-feroceon-l2.h
  *
  * Copyright (C) 2008 Marvell Semiconductor
  *
@@ -9,3 +9,5 @@
  */
 
 extern void __init feroceon_l2_init(int l2_wt_override);
+extern int __init feroceon_of_init(void);
+
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index 03243f7eeddf..85c60adc8b60 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -120,13 +120,16 @@
 /*
  * 2nd stage PTE definitions for LPAE.
  */
-#define L_PTE_S2_MT_UNCACHED     (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
-#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
-#define L_PTE_S2_MT_WRITEBACK    (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
-#define L_PTE_S2_RDONLY          (_AT(pteval_t, 1) << 6)   /* HAP[1]   */
-#define L_PTE_S2_RDWR            (_AT(pteval_t, 3) << 6)   /* HAP[2:1] */
+#define L_PTE_S2_MT_UNCACHED            (_AT(pteval_t, 0x0) << 2) /* strongly ordered */
+#define L_PTE_S2_MT_WRITETHROUGH        (_AT(pteval_t, 0xa) << 2) /* normal inner write-through */
+#define L_PTE_S2_MT_WRITEBACK           (_AT(pteval_t, 0xf) << 2) /* normal inner write-back */
+#define L_PTE_S2_MT_DEV_SHARED          (_AT(pteval_t, 0x1) << 2) /* device */
+#define L_PTE_S2_MT_MASK                (_AT(pteval_t, 0xf) << 2)
 
-#define L_PMD_S2_RDWR            (_AT(pmdval_t, 3) << 6)   /* HAP[2:1] */
+#define L_PTE_S2_RDONLY                 (_AT(pteval_t, 1) << 6)   /* HAP[1]   */
+#define L_PTE_S2_RDWR                   (_AT(pteval_t, 3) << 6)   /* HAP[2:1] */
+
+#define L_PMD_S2_RDWR                   (_AT(pmdval_t, 3) << 6)   /* HAP[2:1] */
 
 /*
  * Hyp-mode PL2 PTE definitions for LPAE.
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 22a3b9b5d4a1..772435b08207 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -114,6 +114,15 @@ struct smp_operations {
 #endif
 };
 
+struct of_cpu_method {
+        const char *method;
+        struct smp_operations *ops;
+};
+
+#define CPU_METHOD_OF_DECLARE(name, _method, _ops)                      \
+        static const struct of_cpu_method __cpu_method_of_table_##name  \
+                __used __section(__cpu_method_of_table)                 \
+                = { .method = _method, .ops = _ops }
 /*
  * set platform specific SMP operations
  */
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index ef3c6072aa45..ac4bfae26702 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -37,18 +37,9 @@
 
 static inline void dsb_sev(void)
 {
-#if __LINUX_ARM_ARCH__ >= 7
-        __asm__ __volatile__ (
-                "dsb ishst\n"
-                SEV
-        );
-#else
-        __asm__ __volatile__ (
-                "mcr p15, 0, %0, c7, c10, 4\n"
-                SEV
-                : : "r" (0)
-        );
-#endif
+
+        dsb(ishst);
+        __asm__(SEV);
 }
 
 /*
diff --git a/arch/arm/include/asm/trusted_foundations.h b/arch/arm/include/asm/trusted_foundations.h
index 3bd36e2c5f2e..b5f7705abcb0 100644
--- a/arch/arm/include/asm/trusted_foundations.h
+++ b/arch/arm/include/asm/trusted_foundations.h
@@ -30,6 +30,8 @@
 #include <linux/printk.h>
 #include <linux/bug.h>
 #include <linux/of.h>
+#include <linux/cpu.h>
+#include <linux/smp.h>
 
 struct trusted_foundations_platform_data {
         unsigned int version_major;
@@ -47,10 +49,13 @@ static inline void register_trusted_foundations(
                                    struct trusted_foundations_platform_data *pd)
 {
         /*
-         * If we try to register TF, this means the system needs it to continue.
-         * Its absence if thus a fatal error.
+         * If the system requires TF and we cannot provide it, continue booting
+         * but disable features that cannot be provided.
          */
-        panic("No support for Trusted Foundations, stopping...\n");
+        pr_err("No support for Trusted Foundations, continuing in degraded mode.\n");
+        pr_err("Secondary processors as well as CPU PM will be disabled.\n");
+        setup_max_cpus = 0;
+        cpu_idle_poll_ctrl(true);
 }
 
 static inline void of_register_trusted_foundations(void)
@@ -59,7 +64,7 @@ static inline void of_register_trusted_foundations(void)
          * If we find the target should enable TF but does not support it,
          * fail as the system won't be able to do much anyway
          */
-        if (of_find_compatible_node(NULL, NULL, "tl,trusted-foundations"))
+        if (of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations"))
                 register_trusted_foundations(NULL);
 }
 #endif /* CONFIG_TRUSTED_FOUNDATIONS */
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index f751714d52c1..c7419a585ddc 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -18,6 +18,7 @@
 #include <linux/of_fdt.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/smp.h>
 
 #include <asm/cputype.h>
 #include <asm/setup.h>
@@ -63,6 +64,34 @@ void __init arm_dt_memblock_reserve(void)
         }
 }
 
+#ifdef CONFIG_SMP
+extern struct of_cpu_method __cpu_method_of_table_begin[];
+extern struct of_cpu_method __cpu_method_of_table_end[];
+
+static int __init set_smp_ops_by_method(struct device_node *node)
+{
+        const char *method;
+        struct of_cpu_method *m = __cpu_method_of_table_begin;
+
+        if (of_property_read_string(node, "enable-method", &method))
+                return 0;
+
+        for (; m < __cpu_method_of_table_end; m++)
+                if (!strcmp(m->method, method)) {
+                        smp_set_ops(m->ops);
+                        return 1;
+                }
+
+        return 0;
+}
+#else
+static inline int set_smp_ops_by_method(struct device_node *node)
+{
+        return 1;
+}
+#endif
+
+
 /*
  * arm_dt_init_cpu_maps - Function retrieves cpu nodes from the device tree
  * and builds the cpu logical map array containing MPIDR values related to
@@ -79,6 +108,7 @@ void __init arm_dt_init_cpu_maps(void)
          * read as 0.
          */
         struct device_node *cpu, *cpus;
+        int found_method = 0;
         u32 i, j, cpuidx = 1;
         u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
 
@@ -150,8 +180,18 @@ void __init arm_dt_init_cpu_maps(void)
                 }
 
                 tmp_map[i] = hwid;
+
+                if (!found_method)
+                        found_method = set_smp_ops_by_method(cpu);
         }
 
+        /*
+         * Fallback to an enable-method in the cpus node if nothing found in
+         * a cpu node.
+         */
+        if (!found_method)
+                set_smp_ops_by_method(cpus);
+
         if (!bootcpu_valid) {
                 pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n");
                 return;
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index b0df9761de6d..1e8b030dbefd 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -731,7 +731,7 @@ static void __init request_standard_resources(const struct machine_desc *mdesc)
         kernel_data.end     = virt_to_phys(_end - 1);
 
         for_each_memblock(memory, region) {
-                res = memblock_virt_alloc_low(sizeof(*res), 0);
+                res = memblock_virt_alloc(sizeof(*res), 0);
                 res->name  = "System RAM";
                 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
                 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index b1aa6a9b3bd1..21474458aa56 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -16,12 +16,7 @@ config ARCH_BCM_MOBILE
         select ARM_ERRATA_754322
         select ARM_ERRATA_764369 if SMP
         select ARM_GIC
-        select CPU_V7
-        select CLKSRC_OF
-        select GENERIC_CLOCKEVENTS
-        select GENERIC_TIME
         select GPIO_BCM_KONA
-        select SPARSE_IRQ
         select TICK_ONESHOT
         select CACHE_L2X0
         select HAVE_ARM_ARCH_TIMER
@@ -32,6 +27,32 @@ config ARCH_BCM_MOBILE
           BCM11130, BCM11140, BCM11351, BCM28145 and
           BCM28155 variants.
 
+config ARCH_BCM_5301X
+        bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
+        depends on MMU
+        select ARM_GIC
+        select CACHE_L2X0
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if SMP
+        select HAVE_SMP
+        select COMMON_CLK
+        select GENERIC_CLOCKEVENTS
+        select ARM_GLOBAL_TIMER
+        select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
+        select MIGHT_HAVE_PCI
+        help
+          Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
+
+          This is a network SoC line mostly used in home routers and
+          wifi access points, it's internal name is Northstar.
+          This inclused the following SoC: BCM53010, BCM53011, BCM53012,
+          BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
+          BCM4708 and BCM4709.
+
+          Do not confuse this with the BCM4760 which is a totally
+          different SoC or with the older BCM47XX and BCM53XX based
+          network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index c2ccd5a0f772..4e4a2ed6851e 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -1,5 +1,5 @@
 #
-# Copyright (C) 2012-2013 Broadcom Corporation
+# Copyright (C) 2012-2014 Broadcom Corporation
 #
 # This program is free software; you can redistribute it and/or
 # modify it under the terms of the GNU General Public License as
@@ -10,6 +10,9 @@
 # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 
-obj-$(CONFIG_ARCH_BCM_MOBILE)   := board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
+obj-$(CONFIG_ARCH_BCM_MOBILE)   := board_bcm281xx.o board_bcm21664.o \
+                                bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
+
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_bcm_kona_smc_asm.o       :=-Wa,-march=armv7-a$(plus_sec)
+obj-$(CONFIG_ARCH_BCM_5301X)    += bcm_5301x.o
diff --git a/arch/arm/mach-bcm/bcm_5301x.c b/arch/arm/mach-bcm/bcm_5301x.c
new file mode 100644
index 000000000000..edff69761e04
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm_5301x.c
@@ -0,0 +1,61 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ *
+ * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+#include <linux/of_platform.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <asm/mach/arch.h>
+#include <asm/siginfo.h>
+#include <asm/signal.h>
+
+
+static bool first_fault = true;
+
+static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr,
+                                 struct pt_regs *regs)
+{
+        if (fsr == 0x1c06 && first_fault) {
+                first_fault = false;
+
+                /*
+                 * These faults with code 0x1c06 happens for no good reason,
+                 * possibly left over from the CFE boot loader.
+                 */
+                pr_warn("External imprecise Data abort at addr=%#lx, fsr=%#x ignored.\n",
+                addr, fsr);
+
+                /* Returning non-zero causes fault display and panic */
+                return 0;
+        }
+
+        /* Others should cause a fault */
+        return 1;
+}
+
+static void __init bcm5301x_init_early(void)
+{
+        /* Install our hook */
+        hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, BUS_OBJERR,
+                        "imprecise external abort");
+}
+
+static void __init bcm5301x_dt_init(void)
+{
+        l2x0_of_init(0, ~0UL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char __initconst *bcm5301x_dt_compat[] = {
+        "brcm,bcm4708",
+        NULL,
+};
+
+DT_MACHINE_START(BCM5301X, "BCM5301X")
+        .init_early     = bcm5301x_init_early,
+        .init_machine   = bcm5301x_dt_init,
+        .dt_compat      = bcm5301x_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-bcm/board_bcm21664.c b/arch/arm/mach-bcm/board_bcm21664.c
new file mode 100644
index 000000000000..acc1573fd005
--- /dev/null
+++ b/arch/arm/mach-bcm/board_bcm21664.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clocksource.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach/arch.h>
+
+#include "bcm_kona_smc.h"
+#include "kona.h"
+
+#define RSTMGR_DT_STRING                "brcm,bcm21664-resetmgr"
+
+#define RSTMGR_REG_WR_ACCESS_OFFSET     0
+#define RSTMGR_REG_CHIP_SOFT_RST_OFFSET 4
+
+#define RSTMGR_WR_PASSWORD              0xa5a5
+#define RSTMGR_WR_PASSWORD_SHIFT        8
+#define RSTMGR_WR_ACCESS_ENABLE         1
+
+static void bcm21664_restart(enum reboot_mode mode, const char *cmd)
+{
+        void __iomem *base;
+        struct device_node *resetmgr;
+
+        resetmgr = of_find_compatible_node(NULL, NULL, RSTMGR_DT_STRING);
+        if (!resetmgr) {
+                pr_emerg("Couldn't find " RSTMGR_DT_STRING "\n");
+                return;
+        }
+        base = of_iomap(resetmgr, 0);
+        if (!base) {
+                pr_emerg("Couldn't map " RSTMGR_DT_STRING "\n");
+                return;
+        }
+
+        /*
+         * A soft reset is triggered by writing a 0 to bit 0 of the soft reset
+         * register. To write to that register we must first write the password
+         * and the enable bit in the write access enable register.
+         */
+        writel((RSTMGR_WR_PASSWORD << RSTMGR_WR_PASSWORD_SHIFT) |
+                RSTMGR_WR_ACCESS_ENABLE,
+                base + RSTMGR_REG_WR_ACCESS_OFFSET);
+        writel(0, base + RSTMGR_REG_CHIP_SOFT_RST_OFFSET);
+
+        /* Wait for reset */
+        while (1);
+}
+
+static void __init bcm21664_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL,
+                &platform_bus);
+        kona_l2_cache_init();
+}
+
+static const char * const bcm21664_dt_compat[] = {
+        "brcm,bcm21664",
+        NULL,
+};
+
+DT_MACHINE_START(BCM21664_DT, "BCM21664 Broadcom Application Processor")
+        .init_machine = bcm21664_init,
+        .restart = bcm21664_restart,
+        .dt_compat = bcm21664_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-bcm/board_bcm281xx.c b/arch/arm/mach-bcm/board_bcm281xx.c
index cb3dc364405c..6be54c10f8cb 100644
--- a/arch/arm/mach-bcm/board_bcm281xx.c
+++ b/arch/arm/mach-bcm/board_bcm281xx.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012-2013 Broadcom Corporation
+ * Copyright (C) 2012-2014 Broadcom Corporation
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -11,64 +11,65 @@
  * GNU General Public License for more details.
  */
 
-#include <linux/of_platform.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
 #include <linux/clocksource.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
 
 #include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/hardware/cache-l2x0.h>
 
-#include "bcm_kona_smc.h"
 #include "kona.h"
 
-static int __init kona_l2_cache_init(void)
+#define SECWDOG_OFFSET                  0x00000000
+#define SECWDOG_RESERVED_MASK           0xe2000000
+#define SECWDOG_WD_LOAD_FLAG_MASK       0x10000000
+#define SECWDOG_EN_MASK                 0x08000000
+#define SECWDOG_SRSTEN_MASK             0x04000000
+#define SECWDOG_CLKS_SHIFT              20
+#define SECWDOG_COUNT_SHIFT             0
+
+static void bcm281xx_restart(enum reboot_mode mode, const char *cmd)
 {
-        if (!IS_ENABLED(CONFIG_CACHE_L2X0))
-                return 0;
+        uint32_t val;
+        void __iomem *base;
+        struct device_node *np_wdog;
 
-        if (bcm_kona_smc_init() < 0) {
-                pr_info("Kona secure API not available. Skipping L2 init\n");
-                return 0;
+        np_wdog = of_find_compatible_node(NULL, NULL, "brcm,kona-wdt");
+        if (!np_wdog) {
+                pr_emerg("Couldn't find brcm,kona-wdt\n");
+                return;
+        }
+        base = of_iomap(np_wdog, 0);
+        if (!base) {
+                pr_emerg("Couldn't map brcm,kona-wdt\n");
+                return;
         }
 
-        bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0);
-
-        /*
-         * The aux_val and aux_mask have no effect since L2 cache is already
-         * enabled.  Pass 0s for aux_val and 1s for aux_mask for default value.
-         */
-        return l2x0_of_init(0, ~0);
-}
-
-static void bcm_board_setup_restart(void)
-{
-        struct device_node *np;
+        /* Enable watchdog with short timeout (244us). */
+        val = readl(base + SECWDOG_OFFSET);
+        val &= SECWDOG_RESERVED_MASK | SECWDOG_WD_LOAD_FLAG_MASK;
+        val |= SECWDOG_EN_MASK | SECWDOG_SRSTEN_MASK |
+                (0x15 << SECWDOG_CLKS_SHIFT) |
+                (0x8 << SECWDOG_COUNT_SHIFT);
+        writel(val, base + SECWDOG_OFFSET);
 
-        np = of_find_compatible_node(NULL, NULL, "brcm,bcm11351");
-        if (np) {
-                if (of_device_is_available(np))
-                        bcm_kona_setup_restart();
-                of_node_put(np);
-        }
-        /* Restart setup for other boards goes here */
+        /* Wait for reset */
+        while (1);
 }
 
-static void __init board_init(void)
+static void __init bcm281xx_init(void)
 {
         of_platform_populate(NULL, of_default_bus_match_table, NULL,
                 &platform_bus);
-
-        bcm_board_setup_restart();
         kona_l2_cache_init();
 }
 
-static const char * const bcm11351_dt_compat[] = { "brcm,bcm11351", NULL, };
+static const char * const bcm281xx_dt_compat[] = {
+        "brcm,bcm11351",        /* Have to use the first number upstreamed */
+        NULL,
+};
 
-DT_MACHINE_START(BCM11351_DT, "BCM281xx Broadcom Application Processor")
-        .init_machine = board_init,
-        .restart = bcm_kona_restart,
-        .dt_compat = bcm11351_dt_compat,
+DT_MACHINE_START(BCM281XX_DT, "BCM281xx Broadcom Application Processor")
+        .init_machine = bcm281xx_init,
+        .restart = bcm281xx_restart,
+        .dt_compat = bcm281xx_dt_compat,
 MACHINE_END
diff --git a/arch/arm/mach-bcm/kona.c b/arch/arm/mach-bcm/kona.c
index 6939d9017f63..768bc2837bf5 100644
--- a/arch/arm/mach-bcm/kona.c
+++ b/arch/arm/mach-bcm/kona.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Broadcom Corporation
+ * Copyright (C) 2012-2014 Broadcom Corporation
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -11,55 +11,33 @@
  * GNU General Public License for more details.
  */
 
-#include <linux/of_address.h>
-#include <asm/io.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/cache-l2x0.h>
 
+#include "bcm_kona_smc.h"
 #include "kona.h"
 
-static void __iomem *watchdog_base;
-
-void bcm_kona_setup_restart(void)
+void __init kona_l2_cache_init(void)
 {
-        struct device_node *np_wdog;
+        int ret;
 
-        /*
-         * The assumption is that whoever calls bcm_kona_setup_restart()
-         * also needs a Kona Watchdog Timer entry in Device Tree, i.e. we
-         * report an error if the DT entry is missing.
-         */
-        np_wdog = of_find_compatible_node(NULL, NULL, "brcm,kona-wdt");
-        if (!np_wdog) {
-                pr_err("brcm,kona-wdt not found in DT, reboot disabled\n");
+        if (!IS_ENABLED(CONFIG_CACHE_L2X0))
                 return;
-        }
-        watchdog_base = of_iomap(np_wdog, 0);
-        WARN(!watchdog_base, "failed to map watchdog base");
-        of_node_put(np_wdog);
-}
-
-#define SECWDOG_OFFSET                  0x00000000
-#define SECWDOG_RESERVED_MASK           0xE2000000
-#define SECWDOG_WD_LOAD_FLAG_MASK       0x10000000
-#define SECWDOG_EN_MASK                 0x08000000
-#define SECWDOG_SRSTEN_MASK             0x04000000
-#define SECWDOG_CLKS_SHIFT              20
-#define SECWDOG_LOCK_SHIFT              0
 
-void bcm_kona_restart(enum reboot_mode mode, const char *cmd)
-{
-        uint32_t val;
-
-        if (!watchdog_base)
-                panic("Watchdog not mapped. Reboot failed.\n");
+        ret = bcm_kona_smc_init();
+        if (ret) {
+                pr_info("Secure API not available (%d). Skipping L2 init.\n",
+                        ret);
+                return;
+        }
 
-        /* Enable watchdog2 with very short timeout. */
-        val = readl(watchdog_base + SECWDOG_OFFSET);
-        val &= SECWDOG_RESERVED_MASK | SECWDOG_WD_LOAD_FLAG_MASK;
-        val |= SECWDOG_EN_MASK | SECWDOG_SRSTEN_MASK |
-                (0x8 << SECWDOG_CLKS_SHIFT) |
-                (0x8 << SECWDOG_LOCK_SHIFT);
-        writel(val, watchdog_base + SECWDOG_OFFSET);
+        bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0);
 
-        while (1)
-                ;
+        /*
+         * The aux_val and aux_mask have no effect since L2 cache is already
+         * enabled.  Pass 0s for aux_val and 1s for aux_mask for default value.
+         */
+        ret = l2x0_of_init(0, ~0);
+        if (ret)
+                pr_err("Couldn't enable L2 cache: %d\n", ret);
 }
diff --git a/arch/arm/mach-bcm/kona.h b/arch/arm/mach-bcm/kona.h
index 291eca3e06ff..3a7a017c29cd 100644
--- a/arch/arm/mach-bcm/kona.h
+++ b/arch/arm/mach-bcm/kona.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Broadcom Corporation
+ * Copyright (C) 2012-2014 Broadcom Corporation
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -11,7 +11,4 @@
  * GNU General Public License for more details.
  */
 
-#include <linux/reboot.h>
-
-void bcm_kona_setup_restart(void);
-void bcm_kona_restart(enum reboot_mode mode, const char *cmd);
+void __init kona_l2_cache_init(void);
diff --git a/arch/arm/mach-bcm2835/Kconfig b/arch/arm/mach-bcm2835/Kconfig
index d1f9612f8c15..3a369350a26f 100644
--- a/arch/arm/mach-bcm2835/Kconfig
+++ b/arch/arm/mach-bcm2835/Kconfig
@@ -4,10 +4,6 @@ config ARCH_BCM2835
         select ARM_AMBA
         select ARM_ERRATA_411920
         select ARM_TIMER_SP804
-        select CLKDEV_LOOKUP
-        select CLKSRC_OF
-        select CPU_V6
-        select GENERIC_CLOCKEVENTS
         select PINCTRL
         select PINCTRL_BCM2835
         help
diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
index 7a02d222c378..b0cb0722acd2 100644
--- a/arch/arm/mach-berlin/Kconfig
+++ b/arch/arm/mach-berlin/Kconfig
@@ -1,9 +1,7 @@
 config ARCH_BERLIN
         bool "Marvell Berlin SoCs" if ARCH_MULTI_V7
         select ARM_GIC
-        select GENERIC_CLOCKEVENTS
         select GENERIC_IRQ_CHIP
-        select COMMON_CLK
         select DW_APB_ICTL
         select DW_APB_TIMER_OF
 
@@ -16,12 +14,10 @@ config MACH_BERLIN_BG2
         select CACHE_L2X0
         select CPU_PJ4B
         select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
 
 config MACH_BERLIN_BG2CD
         bool "Marvell Armada 1500-mini (BG2CD)"
         select CACHE_L2X0
-        select CPU_V7
         select HAVE_ARM_TWD if SMP
 
 endmenu
diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c
index f8d71a89644a..eb945b2a0042 100644
--- a/arch/arm/mach-clps711x/board-autcpu12.c
+++ b/arch/arm/mach-clps711x/board-autcpu12.c
@@ -265,14 +265,12 @@ static void __init autcpu12_init_late(void)
 MACHINE_START(AUTCPU12, "autronix autcpu12")
         /* Maintainer: Thomas Gleixner */
         .atag_offset    = 0x20000,
-        .nr_irqs        = CLPS711X_NR_IRQS,
         .map_io         = clps711x_map_io,
         .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
         .init_machine   = autcpu12_init,
         .init_late      = autcpu12_init_late,
-        .handle_irq     = clps711x_handle_irq,
         .restart        = clps711x_restart,
 MACHINE_END
 
diff --git a/arch/arm/mach-clps711x/board-cdb89712.c b/arch/arm/mach-clps711x/board-cdb89712.c
index a9e38c6bcfb4..e261a47f2aff 100644
--- a/arch/arm/mach-clps711x/board-cdb89712.c
+++ b/arch/arm/mach-clps711x/board-cdb89712.c
@@ -139,12 +139,10 @@ static void __init cdb89712_init(void)
 MACHINE_START(CDB89712, "Cirrus-CDB89712")
         /* Maintainer: Ray Lehtiniemi */
         .atag_offset    = 0x100,
-        .nr_irqs        = CLPS711X_NR_IRQS,
         .map_io         = clps711x_map_io,
         .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
         .init_machine   = cdb89712_init,
-        .handle_irq     = clps711x_handle_irq,
         .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-clep7312.c b/arch/arm/mach-clps711x/board-clep7312.c
index b4764246d0f8..221b9de32dd6 100644
--- a/arch/arm/mach-clps711x/board-clep7312.c
+++ b/arch/arm/mach-clps711x/board-clep7312.c
@@ -36,12 +36,10 @@ fixup_clep7312(struct tag *tags, char **cmdline, struct meminfo *mi)
 MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
         /* Maintainer: Nobody */
         .atag_offset    = 0x0100,
-        .nr_irqs        = CLPS711X_NR_IRQS,
         .fixup          = fixup_clep7312,
         .map_io         = clps711x_map_io,
         .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
-        .handle_irq     = clps711x_handle_irq,
         .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
index fe6184ead896..077609841f14 100644
--- a/arch/arm/mach-clps711x/board-edb7211.c
+++ b/arch/arm/mach-clps711x/board-edb7211.c
@@ -177,7 +177,6 @@ static void __init edb7211_init_late(void)
 MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
         /* Maintainer: Jon McClintock */
         .atag_offset    = VIDEORAM_SIZE + 0x100,
-        .nr_irqs        = CLPS711X_NR_IRQS,
         .fixup          = fixup_edb7211,
         .reserve        = edb7211_reserve,
         .map_io         = clps711x_map_io,
@@ -186,6 +185,5 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
         .init_time      = clps711x_timer_init,
         .init_machine   = edb7211_init,
         .init_late      = edb7211_init_late,
-        .handle_irq     = clps711x_handle_irq,
         .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c
index dd81b06f68fe..67b733744ed7 100644
--- a/arch/arm/mach-clps711x/board-p720t.c
+++ b/arch/arm/mach-clps711x/board-p720t.c
@@ -363,7 +363,6 @@ static void __init p720t_init_late(void)
 MACHINE_START(P720T, "ARM-Prospector720T")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
         .atag_offset    = 0x100,
-        .nr_irqs        = CLPS711X_NR_IRQS,
         .fixup          = fixup_p720t,
         .map_io         = clps711x_map_io,
         .init_early     = clps711x_init_early,
@@ -371,6 +370,5 @@ MACHINE_START(P720T, "ARM-Prospector720T")
         .init_time      = clps711x_timer_init,
         .init_machine   = p720t_init,
         .init_late      = p720t_init_late,
-        .handle_irq     = clps711x_handle_irq,
         .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index a1935911e4f1..aee81fa46ccf 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -31,14 +31,14 @@
 #include <linux/clk-provider.h>
 #include <linux/sched_clock.h>
 
-#include <asm/exception.h>
-#include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
 
 #include <mach/hardware.h>
 
+#include "common.h"
+
 static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
                   *clk_tint, *clk_spi;
 
@@ -59,204 +59,9 @@ void __init clps711x_map_io(void)
         iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
 }
 
-static void int1_mask(struct irq_data *d)
-{
-        u32 intmr1;
-
-        intmr1 = clps_readl(INTMR1);
-        intmr1 &= ~(1 << d->irq);
-        clps_writel(intmr1, INTMR1);
-}
-
-static void int1_eoi(struct irq_data *d)
-{
-        switch (d->irq) {
-        case IRQ_CSINT:  clps_writel(0, COEOI);  break;
-        case IRQ_TC1OI:  clps_writel(0, TC1EOI); break;
-        case IRQ_TC2OI:  clps_writel(0, TC2EOI); break;
-        case IRQ_RTCMI:  clps_writel(0, RTCEOI); break;
-        case IRQ_TINT:   clps_writel(0, TEOI);   break;
-        case IRQ_UMSINT: clps_writel(0, UMSEOI); break;
-        }
-}
-
-static void int1_unmask(struct irq_data *d)
-{
-        u32 intmr1;
-
-        intmr1 = clps_readl(INTMR1);
-        intmr1 |= 1 << d->irq;
-        clps_writel(intmr1, INTMR1);
-}
-
-static struct irq_chip int1_chip = {
-        .name           = "Interrupt Vector 1",
-        .irq_eoi        = int1_eoi,
-        .irq_mask       = int1_mask,
-        .irq_unmask     = int1_unmask,
-};
-
-static void int2_mask(struct irq_data *d)
-{
-        u32 intmr2;
-
-        intmr2 = clps_readl(INTMR2);
-        intmr2 &= ~(1 << (d->irq - 16));
-        clps_writel(intmr2, INTMR2);
-}
-
-static void int2_eoi(struct irq_data *d)
-{
-        switch (d->irq) {
-        case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
-        }
-}
-
-static void int2_unmask(struct irq_data *d)
-{
-        u32 intmr2;
-
-        intmr2 = clps_readl(INTMR2);
-        intmr2 |= 1 << (d->irq - 16);
-        clps_writel(intmr2, INTMR2);
-}
-
-static struct irq_chip int2_chip = {
-        .name           = "Interrupt Vector 2",
-        .irq_eoi        = int2_eoi,
-        .irq_mask       = int2_mask,
-        .irq_unmask     = int2_unmask,
-};
-
-static void int3_mask(struct irq_data *d)
-{
-        u32 intmr3;
-
-        intmr3 = clps_readl(INTMR3);
-        intmr3 &= ~(1 << (d->irq - 32));
-        clps_writel(intmr3, INTMR3);
-}
-
-static void int3_unmask(struct irq_data *d)
-{
-        u32 intmr3;
-
-        intmr3 = clps_readl(INTMR3);
-        intmr3 |= 1 << (d->irq - 32);
-        clps_writel(intmr3, INTMR3);
-}
-
-static struct irq_chip int3_chip = {
-        .name           = "Interrupt Vector 3",
-        .irq_mask       = int3_mask,
-        .irq_unmask     = int3_unmask,
-};
-
-static struct {
-        int                     nr;
-        struct irq_chip         *chip;
-        irq_flow_handler_t      handle;
-} clps711x_irqdescs[] __initdata = {
-        { IRQ_CSINT,    &int1_chip,     handle_fasteoi_irq,     },
-        { IRQ_EINT1,    &int1_chip,     handle_level_irq,       },
-        { IRQ_EINT2,    &int1_chip,     handle_level_irq,       },
-        { IRQ_EINT3,    &int1_chip,     handle_level_irq,       },
-        { IRQ_TC1OI,    &int1_chip,     handle_fasteoi_irq,     },
-        { IRQ_TC2OI,    &int1_chip,     handle_fasteoi_irq,     },
-        { IRQ_RTCMI,    &int1_chip,     handle_fasteoi_irq,     },
-        { IRQ_TINT,     &int1_chip,     handle_fasteoi_irq,     },
-        { IRQ_UTXINT1,  &int1_chip,     handle_level_irq,       },
-        { IRQ_URXINT1,  &int1_chip,     handle_level_irq,       },
-        { IRQ_UMSINT,   &int1_chip,     handle_fasteoi_irq,     },
-        { IRQ_SSEOTI,   &int1_chip,     handle_level_irq,       },
-        { IRQ_KBDINT,   &int2_chip,     handle_fasteoi_irq,     },
-        { IRQ_SS2RX,    &int2_chip,     handle_level_irq,       },
-        { IRQ_SS2TX,    &int2_chip,     handle_level_irq,       },
-        { IRQ_UTXINT2,  &int2_chip,     handle_level_irq,       },
-        { IRQ_URXINT2,  &int2_chip,     handle_level_irq,       },
-};
-
 void __init clps711x_init_irq(void)
 {
-        unsigned int i;
-
-        /* Disable interrupts */
-        clps_writel(0, INTMR1);
-        clps_writel(0, INTMR2);
-        clps_writel(0, INTMR3);
-
-        /* Clear down any pending interrupts */
-        clps_writel(0, BLEOI);
-        clps_writel(0, MCEOI);
-        clps_writel(0, COEOI);
-        clps_writel(0, TC1EOI);
-        clps_writel(0, TC2EOI);
-        clps_writel(0, RTCEOI);
-        clps_writel(0, TEOI);
-        clps_writel(0, UMSEOI);
-        clps_writel(0, KBDEOI);
-        clps_writel(0, SRXEOF);
-        clps_writel(0xffffffff, DAISR);
-
-        for (i = 0; i < ARRAY_SIZE(clps711x_irqdescs); i++) {
-                irq_set_chip_and_handler(clps711x_irqdescs[i].nr,
-                                         clps711x_irqdescs[i].chip,
-                                         clps711x_irqdescs[i].handle);
-                set_irq_flags(clps711x_irqdescs[i].nr,
-                              IRQF_VALID | IRQF_PROBE);
-        }
-
-        if (IS_ENABLED(CONFIG_FIQ)) {
-                init_FIQ(0);
-                irq_set_chip_and_handler(IRQ_DAIINT, &int3_chip,
-                                         handle_bad_irq);
-                set_irq_flags(IRQ_DAIINT,
-                              IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
-        }
-}
-
-static inline u32 fls16(u32 x)
-{
-        u32 r = 15;
-
-        if (!(x & 0xff00)) {
-                x <<= 8;
-                r -= 8;
-        }
-        if (!(x & 0xf000)) {
-                x <<= 4;
-                r -= 4;
-        }
-        if (!(x & 0xc000)) {
-                x <<= 2;
-                r -= 2;
-        }
-        if (!(x & 0x8000))
-                r--;
-
-        return r;
-}
-
-asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs)
-{
-        do {
-                u32 irqstat;
-                void __iomem *base = CLPS711X_VIRT_BASE;
-
-                irqstat = readw_relaxed(base + INTSR1) &
-                          readw_relaxed(base + INTMR1);
-                if (irqstat)
-                        handle_IRQ(fls16(irqstat), regs);
-
-                irqstat = readw_relaxed(base + INTSR2) &
-                          readw_relaxed(base + INTMR2);
-                if (irqstat) {
-                        handle_IRQ(fls16(irqstat) + 16, regs);
-                        continue;
-                }
-
-                break;
-        } while (1);
+        clps711x_intc_init(CLPS711X_PHYS_BASE, SZ_16K);
 }
 
 static u64 notrace clps711x_sched_clock_read(void)
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index 9a6767bfdc47..7489139d5d63 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -6,13 +6,14 @@
 
 #include <linux/reboot.h>
 
-#define CLPS711X_NR_IRQS        (33)
 #define CLPS711X_NR_GPIO        (4 * 8 + 3)
 #define CLPS711X_GPIO(prt, bit) ((prt) * 8 + (bit))
 
 extern void clps711x_map_io(void);
 extern void clps711x_init_irq(void);
 extern void clps711x_timer_init(void);
-extern void clps711x_handle_irq(struct pt_regs *regs);
 extern void clps711x_restart(enum reboot_mode mode, const char *cmd);
 extern void clps711x_init_early(void);
+
+/* drivers/irqchip/irq-clps711x.c */
+void clps711x_intc_init(phys_addr_t, resource_size_t);
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
index 0286f4bf9945..eb052a11aa9d 100644
--- a/arch/arm/mach-clps711x/include/mach/clps711x.h
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -40,8 +40,6 @@
 #define MEMCFG1         (0x0180)
 #define MEMCFG2         (0x01c0)
 #define DRFPR           (0x0200)
-#define INTSR1          (0x0240)
-#define INTMR1          (0x0280)
 #define LCDCON          (0x02c0)
 #define TC1D            (0x0300)
 #define TC2D            (0x0340)
@@ -55,28 +53,16 @@
 #define PALLSW          (0x0540)
 #define PALMSW          (0x0580)
 #define STFCLR          (0x05c0)
-#define BLEOI           (0x0600)
-#define MCEOI           (0x0640)
-#define TEOI            (0x0680)
-#define TC1EOI          (0x06c0)
-#define TC2EOI          (0x0700)
-#define RTCEOI          (0x0740)
-#define UMSEOI          (0x0780)
-#define COEOI           (0x07c0)
 #define HALT            (0x0800)
 #define STDBY           (0x0840)
 
 #define FBADDR          (0x1000)
 #define SYSCON2         (0x1100)
 #define SYSFLG2         (0x1140)
-#define INTSR2          (0x1240)
-#define INTMR2          (0x1280)
 #define UARTDR2         (0x1480)
 #define UBRLCR2         (0x14c0)
 #define SS2DR           (0x1500)
-#define SRXEOF          (0x1600)
 #define SS2POP          (0x16c0)
-#define KBDEOI          (0x1700)
 
 #define DAIR            (0x2000)
 #define DAIDR0          (0x2040)
@@ -84,8 +70,6 @@
 #define DAIDR2          (0x20c0)
 #define DAISR           (0x2100)
 #define SYSCON3         (0x2200)
-#define INTSR3          (0x2240)
-#define INTMR3          (0x2280)
 #define LEDFLSH         (0x22c0)
 #define SDCONF          (0x2300)
 #define SDRFPR          (0x2340)
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig
index dbf0df8bb0ac..dce8decd5d46 100644
--- a/arch/arm/mach-cns3xxx/Kconfig
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -1,9 +1,6 @@
 config ARCH_CNS3XXX
         bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
         select ARM_GIC
-        select CPU_V6K
-        select GENERIC_CLOCKEVENTS
-        select MIGHT_HAVE_CACHE_L2X0
         select MIGHT_HAVE_PCI
         select PCI_DOMAINS if PCI
         help
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index a075b3e0c5c7..3b98e348d8d5 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -51,11 +51,6 @@ config ARCH_DAVINCI_DM365
         select AINTC
         select ARCH_DAVINCI_DMx
 
-config ARCH_DAVINCI_TNETV107X
-        bool "TNETV107X based system"
-        select CPU_V6
-        select CP_INTC
-
 comment "DaVinci Board Type"
 
 config MACH_DA8XX_DT
@@ -220,13 +215,6 @@ config GPIO_PCA953X
 config KEYBOARD_GPIO_POLLED
         default MACH_DAVINCI_DA850_EVM
 
-config MACH_TNETV107X
-        bool "TI TNETV107X Reference Platform"
-        default ARCH_DAVINCI_TNETV107X
-        depends on ARCH_DAVINCI_TNETV107X
-        help
-          Say Y here to select the TI TNETV107X Evaluation Module.
-
 config MACH_MITYOMAPL138
         bool "Critical Link MityDSP-L138/MityARM-1808 SoM"
         depends on ARCH_DAVINCI_DA850
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 63997a1128e6..2204239ed243 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -16,7 +16,6 @@ obj-$(CONFIG_ARCH_DAVINCI_DM646x)       += dm646x.o devices.o
 obj-$(CONFIG_ARCH_DAVINCI_DM365)        += dm365.o devices.o
 obj-$(CONFIG_ARCH_DAVINCI_DA830)        += da830.o devices-da8xx.o
 obj-$(CONFIG_ARCH_DAVINCI_DA850)        += da850.o devices-da8xx.o
-obj-$(CONFIG_ARCH_DAVINCI_TNETV107X)    += tnetv107x.o devices-tnetv107x.o
 
 obj-$(CONFIG_AINTC)                     += irq.o
 obj-$(CONFIG_CP_INTC)                   += cp_intc.o
@@ -32,7 +31,6 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM)	+= board-dm646x-evm.o cdce949.o
 obj-$(CONFIG_MACH_DAVINCI_DM365_EVM)    += board-dm365-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA830_EVM)    += board-da830-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)    += board-da850-evm.o
-obj-$(CONFIG_MACH_TNETV107X)            += board-tnetv107x-evm.o
 obj-$(CONFIG_MACH_MITYOMAPL138)         += board-mityomapl138.o
 obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD)   += board-omapl138-hawk.o
 
diff --git a/arch/arm/mach-davinci/Makefile.boot b/arch/arm/mach-davinci/Makefile.boot
index 04a6c4e67b14..4b81601754a2 100644
--- a/arch/arm/mach-davinci/Makefile.boot
+++ b/arch/arm/mach-davinci/Makefile.boot
@@ -1,13 +1,7 @@
-ifeq ($(CONFIG_ARCH_DAVINCI_DA8XX),y)
-ifeq ($(CONFIG_ARCH_DAVINCI_DMx),y)
-$(error Cannot enable DaVinci and DA8XX platforms concurrently)
-else
-   zreladdr-y   += 0xc0008000
-params_phys-y   := 0xc0000100
-initrd_phys-y   := 0xc0800000
-endif
-else
-   zreladdr-y   += 0x80008000
-params_phys-y   := 0x80000100
-initrd_phys-y   := 0x80800000
-endif
+zreladdr-$(CONFIG_ARCH_DAVINCI_DA8XX)           += 0xc0008000
+params_phys-$(CONFIG_ARCH_DAVINCI_DA8XX)        := 0xc0000100
+initrd_phys-$(CONFIG_ARCH_DAVINCI_DA8XX)        := 0xc0800000
+
+zreladdr-$(CONFIG_ARCH_DAVINCI_DMx)             += 0x80008000
+params_phys-$(CONFIG_ARCH_DAVINCI_DMx)          := 0x80000100
+initrd_phys-$(CONFIG_ARCH_DAVINCI_DMx)          := 0x80800000
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
deleted file mode 100644
index 78ea395d2aca..000000000000
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- * Texas Instruments TNETV107X EVM Board Support
- *
- * Copyright (C) 2010 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/dma-mapping.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/ratelimit.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/input.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/spi/spi.h>
-#include <linux/platform_data/edma.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <mach/irqs.h>
-#include <mach/mux.h>
-#include <mach/cp_intc.h>
-#include <mach/tnetv107x.h>
-
-#define EVM_MMC_WP_GPIO         21
-#define EVM_MMC_CD_GPIO         24
-#define EVM_SPI_CS_GPIO         54
-
-static int initialize_gpio(int gpio, char *desc)
-{
-        int ret;
-
-        ret = gpio_request(gpio, desc);
-        if (ret < 0) {
-                pr_err_ratelimited("cannot open %s gpio\n", desc);
-                return -ENOSYS;
-        }
-        gpio_direction_input(gpio);
-        return gpio;
-}
-
-static int mmc_get_cd(int index)
-{
-        static int gpio;
-
-        if (!gpio)
-                gpio = initialize_gpio(EVM_MMC_CD_GPIO, "mmc card detect");
-
-        if (gpio < 0)
-                return gpio;
-
-        return gpio_get_value(gpio) ? 0 : 1;
-}
-
-static int mmc_get_ro(int index)
-{
-        static int gpio;
-
-        if (!gpio)
-                gpio = initialize_gpio(EVM_MMC_WP_GPIO, "mmc write protect");
-
-        if (gpio < 0)
-                return gpio;
-
-        return gpio_get_value(gpio) ? 1 : 0;
-}
-
-static struct davinci_mmc_config mmc_config = {
-        .get_cd         = mmc_get_cd,
-        .get_ro         = mmc_get_ro,
-        .wires          = 4,
-        .max_freq       = 50000000,
-        .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-};
-
-static const short sdio1_pins[] __initconst = {
-        TNETV107X_SDIO1_CLK_1,          TNETV107X_SDIO1_CMD_1,
-        TNETV107X_SDIO1_DATA0_1,        TNETV107X_SDIO1_DATA1_1,
-        TNETV107X_SDIO1_DATA2_1,        TNETV107X_SDIO1_DATA3_1,
-        TNETV107X_GPIO21,               TNETV107X_GPIO24,
-        -1
-};
-
-static const short uart1_pins[] __initconst = {
-        TNETV107X_UART1_RD,             TNETV107X_UART1_TD,
-        -1
-};
-
-static const short ssp_pins[] __initconst = {
-        TNETV107X_SSP0_0, TNETV107X_SSP0_1, TNETV107X_SSP0_2,
-        TNETV107X_SSP1_0, TNETV107X_SSP1_1, TNETV107X_SSP1_2,
-        TNETV107X_SSP1_3, -1
-};
-
-static struct mtd_partition nand_partitions[] = {
-        /* bootloader (U-Boot, etc) in first 12 sectors */
-        {
-                .name           = "bootloader",
-                .offset         = 0,
-                .size           = (12*SZ_128K),
-                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
-        },
-        /* bootloader params in the next sector */
-        {
-                .name           = "params",
-                .offset         = MTDPART_OFS_NXTBLK,
-                .size           = SZ_128K,
-                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
-        },
-        /* kernel */
-        {
-                .name           = "kernel",
-                .offset         = MTDPART_OFS_NXTBLK,
-                .size           = SZ_4M,
-                .mask_flags     = 0,
-        },
-        /* file system */
-        {
-                .name           = "filesystem",
-                .offset         = MTDPART_OFS_NXTBLK,
-                .size           = MTDPART_SIZ_FULL,
-                .mask_flags     = 0,
-        }
-};
-
-static struct davinci_nand_pdata nand_config = {
-        .mask_cle       = 0x4000,
-        .mask_ale       = 0x2000,
-        .parts          = nand_partitions,
-        .nr_parts       = ARRAY_SIZE(nand_partitions),
-        .ecc_mode       = NAND_ECC_HW,
-        .bbt_options    = NAND_BBT_USE_FLASH,
-        .ecc_bits       = 1,
-};
-
-static struct davinci_uart_config serial_config __initconst = {
-        .enabled_uarts  = BIT(1),
-};
-
-static const uint32_t keymap[] = {
-        KEY(0, 0, KEY_NUMERIC_1),
-        KEY(0, 1, KEY_NUMERIC_2),
-        KEY(0, 2, KEY_NUMERIC_3),
-        KEY(0, 3, KEY_FN_F1),
-        KEY(0, 4, KEY_MENU),
-
-        KEY(1, 0, KEY_NUMERIC_4),
-        KEY(1, 1, KEY_NUMERIC_5),
-        KEY(1, 2, KEY_NUMERIC_6),
-        KEY(1, 3, KEY_UP),
-        KEY(1, 4, KEY_FN_F2),
-
-        KEY(2, 0, KEY_NUMERIC_7),
-        KEY(2, 1, KEY_NUMERIC_8),
-        KEY(2, 2, KEY_NUMERIC_9),
-        KEY(2, 3, KEY_LEFT),
-        KEY(2, 4, KEY_ENTER),
-
-        KEY(3, 0, KEY_NUMERIC_STAR),
-        KEY(3, 1, KEY_NUMERIC_0),
-        KEY(3, 2, KEY_NUMERIC_POUND),
-        KEY(3, 3, KEY_DOWN),
-        KEY(3, 4, KEY_RIGHT),
-
-        KEY(4, 0, KEY_FN_F3),
-        KEY(4, 1, KEY_FN_F4),
-        KEY(4, 2, KEY_MUTE),
-        KEY(4, 3, KEY_HOME),
-        KEY(4, 4, KEY_BACK),
-
-        KEY(5, 0, KEY_VOLUMEDOWN),
-        KEY(5, 1, KEY_VOLUMEUP),
-        KEY(5, 2, KEY_F1),
-        KEY(5, 3, KEY_F2),
-        KEY(5, 4, KEY_F3),
-};
-
-static const struct matrix_keymap_data keymap_data = {
-        .keymap         = keymap,
-        .keymap_size    = ARRAY_SIZE(keymap),
-};
-
-static struct matrix_keypad_platform_data keypad_config = {
-        .keymap_data    = &keymap_data,
-        .num_row_gpios  = 6,
-        .num_col_gpios  = 5,
-        .debounce_ms    = 0, /* minimum */
-        .active_low     = 0, /* pull up realization */
-        .no_autorepeat  = 0,
-};
-
-static void spi_select_device(int cs)
-{
-        static int gpio;
-
-        if (!gpio) {
-                int ret;
-                ret = gpio_request(EVM_SPI_CS_GPIO, "spi chipsel");
-                if (ret < 0) {
-                        pr_err("cannot open spi chipsel gpio\n");
-                        gpio = -ENOSYS;
-                        return;
-                } else {
-                        gpio = EVM_SPI_CS_GPIO;
-                        gpio_direction_output(gpio, 0);
-                }
-        }
-
-        if (gpio < 0)
-                return;
-
-        return gpio_set_value(gpio, cs ? 1 : 0);
-}
-
-static struct ti_ssp_spi_data spi_master_data = {
-        .num_cs = 2,
-        .select = spi_select_device,
-        .iosel  = SSP_PIN_SEL(0, SSP_CLOCK)     | SSP_PIN_SEL(1, SSP_DATA) |
-                  SSP_PIN_SEL(2, SSP_CHIPSEL)   | SSP_PIN_SEL(3, SSP_IN)   |
-                  SSP_INPUT_SEL(3),
-};
-
-static struct ti_ssp_data ssp_config = {
-        .out_clock      = 250 * 1000,
-        .dev_data       = {
-                [1] = {
-                        .dev_name = "ti-ssp-spi",
-                        .pdata = &spi_master_data,
-                        .pdata_size = sizeof(spi_master_data),
-                },
-        },
-};
-
-static struct tnetv107x_device_info evm_device_info __initconst = {
-        .serial_config          = &serial_config,
-        .mmc_config[1]          = &mmc_config,  /* controller 1 */
-        .nand_config[0]         = &nand_config, /* chip select 0 */
-        .keypad_config          = &keypad_config,
-        .ssp_config             = &ssp_config,
-};
-
-static struct spi_board_info spi_info[] __initconst = {
-};
-
-static __init void tnetv107x_evm_board_init(void)
-{
-        davinci_cfg_reg_list(sdio1_pins);
-        davinci_cfg_reg_list(uart1_pins);
-        davinci_cfg_reg_list(ssp_pins);
-
-        tnetv107x_devices_init(&evm_device_info);
-
-        spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
-}
-
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-static int __init tnetv107x_evm_console_init(void)
-{
-        return add_preferred_console("ttyS", 0, "115200");
-}
-console_initcall(tnetv107x_evm_console_init);
-#endif
-
-MACHINE_START(TNETV107X, "TNETV107X EVM")
-        .atag_offset    = 0x100,
-        .map_io         = tnetv107x_init,
-        .init_irq       = cp_intc_init,
-        .init_time      = davinci_timer_init,
-        .init_machine   = tnetv107x_evm_board_init,
-        .init_late      = davinci_init_late,
-        .dma_zone_size  = SZ_128M,
-        .restart        = tnetv107x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index 2eebc4338802..4ffc37accce0 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -79,6 +79,8 @@ int davinci_gpio_register(struct resource *res, int size, void *pdata);
 #define DM646X_ASYNC_EMIF_CONTROL_BASE  0x20008000
 #define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
 
+int davinci_init_wdt(void);
+
 /* DM355 function declarations */
 void dm355_init(void);
 void dm355_init_spi0(unsigned chipselect_mask,
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
deleted file mode 100644
index 01d8686e553c..000000000000
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ /dev/null
@@ -1,434 +0,0 @@
-/*
- * Texas Instruments TNETV107X SoC devices
- *
- * Copyright (C) 2010 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/clk.h>
-#include <linux/slab.h>
-#include <linux/platform_data/edma.h>
-
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/tnetv107x.h>
-
-#include "clock.h"
-
-/* Base addresses for on-chip devices */
-#define TNETV107X_TPCC_BASE                     0x01c00000
-#define TNETV107X_TPTC0_BASE                    0x01c10000
-#define TNETV107X_TPTC1_BASE                    0x01c10400
-#define TNETV107X_WDOG_BASE                     0x08086700
-#define TNETV107X_TSC_BASE                      0x08088500
-#define TNETV107X_SDIO0_BASE                    0x08088700
-#define TNETV107X_SDIO1_BASE                    0x08088800
-#define TNETV107X_KEYPAD_BASE                   0x08088a00
-#define TNETV107X_SSP_BASE                      0x08088c00
-#define TNETV107X_ASYNC_EMIF_CNTRL_BASE         0x08200000
-#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE      0x30000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE      0x40000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE      0x44000000
-#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE      0x48000000
-
-/* TNETV107X specific EDMA3 information */
-#define EDMA_TNETV107X_NUM_DMACH        64
-#define EDMA_TNETV107X_NUM_TCC          64
-#define EDMA_TNETV107X_NUM_PARAMENTRY   128
-#define EDMA_TNETV107X_NUM_EVQUE        2
-#define EDMA_TNETV107X_NUM_TC           2
-#define EDMA_TNETV107X_CHMAP_EXIST      0
-#define EDMA_TNETV107X_NUM_REGIONS      4
-#define TNETV107X_DMACH2EVENT_MAP0      0x3C0CE000u
-#define TNETV107X_DMACH2EVENT_MAP1      0x000FFFFFu
-
-#define TNETV107X_DMACH_SDIO0_RX                26
-#define TNETV107X_DMACH_SDIO0_TX                27
-#define TNETV107X_DMACH_SDIO1_RX                28
-#define TNETV107X_DMACH_SDIO1_TX                29
-
-static s8 edma_tc_mapping[][2] = {
-        /* event queue no       TC no   */
-        {        0,              0      },
-        {        1,              1      },
-        {       -1,             -1      }
-};
-
-static s8 edma_priority_mapping[][2] = {
-        /* event queue no       Prio    */
-        {        0,              3      },
-        {        1,              7      },
-        {       -1,             -1      }
-};
-
-static struct edma_soc_info edma_cc0_info = {
-        .n_channel              = EDMA_TNETV107X_NUM_DMACH,
-        .n_region               = EDMA_TNETV107X_NUM_REGIONS,
-        .n_slot                 = EDMA_TNETV107X_NUM_PARAMENTRY,
-        .n_tc                   = EDMA_TNETV107X_NUM_TC,
-        .n_cc                   = 1,
-        .queue_tc_mapping       = edma_tc_mapping,
-        .queue_priority_mapping = edma_priority_mapping,
-        .default_queue          = EVENTQ_1,
-};
-
-static struct edma_soc_info *tnetv107x_edma_info[EDMA_MAX_CC] = {
-        &edma_cc0_info,
-};
-
-static struct resource edma_resources[] = {
-        {
-                .name   = "edma_cc0",
-                .start  = TNETV107X_TPCC_BASE,
-                .end    = TNETV107X_TPCC_BASE + SZ_32K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "edma_tc0",
-                .start  = TNETV107X_TPTC0_BASE,
-                .end    = TNETV107X_TPTC0_BASE + SZ_1K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "edma_tc1",
-                .start  = TNETV107X_TPTC1_BASE,
-                .end    = TNETV107X_TPTC1_BASE + SZ_1K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "edma0",
-                .start  = IRQ_TNETV107X_TPCC,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .name   = "edma0_err",
-                .start  = IRQ_TNETV107X_TPCC_ERR,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device edma_device = {
-        .name           = "edma",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(edma_resources),
-        .resource       = edma_resources,
-        .dev.platform_data = tnetv107x_edma_info,
-};
-
-static struct plat_serial8250_port serial0_platform_data[] = {
-        {
-                .mapbase        = TNETV107X_UART0_BASE,
-                .irq            = IRQ_TNETV107X_UART0,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
-                                        UPF_FIXED_TYPE | UPF_IOREMAP,
-                .type           = PORT_AR7,
-                .iotype         = UPIO_MEM32,
-                .regshift       = 2,
-        },
-        {
-                .flags  = 0,
-        }
-};
-static struct plat_serial8250_port serial1_platform_data[] = {
-        {
-                .mapbase        = TNETV107X_UART1_BASE,
-                .irq            = IRQ_TNETV107X_UART1,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
-                                        UPF_FIXED_TYPE | UPF_IOREMAP,
-                .type           = PORT_AR7,
-                .iotype         = UPIO_MEM32,
-                .regshift       = 2,
-        },
-        {
-                .flags  = 0,
-        }
-};
-static struct plat_serial8250_port serial2_platform_data[] = {
-        {
-                .mapbase        = TNETV107X_UART2_BASE,
-                .irq            = IRQ_TNETV107X_UART2,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
-                                        UPF_FIXED_TYPE | UPF_IOREMAP,
-                .type           = PORT_AR7,
-                .iotype         = UPIO_MEM32,
-                .regshift       = 2,
-        },
-        {
-                .flags  = 0,
-        }
-};
-
-
-struct platform_device tnetv107x_serial_device[] = {
-        {
-                .name                   = "serial8250",
-                .id                     = PLAT8250_DEV_PLATFORM,
-                .dev.platform_data      = serial0_platform_data,
-        },
-        {
-                .name                   = "serial8250",
-                .id                     = PLAT8250_DEV_PLATFORM1,
-                .dev.platform_data      = serial1_platform_data,
-        },
-        {
-                .name                   = "serial8250",
-                .id                     = PLAT8250_DEV_PLATFORM2,
-                .dev.platform_data      = serial2_platform_data,
-        },
-        {
-        }
-};
-
-static struct resource mmc0_resources[] = {
-        { /* Memory mapped registers */
-                .start  = TNETV107X_SDIO0_BASE,
-                .end    = TNETV107X_SDIO0_BASE + 0x0ff,
-                .flags  = IORESOURCE_MEM
-        },
-        { /* MMC interrupt */
-                .start  = IRQ_TNETV107X_MMC0,
-                .flags  = IORESOURCE_IRQ
-        },
-        { /* SDIO interrupt */
-                .start  = IRQ_TNETV107X_SDIO0,
-                .flags  = IORESOURCE_IRQ
-        },
-        { /* DMA RX */
-                .start  = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_RX),
-                .flags  = IORESOURCE_DMA
-        },
-        { /* DMA TX */
-                .start  = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_TX),
-                .flags  = IORESOURCE_DMA
-        },
-};
-
-static struct resource mmc1_resources[] = {
-        { /* Memory mapped registers */
-                .start  = TNETV107X_SDIO1_BASE,
-                .end    = TNETV107X_SDIO1_BASE + 0x0ff,
-                .flags  = IORESOURCE_MEM
-        },
-        { /* MMC interrupt */
-                .start  = IRQ_TNETV107X_MMC1,
-                .flags  = IORESOURCE_IRQ
-        },
-        { /* SDIO interrupt */
-                .start  = IRQ_TNETV107X_SDIO1,
-                .flags  = IORESOURCE_IRQ
-        },
-        { /* DMA RX */
-                .start  = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_RX),
-                .flags  = IORESOURCE_DMA
-        },
-        { /* DMA TX */
-                .start  = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_TX),
-                .flags  = IORESOURCE_DMA
-        },
-};
-
-static u64 mmc0_dma_mask = DMA_BIT_MASK(32);
-static u64 mmc1_dma_mask = DMA_BIT_MASK(32);
-
-static struct platform_device mmc_devices[2] = {
-        {
-                .name           = "dm6441-mmc",
-                .id             = 0,
-                .dev            = {
-                        .dma_mask               = &mmc0_dma_mask,
-                        .coherent_dma_mask      = DMA_BIT_MASK(32),
-                },
-                .num_resources  = ARRAY_SIZE(mmc0_resources),
-                .resource       = mmc0_resources
-        },
-        {
-                .name           = "dm6441-mmc",
-                .id             = 1,
-                .dev            = {
-                        .dma_mask               = &mmc1_dma_mask,
-                        .coherent_dma_mask      = DMA_BIT_MASK(32),
-                },
-                .num_resources  = ARRAY_SIZE(mmc1_resources),
-                .resource       = mmc1_resources
-        },
-};
-
-static const u32 emif_windows[] = {
-        TNETV107X_ASYNC_EMIF_DATA_CE0_BASE, TNETV107X_ASYNC_EMIF_DATA_CE1_BASE,
-        TNETV107X_ASYNC_EMIF_DATA_CE2_BASE, TNETV107X_ASYNC_EMIF_DATA_CE3_BASE,
-};
-
-static const u32 emif_window_sizes[] = { SZ_256M, SZ_64M, SZ_64M, SZ_64M };
-
-static struct resource wdt_resources[] = {
-        {
-                .start  = TNETV107X_WDOG_BASE,
-                .end    = TNETV107X_WDOG_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-struct platform_device tnetv107x_wdt_device = {
-        .name           = "tnetv107x_wdt",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(wdt_resources),
-        .resource       = wdt_resources,
-};
-
-static int __init nand_init(int chipsel, struct davinci_nand_pdata *data)
-{
-        struct resource res[2];
-        struct platform_device *pdev;
-        u32     range;
-        int     ret;
-
-        /* Figure out the resource range from the ale/cle masks */
-        range = max(data->mask_cle, data->mask_ale);
-        range = PAGE_ALIGN(range + 4) - 1;
-
-        if (range >= emif_window_sizes[chipsel])
-                return -EINVAL;
-
-        pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
-        if (!pdev)
-                return -ENOMEM;
-
-        pdev->name              = "davinci_nand";
-        pdev->id                = chipsel;
-        pdev->dev.platform_data = data;
-
-        memset(res, 0, sizeof(res));
-
-        res[0].start    = emif_windows[chipsel];
-        res[0].end      = res[0].start + range;
-        res[0].flags    = IORESOURCE_MEM;
-
-        res[1].start    = TNETV107X_ASYNC_EMIF_CNTRL_BASE;
-        res[1].end      = res[1].start + SZ_4K - 1;
-        res[1].flags    = IORESOURCE_MEM;
-
-        ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
-        if (ret < 0) {
-                kfree(pdev);
-                return ret;
-        }
-
-        return platform_device_register(pdev);
-}
-
-static struct resource keypad_resources[] = {
-        {
-                .start  = TNETV107X_KEYPAD_BASE,
-                .end    = TNETV107X_KEYPAD_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = IRQ_TNETV107X_KEYPAD,
-                .flags  = IORESOURCE_IRQ,
-                .name   = "press",
-        },
-        {
-                .start  = IRQ_TNETV107X_KEYPAD_FREE,
-                .flags  = IORESOURCE_IRQ,
-                .name   = "release",
-        },
-};
-
-static struct platform_device keypad_device = {
-        .name           = "tnetv107x-keypad",
-        .num_resources  = ARRAY_SIZE(keypad_resources),
-        .resource       = keypad_resources,
-};
-
-static struct resource tsc_resources[] = {
-        {
-                .start  = TNETV107X_TSC_BASE,
-                .end    = TNETV107X_TSC_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = IRQ_TNETV107X_TSC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device tsc_device = {
-        .name           = "tnetv107x-ts",
-        .num_resources  = ARRAY_SIZE(tsc_resources),
-        .resource       = tsc_resources,
-};
-
-static struct resource ssp_resources[] = {
-        {
-                .start  = TNETV107X_SSP_BASE,
-                .end    = TNETV107X_SSP_BASE + 0x1ff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = IRQ_TNETV107X_SSP,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device ssp_device = {
-        .name           = "ti-ssp",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(ssp_resources),
-        .resource       = ssp_resources,
-};
-
-void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
-{
-        int i, error;
-        struct clk *tsc_clk;
-
-        /*
-         * The reset defaults for tnetv107x tsc clock divider is set too high.
-         * This forces the clock down to a range that allows the ADC to
-         * complete sample conversion in time.
-         */
-        tsc_clk = clk_get(NULL, "sys_tsc_clk");
-        if (!IS_ERR(tsc_clk)) {
-                error = clk_set_rate(tsc_clk, 5000000);
-                WARN_ON(error < 0);
-                clk_put(tsc_clk);
-        }
-
-        platform_device_register(&edma_device);
-        platform_device_register(&tnetv107x_wdt_device);
-        platform_device_register(&tsc_device);
-
-        if (info->serial_config)
-                davinci_serial_init(tnetv107x_serial_device);
-
-        for (i = 0; i < 2; i++)
-                if (info->mmc_config[i]) {
-                        mmc_devices[i].dev.platform_data = info->mmc_config[i];
-                        platform_device_register(&mmc_devices[i]);
-                }
-
-        for (i = 0; i < 4; i++)
-                if (info->nand_config[i])
-                        nand_init(i, info->nand_config[i]);
-
-        if (info->keypad_config) {
-                keypad_device.dev.platform_data = info->keypad_config;
-                platform_device_register(&keypad_device);
-        }
-
-        if (info->ssp_config) {
-                ssp_device.dev.platform_data = info->ssp_config;
-                platform_device_register(&ssp_device);
-        }
-}
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 5cf9a027dcc6..6257aa452568 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -313,9 +313,9 @@ void davinci_restart(enum reboot_mode mode, const char *cmd)
         davinci_watchdog_reset(&davinci_wdt_device);
 }
 
-static void davinci_init_wdt(void)
+int davinci_init_wdt(void)
 {
-        platform_device_register(&davinci_wdt_device);
+        return platform_device_register(&davinci_wdt_device);
 }
 
 static struct platform_device davinci_gpio_device = {
@@ -348,16 +348,3 @@ struct davinci_timer_instance davinci_timer_instance[2] = {
         },
 };
 
-/*-------------------------------------------------------------------------*/
-
-static int __init davinci_init_devices(void)
-{
-        /* please keep these calls, and their implementations above,
-         * in alphabetical order so they're easier to sort through.
-         */
-        davinci_init_wdt();
-
-        return 0;
-}
-arch_initcall(davinci_init_devices);
-
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 4668c0e19767..07381d8cea62 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -1076,12 +1076,18 @@ int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
 
 static int __init dm355_init_devices(void)
 {
+        int ret = 0;
+
         if (!cpu_is_davinci_dm355())
                 return 0;
 
         davinci_cfg_reg(DM355_INT_EDMA_CC);
         platform_device_register(&dm355_edma_device);
 
-        return 0;
+        ret = davinci_init_wdt();
+        if (ret)
+                pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
+
+        return ret;
 }
 postcore_initcall(dm355_init_devices);
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index b44b49e2801a..08a61b938333 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1436,6 +1436,8 @@ int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
 
 static int __init dm365_init_devices(void)
 {
+        int ret = 0;
+
         if (!cpu_is_davinci_dm365())
                 return 0;
 
@@ -1445,6 +1447,10 @@ static int __init dm365_init_devices(void)
         platform_device_register(&dm365_mdio_device);
         platform_device_register(&dm365_emac_device);
 
-        return 0;
+        ret = davinci_init_wdt();
+        if (ret)
+                pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
+
+        return ret;
 }
 postcore_initcall(dm365_init_devices);
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 5c3e0be95ef3..5debffba4b24 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -964,6 +964,8 @@ int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
 
 static int __init dm644x_init_devices(void)
 {
+        int ret = 0;
+
         if (!cpu_is_davinci_dm644x())
                 return 0;
 
@@ -972,6 +974,10 @@ static int __init dm644x_init_devices(void)
         platform_device_register(&dm644x_mdio_device);
         platform_device_register(&dm644x_emac_device);
 
-        return 0;
+        ret = davinci_init_wdt();
+        if (ret)
+                pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
+
+        return ret;
 }
 postcore_initcall(dm644x_init_devices);
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 81768dd47096..332d00d24dc2 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -955,12 +955,18 @@ void __init dm646x_init(void)
 
 static int __init dm646x_init_devices(void)
 {
+        int ret = 0;
+
         if (!cpu_is_davinci_dm646x())
                 return 0;
 
         platform_device_register(&dm646x_mdio_device);
         platform_device_register(&dm646x_emac_device);
 
-        return 0;
+        ret = davinci_init_wdt();
+        if (ret)
+                pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
+
+        return ret;
 }
 postcore_initcall(dm646x_init_devices);
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index 957fb87e832e..1fc84e21664d 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -33,7 +33,6 @@ struct davinci_id {
 #define DAVINCI_CPU_ID_DM365            0x03650000
 #define DAVINCI_CPU_ID_DA830            0x08300000
 #define DAVINCI_CPU_ID_DA850            0x08500000
-#define DAVINCI_CPU_ID_TNETV107X        0x0b8a0000
 
 #define IS_DAVINCI_CPU(type, id)                                        \
 static inline int is_davinci_ ##type(void)                              \
@@ -47,7 +46,6 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
 IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
 IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
 IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
-IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
 
 #ifdef CONFIG_ARCH_DAVINCI_DM644x
 #define cpu_is_davinci_dm644x() is_davinci_dm644x()
@@ -85,10 +83,4 @@ IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
 #define cpu_is_davinci_da850() 0
 #endif
 
-#ifdef CONFIG_ARCH_DAVINCI_TNETV107X
-#define cpu_is_davinci_tnetv107x() is_davinci_tnetv107x()
-#else
-#define cpu_is_davinci_tnetv107x() 0
-#endif
-
 #endif
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index ec76c7775c2e..354af71798dc 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -401,103 +401,6 @@
 
 #define DA850_N_CP_INTC_IRQ             101
 
-
-/* TNETV107X specific interrupts */
-#define IRQ_TNETV107X_TDM1_TXDMA                0
-#define IRQ_TNETV107X_EXT_INT_0                 1
-#define IRQ_TNETV107X_EXT_INT_1                 2
-#define IRQ_TNETV107X_GPIO_INT12                3
-#define IRQ_TNETV107X_GPIO_INT13                4
-#define IRQ_TNETV107X_TIMER_0_TINT12            5
-#define IRQ_TNETV107X_TIMER_1_TINT12            6
-#define IRQ_TNETV107X_UART0                     7
-#define IRQ_TNETV107X_TDM1_RXDMA                8
-#define IRQ_TNETV107X_MCDMA_INT0                9
-#define IRQ_TNETV107X_MCDMA_INT1                10
-#define IRQ_TNETV107X_TPCC                      11
-#define IRQ_TNETV107X_TPCC_INT0                 12
-#define IRQ_TNETV107X_TPCC_INT1                 13
-#define IRQ_TNETV107X_TPCC_INT2                 14
-#define IRQ_TNETV107X_TPCC_INT3                 15
-#define IRQ_TNETV107X_TPTC0                     16
-#define IRQ_TNETV107X_TPTC1                     17
-#define IRQ_TNETV107X_TIMER_0_TINT34            18
-#define IRQ_TNETV107X_ETHSS                     19
-#define IRQ_TNETV107X_TIMER_1_TINT34            20
-#define IRQ_TNETV107X_DSP2ARM_INT0              21
-#define IRQ_TNETV107X_DSP2ARM_INT1              22
-#define IRQ_TNETV107X_ARM_NPMUIRQ               23
-#define IRQ_TNETV107X_USB1                      24
-#define IRQ_TNETV107X_VLYNQ                     25
-#define IRQ_TNETV107X_UART0_DMATX               26
-#define IRQ_TNETV107X_UART0_DMARX               27
-#define IRQ_TNETV107X_TDM1_TXMCSP               28
-#define IRQ_TNETV107X_SSP                       29
-#define IRQ_TNETV107X_MCDMA_INT2                30
-#define IRQ_TNETV107X_MCDMA_INT3                31
-#define IRQ_TNETV107X_TDM_CODECIF_EOT           32
-#define IRQ_TNETV107X_IMCOP_SQR_ARM             33
-#define IRQ_TNETV107X_USB0                      34
-#define IRQ_TNETV107X_USB_CDMA                  35
-#define IRQ_TNETV107X_LCD                       36
-#define IRQ_TNETV107X_KEYPAD                    37
-#define IRQ_TNETV107X_KEYPAD_FREE               38
-#define IRQ_TNETV107X_RNG                       39
-#define IRQ_TNETV107X_PKA                       40
-#define IRQ_TNETV107X_TDM0_TXDMA                41
-#define IRQ_TNETV107X_TDM0_RXDMA                42
-#define IRQ_TNETV107X_TDM0_TXMCSP               43
-#define IRQ_TNETV107X_TDM0_RXMCSP               44
-#define IRQ_TNETV107X_TDM1_RXMCSP               45
-#define IRQ_TNETV107X_SDIO1                     46
-#define IRQ_TNETV107X_SDIO0                     47
-#define IRQ_TNETV107X_TSC                       48
-#define IRQ_TNETV107X_TS                        49
-#define IRQ_TNETV107X_UART1                     50
-#define IRQ_TNETV107X_MBX_LITE                  51
-#define IRQ_TNETV107X_GPIO_INT00                52
-#define IRQ_TNETV107X_GPIO_INT01                53
-#define IRQ_TNETV107X_GPIO_INT02                54
-#define IRQ_TNETV107X_GPIO_INT03                55
-#define IRQ_TNETV107X_UART2                     56
-#define IRQ_TNETV107X_UART2_DMATX               57
-#define IRQ_TNETV107X_UART2_DMARX               58
-#define IRQ_TNETV107X_IMCOP_IMX                 59
-#define IRQ_TNETV107X_IMCOP_VLCD                60
-#define IRQ_TNETV107X_AES                       61
-#define IRQ_TNETV107X_DES                       62
-#define IRQ_TNETV107X_SHAMD5                    63
-#define IRQ_TNETV107X_TPCC_ERR                  68
-#define IRQ_TNETV107X_TPCC_PROT                 69
-#define IRQ_TNETV107X_TPTC0_ERR                 70
-#define IRQ_TNETV107X_TPTC1_ERR                 71
-#define IRQ_TNETV107X_UART0_ERR                 72
-#define IRQ_TNETV107X_UART1_ERR                 73
-#define IRQ_TNETV107X_AEMIF_ERR                 74
-#define IRQ_TNETV107X_DDR_ERR                   75
-#define IRQ_TNETV107X_WDTARM_INT0               76
-#define IRQ_TNETV107X_MCDMA_ERR                 77
-#define IRQ_TNETV107X_GPIO_ERR                  78
-#define IRQ_TNETV107X_MPU_ADDR                  79
-#define IRQ_TNETV107X_MPU_PROT                  80
-#define IRQ_TNETV107X_IOPU_ADDR                 81
-#define IRQ_TNETV107X_IOPU_PROT                 82
-#define IRQ_TNETV107X_KEYPAD_ADDR_ERR           83
-#define IRQ_TNETV107X_WDT0_ADDR_ERR             84
-#define IRQ_TNETV107X_WDT1_ADDR_ERR             85
-#define IRQ_TNETV107X_CLKCTL_ADDR_ERR           86
-#define IRQ_TNETV107X_PLL_UNLOCK                87
-#define IRQ_TNETV107X_WDTDSP_INT0               88
-#define IRQ_TNETV107X_SEC_CTRL_VIOLATION        89
-#define IRQ_TNETV107X_KEY_MNG_VIOLATION         90
-#define IRQ_TNETV107X_PBIST_CPU                 91
-#define IRQ_TNETV107X_WDTARM                    92
-#define IRQ_TNETV107X_PSC                       93
-#define IRQ_TNETV107X_MMC0                      94
-#define IRQ_TNETV107X_MMC1                      95
-
-#define TNETV107X_N_CP_INTC_IRQ                 96
-
 /* da850 currently has the most gpio pins (144) */
 #define DAVINCI_N_GPIO                  144
 /* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 9e95b8a1edb6..631655e68ae0 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -972,275 +972,6 @@ enum davinci_da850_index {
         DA850_VPIF_CLKO3,
 };
 
-enum davinci_tnetv107x_index {
-        TNETV107X_ASR_A00,
-        TNETV107X_GPIO32,
-        TNETV107X_ASR_A01,
-        TNETV107X_GPIO33,
-        TNETV107X_ASR_A02,
-        TNETV107X_GPIO34,
-        TNETV107X_ASR_A03,
-        TNETV107X_GPIO35,
-        TNETV107X_ASR_A04,
-        TNETV107X_GPIO36,
-        TNETV107X_ASR_A05,
-        TNETV107X_GPIO37,
-        TNETV107X_ASR_A06,
-        TNETV107X_GPIO38,
-        TNETV107X_ASR_A07,
-        TNETV107X_GPIO39,
-        TNETV107X_ASR_A08,
-        TNETV107X_GPIO40,
-        TNETV107X_ASR_A09,
-        TNETV107X_GPIO41,
-        TNETV107X_ASR_A10,
-        TNETV107X_GPIO42,
-        TNETV107X_ASR_A11,
-        TNETV107X_BOOT_STRP_0,
-        TNETV107X_ASR_A12,
-        TNETV107X_BOOT_STRP_1,
-        TNETV107X_ASR_A13,
-        TNETV107X_GPIO43,
-        TNETV107X_ASR_A14,
-        TNETV107X_GPIO44,
-        TNETV107X_ASR_A15,
-        TNETV107X_GPIO45,
-        TNETV107X_ASR_A16,
-        TNETV107X_GPIO46,
-        TNETV107X_ASR_A17,
-        TNETV107X_GPIO47,
-        TNETV107X_ASR_A18,
-        TNETV107X_GPIO48,
-        TNETV107X_SDIO1_DATA3_0,
-        TNETV107X_ASR_A19,
-        TNETV107X_GPIO49,
-        TNETV107X_SDIO1_DATA2_0,
-        TNETV107X_ASR_A20,
-        TNETV107X_GPIO50,
-        TNETV107X_SDIO1_DATA1_0,
-        TNETV107X_ASR_A21,
-        TNETV107X_GPIO51,
-        TNETV107X_SDIO1_DATA0_0,
-        TNETV107X_ASR_A22,
-        TNETV107X_GPIO52,
-        TNETV107X_SDIO1_CMD_0,
-        TNETV107X_ASR_A23,
-        TNETV107X_GPIO53,
-        TNETV107X_SDIO1_CLK_0,
-        TNETV107X_ASR_BA_1,
-        TNETV107X_GPIO54,
-        TNETV107X_SYS_PLL_CLK,
-        TNETV107X_ASR_CS0,
-        TNETV107X_ASR_CS1,
-        TNETV107X_ASR_CS2,
-        TNETV107X_TDM_PLL_CLK,
-        TNETV107X_ASR_CS3,
-        TNETV107X_ETH_PHY_CLK,
-        TNETV107X_ASR_D00,
-        TNETV107X_GPIO55,
-        TNETV107X_ASR_D01,
-        TNETV107X_GPIO56,
-        TNETV107X_ASR_D02,
-        TNETV107X_GPIO57,
-        TNETV107X_ASR_D03,
-        TNETV107X_GPIO58,
-        TNETV107X_ASR_D04,
-        TNETV107X_GPIO59_0,
-        TNETV107X_ASR_D05,
-        TNETV107X_GPIO60_0,
-        TNETV107X_ASR_D06,
-        TNETV107X_GPIO61_0,
-        TNETV107X_ASR_D07,
-        TNETV107X_GPIO62_0,
-        TNETV107X_ASR_D08,
-        TNETV107X_GPIO63_0,
-        TNETV107X_ASR_D09,
-        TNETV107X_GPIO64_0,
-        TNETV107X_ASR_D10,
-        TNETV107X_SDIO1_DATA3_1,
-        TNETV107X_ASR_D11,
-        TNETV107X_SDIO1_DATA2_1,
-        TNETV107X_ASR_D12,
-        TNETV107X_SDIO1_DATA1_1,
-        TNETV107X_ASR_D13,
-        TNETV107X_SDIO1_DATA0_1,
-        TNETV107X_ASR_D14,
-        TNETV107X_SDIO1_CMD_1,
-        TNETV107X_ASR_D15,
-        TNETV107X_SDIO1_CLK_1,
-        TNETV107X_ASR_OE,
-        TNETV107X_BOOT_STRP_2,
-        TNETV107X_ASR_RNW,
-        TNETV107X_GPIO29_0,
-        TNETV107X_ASR_WAIT,
-        TNETV107X_GPIO30_0,
-        TNETV107X_ASR_WE,
-        TNETV107X_BOOT_STRP_3,
-        TNETV107X_ASR_WE_DQM0,
-        TNETV107X_GPIO31,
-        TNETV107X_LCD_PD17_0,
-        TNETV107X_ASR_WE_DQM1,
-        TNETV107X_ASR_BA0_0,
-        TNETV107X_VLYNQ_CLK,
-        TNETV107X_GPIO14,
-        TNETV107X_LCD_PD19_0,
-        TNETV107X_VLYNQ_RXD0,
-        TNETV107X_GPIO15,
-        TNETV107X_LCD_PD20_0,
-        TNETV107X_VLYNQ_RXD1,
-        TNETV107X_GPIO16,
-        TNETV107X_LCD_PD21_0,
-        TNETV107X_VLYNQ_TXD0,
-        TNETV107X_GPIO17,
-        TNETV107X_LCD_PD22_0,
-        TNETV107X_VLYNQ_TXD1,
-        TNETV107X_GPIO18,
-        TNETV107X_LCD_PD23_0,
-        TNETV107X_SDIO0_CLK,
-        TNETV107X_GPIO19,
-        TNETV107X_SDIO0_CMD,
-        TNETV107X_GPIO20,
-        TNETV107X_SDIO0_DATA0,
-        TNETV107X_GPIO21,
-        TNETV107X_SDIO0_DATA1,
-        TNETV107X_GPIO22,
-        TNETV107X_SDIO0_DATA2,
-        TNETV107X_GPIO23,
-        TNETV107X_SDIO0_DATA3,
-        TNETV107X_GPIO24,
-        TNETV107X_EMU0,
-        TNETV107X_EMU1,
-        TNETV107X_RTCK,
-        TNETV107X_TRST_N,
-        TNETV107X_TCK,
-        TNETV107X_TDI,
-        TNETV107X_TDO,
-        TNETV107X_TMS,
-        TNETV107X_TDM1_CLK,
-        TNETV107X_TDM1_RX,
-        TNETV107X_TDM1_TX,
-        TNETV107X_TDM1_FS,
-        TNETV107X_KEYPAD_R0,
-        TNETV107X_KEYPAD_R1,
-        TNETV107X_KEYPAD_R2,
-        TNETV107X_KEYPAD_R3,
-        TNETV107X_KEYPAD_R4,
-        TNETV107X_KEYPAD_R5,
-        TNETV107X_KEYPAD_R6,
-        TNETV107X_GPIO12,
-        TNETV107X_KEYPAD_R7,
-        TNETV107X_GPIO10,
-        TNETV107X_KEYPAD_C0,
-        TNETV107X_KEYPAD_C1,
-        TNETV107X_KEYPAD_C2,
-        TNETV107X_KEYPAD_C3,
-        TNETV107X_KEYPAD_C4,
-        TNETV107X_KEYPAD_C5,
-        TNETV107X_KEYPAD_C6,
-        TNETV107X_GPIO13,
-        TNETV107X_TEST_CLK_IN,
-        TNETV107X_KEYPAD_C7,
-        TNETV107X_GPIO11,
-        TNETV107X_SSP0_0,
-        TNETV107X_SCC_DCLK,
-        TNETV107X_LCD_PD20_1,
-        TNETV107X_SSP0_1,
-        TNETV107X_SCC_CS_N,
-        TNETV107X_LCD_PD21_1,
-        TNETV107X_SSP0_2,
-        TNETV107X_SCC_D,
-        TNETV107X_LCD_PD22_1,
-        TNETV107X_SSP0_3,
-        TNETV107X_SCC_RESETN,
-        TNETV107X_LCD_PD23_1,
-        TNETV107X_SSP1_0,
-        TNETV107X_GPIO25,
-        TNETV107X_UART2_CTS,
-        TNETV107X_SSP1_1,
-        TNETV107X_GPIO26,
-        TNETV107X_UART2_RD,
-        TNETV107X_SSP1_2,
-        TNETV107X_GPIO27,
-        TNETV107X_UART2_RTS,
-        TNETV107X_SSP1_3,
-        TNETV107X_GPIO28,
-        TNETV107X_UART2_TD,
-        TNETV107X_UART0_CTS,
-        TNETV107X_UART0_RD,
-        TNETV107X_UART0_RTS,
-        TNETV107X_UART0_TD,
-        TNETV107X_UART1_RD,
-        TNETV107X_UART1_TD,
-        TNETV107X_LCD_AC_NCS,
-        TNETV107X_LCD_HSYNC_RNW,
-        TNETV107X_LCD_VSYNC_A0,
-        TNETV107X_LCD_MCLK,
-        TNETV107X_LCD_PD16_0,
-        TNETV107X_LCD_PCLK_E,
-        TNETV107X_LCD_PD00,
-        TNETV107X_LCD_PD01,
-        TNETV107X_LCD_PD02,
-        TNETV107X_LCD_PD03,
-        TNETV107X_LCD_PD04,
-        TNETV107X_LCD_PD05,
-        TNETV107X_LCD_PD06,
-        TNETV107X_LCD_PD07,
-        TNETV107X_LCD_PD08,
-        TNETV107X_GPIO59_1,
-        TNETV107X_LCD_PD09,
-        TNETV107X_GPIO60_1,
-        TNETV107X_LCD_PD10,
-        TNETV107X_ASR_BA0_1,
-        TNETV107X_GPIO61_1,
-        TNETV107X_LCD_PD11,
-        TNETV107X_GPIO62_1,
-        TNETV107X_LCD_PD12,
-        TNETV107X_GPIO63_1,
-        TNETV107X_LCD_PD13,
-        TNETV107X_GPIO64_1,
-        TNETV107X_LCD_PD14,
-        TNETV107X_GPIO29_1,
-        TNETV107X_LCD_PD15,
-        TNETV107X_GPIO30_1,
-        TNETV107X_EINT0,
-        TNETV107X_GPIO08,
-        TNETV107X_EINT1,
-        TNETV107X_GPIO09,
-        TNETV107X_GPIO00,
-        TNETV107X_LCD_PD20_2,
-        TNETV107X_TDM_CLK_IN_2,
-        TNETV107X_GPIO01,
-        TNETV107X_LCD_PD21_2,
-        TNETV107X_24M_CLK_OUT_1,
-        TNETV107X_GPIO02,
-        TNETV107X_LCD_PD22_2,
-        TNETV107X_GPIO03,
-        TNETV107X_LCD_PD23_2,
-        TNETV107X_GPIO04,
-        TNETV107X_LCD_PD16_1,
-        TNETV107X_USB0_RXERR,
-        TNETV107X_GPIO05,
-        TNETV107X_LCD_PD17_1,
-        TNETV107X_TDM_CLK_IN_1,
-        TNETV107X_GPIO06,
-        TNETV107X_LCD_PD18,
-        TNETV107X_24M_CLK_OUT_2,
-        TNETV107X_GPIO07,
-        TNETV107X_LCD_PD19_1,
-        TNETV107X_USB1_RXERR,
-        TNETV107X_ETH_PLL_CLK,
-        TNETV107X_MDIO,
-        TNETV107X_MDC,
-        TNETV107X_AIC_MUTE_STAT_N,
-        TNETV107X_TDM0_CLK,
-        TNETV107X_AIC_HNS_EN_N,
-        TNETV107X_TDM0_FS,
-        TNETV107X_AIC_HDS_EN_STAT_N,
-        TNETV107X_TDM0_TX,
-        TNETV107X_AIC_HNF_EN_STAT_N,
-        TNETV107X_TDM0_RX,
-};
-
 #define PINMUX(x)               (4 * (x))
 
 #ifdef CONFIG_DAVINCI_MUX
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 0a22710493fd..99d47cfa301f 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -182,53 +182,6 @@
 #define DA8XX_LPSC1_CR_P3_SS            26
 #define DA8XX_LPSC1_L3_CBA_RAM          31
 
-/* TNETV107X LPSC Assignments */
-#define TNETV107X_LPSC_ARM                      0
-#define TNETV107X_LPSC_GEM                      1
-#define TNETV107X_LPSC_DDR2_PHY                 2
-#define TNETV107X_LPSC_TPCC                     3
-#define TNETV107X_LPSC_TPTC0                    4
-#define TNETV107X_LPSC_TPTC1                    5
-#define TNETV107X_LPSC_RAM                      6
-#define TNETV107X_LPSC_MBX_LITE                 7
-#define TNETV107X_LPSC_LCD                      8
-#define TNETV107X_LPSC_ETHSS                    9
-#define TNETV107X_LPSC_AEMIF                    10
-#define TNETV107X_LPSC_CHIP_CFG                 11
-#define TNETV107X_LPSC_TSC                      12
-#define TNETV107X_LPSC_ROM                      13
-#define TNETV107X_LPSC_UART2                    14
-#define TNETV107X_LPSC_PKTSEC                   15
-#define TNETV107X_LPSC_SECCTL                   16
-#define TNETV107X_LPSC_KEYMGR                   17
-#define TNETV107X_LPSC_KEYPAD                   18
-#define TNETV107X_LPSC_GPIO                     19
-#define TNETV107X_LPSC_MDIO                     20
-#define TNETV107X_LPSC_SDIO0                    21
-#define TNETV107X_LPSC_UART0                    22
-#define TNETV107X_LPSC_UART1                    23
-#define TNETV107X_LPSC_TIMER0                   24
-#define TNETV107X_LPSC_TIMER1                   25
-#define TNETV107X_LPSC_WDT_ARM                  26
-#define TNETV107X_LPSC_WDT_DSP                  27
-#define TNETV107X_LPSC_SSP                      28
-#define TNETV107X_LPSC_TDM0                     29
-#define TNETV107X_LPSC_VLYNQ                    30
-#define TNETV107X_LPSC_MCDMA                    31
-#define TNETV107X_LPSC_USB0                     32
-#define TNETV107X_LPSC_TDM1                     33
-#define TNETV107X_LPSC_DEBUGSS                  34
-#define TNETV107X_LPSC_ETHSS_RGMII              35
-#define TNETV107X_LPSC_SYSTEM                   36
-#define TNETV107X_LPSC_IMCOP                    37
-#define TNETV107X_LPSC_SPARE                    38
-#define TNETV107X_LPSC_SDIO1                    39
-#define TNETV107X_LPSC_USB1                     40
-#define TNETV107X_LPSC_USBSS                    41
-#define TNETV107X_LPSC_DDR2_EMIF1_VRST          42
-#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST      43
-#define TNETV107X_LPSC_MAX                      44
-
 /* PSC register offsets */
 #define EPCPR           0x070
 #define PTCMD           0x120
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index ce402cd21fa0..d4b4aa87964f 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -23,14 +23,6 @@
 #define DA8XX_UART1_BASE        (IO_PHYS + 0x10c000)
 #define DA8XX_UART2_BASE        (IO_PHYS + 0x10d000)
 
-#define TNETV107X_UART0_BASE    0x08108100
-#define TNETV107X_UART1_BASE    0x08088400
-#define TNETV107X_UART2_BASE    0x08108300
-
-#define TNETV107X_UART0_VIRT    IOMEM(0xfee08100)
-#define TNETV107X_UART1_VIRT    IOMEM(0xfed88400)
-#define TNETV107X_UART2_VIRT    IOMEM(0xfee08300)
-
 /* DaVinci UART register offsets */
 #define UART_DAVINCI_PWREMU             0x0c
 #define UART_DM646X_SCR                 0x10
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
deleted file mode 100644
index 494fcf5ccfe1..000000000000
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Texas Instruments TNETV107X SoC Specific Defines
- *
- * Copyright (C) 2010 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __ASM_ARCH_DAVINCI_TNETV107X_H
-#define __ASM_ARCH_DAVINCI_TNETV107X_H
-
-#include <asm/sizes.h>
-
-#define TNETV107X_DDR_BASE      0x80000000
-
-/*
- * Fixed mapping for early init starts here. If low-level debug is enabled,
- * this area also gets mapped via io_pg_offset and io_phys by the boot code.
- * To fit in with the io_pg_offset calculation, the io base address selected
- * here _must_ be a multiple of 2^20.
- */
-#define TNETV107X_IO_BASE       0x08000000
-#define TNETV107X_IO_VIRT       (IO_VIRT + SZ_1M)
-
-#define TNETV107X_N_GPIO        65
-
-#ifndef __ASSEMBLY__
-
-#include <linux/serial_8250.h>
-#include <linux/input/matrix_keypad.h>
-#include <linux/mfd/ti_ssp.h>
-#include <linux/reboot.h>
-
-#include <linux/platform_data/mmc-davinci.h>
-#include <linux/platform_data/mtd-davinci.h>
-#include <mach/serial.h>
-
-struct tnetv107x_device_info {
-        struct davinci_mmc_config       *mmc_config[2];  /* 2 controllers */
-        struct davinci_nand_pdata       *nand_config[4]; /* 4 chipsels */
-        struct matrix_keypad_platform_data *keypad_config;
-        struct ti_ssp_data              *ssp_config;
-};
-
-extern struct platform_device tnetv107x_wdt_device;
-extern struct platform_device tnetv107x_serial_device[];
-
-extern void tnetv107x_init(void);
-extern void tnetv107x_devices_init(struct tnetv107x_device_info *);
-extern void tnetv107x_irq_init(void);
-void tnetv107x_restart(enum reboot_mode mode, const char *cmd);
-
-#endif
-
-#endif /* __ASM_ARCH_DAVINCI_TNETV107X_H */
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index f49c2916aa3a..8fb97b93b6bb 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -68,9 +68,6 @@ static inline void set_uart_info(u32 phys)
 #define DEBUG_LL_DA8XX(machine, port)                           \
         _DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE)
 
-#define DEBUG_LL_TNETV107X(machine, port)                       \
-        _DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE)
-
 static inline void __arch_decomp_setup(unsigned long arch_id)
 {
         /*
@@ -94,9 +91,6 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                 DEBUG_LL_DA8XX(davinci_da850_evm,       2);
                 DEBUG_LL_DA8XX(mityomapl138,            1);
                 DEBUG_LL_DA8XX(omapl138_hawkboard,      2);
-
-                /* TNETV107x boards */
-                DEBUG_LL_TNETV107X(tnetv107x,           1);
         } while (0);
 }
 
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
deleted file mode 100644
index f4d7fbb24b3b..000000000000
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ /dev/null
@@ -1,766 +0,0 @@
-/*
- * Texas Instruments TNETV107X SoC Support
- *
- * Copyright (C) 2010 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/reboot.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/common.h>
-#include <mach/time.h>
-#include <mach/cputype.h>
-#include <mach/psc.h>
-#include <mach/cp_intc.h>
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/tnetv107x.h>
-#include <mach/gpio-davinci.h>
-
-#include "clock.h"
-#include "mux.h"
-
-/* Base addresses for on-chip devices */
-#define TNETV107X_INTC_BASE                     0x03000000
-#define TNETV107X_TIMER0_BASE                   0x08086500
-#define TNETV107X_TIMER1_BASE                   0x08086600
-#define TNETV107X_CHIP_CFG_BASE                 0x08087000
-#define TNETV107X_GPIO_BASE                     0x08088000
-#define TNETV107X_CLOCK_CONTROL_BASE            0x0808a000
-#define TNETV107X_PSC_BASE                      0x0808b000
-
-/* Reference clock frequencies */
-#define OSC_FREQ_ONCHIP         (24000 * 1000)
-#define OSC_FREQ_OFFCHIP_SYS    (25000 * 1000)
-#define OSC_FREQ_OFFCHIP_ETH    (25000 * 1000)
-#define OSC_FREQ_OFFCHIP_TDM    (19200 * 1000)
-
-#define N_PLLS  3
-
-/* Clock Control Registers */
-struct clk_ctrl_regs {
-        u32     pll_bypass;
-        u32     _reserved0;
-        u32     gem_lrst;
-        u32     _reserved1;
-        u32     pll_unlock_stat;
-        u32     sys_unlock;
-        u32     eth_unlock;
-        u32     tdm_unlock;
-};
-
-/* SSPLL Registers */
-struct sspll_regs {
-        u32     modes;
-        u32     post_div;
-        u32     pre_div;
-        u32     mult_factor;
-        u32     divider_range;
-        u32     bw_divider;
-        u32     spr_amount;
-        u32     spr_rate_div;
-        u32     diag;
-};
-
-/* Watchdog Timer Registers */
-struct wdt_regs {
-        u32     kick_lock;
-        u32     kick;
-        u32     change_lock;
-        u32     change ;
-        u32     disable_lock;
-        u32     disable;
-        u32     prescale_lock;
-        u32     prescale;
-};
-
-static struct clk_ctrl_regs __iomem *clk_ctrl_regs;
-
-static struct sspll_regs __iomem *sspll_regs[N_PLLS];
-static int sspll_regs_base[N_PLLS] = { 0x40, 0x80, 0xc0 };
-
-/* PLL bypass bit shifts in clk_ctrl_regs->pll_bypass register */
-static u32 bypass_mask[N_PLLS] = { BIT(0), BIT(2), BIT(1) };
-
-/* offchip (external) reference clock frequencies */
-static u32 pll_ext_freq[] = {
-        OSC_FREQ_OFFCHIP_SYS,
-        OSC_FREQ_OFFCHIP_TDM,
-        OSC_FREQ_OFFCHIP_ETH
-};
-
-/* PSC control registers */
-static u32 psc_regs[] = { TNETV107X_PSC_BASE };
-
-/* Host map for interrupt controller */
-static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 };
-
-static unsigned long clk_sspll_recalc(struct clk *clk);
-
-/* Level 1 - the PLLs */
-#define define_pll_clk(cname, pll, divmask, base)       \
-        static struct pll_data pll_##cname##_data = {   \
-                .num            = pll,                  \
-                .div_ratio_mask = divmask,              \
-                .phys_base      = base +                \
-                        TNETV107X_CLOCK_CONTROL_BASE,   \
-        };                                              \
-        static struct clk pll_##cname##_clk = {         \
-                .name           = "pll_" #cname "_clk", \
-                .pll_data       = &pll_##cname##_data,  \
-                .flags          = CLK_PLL,              \
-                .recalc         = clk_sspll_recalc,     \
-        }
-
-define_pll_clk(sys, 0, 0x1ff, 0x600);
-define_pll_clk(tdm, 1, 0x0ff, 0x200);
-define_pll_clk(eth, 2, 0x0ff, 0x400);
-
-/* Level 2 - divided outputs from the PLLs */
-#define define_pll_div_clk(pll, cname, div)                     \
-        static struct clk pll##_##cname##_clk = {               \
-                .name           = #pll "_" #cname "_clk",       \
-                .parent         = &pll_##pll##_clk,             \
-                .flags          = CLK_PLL,                      \
-                .div_reg        = PLLDIV##div,                  \
-                .set_rate       = davinci_set_sysclk_rate,      \
-        }
-
-define_pll_div_clk(sys, arm1176,        1);
-define_pll_div_clk(sys, dsp,            2);
-define_pll_div_clk(sys, ddr,            3);
-define_pll_div_clk(sys, full,           4);
-define_pll_div_clk(sys, lcd,            5);
-define_pll_div_clk(sys, vlynq_ref,      6);
-define_pll_div_clk(sys, tsc,            7);
-define_pll_div_clk(sys, half,           8);
-
-define_pll_div_clk(eth, 5mhz,           1);
-define_pll_div_clk(eth, 50mhz,          2);
-define_pll_div_clk(eth, 125mhz,         3);
-define_pll_div_clk(eth, 250mhz,         4);
-define_pll_div_clk(eth, 25mhz,          5);
-
-define_pll_div_clk(tdm, 0,              1);
-define_pll_div_clk(tdm, extra,          2);
-define_pll_div_clk(tdm, 1,              3);
-
-
-/* Level 3 - LPSC gated clocks */
-#define __lpsc_clk(cname, _parent, mod, flg)            \
-        static struct clk clk_##cname = {               \
-                .name           = #cname,               \
-                .parent         = &_parent,             \
-                .lpsc           = TNETV107X_LPSC_##mod,\
-                .flags          = flg,                  \
-        }
-
-#define lpsc_clk_enabled(cname, parent, mod)            \
-        __lpsc_clk(cname, parent, mod, ALWAYS_ENABLED)
-
-#define lpsc_clk(cname, parent, mod)                    \
-        __lpsc_clk(cname, parent, mod, 0)
-
-lpsc_clk_enabled(arm,           sys_arm1176_clk, ARM);
-lpsc_clk_enabled(gem,           sys_dsp_clk,    GEM);
-lpsc_clk_enabled(ddr2_phy,      sys_ddr_clk,    DDR2_PHY);
-lpsc_clk_enabled(tpcc,          sys_full_clk,   TPCC);
-lpsc_clk_enabled(tptc0,         sys_full_clk,   TPTC0);
-lpsc_clk_enabled(tptc1,         sys_full_clk,   TPTC1);
-lpsc_clk_enabled(ram,           sys_full_clk,   RAM);
-lpsc_clk_enabled(aemif,         sys_full_clk,   AEMIF);
-lpsc_clk_enabled(chipcfg,       sys_half_clk,   CHIP_CFG);
-lpsc_clk_enabled(rom,           sys_half_clk,   ROM);
-lpsc_clk_enabled(secctl,        sys_half_clk,   SECCTL);
-lpsc_clk_enabled(keymgr,        sys_half_clk,   KEYMGR);
-lpsc_clk_enabled(gpio,          sys_half_clk,   GPIO);
-lpsc_clk_enabled(debugss,       sys_half_clk,   DEBUGSS);
-lpsc_clk_enabled(system,        sys_half_clk,   SYSTEM);
-lpsc_clk_enabled(ddr2_vrst,     sys_ddr_clk,    DDR2_EMIF1_VRST);
-lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk,    DDR2_EMIF2_VCTL_RST);
-lpsc_clk_enabled(wdt_arm,       sys_half_clk,   WDT_ARM);
-lpsc_clk_enabled(timer1,        sys_half_clk,   TIMER1);
-
-lpsc_clk(mbx_lite,      sys_arm1176_clk,        MBX_LITE);
-lpsc_clk(ethss,         eth_125mhz_clk,         ETHSS);
-lpsc_clk(tsc,           sys_tsc_clk,            TSC);
-lpsc_clk(uart0,         sys_half_clk,           UART0);
-lpsc_clk(uart1,         sys_half_clk,           UART1);
-lpsc_clk(uart2,         sys_half_clk,           UART2);
-lpsc_clk(pktsec,        sys_half_clk,           PKTSEC);
-lpsc_clk(keypad,        sys_half_clk,           KEYPAD);
-lpsc_clk(mdio,          sys_half_clk,           MDIO);
-lpsc_clk(sdio0,         sys_half_clk,           SDIO0);
-lpsc_clk(sdio1,         sys_half_clk,           SDIO1);
-lpsc_clk(timer0,        sys_half_clk,           TIMER0);
-lpsc_clk(wdt_dsp,       sys_half_clk,           WDT_DSP);
-lpsc_clk(ssp,           sys_half_clk,           SSP);
-lpsc_clk(tdm0,          tdm_0_clk,              TDM0);
-lpsc_clk(tdm1,          tdm_1_clk,              TDM1);
-lpsc_clk(vlynq,         sys_vlynq_ref_clk,      VLYNQ);
-lpsc_clk(mcdma,         sys_half_clk,           MCDMA);
-lpsc_clk(usbss,         sys_half_clk,           USBSS);
-lpsc_clk(usb0,          clk_usbss,              USB0);
-lpsc_clk(usb1,          clk_usbss,              USB1);
-lpsc_clk(ethss_rgmii,   eth_250mhz_clk,         ETHSS_RGMII);
-lpsc_clk(imcop,         sys_dsp_clk,            IMCOP);
-lpsc_clk(spare,         sys_half_clk,           SPARE);
-
-/* LCD needs a full power down to clear controller state */
-__lpsc_clk(lcd, sys_lcd_clk, LCD, PSC_SWRSTDISABLE);
-
-
-/* Level 4 - leaf clocks for LPSC modules shared across drivers */
-static struct clk clk_rng = { .name = "rng", .parent = &clk_pktsec };
-static struct clk clk_pka = { .name = "pka", .parent = &clk_pktsec };
-
-static struct clk_lookup clks[] = {
-        CLK(NULL,               "pll_sys_clk",          &pll_sys_clk),
-        CLK(NULL,               "pll_eth_clk",          &pll_eth_clk),
-        CLK(NULL,               "pll_tdm_clk",          &pll_tdm_clk),
-        CLK(NULL,               "sys_arm1176_clk",      &sys_arm1176_clk),
-        CLK(NULL,               "sys_dsp_clk",          &sys_dsp_clk),
-        CLK(NULL,               "sys_ddr_clk",          &sys_ddr_clk),
-        CLK(NULL,               "sys_full_clk",         &sys_full_clk),
-        CLK(NULL,               "sys_lcd_clk",          &sys_lcd_clk),
-        CLK(NULL,               "sys_vlynq_ref_clk",    &sys_vlynq_ref_clk),
-        CLK(NULL,               "sys_tsc_clk",          &sys_tsc_clk),
-        CLK(NULL,               "sys_half_clk",         &sys_half_clk),
-        CLK(NULL,               "eth_5mhz_clk",         &eth_5mhz_clk),
-        CLK(NULL,               "eth_50mhz_clk",        &eth_50mhz_clk),
-        CLK(NULL,               "eth_125mhz_clk",       &eth_125mhz_clk),
-        CLK(NULL,               "eth_250mhz_clk",       &eth_250mhz_clk),
-        CLK(NULL,               "eth_25mhz_clk",        &eth_25mhz_clk),
-        CLK(NULL,               "tdm_0_clk",            &tdm_0_clk),
-        CLK(NULL,               "tdm_extra_clk",        &tdm_extra_clk),
-        CLK(NULL,               "tdm_1_clk",            &tdm_1_clk),
-        CLK(NULL,               "clk_arm",              &clk_arm),
-        CLK(NULL,               "clk_gem",              &clk_gem),
-        CLK(NULL,               "clk_ddr2_phy",         &clk_ddr2_phy),
-        CLK(NULL,               "clk_tpcc",             &clk_tpcc),
-        CLK(NULL,               "clk_tptc0",            &clk_tptc0),
-        CLK(NULL,               "clk_tptc1",            &clk_tptc1),
-        CLK(NULL,               "clk_ram",              &clk_ram),
-        CLK(NULL,               "clk_mbx_lite",         &clk_mbx_lite),
-        CLK("tnetv107x-fb.0",   NULL,                   &clk_lcd),
-        CLK(NULL,               "clk_ethss",            &clk_ethss),
-        CLK(NULL,               "aemif",                &clk_aemif),
-        CLK(NULL,               "clk_chipcfg",          &clk_chipcfg),
-        CLK("tnetv107x-ts.0",   NULL,                   &clk_tsc),
-        CLK(NULL,               "clk_rom",              &clk_rom),
-        CLK("serial8250.2",     NULL,                   &clk_uart2),
-        CLK(NULL,               "clk_pktsec",           &clk_pktsec),
-        CLK("tnetv107x-rng.0",  NULL,                   &clk_rng),
-        CLK("tnetv107x-pka.0",  NULL,                   &clk_pka),
-        CLK(NULL,               "clk_secctl",           &clk_secctl),
-        CLK(NULL,               "clk_keymgr",           &clk_keymgr),
-        CLK("tnetv107x-keypad.0", NULL,                 &clk_keypad),
-        CLK(NULL,               "clk_gpio",             &clk_gpio),
-        CLK(NULL,               "clk_mdio",             &clk_mdio),
-        CLK("dm6441-mmc.0",     NULL,                   &clk_sdio0),
-        CLK("serial8250.0",     NULL,                   &clk_uart0),
-        CLK("serial8250.1",     NULL,                   &clk_uart1),
-        CLK(NULL,               "timer0",               &clk_timer0),
-        CLK(NULL,               "timer1",               &clk_timer1),
-        CLK("tnetv107x_wdt.0",  NULL,                   &clk_wdt_arm),
-        CLK(NULL,               "clk_wdt_dsp",          &clk_wdt_dsp),
-        CLK("ti-ssp",           NULL,                   &clk_ssp),
-        CLK(NULL,               "clk_tdm0",             &clk_tdm0),
-        CLK(NULL,               "clk_vlynq",            &clk_vlynq),
-        CLK(NULL,               "clk_mcdma",            &clk_mcdma),
-        CLK(NULL,               "clk_usbss",            &clk_usbss),
-        CLK(NULL,               "clk_usb0",             &clk_usb0),
-        CLK(NULL,               "clk_usb1",             &clk_usb1),
-        CLK(NULL,               "clk_tdm1",             &clk_tdm1),
-        CLK(NULL,               "clk_debugss",          &clk_debugss),
-        CLK(NULL,               "clk_ethss_rgmii",      &clk_ethss_rgmii),
-        CLK(NULL,               "clk_system",           &clk_system),
-        CLK(NULL,               "clk_imcop",            &clk_imcop),
-        CLK(NULL,               "clk_spare",            &clk_spare),
-        CLK("dm6441-mmc.1",     NULL,                   &clk_sdio1),
-        CLK(NULL,               "clk_ddr2_vrst",        &clk_ddr2_vrst),
-        CLK(NULL,               "clk_ddr2_vctl_rst",    &clk_ddr2_vctl_rst),
-        CLK(NULL,               NULL,                   NULL),
-};
-
-static const struct mux_config pins[] = {
-#ifdef CONFIG_DAVINCI_MUX
-        MUX_CFG(TNETV107X, ASR_A00,             0, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO32,              0, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A01,             0, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO33,              0, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A02,             0, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO34,              0, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A03,             0, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO35,              0, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A04,             0, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO36,              0, 20, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A05,             0, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO37,              0, 25, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A06,             1, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO38,              1, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A07,             1, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO39,              1, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A08,             1, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO40,              1, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A09,             1, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO41,              1, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A10,             1, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO42,              1, 20, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A11,             1, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, BOOT_STRP_0,         1, 25, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A12,             2, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, BOOT_STRP_1,         2, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A13,             2, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO43,              2, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A14,             2, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO44,              2, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A15,             2, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO45,              2, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A16,             2, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO46,              2, 20, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A17,             2, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO47,              2, 25, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_A18,             3, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO48,              3, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO1_DATA3_0,       3, 0, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_A19,             3, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO49,              3, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO1_DATA2_0,       3, 5, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_A20,             3, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO50,              3, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO1_DATA1_0,       3, 10, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_A21,             3, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO51,              3, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO1_DATA0_0,       3, 15, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_A22,             3, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO52,              3, 20, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO1_CMD_0,         3, 20, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_A23,             3, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO53,              3, 25, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO1_CLK_0,         3, 25, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_BA_1,            4, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO54,              4, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SYS_PLL_CLK,         4, 0, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_CS0,             4, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, ASR_CS1,             4, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, ASR_CS2,             4, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDM_PLL_CLK,         4, 15, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_CS3,             4, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, ETH_PHY_CLK,         4, 20, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, ASR_D00,             4, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO55,              4, 25, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D01,             5, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO56,              5, 0, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D02,             5, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO57,              5, 5, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D03,             5, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO58,              5, 10, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D04,             5, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO59_0,            5, 15, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D05,             5, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO60_0,            5, 20, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D06,             5, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO61_0,            5, 25, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D07,             6, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO62_0,            6, 0, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D08,             6, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO63_0,            6, 5, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D09,             6, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO64_0,            6, 10, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D10,             6, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SDIO1_DATA3_1,       6, 15, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D11,             6, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SDIO1_DATA2_1,       6, 20, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D12,             6, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SDIO1_DATA1_1,       6, 25, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D13,             7, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SDIO1_DATA0_1,       7, 0, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D14,             7, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SDIO1_CMD_1,         7, 5, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_D15,             7, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SDIO1_CLK_1,         7, 10, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_OE,              7, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, BOOT_STRP_2,         7, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_RNW,             7, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO29_0,            7, 20, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_WAIT,            7, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO30_0,            7, 25, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_WE,              8, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, BOOT_STRP_3,         8, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, ASR_WE_DQM0,         8, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO31,              8, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD17_0,          8, 5, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, ASR_WE_DQM1,         8, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, ASR_BA0_0,           8, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, VLYNQ_CLK,           9, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO14,              9, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD19_0,          9, 0, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, VLYNQ_RXD0,          9, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO15,              9, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD20_0,          9, 5, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, VLYNQ_RXD1,          9, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO16,              9, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD21_0,          9, 10, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, VLYNQ_TXD0,          9, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO17,              9, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD22_0,          9, 15, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, VLYNQ_TXD1,          9, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO18,              9, 20, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD23_0,          9, 20, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, SDIO0_CLK,           10, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO19,              10, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO0_CMD,           10, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO20,              10, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO0_DATA0,         10, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO21,              10, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO0_DATA1,         10, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO22,              10, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO0_DATA2,         10, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO23,              10, 20, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SDIO0_DATA3,         10, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO24,              10, 25, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, EMU0,                11, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, EMU1,                11, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, RTCK,                12, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TRST_N,              12, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TCK,                 12, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDI,                 12, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDO,                 12, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TMS,                 12, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDM1_CLK,            13, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDM1_RX,             13, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDM1_TX,             13, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDM1_FS,             13, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_R0,           14, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_R1,           14, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_R2,           14, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_R3,           14, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_R4,           14, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_R5,           14, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_R6,           15, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO12,              15, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, KEYPAD_R7,           15, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO10,              15, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, KEYPAD_C0,           15, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_C1,           15, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_C2,           15, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_C3,           15, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_C4,           16, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_C5,           16, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, KEYPAD_C6,           16, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO13,              16, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, TEST_CLK_IN,         16, 10, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, KEYPAD_C7,           16, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO11,              16, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, SSP0_0,              17, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SCC_DCLK,            17, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD20_1,          17, 0, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, SSP0_1,              17, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SCC_CS_N,            17, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD21_1,          17, 5, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, SSP0_2,              17, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SCC_D,               17, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD22_1,          17, 10, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, SSP0_3,              17, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, SCC_RESETN,          17, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, LCD_PD23_1,          17, 15, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, SSP1_0,              18, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO25,              18, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, UART2_CTS,           18, 0, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, SSP1_1,              18, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO26,              18, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, UART2_RD,            18, 5, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, SSP1_2,              18, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO27,              18, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, UART2_RTS,           18, 10, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, SSP1_3,              18, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO28,              18, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, UART2_TD,            18, 15, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, UART0_CTS,           19, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, UART0_RD,            19, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, UART0_RTS,           19, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, UART0_TD,            19, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, UART1_RD,            19, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, UART1_TD,            19, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_AC_NCS,          20, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_HSYNC_RNW,       20, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_VSYNC_A0,        20, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_MCLK,            20, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD16_0,          20, 15, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, LCD_PCLK_E,          20, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD00,            20, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD01,            21, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD02,            21, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD03,            21, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD04,            21, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD05,            21, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD06,            21, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD07,            22, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD08,            22, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO59_1,            22, 5, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, LCD_PD09,            22, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO60_1,            22, 10, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, LCD_PD10,            22, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, ASR_BA0_1,           22, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, GPIO61_1,            22, 15, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, LCD_PD11,            22, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO62_1,            22, 20, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, LCD_PD12,            22, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO63_1,            22, 25, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, LCD_PD13,            23, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO64_1,            23, 0, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, LCD_PD14,            23, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO29_1,            23, 5, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, LCD_PD15,            23, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO30_1,            23, 10, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, EINT0,               24, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO08,              24, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, EINT1,               24, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, GPIO09,              24, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, GPIO00,              24, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD20_2,          24, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, TDM_CLK_IN_2,        24, 10, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, GPIO01,              24, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD21_2,          24, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, 24M_CLK_OUT_1,       24, 15, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, GPIO02,              24, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD22_2,          24, 20, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, GPIO03,              24, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD23_2,          24, 25, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, GPIO04,              25, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD16_1,          25, 0, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, USB0_RXERR,          25, 0, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, GPIO05,              25, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD17_1,          25, 5, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, TDM_CLK_IN_1,        25, 5, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, GPIO06,              25, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD18,            25, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, 24M_CLK_OUT_2,       25, 10, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, GPIO07,              25, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, LCD_PD19_1,          25, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, USB1_RXERR,          25, 15, 0x1f, 0x0c, false)
-        MUX_CFG(TNETV107X, ETH_PLL_CLK,         25, 15, 0x1f, 0x1c, false)
-        MUX_CFG(TNETV107X, MDIO,                26, 0, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, MDC,                 26, 5, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, AIC_MUTE_STAT_N,     26, 10, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDM0_CLK,            26, 10, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, AIC_HNS_EN_N,        26, 15, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDM0_FS,             26, 15, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, AIC_HDS_EN_STAT_N,   26, 20, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDM0_TX,             26, 20, 0x1f, 0x04, false)
-        MUX_CFG(TNETV107X, AIC_HNF_EN_STAT_N,   26, 25, 0x1f, 0x00, false)
-        MUX_CFG(TNETV107X, TDM0_RX,             26, 25, 0x1f, 0x04, false)
-#endif
-};
-
-/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
-static u8 irq_prios[TNETV107X_N_CP_INTC_IRQ] = {
-        /* fill in default priority 7 */
-        [0 ... (TNETV107X_N_CP_INTC_IRQ - 1)]   = 7,
-        /* now override as needed, e.g. [xxx] = 5 */
-};
-
-/* Contents of JTAG ID register used to identify exact cpu type */
-static struct davinci_id ids[] = {
-        {
-                .variant        = 0x0,
-                .part_no        = 0xb8a1,
-                .manufacturer   = 0x017,
-                .cpu_id         = DAVINCI_CPU_ID_TNETV107X,
-                .name           = "tnetv107x rev 1.0",
-        },
-        {
-                .variant        = 0x1,
-                .part_no        = 0xb8a1,
-                .manufacturer   = 0x017,
-                .cpu_id         = DAVINCI_CPU_ID_TNETV107X,
-                .name           = "tnetv107x rev 1.1/1.2",
-        },
-};
-
-static struct davinci_timer_instance timer_instance[2] = {
-        {
-                .base           = TNETV107X_TIMER0_BASE,
-                .bottom_irq     = IRQ_TNETV107X_TIMER_0_TINT12,
-                .top_irq        = IRQ_TNETV107X_TIMER_0_TINT34,
-        },
-        {
-                .base           = TNETV107X_TIMER1_BASE,
-                .bottom_irq     = IRQ_TNETV107X_TIMER_1_TINT12,
-                .top_irq        = IRQ_TNETV107X_TIMER_1_TINT34,
-        },
-};
-
-static struct davinci_timer_info timer_info = {
-        .timers         = timer_instance,
-        .clockevent_id  = T0_BOT,
-        .clocksource_id = T0_TOP,
-};
-
-/*
- * TNETV107X platforms do not use the static mappings from Davinci
- * IO_PHYS/IO_VIRT. This SOC's interesting MMRs are at different addresses,
- * and changing IO_PHYS would break away from existing Davinci SOCs.
- *
- * The primary impact of the current model is that IO_ADDRESS() is not to be
- * used to map registers on TNETV107X.
- *
- * 1.   The first chunk is for INTC:  This needs to be mapped in via iotable
- *      because ioremap() does not seem to be operational at the time when
- *      irqs are initialized.  Without this, consistent dma init bombs.
- *
- * 2.   The second chunk maps in register areas that need to be populated into
- *      davinci_soc_info.  Note that alignment restrictions come into play if
- *      low-level debug is enabled (see note in <mach/tnetv107x.h>).
- */
-static struct map_desc io_desc[] = {
-        {       /* INTC */
-                .virtual        = IO_VIRT,
-                .pfn            = __phys_to_pfn(TNETV107X_INTC_BASE),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE
-        },
-        {       /* Most of the rest */
-                .virtual        = TNETV107X_IO_VIRT,
-                .pfn            = __phys_to_pfn(TNETV107X_IO_BASE),
-                .length         = IO_SIZE - SZ_1M,
-                .type           = MT_DEVICE
-        },
-};
-
-static unsigned long clk_sspll_recalc(struct clk *clk)
-{
-        int             pll;
-        unsigned long   mult = 0, prediv = 1, postdiv = 1;
-        unsigned long   ref = OSC_FREQ_ONCHIP, ret;
-        u32             tmp;
-
-        if (WARN_ON(!clk->pll_data))
-                return clk->rate;
-
-        if (!clk_ctrl_regs) {
-                void __iomem *tmp;
-
-                tmp = ioremap(TNETV107X_CLOCK_CONTROL_BASE, SZ_4K);
-
-                if (WARN(!tmp, "failed ioremap for clock control regs\n"))
-                        return clk->parent ? clk->parent->rate : 0;
-
-                for (pll = 0; pll < N_PLLS; pll++)
-                        sspll_regs[pll] = tmp + sspll_regs_base[pll];
-
-                clk_ctrl_regs = tmp;
-        }
-
-        pll = clk->pll_data->num;
-
-        tmp = __raw_readl(&clk_ctrl_regs->pll_bypass);
-        if (!(tmp & bypass_mask[pll])) {
-                mult    = __raw_readl(&sspll_regs[pll]->mult_factor);
-                prediv  = __raw_readl(&sspll_regs[pll]->pre_div) + 1;
-                postdiv = __raw_readl(&sspll_regs[pll]->post_div) + 1;
-        }
-
-        tmp = __raw_readl(clk->pll_data->base + PLLCTL);
-        if (tmp & PLLCTL_CLKMODE)
-                ref = pll_ext_freq[pll];
-
-        clk->pll_data->input_rate = ref;
-
-        tmp = __raw_readl(clk->pll_data->base + PLLCTL);
-        if (!(tmp & PLLCTL_PLLEN))
-                return ref;
-
-        ret = ref;
-        if (mult)
-                ret += ((unsigned long long)ref * mult) / 256;
-
-        ret /= (prediv * postdiv);
-
-        return ret;
-}
-
-static void tnetv107x_watchdog_reset(struct platform_device *pdev)
-{
-        struct wdt_regs __iomem *regs;
-
-        regs = ioremap(pdev->resource[0].start, SZ_4K);
-
-        /* disable watchdog */
-        __raw_writel(0x7777, &regs->disable_lock);
-        __raw_writel(0xcccc, &regs->disable_lock);
-        __raw_writel(0xdddd, &regs->disable_lock);
-        __raw_writel(0, &regs->disable);
-
-        /* program prescale */
-        __raw_writel(0x5a5a, &regs->prescale_lock);
-        __raw_writel(0xa5a5, &regs->prescale_lock);
-        __raw_writel(0, &regs->prescale);
-
-        /* program countdown */
-        __raw_writel(0x6666, &regs->change_lock);
-        __raw_writel(0xbbbb, &regs->change_lock);
-        __raw_writel(1, &regs->change);
-
-        /* enable watchdog */
-        __raw_writel(0x7777, &regs->disable_lock);
-        __raw_writel(0xcccc, &regs->disable_lock);
-        __raw_writel(0xdddd, &regs->disable_lock);
-        __raw_writel(1, &regs->disable);
-
-        /* kick */
-        __raw_writel(0x5555, &regs->kick_lock);
-        __raw_writel(0xaaaa, &regs->kick_lock);
-        __raw_writel(1, &regs->kick);
-}
-
-void tnetv107x_restart(enum reboot_mode mode, const char *cmd)
-{
-        tnetv107x_watchdog_reset(&tnetv107x_wdt_device);
-}
-
-static struct davinci_soc_info tnetv107x_soc_info = {
-        .io_desc                = io_desc,
-        .io_desc_num            = ARRAY_SIZE(io_desc),
-        .ids                    = ids,
-        .ids_num                = ARRAY_SIZE(ids),
-        .jtag_id_reg            = TNETV107X_CHIP_CFG_BASE + 0x018,
-        .cpu_clks               = clks,
-        .psc_bases              = psc_regs,
-        .psc_bases_num          = ARRAY_SIZE(psc_regs),
-        .pinmux_base            = TNETV107X_CHIP_CFG_BASE + 0x150,
-        .pinmux_pins            = pins,
-        .pinmux_pins_num        = ARRAY_SIZE(pins),
-        .intc_type              = DAVINCI_INTC_TYPE_CP_INTC,
-        .intc_base              = TNETV107X_INTC_BASE,
-        .intc_irq_prios         = irq_prios,
-        .intc_irq_num           = TNETV107X_N_CP_INTC_IRQ,
-        .intc_host_map          = intc_host_map,
-        .gpio_base              = TNETV107X_GPIO_BASE,
-        .gpio_type              = GPIO_TYPE_TNETV107X,
-        .gpio_num               = TNETV107X_N_GPIO,
-        .timer_info             = &timer_info,
-        .serial_dev             = tnetv107x_serial_device,
-};
-
-void __init tnetv107x_init(void)
-{
-        davinci_common_init(&tnetv107x_soc_info);
-}
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index 0bc7cdf8cf46..d8c439c89ea9 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -20,18 +20,6 @@ config MACH_CM_A510
           Say 'Y' here if you want your kernel to support the
           CompuLab CM-A510 Board.
 
-config MACH_DOVE_DT
-        bool "Marvell Dove Flattened Device Tree"
-        select DOVE_CLK
-        select ORION_IRQCHIP
-        select ORION_TIMER
-        select REGULATOR
-        select REGULATOR_FIXED_VOLTAGE
-        select USE_OF
-        help
-          Say 'Y' here if you want your kernel to support the
-          Marvell Dove using flattened device tree.
-
 endmenu
 
 endif
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index cbc5c0618788..b608a21919fb 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -2,5 +2,4 @@ obj-y				+= common.o
 obj-$(CONFIG_DOVE_LEGACY)       += irq.o mpp.o
 obj-$(CONFIG_PCI)               += pcie.o
 obj-$(CONFIG_MACH_DOVE_DB)      += dove-db-setup.o
-obj-$(CONFIG_MACH_DOVE_DT)      += board-dt.o
 obj-$(CONFIG_MACH_CM_A510)      += cm-a510.o
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index 0aded64a9ebc..830b76e70250 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -5,7 +5,6 @@ config ARCH_HIGHBANK
         select ARCH_HAS_HOLES_MEMORYMODEL
         select ARCH_HAS_OPP
         select ARCH_SUPPORTS_BIG_ENDIAN
-        select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_AMBA
         select ARM_ERRATA_764369 if SMP
         select ARM_ERRATA_775420
@@ -14,14 +13,8 @@ config ARCH_HIGHBANK
         select ARM_PSCI
         select ARM_TIMER_SP804
         select CACHE_L2X0
-        select COMMON_CLK
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
         select HAVE_ARM_SCU
         select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
         select MAILBOX
         select PL320_MBOX
-        select SPARSE_IRQ
-        select USE_OF
         select ZONE_DMA if ARM_LPAE
diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig
index 8f4649b301b2..9d0a87b025e3 100644
--- a/arch/arm/mach-hisi/Kconfig
+++ b/arch/arm/mach-hisi/Kconfig
@@ -3,13 +3,9 @@ config ARCH_HI3xxx
         select ARM_AMBA
         select ARM_GIC
         select ARM_TIMER_SP804
-        select ARCH_WANT_OPTIONAL_GPIOLIB
         select CACHE_L2X0
-        select CLKSRC_OF
-        select GENERIC_CLOCKEVENTS
         select HAVE_ARM_SCU
-        select HAVE_ARM_TWD
-        select HAVE_SMP
+        select HAVE_ARM_TWD if SMP
         select PINCTRL
         select PINCTRL_SINGLE
         help
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 33567aa5880f..5740296dc429 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,19 +1,15 @@
 config ARCH_MXC
         bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7
+        select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_OPP
         select ARCH_REQUIRE_GPIOLIB
         select ARM_CPU_SUSPEND if PM
-        select ARM_PATCH_PHYS_VIRT
         select CLKSRC_MMIO
-        select COMMON_CLK
-        select GENERIC_ALLOCATOR
-        select GENERIC_CLOCKEVENTS
         select GENERIC_IRQ_CHIP
-        select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7
-        select MULTI_IRQ_HANDLER
         select PINCTRL
+        select PM_OPP if PM
         select SOC_BUS
-        select SPARSE_IRQ
-        select USE_OF
+        select SRAM
         help
           Support for Freescale MXC/iMX-based family of processors
 
@@ -121,18 +117,16 @@ config SOC_IMX31
 config SOC_IMX35
         bool
         select ARCH_MXC_IOMUX_V3
-        select CPU_V6K
         select HAVE_EPIT
         select MXC_AVIC
+        select PINCTRL_IMX35
         select SMP_ON_UP if SMP
-        select PINCTRL
 
 config SOC_IMX5
         bool
         select ARCH_HAS_CPUFREQ
         select ARCH_HAS_OPP
         select ARCH_MXC_IOMUX_V3
-        select CPU_V7
         select MXC_TZIC
 
 config  SOC_IMX51
@@ -777,65 +771,50 @@ config	SOC_IMX50
 config  SOC_IMX53
         bool "i.MX53 support"
         select HAVE_IMX_SRC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
         select PINCTRL_IMX53
         select SOC_IMX5
 
         help
           This enables support for Freescale i.MX53 processor.
 
-config SOC_IMX6Q
-        bool "i.MX6 Quad/DualLite support"
-        select ARCH_HAS_CPUFREQ
-        select ARCH_HAS_OPP
+config SOC_IMX6
+        bool
         select ARM_ERRATA_754322
-        select ARM_ERRATA_764369 if SMP
         select ARM_ERRATA_775420
         select ARM_GIC
-        select CPU_V7
-        select HAVE_ARM_SCU if SMP
-        select HAVE_ARM_TWD if SMP
         select HAVE_IMX_ANATOP
         select HAVE_IMX_GPC
         select HAVE_IMX_MMDC
         select HAVE_IMX_SRC
-        select HAVE_SMP
         select MFD_SYSCON
-        select MIGHT_HAVE_PCI
-        select PCI_DOMAINS if PCI
-        select PINCTRL_IMX6Q
         select PL310_ERRATA_588369 if CACHE_PL310
         select PL310_ERRATA_727915 if CACHE_PL310
         select PL310_ERRATA_769419 if CACHE_PL310
-        select PM_OPP if PM
+
+config SOC_IMX6Q
+        bool "i.MX6 Quad/DualLite support"
+        select ARM_ERRATA_764369 if SMP
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if SMP
+        select MIGHT_HAVE_PCI
+        select PCI_DOMAINS if PCI
+        select PINCTRL_IMX6Q
+        select SOC_IMX6
 
         help
           This enables support for Freescale i.MX6 Quad processor.
 
 config SOC_IMX6SL
         bool "i.MX6 SoloLite support"
-        select ARM_ERRATA_754322
-        select ARM_ERRATA_775420
-        select ARM_GIC
-        select CPU_V7
-        select HAVE_IMX_ANATOP
-        select HAVE_IMX_GPC
-        select HAVE_IMX_MMDC
-        select HAVE_IMX_SRC
-        select MFD_SYSCON
         select PINCTRL_IMX6SL
-        select PL310_ERRATA_588369 if CACHE_PL310
-        select PL310_ERRATA_727915 if CACHE_PL310
-        select PL310_ERRATA_769419 if CACHE_PL310
+        select SOC_IMX6
 
         help
           This enables support for Freescale i.MX6 SoloLite processor.
 
 config SOC_VF610
         bool "Vybrid Family VF610 support"
-        select CPU_V7
         select ARM_GIC
-        select CLKSRC_OF
         select PINCTRL_VF610
         select VF_PIT_TIMER
         select PL310_ERRATA_588369 if CACHE_PL310
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index befcaf5d0574..f4ed83032dd0 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
 obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
+obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o
 endif
 
 ifdef CONFIG_SND_IMX_SOC
@@ -101,11 +102,11 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
 obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
 
-ifeq ($(CONFIG_PM),y)
-obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
-# i.MX6SL reuses i.MX6Q code
-obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o
+ifeq ($(CONFIG_SUSPEND),y)
+AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
+obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
 endif
+obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
 
 # i.MX5 based machines
 obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index d7ed66091a2a..bdc2e4630a08 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -149,7 +149,6 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
         clk_register_clkdev(clk[per1], "per", "imx-gpt.1");
         clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
         clk_register_clkdev(clk[per1], "per", "imx-gpt.2");
-        clk_register_clkdev(clk[pwm_ipg_gate], "pwm", "mxc_pwm.0");
         clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");
         clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");
         clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 69858c78f40d..dc36e6c2f1da 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -265,14 +265,6 @@ int __init mx25_clocks_init(void)
         clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
         clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1");
         clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2");
-        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.0");
-        clk_register_clkdev(clk[per10], "per", "mxc_pwm.0");
-        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.1");
-        clk_register_clkdev(clk[per10], "per", "mxc_pwm.1");
-        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.2");
-        clk_register_clkdev(clk[per10], "per", "mxc_pwm.2");
-        clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.3");
-        clk_register_clkdev(clk[per10], "per", "mxc_pwm.3");
         clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad");
         clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc");
         clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.0");
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index c6b40f386786..d2da8908b268 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -231,7 +231,6 @@ int __init mx27_clocks_init(unsigned long fref)
         clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.4");
         clk_register_clkdev(clk[gpt6_ipg_gate], "ipg", "imx-gpt.5");
         clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.5");
-        clk_register_clkdev(clk[pwm_ipg_gate], NULL, "mxc_pwm.0");
         clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0");
         clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0");
         clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1");
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 19fca1fdc6fe..568ef0a4de84 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -266,8 +266,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1");
         clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1");
         clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2");
-        clk_register_clkdev(clk[IMX5_CLK_PWM1_IPG_GATE], "pwm", "mxc_pwm.0");
-        clk_register_clkdev(clk[IMX5_CLK_PWM2_IPG_GATE], "pwm", "mxc_pwm.1");
         clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0");
         clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1");
         clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0");
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index af2e582d2b74..b0e7f9d2c245 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -437,12 +437,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 
         clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
         clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
-        clk_register_clkdev(clk[ahb], "ahb", NULL);
-        clk_register_clkdev(clk[cko1], "cko1", NULL);
-        clk_register_clkdev(clk[arm], NULL, "cpu0");
-        clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
-        clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
+        clk_register_clkdev(clk[enet_ref], "enet_ref", NULL);
 
         if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
             cpu_is_imx6dl()) {
@@ -482,6 +477,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         if (IS_ENABLED(CONFIG_PCI_IMX6))
                 clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
 
+        /* Set initial power mode */
+        imx6q_set_lpm(WAIT_CLOCKED);
+
         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
         base = of_iomap(np, 0);
         WARN_ON(!base);
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index 3781a1853998..f7073c0782fb 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -18,27 +18,43 @@
 #include "clk.h"
 #include "common.h"
 
-static const char const *step_sels[]            = { "osc", "pll2_pfd2", };
-static const char const *pll1_sw_sels[]         = { "pll1_sys", "step", };
-static const char const *ocram_alt_sels[]       = { "pll2_pfd2", "pll3_pfd1", };
-static const char const *ocram_sels[]           = { "periph", "ocram_alt_sels", };
-static const char const *pre_periph_sels[]      = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
-static const char const *periph_clk2_sels[]     = { "pll3_usb_otg", "osc", "osc", "dummy", };
-static const char const *periph2_clk2_sels[]    = { "pll3_usb_otg", "pll2_bus", };
-static const char const *periph_sels[]          = { "pre_periph_sel", "periph_clk2_podf", };
-static const char const *periph2_sels[]         = { "pre_periph2_sel", "periph2_clk2_podf", };
-static const char const *csi_lcdif_sels[]       = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
-static const char const *usdhc_sels[]           = { "pll2_pfd2", "pll2_pfd0", };
-static const char const *ssi_sels[]             = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
-static const char const *perclk_sels[]          = { "ipg", "osc", };
-static const char const *epdc_pxp_sels[]        = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
-static const char const *gpu2d_ovg_sels[]       = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
-static const char const *gpu2d_sels[]           = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
-static const char const *lcdif_pix_sels[]       = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
-static const char const *epdc_pix_sels[]        = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
-static const char const *audio_sels[]           = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
-static const char const *ecspi_sels[]           = { "pll3_60m", "osc", };
-static const char const *uart_sels[]            = { "pll3_80m", "osc", };
+#define CCSR                    0xc
+#define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
+#define CACRR                   0x10
+#define CDHIPR                  0x48
+#define BM_CDHIPR_ARM_PODF_BUSY (1 << 16)
+#define ARM_WAIT_DIV_396M       2
+#define ARM_WAIT_DIV_792M       4
+#define ARM_WAIT_DIV_996M       6
+
+#define PLL_ARM                 0x0
+#define BM_PLL_ARM_DIV_SELECT   (0x7f << 0)
+#define BM_PLL_ARM_POWERDOWN    (1 << 12)
+#define BM_PLL_ARM_ENABLE       (1 << 13)
+#define BM_PLL_ARM_LOCK         (1 << 31)
+#define PLL_ARM_DIV_792M        66
+
+static const char *step_sels[]          = { "osc", "pll2_pfd2", };
+static const char *pll1_sw_sels[]       = { "pll1_sys", "step", };
+static const char *ocram_alt_sels[]     = { "pll2_pfd2", "pll3_pfd1", };
+static const char *ocram_sels[]         = { "periph", "ocram_alt_sels", };
+static const char *pre_periph_sels[]    = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
+static const char *periph_clk2_sels[]   = { "pll3_usb_otg", "osc", "osc", "dummy", };
+static const char *periph2_clk2_sels[]  = { "pll3_usb_otg", "pll2_bus", };
+static const char *periph_sels[]        = { "pre_periph_sel", "periph_clk2_podf", };
+static const char *periph2_sels[]       = { "pre_periph2_sel", "periph2_clk2_podf", };
+static const char *csi_lcdif_sels[]     = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
+static const char *usdhc_sels[]         = { "pll2_pfd2", "pll2_pfd0", };
+static const char *ssi_sels[]           = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
+static const char *perclk_sels[]        = { "ipg", "osc", };
+static const char *epdc_pxp_sels[]      = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
+static const char *gpu2d_ovg_sels[]     = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
+static const char *gpu2d_sels[]         = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
+static const char *lcdif_pix_sels[]     = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
+static const char *epdc_pix_sels[]      = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
+static const char *audio_sels[]         = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
+static const char *ecspi_sels[]         = { "pll3_60m", "osc", };
+static const char *uart_sels[]          = { "pll3_80m", "osc", };
 
 static struct clk_div_table clk_enet_ref_table[] = {
         { .val = 0, .div = 20, },
@@ -65,6 +81,89 @@ static struct clk_div_table video_div_table[] = {
 
 static struct clk *clks[IMX6SL_CLK_END];
 static struct clk_onecell_data clk_data;
+static void __iomem *ccm_base;
+static void __iomem *anatop_base;
+
+static const u32 clks_init_on[] __initconst = {
+        IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT,
+};
+
+/*
+ * ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken
+ *           during WAIT mode entry process could cause cache memory
+ *           corruption.
+ *
+ * Software workaround:
+ *     To prevent this issue from occurring, software should ensure that the
+ * ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before
+ * entering WAIT mode.
+ *
+ * This function will set the ARM clk to max value within the 12:5 limit.
+ * As IPG clock is fixed at 66MHz(so ARM freq must not exceed 158.4MHz),
+ * ARM freq are one of below setpoints: 396MHz, 792MHz and 996MHz, since
+ * the clk APIs can NOT be called in idle thread(may cause kernel schedule
+ * as there is sleep function in PLL wait function), so here we just slow
+ * down ARM to below freq according to previous freq:
+ *
+ * run mode      wait mode
+ * 396MHz   ->   132MHz;
+ * 792MHz   ->   158.4MHz;
+ * 996MHz   ->   142.3MHz;
+ */
+static int imx6sl_get_arm_divider_for_wait(void)
+{
+        if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) {
+                return ARM_WAIT_DIV_396M;
+        } else {
+                if ((readl_relaxed(anatop_base + PLL_ARM) &
+                        BM_PLL_ARM_DIV_SELECT) == PLL_ARM_DIV_792M)
+                        return ARM_WAIT_DIV_792M;
+                else
+                        return ARM_WAIT_DIV_996M;
+        }
+}
+
+static void imx6sl_enable_pll_arm(bool enable)
+{
+        static u32 saved_pll_arm;
+        u32 val;
+
+        if (enable) {
+                saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM);
+                val |= BM_PLL_ARM_ENABLE;
+                val &= ~BM_PLL_ARM_POWERDOWN;
+                writel_relaxed(val, anatop_base + PLL_ARM);
+                while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK))
+                        ;
+        } else {
+                 writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM);
+        }
+}
+
+void imx6sl_set_wait_clk(bool enter)
+{
+        static unsigned long saved_arm_div;
+        int arm_div_for_wait = imx6sl_get_arm_divider_for_wait();
+
+        /*
+         * According to hardware design, arm podf change need
+         * PLL1 clock enabled.
+         */
+        if (arm_div_for_wait == ARM_WAIT_DIV_396M)
+                imx6sl_enable_pll_arm(true);
+
+        if (enter) {
+                saved_arm_div = readl_relaxed(ccm_base + CACRR);
+                writel_relaxed(arm_div_for_wait, ccm_base + CACRR);
+        } else {
+                writel_relaxed(saved_arm_div, ccm_base + CACRR);
+        }
+        while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY)
+                ;
+
+        if (arm_div_for_wait == ARM_WAIT_DIV_396M)
+                imx6sl_enable_pll_arm(false);
+}
 
 static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 {
@@ -72,6 +171,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
         void __iomem *base;
         int irq;
         int i;
+        int ret;
 
         clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
         clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
@@ -80,6 +180,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
         np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
         base = of_iomap(np, 0);
         WARN_ON(!base);
+        anatop_base = base;
 
         /*                                             type               name            parent  base         div_mask */
         clks[IMX6SL_CLK_PLL1_SYS]      = imx_clk_pllv3(IMX_PLLV3_SYS,     "pll1_sys",      "osc", base,        0x7f);
@@ -127,6 +228,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
         np = ccm_node;
         base = of_iomap(np, 0);
         WARN_ON(!base);
+        ccm_base = base;
 
         /* Reuse imx6q pm code */
         imx6q_pm_set_ccm_base(base);
@@ -258,6 +360,19 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
         clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");
         clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
 
+        /* Ensure the AHB clk is at 132MHz. */
+        ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
+        if (ret)
+                pr_warn("%s: failed to set AHB clock rate %d!\n",
+                        __func__, ret);
+
+        /*
+         * Make sure those always on clocks are enabled to maintain the correct
+         * usecount and enabling/disabling of parent PLLs.
+         */
+        for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
+                clk_prepare_enable(clks[clks_init_on[i]]);
+
         if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
                 clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
                 clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
@@ -266,6 +381,9 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
         /* Audio-related clocks configuration */
         clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
 
+        /* Set initial power mode */
+        imx6q_set_lpm(WAIT_CLOCKED);
+
         np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
         base = of_iomap(np, 0);
         WARN_ON(!base);
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index ecd66d8e20b6..22dc3ee21fd4 100644
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -63,25 +63,25 @@ static void __iomem *anatop_base;
 static void __iomem *ccm_base;
 
 /* sources for multiplexer clocks, this is used multiple times */
-static const char const *fast_sels[]    = { "firc", "fxosc", };
-static const char const *slow_sels[]    = { "sirc_32k", "sxosc", };
-static const char const *pll1_sels[]    = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
-static const char const *pll2_sels[]    = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
-static const char const *sys_sels[]     = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", };
-static const char const *ddr_sels[]     = { "pll2_pfd2", "sys_sel", };
-static const char const *rmii_sels[]    = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
-static const char const *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
-static const char const *esai_sels[]    = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
-static const char const *sai_sels[]     = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
-static const char const *nfc_sels[]     = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
-static const char const *qspi_sels[]    = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
-static const char const *esdhc_sels[]   = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
-static const char const *dcu_sels[]     = { "pll1_pfd2", "pll3_main", };
-static const char const *gpu_sels[]     = { "pll2_pfd2", "pll3_pfd2", };
-static const char const *vadc_sels[]    = { "pll6_main_div", "pll3_main_div", "pll3_main", };
+static const char *fast_sels[]  = { "firc", "fxosc", };
+static const char *slow_sels[]  = { "sirc_32k", "sxosc", };
+static const char *pll1_sels[]  = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
+static const char *pll2_sels[]  = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
+static const char *sys_sels[]   = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", };
+static const char *ddr_sels[]   = { "pll2_pfd2", "sys_sel", };
+static const char *rmii_sels[]  = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
+static const char *enet_ts_sels[]       = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
+static const char *esai_sels[]  = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
+static const char *sai_sels[]   = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
+static const char *nfc_sels[]   = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
+static const char *qspi_sels[]  = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
+static const char *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
+static const char *dcu_sels[]   = { "pll1_pfd2", "pll3_main", };
+static const char *gpu_sels[]   = { "pll2_pfd2", "pll3_pfd2", };
+static const char *vadc_sels[]  = { "pll6_main_div", "pll3_main_div", "pll3_main", };
 /* FTM counter clock source, not module clock */
-static const char const *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
-static const char const *ftm_fix_sels[] = { "sxosc", "ipg_bus", };
+static const char *ftm_ext_sels[]       = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
+static const char *ftm_fix_sels[]       = { "sxosc", "ipg_bus", };
 
 static struct clk_div_table pll4_main_div_table[] = {
         { .val = 0, .div = 1 },
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 59c3b9b26bb4..b5241ea76706 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -116,7 +116,6 @@ void imx_enable_cpu(int cpu, bool enable);
 void imx_set_cpu_jump(int cpu, void *jump_addr);
 u32 imx_get_cpu_arg(int cpu);
 void imx_set_cpu_arg(int cpu, u32 arg);
-void v7_cpu_resume(void);
 #ifdef CONFIG_SMP
 void v7_secondary_startup(void);
 void imx_scu_map_io(void);
@@ -139,18 +138,28 @@ void imx_anatop_init(void);
 void imx_anatop_pre_suspend(void);
 void imx_anatop_post_resume(void);
 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
-void imx6q_set_chicken_bit(void);
+void imx6q_set_int_mem_clk_lpm(void);
+void imx6sl_set_wait_clk(bool enter);
 
 void imx_cpu_die(unsigned int cpu);
 int imx_cpu_kill(unsigned int cpu);
 
-#ifdef CONFIG_PM
+#ifdef CONFIG_SUSPEND
+void v7_cpu_resume(void);
+void imx6_suspend(void __iomem *ocram_vbase);
+#else
+static inline void v7_cpu_resume(void) {}
+static inline void imx6_suspend(void __iomem *ocram_vbase) {}
+#endif
+
 void imx6q_pm_init(void);
+void imx6dl_pm_init(void);
+void imx6sl_pm_init(void);
 void imx6q_pm_set_ccm_base(void __iomem *base);
+
+#ifdef CONFIG_PM
 void imx5_pm_init(void);
 #else
-static inline void imx6q_pm_init(void) {}
-static inline void imx6q_pm_set_ccm_base(void __iomem *base) {}
 static inline void imx5_pm_init(void) {}
 #endif
 
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
index 23ddfb693b2d..6bcae0479049 100644
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -68,8 +68,8 @@ int __init imx6q_cpuidle_init(void)
         /* Need to enable SCU standby for entering WAIT modes */
         imx_scu_standby_enable();
 
-        /* Set chicken bit to get a reliable WAIT mode support */
-        imx6q_set_chicken_bit();
+        /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
+        imx6q_set_int_mem_clk_lpm();
 
         return cpuidle_register(&imx6q_cpuidle_driver, NULL);
 }
diff --git a/arch/arm/mach-imx/cpuidle-imx6sl.c b/arch/arm/mach-imx/cpuidle-imx6sl.c
new file mode 100644
index 000000000000..d4b6b8171fa9
--- /dev/null
+++ b/arch/arm/mach-imx/cpuidle-imx6sl.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/cpuidle.h>
+#include <linux/module.h>
+#include <asm/cpuidle.h>
+#include <asm/proc-fns.h>
+
+#include "common.h"
+#include "cpuidle.h"
+
+static int imx6sl_enter_wait(struct cpuidle_device *dev,
+                            struct cpuidle_driver *drv, int index)
+{
+        imx6q_set_lpm(WAIT_UNCLOCKED);
+        /*
+         * Software workaround for ERR005311, see function
+         * description for details.
+         */
+        imx6sl_set_wait_clk(true);
+        cpu_do_idle();
+        imx6sl_set_wait_clk(false);
+        imx6q_set_lpm(WAIT_CLOCKED);
+
+        return index;
+}
+
+static struct cpuidle_driver imx6sl_cpuidle_driver = {
+        .name = "imx6sl_cpuidle",
+        .owner = THIS_MODULE,
+        .states = {
+                /* WFI */
+                ARM_CPUIDLE_WFI_STATE,
+                /* WAIT */
+                {
+                        .exit_latency = 50,
+                        .target_residency = 75,
+                        .flags = CPUIDLE_FLAG_TIME_VALID |
+                                CPUIDLE_FLAG_TIMER_STOP,
+                        .enter = imx6sl_enter_wait,
+                        .name = "WAIT",
+                        .desc = "Clock off",
+                },
+        },
+        .state_count = 2,
+        .safe_state_index = 0,
+};
+
+int __init imx6sl_cpuidle_init(void)
+{
+        return cpuidle_register(&imx6sl_cpuidle_driver, NULL);
+}
diff --git a/arch/arm/mach-imx/cpuidle.h b/arch/arm/mach-imx/cpuidle.h
index 786f98ecc145..24e33670417c 100644
--- a/arch/arm/mach-imx/cpuidle.h
+++ b/arch/arm/mach-imx/cpuidle.h
@@ -13,6 +13,7 @@
 #ifdef CONFIG_CPU_IDLE
 extern int imx5_cpuidle_init(void);
 extern int imx6q_cpuidle_init(void);
+extern int imx6sl_cpuidle_init(void);
 #else
 static inline int imx5_cpuidle_init(void)
 {
@@ -22,4 +23,8 @@ static inline int imx6q_cpuidle_init(void)
 {
         return 0;
 }
+static inline int imx6sl_cpuidle_init(void)
+{
+        return 0;
+}
 #endif
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
index 769563fdeaa0..61a114cddc39 100644
--- a/arch/arm/mach-imx/devices-imx25.h
+++ b/arch/arm/mach-imx/devices-imx25.h
@@ -83,7 +83,3 @@ extern const struct imx_spi_imx_data imx25_cspi_data[];
 #define imx25_add_spi_imx0(pdata)       imx25_add_spi_imx(0, pdata)
 #define imx25_add_spi_imx1(pdata)       imx25_add_spi_imx(1, pdata)
 #define imx25_add_spi_imx2(pdata)       imx25_add_spi_imx(2, pdata)
-
-extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[];
-#define imx25_add_mxc_pwm(id)   \
-        imx_add_mxc_pwm(&imx25_mxc_pwm_data[id])
diff --git a/arch/arm/mach-imx/devices-imx51.h b/arch/arm/mach-imx/devices-imx51.h
index deee5baee88c..26389f35a2b2 100644
--- a/arch/arm/mach-imx/devices-imx51.h
+++ b/arch/arm/mach-imx/devices-imx51.h
@@ -57,10 +57,6 @@ extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
 #define imx51_add_imx2_wdt(id)  \
         imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
 
-extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[];
-#define imx51_add_mxc_pwm(id)   \
-        imx_add_mxc_pwm(&imx51_mxc_pwm_data[id])
-
 extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
 #define imx51_add_imx_keypad(pdata)     \
         imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index 68c74fb0373c..2d260a5a307c 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -67,9 +67,6 @@ config IMX_HAVE_PLATFORM_MXC_MMC
 config IMX_HAVE_PLATFORM_MXC_NAND
         bool
 
-config IMX_HAVE_PLATFORM_MXC_PWM
-        bool
-
 config IMX_HAVE_PLATFORM_MXC_RNGA
         bool
         select ARCH_HAS_RNGA
diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile
index 67416fb1dc69..1cbc14cd80d1 100644
--- a/arch/arm/mach-imx/devices/Makefile
+++ b/arch/arm/mach-imx/devices/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
index c13b76b9f6b3..61352a80bb59 100644
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -290,15 +290,6 @@ struct imx_pata_imx_data {
 struct platform_device *__init imx_add_pata_imx(
                 const struct imx_pata_imx_data *data);
 
-struct imx_mxc_pwm_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_mxc_pwm(
-                const struct imx_mxc_pwm_data *data);
-
 /* mxc_rtc */
 struct imx_mxc_rtc_data {
         const char *devid;
diff --git a/arch/arm/mach-imx/devices/platform-mxc_pwm.c b/arch/arm/mach-imx/devices/platform-mxc_pwm.c
deleted file mode 100644
index dcd289777687..000000000000
--- a/arch/arm/mach-imx/devices/platform-mxc_pwm.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size)           \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _PWM ## _hwid ## _BASE_ADDR,           \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_PWM ## _hwid,                        \
-        }
-#define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size)                  \
-        [_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size)
-
-#ifdef CONFIG_SOC_IMX21
-const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst =
-        imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX21 */
-
-#ifdef CONFIG_SOC_IMX25
-const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = {
-#define imx25_mxc_pwm_data_entry(_id, _hwid)                            \
-        imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K)
-        imx25_mxc_pwm_data_entry(0, 1),
-        imx25_mxc_pwm_data_entry(1, 2),
-        imx25_mxc_pwm_data_entry(2, 3),
-        imx25_mxc_pwm_data_entry(3, 4),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
-#ifdef CONFIG_SOC_IMX27
-const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst =
-        imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K);
-#endif /* ifdef CONFIG_SOC_IMX27 */
-
-#ifdef CONFIG_SOC_IMX51
-const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst = {
-#define imx51_mxc_pwm_data_entry(_id, _hwid)                            \
-        imx_mxc_pwm_data_entry(MX51, _id, _hwid, SZ_16K)
-        imx51_mxc_pwm_data_entry(0, 1),
-        imx51_mxc_pwm_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX51 */
-
-struct platform_device *__init imx_add_mxc_pwm(
-                const struct imx_mxc_pwm_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return imx_add_platform_device("mxc_pwm", data->id,
-                        res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index a3b0b04b45c9..abf43bb47eca 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2007, 2014 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  *
  * This program is free software; you can redistribute it and/or
@@ -20,7 +20,9 @@
 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
 #define __ASM_ARCH_MXC_HARDWARE_H__
 
+#ifndef __ASSEMBLY__
 #include <asm/io.h>
+#endif
 #include <asm/sizes.h>
 
 #define addr_in_module(addr, mod) \
diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index 627f16f0e9d1..de5047c8a6c8 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -12,12 +12,7 @@
 
 #include <linux/linkage.h>
 #include <linux/init.h>
-#include <asm/asm-offsets.h>
-#include <asm/hardware/cache-l2x0.h>
 
-        .section ".text.head", "ax"
-
-#ifdef CONFIG_SMP
 diag_reg_offset:
         .word   g_diag_reg - .
 
@@ -34,38 +29,3 @@ ENTRY(v7_secondary_startup)
         set_diag_reg
         b       secondary_startup
 ENDPROC(v7_secondary_startup)
-#endif
-
-#ifdef CONFIG_ARM_CPU_SUSPEND
-/*
- * The following code must assume it is running from physical address
- * where absolute virtual addresses to the data section have to be
- * turned into relative ones.
- */
-
-#ifdef CONFIG_CACHE_L2X0
-        .macro  pl310_resume
-        adr     r0, l2x0_saved_regs_offset
-        ldr     r2, [r0]
-        add     r2, r2, r0
-        ldr     r0, [r2, #L2X0_R_PHY_BASE]      @ get physical base of l2x0
-        ldr     r1, [r2, #L2X0_R_AUX_CTRL]      @ get aux_ctrl value
-        str     r1, [r0, #L2X0_AUX_CTRL]        @ restore aux_ctrl
-        mov     r1, #0x1
-        str     r1, [r0, #L2X0_CTRL]            @ re-enable L2
-        .endm
-
-l2x0_saved_regs_offset:
-        .word   l2x0_saved_regs - .
-
-#else
-        .macro  pl310_resume
-        .endm
-#endif
-
-ENTRY(v7_cpu_resume)
-        bl      v7_invalidate_l1
-        pl310_resume
-        b       cpu_resume
-ENDPROC(v7_cpu_resume)
-#endif
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 76e5db4fce35..e60456d85c9d 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -182,16 +182,83 @@ static void __init imx6q_enet_phy_init(void)
 
 static void __init imx6q_1588_init(void)
 {
+        struct device_node *np;
+        struct clk *ptp_clk;
+        struct clk *enet_ref;
         struct regmap *gpr;
+        u32 clksel;
 
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec");
+        if (!np) {
+                pr_warn("%s: failed to find fec node\n", __func__);
+                return;
+        }
+
+        ptp_clk = of_clk_get(np, 2);
+        if (IS_ERR(ptp_clk)) {
+                pr_warn("%s: failed to get ptp clock\n", __func__);
+                goto put_node;
+        }
+
+        enet_ref = clk_get_sys(NULL, "enet_ref");
+        if (IS_ERR(enet_ref)) {
+                pr_warn("%s: failed to get enet clock\n", __func__);
+                goto put_ptp_clk;
+        }
+
+        /*
+         * If enet_ref from ANATOP/CCM is the PTP clock source, we need to
+         * set bit IOMUXC_GPR1[21].  Or the PTP clock must be from pad
+         * (external OSC), and we need to clear the bit.
+         */
+        clksel = ptp_clk == enet_ref ? IMX6Q_GPR1_ENET_CLK_SEL_ANATOP :
+                                       IMX6Q_GPR1_ENET_CLK_SEL_PAD;
         gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
         if (!IS_ERR(gpr))
                 regmap_update_bits(gpr, IOMUXC_GPR1,
                                 IMX6Q_GPR1_ENET_CLK_SEL_MASK,
-                                IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
+                                clksel);
         else
                 pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
 
+        clk_put(enet_ref);
+put_ptp_clk:
+        clk_put(ptp_clk);
+put_node:
+        of_node_put(np);
+}
+
+static void __init imx6q_axi_init(void)
+{
+        struct regmap *gpr;
+        unsigned int mask;
+
+        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+        if (!IS_ERR(gpr)) {
+                /*
+                 * Enable the cacheable attribute of VPU and IPU
+                 * AXI transactions.
+                 */
+                mask = IMX6Q_GPR4_VPU_WR_CACHE_SEL |
+                        IMX6Q_GPR4_VPU_RD_CACHE_SEL |
+                        IMX6Q_GPR4_VPU_P_WR_CACHE_VAL |
+                        IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |
+                        IMX6Q_GPR4_IPU_WR_CACHE_CTL |
+                        IMX6Q_GPR4_IPU_RD_CACHE_CTL;
+                regmap_update_bits(gpr, IOMUXC_GPR4, mask, mask);
+
+                /* Increase IPU read QoS priority */
+                regmap_update_bits(gpr, IOMUXC_GPR6,
+                                IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK |
+                                IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK,
+                                (0xf << 16) | (0x7 << 20));
+                regmap_update_bits(gpr, IOMUXC_GPR7,
+                                IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK |
+                                IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK,
+                                (0xf << 16) | (0x7 << 20));
+        } else {
+                pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n");
+        }
 }
 
 static void __init imx6q_init_machine(void)
@@ -212,15 +279,18 @@ static void __init imx6q_init_machine(void)
         of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
 
         imx_anatop_init();
-        imx6q_pm_init();
+        cpu_is_imx6q() ?  imx6q_pm_init() : imx6dl_pm_init();
         imx6q_1588_init();
+        imx6q_axi_init();
 }
 
 #define OCOTP_CFG3                      0x440
 #define OCOTP_CFG3_SPEED_SHIFT          16
 #define OCOTP_CFG3_SPEED_1P2GHZ         0x3
+#define OCOTP_CFG3_SPEED_996MHZ         0x2
+#define OCOTP_CFG3_SPEED_852MHZ         0x1
 
-static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
+static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev)
 {
         struct device_node *np;
         void __iomem *base;
@@ -238,11 +308,29 @@ static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
                 goto put_node;
         }
 
+        /*
+         * SPEED_GRADING[1:0] defines the max speed of ARM:
+         * 2b'11: 1200000000Hz;
+         * 2b'10: 996000000Hz;
+         * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
+         * 2b'00: 792000000Hz;
+         * We need to set the max speed of ARM according to fuse map.
+         */
         val = readl_relaxed(base + OCOTP_CFG3);
         val >>= OCOTP_CFG3_SPEED_SHIFT;
-        if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
+        val &= 0x3;
+
+        if (val != OCOTP_CFG3_SPEED_1P2GHZ)
                 if (dev_pm_opp_disable(cpu_dev, 1200000000))
                         pr_warn("failed to disable 1.2 GHz OPP\n");
+        if (val < OCOTP_CFG3_SPEED_996MHZ)
+                if (dev_pm_opp_disable(cpu_dev, 996000000))
+                        pr_warn("failed to disable 996 MHz OPP\n");
+        if (cpu_is_imx6q()) {
+                if (val != OCOTP_CFG3_SPEED_852MHZ)
+                        if (dev_pm_opp_disable(cpu_dev, 852000000))
+                                pr_warn("failed to disable 852 MHz OPP\n");
+        }
 
 put_node:
         of_node_put(np);
@@ -268,7 +356,7 @@ static void __init imx6q_opp_init(void)
                 goto put_node;
         }
 
-        imx6q_opp_check_1p2ghz(cpu_dev);
+        imx6q_opp_check_speed_grading(cpu_dev);
 
 put_node:
         of_node_put(np);
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index 0f4fd4c0ab8e..ad323385115c 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -17,6 +17,7 @@
 #include <asm/mach/map.h>
 
 #include "common.h"
+#include "cpuidle.h"
 
 static void __init imx6sl_fec_init(void)
 {
@@ -39,6 +40,8 @@ static void __init imx6sl_init_late(void)
         /* imx6sl reuses imx6q cpufreq driver */
         if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
                 platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
+
+        imx6sl_cpuidle_init();
 }
 
 static void __init imx6sl_init_machine(void)
@@ -55,8 +58,7 @@ static void __init imx6sl_init_machine(void)
 
         imx6sl_fec_init();
         imx_anatop_init();
-        /* Reuse imx6q pm code */
-        imx6q_pm_init();
+        imx6sl_pm_init();
 }
 
 static void __init imx6sl_init_irq(void)
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
new file mode 100644
index 000000000000..16f0d249f6a7
--- /dev/null
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -0,0 +1,552 @@
+/*
+ * Copyright 2011-2014 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/genalloc.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/regmap.h>
+#include <linux/suspend.h>
+#include <asm/cacheflush.h>
+#include <asm/fncpy.h>
+#include <asm/proc-fns.h>
+#include <asm/suspend.h>
+#include <asm/tlb.h>
+
+#include "common.h"
+#include "hardware.h"
+
+#define CCR                             0x0
+#define BM_CCR_WB_COUNT                 (0x7 << 16)
+#define BM_CCR_RBC_BYPASS_COUNT         (0x3f << 21)
+#define BM_CCR_RBC_EN                   (0x1 << 27)
+
+#define CLPCR                           0x54
+#define BP_CLPCR_LPM                    0
+#define BM_CLPCR_LPM                    (0x3 << 0)
+#define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
+#define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
+#define BM_CLPCR_SBYOS                  (0x1 << 6)
+#define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
+#define BM_CLPCR_VSTBY                  (0x1 << 8)
+#define BP_CLPCR_STBY_COUNT             9
+#define BM_CLPCR_STBY_COUNT             (0x3 << 9)
+#define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
+#define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
+#define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
+#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
+#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
+#define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
+#define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
+#define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
+#define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
+#define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
+#define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
+
+#define CGPR                            0x64
+#define BM_CGPR_INT_MEM_CLK_LPM         (0x1 << 17)
+
+#define MX6Q_SUSPEND_OCRAM_SIZE         0x1000
+#define MX6_MAX_MMDC_IO_NUM             33
+
+static void __iomem *ccm_base;
+static void __iomem *suspend_ocram_base;
+static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
+
+/*
+ * suspend ocram space layout:
+ * ======================== high address ======================
+ *                              .
+ *                              .
+ *                              .
+ *                              ^
+ *                              ^
+ *                              ^
+ *                      imx6_suspend code
+ *              PM_INFO structure(imx6_cpu_pm_info)
+ * ======================== low address =======================
+ */
+
+struct imx6_pm_base {
+        phys_addr_t pbase;
+        void __iomem *vbase;
+};
+
+struct imx6_pm_socdata {
+        u32 cpu_type;
+        const char *mmdc_compat;
+        const char *src_compat;
+        const char *iomuxc_compat;
+        const char *gpc_compat;
+        const u32 mmdc_io_num;
+        const u32 *mmdc_io_offset;
+};
+
+static const u32 imx6q_mmdc_io_offset[] __initconst = {
+        0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
+        0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
+        0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
+        0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
+        0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
+        0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
+        0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
+        0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
+        0x74c,                      /* GPR_ADDS */
+};
+
+static const u32 imx6dl_mmdc_io_offset[] __initconst = {
+        0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
+        0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
+        0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
+        0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
+        0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
+        0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
+        0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
+        0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
+        0x74c,                      /* GPR_ADDS */
+};
+
+static const u32 imx6sl_mmdc_io_offset[] __initconst = {
+        0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
+        0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
+        0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
+        0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
+        0x330, 0x334, 0x320,        /* SDCKE0, SDCKE1, RESET */
+};
+
+static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
+        .cpu_type = MXC_CPU_IMX6Q,
+        .mmdc_compat = "fsl,imx6q-mmdc",
+        .src_compat = "fsl,imx6q-src",
+        .iomuxc_compat = "fsl,imx6q-iomuxc",
+        .gpc_compat = "fsl,imx6q-gpc",
+        .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
+        .mmdc_io_offset = imx6q_mmdc_io_offset,
+};
+
+static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
+        .cpu_type = MXC_CPU_IMX6DL,
+        .mmdc_compat = "fsl,imx6q-mmdc",
+        .src_compat = "fsl,imx6q-src",
+        .iomuxc_compat = "fsl,imx6dl-iomuxc",
+        .gpc_compat = "fsl,imx6q-gpc",
+        .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
+        .mmdc_io_offset = imx6dl_mmdc_io_offset,
+};
+
+static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
+        .cpu_type = MXC_CPU_IMX6SL,
+        .mmdc_compat = "fsl,imx6sl-mmdc",
+        .src_compat = "fsl,imx6sl-src",
+        .iomuxc_compat = "fsl,imx6sl-iomuxc",
+        .gpc_compat = "fsl,imx6sl-gpc",
+        .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
+        .mmdc_io_offset = imx6sl_mmdc_io_offset,
+};
+
+/*
+ * This structure is for passing necessary data for low level ocram
+ * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
+ * definition is changed, the offset definition in
+ * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly,
+ * otherwise, the suspend to ocram function will be broken!
+ */
+struct imx6_cpu_pm_info {
+        phys_addr_t pbase; /* The physical address of pm_info. */
+        phys_addr_t resume_addr; /* The physical resume address for asm code */
+        u32 cpu_type;
+        u32 pm_info_size; /* Size of pm_info. */
+        struct imx6_pm_base mmdc_base;
+        struct imx6_pm_base src_base;
+        struct imx6_pm_base iomuxc_base;
+        struct imx6_pm_base ccm_base;
+        struct imx6_pm_base gpc_base;
+        struct imx6_pm_base l2_base;
+        u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
+        u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
+} __aligned(8);
+
+void imx6q_set_int_mem_clk_lpm(void)
+{
+        u32 val = readl_relaxed(ccm_base + CGPR);
+
+        val |= BM_CGPR_INT_MEM_CLK_LPM;
+        writel_relaxed(val, ccm_base + CGPR);
+}
+
+static void imx6q_enable_rbc(bool enable)
+{
+        u32 val;
+
+        /*
+         * need to mask all interrupts in GPC before
+         * operating RBC configurations
+         */
+        imx_gpc_mask_all();
+
+        /* configure RBC enable bit */
+        val = readl_relaxed(ccm_base + CCR);
+        val &= ~BM_CCR_RBC_EN;
+        val |= enable ? BM_CCR_RBC_EN : 0;
+        writel_relaxed(val, ccm_base + CCR);
+
+        /* configure RBC count */
+        val = readl_relaxed(ccm_base + CCR);
+        val &= ~BM_CCR_RBC_BYPASS_COUNT;
+        val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
+        writel(val, ccm_base + CCR);
+
+        /*
+         * need to delay at least 2 cycles of CKIL(32K)
+         * due to hardware design requirement, which is
+         * ~61us, here we use 65us for safe
+         */
+        udelay(65);
+
+        /* restore GPC interrupt mask settings */
+        imx_gpc_restore_all();
+}
+
+static void imx6q_enable_wb(bool enable)
+{
+        u32 val;
+
+        /* configure well bias enable bit */
+        val = readl_relaxed(ccm_base + CLPCR);
+        val &= ~BM_CLPCR_WB_PER_AT_LPM;
+        val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
+        writel_relaxed(val, ccm_base + CLPCR);
+
+        /* configure well bias count */
+        val = readl_relaxed(ccm_base + CCR);
+        val &= ~BM_CCR_WB_COUNT;
+        val |= enable ? BM_CCR_WB_COUNT : 0;
+        writel_relaxed(val, ccm_base + CCR);
+}
+
+int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
+{
+        struct irq_desc *iomuxc_irq_desc;
+        u32 val = readl_relaxed(ccm_base + CLPCR);
+
+        val &= ~BM_CLPCR_LPM;
+        switch (mode) {
+        case WAIT_CLOCKED:
+                break;
+        case WAIT_UNCLOCKED:
+                val |= 0x1 << BP_CLPCR_LPM;
+                val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
+                break;
+        case STOP_POWER_ON:
+                val |= 0x2 << BP_CLPCR_LPM;
+                break;
+        case WAIT_UNCLOCKED_POWER_OFF:
+                val |= 0x1 << BP_CLPCR_LPM;
+                val &= ~BM_CLPCR_VSTBY;
+                val &= ~BM_CLPCR_SBYOS;
+                break;
+        case STOP_POWER_OFF:
+                val |= 0x2 << BP_CLPCR_LPM;
+                val |= 0x3 << BP_CLPCR_STBY_COUNT;
+                val |= BM_CLPCR_VSTBY;
+                val |= BM_CLPCR_SBYOS;
+                if (cpu_is_imx6sl()) {
+                        val |= BM_CLPCR_BYPASS_PMIC_READY;
+                        val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
+                } else {
+                        val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
+                }
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /*
+         * ERR007265: CCM: When improper low-power sequence is used,
+         * the SoC enters low power mode before the ARM core executes WFI.
+         *
+         * Software workaround:
+         * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
+         *    by setting IOMUX_GPR1_GINT.
+         * 2) Software should then unmask IRQ #32 in GPC before setting CCM
+         *    Low-Power mode.
+         * 3) Software should mask IRQ #32 right after CCM Low-Power mode
+         *    is set (set bits 0-1 of CCM_CLPCR).
+         */
+        iomuxc_irq_desc = irq_to_desc(32);
+        imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data);
+        writel_relaxed(val, ccm_base + CLPCR);
+        imx_gpc_irq_mask(&iomuxc_irq_desc->irq_data);
+
+        return 0;
+}
+
+static int imx6q_suspend_finish(unsigned long val)
+{
+        if (!imx6_suspend_in_ocram_fn) {
+                cpu_do_idle();
+        } else {
+                /*
+                 * call low level suspend function in ocram,
+                 * as we need to float DDR IO.
+                 */
+                local_flush_tlb_all();
+                imx6_suspend_in_ocram_fn(suspend_ocram_base);
+        }
+
+        return 0;
+}
+
+static int imx6q_pm_enter(suspend_state_t state)
+{
+        switch (state) {
+        case PM_SUSPEND_MEM:
+                imx6q_set_lpm(STOP_POWER_OFF);
+                imx6q_enable_wb(true);
+                /*
+                 * For suspend into ocram, asm code already take care of
+                 * RBC setting, so we do NOT need to do that here.
+                 */
+                if (!imx6_suspend_in_ocram_fn)
+                        imx6q_enable_rbc(true);
+                imx_gpc_pre_suspend();
+                imx_anatop_pre_suspend();
+                imx_set_cpu_jump(0, v7_cpu_resume);
+                /* Zzz ... */
+                cpu_suspend(0, imx6q_suspend_finish);
+                if (cpu_is_imx6q() || cpu_is_imx6dl())
+                        imx_smp_prepare();
+                imx_anatop_post_resume();
+                imx_gpc_post_resume();
+                imx6q_enable_rbc(false);
+                imx6q_enable_wb(false);
+                imx6q_set_lpm(WAIT_CLOCKED);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static const struct platform_suspend_ops imx6q_pm_ops = {
+        .enter = imx6q_pm_enter,
+        .valid = suspend_valid_only_mem,
+};
+
+void __init imx6q_pm_set_ccm_base(void __iomem *base)
+{
+        ccm_base = base;
+}
+
+static int __init imx6_pm_get_base(struct imx6_pm_base *base,
+                                const char *compat)
+{
+        struct device_node *node;
+        struct resource res;
+        int ret = 0;
+
+        node = of_find_compatible_node(NULL, NULL, compat);
+        if (!node) {
+                ret = -ENODEV;
+                goto out;
+        }
+
+        ret = of_address_to_resource(node, 0, &res);
+        if (ret)
+                goto put_node;
+
+        base->pbase = res.start;
+        base->vbase = ioremap(res.start, resource_size(&res));
+        if (!base->vbase)
+                ret = -ENOMEM;
+
+put_node:
+        of_node_put(node);
+out:
+        return ret;
+}
+
+static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
+{
+        phys_addr_t ocram_pbase;
+        struct device_node *node;
+        struct platform_device *pdev;
+        struct imx6_cpu_pm_info *pm_info;
+        struct gen_pool *ocram_pool;
+        unsigned long ocram_base;
+        int i, ret = 0;
+        const u32 *mmdc_offset_array;
+
+        suspend_set_ops(&imx6q_pm_ops);
+
+        if (!socdata) {
+                pr_warn("%s: invalid argument!\n", __func__);
+                return -EINVAL;
+        }
+
+        node = of_find_compatible_node(NULL, NULL, "mmio-sram");
+        if (!node) {
+                pr_warn("%s: failed to find ocram node!\n", __func__);
+                return -ENODEV;
+        }
+
+        pdev = of_find_device_by_node(node);
+        if (!pdev) {
+                pr_warn("%s: failed to find ocram device!\n", __func__);
+                ret = -ENODEV;
+                goto put_node;
+        }
+
+        ocram_pool = dev_get_gen_pool(&pdev->dev);
+        if (!ocram_pool) {
+                pr_warn("%s: ocram pool unavailable!\n", __func__);
+                ret = -ENODEV;
+                goto put_node;
+        }
+
+        ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE);
+        if (!ocram_base) {
+                pr_warn("%s: unable to alloc ocram!\n", __func__);
+                ret = -ENOMEM;
+                goto put_node;
+        }
+
+        ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base);
+
+        suspend_ocram_base = __arm_ioremap_exec(ocram_pbase,
+                MX6Q_SUSPEND_OCRAM_SIZE, false);
+
+        pm_info = suspend_ocram_base;
+        pm_info->pbase = ocram_pbase;
+        pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
+        pm_info->pm_info_size = sizeof(*pm_info);
+
+        /*
+         * ccm physical address is not used by asm code currently,
+         * so get ccm virtual address directly, as we already have
+         * it from ccm driver.
+         */
+        pm_info->ccm_base.vbase = ccm_base;
+
+        ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat);
+        if (ret) {
+                pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret);
+                goto put_node;
+        }
+
+        ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat);
+        if (ret) {
+                pr_warn("%s: failed to get src base %d!\n", __func__, ret);
+                goto src_map_failed;
+        }
+
+        ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat);
+        if (ret) {
+                pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret);
+                goto iomuxc_map_failed;
+        }
+
+        ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
+        if (ret) {
+                pr_warn("%s: failed to get gpc base %d!\n", __func__, ret);
+                goto gpc_map_failed;
+        }
+
+        ret = imx6_pm_get_base(&pm_info->l2_base, "arm,pl310-cache");
+        if (ret) {
+                pr_warn("%s: failed to get pl310-cache base %d!\n",
+                        __func__, ret);
+                goto pl310_cache_map_failed;
+        }
+
+        pm_info->cpu_type = socdata->cpu_type;
+        pm_info->mmdc_io_num = socdata->mmdc_io_num;
+        mmdc_offset_array = socdata->mmdc_io_offset;
+
+        for (i = 0; i < pm_info->mmdc_io_num; i++) {
+                pm_info->mmdc_io_val[i][0] =
+                        mmdc_offset_array[i];
+                pm_info->mmdc_io_val[i][1] =
+                        readl_relaxed(pm_info->iomuxc_base.vbase +
+                        mmdc_offset_array[i]);
+        }
+
+        imx6_suspend_in_ocram_fn = fncpy(
+                suspend_ocram_base + sizeof(*pm_info),
+                &imx6_suspend,
+                MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
+
+        goto put_node;
+
+pl310_cache_map_failed:
+        iounmap(&pm_info->gpc_base.vbase);
+gpc_map_failed:
+        iounmap(&pm_info->iomuxc_base.vbase);
+iomuxc_map_failed:
+        iounmap(&pm_info->src_base.vbase);
+src_map_failed:
+        iounmap(&pm_info->mmdc_base.vbase);
+put_node:
+        of_node_put(node);
+
+        return ret;
+}
+
+static void __init imx6_pm_common_init(const struct imx6_pm_socdata
+                                        *socdata)
+{
+        struct regmap *gpr;
+        int ret;
+
+        WARN_ON(!ccm_base);
+
+        if (IS_ENABLED(CONFIG_SUSPEND)) {
+                ret = imx6q_suspend_init(socdata);
+                if (ret)
+                        pr_warn("%s: No DDR LPM support with suspend %d!\n",
+                                __func__, ret);
+        }
+
+        /*
+         * This is for SW workaround step #1 of ERR007265, see comments
+         * in imx6q_set_lpm for details of this errata.
+         * Force IOMUXC irq pending, so that the interrupt to GPC can be
+         * used to deassert dsm_request signal when the signal gets
+         * asserted unexpectedly.
+         */
+        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+        if (!IS_ERR(gpr))
+                regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
+                                   IMX6Q_GPR1_GINT);
+}
+
+void __init imx6q_pm_init(void)
+{
+        imx6_pm_common_init(&imx6q_pm_data);
+}
+
+void __init imx6dl_pm_init(void)
+{
+        imx6_pm_common_init(&imx6dl_pm_data);
+}
+
+void __init imx6sl_pm_init(void)
+{
+        imx6_pm_common_init(&imx6sl_pm_data);
+}
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
deleted file mode 100644
index 9d47adc078aa..000000000000
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * Copyright 2011-2013 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/mfd/syscon.h>
-#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/regmap.h>
-#include <linux/suspend.h>
-#include <asm/cacheflush.h>
-#include <asm/proc-fns.h>
-#include <asm/suspend.h>
-#include <asm/hardware/cache-l2x0.h>
-
-#include "common.h"
-#include "hardware.h"
-
-#define CCR                             0x0
-#define BM_CCR_WB_COUNT                 (0x7 << 16)
-#define BM_CCR_RBC_BYPASS_COUNT         (0x3f << 21)
-#define BM_CCR_RBC_EN                   (0x1 << 27)
-
-#define CLPCR                           0x54
-#define BP_CLPCR_LPM                    0
-#define BM_CLPCR_LPM                    (0x3 << 0)
-#define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
-#define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
-#define BM_CLPCR_SBYOS                  (0x1 << 6)
-#define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
-#define BM_CLPCR_VSTBY                  (0x1 << 8)
-#define BP_CLPCR_STBY_COUNT             9
-#define BM_CLPCR_STBY_COUNT             (0x3 << 9)
-#define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
-#define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
-#define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
-#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
-#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
-#define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
-#define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
-#define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
-#define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
-#define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
-#define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
-
-#define CGPR                            0x64
-#define BM_CGPR_CHICKEN_BIT             (0x1 << 17)
-
-static void __iomem *ccm_base;
-
-void imx6q_set_chicken_bit(void)
-{
-        u32 val = readl_relaxed(ccm_base + CGPR);
-
-        val |= BM_CGPR_CHICKEN_BIT;
-        writel_relaxed(val, ccm_base + CGPR);
-}
-
-static void imx6q_enable_rbc(bool enable)
-{
-        u32 val;
-
-        /*
-         * need to mask all interrupts in GPC before
-         * operating RBC configurations
-         */
-        imx_gpc_mask_all();
-
-        /* configure RBC enable bit */
-        val = readl_relaxed(ccm_base + CCR);
-        val &= ~BM_CCR_RBC_EN;
-        val |= enable ? BM_CCR_RBC_EN : 0;
-        writel_relaxed(val, ccm_base + CCR);
-
-        /* configure RBC count */
-        val = readl_relaxed(ccm_base + CCR);
-        val &= ~BM_CCR_RBC_BYPASS_COUNT;
-        val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
-        writel(val, ccm_base + CCR);
-
-        /*
-         * need to delay at least 2 cycles of CKIL(32K)
-         * due to hardware design requirement, which is
-         * ~61us, here we use 65us for safe
-         */
-        udelay(65);
-
-        /* restore GPC interrupt mask settings */
-        imx_gpc_restore_all();
-}
-
-static void imx6q_enable_wb(bool enable)
-{
-        u32 val;
-
-        /* configure well bias enable bit */
-        val = readl_relaxed(ccm_base + CLPCR);
-        val &= ~BM_CLPCR_WB_PER_AT_LPM;
-        val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
-        writel_relaxed(val, ccm_base + CLPCR);
-
-        /* configure well bias count */
-        val = readl_relaxed(ccm_base + CCR);
-        val &= ~BM_CCR_WB_COUNT;
-        val |= enable ? BM_CCR_WB_COUNT : 0;
-        writel_relaxed(val, ccm_base + CCR);
-}
-
-int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
-{
-        struct irq_desc *iomuxc_irq_desc;
-        u32 val = readl_relaxed(ccm_base + CLPCR);
-
-        val &= ~BM_CLPCR_LPM;
-        switch (mode) {
-        case WAIT_CLOCKED:
-                break;
-        case WAIT_UNCLOCKED:
-                val |= 0x1 << BP_CLPCR_LPM;
-                val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
-                break;
-        case STOP_POWER_ON:
-                val |= 0x2 << BP_CLPCR_LPM;
-                break;
-        case WAIT_UNCLOCKED_POWER_OFF:
-                val |= 0x1 << BP_CLPCR_LPM;
-                val &= ~BM_CLPCR_VSTBY;
-                val &= ~BM_CLPCR_SBYOS;
-                break;
-        case STOP_POWER_OFF:
-                val |= 0x2 << BP_CLPCR_LPM;
-                val |= 0x3 << BP_CLPCR_STBY_COUNT;
-                val |= BM_CLPCR_VSTBY;
-                val |= BM_CLPCR_SBYOS;
-                if (cpu_is_imx6sl()) {
-                        val |= BM_CLPCR_BYPASS_PMIC_READY;
-                        val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
-                } else {
-                        val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
-                }
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        /*
-         * ERR007265: CCM: When improper low-power sequence is used,
-         * the SoC enters low power mode before the ARM core executes WFI.
-         *
-         * Software workaround:
-         * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
-         *    by setting IOMUX_GPR1_GINT.
-         * 2) Software should then unmask IRQ #32 in GPC before setting CCM
-         *    Low-Power mode.
-         * 3) Software should mask IRQ #32 right after CCM Low-Power mode
-         *    is set (set bits 0-1 of CCM_CLPCR).
-         */
-        iomuxc_irq_desc = irq_to_desc(32);
-        imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data);
-        writel_relaxed(val, ccm_base + CLPCR);
-        imx_gpc_irq_mask(&iomuxc_irq_desc->irq_data);
-
-        return 0;
-}
-
-static int imx6q_suspend_finish(unsigned long val)
-{
-        cpu_do_idle();
-        return 0;
-}
-
-static int imx6q_pm_enter(suspend_state_t state)
-{
-        switch (state) {
-        case PM_SUSPEND_MEM:
-                imx6q_set_lpm(STOP_POWER_OFF);
-                imx6q_enable_wb(true);
-                imx6q_enable_rbc(true);
-                imx_gpc_pre_suspend();
-                imx_anatop_pre_suspend();
-                imx_set_cpu_jump(0, v7_cpu_resume);
-                /* Zzz ... */
-                cpu_suspend(0, imx6q_suspend_finish);
-                if (cpu_is_imx6q() || cpu_is_imx6dl())
-                        imx_smp_prepare();
-                imx_anatop_post_resume();
-                imx_gpc_post_resume();
-                imx6q_enable_rbc(false);
-                imx6q_enable_wb(false);
-                imx6q_set_lpm(WAIT_CLOCKED);
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static const struct platform_suspend_ops imx6q_pm_ops = {
-        .enter = imx6q_pm_enter,
-        .valid = suspend_valid_only_mem,
-};
-
-void __init imx6q_pm_set_ccm_base(void __iomem *base)
-{
-        ccm_base = base;
-}
-
-void __init imx6q_pm_init(void)
-{
-        struct regmap *gpr;
-
-        WARN_ON(!ccm_base);
-
-        /*
-         * This is for SW workaround step #1 of ERR007265, see comments
-         * in imx6q_set_lpm for details of this errata.
-         * Force IOMUXC irq pending, so that the interrupt to GPC can be
-         * used to deassert dsm_request signal when the signal gets
-         * asserted unexpectedly.
-         */
-        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
-        if (!IS_ERR(gpr))
-                regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
-                                   IMX6Q_GPR1_GINT);
-
-        /* Set initial power mode */
-        imx6q_set_lpm(WAIT_CLOCKED);
-
-        suspend_set_ops(&imx6q_pm_ops);
-}
diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S
new file mode 100644
index 000000000000..20048ff05739
--- /dev/null
+++ b/arch/arm/mach-imx/suspend-imx6.S
@@ -0,0 +1,361 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/linkage.h>
+#include <asm/asm-offsets.h>
+#include <asm/hardware/cache-l2x0.h>
+#include "hardware.h"
+
+/*
+ * ==================== low level suspend ====================
+ *
+ * Better to follow below rules to use ARM registers:
+ * r0: pm_info structure address;
+ * r1 ~ r4: for saving pm_info members;
+ * r5 ~ r10: free registers;
+ * r11: io base address.
+ *
+ * suspend ocram space layout:
+ * ======================== high address ======================
+ *                              .
+ *                              .
+ *                              .
+ *                              ^
+ *                              ^
+ *                              ^
+ *                      imx6_suspend code
+ *              PM_INFO structure(imx6_cpu_pm_info)
+ * ======================== low address =======================
+ */
+
+/*
+ * Below offsets are based on struct imx6_cpu_pm_info
+ * which defined in arch/arm/mach-imx/pm-imx6q.c, this
+ * structure contains necessary pm info for low level
+ * suspend related code.
+ */
+#define PM_INFO_PBASE_OFFSET                    0x0
+#define PM_INFO_RESUME_ADDR_OFFSET              0x4
+#define PM_INFO_CPU_TYPE_OFFSET                 0x8
+#define PM_INFO_PM_INFO_SIZE_OFFSET             0xC
+#define PM_INFO_MX6Q_MMDC_P_OFFSET              0x10
+#define PM_INFO_MX6Q_MMDC_V_OFFSET              0x14
+#define PM_INFO_MX6Q_SRC_P_OFFSET               0x18
+#define PM_INFO_MX6Q_SRC_V_OFFSET               0x1C
+#define PM_INFO_MX6Q_IOMUXC_P_OFFSET            0x20
+#define PM_INFO_MX6Q_IOMUXC_V_OFFSET            0x24
+#define PM_INFO_MX6Q_CCM_P_OFFSET               0x28
+#define PM_INFO_MX6Q_CCM_V_OFFSET               0x2C
+#define PM_INFO_MX6Q_GPC_P_OFFSET               0x30
+#define PM_INFO_MX6Q_GPC_V_OFFSET               0x34
+#define PM_INFO_MX6Q_L2_P_OFFSET                0x38
+#define PM_INFO_MX6Q_L2_V_OFFSET                0x3C
+#define PM_INFO_MMDC_IO_NUM_OFFSET              0x40
+#define PM_INFO_MMDC_IO_VAL_OFFSET              0x44
+
+#define MX6Q_SRC_GPR1   0x20
+#define MX6Q_SRC_GPR2   0x24
+#define MX6Q_MMDC_MAPSR 0x404
+#define MX6Q_MMDC_MPDGCTRL0     0x83c
+#define MX6Q_GPC_IMR1   0x08
+#define MX6Q_GPC_IMR2   0x0c
+#define MX6Q_GPC_IMR3   0x10
+#define MX6Q_GPC_IMR4   0x14
+#define MX6Q_CCM_CCR    0x0
+
+        .align 3
+
+        .macro  sync_l2_cache
+
+        /* sync L2 cache to drain L2's buffers to DRAM. */
+#ifdef CONFIG_CACHE_L2X0
+        ldr     r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
+        mov     r6, #0x0
+        str     r6, [r11, #L2X0_CACHE_SYNC]
+1:
+        ldr     r6, [r11, #L2X0_CACHE_SYNC]
+        ands    r6, r6, #0x1
+        bne     1b
+#endif
+
+        .endm
+
+        .macro  resume_mmdc
+
+        /* restore MMDC IO */
+        cmp     r5, #0x0
+        ldreq   r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
+        ldrne   r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET]
+
+        ldr     r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
+        ldr     r7, =PM_INFO_MMDC_IO_VAL_OFFSET
+        add     r7, r7, r0
+1:
+        ldr     r8, [r7], #0x4
+        ldr     r9, [r7], #0x4
+        str     r9, [r11, r8]
+        subs    r6, r6, #0x1
+        bne     1b
+
+        cmp     r5, #0x0
+        ldreq   r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
+        ldrne   r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
+
+        cmp     r3, #MXC_CPU_IMX6SL
+        bne     4f
+
+        /* reset read FIFO, RST_RD_FIFO */
+        ldr     r7, =MX6Q_MMDC_MPDGCTRL0
+        ldr     r6, [r11, r7]
+        orr     r6, r6, #(1 << 31)
+        str     r6, [r11, r7]
+2:
+        ldr     r6, [r11, r7]
+        ands    r6, r6, #(1 << 31)
+        bne     2b
+
+        /* reset FIFO a second time */
+        ldr     r6, [r11, r7]
+        orr     r6, r6, #(1 << 31)
+        str     r6, [r11, r7]
+3:
+        ldr     r6, [r11, r7]
+        ands    r6, r6, #(1 << 31)
+        bne     3b
+4:
+        /* let DDR out of self-refresh */
+        ldr     r7, [r11, #MX6Q_MMDC_MAPSR]
+        bic     r7, r7, #(1 << 21)
+        str     r7, [r11, #MX6Q_MMDC_MAPSR]
+5:
+        ldr     r7, [r11, #MX6Q_MMDC_MAPSR]
+        ands    r7, r7, #(1 << 25)
+        bne     5b
+
+        /* enable DDR auto power saving */
+        ldr     r7, [r11, #MX6Q_MMDC_MAPSR]
+        bic     r7, r7, #0x1
+        str     r7, [r11, #MX6Q_MMDC_MAPSR]
+
+        .endm
+
+ENTRY(imx6_suspend)
+        ldr     r1, [r0, #PM_INFO_PBASE_OFFSET]
+        ldr     r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
+        ldr     r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
+        ldr     r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
+
+        /*
+         * counting the resume address in iram
+         * to set it in SRC register.
+         */
+        ldr     r6, =imx6_suspend
+        ldr     r7, =resume
+        sub     r7, r7, r6
+        add     r8, r1, r4
+        add     r9, r8, r7
+
+        /*
+         * make sure TLB contain the addr we want,
+         * as we will access them after MMDC IO floated.
+         */
+
+        ldr     r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
+        ldr     r6, [r11, #0x0]
+        ldr     r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
+        ldr     r6, [r11, #0x0]
+
+        /* use r11 to store the IO address */
+        ldr     r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
+        /* store physical resume addr and pm_info address. */
+        str     r9, [r11, #MX6Q_SRC_GPR1]
+        str     r1, [r11, #MX6Q_SRC_GPR2]
+
+        /* need to sync L2 cache before DSM. */
+        sync_l2_cache
+
+        ldr     r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
+        /*
+         * put DDR explicitly into self-refresh and
+         * disable automatic power savings.
+         */
+        ldr     r7, [r11, #MX6Q_MMDC_MAPSR]
+        orr     r7, r7, #0x1
+        str     r7, [r11, #MX6Q_MMDC_MAPSR]
+
+        /* make the DDR explicitly enter self-refresh. */
+        ldr     r7, [r11, #MX6Q_MMDC_MAPSR]
+        orr     r7, r7, #(1 << 21)
+        str     r7, [r11, #MX6Q_MMDC_MAPSR]
+
+poll_dvfs_set:
+        ldr     r7, [r11, #MX6Q_MMDC_MAPSR]
+        ands    r7, r7, #(1 << 25)
+        beq     poll_dvfs_set
+
+        ldr     r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
+        ldr     r6, =0x0
+        ldr     r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
+        ldr     r8, =PM_INFO_MMDC_IO_VAL_OFFSET
+        add     r8, r8, r0
+        /* i.MX6SL's last 3 IOs need special setting */
+        cmp     r3, #MXC_CPU_IMX6SL
+        subeq   r7, r7, #0x3
+set_mmdc_io_lpm:
+        ldr     r9, [r8], #0x8
+        str     r6, [r11, r9]
+        subs    r7, r7, #0x1
+        bne     set_mmdc_io_lpm
+
+        cmp     r3, #MXC_CPU_IMX6SL
+        bne     set_mmdc_io_lpm_done
+        ldr     r6, =0x1000
+        ldr     r9, [r8], #0x8
+        str     r6, [r11, r9]
+        ldr     r9, [r8], #0x8
+        str     r6, [r11, r9]
+        ldr     r6, =0x80000
+        ldr     r9, [r8]
+        str     r6, [r11, r9]
+set_mmdc_io_lpm_done:
+
+        /*
+         * mask all GPC interrupts before
+         * enabling the RBC counters to
+         * avoid the counter starting too
+         * early if an interupt is already
+         * pending.
+         */
+        ldr     r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
+        ldr     r6, [r11, #MX6Q_GPC_IMR1]
+        ldr     r7, [r11, #MX6Q_GPC_IMR2]
+        ldr     r8, [r11, #MX6Q_GPC_IMR3]
+        ldr     r9, [r11, #MX6Q_GPC_IMR4]
+
+        ldr     r10, =0xffffffff
+        str     r10, [r11, #MX6Q_GPC_IMR1]
+        str     r10, [r11, #MX6Q_GPC_IMR2]
+        str     r10, [r11, #MX6Q_GPC_IMR3]
+        str     r10, [r11, #MX6Q_GPC_IMR4]
+
+        /*
+         * enable the RBC bypass counter here
+         * to hold off the interrupts. RBC counter
+         * = 32 (1ms), Minimum RBC delay should be
+         * 400us for the analog LDOs to power down.
+         */
+        ldr     r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
+        ldr     r10, [r11, #MX6Q_CCM_CCR]
+        bic     r10, r10, #(0x3f << 21)
+        orr     r10, r10, #(0x20 << 21)
+        str     r10, [r11, #MX6Q_CCM_CCR]
+
+        /* enable the counter. */
+        ldr     r10, [r11, #MX6Q_CCM_CCR]
+        orr     r10, r10, #(0x1 << 27)
+        str     r10, [r11, #MX6Q_CCM_CCR]
+
+        /* unmask all the GPC interrupts. */
+        ldr     r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
+        str     r6, [r11, #MX6Q_GPC_IMR1]
+        str     r7, [r11, #MX6Q_GPC_IMR2]
+        str     r8, [r11, #MX6Q_GPC_IMR3]
+        str     r9, [r11, #MX6Q_GPC_IMR4]
+
+        /*
+         * now delay for a short while (3usec)
+         * ARM is at 1GHz at this point
+         * so a short loop should be enough.
+         * this delay is required to ensure that
+         * the RBC counter can start counting in
+         * case an interrupt is already pending
+         * or in case an interrupt arrives just
+         * as ARM is about to assert DSM_request.
+         */
+        ldr     r6, =2000
+rbc_loop:
+        subs    r6, r6, #0x1
+        bne     rbc_loop
+
+        /* Zzz, enter stop mode */
+        wfi
+        nop
+        nop
+        nop
+        nop
+
+        /*
+         * run to here means there is pending
+         * wakeup source, system should auto
+         * resume, we need to restore MMDC IO first
+         */
+        mov     r5, #0x0
+        resume_mmdc
+
+        /* return to suspend finish */
+        mov     pc, lr
+
+resume:
+        /* invalidate L1 I-cache first */
+        mov     r6, #0x0
+        mcr     p15, 0, r6, c7, c5, 0
+        mcr     p15, 0, r6, c7, c5, 6
+        /* enable the Icache and branch prediction */
+        mov     r6, #0x1800
+        mcr     p15, 0, r6, c1, c0, 0
+        isb
+
+        /* get physical resume address from pm_info. */
+        ldr     lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
+        /* clear core0's entry and parameter */
+        ldr     r11, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET]
+        mov     r7, #0x0
+        str     r7, [r11, #MX6Q_SRC_GPR1]
+        str     r7, [r11, #MX6Q_SRC_GPR2]
+
+        ldr     r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
+        mov     r5, #0x1
+        resume_mmdc
+
+        mov     pc, lr
+ENDPROC(imx6_suspend)
+
+/*
+ * The following code must assume it is running from physical address
+ * where absolute virtual addresses to the data section have to be
+ * turned into relative ones.
+ */
+
+#ifdef CONFIG_CACHE_L2X0
+        .macro  pl310_resume
+        adr     r0, l2x0_saved_regs_offset
+        ldr     r2, [r0]
+        add     r2, r2, r0
+        ldr     r0, [r2, #L2X0_R_PHY_BASE]      @ get physical base of l2x0
+        ldr     r1, [r2, #L2X0_R_AUX_CTRL]      @ get aux_ctrl value
+        str     r1, [r0, #L2X0_AUX_CTRL]        @ restore aux_ctrl
+        mov     r1, #0x1
+        str     r1, [r0, #L2X0_CTRL]            @ re-enable L2
+        .endm
+
+l2x0_saved_regs_offset:
+        .word   l2x0_saved_regs - .
+
+#else
+        .macro  pl310_resume
+        .endm
+#endif
+
+ENTRY(v7_cpu_resume)
+        bl      v7_invalidate_l1
+        pl310_resume
+        b       cpu_resume
+ENDPROC(v7_cpu_resume)
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index 1a3a5f615770..65222ea0df6d 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -25,6 +25,7 @@
 #include <linux/irq.h>
 #include <linux/clockchips.h>
 #include <linux/clk.h>
+#include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/sched_clock.h>
 
@@ -116,11 +117,22 @@ static u64 notrace mxc_read_sched_clock(void)
         return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
 }
 
+static struct delay_timer imx_delay_timer;
+
+static unsigned long imx_read_current_timer(void)
+{
+        return __raw_readl(sched_clock_reg);
+}
+
 static int __init mxc_clocksource_init(struct clk *timer_clk)
 {
         unsigned int c = clk_get_rate(timer_clk);
         void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
 
+        imx_delay_timer.read_current_timer = &imx_read_current_timer;
+        imx_delay_timer.freq = c;
+        register_current_timer_delay(&imx_delay_timer);
+
         sched_clock_reg = reg;
 
         sched_clock_register(mxc_read_sched_clock, 32, c);
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
index 90a708fef541..f50bc936cb84 100644
--- a/arch/arm/mach-keystone/Kconfig
+++ b/arch/arm/mach-keystone/Kconfig
@@ -1,13 +1,9 @@
 config ARCH_KEYSTONE
         bool "Texas Instruments Keystone Devices"
         depends on ARCH_MULTI_V7
-        select CPU_V7
         select ARM_GIC
         select HAVE_ARM_ARCH_TIMER
-        select HAVE_SMP
         select CLKSRC_MMIO
-        select GENERIC_CLOCKEVENTS
-        select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_ERRATA_798181 if SMP
         select COMMON_CLK_KEYSTONE
         select ARCH_SUPPORTS_BIG_ENDIAN
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index fe8319ad3158..df4b26340ae4 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -106,13 +106,6 @@ config ARCH_KIRKWOOD_DT
           Say 'Y' here if you want your kernel to support the
           Marvell Kirkwood using flattened device tree.
 
-config MACH_MV88F6281GTW_GE_DT
-        bool "Marvell 88F6281 GTW GE Board (Flattened Device Tree)"
-        depends on ARCH_KIRKWOOD_DT
-        help
-          Say 'Y' here if you want your kernel to support the
-          Marvell 88F6281 GTW GE Board (Flattened Device Tree).
-
 endmenu
 
 endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 144b51102939..3a72c5c6e747 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -1,5 +1,4 @@
-obj-y                           += common.o pcie.o
-obj-$(CONFIG_KIRKWOOD_LEGACY)   += irq.o mpp.o
+obj-$(CONFIG_KIRKWOOD_LEGACY)   += irq.o mpp.o common.o pcie.o
 obj-$(CONFIG_PM)                += pm.o
 
 obj-$(CONFIG_MACH_D2NET_V2)             += d2net_v2-setup.o lacie_v2-common.o
@@ -13,4 +12,3 @@ obj-$(CONFIG_MACH_TS219)		+= ts219-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_TS41X)                += ts41x-setup.o tsx1x-common.o
 
 obj-$(CONFIG_ARCH_KIRKWOOD_DT)          += board-dt.o
-obj-$(CONFIG_MACH_MV88F6281GTW_GE_DT)   += board-mv88f6281gtw_ge.o
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 78188159484d..2801da49e2a3 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -19,11 +19,84 @@
 #include <linux/of_platform.h>
 #include <linux/dma-mapping.h>
 #include <linux/irqchip.h>
-#include <linux/kexec.h>
+#include <asm/hardware/cache-feroceon-l2.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/map.h>
 #include <mach/bridge-regs.h>
 #include <plat/common.h>
-#include "common.h"
+#include <plat/pcie.h>
+#include "pm.h"
+
+static struct map_desc kirkwood_io_desc[] __initdata = {
+        {
+                .virtual        = (unsigned long) KIRKWOOD_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
+                .length         = KIRKWOOD_REGS_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+static void __init kirkwood_map_io(void)
+{
+        iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
+}
+
+static struct resource kirkwood_cpufreq_resources[] = {
+        [0] = {
+                .start  = CPU_CONTROL_PHYS,
+                .end    = CPU_CONTROL_PHYS + 3,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device kirkwood_cpufreq_device = {
+        .name           = "kirkwood-cpufreq",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(kirkwood_cpufreq_resources),
+        .resource       = kirkwood_cpufreq_resources,
+};
+
+static void __init kirkwood_cpufreq_init(void)
+{
+        platform_device_register(&kirkwood_cpufreq_device);
+}
+
+static struct resource kirkwood_cpuidle_resource[] = {
+        {
+                .flags  = IORESOURCE_MEM,
+                .start  = DDR_OPERATION_BASE,
+                .end    = DDR_OPERATION_BASE + 3,
+        },
+};
+
+static struct platform_device kirkwood_cpuidle = {
+        .name           = "kirkwood_cpuidle",
+        .id             = -1,
+        .resource       = kirkwood_cpuidle_resource,
+        .num_resources  = 1,
+};
+
+static void __init kirkwood_cpuidle_init(void)
+{
+        platform_device_register(&kirkwood_cpuidle);
+}
+
+/* Temporary here since mach-mvebu has a function we can use */
+static void kirkwood_restart(enum reboot_mode mode, const char *cmd)
+{
+        /*
+         * Enable soft reset to assert RSTOUTn.
+         */
+        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+
+        /*
+         * Assert soft reset.
+         */
+        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+
+        while (1)
+                ;
+}
 
 #define MV643XX_ETH_MAC_ADDR_LOW        0x0414
 #define MV643XX_ETH_MAC_ADDR_HIGH       0x0418
@@ -104,35 +177,35 @@ eth_fixup_skip:
         }
 }
 
-static void __init kirkwood_dt_init(void)
+/*
+ * Disable propagation of mbus errors to the CPU local bus, as this
+ * causes mbus errors (which can occur for example for PCI aborts) to
+ * throw CPU aborts, which we're not set up to deal with.
+ */
+static void __init kirkwood_disable_mbus_error_propagation(void)
 {
-        pr_info("Kirkwood: %s.\n", kirkwood_id());
+        void __iomem *cpu_config;
 
-        /*
-         * Disable propagation of mbus errors to the CPU local bus,
-         * as this causes mbus errors (which can occur for example
-         * for PCI aborts) to throw CPU aborts, which we're not set
-         * up to deal with.
-         */
-        writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
+        cpu_config = ioremap(CPU_CONFIG_PHYS, 4);
+        writel(readl(cpu_config) & ~CPU_CONFIG_ERROR_PROP, cpu_config);
+        iounmap(cpu_config);
+}
 
-        BUG_ON(mvebu_mbus_dt_init());
+static void __init kirkwood_dt_init(void)
+{
+        kirkwood_disable_mbus_error_propagation();
 
-        kirkwood_l2_init();
+        BUG_ON(mvebu_mbus_dt_init());
 
+#ifdef CONFIG_CACHE_FEROCEON_L2
+        feroceon_of_init();
+#endif
         kirkwood_cpufreq_init();
         kirkwood_cpuidle_init();
 
         kirkwood_pm_init();
         kirkwood_dt_eth_fixup();
 
-#ifdef CONFIG_KEXEC
-        kexec_reinit = kirkwood_enable_pcie;
-#endif
-
-        if (of_machine_is_compatible("marvell,mv88f6281gtw-ge"))
-                mv88f6281gtw_ge_init();
-
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
diff --git a/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c b/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c
deleted file mode 100644
index ee5eea678c11..000000000000
--- a/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c
- *
- * Marvell 88F6281 GTW GE Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-#include <linux/timer.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/ethtool.h>
-#include <linux/gpio.h>
-#include <net/dsa.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include <mach/kirkwood.h>
-#include "common.h"
-
-static struct mv643xx_eth_platform_data mv88f6281gtw_ge_ge00_data = {
-        .phy_addr       = MV643XX_ETH_PHY_NONE,
-        .speed          = SPEED_1000,
-        .duplex         = DUPLEX_FULL,
-};
-
-static struct dsa_chip_data mv88f6281gtw_ge_switch_chip_data = {
-        .port_names[0]  = "lan1",
-        .port_names[1]  = "lan2",
-        .port_names[2]  = "lan3",
-        .port_names[3]  = "lan4",
-        .port_names[4]  = "wan",
-        .port_names[5]  = "cpu",
-};
-
-static struct dsa_platform_data mv88f6281gtw_ge_switch_plat_data = {
-        .nr_chips       = 1,
-        .chip           = &mv88f6281gtw_ge_switch_chip_data,
-};
-
-void __init mv88f6281gtw_ge_init(void)
-{
-        kirkwood_ge00_init(&mv88f6281gtw_ge_ge00_data);
-        kirkwood_ge00_switch_init(&mv88f6281gtw_ge_switch_plat_data, NO_IRQ);
-}
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index f3407a5db216..255f33a3903c 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -25,10 +25,10 @@
 #include <asm/page.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include <asm/hardware/cache-feroceon-l2.h>
 #include <mach/kirkwood.h>
 #include <mach/bridge-regs.h>
 #include <linux/platform_data/asoc-kirkwood.h>
-#include <plat/cache-feroceon-l2.h>
 #include <linux/platform_data/mmc-mvsdio.h>
 #include <linux/platform_data/mtd-orion_nand.h>
 #include <linux/platform_data/usb-ehci-orion.h>
@@ -36,6 +36,7 @@
 #include <plat/time.h>
 #include <linux/platform_data/dma-mv_xor.h>
 #include "common.h"
+#include "pm.h"
 
 /* These can go away once Kirkwood uses the mvebu-mbus DT binding */
 #define KIRKWOOD_MBUS_NAND_TARGET 0x01
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 05fd648df543..832a4e2ab8d7 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -58,19 +58,6 @@ void kirkwood_cpufreq_init(void);
 void kirkwood_restart(enum reboot_mode, const char *);
 void kirkwood_clk_init(void);
 
-#ifdef CONFIG_PM
-void kirkwood_pm_init(void);
-#else
-static inline void kirkwood_pm_init(void) {};
-#endif
-
-/* board init functions for boards not fully converted to fdt */
-#ifdef CONFIG_MACH_MV88F6281GTW_GE_DT
-void mv88f6281gtw_ge_init(void);
-#else
-static inline void mv88f6281gtw_ge_init(void) {};
-#endif
-
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 8b9d1c9ff199..6e5077e2ec26 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -14,6 +14,7 @@
 #include <mach/kirkwood.h>
 
 #define CPU_CONFIG              (BRIDGE_VIRT_BASE + 0x0100)
+#define CPU_CONFIG_PHYS         (BRIDGE_PHYS_BASE + 0x0100)
 #define CPU_CONFIG_ERROR_PROP   0x00000004
 
 #define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
@@ -79,5 +80,6 @@
 #define CGC_RESERVED            (0x6 << 21)
 
 #define MEMORY_PM_CTRL          (BRIDGE_VIRT_BASE + 0x118)
+#define MEMORY_PM_CTRL_PHYS     (BRIDGE_PHYS_BASE + 0x118)
 
 #endif
diff --git a/arch/arm/mach-kirkwood/pm.c b/arch/arm/mach-kirkwood/pm.c
index c6ab8d9303a5..8e5e0329d04c 100644
--- a/arch/arm/mach-kirkwood/pm.c
+++ b/arch/arm/mach-kirkwood/pm.c
@@ -21,15 +21,16 @@
 #include "common.h"
 
 static void __iomem *ddr_operation_base;
+static void __iomem *memory_pm_ctrl;
 
 static void kirkwood_low_power(void)
 {
         u32 mem_pm_ctrl;
 
-        mem_pm_ctrl = readl(MEMORY_PM_CTRL);
+        mem_pm_ctrl = readl(memory_pm_ctrl);
 
         /* Set peripherals to low-power mode */
-        writel_relaxed(~0, MEMORY_PM_CTRL);
+        writel_relaxed(~0, memory_pm_ctrl);
 
         /* Set DDR in self-refresh */
         writel_relaxed(0x7, ddr_operation_base);
@@ -41,7 +42,7 @@ static void kirkwood_low_power(void)
          */
         cpu_do_idle();
 
-        writel_relaxed(mem_pm_ctrl, MEMORY_PM_CTRL);
+        writel_relaxed(mem_pm_ctrl, memory_pm_ctrl);
 }
 
 static int kirkwood_suspend_enter(suspend_state_t state)
@@ -69,5 +70,7 @@ static const struct platform_suspend_ops kirkwood_suspend_ops = {
 void __init kirkwood_pm_init(void)
 {
         ddr_operation_base = ioremap(DDR_OPERATION_BASE, 4);
+        memory_pm_ctrl = ioremap(MEMORY_PM_CTRL_PHYS, 4);
+
         suspend_set_ops(&kirkwood_suspend_ops);
 }
diff --git a/arch/arm/mach-kirkwood/pm.h b/arch/arm/mach-kirkwood/pm.h
new file mode 100644
index 000000000000..21e7530f368b
--- /dev/null
+++ b/arch/arm/mach-kirkwood/pm.h
@@ -0,0 +1,26 @@
+/*
+ * Power Management driver for Marvell Kirkwood SoCs
+ *
+ * Copyright (C) 2013 Ezequiel Garcia <ezequiel@free-electrons.com>
+ * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License,
+ * version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_KIRKWOOD_PM_H
+#define __ARCH_KIRKWOOD_PM_H
+
+#ifdef CONFIG_PM
+void kirkwood_pm_init(void);
+#else
+static inline void kirkwood_pm_init(void) {};
+#endif
+
+#endif
diff --git a/arch/arm/mach-moxart/Kconfig b/arch/arm/mach-moxart/Kconfig
index ba470d64493b..95a6a4b43c37 100644
--- a/arch/arm/mach-moxart/Kconfig
+++ b/arch/arm/mach-moxart/Kconfig
@@ -2,15 +2,9 @@ config ARCH_MOXART
         bool "MOXA ART SoC" if ARCH_MULTI_V4T
         select CPU_FA526
         select ARM_DMA_MEM_BUFFERABLE
-        select DMA_OF
-        select USE_OF
-        select CLKSRC_OF
         select CLKSRC_MMIO
-        select HAVE_CLK
-        select COMMON_CLK
         select GENERIC_IRQ_CHIP
         select ARCH_REQUIRE_GPIOLIB
-        select GENERIC_CLOCKEVENTS
         select PHYLIB if NETDEVICES
         help
           Say Y here if you want to run your kernel on hardware with a
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 9625cf378931..a7f959e58c3d 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1,50 +1,9 @@
-config ARCH_MSM
-        bool
-
-config ARCH_MSM_DT
-        bool "Qualcomm MSM DT Support" if ARCH_MULTI_V7
-        select ARCH_MSM
-        select ARCH_REQUIRE_GPIOLIB
-        select CLKSRC_OF
-        select GENERIC_CLOCKEVENTS
-        help
-          Support for Qualcomm's devicetree based MSM systems.
-
 if ARCH_MSM
 
-menu "Qualcomm MSM SoC Selection"
-        depends on ARCH_MSM_DT
-
-config ARCH_MSM8X60
-        bool "Enable support for MSM8X60"
-        select ARM_GIC
-        select CPU_V7
-        select HAVE_SMP
-        select MSM_SCM if SMP
-        select MSM_TIMER
-
-config ARCH_MSM8960
-        bool "Enable support for MSM8960"
-        select ARM_GIC
-        select CPU_V7
-        select HAVE_SMP
-        select MSM_SCM if SMP
-        select MSM_TIMER
-
-config ARCH_MSM8974
-        bool "Enable support for MSM8974"
-        select ARM_GIC
-        select CPU_V7
-        select HAVE_ARM_ARCH_TIMER
-        select HAVE_SMP
-        select MSM_SCM if SMP
-
-endmenu
-
 choice
         prompt "Qualcomm MSM SoC Type"
         default ARCH_MSM7X00A
-        depends on ARCH_MSM_NODT
+        depends on ARCH_MSM
 
 config ARCH_MSM7X00A
         bool "MSM7x00A / MSM7x01A"
@@ -54,7 +13,7 @@ config ARCH_MSM7X00A
         select MACH_TROUT if !MACH_HALIBUT
         select MSM_PROC_COMM
         select MSM_SMD
-        select MSM_TIMER
+        select CLKSRC_QCOM
         select MSM_SMD_PKG3
 
 config ARCH_MSM7X30
@@ -66,7 +25,7 @@ config ARCH_MSM7X30
         select MSM_GPIOMUX
         select MSM_PROC_COMM
         select MSM_SMD
-        select MSM_TIMER
+        select CLKSRC_QCOM
         select MSM_VIC
 
 config ARCH_QSD8X50
@@ -78,7 +37,7 @@ config ARCH_QSD8X50
         select MSM_GPIOMUX
         select MSM_PROC_COMM
         select MSM_SMD
-        select MSM_TIMER
+        select CLKSRC_QCOM
         select MSM_VIC
 
 endchoice
@@ -99,7 +58,7 @@ config  MSM_VIC
         bool
 
 menu "Qualcomm MSM Board Type"
-        depends on ARCH_MSM_NODT
+        depends on ARCH_MSM
 
 config MACH_HALIBUT
         depends on ARCH_MSM
@@ -153,7 +112,4 @@ config MSM_GPIOMUX
 config MSM_SCM
         bool
 
-config MSM_TIMER
-        bool
-
 endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 8e307a10d3c3..27c078a568df 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,4 +1,3 @@
-obj-$(CONFIG_MSM_TIMER) += timer.o
 obj-$(CONFIG_MSM_PROC_COMM) += clock.o
 
 obj-$(CONFIG_MSM_VIC) += irq-vic.o
@@ -14,18 +13,11 @@ obj-$(CONFIG_ARCH_QSD8X50) += dma.o io.o
 
 obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
 obj-$(CONFIG_MSM_SMD) += last_radio_log.o
-obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
-
-CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
-
-obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
-obj-$(CONFIG_SMP) += headsmp.o platsmp.o
 
 obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o
 obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o
 obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
 obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
-obj-$(CONFIG_ARCH_MSM_DT) += board-dt.o
 obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o
 obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h
index 33c7725adae2..572479a3c7be 100644
--- a/arch/arm/mach-msm/common.h
+++ b/arch/arm/mach-msm/common.h
@@ -23,9 +23,6 @@ extern void msm_map_qsd8x50_io(void);
 extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
                                           unsigned int mtype, void *caller);
 
-extern struct smp_operations msm_smp_ops;
-extern void msm_cpu_die(unsigned int cpu);
-
 struct msm_mmc_platform_data;
 
 extern void msm_add_devices(void);
diff --git a/arch/arm/mach-msm/headsmp.S b/arch/arm/mach-msm/headsmp.S
deleted file mode 100644
index 6c62c3f82fe6..000000000000
--- a/arch/arm/mach-msm/headsmp.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  linux/arch/arm/mach-realview/headsmp.S
- *
- *  Copyright (c) 2003 ARM Limited
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-
-/*
- * MSM specific entry point for secondary CPUs.  This provides
- * a "holding pen" into which all secondary cores are held until we're
- * ready for them to initialise.
- */
-ENTRY(msm_secondary_startup)
-        mrc     p15, 0, r0, c0, c0, 5
-        and     r0, r0, #15
-        adr     r4, 1f
-        ldmia   r4, {r5, r6}
-        sub     r4, r4, r5
-        add     r6, r6, r4
-pen:    ldr     r7, [r6]
-        cmp     r7, r0
-        bne     pen
-
-        /*
-         * we've been released from the holding pen: secondary_stack
-         * should now contain the SVC stack for this core
-         */
-        b       secondary_startup
-ENDPROC(msm_secondary_startup)
-
-        .align
-1:      .long   .
-        .long   pen_release
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c
deleted file mode 100644
index 326a87261f9a..000000000000
--- a/arch/arm/mach-msm/hotplug.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-
-#include <asm/smp_plat.h>
-
-#include "common.h"
-
-static inline void cpu_enter_lowpower(void)
-{
-}
-
-static inline void cpu_leave_lowpower(void)
-{
-}
-
-static inline void platform_do_lowpower(unsigned int cpu)
-{
-        /* Just enter wfi for now. TODO: Properly shut off the cpu. */
-        for (;;) {
-                /*
-                 * here's the WFI
-                 */
-                asm("wfi"
-                    :
-                    :
-                    : "memory", "cc");
-
-                if (pen_release == cpu_logical_map(cpu)) {
-                        /*
-                         * OK, proper wakeup, we're done
-                         */
-                        break;
-                }
-
-                /*
-                 * getting here, means that we have come out of WFI without
-                 * having been woken up - this shouldn't happen
-                 *
-                 * The trouble is, letting people know about this is not really
-                 * possible, since we are currently running incoherently, and
-                 * therefore cannot safely call printk() or anything else
-                 */
-                pr_debug("CPU%u: spurious wakeup call\n", cpu);
-        }
-}
-
-/*
- * platform-specific code to shutdown a CPU
- *
- * Called with IRQs disabled
- */
-void __ref msm_cpu_die(unsigned int cpu)
-{
-        /*
-         * we're ready for shutdown now, so do it
-         */
-        cpu_enter_lowpower();
-        platform_do_lowpower(cpu);
-
-        /*
-         * bring this CPU back into the world of cache
-         * coherency, and then restore interrupts
-         */
-        cpu_leave_lowpower();
-}
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
deleted file mode 100644
index f10a1f58fde9..000000000000
--- a/arch/arm/mach-msm/platsmp.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- *  Copyright (C) 2002 ARM Ltd.
- *  All Rights Reserved
- *  Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/jiffies.h>
-#include <linux/smp.h>
-#include <linux/io.h>
-
-#include <asm/cacheflush.h>
-#include <asm/cputype.h>
-#include <asm/mach-types.h>
-#include <asm/smp_plat.h>
-
-#include "scm-boot.h"
-#include "common.h"
-
-#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
-#define SCSS_CPU1CORE_RESET 0xD80
-#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
-
-extern void msm_secondary_startup(void);
-
-static DEFINE_SPINLOCK(boot_lock);
-
-static inline int get_core_count(void)
-{
-        /* 1 + the PART[1:0] field of MIDR */
-        return ((read_cpuid_id() >> 4) & 3) + 1;
-}
-
-static void msm_secondary_init(unsigned int cpu)
-{
-        /*
-         * let the primary processor know we're out of the
-         * pen, then head off into the C entry point
-         */
-        pen_release = -1;
-        smp_wmb();
-
-        /*
-         * Synchronise with the boot thread.
-         */
-        spin_lock(&boot_lock);
-        spin_unlock(&boot_lock);
-}
-
-static void prepare_cold_cpu(unsigned int cpu)
-{
-        int ret;
-        ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
-                                SCM_FLAG_COLDBOOT_CPU1);
-        if (ret == 0) {
-                void __iomem *sc1_base_ptr;
-                sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2);
-                if (sc1_base_ptr) {
-                        writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
-                        writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET);
-                        writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP);
-                        iounmap(sc1_base_ptr);
-                }
-        } else
-                printk(KERN_DEBUG "Failed to set secondary core boot "
-                                  "address\n");
-}
-
-static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
-        unsigned long timeout;
-        static int cold_boot_done;
-
-        /* Only need to bring cpu out of reset this way once */
-        if (cold_boot_done == false) {
-                prepare_cold_cpu(cpu);
-                cold_boot_done = true;
-        }
-
-        /*
-         * set synchronisation state between this boot processor
-         * and the secondary one
-         */
-        spin_lock(&boot_lock);
-
-        /*
-         * The secondary processor is waiting to be released from
-         * the holding pen - release it, then wait for it to flag
-         * that it has been released by resetting pen_release.
-         *
-         * Note that "pen_release" is the hardware CPU ID, whereas
-         * "cpu" is Linux's internal ID.
-         */
-        pen_release = cpu_logical_map(cpu);
-        sync_cache_w(&pen_release);
-
-        /*
-         * Send the secondary CPU a soft interrupt, thereby causing
-         * the boot monitor to read the system wide flags register,
-         * and branch to the address found there.
-         */
-        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
-
-        timeout = jiffies + (1 * HZ);
-        while (time_before(jiffies, timeout)) {
-                smp_rmb();
-                if (pen_release == -1)
-                        break;
-
-                udelay(10);
-        }
-
-        /*
-         * now the secondary core is starting up let it run its
-         * calibrations, then wait for it to finish
-         */
-        spin_unlock(&boot_lock);
-
-        return pen_release != -1 ? -ENOSYS : 0;
-}
-
-/*
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system. The msm8x60
- * does not support the ARM SCU, so just set the possible cpu mask to
- * NR_CPUS.
- */
-static void __init msm_smp_init_cpus(void)
-{
-        unsigned int i, ncores = get_core_count();
-
-        if (ncores > nr_cpu_ids) {
-                pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
-                        ncores, nr_cpu_ids);
-                ncores = nr_cpu_ids;
-        }
-
-        for (i = 0; i < ncores; i++)
-                set_cpu_possible(i, true);
-}
-
-static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
-{
-}
-
-struct smp_operations msm_smp_ops __initdata = {
-        .smp_init_cpus          = msm_smp_init_cpus,
-        .smp_prepare_cpus       = msm_smp_prepare_cpus,
-        .smp_secondary_init     = msm_secondary_init,
-        .smp_boot_secondary     = msm_boot_secondary,
-#ifdef CONFIG_HOTPLUG_CPU
-        .cpu_die                = msm_cpu_die,
-#endif
-};
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
deleted file mode 100644
index fd1644987534..000000000000
--- a/arch/arm/mach-msm/timer.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/*
- *
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/cpu.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/sched_clock.h>
-
-#include <asm/mach/time.h>
-
-#include "common.h"
-
-#define TIMER_MATCH_VAL                 0x0000
-#define TIMER_COUNT_VAL                 0x0004
-#define TIMER_ENABLE                    0x0008
-#define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
-#define TIMER_ENABLE_EN                 BIT(0)
-#define TIMER_CLEAR                     0x000C
-#define DGT_CLK_CTL                     0x10
-#define DGT_CLK_CTL_DIV_4               0x3
-#define TIMER_STS_GPT0_CLR_PEND         BIT(10)
-
-#define GPT_HZ 32768
-
-#define MSM_DGT_SHIFT 5
-
-static void __iomem *event_base;
-static void __iomem *sts_base;
-
-static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
-{
-        struct clock_event_device *evt = dev_id;
-        /* Stop the timer tick */
-        if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
-                u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
-                ctrl &= ~TIMER_ENABLE_EN;
-                writel_relaxed(ctrl, event_base + TIMER_ENABLE);
-        }
-        evt->event_handler(evt);
-        return IRQ_HANDLED;
-}
-
-static int msm_timer_set_next_event(unsigned long cycles,
-                                    struct clock_event_device *evt)
-{
-        u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
-
-        ctrl &= ~TIMER_ENABLE_EN;
-        writel_relaxed(ctrl, event_base + TIMER_ENABLE);
-
-        writel_relaxed(ctrl, event_base + TIMER_CLEAR);
-        writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
-
-        if (sts_base)
-                while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
-                        cpu_relax();
-
-        writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
-        return 0;
-}
-
-static void msm_timer_set_mode(enum clock_event_mode mode,
-                              struct clock_event_device *evt)
-{
-        u32 ctrl;
-
-        ctrl = readl_relaxed(event_base + TIMER_ENABLE);
-        ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_RESUME:
-        case CLOCK_EVT_MODE_PERIODIC:
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-                /* Timer is enabled in set_next_event */
-                break;
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-                break;
-        }
-        writel_relaxed(ctrl, event_base + TIMER_ENABLE);
-}
-
-static struct clock_event_device __percpu *msm_evt;
-
-static void __iomem *source_base;
-
-static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
-{
-        return readl_relaxed(source_base + TIMER_COUNT_VAL);
-}
-
-static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
-{
-        /*
-         * Shift timer count down by a constant due to unreliable lower bits
-         * on some targets.
-         */
-        return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
-}
-
-static struct clocksource msm_clocksource = {
-        .name   = "dg_timer",
-        .rating = 300,
-        .read   = msm_read_timer_count,
-        .mask   = CLOCKSOURCE_MASK(32),
-        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static int msm_timer_irq;
-static int msm_timer_has_ppi;
-
-static int msm_local_timer_setup(struct clock_event_device *evt)
-{
-        int cpu = smp_processor_id();
-        int err;
-
-        evt->irq = msm_timer_irq;
-        evt->name = "msm_timer";
-        evt->features = CLOCK_EVT_FEAT_ONESHOT;
-        evt->rating = 200;
-        evt->set_mode = msm_timer_set_mode;
-        evt->set_next_event = msm_timer_set_next_event;
-        evt->cpumask = cpumask_of(cpu);
-
-        clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
-
-        if (msm_timer_has_ppi) {
-                enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
-        } else {
-                err = request_irq(evt->irq, msm_timer_interrupt,
-                                IRQF_TIMER | IRQF_NOBALANCING |
-                                IRQF_TRIGGER_RISING, "gp_timer", evt);
-                if (err)
-                        pr_err("request_irq failed\n");
-        }
-
-        return 0;
-}
-
-static void msm_local_timer_stop(struct clock_event_device *evt)
-{
-        evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
-        disable_percpu_irq(evt->irq);
-}
-
-static int msm_timer_cpu_notify(struct notifier_block *self,
-                                           unsigned long action, void *hcpu)
-{
-        /*
-         * Grab cpu pointer in each case to avoid spurious
-         * preemptible warnings
-         */
-        switch (action & ~CPU_TASKS_FROZEN) {
-        case CPU_STARTING:
-                msm_local_timer_setup(this_cpu_ptr(msm_evt));
-                break;
-        case CPU_DYING:
-                msm_local_timer_stop(this_cpu_ptr(msm_evt));
-                break;
-        }
-
-        return NOTIFY_OK;
-}
-
-static struct notifier_block msm_timer_cpu_nb = {
-        .notifier_call = msm_timer_cpu_notify,
-};
-
-static u64 notrace msm_sched_clock_read(void)
-{
-        return msm_clocksource.read(&msm_clocksource);
-}
-
-static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
-                                  bool percpu)
-{
-        struct clocksource *cs = &msm_clocksource;
-        int res = 0;
-
-        msm_timer_irq = irq;
-        msm_timer_has_ppi = percpu;
-
-        msm_evt = alloc_percpu(struct clock_event_device);
-        if (!msm_evt) {
-                pr_err("memory allocation failed for clockevents\n");
-                goto err;
-        }
-
-        if (percpu)
-                res = request_percpu_irq(irq, msm_timer_interrupt,
-                                         "gp_timer", msm_evt);
-
-        if (res) {
-                pr_err("request_percpu_irq failed\n");
-        } else {
-                res = register_cpu_notifier(&msm_timer_cpu_nb);
-                if (res) {
-                        free_percpu_irq(irq, msm_evt);
-                        goto err;
-                }
-
-                /* Immediately configure the timer on the boot CPU */
-                msm_local_timer_setup(__this_cpu_ptr(msm_evt));
-        }
-
-err:
-        writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
-        res = clocksource_register_hz(cs, dgt_hz);
-        if (res)
-                pr_err("clocksource_register failed\n");
-        sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
-}
-
-#ifdef CONFIG_OF
-static void __init msm_dt_timer_init(struct device_node *np)
-{
-        u32 freq;
-        int irq;
-        struct resource res;
-        u32 percpu_offset;
-        void __iomem *base;
-        void __iomem *cpu0_base;
-
-        base = of_iomap(np, 0);
-        if (!base) {
-                pr_err("Failed to map event base\n");
-                return;
-        }
-
-        /* We use GPT0 for the clockevent */
-        irq = irq_of_parse_and_map(np, 1);
-        if (irq <= 0) {
-                pr_err("Can't get irq\n");
-                return;
-        }
-
-        /* We use CPU0's DGT for the clocksource */
-        if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
-                percpu_offset = 0;
-
-        if (of_address_to_resource(np, 0, &res)) {
-                pr_err("Failed to parse DGT resource\n");
-                return;
-        }
-
-        cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
-        if (!cpu0_base) {
-                pr_err("Failed to map source base\n");
-                return;
-        }
-
-        if (of_property_read_u32(np, "clock-frequency", &freq)) {
-                pr_err("Unknown frequency\n");
-                return;
-        }
-
-        event_base = base + 0x4;
-        sts_base = base + 0x88;
-        source_base = cpu0_base + 0x24;
-        freq /= 4;
-        writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
-
-        msm_timer_init(freq, 32, irq, !!percpu_offset);
-}
-CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
-CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
-#endif
-
-static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
-                                u32 sts)
-{
-        void __iomem *base;
-
-        base = ioremap(addr, SZ_256);
-        if (!base) {
-                pr_err("Failed to map timer base\n");
-                return -ENOMEM;
-        }
-        event_base = base + event;
-        source_base = base + source;
-        if (sts)
-                sts_base = base + sts;
-
-        return 0;
-}
-
-void __init msm7x01_timer_init(void)
-{
-        struct clocksource *cs = &msm_clocksource;
-
-        if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
-                return;
-        cs->read = msm_read_timer_count_shift;
-        cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
-        /* 600 KHz */
-        msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
-                        false);
-}
-
-void __init msm7x30_timer_init(void)
-{
-        if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
-                return;
-        msm_timer_init(24576000 / 4, 32, 1, false);
-}
-
-void __init qsd8x50_timer_init(void)
-{
-        if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
-                return;
-        msm_timer_init(19200000 / 4, 32, 7, false);
-}
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 75062eff2494..e6ac679bece9 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -15,11 +15,11 @@
 #include <linux/ata_platform.h>
 #include <linux/clk-provider.h>
 #include <linux/ethtool.h>
+#include <asm/hardware/cache-feroceon-l2.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <mach/mv78xx0.h>
 #include <mach/bridge-regs.h>
-#include <plat/cache-feroceon-l2.h>
 #include <linux/platform_data/usb-ehci-orion.h>
 #include <linux/platform_data/mtd-orion_nand.h>
 #include <plat/time.h>
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 5e269d7263ce..485513cb98c4 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -1,16 +1,11 @@
 config ARCH_MVEBU
-        bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7
+        bool "Marvell Engineering Business Unit (MVEBU) SoCs" if (ARCH_MULTI_V7 || ARCH_MULTI_V5)
         select ARCH_SUPPORTS_BIG_ENDIAN
         select CLKSRC_MMIO
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
         select GENERIC_IRQ_CHIP
         select IRQ_DOMAIN
-        select MULTI_IRQ_HANDLER
         select PINCTRL
         select PLAT_ORION
-        select SPARSE_IRQ
-        select CLKDEV_LOOKUP
         select MVEBU_MBUS
         select ZONE_DMA if ARM_LPAE
         select ARCH_REQUIRE_GPIOLIB
@@ -19,33 +14,97 @@ config ARCH_MVEBU
 
 if ARCH_MVEBU
 
-menu "Marvell SOC with device tree"
+menu "Marvell EBU SoC variants"
 
-config MACH_ARMADA_370_XP
+config MACH_MVEBU_V7
         bool
         select ARMADA_370_XP_TIMER
-        select HAVE_SMP
         select CACHE_L2X0
-        select CPU_PJ4B
 
 config MACH_ARMADA_370
-        bool "Marvell Armada 370 boards"
+        bool "Marvell Armada 370 boards" if ARCH_MULTI_V7
         select ARMADA_370_CLK
-        select MACH_ARMADA_370_XP
+        select CPU_PJ4B
+        select MACH_MVEBU_V7
         select PINCTRL_ARMADA_370
         help
           Say 'Y' here if you want your kernel to support boards based
           on the Marvell Armada 370 SoC with device tree.
 
+config MACH_ARMADA_375
+        bool "Marvell Armada 375 boards" if ARCH_MULTI_V7
+        select ARM_ERRATA_720789
+        select ARM_ERRATA_753970
+        select ARM_GIC
+        select ARMADA_375_CLK
+        select CPU_V7
+        select MACH_MVEBU_V7
+        select NEON
+        select PINCTRL_ARMADA_375
+        help
+          Say 'Y' here if you want your kernel to support boards based
+          on the Marvell Armada 375 SoC with device tree.
+
+config MACH_ARMADA_38X
+        bool "Marvell Armada 380/385 boards" if ARCH_MULTI_V7
+        select ARM_ERRATA_720789
+        select ARM_ERRATA_753970
+        select ARM_GIC
+        select ARMADA_38X_CLK
+        select CPU_V7
+        select MACH_MVEBU_V7
+        select NEON
+        select PINCTRL_ARMADA_38X
+        help
+          Say 'Y' here if you want your kernel to support boards based
+          on the Marvell Armada 380/385 SoC with device tree.
+
 config MACH_ARMADA_XP
-        bool "Marvell Armada XP boards"
+        bool "Marvell Armada XP boards" if ARCH_MULTI_V7
         select ARMADA_XP_CLK
-        select MACH_ARMADA_370_XP
+        select CPU_PJ4B
+        select MACH_MVEBU_V7
         select PINCTRL_ARMADA_XP
         help
           Say 'Y' here if you want your kernel to support boards based
           on the Marvell Armada XP SoC with device tree.
 
+config MACH_DOVE
+        bool "Marvell Dove boards" if ARCH_MULTI_V7
+        select CACHE_L2X0
+        select CPU_PJ4
+        select DOVE_CLK
+        select ORION_IRQCHIP
+        select ORION_TIMER
+        select PINCTRL_DOVE
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell Dove using flattened device tree.
+
+config MACH_KIRKWOOD
+        bool "Marvell Kirkwood boards" if ARCH_MULTI_V5
+        select ARCH_HAS_CPUFREQ
+        select ARCH_REQUIRE_GPIOLIB
+        select CPU_FEROCEON
+        select KIRKWOOD_CLK
+        select OF_IRQ
+        select ORION_IRQCHIP
+        select ORION_TIMER
+        select PCI
+        select PCI_QUIRKS
+        select PINCTRL_KIRKWOOD
+        select USE_OF
+        help
+          Say 'Y' here if you want your kernel to support boards based
+          on the Marvell Kirkwood device tree.
+
+config MACH_T5325
+        bool "HP T5325 thin client"
+        depends on MACH_KIRKWOOD
+        help
+          Say 'Y' here if you want your kernel to support the
+          HP T5325 Thin client
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 878aebe98dcc..a63e43b6b451 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -4,7 +4,10 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
 AFLAGS_coherency_ll.o           := -Wa,-march=armv7-a
 
 obj-y                            += system-controller.o mvebu-soc-id.o
-obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o
+obj-$(CONFIG_MACH_MVEBU_V7)      += board-v7.o
+obj-$(CONFIG_MACH_DOVE)          += dove.o
 obj-$(CONFIG_ARCH_MVEBU)         += coherency.o coherency_ll.o pmsu.o
 obj-$(CONFIG_SMP)                += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)        += hotplug.o
+obj-$(CONFIG_MACH_KIRKWOOD)      += kirkwood.o kirkwood-pm.o
+obj-$(CONFIG_MACH_T5325)         += board-t5325.o
diff --git a/arch/arm/mach-mvebu/board-t5325.c b/arch/arm/mach-mvebu/board-t5325.c
new file mode 100644
index 000000000000..65ace6db9f28
--- /dev/null
+++ b/arch/arm/mach-mvebu/board-t5325.c
@@ -0,0 +1,41 @@
+/*
+ * HP T5325 Board Setup
+ *
+ * Copyright (C) 2014
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <sound/alc5623.h>
+#include "board.h"
+
+static struct platform_device hp_t5325_audio_device = {
+        .name           = "t5325-audio",
+        .id             = -1,
+};
+
+static struct alc5623_platform_data alc5621_data = {
+        .add_ctrl = 0x3700,
+        .jack_det_ctrl = 0x4810,
+};
+
+static struct i2c_board_info i2c_board_info[] __initdata = {
+        {
+                I2C_BOARD_INFO("alc5621", 0x1a),
+                .platform_data = &alc5621_data,
+        },
+};
+
+void __init t5325_init(void)
+{
+        i2c_register_board_info(0, i2c_board_info, ARRAY_SIZE(i2c_board_info));
+        platform_device_register(&hp_t5325_audio_device);
+}
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/board-v7.c
index f6c9d1d85c14..746134ecdfc2 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -31,12 +31,28 @@
 #include "coherency.h"
 #include "mvebu-soc-id.h"
 
-static void __init armada_370_xp_map_io(void)
+/*
+ * Early versions of Armada 375 SoC have a bug where the BootROM
+ * leaves an external data abort pending. The kernel is hit by this
+ * data abort as soon as it enters userspace, because it unmasks the
+ * data aborts at this moment. We register a custom abort handler
+ * below to ignore the first data abort to work around this
+ * problem.
+ */
+static int armada_375_external_abort_wa(unsigned long addr, unsigned int fsr,
+                                        struct pt_regs *regs)
 {
-        debug_ll_io_init();
+        static int ignore_first;
+
+        if (!ignore_first && fsr == 0x1406) {
+                ignore_first = 1;
+                return 0;
+        }
+
+        return 1;
 }
 
-static void __init armada_370_xp_timer_and_clk_init(void)
+static void __init mvebu_timer_and_clk_init(void)
 {
         of_clk_init(NULL);
         clocksource_of_init();
@@ -45,6 +61,10 @@ static void __init armada_370_xp_timer_and_clk_init(void)
 #ifdef CONFIG_CACHE_L2X0
         l2x0_of_init(0, ~0UL);
 #endif
+
+        if (of_machine_is_compatible("marvell,armada375"))
+                hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0,
+                                "imprecise external abort");
 }
 
 static void __init i2c_quirk(void)
@@ -75,7 +95,7 @@ static void __init i2c_quirk(void)
         return;
 }
 
-static void __init armada_370_xp_dt_init(void)
+static void __init mvebu_dt_init(void)
 {
         if (of_machine_is_compatible("plathome,openblocks-ax3-4"))
                 i2c_quirk();
@@ -87,11 +107,33 @@ static const char * const armada_370_xp_dt_compat[] = {
         NULL,
 };
 
-DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)")
+DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
         .smp            = smp_ops(armada_xp_smp_ops),
-        .init_machine   = armada_370_xp_dt_init,
-        .map_io         = armada_370_xp_map_io,
-        .init_time      = armada_370_xp_timer_and_clk_init,
+        .init_machine   = mvebu_dt_init,
+        .init_time      = mvebu_timer_and_clk_init,
         .restart        = mvebu_restart,
         .dt_compat      = armada_370_xp_dt_compat,
 MACHINE_END
+
+static const char * const armada_375_dt_compat[] = {
+        "marvell,armada375",
+        NULL,
+};
+
+DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
+        .init_time      = mvebu_timer_and_clk_init,
+        .restart        = mvebu_restart,
+        .dt_compat      = armada_375_dt_compat,
+MACHINE_END
+
+static const char * const armada_38x_dt_compat[] = {
+        "marvell,armada380",
+        "marvell,armada385",
+        NULL,
+};
+
+DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
+        .init_time      = mvebu_timer_and_clk_init,
+        .restart        = mvebu_restart,
+        .dt_compat      = armada_38x_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-mvebu/board.h b/arch/arm/mach-mvebu/board.h
new file mode 100644
index 000000000000..de7f0a191394
--- /dev/null
+++ b/arch/arm/mach-mvebu/board.h
@@ -0,0 +1,22 @@
+/*
+ * Board functions for Marvell System On Chip
+ *
+ * Copyright (C) 2014
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARCH_MVEBU_BOARD_H
+#define __ARCH_MVEBU_BOARD_H
+
+#ifdef CONFIG_MACH_T5325
+void t5325_init(void);
+#else
+static inline void t5325_init(void) {};
+#endif
+
+#endif
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-mvebu/dove.c
index 49fa9abd09da..5e5a43624237 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-dove/board-dt.c
+ * arch/arm/mach-mvebu/dove.c
  *
  * Marvell Dove 88AP510 System On Chip FDT Board
  *
@@ -9,17 +9,14 @@
  */
 
 #include <linux/init.h>
-#include <linux/clk-provider.h>
+#include <linux/mbus.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <asm/hardware/cache-tauros2.h>
 #include <asm/mach/arch.h>
-#include <mach/dove.h>
-#include <mach/pm.h>
-#include <plat/common.h>
 #include "common.h"
 
-static void __init dove_dt_init(void)
+static void __init dove_init(void)
 {
         pr_info("Dove 88AP510 SoC\n");
 
@@ -30,14 +27,13 @@ static void __init dove_dt_init(void)
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static const char * const dove_dt_board_compat[] = {
+static const char * const dove_dt_compat[] = {
         "marvell,dove",
         NULL
 };
 
-DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
-        .map_io         = dove_map_io,
-        .init_machine   = dove_dt_init,
-        .restart        = dove_restart,
-        .dt_compat      = dove_dt_board_compat,
+DT_MACHINE_START(DOVE_DT, "Marvell Dove")
+        .init_machine   = dove_init,
+        .restart        = mvebu_restart,
+        .dt_compat      = dove_dt_compat,
 MACHINE_END
diff --git a/arch/arm/mach-mvebu/kirkwood-pm.c b/arch/arm/mach-mvebu/kirkwood-pm.c
new file mode 100644
index 000000000000..cbb816f2120c
--- /dev/null
+++ b/arch/arm/mach-mvebu/kirkwood-pm.c
@@ -0,0 +1,76 @@
+/*
+ * Power Management driver for Marvell Kirkwood SoCs
+ *
+ * Copyright (C) 2013 Ezequiel Garcia <ezequiel@free-electrons.com>
+ * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License,
+ * version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/io.h>
+#include "kirkwood.h"
+
+static void __iomem *ddr_operation_base;
+static void __iomem *memory_pm_ctrl;
+
+static void kirkwood_low_power(void)
+{
+        u32 mem_pm_ctrl;
+
+        mem_pm_ctrl = readl(memory_pm_ctrl);
+
+        /* Set peripherals to low-power mode */
+        writel_relaxed(~0, memory_pm_ctrl);
+
+        /* Set DDR in self-refresh */
+        writel_relaxed(0x7, ddr_operation_base);
+
+        /*
+         * Set CPU in wait-for-interrupt state.
+         * This disables the CPU core clocks,
+         * the array clocks, and also the L2 controller.
+         */
+        cpu_do_idle();
+
+        writel_relaxed(mem_pm_ctrl, memory_pm_ctrl);
+}
+
+static int kirkwood_suspend_enter(suspend_state_t state)
+{
+        switch (state) {
+        case PM_SUSPEND_STANDBY:
+                kirkwood_low_power();
+                break;
+        default:
+                return -EINVAL;
+        }
+        return 0;
+}
+
+static int kirkwood_pm_valid_standby(suspend_state_t state)
+{
+        return state == PM_SUSPEND_STANDBY;
+}
+
+static const struct platform_suspend_ops kirkwood_suspend_ops = {
+        .enter = kirkwood_suspend_enter,
+        .valid = kirkwood_pm_valid_standby,
+};
+
+int __init kirkwood_pm_init(void)
+{
+        ddr_operation_base = ioremap(DDR_OPERATION_BASE, 4);
+        memory_pm_ctrl = ioremap(MEMORY_PM_CTRL_PHYS, 4);
+
+        suspend_set_ops(&kirkwood_suspend_ops);
+        return 0;
+}
diff --git a/arch/arm/mach-mvebu/kirkwood-pm.h b/arch/arm/mach-mvebu/kirkwood-pm.h
new file mode 100644
index 000000000000..21e7530f368b
--- /dev/null
+++ b/arch/arm/mach-mvebu/kirkwood-pm.h
@@ -0,0 +1,26 @@
+/*
+ * Power Management driver for Marvell Kirkwood SoCs
+ *
+ * Copyright (C) 2013 Ezequiel Garcia <ezequiel@free-electrons.com>
+ * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License,
+ * version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_KIRKWOOD_PM_H
+#define __ARCH_KIRKWOOD_PM_H
+
+#ifdef CONFIG_PM
+void kirkwood_pm_init(void);
+#else
+static inline void kirkwood_pm_init(void) {};
+#endif
+
+#endif
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
new file mode 100644
index 000000000000..120207fc36f1
--- /dev/null
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net>
+ *
+ * arch/arm/mach-mvebu/kirkwood.c
+ *
+ * Flattened Device Tree board initialization
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_net.h>
+#include <linux/of_platform.h>
+#include <linux/slab.h>
+#include <asm/hardware/cache-feroceon-l2.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include "kirkwood.h"
+#include "kirkwood-pm.h"
+#include "common.h"
+#include "board.h"
+
+static struct resource kirkwood_cpufreq_resources[] = {
+        [0] = {
+                .start  = CPU_CONTROL_PHYS,
+                .end    = CPU_CONTROL_PHYS + 3,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device kirkwood_cpufreq_device = {
+        .name           = "kirkwood-cpufreq",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(kirkwood_cpufreq_resources),
+        .resource       = kirkwood_cpufreq_resources,
+};
+
+static void __init kirkwood_cpufreq_init(void)
+{
+        platform_device_register(&kirkwood_cpufreq_device);
+}
+
+static struct resource kirkwood_cpuidle_resource[] = {
+        {
+                .flags  = IORESOURCE_MEM,
+                .start  = DDR_OPERATION_BASE,
+                .end    = DDR_OPERATION_BASE + 3,
+        },
+};
+
+static struct platform_device kirkwood_cpuidle = {
+        .name           = "kirkwood_cpuidle",
+        .id             = -1,
+        .resource       = kirkwood_cpuidle_resource,
+        .num_resources  = 1,
+};
+
+static void __init kirkwood_cpuidle_init(void)
+{
+        platform_device_register(&kirkwood_cpuidle);
+}
+
+#define MV643XX_ETH_MAC_ADDR_LOW        0x0414
+#define MV643XX_ETH_MAC_ADDR_HIGH       0x0418
+
+static void __init kirkwood_dt_eth_fixup(void)
+{
+        struct device_node *np;
+
+        /*
+         * The ethernet interfaces forget the MAC address assigned by u-boot
+         * if the clocks are turned off. Usually, u-boot on kirkwood boards
+         * has no DT support to properly set local-mac-address property.
+         * As a workaround, we get the MAC address from mv643xx_eth registers
+         * and update the port device node if no valid MAC address is set.
+         */
+        for_each_compatible_node(np, NULL, "marvell,kirkwood-eth-port") {
+                struct device_node *pnp = of_get_parent(np);
+                struct clk *clk;
+                struct property *pmac;
+                void __iomem *io;
+                u8 *macaddr;
+                u32 reg;
+
+                if (!pnp)
+                        continue;
+
+                /* skip disabled nodes or nodes with valid MAC address*/
+                if (!of_device_is_available(pnp) || of_get_mac_address(np))
+                        goto eth_fixup_skip;
+
+                clk = of_clk_get(pnp, 0);
+                if (IS_ERR(clk))
+                        goto eth_fixup_skip;
+
+                io = of_iomap(pnp, 0);
+                if (!io)
+                        goto eth_fixup_no_map;
+
+                /* ensure port clock is not gated to not hang CPU */
+                clk_prepare_enable(clk);
+
+                /* store MAC address register contents in local-mac-address */
+                pr_err(FW_INFO "%s: local-mac-address is not set\n",
+                       np->full_name);
+
+                pmac = kzalloc(sizeof(*pmac) + 6, GFP_KERNEL);
+                if (!pmac)
+                        goto eth_fixup_no_mem;
+
+                pmac->value = pmac + 1;
+                pmac->length = 6;
+                pmac->name = kstrdup("local-mac-address", GFP_KERNEL);
+                if (!pmac->name) {
+                        kfree(pmac);
+                        goto eth_fixup_no_mem;
+                }
+
+                macaddr = pmac->value;
+                reg = readl(io + MV643XX_ETH_MAC_ADDR_HIGH);
+                macaddr[0] = (reg >> 24) & 0xff;
+                macaddr[1] = (reg >> 16) & 0xff;
+                macaddr[2] = (reg >> 8) & 0xff;
+                macaddr[3] = reg & 0xff;
+
+                reg = readl(io + MV643XX_ETH_MAC_ADDR_LOW);
+                macaddr[4] = (reg >> 8) & 0xff;
+                macaddr[5] = reg & 0xff;
+
+                of_update_property(np, pmac);
+
+eth_fixup_no_mem:
+                iounmap(io);
+                clk_disable_unprepare(clk);
+eth_fixup_no_map:
+                clk_put(clk);
+eth_fixup_skip:
+                of_node_put(pnp);
+        }
+}
+
+/*
+ * Disable propagation of mbus errors to the CPU local bus, as this
+ * causes mbus errors (which can occur for example for PCI aborts) to
+ * throw CPU aborts, which we're not set up to deal with.
+ */
+void kirkwood_disable_mbus_error_propagation(void)
+{
+        void __iomem *cpu_config;
+
+        cpu_config = ioremap(CPU_CONFIG_PHYS, 4);
+        writel(readl(cpu_config) & ~CPU_CONFIG_ERROR_PROP, cpu_config);
+}
+
+static struct of_dev_auxdata auxdata[] __initdata = {
+        OF_DEV_AUXDATA("marvell,kirkwood-audio", 0xf10a0000,
+                       "mvebu-audio", NULL),
+        { /* sentinel */ }
+};
+
+static void __init kirkwood_dt_init(void)
+{
+        kirkwood_disable_mbus_error_propagation();
+
+        BUG_ON(mvebu_mbus_dt_init());
+
+#ifdef CONFIG_CACHE_FEROCEON_L2
+        feroceon_of_init();
+#endif
+        kirkwood_cpufreq_init();
+        kirkwood_cpuidle_init();
+
+        kirkwood_pm_init();
+        kirkwood_dt_eth_fixup();
+
+        if (of_machine_is_compatible("hp,t5325"))
+                t5325_init();
+
+        of_platform_populate(NULL, of_default_bus_match_table, auxdata, NULL);
+}
+
+static const char * const kirkwood_dt_board_compat[] = {
+        "marvell,kirkwood",
+        NULL
+};
+
+DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)")
+        /* Maintainer: Jason Cooper <jason@lakedaemon.net> */
+        .init_machine   = kirkwood_dt_init,
+        .restart        = mvebu_restart,
+        .dt_compat      = kirkwood_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-mvebu/kirkwood.h b/arch/arm/mach-mvebu/kirkwood.h
new file mode 100644
index 000000000000..89f3d1f51643
--- /dev/null
+++ b/arch/arm/mach-mvebu/kirkwood.h
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-mvebu/kirkwood.h
+ *
+ * Generic definitions for Marvell Kirkwood SoC flavors:
+ * 88F6180, 88F6192 and 88F6281.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
+#define DDR_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE + 0x00000)
+#define BRIDGE_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
+
+#define DDR_OPERATION_BASE      (DDR_PHYS_BASE + 0x1418)
+
+#define CPU_CONFIG_PHYS         (BRIDGE_PHYS_BASE + 0x0100)
+#define CPU_CONFIG_ERROR_PROP   0x00000004
+
+#define CPU_CONTROL_PHYS        (BRIDGE_PHYS_BASE + 0x0104)
+#define MEMORY_PM_CTRL_PHYS     (BRIDGE_PHYS_BASE + 0x0118)
diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c
index f3b325f6cbd4..f3d4cf53f746 100644
--- a/arch/arm/mach-mvebu/mvebu-soc-id.c
+++ b/arch/arm/mach-mvebu/mvebu-soc-id.c
@@ -38,6 +38,7 @@ static bool is_id_valid;
 static const struct of_device_id mvebu_pcie_of_match_table[] = {
         { .compatible = "marvell,armada-xp-pcie", },
         { .compatible = "marvell,armada-370-pcie", },
+        { .compatible = "marvell,kirkwood-pcie" },
         {},
 };
 
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index a7fb89a5b5d9..614ba6832ff3 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -1,5 +1,5 @@
 /*
- * System controller support for Armada 370 and XP platforms.
+ * System controller support for Armada 370, 375 and XP platforms.
  *
  * Copyright (C) 2012 Marvell
  *
@@ -11,7 +11,7 @@
  * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  *
- * The Armada 370 and Armada XP SoCs both have a range of
+ * The Armada 370, 375 and Armada XP SoCs have a range of
  * miscellaneous registers, that do not belong to a particular device,
  * but rather provide system-level features. This basic
  * system-controller driver provides a device tree binding for those
@@ -47,6 +47,13 @@ static const struct mvebu_system_controller armada_370_xp_system_controller = {
         .system_soft_reset = 0x1,
 };
 
+static const struct mvebu_system_controller armada_375_system_controller = {
+        .rstoutn_mask_offset = 0x54,
+        .system_soft_reset_offset = 0x58,
+        .rstoutn_mask_reset_out_en = 0x1,
+        .system_soft_reset = 0x1,
+};
+
 static const struct mvebu_system_controller orion_system_controller = {
         .rstoutn_mask_offset = 0x108,
         .system_soft_reset_offset = 0x10c,
@@ -54,13 +61,16 @@ static const struct mvebu_system_controller orion_system_controller = {
         .system_soft_reset = 0x1,
 };
 
-static struct of_device_id of_system_controller_table[] = {
+static const struct of_device_id of_system_controller_table[] = {
         {
                 .compatible = "marvell,orion-system-controller",
                 .data = (void *) &orion_system_controller,
         }, {
                 .compatible = "marvell,armada-370-xp-system-controller",
                 .data = (void *) &armada_370_xp_system_controller,
+        }, {
+                .compatible = "marvell,armada-375-system-controller",
+                .data = (void *) &armada_375_system_controller,
         },
         { /* end of list */ },
 };
@@ -90,13 +100,12 @@ void mvebu_restart(enum reboot_mode mode, const char *cmd)
 
 static int __init mvebu_system_controller_init(void)
 {
+        const struct of_device_id *match;
         struct device_node *np;
 
-        np = of_find_matching_node(NULL, of_system_controller_table);
+        np = of_find_matching_node_and_match(NULL, of_system_controller_table,
+                                             &match);
         if (np) {
-                const struct of_device_id *match =
-                    of_match_node(of_system_controller_table, np);
-                BUG_ON(!match);
                 system_controller_base = of_iomap(np, 0);
                 mvebu_sc = (struct mvebu_system_controller *)match->data;
                 of_node_put(np);
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 8cde9e05b5d6..84794137b175 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -16,11 +16,7 @@ config ARCH_MXS
         bool "Freescale MXS (i.MX23, i.MX28) support"
         depends on ARCH_MULTI_V5
         select ARCH_REQUIRE_GPIOLIB
-        select CLKDEV_LOOKUP
         select CLKSRC_MMIO
-        select CLKSRC_OF
-        select GENERIC_CLOCKEVENTS
-        select HAVE_CLK_PREPARE
         select PINCTRL
         select SOC_BUS
         select SOC_IMX23
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 4d42da49753c..486d301f43fd 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -6,16 +6,11 @@ config ARCH_NOMADIK
         select ARM_VIC
         select CLKSRC_NOMADIK_MTU
         select CLKSRC_NOMADIK_MTU_SCHED_CLOCK
-        select CLKSRC_OF
-        select COMMON_CLK
         select CPU_ARM926T
-        select GENERIC_CLOCKEVENTS
         select MIGHT_HAVE_CACHE_L2X0
         select PINCTRL
         select PINCTRL_NOMADIK
         select PINCTRL_STN8815
-        select SPARSE_IRQ
-        select USE_OF
         help
           Support for the Nomadik platform by ST-Ericsson
 
diff --git a/arch/arm/mach-nspire/Kconfig b/arch/arm/mach-nspire/Kconfig
index 59d8f0a70919..bc41f26c1a12 100644
--- a/arch/arm/mach-nspire/Kconfig
+++ b/arch/arm/mach-nspire/Kconfig
@@ -3,14 +3,9 @@ config ARCH_NSPIRE
         depends on ARCH_MULTI_V4_V5
         depends on MMU
         select CPU_ARM926T
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
         select GENERIC_IRQ_CHIP
-        select SPARSE_IRQ
         select ARM_AMBA
         select ARM_VIC
         select ARM_TIMER_SP804
-        select USE_OF
-        select CLKSRC_OF
         help
           This enables support for systems using the TI-NSPIRE CPU
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 91449c5cb70f..85089d821982 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -156,6 +156,7 @@ static struct omap_usb_config nokia770_usb_config __initdata = {
         .register_dev   = 1,
         .hmc_mode       = 16,
         .pins[0]        = 6,
+        .extcon         = "tahvo-usb",
 };
 
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 653b489479e0..e55ae63bb030 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -6,7 +6,6 @@ config ARCH_OMAP2
         depends on ARCH_MULTI_V6
         select ARCH_OMAP2PLUS
         select CPU_V6
-        select MULTI_IRQ_HANDLER
         select SOC_HAS_OMAP2_SDRC
 
 config ARCH_OMAP3
@@ -15,8 +14,6 @@ config ARCH_OMAP3
         select ARCH_OMAP2PLUS
         select ARCH_HAS_OPP
         select ARM_CPU_SUSPEND if PM
-        select CPU_V7
-        select MULTI_IRQ_HANDLER
         select OMAP_INTERCONNECT
         select PM_OPP if PM
         select PM_RUNTIME if CPU_IDLE
@@ -33,10 +30,8 @@ config ARCH_OMAP4
         select ARM_ERRATA_720789
         select ARM_GIC
         select CACHE_L2X0
-        select CPU_V7
         select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
         select OMAP_INTERCONNECT
         select PL310_ERRATA_588369
         select PL310_ERRATA_727915
@@ -50,12 +45,11 @@ config SOC_OMAP5
         bool "TI OMAP5"
         depends on ARCH_MULTI_V7
         select ARCH_OMAP2PLUS
+        select ARCH_HAS_OPP
         select ARM_CPU_SUSPEND if PM
         select ARM_GIC
-        select CPU_V7
         select HAVE_ARM_SCU if SMP
-        select HAVE_ARM_TWD if LOCAL_TIMERS
-        select HAVE_SMP
+        select HAVE_ARM_TWD if SMP
         select HAVE_ARM_ARCH_TIMER
         select ARM_ERRATA_798181 if SMP
 
@@ -63,16 +57,14 @@ config SOC_AM33XX
         bool "TI AM33XX"
         depends on ARCH_MULTI_V7
         select ARCH_OMAP2PLUS
+        select ARCH_HAS_OPP
         select ARM_CPU_SUSPEND if PM
-        select CPU_V7
-        select MULTI_IRQ_HANDLER
 
 config SOC_AM43XX
         bool "TI AM43x"
         depends on ARCH_MULTI_V7
-        select CPU_V7
         select ARCH_OMAP2PLUS
-        select MULTI_IRQ_HANDLER
+        select ARCH_HAS_OPP
         select ARM_GIC
         select MACH_OMAP_GENERIC
 
@@ -80,10 +72,9 @@ config SOC_DRA7XX
         bool "TI DRA7XX"
         depends on ARCH_MULTI_V7
         select ARCH_OMAP2PLUS
+        select ARCH_HAS_OPP
         select ARM_CPU_SUSPEND if PM
         select ARM_GIC
-        select CPU_V7
-        select HAVE_SMP
         select HAVE_ARM_ARCH_TIMER
 
 config ARCH_OMAP2PLUS
@@ -94,17 +85,13 @@ config ARCH_OMAP2PLUS
         select ARCH_OMAP
         select ARCH_REQUIRE_GPIOLIB
         select CLKSRC_MMIO
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
         select GENERIC_IRQ_CHIP
         select MACH_OMAP_GENERIC
         select OMAP_DM_TIMER
         select PINCTRL
         select PROC_DEVICETREE if PROC_FS
         select SOC_BUS
-        select SPARSE_IRQ
         select TI_PRIV_EDMA
-        select USE_OF
         help
           Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
 
@@ -165,12 +152,6 @@ config SOC_TI81XX
         depends on ARCH_OMAP3
         default y
 
-config OMAP_PACKAGE_ZAF
-       bool
-
-config OMAP_PACKAGE_ZAC
-       bool
-
 config OMAP_PACKAGE_CBC
        bool
 
@@ -268,9 +249,6 @@ config MACH_OMAP_3430SDP
         default y
         select OMAP_PACKAGE_CBB
 
-config MACH_NOKIA_N800
-       bool
-
 config MACH_NOKIA_N810
        bool
 
@@ -281,10 +259,8 @@ config MACH_NOKIA_N8X0
         bool "Nokia N800/N810"
         depends on SOC_OMAP2420
         default y
-        select MACH_NOKIA_N800
         select MACH_NOKIA_N810
         select MACH_NOKIA_N810_WIMAX
-        select OMAP_PACKAGE_ZAC
 
 config MACH_NOKIA_RX51
         bool "Nokia N900 (RX-51) phone"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index e6eec6f72fd3..8421f38cf445 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -60,6 +60,7 @@ AFLAGS_sram34xx.o			:=-Wa,-march=armv7-a
 obj-$(CONFIG_SOC_OMAP2420)              += omap2-restart.o
 obj-$(CONFIG_SOC_OMAP2430)              += omap2-restart.o
 obj-$(CONFIG_SOC_AM33XX)                += am33xx-restart.o
+obj-$(CONFIG_SOC_AM43XX)                += omap4-restart.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap3-restart.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap4-restart.o
 obj-$(CONFIG_SOC_OMAP5)                 += omap4-restart.o
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 8e3daa11602b..bc6013fbb773 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -229,8 +229,9 @@ DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
         .init_late      = am43xx_init_late,
         .init_irq       = omap_gic_of_init,
         .init_machine   = omap_generic_init,
-        .init_time      = omap3_sync32k_timer_init,
+        .init_time      = omap3_gptimer_timer_init,
         .dt_compat      = am43_boards_compat,
+        .restart        = omap44xx_restart,
 MACHINE_END
 #endif
 
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 47f9562ca7aa..2649ce445845 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -306,7 +306,7 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
 
         ref_rate = __clk_get_rate(dd->clk_ref);
         clk_name = __clk_get_name(hw->clk);
-        pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
+        pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
                  clk_name, target_rate);
 
         scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
@@ -342,7 +342,7 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
                 if (r == DPLL_MULT_UNDERFLOW)
                         continue;
 
-                pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
+                pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n",
                          clk_name, m, n, new_rate);
 
                 if (target_rate == new_rate) {
@@ -354,7 +354,7 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
         }
 
         if (target_rate != new_rate) {
-                pr_debug("clock: %s: cannot round to rate %ld\n",
+                pr_debug("clock: %s: cannot round to rate %lu\n",
                          clk_name, target_rate);
                 return ~0;
         }
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 731ca134348c..f5c4731b6f06 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -254,6 +254,11 @@ void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs)
  *
  */
 
+void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs)
+{
+        _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
+}
+
 /**
  * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state
  * @part: PRCM partition ID that the CM_CLKCTRL register exists in
@@ -404,8 +409,17 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
 
 static int omap4_clkdm_sleep(struct clockdomain *clkdm)
 {
-        omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
-                                        clkdm->cm_inst, clkdm->clkdm_offs);
+        if (clkdm->flags & CLKDM_CAN_HWSUP)
+                omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
+                                                clkdm->cm_inst,
+                                                clkdm->clkdm_offs);
+        else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
+                omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
+                                               clkdm->cm_inst,
+                                               clkdm->clkdm_offs);
+        else
+                return -EINVAL;
+
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 3185ced807c9..d9bcbf7641b5 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -525,7 +525,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
         * stuff is inherited for free
         */
 
-        if (!ret)
+        if (!ret && clk_get_parent(hw->clk) != new_parent)
                 __clk_reparent(hw->clk, new_parent);
 
         return 0;
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index d24926e6340f..ab43755364f5 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1339,7 +1339,7 @@ static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
                 of_property_read_bool(np, "gpmc,time-para-granularity");
 }
 
-#ifdef CONFIG_MTD_NAND
+#if IS_ENABLED(CONFIG_MTD_NAND)
 
 static const char * const nand_xfer_types[] = {
         [NAND_OMAP_PREFETCH_POLLED]             = "prefetch-polled",
@@ -1429,7 +1429,7 @@ static int gpmc_probe_nand_child(struct platform_device *pdev,
 }
 #endif
 
-#ifdef CONFIG_MTD_ONENAND
+#if IS_ENABLED(CONFIG_MTD_ONENAND)
 static int gpmc_probe_onenand_child(struct platform_device *pdev,
                                  struct device_node *child)
 {
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 9428c5f9d4f2..157412e4273a 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -465,8 +465,18 @@ void __init omap3xxx_check_revision(void)
                 }
                 break;
         case 0xb98c:
-                omap_revision = AM437X_REV_ES1_0;
-                cpu_rev = "1.0";
+                switch (rev) {
+                case 0:
+                        omap_revision = AM437X_REV_ES1_0;
+                        cpu_rev = "1.0";
+                        break;
+                case 1:
+                /* FALLTHROUGH */
+                default:
+                        omap_revision = AM437X_REV_ES1_1;
+                        cpu_rev = "1.1";
+                        break;
+                }
                 break;
         case 0xb8f2:
                 switch (rev) {
@@ -657,6 +667,8 @@ static const char * __init omap_get_family(void)
                 return kasprintf(GFP_KERNEL, "OMAP4");
         else if (soc_is_omap54xx())
                 return kasprintf(GFP_KERNEL, "OMAP5");
+        else if (soc_is_am43xx())
+                return kasprintf(GFP_KERNEL, "AM43xx");
         else
                 return kasprintf(GFP_KERNEL, "Unknown");
 }
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index d408b15b4fbf..f14f9ac2dca1 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -179,15 +179,6 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
                 .length         = L4_EMU_34XX_SIZE,
                 .type           = MT_DEVICE
         },
-#if defined(CONFIG_DEBUG_LL) &&                                                 \
-        (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
-        {
-                .virtual        = ZOOM_UART_VIRT,
-                .pfn            = __phys_to_pfn(ZOOM_UART_BASE),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE
-        },
-#endif
 };
 #endif
 
@@ -613,6 +604,7 @@ void __init am43xx_init_early(void)
         omap_prm_base_init();
         omap_cm_base_init();
         omap3xxx_check_revision();
+        am33xx_check_features();
         am43xx_powerdomains_init();
         am43xx_clockdomains_init();
         am43xx_hwmod_init();
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index a722330d4d53..d121fb6df4e6 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -63,9 +63,6 @@
 #define OMAP_PACKAGE_CUS                5               /* 423-pin 0.65 */
 #define OMAP_PACKAGE_CBB                4               /* 515-pin 0.40 0.50 */
 #define OMAP_PACKAGE_CBC                3               /* 515-pin 0.50 0.65 */
-#define OMAP_PACKAGE_ZAC                2               /* 24xx 447-pin POP */
-#define OMAP_PACKAGE_ZAF                1               /* 2420 447-pin SIP */
-
 
 #define OMAP_MUX_NR_MODES               8               /* Available modes */
 #define OMAP_MUX_NR_SIDES               2               /* Bottom & top */
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index 9002fca76699..5c2cc8083fdd 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -719,6 +719,7 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
         &am33xx_l4_ls__uart4,
         &am33xx_l4_ls__uart5,
         &am33xx_l4_ls__uart6,
+        &am33xx_l4_ls__spinlock,
         &am33xx_l4_ls__elm,
         &am33xx_l4_ls__epwmss0,
         &am33xx_epwmss0__ecap0,
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 6334b96b4097..f5989f2af89f 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -25,6 +25,7 @@
 #include "prminst44xx.h"
 #include "prm-regbits-44xx.h"
 #include "prcm44xx.h"
+#include "prcm43xx.h"
 #include "prcm_mpu44xx.h"
 #include "soc.h"
 
@@ -176,6 +177,8 @@ void omap4_prminst_global_warm_sw_reset(void)
                 dev_inst = OMAP54XX_PRM_DEVICE_INST;
         else if (soc_is_dra7xx())
                 dev_inst = DRA7XX_PRM_DEVICE_INST;
+        else if (soc_is_am43xx())
+                dev_inst = AM43XX_PRM_DEVICE_INST;
         else
                 return;
 
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 076bd90a6ce0..30abcc8b20e0 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -438,7 +438,8 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define AM335X_REV_ES2_1        (AM335X_CLASS | (0x2 << 8))
 
 #define AM437X_CLASS            0x43700000
-#define AM437X_REV_ES1_0        AM437X_CLASS
+#define AM437X_REV_ES1_0        (AM437X_CLASS | (0x10 << 8))
+#define AM437X_REV_ES1_1        (AM437X_CLASS | (0x11 << 8))
 
 #define OMAP443X_CLASS          0x44300044
 #define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 74044aaf438b..b62de9f9d05c 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -604,7 +604,8 @@ OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure",
                         2, "timer_sys_ck", NULL);
 #endif /* CONFIG_ARCH_OMAP3 */
 
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
+        defined(CONFIG_SOC_AM43XX)
 OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL,
                        1, "timer_sys_ck", "ti,timer-alwon");
 #endif
diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig
index b1022f4315f7..eca9eb1c5931 100644
--- a/arch/arm/mach-picoxcell/Kconfig
+++ b/arch/arm/mach-picoxcell/Kconfig
@@ -1,12 +1,7 @@
 config ARCH_PICOXCELL
         bool "Picochip PicoXcell" if ARCH_MULTI_V6
         select ARCH_REQUIRE_GPIOLIB
-        select ARM_PATCH_PHYS_VIRT
         select ARM_VIC
-        select CPU_V6K
         select DW_APB_TIMER_OF
-        select GENERIC_CLOCKEVENTS
         select HAVE_TCM
         select NO_IOPORT
-        select SPARSE_IRQ
-        select USE_OF
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
index 6988b117fc17..2c726b4f9356 100644
--- a/arch/arm/mach-prima2/Kconfig
+++ b/arch/arm/mach-prima2/Kconfig
@@ -1,9 +1,7 @@
 config ARCH_SIRF
         bool "CSR SiRF" if ARCH_MULTI_V7
         select ARCH_REQUIRE_GPIOLIB
-        select GENERIC_CLOCKEVENTS
         select GENERIC_IRQ_CHIP
-        select MIGHT_HAVE_CACHE_L2X0
         select NO_IOPORT
         select PINCTRL
         select PINCTRL_SIRF
@@ -17,7 +15,6 @@ menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features"
 config ARCH_ATLAS6
         bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
         default y
-        select CPU_V7
         select SIRF_IRQ
         help
           Support for CSR SiRFSoC ARM Cortex A9 Platform
@@ -25,7 +22,6 @@ config ARCH_ATLAS6
 config ARCH_PRIMA2
         bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
         default y
-        select CPU_V7
         select SIRF_IRQ
         select ZONE_DMA
         help
@@ -35,9 +31,7 @@ config ARCH_MARCO
         bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform"
         default y
         select ARM_GIC
-        select CPU_V7
         select HAVE_ARM_SCU if SMP
-        select HAVE_SMP
         select SMP_ON_UP if SMP
         help
           Support for CSR SiRFSoC ARM Cortex A9 Platform
diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c
index c9f309ae88c5..8b90c4f2d430 100644
--- a/arch/arm/mach-pxa/am300epd.c
+++ b/arch/arm/mach-pxa/am300epd.c
@@ -30,6 +30,7 @@
 
 #include <mach/gumstix.h>
 #include <mach/mfp-pxa25x.h>
+#include <mach/irqs.h>
 #include <linux/platform_data/video-pxafb.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h
index 954641e6c8b1..1b0825911e62 100644
--- a/arch/arm/mach-pxa/include/mach/balloon3.h
+++ b/arch/arm/mach-pxa/include/mach/balloon3.h
@@ -14,6 +14,8 @@
 #ifndef ASM_ARCH_BALLOON3_H
 #define ASM_ARCH_BALLOON3_H
 
+#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */
+
 enum balloon3_features {
         BALLOON3_FEATURE_OHCI,
         BALLOON3_FEATURE_MMC,
diff --git a/arch/arm/mach-pxa/include/mach/corgi.h b/arch/arm/mach-pxa/include/mach/corgi.h
index f3c3493b468d..c030d955bbd7 100644
--- a/arch/arm/mach-pxa/include/mach/corgi.h
+++ b/arch/arm/mach-pxa/include/mach/corgi.h
@@ -13,6 +13,7 @@
 #ifndef __ASM_ARCH_CORGI_H
 #define __ASM_ARCH_CORGI_H  1
 
+#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */
 
 /*
  * Corgi (Non Standard) GPIO Definitions
diff --git a/arch/arm/mach-pxa/include/mach/csb726.h b/arch/arm/mach-pxa/include/mach/csb726.h
index 2628e7b72116..00cfbbbf73f7 100644
--- a/arch/arm/mach-pxa/include/mach/csb726.h
+++ b/arch/arm/mach-pxa/include/mach/csb726.h
@@ -11,6 +11,8 @@
 #ifndef CSB726_H
 #define CSB726_H
 
+#include "irqs.h" /* PXA_GPIO_TO_IRQ */
+
 #define CSB726_GPIO_IRQ_LAN     52
 #define CSB726_GPIO_IRQ_SM501   53
 #define CSB726_GPIO_MMC_DETECT  100
diff --git a/arch/arm/mach-pxa/include/mach/gumstix.h b/arch/arm/mach-pxa/include/mach/gumstix.h
index dba14b6503ad..f7df27bbb42e 100644
--- a/arch/arm/mach-pxa/include/mach/gumstix.h
+++ b/arch/arm/mach-pxa/include/mach/gumstix.h
@@ -6,6 +6,7 @@
  * published by the Free Software Foundation.
  */
 
+#include "irqs.h" /* PXA_GPIO_TO_IRQ */
 
 /* BTRESET - Reset line to Bluetooth module, active low signal. */
 #define GPIO_GUMSTIX_BTRESET          7
diff --git a/arch/arm/mach-pxa/include/mach/idp.h b/arch/arm/mach-pxa/include/mach/idp.h
index 22a96f87232b..7e63f4680271 100644
--- a/arch/arm/mach-pxa/include/mach/idp.h
+++ b/arch/arm/mach-pxa/include/mach/idp.h
@@ -23,6 +23,7 @@
  * IDP hardware.
  */
 
+#include "irqs.h" /* PXA_GPIO_TO_IRQ */
 
 #define IDP_FLASH_PHYS          (PXA_CS0_PHYS)
 #define IDP_ALT_FLASH_PHYS      (PXA_CS1_PHYS)
diff --git a/arch/arm/mach-pxa/include/mach/palmld.h b/arch/arm/mach-pxa/include/mach/palmld.h
index 2c4471336570..b184f296023b 100644
--- a/arch/arm/mach-pxa/include/mach/palmld.h
+++ b/arch/arm/mach-pxa/include/mach/palmld.h
@@ -13,6 +13,8 @@
 #ifndef _INCLUDE_PALMLD_H_
 #define _INCLUDE_PALMLD_H_
 
+#include "irqs.h" /* PXA_GPIO_TO_IRQ */
+
 /** HERE ARE GPIOs **/
 
 /* GPIOs */
diff --git a/arch/arm/mach-pxa/include/mach/palmt5.h b/arch/arm/mach-pxa/include/mach/palmt5.h
index 0bd4f036c72f..e342c5921405 100644
--- a/arch/arm/mach-pxa/include/mach/palmt5.h
+++ b/arch/arm/mach-pxa/include/mach/palmt5.h
@@ -15,6 +15,8 @@
 #ifndef _INCLUDE_PALMT5_H_
 #define _INCLUDE_PALMT5_H_
 
+#include "irqs.h" /* PXA_GPIO_TO_IRQ */
+
 /** HERE ARE GPIOs **/
 
 /* GPIOs */
diff --git a/arch/arm/mach-pxa/include/mach/palmtc.h b/arch/arm/mach-pxa/include/mach/palmtc.h
index c383a21680b6..81c727b3cfd2 100644
--- a/arch/arm/mach-pxa/include/mach/palmtc.h
+++ b/arch/arm/mach-pxa/include/mach/palmtc.h
@@ -16,6 +16,8 @@
 #ifndef _INCLUDE_PALMTC_H_
 #define _INCLUDE_PALMTC_H_
 
+#include "irqs.h" /* PXA_GPIO_TO_IRQ */
+
 /** HERE ARE GPIOs **/
 
 /* GPIOs */
diff --git a/arch/arm/mach-pxa/include/mach/palmtx.h b/arch/arm/mach-pxa/include/mach/palmtx.h
index f2e530380253..92bc1f05300d 100644
--- a/arch/arm/mach-pxa/include/mach/palmtx.h
+++ b/arch/arm/mach-pxa/include/mach/palmtx.h
@@ -16,6 +16,8 @@
 #ifndef _INCLUDE_PALMTX_H_
 #define _INCLUDE_PALMTX_H_
 
+#include "irqs.h" /* PXA_GPIO_TO_IRQ */
+
 /** HERE ARE GPIOs **/
 
 /* GPIOs */
diff --git a/arch/arm/mach-pxa/include/mach/pcm027.h b/arch/arm/mach-pxa/include/mach/pcm027.h
index 6bf28de228bd..86ebd7b6c960 100644
--- a/arch/arm/mach-pxa/include/mach/pcm027.h
+++ b/arch/arm/mach-pxa/include/mach/pcm027.h
@@ -23,6 +23,8 @@
  * Definitions of CPU card resources only
  */
 
+#include "irqs.h" /* PXA_GPIO_TO_IRQ */
+
 /* phyCORE-PXA270 (PCM027) Interrupts */
 #define PCM027_IRQ(x)          (IRQ_BOARD_START + (x))
 #define PCM027_BTDET_IRQ       PCM027_IRQ(0)
diff --git a/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h b/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
index 0260aaa2fc17..7e544c14967e 100644
--- a/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
+++ b/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
@@ -20,6 +20,7 @@
  */
 
 #include <mach/pcm027.h>
+#include "irqs.h" /* PXA_GPIO_TO_IRQ */
 
 /*
  * definitions relevant only when the PCM-990
diff --git a/arch/arm/mach-pxa/include/mach/poodle.h b/arch/arm/mach-pxa/include/mach/poodle.h
index f32ff75dcca8..b56b19351a03 100644
--- a/arch/arm/mach-pxa/include/mach/poodle.h
+++ b/arch/arm/mach-pxa/include/mach/poodle.h
@@ -15,6 +15,8 @@
 #ifndef __ASM_ARCH_POODLE_H
 #define __ASM_ARCH_POODLE_H  1
 
+#include "irqs.h" /* PXA_GPIO_TO_IRQ */
+
 /*
  * GPIOs
  */
diff --git a/arch/arm/mach-pxa/include/mach/spitz.h b/arch/arm/mach-pxa/include/mach/spitz.h
index 0bfe6507c95d..25c9f62e46aa 100644
--- a/arch/arm/mach-pxa/include/mach/spitz.h
+++ b/arch/arm/mach-pxa/include/mach/spitz.h
@@ -15,8 +15,8 @@
 #define __ASM_ARCH_SPITZ_H  1
 #endif
 
+#include "irqs.h" /* PXA_NR_BUILTIN_GPIO, PXA_GPIO_TO_IRQ */
 #include <linux/fb.h>
-#include <linux/gpio.h>
 
 /* Spitz/Akita GPIOs */
 
diff --git a/arch/arm/mach-pxa/include/mach/tosa.h b/arch/arm/mach-pxa/include/mach/tosa.h
index 2bb0e862598c..0497d95cef25 100644
--- a/arch/arm/mach-pxa/include/mach/tosa.h
+++ b/arch/arm/mach-pxa/include/mach/tosa.h
@@ -13,6 +13,8 @@
 #ifndef _ASM_ARCH_TOSA_H_
 #define _ASM_ARCH_TOSA_H_ 1
 
+#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */
+
 /*  TOSA Chip selects  */
 #define TOSA_LCDC_PHYS          PXA_CS4_PHYS
 /* Internel Scoop */
diff --git a/arch/arm/mach-pxa/include/mach/trizeps4.h b/arch/arm/mach-pxa/include/mach/trizeps4.h
index d2ca01053f69..ae3ca013afab 100644
--- a/arch/arm/mach-pxa/include/mach/trizeps4.h
+++ b/arch/arm/mach-pxa/include/mach/trizeps4.h
@@ -10,6 +10,8 @@
 #ifndef _TRIPEPS4_H_
 #define _TRIPEPS4_H_
 
+#include "irqs.h" /* PXA_GPIO_TO_IRQ */
+
 /* physical memory regions */
 #define TRIZEPS4_FLASH_PHYS     (PXA_CS0_PHYS)  /* Flash region */
 #define TRIZEPS4_DISK_PHYS      (PXA_CS1_PHYS)  /* Disk On Chip region */
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index f70583fee59f..29997bde277d 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -38,6 +38,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/usb/gpio_vbus.h>
 #include <linux/reboot.h>
+#include <linux/regulator/fixed.h>
 #include <linux/regulator/max1586.h>
 #include <linux/slab.h>
 #include <linux/i2c/pxa-i2c.h>
@@ -714,6 +715,10 @@ static struct gpio global_gpios[] = {
         { GPIO56_MT9M111_nOE, GPIOF_OUT_INIT_LOW, "Camera nOE" },
 };
 
+static struct regulator_consumer_supply fixed_5v0_consumers[] = {
+        REGULATOR_SUPPLY("power", "pwm-backlight"),
+};
+
 static void __init mioa701_machine_init(void)
 {
         int rc;
@@ -753,6 +758,10 @@ static void __init mioa701_machine_init(void)
         pxa_set_i2c_info(&i2c_pdata);
         pxa27x_set_i2c_power_info(NULL);
         pxa_set_camera_info(&mioa701_pxacamera_platform_data);
+
+        regulator_register_always_on(0, "fixed-5.0V", fixed_5v0_consumers,
+                                     ARRAY_SIZE(fixed_5v0_consumers),
+                                     5000000);
 }
 
 static void mioa701_machine_exit(void)
diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig
new file mode 100644
index 000000000000..a028be234334
--- /dev/null
+++ b/arch/arm/mach-qcom/Kconfig
@@ -0,0 +1,33 @@
+config ARCH_QCOM
+        bool "Qualcomm Support" if ARCH_MULTI_V7
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_GIC
+        select CLKSRC_OF
+        select GENERIC_CLOCKEVENTS
+        select HAVE_SMP
+        select QCOM_SCM if SMP
+        help
+          Support for Qualcomm's devicetree based systems.
+
+if ARCH_QCOM
+
+menu "Qualcomm SoC Selection"
+
+config ARCH_MSM8X60
+        bool "Enable support for MSM8X60"
+        select CLKSRC_QCOM
+
+config ARCH_MSM8960
+        bool "Enable support for MSM8960"
+        select CLKSRC_QCOM
+
+config ARCH_MSM8974
+        bool "Enable support for MSM8974"
+        select HAVE_ARM_ARCH_TIMER
+
+endmenu
+
+config QCOM_SCM
+        bool
+
+endif
diff --git a/arch/arm/mach-qcom/Makefile b/arch/arm/mach-qcom/Makefile
new file mode 100644
index 000000000000..8f756ae1ae31
--- /dev/null
+++ b/arch/arm/mach-qcom/Makefile
@@ -0,0 +1,5 @@
+obj-y                   := board.o
+obj-$(CONFIG_SMP)       += platsmp.o
+obj-$(CONFIG_QCOM_SCM)  += scm.o scm-boot.o
+
+CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1)
diff --git a/arch/arm/mach-msm/board-dt.c b/arch/arm/mach-qcom/board.c
index 1f11d93e700e..bae617ef0b31 100644
--- a/arch/arm/mach-msm/board-dt.c
+++ b/arch/arm/mach-qcom/board.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2012,2013 The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2014 The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -11,31 +11,16 @@
  */
 
 #include <linux/init.h>
-#include <linux/of.h>
-#include <linux/of_platform.h>
 
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
 
-#include "common.h"
-
-static const char * const msm_dt_match[] __initconst = {
-        "qcom,msm8660-fluid",
+static const char * const qcom_dt_match[] __initconst = {
         "qcom,msm8660-surf",
         "qcom,msm8960-cdp",
-        NULL
-};
-
-static const char * const apq8074_dt_match[] __initconst = {
         "qcom,apq8074-dragonboard",
         NULL
 };
 
-DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
-        .smp = smp_ops(msm_smp_ops),
-        .dt_compat = msm_dt_match,
-MACHINE_END
-
-DT_MACHINE_START(APQ_DT, "Qualcomm MSM (Flattened Device Tree)")
-        .dt_compat = apq8074_dt_match,
+DT_MACHINE_START(QCOM_DT, "Qualcomm (Flattened Device Tree)")
+        .dt_compat = qcom_dt_match,
 MACHINE_END
diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c
new file mode 100644
index 000000000000..d6908569ecaf
--- /dev/null
+++ b/arch/arm/mach-qcom/platsmp.c
@@ -0,0 +1,378 @@
+/*
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *  Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *  Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+
+#include <asm/smp_plat.h>
+
+#include "scm-boot.h"
+
+#define VDD_SC1_ARRAY_CLAMP_GFS_CTL     0x35a0
+#define SCSS_CPU1CORE_RESET             0x2d80
+#define SCSS_DBG_STATUS_CORE_PWRDUP     0x2e64
+
+#define APCS_CPU_PWR_CTL        0x04
+#define PLL_CLAMP               BIT(8)
+#define CORE_PWRD_UP            BIT(7)
+#define COREPOR_RST             BIT(5)
+#define CORE_RST                BIT(4)
+#define L2DT_SLP                BIT(3)
+#define CLAMP                   BIT(0)
+
+#define APC_PWR_GATE_CTL        0x14
+#define BHS_CNT_SHIFT           24
+#define LDO_PWR_DWN_SHIFT       16
+#define LDO_BYP_SHIFT           8
+#define BHS_SEG_SHIFT           1
+#define BHS_EN                  BIT(0)
+
+#define APCS_SAW2_VCTL          0x14
+#define APCS_SAW2_2_VCTL        0x1c
+
+extern void secondary_startup(void);
+
+static DEFINE_SPINLOCK(boot_lock);
+
+#ifdef CONFIG_HOTPLUG_CPU
+static void __ref qcom_cpu_die(unsigned int cpu)
+{
+        wfi();
+}
+#endif
+
+static void qcom_secondary_init(unsigned int cpu)
+{
+        /*
+         * Synchronise with the boot thread.
+         */
+        spin_lock(&boot_lock);
+        spin_unlock(&boot_lock);
+}
+
+static int scss_release_secondary(unsigned int cpu)
+{
+        struct device_node *node;
+        void __iomem *base;
+
+        node = of_find_compatible_node(NULL, NULL, "qcom,gcc-msm8660");
+        if (!node) {
+                pr_err("%s: can't find node\n", __func__);
+                return -ENXIO;
+        }
+
+        base = of_iomap(node, 0);
+        of_node_put(node);
+        if (!base)
+                return -ENOMEM;
+
+        writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
+        writel_relaxed(0, base + SCSS_CPU1CORE_RESET);
+        writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP);
+        mb();
+        iounmap(base);
+
+        return 0;
+}
+
+static int kpssv1_release_secondary(unsigned int cpu)
+{
+        int ret = 0;
+        void __iomem *reg, *saw_reg;
+        struct device_node *cpu_node, *acc_node, *saw_node;
+        u32 val;
+
+        cpu_node = of_get_cpu_node(cpu, NULL);
+        if (!cpu_node)
+                return -ENODEV;
+
+        acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
+        if (!acc_node) {
+                ret = -ENODEV;
+                goto out_acc;
+        }
+
+        saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
+        if (!saw_node) {
+                ret = -ENODEV;
+                goto out_saw;
+        }
+
+        reg = of_iomap(acc_node, 0);
+        if (!reg) {
+                ret = -ENOMEM;
+                goto out_acc_map;
+        }
+
+        saw_reg = of_iomap(saw_node, 0);
+        if (!saw_reg) {
+                ret = -ENOMEM;
+                goto out_saw_map;
+        }
+
+        /* Turn on CPU rail */
+        writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL);
+        mb();
+        udelay(512);
+
+        /* Krait bring-up sequence */
+        val = PLL_CLAMP | L2DT_SLP | CLAMP;
+        writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
+        val &= ~L2DT_SLP;
+        writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
+        mb();
+        ndelay(300);
+
+        val |= COREPOR_RST;
+        writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
+        mb();
+        udelay(2);
+
+        val &= ~CLAMP;
+        writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
+        mb();
+        udelay(2);
+
+        val &= ~COREPOR_RST;
+        writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
+        mb();
+        udelay(100);
+
+        val |= CORE_PWRD_UP;
+        writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
+        mb();
+
+        iounmap(saw_reg);
+out_saw_map:
+        iounmap(reg);
+out_acc_map:
+        of_node_put(saw_node);
+out_saw:
+        of_node_put(acc_node);
+out_acc:
+        of_node_put(cpu_node);
+        return ret;
+}
+
+static int kpssv2_release_secondary(unsigned int cpu)
+{
+        void __iomem *reg;
+        struct device_node *cpu_node, *l2_node, *acc_node, *saw_node;
+        void __iomem *l2_saw_base;
+        unsigned reg_val;
+        int ret;
+
+        cpu_node = of_get_cpu_node(cpu, NULL);
+        if (!cpu_node)
+                return -ENODEV;
+
+        acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
+        if (!acc_node) {
+                ret = -ENODEV;
+                goto out_acc;
+        }
+
+        l2_node = of_parse_phandle(cpu_node, "next-level-cache", 0);
+        if (!l2_node) {
+                ret = -ENODEV;
+                goto out_l2;
+        }
+
+        saw_node = of_parse_phandle(l2_node, "qcom,saw", 0);
+        if (!saw_node) {
+                ret = -ENODEV;
+                goto out_saw;
+        }
+
+        reg = of_iomap(acc_node, 0);
+        if (!reg) {
+                ret = -ENOMEM;
+                goto out_map;
+        }
+
+        l2_saw_base = of_iomap(saw_node, 0);
+        if (!l2_saw_base) {
+                ret = -ENOMEM;
+                goto out_saw_map;
+        }
+
+        /* Turn on the BHS, turn off LDO Bypass and power down LDO */
+        reg_val = (64 << BHS_CNT_SHIFT) | (0x3f << LDO_PWR_DWN_SHIFT) | BHS_EN;
+        writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
+        mb();
+        /* wait for the BHS to settle */
+        udelay(1);
+
+        /* Turn on BHS segments */
+        reg_val |= 0x3f << BHS_SEG_SHIFT;
+        writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
+        mb();
+         /* wait for the BHS to settle */
+        udelay(1);
+
+        /* Finally turn on the bypass so that BHS supplies power */
+        reg_val |= 0x3f << LDO_BYP_SHIFT;
+        writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
+
+        /* enable max phases */
+        writel_relaxed(0x10003, l2_saw_base + APCS_SAW2_2_VCTL);
+        mb();
+        udelay(50);
+
+        reg_val = COREPOR_RST | CLAMP;
+        writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
+        mb();
+        udelay(2);
+
+        reg_val &= ~CLAMP;
+        writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
+        mb();
+        udelay(2);
+
+        reg_val &= ~COREPOR_RST;
+        writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
+        mb();
+
+        reg_val |= CORE_PWRD_UP;
+        writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
+        mb();
+
+        ret = 0;
+
+        iounmap(l2_saw_base);
+out_saw_map:
+        iounmap(reg);
+out_map:
+        of_node_put(saw_node);
+out_saw:
+        of_node_put(l2_node);
+out_l2:
+        of_node_put(acc_node);
+out_acc:
+        of_node_put(cpu_node);
+
+        return ret;
+}
+
+static DEFINE_PER_CPU(int, cold_boot_done);
+
+static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
+{
+        int ret = 0;
+
+        if (!per_cpu(cold_boot_done, cpu)) {
+                ret = func(cpu);
+                if (!ret)
+                        per_cpu(cold_boot_done, cpu) = true;
+        }
+
+        /*
+         * set synchronisation state between this boot processor
+         * and the secondary one
+         */
+        spin_lock(&boot_lock);
+
+        /*
+         * Send the secondary CPU a soft interrupt, thereby causing
+         * the boot monitor to read the system wide flags register,
+         * and branch to the address found there.
+         */
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+        /*
+         * now the secondary core is starting up let it run its
+         * calibrations, then wait for it to finish
+         */
+        spin_unlock(&boot_lock);
+
+        return ret;
+}
+
+static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        return qcom_boot_secondary(cpu, scss_release_secondary);
+}
+
+static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        return qcom_boot_secondary(cpu, kpssv1_release_secondary);
+}
+
+static int kpssv2_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        return qcom_boot_secondary(cpu, kpssv2_release_secondary);
+}
+
+static void __init qcom_smp_prepare_cpus(unsigned int max_cpus)
+{
+        int cpu, map;
+        unsigned int flags = 0;
+        static const int cold_boot_flags[] = {
+                0,
+                SCM_FLAG_COLDBOOT_CPU1,
+                SCM_FLAG_COLDBOOT_CPU2,
+                SCM_FLAG_COLDBOOT_CPU3,
+        };
+
+        for_each_present_cpu(cpu) {
+                map = cpu_logical_map(cpu);
+                if (WARN_ON(map >= ARRAY_SIZE(cold_boot_flags))) {
+                        set_cpu_present(cpu, false);
+                        continue;
+                }
+                flags |= cold_boot_flags[map];
+        }
+
+        if (scm_set_boot_addr(virt_to_phys(secondary_startup), flags)) {
+                for_each_present_cpu(cpu) {
+                        if (cpu == smp_processor_id())
+                                continue;
+                        set_cpu_present(cpu, false);
+                }
+                pr_warn("Failed to set CPU boot address, disabling SMP\n");
+        }
+}
+
+static struct smp_operations smp_msm8660_ops __initdata = {
+        .smp_prepare_cpus       = qcom_smp_prepare_cpus,
+        .smp_secondary_init     = qcom_secondary_init,
+        .smp_boot_secondary     = msm8660_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = qcom_cpu_die,
+#endif
+};
+CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops);
+
+static struct smp_operations qcom_smp_kpssv1_ops __initdata = {
+        .smp_prepare_cpus       = qcom_smp_prepare_cpus,
+        .smp_secondary_init     = qcom_secondary_init,
+        .smp_boot_secondary     = kpssv1_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = qcom_cpu_die,
+#endif
+};
+CPU_METHOD_OF_DECLARE(qcom_smp_kpssv1, "qcom,kpss-acc-v1", &qcom_smp_kpssv1_ops);
+
+static struct smp_operations qcom_smp_kpssv2_ops __initdata = {
+        .smp_prepare_cpus       = qcom_smp_prepare_cpus,
+        .smp_secondary_init     = qcom_secondary_init,
+        .smp_boot_secondary     = kpssv2_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = qcom_cpu_die,
+#endif
+};
+CPU_METHOD_OF_DECLARE(qcom_smp_kpssv2, "qcom,kpss-acc-v2", &qcom_smp_kpssv2_ops);
diff --git a/arch/arm/mach-msm/scm-boot.c b/arch/arm/mach-qcom/scm-boot.c
index 45cee3e469a5..45cee3e469a5 100644
--- a/arch/arm/mach-msm/scm-boot.c
+++ b/arch/arm/mach-qcom/scm-boot.c
diff --git a/arch/arm/mach-msm/scm-boot.h b/arch/arm/mach-qcom/scm-boot.h
index 7be32ff5d687..6aabb2428176 100644
--- a/arch/arm/mach-msm/scm-boot.h
+++ b/arch/arm/mach-qcom/scm-boot.h
@@ -13,9 +13,11 @@
 #define __MACH_SCM_BOOT_H
 
 #define SCM_BOOT_ADDR                   0x1
-#define SCM_FLAG_COLDBOOT_CPU1          0x1
-#define SCM_FLAG_WARMBOOT_CPU1          0x2
-#define SCM_FLAG_WARMBOOT_CPU0          0x4
+#define SCM_FLAG_COLDBOOT_CPU1          0x01
+#define SCM_FLAG_COLDBOOT_CPU2          0x08
+#define SCM_FLAG_COLDBOOT_CPU3          0x20
+#define SCM_FLAG_WARMBOOT_CPU0          0x04
+#define SCM_FLAG_WARMBOOT_CPU1          0x02
 
 int scm_set_boot_addr(phys_addr_t addr, int flags);
 
diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-qcom/scm.c
index c536fd6bf827..c536fd6bf827 100644
--- a/arch/arm/mach-msm/scm.c
+++ b/arch/arm/mach-qcom/scm.c
diff --git a/arch/arm/mach-msm/scm.h b/arch/arm/mach-qcom/scm.h
index 00b31ea58f29..00b31ea58f29 100644
--- a/arch/arm/mach-msm/scm.h
+++ b/arch/arm/mach-qcom/scm.h
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index cf073dea5784..1caee6d548b8 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -5,10 +5,8 @@ config ARCH_ROCKCHIP
         select ARCH_REQUIRE_GPIOLIB
         select ARM_GIC
         select CACHE_L2X0
+        select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
         select DW_APB_TIMER_OF
         select ARM_GLOBAL_TIMER
         select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 1547d4fc920a..4377a1436a98 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o
+obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/arch/arm/mach-rockchip/core.h b/arch/arm/mach-rockchip/core.h
new file mode 100644
index 000000000000..e2e7c9dbb200
--- /dev/null
+++ b/arch/arm/mach-rockchip/core.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+extern char rockchip_secondary_trampoline;
+extern char rockchip_secondary_trampoline_end;
+
+extern unsigned long rockchip_boot_fn;
+extern void rockchip_secondary_startup(void);
+
+extern struct smp_operations rockchip_smp_ops;
diff --git a/arch/arm/mach-rockchip/headsmp.S b/arch/arm/mach-rockchip/headsmp.S
new file mode 100644
index 000000000000..73206e360e31
--- /dev/null
+++ b/arch/arm/mach-rockchip/headsmp.S
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+ENTRY(rockchip_secondary_startup)
+        bl      v7_invalidate_l1
+        b       secondary_startup
+ENDPROC(rockchip_secondary_startup)
+
+ENTRY(rockchip_secondary_trampoline)
+        ldr     pc, 1f
+ENDPROC(rockchip_secondary_trampoline)
+        .globl  rockchip_boot_fn
+rockchip_boot_fn:
+1:      .space  4
+
+ENTRY(rockchip_secondary_trampoline_end)
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
new file mode 100644
index 000000000000..dbfa5a26cfff
--- /dev/null
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <asm/cacheflush.h>
+#include <asm/smp_scu.h>
+#include <asm/smp_plat.h>
+#include <asm/mach/map.h>
+
+#include "core.h"
+
+static void __iomem *scu_base_addr;
+static void __iomem *sram_base_addr;
+static int ncores;
+
+#define PMU_PWRDN_CON           0x08
+#define PMU_PWRDN_ST            0x0c
+
+#define PMU_PWRDN_SCU           4
+
+static void __iomem *pmu_base_addr;
+
+static inline bool pmu_power_domain_is_on(int pd)
+{
+        return !(readl_relaxed(pmu_base_addr + PMU_PWRDN_ST) & BIT(pd));
+}
+
+static void pmu_set_power_domain(int pd, bool on)
+{
+        u32 val = readl_relaxed(pmu_base_addr + PMU_PWRDN_CON);
+        if (on)
+                val &= ~BIT(pd);
+        else
+                val |=  BIT(pd);
+        writel(val, pmu_base_addr + PMU_PWRDN_CON);
+
+        while (pmu_power_domain_is_on(pd) != on) { }
+}
+
+/*
+ * Handling of CPU cores
+ */
+
+static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
+                                             struct task_struct *idle)
+{
+        if (!sram_base_addr || !pmu_base_addr) {
+                pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
+                return -ENXIO;
+        }
+
+        if (cpu >= ncores) {
+                pr_err("%s: cpu %d outside maximum number of cpus %d\n",
+                                                        __func__, cpu, ncores);
+                return -ENXIO;
+        }
+
+        /* start the core */
+        pmu_set_power_domain(0 + cpu, true);
+
+        return 0;
+}
+
+/**
+ * rockchip_smp_prepare_sram - populate necessary sram block
+ * Starting cores execute the code residing at the start of the on-chip sram
+ * after power-on. Therefore make sure, this sram region is reserved and
+ * big enough. After this check, copy the trampoline code that directs the
+ * core to the real startup code in ram into the sram-region.
+ * @node: mmio-sram device node
+ */
+static int __init rockchip_smp_prepare_sram(struct device_node *node)
+{
+        unsigned int trampoline_sz = &rockchip_secondary_trampoline_end -
+                                            &rockchip_secondary_trampoline;
+        struct resource res;
+        unsigned int rsize;
+        int ret;
+
+        ret = of_address_to_resource(node, 0, &res);
+        if (ret < 0) {
+                pr_err("%s: could not get address for node %s\n",
+                       __func__, node->full_name);
+                return ret;
+        }
+
+        rsize = resource_size(&res);
+        if (rsize < trampoline_sz) {
+                pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n",
+                       __func__, rsize, trampoline_sz);
+                return -EINVAL;
+        }
+
+        sram_base_addr = of_iomap(node, 0);
+
+        /* set the boot function for the sram code */
+        rockchip_boot_fn = virt_to_phys(rockchip_secondary_startup);
+
+        /* copy the trampoline to sram, that runs during startup of the core */
+        memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
+        flush_cache_all();
+        outer_clean_range(0, trampoline_sz);
+
+        dsb_sev();
+
+        return 0;
+}
+
+static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
+{
+        struct device_node *node;
+        unsigned int i;
+
+        node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
+        if (!node) {
+                pr_err("%s: missing scu\n", __func__);
+                return;
+        }
+
+        scu_base_addr = of_iomap(node, 0);
+        if (!scu_base_addr) {
+                pr_err("%s: could not map scu registers\n", __func__);
+                return;
+        }
+
+        node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
+        if (!node) {
+                pr_err("%s: could not find sram dt node\n", __func__);
+                return;
+        }
+
+        if (rockchip_smp_prepare_sram(node))
+                return;
+
+        node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
+        if (!node) {
+                pr_err("%s: could not find sram dt node\n", __func__);
+                return;
+        }
+
+        pmu_base_addr = of_iomap(node, 0);
+        if (!pmu_base_addr) {
+                pr_err("%s: could not map pmu registers\n", __func__);
+                return;
+        }
+
+        /* enable the SCU power domain */
+        pmu_set_power_domain(PMU_PWRDN_SCU, true);
+
+        /*
+         * While the number of cpus is gathered from dt, also get the number
+         * of cores from the scu to verify this value when booting the cores.
+         */
+        ncores = scu_get_core_count(scu_base_addr);
+
+        scu_enable(scu_base_addr);
+
+        /* Make sure that all cores except the first are really off */
+        for (i = 1; i < ncores; i++)
+                pmu_set_power_domain(0 + i, false);
+}
+
+struct smp_operations rockchip_smp_ops __initdata = {
+        .smp_prepare_cpus       = rockchip_smp_prepare_cpus,
+        .smp_boot_secondary     = rockchip_boot_secondary,
+};
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index 82c0b0709712..d211d6fa0d98 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -22,6 +22,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/hardware/cache-l2x0.h>
+#include "core.h"
 
 static void __init rockchip_dt_init(void)
 {
@@ -38,6 +39,7 @@ static const char * const rockchip_board_dt_compat[] = {
 };
 
 DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
+        .smp            = smp_ops(rockchip_smp_ops),
         .init_machine   = rockchip_dt_init,
         .dt_compat      = rockchip_board_dt_compat,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 338640631e08..c54db0046ce3 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -5,18 +5,14 @@ config ARCH_SHMOBILE_MULTI
         bool "Renesas ARM SoCs" if ARCH_MULTI_V7
         depends on MMU
         select ARCH_SHMOBILE
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
         select HAVE_ARM_SCU if SMP
-        select HAVE_ARM_TWD if LOCAL_TIMERS
-        select HAVE_SMP
+        select HAVE_ARM_TWD if SMP
         select ARM_GIC
-        select MIGHT_HAVE_CACHE_L2X0
         select MIGHT_HAVE_PCI
+        select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
         select NO_IOPORT
         select PINCTRL
         select ARCH_REQUIRE_GPIOLIB
-        select CLKDEV_LOOKUP
 
 if ARCH_SHMOBILE_MULTI
 
@@ -123,6 +119,7 @@ config ARCH_R8A7790
         select MIGHT_HAVE_PCI
         select SH_CLK_CPG
         select RENESAS_IRQC
+        select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
 
 config ARCH_R8A7791
         bool "R-Car M2 (R8A77910)"
@@ -132,6 +129,7 @@ config ARCH_R8A7791
         select MIGHT_HAVE_PCI
         select SH_CLK_CPG
         select RENESAS_IRQC
+        select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
 
 config ARCH_EMEV2
         bool "Emma Mobile EV2"
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index fe7d4ff706e4..d38a6362e5f8 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -52,7 +52,8 @@ obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
 obj-$(CONFIG_ARCH_SH7372)       += pm-sh7372.o sleep-sh7372.o pm-rmobile.o
 obj-$(CONFIG_ARCH_SH73A0)       += pm-sh73a0.o
 obj-$(CONFIG_ARCH_R8A7740)      += pm-r8a7740.o pm-rmobile.o
-obj-$(CONFIG_ARCH_R8A7779)      += pm-r8a7779.o
+obj-$(CONFIG_ARCH_R8A7779)      += pm-r8a7779.o pm-rcar.o
+obj-$(CONFIG_ARCH_R8A7790)      += pm-r8a7790.o pm-rcar.o
 
 # Board objects
 ifdef CONFIG_ARCH_SHMOBILE_MULTI
diff --git a/arch/arm/mach-shmobile/include/mach/pm-rcar.h b/arch/arm/mach-shmobile/include/mach/pm-rcar.h
new file mode 100644
index 000000000000..ef3a1ef628f1
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/pm-rcar.h
@@ -0,0 +1,15 @@
+#ifndef PM_RCAR_H
+#define PM_RCAR_H
+
+struct rcar_sysc_ch {
+        unsigned long chan_offs;
+        unsigned int chan_bit;
+        unsigned int isr_bit;
+};
+
+int rcar_sysc_power_down(struct rcar_sysc_ch *sysc_ch);
+int rcar_sysc_power_up(struct rcar_sysc_ch *sysc_ch);
+bool rcar_sysc_power_is_off(struct rcar_sysc_ch *sysc_ch);
+void __iomem *rcar_sysc_init(phys_addr_t base);
+
+#endif /* PM_RCAR_H */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index b40e13631f6a..88eeceaf1088 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -3,6 +3,7 @@
 
 #include <linux/sh_clk.h>
 #include <linux/pm_domain.h>
+#include <mach/pm-rcar.h>
 
 /* HPB-DMA slave IDs */
 enum {
@@ -11,18 +12,12 @@ enum {
         HPBDMA_SLAVE_SDHI0_RX,
 };
 
-struct r8a7779_pm_ch {
-        unsigned long chan_offs;
-        unsigned int chan_bit;
-        unsigned int isr_bit;
-};
-
 struct r8a7779_pm_domain {
         struct generic_pm_domain genpd;
-        struct r8a7779_pm_ch ch;
+        struct rcar_sysc_ch ch;
 };
 
-static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d)
+static inline struct rcar_sysc_ch *to_r8a7779_ch(struct generic_pm_domain *d)
 {
         return &container_of(d, struct r8a7779_pm_domain, genpd)->ch;
 }
@@ -41,8 +36,6 @@ extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
 extern void r8a7779_register_twd(void);
-extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch);
-extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch);
 
 #ifdef CONFIG_PM
 extern void __init r8a7779_init_pm_domains(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
index 5fbfa28b40b6..3389f0775def 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
@@ -7,6 +7,7 @@ void r8a7790_add_standard_devices(void);
 void r8a7790_add_dt_devices(void);
 void r8a7790_clock_init(void);
 void r8a7790_pinmux_init(void);
+void r8a7790_pm_init(void);
 void r8a7790_init_early(void);
 extern struct smp_operations r8a7790_smp_ops;
 
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index 1da5a72d9642..8cb641c00fdb 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -75,8 +75,7 @@ static void apmu_init_cpu(struct resource *res, int cpu, int bit)
         apmu_cpus[cpu].iomem = ioremap_nocache(res->start, resource_size(res));
         apmu_cpus[cpu].bit = bit;
 
-        pr_debug("apmu ioremap %d %d 0x%08x 0x%08x\n", cpu, bit,
-                 res->start, resource_size(res));
+        pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res);
 }
 
 static struct {
diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c
index d50a8e9b94a4..d6fe189b2df6 100644
--- a/arch/arm/mach-shmobile/pm-r8a7779.c
+++ b/arch/arm/mach-shmobile/pm-r8a7779.c
@@ -20,132 +20,22 @@
 #include <linux/console.h>
 #include <asm/io.h>
 #include <mach/common.h>
+#include <mach/pm-rcar.h>
 #include <mach/r8a7779.h>
 
-static void __iomem *r8a7779_sysc_base;
-
 /* SYSC */
-#define SYSCSR 0x00
-#define SYSCISR 0x04
-#define SYSCISCR 0x08
 #define SYSCIER 0x0c
 #define SYSCIMR 0x10
-#define PWRSR0 0x40
-#define PWRSR1 0x80
-#define PWRSR2 0xc0
-#define PWRSR3 0x100
-#define PWRSR4 0x140
-
-#define PWRSR_OFFS 0x00
-#define PWROFFCR_OFFS 0x04
-#define PWRONCR_OFFS 0x0c
-#define PWRER_OFFS 0x14
-
-#define SYSCSR_RETRIES 100
-#define SYSCSR_DELAY_US 1
-
-#define SYSCISR_RETRIES 1000
-#define SYSCISR_DELAY_US 1
 
 #if defined(CONFIG_PM) || defined(CONFIG_SMP)
 
-static DEFINE_SPINLOCK(r8a7779_sysc_lock); /* SMP CPUs + I/O devices */
-
-static int r8a7779_sysc_pwr_on_off(struct r8a7779_pm_ch *r8a7779_ch,
-                                   int sr_bit, int reg_offs)
-{
-        int k;
-
-        for (k = 0; k < SYSCSR_RETRIES; k++) {
-                if (ioread32(r8a7779_sysc_base + SYSCSR) & (1 << sr_bit))
-                        break;
-                udelay(SYSCSR_DELAY_US);
-        }
-
-        if (k == SYSCSR_RETRIES)
-                return -EAGAIN;
-
-        iowrite32(1 << r8a7779_ch->chan_bit,
-                  r8a7779_sysc_base + r8a7779_ch->chan_offs + reg_offs);
-
-        return 0;
-}
-
-static int r8a7779_sysc_pwr_off(struct r8a7779_pm_ch *r8a7779_ch)
-{
-        return r8a7779_sysc_pwr_on_off(r8a7779_ch, 0, PWROFFCR_OFFS);
-}
-
-static int r8a7779_sysc_pwr_on(struct r8a7779_pm_ch *r8a7779_ch)
-{
-        return r8a7779_sysc_pwr_on_off(r8a7779_ch, 1, PWRONCR_OFFS);
-}
-
-static int r8a7779_sysc_update(struct r8a7779_pm_ch *r8a7779_ch,
-                               int (*on_off_fn)(struct r8a7779_pm_ch *))
-{
-        unsigned int isr_mask = 1 << r8a7779_ch->isr_bit;
-        unsigned int chan_mask = 1 << r8a7779_ch->chan_bit;
-        unsigned int status;
-        unsigned long flags;
-        int ret = 0;
-        int k;
-
-        spin_lock_irqsave(&r8a7779_sysc_lock, flags);
-
-        iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
-
-        do {
-                ret = on_off_fn(r8a7779_ch);
-                if (ret)
-                        goto out;
-
-                status = ioread32(r8a7779_sysc_base +
-                                  r8a7779_ch->chan_offs + PWRER_OFFS);
-        } while (status & chan_mask);
-
-        for (k = 0; k < SYSCISR_RETRIES; k++) {
-                if (ioread32(r8a7779_sysc_base + SYSCISR) & isr_mask)
-                        break;
-                udelay(SYSCISR_DELAY_US);
-        }
-
-        if (k == SYSCISR_RETRIES)
-                ret = -EIO;
-
-        iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
-
- out:
-        spin_unlock_irqrestore(&r8a7779_sysc_lock, flags);
-
-        pr_debug("r8a7779 power domain %d: %02x %02x %02x %02x %02x -> %d\n",
-                 r8a7779_ch->isr_bit, ioread32(r8a7779_sysc_base + PWRSR0),
-                 ioread32(r8a7779_sysc_base + PWRSR1),
-                 ioread32(r8a7779_sysc_base + PWRSR2),
-                 ioread32(r8a7779_sysc_base + PWRSR3),
-                 ioread32(r8a7779_sysc_base + PWRSR4), ret);
-        return ret;
-}
-
-int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch)
-{
-        return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_off);
-}
-
-int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch)
-{
-        return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_on);
-}
-
 static void __init r8a7779_sysc_init(void)
 {
-        r8a7779_sysc_base = ioremap_nocache(0xffd85000, PAGE_SIZE);
-        if (!r8a7779_sysc_base)
-                panic("unable to ioremap r8a7779 SYSC hardware block\n");
+        void __iomem *base = rcar_sysc_init(0xffd85000);
 
         /* enable all interrupt sources, but do not use interrupt handler */
-        iowrite32(0x0131000e, r8a7779_sysc_base + SYSCIER);
-        iowrite32(0, r8a7779_sysc_base + SYSCIMR);
+        iowrite32(0x0131000e, base + SYSCIER);
+        iowrite32(0, base + SYSCIMR);
 }
 
 #else /* CONFIG_PM || CONFIG_SMP */
@@ -158,24 +48,17 @@ static inline void r8a7779_sysc_init(void) {}
 
 static int pd_power_down(struct generic_pm_domain *genpd)
 {
-        return r8a7779_sysc_power_down(to_r8a7779_ch(genpd));
+        return rcar_sysc_power_down(to_r8a7779_ch(genpd));
 }
 
 static int pd_power_up(struct generic_pm_domain *genpd)
 {
-        return r8a7779_sysc_power_up(to_r8a7779_ch(genpd));
+        return rcar_sysc_power_up(to_r8a7779_ch(genpd));
 }
 
 static bool pd_is_off(struct generic_pm_domain *genpd)
 {
-        struct r8a7779_pm_ch *r8a7779_ch = to_r8a7779_ch(genpd);
-        unsigned int st;
-
-        st = ioread32(r8a7779_sysc_base + r8a7779_ch->chan_offs + PWRSR_OFFS);
-        if (st & (1 << r8a7779_ch->chan_bit))
-                return true;
-
-        return false;
+        return rcar_sysc_power_is_off(to_r8a7779_ch(genpd));
 }
 
 static bool pd_active_wakeup(struct device *dev)
diff --git a/arch/arm/mach-shmobile/pm-r8a7790.c b/arch/arm/mach-shmobile/pm-r8a7790.c
new file mode 100644
index 000000000000..fc82839e2c2a
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm-r8a7790.c
@@ -0,0 +1,45 @@
+/*
+ * r8a7790 Power management support
+ *
+ * Copyright (C) 2013  Renesas Electronics Corporation
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/kernel.h>
+#include <asm/io.h>
+#include <mach/pm-rcar.h>
+#include <mach/r8a7790.h>
+
+/* SYSC */
+#define SYSCIER 0x0c
+#define SYSCIMR 0x10
+
+#if defined(CONFIG_SMP)
+
+static void __init r8a7790_sysc_init(void)
+{
+        void __iomem *base = rcar_sysc_init(0xe6180000);
+
+        /* enable all interrupt sources, but do not use interrupt handler */
+        iowrite32(0x0131000e, base + SYSCIER);
+        iowrite32(0, base + SYSCIMR);
+}
+
+#else /* CONFIG_SMP */
+
+static inline void r8a7790_sysc_init(void) {}
+
+#endif /* CONFIG_SMP */
+
+void __init r8a7790_pm_init(void)
+{
+        static int once;
+
+        if (!once++)
+                r8a7790_sysc_init();
+}
diff --git a/arch/arm/mach-shmobile/pm-rcar.c b/arch/arm/mach-shmobile/pm-rcar.c
new file mode 100644
index 000000000000..1f465a12d1b1
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm-rcar.c
@@ -0,0 +1,141 @@
+/*
+ * R-Car SYSC Power management support
+ *
+ * Copyright (C) 2014  Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/mm.h>
+#include <linux/spinlock.h>
+#include <asm/io.h>
+#include <mach/pm-rcar.h>
+
+/* SYSC */
+#define SYSCSR 0x00
+#define SYSCISR 0x04
+#define SYSCISCR 0x08
+
+#define PWRSR_OFFS 0x00
+#define PWROFFCR_OFFS 0x04
+#define PWRONCR_OFFS 0x0c
+#define PWRER_OFFS 0x14
+
+#define SYSCSR_RETRIES 100
+#define SYSCSR_DELAY_US 1
+
+#define SYSCISR_RETRIES 1000
+#define SYSCISR_DELAY_US 1
+
+#if defined(CONFIG_PM) || defined(CONFIG_SMP)
+
+static void __iomem *rcar_sysc_base;
+static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
+
+static int rcar_sysc_pwr_on_off(struct rcar_sysc_ch *sysc_ch,
+                                int sr_bit, int reg_offs)
+{
+        int k;
+
+        for (k = 0; k < SYSCSR_RETRIES; k++) {
+                if (ioread32(rcar_sysc_base + SYSCSR) & (1 << sr_bit))
+                        break;
+                udelay(SYSCSR_DELAY_US);
+        }
+
+        if (k == SYSCSR_RETRIES)
+                return -EAGAIN;
+
+        iowrite32(1 << sysc_ch->chan_bit,
+                  rcar_sysc_base + sysc_ch->chan_offs + reg_offs);
+
+        return 0;
+}
+
+static int rcar_sysc_pwr_off(struct rcar_sysc_ch *sysc_ch)
+{
+        return rcar_sysc_pwr_on_off(sysc_ch, 0, PWROFFCR_OFFS);
+}
+
+static int rcar_sysc_pwr_on(struct rcar_sysc_ch *sysc_ch)
+{
+        return rcar_sysc_pwr_on_off(sysc_ch, 1, PWRONCR_OFFS);
+}
+
+static int rcar_sysc_update(struct rcar_sysc_ch *sysc_ch,
+                            int (*on_off_fn)(struct rcar_sysc_ch *))
+{
+        unsigned int isr_mask = 1 << sysc_ch->isr_bit;
+        unsigned int chan_mask = 1 << sysc_ch->chan_bit;
+        unsigned int status;
+        unsigned long flags;
+        int ret = 0;
+        int k;
+
+        spin_lock_irqsave(&rcar_sysc_lock, flags);
+
+        iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
+
+        do {
+                ret = on_off_fn(sysc_ch);
+                if (ret)
+                        goto out;
+
+                status = ioread32(rcar_sysc_base +
+                                  sysc_ch->chan_offs + PWRER_OFFS);
+        } while (status & chan_mask);
+
+        for (k = 0; k < SYSCISR_RETRIES; k++) {
+                if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask)
+                        break;
+                udelay(SYSCISR_DELAY_US);
+        }
+
+        if (k == SYSCISR_RETRIES)
+                ret = -EIO;
+
+        iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
+
+ out:
+        spin_unlock_irqrestore(&rcar_sysc_lock, flags);
+
+        pr_debug("sysc power domain %d: %08x -> %d\n",
+                 sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret);
+        return ret;
+}
+
+int rcar_sysc_power_down(struct rcar_sysc_ch *sysc_ch)
+{
+        return rcar_sysc_update(sysc_ch, rcar_sysc_pwr_off);
+}
+
+int rcar_sysc_power_up(struct rcar_sysc_ch *sysc_ch)
+{
+        return rcar_sysc_update(sysc_ch, rcar_sysc_pwr_on);
+}
+
+bool rcar_sysc_power_is_off(struct rcar_sysc_ch *sysc_ch)
+{
+        unsigned int st;
+
+        st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
+        if (st & (1 << sysc_ch->chan_bit))
+                return true;
+
+        return false;
+}
+
+void __iomem *rcar_sysc_init(phys_addr_t base)
+{
+        rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE);
+        if (!rcar_sysc_base)
+                panic("unable to ioremap R-Car SYSC hardware block\n");
+
+        return rcar_sysc_base;
+}
+
+#endif /* CONFIG_PM || CONFIG_SMP */
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 69ccc6c6fd33..10604480f325 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -28,7 +28,7 @@
 
 #define MODEMR 0xe6160060
 
-u32 __init rcar_gen2_read_mode_pins(void)
+u32 rcar_gen2_read_mode_pins(void)
 {
         void __iomem *modemr = ioremap_nocache(MODEMR, 4);
         u32 mode;
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 627c1f0d9478..e7a3201473d0 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -24,6 +24,7 @@
 #include <linux/io.h>
 #include <linux/delay.h>
 #include <mach/common.h>
+#include <mach/pm-rcar.h>
 #include <mach/r8a7779.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
@@ -33,25 +34,25 @@
 #define AVECR IOMEM(0xfe700040)
 #define R8A7779_SCU_BASE 0xf0000000
 
-static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
+static struct rcar_sysc_ch r8a7779_ch_cpu1 = {
         .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
         .chan_bit = 1, /* ARM1 */
         .isr_bit = 1, /* ARM1 */
 };
 
-static struct r8a7779_pm_ch r8a7779_ch_cpu2 = {
+static struct rcar_sysc_ch r8a7779_ch_cpu2 = {
         .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
         .chan_bit = 2, /* ARM2 */
         .isr_bit = 2, /* ARM2 */
 };
 
-static struct r8a7779_pm_ch r8a7779_ch_cpu3 = {
+static struct rcar_sysc_ch r8a7779_ch_cpu3 = {
         .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
         .chan_bit = 3, /* ARM3 */
         .isr_bit = 3, /* ARM3 */
 };
 
-static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = {
+static struct rcar_sysc_ch *r8a7779_ch_cpu[4] = {
         [1] = &r8a7779_ch_cpu1,
         [2] = &r8a7779_ch_cpu2,
         [3] = &r8a7779_ch_cpu3,
@@ -67,7 +68,7 @@ void __init r8a7779_register_twd(void)
 
 static int r8a7779_platform_cpu_kill(unsigned int cpu)
 {
-        struct r8a7779_pm_ch *ch = NULL;
+        struct rcar_sysc_ch *ch = NULL;
         int ret = -EIO;
 
         cpu = cpu_logical_map(cpu);
@@ -76,14 +77,14 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
                 ch = r8a7779_ch_cpu[cpu];
 
         if (ch)
-                ret = r8a7779_sysc_power_down(ch);
+                ret = rcar_sysc_power_down(ch);
 
         return ret ? ret : 1;
 }
 
 static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        struct r8a7779_pm_ch *ch = NULL;
+        struct rcar_sysc_ch *ch = NULL;
         unsigned int lcpu = cpu_logical_map(cpu);
         int ret;
 
@@ -91,7 +92,7 @@ static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
                 ch = r8a7779_ch_cpu[lcpu];
 
         if (ch)
-                ret = r8a7779_sysc_power_up(ch);
+                ret = rcar_sysc_power_up(ch);
         else
                 ret = -EIO;
 
diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c
index 015e2753de1f..591052799e8f 100644
--- a/arch/arm/mach-shmobile/smp-r8a7790.c
+++ b/arch/arm/mach-shmobile/smp-r8a7790.c
@@ -19,6 +19,8 @@
 #include <linux/io.h>
 #include <asm/smp_plat.h>
 #include <mach/common.h>
+#include <mach/pm-rcar.h>
+#include <mach/r8a7790.h>
 
 #define RST             0xe6160000
 #define CA15BAR         0x0020
@@ -27,6 +29,16 @@
 #define CA7RESCNT       0x0044
 #define MERAM           0xe8080000
 
+static struct rcar_sysc_ch r8a7790_ca15_scu = {
+        .chan_offs = 0x180, /* PWRSR5 .. PWRER5 */
+        .isr_bit = 12, /* CA15-SCU */
+};
+
+static struct rcar_sysc_ch r8a7790_ca7_scu = {
+        .chan_offs = 0x100, /* PWRSR3 .. PWRER3 */
+        .isr_bit = 21, /* CA7-SCU */
+};
+
 static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus)
 {
         void __iomem *p;
@@ -54,6 +66,11 @@ static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus)
         writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) | 0x5a5a0000,
                        p + CA7RESCNT);
         iounmap(p);
+
+        /* turn on power to SCU */
+        r8a7790_pm_init();
+        rcar_sysc_power_up(&r8a7790_ca15_scu);
+        rcar_sysc_power_up(&r8a7790_ca7_scu);
 }
 
 struct smp_operations r8a7790_smp_ops __initdata = {
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index aee77f06f887..b5f8d75d51a0 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -1,17 +1,10 @@
 config ARCH_SOCFPGA
         bool "Altera SOCFPGA family" if ARCH_MULTI_V7
-        select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_AMBA
         select ARM_GIC
         select CACHE_L2X0
-        select COMMON_CLK
-        select CPU_V7
         select DW_APB_TIMER_OF
-        select GENERIC_CLOCKEVENTS
         select GPIO_PL061 if GPIOLIB
         select HAVE_ARM_SCU
         select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
         select MFD_SYSCON
-        select SPARSE_IRQ
-        select USE_OF
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index ac1710e64d9a..5c57262b97e9 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -8,8 +8,6 @@ menuconfig PLAT_SPEAR
         select ARCH_REQUIRE_GPIOLIB
         select ARM_AMBA
         select CLKSRC_MMIO
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
 
 if PLAT_SPEAR
 
@@ -18,14 +16,10 @@ config ARCH_SPEAR13XX
         depends on ARCH_MULTI_V7 || PLAT_SPEAR_SINGLE
         select ARCH_HAS_CPUFREQ
         select ARM_GIC
-        select CPU_V7
         select GPIO_SPEAR_SPICS
         select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
-        select MIGHT_HAVE_CACHE_L2X0
         select PINCTRL
-        select USE_OF
         help
           Supports for ARM's SPEAR13XX family
 
@@ -50,9 +44,7 @@ config ARCH_SPEAR3XX
         depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
         depends on !ARCH_SPEAR13XX
         select ARM_VIC
-        select CPU_ARM926T
         select PINCTRL
-        select USE_OF
         help
           Supports for ARM's SPEAR3XX family
 
@@ -83,14 +75,12 @@ config ARCH_SPEAR6XX
         depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
         depends on !ARCH_SPEAR13XX
         select ARM_VIC
-        select CPU_ARM926T
         help
           Supports for ARM's SPEAR6XX family
 
 config MACH_SPEAR600
         def_bool y
         depends on ARCH_SPEAR6XX
-        select USE_OF
         help
           Supports ST SPEAr600 boards configured via the device-treesource "arch/arm/mach-spear6xx/Kconfig"
 
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
index d71654bc8d54..d2c13ba1190b 100644
--- a/arch/arm/mach-sti/Kconfig
+++ b/arch/arm/mach-sti/Kconfig
@@ -1,14 +1,10 @@
 menuconfig ARCH_STI
         bool "STMicroelectronics Consumer Electronics SOCs with Device Trees" if ARCH_MULTI_V7
-        select GENERIC_CLOCKEVENTS
-        select CLKDEV_LOOKUP
         select ARM_GIC
         select ARM_GLOBAL_TIMER
         select PINCTRL
         select PINCTRL_ST
         select MFD_SYSCON
-        select MIGHT_HAVE_CACHE_L2X0
-        select HAVE_SMP
         select HAVE_ARM_SCU if SMP
         select ARCH_REQUIRE_GPIOLIB
         select ARM_ERRATA_754322
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index b9d6cad8669b..9de27cfa688f 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -5,14 +5,9 @@ config ARCH_SUNXI
         select ARM_GIC
         select ARM_PSCI
         select CLKSRC_MMIO
-        select CLKSRC_OF
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
         select GENERIC_IRQ_CHIP
-        select HAVE_SMP
         select PINCTRL
         select PINCTRL_SUNXI
         select RESET_CONTROLLER
-        select SPARSE_IRQ
         select SUN4I_TIMER
         select SUN5I_HSTIMER
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index aeea6ceea725..460b5a4962ef 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -94,8 +94,8 @@ static void sun6i_restart(enum reboot_mode mode, const char *cmd)
 }
 
 static struct of_device_id sunxi_restart_ids[] = {
-        { .compatible = "allwinner,sun4i-wdt" },
-        { .compatible = "allwinner,sun6i-wdt" },
+        { .compatible = "allwinner,sun4i-a10-wdt" },
+        { .compatible = "allwinner,sun6i-a31-wdt" },
         { /*sentinel*/ }
 };
 
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index b1232d8be6f5..f61cd5b9f103 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -5,24 +5,16 @@ config ARCH_TEGRA
         select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
         select ARM_GIC
         select CLKSRC_MMIO
-        select CLKSRC_OF
-        select COMMON_CLK
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
         select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
-        select MIGHT_HAVE_CACHE_L2X0
         select MIGHT_HAVE_PCI
         select PINCTRL
         select ARCH_HAS_RESET_CONTROLLER
         select RESET_CONTROLLER
         select SOC_BUS
-        select SPARSE_IRQ
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
         select USB_ULPI if USB_PHY
         select USB_ULPI_VIEWPORT if USB_PHY
-        select USE_OF
         help
           This enables support for NVIDIA Tegra based systems.
 
diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
index e0b87300243d..b5fb7c110c64 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra114.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
@@ -19,6 +19,7 @@
 #include <linux/cpuidle.h>
 #include <linux/cpu_pm.h>
 #include <linux/clockchips.h>
+#include <asm/firmware.h>
 
 #include <asm/cpuidle.h>
 #include <asm/suspend.h>
@@ -45,7 +46,11 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev,
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
 
-        cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
+        call_firmware_op(prepare_idle);
+
+        /* Do suspend by ourselves if the firmware does not implement it */
+        if (call_firmware_op(do_idle) == -ENOSYS)
+                cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
 
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 4ae0286b468d..f55b05a29b55 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -24,6 +24,7 @@
 #include <linux/cpu_pm.h>
 #include <linux/suspend.h>
 #include <linux/err.h>
+#include <linux/slab.h>
 #include <linux/clk/tegra.h>
 
 #include <asm/smp_plat.h>
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 303a285d80fd..6191603379e1 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -73,10 +73,20 @@ u32 tegra_uart_config[3] = {
 static void __init tegra_init_cache(void)
 {
 #ifdef CONFIG_CACHE_L2X0
+        static const struct of_device_id pl310_ids[] __initconst = {
+                { .compatible = "arm,pl310-cache",  },
+                {}
+        };
+
+        struct device_node *np;
         int ret;
         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
         u32 aux_ctrl, cache_type;
 
+        np = of_find_matching_node(NULL, pl310_ids);
+        if (!np)
+                return;
+
         cache_type = readl(p + L2X0_CACHE_TYPE);
         aux_ctrl = (cache_type & 0x700) << (17-8);
         aux_ctrl |= 0x7C400001;
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 8e23071bd1b3..e3a96d7302e9 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -3,20 +3,14 @@ config ARCH_U300
         depends on MMU
         select ARCH_REQUIRE_GPIOLIB
         select ARM_AMBA
-        select ARM_PATCH_PHYS_VIRT
         select ARM_VIC
         select CLKSRC_MMIO
-        select CLKSRC_OF
-        select COMMON_CLK
         select CPU_ARM926T
-        select GENERIC_CLOCKEVENTS
         select HAVE_TCM
         select PINCTRL
         select PINCTRL_COH901
         select PINCTRL_U300
-        select SPARSE_IRQ
         select MFD_SYSCON
-        select USE_OF
         help
           Support for ST-Ericsson U300 series mobile platforms.
 
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 0034d2cd6973..8052bd52450d 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -11,13 +11,8 @@ config ARCH_U8500
         select ARM_GIC
         select CACHE_L2X0
         select CLKSRC_NOMADIK_MTU
-        select COMMON_CLK
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
         select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
-        select MIGHT_HAVE_CACHE_L2X0
         select PINCTRL
         select PINCTRL_ABX500
         select PINCTRL_NOMADIK
@@ -76,7 +71,6 @@ config UX500_AUTO_PLATFORM
 config MACH_UX500_DT
         bool "Generic U8500 support using device tree"
         depends on MACH_MOP500
-        select USE_OF
 
 endmenu
 
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 4a70be485ff8..80b4be36f10a 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -5,16 +5,11 @@ config ARCH_VEXPRESS
         select ARM_AMBA
         select ARM_GIC
         select ARM_TIMER_SP804
-        select COMMON_CLK
         select COMMON_CLK_VERSATILE
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
         select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
         select HAVE_PATA_PLATFORM
-        select HAVE_SMP
         select ICST
-        select MIGHT_HAVE_CACHE_L2X0
         select NO_IOPORT
         select PLAT_VERSATILE
         select PLAT_VERSATILE_CLCD
diff --git a/arch/arm/mach-virt/Kconfig b/arch/arm/mach-virt/Kconfig
deleted file mode 100644
index 081d46929436..000000000000
--- a/arch/arm/mach-virt/Kconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-config ARCH_VIRT
-        bool "Dummy Virtual Machine" if ARCH_MULTI_V7
-        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select ARM_GIC
-        select HAVE_ARM_ARCH_TIMER
-        select ARM_PSCI
-        select HAVE_SMP
-        select CPU_V7
-        select SPARSE_IRQ
-        select USE_OF
diff --git a/arch/arm/mach-virt/Makefile b/arch/arm/mach-virt/Makefile
deleted file mode 100644
index 7ddbfa60227f..000000000000
--- a/arch/arm/mach-virt/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-obj-y                                   := virt.o
diff --git a/arch/arm/mach-virt/virt.c b/arch/arm/mach-virt/virt.c
deleted file mode 100644
index b184e57d1854..000000000000
--- a/arch/arm/mach-virt/virt.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Dummy Virtual Machine - does what it says on the tin.
- *
- * Copyright (C) 2012 ARM Ltd
- * Authors: Will Deacon <will.deacon@arm.com>,
- *          Marc Zyngier <marc.zyngier@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <linux/smp.h>
-
-#include <asm/mach/arch.h>
-
-static void __init virt_init(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
-static const char *virt_dt_match[] = {
-        "linux,dummy-virt",
-        "xen,xenvm",
-        NULL
-};
-
-DT_MACHINE_START(VIRT, "Dummy Virtual Machine")
-        .init_machine   = virt_init,
-        .dt_compat      = virt_dt_match,
-MACHINE_END
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
index 927be93b692e..08f56a41cb55 100644
--- a/arch/arm/mach-vt8500/Kconfig
+++ b/arch/arm/mach-vt8500/Kconfig
@@ -3,8 +3,6 @@ config ARCH_VT8500
         select ARCH_HAS_CPUFREQ
         select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
-        select CLKSRC_OF
-        select GENERIC_CLOCKEVENTS
         select VT8500_TIMER
         select PINCTRL
         help
@@ -21,7 +19,6 @@ config ARCH_WM8750
         bool "WonderMedia WM8750"
         depends on ARCH_MULTI_V6
         select ARCH_VT8500
-        select CPU_V6
         help
           Support for WonderMedia WM8750 System-on-Chip.
 
@@ -29,6 +26,5 @@ config ARCH_WM8850
         bool "WonderMedia WM8850"
         depends on ARCH_MULTI_V7
         select ARCH_VT8500
-        select CPU_V7
         help
           Support for WonderMedia WM8850 System-on-Chip.
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 6b04260aa142..105d39b72a25 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -2,16 +2,9 @@ config ARCH_ZYNQ
         bool "Xilinx Zynq ARM Cortex A9 Platform" if ARCH_MULTI_V7
         select ARM_AMBA
         select ARM_GIC
-        select COMMON_CLK
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
         select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
         select ICST
-        select MIGHT_HAVE_CACHE_L2X0
-        select USE_OF
-        select HAVE_SMP
-        select SPARSE_IRQ
         select CADENCE_TTC_TIMER
         select ARM_GLOBAL_TIMER
         help
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 1db2a5ca9ab8..8c09a8393fb6 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -25,6 +25,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/of.h>
+#include <linux/memblock.h>
 #include <linux/irqchip.h>
 #include <linux/irqchip/arm-gic.h>
 
@@ -41,6 +42,18 @@
 
 void __iomem *zynq_scu_base;
 
+/**
+ * zynq_memory_init - Initialize special memory
+ *
+ * We need to stop things allocating the low memory as DMA can't work in
+ * the 1st 512K of memory.
+ */
+static void __init zynq_memory_init(void)
+{
+        if (!__pa(PAGE_OFFSET))
+                memblock_reserve(__pa(PAGE_OFFSET), __pa(swapper_pg_dir));
+}
+
 static struct platform_device zynq_cpuidle_device = {
         .name = "cpuidle-zynq",
 };
@@ -117,5 +130,6 @@ DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
         .init_machine   = zynq_init_machine,
         .init_time      = zynq_timer_init,
         .dt_compat      = zynq_dt_match,
+        .reserve        = zynq_memory_init,
         .restart        = zynq_system_reset,
 MACHINE_END
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 1f8fed94c2a4..dccd7e177653 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -855,7 +855,7 @@ config OUTER_CACHE_SYNC
 
 config CACHE_FEROCEON_L2
         bool "Enable the Feroceon L2 cache controller"
-        depends on ARCH_KIRKWOOD || ARCH_MV78XX0
+        depends on ARCH_KIRKWOOD || ARCH_MV78XX0 || ARCH_MVEBU
         default y
         select OUTER_CACHE
         help
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index 48bc3c0a87ce..8dc1a2b5a8ed 100644
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -13,10 +13,15 @@
  */
 
 #include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/highmem.h>
+#include <linux/io.h>
 #include <asm/cacheflush.h>
 #include <asm/cp15.h>
-#include <plat/cache-feroceon-l2.h>
+#include <asm/hardware/cache-feroceon-l2.h>
+
+#define L2_WRITETHROUGH_KIRKWOOD        BIT(4)
 
 /*
  * Low-level cache maintenance operations.
@@ -350,3 +355,41 @@ void __init feroceon_l2_init(int __l2_wt_override)
         printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n",
                          l2_wt_override ? ", in WT override mode" : "");
 }
+#ifdef CONFIG_OF
+static const struct of_device_id feroceon_ids[] __initconst = {
+        { .compatible = "marvell,kirkwood-cache"},
+        { .compatible = "marvell,feroceon-cache"},
+        {}
+};
+
+int __init feroceon_of_init(void)
+{
+        struct device_node *node;
+        void __iomem *base;
+        bool l2_wt_override = false;
+        struct resource res;
+
+#if defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
+        l2_wt_override = true;
+#endif
+
+        node = of_find_matching_node(NULL, feroceon_ids);
+        if (node && of_device_is_compatible(node, "marvell,kirkwood-cache")) {
+                if (of_address_to_resource(node, 0, &res))
+                        return -ENODEV;
+
+                base = ioremap(res.start, resource_size(&res));
+                if (!base)
+                        return -ENOMEM;
+
+                if (l2_wt_override)
+                        writel(readl(base) | L2_WRITETHROUGH_KIRKWOOD, base);
+                else
+                        writel(readl(base) & ~L2_WRITETHROUGH_KIRKWOOD, base);
+        }
+
+        feroceon_l2_init(l2_wt_override);
+
+        return 0;
+}
+#endif
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 1a77450e728a..11b3914660d2 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1358,7 +1358,7 @@ static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
         *handle = DMA_ERROR_CODE;
         size = PAGE_ALIGN(size);
 
-        if (gfp & GFP_ATOMIC)
+        if (!(gfp & __GFP_WAIT))
                 return __iommu_alloc_atomic(dev, size, handle);
 
         /*
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index d5a982d15a88..7ea641b7aa7d 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -38,6 +38,7 @@ static inline pmd_t *pmd_off_k(unsigned long virt)
 
 struct mem_type {
         pteval_t prot_pte;
+        pteval_t prot_pte_s2;
         pmdval_t prot_l1;
         pmdval_t prot_sect;
         unsigned int domain;
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 4f08c133cc25..a623cb3ad012 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -232,12 +232,16 @@ __setup("noalign", noalign_setup);
 #endif /* ifdef CONFIG_CPU_CP15 / else */
 
 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
+#define PROT_PTE_S2_DEVICE      PROT_PTE_DEVICE
 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 
 static struct mem_type mem_types[] = {
         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
                                   L_PTE_SHARED,
+                .prot_pte_s2    = s2_policy(PROT_PTE_S2_DEVICE) |
+                                  s2_policy(L_PTE_S2_MT_DEV_SHARED) |
+                                  L_PTE_SHARED,
                 .prot_l1        = PMD_TYPE_TABLE,
                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
                 .domain         = DOMAIN_IO,
@@ -508,7 +512,8 @@ static void __init build_mem_type_table(void)
         cp = &cache_policies[cachepolicy];
         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
         s2_pgprot = cp->pte_s2;
-        hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
+        hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
+        s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
 
         /*
          * ARMv6 and above have extended page tables.
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 45dc29f85d56..32b3558321c4 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -208,7 +208,6 @@ __v6_setup:
         mcr     p15, 0, r0, c7, c14, 0          @ clean+invalidate D cache
         mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
         mcr     p15, 0, r0, c7, c15, 0          @ clean+invalidate cache
-        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
 #ifdef CONFIG_MMU
         mcr     p15, 0, r0, c8, c7, 0           @ invalidate I + D TLBs
         mcr     p15, 0, r0, c2, c0, 2           @ TTB control register
@@ -218,6 +217,8 @@ __v6_setup:
         ALT_UP(orr      r8, r8, #TTB_FLAGS_UP)
         mcr     p15, 0, r8, c2, c0, 1           @ load TTB1
 #endif /* CONFIG_MMU */
+        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer and
+                                                @ complete invalidations
         adr     r5, v6_crval
         ldmia   r5, {r5, r6}
  ARM_BE8(orr    r6, r6, #1 << 25)               @ big-endian page tables
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index bd1781979a39..74f6033e76dd 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -351,7 +351,6 @@ __v7_setup:
 
 4:      mov     r10, #0
         mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
-        dsb
 #ifdef CONFIG_MMU
         mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
         v7_ttb_setup r10, r4, r8, r5            @ TTBCR, TTBRx setup
@@ -360,6 +359,7 @@ __v7_setup:
         mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
         mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
 #endif
+        dsb                                     @ Complete invalidations
 #ifndef CONFIG_ARM_THUMBEE
         mrc     p15, 0, r0, c0, c1, 0           @ read ID_PFR0 for ThumbEE
         and     r0, r0, #(0xf << 12)            @ ThumbEE enabled field
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index dd4327f09ba4..27bbcfc7202a 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -36,6 +36,7 @@ config ARM64
         select HAVE_GENERIC_DMA_COHERENT
         select HAVE_HW_BREAKPOINT if PERF_EVENTS
         select HAVE_MEMBLOCK
+        select HAVE_PATA_PLATFORM
         select HAVE_PERF_EVENTS
         select IRQ_DOMAIN
         select MODULES_USE_ELF_RELA
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 84139be62ae6..7959dd0ca5d5 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
@@ -19,6 +18,7 @@ CONFIG_BLK_DEV_INITRD=y
 CONFIG_KALLSYMS_ALL=y
 # CONFIG_COMPAT_BRK is not set
 CONFIG_PROFILING=y
+CONFIG_JUMP_LABEL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
@@ -27,6 +27,7 @@ CONFIG_ARCH_VEXPRESS=y
 CONFIG_ARCH_XGENE=y
 CONFIG_SMP=y
 CONFIG_PREEMPT=y
+CONFIG_CMA=y
 CONFIG_CMDLINE="console=ttyAMA0"
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_COMPAT=y
@@ -42,14 +43,17 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
-CONFIG_BLK_DEV=y
+CONFIG_DMA_CMA=y
 CONFIG_SCSI=y
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_ATA=y
+CONFIG_PATA_PLATFORM=y
+CONFIG_PATA_OF_PLATFORM=y
 CONFIG_NETDEVICES=y
-CONFIG_MII=y
 CONFIG_SMC91X=y
+CONFIG_SMSC911X=y
 # CONFIG_WLAN is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_SERIO_I8042 is not set
@@ -62,13 +66,19 @@ CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 # CONFIG_HWMON is not set
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_FB=y
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_MONO is not set
 # CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_ISP1760_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
diff --git a/arch/arm64/include/asm/atomic.h b/arch/arm64/include/asm/atomic.h
index 01de5aaa3edc..0237f0867e37 100644
--- a/arch/arm64/include/asm/atomic.h
+++ b/arch/arm64/include/asm/atomic.h
@@ -54,8 +54,7 @@ static inline void atomic_add(int i, atomic_t *v)
 "       stxr    %w1, %w0, %2\n"
 "       cbnz    %w1, 1b"
         : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
-        : "Ir" (i)
-        : "cc");
+        : "Ir" (i));
 }
 
 static inline int atomic_add_return(int i, atomic_t *v)
@@ -64,14 +63,15 @@ static inline int atomic_add_return(int i, atomic_t *v)
         int result;
 
         asm volatile("// atomic_add_return\n"
-"1:     ldaxr   %w0, %2\n"
+"1:     ldxr    %w0, %2\n"
 "       add     %w0, %w0, %w3\n"
 "       stlxr   %w1, %w0, %2\n"
 "       cbnz    %w1, 1b"
         : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
         : "Ir" (i)
-        : "cc", "memory");
+        : "memory");
 
+        smp_mb();
         return result;
 }
 
@@ -86,8 +86,7 @@ static inline void atomic_sub(int i, atomic_t *v)
 "       stxr    %w1, %w0, %2\n"
 "       cbnz    %w1, 1b"
         : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
-        : "Ir" (i)
-        : "cc");
+        : "Ir" (i));
 }
 
 static inline int atomic_sub_return(int i, atomic_t *v)
@@ -96,14 +95,15 @@ static inline int atomic_sub_return(int i, atomic_t *v)
         int result;
 
         asm volatile("// atomic_sub_return\n"
-"1:     ldaxr   %w0, %2\n"
+"1:     ldxr    %w0, %2\n"
 "       sub     %w0, %w0, %w3\n"
 "       stlxr   %w1, %w0, %2\n"
 "       cbnz    %w1, 1b"
         : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
         : "Ir" (i)
-        : "cc", "memory");
+        : "memory");
 
+        smp_mb();
         return result;
 }
 
@@ -112,17 +112,20 @@ static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
         unsigned long tmp;
         int oldval;
 
+        smp_mb();
+
         asm volatile("// atomic_cmpxchg\n"
-"1:     ldaxr   %w1, %2\n"
+"1:     ldxr    %w1, %2\n"
 "       cmp     %w1, %w3\n"
 "       b.ne    2f\n"
-"       stlxr   %w0, %w4, %2\n"
+"       stxr    %w0, %w4, %2\n"
 "       cbnz    %w0, 1b\n"
 "2:"
         : "=&r" (tmp), "=&r" (oldval), "+Q" (ptr->counter)
         : "Ir" (old), "r" (new)
-        : "cc", "memory");
+        : "cc");
 
+        smp_mb();
         return oldval;
 }
 
@@ -173,8 +176,7 @@ static inline void atomic64_add(u64 i, atomic64_t *v)
 "       stxr    %w1, %0, %2\n"
 "       cbnz    %w1, 1b"
         : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
-        : "Ir" (i)
-        : "cc");
+        : "Ir" (i));
 }
 
 static inline long atomic64_add_return(long i, atomic64_t *v)
@@ -183,14 +185,15 @@ static inline long atomic64_add_return(long i, atomic64_t *v)
         unsigned long tmp;
 
         asm volatile("// atomic64_add_return\n"
-"1:     ldaxr   %0, %2\n"
+"1:     ldxr    %0, %2\n"
 "       add     %0, %0, %3\n"
 "       stlxr   %w1, %0, %2\n"
 "       cbnz    %w1, 1b"
         : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
         : "Ir" (i)
-        : "cc", "memory");
+        : "memory");
 
+        smp_mb();
         return result;
 }
 
@@ -205,8 +208,7 @@ static inline void atomic64_sub(u64 i, atomic64_t *v)
 "       stxr    %w1, %0, %2\n"
 "       cbnz    %w1, 1b"
         : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
-        : "Ir" (i)
-        : "cc");
+        : "Ir" (i));
 }
 
 static inline long atomic64_sub_return(long i, atomic64_t *v)
@@ -215,14 +217,15 @@ static inline long atomic64_sub_return(long i, atomic64_t *v)
         unsigned long tmp;
 
         asm volatile("// atomic64_sub_return\n"
-"1:     ldaxr   %0, %2\n"
+"1:     ldxr    %0, %2\n"
 "       sub     %0, %0, %3\n"
 "       stlxr   %w1, %0, %2\n"
 "       cbnz    %w1, 1b"
         : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
         : "Ir" (i)
-        : "cc", "memory");
+        : "memory");
 
+        smp_mb();
         return result;
 }
 
@@ -231,17 +234,20 @@ static inline long atomic64_cmpxchg(atomic64_t *ptr, long old, long new)
         long oldval;
         unsigned long res;
 
+        smp_mb();
+
         asm volatile("// atomic64_cmpxchg\n"
-"1:     ldaxr   %1, %2\n"
+"1:     ldxr    %1, %2\n"
 "       cmp     %1, %3\n"
 "       b.ne    2f\n"
-"       stlxr   %w0, %4, %2\n"
+"       stxr    %w0, %4, %2\n"
 "       cbnz    %w0, 1b\n"
 "2:"
         : "=&r" (res), "=&r" (oldval), "+Q" (ptr->counter)
         : "Ir" (old), "r" (new)
-        : "cc", "memory");
+        : "cc");
 
+        smp_mb();
         return oldval;
 }
 
@@ -253,11 +259,12 @@ static inline long atomic64_dec_if_positive(atomic64_t *v)
         unsigned long tmp;
 
         asm volatile("// atomic64_dec_if_positive\n"
-"1:     ldaxr   %0, %2\n"
+"1:     ldxr    %0, %2\n"
 "       subs    %0, %0, #1\n"
 "       b.mi    2f\n"
 "       stlxr   %w1, %0, %2\n"
 "       cbnz    %w1, 1b\n"
+"       dmb     ish\n"
 "2:"
         : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
         :
diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h
index 78e20ba8806b..409ca370cfe2 100644
--- a/arch/arm64/include/asm/barrier.h
+++ b/arch/arm64/include/asm/barrier.h
@@ -25,7 +25,7 @@
 #define wfi()           asm volatile("wfi" : : : "memory")
 
 #define isb()           asm volatile("isb" : : : "memory")
-#define dsb()           asm volatile("dsb sy" : : : "memory")
+#define dsb(opt)        asm volatile("dsb sy" : : : "memory")
 
 #define mb()            dsb()
 #define rmb()           asm volatile("dsb ld" : : : "memory")
diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
index fea9ee327206..889324981aa4 100644
--- a/arch/arm64/include/asm/cacheflush.h
+++ b/arch/arm64/include/asm/cacheflush.h
@@ -116,6 +116,7 @@ extern void flush_dcache_page(struct page *);
 static inline void __flush_icache_all(void)
 {
         asm("ic ialluis");
+        dsb();
 }
 
 #define flush_dcache_mmap_lock(mapping) \
diff --git a/arch/arm64/include/asm/cmpxchg.h b/arch/arm64/include/asm/cmpxchg.h
index 56166d7f4a25..57c0fa7bf711 100644
--- a/arch/arm64/include/asm/cmpxchg.h
+++ b/arch/arm64/include/asm/cmpxchg.h
@@ -29,44 +29,45 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
         switch (size) {
         case 1:
                 asm volatile("//        __xchg1\n"
-                "1:     ldaxrb  %w0, %2\n"
+                "1:     ldxrb   %w0, %2\n"
                 "       stlxrb  %w1, %w3, %2\n"
                 "       cbnz    %w1, 1b\n"
                         : "=&r" (ret), "=&r" (tmp), "+Q" (*(u8 *)ptr)
                         : "r" (x)
-                        : "cc", "memory");
+                        : "memory");
                 break;
         case 2:
                 asm volatile("//        __xchg2\n"
-                "1:     ldaxrh  %w0, %2\n"
+                "1:     ldxrh   %w0, %2\n"
                 "       stlxrh  %w1, %w3, %2\n"
                 "       cbnz    %w1, 1b\n"
                         : "=&r" (ret), "=&r" (tmp), "+Q" (*(u16 *)ptr)
                         : "r" (x)
-                        : "cc", "memory");
+                        : "memory");
                 break;
         case 4:
                 asm volatile("//        __xchg4\n"
-                "1:     ldaxr   %w0, %2\n"
+                "1:     ldxr    %w0, %2\n"
                 "       stlxr   %w1, %w3, %2\n"
                 "       cbnz    %w1, 1b\n"
                         : "=&r" (ret), "=&r" (tmp), "+Q" (*(u32 *)ptr)
                         : "r" (x)
-                        : "cc", "memory");
+                        : "memory");
                 break;
         case 8:
                 asm volatile("//        __xchg8\n"
-                "1:     ldaxr   %0, %2\n"
+                "1:     ldxr    %0, %2\n"
                 "       stlxr   %w1, %3, %2\n"
                 "       cbnz    %w1, 1b\n"
                         : "=&r" (ret), "=&r" (tmp), "+Q" (*(u64 *)ptr)
                         : "r" (x)
-                        : "cc", "memory");
+                        : "memory");
                 break;
         default:
                 BUILD_BUG();
         }
 
+        smp_mb();
         return ret;
 }
 
diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
index 78834123a32e..c4a7f940b387 100644
--- a/arch/arm64/include/asm/esr.h
+++ b/arch/arm64/include/asm/esr.h
@@ -42,7 +42,7 @@
 #define ESR_EL1_EC_SP_ALIGN     (0x26)
 #define ESR_EL1_EC_FP_EXC32     (0x28)
 #define ESR_EL1_EC_FP_EXC64     (0x2C)
-#define ESR_EL1_EC_SERRROR      (0x2F)
+#define ESR_EL1_EC_SERROR       (0x2F)
 #define ESR_EL1_EC_BREAKPT_EL0  (0x30)
 #define ESR_EL1_EC_BREAKPT_EL1  (0x31)
 #define ESR_EL1_EC_SOFTSTP_EL0  (0x32)
diff --git a/arch/arm64/include/asm/futex.h b/arch/arm64/include/asm/futex.h
index 78cc3aba5d69..5f750dc96e0f 100644
--- a/arch/arm64/include/asm/futex.h
+++ b/arch/arm64/include/asm/futex.h
@@ -24,10 +24,11 @@
 
 #define __futex_atomic_op(insn, ret, oldval, uaddr, tmp, oparg)         \
         asm volatile(                                                   \
-"1:     ldaxr   %w1, %2\n"                                              \
+"1:     ldxr    %w1, %2\n"                                              \
         insn "\n"                                                       \
 "2:     stlxr   %w3, %w0, %2\n"                                         \
 "       cbnz    %w3, 1b\n"                                              \
+"       dmb     ish\n"                                                  \
 "3:\n"                                                                  \
 "       .pushsection .fixup,\"ax\"\n"                                   \
 "       .align  2\n"                                                    \
@@ -40,7 +41,7 @@
 "       .popsection\n"                                                  \
         : "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp)       \
         : "r" (oparg), "Ir" (-EFAULT)                                   \
-        : "cc", "memory")
+        : "memory")
 
 static inline int
 futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
@@ -111,11 +112,12 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
                 return -EFAULT;
 
         asm volatile("// futex_atomic_cmpxchg_inatomic\n"
-"1:     ldaxr   %w1, %2\n"
+"1:     ldxr    %w1, %2\n"
 "       sub     %w3, %w1, %w4\n"
 "       cbnz    %w3, 3f\n"
 "2:     stlxr   %w3, %w5, %2\n"
 "       cbnz    %w3, 1b\n"
+"       dmb     ish\n"
 "3:\n"
 "       .pushsection .fixup,\"ax\"\n"
 "4:     mov     %w0, %w6\n"
@@ -127,7 +129,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
 "       .popsection\n"
         : "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp)
         : "r" (oldval), "r" (newval), "Ir" (-EFAULT)
-        : "cc", "memory");
+        : "memory");
 
         *uval = val;
         return ret;
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index c98ef4771c73..0eb398655378 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -231,7 +231,7 @@
 #define ESR_EL2_EC_SP_ALIGN     (0x26)
 #define ESR_EL2_EC_FP_EXC32     (0x28)
 #define ESR_EL2_EC_FP_EXC64     (0x2C)
-#define ESR_EL2_EC_SERRROR      (0x2F)
+#define ESR_EL2_EC_SERROR       (0x2F)
 #define ESR_EL2_EC_BREAKPT      (0x30)
 #define ESR_EL2_EC_BREAKPT_HYP  (0x31)
 #define ESR_EL2_EC_SOFTSTP      (0x32)
diff --git a/arch/arm64/include/asm/spinlock.h b/arch/arm64/include/asm/spinlock.h
index 3d5cf064d7a1..c45b7b1b7197 100644
--- a/arch/arm64/include/asm/spinlock.h
+++ b/arch/arm64/include/asm/spinlock.h
@@ -132,7 +132,7 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
         "       cbnz    %w0, 2b\n"
         : "=&r" (tmp), "+Q" (rw->lock)
         : "r" (0x80000000)
-        : "cc", "memory");
+        : "memory");
 }
 
 static inline int arch_write_trylock(arch_rwlock_t *rw)
@@ -146,7 +146,7 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
         "1:\n"
         : "=&r" (tmp), "+Q" (rw->lock)
         : "r" (0x80000000)
-        : "cc", "memory");
+        : "memory");
 
         return !tmp;
 }
@@ -187,7 +187,7 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
         "       cbnz    %w1, 2b\n"
         : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
         :
-        : "cc", "memory");
+        : "memory");
 }
 
 static inline void arch_read_unlock(arch_rwlock_t *rw)
@@ -201,7 +201,7 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
         "       cbnz    %w1, 1b\n"
         : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
         :
-        : "cc", "memory");
+        : "memory");
 }
 
 static inline int arch_read_trylock(arch_rwlock_t *rw)
@@ -216,7 +216,7 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
         "1:\n"
         : "=&r" (tmp), "+r" (tmp2), "+Q" (rw->lock)
         :
-        : "cc", "memory");
+        : "memory");
 
         return !tmp2;
 }
diff --git a/arch/arm64/include/asm/unistd32.h b/arch/arm64/include/asm/unistd32.h
index 58125bf008d3..bb8eb8a78e67 100644
--- a/arch/arm64/include/asm/unistd32.h
+++ b/arch/arm64/include/asm/unistd32.h
@@ -399,7 +399,10 @@ __SYSCALL(374, compat_sys_sendmmsg)
 __SYSCALL(375, sys_setns)
 __SYSCALL(376, compat_sys_process_vm_readv)
 __SYSCALL(377, compat_sys_process_vm_writev)
-__SYSCALL(378, sys_ni_syscall)                  /* 378 for kcmp */
+__SYSCALL(378, sys_kcmp)
+__SYSCALL(379, sys_finit_module)
+__SYSCALL(380, sys_sched_setattr)
+__SYSCALL(381, sys_sched_getattr)
 
 #define __NR_compat_syscalls            379
 
diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
index 495ab6f84a61..eaf54a30bedc 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -148,6 +148,15 @@ struct kvm_arch_memory_slot {
 #define KVM_REG_ARM_TIMER_CNT           ARM64_SYS_REG(3, 3, 14, 3, 2)
 #define KVM_REG_ARM_TIMER_CVAL          ARM64_SYS_REG(3, 3, 14, 0, 2)
 
+/* Device Control API: ARM VGIC */
+#define KVM_DEV_ARM_VGIC_GRP_ADDR       0
+#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS  1
+#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS   2
+#define   KVM_DEV_ARM_VGIC_CPUID_SHIFT  32
+#define   KVM_DEV_ARM_VGIC_CPUID_MASK   (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
+#define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
+#define   KVM_DEV_ARM_VGIC_OFFSET_MASK  (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
+
 /* KVM_IRQ_LINE irq field index values */
 #define KVM_ARM_IRQ_TYPE_SHIFT          24
 #define KVM_ARM_IRQ_TYPE_MASK           0xff
diff --git a/arch/arm64/kernel/kuser32.S b/arch/arm64/kernel/kuser32.S
index 63c48ffdf230..7787208e8cc6 100644
--- a/arch/arm64/kernel/kuser32.S
+++ b/arch/arm64/kernel/kuser32.S
@@ -38,12 +38,13 @@ __kuser_cmpxchg64:			// 0xffff0f60
         .inst   0xe92d00f0              //      push            {r4, r5, r6, r7}
         .inst   0xe1c040d0              //      ldrd            r4, r5, [r0]
         .inst   0xe1c160d0              //      ldrd            r6, r7, [r1]
-        .inst   0xe1b20e9f              // 1:   ldaexd          r0, r1, [r2]
+        .inst   0xe1b20f9f              // 1:   ldrexd          r0, r1, [r2]
         .inst   0xe0303004              //      eors            r3, r0, r4
         .inst   0x00313005              //      eoreqs          r3, r1, r5
         .inst   0x01a23e96              //      stlexdeq        r3, r6, [r2]
         .inst   0x03330001              //      teqeq           r3, #1
         .inst   0x0afffff9              //      beq             1b
+        .inst   0xf57ff05b              //      dmb             ish
         .inst   0xe2730000              //      rsbs            r0, r3, #0
         .inst   0xe8bd00f0              //      pop             {r4, r5, r6, r7}
         .inst   0xe12fff1e              //      bx              lr
@@ -55,11 +56,12 @@ __kuser_memory_barrier:			// 0xffff0fa0
 
         .align  5
 __kuser_cmpxchg:                        // 0xffff0fc0
-        .inst   0xe1923e9f              // 1:   ldaex           r3, [r2]
+        .inst   0xe1923f9f              // 1:   ldrex           r3, [r2]
         .inst   0xe0533000              //      subs            r3, r3, r0
         .inst   0x01823e91              //      stlexeq         r3, r1, [r2]
         .inst   0x03330001              //      teqeq           r3, #1
         .inst   0x0afffffa              //      beq             1b
+        .inst   0xf57ff05b              //      dmb             ish
         .inst   0xe2730000              //      rsbs            r0, r3, #0
         .inst   0xe12fff1e              //      bx              lr
 
diff --git a/arch/arm64/kernel/vdso.c b/arch/arm64/kernel/vdso.c
index 65d40cf6945a..a7149cae1615 100644
--- a/arch/arm64/kernel/vdso.c
+++ b/arch/arm64/kernel/vdso.c
@@ -238,6 +238,8 @@ void update_vsyscall(struct timekeeper *tk)
         vdso_data->use_syscall                  = use_syscall;
         vdso_data->xtime_coarse_sec             = xtime_coarse.tv_sec;
         vdso_data->xtime_coarse_nsec            = xtime_coarse.tv_nsec;
+        vdso_data->wtm_clock_sec                = tk->wall_to_monotonic.tv_sec;
+        vdso_data->wtm_clock_nsec               = tk->wall_to_monotonic.tv_nsec;
 
         if (!use_syscall) {
                 vdso_data->cs_cycle_last        = tk->clock->cycle_last;
@@ -245,8 +247,6 @@ void update_vsyscall(struct timekeeper *tk)
                 vdso_data->xtime_clock_nsec     = tk->xtime_nsec;
                 vdso_data->cs_mult              = tk->mult;
                 vdso_data->cs_shift             = tk->shift;
-                vdso_data->wtm_clock_sec        = tk->wall_to_monotonic.tv_sec;
-                vdso_data->wtm_clock_nsec       = tk->wall_to_monotonic.tv_nsec;
         }
 
         smp_wmb();
diff --git a/arch/arm64/kernel/vdso/Makefile b/arch/arm64/kernel/vdso/Makefile
index d8064af42e62..6d20b7d162d8 100644
--- a/arch/arm64/kernel/vdso/Makefile
+++ b/arch/arm64/kernel/vdso/Makefile
@@ -48,7 +48,7 @@ $(obj-vdso): %.o: %.S
 
 # Actual build commands
 quiet_cmd_vdsold = VDSOL $@
-      cmd_vdsold = $(CC) $(c_flags) -Wl,-T $^ -o $@
+      cmd_vdsold = $(CC) $(c_flags) -Wl,-n -Wl,-T $^ -o $@
 quiet_cmd_vdsoas = VDSOA $@
       cmd_vdsoas = $(CC) $(a_flags) -c -o $@ $<
 
diff --git a/arch/arm64/kernel/vdso/gettimeofday.S b/arch/arm64/kernel/vdso/gettimeofday.S
index f0a6d10b5211..fe652ffd34c2 100644
--- a/arch/arm64/kernel/vdso/gettimeofday.S
+++ b/arch/arm64/kernel/vdso/gettimeofday.S
@@ -103,6 +103,8 @@ ENTRY(__kernel_clock_gettime)
         bl      __do_get_tspec
         seqcnt_check w9, 1b
 
+        mov     x30, x2
+
         cmp     w0, #CLOCK_MONOTONIC
         b.ne    6f
 
@@ -118,6 +120,9 @@ ENTRY(__kernel_clock_gettime)
         ccmp    w0, #CLOCK_MONOTONIC_COARSE, #0x4, ne
         b.ne    8f
 
+        /* xtime_coarse_nsec is already right-shifted */
+        mov     x12, #0
+
         /* Get coarse timespec. */
         adr     vdso_data, _vdso_data
 3:      seqcnt_acquire
@@ -156,7 +161,7 @@ ENTRY(__kernel_clock_gettime)
         lsr     x11, x11, x12
         stp     x10, x11, [x1, #TSPEC_TV_SEC]
         mov     x0, xzr
-        ret     x2
+        ret
 7:
         mov     x30, x2
 8:      /* Syscall fallback. */
diff --git a/arch/arm64/lib/bitops.S b/arch/arm64/lib/bitops.S
index e5db797790d3..7dac371cc9a2 100644
--- a/arch/arm64/lib/bitops.S
+++ b/arch/arm64/lib/bitops.S
@@ -46,11 +46,12 @@ ENTRY(	\name	)
         mov     x2, #1
         add     x1, x1, x0, lsr #3      // Get word offset
         lsl     x4, x2, x3              // Create mask
-1:      ldaxr   x2, [x1]
+1:      ldxr    x2, [x1]
         lsr     x0, x2, x3              // Save old value of bit
         \instr  x2, x2, x4              // toggle bit
         stlxr   w5, x2, [x1]
         cbnz    w5, 1b
+        dmb     ish
         and     x0, x0, #1
 3:      ret
 ENDPROC(\name   )
diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
index 45b5ab54c9ee..fbd76785c5db 100644
--- a/arch/arm64/mm/dma-mapping.c
+++ b/arch/arm64/mm/dma-mapping.c
@@ -45,6 +45,7 @@ static void *arm64_swiotlb_alloc_coherent(struct device *dev, size_t size,
         if (IS_ENABLED(CONFIG_DMA_CMA)) {
                 struct page *page;
 
+                size = PAGE_ALIGN(size);
                 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
                                                         get_order(size));
                 if (!page)
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index f557ebbe7013..f8dc7e8fce6f 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -203,10 +203,18 @@ static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
         do {
                 next = pmd_addr_end(addr, end);
                 /* try section mapping first */
-                if (((addr | next | phys) & ~SECTION_MASK) == 0)
+                if (((addr | next | phys) & ~SECTION_MASK) == 0) {
+                        pmd_t old_pmd =*pmd;
                         set_pmd(pmd, __pmd(phys | prot_sect_kernel));
-                else
+                        /*
+                         * Check for previous table entries created during
+                         * boot (__create_page_tables) and flush them.
+                         */
+                        if (!pmd_none(old_pmd))
+                                flush_tlb_all();
+                } else {
                         alloc_init_pte(pmd, addr, next, __phys_to_pfn(phys));
+                }
                 phys += next - addr;
         } while (pmd++, addr = next, addr != end);
 }
diff --git a/arch/arm64/mm/pgd.c b/arch/arm64/mm/pgd.c
index 7083cdada657..62c6101df260 100644
--- a/arch/arm64/mm/pgd.c
+++ b/arch/arm64/mm/pgd.c
@@ -32,17 +32,10 @@
 
 pgd_t *pgd_alloc(struct mm_struct *mm)
 {
-        pgd_t *new_pgd;
-
         if (PGD_SIZE == PAGE_SIZE)
-                new_pgd = (pgd_t *)get_zeroed_page(GFP_KERNEL);
+                return (pgd_t *)get_zeroed_page(GFP_KERNEL);
         else
-                new_pgd = kzalloc(PGD_SIZE, GFP_KERNEL);
-
-        if (!new_pgd)
-                return NULL;
-
-        return new_pgd;
+                return kzalloc(PGD_SIZE, GFP_KERNEL);
 }
 
 void pgd_free(struct mm_struct *mm, pgd_t *pgd)
diff --git a/arch/avr32/Makefile b/arch/avr32/Makefile
index 22fb66590dcd..dba48a5d5bb9 100644
--- a/arch/avr32/Makefile
+++ b/arch/avr32/Makefile
@@ -11,7 +11,7 @@ all: uImage vmlinux.elf
 
 KBUILD_DEFCONFIG        := atstk1002_defconfig
 
-KBUILD_CFLAGS   += -pipe -fno-builtin -mno-pic
+KBUILD_CFLAGS   += -pipe -fno-builtin -mno-pic -D__linux__
 KBUILD_AFLAGS   += -mrelax -mno-pic
 KBUILD_CFLAGS_MODULE += -mno-relax
 LDFLAGS_vmlinux += --relax
diff --git a/arch/avr32/boards/mimc200/fram.c b/arch/avr32/boards/mimc200/fram.c
index 9764a1a1073e..c1466a872b9c 100644
--- a/arch/avr32/boards/mimc200/fram.c
+++ b/arch/avr32/boards/mimc200/fram.c
@@ -11,6 +11,7 @@
 #define FRAM_VERSION    "1.0"
 
 #include <linux/miscdevice.h>
+#include <linux/module.h>
 #include <linux/proc_fs.h>
 #include <linux/mm.h>
 #include <linux/io.h>
diff --git a/arch/avr32/include/asm/Kbuild b/arch/avr32/include/asm/Kbuild
index cfb9fe1b8df9..c7c64a63c29f 100644
--- a/arch/avr32/include/asm/Kbuild
+++ b/arch/avr32/include/asm/Kbuild
@@ -17,5 +17,6 @@ generic-y       += scatterlist.h
 generic-y       += sections.h
 generic-y       += topology.h
 generic-y       += trace_clock.h
+generic-y += vga.h
 generic-y       += xor.h
 generic-y       += hash.h
diff --git a/arch/avr32/include/asm/io.h b/arch/avr32/include/asm/io.h
index fc6483f83ccc..4f5ec2bb7172 100644
--- a/arch/avr32/include/asm/io.h
+++ b/arch/avr32/include/asm/io.h
@@ -295,6 +295,8 @@ extern void __iounmap(void __iomem *addr);
 #define iounmap(addr)                           \
         __iounmap(addr)
 
+#define ioremap_wc ioremap_nocache
+
 #define cached(addr) P1SEGADDR(addr)
 #define uncached(addr) P2SEGADDR(addr)
 
diff --git a/arch/ia64/include/asm/unistd.h b/arch/ia64/include/asm/unistd.h
index afd45e0d552e..ae763d8bf55a 100644
--- a/arch/ia64/include/asm/unistd.h
+++ b/arch/ia64/include/asm/unistd.h
@@ -11,7 +11,7 @@
 
 
 
-#define NR_syscalls                     312 /* length of syscall table */
+#define NR_syscalls                     314 /* length of syscall table */
 
 /*
  * The following defines stop scripts/checksyscalls.sh from complaining about
diff --git a/arch/ia64/include/uapi/asm/unistd.h b/arch/ia64/include/uapi/asm/unistd.h
index 34fd6fe46da1..715e85f858de 100644
--- a/arch/ia64/include/uapi/asm/unistd.h
+++ b/arch/ia64/include/uapi/asm/unistd.h
@@ -325,5 +325,7 @@
 #define __NR_process_vm_writev          1333
 #define __NR_accept4                    1334
 #define __NR_finit_module               1335
+#define __NR_sched_setattr              1336
+#define __NR_sched_getattr              1337
 
 #endif /* _UAPI_ASM_IA64_UNISTD_H */
diff --git a/arch/ia64/kernel/entry.S b/arch/ia64/kernel/entry.S
index ddea607f948a..fa8d61a312a7 100644
--- a/arch/ia64/kernel/entry.S
+++ b/arch/ia64/kernel/entry.S
@@ -1773,6 +1773,8 @@ sys_call_table:
         data8 sys_process_vm_writev
         data8 sys_accept4
         data8 sys_finit_module                  // 1335
+        data8 sys_sched_setattr
+        data8 sys_sched_getattr
 
         .org sys_call_table + 8*NR_syscalls     // guard against failures to increase NR_syscalls
 #endif /* __IA64_ASM_PARAVIRTUALIZED_NATIVE */
diff --git a/arch/microblaze/include/asm/delay.h b/arch/microblaze/include/asm/delay.h
index 05b7d39e4391..66fc24c24238 100644
--- a/arch/microblaze/include/asm/delay.h
+++ b/arch/microblaze/include/asm/delay.h
@@ -13,6 +13,8 @@
 #ifndef _ASM_MICROBLAZE_DELAY_H
 #define _ASM_MICROBLAZE_DELAY_H
 
+#include <linux/param.h>
+
 extern inline void __delay(unsigned long loops)
 {
         asm volatile ("# __delay                \n\t"           \
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
index a2cea7206077..3fbb7f1db3bc 100644
--- a/arch/microblaze/include/asm/io.h
+++ b/arch/microblaze/include/asm/io.h
@@ -89,6 +89,11 @@ static inline unsigned int readl(const volatile void __iomem *addr)
 {
         return le32_to_cpu(*(volatile unsigned int __force *)addr);
 }
+#define readq readq
+static inline u64 readq(const volatile void __iomem *addr)
+{
+        return le64_to_cpu(__raw_readq(addr));
+}
 static inline void writeb(unsigned char v, volatile void __iomem *addr)
 {
         *(volatile unsigned char __force *)addr = v;
@@ -101,6 +106,7 @@ static inline void writel(unsigned int v, volatile void __iomem *addr)
 {
         *(volatile unsigned int __force *)addr = cpu_to_le32(v);
 }
+#define writeq(b, addr) __raw_writeq(cpu_to_le64(b), addr)
 
 /* ioread and iowrite variants. thease are for now same as __raw_
  * variants of accessors. we might check for endianess in the feature
diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S
index b7fb0438458c..17645b2e2f07 100644
--- a/arch/microblaze/kernel/head.S
+++ b/arch/microblaze/kernel/head.S
@@ -66,7 +66,7 @@ real_start:
         mts     rmsr, r0
 /* Disable stack protection from bootloader */
         mts     rslr, r0
-        addi    r8, r0, 0xFFFFFFF
+        addi    r8, r0, 0xFFFFFFFF
         mts     rshr, r8
 /*
  * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c
index 11f3ad20321c..5483906e0f86 100644
--- a/arch/mips/alchemy/devboards/db1000.c
+++ b/arch/mips/alchemy/devboards/db1000.c
@@ -534,13 +534,10 @@ static int __init db1000_dev_init(void)
                 s0 = AU1100_GPIO1_INT;
                 s1 = AU1100_GPIO4_INT;
 
+                gpio_request(19, "sd0_cd");
+                gpio_request(20, "sd1_cd");
                 gpio_direction_input(19);       /* sd0 cd# */
                 gpio_direction_input(20);       /* sd1 cd# */
-                gpio_direction_input(21);       /* touch pendown# */
-                gpio_direction_input(207);      /* SPI MISO */
-                gpio_direction_output(208, 0);  /* SPI MOSI */
-                gpio_direction_output(209, 1);  /* SPI SCK */
-                gpio_direction_output(210, 1);  /* SPI CS# */
 
                 /* spi_gpio on SSI0 pins */
                 pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index cfe092fc720d..6b9749540edf 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -74,6 +74,8 @@ static inline int __enable_fpu(enum fpu_mode mode)
         default:
                 BUG();
         }
+
+        return SIGFPE;
 }
 
 #define __disable_fpu()                                                 \
diff --git a/arch/mips/include/uapi/asm/unistd.h b/arch/mips/include/uapi/asm/unistd.h
index 1dee279f9665..d6e154a9e6a5 100644
--- a/arch/mips/include/uapi/asm/unistd.h
+++ b/arch/mips/include/uapi/asm/unistd.h
@@ -369,16 +369,18 @@
 #define __NR_process_vm_writev          (__NR_Linux + 346)
 #define __NR_kcmp                       (__NR_Linux + 347)
 #define __NR_finit_module               (__NR_Linux + 348)
+#define __NR_sched_setattr              (__NR_Linux + 349)
+#define __NR_sched_getattr              (__NR_Linux + 350)
 
 /*
  * Offset of the last Linux o32 flavoured syscall
  */
-#define __NR_Linux_syscalls             348
+#define __NR_Linux_syscalls             350
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 
 #define __NR_O32_Linux                  4000
-#define __NR_O32_Linux_syscalls         348
+#define __NR_O32_Linux_syscalls         350
 
 #if _MIPS_SIM == _MIPS_SIM_ABI64
 
@@ -695,16 +697,18 @@
 #define __NR_kcmp                       (__NR_Linux + 306)
 #define __NR_finit_module               (__NR_Linux + 307)
 #define __NR_getdents64                 (__NR_Linux + 308)
+#define __NR_sched_setattr              (__NR_Linux + 309)
+#define __NR_sched_getattr              (__NR_Linux + 310)
 
 /*
  * Offset of the last Linux 64-bit flavoured syscall
  */
-#define __NR_Linux_syscalls             308
+#define __NR_Linux_syscalls             310
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
 
 #define __NR_64_Linux                   5000
-#define __NR_64_Linux_syscalls          308
+#define __NR_64_Linux_syscalls          310
 
 #if _MIPS_SIM == _MIPS_SIM_NABI32
 
@@ -1025,15 +1029,17 @@
 #define __NR_process_vm_writev          (__NR_Linux + 310)
 #define __NR_kcmp                       (__NR_Linux + 311)
 #define __NR_finit_module               (__NR_Linux + 312)
+#define __NR_sched_setattr              (__NR_Linux + 313)
+#define __NR_sched_getattr              (__NR_Linux + 314)
 
 /*
  * Offset of the last N32 flavoured syscall
  */
-#define __NR_Linux_syscalls             312
+#define __NR_Linux_syscalls             314
 
 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
 
 #define __NR_N32_Linux                  6000
-#define __NR_N32_Linux_syscalls         312
+#define __NR_N32_Linux_syscalls         314
 
 #endif /* _UAPI_ASM_UNISTD_H */
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index e8e541b40d86..a5b14f48e1af 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -563,3 +563,5 @@ EXPORT(sys_call_table)
         PTR     sys_process_vm_writev
         PTR     sys_kcmp
         PTR     sys_finit_module
+        PTR     sys_sched_setattr
+        PTR     sys_sched_getattr               /* 4350 */
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 57e3742fec59..b56e254beb15 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -425,4 +425,6 @@ EXPORT(sys_call_table)
         PTR     sys_kcmp
         PTR     sys_finit_module
         PTR     sys_getdents64
+        PTR     sys_sched_setattr
+        PTR     sys_sched_getattr               /* 5310 */
         .size   sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 2f48f5934399..f7e5b72cf481 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -418,4 +418,6 @@ EXPORT(sysn32_call_table)
         PTR     compat_sys_process_vm_writev    /* 6310 */
         PTR     sys_kcmp
         PTR     sys_finit_module
+        PTR     sys_sched_setattr
+        PTR     sys_sched_getattr
         .size   sysn32_call_table,.-sysn32_call_table
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index f1acdb429f4f..6788727d91af 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -541,4 +541,6 @@ EXPORT(sys32_call_table)
         PTR     compat_sys_process_vm_writev
         PTR     sys_kcmp
         PTR     sys_finit_module
+        PTR     sys_sched_setattr
+        PTR     sys_sched_getattr               /* 4350 */
         .size   sys32_call_table,.-sys32_call_table
diff --git a/arch/parisc/hpux/fs.c b/arch/parisc/hpux/fs.c
index 88d0962de65a..2bedafea3d94 100644
--- a/arch/parisc/hpux/fs.c
+++ b/arch/parisc/hpux/fs.c
@@ -33,22 +33,9 @@
 
 int hpux_execve(struct pt_regs *regs)
 {
-        int error;
-        struct filename *filename;
-
-        filename = getname((const char __user *) regs->gr[26]);
-        error = PTR_ERR(filename);
-        if (IS_ERR(filename))
-                goto out;
-
-        error = do_execve(filename->name,
+        return  do_execve(getname((const char __user *) regs->gr[26]),
                           (const char __user *const __user *) regs->gr[25],
                           (const char __user *const __user *) regs->gr[24]);
-
-        putname(filename);
-
-out:
-        return error;
 }
 
 struct hpux_dirent {
diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h
index e27e9ad6818e..150866b2a3fe 100644
--- a/arch/powerpc/include/asm/dma-mapping.h
+++ b/arch/powerpc/include/asm/dma-mapping.h
@@ -134,6 +134,7 @@ static inline int dma_supported(struct device *dev, u64 mask)
 }
 
 extern int dma_set_mask(struct device *dev, u64 dma_mask);
+extern int __dma_set_mask(struct device *dev, u64 dma_mask);
 
 #define dma_alloc_coherent(d,s,h,f)     dma_alloc_attrs(d,s,h,f,NULL)
 
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
index 9e39ceb1d19f..d4dd41fb951b 100644
--- a/arch/powerpc/include/asm/eeh.h
+++ b/arch/powerpc/include/asm/eeh.h
@@ -172,10 +172,20 @@ struct eeh_ops {
 };
 
 extern struct eeh_ops *eeh_ops;
-extern int eeh_subsystem_enabled;
+extern bool eeh_subsystem_enabled;
 extern raw_spinlock_t confirm_error_lock;
 extern int eeh_probe_mode;
 
+static inline bool eeh_enabled(void)
+{
+        return eeh_subsystem_enabled;
+}
+
+static inline void eeh_set_enable(bool mode)
+{
+        eeh_subsystem_enabled = mode;
+}
+
 #define EEH_PROBE_MODE_DEV      (1<<0)  /* From PCI device      */
 #define EEH_PROBE_MODE_DEVTREE  (1<<1)  /* From device tree     */
 
@@ -246,7 +256,7 @@ void eeh_remove_device(struct pci_dev *);
  * If this macro yields TRUE, the caller relays to eeh_check_failure()
  * which does further tests out of line.
  */
-#define EEH_POSSIBLE_ERROR(val, type)   ((val) == (type)~0 && eeh_subsystem_enabled)
+#define EEH_POSSIBLE_ERROR(val, type)   ((val) == (type)~0 && eeh_enabled())
 
 /*
  * Reads from a device which has been isolated by EEH will return
@@ -257,6 +267,13 @@ void eeh_remove_device(struct pci_dev *);
 
 #else /* !CONFIG_EEH */
 
+static inline bool eeh_enabled(void)
+{
+        return false;
+}
+
+static inline void eeh_set_enable(bool mode) { }
+
 static inline int eeh_init(void)
 {
         return 0;
diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index d750336b171d..623f2971ce0e 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -127,7 +127,7 @@ static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
                                             unsigned long addr, pte_t *ptep)
 {
 #ifdef CONFIG_PPC64
-        return __pte(pte_update(mm, addr, ptep, ~0UL, 1));
+        return __pte(pte_update(mm, addr, ptep, ~0UL, 0, 1));
 #else
         return __pte(pte_update(ptep, ~0UL, 0));
 #endif
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
index f7a8036579b5..42632c7a2a4e 100644
--- a/arch/powerpc/include/asm/iommu.h
+++ b/arch/powerpc/include/asm/iommu.h
@@ -77,6 +77,7 @@ struct iommu_table {
 #ifdef CONFIG_IOMMU_API
         struct iommu_group *it_group;
 #endif
+        void (*set_bypass)(struct iommu_table *tbl, bool enable);
 };
 
 /* Pure 2^n version of get_order */
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index bc141c950b1e..eb9261024f51 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -195,6 +195,7 @@ extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
 static inline unsigned long pte_update(struct mm_struct *mm,
                                        unsigned long addr,
                                        pte_t *ptep, unsigned long clr,
+                                       unsigned long set,
                                        int huge)
 {
 #ifdef PTE_ATOMIC_UPDATES
@@ -205,14 +206,15 @@ static inline unsigned long pte_update(struct mm_struct *mm,
         andi.   %1,%0,%6\n\
         bne-    1b \n\
         andc    %1,%0,%4 \n\
+        or      %1,%1,%7\n\
         stdcx.  %1,0,%3 \n\
         bne-    1b"
         : "=&r" (old), "=&r" (tmp), "=m" (*ptep)
-        : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY)
+        : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY), "r" (set)
         : "cc" );
 #else
         unsigned long old = pte_val(*ptep);
-        *ptep = __pte(old & ~clr);
+        *ptep = __pte((old & ~clr) | set);
 #endif
         /* huge pages use the old page table lock */
         if (!huge)
@@ -231,9 +233,9 @@ static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
 {
         unsigned long old;
 
-        if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
+        if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
                 return 0;
-        old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0);
+        old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
         return (old & _PAGE_ACCESSED) != 0;
 }
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
@@ -252,7 +254,7 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
         if ((pte_val(*ptep) & _PAGE_RW) == 0)
                 return;
 
-        pte_update(mm, addr, ptep, _PAGE_RW, 0);
+        pte_update(mm, addr, ptep, _PAGE_RW, 0, 0);
 }
 
 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
@@ -261,7 +263,7 @@ static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
         if ((pte_val(*ptep) & _PAGE_RW) == 0)
                 return;
 
-        pte_update(mm, addr, ptep, _PAGE_RW, 1);
+        pte_update(mm, addr, ptep, _PAGE_RW, 0, 1);
 }
 
 /*
@@ -284,14 +286,14 @@ static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
                                        unsigned long addr, pte_t *ptep)
 {
-        unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0);
+        unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
         return __pte(old);
 }
 
 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
                              pte_t * ptep)
 {
-        pte_update(mm, addr, ptep, ~0UL, 0);
+        pte_update(mm, addr, ptep, ~0UL, 0, 0);
 }
 
 
@@ -506,7 +508,9 @@ extern int pmdp_set_access_flags(struct vm_area_struct *vma,
 
 extern unsigned long pmd_hugepage_update(struct mm_struct *mm,
                                          unsigned long addr,
-                                         pmd_t *pmdp, unsigned long clr);
+                                         pmd_t *pmdp,
+                                         unsigned long clr,
+                                         unsigned long set);
 
 static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
                                               unsigned long addr, pmd_t *pmdp)
@@ -515,7 +519,7 @@ static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
 
         if ((pmd_val(*pmdp) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
                 return 0;
-        old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED);
+        old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0);
         return ((old & _PAGE_ACCESSED) != 0);
 }
 
@@ -542,7 +546,7 @@ static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
         if ((pmd_val(*pmdp) & _PAGE_RW) == 0)
                 return;
 
-        pmd_hugepage_update(mm, addr, pmdp, _PAGE_RW);
+        pmd_hugepage_update(mm, addr, pmdp, _PAGE_RW, 0);
 }
 
 #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index f83b6f3e1b39..3ebb188c3ff5 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -75,12 +75,34 @@ static inline pte_t pte_mknuma(pte_t pte)
         return pte;
 }
 
+#define ptep_set_numa ptep_set_numa
+static inline void ptep_set_numa(struct mm_struct *mm, unsigned long addr,
+                                 pte_t *ptep)
+{
+        if ((pte_val(*ptep) & _PAGE_PRESENT) == 0)
+                VM_BUG_ON(1);
+
+        pte_update(mm, addr, ptep, _PAGE_PRESENT, _PAGE_NUMA, 0);
+        return;
+}
+
 #define pmd_numa pmd_numa
 static inline int pmd_numa(pmd_t pmd)
 {
         return pte_numa(pmd_pte(pmd));
 }
 
+#define pmdp_set_numa pmdp_set_numa
+static inline void pmdp_set_numa(struct mm_struct *mm, unsigned long addr,
+                                 pmd_t *pmdp)
+{
+        if ((pmd_val(*pmdp) & _PAGE_PRESENT) == 0)
+                VM_BUG_ON(1);
+
+        pmd_hugepage_update(mm, addr, pmdp, _PAGE_PRESENT, _PAGE_NUMA);
+        return;
+}
+
 #define pmd_mknonnuma pmd_mknonnuma
 static inline pmd_t pmd_mknonnuma(pmd_t pmd)
 {
diff --git a/arch/powerpc/include/asm/sections.h b/arch/powerpc/include/asm/sections.h
index 4ee06fe15de4..d0e784e0ff48 100644
--- a/arch/powerpc/include/asm/sections.h
+++ b/arch/powerpc/include/asm/sections.h
@@ -8,6 +8,7 @@
 
 #ifdef __powerpc64__
 
+extern char __start_interrupts[];
 extern char __end_interrupts[];
 
 extern char __prom_init_toc_start[];
@@ -21,6 +22,17 @@ static inline int in_kernel_text(unsigned long addr)
         return 0;
 }
 
+static inline int overlaps_interrupt_vector_text(unsigned long start,
+                                                        unsigned long end)
+{
+        unsigned long real_start, real_end;
+        real_start = __start_interrupts - _stext;
+        real_end = __end_interrupts - _stext;
+
+        return start < (unsigned long)__va(real_end) &&
+                (unsigned long)__va(real_start) < end;
+}
+
 static inline int overlaps_kernel_text(unsigned long start, unsigned long end)
 {
         return start < (unsigned long)__init_end &&
diff --git a/arch/powerpc/include/asm/vdso.h b/arch/powerpc/include/asm/vdso.h
index 0d9cecddf8a4..c53f5f6d1761 100644
--- a/arch/powerpc/include/asm/vdso.h
+++ b/arch/powerpc/include/asm/vdso.h
@@ -4,11 +4,11 @@
 #ifdef __KERNEL__
 
 /* Default link addresses for the vDSOs */
-#define VDSO32_LBASE    0x100000
-#define VDSO64_LBASE    0x100000
+#define VDSO32_LBASE    0x0
+#define VDSO64_LBASE    0x0
 
 /* Default map addresses for 32bit vDSO */
-#define VDSO32_MBASE    VDSO32_LBASE
+#define VDSO32_MBASE    0x100000
 
 #define VDSO_VERSION_STRING     LINUX_2.6.15
 
diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c
index 8032b97ccdcb..ee78f6e49d64 100644
--- a/arch/powerpc/kernel/dma.c
+++ b/arch/powerpc/kernel/dma.c
@@ -191,12 +191,10 @@ EXPORT_SYMBOL(dma_direct_ops);
 
 #define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
 
-int dma_set_mask(struct device *dev, u64 dma_mask)
+int __dma_set_mask(struct device *dev, u64 dma_mask)
 {
         struct dma_map_ops *dma_ops = get_dma_ops(dev);
 
-        if (ppc_md.dma_set_mask)
-                return ppc_md.dma_set_mask(dev, dma_mask);
         if ((dma_ops != NULL) && (dma_ops->set_dma_mask != NULL))
                 return dma_ops->set_dma_mask(dev, dma_mask);
         if (!dev->dma_mask || !dma_supported(dev, dma_mask))
@@ -204,6 +202,12 @@ int dma_set_mask(struct device *dev, u64 dma_mask)
         *dev->dma_mask = dma_mask;
         return 0;
 }
+int dma_set_mask(struct device *dev, u64 dma_mask)
+{
+        if (ppc_md.dma_set_mask)
+                return ppc_md.dma_set_mask(dev, dma_mask);
+        return __dma_set_mask(dev, dma_mask);
+}
 EXPORT_SYMBOL(dma_set_mask);
 
 u64 dma_get_required_mask(struct device *dev)
diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index 148db72a8c43..e7b76a6bf150 100644
--- a/arch/powerpc/kernel/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -28,6 +28,7 @@
 #include <linux/pci.h>
 #include <linux/proc_fs.h>
 #include <linux/rbtree.h>
+#include <linux/reboot.h>
 #include <linux/seq_file.h>
 #include <linux/spinlock.h>
 #include <linux/export.h>
@@ -89,7 +90,7 @@
 /* Platform dependent EEH operations */
 struct eeh_ops *eeh_ops = NULL;
 
-int eeh_subsystem_enabled;
+bool eeh_subsystem_enabled = false;
 EXPORT_SYMBOL(eeh_subsystem_enabled);
 
 /*
@@ -364,7 +365,7 @@ int eeh_dev_check_failure(struct eeh_dev *edev)
 
         eeh_stats.total_mmio_ffs++;
 
-        if (!eeh_subsystem_enabled)
+        if (!eeh_enabled())
                 return 0;
 
         if (!edev) {
@@ -747,6 +748,17 @@ int __exit eeh_ops_unregister(const char *name)
         return -EEXIST;
 }
 
+static int eeh_reboot_notifier(struct notifier_block *nb,
+                               unsigned long action, void *unused)
+{
+        eeh_set_enable(false);
+        return NOTIFY_DONE;
+}
+
+static struct notifier_block eeh_reboot_nb = {
+        .notifier_call = eeh_reboot_notifier,
+};
+
 /**
  * eeh_init - EEH initialization
  *
@@ -778,6 +790,14 @@ int eeh_init(void)
         if (machine_is(powernv) && cnt++ <= 0)
                 return ret;
 
+        /* Register reboot notifier */
+        ret = register_reboot_notifier(&eeh_reboot_nb);
+        if (ret) {
+                pr_warn("%s: Failed to register notifier (%d)\n",
+                        __func__, ret);
+                return ret;
+        }
+
         /* call platform initialization function */
         if (!eeh_ops) {
                 pr_warning("%s: Platform EEH operation not found\n",
@@ -822,7 +842,7 @@ int eeh_init(void)
                         return ret;
         }
 
-        if (eeh_subsystem_enabled)
+        if (eeh_enabled())
                 pr_info("EEH: PCI Enhanced I/O Error Handling Enabled\n");
         else
                 pr_warning("EEH: No capable adapters found\n");
@@ -897,7 +917,7 @@ void eeh_add_device_late(struct pci_dev *dev)
         struct device_node *dn;
         struct eeh_dev *edev;
 
-        if (!dev || !eeh_subsystem_enabled)
+        if (!dev || !eeh_enabled())
                 return;
 
         pr_debug("EEH: Adding device %s\n", pci_name(dev));
@@ -1005,7 +1025,7 @@ void eeh_remove_device(struct pci_dev *dev)
 {
         struct eeh_dev *edev;
 
-        if (!dev || !eeh_subsystem_enabled)
+        if (!dev || !eeh_enabled())
                 return;
         edev = pci_dev_to_eeh_dev(dev);
 
@@ -1045,7 +1065,7 @@ void eeh_remove_device(struct pci_dev *dev)
 
 static int proc_eeh_show(struct seq_file *m, void *v)
 {
-        if (0 == eeh_subsystem_enabled) {
+        if (!eeh_enabled()) {
                 seq_printf(m, "EEH Subsystem is globally disabled\n");
                 seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs);
         } else {
diff --git a/arch/powerpc/kernel/eeh_driver.c b/arch/powerpc/kernel/eeh_driver.c
index 7bb30dca4e19..fdc679d309ec 100644
--- a/arch/powerpc/kernel/eeh_driver.c
+++ b/arch/powerpc/kernel/eeh_driver.c
@@ -362,9 +362,13 @@ static void *eeh_rmv_device(void *data, void *userdata)
          */
         if (!dev || (dev->hdr_type & PCI_HEADER_TYPE_BRIDGE))
                 return NULL;
+
         driver = eeh_pcid_get(dev);
-        if (driver && driver->err_handler)
-                return NULL;
+        if (driver) {
+                eeh_pcid_put(dev);
+                if (driver->err_handler)
+                        return NULL;
+        }
 
         /* Remove it from PCI subsystem */
         pr_debug("EEH: Removing %s without EEH sensitive driver\n",
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index d773dd440a45..88e3ec6e1d96 100644
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -1088,6 +1088,14 @@ int iommu_take_ownership(struct iommu_table *tbl)
         memset(tbl->it_map, 0xff, sz);
         iommu_clear_tces_and_put_pages(tbl, tbl->it_offset, tbl->it_size);
 
+        /*
+         * Disable iommu bypass, otherwise the user can DMA to all of
+         * our physical memory via the bypass window instead of just
+         * the pages that has been explicitly mapped into the iommu
+         */
+        if (tbl->set_bypass)
+                tbl->set_bypass(tbl, false);
+
         return 0;
 }
 EXPORT_SYMBOL_GPL(iommu_take_ownership);
@@ -1102,6 +1110,10 @@ void iommu_release_ownership(struct iommu_table *tbl)
         /* Restore bit#0 set by iommu_init_table() */
         if (tbl->it_offset == 0)
                 set_bit(0, tbl->it_map);
+
+        /* The kernel owns the device now, we can restore the iommu bypass */
+        if (tbl->set_bypass)
+                tbl->set_bypass(tbl, true);
 }
 EXPORT_SYMBOL_GPL(iommu_release_ownership);
 
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 9729b23bfb0a..1d0848bba049 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -559,8 +559,13 @@ void exc_lvl_ctx_init(void)
 #ifdef CONFIG_PPC64
                 cpu_nr = i;
 #else
+#ifdef CONFIG_SMP
                 cpu_nr = get_hard_smp_processor_id(i);
+#else
+                cpu_nr = 0;
 #endif
+#endif
+
                 memset((void *)critirq_ctx[cpu_nr], 0, THREAD_SIZE);
                 tp = critirq_ctx[cpu_nr];
                 tp->cpu = cpu_nr;
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c
index 75d4f7340da8..015ae55c1868 100644
--- a/arch/powerpc/kernel/machine_kexec.c
+++ b/arch/powerpc/kernel/machine_kexec.c
@@ -196,7 +196,9 @@ int overlaps_crashkernel(unsigned long start, unsigned long size)
 
 /* Values we need to export to the second kernel via the device tree. */
 static phys_addr_t kernel_end;
+static phys_addr_t crashk_base;
 static phys_addr_t crashk_size;
+static unsigned long long mem_limit;
 
 static struct property kernel_end_prop = {
         .name = "linux,kernel-end",
@@ -207,7 +209,7 @@ static struct property kernel_end_prop = {
 static struct property crashk_base_prop = {
         .name = "linux,crashkernel-base",
         .length = sizeof(phys_addr_t),
-        .value = &crashk_res.start,
+        .value = &crashk_base
 };
 
 static struct property crashk_size_prop = {
@@ -219,9 +221,11 @@ static struct property crashk_size_prop = {
 static struct property memory_limit_prop = {
         .name = "linux,memory-limit",
         .length = sizeof(unsigned long long),
-        .value = &memory_limit,
+        .value = &mem_limit,
 };
 
+#define cpu_to_be_ulong __PASTE(cpu_to_be, BITS_PER_LONG)
+
 static void __init export_crashk_values(struct device_node *node)
 {
         struct property *prop;
@@ -237,8 +241,9 @@ static void __init export_crashk_values(struct device_node *node)
                 of_remove_property(node, prop);
 
         if (crashk_res.start != 0) {
+                crashk_base = cpu_to_be_ulong(crashk_res.start),
                 of_add_property(node, &crashk_base_prop);
-                crashk_size = resource_size(&crashk_res);
+                crashk_size = cpu_to_be_ulong(resource_size(&crashk_res));
                 of_add_property(node, &crashk_size_prop);
         }
 
@@ -246,6 +251,7 @@ static void __init export_crashk_values(struct device_node *node)
          * memory_limit is required by the kexec-tools to limit the
          * crash regions to the actual memory used.
          */
+        mem_limit = cpu_to_be_ulong(memory_limit);
         of_update_property(node, &memory_limit_prop);
 }
 
@@ -264,7 +270,7 @@ static int __init kexec_setup(void)
                 of_remove_property(node, prop);
 
         /* information needed by userspace when using default_machine_kexec */
-        kernel_end = __pa(_end);
+        kernel_end = cpu_to_be_ulong(__pa(_end));
         of_add_property(node, &kernel_end_prop);
 
         export_crashk_values(node);
diff --git a/arch/powerpc/kernel/machine_kexec_64.c b/arch/powerpc/kernel/machine_kexec_64.c
index be4e6d648f60..59d229a2a3e0 100644
--- a/arch/powerpc/kernel/machine_kexec_64.c
+++ b/arch/powerpc/kernel/machine_kexec_64.c
@@ -369,6 +369,7 @@ void default_machine_kexec(struct kimage *image)
 
 /* Values we need to export to the second kernel via the device tree. */
 static unsigned long htab_base;
+static unsigned long htab_size;
 
 static struct property htab_base_prop = {
         .name = "linux,htab-base",
@@ -379,7 +380,7 @@ static struct property htab_base_prop = {
 static struct property htab_size_prop = {
         .name = "linux,htab-size",
         .length = sizeof(unsigned long),
-        .value = &htab_size_bytes,
+        .value = &htab_size,
 };
 
 static int __init export_htab_values(void)
@@ -403,8 +404,9 @@ static int __init export_htab_values(void)
         if (prop)
                 of_remove_property(node, prop);
 
-        htab_base = __pa(htab_address);
+        htab_base = cpu_to_be64(__pa(htab_address));
         of_add_property(node, &htab_base_prop);
+        htab_size = cpu_to_be64(htab_size_bytes);
         of_add_property(node, &htab_size_prop);
 
         of_node_put(node);
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 879f09620f83..7c6bb4b17b49 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -57,11 +57,14 @@ _GLOBAL(call_do_softirq)
         mtlr    r0
         blr
 
+/*
+ * void call_do_irq(struct pt_regs *regs, struct thread_info *irqtp);
+ */
 _GLOBAL(call_do_irq)
         mflr    r0
         stw     r0,4(r1)
         lwz     r10,THREAD+KSP_LIMIT(r2)
-        addi    r11,r3,THREAD_INFO_GAP
+        addi    r11,r4,THREAD_INFO_GAP
         stwu    r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
         mr      r1,r4
         stw     r10,8(r1)
diff --git a/arch/powerpc/kernel/reloc_64.S b/arch/powerpc/kernel/reloc_64.S
index b47a0e1ab001..1482327cfeba 100644
--- a/arch/powerpc/kernel/reloc_64.S
+++ b/arch/powerpc/kernel/reloc_64.S
@@ -69,8 +69,8 @@ _GLOBAL(relocate)
          * R_PPC64_RELATIVE ones.
          */
         mtctr   r8
-5:      lwz     r0,12(9)        /* ELF64_R_TYPE(reloc->r_info) */
-        cmpwi   r0,R_PPC64_RELATIVE
+5:      ld      r0,8(9)         /* ELF64_R_TYPE(reloc->r_info) */
+        cmpdi   r0,R_PPC64_RELATIVE
         bne     6f
         ld      r6,0(r9)        /* reloc->r_offset */
         ld      r0,16(r9)       /* reloc->r_addend */
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 2b0da27eaee4..04cc4fcca78b 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -247,7 +247,12 @@ static void __init exc_lvl_early_init(void)
         /* interrupt stacks must be in lowmem, we get that for free on ppc32
          * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */
         for_each_possible_cpu(i) {
+#ifdef CONFIG_SMP
                 hw_cpu = get_hard_smp_processor_id(i);
+#else
+                hw_cpu = 0;
+#endif
+
                 critirq_ctx[hw_cpu] = (struct thread_info *)
                         __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
 #ifdef CONFIG_BOOKE
diff --git a/arch/powerpc/kernel/vdso32/vdso32_wrapper.S b/arch/powerpc/kernel/vdso32/vdso32_wrapper.S
index 79683d0393f5..6ac107ac402a 100644
--- a/arch/powerpc/kernel/vdso32/vdso32_wrapper.S
+++ b/arch/powerpc/kernel/vdso32/vdso32_wrapper.S
@@ -6,7 +6,7 @@
         .globl vdso32_start, vdso32_end
         .balign PAGE_SIZE
 vdso32_start:
-        .incbin "arch/powerpc/kernel/vdso32/vdso32.so"
+        .incbin "arch/powerpc/kernel/vdso32/vdso32.so.dbg"
         .balign PAGE_SIZE
 vdso32_end:
 
diff --git a/arch/powerpc/kernel/vdso64/vdso64_wrapper.S b/arch/powerpc/kernel/vdso64/vdso64_wrapper.S
index 8df9e2463007..df60fca6a13d 100644
--- a/arch/powerpc/kernel/vdso64/vdso64_wrapper.S
+++ b/arch/powerpc/kernel/vdso64/vdso64_wrapper.S
@@ -6,7 +6,7 @@
         .globl vdso64_start, vdso64_end
         .balign PAGE_SIZE
 vdso64_start:
-        .incbin "arch/powerpc/kernel/vdso64/vdso64.so"
+        .incbin "arch/powerpc/kernel/vdso64/vdso64.so.dbg"
         .balign PAGE_SIZE
 vdso64_end:
 
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index de6881259aef..d766d6ee33fe 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -207,6 +207,20 @@ int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
                 if (overlaps_kernel_text(vaddr, vaddr + step))
                         tprot &= ~HPTE_R_N;
 
+                /*
+                 * If relocatable, check if it overlaps interrupt vectors that
+                 * are copied down to real 0. For relocatable kernel
+                 * (e.g. kdump case) we copy interrupt vectors down to real
+                 * address 0. Mark that region as executable. This is
+                 * because on p8 system with relocation on exception feature
+                 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
+                 * in order to execute the interrupt handlers in virtual
+                 * mode the vector region need to be marked as executable.
+                 */
+                if ((PHYSICAL_START > MEMORY_START) &&
+                        overlaps_interrupt_vector_text(vaddr, vaddr + step))
+                                tprot &= ~HPTE_R_N;
+
                 hash = hpt_hash(vpn, shift, ssize);
                 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
 
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index 65b7b65e8708..62bf5e8e78da 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -510,7 +510,8 @@ int pmdp_set_access_flags(struct vm_area_struct *vma, unsigned long address,
 }
 
 unsigned long pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
-                                  pmd_t *pmdp, unsigned long clr)
+                                  pmd_t *pmdp, unsigned long clr,
+                                  unsigned long set)
 {
 
         unsigned long old, tmp;
@@ -526,14 +527,15 @@ unsigned long pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
                 andi.   %1,%0,%6\n\
                 bne-    1b \n\
                 andc    %1,%0,%4 \n\
+                or      %1,%1,%7\n\
                 stdcx.  %1,0,%3 \n\
                 bne-    1b"
         : "=&r" (old), "=&r" (tmp), "=m" (*pmdp)
-        : "r" (pmdp), "r" (clr), "m" (*pmdp), "i" (_PAGE_BUSY)
+        : "r" (pmdp), "r" (clr), "m" (*pmdp), "i" (_PAGE_BUSY), "r" (set)
         : "cc" );
 #else
         old = pmd_val(*pmdp);
-        *pmdp = __pmd(old & ~clr);
+        *pmdp = __pmd((old & ~clr) | set);
 #endif
         if (old & _PAGE_HASHPTE)
                 hpte_do_hugepage_flush(mm, addr, pmdp);
@@ -708,7 +710,7 @@ void set_pmd_at(struct mm_struct *mm, unsigned long addr,
 void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
                      pmd_t *pmdp)
 {
-        pmd_hugepage_update(vma->vm_mm, address, pmdp, _PAGE_PRESENT);
+        pmd_hugepage_update(vma->vm_mm, address, pmdp, _PAGE_PRESENT, 0);
 }
 
 /*
@@ -835,7 +837,7 @@ pmd_t pmdp_get_and_clear(struct mm_struct *mm,
         unsigned long old;
         pgtable_t *pgtable_slot;
 
-        old = pmd_hugepage_update(mm, addr, pmdp, ~0UL);
+        old = pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
         old_pmd = __pmd(old);
         /*
          * We have pmd == none and we are holding page_table_lock.
diff --git a/arch/powerpc/mm/subpage-prot.c b/arch/powerpc/mm/subpage-prot.c
index a770df2dae70..6c0b1f5f8d2c 100644
--- a/arch/powerpc/mm/subpage-prot.c
+++ b/arch/powerpc/mm/subpage-prot.c
@@ -78,7 +78,7 @@ static void hpte_flush_range(struct mm_struct *mm, unsigned long addr,
         pte = pte_offset_map_lock(mm, pmd, addr, &ptl);
         arch_enter_lazy_mmu_mode();
         for (; npages > 0; --npages) {
-                pte_update(mm, addr, pte, 0, 0);
+                pte_update(mm, addr, pte, 0, 0, 0);
                 addr += PAGE_SIZE;
                 ++pte;
         }
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 29b89e863d7c..67cf22083f4c 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -1147,6 +1147,9 @@ static void power_pmu_enable(struct pmu *pmu)
         mmcr0 = ebb_switch_in(ebb, cpuhw->mmcr[0]);
 
         mb();
+        if (cpuhw->bhrb_users)
+                ppmu->config_bhrb(cpuhw->bhrb_filter);
+
         write_mmcr0(cpuhw, mmcr0);
 
         /*
@@ -1158,8 +1161,6 @@ static void power_pmu_enable(struct pmu *pmu)
         }
 
  out:
-        if (cpuhw->bhrb_users)
-                ppmu->config_bhrb(cpuhw->bhrb_filter);
 
         local_irq_restore(flags);
 }
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index a3f7abd2f13f..96cee20dcd34 100644
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -25,6 +25,37 @@
 #define PM_BRU_FIN                      0x10068
 #define PM_BR_MPRED_CMPL                0x400f6
 
+/* All L1 D cache load references counted at finish, gated by reject */
+#define PM_LD_REF_L1                    0x100ee
+/* Load Missed L1 */
+#define PM_LD_MISS_L1                   0x3e054
+/* Store Missed L1 */
+#define PM_ST_MISS_L1                   0x300f0
+/* L1 cache data prefetches */
+#define PM_L1_PREF                      0x0d8b8
+/* Instruction fetches from L1 */
+#define PM_INST_FROM_L1                 0x04080
+/* Demand iCache Miss */
+#define PM_L1_ICACHE_MISS               0x200fd
+/* Instruction Demand sectors wriittent into IL1 */
+#define PM_L1_DEMAND_WRITE              0x0408c
+/* Instruction prefetch written into IL1 */
+#define PM_IC_PREF_WRITE                0x0408e
+/* The data cache was reloaded from local core's L3 due to a demand load */
+#define PM_DATA_FROM_L3                 0x4c042
+/* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
+#define PM_DATA_FROM_L3MISS             0x300fe
+/* All successful D-side store dispatches for this thread */
+#define PM_L2_ST                        0x17080
+/* All successful D-side store dispatches for this thread that were L2 Miss */
+#define PM_L2_ST_MISS                   0x17082
+/* Total HW L3 prefetches(Load+store) */
+#define PM_L3_PREF_ALL                  0x4e052
+/* Data PTEG reload */
+#define PM_DTLB_MISS                    0x300fc
+/* ITLB Reloaded */
+#define PM_ITLB_MISS                    0x400fc
+
 
 /*
  * Raw event encoding for POWER8:
@@ -557,6 +588,8 @@ static int power8_generic_events[] = {
         [PERF_COUNT_HW_INSTRUCTIONS] =                  PM_INST_CMPL,
         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =           PM_BRU_FIN,
         [PERF_COUNT_HW_BRANCH_MISSES] =                 PM_BR_MPRED_CMPL,
+        [PERF_COUNT_HW_CACHE_REFERENCES] =              PM_LD_REF_L1,
+        [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1,
 };
 
 static u64 power8_bhrb_filter_map(u64 branch_sample_type)
@@ -596,6 +629,116 @@ static void power8_config_bhrb(u64 pmu_bhrb_filter)
         mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
 }
 
+#define C(x)    PERF_COUNT_HW_CACHE_##x
+
+/*
+ * Table of generalized cache-related events.
+ * 0 means not supported, -1 means nonsensical, other values
+ * are event codes.
+ */
+static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
+        [ C(L1D) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
+                        [ C(RESULT_MISS)   ] = PM_LD_MISS_L1,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = PM_ST_MISS_L1,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = PM_L1_PREF,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+        },
+        [ C(L1I) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
+                        [ C(RESULT_MISS)   ] = PM_L1_ICACHE_MISS,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+        },
+        [ C(LL) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
+                        [ C(RESULT_MISS)   ] = PM_DATA_FROM_L3MISS,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = PM_L2_ST,
+                        [ C(RESULT_MISS)   ] = PM_L2_ST_MISS,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
+                        [ C(RESULT_MISS)   ] = 0,
+                },
+        },
+        [ C(DTLB) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = PM_DTLB_MISS,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+        },
+        [ C(ITLB) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = PM_ITLB_MISS,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+        },
+        [ C(BPU) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = PM_BRU_FIN,
+                        [ C(RESULT_MISS)   ] = PM_BR_MPRED_CMPL,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+        },
+        [ C(NODE) ] = {
+                [ C(OP_READ) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_WRITE) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+                [ C(OP_PREFETCH) ] = {
+                        [ C(RESULT_ACCESS) ] = -1,
+                        [ C(RESULT_MISS)   ] = -1,
+                },
+        },
+};
+
+#undef C
+
 static struct power_pmu power8_pmu = {
         .name                   = "POWER8",
         .n_counter              = 6,
@@ -611,6 +754,7 @@ static struct power_pmu power8_pmu = {
         .flags                  = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_BHRB | PPMU_EBB,
         .n_generic              = ARRAY_SIZE(power8_generic_events),
         .generic_events         = power8_generic_events,
+        .cache_events           = &power8_cache_events,
         .attr_groups            = power8_pmu_attr_groups,
         .bhrb_nr                = 32,
 };
diff --git a/arch/powerpc/platforms/powernv/eeh-ioda.c b/arch/powerpc/platforms/powernv/eeh-ioda.c
index e1e71618b70c..f51474336460 100644
--- a/arch/powerpc/platforms/powernv/eeh-ioda.c
+++ b/arch/powerpc/platforms/powernv/eeh-ioda.c
@@ -44,7 +44,8 @@ static int ioda_eeh_event(struct notifier_block *nb,
 
         /* We simply send special EEH event */
         if ((changed_evts & OPAL_EVENT_PCI_ERROR) &&
-            (events & OPAL_EVENT_PCI_ERROR))
+            (events & OPAL_EVENT_PCI_ERROR) &&
+            eeh_enabled())
                 eeh_send_failure_event(NULL);
 
         return 0;
@@ -489,8 +490,7 @@ static int ioda_eeh_bridge_reset(struct pci_controller *hose,
 static int ioda_eeh_reset(struct eeh_pe *pe, int option)
 {
         struct pci_controller *hose = pe->phb;
-        struct eeh_dev *edev;
-        struct pci_dev *dev;
+        struct pci_bus *bus;
         int ret;
 
         /*
@@ -519,31 +519,11 @@ static int ioda_eeh_reset(struct eeh_pe *pe, int option)
         if (pe->type & EEH_PE_PHB) {
                 ret = ioda_eeh_phb_reset(hose, option);
         } else {
-                if (pe->type & EEH_PE_DEVICE) {
-                        /*
-                         * If it's device PE, we didn't refer to the parent
-                         * PCI bus yet. So we have to figure it out indirectly.
-                         */
-                        edev = list_first_entry(&pe->edevs,
-                                        struct eeh_dev, list);
-                        dev = eeh_dev_to_pci_dev(edev);
-                        dev = dev->bus->self;
-                } else {
-                        /*
-                         * If it's bus PE, the parent PCI bus is already there
-                         * and just pick it up.
-                         */
-                        dev = pe->bus->self;
-                }
-
-                /*
-                 * Do reset based on the fact that the direct upstream bridge
-                 * is root bridge (port) or not.
-                 */
-                if (dev->bus->number == 0)
+                bus = eeh_pe_bus_get(pe);
+                if (pci_is_root_bus(bus))
                         ret = ioda_eeh_root_reset(hose, option);
                 else
-                        ret = ioda_eeh_bridge_reset(hose, dev, option);
+                        ret = ioda_eeh_bridge_reset(hose, bus->self, option);
         }
 
         return ret;
diff --git a/arch/powerpc/platforms/powernv/eeh-powernv.c b/arch/powerpc/platforms/powernv/eeh-powernv.c
index a79fddc5e74e..a59788e83b8b 100644
--- a/arch/powerpc/platforms/powernv/eeh-powernv.c
+++ b/arch/powerpc/platforms/powernv/eeh-powernv.c
@@ -145,7 +145,7 @@ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag)
          * Enable EEH explicitly so that we will do EEH check
          * while accessing I/O stuff
          */
-        eeh_subsystem_enabled = 1;
+        eeh_set_enable(true);
 
         /* Save memory bars */
         eeh_save_bars(edev);
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index 7d6dcc6d5fa9..3b2b4fb3585b 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -21,6 +21,7 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/msi.h>
+#include <linux/memblock.h>
 
 #include <asm/sections.h>
 #include <asm/io.h>
@@ -460,9 +461,39 @@ static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev
                 return;
 
         pe = &phb->ioda.pe_array[pdn->pe_number];
+        WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
         set_iommu_table_base_and_group(&pdev->dev, &pe->tce32_table);
 }
 
+static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb,
+                                     struct pci_dev *pdev, u64 dma_mask)
+{
+        struct pci_dn *pdn = pci_get_pdn(pdev);
+        struct pnv_ioda_pe *pe;
+        uint64_t top;
+        bool bypass = false;
+
+        if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
+                return -ENODEV;;
+
+        pe = &phb->ioda.pe_array[pdn->pe_number];
+        if (pe->tce_bypass_enabled) {
+                top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
+                bypass = (dma_mask >= top);
+        }
+
+        if (bypass) {
+                dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
+                set_dma_ops(&pdev->dev, &dma_direct_ops);
+                set_dma_offset(&pdev->dev, pe->tce_bypass_base);
+        } else {
+                dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
+                set_dma_ops(&pdev->dev, &dma_iommu_ops);
+                set_iommu_table_base(&pdev->dev, &pe->tce32_table);
+        }
+        return 0;
+}
+
 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
 {
         struct pci_dev *dev;
@@ -657,6 +688,56 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
                 __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
 }
 
+static void pnv_pci_ioda2_set_bypass(struct iommu_table *tbl, bool enable)
+{
+        struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe,
+                                              tce32_table);
+        uint16_t window_id = (pe->pe_number << 1 ) + 1;
+        int64_t rc;
+
+        pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
+        if (enable) {
+                phys_addr_t top = memblock_end_of_DRAM();
+
+                top = roundup_pow_of_two(top);
+                rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
+                                                     pe->pe_number,
+                                                     window_id,
+                                                     pe->tce_bypass_base,
+                                                     top);
+        } else {
+                rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
+                                                     pe->pe_number,
+                                                     window_id,
+                                                     pe->tce_bypass_base,
+                                                     0);
+
+                /*
+                 * We might want to reset the DMA ops of all devices on
+                 * this PE. However in theory, that shouldn't be necessary
+                 * as this is used for VFIO/KVM pass-through and the device
+                 * hasn't yet been returned to its kernel driver
+                 */
+        }
+        if (rc)
+                pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
+        else
+                pe->tce_bypass_enabled = enable;
+}
+
+static void pnv_pci_ioda2_setup_bypass_pe(struct pnv_phb *phb,
+                                          struct pnv_ioda_pe *pe)
+{
+        /* TVE #1 is selected by PCI address bit 59 */
+        pe->tce_bypass_base = 1ull << 59;
+
+        /* Install set_bypass callback for VFIO */
+        pe->tce32_table.set_bypass = pnv_pci_ioda2_set_bypass;
+
+        /* Enable bypass by default */
+        pnv_pci_ioda2_set_bypass(&pe->tce32_table, true);
+}
+
 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
                                        struct pnv_ioda_pe *pe)
 {
@@ -727,6 +808,8 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
         else
                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
 
+        /* Also create a bypass window */
+        pnv_pci_ioda2_setup_bypass_pe(phb, pe);
         return;
 fail:
         if (pe->tce32_seg >= 0)
@@ -1286,6 +1369,7 @@ void __init pnv_pci_init_ioda_phb(struct device_node *np,
 
         /* Setup TCEs */
         phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
+        phb->dma_set_mask = pnv_pci_ioda_dma_set_mask;
 
         /* Setup shutdown function for kexec */
         phb->shutdown = pnv_pci_ioda_shutdown;
diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index b555ebc57ef5..95633d79ef5d 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -634,6 +634,16 @@ static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
                 pnv_pci_dma_fallback_setup(hose, pdev);
 }
 
+int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
+{
+        struct pci_controller *hose = pci_bus_to_host(pdev->bus);
+        struct pnv_phb *phb = hose->private_data;
+
+        if (phb && phb->dma_set_mask)
+                return phb->dma_set_mask(phb, pdev, dma_mask);
+        return __dma_set_mask(&pdev->dev, dma_mask);
+}
+
 void pnv_pci_shutdown(void)
 {
         struct pci_controller *hose;
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index 13f1942a9a5f..cde169442775 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -54,7 +54,9 @@ struct pnv_ioda_pe {
         struct iommu_table      tce32_table;
         phys_addr_t             tce_inval_reg_phys;
 
-        /* XXX TODO: Add support for additional 64-bit iommus */
+        /* 64-bit TCE bypass region */
+        bool                    tce_bypass_enabled;
+        uint64_t                tce_bypass_base;
 
         /* MSIs. MVE index is identical for for 32 and 64 bit MSI
          * and -1 if not supported. (It's actually identical to the
@@ -113,6 +115,8 @@ struct pnv_phb {
                          unsigned int hwirq, unsigned int virq,
                          unsigned int is_64, struct msi_msg *msg);
         void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
+        int (*dma_set_mask)(struct pnv_phb *phb, struct pci_dev *pdev,
+                            u64 dma_mask);
         void (*fixup_phb)(struct pci_controller *hose);
         u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
         void (*shutdown)(struct pnv_phb *phb);
diff --git a/arch/powerpc/platforms/powernv/powernv.h b/arch/powerpc/platforms/powernv/powernv.h
index de6819be1f95..0051e108ef0f 100644
--- a/arch/powerpc/platforms/powernv/powernv.h
+++ b/arch/powerpc/platforms/powernv/powernv.h
@@ -7,12 +7,20 @@ extern void pnv_smp_init(void);
 static inline void pnv_smp_init(void) { }
 #endif
 
+struct pci_dev;
+
 #ifdef CONFIG_PCI
 extern void pnv_pci_init(void);
 extern void pnv_pci_shutdown(void);
+extern int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask);
 #else
 static inline void pnv_pci_init(void) { }
 static inline void pnv_pci_shutdown(void) { }
+
+static inline int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
+{
+        return -ENODEV;
+}
 #endif
 
 extern void pnv_lpc_init(void);
diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c
index 21166f65c97c..110f4fbd319f 100644
--- a/arch/powerpc/platforms/powernv/setup.c
+++ b/arch/powerpc/platforms/powernv/setup.c
@@ -27,6 +27,7 @@
 #include <linux/interrupt.h>
 #include <linux/bug.h>
 #include <linux/cpuidle.h>
+#include <linux/pci.h>
 
 #include <asm/machdep.h>
 #include <asm/firmware.h>
@@ -141,6 +142,13 @@ static void pnv_progress(char *s, unsigned short hex)
 {
 }
 
+static int pnv_dma_set_mask(struct device *dev, u64 dma_mask)
+{
+        if (dev_is_pci(dev))
+                return pnv_pci_dma_set_mask(to_pci_dev(dev), dma_mask);
+        return __dma_set_mask(dev, dma_mask);
+}
+
 static void pnv_shutdown(void)
 {
         /* Let the PCI code clear up IODA tables */
@@ -238,6 +246,7 @@ define_machine(powernv) {
         .machine_shutdown       = pnv_shutdown,
         .power_save             = powernv_idle,
         .calibrate_decr         = generic_calibrate_decr,
+        .dma_set_mask           = pnv_dma_set_mask,
 #ifdef CONFIG_KEXEC
         .kexec_cpu_down         = pnv_kexec_cpu_down,
 #endif
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index 37300f6ee244..80b1d57c306a 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -20,6 +20,7 @@ config PPC_PSERIES
         select PPC_DOORBELL
         select HAVE_CONTEXT_TRACKING
         select HOTPLUG_CPU if SMP
+        select ARCH_RANDOM
         default y
 
 config PPC_SPLPAR
diff --git a/arch/powerpc/platforms/pseries/eeh_pseries.c b/arch/powerpc/platforms/pseries/eeh_pseries.c
index 9ef3cc8ebc11..8a8f0472d98f 100644
--- a/arch/powerpc/platforms/pseries/eeh_pseries.c
+++ b/arch/powerpc/platforms/pseries/eeh_pseries.c
@@ -265,7 +265,7 @@ static void *pseries_eeh_of_probe(struct device_node *dn, void *flag)
                         enable = 1;
 
                 if (enable) {
-                        eeh_subsystem_enabled = 1;
+                        eeh_set_enable(true);
                         eeh_add_to_parent_pe(edev);
 
                         pr_debug("%s: EEH enabled on %s PHB#%d-PE#%x, config addr#%x\n",
diff --git a/arch/powerpc/platforms/pseries/pci.c b/arch/powerpc/platforms/pseries/pci.c
index 70670a2d9cf2..c413ec158ff5 100644
--- a/arch/powerpc/platforms/pseries/pci.c
+++ b/arch/powerpc/platforms/pseries/pci.c
@@ -113,7 +113,8 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
 {
         struct device_node *dn, *pdn;
         struct pci_bus *bus;
-        const __be32 *pcie_link_speed_stats;
+        u32 pcie_link_speed_stats[2];
+        int rc;
 
         bus = bridge->bus;
 
@@ -122,38 +123,45 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
                 return 0;
 
         for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) {
-                pcie_link_speed_stats = of_get_property(pdn,
-                        "ibm,pcie-link-speed-stats", NULL);
-                if (pcie_link_speed_stats)
+                rc = of_property_read_u32_array(pdn,
+                                "ibm,pcie-link-speed-stats",
+                                &pcie_link_speed_stats[0], 2);
+                if (!rc)
                         break;
         }
 
         of_node_put(pdn);
 
-        if (!pcie_link_speed_stats) {
+        if (rc) {
                 pr_err("no ibm,pcie-link-speed-stats property\n");
                 return 0;
         }
 
-        switch (be32_to_cpup(pcie_link_speed_stats)) {
+        switch (pcie_link_speed_stats[0]) {
         case 0x01:
                 bus->max_bus_speed = PCIE_SPEED_2_5GT;
                 break;
         case 0x02:
                 bus->max_bus_speed = PCIE_SPEED_5_0GT;
                 break;
+        case 0x04:
+                bus->max_bus_speed = PCIE_SPEED_8_0GT;
+                break;
         default:
                 bus->max_bus_speed = PCI_SPEED_UNKNOWN;
                 break;
         }
 
-        switch (be32_to_cpup(pcie_link_speed_stats)) {
+        switch (pcie_link_speed_stats[1]) {
         case 0x01:
                 bus->cur_bus_speed = PCIE_SPEED_2_5GT;
                 break;
         case 0x02:
                 bus->cur_bus_speed = PCIE_SPEED_5_0GT;
                 break;
+        case 0x04:
+                bus->cur_bus_speed = PCIE_SPEED_8_0GT;
+                break;
         default:
                 bus->cur_bus_speed = PCI_SPEED_UNKNOWN;
                 break;
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 8e639d7cbda7..972df0ffd4dc 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -430,8 +430,7 @@ static void pSeries_machine_kexec(struct kimage *image)
 {
         long rc;
 
-        if (firmware_has_feature(FW_FEATURE_SET_MODE) &&
-            (image->type != KEXEC_TYPE_CRASH)) {
+        if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
                 rc = pSeries_disable_reloc_on_exc();
                 if (rc != H_SUCCESS)
                         pr_warning("Warning: Failed to disable relocation on "
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 0e166ed4cd16..8209744b2829 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -886,25 +886,25 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
 
         /* Default: read HW settings */
         if (flow_type == IRQ_TYPE_DEFAULT) {
-                switch(vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
-                               MPIC_INFO(VECPRI_SENSE_MASK))) {
-                        case MPIC_INFO(VECPRI_SENSE_EDGE) |
-                             MPIC_INFO(VECPRI_POLARITY_POSITIVE):
-                                flow_type = IRQ_TYPE_EDGE_RISING;
-                                break;
-                        case MPIC_INFO(VECPRI_SENSE_EDGE) |
-                             MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
-                                flow_type = IRQ_TYPE_EDGE_FALLING;
-                                break;
-                        case MPIC_INFO(VECPRI_SENSE_LEVEL) |
-                             MPIC_INFO(VECPRI_POLARITY_POSITIVE):
-                                flow_type = IRQ_TYPE_LEVEL_HIGH;
-                                break;
-                        case MPIC_INFO(VECPRI_SENSE_LEVEL) |
-                             MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
-                                flow_type = IRQ_TYPE_LEVEL_LOW;
-                                break;
-                }
+                int vold_ps;
+
+                vold_ps = vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
+                                  MPIC_INFO(VECPRI_SENSE_MASK));
+
+                if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
+                                MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
+                        flow_type = IRQ_TYPE_EDGE_RISING;
+                else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
+                                     MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
+                        flow_type = IRQ_TYPE_EDGE_FALLING;
+                else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
+                                     MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
+                        flow_type = IRQ_TYPE_LEVEL_HIGH;
+                else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
+                                     MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
+                        flow_type = IRQ_TYPE_LEVEL_LOW;
+                else
+                        WARN_ONCE(1, "mpic: unknown IRQ type %d\n", vold);
         }
 
         /* Apply to irq desc */
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index a90731b3d44a..b07909850f77 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -309,16 +309,23 @@ static void get_output_lock(void)
 
         if (xmon_speaker == me)
                 return;
+
         for (;;) {
-                if (xmon_speaker == 0) {
-                        last_speaker = cmpxchg(&xmon_speaker, 0, me);
-                        if (last_speaker == 0)
-                                return;
-                }
-                timeout = 10000000;
+                last_speaker = cmpxchg(&xmon_speaker, 0, me);
+                if (last_speaker == 0)
+                        return;
+
+                /*
+                 * Wait a full second for the lock, we might be on a slow
+                 * console, but check every 100us.
+                 */
+                timeout = 10000;
                 while (xmon_speaker == last_speaker) {
-                        if (--timeout > 0)
+                        if (--timeout > 0) {
+                                udelay(100);
                                 continue;
+                        }
+
                         /* hostile takeover */
                         prev = cmpxchg(&xmon_speaker, last_speaker, me);
                         if (prev == last_speaker)
@@ -397,7 +404,6 @@ static int xmon_core(struct pt_regs *regs, int fromipi)
         }
 
         xmon_fault_jmp[cpu] = recurse_jmp;
-        cpumask_set_cpu(cpu, &cpus_in_xmon);
 
         bp = NULL;
         if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) == (MSR_IR|MSR_64BIT))
@@ -419,6 +425,8 @@ static int xmon_core(struct pt_regs *regs, int fromipi)
                 release_output_lock();
         }
 
+        cpumask_set_cpu(cpu, &cpus_in_xmon);
+
  waiting:
         secondary = 1;
         while (secondary && !xmon_gate) {
diff --git a/arch/s390/appldata/appldata_base.c b/arch/s390/appldata/appldata_base.c
index 4c4a1cef5208..47c8630c93cd 100644
--- a/arch/s390/appldata/appldata_base.c
+++ b/arch/s390/appldata/appldata_base.c
@@ -529,6 +529,7 @@ static int __init appldata_init(void)
 {
         int rc;
 
+        init_virt_timer(&appldata_timer);
         appldata_timer.function = appldata_timer_function;
         appldata_timer.data = (unsigned long) &appldata_work;
 
diff --git a/arch/s390/crypto/aes_s390.c b/arch/s390/crypto/aes_s390.c
index b3feabd39f31..cf3c0089bef2 100644
--- a/arch/s390/crypto/aes_s390.c
+++ b/arch/s390/crypto/aes_s390.c
@@ -25,6 +25,7 @@
 #include <linux/err.h>
 #include <linux/module.h>
 #include <linux/init.h>
+#include <linux/spinlock.h>
 #include "crypt_s390.h"
 
 #define AES_KEYLEN_128          1
@@ -32,6 +33,7 @@
 #define AES_KEYLEN_256          4
 
 static u8 *ctrblk;
+static DEFINE_SPINLOCK(ctrblk_lock);
 static char keylen_flag;
 
 struct s390_aes_ctx {
@@ -758,43 +760,67 @@ static int ctr_aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
         return aes_set_key(tfm, in_key, key_len);
 }
 
+static unsigned int __ctrblk_init(u8 *ctrptr, unsigned int nbytes)
+{
+        unsigned int i, n;
+
+        /* only use complete blocks, max. PAGE_SIZE */
+        n = (nbytes > PAGE_SIZE) ? PAGE_SIZE : nbytes & ~(AES_BLOCK_SIZE - 1);
+        for (i = AES_BLOCK_SIZE; i < n; i += AES_BLOCK_SIZE) {
+                memcpy(ctrptr + i, ctrptr + i - AES_BLOCK_SIZE,
+                       AES_BLOCK_SIZE);
+                crypto_inc(ctrptr + i, AES_BLOCK_SIZE);
+        }
+        return n;
+}
+
 static int ctr_aes_crypt(struct blkcipher_desc *desc, long func,
                          struct s390_aes_ctx *sctx, struct blkcipher_walk *walk)
 {
         int ret = blkcipher_walk_virt_block(desc, walk, AES_BLOCK_SIZE);
-        unsigned int i, n, nbytes;
-        u8 buf[AES_BLOCK_SIZE];
-        u8 *out, *in;
+        unsigned int n, nbytes;
+        u8 buf[AES_BLOCK_SIZE], ctrbuf[AES_BLOCK_SIZE];
+        u8 *out, *in, *ctrptr = ctrbuf;
 
         if (!walk->nbytes)
                 return ret;
 
-        memcpy(ctrblk, walk->iv, AES_BLOCK_SIZE);
+        if (spin_trylock(&ctrblk_lock))
+                ctrptr = ctrblk;
+
+        memcpy(ctrptr, walk->iv, AES_BLOCK_SIZE);
         while ((nbytes = walk->nbytes) >= AES_BLOCK_SIZE) {
                 out = walk->dst.virt.addr;
                 in = walk->src.virt.addr;
                 while (nbytes >= AES_BLOCK_SIZE) {
-                        /* only use complete blocks, max. PAGE_SIZE */
-                        n = (nbytes > PAGE_SIZE) ? PAGE_SIZE :
-                                                 nbytes & ~(AES_BLOCK_SIZE - 1);
-                        for (i = AES_BLOCK_SIZE; i < n; i += AES_BLOCK_SIZE) {
-                                memcpy(ctrblk + i, ctrblk + i - AES_BLOCK_SIZE,
-                                       AES_BLOCK_SIZE);
-                                crypto_inc(ctrblk + i, AES_BLOCK_SIZE);
-                        }
-                        ret = crypt_s390_kmctr(func, sctx->key, out, in, n, ctrblk);
-                        if (ret < 0 || ret != n)
+                        if (ctrptr == ctrblk)
+                                n = __ctrblk_init(ctrptr, nbytes);
+                        else
+                                n = AES_BLOCK_SIZE;
+                        ret = crypt_s390_kmctr(func, sctx->key, out, in,
+                                               n, ctrptr);
+                        if (ret < 0 || ret != n) {
+                                if (ctrptr == ctrblk)
+                                        spin_unlock(&ctrblk_lock);
                                 return -EIO;
+                        }
                         if (n > AES_BLOCK_SIZE)
-                                memcpy(ctrblk, ctrblk + n - AES_BLOCK_SIZE,
+                                memcpy(ctrptr, ctrptr + n - AES_BLOCK_SIZE,
                                        AES_BLOCK_SIZE);
-                        crypto_inc(ctrblk, AES_BLOCK_SIZE);
+                        crypto_inc(ctrptr, AES_BLOCK_SIZE);
                         out += n;
                         in += n;
                         nbytes -= n;
                 }
                 ret = blkcipher_walk_done(desc, walk, nbytes);
         }
+        if (ctrptr == ctrblk) {
+                if (nbytes)
+                        memcpy(ctrbuf, ctrptr, AES_BLOCK_SIZE);
+                else
+                        memcpy(walk->iv, ctrptr, AES_BLOCK_SIZE);
+                spin_unlock(&ctrblk_lock);
+        }
         /*
          * final block may be < AES_BLOCK_SIZE, copy only nbytes
          */
@@ -802,14 +828,15 @@ static int ctr_aes_crypt(struct blkcipher_desc *desc, long func,
                 out = walk->dst.virt.addr;
                 in = walk->src.virt.addr;
                 ret = crypt_s390_kmctr(func, sctx->key, buf, in,
-                                       AES_BLOCK_SIZE, ctrblk);
+                                       AES_BLOCK_SIZE, ctrbuf);
                 if (ret < 0 || ret != AES_BLOCK_SIZE)
                         return -EIO;
                 memcpy(out, buf, nbytes);
-                crypto_inc(ctrblk, AES_BLOCK_SIZE);
+                crypto_inc(ctrbuf, AES_BLOCK_SIZE);
                 ret = blkcipher_walk_done(desc, walk, 0);
+                memcpy(walk->iv, ctrbuf, AES_BLOCK_SIZE);
         }
-        memcpy(walk->iv, ctrblk, AES_BLOCK_SIZE);
+
         return ret;
 }
 
diff --git a/arch/s390/crypto/des_s390.c b/arch/s390/crypto/des_s390.c
index 200f2a1b599d..0a5aac8a9412 100644
--- a/arch/s390/crypto/des_s390.c
+++ b/arch/s390/crypto/des_s390.c
@@ -25,6 +25,7 @@
 #define DES3_KEY_SIZE   (3 * DES_KEY_SIZE)
 
 static u8 *ctrblk;
+static DEFINE_SPINLOCK(ctrblk_lock);
 
 struct s390_des_ctx {
         u8 iv[DES_BLOCK_SIZE];
@@ -105,29 +106,35 @@ static int ecb_desall_crypt(struct blkcipher_desc *desc, long func,
 }
 
 static int cbc_desall_crypt(struct blkcipher_desc *desc, long func,
-                            u8 *iv, struct blkcipher_walk *walk)
+                            struct blkcipher_walk *walk)
 {
+        struct s390_des_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
         int ret = blkcipher_walk_virt(desc, walk);
         unsigned int nbytes = walk->nbytes;
+        struct {
+                u8 iv[DES_BLOCK_SIZE];
+                u8 key[DES3_KEY_SIZE];
+        } param;
 
         if (!nbytes)
                 goto out;
 
-        memcpy(iv, walk->iv, DES_BLOCK_SIZE);
+        memcpy(param.iv, walk->iv, DES_BLOCK_SIZE);
+        memcpy(param.key, ctx->key, DES3_KEY_SIZE);
         do {
                 /* only use complete blocks */
                 unsigned int n = nbytes & ~(DES_BLOCK_SIZE - 1);
                 u8 *out = walk->dst.virt.addr;
                 u8 *in = walk->src.virt.addr;
 
-                ret = crypt_s390_kmc(func, iv, out, in, n);
+                ret = crypt_s390_kmc(func, &param, out, in, n);
                 if (ret < 0 || ret != n)
                         return -EIO;
 
                 nbytes &= DES_BLOCK_SIZE - 1;
                 ret = blkcipher_walk_done(desc, walk, nbytes);
         } while ((nbytes = walk->nbytes));
-        memcpy(walk->iv, iv, DES_BLOCK_SIZE);
+        memcpy(walk->iv, param.iv, DES_BLOCK_SIZE);
 
 out:
         return ret;
@@ -179,22 +186,20 @@ static int cbc_des_encrypt(struct blkcipher_desc *desc,
                            struct scatterlist *dst, struct scatterlist *src,
                            unsigned int nbytes)
 {
-        struct s390_des_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
         struct blkcipher_walk walk;
 
         blkcipher_walk_init(&walk, dst, src, nbytes);
-        return cbc_desall_crypt(desc, KMC_DEA_ENCRYPT, ctx->iv, &walk);
+        return cbc_desall_crypt(desc, KMC_DEA_ENCRYPT, &walk);
 }
 
 static int cbc_des_decrypt(struct blkcipher_desc *desc,
                            struct scatterlist *dst, struct scatterlist *src,
                            unsigned int nbytes)
 {
-        struct s390_des_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
         struct blkcipher_walk walk;
 
         blkcipher_walk_init(&walk, dst, src, nbytes);
-        return cbc_desall_crypt(desc, KMC_DEA_DECRYPT, ctx->iv, &walk);
+        return cbc_desall_crypt(desc, KMC_DEA_DECRYPT, &walk);
 }
 
 static struct crypto_alg cbc_des_alg = {
@@ -327,22 +332,20 @@ static int cbc_des3_encrypt(struct blkcipher_desc *desc,
                             struct scatterlist *dst, struct scatterlist *src,
                             unsigned int nbytes)
 {
-        struct s390_des_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
         struct blkcipher_walk walk;
 
         blkcipher_walk_init(&walk, dst, src, nbytes);
-        return cbc_desall_crypt(desc, KMC_TDEA_192_ENCRYPT, ctx->iv, &walk);
+        return cbc_desall_crypt(desc, KMC_TDEA_192_ENCRYPT, &walk);
 }
 
 static int cbc_des3_decrypt(struct blkcipher_desc *desc,
                             struct scatterlist *dst, struct scatterlist *src,
                             unsigned int nbytes)
 {
-        struct s390_des_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
         struct blkcipher_walk walk;
 
         blkcipher_walk_init(&walk, dst, src, nbytes);
-        return cbc_desall_crypt(desc, KMC_TDEA_192_DECRYPT, ctx->iv, &walk);
+        return cbc_desall_crypt(desc, KMC_TDEA_192_DECRYPT, &walk);
 }
 
 static struct crypto_alg cbc_des3_alg = {
@@ -366,54 +369,80 @@ static struct crypto_alg cbc_des3_alg = {
         }
 };
 
+static unsigned int __ctrblk_init(u8 *ctrptr, unsigned int nbytes)
+{
+        unsigned int i, n;
+
+        /* align to block size, max. PAGE_SIZE */
+        n = (nbytes > PAGE_SIZE) ? PAGE_SIZE : nbytes & ~(DES_BLOCK_SIZE - 1);
+        for (i = DES_BLOCK_SIZE; i < n; i += DES_BLOCK_SIZE) {
+                memcpy(ctrptr + i, ctrptr + i - DES_BLOCK_SIZE, DES_BLOCK_SIZE);
+                crypto_inc(ctrptr + i, DES_BLOCK_SIZE);
+        }
+        return n;
+}
+
 static int ctr_desall_crypt(struct blkcipher_desc *desc, long func,
-                            struct s390_des_ctx *ctx, struct blkcipher_walk *walk)
+                            struct s390_des_ctx *ctx,
+                            struct blkcipher_walk *walk)
 {
         int ret = blkcipher_walk_virt_block(desc, walk, DES_BLOCK_SIZE);
-        unsigned int i, n, nbytes;
-        u8 buf[DES_BLOCK_SIZE];
-        u8 *out, *in;
+        unsigned int n, nbytes;
+        u8 buf[DES_BLOCK_SIZE], ctrbuf[DES_BLOCK_SIZE];
+        u8 *out, *in, *ctrptr = ctrbuf;
+
+        if (!walk->nbytes)
+                return ret;
 
-        memcpy(ctrblk, walk->iv, DES_BLOCK_SIZE);
+        if (spin_trylock(&ctrblk_lock))
+                ctrptr = ctrblk;
+
+        memcpy(ctrptr, walk->iv, DES_BLOCK_SIZE);
         while ((nbytes = walk->nbytes) >= DES_BLOCK_SIZE) {
                 out = walk->dst.virt.addr;
                 in = walk->src.virt.addr;
                 while (nbytes >= DES_BLOCK_SIZE) {
-                        /* align to block size, max. PAGE_SIZE */
-                        n = (nbytes > PAGE_SIZE) ? PAGE_SIZE :
-                                nbytes & ~(DES_BLOCK_SIZE - 1);
-                        for (i = DES_BLOCK_SIZE; i < n; i += DES_BLOCK_SIZE) {
-                                memcpy(ctrblk + i, ctrblk + i - DES_BLOCK_SIZE,
-                                       DES_BLOCK_SIZE);
-                                crypto_inc(ctrblk + i, DES_BLOCK_SIZE);
-                        }
-                        ret = crypt_s390_kmctr(func, ctx->key, out, in, n, ctrblk);
-                        if (ret < 0 || ret != n)
+                        if (ctrptr == ctrblk)
+                                n = __ctrblk_init(ctrptr, nbytes);
+                        else
+                                n = DES_BLOCK_SIZE;
+                        ret = crypt_s390_kmctr(func, ctx->key, out, in,
+                                               n, ctrptr);
+                        if (ret < 0 || ret != n) {
+                                if (ctrptr == ctrblk)
+                                        spin_unlock(&ctrblk_lock);
                                 return -EIO;
+                        }
                         if (n > DES_BLOCK_SIZE)
-                                memcpy(ctrblk, ctrblk + n - DES_BLOCK_SIZE,
+                                memcpy(ctrptr, ctrptr + n - DES_BLOCK_SIZE,
                                        DES_BLOCK_SIZE);
-                        crypto_inc(ctrblk, DES_BLOCK_SIZE);
+                        crypto_inc(ctrptr, DES_BLOCK_SIZE);
                         out += n;
                         in += n;
                         nbytes -= n;
                 }
                 ret = blkcipher_walk_done(desc, walk, nbytes);
         }
-
+        if (ctrptr == ctrblk) {
+                if (nbytes)
+                        memcpy(ctrbuf, ctrptr, DES_BLOCK_SIZE);
+                else
+                        memcpy(walk->iv, ctrptr, DES_BLOCK_SIZE);
+                spin_unlock(&ctrblk_lock);
+        }
         /* final block may be < DES_BLOCK_SIZE, copy only nbytes */
         if (nbytes) {
                 out = walk->dst.virt.addr;
                 in = walk->src.virt.addr;
                 ret = crypt_s390_kmctr(func, ctx->key, buf, in,
-                                       DES_BLOCK_SIZE, ctrblk);
+                                       DES_BLOCK_SIZE, ctrbuf);
                 if (ret < 0 || ret != DES_BLOCK_SIZE)
                         return -EIO;
                 memcpy(out, buf, nbytes);
-                crypto_inc(ctrblk, DES_BLOCK_SIZE);
+                crypto_inc(ctrbuf, DES_BLOCK_SIZE);
                 ret = blkcipher_walk_done(desc, walk, 0);
+                memcpy(walk->iv, ctrbuf, DES_BLOCK_SIZE);
         }
-        memcpy(walk->iv, ctrblk, DES_BLOCK_SIZE);
         return ret;
 }
 
diff --git a/arch/s390/kernel/head64.S b/arch/s390/kernel/head64.S
index b9e25ae2579c..d7c00507568a 100644
--- a/arch/s390/kernel/head64.S
+++ b/arch/s390/kernel/head64.S
@@ -59,7 +59,7 @@ ENTRY(startup_continue)
         .quad   0                       # cr12: tracing off
         .quad   0                       # cr13: home space segment table
         .quad   0xc0000000              # cr14: machine check handling off
-        .quad   0                       # cr15: linkage stack operations
+        .quad   .Llinkage_stack         # cr15: linkage stack operations
 .Lpcmsk:.quad   0x0000000180000000
 .L4malign:.quad 0xffffffffffc00000
 .Lscan2g:.quad  0x80000000 + 0x20000 - 8        # 2GB + 128K - 8
@@ -67,12 +67,15 @@ ENTRY(startup_continue)
 .Lparmaddr:
         .quad   PARMAREA
         .align  64
-.Lduct: .long   0,0,0,0,.Lduald,0,0,0
+.Lduct: .long   0,.Laste,.Laste,0,.Lduald,0,0,0
         .long   0,0,0,0,0,0,0,0
+.Laste: .quad   0,0xffffffffffffffff,0,0,0,0,0,0
         .align  128
 .Lduald:.rept   8
         .long   0x80000000,0,0,0        # invalid access-list entries
         .endr
+.Llinkage_stack:
+        .long   0,0,0x89000000,0,0,0,0x8a000000,0
 
 ENTRY(_ehead)
 
diff --git a/arch/s390/mm/page-states.c b/arch/s390/mm/page-states.c
index a90d45e9dfb0..27c50f4d90cb 100644
--- a/arch/s390/mm/page-states.c
+++ b/arch/s390/mm/page-states.c
@@ -12,6 +12,8 @@
 #include <linux/mm.h>
 #include <linux/gfp.h>
 #include <linux/init.h>
+#include <asm/setup.h>
+#include <asm/ipl.h>
 
 #define ESSA_SET_STABLE         1
 #define ESSA_SET_UNUSED         2
@@ -41,6 +43,14 @@ void __init cmma_init(void)
 
         if (!cmma_flag)
                 return;
+        /*
+         * Disable CMM for dump, otherwise  the tprot based memory
+         * detection can fail because of unstable pages.
+         */
+        if (OLDMEM_BASE || ipl_info.type == IPL_TYPE_FCP_DUMP) {
+                cmma_flag = 0;
+                return;
+        }
         asm volatile(
                 "       .insn rrf,0xb9ab0000,%1,%1,0,0\n"
                 "0:     la      %0,0\n"
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index c51efdcd07a2..7d8b7e94b93b 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -27,7 +27,7 @@ config SPARC
         select RTC_DRV_M48T59
         select HAVE_DMA_ATTRS
         select HAVE_DMA_API_DEBUG
-        select HAVE_ARCH_JUMP_LABEL
+        select HAVE_ARCH_JUMP_LABEL if SPARC64
         select GENERIC_IRQ_SHOW
         select ARCH_WANT_IPC_PARSE_VERSION
         select GENERIC_PCI_IOMAP
diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c
index 869023abe5a4..cfbe53c17b0d 100644
--- a/arch/sparc/mm/srmmu.c
+++ b/arch/sparc/mm/srmmu.c
@@ -14,6 +14,7 @@
 #include <linux/pagemap.h>
 #include <linux/vmalloc.h>
 #include <linux/kdebug.h>
+#include <linux/export.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/log2.h>
@@ -62,6 +63,7 @@ extern unsigned long last_valid_pfn;
 static pgd_t *srmmu_swapper_pg_dir;
 
 const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops;
+EXPORT_SYMBOL(sparc32_cachetlb_ops);
 
 #ifdef CONFIG_SMP
 const struct sparc32_cachetlb_ops *local_ops;
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 940e50ebfafa..0af5250d914f 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -444,6 +444,7 @@ config X86_INTEL_MID
         bool "Intel MID platform support"
         depends on X86_32
         depends on X86_EXTENDED_PLATFORM
+        depends on X86_PLATFORM_DEVICES
         depends on PCI
         depends on PCI_GOANY
         depends on X86_IO_APIC
@@ -1051,9 +1052,9 @@ config MICROCODE_INTEL
           This options enables microcode patch loading support for Intel
           processors.
 
-          For latest news and information on obtaining all the required
-          Intel ingredients for this driver, check:
-          <http://www.urbanmyth.org/microcode/>.
+          For the current Intel microcode data package go to
+          <https://downloadcenter.intel.com> and search for
+          'Linux Processor Microcode Data File'.
 
 config MICROCODE_AMD
         bool "AMD microcode loading support"
diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug
index 0f3621ed1db6..321a52ccf63a 100644
--- a/arch/x86/Kconfig.debug
+++ b/arch/x86/Kconfig.debug
@@ -184,6 +184,7 @@ config HAVE_MMIOTRACE_SUPPORT
 config X86_DECODER_SELFTEST
         bool "x86 instruction decoder selftest"
         depends on DEBUG_KERNEL && KPROBES
+        depends on !COMPILE_TEST
         ---help---
          Perform x86 instruction decoder selftests at build time.
          This option is useful for checking the sanity of x86 instruction
diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index a54ee1d054d9..aaac3b2fb746 100644
--- a/arch/x86/include/asm/amd_nb.h
+++ b/arch/x86/include/asm/amd_nb.h
@@ -19,7 +19,7 @@ extern int amd_cache_northbridges(void);
 extern void amd_flush_garts(void);
 extern int amd_numa_init(void);
 extern int amd_get_subcaches(int);
-extern int amd_set_subcaches(int, int);
+extern int amd_set_subcaches(int, unsigned long);
 
 struct amd_l3_cache {
         unsigned indices;
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
index 3b978c472d08..3d6b9f81cc68 100644
--- a/arch/x86/include/asm/efi.h
+++ b/arch/x86/include/asm/efi.h
@@ -132,6 +132,8 @@ extern void __init efi_map_region_fixed(efi_memory_desc_t *md);
 extern void efi_sync_low_kernel_mappings(void);
 extern void efi_setup_page_tables(void);
 extern void __init old_map_region(efi_memory_desc_t *md);
+extern void __init runtime_code_page_mkexec(void);
+extern void __init efi_runtime_mkexec(void);
 
 struct efi_setup_data {
         u64 fw_vendor;
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index bbc8b12fa443..5ad38ad07890 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -445,10 +445,20 @@ static inline int pte_same(pte_t a, pte_t b)
         return a.pte == b.pte;
 }
 
+static inline int pteval_present(pteval_t pteval)
+{
+        /*
+         * Yes Linus, _PAGE_PROTNONE == _PAGE_NUMA. Expressing it this
+         * way clearly states that the intent is that protnone and numa
+         * hinting ptes are considered present for the purposes of
+         * pagetable operations like zapping, protection changes, gup etc.
+         */
+        return pteval & (_PAGE_PRESENT | _PAGE_PROTNONE | _PAGE_NUMA);
+}
+
 static inline int pte_present(pte_t a)
 {
-        return pte_flags(a) & (_PAGE_PRESENT | _PAGE_PROTNONE |
-                               _PAGE_NUMA);
+        return pteval_present(pte_flags(a));
 }
 
 #define pte_accessible pte_accessible
diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
index e6d90babc245..04905bfc508b 100644
--- a/arch/x86/include/asm/tlbflush.h
+++ b/arch/x86/include/asm/tlbflush.h
@@ -62,7 +62,7 @@ static inline void __flush_tlb_all(void)
 
 static inline void __flush_tlb_one(unsigned long addr)
 {
-        count_vm_event(NR_TLB_LOCAL_FLUSH_ONE);
+        count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
         __flush_tlb_single(addr);
 }
 
@@ -93,13 +93,13 @@ static inline void __flush_tlb_one(unsigned long addr)
  */
 static inline void __flush_tlb_up(void)
 {
-        count_vm_event(NR_TLB_LOCAL_FLUSH_ALL);
+        count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
         __flush_tlb();
 }
 
 static inline void flush_tlb_all(void)
 {
-        count_vm_event(NR_TLB_LOCAL_FLUSH_ALL);
+        count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
         __flush_tlb_all();
 }
 
diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
index 57ae63cd6ee2..94605c0e9cee 100644
--- a/arch/x86/include/asm/tsc.h
+++ b/arch/x86/include/asm/tsc.h
@@ -66,6 +66,6 @@ extern void tsc_save_sched_clock_state(void);
 extern void tsc_restore_sched_clock_state(void);
 
 /* MSR based TSC calibration for Intel Atom SoC platforms */
-int try_msr_calibrate_tsc(unsigned long *fast_calibrate);
+unsigned long try_msr_calibrate_tsc(void);
 
 #endif /* _ASM_X86_TSC_H */
diff --git a/arch/x86/include/asm/xen/page.h b/arch/x86/include/asm/xen/page.h
index 787e1bb5aafc..3e276eb23d1b 100644
--- a/arch/x86/include/asm/xen/page.h
+++ b/arch/x86/include/asm/xen/page.h
@@ -52,8 +52,7 @@ extern unsigned long set_phys_range_identity(unsigned long pfn_s,
 extern int m2p_add_override(unsigned long mfn, struct page *page,
                             struct gnttab_map_grant_ref *kmap_op);
 extern int m2p_remove_override(struct page *page,
-                               struct gnttab_map_grant_ref *kmap_op,
-                               unsigned long mfn);
+                                struct gnttab_map_grant_ref *kmap_op);
 extern struct page *m2p_find_override(unsigned long mfn);
 extern unsigned long m2p_find_override_pfn(unsigned long mfn, unsigned long pfn);
 
@@ -122,7 +121,7 @@ static inline unsigned long mfn_to_pfn(unsigned long mfn)
                 pfn = m2p_find_override_pfn(mfn, ~0);
         }
 
-        /*
+        /* 
          * pfn is ~0 if there are no entries in the m2p for mfn or if the
          * entry doesn't map back to the mfn and m2p_override doesn't have a
          * valid entry for it.
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 59554dca96ec..dec8de4e1663 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -179,7 +179,7 @@ int amd_get_subcaches(int cpu)
         return (mask >> (4 * cuid)) & 0xf;
 }
 
-int amd_set_subcaches(int cpu, int mask)
+int amd_set_subcaches(int cpu, unsigned long mask)
 {
         static unsigned int reset, ban;
         struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu));
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index d3153e281d72..c67ffa686064 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -767,10 +767,7 @@ static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 
 static void cpu_set_tlb_flushall_shift(struct cpuinfo_x86 *c)
 {
-        tlb_flushall_shift = 5;
-
-        if (c->x86 <= 0x11)
-                tlb_flushall_shift = 4;
+        tlb_flushall_shift = 6;
 }
 
 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 24b6fd10625a..8e28bf2fc3ef 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -284,8 +284,13 @@ static __always_inline void setup_smap(struct cpuinfo_x86 *c)
         raw_local_save_flags(eflags);
         BUG_ON(eflags & X86_EFLAGS_AC);
 
-        if (cpu_has(c, X86_FEATURE_SMAP))
+        if (cpu_has(c, X86_FEATURE_SMAP)) {
+#ifdef CONFIG_X86_SMAP
                 set_in_cr4(X86_CR4_SMAP);
+#else
+                clear_in_cr4(X86_CR4_SMAP);
+#endif
+        }
 }
 
 /*
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 3db61c644e44..5cd9bfabd645 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -640,21 +640,17 @@ static void intel_tlb_flushall_shift_set(struct cpuinfo_x86 *c)
         case 0x61d: /* six-core 45 nm xeon "Dunnington" */
                 tlb_flushall_shift = -1;
                 break;
+        case 0x63a: /* Ivybridge */
+                tlb_flushall_shift = 2;
+                break;
         case 0x61a: /* 45 nm nehalem, "Bloomfield" */
         case 0x61e: /* 45 nm nehalem, "Lynnfield" */
         case 0x625: /* 32 nm nehalem, "Clarkdale" */
         case 0x62c: /* 32 nm nehalem, "Gulftown" */
         case 0x62e: /* 45 nm nehalem-ex, "Beckton" */
         case 0x62f: /* 32 nm Xeon E7 */
-                tlb_flushall_shift = 6;
-                break;
         case 0x62a: /* SandyBridge */
         case 0x62d: /* SandyBridge, "Romely-EP" */
-                tlb_flushall_shift = 5;
-                break;
-        case 0x63a: /* Ivybridge */
-                tlb_flushall_shift = 1;
-                break;
         default:
                 tlb_flushall_shift = 6;
         }
diff --git a/arch/x86/kernel/cpu/microcode/amd_early.c b/arch/x86/kernel/cpu/microcode/amd_early.c
index 8384c0fa206f..617a9e284245 100644
--- a/arch/x86/kernel/cpu/microcode/amd_early.c
+++ b/arch/x86/kernel/cpu/microcode/amd_early.c
@@ -285,6 +285,15 @@ static void __init collect_cpu_sig_on_bsp(void *arg)
 
         uci->cpu_sig.sig = cpuid_eax(0x00000001);
 }
+
+static void __init get_bsp_sig(void)
+{
+        unsigned int bsp = boot_cpu_data.cpu_index;
+        struct ucode_cpu_info *uci = ucode_cpu_info + bsp;
+
+        if (!uci->cpu_sig.sig)
+                smp_call_function_single(bsp, collect_cpu_sig_on_bsp, NULL, 1);
+}
 #else
 void load_ucode_amd_ap(void)
 {
@@ -337,31 +346,37 @@ void load_ucode_amd_ap(void)
 
 int __init save_microcode_in_initrd_amd(void)
 {
+        unsigned long cont;
         enum ucode_state ret;
         u32 eax;
 
-#ifdef CONFIG_X86_32
-        unsigned int bsp = boot_cpu_data.cpu_index;
-        struct ucode_cpu_info *uci = ucode_cpu_info + bsp;
-
-        if (!uci->cpu_sig.sig)
-                smp_call_function_single(bsp, collect_cpu_sig_on_bsp, NULL, 1);
+        if (!container)
+                return -EINVAL;
 
+#ifdef CONFIG_X86_32
+        get_bsp_sig();
+        cont = (unsigned long)container;
+#else
         /*
-         * Take into account the fact that the ramdisk might get relocated
-         * and therefore we need to recompute the container's position in
-         * virtual memory space.
+         * We need the physical address of the container for both bitness since
+         * boot_params.hdr.ramdisk_image is a physical address.
          */
-        container = (u8 *)(__va((u32)relocated_ramdisk) +
-                           ((u32)container - boot_params.hdr.ramdisk_image));
+        cont = __pa(container);
 #endif
+
+        /*
+         * Take into account the fact that the ramdisk might get relocated and
+         * therefore we need to recompute the container's position in virtual
+         * memory space.
+         */
+        if (relocated_ramdisk)
+                container = (u8 *)(__va(relocated_ramdisk) +
+                             (cont - boot_params.hdr.ramdisk_image));
+
         if (ucode_new_rev)
                 pr_info("microcode: updated early to new patch_level=0x%08x\n",
                         ucode_new_rev);
 
-        if (!container)
-                return -EINVAL;
-
         eax   = cpuid_eax(0x00000001);
         eax   = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
 
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index ce2d0a2c3e4f..0e25a1bc5ab5 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -683,7 +683,7 @@ static void prepare_set(void) __acquires(set_atomicity_lock)
         }
 
         /* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
-        count_vm_event(NR_TLB_LOCAL_FLUSH_ALL);
+        count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
         __flush_tlb();
 
         /* Save MTRR state */
@@ -697,7 +697,7 @@ static void prepare_set(void) __acquires(set_atomicity_lock)
 static void post_set(void) __releases(set_atomicity_lock)
 {
         /* Flush TLBs (no need to flush caches - they are disabled) */
-        count_vm_event(NR_TLB_LOCAL_FLUSH_ALL);
+        count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
         __flush_tlb();
 
         /* Intel (P6) standard MTRRs */
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index b88645191fe5..895604f2e916 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -1521,6 +1521,8 @@ static int __init init_hw_perf_events(void)
 
         pr_cont("%s PMU driver.\n", x86_pmu.name);
 
+        x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
+
         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
                 quirk->func();
 
@@ -1534,7 +1536,6 @@ static int __init init_hw_perf_events(void)
                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
                                    0, x86_pmu.num_counters, 0, 0);
 
-        x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
 
         if (x86_pmu.event_attrs)
@@ -1820,9 +1821,12 @@ static ssize_t set_attr_rdpmc(struct device *cdev,
         if (ret)
                 return ret;
 
+        if (x86_pmu.attr_rdpmc_broken)
+                return -ENOTSUPP;
+
         if (!!val != !!x86_pmu.attr_rdpmc) {
                 x86_pmu.attr_rdpmc = !!val;
-                smp_call_function(change_rdpmc, (void *)val, 1);
+                on_each_cpu(change_rdpmc, (void *)val, 1);
         }
 
         return count;
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index c1a861829d81..4972c244d0bc 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -409,6 +409,7 @@ struct x86_pmu {
         /*
          * sysfs attrs
          */
+        int             attr_rdpmc_broken;
         int             attr_rdpmc;
         struct attribute **format_attrs;
         struct attribute **event_attrs;
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 0fa4f242f050..aa333d966886 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1361,10 +1361,8 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
         intel_pmu_disable_all();
         handled = intel_pmu_drain_bts_buffer();
         status = intel_pmu_get_status();
-        if (!status) {
-                intel_pmu_enable_all(0);
-                return handled;
-        }
+        if (!status)
+                goto done;
 
         loops = 0;
 again:
@@ -2310,10 +2308,7 @@ __init int intel_pmu_init(void)
         if (version > 1)
                 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
 
-        /*
-         * v2 and above have a perf capabilities MSR
-         */
-        if (version > 1) {
+        if (boot_cpu_has(X86_FEATURE_PDCM)) {
                 u64 capabilities;
 
                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
index 29c248799ced..c88f7f4b03ee 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
@@ -501,8 +501,11 @@ static struct extra_reg snbep_uncore_cbox_extra_regs[] = {
         SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
                                   SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0x6),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0x6),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0x6),
         SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x6),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x8),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x8),
@@ -1178,10 +1181,15 @@ static struct extra_reg ivt_uncore_cbox_extra_regs[] = {
         SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
                                   SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
         SNBEP_CBO_EVENT_EXTRA_REG(0x1031, 0x10ff, 0x2),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0xc),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x5134, 0xffff, 0xc),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0xc),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0xc),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
-        SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0xc),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0xc),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x10),
         SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10),
         SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10),
diff --git a/arch/x86/kernel/cpu/perf_event_p6.c b/arch/x86/kernel/cpu/perf_event_p6.c
index b1e2fe115323..7c1a0c07b607 100644
--- a/arch/x86/kernel/cpu/perf_event_p6.c
+++ b/arch/x86/kernel/cpu/perf_event_p6.c
@@ -231,31 +231,49 @@ static __initconst const struct x86_pmu p6_pmu = {
 
 };
 
+static __init void p6_pmu_rdpmc_quirk(void)
+{
+        if (boot_cpu_data.x86_mask < 9) {
+                /*
+                 * PPro erratum 26; fixed in stepping 9 and above.
+                 */
+                pr_warn("Userspace RDPMC support disabled due to a CPU erratum\n");
+                x86_pmu.attr_rdpmc_broken = 1;
+                x86_pmu.attr_rdpmc = 0;
+        }
+}
+
 __init int p6_pmu_init(void)
 {
+        x86_pmu = p6_pmu;
+
         switch (boot_cpu_data.x86_model) {
-        case 1:
-        case 3:  /* Pentium Pro */
-        case 5:
-        case 6:  /* Pentium II */
-        case 7:
-        case 8:
-        case 11: /* Pentium III */
-        case 9:
-        case 13:
-                /* Pentium M */
+        case  1: /* Pentium Pro */
+                x86_add_quirk(p6_pmu_rdpmc_quirk);
+                break;
+
+        case  3: /* Pentium II - Klamath */
+        case  5: /* Pentium II - Deschutes */
+        case  6: /* Pentium II - Mendocino */
                 break;
+
+        case  7: /* Pentium III - Katmai */
+        case  8: /* Pentium III - Coppermine */
+        case 10: /* Pentium III Xeon */
+        case 11: /* Pentium III - Tualatin */
+                break;
+
+        case  9: /* Pentium M - Banias */
+        case 13: /* Pentium M - Dothan */
+                break;
+
         default:
-                pr_cont("unsupported p6 CPU model %d ",
-                        boot_cpu_data.x86_model);
+                pr_cont("unsupported p6 CPU model %d ", boot_cpu_data.x86_model);
                 return -ENODEV;
         }
 
-        x86_pmu = p6_pmu;
-
         memcpy(hw_cache_event_ids, p6_hw_cache_event_ids,
                 sizeof(hw_cache_event_ids));
 
-
         return 0;
 }
diff --git a/arch/x86/kernel/ftrace.c b/arch/x86/kernel/ftrace.c
index d4bdd253fea7..e6253195a301 100644
--- a/arch/x86/kernel/ftrace.c
+++ b/arch/x86/kernel/ftrace.c
@@ -77,8 +77,7 @@ within(unsigned long addr, unsigned long start, unsigned long end)
         return addr >= start && addr < end;
 }
 
-static int
-do_ftrace_mod_code(unsigned long ip, const void *new_code)
+static unsigned long text_ip_addr(unsigned long ip)
 {
         /*
          * On x86_64, kernel text mappings are mapped read-only with
@@ -91,7 +90,7 @@ do_ftrace_mod_code(unsigned long ip, const void *new_code)
         if (within(ip, (unsigned long)_text, (unsigned long)_etext))
                 ip = (unsigned long)__va(__pa_symbol(ip));
 
-        return probe_kernel_write((void *)ip, new_code, MCOUNT_INSN_SIZE);
+        return ip;
 }
 
 static const unsigned char *ftrace_nop_replace(void)
@@ -123,8 +122,10 @@ ftrace_modify_code_direct(unsigned long ip, unsigned const char *old_code,
         if (memcmp(replaced, old_code, MCOUNT_INSN_SIZE) != 0)
                 return -EINVAL;
 
+        ip = text_ip_addr(ip);
+
         /* replace the text with the new text */
-        if (do_ftrace_mod_code(ip, new_code))
+        if (probe_kernel_write((void *)ip, new_code, MCOUNT_INSN_SIZE))
                 return -EPERM;
 
         sync_core();
@@ -221,37 +222,51 @@ int ftrace_modify_call(struct dyn_ftrace *rec, unsigned long old_addr,
         return -EINVAL;
 }
 
-int ftrace_update_ftrace_func(ftrace_func_t func)
+static unsigned long ftrace_update_func;
+
+static int update_ftrace_func(unsigned long ip, void *new)
 {
-        unsigned long ip = (unsigned long)(&ftrace_call);
-        unsigned char old[MCOUNT_INSN_SIZE], *new;
+        unsigned char old[MCOUNT_INSN_SIZE];
         int ret;
 
-        memcpy(old, &ftrace_call, MCOUNT_INSN_SIZE);
-        new = ftrace_call_replace(ip, (unsigned long)func);
+        memcpy(old, (void *)ip, MCOUNT_INSN_SIZE);
+
+        ftrace_update_func = ip;
+        /* Make sure the breakpoints see the ftrace_update_func update */
+        smp_wmb();
 
         /* See comment above by declaration of modifying_ftrace_code */
         atomic_inc(&modifying_ftrace_code);
 
         ret = ftrace_modify_code(ip, old, new);
 
+        atomic_dec(&modifying_ftrace_code);
+
+        return ret;
+}
+
+int ftrace_update_ftrace_func(ftrace_func_t func)
+{
+        unsigned long ip = (unsigned long)(&ftrace_call);
+        unsigned char *new;
+        int ret;
+
+        new = ftrace_call_replace(ip, (unsigned long)func);
+        ret = update_ftrace_func(ip, new);
+
         /* Also update the regs callback function */
         if (!ret) {
                 ip = (unsigned long)(&ftrace_regs_call);
-                memcpy(old, &ftrace_regs_call, MCOUNT_INSN_SIZE);
                 new = ftrace_call_replace(ip, (unsigned long)func);
-                ret = ftrace_modify_code(ip, old, new);
+                ret = update_ftrace_func(ip, new);
         }
 
-        atomic_dec(&modifying_ftrace_code);
-
         return ret;
 }
 
 static int is_ftrace_caller(unsigned long ip)
 {
-        if (ip == (unsigned long)(&ftrace_call) ||
-                ip == (unsigned long)(&ftrace_regs_call))
+        if (ip == ftrace_update_func)
                 return 1;
 
         return 0;
@@ -677,45 +692,41 @@ int __init ftrace_dyn_arch_init(void *data)
 #ifdef CONFIG_DYNAMIC_FTRACE
 extern void ftrace_graph_call(void);
 
-static int ftrace_mod_jmp(unsigned long ip,
-                          int old_offset, int new_offset)
+static unsigned char *ftrace_jmp_replace(unsigned long ip, unsigned long addr)
 {
-        unsigned char code[MCOUNT_INSN_SIZE];
+        static union ftrace_code_union calc;
 
-        if (probe_kernel_read(code, (void *)ip, MCOUNT_INSN_SIZE))
-                return -EFAULT;
+        /* Jmp not a call (ignore the .e8) */
+        calc.e8         = 0xe9;
+        calc.offset     = ftrace_calc_offset(ip + MCOUNT_INSN_SIZE, addr);
 
-        if (code[0] != 0xe9 || old_offset != *(int *)(&code[1]))
-                return -EINVAL;
+        /*
+         * ftrace external locks synchronize the access to the static variable.
+         */
+        return calc.code;
+}
 
-        *(int *)(&code[1]) = new_offset;
+static int ftrace_mod_jmp(unsigned long ip, void *func)
+{
+        unsigned char *new;
 
-        if (do_ftrace_mod_code(ip, &code))
-                return -EPERM;
+        new = ftrace_jmp_replace(ip, (unsigned long)func);
 
-        return 0;
+        return update_ftrace_func(ip, new);
 }
 
 int ftrace_enable_ftrace_graph_caller(void)
 {
         unsigned long ip = (unsigned long)(&ftrace_graph_call);
-        int old_offset, new_offset;
 
-        old_offset = (unsigned long)(&ftrace_stub) - (ip + MCOUNT_INSN_SIZE);
-        new_offset = (unsigned long)(&ftrace_graph_caller) - (ip + MCOUNT_INSN_SIZE);
-
-        return ftrace_mod_jmp(ip, old_offset, new_offset);
+        return ftrace_mod_jmp(ip, &ftrace_graph_caller);
 }
 
 int ftrace_disable_ftrace_graph_caller(void)
 {
         unsigned long ip = (unsigned long)(&ftrace_graph_call);
-        int old_offset, new_offset;
-
-        old_offset = (unsigned long)(&ftrace_graph_caller) - (ip + MCOUNT_INSN_SIZE);
-        new_offset = (unsigned long)(&ftrace_stub) - (ip + MCOUNT_INSN_SIZE);
 
-        return ftrace_mod_jmp(ip, old_offset, new_offset);
+        return ftrace_mod_jmp(ip, &ftrace_stub);
 }
 
 #endif /* !CONFIG_DYNAMIC_FTRACE */
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c
index dbb60878b744..d99f31d9a750 100644
--- a/arch/x86/kernel/irq.c
+++ b/arch/x86/kernel/irq.c
@@ -266,6 +266,14 @@ __visible void smp_trace_x86_platform_ipi(struct pt_regs *regs)
 EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
 
 #ifdef CONFIG_HOTPLUG_CPU
+
+/* These two declarations are only used in check_irq_vectors_for_cpu_disable()
+ * below, which is protected by stop_machine().  Putting them on the stack
+ * results in a stack frame overflow.  Dynamically allocating could result in a
+ * failure so declare these two cpumasks as global.
+ */
+static struct cpumask affinity_new, online_new;
+
 /*
  * This cpu is going to be removed and its vectors migrated to the remaining
  * online cpus.  Check to see if there are enough vectors in the remaining cpus.
@@ -277,7 +285,6 @@ int check_irq_vectors_for_cpu_disable(void)
         unsigned int this_cpu, vector, this_count, count;
         struct irq_desc *desc;
         struct irq_data *data;
-        struct cpumask affinity_new, online_new;
 
         this_cpu = smp_processor_id();
         cpumask_copy(&online_new, cpu_online_mask);
diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c
index 872079a67e4d..f7d0672481fd 100644
--- a/arch/x86/kernel/pci-dma.c
+++ b/arch/x86/kernel/pci-dma.c
@@ -100,8 +100,10 @@ void *dma_generic_alloc_coherent(struct device *dev, size_t size,
         flag |= __GFP_ZERO;
 again:
         page = NULL;
-        if (!(flag & GFP_ATOMIC))
+        /* CMA can be used only in the context which permits sleeping */
+        if (flag & __GFP_WAIT)
                 page = dma_alloc_from_contiguous(dev, count, get_order(size));
+        /* fallback */
         if (!page)
                 page = alloc_pages_node(dev_to_node(dev), flag, get_order(size));
         if (!page)
diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c
index 04ee1e2e4c02..7c6acd4b8995 100644
--- a/arch/x86/kernel/quirks.c
+++ b/arch/x86/kernel/quirks.c
@@ -571,3 +571,40 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F5,
                         quirk_amd_nb_node);
 
 #endif
+
+#ifdef CONFIG_PCI
+/*
+ * Processor does not ensure DRAM scrub read/write sequence
+ * is atomic wrt accesses to CC6 save state area. Therefore
+ * if a concurrent scrub read/write access is to same address
+ * the entry may appear as if it is not written. This quirk
+ * applies to Fam16h models 00h-0Fh
+ *
+ * See "Revision Guide" for AMD F16h models 00h-0fh,
+ * document 51810 rev. 3.04, Nov 2013
+ */
+static void amd_disable_seq_and_redirect_scrub(struct pci_dev *dev)
+{
+        u32 val;
+
+        /*
+         * Suggested workaround:
+         * set D18F3x58[4:0] = 00h and set D18F3x5C[0] = 0b
+         */
+        pci_read_config_dword(dev, 0x58, &val);
+        if (val & 0x1F) {
+                val &= ~(0x1F);
+                pci_write_config_dword(dev, 0x58, val);
+        }
+
+        pci_read_config_dword(dev, 0x5C, &val);
+        if (val & BIT(0)) {
+                val &= ~BIT(0);
+                pci_write_config_dword(dev, 0x5c, val);
+        }
+}
+
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3,
+                        amd_disable_seq_and_redirect_scrub);
+
+#endif
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 19e5adb49a27..cfbe99f88830 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -209,7 +209,7 @@ static inline unsigned long long cycles_2_ns(unsigned long long cyc)
          * dance when its actually needed.
          */
 
-        preempt_disable();
+        preempt_disable_notrace();
         data = this_cpu_read(cyc2ns.head);
         tail = this_cpu_read(cyc2ns.tail);
 
@@ -229,7 +229,7 @@ static inline unsigned long long cycles_2_ns(unsigned long long cyc)
                 if (!--data->__count)
                         this_cpu_write(cyc2ns.tail, data);
         }
-        preempt_enable();
+        preempt_enable_notrace();
 
         return ns;
 }
@@ -653,13 +653,10 @@ unsigned long native_calibrate_tsc(void)
 
         /* Calibrate TSC using MSR for Intel Atom SoCs */
         local_irq_save(flags);
-        i = try_msr_calibrate_tsc(&fast_calibrate);
+        fast_calibrate = try_msr_calibrate_tsc();
         local_irq_restore(flags);
-        if (i >= 0) {
-                if (i == 0)
-                        pr_warn("Fast TSC calibration using MSR failed\n");
+        if (fast_calibrate)
                 return fast_calibrate;
-        }
 
         local_irq_save(flags);
         fast_calibrate = quick_pit_calibrate();
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 8b5434f4389f..92ae6acac8a7 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -53,7 +53,7 @@ static struct freq_desc freq_desc_tables[] = {
         /* TNG */
         { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
         /* VLV2 */
-        { 6, 0x37, 1, { 0, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
+        { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
         /* ANN */
         { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
 };
@@ -77,21 +77,18 @@ static int match_cpu(u8 family, u8 model)
 
 /*
  * Do MSR calibration only for known/supported CPUs.
- * Return values:
- * -1: CPU is unknown/unsupported for MSR based calibration
- *  0: CPU is known/supported, but calibration failed
- *  1: CPU is known/supported, and calibration succeeded
+ *
+ * Returns the calibration value or 0 if MSR calibration failed.
  */
-int try_msr_calibrate_tsc(unsigned long *fast_calibrate)
+unsigned long try_msr_calibrate_tsc(void)
 {
-        int cpu_index;
         u32 lo, hi, ratio, freq_id, freq;
+        unsigned long res;
+        int cpu_index;
 
         cpu_index = match_cpu(boot_cpu_data.x86, boot_cpu_data.x86_model);
         if (cpu_index < 0)
-                return -1;
-
-        *fast_calibrate = 0;
+                return 0;
 
         if (freq_desc_tables[cpu_index].msr_plat) {
                 rdmsr(MSR_PLATFORM_INFO, lo, hi);
@@ -103,7 +100,7 @@ int try_msr_calibrate_tsc(unsigned long *fast_calibrate)
         pr_info("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
 
         if (!ratio)
-                return 0;
+                goto fail;
 
         /* Get FSB FREQ ID */
         rdmsr(MSR_FSB_FREQ, lo, hi);
@@ -112,16 +109,19 @@ int try_msr_calibrate_tsc(unsigned long *fast_calibrate)
         pr_info("Resolved frequency ID: %u, frequency: %u KHz\n",
                                 freq_id, freq);
         if (!freq)
-                return 0;
+                goto fail;
 
         /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
-        *fast_calibrate = freq * ratio;
-        pr_info("TSC runs at %lu KHz\n", *fast_calibrate);
+        res = freq * ratio;
+        pr_info("TSC runs at %lu KHz\n", res);
 
 #ifdef CONFIG_X86_LOCAL_APIC
         lapic_timer_frequency = (freq * 1000) / HZ;
         pr_info("lapic_timer_frequency = %d\n", lapic_timer_frequency);
 #endif
+        return res;
 
-        return 1;
+fail:
+        pr_warn("Fast TSC calibration using MSR failed\n");
+        return 0;
 }
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index 9d591c895803..6dea040cc3a1 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -1001,6 +1001,12 @@ static int fault_in_kernel_space(unsigned long address)
 
 static inline bool smap_violation(int error_code, struct pt_regs *regs)
 {
+        if (!IS_ENABLED(CONFIG_X86_SMAP))
+                return false;
+
+        if (!static_cpu_has(X86_FEATURE_SMAP))
+                return false;
+
         if (error_code & PF_USER)
                 return false;
 
@@ -1087,11 +1093,9 @@ __do_page_fault(struct pt_regs *regs, unsigned long error_code)
         if (unlikely(error_code & PF_RSVD))
                 pgtable_bad(regs, error_code, address);
 
-        if (static_cpu_has(X86_FEATURE_SMAP)) {
-                if (unlikely(smap_violation(error_code, regs))) {
-                        bad_area_nosemaphore(regs, error_code, address);
-                        return;
-                }
+        if (unlikely(smap_violation(error_code, regs))) {
+                bad_area_nosemaphore(regs, error_code, address);
+                return;
         }
 
         /*
diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c
index 81b2750f3666..27aa0455fab3 100644
--- a/arch/x86/mm/numa.c
+++ b/arch/x86/mm/numa.c
@@ -493,14 +493,6 @@ static int __init numa_register_memblks(struct numa_meminfo *mi)
                 struct numa_memblk *mb = &mi->blk[i];
                 memblock_set_node(mb->start, mb->end - mb->start,
                                   &memblock.memory, mb->nid);
-
-                /*
-                 * At this time, all memory regions reserved by memblock are
-                 * used by the kernel. Set the nid in memblock.reserved will
-                 * mark out all the nodes the kernel resides in.
-                 */
-                memblock_set_node(mb->start, mb->end - mb->start,
-                                  &memblock.reserved, mb->nid);
         }
 
         /*
@@ -565,10 +557,21 @@ static void __init numa_init_array(void)
 static void __init numa_clear_kernel_node_hotplug(void)
 {
         int i, nid;
-        nodemask_t numa_kernel_nodes;
+        nodemask_t numa_kernel_nodes = NODE_MASK_NONE;
         unsigned long start, end;
         struct memblock_type *type = &memblock.reserved;
 
+        /*
+         * At this time, all memory regions reserved by memblock are
+         * used by the kernel. Set the nid in memblock.reserved will
+         * mark out all the nodes the kernel resides in.
+         */
+        for (i = 0; i < numa_meminfo.nr_blks; i++) {
+                struct numa_memblk *mb = &numa_meminfo.blk[i];
+                memblock_set_node(mb->start, mb->end - mb->start,
+                                  &memblock.reserved, mb->nid);
+        }
+
         /* Mark all kernel nodes. */
         for (i = 0; i < type->cnt; i++)
                 node_set(type->regions[i].nid, numa_kernel_nodes);
diff --git a/arch/x86/mm/numa_32.c b/arch/x86/mm/numa_32.c
index 0342d27ca798..47b6436e41c2 100644
--- a/arch/x86/mm/numa_32.c
+++ b/arch/x86/mm/numa_32.c
@@ -52,6 +52,8 @@ void memory_present(int nid, unsigned long start, unsigned long end)
                         nid, start, end);
         printk(KERN_DEBUG "  Setting physnode_map array to node %d for pfns:\n", nid);
         printk(KERN_DEBUG "  ");
+        start = round_down(start, PAGES_PER_SECTION);
+        end = round_up(end, PAGES_PER_SECTION);
         for (pfn = start; pfn < end; pfn += PAGES_PER_SECTION) {
                 physnode_map[pfn / PAGES_PER_SECTION] = nid;
                 printk(KERN_CONT "%lx ", pfn);
diff --git a/arch/x86/mm/srat.c b/arch/x86/mm/srat.c
index 1a25187e151e..1953e9c9391a 100644
--- a/arch/x86/mm/srat.c
+++ b/arch/x86/mm/srat.c
@@ -42,15 +42,25 @@ static __init inline int srat_disabled(void)
         return acpi_numa < 0;
 }
 
-/* Callback for SLIT parsing */
+/*
+ * Callback for SLIT parsing.  pxm_to_node() returns NUMA_NO_NODE for
+ * I/O localities since SRAT does not list them.  I/O localities are
+ * not supported at this point.
+ */
 void __init acpi_numa_slit_init(struct acpi_table_slit *slit)
 {
         int i, j;
 
-        for (i = 0; i < slit->locality_count; i++)
-                for (j = 0; j < slit->locality_count; j++)
+        for (i = 0; i < slit->locality_count; i++) {
+                if (pxm_to_node(i) == NUMA_NO_NODE)
+                        continue;
+                for (j = 0; j < slit->locality_count; j++) {
+                        if (pxm_to_node(j) == NUMA_NO_NODE)
+                                continue;
                         numa_set_distance(pxm_to_node(i), pxm_to_node(j),
                                 slit->entry[slit->locality_count * i + j]);
+                }
+        }
 }
 
 /* Callback for Proximity Domain -> x2APIC mapping */
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index ae699b3bbac8..dd8dda167a24 100644
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -103,7 +103,7 @@ static void flush_tlb_func(void *info)
         if (f->flush_mm != this_cpu_read(cpu_tlbstate.active_mm))
                 return;
 
-        count_vm_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
+        count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
         if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
                 if (f->flush_end == TLB_FLUSH_ALL)
                         local_flush_tlb();
@@ -131,7 +131,7 @@ void native_flush_tlb_others(const struct cpumask *cpumask,
         info.flush_start = start;
         info.flush_end = end;
 
-        count_vm_event(NR_TLB_REMOTE_FLUSH);
+        count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
         if (is_uv_system()) {
                 unsigned int cpu;
 
@@ -151,44 +151,19 @@ void flush_tlb_current_task(void)
 
         preempt_disable();
 
-        count_vm_event(NR_TLB_LOCAL_FLUSH_ALL);
+        count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
         local_flush_tlb();
         if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
                 flush_tlb_others(mm_cpumask(mm), mm, 0UL, TLB_FLUSH_ALL);
         preempt_enable();
 }
 
-/*
- * It can find out the THP large page, or
- * HUGETLB page in tlb_flush when THP disabled
- */
-static inline unsigned long has_large_page(struct mm_struct *mm,
-                                 unsigned long start, unsigned long end)
-{
-        pgd_t *pgd;
-        pud_t *pud;
-        pmd_t *pmd;
-        unsigned long addr = ALIGN(start, HPAGE_SIZE);
-        for (; addr < end; addr += HPAGE_SIZE) {
-                pgd = pgd_offset(mm, addr);
-                if (likely(!pgd_none(*pgd))) {
-                        pud = pud_offset(pgd, addr);
-                        if (likely(!pud_none(*pud))) {
-                                pmd = pmd_offset(pud, addr);
-                                if (likely(!pmd_none(*pmd)))
-                                        if (pmd_large(*pmd))
-                                                return addr;
-                        }
-                }
-        }
-        return 0;
-}
-
 void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
                                 unsigned long end, unsigned long vmflag)
 {
         unsigned long addr;
         unsigned act_entries, tlb_entries = 0;
+        unsigned long nr_base_pages;
 
         preempt_disable();
         if (current->active_mm != mm)
@@ -210,21 +185,20 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
                 tlb_entries = tlb_lli_4k[ENTRIES];
         else
                 tlb_entries = tlb_lld_4k[ENTRIES];
+
         /* Assume all of TLB entries was occupied by this task */
-        act_entries = mm->total_vm > tlb_entries ? tlb_entries : mm->total_vm;
+        act_entries = tlb_entries >> tlb_flushall_shift;
+        act_entries = mm->total_vm > act_entries ? act_entries : mm->total_vm;
+        nr_base_pages = (end - start) >> PAGE_SHIFT;
 
         /* tlb_flushall_shift is on balance point, details in commit log */
-        if ((end - start) >> PAGE_SHIFT > act_entries >> tlb_flushall_shift) {
-                count_vm_event(NR_TLB_LOCAL_FLUSH_ALL);
+        if (nr_base_pages > act_entries) {
+                count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
                 local_flush_tlb();
         } else {
-                if (has_large_page(mm, start, end)) {
-                        local_flush_tlb();
-                        goto flush_all;
-                }
                 /* flush range by one by one 'invlpg' */
                 for (addr = start; addr < end;  addr += PAGE_SIZE) {
-                        count_vm_event(NR_TLB_LOCAL_FLUSH_ONE);
+                        count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
                         __flush_tlb_single(addr);
                 }
 
@@ -262,7 +236,7 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long start)
 
 static void do_flush_tlb_all(void *info)
 {
-        count_vm_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
+        count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
         __flush_tlb_all();
         if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_LAZY)
                 leave_mm(smp_processor_id());
@@ -270,7 +244,7 @@ static void do_flush_tlb_all(void *info)
 
 void flush_tlb_all(void)
 {
-        count_vm_event(NR_TLB_REMOTE_FLUSH);
+        count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
         on_each_cpu(do_flush_tlb_all, NULL, 1);
 }
 
diff --git a/arch/x86/platform/efi/efi-bgrt.c b/arch/x86/platform/efi/efi-bgrt.c
index 7145ec63c520..f15103dff4b4 100644
--- a/arch/x86/platform/efi/efi-bgrt.c
+++ b/arch/x86/platform/efi/efi-bgrt.c
@@ -42,14 +42,15 @@ void __init efi_bgrt_init(void)
 
         if (bgrt_tab->header.length < sizeof(*bgrt_tab))
                 return;
-        if (bgrt_tab->version != 1)
+        if (bgrt_tab->version != 1 || bgrt_tab->status != 1)
                 return;
         if (bgrt_tab->image_type != 0 || !bgrt_tab->image_address)
                 return;
 
         image = efi_lookup_mapped_addr(bgrt_tab->image_address);
         if (!image) {
-                image = ioremap(bgrt_tab->image_address, sizeof(bmp_header));
+                image = early_memremap(bgrt_tab->image_address,
+                                       sizeof(bmp_header));
                 ioremapped = true;
                 if (!image)
                         return;
@@ -57,7 +58,7 @@ void __init efi_bgrt_init(void)
 
         memcpy_fromio(&bmp_header, image, sizeof(bmp_header));
         if (ioremapped)
-                iounmap(image);
+                early_iounmap(image, sizeof(bmp_header));
         bgrt_image_size = bmp_header.size;
 
         bgrt_image = kmalloc(bgrt_image_size, GFP_KERNEL);
@@ -65,7 +66,8 @@ void __init efi_bgrt_init(void)
                 return;
 
         if (ioremapped) {
-                image = ioremap(bgrt_tab->image_address, bmp_header.size);
+                image = early_memremap(bgrt_tab->image_address,
+                                       bmp_header.size);
                 if (!image) {
                         kfree(bgrt_image);
                         bgrt_image = NULL;
@@ -75,5 +77,5 @@ void __init efi_bgrt_init(void)
 
         memcpy_fromio(bgrt_image, image, bgrt_image_size);
         if (ioremapped)
-                iounmap(image);
+                early_iounmap(image, bmp_header.size);
 }
diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c
index d62ec87a2b26..1a201ac7cef8 100644
--- a/arch/x86/platform/efi/efi.c
+++ b/arch/x86/platform/efi/efi.c
@@ -792,7 +792,7 @@ void __init efi_set_executable(efi_memory_desc_t *md, bool executable)
                 set_memory_nx(addr, npages);
 }
 
-static void __init runtime_code_page_mkexec(void)
+void __init runtime_code_page_mkexec(void)
 {
         efi_memory_desc_t *md;
         void *p;
@@ -1069,8 +1069,7 @@ void __init efi_enter_virtual_mode(void)
         efi.update_capsule = virt_efi_update_capsule;
         efi.query_capsule_caps = virt_efi_query_capsule_caps;
 
-        if (efi_enabled(EFI_OLD_MEMMAP) && (__supported_pte_mask & _PAGE_NX))
-                runtime_code_page_mkexec();
+        efi_runtime_mkexec();
 
         kfree(new_memmap);
 
diff --git a/arch/x86/platform/efi/efi_32.c b/arch/x86/platform/efi/efi_32.c
index 249b183cf417..0b74cdf7f816 100644
--- a/arch/x86/platform/efi/efi_32.c
+++ b/arch/x86/platform/efi/efi_32.c
@@ -77,3 +77,9 @@ void efi_call_phys_epilog(void)
 
         local_irq_restore(efi_rt_eflags);
 }
+
+void __init efi_runtime_mkexec(void)
+{
+        if (__supported_pte_mask & _PAGE_NX)
+                runtime_code_page_mkexec();
+}
diff --git a/arch/x86/platform/efi/efi_64.c b/arch/x86/platform/efi/efi_64.c
index 6284f158a47d..0c2a234fef1e 100644
--- a/arch/x86/platform/efi/efi_64.c
+++ b/arch/x86/platform/efi/efi_64.c
@@ -233,3 +233,12 @@ void __init parse_efi_setup(u64 phys_addr, u32 data_len)
 {
         efi_setup = phys_addr + sizeof(struct setup_data);
 }
+
+void __init efi_runtime_mkexec(void)
+{
+        if (!efi_enabled(EFI_OLD_MEMMAP))
+                return;
+
+        if (__supported_pte_mask & _PAGE_NX)
+                runtime_code_page_mkexec();
+}
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index a4d7b647867f..201d09a7c46b 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -1473,6 +1473,18 @@ static void xen_pvh_set_cr_flags(int cpu)
          * X86_CR0_TS, X86_CR0_PE, X86_CR0_ET are set by Xen for HVM guests
          * (which PVH shared codepaths), while X86_CR0_PG is for PVH. */
         write_cr0(read_cr0() | X86_CR0_MP | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM);
+
+        if (!cpu)
+                return;
+        /*
+         * For BSP, PSE PGE are set in probe_page_size_mask(), for APs
+         * set them here. For all, OSFXSR OSXMMEXCPT are set in fpu_init.
+        */
+        if (cpu_has_pse)
+                set_in_cr4(X86_CR4_PSE);
+
+        if (cpu_has_pge)
+                set_in_cr4(X86_CR4_PGE);
 }
 
 /*
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index 2423ef04ffea..256282e7888b 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -365,7 +365,7 @@ void xen_ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
 /* Assume pteval_t is equivalent to all the other *val_t types. */
 static pteval_t pte_mfn_to_pfn(pteval_t val)
 {
-        if (val & _PAGE_PRESENT) {
+        if (pteval_present(val)) {
                 unsigned long mfn = (val & PTE_PFN_MASK) >> PAGE_SHIFT;
                 unsigned long pfn = mfn_to_pfn(mfn);
 
@@ -381,7 +381,7 @@ static pteval_t pte_mfn_to_pfn(pteval_t val)
 
 static pteval_t pte_pfn_to_mfn(pteval_t val)
 {
-        if (val & _PAGE_PRESENT) {
+        if (pteval_present(val)) {
                 unsigned long pfn = (val & PTE_PFN_MASK) >> PAGE_SHIFT;
                 pteval_t flags = val & PTE_FLAGS_MASK;
                 unsigned long mfn;
diff --git a/arch/x86/xen/p2m.c b/arch/x86/xen/p2m.c
index 8009acbe41e4..696c694986d0 100644
--- a/arch/x86/xen/p2m.c
+++ b/arch/x86/xen/p2m.c
@@ -899,6 +899,13 @@ int m2p_add_override(unsigned long mfn, struct page *page,
                                         "m2p_add_override: pfn %lx not mapped", pfn))
                         return -EINVAL;
         }
+        WARN_ON(PagePrivate(page));
+        SetPagePrivate(page);
+        set_page_private(page, mfn);
+        page->index = pfn_to_mfn(pfn);
+
+        if (unlikely(!set_phys_to_machine(pfn, FOREIGN_FRAME(mfn))))
+                return -ENOMEM;
 
         if (kmap_op != NULL) {
                 if (!PageHighMem(page)) {
@@ -937,16 +944,19 @@ int m2p_add_override(unsigned long mfn, struct page *page,
 }
 EXPORT_SYMBOL_GPL(m2p_add_override);
 int m2p_remove_override(struct page *page,
-                        struct gnttab_map_grant_ref *kmap_op,
-                        unsigned long mfn)
+                struct gnttab_map_grant_ref *kmap_op)
 {
         unsigned long flags;
+        unsigned long mfn;
         unsigned long pfn;
         unsigned long uninitialized_var(address);
         unsigned level;
         pte_t *ptep = NULL;
 
         pfn = page_to_pfn(page);
+        mfn = get_phys_to_machine(pfn);
+        if (mfn == INVALID_P2M_ENTRY || !(mfn & FOREIGN_FRAME_BIT))
+                return -EINVAL;
 
         if (!PageHighMem(page)) {
                 address = (unsigned long)__va(pfn << PAGE_SHIFT);
@@ -960,7 +970,10 @@ int m2p_remove_override(struct page *page,
         spin_lock_irqsave(&m2p_override_lock, flags);
         list_del(&page->lru);
         spin_unlock_irqrestore(&m2p_override_lock, flags);
+        WARN_ON(!PagePrivate(page));
+        ClearPagePrivate(page);
 
+        set_phys_to_machine(pfn, page->index);
         if (kmap_op != NULL) {
                 if (!PageHighMem(page)) {
                         struct multicall_space mcs;