2001 files changed, 64868 insertions, 40029 deletions

diff --git a/arch/Kconfig b/arch/Kconfig
index 1455579791ec..dd0e8eb8042f 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -157,9 +157,6 @@ config ARCH_USE_BUILTIN_BSWAP
          instructions should set this. And it shouldn't hurt to set it
          on architectures that don't have such instructions.
 
-config HAVE_SYSCALL_WRAPPERS
-        bool
-
 config KRETPROBES
         def_bool y
         depends on KPROBES && HAVE_KRETPROBES
@@ -384,6 +381,12 @@ config MODULES_USE_ELF_REL
           Modules only use ELF REL relocations.  Modules with ELF RELA
           relocations will give an error.
 
+config HAVE_UNDERSCORE_SYMBOL_PREFIX
+        bool
+        help
+          Some architectures generate an _ in front of C symbols; things like
+          module loading and assembly files need to know about this.
+
 #
 # ABI hall of shame
 #
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 8a33ba01301f..8629127640cf 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -4,7 +4,6 @@ config ALPHA
         select HAVE_AOUT
         select HAVE_IDE
         select HAVE_OPROFILE
-        select HAVE_SYSCALL_WRAPPERS
         select HAVE_PCSPKR_PLATFORM
         select HAVE_PERF_EVENTS
         select HAVE_DMA_ATTRS
diff --git a/arch/alpha/include/asm/linkage.h b/arch/alpha/include/asm/linkage.h
index 291c2d01c44f..7cfd06e8c935 100644
--- a/arch/alpha/include/asm/linkage.h
+++ b/arch/alpha/include/asm/linkage.h
@@ -1,6 +1,8 @@
 #ifndef __ASM_LINKAGE_H
 #define __ASM_LINKAGE_H
 
-/* Nothing to see here... */
+#define cond_syscall(x)  asm(".weak\t" #x "\n" #x " = sys_ni_syscall")
+#define SYSCALL_ALIAS(alias, name)                                      \
+        asm ( #alias " = " #name "\n\t.globl " #alias)
 
 #endif
diff --git a/arch/alpha/include/asm/thread_info.h b/arch/alpha/include/asm/thread_info.h
index 1f8c72959fb6..52cd2a4a3ff4 100644
--- a/arch/alpha/include/asm/thread_info.h
+++ b/arch/alpha/include/asm/thread_info.h
@@ -95,8 +95,6 @@ register struct thread_info *__current_thread_info __asm__("$8");
 #define TS_POLLING              0x0010  /* idle task polling need_resched,
                                            skip sending interrupt */
 
-#define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING)
-
 #ifndef __ASSEMBLY__
 #define HAVE_SET_RESTORE_SIGMASK        1
 static inline void set_restore_sigmask(void)
diff --git a/arch/alpha/include/asm/unistd.h b/arch/alpha/include/asm/unistd.h
index 6d6fe7ab5473..43baee17acdf 100644
--- a/arch/alpha/include/asm/unistd.h
+++ b/arch/alpha/include/asm/unistd.h
@@ -18,16 +18,4 @@
 #define __ARCH_WANT_SYS_VFORK
 #define __ARCH_WANT_SYS_CLONE
 
-/* "Conditional" syscalls.  What we want is
-
-        __attribute__((weak,alias("sys_ni_syscall")))
-
-   but that raises the problem of what type to give the symbol.  If we use
-   a prototype, it'll conflict with the definition given in this file and
-   others.  If we use __typeof, we discover that not all symbols actually
-   have declarations.  If we use no prototype, then we get warnings from
-   -Wstrict-prototypes.  Ho hum.  */
-
-#define cond_syscall(x)  asm(".weak\t" #x "\n" #x " = sys_ni_syscall")
-
 #endif /* _ALPHA_UNISTD_H */
diff --git a/arch/alpha/kernel/process.c b/arch/alpha/kernel/process.c
index 63d27fb9b023..ab80a80d38a2 100644
--- a/arch/alpha/kernel/process.c
+++ b/arch/alpha/kernel/process.c
@@ -46,25 +46,6 @@
 void (*pm_power_off)(void) = machine_power_off;
 EXPORT_SYMBOL(pm_power_off);
 
-void
-cpu_idle(void)
-{
-        current_thread_info()->status |= TS_POLLING;
-
-        while (1) {
-                /* FIXME -- EV6 and LCA45 know how to power down
-                   the CPU.  */
-
-                rcu_idle_enter();
-                while (!need_resched())
-                        cpu_relax();
-
-                rcu_idle_exit();
-                schedule_preempt_disabled();
-        }
-}
-
-
 struct halt_info {
         int mode;
         char *restart_cmd;
@@ -194,6 +175,7 @@ machine_power_off(void)
 void
 show_regs(struct pt_regs *regs)
 {
+        show_regs_print_info(KERN_DEFAULT);
         dik_show_regs(regs, NULL);
 }
 
diff --git a/arch/alpha/kernel/smp.c b/arch/alpha/kernel/smp.c
index 9603bc234b47..7b60834fb4b2 100644
--- a/arch/alpha/kernel/smp.c
+++ b/arch/alpha/kernel/smp.c
@@ -167,8 +167,7 @@ smp_callin(void)
               cpuid, current, current->active_mm));
 
         preempt_disable();
-        /* Do nothing.  */
-        cpu_idle();
+        cpu_startup_entry(CPUHP_ONLINE);
 }
 
 /* Wait until hwrpb->txrdy is clear for cpu.  Return -1 on timeout.  */
diff --git a/arch/alpha/kernel/srm_env.c b/arch/alpha/kernel/srm_env.c
index e64559f0a82d..ffe996a54fad 100644
--- a/arch/alpha/kernel/srm_env.c
+++ b/arch/alpha/kernel/srm_env.c
@@ -51,13 +51,11 @@ MODULE_LICENSE("GPL");
 typedef struct _srm_env {
         char                    *name;
         unsigned long           id;
-        struct proc_dir_entry   *proc_entry;
 } srm_env_t;
 
 static struct proc_dir_entry    *base_dir;
 static struct proc_dir_entry    *named_dir;
 static struct proc_dir_entry    *numbered_dir;
-static char                     number[256][4];
 
 static srm_env_t        srm_named_entries[] = {
         { "auto_action",        ENV_AUTO_ACTION         },
@@ -77,21 +75,18 @@ static srm_env_t	srm_named_entries[] = {
         { "tty_dev",            ENV_TTY_DEV             },
         { NULL,                 0                       },
 };
-static srm_env_t        srm_numbered_entries[256];
-
 
 static int srm_env_proc_show(struct seq_file *m, void *v)
 {
         unsigned long   ret;
-        srm_env_t       *entry;
+        unsigned long   id = (unsigned long)m->private;
         char            *page;
 
-        entry = m->private;
         page = (char *)__get_free_page(GFP_USER);
         if (!page)
                 return -ENOMEM;
 
-        ret = callback_getenv(entry->id, page, PAGE_SIZE);
+        ret = callback_getenv(id, page, PAGE_SIZE);
 
         if ((ret >> 61) == 0) {
                 seq_write(m, page, ret);
@@ -104,14 +99,14 @@ static int srm_env_proc_show(struct seq_file *m, void *v)
 
 static int srm_env_proc_open(struct inode *inode, struct file *file)
 {
-        return single_open(file, srm_env_proc_show, PDE(inode)->data);
+        return single_open(file, srm_env_proc_show, PDE_DATA(inode));
 }
 
 static ssize_t srm_env_proc_write(struct file *file, const char __user *buffer,
                                   size_t count, loff_t *pos)
 {
         int res;
-        srm_env_t       *entry = PDE(file_inode(file))->data;
+        unsigned long   id = (unsigned long)PDE_DATA(file_inode(file));
         char            *buf = (char *) __get_free_page(GFP_USER);
         unsigned long   ret1, ret2;
 
@@ -127,7 +122,7 @@ static ssize_t srm_env_proc_write(struct file *file, const char __user *buffer,
                 goto out;
         buf[count] = '\0';
 
-        ret1 = callback_setenv(entry->id, buf, count);
+        ret1 = callback_setenv(id, buf, count);
         if ((ret1 >> 61) == 0) {
                 do
                         ret2 = callback_save_env();
@@ -149,52 +144,6 @@ static const struct file_operations srm_env_proc_fops = {
         .write          = srm_env_proc_write,
 };
 
-static void
-srm_env_cleanup(void)
-{
-        srm_env_t       *entry;
-        unsigned long   var_num;
-
-        if (base_dir) {
-                /*
-                 * Remove named entries
-                 */
-                if (named_dir) {
-                        entry = srm_named_entries;
-                        while (entry->name != NULL && entry->id != 0) {
-                                if (entry->proc_entry) {
-                                        remove_proc_entry(entry->name,
-                                                        named_dir);
-                                        entry->proc_entry = NULL;
-                                }
-                                entry++;
-                        }
-                        remove_proc_entry(NAMED_DIR, base_dir);
-                }
-
-                /*
-                 * Remove numbered entries
-                 */
-                if (numbered_dir) {
-                        for (var_num = 0; var_num <= 255; var_num++) {
-                                entry = &srm_numbered_entries[var_num];
-
-                                if (entry->proc_entry) {
-                                        remove_proc_entry(entry->name,
-                                                        numbered_dir);
-                                        entry->proc_entry       = NULL;
-                                        entry->name             = NULL;
-                                }
-                        }
-                        remove_proc_entry(NUMBERED_DIR, base_dir);
-                }
-
-                remove_proc_entry(BASE_DIR, NULL);
-        }
-
-        return;
-}
-
 static int __init
 srm_env_init(void)
 {
@@ -213,19 +162,13 @@ srm_env_init(void)
         }
 
         /*
-         * Init numbers
-         */
-        for (var_num = 0; var_num <= 255; var_num++)
-                sprintf(number[var_num], "%ld", var_num);
-
-        /*
          * Create base directory
          */
         base_dir = proc_mkdir(BASE_DIR, NULL);
         if (!base_dir) {
                 printk(KERN_ERR "Couldn't create base dir /proc/%s\n",
                                 BASE_DIR);
-                goto cleanup;
+                return -ENOMEM;
         }
 
         /*
@@ -254,9 +197,8 @@ srm_env_init(void)
          */
         entry = srm_named_entries;
         while (entry->name && entry->id) {
-                entry->proc_entry = proc_create_data(entry->name, 0644, named_dir,
-                                                     &srm_env_proc_fops, entry);
-                if (!entry->proc_entry)
+                if (!proc_create_data(entry->name, 0644, named_dir,
+                             &srm_env_proc_fops, (void *)entry->id))
                         goto cleanup;
                 entry++;
         }
@@ -265,15 +207,11 @@ srm_env_init(void)
          * Create all numbered nodes
          */
         for (var_num = 0; var_num <= 255; var_num++) {
-                entry = &srm_numbered_entries[var_num];
-                entry->name = number[var_num];
-
-                entry->proc_entry = proc_create_data(entry->name, 0644, numbered_dir,
-                                                     &srm_env_proc_fops, entry);
-                if (!entry->proc_entry)
+                char name[4];
+                sprintf(name, "%ld", var_num);
+                if (!proc_create_data(name, 0644, numbered_dir,
+                             &srm_env_proc_fops, (void *)var_num))
                         goto cleanup;
-
-                entry->id                       = var_num;
         }
 
         printk(KERN_INFO "%s: version %s loaded successfully\n", NAME,
@@ -282,18 +220,15 @@ srm_env_init(void)
         return 0;
 
 cleanup:
-        srm_env_cleanup();
-
+        remove_proc_subtree(BASE_DIR, NULL);
         return -ENOMEM;
 }
 
 static void __exit
 srm_env_exit(void)
 {
-        srm_env_cleanup();
+        remove_proc_subtree(BASE_DIR, NULL);
         printk(KERN_INFO "%s: unloaded successfully\n", NAME);
-
-        return;
 }
 
 module_init(srm_env_init);
diff --git a/arch/alpha/kernel/sys_nautilus.c b/arch/alpha/kernel/sys_nautilus.c
index 1383f8601a93..1d4aabfcf9a1 100644
--- a/arch/alpha/kernel/sys_nautilus.c
+++ b/arch/alpha/kernel/sys_nautilus.c
@@ -185,7 +185,6 @@ nautilus_machine_check(unsigned long vector, unsigned long la_ptr)
         mb();
 }
 
-extern void free_reserved_mem(void *, void *);
 extern void pcibios_claim_one_bus(struct pci_bus *);
 
 static struct resource irongate_io = {
@@ -239,8 +238,8 @@ nautilus_init_pci(void)
         if (pci_mem < memtop)
                 memtop = pci_mem;
         if (memtop > alpha_mv.min_mem_address) {
-                free_reserved_mem(__va(alpha_mv.min_mem_address),
-                                  __va(memtop));
+                free_reserved_area((unsigned long)__va(alpha_mv.min_mem_address),
+                                   (unsigned long)__va(memtop), 0, NULL);
                 printk("nautilus_init_pci: %ldk freed\n",
                         (memtop - alpha_mv.min_mem_address) >> 10);
         }
diff --git a/arch/alpha/kernel/traps.c b/arch/alpha/kernel/traps.c
index 4037461a6493..affccb959a9e 100644
--- a/arch/alpha/kernel/traps.c
+++ b/arch/alpha/kernel/traps.c
@@ -169,13 +169,6 @@ void show_stack(struct task_struct *task, unsigned long *sp)
         dik_show_trace(sp);
 }
 
-void dump_stack(void)
-{
-        show_stack(NULL, NULL);
-}
-
-EXPORT_SYMBOL(dump_stack);
-
 void
 die_if_kernel(char * str, struct pt_regs *regs, long err, unsigned long *r9_15)
 {
diff --git a/arch/alpha/mm/init.c b/arch/alpha/mm/init.c
index 1ad6ca74bed2..0ba85ee4a466 100644
--- a/arch/alpha/mm/init.c
+++ b/arch/alpha/mm/init.c
@@ -31,6 +31,7 @@
 #include <asm/console.h>
 #include <asm/tlb.h>
 #include <asm/setup.h>
+#include <asm/sections.h>
 
 extern void die_if_kernel(char *,struct pt_regs *,long);
 
@@ -281,8 +282,6 @@ printk_memory_info(void)
 {
         unsigned long codesize, reservedpages, datasize, initsize, tmp;
         extern int page_is_ram(unsigned long) __init;
-        extern char _text, _etext, _data, _edata;
-        extern char __init_begin, __init_end;
 
         /* printk all informations */
         reservedpages = 0;
@@ -318,32 +317,15 @@ mem_init(void)
 #endif /* CONFIG_DISCONTIGMEM */
 
 void
-free_reserved_mem(void *start, void *end)
-{
-        void *__start = start;
-        for (; __start < end; __start += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(__start));
-                init_page_count(virt_to_page(__start));
-                free_page((long)__start);
-                totalram_pages++;
-        }
-}
-
-void
 free_initmem(void)
 {
-        extern char __init_begin, __init_end;
-
-        free_reserved_mem(&__init_begin, &__init_end);
-        printk ("Freeing unused kernel memory: %ldk freed\n",
-                (&__init_end - &__init_begin) >> 10);
+        free_initmem_default(0);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
 void
 free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_reserved_mem((void *)start, (void *)end);
-        printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
+        free_reserved_area(start, end, 0, "initrd");
 }
 #endif
diff --git a/arch/alpha/mm/numa.c b/arch/alpha/mm/numa.c
index 3973ae395772..33885048fa36 100644
--- a/arch/alpha/mm/numa.c
+++ b/arch/alpha/mm/numa.c
@@ -17,6 +17,7 @@
 
 #include <asm/hwrpb.h>
 #include <asm/pgalloc.h>
+#include <asm/sections.h>
 
 pg_data_t node_data[MAX_NUMNODES];
 EXPORT_SYMBOL(node_data);
@@ -325,8 +326,6 @@ void __init mem_init(void)
 {
         unsigned long codesize, reservedpages, datasize, initsize, pfn;
         extern int page_is_ram(unsigned long) __init;
-        extern char _text, _etext, _data, _edata;
-        extern char __init_begin, __init_end;
         unsigned long nid, i;
         high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
 
diff --git a/arch/arc/kernel/disasm.c b/arch/arc/kernel/disasm.c
index 2f390289a792..d14764ae2c60 100644
--- a/arch/arc/kernel/disasm.c
+++ b/arch/arc/kernel/disasm.c
@@ -535,4 +535,4 @@ int __kprobes disasm_next_pc(unsigned long pc, struct pt_regs *regs,
         return instr.is_branch;
 }
 
-#endif /* CONFIG_KGDB || CONFIG_MISALIGN_ACCESS || CONFIG_KPROBES */
+#endif /* CONFIG_KGDB || CONFIG_ARC_MISALIGN_ACCESS || CONFIG_KPROBES */
diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c
index 0a7531d99294..cad66851e0c4 100644
--- a/arch/arc/kernel/process.c
+++ b/arch/arc/kernel/process.c
@@ -41,37 +41,12 @@ SYSCALL_DEFINE0(arc_gettls)
         return task_thread_info(current)->thr_ptr;
 }
 
-static inline void arch_idle(void)
+void arch_cpu_idle(void)
 {
         /* sleep, but enable all interrupts before committing */
         __asm__("sleep 0x3");
 }
 
-void cpu_idle(void)
-{
-        /* Since we SLEEP in idle loop, TIF_POLLING_NRFLAG can't be set */
-
-        /* endless idle loop with no priority at all */
-        while (1) {
-                tick_nohz_idle_enter();
-                rcu_idle_enter();
-
-doze:
-                local_irq_disable();
-                if (!need_resched()) {
-                        arch_idle();
-                        goto doze;
-                } else {
-                        local_irq_enable();
-                }
-
-                rcu_idle_exit();
-                tick_nohz_idle_exit();
-
-                schedule_preempt_disabled();
-        }
-}
-
 asmlinkage void ret_from_fork(void);
 
 /* Layout of Child kernel mode stack as setup at the end of this function is
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index 3af3e06dcf02..5c7fd603d216 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -141,7 +141,7 @@ void __cpuinit start_kernel_secondary(void)
 
         local_irq_enable();
         preempt_disable();
-        cpu_idle();
+        cpu_startup_entry(CPUHP_ONLINE);
 }
 
 /*
diff --git a/arch/arc/kernel/stacktrace.c b/arch/arc/kernel/stacktrace.c
index a63ff842564b..ca0207b9d5b6 100644
--- a/arch/arc/kernel/stacktrace.c
+++ b/arch/arc/kernel/stacktrace.c
@@ -220,13 +220,6 @@ void show_stack(struct task_struct *tsk, unsigned long *sp)
         show_stacktrace(tsk, NULL);
 }
 
-/* Expected by Rest of kernel code */
-void dump_stack(void)
-{
-        show_stacktrace(NULL, NULL);
-}
-EXPORT_SYMBOL(dump_stack);
-
 /* Another API expected by schedular, shows up in "ps" as Wait Channel
  * Ofcourse just returning schedule( ) would be pointless so unwind until
  * the function is not in schedular code
diff --git a/arch/arc/kernel/troubleshoot.c b/arch/arc/kernel/troubleshoot.c
index 7c10873c311f..0aec01985bf9 100644
--- a/arch/arc/kernel/troubleshoot.c
+++ b/arch/arc/kernel/troubleshoot.c
@@ -71,7 +71,7 @@ void print_task_path_n_nm(struct task_struct *tsk, char *buf)
         }
 
 done:
-        pr_info("%s, TGID %u\n", path_nm, tsk->tgid);
+        pr_info("Path: %s\n", path_nm);
 }
 EXPORT_SYMBOL(print_task_path_n_nm);
 
@@ -163,6 +163,7 @@ void show_regs(struct pt_regs *regs)
                 return;
 
         print_task_path_n_nm(tsk, buf);
+        show_regs_print_info(KERN_INFO);
 
         if (current->thread.cause_code)
                 show_ecr_verbose(regs);
diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c
index caf797de23fc..727d4794ea0f 100644
--- a/arch/arc/mm/init.c
+++ b/arch/arc/mm/init.c
@@ -144,37 +144,18 @@ void __init mem_init(void)
                 PAGES_TO_KB(reserved_pages));
 }
 
-static void __init free_init_pages(const char *what, unsigned long begin,
-                                   unsigned long end)
-{
-        unsigned long addr;
-
-        pr_info("Freeing %s: %ldk [%lx] to [%lx]\n",
-                what, TO_KB(end - begin), begin, end);
-
-        /* need to check that the page we free is not a partial page */
-        for (addr = begin; addr + PAGE_SIZE <= end; addr += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(addr));
-                init_page_count(virt_to_page(addr));
-                free_page(addr);
-                totalram_pages++;
-        }
-}
-
 /*
  * free_initmem: Free all the __init memory.
  */
 void __init_refok free_initmem(void)
 {
-        free_init_pages("unused kernel memory",
-                        (unsigned long)__init_begin,
-                        (unsigned long)__init_end);
+        free_initmem_default(0);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_init_pages("initrd memory", start, end);
+        free_reserved_area(start, end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/arc/plat-arcfpga/Kconfig b/arch/arc/plat-arcfpga/Kconfig
index b41e786cdbc0..295cefeb25d3 100644
--- a/arch/arc/plat-arcfpga/Kconfig
+++ b/arch/arc/plat-arcfpga/Kconfig
@@ -53,7 +53,7 @@ menuconfig ARC_HAS_BVCI_LAT_UNIT
         bool "BVCI Bus Latency Unit"
         depends on ARC_BOARD_ML509 || ARC_BOARD_ANGEL4
         help
-          IP to add artifical latency to BVCI Bus Based FPGA builds.
+          IP to add artificial latency to BVCI Bus Based FPGA builds.
           The default latency (even worst case) for FPGA is non-realistic
           (~10 SDRAM, ~5 SSRAM).
 
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1cacda426a0e..1e31dac36a5f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -15,6 +15,7 @@ config ARM
         select GENERIC_IRQ_SHOW
         select GENERIC_PCI_IOMAP
         select GENERIC_SMP_IDLE_THREAD
+        select GENERIC_IDLE_POLL_SETUP
         select GENERIC_STRNCPY_FROM_USER
         select GENERIC_STRNLEN_USER
         select HARDIRQS_SW_RESEND
@@ -58,6 +59,7 @@ config ARM
         select CLONE_BACKWARDS
         select OLD_SIGSUSPEND3
         select OLD_SIGACTION
+        select HAVE_CONTEXT_TRACKING
         help
           The ARM series is a line of low-power-consumption RISC chip designs
           licensed by ARM Ltd and targeted at embedded applications and
@@ -361,37 +363,6 @@ config ARCH_AT91
           This enables support for systems based on Atmel
           AT91RM9200 and AT91SAM9* processors.
 
-config ARCH_BCM2835
-        bool "Broadcom BCM2835 family"
-        select ARCH_REQUIRE_GPIOLIB
-        select ARM_AMBA
-        select ARM_ERRATA_411920
-        select ARM_TIMER_SP804
-        select CLKDEV_LOOKUP
-        select CLKSRC_OF
-        select COMMON_CLK
-        select CPU_V6
-        select GENERIC_CLOCKEVENTS
-        select MULTI_IRQ_HANDLER
-        select PINCTRL
-        select PINCTRL_BCM2835
-        select SPARSE_IRQ
-        select USE_OF
-        help
-          This enables support for the Broadcom BCM2835 SoC. This SoC is
-          use in the Raspberry Pi, and Roku 2 devices.
-
-config ARCH_CNS3XXX
-        bool "Cavium Networks CNS3XXX family"
-        select ARM_GIC
-        select CPU_V6K
-        select GENERIC_CLOCKEVENTS
-        select MIGHT_HAVE_CACHE_L2X0
-        select MIGHT_HAVE_PCI
-        select PCI_DOMAINS if PCI
-        help
-          Support for Cavium Networks CNS3XXX platform.
-
 config ARCH_CLPS711X
         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
         select ARCH_REQUIRE_GPIOLIB
@@ -410,25 +381,11 @@ config ARCH_GEMINI
         bool "Cortina Systems Gemini"
         select ARCH_REQUIRE_GPIOLIB
         select ARCH_USES_GETTIMEOFFSET
+        select NEED_MACH_GPIO_H
         select CPU_FA526
         help
           Support for the Cortina Systems Gemini family SoCs
 
-config ARCH_SIRF
-        bool "CSR SiRF"
-        select ARCH_REQUIRE_GPIOLIB
-        select AUTO_ZRELADDR
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
-        select GENERIC_IRQ_CHIP
-        select MIGHT_HAVE_CACHE_L2X0
-        select NO_IOPORT
-        select PINCTRL
-        select PINCTRL_SIRF
-        select USE_OF
-        help
-          Support for CSR SiRFprimaII/Marco/Polo platforms
-
 config ARCH_EBSA110
         bool "EBSA-110"
         select ARCH_USES_GETTIMEOFFSET
@@ -468,21 +425,6 @@ config ARCH_FOOTBRIDGE
           Support for systems based on the DC21285 companion chip
           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 
-config ARCH_MXS
-        bool "Freescale MXS-based"
-        select ARCH_REQUIRE_GPIOLIB
-        select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
-        select HAVE_CLK_PREPARE
-        select MULTI_IRQ_HANDLER
-        select PINCTRL
-        select SPARSE_IRQ
-        select USE_OF
-        help
-          Support for Freescale MXS-based family of processors
-
 config ARCH_NETX
         bool "Hilscher NetX based"
         select ARM_VIC
@@ -492,14 +434,6 @@ config ARCH_NETX
         help
           This enables support for systems based on the Hilscher NetX Soc
 
-config ARCH_H720X
-        bool "Hynix HMS720x-based"
-        select ARCH_USES_GETTIMEOFFSET
-        select CPU_ARM720T
-        select ISA_DMA_API
-        help
-          This enables support for systems based on the Hynix HMS720x
-
 config ARCH_IOP13XX
         bool "IOP13xx-based"
         depends on MMU
@@ -549,6 +483,8 @@ config ARCH_IXP4XX
         select GENERIC_CLOCKEVENTS
         select MIGHT_HAVE_PCI
         select NEED_MACH_IO_H
+        select USB_EHCI_BIG_ENDIAN_MMIO
+        select USB_EHCI_BIG_ENDIAN_DESC
         help
           Support for Intel's IXP4XX (XScale) family of processors.
 
@@ -661,24 +597,6 @@ config ARCH_LPC32XX
         help
           Support for the NXP LPC32XX family of processors
 
-config ARCH_TEGRA
-        bool "NVIDIA Tegra"
-        select ARCH_HAS_CPUFREQ
-        select ARCH_REQUIRE_GPIOLIB
-        select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
-        select CLKSRC_OF
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
-        select HAVE_CLK
-        select HAVE_SMP
-        select MIGHT_HAVE_CACHE_L2X0
-        select SPARSE_IRQ
-        select USE_OF
-        help
-          This enables support for NVIDIA Tegra based systems (Tegra APX,
-          Tegra 6xx and Tegra 2 series).
-
 config ARCH_PXA
         bool "PXA2xx/PXA3xx-based"
         depends on MMU
@@ -716,6 +634,8 @@ config ARCH_SHMOBILE
         bool "Renesas SH-Mobile / R-Mobile"
         select CLKDEV_LOOKUP
         select GENERIC_CLOCKEVENTS
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
         select HAVE_CLK
         select HAVE_MACH_CLKDEV
         select HAVE_SMP
@@ -769,12 +689,15 @@ config ARCH_SA1100
 config ARCH_S3C24XX
         bool "Samsung S3C24XX SoCs"
         select ARCH_HAS_CPUFREQ
-        select ARCH_USES_GETTIMEOFFSET
+        select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
+        select GENERIC_CLOCKEVENTS
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
         select HAVE_S3C_RTC if RTC_CLASS
+        select MULTI_IRQ_HANDLER
         select NEED_MACH_GPIO_H
         select NEED_MACH_IO_H
         help
@@ -787,10 +710,11 @@ config ARCH_S3C64XX
         bool "Samsung S3C64XX"
         select ARCH_HAS_CPUFREQ
         select ARCH_REQUIRE_GPIOLIB
-        select ARCH_USES_GETTIMEOFFSET
         select ARM_VIC
         select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
         select CPU_V6
+        select GENERIC_CLOCKEVENTS
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -824,9 +748,11 @@ config ARCH_S5P64X0
 
 config ARCH_S5PC100
         bool "Samsung S5PC100"
-        select ARCH_USES_GETTIMEOFFSET
+        select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
         select CPU_V7
+        select GENERIC_CLOCKEVENTS
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -859,6 +785,7 @@ config ARCH_EXYNOS
         select ARCH_HAS_HOLES_MEMORYMODEL
         select ARCH_SPARSEMEM_ENABLE
         select CLKDEV_LOOKUP
+        select COMMON_CLK
         select CPU_V7
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK
@@ -901,51 +828,6 @@ config ARCH_U300
         help
           Support for ST-Ericsson U300 series mobile platforms.
 
-config ARCH_U8500
-        bool "ST-Ericsson U8500 Series"
-        depends on MMU
-        select ARCH_HAS_CPUFREQ
-        select ARCH_REQUIRE_GPIOLIB
-        select ARM_AMBA
-        select CLKDEV_LOOKUP
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
-        select HAVE_SMP
-        select MIGHT_HAVE_CACHE_L2X0
-        select SPARSE_IRQ
-        help
-          Support for ST-Ericsson's Ux500 architecture
-
-config ARCH_NOMADIK
-        bool "STMicroelectronics Nomadik"
-        select ARCH_REQUIRE_GPIOLIB
-        select ARM_AMBA
-        select ARM_VIC
-        select CLKSRC_NOMADIK_MTU
-        select COMMON_CLK
-        select CPU_ARM926T
-        select GENERIC_CLOCKEVENTS
-        select MIGHT_HAVE_CACHE_L2X0
-        select USE_OF
-        select PINCTRL
-        select PINCTRL_STN8815
-        select SPARSE_IRQ
-        help
-          Support for the Nomadik platform by ST-Ericsson
-
-config PLAT_SPEAR
-        bool "ST SPEAr"
-        select ARCH_HAS_CPUFREQ
-        select ARCH_REQUIRE_GPIOLIB
-        select ARM_AMBA
-        select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
-        select HAVE_CLK
-        help
-          Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
-
 config ARCH_DAVINCI
         bool "TI DaVinci"
         select ARCH_HAS_HOLES_MEMORYMODEL
@@ -1037,6 +919,8 @@ source "arch/arm/mach-at91/Kconfig"
 
 source "arch/arm/mach-bcm/Kconfig"
 
+source "arch/arm/mach-bcm2835/Kconfig"
+
 source "arch/arm/mach-clps711x/Kconfig"
 
 source "arch/arm/mach-cns3xxx/Kconfig"
@@ -1051,8 +935,6 @@ source "arch/arm/mach-footbridge/Kconfig"
 
 source "arch/arm/mach-gemini/Kconfig"
 
-source "arch/arm/mach-h720x/Kconfig"
-
 source "arch/arm/mach-highbank/Kconfig"
 
 source "arch/arm/mach-integrator/Kconfig"
@@ -1104,7 +986,7 @@ source "arch/arm/plat-samsung/Kconfig"
 
 source "arch/arm/mach-socfpga/Kconfig"
 
-source "arch/arm/plat-spear/Kconfig"
+source "arch/arm/mach-spear/Kconfig"
 
 source "arch/arm/mach-s3c24xx/Kconfig"
 
@@ -1173,7 +1055,6 @@ config PLAT_VERSATILE
 config ARM_TIMER_SP804
         bool
         select CLKSRC_MMIO
-        select HAVE_SCHED_CLOCK
 
 source arch/arm/mm/Kconfig
 
@@ -1532,7 +1413,6 @@ config SMP
         depends on GENERIC_CLOCKEVENTS
         depends on HAVE_SMP
         depends on MMU
-        select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
         select USE_GENERIC_SMP_HELPERS
         help
           This enables support for systems with more than one CPU. If you have
@@ -1603,9 +1483,18 @@ config HAVE_ARM_ARCH_TIMER
 config HAVE_ARM_TWD
         bool
         depends on SMP
+        select CLKSRC_OF if OF
         help
           This options enables support for the ARM timer and watchdog unit
 
+config MCPM
+        bool "Multi-Cluster Power Management"
+        depends on CPU_V7 && SMP
+        help
+          This option provides the common power management infrastructure
+          for (multi-)cluster based systems, such as big.LITTLE based
+          systems.
+
 choice
         prompt "Memory split"
         default VMSPLIT_3G
@@ -1656,7 +1545,6 @@ config LOCAL_TIMERS
         bool "Use local timer interrupts"
         depends on SMP
         default y
-        select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
         help
           Enable support for local timers on SMP platforms, rather then the
           legacy IPI broadcast method.  Local timers allows the system
@@ -1670,8 +1558,9 @@ config ARCH_NR_GPIO
         int
         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
         default 512 if SOC_OMAP5
-        default 355 if ARCH_U8500
-        default 288 if ARCH_VT8500 || ARCH_SUNXI
+        default 392 if ARCH_U8500
+        default 352 if ARCH_VT8500
+        default 288 if ARCH_SUNXI
         default 264 if MACH_H4700
         default 0
         help
@@ -1693,8 +1582,9 @@ config SCHED_HRTICK
         def_bool HIGH_RES_TIMERS
 
 config THUMB2_KERNEL
-        bool "Compile the kernel in Thumb-2 mode"
+        bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
         depends on CPU_V7 && !CPU_V6 && !CPU_V6K
+        default y if CPU_THUMBONLY
         select AEABI
         select ARM_ASM_UNIFIED
         select ARM_UNWIND
@@ -2160,40 +2050,8 @@ endmenu
 menu "CPU Power Management"
 
 if ARCH_HAS_CPUFREQ
-
 source "drivers/cpufreq/Kconfig"
 
-config CPU_FREQ_IMX
-        tristate "CPUfreq driver for i.MX CPUs"
-        depends on ARCH_MXC && CPU_FREQ
-        select CPU_FREQ_TABLE
-        help
-          This enables the CPUfreq driver for i.MX CPUs.
-
-config CPU_FREQ_SA1100
-        bool
-
-config CPU_FREQ_SA1110
-        bool
-
-config CPU_FREQ_INTEGRATOR
-        tristate "CPUfreq driver for ARM Integrator CPUs"
-        depends on ARCH_INTEGRATOR && CPU_FREQ
-        default y
-        help
-          This enables the CPUfreq driver for ARM Integrator CPUs.
-
-          For details, take a look at <file:Documentation/cpu-freq>.
-
-          If in doubt, say Y.
-
-config CPU_FREQ_PXA
-        bool
-        depends on CPU_FREQ && ARCH_PXA && PXA25x
-        default y
-        select CPU_FREQ_DEFAULT_GOV_USERSPACE
-        select CPU_FREQ_TABLE
-
 config CPU_FREQ_S3C
         bool
         help
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 9b31f4311ea2..f57a6ba26e04 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -89,6 +89,10 @@ choice
                 bool "Kernel low-level debugging on 9263 and 9g45"
                 depends on HAVE_AT91_DBGU1
 
+        config DEBUG_BCM2835
+                bool "Kernel low-level debugging on BCM2835 PL011 UART"
+                depends on ARCH_BCM2835
+
         config DEBUG_CLPS711X_UART1
                 bool "Kernel low-level debugging messages via UART1"
                 depends on ARCH_CLPS711X
@@ -103,6 +107,13 @@ choice
                   Say Y here if you want the debug print routines to direct
                   their output to the second serial port on these devices.
 
+        config DEBUG_CNS3XXX
+                bool "Kernel Kernel low-level debugging on Cavium Networks CNS3xxx"
+                depends on ARCH_CNS3XXX
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the CNS3xxx UART0.
+
         config DEBUG_DAVINCI_DA8XX_UART1
                 bool "Kernel low-level debugging on DaVinci DA8XX using UART1"
                 depends on ARCH_DAVINCI_DA8XX
@@ -298,6 +309,13 @@ choice
                   Say Y here if you want kernel low-level debugging support
                   on MVEBU based platforms.
 
+        config DEBUG_NOMADIK_UART
+                bool "Kernel low-level debugging messages via NOMADIK UART"
+                depends on ARCH_NOMADIK
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on NOMADIK based platforms.
+
         config DEBUG_OMAP2PLUS_UART
                 bool "Kernel low-level debugging messages via OMAP2PLUS UART"
                 depends on ARCH_OMAP2PLUS
@@ -312,6 +330,13 @@ choice
                   Say Y here if you want kernel low-level debugging support
                   on PicoXcell based platforms.
 
+        config DEBUG_PXA_UART1
+                depends on ARCH_PXA
+                bool "Use PXA UART1 for low-level debug"
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on PXA UART1.
+
         config DEBUG_REALVIEW_STD_PORT
                 bool "RealView Default UART"
                 depends on ARCH_REALVIEW
@@ -330,6 +355,7 @@ choice
 
         config DEBUG_S3C_UART0
                 depends on PLAT_SAMSUNG
+                select DEBUG_EXYNOS_UART if ARCH_EXYNOS
                 bool "Use S3C UART 0 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
@@ -341,6 +367,7 @@ choice
 
         config DEBUG_S3C_UART1
                 depends on PLAT_SAMSUNG
+                select DEBUG_EXYNOS_UART if ARCH_EXYNOS
                 bool "Use S3C UART 1 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
@@ -352,6 +379,7 @@ choice
 
         config DEBUG_S3C_UART2
                 depends on PLAT_SAMSUNG
+                select DEBUG_EXYNOS_UART if ARCH_EXYNOS
                 bool "Use S3C UART 2 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
@@ -363,6 +391,7 @@ choice
 
         config DEBUG_S3C_UART3
                 depends on PLAT_SAMSUNG && ARCH_EXYNOS
+                select DEBUG_EXYNOS_UART
                 bool "Use S3C UART 3 for low-level debug"
                 help
                   Say Y here if you want the debug print routines to direct
@@ -414,6 +443,13 @@ choice
                   Say Y here if you want the debug print routines to direct
                   their output to the uart1 port on SiRFmarco devices.
 
+        config DEBUG_UX500_UART
+                depends on ARCH_U8500
+                bool "Use Ux500 UART for low-level debug"
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on Ux500 based platforms.
+
         config DEBUG_VEXPRESS_UART0_DETECT
                 bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
                 depends on ARCH_VEXPRESS && CPU_CP15_MMU
@@ -485,6 +521,9 @@ choice
 
 endchoice
 
+config DEBUG_EXYNOS_UART
+        bool
+
 config DEBUG_IMX_UART_PORT
         int "i.MX Debug UART Port Selection" if DEBUG_IMX1_UART || \
                                                 DEBUG_IMX25_UART || \
@@ -580,6 +619,10 @@ endchoice
 
 config DEBUG_LL_INCLUDE
         string
+        default "debug/bcm2835.S" if DEBUG_BCM2835
+        default "debug/cns3xxx.S" if DEBUG_CNS3XXX
+        default "debug/exynos.S" if DEBUG_EXYNOS_UART
+        default "debug/highbank.S" if DEBUG_HIGHBANK_UART
         default "debug/icedcc.S" if DEBUG_ICEDCC
         default "debug/imx.S" if DEBUG_IMX1_UART || \
                                  DEBUG_IMX25_UART || \
@@ -589,19 +632,35 @@ config DEBUG_LL_INCLUDE
                                  DEBUG_IMX51_UART || \
                                  DEBUG_IMX53_UART ||\
                                  DEBUG_IMX6Q_UART
-        default "debug/highbank.S" if DEBUG_HIGHBANK_UART
         default "debug/mvebu.S" if DEBUG_MVEBU_UART
+        default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART
+        default "debug/nomadik.S" if DEBUG_NOMADIK_UART
         default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
         default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
+        default "debug/pxa.S" if DEBUG_PXA_UART1 || DEBUG_MMP_UART2 || \
+                                 DEBUG_MMP_UART3
+        default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
         default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
         default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
+        default "debug/tegra.S" if DEBUG_TEGRA_UART
+        default "debug/ux500.S" if DEBUG_UX500_UART
         default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
                 DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
         default "debug/vt8500.S" if DEBUG_VT8500_UART0
-        default "debug/tegra.S" if DEBUG_TEGRA_UART
         default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
         default "mach/debug-macro.S"
 
+config DEBUG_UNCOMPRESS
+        bool
+        default y if ARCH_MULTIPLATFORM && DEBUG_LL && \
+                     !DEBUG_OMAP2PLUS_UART && \
+                     !DEBUG_TEGRA_UART
+
+config UNCOMPRESS_INCLUDE
+        string
+        default "debug/uncompress.h" if ARCH_MULTIPLATFORM
+        default "mach/uncompress.h"
+
 config EARLY_PRINTK
         bool "Early printk"
         depends on DEBUG_LL
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ee4605f400b0..47374085befd 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -147,7 +147,6 @@ machine-$(CONFIG_ARCH_DOVE)		+= dove
 machine-$(CONFIG_ARCH_EBSA110)          += ebsa110
 machine-$(CONFIG_ARCH_EP93XX)           += ep93xx
 machine-$(CONFIG_ARCH_GEMINI)           += gemini
-machine-$(CONFIG_ARCH_H720X)            += h720x
 machine-$(CONFIG_ARCH_HIGHBANK)         += highbank
 machine-$(CONFIG_ARCH_INTEGRATOR)       += integrator
 machine-$(CONFIG_ARCH_IOP13XX)          += iop13xx
@@ -191,9 +190,7 @@ machine-$(CONFIG_ARCH_VT8500)		+= vt8500
 machine-$(CONFIG_ARCH_W90X900)          += w90x900
 machine-$(CONFIG_FOOTBRIDGE)            += footbridge
 machine-$(CONFIG_ARCH_SOCFPGA)          += socfpga
-machine-$(CONFIG_ARCH_SPEAR13XX)        += spear13xx
-machine-$(CONFIG_ARCH_SPEAR3XX)         += spear3xx
-machine-$(CONFIG_MACH_SPEAR600)         += spear6xx
+machine-$(CONFIG_PLAT_SPEAR)            += spear
 machine-$(CONFIG_ARCH_VIRT)             += virt
 machine-$(CONFIG_ARCH_ZYNQ)             += zynq
 machine-$(CONFIG_ARCH_SUNXI)            += sunxi
@@ -207,7 +204,6 @@ plat-$(CONFIG_PLAT_ORION)	+= orion
 plat-$(CONFIG_PLAT_PXA)         += pxa
 plat-$(CONFIG_PLAT_S3C24XX)     += samsung
 plat-$(CONFIG_PLAT_S5P)         += samsung
-plat-$(CONFIG_PLAT_SPEAR)       += spear
 plat-$(CONFIG_PLAT_VERSATILE)   += versatile
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index afed28e37ea5..3580d57ea218 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -24,6 +24,9 @@ endif
 AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
 HEAD    = head.o
 OBJS    += misc.o decompress.o
+ifeq ($(CONFIG_DEBUG_UNCOMPRESS),y)
+OBJS    += debug.o
+endif
 FONTC   = $(srctree)/drivers/video/console/font_acorn_8x8.c
 
 # string library code (-Os is enforced to keep it much smaller)
diff --git a/arch/arm/boot/compressed/debug.S b/arch/arm/boot/compressed/debug.S
new file mode 100644
index 000000000000..6e8382d5b7a4
--- /dev/null
+++ b/arch/arm/boot/compressed/debug.S
@@ -0,0 +1,12 @@
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+#include CONFIG_DEBUG_LL_INCLUDE
+
+ENTRY(putc)
+        addruart r1, r2, r3
+        waituart r3, r1
+        senduart r0, r1
+        busyuart r3, r1
+        mov      pc, lr
+ENDPROC(putc)
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index df899834d84e..31bd43b82095 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -25,13 +25,7 @@ unsigned int __machine_arch_type;
 static void putstr(const char *ptr);
 extern void error(char *x);
 
-#ifdef CONFIG_ARCH_MULTIPLATFORM
-static inline void putc(int c) {}
-static inline void flush(void) {}
-static inline void arch_decomp_setup(void) {}
-#else
-#include <mach/uncompress.h>
-#endif
+#include CONFIG_UNCOMPRESS_INCLUDE
 
 #ifdef CONFIG_DEBUG_ICEDCC
 
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9c6255884cbb..853e199ea89f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -3,6 +3,7 @@ ifeq ($(CONFIG_OF),y)
 # Keep at91 dtb files sorted alphabetically for each SoC
 # rm9200
 dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += mpa1600.dtb
 # sam9260
 dtb-$(CONFIG_ARCH_AT91) += animeo_ip.dtb
 dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb
@@ -26,11 +27,17 @@ dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
 # sam9n12
 dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
 # sam9x5
+dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
+# sama5d3
+dtb-$(CONFIG_ARCH_AT91) += sama5d31ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
 
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb
@@ -42,7 +49,10 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
 dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
         exynos4210-smdkv310.dtb \
         exynos4210-trats.dtb \
+        exynos4412-odroidx.dtb \
         exynos4412-smdk4412.dtb \
+        exynos4412-origen.dtb \
+        exynos5250-arndale.dtb \
         exynos5250-smdk5250.dtb \
         exynos5250-snow.dtb \
         exynos5440-ssdk5440.dtb
@@ -51,7 +61,8 @@ dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
 dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
         integratorcp.dtb
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
-dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
+dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
+        kirkwood-dns320.dtb \
         kirkwood-dns325.dtb \
         kirkwood-dockstar.dtb \
         kirkwood-dreamplug.dtb \
@@ -65,6 +76,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
         kirkwood-lschlv2.dtb \
         kirkwood-lsxhl.dtb \
         kirkwood-mplcec4.dtb \
+        kirkwood-netgear_readynas_duo_v2.dtb \
         kirkwood-ns2.dtb \
         kirkwood-ns2lite.dtb \
         kirkwood-ns2max.dtb \
@@ -87,19 +99,26 @@ dtb-$(CONFIG_ARCH_MXC) += \
         imx25-karo-tx25.dtb \
         imx25-pdk.dtb \
         imx27-apf27.dtb \
+        imx27-apf27dev.dtb \
         imx27-pdk.dtb \
+        imx27-phytec-phycore.dtb \
         imx31-bug.dtb \
         imx51-apf51.dtb \
+        imx51-apf51dev.dtb \
         imx51-babbage.dtb \
         imx53-ard.dtb \
         imx53-evk.dtb \
         imx53-mba53.dtb \
         imx53-qsb.dtb \
         imx53-smd.dtb \
+        imx6dl-sabreauto.dtb \
+        imx6dl-sabresd.dtb \
+        imx6dl-wandboard.dtb \
         imx6q-arm2.dtb \
         imx6q-sabreauto.dtb \
         imx6q-sabrelite.dtb \
-        imx6q-sabresd.dtb
+        imx6q-sabresd.dtb \
+        imx6q-sbc6x.dtb
 dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
         imx23-olinuxino.dtb \
         imx23-stmp378x_devb.dtb \
@@ -136,7 +155,9 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
         ccu9540.dtb
 dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
         r8a7740-armadillo800eva.dtb \
+        r8a7779-marzen-reference.dtb \
         sh73a0-kzm9g.dtb \
+        sh73a0-kzm9g-reference.dtb \
         sh7372-mackerel.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
         socfpga_vt.dtb
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index e34b280ce6ec..6403acdbb75f 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -94,5 +94,22 @@
                                 spi-max-frequency = <50000000>;
                         };
                 };
+
+                pcie-controller {
+                        status = "okay";
+                        /*
+                         * The two PCIe units are accessible through
+                         * both standard PCIe slots and mini-PCIe
+                         * slots on the board.
+                         */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@2,0 {
+                                /* Port 1, Lane 0 */
+                                status = "okay";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 3234875824dc..58ee79372206 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -33,6 +33,43 @@
                         clock-frequency = <600000000>;
                         status = "okay";
                 };
+
+                pinctrl {
+                        pwr_led_pin: pwr-led-pin {
+                                marvell,pins = "mpp63";
+                                marvell,function = "gpo";
+                        };
+
+                        stat_led_pins: stat-led-pins {
+                                marvell,pins = "mpp64", "mpp65";
+                                marvell,function = "gpio";
+                        };
+                };
+
+                gpio_leds {
+                        compatible = "gpio-leds";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pwr_led_pin &stat_led_pins>;
+
+                        green_pwr_led {
+                                label = "mirabox:green:pwr";
+                                gpios = <&gpio1 31 1>;
+                                linux,default-trigger = "heartbeat";
+                        };
+
+                        blue_stat_led {
+                                label = "mirabox:blue:stat";
+                                gpios = <&gpio2 0 1>;
+                                linux,default-trigger = "cpu0";
+                        };
+
+                        green_stat_led {
+                                label = "mirabox:green:stat";
+                                gpios = <&gpio2 1 1>;
+                                default-state = "off";
+                        };
+                };
+
                 mdio {
                         phy0: ethernet-phy@0 {
                                 reg = <0>;
@@ -70,5 +107,32 @@
                 usb@d0051000 {
                         status = "okay";
                 };
+
+                i2c@d0011000 {
+                        status = "okay";
+                        clock-frequency = <100000>;
+                        pca9505: pca9505@25 {
+                                compatible = "nxp,pca9505";
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                reg = <0x25>;
+                        };
+                };
+
+                pcie-controller {
+                        status = "okay";
+
+                        /* Internal mini-PCIe connector */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+
+                        /* Connected on the PCB to a USB 3.0 XHCI controller */
+                        pcie@2,0 {
+                                /* Port 1, Lane 0 */
+                                status = "okay";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 070bba4f2585..516dec31b469 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -73,4 +73,15 @@
                         status = "okay";
                 };
         };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button@1 {
+                        label = "Software Button";
+                        linux,code = <116>;
+                        gpios = <&gpio0 6 1>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 5b708208b607..758c4ea90344 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -181,6 +181,51 @@
                         clocks = <&coreclk 0>;
                         status = "disabled";
                 };
+
+                devbus-bootcs@d0010400 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <0xd0010400 0x8>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+
+                devbus-cs0@d0010408 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <0xd0010408 0x8>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+
+                devbus-cs1@d0010410 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <0xd0010410 0x8>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+
+                devbus-cs2@d0010418 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <0xd0010418 0x8>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+
+                devbus-cs3@d0010420 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <0xd0010420 0x8>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index a195debb67d3..18f6eb47cc50 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -159,5 +159,63 @@
                         clocks = <&coreclk 0>;
                 };
 
+                thermal@d0018300 {
+                        compatible = "marvell,armada370-thermal";
+                        reg = <0xd0018300 0x4
+                               0xd0018304 0x4>;
+                        status = "okay";
+                };
+
+                pcie-controller {
+                        compatible = "marvell,armada-370-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        reg = <0xd0040000 0x2000>, <0xd0080000 0x2000>;
+
+                        reg-names = "pcie0.0", "pcie1.0";
+
+                        ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
+                                  0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */
+                                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 58>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 62>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 9>;
+                                status = "disabled";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index e83505e4c236..54cc5bb705fb 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -121,5 +121,38 @@
                                 spi-max-frequency = <20000000>;
                         };
                 };
+
+                pcie-controller {
+                        status = "okay";
+
+                        /*
+                         * All 6 slots are physically present as
+                         * standard PCIe slots on the board.
+                         */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@2,0 {
+                                /* Port 0, Lane 1 */
+                                status = "okay";
+                        };
+                        pcie@3,0 {
+                                /* Port 0, Lane 2 */
+                                status = "okay";
+                        };
+                        pcie@4,0 {
+                                /* Port 0, Lane 3 */
+                                status = "okay";
+                        };
+                        pcie@9,0 {
+                                /* Port 2, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@10,0 {
+                                /* Port 3, Lane 0 */
+                                status = "okay";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 1c8afe2ffebc..04f28a712b98 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -109,5 +109,55 @@
                                 spi-max-frequency = <108000000>;
                         };
                 };
+
+                devbus-bootcs@d0010400 {
+                        status = "okay";
+                        ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
+
+                        /* Device Bus parameters are required */
+
+                        /* Read parameters */
+                        devbus,bus-width    = <8>;
+                        devbus,turn-off-ps  = <60000>;
+                        devbus,badr-skew-ps = <0>;
+                        devbus,acc-first-ps = <124000>;
+                        devbus,acc-next-ps  = <248000>;
+                        devbus,rd-setup-ps  = <0>;
+                        devbus,rd-hold-ps   = <0>;
+
+                        /* Write parameters */
+                        devbus,sync-enable = <0>;
+                        devbus,wr-high-ps  = <60000>;
+                        devbus,wr-low-ps   = <60000>;
+                        devbus,ale-wr-ps   = <60000>;
+
+                        /* NOR 16 MiB */
+                        nor@0 {
+                                compatible = "cfi-flash";
+                                reg = <0 0x1000000>;
+                                bank-width = <2>;
+                        };
+                };
+
+                pcie-controller {
+                        status = "okay";
+
+                        /*
+                         * The 3 slots are physically present as
+                         * standard PCIe slots on the board.
+                         */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@9,0 {
+                                /* Port 2, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@10,0 {
+                                /* Port 3, Lane 0 */
+                                status = "okay";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index f56c40599f5b..c2c78459a4d4 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -76,5 +76,109 @@
                         #interrupts-cells = <2>;
                         interrupts = <87>, <88>, <89>;
                 };
+
+                /*
+                 * MV78230 has 2 PCIe units Gen2.0: One unit can be
+                 * configured as x4 or quad x1 lanes. One unit is
+                 * x4/x1.
+                 */
+                pcie-controller {
+                        compatible = "marvell,armada-xp-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
+                                  0x82000000 0 0xd0042000 0xd0042000 0 0x00002000   /* Port 2.0 registers */
+                                  0x82000000 0 0xd0044000 0xd0044000 0 0x00002000   /* Port 0.1 registers */
+                                  0x82000000 0 0xd0048000 0xd0048000 0 0x00002000   /* Port 0.2 registers */
+                                  0x82000000 0 0xd004c000 0xd004c000 0 0x00002000   /* Port 0.3 registers */
+                                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 58>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 59>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <1>;
+                                clocks = <&gateclk 6>;
+                                status = "disabled";
+                        };
+
+                        pcie@3,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>;
+                                reg = <0x1800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 60>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <2>;
+                                clocks = <&gateclk 7>;
+                                status = "disabled";
+                        };
+
+                        pcie@4,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>;
+                                reg = <0x2000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 61>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <3>;
+                                clocks = <&gateclk 8>;
+                                status = "disabled";
+                        };
+
+                        pcie@9,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>;
+                                reg = <0x4800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 99>;
+                                marvell,pcie-port = <2>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 26>;
+                                status = "disabled";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index f8f2b787d2b0..885bf229eef7 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -96,5 +96,127 @@
                                 clocks = <&gateclk 1>;
                                 status = "disabled";
                 };
+
+                /*
+                 * MV78260 has 3 PCIe units Gen2.0: Two units can be
+                 * configured as x4 or quad x1 lanes. One unit is
+                 * x4/x1.
+                 */
+                pcie-controller {
+                        compatible = "marvell,armada-xp-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
+                                  0x82000000 0 0xd0042000 0xd0042000 0 0x00002000   /* Port 2.0 registers */
+                                  0x82000000 0 0xd0044000 0xd0044000 0 0x00002000   /* Port 0.1 registers */
+                                  0x82000000 0 0xd0048000 0xd0048000 0 0x00002000   /* Port 0.2 registers */
+                                  0x82000000 0 0xd004c000 0xd004c000 0 0x00002000   /* Port 0.3 registers */
+                                  0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */
+                                  0x82000000 0 0xd0082000 0xd0082000 0 0x00002000   /* Port 3.0 registers */
+                                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 58>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 59>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <1>;
+                                clocks = <&gateclk 6>;
+                                status = "disabled";
+                        };
+
+                        pcie@3,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>;
+                                reg = <0x1800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 60>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <2>;
+                                clocks = <&gateclk 7>;
+                                status = "disabled";
+                        };
+
+                        pcie@4,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>;
+                                reg = <0x2000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 61>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <3>;
+                                clocks = <&gateclk 8>;
+                                status = "disabled";
+                        };
+
+                        pcie@9,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>;
+                                reg = <0x4800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 99>;
+                                marvell,pcie-port = <2>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 26>;
+                                status = "disabled";
+                        };
+
+                        pcie@10,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0082000 0 0x2000>;
+                                reg = <0x5000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 103>;
+                                marvell,pcie-port = <3>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 27>;
+                                status = "disabled";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 936c25dc32b0..23a5ac4490a8 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -111,5 +111,193 @@
                                 clocks = <&gateclk 1>;
                                 status = "disabled";
                 };
+
+                /*
+                 * MV78460 has 4 PCIe units Gen2.0: Two units can be
+                 * configured as x4 or quad x1 lanes. Two units are
+                 * x4/x1.
+                 */
+                pcie-controller {
+                        compatible = "marvell,armada-xp-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
+                                  0x82000000 0 0xd0042000 0xd0042000 0 0x00002000   /* Port 2.0 registers */
+                                  0x82000000 0 0xd0044000 0xd0044000 0 0x00002000   /* Port 0.1 registers */
+                                  0x82000000 0 0xd0048000 0xd0048000 0 0x00002000   /* Port 0.2 registers */
+                                  0x82000000 0 0xd004c000 0xd004c000 0 0x00002000   /* Port 0.3 registers */
+                                  0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */
+                                  0x82000000 0 0xd0082000 0xd0082000 0 0x00002000   /* Port 3.0 registers */
+                                  0x82000000 0 0xd0084000 0xd0084000 0 0x00002000   /* Port 1.1 registers */
+                                  0x82000000 0 0xd0088000 0xd0088000 0 0x00002000   /* Port 1.2 registers */
+                                  0x82000000 0 0xd008c000 0xd008c000 0 0x00002000   /* Port 1.3 registers */
+                                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 58>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 59>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <1>;
+                                clocks = <&gateclk 6>;
+                                status = "disabled";
+                        };
+
+                        pcie@3,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
+                                reg = <0x1800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 60>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <2>;
+                                clocks = <&gateclk 7>;
+                                status = "disabled";
+                        };
+
+                        pcie@4,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
+                                reg = <0x2000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 61>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <3>;
+                                clocks = <&gateclk 8>;
+                                status = "disabled";
+                        };
+
+                        pcie@5,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
+                                reg = <0x2800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 62>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 9>;
+                                status = "disabled";
+                        };
+
+                        pcie@6,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
+                                reg = <0x3000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 63>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <1>;
+                                clocks = <&gateclk 10>;
+                                status = "disabled";
+                        };
+
+                        pcie@7,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
+                                reg = <0x3800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 64>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <2>;
+                                clocks = <&gateclk 11>;
+                                status = "disabled";
+                        };
+
+                        pcie@8,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
+                                reg = <0x4000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 65>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <3>;
+                                clocks = <&gateclk 12>;
+                                status = "disabled";
+                        };
+                        pcie@9,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
+                                reg = <0x4800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 99>;
+                                marvell,pcie-port = <2>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 26>;
+                                status = "disabled";
+                        };
+
+                        pcie@10,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
+                                reg = <0x5000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 103>;
+                                marvell,pcie-port = <3>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 27>;
+                                status = "disabled";
+                        };
+                };
         };
  };
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 3818a82176a2..9d04f04d4e39 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -139,5 +139,43 @@
                 usb@d0051000 {
                         status = "okay";
                 };
+
+                devbus-bootcs@d0010400 {
+                        status = "okay";
+                        ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
+
+                        /* Device Bus parameters are required */
+
+                        /* Read parameters */
+                        devbus,bus-width    = <8>;
+                        devbus,turn-off-ps  = <60000>;
+                        devbus,badr-skew-ps = <0>;
+                        devbus,acc-first-ps = <124000>;
+                        devbus,acc-next-ps  = <248000>;
+                        devbus,rd-setup-ps  = <0>;
+                        devbus,rd-hold-ps   = <0>;
+
+                        /* Write parameters */
+                        devbus,sync-enable = <0>;
+                        devbus,wr-high-ps  = <60000>;
+                        devbus,wr-low-ps   = <60000>;
+                        devbus,ale-wr-ps   = <60000>;
+
+                        /* NOR 128 MiB */
+                        nor@0 {
+                                compatible = "cfi-flash";
+                                reg = <0 0x8000000>;
+                                bank-width = <2>;
+                        };
+                };
+
+                pcie-controller {
+                        status = "okay";
+                        /* Internal mini-PCIe connector */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index ca00d8326c87..29dfeb6d4a26 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -151,5 +151,11 @@
                         status = "disabled";
                 };
 
+                thermal@d00182b0 {
+                        compatible = "marvell,armadaxp-thermal";
+                        reg = <0xd00182b0 0x4
+                               0xd00184d0 0x4>;
+                        status = "okay";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts
new file mode 100644
index 000000000000..c7aebba4e8e7
--- /dev/null
+++ b/arch/arm/boot/dts/at91-ariag25.dts
@@ -0,0 +1,171 @@
+/*
+ * at91-ariag25.dts - Device Tree file for Acme Systems Aria G25 (AT91SAM9G25 based)
+ *
+ * Copyright (C) 2013 Douglas Gilbert <dgilbert@interlog.com>,
+ *                    Robert Nelson <robertcnelson@gmail.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9g25.dtsi"
+
+/ {
+        model = "Acme Systems Aria G25";
+        compatible = "acme,ariag25", "atmel,at91sam9x5ek",
+                     "atmel,at91sam9x5", "atmel,at91sam9";
+
+        aliases {
+                serial0 = &dbgu;
+                serial1 = &usart0;
+                serial2 = &usart1;
+                serial3 = &usart2;
+                serial4 = &usart3;
+                serial5 = &uart0;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait";
+        };
+
+        memory {
+                /* 128 MB, change this for 256 MB revision */
+                reg = <0x20000000 0x8000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        mmc0: mmc@f0008000 {
+                                /* N.B. Aria has no SD card detect (CD), assumed present */
+
+                                pinctrl-0 = <
+                                        &pinctrl_mmc0_slot0_clk_cmd_dat0
+                                        &pinctrl_mmc0_slot0_dat1_3>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                };
+                        };
+
+                        i2c0: i2c@f8010000 {
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@f8014000 {
+                                status = "okay";
+                        };
+
+                        /* TWD2+TCLK2 hidden behind ethernet, so no i2c2 */
+
+                        usart0: serial@f801c000 {
+                                pinctrl-0 = <&pinctrl_usart0
+                                             &pinctrl_usart0_rts
+                                             &pinctrl_usart0_cts>;
+                                status = "okay";
+                        };
+
+                        usart1: serial@f8020000 {
+                                pinctrl-0 = <&pinctrl_usart1
+                                             /* &pinctrl_usart1_rts */
+                                             /* &pinctrl_usart1_cts */
+                                            >;
+                                status = "okay";
+                        };
+
+                        usart2: serial@f8024000 {
+                                /* cannot activate RTS2+CTS2, clash with
+                                 * ethernet on PB0 and PB1 */
+                                pinctrl-0 = <&pinctrl_usart2>;
+                                status = "okay";
+                        };
+
+                        usart3: serial@f8028000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8028000 0x200>;
+                                interrupts = <8 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart3
+                                             /* &pinctrl_usart3_rts */
+                                             /* &pinctrl_usart3_cts */
+                                            >;
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@f802c000 {
+                                phy-mode = "rmii";
+                                /*
+                                 * following can be overwritten by bootloader:
+                                 * for example u-boot 'ftd set' command
+                                 */
+                                local-mac-address = [00 00 00 00 00 00];
+                                status = "okay";
+                        };
+
+                        uart0: serial@f8040000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8040000 0x200>;
+                                interrupts = <15 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart0>;
+                                status = "okay";
+                        };
+
+                        adc0: adc@f804c000 {
+                                status = "okay";
+                                atmel,adc-channels-used = <0xf>;
+                                atmel,adc-num-channels = <4>;
+                        };
+
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+
+                        pinctrl@fffff400 {
+                                w1_0 {
+                                        pinctrl_w1_0: w1_0-0 {
+                                                atmel,pins = <0 21 0x0 0x1>; /* PA21 PIO, pull-up */
+                                        };
+                                };
+                        };
+                };
+
+                usb0: ohci@00600000 {
+                        status = "okay";
+                        num-ports = <3>;
+                };
+
+                usb1: ehci@00700000 {
+                        status = "okay";
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                /* little green LED in middle of Aria G25 module */
+                aria_led {
+                        label = "aria_led";
+                        gpios = <&pioB 8 0>; /* PB8 */
+                        linux,default-trigger = "heartbeat";
+                };
+
+        };
+
+        onewire@0 {
+                compatible = "w1-gpio";
+                gpios = <&pioA 21 1>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_w1_0>;
+        };
+};
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index b0268a5f4b4e..5d3ed5aafc69 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -29,6 +29,7 @@
                 gpio3 = &pioD;
                 tcb0 = &tcb0;
                 tcb1 = &tcb1;
+                i2c0 = &i2c0;
                 ssc0 = &ssc0;
                 ssc1 = &ssc1;
                 ssc2 = &ssc2;
@@ -91,6 +92,17 @@
                                 interrupts = <20 4 0 21 4 0 22 4 0>;
                         };
 
+                        i2c0: i2c@fffb8000 {
+                                compatible = "atmel,at91rm9200-i2c";
+                                reg = <0xfffb8000 0x4000>;
+                                interrupts = <12 4 6>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_twi>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+
                         mmc0: mmc@fffb4000 {
                                 compatible = "atmel,hsmci";
                                 reg = <0xfffb4000 0x4000>;
@@ -365,6 +377,20 @@
                                         };
                                 };
 
+                                twi {
+                                        pinctrl_twi: twi-0 {
+                                                atmel,pins =
+                                                        <0 25 0x1 0x2   /* PA25 periph A with multi drive */
+                                                         0 26 0x1 0x2>; /* PA26 periph A with multi drive */
+                                        };
+
+                                        pinctrl_twi_gpio: twi_gpio-0 {
+                                                atmel,pins =
+                                                        <0 25 0x0 0x2   /* PA25 GPIO with multi drive */
+                                                         0 26 0x0 0x2>; /* PA26 GPIO with multi drive */
+                                        };
+                                };
+
                                 pioA: gpio@fffff400 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff400 0x200>;
@@ -500,6 +526,8 @@
                 i2c-gpio,sda-open-drain;
                 i2c-gpio,scl-open-drain;
                 i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_twi_gpio>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 status = "disabled";
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index cb7bcc51608d..70b5ccbac234 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -158,8 +158,8 @@
                                 usart1 {
                                         pinctrl_usart1: usart1-0 {
                                                 atmel,pins =
-                                                        <2 6 0x1 0x1    /* PB6 periph A with pullup */
-                                                         2 7 0x1 0x0>;  /* PB7 periph A */
+                                                        <1 6 0x1 0x1    /* PB6 periph A with pullup */
+                                                         1 7 0x1 0x0>;  /* PB7 periph A */
                                         };
 
                                         pinctrl_usart1_rts: usart1_rts-0 {
@@ -194,18 +194,18 @@
                                 usart3 {
                                         pinctrl_usart3: usart3-0 {
                                                 atmel,pins =
-                                                        <2 10 0x1 0x1   /* PB10 periph A with pullup */
-                                                         2 11 0x1 0x0>; /* PB11 periph A */
+                                                        <1 10 0x1 0x1   /* PB10 periph A with pullup */
+                                                         1 11 0x1 0x0>; /* PB11 periph A */
                                         };
 
                                         pinctrl_usart3_rts: usart3_rts-0 {
                                                 atmel,pins =
-                                                        <3 8 0x2 0x0>;  /* PB8 periph B */
+                                                        <2 8 0x2 0x0>;  /* PC8 periph B */
                                         };
 
                                         pinctrl_usart3_cts: usart3_cts-0 {
                                                 atmel,pins =
-                                                        <3 10 0x2 0x0>; /* PB10 periph B */
+                                                        <2 10 0x2 0x0>; /* PC10 periph B */
                                         };
                                 };
 
@@ -220,8 +220,8 @@
                                 uart1 {
                                         pinctrl_uart1: uart1-0 {
                                                 atmel,pins =
-                                                        <2 12 0x1 0x1   /* PB12 periph A with pullup */
-                                                         2 13 0x1 0x0>; /* PB13 periph A */
+                                                        <1 12 0x1 0x1   /* PB12 periph A with pullup */
+                                                         1 13 0x1 0x0>; /* PB13 periph A */
                                         };
                                 };
 
@@ -322,6 +322,24 @@
                                         };
                                 };
 
+                                spi0 {
+                                        pinctrl_spi0: spi0-0 {
+                                                atmel,pins =
+                                                        <0 0 0x1 0x0    /* PA0 periph A SPI0_MISO pin */
+                                                         0 1 0x1 0x0    /* PA1 periph A SPI0_MOSI pin */
+                                                         0 2 0x1 0x0>;  /* PA2 periph A SPI0_SPCK pin */
+                                        };
+                                };
+
+                                spi1 {
+                                        pinctrl_spi1: spi1-0 {
+                                                atmel,pins =
+                                                        <1 0 0x1 0x0    /* PB0 periph A SPI1_MISO pin */
+                                                         1 1 0x1 0x0    /* PB1 periph A SPI1_MOSI pin */
+                                                         1 2 0x1 0x0>;  /* PB2 periph A SPI1_SPCK pin */
+                                        };
+                                };
+
                                 pioA: gpio@fffff400 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff400 0x200>;
@@ -471,6 +489,28 @@
                                 status = "disabled";
                         };
 
+                        spi0: spi@fffc8000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91rm9200-spi";
+                                reg = <0xfffc8000 0x200>;
+                                interrupts = <12 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi0>;
+                                status = "disabled";
+                        };
+
+                        spi1: spi@fffcc000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91rm9200-spi";
+                                reg = <0xfffcc000 0x200>;
+                                interrupts = <13 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi1>;
+                                status = "disabled";
+                        };
+
                         adc0: adc@fffe0000 {
                                 compatible = "atmel,at91sam9260-adc";
                                 reg = <0xfffe0000 0x100>;
@@ -484,6 +524,9 @@
                                 atmel,adc-drdy-mask = <0x10000>;
                                 atmel,adc-status-register = <0x1c>;
                                 atmel,adc-trigger-register = <0x04>;
+                                atmel,adc-res = <8 10>;
+                                atmel,adc-res-names = "lowres", "highres";
+                                atmel,adc-use-res = "highres";
 
                                 trigger@0 {
                                         trigger-name = "timer-counter-0";
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 271d4de026e9..94b58ab2cc08 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -303,6 +303,24 @@
                                         };
                                 };
 
+                                spi0 {
+                                        pinctrl_spi0: spi0-0 {
+                                                atmel,pins =
+                                                        <0 0 0x2 0x0    /* PA0 periph B SPI0_MISO pin */
+                                                         0 1 0x2 0x0    /* PA1 periph B SPI0_MOSI pin */
+                                                         0 2 0x2 0x0>;  /* PA2 periph B SPI0_SPCK pin */
+                                        };
+                                };
+
+                                spi1 {
+                                        pinctrl_spi1: spi1-0 {
+                                                atmel,pins =
+                                                        <1 12 0x1 0x0   /* PB12 periph A SPI1_MISO pin */
+                                                         1 13 0x1 0x0   /* PB13 periph A SPI1_MOSI pin */
+                                                         1 14 0x1 0x0>; /* PB14 periph A SPI1_SPCK pin */
+                                        };
+                                };
+
                                 pioA: gpio@fffff200 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff200 0x200>;
@@ -462,6 +480,28 @@
                                 reg = <0xfffffd40 0x10>;
                                 status = "disabled";
                         };
+
+                        spi0: spi@fffa4000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91rm9200-spi";
+                                reg = <0xfffa4000 0x200>;
+                                interrupts = <14 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi0>;
+                                status = "disabled";
+                        };
+
+                        spi1: spi@fffa8000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91rm9200-spi";
+                                reg = <0xfffa8000 0x200>;
+                                interrupts = <15 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi1>;
+                                status = "disabled";
+                        };
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 1eb08728f527..3b82d91e7fcc 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -79,6 +79,16 @@
                                         };
                                 };
                         };
+
+                        spi0: spi@fffa4000 {
+                                status = "okay";
+                                cs-gpios = <&pioA 5 0>, <0>, <0>, <0>;
+                                mtd_dataflash@0 {
+                                        compatible = "atmel,at45", "atmel,dataflash";
+                                        spi-max-frequency = <50000000>;
+                                        reg = <0>;
+                                };
+                        };
                 };
 
                 nand0: nand@40000000 {
@@ -155,8 +165,6 @@
 
         gpio_keys {
                 compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
 
                 left_click {
                         label = "left_click";
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi
index fbe7a7089c2a..28467fd6bf96 100644
--- a/arch/arm/boot/dts/at91sam9g15.dtsi
+++ b/arch/arm/boot/dts/at91sam9g15.dtsi
@@ -10,7 +10,7 @@
 
 / {
         model = "Atmel AT91SAM9G15 SoC";
-        compatible = "atmel, at91sam9g15, atmel,at91sam9x5";
+        compatible = "atmel,at91sam9g15", "atmel,at91sam9x5";
 
         ahb {
                 apb {
diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts
index 86dd3f6d938f..5427b2dba87e 100644
--- a/arch/arm/boot/dts/at91sam9g15ek.dts
+++ b/arch/arm/boot/dts/at91sam9g15ek.dts
@@ -11,6 +11,6 @@
 /include/ "at91sam9x5ek.dtsi"
 
 / {
-        model = "Atmel AT91SAM9G25-EK";
+        model = "Atmel AT91SAM9G15-EK";
         compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
 };
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index da15e83e7f17..6a92c5baef8c 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -96,6 +96,16 @@
                                 status = "okay";
                                 pinctrl-0 = <&pinctrl_ssc0_tx>;
                         };
+
+                        spi0: spi@fffc8000 {
+                                status = "okay";
+                                cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
+                                mtd_dataflash@0 {
+                                        compatible = "atmel,at45", "atmel,dataflash";
+                                        spi-max-frequency = <50000000>;
+                                        reg = <1>;
+                                };
+                        };
                 };
 
                 nand0: nand@40000000 {
@@ -167,8 +177,6 @@
 
         gpio_keys {
                 compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
 
                 btn3 {
                         label = "Button 3";
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
index 05a718fb83c4..5fd32df03f25 100644
--- a/arch/arm/boot/dts/at91sam9g25.dtsi
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -10,7 +10,7 @@
 
 / {
         model = "Atmel AT91SAM9G25 SoC";
-        compatible = "atmel, at91sam9g25, atmel,at91sam9x5";
+        compatible = "atmel,at91sam9g25", "atmel,at91sam9x5";
 
         ahb {
                 apb {
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index c5ab16fba059..a1c511fecdc1 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -13,4 +13,13 @@
 / {
         model = "Atmel AT91SAM9G25-EK";
         compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+
+        ahb {
+                apb {
+                        macb0: ethernet@f802c000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
index f9d14a722794..d6fa8af50724 100644
--- a/arch/arm/boot/dts/at91sam9g35.dtsi
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -10,7 +10,7 @@
 
 / {
         model = "Atmel AT91SAM9G35 SoC";
-        compatible = "atmel, at91sam9g35, atmel,at91sam9x5";
+        compatible = "atmel,at91sam9g35", "atmel,at91sam9x5";
 
         ahb {
                 apb {
diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts
index 95944bdd798d..6f58ab8d21f5 100644
--- a/arch/arm/boot/dts/at91sam9g35ek.dts
+++ b/arch/arm/boot/dts/at91sam9g35ek.dts
@@ -13,4 +13,13 @@
 / {
         model = "Atmel AT91SAM9G35-EK";
         compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+
+        ahb {
+                apb {
+                        macb0: ethernet@f802c000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 6b1d4cab24c2..f8f7370e8669 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -322,6 +322,24 @@
                                         };
                                 };
 
+                                spi0 {
+                                        pinctrl_spi0: spi0-0 {
+                                                atmel,pins =
+                                                        <1 0 0x1 0x0    /* PB0 periph A SPI0_MISO pin */
+                                                         1 1 0x1 0x0    /* PB1 periph A SPI0_MOSI pin */
+                                                         1 2 0x1 0x0>;  /* PB2 periph A SPI0_SPCK pin */
+                                        };
+                                };
+
+                                spi1 {
+                                        pinctrl_spi1: spi1-0 {
+                                                atmel,pins =
+                                                        <1 14 0x1 0x0   /* PB14 periph A SPI1_MISO pin */
+                                                         1 15 0x1 0x0   /* PB15 periph A SPI1_MOSI pin */
+                                                         1 16 0x1 0x0>; /* PB16 periph A SPI1_SPCK pin */
+                                        };
+                                };
+
                                 pioA: gpio@fffff200 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff200 0x200>;
@@ -484,6 +502,9 @@
                                 atmel,adc-drdy-mask = <0x10000>;
                                 atmel,adc-status-register = <0x1c>;
                                 atmel,adc-trigger-register = <0x08>;
+                                atmel,adc-res = <8 10>;
+                                atmel,adc-res-names = "lowres", "highres";
+                                atmel,adc-use-res = "highres";
 
                                 trigger@0 {
                                         trigger-name = "external-rising";
@@ -531,6 +552,28 @@
                                 reg = <0xfffffd40 0x10>;
                                 status = "disabled";
                         };
+
+                        spi0: spi@fffa4000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91rm9200-spi";
+                                reg = <0xfffa4000 0x200>;
+                                interrupts = <14 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi0>;
+                                status = "disabled";
+                        };
+
+                        spi1: spi@fffa8000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91rm9200-spi";
+                                reg = <0xfffa8000 0x200>;
+                                interrupts = <15 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi1>;
+                                status = "disabled";
+                        };
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 20c31913c270..51d9251b5bbe 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -102,6 +102,16 @@
                                         };
                                 };
                         };
+
+                        spi0: spi@fffa4000{
+                                status = "okay";
+                                cs-gpios = <&pioB 3 0>, <0>, <0>, <0>;
+                                mtd_dataflash@0 {
+                                        compatible = "atmel,at45", "atmel,dataflash";
+                                        spi-max-frequency = <13000000>;
+                                        reg = <0>;
+                                };
+                        };
                 };
 
                 nand0: nand@40000000 {
@@ -162,8 +172,6 @@
 
         gpio_keys {
                 compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
 
                 left_click {
                         label = "left_click";
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 7750f98dd764..b2961f1ea51b 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -261,6 +261,24 @@
                                         };
                                 };
 
+                                spi0 {
+                                        pinctrl_spi0: spi0-0 {
+                                                atmel,pins =
+                                                        <0 11 0x1 0x0   /* PA11 periph A SPI0_MISO pin */
+                                                         0 12 0x1 0x0   /* PA12 periph A SPI0_MOSI pin */
+                                                         0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */
+                                        };
+                                };
+
+                                spi1 {
+                                        pinctrl_spi1: spi1-0 {
+                                                atmel,pins =
+                                                        <0 21 0x2 0x0   /* PA21 periph B SPI1_MISO pin */
+                                                         0 22 0x2 0x0   /* PA22 periph B SPI1_MOSI pin */
+                                                         0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */
+                                        };
+                                };
+
                                 pioA: gpio@fffff400 {
                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                         reg = <0xfffff400 0x200>;
@@ -373,6 +391,28 @@
                                 #size-cells = <0>;
                                 status = "disabled";
                         };
+
+                        spi0: spi@f0000000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91rm9200-spi";
+                                reg = <0xf0000000 0x100>;
+                                interrupts = <13 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi0>;
+                                status = "disabled";
+                        };
+
+                        spi1: spi@f0004000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91rm9200-spi";
+                                reg = <0xf0004000 0x100>;
+                                interrupts = <14 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi1>;
+                                status = "disabled";
+                        };
                 };
 
                 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index d400f8de4387..d30e48bd1e9d 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -67,6 +67,16 @@
                                         };
                                 };
                         };
+
+                        spi0: spi@f0000000 {
+                                status = "okay";
+                                cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;
+                                m25p80@0 {
+                                        compatible = "atmel,at25df321a";
+                                        spi-max-frequency = <50000000>;
+                                        reg = <0>;
+                                };
+                        };
                 };
 
                 nand0: nand@40000000 {
@@ -104,8 +114,6 @@
 
         gpio_keys {
                 compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
 
                 enter {
                         label = "Enter";
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
index 54eb33ba6d22..9ac2bc2b4f07 100644
--- a/arch/arm/boot/dts/at91sam9x25.dtsi
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -10,7 +10,7 @@
 
 / {
         model = "Atmel AT91SAM9X25 SoC";
-        compatible = "atmel, at91sam9x25, atmel,at91sam9x5";
+        compatible = "atmel,at91sam9x25", "atmel,at91sam9x5";
 
         ahb {
                 apb {
diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts
index af907eaa1f25..3b40d11d65e7 100644
--- a/arch/arm/boot/dts/at91sam9x25ek.dts
+++ b/arch/arm/boot/dts/at91sam9x25ek.dts
@@ -13,4 +13,18 @@
 / {
         model = "Atmel AT91SAM9G25-EK";
         compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+
+        ahb {
+                apb {
+                        macb0: ethernet@f802c000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        macb1: ethernet@f8030000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
index fb102d6126ce..ba67d83d17ac 100644
--- a/arch/arm/boot/dts/at91sam9x35.dtsi
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -10,7 +10,7 @@
 
 / {
         model = "Atmel AT91SAM9X35 SoC";
-        compatible = "atmel, at91sam9x35, atmel,at91sam9x5";
+        compatible = "atmel,at91sam9x35", "atmel,at91sam9x5";
 
         ahb {
                 apb {
diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts
index 5ccb607b5414..6ad19a0d5424 100644
--- a/arch/arm/boot/dts/at91sam9x35ek.dts
+++ b/arch/arm/boot/dts/at91sam9x35ek.dts
@@ -13,4 +13,13 @@
 / {
         model = "Atmel AT91SAM9X35-EK";
         compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+
+        ahb {
+                apb {
+                        macb0: ethernet@f802c000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index a98c0d50fbbe..640b3bbbb706 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -343,6 +343,72 @@
                                         };
                                 };
 
+                                spi0 {
+                                        pinctrl_spi0: spi0-0 {
+                                                atmel,pins =
+                                                        <0 11 0x1 0x0   /* PA11 periph A SPI0_MISO pin */
+                                                         0 12 0x1 0x0   /* PA12 periph A SPI0_MOSI pin */
+                                                         0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */
+                                        };
+                                };
+
+                                spi1 {
+                                        pinctrl_spi1: spi1-0 {
+                                                atmel,pins =
+                                                        <0 21 0x2 0x0   /* PA21 periph B SPI1_MISO pin */
+                                                         0 22 0x2 0x0   /* PA22 periph B SPI1_MOSI pin */
+                                                         0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */
+                                        };
+                                };
+
+                                i2c0 {
+                                        pinctrl_i2c0: i2c0-0 {
+                                                atmel,pins =
+                                                        <0 30 0x1 0x0   /* PA30 periph A I2C0 data */
+                                                         0 31 0x1 0x0>; /* PA31 periph A I2C0 clock */
+                                        };
+                                };
+
+                                i2c1 {
+                                        pinctrl_i2c1: i2c1-0 {
+                                                atmel,pins =
+                                                        <2 0 0x3 0x0    /* PC0 periph C I2C1 data */
+                                                         2 1 0x3 0x0>;  /* PC1 periph C I2C1 clock */
+                                        };
+                                };
+
+                                i2c2 {
+                                        pinctrl_i2c2: i2c2-0 {
+                                                atmel,pins =
+                                                        <1 4 0x2 0x0    /* PB4 periph B I2C2 data */
+                                                         1 5 0x2 0x0>;  /* PB5 periph B I2C2 clock */
+                                        };
+                                };
+
+                                i2c_gpio0 {
+                                        pinctrl_i2c_gpio0: i2c_gpio0-0 {
+                                                atmel,pins =
+                                                        <0 30 0x0 0x2   /* PA30 gpio multidrive I2C0 data */
+                                                         0 31 0x0 0x2>; /* PA31 gpio multidrive I2C0 clock */
+                                        };
+                                };
+
+                                i2c_gpio1 {
+                                        pinctrl_i2c_gpio1: i2c_gpio1-0 {
+                                                atmel,pins =
+                                                        <2 0 0x0 0x2    /* PC0 gpio multidrive I2C1 data */
+                                                         2 1 0x0 0x2>;  /* PC1 gpio multidrive I2C1 clock */
+                                        };
+                                };
+
+                                i2c_gpio2 {
+                                        pinctrl_i2c_gpio2: i2c_gpio2-0 {
+                                                atmel,pins =
+                                                        <1 4 0x0 0x2    /* PB4 gpio multidrive I2C2 data */
+                                                         1 5 0x0 0x2>;  /* PB5 gpio multidrive I2C2 clock */
+                                        };
+                                };
+
                                 pioA: gpio@fffff400 {
                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                         reg = <0xfffff400 0x200>;
@@ -471,6 +537,8 @@
                                 interrupts = <9 4 6>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c0>;
                                 status = "disabled";
                         };
 
@@ -480,6 +548,8 @@
                                 interrupts = <10 4 6>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c1>;
                                 status = "disabled";
                         };
 
@@ -489,6 +559,8 @@
                                 interrupts = <11 4 6>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c2>;
                                 status = "disabled";
                         };
 
@@ -505,6 +577,9 @@
                                 atmel,adc-drdy-mask = <0x1000000>;
                                 atmel,adc-status-register = <0x30>;
                                 atmel,adc-trigger-register = <0xc0>;
+                                atmel,adc-res = <8 10>;
+                                atmel,adc-res-names = "lowres", "highres";
+                                atmel,adc-use-res = "highres";
 
                                 trigger@0 {
                                         trigger-name = "external-rising";
@@ -529,6 +604,35 @@
                                         trigger-value = <0x6>;
                                 };
                         };
+
+                        spi0: spi@f0000000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91rm9200-spi";
+                                reg = <0xf0000000 0x100>;
+                                interrupts = <13 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi0>;
+                                status = "disabled";
+                        };
+
+                        spi1: spi@f0004000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91rm9200-spi";
+                                reg = <0xf0004000 0x100>;
+                                interrupts = <14 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi1>;
+                                status = "disabled";
+                        };
+
+                        rtc@fffffeb0 {
+                                compatible = "atmel,at91rm9200-rtc";
+                                reg = <0xfffffeb0 0x40>;
+                                interrupts = <1 4 7>;
+                                status = "disabled";
+                        };
                 };
 
                 nand0: nand@40000000 {
@@ -577,6 +681,8 @@
                 i2c-gpio,delay-us = <2>;        /* ~100 kHz */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_i2c_gpio0>;
                 status = "disabled";
         };
 
@@ -590,6 +696,8 @@
                 i2c-gpio,delay-us = <2>;        /* ~100 kHz */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_i2c_gpio1>;
                 status = "disabled";
         };
 
@@ -603,6 +711,8 @@
                 i2c-gpio,delay-us = <2>;        /* ~100 kHz */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_i2c_gpio2>;
                 status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 4027ac7e4502..347a74a857f6 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -24,6 +24,16 @@
         };
 
         ahb {
+                apb {
+                        pinctrl@fffff400 {
+                                1wire_cm {
+                                        pinctrl_1wire_cm: 1wire_cm-0 {
+                                                atmel,pins = <1 18 0x0 0x2>; /* PB18 multidrive, conflicts with led */
+                                        };
+                                };
+                        };
+                };
+
                 nand0: nand@40000000 {
                         nand-bus-width = <8>;
                         nand-ecc-mode = "hw";
@@ -74,4 +84,14 @@
                         gpios = <&pioD 21 0>;
                 };
         };
+
+        1wire_cm {
+                compatible = "w1-gpio";
+                gpios = <&pioB 18 0>;
+                linux,open-drain;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_1wire_cm>;
+                status = "okay";
+        };
+
 };
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index 8a7cf1d9cf5d..1fa48d2bfd80 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -13,7 +13,7 @@
         compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
 
         chosen {
-                bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
+                bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
         };
 
         ahb {
@@ -52,23 +52,10 @@
                                 status = "okay";
                         };
 
-                        macb0: ethernet@f802c000 {
-                                phy-mode = "rmii";
-                                status = "okay";
-                        };
-
                         i2c0: i2c@f8010000 {
                                 status = "okay";
                         };
 
-                        i2c1: i2c@f8014000 {
-                                status = "okay";
-                        };
-
-                        i2c2: i2c@f8018000 {
-                                status = "okay";
-                        };
-
                         pinctrl@fffff400 {
                                 mmc0 {
                                         pinctrl_board_mmc0: mmc0-board {
@@ -84,6 +71,16 @@
                                         };
                                 };
                         };
+
+                        spi0: spi@f0000000 {
+                                status = "okay";
+                                cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;
+                                m25p80@0 {
+                                        compatible = "atmel,at25df321a";
+                                        spi-max-frequency = <50000000>;
+                                        reg = <0>;
+                                };
+                        };
                 };
 
                 usb0: ohci@00600000 {
diff --git a/arch/arm/boot/dts/atlas6-evb.dts b/arch/arm/boot/dts/atlas6-evb.dts
new file mode 100644
index 000000000000..ab042ca8dea1
--- /dev/null
+++ b/arch/arm/boot/dts/atlas6-evb.dts
@@ -0,0 +1,78 @@
+/*
+ * DTS file for CSR SiRFatlas6 Evaluation Board
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/dts-v1/;
+
+/include/ "atlas6.dtsi"
+
+/ {
+        model = "CSR SiRFatlas6 Evaluation Board";
+        compatible = "sirf,atlas6-cb", "sirf,atlas6";
+
+        memory {
+                reg = <0x00000000 0x20000000>;
+        };
+
+        axi {
+                peri-iobg {
+                        uart@b0060000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&uart1_pins_a>;
+                        };
+                        spi@b00d0000 {
+                                status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi0_pins_a>;
+                                spi@0 {
+                                        compatible = "spidev";
+                                        reg = <0>;
+                                        spi-max-frequency = <1000000>;
+                                };
+                        };
+                        spi@b0170000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi1_pins_a>;
+                        };
+                        i2c0: i2c@b00e0000 {
+                                status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c0_pins_a>;
+                                lcd@40 {
+                                        compatible = "sirf,lcd";
+                                        reg = <0x40>;
+                                };
+                        };
+
+                };
+                disp-iobg {
+                        lcd@90010000 {
+                                status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&lcd_24pins_a>;
+                        };
+                };
+        };
+        display: display@0 {
+            panels {
+                panel0: panel@0 {
+                        panel-name = "Innolux TFT";
+                        hactive = <800>;
+                        vactive = <480>;
+                        left_margin = <20>;
+                        right_margin = <234>;
+                        upper_margin = <3>;
+                        lower_margin = <41>;
+                        hsync_len = <3>;
+                        vsync_len = <2>;
+                        pixclock = <33264000>;
+                        sync = <3>;
+                        timing = <0x88>;
+                        };
+            };
+        };
+};
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
new file mode 100644
index 000000000000..7d1a27949c13
--- /dev/null
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -0,0 +1,668 @@
+/*
+ * DTS file for CSR SiRFatlas6 SoC
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "sirf,atlas6";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        interrupt-parent = <&intc>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;
+                        i-cache-line-size = <32>;
+                        d-cache-size = <32768>;
+                        i-cache-size = <32768>;
+                        /* from bootloader */
+                        timebase-frequency = <0>;
+                        bus-frequency = <0>;
+                        clock-frequency = <0>;
+                };
+        };
+
+        axi {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x40000000 0x40000000 0x80000000>;
+
+                intc: interrupt-controller@80020000 {
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
+                        compatible = "sirf,prima2-intc";
+                        reg = <0x80020000 0x1000>;
+                };
+
+                sys-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x88000000 0x88000000 0x40000>;
+
+                        clks: clock-controller@88000000 {
+                                compatible = "sirf,atlas6-clkc";
+                                reg = <0x88000000 0x1000>;
+                                interrupts = <3>;
+                                #clock-cells = <1>;
+                        };
+
+                        reset-controller@88010000 {
+                                compatible = "sirf,prima2-rstc";
+                                reg = <0x88010000 0x1000>;
+                        };
+
+                        rsc-controller@88020000 {
+                                compatible = "sirf,prima2-rsc";
+                                reg = <0x88020000 0x1000>;
+                        };
+                };
+
+                mem-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x90000000 0x90000000 0x10000>;
+
+                        memory-controller@90000000 {
+                                compatible = "sirf,prima2-memc";
+                                reg = <0x90000000 0x10000>;
+                                interrupts = <27>;
+                                clocks = <&clks 5>;
+                        };
+                };
+
+                disp-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x90010000 0x90010000 0x30000>;
+
+                        lcd@90010000 {
+                                compatible = "sirf,prima2-lcd";
+                                reg = <0x90010000 0x20000>;
+                                interrupts = <30>;
+                                clocks = <&clks 34>;
+                                display=<&display>;
+                                /* later transfer to pwm */
+                                bl-gpio = <&gpio 7 0>;
+                                default-panel = <&panel0>;
+                        };
+
+                        vpp@90020000 {
+                                compatible = "sirf,prima2-vpp";
+                                reg = <0x90020000 0x10000>;
+                                interrupts = <31>;
+                                clocks = <&clks 35>;
+                        };
+                };
+
+                graphics-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x98000000 0x98000000 0x8000000>;
+
+                        graphics@98000000 {
+                                compatible = "powervr,sgx510";
+                                reg = <0x98000000 0x8000000>;
+                                interrupts = <6>;
+                                clocks = <&clks 32>;
+                        };
+                };
+
+                dsp-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xa8000000 0xa8000000 0x2000000>;
+
+                        dspif@a8000000 {
+                                compatible = "sirf,prima2-dspif";
+                                reg = <0xa8000000 0x10000>;
+                                interrupts = <9>;
+                        };
+
+                        gps@a8010000 {
+                                compatible = "sirf,prima2-gps";
+                                reg = <0xa8010000 0x10000>;
+                                interrupts = <7>;
+                                clocks = <&clks 9>;
+                        };
+
+                        dsp@a9000000 {
+                                compatible = "sirf,prima2-dsp";
+                                reg = <0xa9000000 0x1000000>;
+                                interrupts = <8>;
+                                clocks = <&clks 8>;
+                        };
+                };
+
+                peri-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xb0000000 0xb0000000 0x180000>,
+                               <0x56000000 0x56000000 0x1b00000>;
+
+                        timer@b0020000 {
+                                compatible = "sirf,prima2-tick";
+                                reg = <0xb0020000 0x1000>;
+                                interrupts = <0>;
+                        };
+
+                        nand@b0030000 {
+                                compatible = "sirf,prima2-nand";
+                                reg = <0xb0030000 0x10000>;
+                                interrupts = <41>;
+                                clocks = <&clks 26>;
+                        };
+
+                        audio@b0040000 {
+                                compatible = "sirf,prima2-audio";
+                                reg = <0xb0040000 0x10000>;
+                                interrupts = <35>;
+                                clocks = <&clks 27>;
+                        };
+
+                        uart0: uart@b0050000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-uart";
+                                reg = <0xb0050000 0x1000>;
+                                interrupts = <17>;
+                                fifosize = <128>;
+                                clocks = <&clks 13>;
+                        };
+
+                        uart1: uart@b0060000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-uart";
+                                reg = <0xb0060000 0x1000>;
+                                interrupts = <18>;
+                                fifosize = <32>;
+                                clocks = <&clks 14>;
+                        };
+
+                        uart2: uart@b0070000 {
+                                cell-index = <2>;
+                                compatible = "sirf,prima2-uart";
+                                reg = <0xb0070000 0x1000>;
+                                interrupts = <19>;
+                                fifosize = <128>;
+                                clocks = <&clks 15>;
+                        };
+
+                        usp0: usp@b0080000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-usp";
+                                reg = <0xb0080000 0x10000>;
+                                interrupts = <20>;
+                                clocks = <&clks 28>;
+                        };
+
+                        usp1: usp@b0090000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-usp";
+                                reg = <0xb0090000 0x10000>;
+                                interrupts = <21>;
+                                clocks = <&clks 29>;
+                        };
+
+                        dmac0: dma-controller@b00b0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-dmac";
+                                reg = <0xb00b0000 0x10000>;
+                                interrupts = <12>;
+                                clocks = <&clks 24>;
+                        };
+
+                        dmac1: dma-controller@b0160000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-dmac";
+                                reg = <0xb0160000 0x10000>;
+                                interrupts = <13>;
+                                clocks = <&clks 25>;
+                        };
+
+                        vip@b00C0000 {
+                                compatible = "sirf,prima2-vip";
+                                reg = <0xb00C0000 0x10000>;
+                                clocks = <&clks 31>;
+                        };
+
+                        spi0: spi@b00d0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-spi";
+                                reg = <0xb00d0000 0x10000>;
+                                interrupts = <15>;
+                                sirf,spi-num-chipselects = <1>;
+                                cs-gpios = <&gpio 0 0>;
+                                sirf,spi-dma-rx-channel = <25>;
+                                sirf,spi-dma-tx-channel = <20>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                clocks = <&clks 19>;
+                                status = "disabled";
+                        };
+
+                        spi1: spi@b0170000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-spi";
+                                reg = <0xb0170000 0x10000>;
+                                interrupts = <16>;
+                                clocks = <&clks 20>;
+                                status = "disabled";
+                        };
+
+                        i2c0: i2c@b00e0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-i2c";
+                                reg = <0xb00e0000 0x10000>;
+                                interrupts = <24>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                clocks = <&clks 17>;
+                        };
+
+                        i2c1: i2c@b00f0000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-i2c";
+                                reg = <0xb00f0000 0x10000>;
+                                interrupts = <25>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                clocks = <&clks 18>;
+                        };
+
+                        tsc@b0110000 {
+                                compatible = "sirf,prima2-tsc";
+                                reg = <0xb0110000 0x10000>;
+                                interrupts = <33>;
+                                clocks = <&clks 16>;
+                        };
+
+                        gpio: pinctrl@b0120000 {
+                                #gpio-cells = <2>;
+                                #interrupt-cells = <2>;
+                                compatible = "sirf,atlas6-pinctrl";
+                                reg = <0xb0120000 0x10000>;
+                                interrupts = <43 44 45 46 47>;
+                                gpio-controller;
+                                interrupt-controller;
+
+                                lcd_16pins_a: lcd0@0 {
+                                        lcd {
+                                                sirf,pins = "lcd_16bitsgrp";
+                                                sirf,function = "lcd_16bits";
+                                        };
+                                };
+                                lcd_18pins_a: lcd0@1 {
+                                        lcd {
+                                                sirf,pins = "lcd_18bitsgrp";
+                                                sirf,function = "lcd_18bits";
+                                        };
+                                };
+                                lcd_24pins_a: lcd0@2 {
+                                        lcd {
+                                                sirf,pins = "lcd_24bitsgrp";
+                                                sirf,function = "lcd_24bits";
+                                        };
+                                };
+                                lcdrom_pins_a: lcdrom0@0 {
+                                        lcd {
+                                                sirf,pins = "lcdromgrp";
+                                                sirf,function = "lcdrom";
+                                        };
+                                };
+                                uart0_pins_a: uart0@0 {
+                                        uart {
+                                                sirf,pins = "uart0grp";
+                                                sirf,function = "uart0";
+                                        };
+                                };
+                                uart1_pins_a: uart1@0 {
+                                        uart {
+                                                sirf,pins = "uart1grp";
+                                                sirf,function = "uart1";
+                                        };
+                                };
+                                uart2_pins_a: uart2@0 {
+                                        uart {
+                                                sirf,pins = "uart2grp";
+                                                sirf,function = "uart2";
+                                        };
+                                };
+                                uart2_noflow_pins_a: uart2@1 {
+                                        uart {
+                                                sirf,pins = "uart2_nostreamctrlgrp";
+                                                sirf,function = "uart2_nostreamctrl";
+                                        };
+                                };
+                                spi0_pins_a: spi0@0 {
+                                        spi {
+                                                sirf,pins = "spi0grp";
+                                                sirf,function = "spi0";
+                                        };
+                                };
+                                spi1_pins_a: spi1@0 {
+                                        spi {
+                                                sirf,pins = "spi1grp";
+                                                sirf,function = "spi1";
+                                        };
+                                };
+                                i2c0_pins_a: i2c0@0 {
+                                        i2c {
+                                                sirf,pins = "i2c0grp";
+                                                sirf,function = "i2c0";
+                                        };
+                                };
+                                i2c1_pins_a: i2c1@0 {
+                                        i2c {
+                                                sirf,pins = "i2c1grp";
+                                                sirf,function = "i2c1";
+                                        };
+                                };
+                                pwm0_pins_a: pwm0@0 {
+                                        pwm {
+                                                sirf,pins = "pwm0grp";
+                                                sirf,function = "pwm0";
+                                        };
+                                };
+                                pwm1_pins_a: pwm1@0 {
+                                        pwm {
+                                                sirf,pins = "pwm1grp";
+                                                sirf,function = "pwm1";
+                                        };
+                                };
+                                pwm2_pins_a: pwm2@0 {
+                                        pwm {
+                                                sirf,pins = "pwm2grp";
+                                                sirf,function = "pwm2";
+                                        };
+                                };
+                                pwm3_pins_a: pwm3@0 {
+                                        pwm {
+                                                sirf,pins = "pwm3grp";
+                                                sirf,function = "pwm3";
+                                        };
+                                };
+                                pwm4_pins_a: pwm4@0 {
+                                        pwm {
+                                                sirf,pins = "pwm4grp";
+                                                sirf,function = "pwm4";
+                                        };
+                                };
+                                gps_pins_a: gps@0 {
+                                        gps {
+                                                sirf,pins = "gpsgrp";
+                                                sirf,function = "gps";
+                                        };
+                                };
+                                vip_pins_a: vip@0 {
+                                        vip {
+                                                sirf,pins = "vipgrp";
+                                                sirf,function = "vip";
+                                        };
+                                };
+                                sdmmc0_pins_a: sdmmc0@0 {
+                                        sdmmc0 {
+                                                sirf,pins = "sdmmc0grp";
+                                                sirf,function = "sdmmc0";
+                                        };
+                                };
+                                sdmmc1_pins_a: sdmmc1@0 {
+                                        sdmmc1 {
+                                                sirf,pins = "sdmmc1grp";
+                                                sirf,function = "sdmmc1";
+                                        };
+                                };
+                                sdmmc2_pins_a: sdmmc2@0 {
+                                        sdmmc2 {
+                                                sirf,pins = "sdmmc2grp";
+                                                sirf,function = "sdmmc2";
+                                        };
+                                };
+                                sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
+                                        sdmmc2_nowp {
+                                                sirf,pins = "sdmmc2_nowpgrp";
+                                                sirf,function = "sdmmc2_nowp";
+                                        };
+                                };
+                                sdmmc3_pins_a: sdmmc3@0 {
+                                        sdmmc3 {
+                                                sirf,pins = "sdmmc3grp";
+                                                sirf,function = "sdmmc3";
+                                        };
+                                };
+                                sdmmc5_pins_a: sdmmc5@0 {
+                                        sdmmc5 {
+                                                sirf,pins = "sdmmc5grp";
+                                                sirf,function = "sdmmc5";
+                                        };
+                                };
+                                i2s_pins_a: i2s@0 {
+                                        i2s {
+                                                sirf,pins = "i2sgrp";
+                                                sirf,function = "i2s";
+                                        };
+                                };
+                                i2s_no_din_pins_a: i2s_no_din@0 {
+                                        i2s_no_din {
+                                                sirf,pins = "i2s_no_dingrp";
+                                                sirf,function = "i2s_no_din";
+                                        };
+                                };
+                                i2s_6chn_pins_a: i2s_6chn@0 {
+                                        i2s_6chn {
+                                                sirf,pins = "i2s_6chngrp";
+                                                sirf,function = "i2s_6chn";
+                                        };
+                                };
+                                ac97_pins_a: ac97@0 {
+                                        ac97 {
+                                                sirf,pins = "ac97grp";
+                                                sirf,function = "ac97";
+                                        };
+                                };
+                                nand_pins_a: nand@0 {
+                                        nand {
+                                                sirf,pins = "nandgrp";
+                                                sirf,function = "nand";
+                                        };
+                                };
+                                usp0_pins_a: usp0@0 {
+                                        usp0 {
+                                                sirf,pins = "usp0grp";
+                                                sirf,function = "usp0";
+                                        };
+                                };
+                                usp1_pins_a: usp1@0 {
+                                        usp1 {
+                                                sirf,pins = "usp1grp";
+                                                sirf,function = "usp1";
+                                        };
+                                };
+                                usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
+                                        usb0_upli_drvbus {
+                                                sirf,pins = "usb0_upli_drvbusgrp";
+                                                sirf,function = "usb0_upli_drvbus";
+                                        };
+                                };
+                                usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
+                                        usb1_utmi_drvbus {
+                                                sirf,pins = "usb1_utmi_drvbusgrp";
+                                                sirf,function = "usb1_utmi_drvbus";
+                                        };
+                                };
+                                warm_rst_pins_a: warm_rst@0 {
+                                        warm_rst {
+                                                sirf,pins = "warm_rstgrp";
+                                                sirf,function = "warm_rst";
+                                        };
+                                };
+                                pulse_count_pins_a: pulse_count@0 {
+                                        pulse_count {
+                                                sirf,pins = "pulse_countgrp";
+                                                sirf,function = "pulse_count";
+                                        };
+                                };
+                                cko0_rst_pins_a: cko0_rst@0 {
+                                        cko0_rst {
+                                                sirf,pins = "cko0_rstgrp";
+                                                sirf,function = "cko0_rst";
+                                        };
+                                };
+                                cko1_rst_pins_a: cko1_rst@0 {
+                                        cko1_rst {
+                                                sirf,pins = "cko1_rstgrp";
+                                                sirf,function = "cko1_rst";
+                                        };
+                                };
+                        };
+
+                        pwm@b0130000 {
+                                compatible = "sirf,prima2-pwm";
+                                reg = <0xb0130000 0x10000>;
+                                clocks = <&clks 21>;
+                        };
+
+                        efusesys@b0140000 {
+                                compatible = "sirf,prima2-efuse";
+                                reg = <0xb0140000 0x10000>;
+                                clocks = <&clks 22>;
+                        };
+
+                        pulsec@b0150000 {
+                                compatible = "sirf,prima2-pulsec";
+                                reg = <0xb0150000 0x10000>;
+                                interrupts = <48>;
+                                clocks = <&clks 23>;
+                        };
+
+                        pci-iobg {
+                                compatible = "sirf,prima2-pciiobg", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0x56000000 0x56000000 0x1b00000>;
+
+                                sd0: sdhci@56000000 {
+                                        cell-index = <0>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56000000 0x100000>;
+                                        interrupts = <38>;
+                                        bus-width = <8>;
+                                        clocks = <&clks 36>;
+                                };
+
+                                sd1: sdhci@56100000 {
+                                        cell-index = <1>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56100000 0x100000>;
+                                        interrupts = <38>;
+                                        status = "disabled";
+                                        clocks = <&clks 36>;
+                                };
+
+                                sd2: sdhci@56200000 {
+                                        cell-index = <2>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56200000 0x100000>;
+                                        interrupts = <23>;
+                                        status = "disabled";
+                                        clocks = <&clks 37>;
+                                };
+
+                                sd3: sdhci@56300000 {
+                                        cell-index = <3>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56300000 0x100000>;
+                                        interrupts = <23>;
+                                        status = "disabled";
+                                        clocks = <&clks 37>;
+                                };
+
+                                sd5: sdhci@56500000 {
+                                        cell-index = <5>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56500000 0x100000>;
+                                        interrupts = <39>;
+                                        status = "disabled";
+                                        clocks = <&clks 38>;
+                                };
+
+                                pci-copy@57900000 {
+                                        compatible = "sirf,prima2-pcicp";
+                                        reg = <0x57900000 0x100000>;
+                                        interrupts = <40>;
+                                };
+
+                                rom-interface@57a00000 {
+                                        compatible = "sirf,prima2-romif";
+                                        reg = <0x57a00000 0x100000>;
+                                };
+                        };
+                };
+
+                rtc-iobg {
+                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x80030000 0x10000>;
+
+                        gpsrtc@1000 {
+                                compatible = "sirf,prima2-gpsrtc";
+                                reg = <0x1000 0x1000>;
+                                interrupts = <55 56 57>;
+                        };
+
+                        sysrtc@2000 {
+                                compatible = "sirf,prima2-sysrtc";
+                                reg = <0x2000 0x1000>;
+                                interrupts = <52 53 54>;
+                        };
+
+                        pwrc@3000 {
+                                compatible = "sirf,prima2-pwrc";
+                                reg = <0x3000 0x1000>;
+                                interrupts = <32>;
+                        };
+                };
+
+                uus-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xb8000000 0xb8000000 0x40000>;
+
+                        usb0: usb@b00e0000 {
+                                compatible = "chipidea,ci13611a-prima2";
+                                reg = <0xb8000000 0x10000>;
+                                interrupts = <10>;
+                                clocks = <&clks 40>;
+                        };
+
+                        usb1: usb@b00f0000 {
+                                compatible = "chipidea,ci13611a-prima2";
+                                reg = <0xb8010000 0x10000>;
+                                interrupts = <11>;
+                                clocks = <&clks 41>;
+                        };
+
+                        security@b00f0000 {
+                                compatible = "sirf,prima2-security";
+                                reg = <0xb8030000 0x10000>;
+                                interrupts = <42>;
+                                clocks = <&clks 7>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index ad135885bd2a..41b2c6c33f09 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -31,6 +31,11 @@
                       <0x3ff00100 0x100>;
         };
 
+        smc@0x3404c000 {
+                compatible = "bcm,bcm11351-smc", "bcm,kona-smc";
+                reg = <0x3404c000 0x400>; //1 KiB in SRAM
+        };
+
         uart@3e000000 {
                 compatible = "bcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
                 status = "disabled";
@@ -47,4 +52,12 @@
                     cache-unified;
                     cache-level = <2>;
         };
+
+        timer@35006000 {
+                compatible = "bcm,kona-timer";
+                reg = <0x35006000 0x1000>;
+                interrupts = <0x0 7 0x4>;
+                clock-frequency = <32768>;
+        };
+
 };
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 7e0481e2441a..f0052dccf9a8 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -34,6 +34,11 @@
                         reg = <0x7e100000 0x28>;
                 };
 
+                rng {
+                        compatible = "brcm,bcm2835-rng";
+                        reg = <0x7e104000 0x10>;
+                };
+
                 uart@20201000 {
                         compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
                         reg = <0x7e201000 0x1000>;
@@ -64,6 +69,16 @@
                         #interrupt-cells = <2>;
                 };
 
+                spi: spi@20204000 {
+                        compatible = "brcm,bcm2835-spi";
+                        reg = <0x7e204000 0x1000>;
+                        interrupts = <2 22>;
+                        clocks = <&clk_spi>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
                 i2c0: i2c@20205000 {
                         compatible = "brcm,bcm2835-i2c";
                         reg = <0x7e205000 0x1000>;
@@ -107,5 +122,12 @@
                         #clock-cells = <0>;
                         clock-frequency = <250000000>;
                 };
+
+                clk_spi: spi {
+                        compatible = "fixed-clock";
+                        reg = <2>;
+                        #clock-cells = <0>;
+                        clock-frequency = <250000000>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi
index 46c098017036..62eceb4f0d3f 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/cros5250-common.dtsi
@@ -24,6 +24,144 @@
                 samsung,i2c-max-bus-freq = <378000>;
                 gpios = <&gpb3 0 2 3 0>,
                         <&gpb3 1 2 3 0>;
+
+                max77686@09 {
+                        compatible = "maxim,max77686";
+                        reg = <0x09>;
+
+                        voltage-regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "P1.0V_LDO_OUT1";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "P1.8V_LDO_OUT2";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "P1.8V_LDO_OUT3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "P1.1V_LDO_OUT7";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo8_reg: LDO8 {
+                                        regulator-name = "P1.0V_LDO_OUT8";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo10_reg: LDO10 {
+                                        regulator-name = "P1.8V_LDO_OUT10";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo12_reg: LDO12 {
+                                        regulator-name = "P3.0V_LDO_OUT12";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "P1.8V_LDO_OUT14";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo15_reg: LDO15 {
+                                        regulator-name = "P1.0V_LDO_OUT15";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo16_reg: LDO16 {
+                                        regulator-name = "P1.8V_LDO_OUT16";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "vdd_mif";
+                                        regulator-min-microvolt = <950000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "vdd_arm";
+                                        regulator-min-microvolt = <850000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "vdd_int";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck4_reg: BUCK4 {
+                                        regulator-name = "vdd_g3d";
+                                        regulator-min-microvolt = <850000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "P1.8V_BUCK_OUT5";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck6_reg: BUCK6 {
+                                        regulator-name = "P1.35V_BUCK_OUT6";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                };
+
+                                buck7_reg: BUCK7 {
+                                        regulator-name = "P2.0V_BUCK_OUT7";
+                                        regulator-min-microvolt = <2000000>;
+                                        regulator-max-microvolt = <2000000>;
+                                        regulator-always-on;
+                                };
+
+                                buck8_reg: BUCK8 {
+                                        regulator-name = "P2.85V_BUCK_OUT8";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
         };
 
         i2c@12C70000 {
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index f712fb607a42..c5834a6c5bf4 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -35,14 +35,84 @@
                         clock-frequency = <100000>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&i2c0_pins>;
+
+                        tps: tps@48 {
+                                reg = <0x48>;
+                        };
                 };
                 wdt: wdt@1c21000 {
                         status = "okay";
                 };
+                mmc0: mmc@1c40000 {
+                        max-frequency = <50000000>;
+                        bus-width = <4>;
+                        status = "okay";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins>;
+                };
         };
         nand_cs3@62000000 {
                 status = "okay";
                 pinctrl-names = "default";
                 pinctrl-0 = <&nand_cs3_pins>;
         };
+        vbat: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vbat";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+        };
+};
+
+/include/ "tps6507x.dtsi"
+
+&tps {
+        vdcdc1_2-supply = <&vbat>;
+        vdcdc3-supply = <&vbat>;
+        vldo1_2-supply = <&vbat>;
+
+        regulators {
+                vdcdc1_reg: regulator@0 {
+                        regulator-name = "VDCDC1_3.3V";
+                        regulator-min-microvolt = <3150000>;
+                        regulator-max-microvolt = <3450000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+
+                vdcdc2_reg: regulator@1 {
+                        regulator-name = "VDCDC2_3.3V";
+                        regulator-min-microvolt = <1710000>;
+                        regulator-max-microvolt = <3450000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        ti,defdcdc_default = <1>;
+                };
+
+                vdcdc3_reg: regulator@2 {
+                        regulator-name = "VDCDC3_1.2V";
+                        regulator-min-microvolt = <950000>;
+                        regulator-max-microvolt = <1350000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        ti,defdcdc_default = <1>;
+                };
+
+                ldo1_reg: regulator@3 {
+                        regulator-name = "LDO1_1.8V";
+                        regulator-min-microvolt = <1710000>;
+                        regulator-max-microvolt = <1890000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+
+                ldo2_reg: regulator@4 {
+                        regulator-name = "LDO2_1.2V";
+                        regulator-min-microvolt = <1140000>;
+                        regulator-max-microvolt = <1320000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 3ec1bda64356..3ade343f13cc 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -62,6 +62,15 @@
                                         0x10 0x00002200 0x0000ff00
                                 >;
                         };
+                        mmc0_pins: pinmux_mmc_pins {
+                                pinctrl-single,bits = <
+                                        /* MMCSD0_DAT[3] MMCSD0_DAT[2]
+                                         * MMCSD0_DAT[1] MMCSD0_DAT[0]
+                                         * MMCSD0_CMD    MMCSD0_CLK
+                                         */
+                                        0x28 0x00222222  0x00ffffff
+                                >;
+                        };
                 };
                 serial0: serial@1c42000 {
                         compatible = "ns16550a";
@@ -107,6 +116,12 @@
                         reg = <0x21000 0x1000>;
                         status = "disabled";
                 };
+                mmc0: mmc@1c40000 {
+                        compatible = "ti,da830-mmc";
+                        reg = <0x40000 0x1000>;
+                        interrupts = <16>;
+                        status = "disabled";
+                };
         };
         nand_cs3@62000000 {
                 compatible = "ti,davinci-nand";
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index aaa63d0a8096..b6bc4ff17f26 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -191,7 +191,7 @@
 
                 prcmu: prcmu@80157000 {
                         compatible = "stericsson,db8500-prcmu";
-                        reg = <0x80157000 0x1000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
+                        reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
                         reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
                         interrupts = <0 47 0x4>;
                         #address-cells = <1>;
@@ -674,10 +674,13 @@
                         compatible = "regulator-gpio";
 
                         regulator-min-microvolt = <1800000>;
-                        regulator-max-microvolt = <2600000>;
+                        regulator-max-microvolt = <2900000>;
                         regulator-name = "mmci-reg";
                         regulator-type = "voltage";
 
+                        startup-delay-us = <100>;
+                        enable-active-high;
+
                         states = <1800000 0x1
                                   2900000 0x0>;
 
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index f7509cafc377..6cab46849cdb 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -50,6 +50,11 @@
                         #clock-cells = <1>;
                 };
 
+                thermal: thermal@d001c {
+                        compatible = "marvell,dove-thermal";
+                        reg = <0xd001c 0x0c>, <0xd005c 0x08>;
+                };
+
                 uart0: serial@12000 {
                         compatible = "ns16550a";
                         reg = <0x12000 0x100>;
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 1a62bcf18aa3..9ac47d51c407 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -86,6 +86,8 @@
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x10060000 0x100>;
                 interrupts = <0 43 0>;
+                clocks = <&clock 345>;
+                clock-names = "watchdog";
                 status = "disabled";
         };
 
@@ -93,6 +95,8 @@
                 compatible = "samsung,s3c6410-rtc";
                 reg = <0x10070000 0x100>;
                 interrupts = <0 44 0>, <0 45 0>;
+                clocks = <&clock 346>;
+                clock-names = "rtc";
                 status = "disabled";
         };
 
@@ -100,6 +104,8 @@
                 compatible = "samsung,s5pv210-keypad";
                 reg = <0x100A0000 0x100>;
                 interrupts = <0 109 0>;
+                clocks = <&clock 347>;
+                clock-names = "keypad";
                 status = "disabled";
         };
 
@@ -107,6 +113,8 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12510000 0x100>;
                 interrupts = <0 73 0>;
+                clocks = <&clock 297>, <&clock 145>;
+                clock-names = "hsmmc", "mmc_busclk.2";
                 status = "disabled";
         };
 
@@ -114,6 +122,8 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12520000 0x100>;
                 interrupts = <0 74 0>;
+                clocks = <&clock 298>, <&clock 146>;
+                clock-names = "hsmmc", "mmc_busclk.2";
                 status = "disabled";
         };
 
@@ -121,6 +131,8 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12530000 0x100>;
                 interrupts = <0 75 0>;
+                clocks = <&clock 299>, <&clock 147>;
+                clock-names = "hsmmc", "mmc_busclk.2";
                 status = "disabled";
         };
 
@@ -128,6 +140,16 @@
                 compatible = "samsung,exynos4210-sdhci";
                 reg = <0x12540000 0x100>;
                 interrupts = <0 76 0>;
+                clocks = <&clock 300>, <&clock 148>;
+                clock-names = "hsmmc", "mmc_busclk.2";
+                status = "disabled";
+        };
+
+        mfc: codec@13400000 {
+                compatible = "samsung,mfc-v5";
+                reg = <0x13400000 0x10000>;
+                interrupts = <0 94 0>;
+                samsung,power-domain = <&pd_mfc>;
                 status = "disabled";
         };
 
@@ -135,6 +157,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13800000 0x100>;
                 interrupts = <0 52 0>;
+                clocks = <&clock 312>, <&clock 151>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -142,6 +166,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13810000 0x100>;
                 interrupts = <0 53 0>;
+                clocks = <&clock 313>, <&clock 152>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -149,6 +175,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13820000 0x100>;
                 interrupts = <0 54 0>;
+                clocks = <&clock 314>, <&clock 153>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -156,6 +184,8 @@
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x13830000 0x100>;
                 interrupts = <0 55 0>;
+                clocks = <&clock 315>, <&clock 154>;
+                clock-names = "uart", "clk_uart_baud0";
                 status = "disabled";
         };
 
@@ -165,6 +195,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13860000 0x100>;
                 interrupts = <0 58 0>;
+                clocks = <&clock 317>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -174,6 +206,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13870000 0x100>;
                 interrupts = <0 59 0>;
+                clocks = <&clock 318>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -183,6 +217,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13880000 0x100>;
                 interrupts = <0 60 0>;
+                clocks = <&clock 319>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -192,6 +228,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x13890000 0x100>;
                 interrupts = <0 61 0>;
+                clocks = <&clock 320>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -201,6 +239,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138A0000 0x100>;
                 interrupts = <0 62 0>;
+                clocks = <&clock 321>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -210,6 +250,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138B0000 0x100>;
                 interrupts = <0 63 0>;
+                clocks = <&clock 322>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -219,6 +261,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138C0000 0x100>;
                 interrupts = <0 64 0>;
+                clocks = <&clock 323>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -228,6 +272,8 @@
                 compatible = "samsung,s3c2440-i2c";
                 reg = <0x138D0000 0x100>;
                 interrupts = <0 65 0>;
+                clocks = <&clock 324>;
+                clock-names = "i2c";
                 status = "disabled";
         };
 
@@ -239,6 +285,8 @@
                 rx-dma-channel = <&pdma0 6>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 327>, <&clock 159>;
+                clock-names = "spi", "spi_busclk0";
                 status = "disabled";
         };
 
@@ -250,6 +298,8 @@
                 rx-dma-channel = <&pdma1 6>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 328>, <&clock 160>;
+                clock-names = "spi", "spi_busclk0";
                 status = "disabled";
         };
 
@@ -261,6 +311,8 @@
                 rx-dma-channel = <&pdma0 8>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 329>, <&clock 161>;
+                clock-names = "spi", "spi_busclk0";
                 status = "disabled";
         };
 
@@ -275,6 +327,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x12680000 0x1000>;
                         interrupts = <0 35 0>;
+                        clocks = <&clock 292>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -284,6 +338,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x12690000 0x1000>;
                         interrupts = <0 36 0>;
+                        clocks = <&clock 293>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -293,6 +349,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x12850000 0x1000>;
                         interrupts = <0 34 0>;
+                        clocks = <&clock 279>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <1>;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index f2710018e84e..1b30bc8e2654 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -57,6 +57,12 @@
                 status = "okay";
         };
 
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+                status = "okay";
+        };
+
         serial@13800000 {
                 status = "okay";
         };
@@ -121,4 +127,16 @@
                         linux,default-trigger = "heartbeat";
                 };
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index f63490707f3a..f52c86e2d424 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -43,6 +43,12 @@
                 status = "okay";
         };
 
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+                status = "okay";
+        };
+
         serial@13800000 {
                 status = "okay";
         };
@@ -189,4 +195,16 @@
                         };
                 };
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <12000000>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index c346b64dff55..9a14484c7bb1 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -289,4 +289,16 @@
                         };
                 };
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 2feffc70814c..15143bdbafb8 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -47,6 +47,42 @@
                              <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
         };
 
+        mct@10050000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+                clocks = <&clock 3>, <&clock 344>;
+                clock-names = "fin_pll", "mct";
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &gic 0 57 0>,
+                                        <0x1 0 &gic 0 69 0>,
+                                        <0x2 0 &combiner 12 6>,
+                                        <0x3 0 &combiner 12 7>,
+                                        <0x4 0 &gic 0 42 0>,
+                                        <0x5 0 &gic 0 48 0>;
+                };
+        };
+
+        clock: clock-controller@0x10030000 {
+                compatible = "samsung,exynos4210-clock";
+                reg = <0x10030000 0x20000>;
+                #clock-cells = <1>;
+        };
+
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupt-parent = <&combiner>;
+                interrupts = <2 2>, <3 2>;
+        };
+
         pinctrl_0: pinctrl@11400000 {
                 compatible = "samsung,exynos4210-pinctrl";
                 reg = <0x11400000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index c6ae2005961f..36d4299789ef 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -25,4 +25,26 @@
         gic:interrupt-controller@10490000 {
                 cpu-offset = <0x8000>;
         };
+
+        mct@10050000 {
+                compatible = "samsung,exynos4412-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &gic 0 57 0>,
+                                        <0x1 0 &combiner 12 5>,
+                                        <0x2 0 &combiner 12 6>,
+                                        <0x3 0 &combiner 12 7>,
+                                        <0x4 0 &gic 1 12 0>,
+                                        <0x5 0 &gic 1 12 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
new file mode 100644
index 000000000000..53bc8bf77984
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -0,0 +1,111 @@
+/*
+ * Hardkernel's Exynos4412 based ODROID-X board device tree source
+ *
+ * Copyright (c) 2012 Dongjin Kim <tobetter@gmail.com>
+ *
+ * Device tree source file for Hardkernel's ODROID-X board which is based on
+ * Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4412.dtsi"
+
+/ {
+        model = "Hardkernel ODROID-X board based on Exynos4412";
+        compatible = "hardkernel,odroid-x", "samsung,exynos4412";
+
+        memory {
+                reg = <0x40000000 0x40000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led1 {
+                        label = "led1:heart";
+                        gpios = <&gpc1 0 1>;
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
+                };
+                led2 {
+                        label = "led2:mmc0";
+                        gpios = <&gpc1 2 1>;
+                        default-state = "on";
+                        linux,default-trigger = "mmc0";
+                };
+        };
+
+        mshc@12550000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                };
+        };
+
+        regulator_p3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "p3v3_en";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpa1 1 1>;
+                enable-active-high;
+                regulator-boot-on;
+        };
+
+        rtc@10070000 {
+                status = "okay";
+        };
+
+        sdhci@12530000 {
+                bus-width = <4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+                pinctrl-names = "default";
+                status = "okay";
+        };
+
+        serial@13800000 {
+                status = "okay";
+        };
+
+        serial@13810000 {
+                status = "okay";
+        };
+
+        serial@13820000 {
+                status = "okay";
+        };
+
+        serial@13830000 {
+                status = "okay";
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
new file mode 100644
index 000000000000..1fecf7666dc0
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -0,0 +1,432 @@
+/*
+ * Insignal's Exynos4412 based Origen board device tree source
+ *
+ * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Device tree source file for Insignal's Origen board which is based on
+ * Samsung's Exynos4412 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos4412.dtsi"
+
+/ {
+        model = "Insignal Origen evaluation board based on Exynos4412";
+        compatible = "insignal,origen4412", "samsung,exynos4412";
+
+        memory {
+                reg = <0x40000000 0x40000000>;
+        };
+
+        chosen {
+                bootargs ="console=ttySAC2,115200";
+        };
+
+        mmc_reg: voltage-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "VMEM_VDD_2.8V";
+                regulator-min-microvolt = <2800000>;
+                regulator-max-microvolt = <2800000>;
+                gpio = <&gpx1 1 0>;
+                enable-active-high;
+        };
+
+        sdhci@12530000 {
+                bus-width = <4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
+                pinctrl-names = "default";
+                vmmc-supply = <&mmc_reg>;
+                status = "okay";
+        };
+
+        mshc@12550000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                };
+        };
+
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+                status = "okay";
+        };
+
+        serial@13800000 {
+                status = "okay";
+        };
+
+        serial@13810000 {
+                status = "okay";
+        };
+
+        serial@13820000 {
+                status = "okay";
+        };
+
+        serial@13830000 {
+                status = "okay";
+        };
+
+        i2c@13860000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <20000>;
+                pinctrl-0 = <&i2c0_bus>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                s5m8767_pmic@66 {
+                        compatible = "samsung,s5m8767-pmic";
+                        reg = <0x66>;
+
+                        s5m8767,pmic-buck-default-dvs-idx = <3>;
+
+                        s5m8767,pmic-buck-dvs-gpios = <&gpx2 3 0>,
+                                                         <&gpx2 4 0>,
+                                                         <&gpx2 5 0>;
+
+                        s5m8767,pmic-buck-ds-gpios = <&gpm3 5 0>,
+                                                        <&gpm3 6 0>,
+                                                        <&gpm3 7 0>;
+
+                        s5m8767,pmic-buck2-dvs-voltage = <1250000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>;
+
+                        s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,
+                                                         <1100000>, <1100000>,
+                                                         <1100000>, <1100000>,
+                                                         <1100000>, <1100000>;
+
+                        s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>,
+                                                         <1200000>, <1200000>;
+
+                        regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "VDD_ALIVE";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "VDDQ_M12";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "VDDIOAP_18";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo4_reg: LDO4 {
+                                        regulator-name = "VDDQ_PRE";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo5_reg: LDO5 {
+                                        regulator-name = "VDD18_2M";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo6_reg: LDO6 {
+                                        regulator-name = "VDD10_MPLL";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "VDD10_XPLL";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo8_reg: LDO8 {
+                                        regulator-name = "VDD10_MIPI";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo9_reg: LDO9 {
+                                        regulator-name = "VDD33_LCD";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo10_reg: LDO10 {
+                                        regulator-name = "VDD18_MIPI";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo11_reg: LDO11 {
+                                        regulator-name = "VDD18_ABB1";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo12_reg: LDO12 {
+                                        regulator-name = "VDD33_UOTG";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo13_reg: LDO13 {
+                                        regulator-name = "VDDIOPERI_18";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "VDD18_ABB02";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo15_reg: LDO15 {
+                                        regulator-name = "VDD10_USH";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo16_reg: LDO16 {
+                                        regulator-name = "VDD18_HSIC";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo17_reg: LDO17 {
+                                        regulator-name = "VDDIOAP_MMC012_28";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo18_reg: LDO18 {
+                                        regulator-name = "VDDIOPERI_28";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo19_reg: LDO19 {
+                                        regulator-name = "DVDD25";
+                                        regulator-min-microvolt = <2500000>;
+                                        regulator-max-microvolt = <2500000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo20_reg: LDO20 {
+                                        regulator-name = "VDD28_CAM";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo21_reg: LDO21 {
+                                        regulator-name = "VDD28_AF";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo22_reg: LDO22 {
+                                        regulator-name = "VDDA28_2M";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo23_reg: LDO23 {
+                                        regulator-name = "VDD28_TF";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo24_reg: LDO24 {
+                                        regulator-name = "VDD33_A31";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo25_reg: LDO25 {
+                                        regulator-name = "VDD18_CAM";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo26_reg: LDO26 {
+                                        regulator-name = "VDD18_A31";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo27_reg: LDO27 {
+                                        regulator-name = "GPS_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                ldo28_reg: LDO28 {
+                                        regulator-name = "DVDD12";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "vdd_mif";
+                                        regulator-min-microvolt = <950000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "vdd_arm";
+                                        regulator-min-microvolt = <925000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "vdd_int";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck4_reg: BUCK4 {
+                                        regulator-name = "vdd_g3d";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "vdd_m12";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck6_reg: BUCK6 {
+                                        regulator-name = "vdd12_5m";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+
+                                buck9_reg: BUCK9 {
+                                        regulator-name = "vddf28_emmc";
+                                        regulator-min-microvolt = <750000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        op_mode = <1>; /* Normal Mode */
+                                };
+                        };
+                };
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index f05bf575cc45..874beeaef99d 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -27,6 +27,19 @@
                 bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
         };
 
+        sdhci@12530000 {
+                bus-width = <4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
+                pinctrl-names = "default";
+                status = "okay";
+        };
+
+        codec@13400000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+                status = "okay";
+        };
+
         serial@13800000 {
                 status = "okay";
         };
@@ -42,4 +55,16 @@
         serial@13830000 {
                 status = "okay";
         };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index d7dfe312772a..d75c047e80a9 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -25,4 +25,30 @@
         gic:interrupt-controller@10490000 {
                 cpu-offset = <0x4000>;
         };
+
+        mct@10050000 {
+                compatible = "samsung,exynos4412-mct";
+                reg = <0x10050000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>, <6 0>, <7 0>;
+                clocks = <&clock 3>, <&clock 344>;
+                clock-names = "fin_pll", "mct";
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &gic 0 57 0>,
+                                        <0x1 0 &combiner 12 5>,
+                                        <0x2 0 &combiner 12 6>,
+                                        <0x3 0 &combiner 12 7>,
+                                        <0x4 0 &gic 1 12 0>,
+                                        <0x5 0 &gic 1 12 0>,
+                                        <0x6 0 &gic 1 12 0>,
+                                        <0x7 0 &gic 1 12 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 9a8780694909..7496b8d633ea 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -36,6 +36,12 @@
                              <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
         };
 
+        clock: clock-controller@0x10030000 {
+                compatible = "samsung,exynos4412-clock";
+                reg = <0x10030000 0x20000>;
+                #clock-cells = <1>;
+        };
+
         pinctrl_0: pinctrl@11400000 {
                 compatible = "samsung,exynos4x12-pinctrl";
                 reg = <0x11400000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
new file mode 100644
index 000000000000..5de019cb0e58
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -0,0 +1,129 @@
+/*
+ * Samsung's Exynos5250 based Arndale board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ "exynos5250.dtsi"
+
+/ {
+        model = "Insignal Arndale evaluation board based on EXYNOS5250";
+        compatible = "insignal,arndale", "samsung,exynos5250";
+
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttySAC2,115200";
+        };
+
+        i2c@12C60000 {
+                status = "disabled";
+        };
+
+        i2c@12C70000 {
+                status = "disabled";
+        };
+
+        i2c@12C80000 {
+                status = "disabled";
+        };
+
+        i2c@12C90000 {
+                status = "disabled";
+        };
+
+        i2c@12CA0000 {
+                status = "disabled";
+        };
+
+        i2c@12CB0000 {
+                status = "disabled";
+        };
+
+        i2c@12CC0000 {
+                status = "disabled";
+        };
+
+        i2c@12CD0000 {
+                status = "disabled";
+        };
+
+        i2c@121D0000 {
+                status = "disabled";
+        };
+
+        dwmmc_0: dwmmc0@12200000 {
+                num-slots = <1>;
+                supports-highspeed;
+                broken-cd;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <8>;
+                        gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
+                                <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
+                                <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>,
+                                <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
+                                <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>;
+                };
+        };
+
+        dwmmc_1: dwmmc1@12210000 {
+                status = "disabled";
+        };
+
+        dwmmc_2: dwmmc2@12220000 {
+                num-slots = <1>;
+                supports-highspeed;
+                fifo-depth = <0x80>;
+                card-detect-delay = <200>;
+                samsung,dw-mshc-ciu-div = <3>;
+                samsung,dw-mshc-sdr-timing = <2 3>;
+                samsung,dw-mshc-ddr-timing = <1 2>;
+
+                slot@0 {
+                        reg = <0>;
+                        bus-width = <4>;
+                        samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
+                        gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
+                                <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
+                                <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
+                };
+        };
+
+        dwmmc_3: dwmmc3@12230000 {
+                status = "disabled";
+        };
+
+        spi_0: spi@12d20000 {
+                status = "disabled";
+        };
+
+        spi_1: spi@12d30000 {
+                status = "disabled";
+        };
+
+        spi_2: spi@12d40000 {
+                status = "disabled";
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 1b8d4106d338..872ae1f93c75 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -231,4 +231,24 @@
                 samsung,i2s-controller = <&i2s0>;
                 samsung,audio-codec = <&wm8994>;
         };
+
+        usb@12110000 {
+                samsung,vbus-gpio = <&gpx2 6 1 3 3>;
+        };
+
+        dp-controller {
+                samsung,color-space = <0>;
+                samsung,dynamic-range = <0>;
+                samsung,ycbcr-coeff = <0>;
+                samsung,color-depth = <1>;
+                samsung,link-rate = <0x0a>;
+                samsung,lane-count = <4>;
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 17dd951c1cd2..babd9f9b1bf9 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -40,4 +40,15 @@
                                 <&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
                 };
         };
+
+        usb@12110000 {
+                samsung,vbus-gpio = <&gpx1 1 1 3 3>;
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti";
+                        clock-frequency = <24000000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index b1ac73e21c80..28758e5dd15c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -46,6 +46,22 @@
                 i2c8 = &i2c_8;
         };
 
+        pd_gsc: gsc-power-domain@0x10044000 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10044000 0x20>;
+        };
+
+        pd_mfc: mfc-power-domain@0x10044040 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10044040 0x20>;
+        };
+
+        clock: clock-controller@0x10010000 {
+                compatible = "samsung,exynos5250-clock";
+                reg = <0x10010000 0x30000>;
+                #clock-cells = <1>;
+        };
+
         gic:interrupt-controller@10481000 {
                 compatible = "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
@@ -69,58 +85,106 @@
                              <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
         };
 
+        mct@101C0000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x101C0000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <2>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                             <4 0>, <5 0>;
+                clocks = <&clock 1>, <&clock 335>;
+                clock-names = "fin_pll", "mct";
+
+                mct_map: mct-map {
+                        #interrupt-cells = <2>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0x0 0 &combiner 23 3>,
+                                        <0x1 0 &combiner 23 4>,
+                                        <0x2 0 &combiner 25 2>,
+                                        <0x3 0 &combiner 25 3>,
+                                        <0x4 0 &gic 0 120 0>,
+                                        <0x5 0 &gic 0 121 0>;
+                };
+        };
+
+        pmu {
+                compatible = "arm,cortex-a15-pmu";
+                interrupt-parent = <&combiner>;
+                interrupts = <1 2>, <22 4>;
+        };
+
         watchdog {
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x101D0000 0x100>;
                 interrupts = <0 42 0>;
+                clocks = <&clock 336>;
+                clock-names = "watchdog";
         };
 
         codec@11000000 {
                 compatible = "samsung,mfc-v6";
                 reg = <0x11000000 0x10000>;
                 interrupts = <0 96 0>;
+                samsung,power-domain = <&pd_mfc>;
         };
 
         rtc {
                 compatible = "samsung,s3c6410-rtc";
                 reg = <0x101E0000 0x100>;
                 interrupts = <0 43 0>, <0 44 0>;
+                clocks = <&clock 337>;
+                clock-names = "rtc";
+                status = "disabled";
         };
 
         tmu@10060000 {
                 compatible = "samsung,exynos5250-tmu";
                 reg = <0x10060000 0x100>;
                 interrupts = <0 65 0>;
+                clocks = <&clock 338>;
+                clock-names = "tmu_apbif";
         };
 
         serial@12C00000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C00000 0x100>;
                 interrupts = <0 51 0>;
+                clocks = <&clock 289>, <&clock 146>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@12C10000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C10000 0x100>;
                 interrupts = <0 52 0>;
+                clocks = <&clock 290>, <&clock 147>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@12C20000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C20000 0x100>;
                 interrupts = <0 53 0>;
+                clocks = <&clock 291>, <&clock 148>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@12C30000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0x12C30000 0x100>;
                 interrupts = <0 54 0>;
+                clocks = <&clock 292>, <&clock 149>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         sata@122F0000 {
                 compatible = "samsung,exynos5-sata-ahci";
                 reg = <0x122F0000 0x1ff>;
                 interrupts = <0 115 0>;
+                clocks = <&clock 277>, <&clock 143>;
+                clock-names = "sata", "sclk_sata";
         };
 
         sata-phy@12170000 {
@@ -134,6 +198,8 @@
                 interrupts = <0 56 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 294>;
+                clock-names = "i2c";
         };
 
         i2c_1: i2c@12C70000 {
@@ -142,6 +208,8 @@
                 interrupts = <0 57 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 295>;
+                clock-names = "i2c";
         };
 
         i2c_2: i2c@12C80000 {
@@ -150,6 +218,8 @@
                 interrupts = <0 58 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 296>;
+                clock-names = "i2c";
         };
 
         i2c_3: i2c@12C90000 {
@@ -158,6 +228,8 @@
                 interrupts = <0 59 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 297>;
+                clock-names = "i2c";
         };
 
         i2c_4: i2c@12CA0000 {
@@ -166,6 +238,8 @@
                 interrupts = <0 60 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 298>;
+                clock-names = "i2c";
         };
 
         i2c_5: i2c@12CB0000 {
@@ -174,6 +248,8 @@
                 interrupts = <0 61 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 299>;
+                clock-names = "i2c";
         };
 
         i2c_6: i2c@12CC0000 {
@@ -182,6 +258,8 @@
                 interrupts = <0 62 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 300>;
+                clock-names = "i2c";
         };
 
         i2c_7: i2c@12CD0000 {
@@ -190,6 +268,8 @@
                 interrupts = <0 63 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 301>;
+                clock-names = "i2c";
         };
 
         i2c_8: i2c@12CE0000 {
@@ -198,6 +278,8 @@
                 interrupts = <0 64 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 302>;
+                clock-names = "i2c";
         };
 
         i2c@121D0000 {
@@ -205,6 +287,8 @@
                 reg = <0x121D0000 0x100>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 288>;
+                clock-names = "i2c";
         };
 
         spi_0: spi@12d20000 {
@@ -216,6 +300,8 @@
                 dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 304>, <&clock 154>;
+                clock-names = "spi", "spi_busclk0";
         };
 
         spi_1: spi@12d30000 {
@@ -227,6 +313,8 @@
                 dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 305>, <&clock 155>;
+                clock-names = "spi", "spi_busclk0";
         };
 
         spi_2: spi@12d40000 {
@@ -238,6 +326,8 @@
                 dma-names = "tx", "rx";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 306>, <&clock 156>;
+                clock-names = "spi", "spi_busclk0";
         };
 
         dwmmc_0: dwmmc0@12200000 {
@@ -246,6 +336,8 @@
                 interrupts = <0 75 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 280>, <&clock 139>;
+                clock-names = "biu", "ciu";
         };
 
         dwmmc_1: dwmmc1@12210000 {
@@ -254,6 +346,8 @@
                 interrupts = <0 76 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 281>, <&clock 140>;
+                clock-names = "biu", "ciu";
         };
 
         dwmmc_2: dwmmc2@12220000 {
@@ -262,6 +356,8 @@
                 interrupts = <0 77 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 282>, <&clock 141>;
+                clock-names = "biu", "ciu";
         };
 
         dwmmc_3: dwmmc3@12230000 {
@@ -270,6 +366,8 @@
                 interrupts = <0 78 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 283>, <&clock 142>;
+                clock-names = "biu", "ciu";
         };
 
         i2s0: i2s@03830000 {
@@ -301,6 +399,18 @@
                 dma-names = "tx", "rx";
         };
 
+        usb@12110000 {
+                compatible = "samsung,exynos4210-ehci";
+                reg = <0x12110000 0x100>;
+                interrupts = <0 71 0>;
+        };
+
+        usb@12120000 {
+                compatible = "samsung,exynos4210-ohci";
+                reg = <0x12120000 0x100>;
+                interrupts = <0 71 0>;
+        };
+
         amba {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -312,6 +422,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x121A0000 0x1000>;
                         interrupts = <0 34 0>;
+                        clocks = <&clock 275>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -321,6 +433,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x121B0000 0x1000>;
                         interrupts = <0 35 0>;
+                        clocks = <&clock 276>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -330,6 +444,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x10800000 0x1000>;
                         interrupts = <0 33 0>;
+                        clocks = <&clock 271>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <1>;
@@ -339,6 +455,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x11C10000 0x1000>;
                         interrupts = <0 124 0>;
+                        clocks = <&clock 271>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <1>;
@@ -592,34 +710,51 @@
                 };
         };
 
+
         gsc_0:  gsc@0x13e00000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e00000 0x1000>;
                 interrupts = <0 85 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 256>;
+                clock-names = "gscl";
         };
 
         gsc_1:  gsc@0x13e10000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e10000 0x1000>;
                 interrupts = <0 86 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 257>;
+                clock-names = "gscl";
         };
 
         gsc_2:  gsc@0x13e20000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e20000 0x1000>;
                 interrupts = <0 87 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 258>;
+                clock-names = "gscl";
         };
 
         gsc_3:  gsc@0x13e30000 {
                 compatible = "samsung,exynos5-gsc";
                 reg = <0x13e30000 0x1000>;
                 interrupts = <0 88 0>;
+                samsung,power-domain = <&pd_gsc>;
+                clocks = <&clock 259>;
+                clock-names = "gscl";
         };
 
         hdmi {
                 compatible = "samsung,exynos5-hdmi";
                 reg = <0x14530000 0x70000>;
                 interrupts = <0 95 0>;
+                clocks = <&clock 333>, <&clock 136>, <&clock 137>,
+                                <&clock 333>, <&clock 333>;
+                clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
+                                "sclk_hdmiphy", "hdmiphy";
         };
 
         mixer {
@@ -627,4 +762,18 @@
                 reg = <0x14450000 0x10000>;
                 interrupts = <0 94 0>;
         };
+
+        dp-controller {
+                compatible = "samsung,exynos5-dp";
+                reg = <0x145b0000 0x1000>;
+                interrupts = <10 3>;
+                interrupt-parent = <&combiner>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                dptx-phy {
+                        reg = <0x10040720>;
+                        samsung,enable-mask = <1>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index 81e2c964a900..a21eb4cbe893 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -28,19 +28,10 @@
                 status = "disabled";
         };
 
-        i2c@F0000 {
-                status = "disabled";
-        };
-
-        i2c@100000 {
-                status = "disabled";
-        };
-
-        watchdog {
-                status = "disabled";
-        };
-
-        rtc {
-                status = "disabled";
+        fixed-rate-clocks {
+                xtal {
+                        compatible = "samsung,clock-xtal";
+                        clock-frequency = <50000000>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 9a99755920c0..48cc96aa0b5f 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -16,6 +16,12 @@
 
         interrupt-parent = <&gic>;
 
+        clock: clock-controller@0x160000 {
+                compatible = "samsung,exynos5440-clock";
+                reg = <0x160000 0x1000>;
+                #clock-cells = <1>;
+        };
+
         gic:interrupt-controller@2E0000 {
                 compatible = "arm,cortex-a15-gic";
                 #interrupt-cells = <3>;
@@ -24,55 +30,51 @@
         };
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
                 cpu@0 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 13 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <0>;
                 };
                 cpu@1 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 14 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <1>;
                 };
                 cpu@2 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 14 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <2>;
                 };
                 cpu@3 {
                         compatible = "arm,cortex-a15";
-                        timer {
-                                compatible = "arm,armv7-timer";
-                                interrupts = <1 14 0xf08>;
-                                clock-frequency = <1000000>;
-                        };
+                        reg = <3>;
                 };
         };
 
-        common {
-                compatible = "samsung,exynos5440";
-
+        timer {
+                compatible = "arm,cortex-a15-timer",
+                             "arm,armv7-timer";
+                interrupts = <1 13 0xf08>,
+                             <1 14 0xf08>,
+                             <1 11 0xf08>,
+                             <1 10 0xf08>;
+                clock-frequency = <50000000>;
         };
 
         serial@B0000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0xB0000 0x1000>;
                 interrupts = <0 2 0>;
+                clocks = <&clock 21>, <&clock 21>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@C0000 {
                 compatible = "samsung,exynos4210-uart";
                 reg = <0xC0000 0x1000>;
                 interrupts = <0 3 0>;
+                clocks = <&clock 21>, <&clock 21>;
+                clock-names = "uart", "clk_uart_baud0";
         };
 
         spi {
@@ -83,6 +85,8 @@
                 rx-dma-channel = <&pdma0 4>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 21>, <&clock 16>;
+                clock-names = "spi", "spi_busclk0";
         };
 
         pinctrl {
@@ -110,25 +114,31 @@
         };
 
         i2c@F0000 {
-                compatible = "samsung,s3c2440-i2c";
+                compatible = "samsung,exynos5440-i2c";
                 reg = <0xF0000 0x1000>;
                 interrupts = <0 5 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 21>;
+                clock-names = "i2c";
         };
 
         i2c@100000 {
-                compatible = "samsung,s3c2440-i2c";
+                compatible = "samsung,exynos5440-i2c";
                 reg = <0x100000 0x1000>;
                 interrupts = <0 6 0>;
                 #address-cells = <1>;
                 #size-cells = <0>;
+                clocks = <&clock 21>;
+                clock-names = "i2c";
         };
 
         watchdog {
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x110000 0x1000>;
                 interrupts = <0 1 0>;
+                clocks = <&clock 21>;
+                clock-names = "watchdog";
         };
 
         amba {
@@ -142,6 +152,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x120000 0x1000>;
                         interrupts = <0 34 0>;
+                        clocks = <&clock 21>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -151,6 +163,8 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x121000 0x1000>;
                         interrupts = <0 35 0>;
+                        clocks = <&clock 21>;
+                        clock-names = "apb_pclk";
                         #dma-cells = <1>;
                         #dma-channels = <8>;
                         #dma-requests = <32>;
@@ -161,5 +175,8 @@
                 compatible = "samsung,s3c6410-rtc";
                 reg = <0x130000 0x1000>;
                 interrupts = <0 17 0>, <0 16 0>;
+                clocks = <&clock 21>;
+                clock-names = "rtc";
+                status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi
index 379128eb9d98..c0bc426952ea 100644
--- a/arch/arm/boot/dts/href.dtsi
+++ b/arch/arm/boot/dts/href.dtsi
@@ -87,6 +87,7 @@
                         mmc-cap-sd-highspeed;
                         mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux3_reg>;
+                        vqmmc-supply = <&vmmci>;
 
                         cd-gpios  = <&tc3589x_gpio 3 0x4>;
 
diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts
index eec29c4a86dc..c2d274815923 100644
--- a/arch/arm/boot/dts/hrefprev60.dts
+++ b/arch/arm/boot/dts/hrefprev60.dts
@@ -25,6 +25,14 @@
         };
 
         soc-u9500 {
+                prcmu@80157000 {
+                        ab8500@5 {
+                                ab8500-gpio {
+                                        compatible = "stericsson,ab8500-gpio";
+                                };
+                        };
+                };
+
                 i2c@80004000 {
                         tps61052@33 {
                                 compatible = "tps61052";
@@ -40,7 +48,7 @@
 
                 vmmci: regulator-gpio {
                         gpios = <&tc3589x_gpio 18 0x4>;
-                        gpio-enable = <&tc3589x_gpio 17 0x4>;
+                        enable-gpio = <&tc3589x_gpio 17 0x4>;
 
                         status = "okay";
                 };
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 56afcf41aae0..ad2d79324cd3 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -295,6 +295,7 @@
                         };
 
                         digctl@8001c000 {
+                                compatible = "fsl,imx23-digctl";
                                 reg = <0x8001c000 2000>;
                                 status = "disabled";
                         };
@@ -321,6 +322,7 @@
                         };
 
                         ocotp@8002c000 {
+                                compatible = "fsl,ocotp";
                                 reg = <0x8002c000 0x2000>;
                                 status = "disabled";
                         };
@@ -360,7 +362,7 @@
                         ranges;
 
                         clks: clkctrl@80040000 {
-                                compatible = "fsl,imx23-clkctrl";
+                                compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
                                 reg = <0x80040000 0x2000>;
                                 #clock-cells = <1>;
                         };
@@ -426,6 +428,7 @@
                                 compatible = "fsl,imx23-timrot", "fsl,timrot";
                                 reg = <0x80068000 0x2000>;
                                 interrupts = <28 29 30 31>;
+                                clocks = <&clks 28>;
                         };
 
                         auart0: serial@8006c000 {
diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts
index 1a9d0491cdce..f8db366c46ff 100644
--- a/arch/arm/boot/dts/imx25-karo-tx25.dts
+++ b/arch/arm/boot/dts/imx25-karo-tx25.dts
@@ -10,7 +10,7 @@
  */
 
 /dts-v1/;
-/include/ "imx25.dtsi"
+#include "imx25.dtsi"
 
 / {
         model = "Ka-Ro TX25";
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index a02a860afd18..f607ce520eda 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -10,7 +10,7 @@
  */
 
 /dts-v1/;
-/include/ "imx25.dtsi"
+#include "imx25.dtsi"
 
 / {
         model = "Freescale i.MX25 Product Development Kit";
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 94f33059158a..d2550e0bca24 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -9,7 +9,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
         aliases {
diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts
index b464c807d8d9..ba4c6df08ece 100644
--- a/arch/arm/boot/dts/imx27-apf27.dts
+++ b/arch/arm/boot/dts/imx27-apf27.dts
@@ -13,7 +13,7 @@
  */
 
 /dts-v1/;
-/include/ "imx27.dtsi"
+#include "imx27.dtsi"
 
 / {
         model = "Armadeus Systems APF27 module";
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts
new file mode 100644
index 000000000000..66b8e1c1b0be
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-apf27dev.dts
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2013 Armadeus Systems - <support@armadeus.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/* APF27Dev is a docking board for the APF27 SOM */
+#include "imx27-apf27.dts"
+
+/ {
+        model = "Armadeus Systems APF27Dev docking/development board";
+        compatible = "armadeus,imx27-apf27dev", "armadeus,imx27-apf27", "fsl,imx27";
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                user-key {
+                        label = "user";
+                        gpios = <&gpio6 13 0>;
+                        linux,code = <276>; /* BTN_EXTRA */
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                user {
+                        label = "Heartbeat";
+                        gpios = <&gpio6 14 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
+
+&cspi1 {
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio4 28 1>;
+        status = "okay";
+};
+
+&cspi2 {
+        fsl,spi-num-chipselects = <3>;
+        cs-gpios = <&gpio4 21 1>, <&gpio4 27 1>,
+                        <&gpio2 17 1>;
+        status = "okay";
+};
+
+&i2c1 {
+        clock-frequency = <400000>;
+        status = "okay";
+};
+
+&i2c2 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts
index 41cd1105608e..5ce89aa275df 100644
--- a/arch/arm/boot/dts/imx27-pdk.dts
+++ b/arch/arm/boot/dts/imx27-pdk.dts
@@ -10,7 +10,7 @@
  */
 
 /dts-v1/;
-/include/ "imx27.dtsi"
+#include "imx27.dtsi"
 
 / {
         model = "Freescale i.MX27 Product Development Kit";
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
index 53b0ec0c228e..fe64e3a91df0 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -10,7 +10,7 @@
  */
 
 /dts-v1/;
-/include/ "imx27.dtsi"
+#include "imx27.dtsi"
 
 / {
         model = "Phytec pcm038";
@@ -71,3 +71,9 @@
                 #size-cells = <1>;
         };
 };
+
+&nfc {
+        nand-bus-width = <8>;
+        nand-ecc-mode = "hw";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 5a82cb5707a8..ff4bd4873edf 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -9,7 +9,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
         aliases {
@@ -60,14 +60,41 @@
 
                         wdog: wdog@10002000 {
                                 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
-                                reg = <0x10002000 0x4000>;
+                                reg = <0x10002000 0x1000>;
                                 interrupts = <27>;
+                                clocks = <&clks 0>;
+                        };
+
+                        gpt1: timer@10003000 {
+                                compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
+                                reg = <0x10003000 0x1000>;
+                                interrupts = <26>;
+                                clocks = <&clks 46>, <&clks 61>;
+                                clock-names = "ipg", "per";
+                        };
+
+                        gpt2: timer@10004000 {
+                                compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
+                                reg = <0x10004000 0x1000>;
+                                interrupts = <25>;
+                                clocks = <&clks 45>, <&clks 61>;
+                                clock-names = "ipg", "per";
+                        };
+
+                        gpt3: timer@10005000 {
+                                compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
+                                reg = <0x10005000 0x1000>;
+                                interrupts = <24>;
+                                clocks = <&clks 44>, <&clks 61>;
+                                clock-names = "ipg", "per";
                         };
 
                         uart1: serial@1000a000 {
                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
                                 reg = <0x1000a000 0x1000>;
                                 interrupts = <20>;
+                                clocks = <&clks 81>, <&clks 61>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -75,6 +102,8 @@
                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
                                 reg = <0x1000b000 0x1000>;
                                 interrupts = <19>;
+                                clocks = <&clks 80>, <&clks 61>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -82,6 +111,8 @@
                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
                                 reg = <0x1000c000 0x1000>;
                                 interrupts = <18>;
+                                clocks = <&clks 79>, <&clks 61>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -89,6 +120,8 @@
                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
                                 reg = <0x1000d000 0x1000>;
                                 interrupts = <17>;
+                                clocks = <&clks 78>, <&clks 61>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -98,6 +131,8 @@
                                 compatible = "fsl,imx27-cspi";
                                 reg = <0x1000e000 0x1000>;
                                 interrupts = <16>;
+                                clocks = <&clks 53>, <&clks 0>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -107,6 +142,8 @@
                                 compatible = "fsl,imx27-cspi";
                                 reg = <0x1000f000 0x1000>;
                                 interrupts = <15>;
+                                clocks = <&clks 52>, <&clks 0>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -116,6 +153,7 @@
                                 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
                                 reg = <0x10012000 0x1000>;
                                 interrupts = <12>;
+                                clocks = <&clks 40>;
                                 status = "disabled";
                         };
 
@@ -185,13 +223,33 @@
                                 compatible = "fsl,imx27-cspi";
                                 reg = <0x10017000 0x1000>;
                                 interrupts = <6>;
+                                clocks = <&clks 51>, <&clks 0>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
+                        gpt4: timer@10019000 {
+                                compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
+                                reg = <0x10019000 0x1000>;
+                                interrupts = <4>;
+                                clocks = <&clks 43>, <&clks 61>;
+                                clock-names = "ipg", "per";
+                        };
+
+                        gpt5: timer@1001a000 {
+                                compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
+                                reg = <0x1001a000 0x1000>;
+                                interrupts = <3>;
+                                clocks = <&clks 42>, <&clks 61>;
+                                clock-names = "ipg", "per";
+                        };
+
                         uart5: serial@1001b000 {
                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
                                 reg = <0x1001b000 0x1000>;
                                 interrupts = <49>;
+                                clocks = <&clks 77>, <&clks 61>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -199,6 +257,8 @@
                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
                                 reg = <0x1001c000 0x1000>;
                                 interrupts = <48>;
+                                clocks = <&clks 78>, <&clks 61>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -208,9 +268,17 @@
                                 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
                                 reg = <0x1001d000 0x1000>;
                                 interrupts = <1>;
+                                clocks = <&clks 39>;
                                 status = "disabled";
                         };
 
+                        gpt6: timer@1001f000 {
+                                compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
+                                reg = <0x1001f000 0x1000>;
+                                interrupts = <2>;
+                                clocks = <&clks 41>, <&clks 61>;
+                                clock-names = "ipg", "per";
+                        };
                 };
 
                 aipi@10020000 { /* AIPI2 */
@@ -224,10 +292,19 @@
                                 compatible = "fsl,imx27-fec";
                                 reg = <0x1002b000 0x4000>;
                                 interrupts = <50>;
+                                clocks = <&clks 48>, <&clks 67>, <&clks 0>;
+                                clock-names = "ipg", "ahb", "ptp";
                                 status = "disabled";
                         };
+
+                        clks: ccm@10027000{
+                                compatible = "fsl,imx27-ccm";
+                                reg = <0x10027000 0x1000>;
+                                #clock-cells = <1>;
+                        };
                 };
 
+
                 nfc: nand@d8000000 {
                         #address-cells = <1>;
                         #size-cells = <1>;
@@ -235,6 +312,7 @@
                         compatible = "fsl,imx27-nand";
                         reg = <0xd8000000 0x1000>;
                         interrupts = <29>;
+                        clocks = <&clks 54>;
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 7ba49662b9bc..64af2381c1b0 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -647,6 +647,7 @@
                         };
 
                         digctl@8001c000 {
+                                compatible = "fsl,imx28-digctl";
                                 reg = <0x8001c000 0x2000>;
                                 interrupts = <89>;
                                 status = "disabled";
@@ -676,6 +677,7 @@
                         };
 
                         ocotp@8002c000 {
+                                compatible = "fsl,ocotp";
                                 reg = <0x8002c000 0x2000>;
                                 status = "disabled";
                         };
@@ -755,7 +757,7 @@
                         ranges;
 
                         clks: clkctrl@80040000 {
-                                compatible = "fsl,imx28-clkctrl";
+                                compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
                                 reg = <0x80040000 0x2000>;
                                 #clock-cells = <1>;
                         };
@@ -838,6 +840,7 @@
                                 compatible = "fsl,imx28-timrot", "fsl,timrot";
                                 reg = <0x80068000 0x2000>;
                                 interrupts = <48 49 50 51>;
+                                clocks = <&clks 26>;
                         };
 
                         auart0: serial@8006a000 {
diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts
index 9ac6f6ba1d64..2424abfc9c7b 100644
--- a/arch/arm/boot/dts/imx31-bug.dts
+++ b/arch/arm/boot/dts/imx31-bug.dts
@@ -10,7 +10,7 @@
  */
 
 /dts-v1/;
-/include/ "imx31.dtsi"
+#include "imx31.dtsi"
 
 / {
         model = "Buglabs i.MX31 Bug 1.x";
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index 454c2d175402..c5449257ad9a 100644
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -9,7 +9,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
         aliases {
@@ -101,5 +101,21 @@
                                 #clock-cells = <1>;
                         };
                 };
+
+                aips@53f00000 { /* AIPS2 */
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x53f00000 0x100000>;
+                        ranges;
+
+                        gpt: timer@53f90000 {
+                                compatible = "fsl,imx31-gpt";
+                                reg = <0x53f90000 0x4000>;
+                                interrupts = <29>;
+                                clocks = <&clks 10>, <&clks 22>;
+                                clock-names = "ipg", "per";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/imx35-pinfunc.h b/arch/arm/boot/dts/imx35-pinfunc.h
new file mode 100644
index 000000000000..4911f2c405fa
--- /dev/null
+++ b/arch/arm/boot/dts/imx35-pinfunc.h
@@ -0,0 +1,970 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX35_PINFUNC_H
+#define __DTS_IMX35_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX35_PAD_CAPTURE__GPT_CAPIN1                            0x004 0x328 0x000 0x0 0x0
+#define MX35_PAD_CAPTURE__GPT_CMPOUT2                           0x004 0x328 0x000 0x1 0x0
+#define MX35_PAD_CAPTURE__CSPI2_SS1                             0x004 0x328 0x7f4 0x2 0x0
+#define MX35_PAD_CAPTURE__EPIT1_EPITO                           0x004 0x328 0x000 0x3 0x0
+#define MX35_PAD_CAPTURE__CCM_CLK32K                            0x004 0x328 0x7d0 0x4 0x0
+#define MX35_PAD_CAPTURE__GPIO1_4                               0x004 0x328 0x850 0x5 0x0
+#define MX35_PAD_COMPARE__GPT_CMPOUT1                           0x008 0x32c 0x000 0x0 0x0
+#define MX35_PAD_COMPARE__GPT_CAPIN2                            0x008 0x32c 0x000 0x1 0x0
+#define MX35_PAD_COMPARE__GPT_CMPOUT3                           0x008 0x32c 0x000 0x2 0x0
+#define MX35_PAD_COMPARE__EPIT2_EPITO                           0x008 0x32c 0x000 0x3 0x0
+#define MX35_PAD_COMPARE__GPIO1_5                               0x008 0x32c 0x854 0x5 0x0
+#define MX35_PAD_COMPARE__SDMA_EXTDMA_2                         0x008 0x32c 0x000 0x7 0x0
+#define MX35_PAD_WDOG_RST__WDOG_WDOG_B                          0x00c 0x330 0x000 0x0 0x0
+#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE                     0x00c 0x330 0x000 0x3 0x0
+#define MX35_PAD_WDOG_RST__GPIO1_6                              0x00c 0x330 0x858 0x5 0x0
+#define MX35_PAD_GPIO1_0__GPIO1_0                               0x010 0x334 0x82c 0x0 0x0
+#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY                          0x010 0x334 0x7d4 0x1 0x0
+#define MX35_PAD_GPIO1_0__OWIRE_LINE                            0x010 0x334 0x990 0x2 0x0
+#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0                         0x010 0x334 0x000 0x7 0x0
+#define MX35_PAD_GPIO1_1__GPIO1_1                               0x014 0x338 0x838 0x0 0x0
+#define MX35_PAD_GPIO1_1__PWM_PWMO                              0x014 0x338 0x000 0x2 0x0
+#define MX35_PAD_GPIO1_1__CSPI1_SS2                             0x014 0x338 0x7d8 0x3 0x0
+#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT                     0x014 0x338 0x000 0x6 0x0
+#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1                         0x014 0x338 0x000 0x7 0x0
+#define MX35_PAD_GPIO2_0__GPIO2_0                               0x018 0x33c 0x868 0x0 0x0
+#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK                    0x018 0x33c 0x000 0x1 0x0
+#define MX35_PAD_GPIO3_0__GPIO3_0                               0x01c 0x340 0x8e8 0x0 0x0
+#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK                     0x01c 0x340 0x000 0x1 0x0
+#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B                     0x000 0x344 0x000 0x0 0x0
+#define MX35_PAD_POR_B__CCM_POR_B                               0x000 0x348 0x000 0x0 0x0
+#define MX35_PAD_CLKO__CCM_CLKO                                 0x020 0x34c 0x000 0x0 0x0
+#define MX35_PAD_CLKO__GPIO1_8                                  0x020 0x34c 0x860 0x5 0x0
+#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0                    0x000 0x350 0x000 0x0 0x0
+#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1                    0x000 0x354 0x000 0x0 0x0
+#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0                      0x000 0x358 0x000 0x0 0x0
+#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1                      0x000 0x35c 0x000 0x0 0x0
+#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26              0x000 0x360 0x000 0x0 0x0
+#define MX35_PAD_VSTBY__CCM_VSTBY                               0x024 0x364 0x000 0x0 0x0
+#define MX35_PAD_VSTBY__GPIO1_7                                 0x024 0x364 0x85c 0x5 0x0
+#define MX35_PAD_A0__EMI_EIM_DA_L_0                             0x028 0x368 0x000 0x0 0x0
+#define MX35_PAD_A1__EMI_EIM_DA_L_1                             0x02c 0x36c 0x000 0x0 0x0
+#define MX35_PAD_A2__EMI_EIM_DA_L_2                             0x030 0x370 0x000 0x0 0x0
+#define MX35_PAD_A3__EMI_EIM_DA_L_3                             0x034 0x374 0x000 0x0 0x0
+#define MX35_PAD_A4__EMI_EIM_DA_L_4                             0x038 0x378 0x000 0x0 0x0
+#define MX35_PAD_A5__EMI_EIM_DA_L_5                             0x03c 0x37c 0x000 0x0 0x0
+#define MX35_PAD_A6__EMI_EIM_DA_L_6                             0x040 0x380 0x000 0x0 0x0
+#define MX35_PAD_A7__EMI_EIM_DA_L_7                             0x044 0x384 0x000 0x0 0x0
+#define MX35_PAD_A8__EMI_EIM_DA_H_8                             0x048 0x388 0x000 0x0 0x0
+#define MX35_PAD_A9__EMI_EIM_DA_H_9                             0x04c 0x38c 0x000 0x0 0x0
+#define MX35_PAD_A10__EMI_EIM_DA_H_10                           0x050 0x390 0x000 0x0 0x0
+#define MX35_PAD_MA10__EMI_MA10                                 0x054 0x394 0x000 0x0 0x0
+#define MX35_PAD_A11__EMI_EIM_DA_H_11                           0x058 0x398 0x000 0x0 0x0
+#define MX35_PAD_A12__EMI_EIM_DA_H_12                           0x05c 0x39c 0x000 0x0 0x0
+#define MX35_PAD_A13__EMI_EIM_DA_H_13                           0x060 0x3a0 0x000 0x0 0x0
+#define MX35_PAD_A14__EMI_EIM_DA_H2_14                          0x064 0x3a4 0x000 0x0 0x0
+#define MX35_PAD_A15__EMI_EIM_DA_H2_15                          0x068 0x3a8 0x000 0x0 0x0
+#define MX35_PAD_A16__EMI_EIM_A_16                              0x06c 0x3ac 0x000 0x0 0x0
+#define MX35_PAD_A17__EMI_EIM_A_17                              0x070 0x3b0 0x000 0x0 0x0
+#define MX35_PAD_A18__EMI_EIM_A_18                              0x074 0x3b4 0x000 0x0 0x0
+#define MX35_PAD_A19__EMI_EIM_A_19                              0x078 0x3b8 0x000 0x0 0x0
+#define MX35_PAD_A20__EMI_EIM_A_20                              0x07c 0x3bc 0x000 0x0 0x0
+#define MX35_PAD_A21__EMI_EIM_A_21                              0x080 0x3c0 0x000 0x0 0x0
+#define MX35_PAD_A22__EMI_EIM_A_22                              0x084 0x3c4 0x000 0x0 0x0
+#define MX35_PAD_A23__EMI_EIM_A_23                              0x088 0x3c8 0x000 0x0 0x0
+#define MX35_PAD_A24__EMI_EIM_A_24                              0x08c 0x3cc 0x000 0x0 0x0
+#define MX35_PAD_A25__EMI_EIM_A_25                              0x090 0x3d0 0x000 0x0 0x0
+#define MX35_PAD_SDBA1__EMI_EIM_SDBA1                           0x000 0x3d4 0x000 0x0 0x0
+#define MX35_PAD_SDBA0__EMI_EIM_SDBA0                           0x000 0x3d8 0x000 0x0 0x0
+#define MX35_PAD_SD0__EMI_DRAM_D_0                              0x000 0x3dc 0x000 0x0 0x0
+#define MX35_PAD_SD1__EMI_DRAM_D_1                              0x000 0x3e0 0x000 0x0 0x0
+#define MX35_PAD_SD2__EMI_DRAM_D_2                              0x000 0x3e4 0x000 0x0 0x0
+#define MX35_PAD_SD3__EMI_DRAM_D_3                              0x000 0x3e8 0x000 0x0 0x0
+#define MX35_PAD_SD4__EMI_DRAM_D_4                              0x000 0x3ec 0x000 0x0 0x0
+#define MX35_PAD_SD5__EMI_DRAM_D_5                              0x000 0x3f0 0x000 0x0 0x0
+#define MX35_PAD_SD6__EMI_DRAM_D_6                              0x000 0x3f4 0x000 0x0 0x0
+#define MX35_PAD_SD7__EMI_DRAM_D_7                              0x000 0x3f8 0x000 0x0 0x0
+#define MX35_PAD_SD8__EMI_DRAM_D_8                              0x000 0x3fc 0x000 0x0 0x0
+#define MX35_PAD_SD9__EMI_DRAM_D_9                              0x000 0x400 0x000 0x0 0x0
+#define MX35_PAD_SD10__EMI_DRAM_D_10                            0x000 0x404 0x000 0x0 0x0
+#define MX35_PAD_SD11__EMI_DRAM_D_11                            0x000 0x408 0x000 0x0 0x0
+#define MX35_PAD_SD12__EMI_DRAM_D_12                            0x000 0x40c 0x000 0x0 0x0
+#define MX35_PAD_SD13__EMI_DRAM_D_13                            0x000 0x410 0x000 0x0 0x0
+#define MX35_PAD_SD14__EMI_DRAM_D_14                            0x000 0x414 0x000 0x0 0x0
+#define MX35_PAD_SD15__EMI_DRAM_D_15                            0x000 0x418 0x000 0x0 0x0
+#define MX35_PAD_SD16__EMI_DRAM_D_16                            0x000 0x41c 0x000 0x0 0x0
+#define MX35_PAD_SD17__EMI_DRAM_D_17                            0x000 0x420 0x000 0x0 0x0
+#define MX35_PAD_SD18__EMI_DRAM_D_18                            0x000 0x424 0x000 0x0 0x0
+#define MX35_PAD_SD19__EMI_DRAM_D_19                            0x000 0x428 0x000 0x0 0x0
+#define MX35_PAD_SD20__EMI_DRAM_D_20                            0x000 0x42c 0x000 0x0 0x0
+#define MX35_PAD_SD21__EMI_DRAM_D_21                            0x000 0x430 0x000 0x0 0x0
+#define MX35_PAD_SD22__EMI_DRAM_D_22                            0x000 0x434 0x000 0x0 0x0
+#define MX35_PAD_SD23__EMI_DRAM_D_23                            0x000 0x438 0x000 0x0 0x0
+#define MX35_PAD_SD24__EMI_DRAM_D_24                            0x000 0x43c 0x000 0x0 0x0
+#define MX35_PAD_SD25__EMI_DRAM_D_25                            0x000 0x440 0x000 0x0 0x0
+#define MX35_PAD_SD26__EMI_DRAM_D_26                            0x000 0x444 0x000 0x0 0x0
+#define MX35_PAD_SD27__EMI_DRAM_D_27                            0x000 0x448 0x000 0x0 0x0
+#define MX35_PAD_SD28__EMI_DRAM_D_28                            0x000 0x44c 0x000 0x0 0x0
+#define MX35_PAD_SD29__EMI_DRAM_D_29                            0x000 0x450 0x000 0x0 0x0
+#define MX35_PAD_SD30__EMI_DRAM_D_30                            0x000 0x454 0x000 0x0 0x0
+#define MX35_PAD_SD31__EMI_DRAM_D_31                            0x000 0x458 0x000 0x0 0x0
+#define MX35_PAD_DQM0__EMI_DRAM_DQM_0                           0x000 0x45c 0x000 0x0 0x0
+#define MX35_PAD_DQM1__EMI_DRAM_DQM_1                           0x000 0x460 0x000 0x0 0x0
+#define MX35_PAD_DQM2__EMI_DRAM_DQM_2                           0x000 0x464 0x000 0x0 0x0
+#define MX35_PAD_DQM3__EMI_DRAM_DQM_3                           0x000 0x468 0x000 0x0 0x0
+#define MX35_PAD_EB0__EMI_EIM_EB0_B                             0x094 0x46c 0x000 0x0 0x0
+#define MX35_PAD_EB1__EMI_EIM_EB1_B                             0x098 0x470 0x000 0x0 0x0
+#define MX35_PAD_OE__EMI_EIM_OE                                 0x09c 0x474 0x000 0x0 0x0
+#define MX35_PAD_CS0__EMI_EIM_CS0                               0x0a0 0x478 0x000 0x0 0x0
+#define MX35_PAD_CS1__EMI_EIM_CS1                               0x0a4 0x47c 0x000 0x0 0x0
+#define MX35_PAD_CS1__EMI_NANDF_CE3                             0x0a4 0x47c 0x000 0x3 0x0
+#define MX35_PAD_CS2__EMI_EIM_CS2                               0x0a8 0x480 0x000 0x0 0x0
+#define MX35_PAD_CS3__EMI_EIM_CS3                               0x0ac 0x484 0x000 0x0 0x0
+#define MX35_PAD_CS4__EMI_EIM_CS4                               0x0b0 0x488 0x000 0x0 0x0
+#define MX35_PAD_CS4__EMI_DTACK_B                               0x0b0 0x488 0x800 0x1 0x0
+#define MX35_PAD_CS4__EMI_NANDF_CE1                             0x0b0 0x488 0x000 0x3 0x0
+#define MX35_PAD_CS4__GPIO1_20                                  0x0b0 0x488 0x83c 0x5 0x0
+#define MX35_PAD_CS5__EMI_EIM_CS5                               0x0b4 0x48c 0x000 0x0 0x0
+#define MX35_PAD_CS5__CSPI2_SS2                                 0x0b4 0x48c 0x7f8 0x1 0x0
+#define MX35_PAD_CS5__CSPI1_SS2                                 0x0b4 0x48c 0x7d8 0x2 0x1
+#define MX35_PAD_CS5__EMI_NANDF_CE2                             0x0b4 0x48c 0x000 0x3 0x0
+#define MX35_PAD_CS5__GPIO1_21                                  0x0b4 0x48c 0x840 0x5 0x0
+#define MX35_PAD_NF_CE0__EMI_NANDF_CE0                          0x0b8 0x490 0x000 0x0 0x0
+#define MX35_PAD_NF_CE0__GPIO1_22                               0x0b8 0x490 0x844 0x5 0x0
+#define MX35_PAD_ECB__EMI_EIM_ECB                               0x000 0x494 0x000 0x0 0x0
+#define MX35_PAD_LBA__EMI_EIM_LBA                               0x0bc 0x498 0x000 0x0 0x0
+#define MX35_PAD_BCLK__EMI_EIM_BCLK                             0x0c0 0x49c 0x000 0x0 0x0
+#define MX35_PAD_RW__EMI_EIM_RW                                 0x0c4 0x4a0 0x000 0x0 0x0
+#define MX35_PAD_RAS__EMI_DRAM_RAS                              0x000 0x4a4 0x000 0x0 0x0
+#define MX35_PAD_CAS__EMI_DRAM_CAS                              0x000 0x4a8 0x000 0x0 0x0
+#define MX35_PAD_SDWE__EMI_DRAM_SDWE                            0x000 0x4ac 0x000 0x0 0x0
+#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0                       0x000 0x4b0 0x000 0x0 0x0
+#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1                       0x000 0x4b4 0x000 0x0 0x0
+#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK                          0x000 0x4b8 0x000 0x0 0x0
+#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0                         0x000 0x4bc 0x000 0x0 0x0
+#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1                         0x000 0x4c0 0x000 0x0 0x0
+#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2                         0x000 0x4c4 0x000 0x0 0x0
+#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3                         0x000 0x4c8 0x000 0x0 0x0
+#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B                         0x0c8 0x4cc 0x000 0x0 0x0
+#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3                   0x0c8 0x4cc 0x9d8 0x1 0x0
+#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC                     0x0c8 0x4cc 0x924 0x2 0x0
+#define MX35_PAD_NFWE_B__GPIO2_18                               0x0c8 0x4cc 0x88c 0x5 0x0
+#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0                     0x0c8 0x4cc 0x000 0x7 0x0
+#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B                         0x0cc 0x4d0 0x000 0x0 0x0
+#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR                      0x0cc 0x4d0 0x9ec 0x1 0x0
+#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK                         0x0cc 0x4d0 0x000 0x2 0x0
+#define MX35_PAD_NFRE_B__GPIO2_19                               0x0cc 0x4d0 0x890 0x5 0x0
+#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1                     0x0cc 0x4d0 0x000 0x7 0x0
+#define MX35_PAD_NFALE__EMI_NANDF_ALE                           0x0d0 0x4d4 0x000 0x0 0x0
+#define MX35_PAD_NFALE__USB_TOP_USBH2_STP                       0x0d0 0x4d4 0x000 0x1 0x0
+#define MX35_PAD_NFALE__IPU_DISPB_CS0                           0x0d0 0x4d4 0x000 0x2 0x0
+#define MX35_PAD_NFALE__GPIO2_20                                0x0d0 0x4d4 0x898 0x5 0x0
+#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2                      0x0d0 0x4d4 0x000 0x7 0x0
+#define MX35_PAD_NFCLE__EMI_NANDF_CLE                           0x0d4 0x4d8 0x000 0x0 0x0
+#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT                       0x0d4 0x4d8 0x9f0 0x1 0x0
+#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS                        0x0d4 0x4d8 0x000 0x2 0x0
+#define MX35_PAD_NFCLE__GPIO2_21                                0x0d4 0x4d8 0x89c 0x5 0x0
+#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3                      0x0d4 0x4d8 0x000 0x7 0x0
+#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B                         0x0d8 0x4dc 0x000 0x0 0x0
+#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7                   0x0d8 0x4dc 0x9e8 0x1 0x0
+#define MX35_PAD_NFWP_B__IPU_DISPB_WR                           0x0d8 0x4dc 0x000 0x2 0x0
+#define MX35_PAD_NFWP_B__GPIO2_22                               0x0d8 0x4dc 0x8a0 0x5 0x0
+#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL                       0x0d8 0x4dc 0x000 0x7 0x0
+#define MX35_PAD_NFRB__EMI_NANDF_RB                             0x0dc 0x4e0 0x000 0x0 0x0
+#define MX35_PAD_NFRB__IPU_DISPB_RD                             0x0dc 0x4e0 0x000 0x2 0x0
+#define MX35_PAD_NFRB__GPIO2_23                                 0x0dc 0x4e0 0x8a4 0x5 0x0
+#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK                         0x0dc 0x4e0 0x000 0x7 0x0
+#define MX35_PAD_D15__EMI_EIM_D_15                              0x000 0x4e4 0x000 0x0 0x0
+#define MX35_PAD_D14__EMI_EIM_D_14                              0x000 0x4e8 0x000 0x0 0x0
+#define MX35_PAD_D13__EMI_EIM_D_13                              0x000 0x4ec 0x000 0x0 0x0
+#define MX35_PAD_D12__EMI_EIM_D_12                              0x000 0x4f0 0x000 0x0 0x0
+#define MX35_PAD_D11__EMI_EIM_D_11                              0x000 0x4f4 0x000 0x0 0x0
+#define MX35_PAD_D10__EMI_EIM_D_10                              0x000 0x4f8 0x000 0x0 0x0
+#define MX35_PAD_D9__EMI_EIM_D_9                                0x000 0x4fc 0x000 0x0 0x0
+#define MX35_PAD_D8__EMI_EIM_D_8                                0x000 0x500 0x000 0x0 0x0
+#define MX35_PAD_D7__EMI_EIM_D_7                                0x000 0x504 0x000 0x0 0x0
+#define MX35_PAD_D6__EMI_EIM_D_6                                0x000 0x508 0x000 0x0 0x0
+#define MX35_PAD_D5__EMI_EIM_D_5                                0x000 0x50c 0x000 0x0 0x0
+#define MX35_PAD_D4__EMI_EIM_D_4                                0x000 0x510 0x000 0x0 0x0
+#define MX35_PAD_D3__EMI_EIM_D_3                                0x000 0x514 0x000 0x0 0x0
+#define MX35_PAD_D2__EMI_EIM_D_2                                0x000 0x518 0x000 0x0 0x0
+#define MX35_PAD_D1__EMI_EIM_D_1                                0x000 0x51c 0x000 0x0 0x0
+#define MX35_PAD_D0__EMI_EIM_D_0                                0x000 0x520 0x000 0x0 0x0
+#define MX35_PAD_CSI_D8__IPU_CSI_D_8                            0x0e0 0x524 0x000 0x0 0x0
+#define MX35_PAD_CSI_D8__KPP_COL_0                              0x0e0 0x524 0x950 0x1 0x0
+#define MX35_PAD_CSI_D8__GPIO1_20                               0x0e0 0x524 0x83c 0x5 0x1
+#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13                  0x0e0 0x524 0x000 0x7 0x0
+#define MX35_PAD_CSI_D9__IPU_CSI_D_9                            0x0e4 0x528 0x000 0x0 0x0
+#define MX35_PAD_CSI_D9__KPP_COL_1                              0x0e4 0x528 0x954 0x1 0x0
+#define MX35_PAD_CSI_D9__GPIO1_21                               0x0e4 0x528 0x840 0x5 0x1
+#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14                  0x0e4 0x528 0x000 0x7 0x0
+#define MX35_PAD_CSI_D10__IPU_CSI_D_10                          0x0e8 0x52c 0x000 0x0 0x0
+#define MX35_PAD_CSI_D10__KPP_COL_2                             0x0e8 0x52c 0x958 0x1 0x0
+#define MX35_PAD_CSI_D10__GPIO1_22                              0x0e8 0x52c 0x844 0x5 0x1
+#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15                 0x0e8 0x52c 0x000 0x7 0x0
+#define MX35_PAD_CSI_D11__IPU_CSI_D_11                          0x0ec 0x530 0x000 0x0 0x0
+#define MX35_PAD_CSI_D11__KPP_COL_3                             0x0ec 0x530 0x95c 0x1 0x0
+#define MX35_PAD_CSI_D11__GPIO1_23                              0x0ec 0x530 0x000 0x5 0x0
+#define MX35_PAD_CSI_D12__IPU_CSI_D_12                          0x0f0 0x534 0x000 0x0 0x0
+#define MX35_PAD_CSI_D12__KPP_ROW_0                             0x0f0 0x534 0x970 0x1 0x0
+#define MX35_PAD_CSI_D12__GPIO1_24                              0x0f0 0x534 0x000 0x5 0x0
+#define MX35_PAD_CSI_D13__IPU_CSI_D_13                          0x0f4 0x538 0x000 0x0 0x0
+#define MX35_PAD_CSI_D13__KPP_ROW_1                             0x0f4 0x538 0x974 0x1 0x0
+#define MX35_PAD_CSI_D13__GPIO1_25                              0x0f4 0x538 0x000 0x5 0x0
+#define MX35_PAD_CSI_D14__IPU_CSI_D_14                          0x0f8 0x53c 0x000 0x0 0x0
+#define MX35_PAD_CSI_D14__KPP_ROW_2                             0x0f8 0x53c 0x978 0x1 0x0
+#define MX35_PAD_CSI_D14__GPIO1_26                              0x0f8 0x53c 0x000 0x5 0x0
+#define MX35_PAD_CSI_D15__IPU_CSI_D_15                          0x0fc 0x540 0x97c 0x0 0x0
+#define MX35_PAD_CSI_D15__KPP_ROW_3                             0x0fc 0x540 0x000 0x1 0x0
+#define MX35_PAD_CSI_D15__GPIO1_27                              0x0fc 0x540 0x000 0x5 0x0
+#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK                         0x100 0x544 0x000 0x0 0x0
+#define MX35_PAD_CSI_MCLK__GPIO1_28                             0x100 0x544 0x000 0x5 0x0
+#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC                       0x104 0x548 0x000 0x0 0x0
+#define MX35_PAD_CSI_VSYNC__GPIO1_29                            0x104 0x548 0x000 0x5 0x0
+#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC                       0x108 0x54c 0x000 0x0 0x0
+#define MX35_PAD_CSI_HSYNC__GPIO1_30                            0x108 0x54c 0x000 0x5 0x0
+#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK                     0x10c 0x550 0x000 0x0 0x0
+#define MX35_PAD_CSI_PIXCLK__GPIO1_31                           0x10c 0x550 0x000 0x5 0x0
+#define MX35_PAD_I2C1_CLK__I2C1_SCL                             0x110 0x554 0x000 0x0 0x0
+#define MX35_PAD_I2C1_CLK__GPIO2_24                             0x110 0x554 0x8a8 0x5 0x0
+#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK                      0x110 0x554 0x000 0x6 0x0
+#define MX35_PAD_I2C1_DAT__I2C1_SDA                             0x114 0x558 0x000 0x0 0x0
+#define MX35_PAD_I2C1_DAT__GPIO2_25                             0x114 0x558 0x8ac 0x5 0x0
+#define MX35_PAD_I2C2_CLK__I2C2_SCL                             0x118 0x55c 0x000 0x0 0x0
+#define MX35_PAD_I2C2_CLK__CAN1_TXCAN                           0x118 0x55c 0x000 0x1 0x0
+#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR                    0x118 0x55c 0x000 0x2 0x0
+#define MX35_PAD_I2C2_CLK__GPIO2_26                             0x118 0x55c 0x8b0 0x5 0x0
+#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2              0x118 0x55c 0x000 0x6 0x0
+#define MX35_PAD_I2C2_DAT__I2C2_SDA                             0x11c 0x560 0x000 0x0 0x0
+#define MX35_PAD_I2C2_DAT__CAN1_RXCAN                           0x11c 0x560 0x7c8 0x1 0x0
+#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC                     0x11c 0x560 0x9f4 0x2 0x0
+#define MX35_PAD_I2C2_DAT__GPIO2_27                             0x11c 0x560 0x8b4 0x5 0x0
+#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3              0x11c 0x560 0x000 0x6 0x0
+#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD                         0x120 0x564 0x000 0x0 0x0
+#define MX35_PAD_STXD4__GPIO2_28                                0x120 0x564 0x8b8 0x5 0x0
+#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0                0x120 0x564 0x000 0x7 0x0
+#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD                         0x124 0x568 0x000 0x0 0x0
+#define MX35_PAD_SRXD4__GPIO2_29                                0x124 0x568 0x8bc 0x5 0x0
+#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1                0x124 0x568 0x000 0x7 0x0
+#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC                          0x128 0x56c 0x000 0x0 0x0
+#define MX35_PAD_SCK4__GPIO2_30                                 0x128 0x56c 0x8c4 0x5 0x0
+#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2                 0x128 0x56c 0x000 0x7 0x0
+#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS                       0x12c 0x570 0x000 0x0 0x0
+#define MX35_PAD_STXFS4__GPIO2_31                               0x12c 0x570 0x8c8 0x5 0x0
+#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3               0x12c 0x570 0x000 0x7 0x0
+#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD                         0x130 0x574 0x000 0x0 0x0
+#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1                        0x130 0x574 0x000 0x1 0x0
+#define MX35_PAD_STXD5__CSPI2_MOSI                              0x130 0x574 0x7ec 0x2 0x0
+#define MX35_PAD_STXD5__GPIO1_0                                 0x130 0x574 0x82c 0x5 0x1
+#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4                0x130 0x574 0x000 0x7 0x0
+#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD                         0x134 0x578 0x000 0x0 0x0
+#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1                         0x134 0x578 0x998 0x1 0x0
+#define MX35_PAD_SRXD5__CSPI2_MISO                              0x134 0x578 0x7e8 0x2 0x0
+#define MX35_PAD_SRXD5__GPIO1_1                                 0x134 0x578 0x838 0x5 0x1
+#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5                0x134 0x578 0x000 0x7 0x0
+#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC                          0x138 0x57c 0x000 0x0 0x0
+#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK                       0x138 0x57c 0x994 0x1 0x0
+#define MX35_PAD_SCK5__CSPI2_SCLK                               0x138 0x57c 0x7e0 0x2 0x0
+#define MX35_PAD_SCK5__GPIO1_2                                  0x138 0x57c 0x848 0x5 0x0
+#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6                 0x138 0x57c 0x000 0x7 0x0
+#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS                       0x13c 0x580 0x000 0x0 0x0
+#define MX35_PAD_STXFS5__CSPI2_RDY                              0x13c 0x580 0x7e4 0x2 0x0
+#define MX35_PAD_STXFS5__GPIO1_3                                0x13c 0x580 0x84c 0x5 0x0
+#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7               0x13c 0x580 0x000 0x7 0x0
+#define MX35_PAD_SCKR__ESAI_SCKR                                0x140 0x584 0x000 0x0 0x0
+#define MX35_PAD_SCKR__GPIO1_4                                  0x140 0x584 0x850 0x5 0x1
+#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10                    0x140 0x584 0x000 0x7 0x0
+#define MX35_PAD_FSR__ESAI_FSR                                  0x144 0x588 0x000 0x0 0x0
+#define MX35_PAD_FSR__GPIO1_5                                   0x144 0x588 0x854 0x5 0x1
+#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11                     0x144 0x588 0x000 0x7 0x0
+#define MX35_PAD_HCKR__ESAI_HCKR                                0x148 0x58c 0x000 0x0 0x0
+#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS                         0x148 0x58c 0x000 0x1 0x0
+#define MX35_PAD_HCKR__CSPI2_SS0                                0x148 0x58c 0x7f0 0x2 0x0
+#define MX35_PAD_HCKR__IPU_FLASH_STROBE                         0x148 0x58c 0x000 0x3 0x0
+#define MX35_PAD_HCKR__GPIO1_6                                  0x148 0x58c 0x858 0x5 0x1
+#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12                    0x148 0x58c 0x000 0x7 0x0
+#define MX35_PAD_SCKT__ESAI_SCKT                                0x14c 0x590 0x000 0x0 0x0
+#define MX35_PAD_SCKT__GPIO1_7                                  0x14c 0x590 0x85c 0x5 0x1
+#define MX35_PAD_SCKT__IPU_CSI_D_0                              0x14c 0x590 0x930 0x6 0x0
+#define MX35_PAD_SCKT__KPP_ROW_2                                0x14c 0x590 0x978 0x7 0x1
+#define MX35_PAD_FST__ESAI_FST                                  0x150 0x594 0x000 0x0 0x0
+#define MX35_PAD_FST__GPIO1_8                                   0x150 0x594 0x860 0x5 0x1
+#define MX35_PAD_FST__IPU_CSI_D_1                               0x150 0x594 0x934 0x6 0x0
+#define MX35_PAD_FST__KPP_ROW_3                                 0x150 0x594 0x97c 0x7 0x1
+#define MX35_PAD_HCKT__ESAI_HCKT                                0x154 0x598 0x000 0x0 0x0
+#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC                          0x154 0x598 0x7a8 0x1 0x0
+#define MX35_PAD_HCKT__GPIO1_9                                  0x154 0x598 0x864 0x5 0x0
+#define MX35_PAD_HCKT__IPU_CSI_D_2                              0x154 0x598 0x938 0x6 0x0
+#define MX35_PAD_HCKT__KPP_COL_3                                0x154 0x598 0x95c 0x7 0x1
+#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0                          0x158 0x59c 0x000 0x0 0x0
+#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC                       0x158 0x59c 0x000 0x1 0x0
+#define MX35_PAD_TX5_RX0__CSPI2_SS2                             0x158 0x59c 0x7f8 0x2 0x1
+#define MX35_PAD_TX5_RX0__CAN2_TXCAN                            0x158 0x59c 0x000 0x3 0x0
+#define MX35_PAD_TX5_RX0__UART2_DTR                             0x158 0x59c 0x000 0x4 0x0
+#define MX35_PAD_TX5_RX0__GPIO1_10                              0x158 0x59c 0x830 0x5 0x0
+#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0              0x158 0x59c 0x000 0x7 0x0
+#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1                          0x15c 0x5a0 0x000 0x0 0x0
+#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS                      0x15c 0x5a0 0x000 0x1 0x0
+#define MX35_PAD_TX4_RX1__CSPI2_SS3                             0x15c 0x5a0 0x7fc 0x2 0x0
+#define MX35_PAD_TX4_RX1__CAN2_RXCAN                            0x15c 0x5a0 0x7cc 0x3 0x0
+#define MX35_PAD_TX4_RX1__UART2_DSR                             0x15c 0x5a0 0x000 0x4 0x0
+#define MX35_PAD_TX4_RX1__GPIO1_11                              0x15c 0x5a0 0x834 0x5 0x0
+#define MX35_PAD_TX4_RX1__IPU_CSI_D_3                           0x15c 0x5a0 0x93c 0x6 0x0
+#define MX35_PAD_TX4_RX1__KPP_ROW_0                             0x15c 0x5a0 0x970 0x7 0x1
+#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2                          0x160 0x5a4 0x000 0x0 0x0
+#define MX35_PAD_TX3_RX2__I2C3_SCL                              0x160 0x5a4 0x91c 0x1 0x0
+#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1                         0x160 0x5a4 0x000 0x3 0x0
+#define MX35_PAD_TX3_RX2__GPIO1_12                              0x160 0x5a4 0x000 0x5 0x0
+#define MX35_PAD_TX3_RX2__IPU_CSI_D_4                           0x160 0x5a4 0x940 0x6 0x0
+#define MX35_PAD_TX3_RX2__KPP_ROW_1                             0x160 0x5a4 0x974 0x7 0x1
+#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3                          0x164 0x5a8 0x000 0x0 0x0
+#define MX35_PAD_TX2_RX3__I2C3_SDA                              0x164 0x5a8 0x920 0x1 0x0
+#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2                         0x164 0x5a8 0x000 0x3 0x0
+#define MX35_PAD_TX2_RX3__GPIO1_13                              0x164 0x5a8 0x000 0x5 0x0
+#define MX35_PAD_TX2_RX3__IPU_CSI_D_5                           0x164 0x5a8 0x944 0x6 0x0
+#define MX35_PAD_TX2_RX3__KPP_COL_0                             0x164 0x5a8 0x950 0x7 0x1
+#define MX35_PAD_TX1__ESAI_TX1                                  0x168 0x5ac 0x000 0x0 0x0
+#define MX35_PAD_TX1__CCM_PMIC_RDY                              0x168 0x5ac 0x7d4 0x1 0x1
+#define MX35_PAD_TX1__CSPI1_SS2                                 0x168 0x5ac 0x7d8 0x2 0x2
+#define MX35_PAD_TX1__EMI_NANDF_CE3                             0x168 0x5ac 0x000 0x3 0x0
+#define MX35_PAD_TX1__UART2_RI                                  0x168 0x5ac 0x000 0x4 0x0
+#define MX35_PAD_TX1__GPIO1_14                                  0x168 0x5ac 0x000 0x5 0x0
+#define MX35_PAD_TX1__IPU_CSI_D_6                               0x168 0x5ac 0x948 0x6 0x0
+#define MX35_PAD_TX1__KPP_COL_1                                 0x168 0x5ac 0x954 0x7 0x1
+#define MX35_PAD_TX0__ESAI_TX0                                  0x16c 0x5b0 0x000 0x0 0x0
+#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK                        0x16c 0x5b0 0x994 0x1 0x1
+#define MX35_PAD_TX0__CSPI1_SS3                                 0x16c 0x5b0 0x7dc 0x2 0x0
+#define MX35_PAD_TX0__EMI_DTACK_B                               0x16c 0x5b0 0x800 0x3 0x1
+#define MX35_PAD_TX0__UART2_DCD                                 0x16c 0x5b0 0x000 0x4 0x0
+#define MX35_PAD_TX0__GPIO1_15                                  0x16c 0x5b0 0x000 0x5 0x0
+#define MX35_PAD_TX0__IPU_CSI_D_7                               0x16c 0x5b0 0x94c 0x6 0x0
+#define MX35_PAD_TX0__KPP_COL_2                                 0x16c 0x5b0 0x958 0x7 0x1
+#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI                         0x170 0x5b4 0x000 0x0 0x0
+#define MX35_PAD_CSPI1_MOSI__GPIO1_16                           0x170 0x5b4 0x000 0x5 0x0
+#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2                0x170 0x5b4 0x000 0x7 0x0
+#define MX35_PAD_CSPI1_MISO__CSPI1_MISO                         0x174 0x5b8 0x000 0x0 0x0
+#define MX35_PAD_CSPI1_MISO__GPIO1_17                           0x174 0x5b8 0x000 0x5 0x0
+#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3                0x174 0x5b8 0x000 0x7 0x0
+#define MX35_PAD_CSPI1_SS0__CSPI1_SS0                           0x178 0x5bc 0x000 0x0 0x0
+#define MX35_PAD_CSPI1_SS0__OWIRE_LINE                          0x178 0x5bc 0x990 0x1 0x1
+#define MX35_PAD_CSPI1_SS0__CSPI2_SS3                           0x178 0x5bc 0x7fc 0x2 0x1
+#define MX35_PAD_CSPI1_SS0__GPIO1_18                            0x178 0x5bc 0x000 0x5 0x0
+#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4                 0x178 0x5bc 0x000 0x7 0x0
+#define MX35_PAD_CSPI1_SS1__CSPI1_SS1                           0x17c 0x5c0 0x000 0x0 0x0
+#define MX35_PAD_CSPI1_SS1__PWM_PWMO                            0x17c 0x5c0 0x000 0x1 0x0
+#define MX35_PAD_CSPI1_SS1__CCM_CLK32K                          0x17c 0x5c0 0x7d0 0x2 0x1
+#define MX35_PAD_CSPI1_SS1__GPIO1_19                            0x17c 0x5c0 0x000 0x5 0x0
+#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29                        0x17c 0x5c0 0x000 0x6 0x0
+#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5                 0x17c 0x5c0 0x000 0x7 0x0
+#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK                         0x180 0x5c4 0x000 0x0 0x0
+#define MX35_PAD_CSPI1_SCLK__GPIO3_4                            0x180 0x5c4 0x904 0x5 0x0
+#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30                       0x180 0x5c4 0x000 0x6 0x0
+#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1           0x180 0x5c4 0x000 0x7 0x0
+#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY                       0x184 0x5c8 0x000 0x0 0x0
+#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5                         0x184 0x5c8 0x908 0x5 0x0
+#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31                    0x184 0x5c8 0x000 0x6 0x0
+#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2        0x184 0x5c8 0x000 0x7 0x0
+#define MX35_PAD_RXD1__UART1_RXD_MUX                            0x188 0x5cc 0x000 0x0 0x0
+#define MX35_PAD_RXD1__CSPI2_MOSI                               0x188 0x5cc 0x7ec 0x1 0x1
+#define MX35_PAD_RXD1__KPP_COL_4                                0x188 0x5cc 0x960 0x4 0x0
+#define MX35_PAD_RXD1__GPIO3_6                                  0x188 0x5cc 0x90c 0x5 0x0
+#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16                    0x188 0x5cc 0x000 0x7 0x0
+#define MX35_PAD_TXD1__UART1_TXD_MUX                            0x18c 0x5d0 0x000 0x0 0x0
+#define MX35_PAD_TXD1__CSPI2_MISO                               0x18c 0x5d0 0x7e8 0x1 0x1
+#define MX35_PAD_TXD1__KPP_COL_5                                0x18c 0x5d0 0x964 0x4 0x0
+#define MX35_PAD_TXD1__GPIO3_7                                  0x18c 0x5d0 0x910 0x5 0x0
+#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17                    0x18c 0x5d0 0x000 0x7 0x0
+#define MX35_PAD_RTS1__UART1_RTS                                0x190 0x5d4 0x000 0x0 0x0
+#define MX35_PAD_RTS1__CSPI2_SCLK                               0x190 0x5d4 0x7e0 0x1 0x1
+#define MX35_PAD_RTS1__I2C3_SCL                                 0x190 0x5d4 0x91c 0x2 0x1
+#define MX35_PAD_RTS1__IPU_CSI_D_0                              0x190 0x5d4 0x930 0x3 0x1
+#define MX35_PAD_RTS1__KPP_COL_6                                0x190 0x5d4 0x968 0x4 0x0
+#define MX35_PAD_RTS1__GPIO3_8                                  0x190 0x5d4 0x914 0x5 0x0
+#define MX35_PAD_RTS1__EMI_NANDF_CE1                            0x190 0x5d4 0x000 0x6 0x0
+#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18                    0x190 0x5d4 0x000 0x7 0x0
+#define MX35_PAD_CTS1__UART1_CTS                                0x194 0x5d8 0x000 0x0 0x0
+#define MX35_PAD_CTS1__CSPI2_RDY                                0x194 0x5d8 0x7e4 0x1 0x1
+#define MX35_PAD_CTS1__I2C3_SDA                                 0x194 0x5d8 0x920 0x2 0x1
+#define MX35_PAD_CTS1__IPU_CSI_D_1                              0x194 0x5d8 0x934 0x3 0x1
+#define MX35_PAD_CTS1__KPP_COL_7                                0x194 0x5d8 0x96c 0x4 0x0
+#define MX35_PAD_CTS1__GPIO3_9                                  0x194 0x5d8 0x918 0x5 0x0
+#define MX35_PAD_CTS1__EMI_NANDF_CE2                            0x194 0x5d8 0x000 0x6 0x0
+#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19                    0x194 0x5d8 0x000 0x7 0x0
+#define MX35_PAD_RXD2__UART2_RXD_MUX                            0x198 0x5dc 0x000 0x0 0x0
+#define MX35_PAD_RXD2__KPP_ROW_4                                0x198 0x5dc 0x980 0x4 0x0
+#define MX35_PAD_RXD2__GPIO3_10                                 0x198 0x5dc 0x8ec 0x5 0x0
+#define MX35_PAD_TXD2__UART2_TXD_MUX                            0x19c 0x5e0 0x000 0x0 0x0
+#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK                       0x19c 0x5e0 0x994 0x1 0x2
+#define MX35_PAD_TXD2__KPP_ROW_5                                0x19c 0x5e0 0x984 0x4 0x0
+#define MX35_PAD_TXD2__GPIO3_11                                 0x19c 0x5e0 0x8f0 0x5 0x0
+#define MX35_PAD_RTS2__UART2_RTS                                0x1a0 0x5e4 0x000 0x0 0x0
+#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1                          0x1a0 0x5e4 0x998 0x1 0x1
+#define MX35_PAD_RTS2__CAN2_RXCAN                               0x1a0 0x5e4 0x7cc 0x2 0x1
+#define MX35_PAD_RTS2__IPU_CSI_D_2                              0x1a0 0x5e4 0x938 0x3 0x1
+#define MX35_PAD_RTS2__KPP_ROW_6                                0x1a0 0x5e4 0x988 0x4 0x0
+#define MX35_PAD_RTS2__GPIO3_12                                 0x1a0 0x5e4 0x8f4 0x5 0x0
+#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC                          0x1a0 0x5e4 0x000 0x6 0x0
+#define MX35_PAD_RTS2__UART3_RXD_MUX                            0x1a0 0x5e4 0x9a0 0x7 0x0
+#define MX35_PAD_CTS2__UART2_CTS                                0x1a4 0x5e8 0x000 0x0 0x0
+#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1                         0x1a4 0x5e8 0x000 0x1 0x0
+#define MX35_PAD_CTS2__CAN2_TXCAN                               0x1a4 0x5e8 0x000 0x2 0x0
+#define MX35_PAD_CTS2__IPU_CSI_D_3                              0x1a4 0x5e8 0x93c 0x3 0x1
+#define MX35_PAD_CTS2__KPP_ROW_7                                0x1a4 0x5e8 0x98c 0x4 0x0
+#define MX35_PAD_CTS2__GPIO3_13                                 0x1a4 0x5e8 0x8f8 0x5 0x0
+#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS                         0x1a4 0x5e8 0x000 0x6 0x0
+#define MX35_PAD_CTS2__UART3_TXD_MUX                            0x1a4 0x5e8 0x000 0x7 0x0
+#define MX35_PAD_RTCK__ARM11P_TOP_RTCK                          0x000 0x5ec 0x000 0x0 0x0
+#define MX35_PAD_TCK__SJC_TCK                                   0x000 0x5f0 0x000 0x0 0x0
+#define MX35_PAD_TMS__SJC_TMS                                   0x000 0x5f4 0x000 0x0 0x0
+#define MX35_PAD_TDI__SJC_TDI                                   0x000 0x5f8 0x000 0x0 0x0
+#define MX35_PAD_TDO__SJC_TDO                                   0x000 0x5fc 0x000 0x0 0x0
+#define MX35_PAD_TRSTB__SJC_TRSTB                               0x000 0x600 0x000 0x0 0x0
+#define MX35_PAD_DE_B__SJC_DE_B                                 0x000 0x604 0x000 0x0 0x0
+#define MX35_PAD_SJC_MOD__SJC_MOD                               0x000 0x608 0x000 0x0 0x0
+#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR                 0x1a8 0x60c 0x000 0x0 0x0
+#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR                  0x1a8 0x60c 0x000 0x1 0x0
+#define MX35_PAD_USBOTG_PWR__GPIO3_14                           0x1a8 0x60c 0x8fc 0x5 0x0
+#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC                   0x1ac 0x610 0x000 0x0 0x0
+#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC                    0x1ac 0x610 0x9f4 0x1 0x1
+#define MX35_PAD_USBOTG_OC__GPIO3_15                            0x1ac 0x610 0x900 0x5 0x0
+#define MX35_PAD_LD0__IPU_DISPB_DAT_0                           0x1b0 0x614 0x000 0x0 0x0
+#define MX35_PAD_LD0__GPIO2_0                                   0x1b0 0x614 0x868 0x5 0x1
+#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0                      0x1b0 0x614 0x000 0x6 0x0
+#define MX35_PAD_LD1__IPU_DISPB_DAT_1                           0x1b4 0x618 0x000 0x0 0x0
+#define MX35_PAD_LD1__GPIO2_1                                   0x1b4 0x618 0x894 0x5 0x0
+#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1                      0x1b4 0x618 0x000 0x6 0x0
+#define MX35_PAD_LD2__IPU_DISPB_DAT_2                           0x1b8 0x61c 0x000 0x0 0x0
+#define MX35_PAD_LD2__GPIO2_2                                   0x1b8 0x61c 0x8c0 0x5 0x0
+#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2                      0x1b8 0x61c 0x000 0x6 0x0
+#define MX35_PAD_LD3__IPU_DISPB_DAT_3                           0x1bc 0x620 0x000 0x0 0x0
+#define MX35_PAD_LD3__GPIO2_3                                   0x1bc 0x620 0x8cc 0x5 0x0
+#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3                      0x1bc 0x620 0x000 0x6 0x0
+#define MX35_PAD_LD4__IPU_DISPB_DAT_4                           0x1c0 0x624 0x000 0x0 0x0
+#define MX35_PAD_LD4__GPIO2_4                                   0x1c0 0x624 0x8d0 0x5 0x0
+#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4                      0x1c0 0x624 0x000 0x6 0x0
+#define MX35_PAD_LD5__IPU_DISPB_DAT_5                           0x1c4 0x628 0x000 0x0 0x0
+#define MX35_PAD_LD5__GPIO2_5                                   0x1c4 0x628 0x8d4 0x5 0x0
+#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5                      0x1c4 0x628 0x000 0x6 0x0
+#define MX35_PAD_LD6__IPU_DISPB_DAT_6                           0x1c8 0x62c 0x000 0x0 0x0
+#define MX35_PAD_LD6__GPIO2_6                                   0x1c8 0x62c 0x8d8 0x5 0x0
+#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6                      0x1c8 0x62c 0x000 0x6 0x0
+#define MX35_PAD_LD7__IPU_DISPB_DAT_7                           0x1cc 0x630 0x000 0x0 0x0
+#define MX35_PAD_LD7__GPIO2_7                                   0x1cc 0x630 0x8dc 0x5 0x0
+#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7                      0x1cc 0x630 0x000 0x6 0x0
+#define MX35_PAD_LD8__IPU_DISPB_DAT_8                           0x1d0 0x634 0x000 0x0 0x0
+#define MX35_PAD_LD8__GPIO2_8                                   0x1d0 0x634 0x8e0 0x5 0x0
+#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8                      0x1d0 0x634 0x000 0x6 0x0
+#define MX35_PAD_LD9__IPU_DISPB_DAT_9                           0x1d4 0x638 0x000 0x0 0x0
+#define MX35_PAD_LD9__GPIO2_9                                   0x1d4 0x638 0x8e4 0x5 0x0
+#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9                      0x1d4 0x638 0x000 0x6 0x0
+#define MX35_PAD_LD10__IPU_DISPB_DAT_10                         0x1d8 0x63c 0x000 0x0 0x0
+#define MX35_PAD_LD10__GPIO2_10                                 0x1d8 0x63c 0x86c 0x5 0x0
+#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10                    0x1d8 0x63c 0x000 0x6 0x0
+#define MX35_PAD_LD11__IPU_DISPB_DAT_11                         0x1dc 0x640 0x000 0x0 0x0
+#define MX35_PAD_LD11__GPIO2_11                                 0x1dc 0x640 0x870 0x5 0x0
+#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11                    0x1dc 0x640 0x000 0x6 0x0
+#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4                       0x1dc 0x640 0x000 0x7 0x0
+#define MX35_PAD_LD12__IPU_DISPB_DAT_12                         0x1e0 0x644 0x000 0x0 0x0
+#define MX35_PAD_LD12__GPIO2_12                                 0x1e0 0x644 0x874 0x5 0x0
+#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12                    0x1e0 0x644 0x000 0x6 0x0
+#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5                       0x1e0 0x644 0x000 0x7 0x0
+#define MX35_PAD_LD13__IPU_DISPB_DAT_13                         0x1e4 0x648 0x000 0x0 0x0
+#define MX35_PAD_LD13__GPIO2_13                                 0x1e4 0x648 0x878 0x5 0x0
+#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13                    0x1e4 0x648 0x000 0x6 0x0
+#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6                       0x1e4 0x648 0x000 0x7 0x0
+#define MX35_PAD_LD14__IPU_DISPB_DAT_14                         0x1e8 0x64c 0x000 0x0 0x0
+#define MX35_PAD_LD14__GPIO2_14                                 0x1e8 0x64c 0x87c 0x5 0x0
+#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0          0x1e8 0x64c 0x000 0x6 0x0
+#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7                       0x1e8 0x64c 0x000 0x7 0x0
+#define MX35_PAD_LD15__IPU_DISPB_DAT_15                         0x1ec 0x650 0x000 0x0 0x0
+#define MX35_PAD_LD15__GPIO2_15                                 0x1ec 0x650 0x880 0x5 0x0
+#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1          0x1ec 0x650 0x000 0x6 0x0
+#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8                       0x1ec 0x650 0x000 0x7 0x0
+#define MX35_PAD_LD16__IPU_DISPB_DAT_16                         0x1f0 0x654 0x000 0x0 0x0
+#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC                      0x1f0 0x654 0x928 0x2 0x0
+#define MX35_PAD_LD16__GPIO2_16                                 0x1f0 0x654 0x884 0x5 0x0
+#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2          0x1f0 0x654 0x000 0x6 0x0
+#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9                       0x1f0 0x654 0x000 0x7 0x0
+#define MX35_PAD_LD17__IPU_DISPB_DAT_17                         0x1f4 0x658 0x000 0x0 0x0
+#define MX35_PAD_LD17__IPU_DISPB_CS2                            0x1f4 0x658 0x000 0x2 0x0
+#define MX35_PAD_LD17__GPIO2_17                                 0x1f4 0x658 0x888 0x5 0x0
+#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3          0x1f4 0x658 0x000 0x6 0x0
+#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10                      0x1f4 0x658 0x000 0x7 0x0
+#define MX35_PAD_LD18__IPU_DISPB_DAT_18                         0x1f8 0x65c 0x000 0x0 0x0
+#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC                       0x1f8 0x65c 0x924 0x1 0x1
+#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC                      0x1f8 0x65c 0x928 0x2 0x1
+#define MX35_PAD_LD18__ESDHC3_CMD                               0x1f8 0x65c 0x818 0x3 0x0
+#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3                    0x1f8 0x65c 0x9b0 0x4 0x0
+#define MX35_PAD_LD18__GPIO3_24                                 0x1f8 0x65c 0x000 0x5 0x0
+#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4          0x1f8 0x65c 0x000 0x6 0x0
+#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11                      0x1f8 0x65c 0x000 0x7 0x0
+#define MX35_PAD_LD19__IPU_DISPB_DAT_19                         0x1fc 0x660 0x000 0x0 0x0
+#define MX35_PAD_LD19__IPU_DISPB_BCLK                           0x1fc 0x660 0x000 0x1 0x0
+#define MX35_PAD_LD19__IPU_DISPB_CS1                            0x1fc 0x660 0x000 0x2 0x0
+#define MX35_PAD_LD19__ESDHC3_CLK                               0x1fc 0x660 0x814 0x3 0x0
+#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR                       0x1fc 0x660 0x9c4 0x4 0x0
+#define MX35_PAD_LD19__GPIO3_25                                 0x1fc 0x660 0x000 0x5 0x0
+#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5          0x1fc 0x660 0x000 0x6 0x0
+#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12                      0x1fc 0x660 0x000 0x7 0x0
+#define MX35_PAD_LD20__IPU_DISPB_DAT_20                         0x200 0x664 0x000 0x0 0x0
+#define MX35_PAD_LD20__IPU_DISPB_CS0                            0x200 0x664 0x000 0x1 0x0
+#define MX35_PAD_LD20__IPU_DISPB_SD_CLK                         0x200 0x664 0x000 0x2 0x0
+#define MX35_PAD_LD20__ESDHC3_DAT0                              0x200 0x664 0x81c 0x3 0x0
+#define MX35_PAD_LD20__GPIO3_26                                 0x200 0x664 0x000 0x5 0x0
+#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3            0x200 0x664 0x000 0x6 0x0
+#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13                      0x200 0x664 0x000 0x7 0x0
+#define MX35_PAD_LD21__IPU_DISPB_DAT_21                         0x204 0x668 0x000 0x0 0x0
+#define MX35_PAD_LD21__IPU_DISPB_PAR_RS                         0x204 0x668 0x000 0x1 0x0
+#define MX35_PAD_LD21__IPU_DISPB_SER_RS                         0x204 0x668 0x000 0x2 0x0
+#define MX35_PAD_LD21__ESDHC3_DAT1                              0x204 0x668 0x820 0x3 0x0
+#define MX35_PAD_LD21__USB_TOP_USBOTG_STP                       0x204 0x668 0x000 0x4 0x0
+#define MX35_PAD_LD21__GPIO3_27                                 0x204 0x668 0x000 0x5 0x0
+#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL             0x204 0x668 0x000 0x6 0x0
+#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14                      0x204 0x668 0x000 0x7 0x0
+#define MX35_PAD_LD22__IPU_DISPB_DAT_22                         0x208 0x66c 0x000 0x0 0x0
+#define MX35_PAD_LD22__IPU_DISPB_WR                             0x208 0x66c 0x000 0x1 0x0
+#define MX35_PAD_LD22__IPU_DISPB_SD_D_I                         0x208 0x66c 0x92c 0x2 0x0
+#define MX35_PAD_LD22__ESDHC3_DAT2                              0x208 0x66c 0x824 0x3 0x0
+#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT                       0x208 0x66c 0x9c8 0x4 0x0
+#define MX35_PAD_LD22__GPIO3_28                                 0x208 0x66c 0x000 0x5 0x0
+#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR                     0x208 0x66c 0x000 0x6 0x0
+#define MX35_PAD_LD22__ARM11P_TOP_TRCTL                         0x208 0x66c 0x000 0x7 0x0
+#define MX35_PAD_LD23__IPU_DISPB_DAT_23                         0x20c 0x670 0x000 0x0 0x0
+#define MX35_PAD_LD23__IPU_DISPB_RD                             0x20c 0x670 0x000 0x1 0x0
+#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO                        0x20c 0x670 0x92c 0x2 0x1
+#define MX35_PAD_LD23__ESDHC3_DAT3                              0x20c 0x670 0x828 0x3 0x0
+#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7                    0x20c 0x670 0x9c0 0x4 0x0
+#define MX35_PAD_LD23__GPIO3_29                                 0x20c 0x670 0x000 0x5 0x0
+#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS                 0x20c 0x670 0x000 0x6 0x0
+#define MX35_PAD_LD23__ARM11P_TOP_TRCLK                         0x20c 0x670 0x000 0x7 0x0
+#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC                   0x210 0x674 0x000 0x0 0x0
+#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO                    0x210 0x674 0x92c 0x2 0x2
+#define MX35_PAD_D3_HSYNC__GPIO3_30                             0x210 0x674 0x000 0x5 0x0
+#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE            0x210 0x674 0x000 0x6 0x0
+#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15                  0x210 0x674 0x000 0x7 0x0
+#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK                   0x214 0x678 0x000 0x0 0x0
+#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK                   0x214 0x678 0x000 0x2 0x0
+#define MX35_PAD_D3_FPSHIFT__GPIO3_31                           0x214 0x678 0x000 0x5 0x0
+#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0      0x214 0x678 0x000 0x6 0x0
+#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16                0x214 0x678 0x000 0x7 0x0
+#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY                     0x218 0x67c 0x000 0x0 0x0
+#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O                      0x218 0x67c 0x000 0x2 0x0
+#define MX35_PAD_D3_DRDY__GPIO1_0                               0x218 0x67c 0x82c 0x5 0x2
+#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1         0x218 0x67c 0x000 0x6 0x0
+#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17                   0x218 0x67c 0x000 0x7 0x0
+#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR                      0x21c 0x680 0x000 0x0 0x0
+#define MX35_PAD_CONTRAST__GPIO1_1                              0x21c 0x680 0x838 0x5 0x2
+#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2        0x21c 0x680 0x000 0x6 0x0
+#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18                  0x21c 0x680 0x000 0x7 0x0
+#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC                   0x220 0x684 0x000 0x0 0x0
+#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1                        0x220 0x684 0x000 0x2 0x0
+#define MX35_PAD_D3_VSYNC__GPIO1_2                              0x220 0x684 0x848 0x5 0x1
+#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD                     0x220 0x684 0x000 0x6 0x0
+#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19                  0x220 0x684 0x000 0x7 0x0
+#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV                       0x224 0x688 0x000 0x0 0x0
+#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS                       0x224 0x688 0x000 0x2 0x0
+#define MX35_PAD_D3_REV__GPIO1_3                                0x224 0x688 0x84c 0x5 0x1
+#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB                     0x224 0x688 0x000 0x6 0x0
+#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20                    0x224 0x688 0x000 0x7 0x0
+#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS                       0x228 0x68c 0x000 0x0 0x0
+#define MX35_PAD_D3_CLS__IPU_DISPB_CS2                          0x228 0x68c 0x000 0x2 0x0
+#define MX35_PAD_D3_CLS__GPIO1_4                                0x228 0x68c 0x850 0x5 0x2
+#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0                0x228 0x68c 0x000 0x6 0x0
+#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21                    0x228 0x68c 0x000 0x7 0x0
+#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL                       0x22c 0x690 0x000 0x0 0x0
+#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC                    0x22c 0x690 0x928 0x2 0x2
+#define MX35_PAD_D3_SPL__GPIO1_5                                0x22c 0x690 0x854 0x5 0x2
+#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1                0x22c 0x690 0x000 0x6 0x0
+#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22                    0x22c 0x690 0x000 0x7 0x0
+#define MX35_PAD_SD1_CMD__ESDHC1_CMD                            0x230 0x694 0x000 0x0 0x0
+#define MX35_PAD_SD1_CMD__MSHC_SCLK                             0x230 0x694 0x000 0x1 0x0
+#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC                    0x230 0x694 0x924 0x3 0x2
+#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4                 0x230 0x694 0x9b4 0x4 0x0
+#define MX35_PAD_SD1_CMD__GPIO1_6                               0x230 0x694 0x858 0x5 0x2
+#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL                      0x230 0x694 0x000 0x7 0x0
+#define MX35_PAD_SD1_CLK__ESDHC1_CLK                            0x234 0x698 0x000 0x0 0x0
+#define MX35_PAD_SD1_CLK__MSHC_BS                               0x234 0x698 0x000 0x1 0x0
+#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK                        0x234 0x698 0x000 0x3 0x0
+#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5                 0x234 0x698 0x9b8 0x4 0x0
+#define MX35_PAD_SD1_CLK__GPIO1_7                               0x234 0x698 0x85c 0x5 0x2
+#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK                      0x234 0x698 0x000 0x7 0x0
+#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0                         0x238 0x69c 0x000 0x0 0x0
+#define MX35_PAD_SD1_DATA0__MSHC_DATA_0                         0x238 0x69c 0x000 0x1 0x0
+#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0                       0x238 0x69c 0x000 0x3 0x0
+#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6               0x238 0x69c 0x9bc 0x4 0x0
+#define MX35_PAD_SD1_DATA0__GPIO1_8                             0x238 0x69c 0x860 0x5 0x2
+#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23                 0x238 0x69c 0x000 0x7 0x0
+#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1                         0x23c 0x6a0 0x000 0x0 0x0
+#define MX35_PAD_SD1_DATA1__MSHC_DATA_1                         0x23c 0x6a0 0x000 0x1 0x0
+#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS                    0x23c 0x6a0 0x000 0x3 0x0
+#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0               0x23c 0x6a0 0x9a4 0x4 0x0
+#define MX35_PAD_SD1_DATA1__GPIO1_9                             0x23c 0x6a0 0x864 0x5 0x1
+#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24                 0x23c 0x6a0 0x000 0x7 0x0
+#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2                         0x240 0x6a4 0x000 0x0 0x0
+#define MX35_PAD_SD1_DATA2__MSHC_DATA_2                         0x240 0x6a4 0x000 0x1 0x0
+#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR                        0x240 0x6a4 0x000 0x3 0x0
+#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1               0x240 0x6a4 0x9a8 0x4 0x0
+#define MX35_PAD_SD1_DATA2__GPIO1_10                            0x240 0x6a4 0x830 0x5 0x1
+#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25                 0x240 0x6a4 0x000 0x7 0x0
+#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3                         0x244 0x6a8 0x000 0x0 0x0
+#define MX35_PAD_SD1_DATA3__MSHC_DATA_3                         0x244 0x6a8 0x000 0x1 0x0
+#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD                        0x244 0x6a8 0x000 0x3 0x0
+#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2               0x244 0x6a8 0x9ac 0x4 0x0
+#define MX35_PAD_SD1_DATA3__GPIO1_11                            0x244 0x6a8 0x834 0x5 0x1
+#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26                 0x244 0x6a8 0x000 0x7 0x0
+#define MX35_PAD_SD2_CMD__ESDHC2_CMD                            0x248 0x6ac 0x000 0x0 0x0
+#define MX35_PAD_SD2_CMD__I2C3_SCL                              0x248 0x6ac 0x91c 0x1 0x2
+#define MX35_PAD_SD2_CMD__ESDHC1_DAT4                           0x248 0x6ac 0x804 0x2 0x0
+#define MX35_PAD_SD2_CMD__IPU_CSI_D_2                           0x248 0x6ac 0x938 0x3 0x2
+#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4                  0x248 0x6ac 0x9dc 0x4 0x0
+#define MX35_PAD_SD2_CMD__GPIO2_0                               0x248 0x6ac 0x868 0x5 0x2
+#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1                      0x248 0x6ac 0x000 0x6 0x0
+#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC                   0x248 0x6ac 0x928 0x7 0x3
+#define MX35_PAD_SD2_CLK__ESDHC2_CLK                            0x24c 0x6b0 0x000 0x0 0x0
+#define MX35_PAD_SD2_CLK__I2C3_SDA                              0x24c 0x6b0 0x920 0x1 0x2
+#define MX35_PAD_SD2_CLK__ESDHC1_DAT5                           0x24c 0x6b0 0x808 0x2 0x0
+#define MX35_PAD_SD2_CLK__IPU_CSI_D_3                           0x24c 0x6b0 0x93c 0x3 0x2
+#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5                  0x24c 0x6b0 0x9e0 0x4 0x0
+#define MX35_PAD_SD2_CLK__GPIO2_1                               0x24c 0x6b0 0x894 0x5 0x1
+#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1                       0x24c 0x6b0 0x998 0x6 0x2
+#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2                         0x24c 0x6b0 0x000 0x7 0x0
+#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0                         0x250 0x6b4 0x000 0x0 0x0
+#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX                       0x250 0x6b4 0x9a0 0x1 0x1
+#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6                         0x250 0x6b4 0x80c 0x2 0x0
+#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4                         0x250 0x6b4 0x940 0x3 0x1
+#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6                0x250 0x6b4 0x9e4 0x4 0x0
+#define MX35_PAD_SD2_DATA0__GPIO2_2                             0x250 0x6b4 0x8c0 0x5 0x1
+#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK                  0x250 0x6b4 0x994 0x6 0x3
+#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1                         0x254 0x6b8 0x000 0x0 0x0
+#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX                       0x254 0x6b8 0x000 0x1 0x0
+#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7                         0x254 0x6b8 0x810 0x2 0x0
+#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5                         0x254 0x6b8 0x944 0x3 0x1
+#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0                0x254 0x6b8 0x9cc 0x4 0x0
+#define MX35_PAD_SD2_DATA1__GPIO2_3                             0x254 0x6b8 0x8cc 0x5 0x1
+#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2                         0x258 0x6bc 0x000 0x0 0x0
+#define MX35_PAD_SD2_DATA2__UART3_RTS                           0x258 0x6bc 0x99c 0x1 0x0
+#define MX35_PAD_SD2_DATA2__CAN1_RXCAN                          0x258 0x6bc 0x7c8 0x2 0x1
+#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6                         0x258 0x6bc 0x948 0x3 0x1
+#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1                0x258 0x6bc 0x9d0 0x4 0x0
+#define MX35_PAD_SD2_DATA2__GPIO2_4                             0x258 0x6bc 0x8d0 0x5 0x1
+#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3                         0x25c 0x6c0 0x000 0x0 0x0
+#define MX35_PAD_SD2_DATA3__UART3_CTS                           0x25c 0x6c0 0x000 0x1 0x0
+#define MX35_PAD_SD2_DATA3__CAN1_TXCAN                          0x25c 0x6c0 0x000 0x2 0x0
+#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7                         0x25c 0x6c0 0x94c 0x3 0x1
+#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2                0x25c 0x6c0 0x9d4 0x4 0x0
+#define MX35_PAD_SD2_DATA3__GPIO2_5                             0x25c 0x6c0 0x8d4 0x5 0x1
+#define MX35_PAD_ATA_CS0__ATA_CS0                               0x260 0x6c4 0x000 0x0 0x0
+#define MX35_PAD_ATA_CS0__CSPI1_SS3                             0x260 0x6c4 0x7dc 0x1 0x1
+#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1                         0x260 0x6c4 0x000 0x3 0x0
+#define MX35_PAD_ATA_CS0__GPIO2_6                               0x260 0x6c4 0x8d8 0x5 0x1
+#define MX35_PAD_ATA_CS0__IPU_DIAGB_0                           0x260 0x6c4 0x000 0x6 0x0
+#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0             0x260 0x6c4 0x000 0x7 0x0
+#define MX35_PAD_ATA_CS1__ATA_CS1                               0x264 0x6c8 0x000 0x0 0x0
+#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2                         0x264 0x6c8 0x000 0x3 0x0
+#define MX35_PAD_ATA_CS1__CSPI2_SS0                             0x264 0x6c8 0x7f0 0x4 0x1
+#define MX35_PAD_ATA_CS1__GPIO2_7                               0x264 0x6c8 0x8dc 0x5 0x1
+#define MX35_PAD_ATA_CS1__IPU_DIAGB_1                           0x264 0x6c8 0x000 0x6 0x0
+#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1             0x264 0x6c8 0x000 0x7 0x0
+#define MX35_PAD_ATA_DIOR__ATA_DIOR                             0x268 0x6cc 0x000 0x0 0x0
+#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0                          0x268 0x6cc 0x81c 0x1 0x1
+#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR                   0x268 0x6cc 0x9c4 0x2 0x1
+#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0                        0x268 0x6cc 0x000 0x3 0x0
+#define MX35_PAD_ATA_DIOR__CSPI2_SS1                            0x268 0x6cc 0x7f4 0x4 0x1
+#define MX35_PAD_ATA_DIOR__GPIO2_8                              0x268 0x6cc 0x8e0 0x5 0x1
+#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2                          0x268 0x6cc 0x000 0x6 0x0
+#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2            0x268 0x6cc 0x000 0x7 0x0
+#define MX35_PAD_ATA_DIOW__ATA_DIOW                             0x26c 0x6d0 0x000 0x0 0x0
+#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1                          0x26c 0x6d0 0x820 0x1 0x1
+#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP                   0x26c 0x6d0 0x000 0x2 0x0
+#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1                        0x26c 0x6d0 0x000 0x3 0x0
+#define MX35_PAD_ATA_DIOW__CSPI2_MOSI                           0x26c 0x6d0 0x7ec 0x4 0x2
+#define MX35_PAD_ATA_DIOW__GPIO2_9                              0x26c 0x6d0 0x8e4 0x5 0x1
+#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3                          0x26c 0x6d0 0x000 0x6 0x0
+#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3            0x26c 0x6d0 0x000 0x7 0x0
+#define MX35_PAD_ATA_DMACK__ATA_DMACK                           0x270 0x6d4 0x000 0x0 0x0
+#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2                         0x270 0x6d4 0x824 0x1 0x1
+#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT                  0x270 0x6d4 0x9c8 0x2 0x1
+#define MX35_PAD_ATA_DMACK__CSPI2_MISO                          0x270 0x6d4 0x7e8 0x4 0x2
+#define MX35_PAD_ATA_DMACK__GPIO2_10                            0x270 0x6d4 0x86c 0x5 0x1
+#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4                         0x270 0x6d4 0x000 0x6 0x0
+#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0           0x270 0x6d4 0x000 0x7 0x0
+#define MX35_PAD_ATA_RESET_B__ATA_RESET_B                       0x274 0x6d8 0x000 0x0 0x0
+#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3                       0x274 0x6d8 0x828 0x1 0x1
+#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0             0x274 0x6d8 0x9a4 0x2 0x1
+#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O                  0x274 0x6d8 0x000 0x3 0x0
+#define MX35_PAD_ATA_RESET_B__CSPI2_RDY                         0x274 0x6d8 0x7e4 0x4 0x2
+#define MX35_PAD_ATA_RESET_B__GPIO2_11                          0x274 0x6d8 0x870 0x5 0x1
+#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5                       0x274 0x6d8 0x000 0x6 0x0
+#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1         0x274 0x6d8 0x000 0x7 0x0
+#define MX35_PAD_ATA_IORDY__ATA_IORDY                           0x278 0x6dc 0x000 0x0 0x0
+#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4                         0x278 0x6dc 0x000 0x1 0x0
+#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1               0x278 0x6dc 0x9a8 0x2 0x1
+#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO                   0x278 0x6dc 0x92c 0x3 0x3
+#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4                         0x278 0x6dc 0x000 0x4 0x0
+#define MX35_PAD_ATA_IORDY__GPIO2_12                            0x278 0x6dc 0x874 0x5 0x1
+#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6                         0x278 0x6dc 0x000 0x6 0x0
+#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2           0x278 0x6dc 0x000 0x7 0x0
+#define MX35_PAD_ATA_DATA0__ATA_DATA_0                          0x27c 0x6e0 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5                         0x27c 0x6e0 0x000 0x1 0x0
+#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2               0x27c 0x6e0 0x9ac 0x2 0x1
+#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC                 0x27c 0x6e0 0x928 0x3 0x4
+#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5                         0x27c 0x6e0 0x000 0x4 0x0
+#define MX35_PAD_ATA_DATA0__GPIO2_13                            0x27c 0x6e0 0x878 0x5 0x1
+#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7                         0x27c 0x6e0 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3           0x27c 0x6e0 0x000 0x7 0x0
+#define MX35_PAD_ATA_DATA1__ATA_DATA_1                          0x280 0x6e4 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6                         0x280 0x6e4 0x000 0x1 0x0
+#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3               0x280 0x6e4 0x9b0 0x2 0x1
+#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK                    0x280 0x6e4 0x000 0x3 0x0
+#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6                         0x280 0x6e4 0x000 0x4 0x0
+#define MX35_PAD_ATA_DATA1__GPIO2_14                            0x280 0x6e4 0x87c 0x5 0x1
+#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8                         0x280 0x6e4 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27                 0x280 0x6e4 0x000 0x7 0x0
+#define MX35_PAD_ATA_DATA2__ATA_DATA_2                          0x284 0x6e8 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7                         0x284 0x6e8 0x000 0x1 0x0
+#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4               0x284 0x6e8 0x9b4 0x2 0x1
+#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS                    0x284 0x6e8 0x000 0x3 0x0
+#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7                         0x284 0x6e8 0x000 0x4 0x0
+#define MX35_PAD_ATA_DATA2__GPIO2_15                            0x284 0x6e8 0x880 0x5 0x1
+#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9                         0x284 0x6e8 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28                 0x284 0x6e8 0x000 0x7 0x0
+#define MX35_PAD_ATA_DATA3__ATA_DATA_3                          0x288 0x6ec 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA3__ESDHC3_CLK                          0x288 0x6ec 0x814 0x1 0x1
+#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5               0x288 0x6ec 0x9b8 0x2 0x1
+#define MX35_PAD_ATA_DATA3__CSPI2_SCLK                          0x288 0x6ec 0x7e0 0x4 0x2
+#define MX35_PAD_ATA_DATA3__GPIO2_16                            0x288 0x6ec 0x884 0x5 0x1
+#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10                        0x288 0x6ec 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29                 0x288 0x6ec 0x000 0x7 0x0
+#define MX35_PAD_ATA_DATA4__ATA_DATA_4                          0x28c 0x6f0 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA4__ESDHC3_CMD                          0x28c 0x6f0 0x818 0x1 0x1
+#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6               0x28c 0x6f0 0x9bc 0x2 0x1
+#define MX35_PAD_ATA_DATA4__GPIO2_17                            0x28c 0x6f0 0x888 0x5 0x1
+#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11                        0x28c 0x6f0 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30                 0x28c 0x6f0 0x000 0x7 0x0
+#define MX35_PAD_ATA_DATA5__ATA_DATA_5                          0x290 0x6f4 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7               0x290 0x6f4 0x9c0 0x2 0x1
+#define MX35_PAD_ATA_DATA5__GPIO2_18                            0x290 0x6f4 0x88c 0x5 0x1
+#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12                        0x290 0x6f4 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31                 0x290 0x6f4 0x000 0x7 0x0
+#define MX35_PAD_ATA_DATA6__ATA_DATA_6                          0x294 0x6f8 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA6__CAN1_TXCAN                          0x294 0x6f8 0x000 0x1 0x0
+#define MX35_PAD_ATA_DATA6__UART1_DTR                           0x294 0x6f8 0x000 0x2 0x0
+#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD                     0x294 0x6f8 0x7b4 0x3 0x0
+#define MX35_PAD_ATA_DATA6__GPIO2_19                            0x294 0x6f8 0x890 0x5 0x1
+#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13                        0x294 0x6f8 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA7__ATA_DATA_7                          0x298 0x6fc 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA7__CAN1_RXCAN                          0x298 0x6fc 0x7c8 0x1 0x2
+#define MX35_PAD_ATA_DATA7__UART1_DSR                           0x298 0x6fc 0x000 0x2 0x0
+#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD                     0x298 0x6fc 0x7b0 0x3 0x0
+#define MX35_PAD_ATA_DATA7__GPIO2_20                            0x298 0x6fc 0x898 0x5 0x1
+#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14                        0x298 0x6fc 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA8__ATA_DATA_8                          0x29c 0x700 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA8__UART3_RTS                           0x29c 0x700 0x99c 0x1 0x1
+#define MX35_PAD_ATA_DATA8__UART1_RI                            0x29c 0x700 0x000 0x2 0x0
+#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC                     0x29c 0x700 0x7c0 0x3 0x0
+#define MX35_PAD_ATA_DATA8__GPIO2_21                            0x29c 0x700 0x89c 0x5 0x1
+#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15                        0x29c 0x700 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA9__ATA_DATA_9                          0x2a0 0x704 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA9__UART3_CTS                           0x2a0 0x704 0x000 0x1 0x0
+#define MX35_PAD_ATA_DATA9__UART1_DCD                           0x2a0 0x704 0x000 0x2 0x0
+#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS                    0x2a0 0x704 0x7c4 0x3 0x0
+#define MX35_PAD_ATA_DATA9__GPIO2_22                            0x2a0 0x704 0x8a0 0x5 0x1
+#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16                        0x2a0 0x704 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA10__ATA_DATA_10                        0x2a4 0x708 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX                      0x2a4 0x708 0x9a0 0x1 0x2
+#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC                    0x2a4 0x708 0x7b8 0x3 0x0
+#define MX35_PAD_ATA_DATA10__GPIO2_23                           0x2a4 0x708 0x8a4 0x5 0x1
+#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17                       0x2a4 0x708 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA11__ATA_DATA_11                        0x2a8 0x70c 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX                      0x2a8 0x70c 0x000 0x1 0x0
+#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS                   0x2a8 0x70c 0x7bc 0x3 0x0
+#define MX35_PAD_ATA_DATA11__GPIO2_24                           0x2a8 0x70c 0x8a8 0x5 0x1
+#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18                       0x2a8 0x70c 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA12__ATA_DATA_12                        0x2ac 0x710 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA12__I2C3_SCL                           0x2ac 0x710 0x91c 0x1 0x3
+#define MX35_PAD_ATA_DATA12__GPIO2_25                           0x2ac 0x710 0x8ac 0x5 0x1
+#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19                       0x2ac 0x710 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA13__ATA_DATA_13                        0x2b0 0x714 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA13__I2C3_SDA                           0x2b0 0x714 0x920 0x1 0x3
+#define MX35_PAD_ATA_DATA13__GPIO2_26                           0x2b0 0x714 0x8b0 0x5 0x1
+#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20                       0x2b0 0x714 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA14__ATA_DATA_14                        0x2b4 0x718 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0                        0x2b4 0x718 0x930 0x1 0x2
+#define MX35_PAD_ATA_DATA14__KPP_ROW_0                          0x2b4 0x718 0x970 0x3 0x2
+#define MX35_PAD_ATA_DATA14__GPIO2_27                           0x2b4 0x718 0x8b4 0x5 0x1
+#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21                       0x2b4 0x718 0x000 0x6 0x0
+#define MX35_PAD_ATA_DATA15__ATA_DATA_15                        0x2b8 0x71c 0x000 0x0 0x0
+#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1                        0x2b8 0x71c 0x934 0x1 0x2
+#define MX35_PAD_ATA_DATA15__KPP_ROW_1                          0x2b8 0x71c 0x974 0x3 0x2
+#define MX35_PAD_ATA_DATA15__GPIO2_28                           0x2b8 0x71c 0x8b8 0x5 0x1
+#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22                       0x2b8 0x71c 0x000 0x6 0x0
+#define MX35_PAD_ATA_INTRQ__ATA_INTRQ                           0x2bc 0x720 0x000 0x0 0x0
+#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2                         0x2bc 0x720 0x938 0x1 0x3
+#define MX35_PAD_ATA_INTRQ__KPP_ROW_2                           0x2bc 0x720 0x978 0x3 0x2
+#define MX35_PAD_ATA_INTRQ__GPIO2_29                            0x2bc 0x720 0x8bc 0x5 0x1
+#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23                        0x2bc 0x720 0x000 0x6 0x0
+#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN                     0x2c0 0x724 0x000 0x0 0x0
+#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3                       0x2c0 0x724 0x93c 0x1 0x3
+#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3                         0x2c0 0x724 0x97c 0x3 0x2
+#define MX35_PAD_ATA_BUFF_EN__GPIO2_30                          0x2c0 0x724 0x8c4 0x5 0x1
+#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24                      0x2c0 0x724 0x000 0x6 0x0
+#define MX35_PAD_ATA_DMARQ__ATA_DMARQ                           0x2c4 0x728 0x000 0x0 0x0
+#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4                         0x2c4 0x728 0x940 0x1 0x2
+#define MX35_PAD_ATA_DMARQ__KPP_COL_0                           0x2c4 0x728 0x950 0x3 0x2
+#define MX35_PAD_ATA_DMARQ__GPIO2_31                            0x2c4 0x728 0x8c8 0x5 0x1
+#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25                        0x2c4 0x728 0x000 0x6 0x0
+#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4                  0x2c4 0x728 0x000 0x7 0x0
+#define MX35_PAD_ATA_DA0__ATA_DA_0                              0x2c8 0x72c 0x000 0x0 0x0
+#define MX35_PAD_ATA_DA0__IPU_CSI_D_5                           0x2c8 0x72c 0x944 0x1 0x2
+#define MX35_PAD_ATA_DA0__KPP_COL_1                             0x2c8 0x72c 0x954 0x3 0x2
+#define MX35_PAD_ATA_DA0__GPIO3_0                               0x2c8 0x72c 0x8e8 0x5 0x1
+#define MX35_PAD_ATA_DA0__IPU_DIAGB_26                          0x2c8 0x72c 0x000 0x6 0x0
+#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5                    0x2c8 0x72c 0x000 0x7 0x0
+#define MX35_PAD_ATA_DA1__ATA_DA_1                              0x2cc 0x730 0x000 0x0 0x0
+#define MX35_PAD_ATA_DA1__IPU_CSI_D_6                           0x2cc 0x730 0x948 0x1 0x2
+#define MX35_PAD_ATA_DA1__KPP_COL_2                             0x2cc 0x730 0x958 0x3 0x2
+#define MX35_PAD_ATA_DA1__GPIO3_1                               0x2cc 0x730 0x000 0x5 0x0
+#define MX35_PAD_ATA_DA1__IPU_DIAGB_27                          0x2cc 0x730 0x000 0x6 0x0
+#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6                    0x2cc 0x730 0x000 0x7 0x0
+#define MX35_PAD_ATA_DA2__ATA_DA_2                              0x2d0 0x734 0x000 0x0 0x0
+#define MX35_PAD_ATA_DA2__IPU_CSI_D_7                           0x2d0 0x734 0x94c 0x1 0x2
+#define MX35_PAD_ATA_DA2__KPP_COL_3                             0x2d0 0x734 0x95c 0x3 0x2
+#define MX35_PAD_ATA_DA2__GPIO3_2                               0x2d0 0x734 0x000 0x5 0x0
+#define MX35_PAD_ATA_DA2__IPU_DIAGB_28                          0x2d0 0x734 0x000 0x6 0x0
+#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7                    0x2d0 0x734 0x000 0x7 0x0
+#define MX35_PAD_MLB_CLK__MLB_MLBCLK                            0x2d4 0x738 0x000 0x0 0x0
+#define MX35_PAD_MLB_CLK__GPIO3_3                               0x2d4 0x738 0x000 0x5 0x0
+#define MX35_PAD_MLB_DAT__MLB_MLBDAT                            0x2d8 0x73c 0x000 0x0 0x0
+#define MX35_PAD_MLB_DAT__GPIO3_4                               0x2d8 0x73c 0x904 0x5 0x1
+#define MX35_PAD_MLB_SIG__MLB_MLBSIG                            0x2dc 0x740 0x000 0x0 0x0
+#define MX35_PAD_MLB_SIG__GPIO3_5                               0x2dc 0x740 0x908 0x5 0x1
+#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK                         0x2e0 0x744 0x000 0x0 0x0
+#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4                        0x2e0 0x744 0x804 0x1 0x1
+#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX                      0x2e0 0x744 0x9a0 0x2 0x3
+#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR                  0x2e0 0x744 0x9ec 0x3 0x1
+#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI                         0x2e0 0x744 0x7ec 0x4 0x3
+#define MX35_PAD_FEC_TX_CLK__GPIO3_6                            0x2e0 0x744 0x90c 0x5 0x1
+#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC                0x2e0 0x744 0x928 0x6 0x5
+#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0               0x2e0 0x744 0x000 0x7 0x0
+#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK                         0x2e4 0x748 0x000 0x0 0x0
+#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5                        0x2e4 0x748 0x808 0x1 0x1
+#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX                      0x2e4 0x748 0x000 0x2 0x0
+#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP                  0x2e4 0x748 0x000 0x3 0x0
+#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO                         0x2e4 0x748 0x7e8 0x4 0x3
+#define MX35_PAD_FEC_RX_CLK__GPIO3_7                            0x2e4 0x748 0x910 0x5 0x1
+#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I                   0x2e4 0x748 0x92c 0x6 0x4
+#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1               0x2e4 0x748 0x000 0x7 0x0
+#define MX35_PAD_FEC_RX_DV__FEC_RX_DV                           0x2e8 0x74c 0x000 0x0 0x0
+#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6                         0x2e8 0x74c 0x80c 0x1 0x1
+#define MX35_PAD_FEC_RX_DV__UART3_RTS                           0x2e8 0x74c 0x99c 0x2 0x2
+#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT                   0x2e8 0x74c 0x9f0 0x3 0x1
+#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK                          0x2e8 0x74c 0x7e0 0x4 0x3
+#define MX35_PAD_FEC_RX_DV__GPIO3_8                             0x2e8 0x74c 0x914 0x5 0x1
+#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK                    0x2e8 0x74c 0x000 0x6 0x0
+#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2                0x2e8 0x74c 0x000 0x7 0x0
+#define MX35_PAD_FEC_COL__FEC_COL                               0x2ec 0x750 0x000 0x0 0x0
+#define MX35_PAD_FEC_COL__ESDHC1_DAT7                           0x2ec 0x750 0x810 0x1 0x1
+#define MX35_PAD_FEC_COL__UART3_CTS                             0x2ec 0x750 0x000 0x2 0x0
+#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0                  0x2ec 0x750 0x9cc 0x3 0x1
+#define MX35_PAD_FEC_COL__CSPI2_RDY                             0x2ec 0x750 0x7e4 0x4 0x3
+#define MX35_PAD_FEC_COL__GPIO3_9                               0x2ec 0x750 0x918 0x5 0x1
+#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS                      0x2ec 0x750 0x000 0x6 0x0
+#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3                  0x2ec 0x750 0x000 0x7 0x0
+#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0                        0x2f0 0x754 0x000 0x0 0x0
+#define MX35_PAD_FEC_RDATA0__PWM_PWMO                           0x2f0 0x754 0x000 0x1 0x0
+#define MX35_PAD_FEC_RDATA0__UART3_DTR                          0x2f0 0x754 0x000 0x2 0x0
+#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1               0x2f0 0x754 0x9d0 0x3 0x1
+#define MX35_PAD_FEC_RDATA0__CSPI2_SS0                          0x2f0 0x754 0x7f0 0x4 0x2
+#define MX35_PAD_FEC_RDATA0__GPIO3_10                           0x2f0 0x754 0x8ec 0x5 0x1
+#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1                      0x2f0 0x754 0x000 0x6 0x0
+#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4               0x2f0 0x754 0x000 0x7 0x0
+#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0                        0x2f4 0x758 0x000 0x0 0x0
+#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1                   0x2f4 0x758 0x000 0x1 0x0
+#define MX35_PAD_FEC_TDATA0__UART3_DSR                          0x2f4 0x758 0x000 0x2 0x0
+#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2               0x2f4 0x758 0x9d4 0x3 0x1
+#define MX35_PAD_FEC_TDATA0__CSPI2_SS1                          0x2f4 0x758 0x7f4 0x4 0x2
+#define MX35_PAD_FEC_TDATA0__GPIO3_11                           0x2f4 0x758 0x8f0 0x5 0x1
+#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0                      0x2f4 0x758 0x000 0x6 0x0
+#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5               0x2f4 0x758 0x000 0x7 0x0
+#define MX35_PAD_FEC_TX_EN__FEC_TX_EN                           0x2f8 0x75c 0x000 0x0 0x0
+#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1                     0x2f8 0x75c 0x998 0x1 0x3
+#define MX35_PAD_FEC_TX_EN__UART3_RI                            0x2f8 0x75c 0x000 0x2 0x0
+#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3                0x2f8 0x75c 0x9d8 0x3 0x1
+#define MX35_PAD_FEC_TX_EN__GPIO3_12                            0x2f8 0x75c 0x8f4 0x5 0x1
+#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS                    0x2f8 0x75c 0x000 0x6 0x0
+#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6                0x2f8 0x75c 0x000 0x7 0x0
+#define MX35_PAD_FEC_MDC__FEC_MDC                               0x2fc 0x760 0x000 0x0 0x0
+#define MX35_PAD_FEC_MDC__CAN2_TXCAN                            0x2fc 0x760 0x000 0x1 0x0
+#define MX35_PAD_FEC_MDC__UART3_DCD                             0x2fc 0x760 0x000 0x2 0x0
+#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4                  0x2fc 0x760 0x9dc 0x3 0x1
+#define MX35_PAD_FEC_MDC__GPIO3_13                              0x2fc 0x760 0x8f8 0x5 0x1
+#define MX35_PAD_FEC_MDC__IPU_DISPB_WR                          0x2fc 0x760 0x000 0x6 0x0
+#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7                  0x2fc 0x760 0x000 0x7 0x0
+#define MX35_PAD_FEC_MDIO__FEC_MDIO                             0x300 0x764 0x000 0x0 0x0
+#define MX35_PAD_FEC_MDIO__CAN2_RXCAN                           0x300 0x764 0x7cc 0x1 0x2
+#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5                 0x300 0x764 0x9e0 0x3 0x1
+#define MX35_PAD_FEC_MDIO__GPIO3_14                             0x300 0x764 0x8fc 0x5 0x1
+#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD                         0x300 0x764 0x000 0x6 0x0
+#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8                 0x300 0x764 0x000 0x7 0x0
+#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR                         0x304 0x768 0x000 0x0 0x0
+#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE                         0x304 0x768 0x990 0x1 0x2
+#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK                 0x304 0x768 0x994 0x2 0x4
+#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6               0x304 0x768 0x9e4 0x3 0x1
+#define MX35_PAD_FEC_TX_ERR__GPIO3_15                           0x304 0x768 0x900 0x5 0x1
+#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC                 0x304 0x768 0x924 0x6 0x3
+#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9               0x304 0x768 0x000 0x7 0x0
+#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR                         0x308 0x76c 0x000 0x0 0x0
+#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0                        0x308 0x76c 0x930 0x1 0x3
+#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7               0x308 0x76c 0x9e8 0x3 0x1
+#define MX35_PAD_FEC_RX_ERR__KPP_COL_4                          0x308 0x76c 0x960 0x4 0x1
+#define MX35_PAD_FEC_RX_ERR__GPIO3_16                           0x308 0x76c 0x000 0x5 0x0
+#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO                  0x308 0x76c 0x92c 0x6 0x5
+#define MX35_PAD_FEC_CRS__FEC_CRS                               0x30c 0x770 0x000 0x0 0x0
+#define MX35_PAD_FEC_CRS__IPU_CSI_D_1                           0x30c 0x770 0x934 0x1 0x3
+#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR                     0x30c 0x770 0x000 0x3 0x0
+#define MX35_PAD_FEC_CRS__KPP_COL_5                             0x30c 0x770 0x964 0x4 0x1
+#define MX35_PAD_FEC_CRS__GPIO3_17                              0x30c 0x770 0x000 0x5 0x0
+#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE                      0x30c 0x770 0x000 0x6 0x0
+#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1                        0x310 0x774 0x000 0x0 0x0
+#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2                        0x310 0x774 0x938 0x1 0x4
+#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC                    0x310 0x774 0x000 0x2 0x0
+#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC                   0x310 0x774 0x9f4 0x3 0x2
+#define MX35_PAD_FEC_RDATA1__KPP_COL_6                          0x310 0x774 0x968 0x4 0x1
+#define MX35_PAD_FEC_RDATA1__GPIO3_18                           0x310 0x774 0x000 0x5 0x0
+#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0                      0x310 0x774 0x000 0x6 0x0
+#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1                        0x314 0x778 0x000 0x0 0x0
+#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3                        0x314 0x778 0x93c 0x1 0x4
+#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS                   0x314 0x778 0x7bc 0x2 0x1
+#define MX35_PAD_FEC_TDATA1__KPP_COL_7                          0x314 0x778 0x96c 0x4 0x1
+#define MX35_PAD_FEC_TDATA1__GPIO3_19                           0x314 0x778 0x000 0x5 0x0
+#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1                      0x314 0x778 0x000 0x6 0x0
+#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2                        0x318 0x77c 0x000 0x0 0x0
+#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4                        0x318 0x77c 0x940 0x1 0x3
+#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD                    0x318 0x77c 0x7b4 0x2 0x1
+#define MX35_PAD_FEC_RDATA2__KPP_ROW_4                          0x318 0x77c 0x980 0x4 0x1
+#define MX35_PAD_FEC_RDATA2__GPIO3_20                           0x318 0x77c 0x000 0x5 0x0
+#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2                        0x31c 0x780 0x000 0x0 0x0
+#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5                        0x31c 0x780 0x944 0x1 0x3
+#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD                    0x31c 0x780 0x7b0 0x2 0x1
+#define MX35_PAD_FEC_TDATA2__KPP_ROW_5                          0x31c 0x780 0x984 0x4 0x1
+#define MX35_PAD_FEC_TDATA2__GPIO3_21                           0x31c 0x780 0x000 0x5 0x0
+#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3                        0x320 0x784 0x000 0x0 0x0
+#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6                        0x320 0x784 0x948 0x1 0x3
+#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC                    0x320 0x784 0x7c0 0x2 0x1
+#define MX35_PAD_FEC_RDATA3__KPP_ROW_6                          0x320 0x784 0x988 0x4 0x1
+#define MX35_PAD_FEC_RDATA3__GPIO3_22                           0x320 0x784 0x000 0x6 0x0
+#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3                        0x324 0x788 0x000 0x0 0x0
+#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7                        0x324 0x788 0x94c 0x1 0x3
+#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS                   0x324 0x788 0x7c4 0x2 0x1
+#define MX35_PAD_FEC_TDATA3__KPP_ROW_7                          0x324 0x788 0x98c 0x4 0x1
+#define MX35_PAD_FEC_TDATA3__GPIO3_23                           0x324 0x788 0x000 0x5 0x0
+#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK                     0x000 0x78c 0x000 0x0 0x0
+#define MX35_PAD_TEST_MODE__TCU_TEST_MODE                       0x000 0x790 0x000 0x0 0x0
+
+#endif /* __DTS_IMX35_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
index 92d3a66a69e2..2bcf6981d490 100644
--- a/arch/arm/boot/dts/imx51-apf51.dts
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -15,7 +15,7 @@
  */
 
 /dts-v1/;
-/include/ "imx51.dtsi"
+#include "imx51.dtsi"
 
 / {
         model = "Armadeus Systems APF51 module";
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts
new file mode 100644
index 000000000000..123fe84e0e8c
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-apf51dev.dts
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2013 Armadeus Systems - <support@armadeus.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/* APF51Dev is a docking board for the APF51 SOM */
+#include "imx51-apf51.dts"
+
+/ {
+        model = "Armadeus Systems APF51Dev docking/development board";
+        compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51";
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                user-key {
+                        label = "user";
+                        gpios = <&gpio1 3 0>;
+                        linux,code = <256>; /* BTN_0 */
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                user {
+                        label = "Heartbeat";
+                        gpios = <&gpio1 2 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
+
+&ecspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1_1>;
+        fsl,spi-num-chipselects = <2>;
+        cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
+        status = "okay";
+};
+
+&ecspi2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi2_1>;
+        fsl,spi-num-chipselects = <2>;
+        cs-gpios = <&gpio3 28 1>, <&gpio3 27 1>;
+        status = "okay";
+};
+
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1_1>;
+        cd-gpios = <&gpio2 29 0>;
+        bus-width = <4>;
+        status = "okay";
+};
+
+&esdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc2_1>;
+        bus-width = <4>;
+        non-removable;
+        status = "okay";
+};
+
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2_2>;
+        status = "okay";
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX51_PAD_EIM_EB2__GPIO2_22   0x0C5
+                                MX51_PAD_EIM_EB3__GPIO2_23   0x0C5
+                                MX51_PAD_EIM_CS4__GPIO2_29   0x100
+                                MX51_PAD_NANDF_D13__GPIO3_27 0x0C5
+                                MX51_PAD_NANDF_D12__GPIO3_28 0x0C5
+                                MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5
+                                MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5
+                                MX51_PAD_GPIO1_2__GPIO1_2    0x0C5
+                                MX51_PAD_GPIO1_3__GPIO1_3    0x0C5
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index aab6e43219af..6dd9486c755b 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -11,7 +11,7 @@
  */
 
 /dts-v1/;
-/include/ "imx51.dtsi"
+#include "imx51.dtsi"
 
 / {
         model = "Freescale i.MX51 Babbage Board";
@@ -222,13 +222,13 @@
         hog {
                 pinctrl_hog: hoggrp {
                         fsl,pins = <
-                                694  0x20d5     /* MX51_PAD_GPIO1_0__SD1_CD */
-                                697  0x20d5     /* MX51_PAD_GPIO1_1__SD1_WP */
-                                737  0x100      /* MX51_PAD_GPIO1_5__GPIO1_5 */
-                                740  0x100      /* MX51_PAD_GPIO1_6__GPIO1_6 */
-                                121  0x5        /* MX51_PAD_EIM_A27__GPIO2_21 */
-                                402  0x85       /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
-                                405  0x85       /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
+                                MX51_PAD_GPIO1_0__SD1_CD     0x20d5
+                                MX51_PAD_GPIO1_1__SD1_WP     0x20d5
+                                MX51_PAD_GPIO1_5__GPIO1_5    0x100
+                                MX51_PAD_GPIO1_6__GPIO1_6    0x100
+                                MX51_PAD_EIM_A27__GPIO2_21   0x5
+                                MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
+                                MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
                         >;
                 };
         };
diff --git a/arch/arm/boot/dts/imx51-pinfunc.h b/arch/arm/boot/dts/imx51-pinfunc.h
new file mode 100644
index 000000000000..9eb92abaeb6d
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-pinfunc.h
@@ -0,0 +1,773 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX51_PINFUNC_H
+#define __DTS_IMX51_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX51_PAD_EIM_D16__AUD4_RXFS                     0x05c 0x3f0 0x000 0x5 0x0
+#define MX51_PAD_EIM_D16__AUD5_TXD                      0x05c 0x3f0 0x8d8 0x7 0x0
+#define MX51_PAD_EIM_D16__EIM_D16                       0x05c 0x3f0 0x000 0x0 0x0
+#define MX51_PAD_EIM_D16__GPIO2_0                       0x05c 0x3f0 0x000 0x1 0x0
+#define MX51_PAD_EIM_D16__I2C1_SDA                      0x05c 0x3f0 0x9b4 0x4 0x0
+#define MX51_PAD_EIM_D16__UART2_CTS                     0x05c 0x3f0 0x000 0x3 0x0
+#define MX51_PAD_EIM_D16__USBH2_DATA0                   0x05c 0x3f0 0x000 0x2 0x0
+#define MX51_PAD_EIM_D17__AUD5_RXD                      0x060 0x3f4 0x8d4 0x7 0x0
+#define MX51_PAD_EIM_D17__EIM_D17                       0x060 0x3f4 0x000 0x0 0x0
+#define MX51_PAD_EIM_D17__GPIO2_1                       0x060 0x3f4 0x000 0x1 0x0
+#define MX51_PAD_EIM_D17__UART2_RXD                     0x060 0x3f4 0x9ec 0x3 0x0
+#define MX51_PAD_EIM_D17__UART3_CTS                     0x060 0x3f4 0x000 0x4 0x0
+#define MX51_PAD_EIM_D17__USBH2_DATA1                   0x060 0x3f4 0x000 0x2 0x0
+#define MX51_PAD_EIM_D18__AUD5_TXC                      0x064 0x3f8 0x8e4 0x7 0x0
+#define MX51_PAD_EIM_D18__EIM_D18                       0x064 0x3f8 0x000 0x0 0x0
+#define MX51_PAD_EIM_D18__GPIO2_2                       0x064 0x3f8 0x000 0x1 0x0
+#define MX51_PAD_EIM_D18__UART2_TXD                     0x064 0x3f8 0x000 0x3 0x0
+#define MX51_PAD_EIM_D18__UART3_RTS                     0x064 0x3f8 0x9f0 0x4 0x1
+#define MX51_PAD_EIM_D18__USBH2_DATA2                   0x064 0x3f8 0x000 0x2 0x0
+#define MX51_PAD_EIM_D19__AUD4_RXC                      0x068 0x3fc 0x000 0x5 0x0
+#define MX51_PAD_EIM_D19__AUD5_TXFS                     0x068 0x3fc 0x8e8 0x7 0x0
+#define MX51_PAD_EIM_D19__EIM_D19                       0x068 0x3fc 0x000 0x0 0x0
+#define MX51_PAD_EIM_D19__GPIO2_3                       0x068 0x3fc 0x000 0x1 0x0
+#define MX51_PAD_EIM_D19__I2C1_SCL                      0x068 0x3fc 0x9b0 0x4 0x0
+#define MX51_PAD_EIM_D19__UART2_RTS                     0x068 0x3fc 0x9e8 0x3 0x1
+#define MX51_PAD_EIM_D19__USBH2_DATA3                   0x068 0x3fc 0x000 0x2 0x0
+#define MX51_PAD_EIM_D20__AUD4_TXD                      0x06c 0x400 0x8c8 0x5 0x0
+#define MX51_PAD_EIM_D20__EIM_D20                       0x06c 0x400 0x000 0x0 0x0
+#define MX51_PAD_EIM_D20__GPIO2_4                       0x06c 0x400 0x000 0x1 0x0
+#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB                0x06c 0x400 0x000 0x4 0x0
+#define MX51_PAD_EIM_D20__USBH2_DATA4                   0x06c 0x400 0x000 0x2 0x0
+#define MX51_PAD_EIM_D21__AUD4_RXD                      0x070 0x404 0x8c4 0x5 0x0
+#define MX51_PAD_EIM_D21__EIM_D21                       0x070 0x404 0x000 0x0 0x0
+#define MX51_PAD_EIM_D21__GPIO2_5                       0x070 0x404 0x000 0x1 0x0
+#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB                0x070 0x404 0x000 0x3 0x0
+#define MX51_PAD_EIM_D21__USBH2_DATA5                   0x070 0x404 0x000 0x2 0x0
+#define MX51_PAD_EIM_D22__AUD4_TXC                      0x074 0x408 0x8cc 0x5 0x0
+#define MX51_PAD_EIM_D22__EIM_D22                       0x074 0x408 0x000 0x0 0x0
+#define MX51_PAD_EIM_D22__GPIO2_6                       0x074 0x408 0x000 0x1 0x0
+#define MX51_PAD_EIM_D22__USBH2_DATA6                   0x074 0x408 0x000 0x2 0x0
+#define MX51_PAD_EIM_D23__AUD4_TXFS                     0x078 0x40c 0x8d0 0x5 0x0
+#define MX51_PAD_EIM_D23__EIM_D23                       0x078 0x40c 0x000 0x0 0x0
+#define MX51_PAD_EIM_D23__GPIO2_7                       0x078 0x40c 0x000 0x1 0x0
+#define MX51_PAD_EIM_D23__SPDIF_OUT1                    0x078 0x40c 0x000 0x4 0x0
+#define MX51_PAD_EIM_D23__USBH2_DATA7                   0x078 0x40c 0x000 0x2 0x0
+#define MX51_PAD_EIM_D24__AUD6_RXFS                     0x07c 0x410 0x8f8 0x5 0x0
+#define MX51_PAD_EIM_D24__EIM_D24                       0x07c 0x410 0x000 0x0 0x0
+#define MX51_PAD_EIM_D24__GPIO2_8                       0x07c 0x410 0x000 0x1 0x0
+#define MX51_PAD_EIM_D24__I2C2_SDA                      0x07c 0x410 0x9bc 0x4 0x0
+#define MX51_PAD_EIM_D24__UART3_CTS                     0x07c 0x410 0x000 0x3 0x0
+#define MX51_PAD_EIM_D24__USBOTG_DATA0                  0x07c 0x410 0x000 0x2 0x0
+#define MX51_PAD_EIM_D25__EIM_D25                       0x080 0x414 0x000 0x0 0x0
+#define MX51_PAD_EIM_D25__KEY_COL6                      0x080 0x414 0x9c8 0x1 0x0
+#define MX51_PAD_EIM_D25__UART2_CTS                     0x080 0x414 0x000 0x4 0x0
+#define MX51_PAD_EIM_D25__UART3_RXD                     0x080 0x414 0x9f4 0x3 0x0
+#define MX51_PAD_EIM_D25__USBOTG_DATA1                  0x080 0x414 0x000 0x2 0x0
+#define MX51_PAD_EIM_D26__EIM_D26                       0x084 0x418 0x000 0x0 0x0
+#define MX51_PAD_EIM_D26__KEY_COL7                      0x084 0x418 0x9cc 0x1 0x0
+#define MX51_PAD_EIM_D26__UART2_RTS                     0x084 0x418 0x9e8 0x4 0x3
+#define MX51_PAD_EIM_D26__UART3_TXD                     0x084 0x418 0x000 0x3 0x0
+#define MX51_PAD_EIM_D26__USBOTG_DATA2                  0x084 0x418 0x000 0x2 0x0
+#define MX51_PAD_EIM_D27__AUD6_RXC                      0x088 0x41c 0x8f4 0x5 0x0
+#define MX51_PAD_EIM_D27__EIM_D27                       0x088 0x41c 0x000 0x0 0x0
+#define MX51_PAD_EIM_D27__GPIO2_9                       0x088 0x41c 0x000 0x1 0x0
+#define MX51_PAD_EIM_D27__I2C2_SCL                      0x088 0x41c 0x9b8 0x4 0x0
+#define MX51_PAD_EIM_D27__UART3_RTS                     0x088 0x41c 0x9f0 0x3 0x3
+#define MX51_PAD_EIM_D27__USBOTG_DATA3                  0x088 0x41c 0x000 0x2 0x0
+#define MX51_PAD_EIM_D28__AUD6_TXD                      0x08c 0x420 0x8f0 0x5 0x0
+#define MX51_PAD_EIM_D28__EIM_D28                       0x08c 0x420 0x000 0x0 0x0
+#define MX51_PAD_EIM_D28__KEY_ROW4                      0x08c 0x420 0x9d0 0x1 0x0
+#define MX51_PAD_EIM_D28__USBOTG_DATA4                  0x08c 0x420 0x000 0x2 0x0
+#define MX51_PAD_EIM_D29__AUD6_RXD                      0x090 0x424 0x8ec 0x5 0x0
+#define MX51_PAD_EIM_D29__EIM_D29                       0x090 0x424 0x000 0x0 0x0
+#define MX51_PAD_EIM_D29__KEY_ROW5                      0x090 0x424 0x9d4 0x1 0x0
+#define MX51_PAD_EIM_D29__USBOTG_DATA5                  0x090 0x424 0x000 0x2 0x0
+#define MX51_PAD_EIM_D30__AUD6_TXC                      0x094 0x428 0x8fc 0x5 0x0
+#define MX51_PAD_EIM_D30__EIM_D30                       0x094 0x428 0x000 0x0 0x0
+#define MX51_PAD_EIM_D30__KEY_ROW6                      0x094 0x428 0x9d8 0x1 0x0
+#define MX51_PAD_EIM_D30__USBOTG_DATA6                  0x094 0x428 0x000 0x2 0x0
+#define MX51_PAD_EIM_D31__AUD6_TXFS                     0x098 0x42c 0x900 0x5 0x0
+#define MX51_PAD_EIM_D31__EIM_D31                       0x098 0x42c 0x000 0x0 0x0
+#define MX51_PAD_EIM_D31__KEY_ROW7                      0x098 0x42c 0x9dc 0x1 0x0
+#define MX51_PAD_EIM_D31__USBOTG_DATA7                  0x098 0x42c 0x000 0x2 0x0
+#define MX51_PAD_EIM_A16__EIM_A16                       0x09c 0x430 0x000 0x0 0x0
+#define MX51_PAD_EIM_A16__GPIO2_10                      0x09c 0x430 0x000 0x1 0x0
+#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0                 0x09c 0x430 0x000 0x7 0x0
+#define MX51_PAD_EIM_A17__EIM_A17                       0x0a0 0x434 0x000 0x0 0x0
+#define MX51_PAD_EIM_A17__GPIO2_11                      0x0a0 0x434 0x000 0x1 0x0
+#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1                 0x0a0 0x434 0x000 0x7 0x0
+#define MX51_PAD_EIM_A18__BOOT_LPB0                     0x0a4 0x438 0x000 0x7 0x0
+#define MX51_PAD_EIM_A18__EIM_A18                       0x0a4 0x438 0x000 0x0 0x0
+#define MX51_PAD_EIM_A18__GPIO2_12                      0x0a4 0x438 0x000 0x1 0x0
+#define MX51_PAD_EIM_A19__BOOT_LPB1                     0x0a8 0x43c 0x000 0x7 0x0
+#define MX51_PAD_EIM_A19__EIM_A19                       0x0a8 0x43c 0x000 0x0 0x0
+#define MX51_PAD_EIM_A19__GPIO2_13                      0x0a8 0x43c 0x000 0x1 0x0
+#define MX51_PAD_EIM_A20__BOOT_UART_SRC0                0x0ac 0x440 0x000 0x7 0x0
+#define MX51_PAD_EIM_A20__EIM_A20                       0x0ac 0x440 0x000 0x0 0x0
+#define MX51_PAD_EIM_A20__GPIO2_14                      0x0ac 0x440 0x000 0x1 0x0
+#define MX51_PAD_EIM_A21__BOOT_UART_SRC1                0x0b0 0x444 0x000 0x7 0x0
+#define MX51_PAD_EIM_A21__EIM_A21                       0x0b0 0x444 0x000 0x0 0x0
+#define MX51_PAD_EIM_A21__GPIO2_15                      0x0b0 0x444 0x000 0x1 0x0
+#define MX51_PAD_EIM_A22__EIM_A22                       0x0b4 0x448 0x000 0x0 0x0
+#define MX51_PAD_EIM_A22__GPIO2_16                      0x0b4 0x448 0x000 0x1 0x0
+#define MX51_PAD_EIM_A23__BOOT_HPN_EN                   0x0b8 0x44c 0x000 0x7 0x0
+#define MX51_PAD_EIM_A23__EIM_A23                       0x0b8 0x44c 0x000 0x0 0x0
+#define MX51_PAD_EIM_A23__GPIO2_17                      0x0b8 0x44c 0x000 0x1 0x0
+#define MX51_PAD_EIM_A24__EIM_A24                       0x0bc 0x450 0x000 0x0 0x0
+#define MX51_PAD_EIM_A24__GPIO2_18                      0x0bc 0x450 0x000 0x1 0x0
+#define MX51_PAD_EIM_A24__USBH2_CLK                     0x0bc 0x450 0x000 0x2 0x0
+#define MX51_PAD_EIM_A25__DISP1_PIN4                    0x0c0 0x454 0x000 0x6 0x0
+#define MX51_PAD_EIM_A25__EIM_A25                       0x0c0 0x454 0x000 0x0 0x0
+#define MX51_PAD_EIM_A25__GPIO2_19                      0x0c0 0x454 0x000 0x1 0x0
+#define MX51_PAD_EIM_A25__USBH2_DIR                     0x0c0 0x454 0x000 0x2 0x0
+#define MX51_PAD_EIM_A26__CSI1_DATA_EN                  0x0c4 0x458 0x9a0 0x5 0x0
+#define MX51_PAD_EIM_A26__DISP2_EXT_CLK                 0x0c4 0x458 0x908 0x6 0x0
+#define MX51_PAD_EIM_A26__EIM_A26                       0x0c4 0x458 0x000 0x0 0x0
+#define MX51_PAD_EIM_A26__GPIO2_20                      0x0c4 0x458 0x000 0x1 0x0
+#define MX51_PAD_EIM_A26__USBH2_STP                     0x0c4 0x458 0x000 0x2 0x0
+#define MX51_PAD_EIM_A27__CSI2_DATA_EN                  0x0c8 0x45c 0x99c 0x5 0x0
+#define MX51_PAD_EIM_A27__DISP1_PIN1                    0x0c8 0x45c 0x9a4 0x6 0x0
+#define MX51_PAD_EIM_A27__EIM_A27                       0x0c8 0x45c 0x000 0x0 0x0
+#define MX51_PAD_EIM_A27__GPIO2_21                      0x0c8 0x45c 0x000 0x1 0x0
+#define MX51_PAD_EIM_A27__USBH2_NXT                     0x0c8 0x45c 0x000 0x2 0x0
+#define MX51_PAD_EIM_EB0__EIM_EB0                       0x0cc 0x460 0x000 0x0 0x0
+#define MX51_PAD_EIM_EB1__EIM_EB1                       0x0d0 0x464 0x000 0x0 0x0
+#define MX51_PAD_EIM_EB2__AUD5_RXFS                     0x0d4 0x468 0x8e0 0x6 0x0
+#define MX51_PAD_EIM_EB2__CSI1_D2                       0x0d4 0x468 0x000 0x5 0x0
+#define MX51_PAD_EIM_EB2__EIM_EB2                       0x0d4 0x468 0x000 0x0 0x0
+#define MX51_PAD_EIM_EB2__FEC_MDIO                      0x0d4 0x468 0x954 0x3 0x0
+#define MX51_PAD_EIM_EB2__GPIO2_22                      0x0d4 0x468 0x000 0x1 0x0
+#define MX51_PAD_EIM_EB2__GPT_CMPOUT1                   0x0d4 0x468 0x000 0x7 0x0
+#define MX51_PAD_EIM_EB3__AUD5_RXC                      0x0d8 0x46c 0x8dc 0x6 0x0
+#define MX51_PAD_EIM_EB3__CSI1_D3                       0x0d8 0x46c 0x000 0x5 0x0
+#define MX51_PAD_EIM_EB3__EIM_EB3                       0x0d8 0x46c 0x000 0x0 0x0
+#define MX51_PAD_EIM_EB3__FEC_RDATA1                    0x0d8 0x46c 0x95c 0x3 0x0
+#define MX51_PAD_EIM_EB3__GPIO2_23                      0x0d8 0x46c 0x000 0x1 0x0
+#define MX51_PAD_EIM_EB3__GPT_CMPOUT2                   0x0d8 0x46c 0x000 0x7 0x0
+#define MX51_PAD_EIM_OE__EIM_OE                         0x0dc 0x470 0x000 0x0 0x0
+#define MX51_PAD_EIM_OE__GPIO2_24                       0x0dc 0x470 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS0__EIM_CS0                       0x0e0 0x474 0x000 0x0 0x0
+#define MX51_PAD_EIM_CS0__GPIO2_25                      0x0e0 0x474 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS1__EIM_CS1                       0x0e4 0x478 0x000 0x0 0x0
+#define MX51_PAD_EIM_CS1__GPIO2_26                      0x0e4 0x478 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS2__AUD5_TXD                      0x0e8 0x47c 0x8d8 0x6 0x1
+#define MX51_PAD_EIM_CS2__CSI1_D4                       0x0e8 0x47c 0x000 0x5 0x0
+#define MX51_PAD_EIM_CS2__EIM_CS2                       0x0e8 0x47c 0x000 0x0 0x0
+#define MX51_PAD_EIM_CS2__FEC_RDATA2                    0x0e8 0x47c 0x960 0x3 0x0
+#define MX51_PAD_EIM_CS2__GPIO2_27                      0x0e8 0x47c 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS2__USBOTG_STP                    0x0e8 0x47c 0x000 0x2 0x0
+#define MX51_PAD_EIM_CS3__AUD5_RXD                      0x0ec 0x480 0x8d4 0x6 0x1
+#define MX51_PAD_EIM_CS3__CSI1_D5                       0x0ec 0x480 0x000 0x5 0x0
+#define MX51_PAD_EIM_CS3__EIM_CS3                       0x0ec 0x480 0x000 0x0 0x0
+#define MX51_PAD_EIM_CS3__FEC_RDATA3                    0x0ec 0x480 0x964 0x3 0x0
+#define MX51_PAD_EIM_CS3__GPIO2_28                      0x0ec 0x480 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS3__USBOTG_NXT                    0x0ec 0x480 0x000 0x2 0x0
+#define MX51_PAD_EIM_CS4__AUD5_TXC                      0x0f0 0x484 0x8e4 0x6 0x1
+#define MX51_PAD_EIM_CS4__CSI1_D6                       0x0f0 0x484 0x000 0x5 0x0
+#define MX51_PAD_EIM_CS4__EIM_CS4                       0x0f0 0x484 0x000 0x0 0x0
+#define MX51_PAD_EIM_CS4__FEC_RX_ER                     0x0f0 0x484 0x970 0x3 0x0
+#define MX51_PAD_EIM_CS4__GPIO2_29                      0x0f0 0x484 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS4__USBOTG_CLK                    0x0f0 0x484 0x000 0x2 0x0
+#define MX51_PAD_EIM_CS5__AUD5_TXFS                     0x0f4 0x488 0x8e8 0x6 0x1
+#define MX51_PAD_EIM_CS5__CSI1_D7                       0x0f4 0x488 0x000 0x5 0x0
+#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK                 0x0f4 0x488 0x904 0x4 0x0
+#define MX51_PAD_EIM_CS5__EIM_CS5                       0x0f4 0x488 0x000 0x0 0x0
+#define MX51_PAD_EIM_CS5__FEC_CRS                       0x0f4 0x488 0x950 0x3 0x0
+#define MX51_PAD_EIM_CS5__GPIO2_30                      0x0f4 0x488 0x000 0x1 0x0
+#define MX51_PAD_EIM_CS5__USBOTG_DIR                    0x0f4 0x488 0x000 0x2 0x0
+#define MX51_PAD_EIM_DTACK__EIM_DTACK                   0x0f8 0x48c 0x000 0x0 0x0
+#define MX51_PAD_EIM_DTACK__GPIO2_31                    0x0f8 0x48c 0x000 0x1 0x0
+#define MX51_PAD_EIM_LBA__EIM_LBA                       0x0fc 0x494 0x000 0x0 0x0
+#define MX51_PAD_EIM_LBA__GPIO3_1                       0x0fc 0x494 0x978 0x1 0x0
+#define MX51_PAD_EIM_CRE__EIM_CRE                       0x100 0x4a0 0x000 0x0 0x0
+#define MX51_PAD_EIM_CRE__GPIO3_2                       0x100 0x4a0 0x97c 0x1 0x0
+#define MX51_PAD_DRAM_CS1__DRAM_CS1                     0x104 0x4d0 0x000 0x0 0x0
+#define MX51_PAD_NANDF_WE_B__GPIO3_3                    0x108 0x4e4 0x980 0x3 0x0
+#define MX51_PAD_NANDF_WE_B__NANDF_WE_B                 0x108 0x4e4 0x000 0x0 0x0
+#define MX51_PAD_NANDF_WE_B__PATA_DIOW                  0x108 0x4e4 0x000 0x1 0x0
+#define MX51_PAD_NANDF_WE_B__SD3_DATA0                  0x108 0x4e4 0x93c 0x2 0x0
+#define MX51_PAD_NANDF_RE_B__GPIO3_4                    0x10c 0x4e8 0x984 0x3 0x0
+#define MX51_PAD_NANDF_RE_B__NANDF_RE_B                 0x10c 0x4e8 0x000 0x0 0x0
+#define MX51_PAD_NANDF_RE_B__PATA_DIOR                  0x10c 0x4e8 0x000 0x1 0x0
+#define MX51_PAD_NANDF_RE_B__SD3_DATA1                  0x10c 0x4e8 0x940 0x2 0x0
+#define MX51_PAD_NANDF_ALE__GPIO3_5                     0x110 0x4ec 0x988 0x3 0x0
+#define MX51_PAD_NANDF_ALE__NANDF_ALE                   0x110 0x4ec 0x000 0x0 0x0
+#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN              0x110 0x4ec 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CLE__GPIO3_6                     0x114 0x4f0 0x98c 0x3 0x0
+#define MX51_PAD_NANDF_CLE__NANDF_CLE                   0x114 0x4f0 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CLE__PATA_RESET_B                0x114 0x4f0 0x000 0x1 0x0
+#define MX51_PAD_NANDF_WP_B__GPIO3_7                    0x118 0x4f4 0x990 0x3 0x0
+#define MX51_PAD_NANDF_WP_B__NANDF_WP_B                 0x118 0x4f4 0x000 0x0 0x0
+#define MX51_PAD_NANDF_WP_B__PATA_DMACK                 0x118 0x4f4 0x000 0x1 0x0
+#define MX51_PAD_NANDF_WP_B__SD3_DATA2                  0x118 0x4f4 0x944 0x2 0x0
+#define MX51_PAD_NANDF_RB0__ECSPI2_SS1                  0x11c 0x4f8 0x930 0x5 0x0
+#define MX51_PAD_NANDF_RB0__GPIO3_8                     0x11c 0x4f8 0x994 0x3 0x0
+#define MX51_PAD_NANDF_RB0__NANDF_RB0                   0x11c 0x4f8 0x000 0x0 0x0
+#define MX51_PAD_NANDF_RB0__PATA_DMARQ                  0x11c 0x4f8 0x000 0x1 0x0
+#define MX51_PAD_NANDF_RB0__SD3_DATA3                   0x11c 0x4f8 0x948 0x2 0x0
+#define MX51_PAD_NANDF_RB1__CSPI_MOSI                   0x120 0x4fc 0x91c 0x6 0x0
+#define MX51_PAD_NANDF_RB1__ECSPI2_RDY                  0x120 0x4fc 0x000 0x2 0x0
+#define MX51_PAD_NANDF_RB1__GPIO3_9                     0x120 0x4fc 0x000 0x3 0x0
+#define MX51_PAD_NANDF_RB1__NANDF_RB1                   0x120 0x4fc 0x000 0x0 0x0
+#define MX51_PAD_NANDF_RB1__PATA_IORDY                  0x120 0x4fc 0x000 0x1 0x0
+#define MX51_PAD_NANDF_RB1__SD4_CMD                     0x120 0x4fc 0x000 0x5 0x0
+#define MX51_PAD_NANDF_RB2__DISP2_WAIT                  0x124 0x500 0x9a8 0x5 0x0
+#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK                 0x124 0x500 0x000 0x2 0x0
+#define MX51_PAD_NANDF_RB2__FEC_COL                     0x124 0x500 0x94c 0x1 0x0
+#define MX51_PAD_NANDF_RB2__GPIO3_10                    0x124 0x500 0x000 0x3 0x0
+#define MX51_PAD_NANDF_RB2__NANDF_RB2                   0x124 0x500 0x000 0x0 0x0
+#define MX51_PAD_NANDF_RB2__USBH3_H3_DP                 0x124 0x500 0x000 0x7 0x0
+#define MX51_PAD_NANDF_RB2__USBH3_NXT                   0x124 0x500 0xa20 0x6 0x0
+#define MX51_PAD_NANDF_RB3__DISP1_WAIT                  0x128 0x504 0x000 0x5 0x0
+#define MX51_PAD_NANDF_RB3__ECSPI2_MISO                 0x128 0x504 0x000 0x2 0x0
+#define MX51_PAD_NANDF_RB3__FEC_RX_CLK                  0x128 0x504 0x968 0x1 0x0
+#define MX51_PAD_NANDF_RB3__GPIO3_11                    0x128 0x504 0x000 0x3 0x0
+#define MX51_PAD_NANDF_RB3__NANDF_RB3                   0x128 0x504 0x000 0x0 0x0
+#define MX51_PAD_NANDF_RB3__USBH3_CLK                   0x128 0x504 0x9f8 0x6 0x0
+#define MX51_PAD_NANDF_RB3__USBH3_H3_DM                 0x128 0x504 0x000 0x7 0x0
+#define MX51_PAD_GPIO_NAND__GPIO_NAND                   0x12c 0x514 0x998 0x0 0x0
+#define MX51_PAD_GPIO_NAND__PATA_INTRQ                  0x12c 0x514 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS0__GPIO3_16                    0x130 0x518 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS0__NANDF_CS0                   0x130 0x518 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS1__GPIO3_17                    0x134 0x51c 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS1__NANDF_CS1                   0x134 0x51c 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS2__CSPI_SCLK                   0x138 0x520 0x914 0x6 0x0
+#define MX51_PAD_NANDF_CS2__FEC_TX_ER                   0x138 0x520 0x000 0x2 0x0
+#define MX51_PAD_NANDF_CS2__GPIO3_18                    0x138 0x520 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS2__NANDF_CS2                   0x138 0x520 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS2__PATA_CS_0                   0x138 0x520 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS2__SD4_CLK                     0x138 0x520 0x000 0x5 0x0
+#define MX51_PAD_NANDF_CS2__USBH3_H1_DP                 0x138 0x520 0x000 0x7 0x0
+#define MX51_PAD_NANDF_CS3__FEC_MDC                     0x13c 0x524 0x000 0x2 0x0
+#define MX51_PAD_NANDF_CS3__GPIO3_19                    0x13c 0x524 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS3__NANDF_CS3                   0x13c 0x524 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS3__PATA_CS_1                   0x13c 0x524 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS3__SD4_DAT0                    0x13c 0x524 0x000 0x5 0x0
+#define MX51_PAD_NANDF_CS3__USBH3_H1_DM                 0x13c 0x524 0x000 0x7 0x0
+#define MX51_PAD_NANDF_CS4__FEC_TDATA1                  0x140 0x528 0x000 0x2 0x0
+#define MX51_PAD_NANDF_CS4__GPIO3_20                    0x140 0x528 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS4__NANDF_CS4                   0x140 0x528 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS4__PATA_DA_0                   0x140 0x528 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS4__SD4_DAT1                    0x140 0x528 0x000 0x5 0x0
+#define MX51_PAD_NANDF_CS4__USBH3_STP                   0x140 0x528 0xa24 0x7 0x0
+#define MX51_PAD_NANDF_CS5__FEC_TDATA2                  0x144 0x52c 0x000 0x2 0x0
+#define MX51_PAD_NANDF_CS5__GPIO3_21                    0x144 0x52c 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS5__NANDF_CS5                   0x144 0x52c 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS5__PATA_DA_1                   0x144 0x52c 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS5__SD4_DAT2                    0x144 0x52c 0x000 0x5 0x0
+#define MX51_PAD_NANDF_CS5__USBH3_DIR                   0x144 0x52c 0xa1c 0x7 0x0
+#define MX51_PAD_NANDF_CS6__CSPI_SS3                    0x148 0x530 0x928 0x7 0x0
+#define MX51_PAD_NANDF_CS6__FEC_TDATA3                  0x148 0x530 0x000 0x2 0x0
+#define MX51_PAD_NANDF_CS6__GPIO3_22                    0x148 0x530 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS6__NANDF_CS6                   0x148 0x530 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS6__PATA_DA_2                   0x148 0x530 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS6__SD4_DAT3                    0x148 0x530 0x000 0x5 0x0
+#define MX51_PAD_NANDF_CS7__FEC_TX_EN                   0x14c 0x534 0x000 0x1 0x0
+#define MX51_PAD_NANDF_CS7__GPIO3_23                    0x14c 0x534 0x000 0x3 0x0
+#define MX51_PAD_NANDF_CS7__NANDF_CS7                   0x14c 0x534 0x000 0x0 0x0
+#define MX51_PAD_NANDF_CS7__SD3_CLK                     0x14c 0x534 0x000 0x5 0x0
+#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0              0x150 0x538 0x000 0x2 0x0
+#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK              0x150 0x538 0x974 0x1 0x0
+#define MX51_PAD_NANDF_RDY_INT__GPIO3_24                0x150 0x538 0x000 0x3 0x0
+#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT           0x150 0x538 0x938 0x0 0x0
+#define MX51_PAD_NANDF_RDY_INT__SD3_CMD                 0x150 0x538 0x000 0x5 0x0
+#define MX51_PAD_NANDF_D15__ECSPI2_MOSI                 0x154 0x53c 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D15__GPIO3_25                    0x154 0x53c 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D15__NANDF_D15                   0x154 0x53c 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D15__PATA_DATA15                 0x154 0x53c 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D15__SD3_DAT7                    0x154 0x53c 0x000 0x5 0x0
+#define MX51_PAD_NANDF_D14__ECSPI2_SS3                  0x158 0x540 0x934 0x2 0x0
+#define MX51_PAD_NANDF_D14__GPIO3_26                    0x158 0x540 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D14__NANDF_D14                   0x158 0x540 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D14__PATA_DATA14                 0x158 0x540 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D14__SD3_DAT6                    0x158 0x540 0x000 0x5 0x0
+#define MX51_PAD_NANDF_D13__ECSPI2_SS2                  0x15c 0x544 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D13__GPIO3_27                    0x15c 0x544 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D13__NANDF_D13                   0x15c 0x544 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D13__PATA_DATA13                 0x15c 0x544 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D13__SD3_DAT5                    0x15c 0x544 0x000 0x5 0x0
+#define MX51_PAD_NANDF_D12__ECSPI2_SS1                  0x160 0x548 0x930 0x2 0x1
+#define MX51_PAD_NANDF_D12__GPIO3_28                    0x160 0x548 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D12__NANDF_D12                   0x160 0x548 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D12__PATA_DATA12                 0x160 0x548 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D12__SD3_DAT4                    0x160 0x548 0x000 0x5 0x0
+#define MX51_PAD_NANDF_D11__FEC_RX_DV                   0x164 0x54c 0x96c 0x2 0x0
+#define MX51_PAD_NANDF_D11__GPIO3_29                    0x164 0x54c 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D11__NANDF_D11                   0x164 0x54c 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D11__PATA_DATA11                 0x164 0x54c 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D11__SD3_DATA3                   0x164 0x54c 0x948 0x5 0x1
+#define MX51_PAD_NANDF_D10__GPIO3_30                    0x168 0x550 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D10__NANDF_D10                   0x168 0x550 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D10__PATA_DATA10                 0x168 0x550 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D10__SD3_DATA2                   0x168 0x550 0x944 0x5 0x1
+#define MX51_PAD_NANDF_D9__FEC_RDATA0                   0x16c 0x554 0x958 0x2 0x0
+#define MX51_PAD_NANDF_D9__GPIO3_31                     0x16c 0x554 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D9__NANDF_D9                     0x16c 0x554 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D9__PATA_DATA9                   0x16c 0x554 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D9__SD3_DATA1                    0x16c 0x554 0x940 0x5 0x1
+#define MX51_PAD_NANDF_D8__FEC_TDATA0                   0x170 0x558 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D8__GPIO4_0                      0x170 0x558 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D8__NANDF_D8                     0x170 0x558 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D8__PATA_DATA8                   0x170 0x558 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D8__SD3_DATA0                    0x170 0x558 0x93c 0x5 0x1
+#define MX51_PAD_NANDF_D7__GPIO4_1                      0x174 0x55c 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D7__NANDF_D7                     0x174 0x55c 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D7__PATA_DATA7                   0x174 0x55c 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D7__USBH3_DATA0                  0x174 0x55c 0x9fc 0x5 0x0
+#define MX51_PAD_NANDF_D6__GPIO4_2                      0x178 0x560 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D6__NANDF_D6                     0x178 0x560 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D6__PATA_DATA6                   0x178 0x560 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D6__SD4_LCTL                     0x178 0x560 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D6__USBH3_DATA1                  0x178 0x560 0xa00 0x5 0x0
+#define MX51_PAD_NANDF_D5__GPIO4_3                      0x17c 0x564 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D5__NANDF_D5                     0x17c 0x564 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D5__PATA_DATA5                   0x17c 0x564 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D5__SD4_WP                       0x17c 0x564 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D5__USBH3_DATA2                  0x17c 0x564 0xa04 0x5 0x0
+#define MX51_PAD_NANDF_D4__GPIO4_4                      0x180 0x568 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D4__NANDF_D4                     0x180 0x568 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D4__PATA_DATA4                   0x180 0x568 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D4__SD4_CD                       0x180 0x568 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D4__USBH3_DATA3                  0x180 0x568 0xa08 0x5 0x0
+#define MX51_PAD_NANDF_D3__GPIO4_5                      0x184 0x56c 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D3__NANDF_D3                     0x184 0x56c 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D3__PATA_DATA3                   0x184 0x56c 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D3__SD4_DAT4                     0x184 0x56c 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D3__USBH3_DATA4                  0x184 0x56c 0xa0c 0x5 0x0
+#define MX51_PAD_NANDF_D2__GPIO4_6                      0x188 0x570 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D2__NANDF_D2                     0x188 0x570 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D2__PATA_DATA2                   0x188 0x570 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D2__SD4_DAT5                     0x188 0x570 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D2__USBH3_DATA5                  0x188 0x570 0xa10 0x5 0x0
+#define MX51_PAD_NANDF_D1__GPIO4_7                      0x18c 0x574 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D1__NANDF_D1                     0x18c 0x574 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D1__PATA_DATA1                   0x18c 0x574 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D1__SD4_DAT6                     0x18c 0x574 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D1__USBH3_DATA6                  0x18c 0x574 0xa14 0x5 0x0
+#define MX51_PAD_NANDF_D0__GPIO4_8                      0x190 0x578 0x000 0x3 0x0
+#define MX51_PAD_NANDF_D0__NANDF_D0                     0x190 0x578 0x000 0x0 0x0
+#define MX51_PAD_NANDF_D0__PATA_DATA0                   0x190 0x578 0x000 0x1 0x0
+#define MX51_PAD_NANDF_D0__SD4_DAT7                     0x190 0x578 0x000 0x2 0x0
+#define MX51_PAD_NANDF_D0__USBH3_DATA7                  0x190 0x578 0xa18 0x5 0x0
+#define MX51_PAD_CSI1_D8__CSI1_D8                       0x194 0x57c 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D8__GPIO3_12                      0x194 0x57c 0x998 0x3 0x1
+#define MX51_PAD_CSI1_D9__CSI1_D9                       0x198 0x580 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D9__GPIO3_13                      0x198 0x580 0x000 0x3 0x0
+#define MX51_PAD_CSI1_D10__CSI1_D10                     0x19c 0x584 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D11__CSI1_D11                     0x1a0 0x588 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D12__CSI1_D12                     0x1a4 0x58c 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D13__CSI1_D13                     0x1a8 0x590 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D14__CSI1_D14                     0x1ac 0x594 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D15__CSI1_D15                     0x1b0 0x598 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D16__CSI1_D16                     0x1b4 0x59c 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D17__CSI1_D17                     0x1b8 0x5a0 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D18__CSI1_D18                     0x1bc 0x5a4 0x000 0x0 0x0
+#define MX51_PAD_CSI1_D19__CSI1_D19                     0x1c0 0x5a8 0x000 0x0 0x0
+#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC                 0x1c4 0x5ac 0x000 0x0 0x0
+#define MX51_PAD_CSI1_VSYNC__GPIO3_14                   0x1c4 0x5ac 0x000 0x3 0x0
+#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC                 0x1c8 0x5b0 0x000 0x0 0x0
+#define MX51_PAD_CSI1_HSYNC__GPIO3_15                   0x1c8 0x5b0 0x000 0x3 0x0
+#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK               0x000 0x5b4 0x000 0x0 0x0
+#define MX51_PAD_CSI1_MCLK__CSI1_MCLK                   0x000 0x5b8 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D12__CSI2_D12                     0x1cc 0x5bc 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D12__GPIO4_9                      0x1cc 0x5bc 0x000 0x3 0x0
+#define MX51_PAD_CSI2_D13__CSI2_D13                     0x1d0 0x5c0 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D13__GPIO4_10                     0x1d0 0x5c0 0x000 0x3 0x0
+#define MX51_PAD_CSI2_D14__CSI2_D14                     0x1d4 0x5c4 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D15__CSI2_D15                     0x1d8 0x5c8 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D16__CSI2_D16                     0x1dc 0x5cc 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D17__CSI2_D17                     0x1e0 0x5d0 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D18__CSI2_D18                     0x1e4 0x5d4 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D18__GPIO4_11                     0x1e4 0x5d4 0x000 0x3 0x0
+#define MX51_PAD_CSI2_D19__CSI2_D19                     0x1e8 0x5d8 0x000 0x0 0x0
+#define MX51_PAD_CSI2_D19__GPIO4_12                     0x1e8 0x5d8 0x000 0x3 0x0
+#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC                 0x1ec 0x5dc 0x000 0x0 0x0
+#define MX51_PAD_CSI2_VSYNC__GPIO4_13                   0x1ec 0x5dc 0x000 0x3 0x0
+#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC                 0x1f0 0x5e0 0x000 0x0 0x0
+#define MX51_PAD_CSI2_HSYNC__GPIO4_14                   0x1f0 0x5e0 0x000 0x3 0x0
+#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK               0x1f4 0x5e4 0x000 0x0 0x0
+#define MX51_PAD_CSI2_PIXCLK__GPIO4_15                  0x1f4 0x5e4 0x000 0x3 0x0
+#define MX51_PAD_I2C1_CLK__GPIO4_16                     0x1f8 0x5e8 0x000 0x3 0x0
+#define MX51_PAD_I2C1_CLK__I2C1_CLK                     0x1f8 0x5e8 0x000 0x0 0x0
+#define MX51_PAD_I2C1_DAT__GPIO4_17                     0x1fc 0x5ec 0x000 0x3 0x0
+#define MX51_PAD_I2C1_DAT__I2C1_DAT                     0x1fc 0x5ec 0x000 0x0 0x0
+#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD                  0x200 0x5f0 0x000 0x0 0x0
+#define MX51_PAD_AUD3_BB_TXD__GPIO4_18                  0x200 0x5f0 0x000 0x3 0x0
+#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD                  0x204 0x5f4 0x000 0x0 0x0
+#define MX51_PAD_AUD3_BB_RXD__GPIO4_19                  0x204 0x5f4 0x000 0x3 0x0
+#define MX51_PAD_AUD3_BB_RXD__UART3_RXD                 0x204 0x5f4 0x9f4 0x1 0x2
+#define MX51_PAD_AUD3_BB_CK__AUD3_TXC                   0x208 0x5f8 0x000 0x0 0x0
+#define MX51_PAD_AUD3_BB_CK__GPIO4_20                   0x208 0x5f8 0x000 0x3 0x0
+#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS                  0x20c 0x5fc 0x000 0x0 0x0
+#define MX51_PAD_AUD3_BB_FS__GPIO4_21                   0x20c 0x5fc 0x000 0x3 0x0
+#define MX51_PAD_AUD3_BB_FS__UART3_TXD                  0x20c 0x5fc 0x000 0x1 0x0
+#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI                0x210 0x600 0x000 0x0 0x0
+#define MX51_PAD_CSPI1_MOSI__GPIO4_22                   0x210 0x600 0x000 0x3 0x0
+#define MX51_PAD_CSPI1_MOSI__I2C1_SDA                   0x210 0x600 0x9b4 0x1 0x1
+#define MX51_PAD_CSPI1_MISO__AUD4_RXD                   0x214 0x604 0x8c4 0x1 0x1
+#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO                0x214 0x604 0x000 0x0 0x0
+#define MX51_PAD_CSPI1_MISO__GPIO4_23                   0x214 0x604 0x000 0x3 0x0
+#define MX51_PAD_CSPI1_SS0__AUD4_TXC                    0x218 0x608 0x8cc 0x1 0x1
+#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0                  0x218 0x608 0x000 0x0 0x0
+#define MX51_PAD_CSPI1_SS0__GPIO4_24                    0x218 0x608 0x000 0x3 0x0
+#define MX51_PAD_CSPI1_SS1__AUD4_TXD                    0x21c 0x60c 0x8c8 0x1 0x1
+#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1                  0x21c 0x60c 0x000 0x0 0x0
+#define MX51_PAD_CSPI1_SS1__GPIO4_25                    0x21c 0x60c 0x000 0x3 0x0
+#define MX51_PAD_CSPI1_RDY__AUD4_TXFS                   0x220 0x610 0x8d0 0x1 0x1
+#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY                  0x220 0x610 0x000 0x0 0x0
+#define MX51_PAD_CSPI1_RDY__GPIO4_26                    0x220 0x610 0x000 0x3 0x0
+#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK                0x224 0x614 0x000 0x0 0x0
+#define MX51_PAD_CSPI1_SCLK__GPIO4_27                   0x224 0x614 0x000 0x3 0x0
+#define MX51_PAD_CSPI1_SCLK__I2C1_SCL                   0x224 0x614 0x9b0 0x1 0x1
+#define MX51_PAD_UART1_RXD__GPIO4_28                    0x228 0x618 0x000 0x3 0x0
+#define MX51_PAD_UART1_RXD__UART1_RXD                   0x228 0x618 0x9e4 0x0 0x0
+#define MX51_PAD_UART1_TXD__GPIO4_29                    0x22c 0x61c 0x000 0x3 0x0
+#define MX51_PAD_UART1_TXD__PWM2_PWMO                   0x22c 0x61c 0x000 0x1 0x0
+#define MX51_PAD_UART1_TXD__UART1_TXD                   0x22c 0x61c 0x000 0x0 0x0
+#define MX51_PAD_UART1_RTS__GPIO4_30                    0x230 0x620 0x000 0x3 0x0
+#define MX51_PAD_UART1_RTS__UART1_RTS                   0x230 0x620 0x9e0 0x0 0x0
+#define MX51_PAD_UART1_CTS__GPIO4_31                    0x234 0x624 0x000 0x3 0x0
+#define MX51_PAD_UART1_CTS__UART1_CTS                   0x234 0x624 0x000 0x0 0x0
+#define MX51_PAD_UART2_RXD__FIRI_TXD                    0x238 0x628 0x000 0x1 0x0
+#define MX51_PAD_UART2_RXD__GPIO1_20                    0x238 0x628 0x000 0x3 0x0
+#define MX51_PAD_UART2_RXD__UART2_RXD                   0x238 0x628 0x9ec 0x0 0x2
+#define MX51_PAD_UART2_TXD__FIRI_RXD                    0x23c 0x62c 0x000 0x1 0x0
+#define MX51_PAD_UART2_TXD__GPIO1_21                    0x23c 0x62c 0x000 0x3 0x0
+#define MX51_PAD_UART2_TXD__UART2_TXD                   0x23c 0x62c 0x000 0x0 0x0
+#define MX51_PAD_UART3_RXD__CSI1_D0                     0x240 0x630 0x000 0x2 0x0
+#define MX51_PAD_UART3_RXD__GPIO1_22                    0x240 0x630 0x000 0x3 0x0
+#define MX51_PAD_UART3_RXD__UART1_DTR                   0x240 0x630 0x000 0x0 0x0
+#define MX51_PAD_UART3_RXD__UART3_RXD                   0x240 0x630 0x9f4 0x1 0x4
+#define MX51_PAD_UART3_TXD__CSI1_D1                     0x244 0x634 0x000 0x2 0x0
+#define MX51_PAD_UART3_TXD__GPIO1_23                    0x244 0x634 0x000 0x3 0x0
+#define MX51_PAD_UART3_TXD__UART1_DSR                   0x244 0x634 0x000 0x0 0x0
+#define MX51_PAD_UART3_TXD__UART3_TXD                   0x244 0x634 0x000 0x1 0x0
+#define MX51_PAD_OWIRE_LINE__GPIO1_24                   0x248 0x638 0x000 0x3 0x0
+#define MX51_PAD_OWIRE_LINE__OWIRE_LINE                 0x248 0x638 0x000 0x0 0x0
+#define MX51_PAD_OWIRE_LINE__SPDIF_OUT                  0x248 0x638 0x000 0x6 0x0
+#define MX51_PAD_KEY_ROW0__KEY_ROW0                     0x24c 0x63c 0x000 0x0 0x0
+#define MX51_PAD_KEY_ROW1__KEY_ROW1                     0x250 0x640 0x000 0x0 0x0
+#define MX51_PAD_KEY_ROW2__KEY_ROW2                     0x254 0x644 0x000 0x0 0x0
+#define MX51_PAD_KEY_ROW3__KEY_ROW3                     0x258 0x648 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL0__KEY_COL0                     0x25c 0x64c 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL0__PLL1_BYP                     0x25c 0x64c 0x90c 0x7 0x0
+#define MX51_PAD_KEY_COL1__KEY_COL1                     0x260 0x650 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL1__PLL2_BYP                     0x260 0x650 0x910 0x7 0x0
+#define MX51_PAD_KEY_COL2__KEY_COL2                     0x264 0x654 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL2__PLL3_BYP                     0x264 0x654 0x000 0x7 0x0
+#define MX51_PAD_KEY_COL3__KEY_COL3                     0x268 0x658 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL4__I2C2_SCL                     0x26c 0x65c 0x9b8 0x3 0x1
+#define MX51_PAD_KEY_COL4__KEY_COL4                     0x26c 0x65c 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL4__SPDIF_OUT1                   0x26c 0x65c 0x000 0x6 0x0
+#define MX51_PAD_KEY_COL4__UART1_RI                     0x26c 0x65c 0x000 0x1 0x0
+#define MX51_PAD_KEY_COL4__UART3_RTS                    0x26c 0x65c 0x9f0 0x2 0x4
+#define MX51_PAD_KEY_COL5__I2C2_SDA                     0x270 0x660 0x9bc 0x3 0x1
+#define MX51_PAD_KEY_COL5__KEY_COL5                     0x270 0x660 0x000 0x0 0x0
+#define MX51_PAD_KEY_COL5__UART1_DCD                    0x270 0x660 0x000 0x1 0x0
+#define MX51_PAD_KEY_COL5__UART3_CTS                    0x270 0x660 0x000 0x2 0x0
+#define MX51_PAD_USBH1_CLK__CSPI_SCLK                   0x278 0x678 0x914 0x1 0x1
+#define MX51_PAD_USBH1_CLK__GPIO1_25                    0x278 0x678 0x000 0x2 0x0
+#define MX51_PAD_USBH1_CLK__I2C2_SCL                    0x278 0x678 0x9b8 0x5 0x2
+#define MX51_PAD_USBH1_CLK__USBH1_CLK                   0x278 0x678 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DIR__CSPI_MOSI                   0x27c 0x67c 0x91c 0x1 0x1
+#define MX51_PAD_USBH1_DIR__GPIO1_26                    0x27c 0x67c 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DIR__I2C2_SDA                    0x27c 0x67c 0x9bc 0x5 0x2
+#define MX51_PAD_USBH1_DIR__USBH1_DIR                   0x27c 0x67c 0x000 0x0 0x0
+#define MX51_PAD_USBH1_STP__CSPI_RDY                    0x280 0x680 0x000 0x1 0x0
+#define MX51_PAD_USBH1_STP__GPIO1_27                    0x280 0x680 0x000 0x2 0x0
+#define MX51_PAD_USBH1_STP__UART3_RXD                   0x280 0x680 0x9f4 0x5 0x6
+#define MX51_PAD_USBH1_STP__USBH1_STP                   0x280 0x680 0x000 0x0 0x0
+#define MX51_PAD_USBH1_NXT__CSPI_MISO                   0x284 0x684 0x918 0x1 0x0
+#define MX51_PAD_USBH1_NXT__GPIO1_28                    0x284 0x684 0x000 0x2 0x0
+#define MX51_PAD_USBH1_NXT__UART3_TXD                   0x284 0x684 0x000 0x5 0x0
+#define MX51_PAD_USBH1_NXT__USBH1_NXT                   0x284 0x684 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA0__GPIO1_11                  0x288 0x688 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA0__UART2_CTS                 0x288 0x688 0x000 0x1 0x0
+#define MX51_PAD_USBH1_DATA0__USBH1_DATA0               0x288 0x688 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA1__GPIO1_12                  0x28c 0x68c 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA1__UART2_RXD                 0x28c 0x68c 0x9ec 0x1 0x4
+#define MX51_PAD_USBH1_DATA1__USBH1_DATA1               0x28c 0x68c 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA2__GPIO1_13                  0x290 0x690 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA2__UART2_TXD                 0x290 0x690 0x000 0x1 0x0
+#define MX51_PAD_USBH1_DATA2__USBH1_DATA2               0x290 0x690 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA3__GPIO1_14                  0x294 0x694 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA3__UART2_RTS                 0x294 0x694 0x9e8 0x1 0x5
+#define MX51_PAD_USBH1_DATA3__USBH1_DATA3               0x294 0x694 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA4__CSPI_SS0                  0x298 0x698 0x000 0x1 0x0
+#define MX51_PAD_USBH1_DATA4__GPIO1_15                  0x298 0x698 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA4__USBH1_DATA4               0x298 0x698 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA5__CSPI_SS1                  0x29c 0x69c 0x920 0x1 0x0
+#define MX51_PAD_USBH1_DATA5__GPIO1_16                  0x29c 0x69c 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA5__USBH1_DATA5               0x29c 0x69c 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA6__CSPI_SS3                  0x2a0 0x6a0 0x928 0x1 0x1
+#define MX51_PAD_USBH1_DATA6__GPIO1_17                  0x2a0 0x6a0 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA6__USBH1_DATA6               0x2a0 0x6a0 0x000 0x0 0x0
+#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3                0x2a4 0x6a4 0x000 0x1 0x0
+#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3                0x2a4 0x6a4 0x934 0x5 0x1
+#define MX51_PAD_USBH1_DATA7__GPIO1_18                  0x2a4 0x6a4 0x000 0x2 0x0
+#define MX51_PAD_USBH1_DATA7__USBH1_DATA7               0x2a4 0x6a4 0x000 0x0 0x0
+#define MX51_PAD_DI1_PIN11__DI1_PIN11                   0x2a8 0x6a8 0x000 0x0 0x0
+#define MX51_PAD_DI1_PIN11__ECSPI1_SS2                  0x2a8 0x6a8 0x000 0x7 0x0
+#define MX51_PAD_DI1_PIN11__GPIO3_0                     0x2a8 0x6a8 0x000 0x4 0x0
+#define MX51_PAD_DI1_PIN12__DI1_PIN12                   0x2ac 0x6ac 0x000 0x0 0x0
+#define MX51_PAD_DI1_PIN12__GPIO3_1                     0x2ac 0x6ac 0x978 0x4 0x1
+#define MX51_PAD_DI1_PIN13__DI1_PIN13                   0x2b0 0x6b0 0x000 0x0 0x0
+#define MX51_PAD_DI1_PIN13__GPIO3_2                     0x2b0 0x6b0 0x97c 0x4 0x1
+#define MX51_PAD_DI1_D0_CS__DI1_D0_CS                   0x2b4 0x6b4 0x000 0x0 0x0
+#define MX51_PAD_DI1_D0_CS__GPIO3_3                     0x2b4 0x6b4 0x980 0x4 0x1
+#define MX51_PAD_DI1_D1_CS__DI1_D1_CS                   0x2b8 0x6b8 0x000 0x0 0x0
+#define MX51_PAD_DI1_D1_CS__DISP1_PIN14                 0x2b8 0x6b8 0x000 0x2 0x0
+#define MX51_PAD_DI1_D1_CS__DISP1_PIN5                  0x2b8 0x6b8 0x000 0x3 0x0
+#define MX51_PAD_DI1_D1_CS__GPIO3_4                     0x2b8 0x6b8 0x984 0x4 0x1
+#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1             0x2bc 0x6bc 0x9a4 0x2 0x1
+#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN         0x2bc 0x6bc 0x9c4 0x0 0x0
+#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5                0x2bc 0x6bc 0x988 0x4 0x1
+#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6             0x2c0 0x6c0 0x000 0x3 0x0
+#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO         0x2c0 0x6c0 0x9c4 0x0 0x1
+#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6                0x2c0 0x6c0 0x98c 0x4 0x1
+#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17            0x2c4 0x6c4 0x000 0x2 0x0
+#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7             0x2c4 0x6c4 0x000 0x3 0x0
+#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK         0x2c4 0x6c4 0x000 0x0 0x0
+#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7                0x2c4 0x6c4 0x990 0x4 0x1
+#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK           0x2c8 0x6c8 0x000 0x2 0x0
+#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16             0x2c8 0x6c8 0x000 0x2 0x0
+#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8              0x2c8 0x6c8 0x000 0x3 0x0
+#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS           0x2c8 0x6c8 0x000 0x0 0x0
+#define MX51_PAD_DISPB2_SER_RS__GPIO3_8                 0x2c8 0x6c8 0x994 0x4 0x1
+#define MX51_PAD_DISP1_DAT0__DISP1_DAT0                 0x2cc 0x6cc 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT1__DISP1_DAT1                 0x2d0 0x6d0 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT2__DISP1_DAT2                 0x2d4 0x6d4 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT3__DISP1_DAT3                 0x2d8 0x6d8 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT4__DISP1_DAT4                 0x2dc 0x6dc 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT5__DISP1_DAT5                 0x2e0 0x6e0 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC               0x2e4 0x6e4 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT6__DISP1_DAT6                 0x2e4 0x6e4 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG            0x2e8 0x6e8 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT7__DISP1_DAT7                 0x2e8 0x6e8 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT8__BOOT_SRC0                  0x2ec 0x6ec 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT8__DISP1_DAT8                 0x2ec 0x6ec 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT9__BOOT_SRC1                  0x2f0 0x6f0 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT9__DISP1_DAT9                 0x2f0 0x6f0 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE           0x2f4 0x6f4 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT10__DISP1_DAT10               0x2f4 0x6f4 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2            0x2f8 0x6f8 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT11__DISP1_DAT11               0x2f8 0x6f8 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL              0x2fc 0x6fc 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT12__DISP1_DAT12               0x2fc 0x6fc 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0             0x300 0x700 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT13__DISP1_DAT13               0x300 0x700 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1             0x304 0x704 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT14__DISP1_DAT14               0x304 0x704 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH            0x308 0x708 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT15__DISP1_DAT15               0x308 0x708 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0           0x30c 0x70c 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT16__DISP1_DAT16               0x30c 0x70c 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1           0x310 0x710 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT17__DISP1_DAT17               0x310 0x710 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0          0x314 0x714 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT18__DISP1_DAT18               0x314 0x714 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT18__DISP2_PIN11               0x314 0x714 0x000 0x5 0x0
+#define MX51_PAD_DISP1_DAT18__DISP2_PIN5                0x314 0x714 0x000 0x4 0x0
+#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1          0x318 0x718 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT19__DISP1_DAT19               0x318 0x718 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT19__DISP2_PIN12               0x318 0x718 0x000 0x5 0x0
+#define MX51_PAD_DISP1_DAT19__DISP2_PIN6                0x318 0x718 0x000 0x4 0x0
+#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0            0x31c 0x71c 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT20__DISP1_DAT20               0x31c 0x71c 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT20__DISP2_PIN13               0x31c 0x71c 0x000 0x5 0x0
+#define MX51_PAD_DISP1_DAT20__DISP2_PIN7                0x31c 0x71c 0x000 0x4 0x0
+#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1            0x320 0x720 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT21__DISP1_DAT21               0x320 0x720 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT21__DISP2_PIN14               0x320 0x720 0x000 0x5 0x0
+#define MX51_PAD_DISP1_DAT21__DISP2_PIN8                0x320 0x720 0x000 0x4 0x0
+#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0            0x324 0x724 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT22__DISP1_DAT22               0x324 0x724 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS               0x324 0x724 0x000 0x6 0x0
+#define MX51_PAD_DISP1_DAT22__DISP2_DAT16               0x324 0x724 0x000 0x5 0x0
+#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1            0x328 0x728 0x000 0x7 0x0
+#define MX51_PAD_DISP1_DAT23__DISP1_DAT23               0x328 0x728 0x000 0x0 0x0
+#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS               0x328 0x728 0x000 0x6 0x0
+#define MX51_PAD_DISP1_DAT23__DISP2_DAT17               0x328 0x728 0x000 0x5 0x0
+#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS              0x328 0x728 0x000 0x4 0x0
+#define MX51_PAD_DI1_PIN3__DI1_PIN3                     0x32c 0x72c 0x000 0x0 0x0
+#define MX51_PAD_DI1_PIN2__DI1_PIN2                     0x330 0x734 0x000 0x0 0x0
+#define MX51_PAD_DI_GP2__DISP1_SER_CLK                  0x338 0x740 0x000 0x0 0x0
+#define MX51_PAD_DI_GP2__DISP2_WAIT                     0x338 0x740 0x9a8 0x2 0x1
+#define MX51_PAD_DI_GP3__CSI1_DATA_EN                   0x33c 0x744 0x9a0 0x3 0x1
+#define MX51_PAD_DI_GP3__DISP1_SER_DIO                  0x33c 0x744 0x9c0 0x0 0x0
+#define MX51_PAD_DI_GP3__FEC_TX_ER                      0x33c 0x744 0x000 0x2 0x0
+#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN                 0x340 0x748 0x99c 0x3 0x1
+#define MX51_PAD_DI2_PIN4__DI2_PIN4                     0x340 0x748 0x000 0x0 0x0
+#define MX51_PAD_DI2_PIN4__FEC_CRS                      0x340 0x748 0x950 0x2 0x1
+#define MX51_PAD_DI2_PIN2__DI2_PIN2                     0x344 0x74c 0x000 0x0 0x0
+#define MX51_PAD_DI2_PIN2__FEC_MDC                      0x344 0x74c 0x000 0x2 0x0
+#define MX51_PAD_DI2_PIN3__DI2_PIN3                     0x348 0x750 0x000 0x0 0x0
+#define MX51_PAD_DI2_PIN3__FEC_MDIO                     0x348 0x750 0x954 0x2 0x1
+#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK             0x34c 0x754 0x000 0x0 0x0
+#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1               0x34c 0x754 0x95c 0x2 0x1
+#define MX51_PAD_DI_GP4__DI2_PIN15                      0x350 0x758 0x000 0x4 0x0
+#define MX51_PAD_DI_GP4__DISP1_SER_DIN                  0x350 0x758 0x9c0 0x0 0x1
+#define MX51_PAD_DI_GP4__DISP2_PIN1                     0x350 0x758 0x000 0x3 0x0
+#define MX51_PAD_DI_GP4__FEC_RDATA2                     0x350 0x758 0x960 0x2 0x1
+#define MX51_PAD_DISP2_DAT0__DISP2_DAT0                 0x354 0x75c 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT0__FEC_RDATA3                 0x354 0x75c 0x964 0x2 0x1
+#define MX51_PAD_DISP2_DAT0__KEY_COL6                   0x354 0x75c 0x9c8 0x4 0x1
+#define MX51_PAD_DISP2_DAT0__UART3_RXD                  0x354 0x75c 0x9f4 0x5 0x8
+#define MX51_PAD_DISP2_DAT0__USBH3_CLK                  0x354 0x75c 0x9f8 0x3 0x1
+#define MX51_PAD_DISP2_DAT1__DISP2_DAT1                 0x358 0x760 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT1__FEC_RX_ER                  0x358 0x760 0x970 0x2 0x1
+#define MX51_PAD_DISP2_DAT1__KEY_COL7                   0x358 0x760 0x9cc 0x4 0x1
+#define MX51_PAD_DISP2_DAT1__UART3_TXD                  0x358 0x760 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT1__USBH3_DIR                  0x358 0x760 0xa1c 0x3 0x1
+#define MX51_PAD_DISP2_DAT2__DISP2_DAT2                 0x35c 0x764 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT3__DISP2_DAT3                 0x360 0x768 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT4__DISP2_DAT4                 0x364 0x76c 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT5__DISP2_DAT5                 0x368 0x770 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT6__DISP2_DAT6                 0x36c 0x774 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT6__FEC_TDATA1                 0x36c 0x774 0x000 0x2 0x0
+#define MX51_PAD_DISP2_DAT6__GPIO1_19                   0x36c 0x774 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT6__KEY_ROW4                   0x36c 0x774 0x9d0 0x4 0x1
+#define MX51_PAD_DISP2_DAT6__USBH3_STP                  0x36c 0x774 0xa24 0x3 0x1
+#define MX51_PAD_DISP2_DAT7__DISP2_DAT7                 0x370 0x778 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT7__FEC_TDATA2                 0x370 0x778 0x000 0x2 0x0
+#define MX51_PAD_DISP2_DAT7__GPIO1_29                   0x370 0x778 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT7__KEY_ROW5                   0x370 0x778 0x9d4 0x4 0x1
+#define MX51_PAD_DISP2_DAT7__USBH3_NXT                  0x370 0x778 0xa20 0x3 0x1
+#define MX51_PAD_DISP2_DAT8__DISP2_DAT8                 0x374 0x77c 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT8__FEC_TDATA3                 0x374 0x77c 0x000 0x2 0x0
+#define MX51_PAD_DISP2_DAT8__GPIO1_30                   0x374 0x77c 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT8__KEY_ROW6                   0x374 0x77c 0x9d8 0x4 0x1
+#define MX51_PAD_DISP2_DAT8__USBH3_DATA0                0x374 0x77c 0x9fc 0x3 0x1
+#define MX51_PAD_DISP2_DAT9__AUD6_RXC                   0x378 0x780 0x8f4 0x4 0x1
+#define MX51_PAD_DISP2_DAT9__DISP2_DAT9                 0x378 0x780 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT9__FEC_TX_EN                  0x378 0x780 0x000 0x2 0x0
+#define MX51_PAD_DISP2_DAT9__GPIO1_31                   0x378 0x780 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT9__USBH3_DATA1                0x378 0x780 0xa00 0x3 0x1
+#define MX51_PAD_DISP2_DAT10__DISP2_DAT10               0x37c 0x784 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS              0x37c 0x784 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT10__FEC_COL                   0x37c 0x784 0x94c 0x2 0x1
+#define MX51_PAD_DISP2_DAT10__KEY_ROW7                  0x37c 0x784 0x9dc 0x4 0x1
+#define MX51_PAD_DISP2_DAT10__USBH3_DATA2               0x37c 0x784 0xa04 0x3 0x1
+#define MX51_PAD_DISP2_DAT11__AUD6_TXD                  0x380 0x788 0x8f0 0x4 0x1
+#define MX51_PAD_DISP2_DAT11__DISP2_DAT11               0x380 0x788 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK                0x380 0x788 0x968 0x2 0x1
+#define MX51_PAD_DISP2_DAT11__GPIO1_10                  0x380 0x788 0x000 0x7 0x0
+#define MX51_PAD_DISP2_DAT11__USBH3_DATA3               0x380 0x788 0xa08 0x3 0x1
+#define MX51_PAD_DISP2_DAT12__AUD6_RXD                  0x384 0x78c 0x8ec 0x4 0x1
+#define MX51_PAD_DISP2_DAT12__DISP2_DAT12               0x384 0x78c 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT12__FEC_RX_DV                 0x384 0x78c 0x96c 0x2 0x1
+#define MX51_PAD_DISP2_DAT12__USBH3_DATA4               0x384 0x78c 0xa0c 0x3 0x1
+#define MX51_PAD_DISP2_DAT13__AUD6_TXC                  0x388 0x790 0x8fc 0x4 0x1
+#define MX51_PAD_DISP2_DAT13__DISP2_DAT13               0x388 0x790 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK                0x388 0x790 0x974 0x2 0x1
+#define MX51_PAD_DISP2_DAT13__USBH3_DATA5               0x388 0x790 0xa10 0x3 0x1
+#define MX51_PAD_DISP2_DAT14__AUD6_TXFS                 0x38c 0x794 0x900 0x4 0x1
+#define MX51_PAD_DISP2_DAT14__DISP2_DAT14               0x38c 0x794 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT14__FEC_RDATA0                0x38c 0x794 0x958 0x2 0x1
+#define MX51_PAD_DISP2_DAT14__USBH3_DATA6               0x38c 0x794 0xa14 0x3 0x1
+#define MX51_PAD_DISP2_DAT15__AUD6_RXFS                 0x390 0x798 0x8f8 0x4 0x1
+#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS              0x390 0x798 0x000 0x5 0x0
+#define MX51_PAD_DISP2_DAT15__DISP2_DAT15               0x390 0x798 0x000 0x0 0x0
+#define MX51_PAD_DISP2_DAT15__FEC_TDATA0                0x390 0x798 0x000 0x2 0x0
+#define MX51_PAD_DISP2_DAT15__USBH3_DATA7               0x390 0x798 0xa18 0x3 0x1
+#define MX51_PAD_SD1_CMD__AUD5_RXFS                     0x394 0x79c 0x8e0 0x1 0x1
+#define MX51_PAD_SD1_CMD__CSPI_MOSI                     0x394 0x79c 0x91c 0x2 0x2
+#define MX51_PAD_SD1_CMD__SD1_CMD                       0x394 0x79c 0x000 0x0 0x0
+#define MX51_PAD_SD1_CLK__AUD5_RXC                      0x398 0x7a0 0x8dc 0x1 0x1
+#define MX51_PAD_SD1_CLK__CSPI_SCLK                     0x398 0x7a0 0x914 0x2 0x2
+#define MX51_PAD_SD1_CLK__SD1_CLK                       0x398 0x7a0 0x000 0x0 0x0
+#define MX51_PAD_SD1_DATA0__AUD5_TXD                    0x39c 0x7a4 0x8d8 0x1 0x2
+#define MX51_PAD_SD1_DATA0__CSPI_MISO                   0x39c 0x7a4 0x918 0x2 0x1
+#define MX51_PAD_SD1_DATA0__SD1_DATA0                   0x39c 0x7a4 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA0__EIM_DA0                       0x01c 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA1__EIM_DA1                       0x020 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA2__EIM_DA2                       0x024 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA3__EIM_DA3                       0x028 0x000 0x000 0x0 0x0
+#define MX51_PAD_SD1_DATA1__AUD5_RXD                    0x3a0 0x7a8 0x8d4 0x1 0x2
+#define MX51_PAD_SD1_DATA1__SD1_DATA1                   0x3a0 0x7a8 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA4__EIM_DA4                       0x02c 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA5__EIM_DA5                       0x030 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA6__EIM_DA6                       0x034 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA7__EIM_DA7                       0x038 0x000 0x000 0x0 0x0
+#define MX51_PAD_SD1_DATA2__AUD5_TXC                    0x3a4 0x7ac 0x8e4 0x1 0x2
+#define MX51_PAD_SD1_DATA2__SD1_DATA2                   0x3a4 0x7ac 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA10__EIM_DA10                     0x044 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA11__EIM_DA11                     0x048 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA8__EIM_DA8                       0x03c 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA9__EIM_DA9                       0x040 0x000 0x000 0x0 0x0
+#define MX51_PAD_SD1_DATA3__AUD5_TXFS                   0x3a8 0x7b0 0x8e8 0x1 0x2
+#define MX51_PAD_SD1_DATA3__CSPI_SS1                    0x3a8 0x7b0 0x920 0x2 0x1
+#define MX51_PAD_SD1_DATA3__SD1_DATA3                   0x3a8 0x7b0 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_0__CSPI_SS2                      0x3ac 0x7b4 0x924 0x2 0x0
+#define MX51_PAD_GPIO1_0__GPIO1_0                       0x3ac 0x7b4 0x000 0x1 0x0
+#define MX51_PAD_GPIO1_0__SD1_CD                        0x3ac 0x7b4 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_1__CSPI_MISO                     0x3b0 0x7b8 0x918 0x2 0x2
+#define MX51_PAD_GPIO1_1__GPIO1_1                       0x3b0 0x7b8 0x000 0x1 0x0
+#define MX51_PAD_GPIO1_1__SD1_WP                        0x3b0 0x7b8 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA12__EIM_DA12                     0x04c 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA13__EIM_DA13                     0x050 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA14__EIM_DA14                     0x054 0x000 0x000 0x0 0x0
+#define MX51_PAD_EIM_DA15__EIM_DA15                     0x058 0x000 0x000 0x0 0x0
+#define MX51_PAD_SD2_CMD__CSPI_MOSI                     0x3b4 0x7bc 0x91c 0x2 0x3
+#define MX51_PAD_SD2_CMD__I2C1_SCL                      0x3b4 0x7bc 0x9b0 0x1 0x2
+#define MX51_PAD_SD2_CMD__SD2_CMD                       0x3b4 0x7bc 0x000 0x0 0x0
+#define MX51_PAD_SD2_CLK__CSPI_SCLK                     0x3b8 0x7c0 0x914 0x2 0x3
+#define MX51_PAD_SD2_CLK__I2C1_SDA                      0x3b8 0x7c0 0x9b4 0x1 0x2
+#define MX51_PAD_SD2_CLK__SD2_CLK                       0x3b8 0x7c0 0x000 0x0 0x0
+#define MX51_PAD_SD2_DATA0__CSPI_MISO                   0x3bc 0x7c4 0x918 0x2 0x3
+#define MX51_PAD_SD2_DATA0__SD1_DAT4                    0x3bc 0x7c4 0x000 0x1 0x0
+#define MX51_PAD_SD2_DATA0__SD2_DATA0                   0x3bc 0x7c4 0x000 0x0 0x0
+#define MX51_PAD_SD2_DATA1__SD1_DAT5                    0x3c0 0x7c8 0x000 0x1 0x0
+#define MX51_PAD_SD2_DATA1__SD2_DATA1                   0x3c0 0x7c8 0x000 0x0 0x0
+#define MX51_PAD_SD2_DATA1__USBH3_H2_DP                 0x3c0 0x7c8 0x000 0x2 0x0
+#define MX51_PAD_SD2_DATA2__SD1_DAT6                    0x3c4 0x7cc 0x000 0x1 0x0
+#define MX51_PAD_SD2_DATA2__SD2_DATA2                   0x3c4 0x7cc 0x000 0x0 0x0
+#define MX51_PAD_SD2_DATA2__USBH3_H2_DM                 0x3c4 0x7cc 0x000 0x2 0x0
+#define MX51_PAD_SD2_DATA3__CSPI_SS2                    0x3c8 0x7d0 0x924 0x2 0x1
+#define MX51_PAD_SD2_DATA3__SD1_DAT7                    0x3c8 0x7d0 0x000 0x1 0x0
+#define MX51_PAD_SD2_DATA3__SD2_DATA3                   0x3c8 0x7d0 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_2__CCM_OUT_2                     0x3cc 0x7d4 0x000 0x5 0x0
+#define MX51_PAD_GPIO1_2__GPIO1_2                       0x3cc 0x7d4 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_2__I2C2_SCL                      0x3cc 0x7d4 0x9b8 0x2 0x3
+#define MX51_PAD_GPIO1_2__PLL1_BYP                      0x3cc 0x7d4 0x90c 0x7 0x1
+#define MX51_PAD_GPIO1_2__PWM1_PWMO                     0x3cc 0x7d4 0x000 0x1 0x0
+#define MX51_PAD_GPIO1_3__GPIO1_3                       0x3d0 0x7d8 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_3__I2C2_SDA                      0x3d0 0x7d8 0x9bc 0x2 0x3
+#define MX51_PAD_GPIO1_3__PLL2_BYP                      0x3d0 0x7d8 0x910 0x7 0x1
+#define MX51_PAD_GPIO1_3__PWM2_PWMO                     0x3d0 0x7d8 0x000 0x1 0x0
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ             0x3d4 0x7fc 0x000 0x0 0x0
+#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B           0x3d4 0x7fc 0x000 0x1 0x0
+#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK                 0x3d8 0x804 0x908 0x4 0x1
+#define MX51_PAD_GPIO1_4__EIM_RDY                       0x3d8 0x804 0x938 0x3 0x1
+#define MX51_PAD_GPIO1_4__GPIO1_4                       0x3d8 0x804 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B                  0x3d8 0x804 0x000 0x2 0x0
+#define MX51_PAD_GPIO1_5__CSI2_MCLK                     0x3dc 0x808 0x000 0x6 0x0
+#define MX51_PAD_GPIO1_5__DISP2_PIN16                   0x3dc 0x808 0x000 0x3 0x0
+#define MX51_PAD_GPIO1_5__GPIO1_5                       0x3dc 0x808 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B                  0x3dc 0x808 0x000 0x2 0x0
+#define MX51_PAD_GPIO1_6__DISP2_PIN17                   0x3e0 0x80c 0x000 0x4 0x0
+#define MX51_PAD_GPIO1_6__GPIO1_6                       0x3e0 0x80c 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_6__REF_EN_B                      0x3e0 0x80c 0x000 0x3 0x0
+#define MX51_PAD_GPIO1_7__CCM_OUT_0                     0x3e4 0x810 0x000 0x3 0x0
+#define MX51_PAD_GPIO1_7__GPIO1_7                       0x3e4 0x810 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_7__SD2_WP                        0x3e4 0x810 0x000 0x6 0x0
+#define MX51_PAD_GPIO1_7__SPDIF_OUT1                    0x3e4 0x810 0x000 0x2 0x0
+#define MX51_PAD_GPIO1_8__CSI2_DATA_EN                  0x3e8 0x814 0x99c 0x2 0x2
+#define MX51_PAD_GPIO1_8__GPIO1_8                       0x3e8 0x814 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_8__SD2_CD                        0x3e8 0x814 0x000 0x6 0x0
+#define MX51_PAD_GPIO1_8__USBH3_PWR                     0x3e8 0x814 0x000 0x1 0x0
+#define MX51_PAD_GPIO1_9__CCM_OUT_1                     0x3ec 0x818 0x000 0x3 0x0
+#define MX51_PAD_GPIO1_9__DISP2_D1_CS                   0x3ec 0x818 0x000 0x2 0x0
+#define MX51_PAD_GPIO1_9__DISP2_SER_CS                  0x3ec 0x818 0x000 0x7 0x0
+#define MX51_PAD_GPIO1_9__GPIO1_9                       0x3ec 0x818 0x000 0x0 0x0
+#define MX51_PAD_GPIO1_9__SD2_LCTL                      0x3ec 0x818 0x000 0x6 0x0
+#define MX51_PAD_GPIO1_9__USBH3_OC                      0x3ec 0x818 0x000 0x1 0x0
+
+#endif /* __DTS_IMX51_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index fcf035bf7c5a..21bb786c5b31 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -10,7 +10,8 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include "imx51-pinfunc.h"
 
 / {
         aliases {
@@ -55,6 +56,24 @@
                 };
         };
 
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a8";
+                        reg = <0>;
+                        clock-latency = <61036>; /* two CLK32 periods */
+                        clocks = <&clks 24>;
+                        clock-names = "cpu";
+                        operating-points = <
+                                /* kHz  uV (No regulator support) */
+                                160000  0
+                                800000  0
+                        >;
+                };
+        };
+
         soc {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -67,6 +86,9 @@
                         compatible = "fsl,imx51-ipu";
                         reg = <0x40000000 0x20000000>;
                         interrupts = <11 10>;
+                        clocks = <&clks 59>, <&clks 110>, <&clks 61>;
+                        clock-names = "bus", "di0", "di1";
+                        resets = <&src 2>;
                 };
 
                 aips@70000000 { /* AIPS1 */
@@ -244,6 +266,14 @@
                                 status = "disabled";
                         };
 
+                        gpt: timer@73fa0000 {
+                                compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
+                                reg = <0x73fa0000 0x4000>;
+                                interrupts = <39>;
+                                clocks = <&clks 36>, <&clks 41>;
+                                clock-names = "ipg", "per";
+                        };
+
                         iomuxc: iomuxc@73fa8000 {
                                 compatible = "fsl,imx51-iomuxc";
                                 reg = <0x73fa8000 0x4000>;
@@ -251,10 +281,10 @@
                                 audmux {
                                         pinctrl_audmux_1: audmuxgrp-1 {
                                                 fsl,pins = <
-                                                        384 0x80000000  /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
-                                                        386 0x80000000  /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
-                                                        389 0x80000000  /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
-                                                        391 0x80000000  /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
+                                                        MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
+                                                        MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
+                                                        MX51_PAD_AUD3_BB_CK__AUD3_TXC  0x80000000
+                                                        MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
                                                 >;
                                         };
                                 };
@@ -262,46 +292,46 @@
                                 fec {
                                         pinctrl_fec_1: fecgrp-1 {
                                                 fsl,pins = <
-                                                        128 0x80000000  /* MX51_PAD_EIM_EB2__FEC_MDIO */
-                                                        134 0x80000000  /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
-                                                        146 0x80000000  /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
-                                                        152 0x80000000  /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
-                                                        158 0x80000000  /* MX51_PAD_EIM_CS4__FEC_RX_ER */
-                                                        165 0x80000000  /* MX51_PAD_EIM_CS5__FEC_CRS */
-                                                        206 0x80000000  /* MX51_PAD_NANDF_RB2__FEC_COL */
-                                                        213 0x80000000  /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
-                                                        293 0x80000000  /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
-                                                        298 0x80000000  /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
-                                                        225 0x80000000  /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
-                                                        231 0x80000000  /* MX51_PAD_NANDF_CS3__FEC_MDC */
-                                                        237 0x80000000  /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
-                                                        243 0x80000000  /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
-                                                        250 0x80000000  /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
-                                                        255 0x80000000  /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
-                                                        260 0x80000000  /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
+                                                        MX51_PAD_EIM_EB2__FEC_MDIO         0x80000000
+                                                        MX51_PAD_EIM_EB3__FEC_RDATA1       0x80000000
+                                                        MX51_PAD_EIM_CS2__FEC_RDATA2       0x80000000
+                                                        MX51_PAD_EIM_CS3__FEC_RDATA3       0x80000000
+                                                        MX51_PAD_EIM_CS4__FEC_RX_ER        0x80000000
+                                                        MX51_PAD_EIM_CS5__FEC_CRS          0x80000000
+                                                        MX51_PAD_NANDF_RB2__FEC_COL        0x80000000
+                                                        MX51_PAD_NANDF_RB3__FEC_RX_CLK     0x80000000
+                                                        MX51_PAD_NANDF_D9__FEC_RDATA0      0x80000000
+                                                        MX51_PAD_NANDF_D8__FEC_TDATA0      0x80000000
+                                                        MX51_PAD_NANDF_CS2__FEC_TX_ER      0x80000000
+                                                        MX51_PAD_NANDF_CS3__FEC_MDC        0x80000000
+                                                        MX51_PAD_NANDF_CS4__FEC_TDATA1     0x80000000
+                                                        MX51_PAD_NANDF_CS5__FEC_TDATA2     0x80000000
+                                                        MX51_PAD_NANDF_CS6__FEC_TDATA3     0x80000000
+                                                        MX51_PAD_NANDF_CS7__FEC_TX_EN      0x80000000
+                                                        MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
                                                 >;
                                         };
 
                                         pinctrl_fec_2: fecgrp-2 {
                                                 fsl,pins = <
-                                                        589 0x80000000 /* MX51_PAD_DI_GP3__FEC_TX_ER */
-                                                        592 0x80000000 /* MX51_PAD_DI2_PIN4__FEC_CRS */
-                                                        594 0x80000000 /* MX51_PAD_DI2_PIN2__FEC_MDC */
-                                                        596 0x80000000 /* MX51_PAD_DI2_PIN3__FEC_MDIO */
-                                                        598 0x80000000 /* MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 */
-                                                        602 0x80000000 /* MX51_PAD_DI_GP4__FEC_RDATA2 */
-                                                        604 0x80000000 /* MX51_PAD_DISP2_DAT0__FEC_RDATA3 */
-                                                        609 0x80000000 /* MX51_PAD_DISP2_DAT1__FEC_RX_ER */
-                                                        618 0x80000000 /* MX51_PAD_DISP2_DAT6__FEC_TDATA1 */
-                                                        623 0x80000000 /* MX51_PAD_DISP2_DAT7__FEC_TDATA2 */
-                                                        628 0x80000000 /* MX51_PAD_DISP2_DAT8__FEC_TDATA3 */
-                                                        634 0x80000000 /* MX51_PAD_DISP2_DAT9__FEC_TX_EN */
-                                                        639 0x80000000 /* MX51_PAD_DISP2_DAT10__FEC_COL */
-                                                        644 0x80000000 /* MX51_PAD_DISP2_DAT11__FEC_RX_CLK */
-                                                        649 0x80000000 /* MX51_PAD_DISP2_DAT12__FEC_RX_DV */
-                                                        653 0x80000000 /* MX51_PAD_DISP2_DAT13__FEC_TX_CLK */
-                                                        657 0x80000000 /* MX51_PAD_DISP2_DAT14__FEC_RDATA0 */
-                                                        662 0x80000000 /* MX51_PAD_DISP2_DAT15__FEC_TDATA0 */
+                                                        MX51_PAD_DI_GP3__FEC_TX_ER        0x80000000
+                                                        MX51_PAD_DI2_PIN4__FEC_CRS        0x80000000
+                                                        MX51_PAD_DI2_PIN2__FEC_MDC        0x80000000
+                                                        MX51_PAD_DI2_PIN3__FEC_MDIO       0x80000000
+                                                        MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
+                                                        MX51_PAD_DI_GP4__FEC_RDATA2       0x80000000
+                                                        MX51_PAD_DISP2_DAT0__FEC_RDATA3   0x80000000
+                                                        MX51_PAD_DISP2_DAT1__FEC_RX_ER    0x80000000
+                                                        MX51_PAD_DISP2_DAT6__FEC_TDATA1   0x80000000
+                                                        MX51_PAD_DISP2_DAT7__FEC_TDATA2   0x80000000
+                                                        MX51_PAD_DISP2_DAT8__FEC_TDATA3   0x80000000
+                                                        MX51_PAD_DISP2_DAT9__FEC_TX_EN    0x80000000
+                                                        MX51_PAD_DISP2_DAT10__FEC_COL     0x80000000
+                                                        MX51_PAD_DISP2_DAT11__FEC_RX_CLK  0x80000000
+                                                        MX51_PAD_DISP2_DAT12__FEC_RX_DV   0x80000000
+                                                        MX51_PAD_DISP2_DAT13__FEC_TX_CLK  0x80000000
+                                                        MX51_PAD_DISP2_DAT14__FEC_RDATA0  0x80000000
+                                                        MX51_PAD_DISP2_DAT15__FEC_TDATA0  0x80000000
                                                 >;
                                         };
                                 };
@@ -309,9 +339,19 @@
                                 ecspi1 {
                                         pinctrl_ecspi1_1: ecspi1grp-1 {
                                                 fsl,pins = <
-                                                        398 0x185       /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
-                                                        394 0x185       /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
-                                                        409 0x185       /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
+                                                        MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
+                                                        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
+                                                        MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
+                                                >;
+                                        };
+                                };
+
+                                ecspi2 {
+                                        pinctrl_ecspi2_1: ecspi2grp-1 {
+                                                fsl,pins = <
+                                                        MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
+                                                        MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
+                                                        MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
                                                 >;
                                         };
                                 };
@@ -319,12 +359,12 @@
                                 esdhc1 {
                                         pinctrl_esdhc1_1: esdhc1grp-1 {
                                                 fsl,pins = <
-                                                        666 0x400020d5  /* MX51_PAD_SD1_CMD__SD1_CMD */
-                                                        669 0x20d5      /* MX51_PAD_SD1_CLK__SD1_CLK */
-                                                        672 0x20d5      /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
-                                                        678 0x20d5      /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
-                                                        684 0x20d5      /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
-                                                        691 0x20d5      /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
+                                                        MX51_PAD_SD1_CMD__SD1_CMD     0x400020d5
+                                                        MX51_PAD_SD1_CLK__SD1_CLK     0x20d5
+                                                        MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
+                                                        MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
+                                                        MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
+                                                        MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
                                                 >;
                                         };
                                 };
@@ -332,12 +372,12 @@
                                 esdhc2 {
                                         pinctrl_esdhc2_1: esdhc2grp-1 {
                                                 fsl,pins = <
-                                                        704 0x400020d5  /* MX51_PAD_SD2_CMD__SD2_CMD */
-                                                        707 0x20d5      /* MX51_PAD_SD2_CLK__SD2_CLK */
-                                                        710 0x20d5      /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
-                                                        712 0x20d5      /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
-                                                        715 0x20d5      /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
-                                                        719 0x20d5      /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
+                                                        MX51_PAD_SD2_CMD__SD2_CMD     0x400020d5
+                                                        MX51_PAD_SD2_CLK__SD2_CLK     0x20d5
+                                                        MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
+                                                        MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
+                                                        MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
+                                                        MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
                                                 >;
                                         };
                                 };
@@ -345,8 +385,15 @@
                                 i2c2 {
                                         pinctrl_i2c2_1: i2c2grp-1 {
                                                 fsl,pins = <
-                                                        449 0x400001ed  /* MX51_PAD_KEY_COL4__I2C2_SCL */
-                                                        454 0x400001ed  /* MX51_PAD_KEY_COL5__I2C2_SDA */
+                                                        MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
+                                                        MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
+                                                >;
+                                        };
+
+                                        pinctrl_i2c2_2: i2c2grp-2 {
+                                                fsl,pins = <
+                                                        MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
+                                                        MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
                                                 >;
                                         };
                                 };
@@ -354,32 +401,32 @@
                                 ipu_disp1 {
                                         pinctrl_ipu_disp1_1: ipudisp1grp-1 {
                                                 fsl,pins = <
-                                                        528 0x5 /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */
-                                                        529 0x5 /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */
-                                                        530 0x5 /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */
-                                                        531 0x5 /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */
-                                                        532 0x5 /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */
-                                                        533 0x5 /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */
-                                                        535 0x5 /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */
-                                                        537 0x5 /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */
-                                                        539 0x5 /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */
-                                                        541 0x5 /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */
-                                                        543 0x5 /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */
-                                                        545 0x5 /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */
-                                                        547 0x5 /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */
-                                                        549 0x5 /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */
-                                                        551 0x5 /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */
-                                                        553 0x5 /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */
-                                                        555 0x5 /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */
-                                                        557 0x5 /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */
-                                                        559 0x5 /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */
-                                                        563 0x5 /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */
-                                                        567 0x5 /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */
-                                                        571 0x5 /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */
-                                                        575 0x5 /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */
-                                                        579 0x5 /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */
-                                                        584 0x5 /* MX51_PAD_DI1_PIN2__DI1_PIN2 (hsync) */
-                                                        583 0x5 /* MX51_PAD_DI1_PIN3__DI1_PIN3 (vsync) */
+                                                        MX51_PAD_DISP1_DAT0__DISP1_DAT0   0x5
+                                                        MX51_PAD_DISP1_DAT1__DISP1_DAT1   0x5
+                                                        MX51_PAD_DISP1_DAT2__DISP1_DAT2   0x5
+                                                        MX51_PAD_DISP1_DAT3__DISP1_DAT3   0x5
+                                                        MX51_PAD_DISP1_DAT4__DISP1_DAT4   0x5
+                                                        MX51_PAD_DISP1_DAT5__DISP1_DAT5   0x5
+                                                        MX51_PAD_DISP1_DAT6__DISP1_DAT6   0x5
+                                                        MX51_PAD_DISP1_DAT7__DISP1_DAT7   0x5
+                                                        MX51_PAD_DISP1_DAT8__DISP1_DAT8   0x5
+                                                        MX51_PAD_DISP1_DAT9__DISP1_DAT9   0x5
+                                                        MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
+                                                        MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
+                                                        MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
+                                                        MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
+                                                        MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
+                                                        MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
+                                                        MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
+                                                        MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
+                                                        MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
+                                                        MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
+                                                        MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
+                                                        MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
+                                                        MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
+                                                        MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
+                                                        MX51_PAD_DI1_PIN2__DI1_PIN2       0x5 /* hsync */
+                                                        MX51_PAD_DI1_PIN3__DI1_PIN3       0x5 /* vsync */
                                                 >;
                                         };
                                 };
@@ -387,26 +434,62 @@
                                 ipu_disp2 {
                                         pinctrl_ipu_disp2_1: ipudisp2grp-1 {
                                                 fsl,pins = <
-                                                        603 0x5 /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */
-                                                        608 0x5 /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */
-                                                        613 0x5 /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */
-                                                        614 0x5 /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */
-                                                        615 0x5 /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */
-                                                        616 0x5 /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */
-                                                        617 0x5 /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */
-                                                        622 0x5 /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */
-                                                        627 0x5 /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */
-                                                        633 0x5 /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */
-                                                        637 0x5 /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */
-                                                        643 0x5 /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */
-                                                        648 0x5 /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */
-                                                        652 0x5 /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */
-                                                        656 0x5 /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */
-                                                        661 0x5 /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */
-                                                        593 0x5 /* MX51_PAD_DI2_PIN2__DI2_PIN2 (hsync) */
-                                                        595 0x5 /* MX51_PAD_DI2_PIN3__DI2_PIN3 (vsync) */
-                                                        597 0x5 /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */
-                                                        599 0x5 /* MX51_PAD_DI_GP4__DI2_PIN15 */
+                                                        MX51_PAD_DISP2_DAT0__DISP2_DAT0     0x5
+                                                        MX51_PAD_DISP2_DAT1__DISP2_DAT1     0x5
+                                                        MX51_PAD_DISP2_DAT2__DISP2_DAT2     0x5
+                                                        MX51_PAD_DISP2_DAT3__DISP2_DAT3     0x5
+                                                        MX51_PAD_DISP2_DAT4__DISP2_DAT4     0x5
+                                                        MX51_PAD_DISP2_DAT5__DISP2_DAT5     0x5
+                                                        MX51_PAD_DISP2_DAT6__DISP2_DAT6     0x5
+                                                        MX51_PAD_DISP2_DAT7__DISP2_DAT7     0x5
+                                                        MX51_PAD_DISP2_DAT8__DISP2_DAT8     0x5
+                                                        MX51_PAD_DISP2_DAT9__DISP2_DAT9     0x5
+                                                        MX51_PAD_DISP2_DAT10__DISP2_DAT10   0x5
+                                                        MX51_PAD_DISP2_DAT11__DISP2_DAT11   0x5
+                                                        MX51_PAD_DISP2_DAT12__DISP2_DAT12   0x5
+                                                        MX51_PAD_DISP2_DAT13__DISP2_DAT13   0x5
+                                                        MX51_PAD_DISP2_DAT14__DISP2_DAT14   0x5
+                                                        MX51_PAD_DISP2_DAT15__DISP2_DAT15   0x5
+                                                        MX51_PAD_DI2_PIN2__DI2_PIN2         0x5 /* hsync */
+                                                        MX51_PAD_DI2_PIN3__DI2_PIN3         0x5 /* vsync */
+                                                        MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
+                                                        MX51_PAD_DI_GP4__DI2_PIN15          0x5
+                                                >;
+                                        };
+                                };
+
+                                pata {
+                                        pinctrl_pata_1: patagrp-1 {
+                                                fsl,pins = <
+                                                        MX51_PAD_NANDF_WE_B__PATA_DIOW          0x2004
+                                                        MX51_PAD_NANDF_RE_B__PATA_DIOR          0x2004
+                                                        MX51_PAD_NANDF_ALE__PATA_BUFFER_EN      0x2004
+                                                        MX51_PAD_NANDF_CLE__PATA_RESET_B        0x2004
+                                                        MX51_PAD_NANDF_WP_B__PATA_DMACK         0x2004
+                                                        MX51_PAD_NANDF_RB0__PATA_DMARQ          0x2004
+                                                        MX51_PAD_NANDF_RB1__PATA_IORDY          0x2004
+                                                        MX51_PAD_GPIO_NAND__PATA_INTRQ          0x2004
+                                                        MX51_PAD_NANDF_CS2__PATA_CS_0           0x2004
+                                                        MX51_PAD_NANDF_CS3__PATA_CS_1           0x2004
+                                                        MX51_PAD_NANDF_CS4__PATA_DA_0           0x2004
+                                                        MX51_PAD_NANDF_CS5__PATA_DA_1           0x2004
+                                                        MX51_PAD_NANDF_CS6__PATA_DA_2           0x2004
+                                                        MX51_PAD_NANDF_D15__PATA_DATA15         0x2004
+                                                        MX51_PAD_NANDF_D14__PATA_DATA14         0x2004
+                                                        MX51_PAD_NANDF_D13__PATA_DATA13         0x2004
+                                                        MX51_PAD_NANDF_D12__PATA_DATA12         0x2004
+                                                        MX51_PAD_NANDF_D11__PATA_DATA11         0x2004
+                                                        MX51_PAD_NANDF_D10__PATA_DATA10         0x2004
+                                                        MX51_PAD_NANDF_D9__PATA_DATA9           0x2004
+                                                        MX51_PAD_NANDF_D8__PATA_DATA8           0x2004
+                                                        MX51_PAD_NANDF_D7__PATA_DATA7           0x2004
+                                                        MX51_PAD_NANDF_D6__PATA_DATA6           0x2004
+                                                        MX51_PAD_NANDF_D5__PATA_DATA5           0x2004
+                                                        MX51_PAD_NANDF_D4__PATA_DATA4           0x2004
+                                                        MX51_PAD_NANDF_D3__PATA_DATA3           0x2004
+                                                        MX51_PAD_NANDF_D2__PATA_DATA2           0x2004
+                                                        MX51_PAD_NANDF_D1__PATA_DATA1           0x2004
+                                                        MX51_PAD_NANDF_D0__PATA_DATA0           0x2004
                                                 >;
                                         };
                                 };
@@ -414,10 +497,10 @@
                                 uart1 {
                                         pinctrl_uart1_1: uart1grp-1 {
                                                 fsl,pins = <
-                                                        413 0x1c5       /* MX51_PAD_UART1_RXD__UART1_RXD */
-                                                        416 0x1c5       /* MX51_PAD_UART1_TXD__UART1_TXD */
-                                                        418 0x1c5       /* MX51_PAD_UART1_RTS__UART1_RTS */
-                                                        420 0x1c5       /* MX51_PAD_UART1_CTS__UART1_CTS */
+                                                        MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
+                                                        MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
+                                                        MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
+                                                        MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
                                                 >;
                                         };
                                 };
@@ -425,8 +508,8 @@
                                 uart2 {
                                         pinctrl_uart2_1: uart2grp-1 {
                                                 fsl,pins = <
-                                                        423 0x1c5       /* MX51_PAD_UART2_RXD__UART2_RXD */
-                                                        426 0x1c5       /* MX51_PAD_UART2_TXD__UART2_TXD */
+                                                        MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
+                                                        MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
                                                 >;
                                         };
                                 };
@@ -434,17 +517,17 @@
                                 uart3 {
                                         pinctrl_uart3_1: uart3grp-1 {
                                                 fsl,pins = <
-                                                        54 0x1c5        /* MX51_PAD_EIM_D25__UART3_RXD */
-                                                        59 0x1c5        /* MX51_PAD_EIM_D26__UART3_TXD */
-                                                        65 0x1c5        /* MX51_PAD_EIM_D27__UART3_RTS */
-                                                        49 0x1c5        /* MX51_PAD_EIM_D24__UART3_CTS */
+                                                        MX51_PAD_EIM_D25__UART3_RXD 0x1c5
+                                                        MX51_PAD_EIM_D26__UART3_TXD 0x1c5
+                                                        MX51_PAD_EIM_D27__UART3_RTS 0x1c5
+                                                        MX51_PAD_EIM_D24__UART3_CTS 0x1c5
                                                 >;
                                         };
 
                                         pinctrl_uart3_2: uart3grp-2 {
                                                 fsl,pins = <
-                                                        434 0x1c5       /* MX51_PAD_UART3_RXD__UART3_RXD */
-                                                        430 0x1c5       /* MX51_PAD_UART3_TXD__UART3_TXD */
+                                                        MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
+                                                        MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
                                                 >;
                                         };
                                 };
@@ -452,14 +535,14 @@
                                 kpp {
                                         pinctrl_kpp_1: kppgrp-1 {
                                                 fsl,pins = <
-                                                        438 0xe0        /* MX51_PAD_KEY_ROW0__KEY_ROW0 */
-                                                        439 0xe0        /* MX51_PAD_KEY_ROW1__KEY_ROW1 */
-                                                        440 0xe0        /* MX51_PAD_KEY_ROW2__KEY_ROW2 */
-                                                        441 0xe0        /* MX51_PAD_KEY_ROW3__KEY_ROW3 */
-                                                        442 0xe8        /* MX51_PAD_KEY_COL0__KEY_COL0 */
-                                                        444 0xe8        /* MX51_PAD_KEY_COL1__KEY_COL1 */
-                                                        446 0xe8        /* MX51_PAD_KEY_COL2__KEY_COL2 */
-                                                        448 0xe8        /* MX51_PAD_KEY_COL3__KEY_COL3 */
+                                                        MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
+                                                        MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
+                                                        MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
+                                                        MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
+                                                        MX51_PAD_KEY_COL0__KEY_COL0 0xe8
+                                                        MX51_PAD_KEY_COL1__KEY_COL1 0xe8
+                                                        MX51_PAD_KEY_COL2__KEY_COL2 0xe8
+                                                        MX51_PAD_KEY_COL3__KEY_COL3 0xe8
                                                 >;
                                         };
                                 };
@@ -501,6 +584,12 @@
                                 status = "disabled";
                         };
 
+                        src: src@73fd0000 {
+                                compatible = "fsl,imx51-src";
+                                reg = <0x73fd0000 0x4000>;
+                                #reset-cells = <1>;
+                        };
+
                         clks: ccm@73fd4000{
                                 compatible = "fsl,imx51-ccm";
                                 reg = <0x73fd4000 0x4000>;
@@ -591,6 +680,14 @@
                                 status = "disabled";
                         };
 
+                        pata: pata@83fe0000 {
+                                compatible = "fsl,imx51-pata", "fsl,imx27-pata";
+                                reg = <0x83fe0000 0x4000>;
+                                interrupts = <70>;
+                                clocks = <&clks 161>;
+                                status = "disabled";
+                        };
+
                         ssi3: ssi@83fe8000 {
                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
                                 reg = <0x83fe8000 0x4000>;
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index e049fd0319e8..174f86938c89 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -11,7 +11,7 @@
  */
 
 /dts-v1/;
-/include/ "imx53.dtsi"
+#include "imx53.dtsi"
 
 / {
         model = "Freescale i.MX53 Automotive Reference Design Board";
@@ -112,40 +112,40 @@
         hog {
                 pinctrl_hog: hoggrp {
                         fsl,pins = <
-                                1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
-                                1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
-                                486  0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
-                                739  0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
-                                218  0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
-                                226  0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
-                                233  0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
-                                241  0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
-                                429  0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
-                                435  0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
-                                441  0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
-                                448  0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
-                                456  0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
-                                464  0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
-                                471  0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
-                                477  0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
-                                492  0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
-                                500  0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
-                                508  0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
-                                516  0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
-                                524  0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
-                                532  0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
-                                540  0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
-                                548  0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
-                                637  0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
-                                642  0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
-                                647  0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
-                                652  0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
-                                657  0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
-                                662  0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
-                                667  0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
-                                611  0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
-                                616  0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
-                                607  0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
+                                MX53_PAD_GPIO_1__GPIO1_1             0x80000000
+                                MX53_PAD_GPIO_9__GPIO1_9             0x80000000
+                                MX53_PAD_EIM_EB3__GPIO2_31           0x80000000
+                                MX53_PAD_GPIO_10__GPIO4_0            0x80000000
+                                MX53_PAD_DISP0_DAT16__GPIO5_10       0x80000000
+                                MX53_PAD_DISP0_DAT17__GPIO5_11       0x80000000
+                                MX53_PAD_DISP0_DAT18__GPIO5_12       0x80000000
+                                MX53_PAD_DISP0_DAT19__GPIO5_13       0x80000000
+                                MX53_PAD_EIM_D16__EMI_WEIM_D_16      0x80000000
+                                MX53_PAD_EIM_D17__EMI_WEIM_D_17      0x80000000
+                                MX53_PAD_EIM_D18__EMI_WEIM_D_18      0x80000000
+                                MX53_PAD_EIM_D19__EMI_WEIM_D_19      0x80000000
+                                MX53_PAD_EIM_D20__EMI_WEIM_D_20      0x80000000
+                                MX53_PAD_EIM_D21__EMI_WEIM_D_21      0x80000000
+                                MX53_PAD_EIM_D22__EMI_WEIM_D_22      0x80000000
+                                MX53_PAD_EIM_D23__EMI_WEIM_D_23      0x80000000
+                                MX53_PAD_EIM_D24__EMI_WEIM_D_24      0x80000000
+                                MX53_PAD_EIM_D25__EMI_WEIM_D_25      0x80000000
+                                MX53_PAD_EIM_D26__EMI_WEIM_D_26      0x80000000
+                                MX53_PAD_EIM_D27__EMI_WEIM_D_27      0x80000000
+                                MX53_PAD_EIM_D28__EMI_WEIM_D_28      0x80000000
+                                MX53_PAD_EIM_D29__EMI_WEIM_D_29      0x80000000
+                                MX53_PAD_EIM_D30__EMI_WEIM_D_30      0x80000000
+                                MX53_PAD_EIM_D31__EMI_WEIM_D_31      0x80000000
+                                MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x80000000
+                                MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x80000000
+                                MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x80000000
+                                MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x80000000
+                                MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x80000000
+                                MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x80000000
+                                MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x80000000
+                                MX53_PAD_EIM_OE__EMI_WEIM_OE         0x80000000
+                                MX53_PAD_EIM_RW__EMI_WEIM_RW         0x80000000
+                                MX53_PAD_EIM_CS1__EMI_WEIM_CS_1      0x80000000
                         >;
                 };
         };
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index 85a89b52f9b8..801fda728ed6 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -11,7 +11,7 @@
  */
 
 /dts-v1/;
-/include/ "imx53.dtsi"
+#include "imx53.dtsi"
 
 / {
         model = "Freescale i.MX53 Evaluation Kit";
@@ -82,14 +82,14 @@
         hog {
                 pinctrl_hog: hoggrp {
                         fsl,pins = <
-                                424  0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
-                                449  0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
-                                693  0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
-                                697  0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
-                                701  0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
-                                705  0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
-                                868  0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
-                                873  0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
+                                MX53_PAD_EIM_EB2__GPIO2_30  0x80000000
+                                MX53_PAD_EIM_D19__GPIO3_19  0x80000000
+                                MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
+                                MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
+                                MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
+                                MX53_PAD_EIM_DA14__GPIO3_14 0x80000000
+                                MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
+                                MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
                         >;
                 };
         };
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts
index 468c0a1d48d9..445a01119cc5 100644
--- a/arch/arm/boot/dts/imx53-mba53.dts
+++ b/arch/arm/boot/dts/imx53-mba53.dts
@@ -11,7 +11,7 @@
  */
 
 /dts-v1/;
-/include/ "imx53-tqma53.dtsi"
+#include "imx53-tqma53.dtsi"
 
 / {
         model = "TQ MBa53 starter kit";
@@ -21,51 +21,57 @@
 &iomuxc {
         lvds1 {
                 pinctrl_lvds1_1: lvds1-grp1 {
-                        fsl,pins = <730 0x10000         /* LVDS0_TX3 */
-                                    732 0x10000         /* LVDS0_CLK */
-                                    734 0x10000         /* LVDS0_TX2 */
-                                    736 0x10000         /* LVDS0_TX1 */
-                                    738 0x10000>;       /* LVDS0_TX0 */
+                        fsl,pins = <
+                                MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x10000
+                                MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x10000
+                                MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x10000
+                                MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x10000
+                                MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x10000
+                        >;
                 };
 
                 pinctrl_lvds1_2: lvds1-grp2 {
-                        fsl,pins = <720 0x10000         /* LVDS1_TX3 */
-                                    722 0x10000         /* LVDS1_TX2 */
-                                    724 0x10000         /* LVDS1_CLK */
-                                    726 0x10000         /* LVDS1_TX1 */
-                                    728 0x10000>;       /* LVDS1_TX0 */
+                        fsl,pins = <
+                                MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x10000
+                                MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x10000
+                                MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x10000
+                                MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x10000
+                                MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x10000
+                        >;
                 };
         };
 
         disp1 {
                 pinctrl_disp1_1: disp1-grp1 {
-                        fsl,pins = <689 0x10000         /* DISP1_DRDY   */
-                                    482 0x10000         /* DISP1_HSYNC  */
-                                    489 0x10000         /* DISP1_VSYNC  */
-                                    515 0x10000         /* DISP1_DAT_22 */
-                                    523 0x10000         /* DISP1_DAT_23 */
-                                    545 0x10000         /* DISP1_DAT_21 */
-                                    553 0x10000         /* DISP1_DAT_20 */
-                                    558 0x10000         /* DISP1_DAT_19 */
-                                    564 0x10000         /* DISP1_DAT_18 */
-                                    570 0x10000         /* DISP1_DAT_17 */
-                                    575 0x10000         /* DISP1_DAT_16 */
-                                    580 0x10000         /* DISP1_DAT_15 */
-                                    585 0x10000         /* DISP1_DAT_14 */
-                                    590 0x10000         /* DISP1_DAT_13 */
-                                    595 0x10000         /* DISP1_DAT_12 */
-                                    628 0x10000         /* DISP1_DAT_11 */
-                                    634 0x10000         /* DISP1_DAT_10 */
-                                    639 0x10000         /* DISP1_DAT_9  */
-                                    644 0x10000         /* DISP1_DAT_8  */
-                                    649 0x10000         /* DISP1_DAT_7  */
-                                    654 0x10000         /* DISP1_DAT_6  */
-                                    659 0x10000         /* DISP1_DAT_5  */
-                                    664 0x10000         /* DISP1_DAT_4  */
-                                    669 0x10000         /* DISP1_DAT_3  */
-                                    674 0x10000         /* DISP1_DAT_2  */
-                                    679 0x10000         /* DISP1_DAT_1  */
-                                    684 0x10000>;       /* DISP1_DAT_0  */
+                        fsl,pins = <
+                                MX53_PAD_EIM_DA10__IPU_DI1_PIN15   0x10000 /* DISP1_DRDY */
+                                MX53_PAD_EIM_D23__IPU_DI1_PIN2     0x10000 /* DISP1_HSYNC */
+                                MX53_PAD_EIM_EB3__IPU_DI1_PIN3     0x10000 /* DISP1_VSYNC */
+                                MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x10000
+                                MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x10000
+                                MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x10000
+                                MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x10000
+                                MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x10000
+                                MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x10000
+                                MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x10000
+                                MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x10000
+                                MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x10000
+                                MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x10000
+                                MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x10000
+                                MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x10000
+                                MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x10000
+                                MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x10000
+                                MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9  0x10000
+                                MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8  0x10000
+                                MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7  0x10000
+                                MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6  0x10000
+                                MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5  0x10000
+                                MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4  0x10000
+                                MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3  0x10000
+                                MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2  0x10000
+                                MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1  0x10000
+                                MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x10000
+                        >;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/imx53-pinfunc.h b/arch/arm/boot/dts/imx53-pinfunc.h
new file mode 100644
index 000000000000..aec406bc65eb
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-pinfunc.h
@@ -0,0 +1,1189 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX53_PINFUNC_H
+#define __DTS_IMX53_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX53_PAD_GPIO_19__KPP_COL_5                             0x020 0x348 0x840 0x0 0x0
+#define MX53_PAD_GPIO_19__GPIO4_5                               0x020 0x348 0x000 0x1 0x0
+#define MX53_PAD_GPIO_19__CCM_CLKO                              0x020 0x348 0x000 0x2 0x0
+#define MX53_PAD_GPIO_19__SPDIF_OUT1                            0x020 0x348 0x000 0x3 0x0
+#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2                  0x020 0x348 0x000 0x4 0x0
+#define MX53_PAD_GPIO_19__ECSPI1_RDY                            0x020 0x348 0x000 0x5 0x0
+#define MX53_PAD_GPIO_19__FEC_TDATA_3                           0x020 0x348 0x000 0x6 0x0
+#define MX53_PAD_GPIO_19__SRC_INT_BOOT                          0x020 0x348 0x000 0x7 0x0
+#define MX53_PAD_KEY_COL0__KPP_COL_0                            0x024 0x34c 0x000 0x0 0x0
+#define MX53_PAD_KEY_COL0__GPIO4_6                              0x024 0x34c 0x000 0x1 0x0
+#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC                      0x024 0x34c 0x758 0x2 0x0
+#define MX53_PAD_KEY_COL0__UART4_TXD_MUX                        0x024 0x34c 0x000 0x4 0x0
+#define MX53_PAD_KEY_COL0__ECSPI1_SCLK                          0x024 0x34c 0x79c 0x5 0x0
+#define MX53_PAD_KEY_COL0__FEC_RDATA_3                          0x024 0x34c 0x000 0x6 0x0
+#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST                       0x024 0x34c 0x000 0x7 0x0
+#define MX53_PAD_KEY_ROW0__KPP_ROW_0                            0x028 0x350 0x000 0x0 0x0
+#define MX53_PAD_KEY_ROW0__GPIO4_7                              0x028 0x350 0x000 0x1 0x0
+#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD                      0x028 0x350 0x74c 0x2 0x0
+#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX                        0x028 0x350 0x890 0x4 0x1
+#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI                          0x028 0x350 0x7a4 0x5 0x0
+#define MX53_PAD_KEY_ROW0__FEC_TX_ER                            0x028 0x350 0x000 0x6 0x0
+#define MX53_PAD_KEY_COL1__KPP_COL_1                            0x02c 0x354 0x000 0x0 0x0
+#define MX53_PAD_KEY_COL1__GPIO4_8                              0x02c 0x354 0x000 0x1 0x0
+#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS                     0x02c 0x354 0x75c 0x2 0x0
+#define MX53_PAD_KEY_COL1__UART5_TXD_MUX                        0x02c 0x354 0x000 0x4 0x0
+#define MX53_PAD_KEY_COL1__ECSPI1_MISO                          0x02c 0x354 0x7a0 0x5 0x0
+#define MX53_PAD_KEY_COL1__FEC_RX_CLK                           0x02c 0x354 0x808 0x6 0x0
+#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY                      0x02c 0x354 0x000 0x7 0x0
+#define MX53_PAD_KEY_ROW1__KPP_ROW_1                            0x030 0x358 0x000 0x0 0x0
+#define MX53_PAD_KEY_ROW1__GPIO4_9                              0x030 0x358 0x000 0x1 0x0
+#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD                      0x030 0x358 0x748 0x2 0x0
+#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX                        0x030 0x358 0x898 0x4 0x1
+#define MX53_PAD_KEY_ROW1__ECSPI1_SS0                           0x030 0x358 0x7a8 0x5 0x0
+#define MX53_PAD_KEY_ROW1__FEC_COL                              0x030 0x358 0x800 0x6 0x0
+#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID                      0x030 0x358 0x000 0x7 0x0
+#define MX53_PAD_KEY_COL2__KPP_COL_2                            0x034 0x35c 0x000 0x0 0x0
+#define MX53_PAD_KEY_COL2__GPIO4_10                             0x034 0x35c 0x000 0x1 0x0
+#define MX53_PAD_KEY_COL2__CAN1_TXCAN                           0x034 0x35c 0x000 0x2 0x0
+#define MX53_PAD_KEY_COL2__FEC_MDIO                             0x034 0x35c 0x804 0x4 0x0
+#define MX53_PAD_KEY_COL2__ECSPI1_SS1                           0x034 0x35c 0x7ac 0x5 0x0
+#define MX53_PAD_KEY_COL2__FEC_RDATA_2                          0x034 0x35c 0x000 0x6 0x0
+#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE                     0x034 0x35c 0x000 0x7 0x0
+#define MX53_PAD_KEY_ROW2__KPP_ROW_2                            0x038 0x360 0x000 0x0 0x0
+#define MX53_PAD_KEY_ROW2__GPIO4_11                             0x038 0x360 0x000 0x1 0x0
+#define MX53_PAD_KEY_ROW2__CAN1_RXCAN                           0x038 0x360 0x760 0x2 0x0
+#define MX53_PAD_KEY_ROW2__FEC_MDC                              0x038 0x360 0x000 0x4 0x0
+#define MX53_PAD_KEY_ROW2__ECSPI1_SS2                           0x038 0x360 0x7b0 0x5 0x0
+#define MX53_PAD_KEY_ROW2__FEC_TDATA_2                          0x038 0x360 0x000 0x6 0x0
+#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR                      0x038 0x360 0x000 0x7 0x0
+#define MX53_PAD_KEY_COL3__KPP_COL_3                            0x03c 0x364 0x000 0x0 0x0
+#define MX53_PAD_KEY_COL3__GPIO4_12                             0x03c 0x364 0x000 0x1 0x0
+#define MX53_PAD_KEY_COL3__USBOH3_H2_DP                         0x03c 0x364 0x000 0x2 0x0
+#define MX53_PAD_KEY_COL3__SPDIF_IN1                            0x03c 0x364 0x870 0x3 0x0
+#define MX53_PAD_KEY_COL3__I2C2_SCL                             0x03c 0x364 0x81c 0x4 0x0
+#define MX53_PAD_KEY_COL3__ECSPI1_SS3                           0x03c 0x364 0x7b4 0x5 0x0
+#define MX53_PAD_KEY_COL3__FEC_CRS                              0x03c 0x364 0x000 0x6 0x0
+#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK                     0x03c 0x364 0x000 0x7 0x0
+#define MX53_PAD_KEY_ROW3__KPP_ROW_3                            0x040 0x368 0x000 0x0 0x0
+#define MX53_PAD_KEY_ROW3__GPIO4_13                             0x040 0x368 0x000 0x1 0x0
+#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM                         0x040 0x368 0x000 0x2 0x0
+#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK                     0x040 0x368 0x768 0x3 0x0
+#define MX53_PAD_KEY_ROW3__I2C2_SDA                             0x040 0x368 0x820 0x4 0x0
+#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT                       0x040 0x368 0x000 0x5 0x0
+#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP                         0x040 0x368 0x77c 0x6 0x0
+#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0                  0x040 0x368 0x000 0x7 0x0
+#define MX53_PAD_KEY_COL4__KPP_COL_4                            0x044 0x36c 0x000 0x0 0x0
+#define MX53_PAD_KEY_COL4__GPIO4_14                             0x044 0x36c 0x000 0x1 0x0
+#define MX53_PAD_KEY_COL4__CAN2_TXCAN                           0x044 0x36c 0x000 0x2 0x0
+#define MX53_PAD_KEY_COL4__IPU_SISG_4                           0x044 0x36c 0x000 0x3 0x0
+#define MX53_PAD_KEY_COL4__UART5_RTS                            0x044 0x36c 0x894 0x4 0x0
+#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC                     0x044 0x36c 0x89c 0x5 0x0
+#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1                  0x044 0x36c 0x000 0x7 0x0
+#define MX53_PAD_KEY_ROW4__KPP_ROW_4                            0x048 0x370 0x000 0x0 0x0
+#define MX53_PAD_KEY_ROW4__GPIO4_15                             0x048 0x370 0x000 0x1 0x0
+#define MX53_PAD_KEY_ROW4__CAN2_RXCAN                           0x048 0x370 0x764 0x2 0x0
+#define MX53_PAD_KEY_ROW4__IPU_SISG_5                           0x048 0x370 0x000 0x3 0x0
+#define MX53_PAD_KEY_ROW4__UART5_CTS                            0x048 0x370 0x000 0x4 0x0
+#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR                    0x048 0x370 0x000 0x5 0x0
+#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID                    0x048 0x370 0x000 0x7 0x0
+#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK                 0x04c 0x378 0x000 0x0 0x0
+#define MX53_PAD_DI0_DISP_CLK__GPIO4_16                         0x04c 0x378 0x000 0x1 0x0
+#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR                 0x04c 0x378 0x000 0x2 0x0
+#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0          0x04c 0x378 0x000 0x5 0x0
+#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0                  0x04c 0x378 0x000 0x6 0x0
+#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID                   0x04c 0x378 0x000 0x7 0x0
+#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15                       0x050 0x37c 0x000 0x0 0x0
+#define MX53_PAD_DI0_PIN15__GPIO4_17                            0x050 0x37c 0x000 0x1 0x0
+#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC                     0x050 0x37c 0x000 0x2 0x0
+#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1             0x050 0x37c 0x000 0x5 0x0
+#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1                     0x050 0x37c 0x000 0x6 0x0
+#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID                      0x050 0x37c 0x000 0x7 0x0
+#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2                         0x054 0x380 0x000 0x0 0x0
+#define MX53_PAD_DI0_PIN2__GPIO4_18                             0x054 0x380 0x000 0x1 0x0
+#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD                      0x054 0x380 0x000 0x2 0x0
+#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2              0x054 0x380 0x000 0x5 0x0
+#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2                      0x054 0x380 0x000 0x6 0x0
+#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION                   0x054 0x380 0x000 0x7 0x0
+#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                         0x058 0x384 0x000 0x0 0x0
+#define MX53_PAD_DI0_PIN3__GPIO4_19                             0x058 0x384 0x000 0x1 0x0
+#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS                     0x058 0x384 0x000 0x2 0x0
+#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3              0x058 0x384 0x000 0x5 0x0
+#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3                      0x058 0x384 0x000 0x6 0x0
+#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG                        0x058 0x384 0x000 0x7 0x0
+#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4                         0x05c 0x388 0x000 0x0 0x0
+#define MX53_PAD_DI0_PIN4__GPIO4_20                             0x05c 0x388 0x000 0x1 0x0
+#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD                      0x05c 0x388 0x000 0x2 0x0
+#define MX53_PAD_DI0_PIN4__ESDHC1_WP                            0x05c 0x388 0x7fc 0x3 0x0
+#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD                     0x05c 0x388 0x000 0x5 0x0
+#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4                      0x05c 0x388 0x000 0x6 0x0
+#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT               0x05c 0x388 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0                    0x060 0x38c 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT0__GPIO4_21                           0x060 0x38c 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT0__CSPI_SCLK                          0x060 0x38c 0x780 0x2 0x0
+#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0                0x060 0x38c 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN                0x060 0x38c 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5                    0x060 0x38c 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY                    0x060 0x38c 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1                    0x064 0x390 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT1__GPIO4_22                           0x064 0x390 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT1__CSPI_MOSI                          0x064 0x390 0x788 0x2 0x0
+#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1                0x064 0x390 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL       0x064 0x390 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6                    0x064 0x390 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID                    0x064 0x390 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2                    0x068 0x394 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT2__GPIO4_23                           0x068 0x394 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT2__CSPI_MISO                          0x068 0x394 0x784 0x2 0x0
+#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2                0x068 0x394 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE                    0x068 0x394 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7                    0x068 0x394 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE                   0x068 0x394 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3                    0x06c 0x398 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT3__GPIO4_24                           0x06c 0x398 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT3__CSPI_SS0                           0x06c 0x398 0x78c 0x2 0x0
+#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3                0x06c 0x398 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR               0x06c 0x398 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8                    0x06c 0x398 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR                    0x06c 0x398 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4                    0x070 0x39c 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT4__GPIO4_25                           0x070 0x39c 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT4__CSPI_SS1                           0x070 0x39c 0x790 0x2 0x0
+#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4                0x070 0x39c 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB                 0x070 0x39c 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9                    0x070 0x39c 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK                   0x070 0x39c 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5                    0x074 0x3a0 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT5__GPIO4_26                           0x074 0x3a0 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT5__CSPI_SS2                           0x074 0x3a0 0x794 0x2 0x0
+#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5                0x074 0x3a0 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS           0x074 0x3a0 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10                   0x074 0x3a0 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0                0x074 0x3a0 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6                    0x078 0x3a4 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT6__GPIO4_27                           0x078 0x3a4 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT6__CSPI_SS3                           0x078 0x3a4 0x798 0x2 0x0
+#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6                0x078 0x3a4 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE          0x078 0x3a4 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11                   0x078 0x3a4 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1                0x078 0x3a4 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7                    0x07c 0x3a8 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT7__GPIO4_28                           0x07c 0x3a8 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT7__CSPI_RDY                           0x07c 0x3a8 0x000 0x2 0x0
+#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7                0x07c 0x3a8 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0         0x07c 0x3a8 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12                   0x07c 0x3a8 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID                  0x07c 0x3a8 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8                    0x080 0x3ac 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT8__GPIO4_29                           0x080 0x3ac 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT8__PWM1_PWMO                          0x080 0x3ac 0x000 0x2 0x0
+#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B                       0x080 0x3ac 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1         0x080 0x3ac 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13                   0x080 0x3ac 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID                     0x080 0x3ac 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9                    0x084 0x3b0 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT9__GPIO4_30                           0x084 0x3b0 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT9__PWM2_PWMO                          0x084 0x3b0 0x000 0x2 0x0
+#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B                       0x084 0x3b0 0x000 0x3 0x0
+#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2         0x084 0x3b0 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14                   0x084 0x3b0 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0                  0x084 0x3b0 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10                  0x088 0x3b4 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT10__GPIO4_31                          0x088 0x3b4 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP                  0x088 0x3b4 0x000 0x2 0x0
+#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3        0x088 0x3b4 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15                  0x088 0x3b4 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1                 0x088 0x3b4 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11                  0x08c 0x3b8 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT11__GPIO5_5                           0x08c 0x3b8 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT                  0x08c 0x3b8 0x000 0x2 0x0
+#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4        0x08c 0x3b8 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16                  0x08c 0x3b8 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2                 0x08c 0x3b8 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12                  0x090 0x3bc 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT12__GPIO5_6                           0x090 0x3bc 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK                  0x090 0x3bc 0x000 0x2 0x0
+#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5        0x090 0x3bc 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17                  0x090 0x3bc 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3                 0x090 0x3bc 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13                  0x094 0x3c0 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT13__GPIO5_7                           0x094 0x3c0 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS                  0x094 0x3c0 0x754 0x3 0x0
+#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0        0x094 0x3c0 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18                  0x094 0x3c0 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4                 0x094 0x3c0 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14                  0x098 0x3c4 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT14__GPIO5_8                           0x098 0x3c4 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC                   0x098 0x3c4 0x750 0x3 0x0
+#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1        0x098 0x3c4 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19                  0x098 0x3c4 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5                 0x098 0x3c4 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15                  0x09c 0x3c8 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT15__GPIO5_9                           0x09c 0x3c8 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1                        0x09c 0x3c8 0x7ac 0x2 0x1
+#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1                        0x09c 0x3c8 0x7c8 0x3 0x0
+#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2        0x09c 0x3c8 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20                  0x09c 0x3c8 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6                 0x09c 0x3c8 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16                  0x0a0 0x3cc 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT16__GPIO5_10                          0x0a0 0x3cc 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI                       0x0a0 0x3cc 0x7c0 0x2 0x0
+#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC                   0x0a0 0x3cc 0x758 0x3 0x1
+#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0                  0x0a0 0x3cc 0x868 0x4 0x0
+#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3        0x0a0 0x3cc 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21                  0x0a0 0x3cc 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7                 0x0a0 0x3cc 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17                  0x0a4 0x3d0 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT17__GPIO5_11                          0x0a4 0x3d0 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO                       0x0a4 0x3d0 0x7bc 0x2 0x0
+#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD                   0x0a4 0x3d0 0x74c 0x3 0x1
+#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1                  0x0a4 0x3d0 0x86c 0x4 0x0
+#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4        0x0a4 0x3d0 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22                  0x0a4 0x3d0 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18                  0x0a8 0x3d4 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT18__GPIO5_12                          0x0a8 0x3d4 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0                        0x0a8 0x3d4 0x7c4 0x2 0x0
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS                  0x0a8 0x3d4 0x75c 0x3 0x1
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS                  0x0a8 0x3d4 0x73c 0x4 0x0
+#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5        0x0a8 0x3d4 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23                  0x0a8 0x3d4 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2                     0x0a8 0x3d4 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19                  0x0ac 0x3d8 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT19__GPIO5_13                          0x0ac 0x3d8 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK                       0x0ac 0x3d8 0x7b8 0x2 0x0
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD                   0x0ac 0x3d8 0x748 0x3 0x1
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC                   0x0ac 0x3d8 0x738 0x4 0x0
+#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6        0x0ac 0x3d8 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24                  0x0ac 0x3d8 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3                     0x0ac 0x3d8 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20                  0x0b0 0x3dc 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT20__GPIO5_14                          0x0b0 0x3dc 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK                       0x0b0 0x3dc 0x79c 0x2 0x1
+#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC                   0x0b0 0x3dc 0x740 0x3 0x0
+#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7        0x0b0 0x3dc 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25                  0x0b0 0x3dc 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI                      0x0b0 0x3dc 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21                  0x0b4 0x3e0 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT21__GPIO5_15                          0x0b4 0x3e0 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI                       0x0b4 0x3e0 0x7a4 0x2 0x1
+#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD                   0x0b4 0x3e0 0x734 0x3 0x0
+#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0           0x0b4 0x3e0 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26                  0x0b4 0x3e0 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO                      0x0b4 0x3e0 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22                  0x0b8 0x3e4 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT22__GPIO5_16                          0x0b8 0x3e4 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO                       0x0b8 0x3e4 0x7a0 0x2 0x1
+#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS                  0x0b8 0x3e4 0x744 0x3 0x0
+#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1           0x0b8 0x3e4 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27                  0x0b8 0x3e4 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK                      0x0b8 0x3e4 0x000 0x7 0x0
+#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23                  0x0bc 0x3e8 0x000 0x0 0x0
+#define MX53_PAD_DISP0_DAT23__GPIO5_17                          0x0bc 0x3e8 0x000 0x1 0x0
+#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0                        0x0bc 0x3e8 0x7a8 0x2 0x1
+#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD                   0x0bc 0x3e8 0x730 0x3 0x0
+#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2           0x0bc 0x3e8 0x000 0x5 0x0
+#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28                  0x0bc 0x3e8 0x000 0x6 0x0
+#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS                      0x0bc 0x3e8 0x000 0x7 0x0
+#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK                   0x0c0 0x3ec 0x000 0x0 0x0
+#define MX53_PAD_CSI0_PIXCLK__GPIO5_18                          0x0c0 0x3ec 0x000 0x1 0x0
+#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0                   0x0c0 0x3ec 0x000 0x5 0x0
+#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29                  0x0c0 0x3ec 0x000 0x6 0x0
+#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC                      0x0c4 0x3f0 0x000 0x0 0x0
+#define MX53_PAD_CSI0_MCLK__GPIO5_19                            0x0c4 0x3f0 0x000 0x1 0x0
+#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK                       0x0c4 0x3f0 0x000 0x2 0x0
+#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1                     0x0c4 0x3f0 0x000 0x5 0x0
+#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30                    0x0c4 0x3f0 0x000 0x6 0x0
+#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL                          0x0c4 0x3f0 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN                 0x0c8 0x3f4 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DATA_EN__GPIO5_20                         0x0c8 0x3f4 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2                  0x0c8 0x3f4 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31                 0x0c8 0x3f4 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK                       0x0c8 0x3f4 0x000 0x7 0x0
+#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC                     0x0cc 0x3f8 0x000 0x0 0x0
+#define MX53_PAD_CSI0_VSYNC__GPIO5_21                           0x0cc 0x3f8 0x000 0x1 0x0
+#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3                    0x0cc 0x3f8 0x000 0x5 0x0
+#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32                   0x0cc 0x3f8 0x000 0x6 0x0
+#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0                       0x0cc 0x3f8 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4                        0x0d0 0x3fc 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT4__GPIO5_22                            0x0d0 0x3fc 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT4__KPP_COL_5                           0x0d0 0x3fc 0x840 0x2 0x1
+#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK                         0x0d0 0x3fc 0x79c 0x3 0x2
+#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP                    0x0d0 0x3fc 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC                     0x0d0 0x3fc 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33                    0x0d0 0x3fc 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1                        0x0d0 0x3fc 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5                        0x0d4 0x400 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT5__GPIO5_23                            0x0d4 0x400 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT5__KPP_ROW_5                           0x0d4 0x400 0x84c 0x2 0x0
+#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI                         0x0d4 0x400 0x7a4 0x3 0x2
+#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT                    0x0d4 0x400 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD                     0x0d4 0x400 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34                    0x0d4 0x400 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2                        0x0d4 0x400 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6                        0x0d8 0x404 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT6__GPIO5_24                            0x0d8 0x404 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT6__KPP_COL_6                           0x0d8 0x404 0x844 0x2 0x0
+#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO                         0x0d8 0x404 0x7a0 0x3 0x2
+#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK                    0x0d8 0x404 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS                    0x0d8 0x404 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35                    0x0d8 0x404 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3                        0x0d8 0x404 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7                        0x0dc 0x408 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT7__GPIO5_25                            0x0dc 0x408 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT7__KPP_ROW_6                           0x0dc 0x408 0x850 0x2 0x0
+#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0                          0x0dc 0x408 0x7a8 0x3 0x2
+#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR                    0x0dc 0x408 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD                     0x0dc 0x408 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36                    0x0dc 0x408 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4                        0x0dc 0x408 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8                        0x0e0 0x40c 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT8__GPIO5_26                            0x0e0 0x40c 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT8__KPP_COL_7                           0x0e0 0x40c 0x848 0x2 0x0
+#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK                         0x0e0 0x40c 0x7b8 0x3 0x1
+#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC                     0x0e0 0x40c 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT8__I2C1_SDA                            0x0e0 0x40c 0x818 0x5 0x0
+#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37                    0x0e0 0x40c 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5                        0x0e0 0x40c 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9                        0x0e4 0x410 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT9__GPIO5_27                            0x0e4 0x410 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT9__KPP_ROW_7                           0x0e4 0x410 0x854 0x2 0x0
+#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI                         0x0e4 0x410 0x7c0 0x3 0x1
+#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR                    0x0e4 0x410 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT9__I2C1_SCL                            0x0e4 0x410 0x814 0x5 0x0
+#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38                    0x0e4 0x410 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6                        0x0e4 0x410 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10                      0x0e8 0x414 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT10__GPIO5_28                           0x0e8 0x414 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX                      0x0e8 0x414 0x000 0x2 0x0
+#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO                        0x0e8 0x414 0x7bc 0x3 0x1
+#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC                    0x0e8 0x414 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4                    0x0e8 0x414 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39                   0x0e8 0x414 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7                       0x0e8 0x414 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11                      0x0ec 0x418 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT11__GPIO5_29                           0x0ec 0x418 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX                      0x0ec 0x418 0x878 0x2 0x1
+#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0                         0x0ec 0x418 0x7c4 0x3 0x1
+#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS                   0x0ec 0x418 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5                    0x0ec 0x418 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40                   0x0ec 0x418 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8                       0x0ec 0x418 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12                      0x0f0 0x41c 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT12__GPIO5_30                           0x0f0 0x41c 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX                      0x0f0 0x41c 0x000 0x2 0x0
+#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0                0x0f0 0x41c 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6                    0x0f0 0x41c 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41                   0x0f0 0x41c 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9                       0x0f0 0x41c 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13                      0x0f4 0x420 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT13__GPIO5_31                           0x0f4 0x420 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX                      0x0f4 0x420 0x890 0x2 0x3
+#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1                0x0f4 0x420 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7                    0x0f4 0x420 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42                   0x0f4 0x420 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10                      0x0f4 0x420 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14                      0x0f8 0x424 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT14__GPIO6_0                            0x0f8 0x424 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX                      0x0f8 0x424 0x000 0x2 0x0
+#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2                0x0f8 0x424 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8                    0x0f8 0x424 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43                   0x0f8 0x424 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11                      0x0f8 0x424 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15                      0x0fc 0x428 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT15__GPIO6_1                            0x0fc 0x428 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX                      0x0fc 0x428 0x898 0x2 0x3
+#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3                0x0fc 0x428 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9                    0x0fc 0x428 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44                   0x0fc 0x428 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12                      0x0fc 0x428 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16                      0x100 0x42c 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT16__GPIO6_2                            0x100 0x42c 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT16__UART4_RTS                          0x100 0x42c 0x88c 0x2 0x0
+#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4                0x100 0x42c 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10                   0x100 0x42c 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45                   0x100 0x42c 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13                      0x100 0x42c 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17                      0x104 0x430 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT17__GPIO6_3                            0x104 0x430 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT17__UART4_CTS                          0x104 0x430 0x000 0x2 0x0
+#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5                0x104 0x430 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11                   0x104 0x430 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46                   0x104 0x430 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14                      0x104 0x430 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18                      0x108 0x434 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT18__GPIO6_4                            0x108 0x434 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT18__UART5_RTS                          0x108 0x434 0x894 0x2 0x2
+#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6                0x108 0x434 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12                   0x108 0x434 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47                   0x108 0x434 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15                      0x108 0x434 0x000 0x7 0x0
+#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19                      0x10c 0x438 0x000 0x0 0x0
+#define MX53_PAD_CSI0_DAT19__GPIO6_5                            0x10c 0x438 0x000 0x1 0x0
+#define MX53_PAD_CSI0_DAT19__UART5_CTS                          0x10c 0x438 0x000 0x2 0x0
+#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7                0x10c 0x438 0x000 0x4 0x0
+#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13                   0x10c 0x438 0x000 0x5 0x0
+#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48                   0x10c 0x438 0x000 0x6 0x0
+#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK                     0x10c 0x438 0x000 0x7 0x0
+#define MX53_PAD_EIM_A25__EMI_WEIM_A_25                         0x110 0x458 0x000 0x0 0x0
+#define MX53_PAD_EIM_A25__GPIO5_2                               0x110 0x458 0x000 0x1 0x0
+#define MX53_PAD_EIM_A25__ECSPI2_RDY                            0x110 0x458 0x000 0x2 0x0
+#define MX53_PAD_EIM_A25__IPU_DI1_PIN12                         0x110 0x458 0x000 0x3 0x0
+#define MX53_PAD_EIM_A25__CSPI_SS1                              0x110 0x458 0x790 0x4 0x1
+#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS                         0x110 0x458 0x000 0x6 0x0
+#define MX53_PAD_EIM_A25__USBPHY1_BISTOK                        0x110 0x458 0x000 0x7 0x0
+#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2                         0x114 0x45c 0x000 0x0 0x0
+#define MX53_PAD_EIM_EB2__GPIO2_30                              0x114 0x45c 0x000 0x1 0x0
+#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK                       0x114 0x45c 0x76c 0x2 0x0
+#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS                      0x114 0x45c 0x000 0x3 0x0
+#define MX53_PAD_EIM_EB2__ECSPI1_SS0                            0x114 0x45c 0x7a8 0x4 0x3
+#define MX53_PAD_EIM_EB2__I2C2_SCL                              0x114 0x45c 0x81c 0x5 0x1
+#define MX53_PAD_EIM_D16__EMI_WEIM_D_16                         0x118 0x460 0x000 0x0 0x0
+#define MX53_PAD_EIM_D16__GPIO3_16                              0x118 0x460 0x000 0x1 0x0
+#define MX53_PAD_EIM_D16__IPU_DI0_PIN5                          0x118 0x460 0x000 0x2 0x0
+#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK                    0x118 0x460 0x000 0x3 0x0
+#define MX53_PAD_EIM_D16__ECSPI1_SCLK                           0x118 0x460 0x79c 0x4 0x3
+#define MX53_PAD_EIM_D16__I2C2_SDA                              0x118 0x460 0x820 0x5 0x1
+#define MX53_PAD_EIM_D17__EMI_WEIM_D_17                         0x11c 0x464 0x000 0x0 0x0
+#define MX53_PAD_EIM_D17__GPIO3_17                              0x11c 0x464 0x000 0x1 0x0
+#define MX53_PAD_EIM_D17__IPU_DI0_PIN6                          0x11c 0x464 0x000 0x2 0x0
+#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN                    0x11c 0x464 0x830 0x3 0x0
+#define MX53_PAD_EIM_D17__ECSPI1_MISO                           0x11c 0x464 0x7a0 0x4 0x3
+#define MX53_PAD_EIM_D17__I2C3_SCL                              0x11c 0x464 0x824 0x5 0x0
+#define MX53_PAD_EIM_D18__EMI_WEIM_D_18                         0x120 0x468 0x000 0x0 0x0
+#define MX53_PAD_EIM_D18__GPIO3_18                              0x120 0x468 0x000 0x1 0x0
+#define MX53_PAD_EIM_D18__IPU_DI0_PIN7                          0x120 0x468 0x000 0x2 0x0
+#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO                    0x120 0x468 0x830 0x3 0x1
+#define MX53_PAD_EIM_D18__ECSPI1_MOSI                           0x120 0x468 0x7a4 0x4 0x3
+#define MX53_PAD_EIM_D18__I2C3_SDA                              0x120 0x468 0x828 0x5 0x0
+#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS                         0x120 0x468 0x000 0x6 0x0
+#define MX53_PAD_EIM_D19__EMI_WEIM_D_19                         0x124 0x46c 0x000 0x0 0x0
+#define MX53_PAD_EIM_D19__GPIO3_19                              0x124 0x46c 0x000 0x1 0x0
+#define MX53_PAD_EIM_D19__IPU_DI0_PIN8                          0x124 0x46c 0x000 0x2 0x0
+#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS                     0x124 0x46c 0x000 0x3 0x0
+#define MX53_PAD_EIM_D19__ECSPI1_SS1                            0x124 0x46c 0x7ac 0x4 0x2
+#define MX53_PAD_EIM_D19__EPIT1_EPITO                           0x124 0x46c 0x000 0x5 0x0
+#define MX53_PAD_EIM_D19__UART1_CTS                             0x124 0x46c 0x000 0x6 0x0
+#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC                       0x124 0x46c 0x8a4 0x7 0x0
+#define MX53_PAD_EIM_D20__EMI_WEIM_D_20                         0x128 0x470 0x000 0x0 0x0
+#define MX53_PAD_EIM_D20__GPIO3_20                              0x128 0x470 0x000 0x1 0x0
+#define MX53_PAD_EIM_D20__IPU_DI0_PIN16                         0x128 0x470 0x000 0x2 0x0
+#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS                      0x128 0x470 0x000 0x3 0x0
+#define MX53_PAD_EIM_D20__CSPI_SS0                              0x128 0x470 0x78c 0x4 0x1
+#define MX53_PAD_EIM_D20__EPIT2_EPITO                           0x128 0x470 0x000 0x5 0x0
+#define MX53_PAD_EIM_D20__UART1_RTS                             0x128 0x470 0x874 0x6 0x1
+#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR                      0x128 0x470 0x000 0x7 0x0
+#define MX53_PAD_EIM_D21__EMI_WEIM_D_21                         0x12c 0x474 0x000 0x0 0x0
+#define MX53_PAD_EIM_D21__GPIO3_21                              0x12c 0x474 0x000 0x1 0x0
+#define MX53_PAD_EIM_D21__IPU_DI0_PIN17                         0x12c 0x474 0x000 0x2 0x0
+#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK                    0x12c 0x474 0x000 0x3 0x0
+#define MX53_PAD_EIM_D21__CSPI_SCLK                             0x12c 0x474 0x780 0x4 0x1
+#define MX53_PAD_EIM_D21__I2C1_SCL                              0x12c 0x474 0x814 0x5 0x1
+#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC                      0x12c 0x474 0x89c 0x6 0x1
+#define MX53_PAD_EIM_D22__EMI_WEIM_D_22                         0x130 0x478 0x000 0x0 0x0
+#define MX53_PAD_EIM_D22__GPIO3_22                              0x130 0x478 0x000 0x1 0x0
+#define MX53_PAD_EIM_D22__IPU_DI0_PIN1                          0x130 0x478 0x000 0x2 0x0
+#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN                    0x130 0x478 0x82c 0x3 0x0
+#define MX53_PAD_EIM_D22__CSPI_MISO                             0x130 0x478 0x784 0x4 0x1
+#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR                     0x130 0x478 0x000 0x6 0x0
+#define MX53_PAD_EIM_D23__EMI_WEIM_D_23                         0x134 0x47c 0x000 0x0 0x0
+#define MX53_PAD_EIM_D23__GPIO3_23                              0x134 0x47c 0x000 0x1 0x0
+#define MX53_PAD_EIM_D23__UART3_CTS                             0x134 0x47c 0x000 0x2 0x0
+#define MX53_PAD_EIM_D23__UART1_DCD                             0x134 0x47c 0x000 0x3 0x0
+#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS                         0x134 0x47c 0x000 0x4 0x0
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN2                          0x134 0x47c 0x000 0x5 0x0
+#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN                      0x134 0x47c 0x834 0x6 0x0
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN14                         0x134 0x47c 0x000 0x7 0x0
+#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3                         0x138 0x480 0x000 0x0 0x0
+#define MX53_PAD_EIM_EB3__GPIO2_31                              0x138 0x480 0x000 0x1 0x0
+#define MX53_PAD_EIM_EB3__UART3_RTS                             0x138 0x480 0x884 0x2 0x1
+#define MX53_PAD_EIM_EB3__UART1_RI                              0x138 0x480 0x000 0x3 0x0
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3                          0x138 0x480 0x000 0x5 0x0
+#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC                        0x138 0x480 0x838 0x6 0x0
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16                         0x138 0x480 0x000 0x7 0x0
+#define MX53_PAD_EIM_D24__EMI_WEIM_D_24                         0x13c 0x484 0x000 0x0 0x0
+#define MX53_PAD_EIM_D24__GPIO3_24                              0x13c 0x484 0x000 0x1 0x0
+#define MX53_PAD_EIM_D24__UART3_TXD_MUX                         0x13c 0x484 0x000 0x2 0x0
+#define MX53_PAD_EIM_D24__ECSPI1_SS2                            0x13c 0x484 0x7b0 0x3 0x1
+#define MX53_PAD_EIM_D24__CSPI_SS2                              0x13c 0x484 0x794 0x4 0x1
+#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS                      0x13c 0x484 0x754 0x5 0x1
+#define MX53_PAD_EIM_D24__ECSPI2_SS2                            0x13c 0x484 0x000 0x6 0x0
+#define MX53_PAD_EIM_D24__UART1_DTR                             0x13c 0x484 0x000 0x7 0x0
+#define MX53_PAD_EIM_D25__EMI_WEIM_D_25                         0x140 0x488 0x000 0x0 0x0
+#define MX53_PAD_EIM_D25__GPIO3_25                              0x140 0x488 0x000 0x1 0x0
+#define MX53_PAD_EIM_D25__UART3_RXD_MUX                         0x140 0x488 0x888 0x2 0x1
+#define MX53_PAD_EIM_D25__ECSPI1_SS3                            0x140 0x488 0x7b4 0x3 0x1
+#define MX53_PAD_EIM_D25__CSPI_SS3                              0x140 0x488 0x798 0x4 0x1
+#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC                       0x140 0x488 0x750 0x5 0x1
+#define MX53_PAD_EIM_D25__ECSPI2_SS3                            0x140 0x488 0x000 0x6 0x0
+#define MX53_PAD_EIM_D25__UART1_DSR                             0x140 0x488 0x000 0x7 0x0
+#define MX53_PAD_EIM_D26__EMI_WEIM_D_26                         0x144 0x48c 0x000 0x0 0x0
+#define MX53_PAD_EIM_D26__GPIO3_26                              0x144 0x48c 0x000 0x1 0x0
+#define MX53_PAD_EIM_D26__UART2_TXD_MUX                         0x144 0x48c 0x000 0x2 0x0
+#define MX53_PAD_EIM_D26__FIRI_RXD                              0x144 0x48c 0x80c 0x3 0x0
+#define MX53_PAD_EIM_D26__IPU_CSI0_D_1                          0x144 0x48c 0x000 0x4 0x0
+#define MX53_PAD_EIM_D26__IPU_DI1_PIN11                         0x144 0x48c 0x000 0x5 0x0
+#define MX53_PAD_EIM_D26__IPU_SISG_2                            0x144 0x48c 0x000 0x6 0x0
+#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22                      0x144 0x48c 0x000 0x7 0x0
+#define MX53_PAD_EIM_D27__EMI_WEIM_D_27                         0x148 0x490 0x000 0x0 0x0
+#define MX53_PAD_EIM_D27__GPIO3_27                              0x148 0x490 0x000 0x1 0x0
+#define MX53_PAD_EIM_D27__UART2_RXD_MUX                         0x148 0x490 0x880 0x2 0x1
+#define MX53_PAD_EIM_D27__FIRI_TXD                              0x148 0x490 0x000 0x3 0x0
+#define MX53_PAD_EIM_D27__IPU_CSI0_D_0                          0x148 0x490 0x000 0x4 0x0
+#define MX53_PAD_EIM_D27__IPU_DI1_PIN13                         0x148 0x490 0x000 0x5 0x0
+#define MX53_PAD_EIM_D27__IPU_SISG_3                            0x148 0x490 0x000 0x6 0x0
+#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23                      0x148 0x490 0x000 0x7 0x0
+#define MX53_PAD_EIM_D28__EMI_WEIM_D_28                         0x14c 0x494 0x000 0x0 0x0
+#define MX53_PAD_EIM_D28__GPIO3_28                              0x14c 0x494 0x000 0x1 0x0
+#define MX53_PAD_EIM_D28__UART2_CTS                             0x14c 0x494 0x000 0x2 0x0
+#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO                    0x14c 0x494 0x82c 0x3 0x1
+#define MX53_PAD_EIM_D28__CSPI_MOSI                             0x14c 0x494 0x788 0x4 0x1
+#define MX53_PAD_EIM_D28__I2C1_SDA                              0x14c 0x494 0x818 0x5 0x1
+#define MX53_PAD_EIM_D28__IPU_EXT_TRIG                          0x14c 0x494 0x000 0x6 0x0
+#define MX53_PAD_EIM_D28__IPU_DI0_PIN13                         0x14c 0x494 0x000 0x7 0x0
+#define MX53_PAD_EIM_D29__EMI_WEIM_D_29                         0x150 0x498 0x000 0x0 0x0
+#define MX53_PAD_EIM_D29__GPIO3_29                              0x150 0x498 0x000 0x1 0x0
+#define MX53_PAD_EIM_D29__UART2_RTS                             0x150 0x498 0x87c 0x2 0x1
+#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS                     0x150 0x498 0x000 0x3 0x0
+#define MX53_PAD_EIM_D29__CSPI_SS0                              0x150 0x498 0x78c 0x4 0x2
+#define MX53_PAD_EIM_D29__IPU_DI1_PIN15                         0x150 0x498 0x000 0x5 0x0
+#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC                        0x150 0x498 0x83c 0x6 0x0
+#define MX53_PAD_EIM_D29__IPU_DI0_PIN14                         0x150 0x498 0x000 0x7 0x0
+#define MX53_PAD_EIM_D30__EMI_WEIM_D_30                         0x154 0x49c 0x000 0x0 0x0
+#define MX53_PAD_EIM_D30__GPIO3_30                              0x154 0x49c 0x000 0x1 0x0
+#define MX53_PAD_EIM_D30__UART3_CTS                             0x154 0x49c 0x000 0x2 0x0
+#define MX53_PAD_EIM_D30__IPU_CSI0_D_3                          0x154 0x49c 0x000 0x3 0x0
+#define MX53_PAD_EIM_D30__IPU_DI0_PIN11                         0x154 0x49c 0x000 0x4 0x0
+#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21                      0x154 0x49c 0x000 0x5 0x0
+#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC                       0x154 0x49c 0x8a0 0x6 0x0
+#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC                       0x154 0x49c 0x8a4 0x7 0x1
+#define MX53_PAD_EIM_D31__EMI_WEIM_D_31                         0x158 0x4a0 0x000 0x0 0x0
+#define MX53_PAD_EIM_D31__GPIO3_31                              0x158 0x4a0 0x000 0x1 0x0
+#define MX53_PAD_EIM_D31__UART3_RTS                             0x158 0x4a0 0x884 0x2 0x3
+#define MX53_PAD_EIM_D31__IPU_CSI0_D_2                          0x158 0x4a0 0x000 0x3 0x0
+#define MX53_PAD_EIM_D31__IPU_DI0_PIN12                         0x158 0x4a0 0x000 0x4 0x0
+#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20                      0x158 0x4a0 0x000 0x5 0x0
+#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR                      0x158 0x4a0 0x000 0x6 0x0
+#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR                      0x158 0x4a0 0x000 0x7 0x0
+#define MX53_PAD_EIM_A24__EMI_WEIM_A_24                         0x15c 0x4a8 0x000 0x0 0x0
+#define MX53_PAD_EIM_A24__GPIO5_4                               0x15c 0x4a8 0x000 0x1 0x0
+#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19                      0x15c 0x4a8 0x000 0x2 0x0
+#define MX53_PAD_EIM_A24__IPU_CSI1_D_19                         0x15c 0x4a8 0x000 0x3 0x0
+#define MX53_PAD_EIM_A24__IPU_SISG_2                            0x15c 0x4a8 0x000 0x6 0x0
+#define MX53_PAD_EIM_A24__USBPHY2_BVALID                        0x15c 0x4a8 0x000 0x7 0x0
+#define MX53_PAD_EIM_A23__EMI_WEIM_A_23                         0x160 0x4ac 0x000 0x0 0x0
+#define MX53_PAD_EIM_A23__GPIO6_6                               0x160 0x4ac 0x000 0x1 0x0
+#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18                      0x160 0x4ac 0x000 0x2 0x0
+#define MX53_PAD_EIM_A23__IPU_CSI1_D_18                         0x160 0x4ac 0x000 0x3 0x0
+#define MX53_PAD_EIM_A23__IPU_SISG_3                            0x160 0x4ac 0x000 0x6 0x0
+#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION                    0x160 0x4ac 0x000 0x7 0x0
+#define MX53_PAD_EIM_A22__EMI_WEIM_A_22                         0x164 0x4b0 0x000 0x0 0x0
+#define MX53_PAD_EIM_A22__GPIO2_16                              0x164 0x4b0 0x000 0x1 0x0
+#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17                      0x164 0x4b0 0x000 0x2 0x0
+#define MX53_PAD_EIM_A22__IPU_CSI1_D_17                         0x164 0x4b0 0x000 0x3 0x0
+#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7                         0x164 0x4b0 0x000 0x7 0x0
+#define MX53_PAD_EIM_A21__EMI_WEIM_A_21                         0x168 0x4b4 0x000 0x0 0x0
+#define MX53_PAD_EIM_A21__GPIO2_17                              0x168 0x4b4 0x000 0x1 0x0
+#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16                      0x168 0x4b4 0x000 0x2 0x0
+#define MX53_PAD_EIM_A21__IPU_CSI1_D_16                         0x168 0x4b4 0x000 0x3 0x0
+#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6                         0x168 0x4b4 0x000 0x7 0x0
+#define MX53_PAD_EIM_A20__EMI_WEIM_A_20                         0x16c 0x4b8 0x000 0x0 0x0
+#define MX53_PAD_EIM_A20__GPIO2_18                              0x16c 0x4b8 0x000 0x1 0x0
+#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15                      0x16c 0x4b8 0x000 0x2 0x0
+#define MX53_PAD_EIM_A20__IPU_CSI1_D_15                         0x16c 0x4b8 0x000 0x3 0x0
+#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5                         0x16c 0x4b8 0x000 0x7 0x0
+#define MX53_PAD_EIM_A19__EMI_WEIM_A_19                         0x170 0x4bc 0x000 0x0 0x0
+#define MX53_PAD_EIM_A19__GPIO2_19                              0x170 0x4bc 0x000 0x1 0x0
+#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14                      0x170 0x4bc 0x000 0x2 0x0
+#define MX53_PAD_EIM_A19__IPU_CSI1_D_14                         0x170 0x4bc 0x000 0x3 0x0
+#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4                         0x170 0x4bc 0x000 0x7 0x0
+#define MX53_PAD_EIM_A18__EMI_WEIM_A_18                         0x174 0x4c0 0x000 0x0 0x0
+#define MX53_PAD_EIM_A18__GPIO2_20                              0x174 0x4c0 0x000 0x1 0x0
+#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13                      0x174 0x4c0 0x000 0x2 0x0
+#define MX53_PAD_EIM_A18__IPU_CSI1_D_13                         0x174 0x4c0 0x000 0x3 0x0
+#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3                         0x174 0x4c0 0x000 0x7 0x0
+#define MX53_PAD_EIM_A17__EMI_WEIM_A_17                         0x178 0x4c4 0x000 0x0 0x0
+#define MX53_PAD_EIM_A17__GPIO2_21                              0x178 0x4c4 0x000 0x1 0x0
+#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12                      0x178 0x4c4 0x000 0x2 0x0
+#define MX53_PAD_EIM_A17__IPU_CSI1_D_12                         0x178 0x4c4 0x000 0x3 0x0
+#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2                         0x178 0x4c4 0x000 0x7 0x0
+#define MX53_PAD_EIM_A16__EMI_WEIM_A_16                         0x17c 0x4c8 0x000 0x0 0x0
+#define MX53_PAD_EIM_A16__GPIO2_22                              0x17c 0x4c8 0x000 0x1 0x0
+#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK                      0x17c 0x4c8 0x000 0x2 0x0
+#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK                       0x17c 0x4c8 0x000 0x3 0x0
+#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1                         0x17c 0x4c8 0x000 0x7 0x0
+#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0                         0x180 0x4cc 0x000 0x0 0x0
+#define MX53_PAD_EIM_CS0__GPIO2_23                              0x180 0x4cc 0x000 0x1 0x0
+#define MX53_PAD_EIM_CS0__ECSPI2_SCLK                           0x180 0x4cc 0x7b8 0x2 0x2
+#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5                          0x180 0x4cc 0x000 0x3 0x0
+#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1                         0x184 0x4d0 0x000 0x0 0x0
+#define MX53_PAD_EIM_CS1__GPIO2_24                              0x184 0x4d0 0x000 0x1 0x0
+#define MX53_PAD_EIM_CS1__ECSPI2_MOSI                           0x184 0x4d0 0x7c0 0x2 0x2
+#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6                          0x184 0x4d0 0x000 0x3 0x0
+#define MX53_PAD_EIM_OE__EMI_WEIM_OE                            0x188 0x4d4 0x000 0x0 0x0
+#define MX53_PAD_EIM_OE__GPIO2_25                               0x188 0x4d4 0x000 0x1 0x0
+#define MX53_PAD_EIM_OE__ECSPI2_MISO                            0x188 0x4d4 0x7bc 0x2 0x2
+#define MX53_PAD_EIM_OE__IPU_DI1_PIN7                           0x188 0x4d4 0x000 0x3 0x0
+#define MX53_PAD_EIM_OE__USBPHY2_IDDIG                          0x188 0x4d4 0x000 0x7 0x0
+#define MX53_PAD_EIM_RW__EMI_WEIM_RW                            0x18c 0x4d8 0x000 0x0 0x0
+#define MX53_PAD_EIM_RW__GPIO2_26                               0x18c 0x4d8 0x000 0x1 0x0
+#define MX53_PAD_EIM_RW__ECSPI2_SS0                             0x18c 0x4d8 0x7c4 0x2 0x2
+#define MX53_PAD_EIM_RW__IPU_DI1_PIN8                           0x18c 0x4d8 0x000 0x3 0x0
+#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT                 0x18c 0x4d8 0x000 0x7 0x0
+#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA                          0x190 0x4dc 0x000 0x0 0x0
+#define MX53_PAD_EIM_LBA__GPIO2_27                              0x190 0x4dc 0x000 0x1 0x0
+#define MX53_PAD_EIM_LBA__ECSPI2_SS1                            0x190 0x4dc 0x7c8 0x2 0x1
+#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17                         0x190 0x4dc 0x000 0x3 0x0
+#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0                         0x190 0x4dc 0x000 0x7 0x0
+#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0                         0x194 0x4e4 0x000 0x0 0x0
+#define MX53_PAD_EIM_EB0__GPIO2_28                              0x194 0x4e4 0x000 0x1 0x0
+#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11                      0x194 0x4e4 0x000 0x3 0x0
+#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11                         0x194 0x4e4 0x000 0x4 0x0
+#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY                          0x194 0x4e4 0x810 0x5 0x0
+#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7                         0x194 0x4e4 0x000 0x7 0x0
+#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1                         0x198 0x4e8 0x000 0x0 0x0
+#define MX53_PAD_EIM_EB1__GPIO2_29                              0x198 0x4e8 0x000 0x1 0x0
+#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10                      0x198 0x4e8 0x000 0x3 0x0
+#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10                         0x198 0x4e8 0x000 0x4 0x0
+#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6                         0x198 0x4e8 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0                    0x19c 0x4ec 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA0__GPIO3_0                               0x19c 0x4ec 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9                       0x19c 0x4ec 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9                          0x19c 0x4ec 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5                         0x19c 0x4ec 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1                    0x1a0 0x4f0 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA1__GPIO3_1                               0x1a0 0x4f0 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8                       0x1a0 0x4f0 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8                          0x1a0 0x4f0 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4                         0x1a0 0x4f0 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2                    0x1a4 0x4f4 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA2__GPIO3_2                               0x1a4 0x4f4 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7                       0x1a4 0x4f4 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7                          0x1a4 0x4f4 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3                         0x1a4 0x4f4 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3                    0x1a8 0x4f8 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA3__GPIO3_3                               0x1a8 0x4f8 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6                       0x1a8 0x4f8 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6                          0x1a8 0x4f8 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2                         0x1a8 0x4f8 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4                    0x1ac 0x4fc 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA4__GPIO3_4                               0x1ac 0x4fc 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5                       0x1ac 0x4fc 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5                          0x1ac 0x4fc 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7                         0x1ac 0x4fc 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5                    0x1b0 0x500 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA5__GPIO3_5                               0x1b0 0x500 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4                       0x1b0 0x500 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4                          0x1b0 0x500 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6                         0x1b0 0x500 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6                    0x1b4 0x504 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA6__GPIO3_6                               0x1b4 0x504 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3                       0x1b4 0x504 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3                          0x1b4 0x504 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5                         0x1b4 0x504 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7                    0x1b8 0x508 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA7__GPIO3_7                               0x1b8 0x508 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2                       0x1b8 0x508 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2                          0x1b8 0x508 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4                         0x1b8 0x508 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8                    0x1bc 0x50c 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA8__GPIO3_8                               0x1bc 0x50c 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1                       0x1bc 0x50c 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1                          0x1bc 0x50c 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3                         0x1bc 0x50c 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9                    0x1c0 0x510 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA9__GPIO3_9                               0x1c0 0x510 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0                       0x1c0 0x510 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0                          0x1c0 0x510 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2                         0x1c0 0x510 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10                  0x1c4 0x514 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA10__GPIO3_10                             0x1c4 0x514 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15                        0x1c4 0x514 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN                     0x1c4 0x514 0x834 0x4 0x1
+#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1                        0x1c4 0x514 0x000 0x7 0x0
+#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11                  0x1c8 0x518 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA11__GPIO3_11                             0x1c8 0x518 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2                         0x1c8 0x518 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC                       0x1c8 0x518 0x838 0x4 0x1
+#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12                  0x1cc 0x51c 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA12__GPIO3_12                             0x1cc 0x51c 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3                         0x1cc 0x51c 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC                       0x1cc 0x51c 0x83c 0x4 0x1
+#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13                  0x1d0 0x520 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA13__GPIO3_13                             0x1d0 0x520 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS                        0x1d0 0x520 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK                      0x1d0 0x520 0x76c 0x4 0x1
+#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14                  0x1d4 0x524 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA14__GPIO3_14                             0x1d4 0x524 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS                        0x1d4 0x524 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK                      0x1d4 0x524 0x000 0x4 0x0
+#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15                  0x1d8 0x528 0x000 0x0 0x0
+#define MX53_PAD_EIM_DA15__GPIO3_15                             0x1d8 0x528 0x000 0x1 0x0
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1                         0x1d8 0x528 0x000 0x3 0x0
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4                         0x1d8 0x528 0x000 0x4 0x0
+#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B                     0x1dc 0x52c 0x000 0x0 0x0
+#define MX53_PAD_NANDF_WE_B__GPIO6_12                           0x1dc 0x52c 0x000 0x1 0x0
+#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B                     0x1e0 0x530 0x000 0x0 0x0
+#define MX53_PAD_NANDF_RE_B__GPIO6_13                           0x1e0 0x530 0x000 0x1 0x0
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT                        0x1e4 0x534 0x000 0x0 0x0
+#define MX53_PAD_EIM_WAIT__GPIO5_0                              0x1e4 0x534 0x000 0x1 0x0
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B                     0x1e4 0x534 0x000 0x2 0x0
+#define MX53_PAD_LVDS1_TX3_P__GPIO6_22                          0x1ec 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3                     0x1ec 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS1_TX2_P__GPIO6_24                          0x1f0 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2                     0x1f0 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS1_CLK_P__GPIO6_26                          0x1f4 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK                     0x1f4 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS1_TX1_P__GPIO6_28                          0x1f8 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1                     0x1f8 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS1_TX0_P__GPIO6_30                          0x1fc 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0                     0x1fc 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS0_TX3_P__GPIO7_22                          0x200 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3                     0x200 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS0_CLK_P__GPIO7_24                          0x204 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK                     0x204 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS0_TX2_P__GPIO7_26                          0x208 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2                     0x208 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS0_TX1_P__GPIO7_28                          0x20c 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1                     0x20c 0x000 0x000 0x1 0x0
+#define MX53_PAD_LVDS0_TX0_P__GPIO7_30                          0x210 0x000 0x000 0x0 0x0
+#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0                     0x210 0x000 0x000 0x1 0x0
+#define MX53_PAD_GPIO_10__GPIO4_0                               0x214 0x540 0x000 0x0 0x0
+#define MX53_PAD_GPIO_10__OSC32k_32K_OUT                        0x214 0x540 0x000 0x1 0x0
+#define MX53_PAD_GPIO_11__GPIO4_1                               0x218 0x544 0x000 0x0 0x0
+#define MX53_PAD_GPIO_12__GPIO4_2                               0x21c 0x548 0x000 0x0 0x0
+#define MX53_PAD_GPIO_13__GPIO4_3                               0x220 0x54c 0x000 0x0 0x0
+#define MX53_PAD_GPIO_14__GPIO4_4                               0x224 0x550 0x000 0x0 0x0
+#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE                       0x228 0x5a0 0x000 0x0 0x0
+#define MX53_PAD_NANDF_CLE__GPIO6_7                             0x228 0x5a0 0x000 0x1 0x0
+#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0                   0x228 0x5a0 0x000 0x7 0x0
+#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE                       0x22c 0x5a4 0x000 0x0 0x0
+#define MX53_PAD_NANDF_ALE__GPIO6_8                             0x22c 0x5a4 0x000 0x1 0x0
+#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1                   0x22c 0x5a4 0x000 0x7 0x0
+#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B                     0x230 0x5a8 0x000 0x0 0x0
+#define MX53_PAD_NANDF_WP_B__GPIO6_9                            0x230 0x5a8 0x000 0x1 0x0
+#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2                  0x230 0x5a8 0x000 0x7 0x0
+#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0                      0x234 0x5ac 0x000 0x0 0x0
+#define MX53_PAD_NANDF_RB0__GPIO6_10                            0x234 0x5ac 0x000 0x1 0x0
+#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3                   0x234 0x5ac 0x000 0x7 0x0
+#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0                      0x238 0x5b0 0x000 0x0 0x0
+#define MX53_PAD_NANDF_CS0__GPIO6_11                            0x238 0x5b0 0x000 0x1 0x0
+#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4                   0x238 0x5b0 0x000 0x7 0x0
+#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1                      0x23c 0x5b4 0x000 0x0 0x0
+#define MX53_PAD_NANDF_CS1__GPIO6_14                            0x23c 0x5b4 0x000 0x1 0x0
+#define MX53_PAD_NANDF_CS1__MLB_MLBCLK                          0x23c 0x5b4 0x858 0x6 0x0
+#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5                   0x23c 0x5b4 0x000 0x7 0x0
+#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2                      0x240 0x5b8 0x000 0x0 0x0
+#define MX53_PAD_NANDF_CS2__GPIO6_15                            0x240 0x5b8 0x000 0x1 0x0
+#define MX53_PAD_NANDF_CS2__IPU_SISG_0                          0x240 0x5b8 0x000 0x2 0x0
+#define MX53_PAD_NANDF_CS2__ESAI1_TX0                           0x240 0x5b8 0x7e4 0x3 0x0
+#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE                        0x240 0x5b8 0x000 0x4 0x0
+#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK                       0x240 0x5b8 0x000 0x5 0x0
+#define MX53_PAD_NANDF_CS2__MLB_MLBSIG                          0x240 0x5b8 0x860 0x6 0x0
+#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6                   0x240 0x5b8 0x000 0x7 0x0
+#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3                      0x244 0x5bc 0x000 0x0 0x0
+#define MX53_PAD_NANDF_CS3__GPIO6_16                            0x244 0x5bc 0x000 0x1 0x0
+#define MX53_PAD_NANDF_CS3__IPU_SISG_1                          0x244 0x5bc 0x000 0x2 0x0
+#define MX53_PAD_NANDF_CS3__ESAI1_TX1                           0x244 0x5bc 0x7e8 0x3 0x0
+#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26                       0x244 0x5bc 0x000 0x4 0x0
+#define MX53_PAD_NANDF_CS3__MLB_MLBDAT                          0x244 0x5bc 0x85c 0x6 0x0
+#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7                   0x244 0x5bc 0x000 0x7 0x0
+#define MX53_PAD_FEC_MDIO__FEC_MDIO                             0x248 0x5c4 0x804 0x0 0x1
+#define MX53_PAD_FEC_MDIO__GPIO1_22                             0x248 0x5c4 0x000 0x1 0x0
+#define MX53_PAD_FEC_MDIO__ESAI1_SCKR                           0x248 0x5c4 0x7dc 0x2 0x0
+#define MX53_PAD_FEC_MDIO__FEC_COL                              0x248 0x5c4 0x800 0x3 0x1
+#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2                       0x248 0x5c4 0x000 0x4 0x0
+#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3              0x248 0x5c4 0x000 0x5 0x0
+#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49                     0x248 0x5c4 0x000 0x6 0x0
+#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK                        0x24c 0x5c8 0x000 0x0 0x0
+#define MX53_PAD_FEC_REF_CLK__GPIO1_23                          0x24c 0x5c8 0x000 0x1 0x0
+#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR                         0x24c 0x5c8 0x7cc 0x2 0x0
+#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4           0x24c 0x5c8 0x000 0x5 0x0
+#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50                  0x24c 0x5c8 0x000 0x6 0x0
+#define MX53_PAD_FEC_RX_ER__FEC_RX_ER                           0x250 0x5cc 0x000 0x0 0x0
+#define MX53_PAD_FEC_RX_ER__GPIO1_24                            0x250 0x5cc 0x000 0x1 0x0
+#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR                          0x250 0x5cc 0x7d4 0x2 0x0
+#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK                          0x250 0x5cc 0x808 0x3 0x1
+#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3                      0x250 0x5cc 0x000 0x4 0x0
+#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV                          0x254 0x5d0 0x000 0x0 0x0
+#define MX53_PAD_FEC_CRS_DV__GPIO1_25                           0x254 0x5d0 0x000 0x1 0x0
+#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT                         0x254 0x5d0 0x7e0 0x2 0x0
+#define MX53_PAD_FEC_RXD1__FEC_RDATA_1                          0x258 0x5d4 0x000 0x0 0x0
+#define MX53_PAD_FEC_RXD1__GPIO1_26                             0x258 0x5d4 0x000 0x1 0x0
+#define MX53_PAD_FEC_RXD1__ESAI1_FST                            0x258 0x5d4 0x7d0 0x2 0x0
+#define MX53_PAD_FEC_RXD1__MLB_MLBSIG                           0x258 0x5d4 0x860 0x3 0x1
+#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1                       0x258 0x5d4 0x000 0x4 0x0
+#define MX53_PAD_FEC_RXD0__FEC_RDATA_0                          0x25c 0x5d8 0x000 0x0 0x0
+#define MX53_PAD_FEC_RXD0__GPIO1_27                             0x25c 0x5d8 0x000 0x1 0x0
+#define MX53_PAD_FEC_RXD0__ESAI1_HCKT                           0x25c 0x5d8 0x7d8 0x2 0x0
+#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT                       0x25c 0x5d8 0x000 0x3 0x0
+#define MX53_PAD_FEC_TX_EN__FEC_TX_EN                           0x260 0x5dc 0x000 0x0 0x0
+#define MX53_PAD_FEC_TX_EN__GPIO1_28                            0x260 0x5dc 0x000 0x1 0x0
+#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2                       0x260 0x5dc 0x7f0 0x2 0x0
+#define MX53_PAD_FEC_TXD1__FEC_TDATA_1                          0x264 0x5e0 0x000 0x0 0x0
+#define MX53_PAD_FEC_TXD1__GPIO1_29                             0x264 0x5e0 0x000 0x1 0x0
+#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3                        0x264 0x5e0 0x7ec 0x2 0x0
+#define MX53_PAD_FEC_TXD1__MLB_MLBCLK                           0x264 0x5e0 0x858 0x3 0x1
+#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK                  0x264 0x5e0 0x000 0x4 0x0
+#define MX53_PAD_FEC_TXD0__FEC_TDATA_0                          0x268 0x5e4 0x000 0x0 0x0
+#define MX53_PAD_FEC_TXD0__GPIO1_30                             0x268 0x5e4 0x000 0x1 0x0
+#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1                        0x268 0x5e4 0x7f4 0x2 0x0
+#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0                    0x268 0x5e4 0x000 0x7 0x0
+#define MX53_PAD_FEC_MDC__FEC_MDC                               0x26c 0x5e8 0x000 0x0 0x0
+#define MX53_PAD_FEC_MDC__GPIO1_31                              0x26c 0x5e8 0x000 0x1 0x0
+#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0                         0x26c 0x5e8 0x7f8 0x2 0x0
+#define MX53_PAD_FEC_MDC__MLB_MLBDAT                            0x26c 0x5e8 0x85c 0x3 0x1
+#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG                0x26c 0x5e8 0x000 0x4 0x0
+#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1                     0x26c 0x5e8 0x000 0x7 0x0
+#define MX53_PAD_PATA_DIOW__PATA_DIOW                           0x270 0x5f0 0x000 0x0 0x0
+#define MX53_PAD_PATA_DIOW__GPIO6_17                            0x270 0x5f0 0x000 0x1 0x0
+#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX                       0x270 0x5f0 0x000 0x3 0x0
+#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2                   0x270 0x5f0 0x000 0x7 0x0
+#define MX53_PAD_PATA_DMACK__PATA_DMACK                         0x274 0x5f4 0x000 0x0 0x0
+#define MX53_PAD_PATA_DMACK__GPIO6_18                           0x274 0x5f4 0x000 0x1 0x0
+#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX                      0x274 0x5f4 0x878 0x3 0x3
+#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3                  0x274 0x5f4 0x000 0x7 0x0
+#define MX53_PAD_PATA_DMARQ__PATA_DMARQ                         0x278 0x5f8 0x000 0x0 0x0
+#define MX53_PAD_PATA_DMARQ__GPIO7_0                            0x278 0x5f8 0x000 0x1 0x0
+#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX                      0x278 0x5f8 0x000 0x3 0x0
+#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0                      0x278 0x5f8 0x000 0x5 0x0
+#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4                  0x278 0x5f8 0x000 0x7 0x0
+#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN                 0x27c 0x5fc 0x000 0x0 0x0
+#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1                        0x27c 0x5fc 0x000 0x1 0x0
+#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX                  0x27c 0x5fc 0x880 0x3 0x3
+#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1                  0x27c 0x5fc 0x000 0x5 0x0
+#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5              0x27c 0x5fc 0x000 0x7 0x0
+#define MX53_PAD_PATA_INTRQ__PATA_INTRQ                         0x280 0x600 0x000 0x0 0x0
+#define MX53_PAD_PATA_INTRQ__GPIO7_2                            0x280 0x600 0x000 0x1 0x0
+#define MX53_PAD_PATA_INTRQ__UART2_CTS                          0x280 0x600 0x000 0x3 0x0
+#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN                         0x280 0x600 0x000 0x4 0x0
+#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2                      0x280 0x600 0x000 0x5 0x0
+#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6                  0x280 0x600 0x000 0x7 0x0
+#define MX53_PAD_PATA_DIOR__PATA_DIOR                           0x284 0x604 0x000 0x0 0x0
+#define MX53_PAD_PATA_DIOR__GPIO7_3                             0x284 0x604 0x000 0x1 0x0
+#define MX53_PAD_PATA_DIOR__UART2_RTS                           0x284 0x604 0x87c 0x3 0x3
+#define MX53_PAD_PATA_DIOR__CAN1_RXCAN                          0x284 0x604 0x760 0x4 0x1
+#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7                   0x284 0x604 0x000 0x7 0x0
+#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B                0x288 0x608 0x000 0x0 0x0
+#define MX53_PAD_PATA_RESET_B__GPIO7_4                          0x288 0x608 0x000 0x1 0x0
+#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD                       0x288 0x608 0x000 0x2 0x0
+#define MX53_PAD_PATA_RESET_B__UART1_CTS                        0x288 0x608 0x000 0x3 0x0
+#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN                       0x288 0x608 0x000 0x4 0x0
+#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0                0x288 0x608 0x000 0x7 0x0
+#define MX53_PAD_PATA_IORDY__PATA_IORDY                         0x28c 0x60c 0x000 0x0 0x0
+#define MX53_PAD_PATA_IORDY__GPIO7_5                            0x28c 0x60c 0x000 0x1 0x0
+#define MX53_PAD_PATA_IORDY__ESDHC3_CLK                         0x28c 0x60c 0x000 0x2 0x0
+#define MX53_PAD_PATA_IORDY__UART1_RTS                          0x28c 0x60c 0x874 0x3 0x3
+#define MX53_PAD_PATA_IORDY__CAN2_RXCAN                         0x28c 0x60c 0x764 0x4 0x1
+#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1                  0x28c 0x60c 0x000 0x7 0x0
+#define MX53_PAD_PATA_DA_0__PATA_DA_0                           0x290 0x610 0x000 0x0 0x0
+#define MX53_PAD_PATA_DA_0__GPIO7_6                             0x290 0x610 0x000 0x1 0x0
+#define MX53_PAD_PATA_DA_0__ESDHC3_RST                          0x290 0x610 0x000 0x2 0x0
+#define MX53_PAD_PATA_DA_0__OWIRE_LINE                          0x290 0x610 0x864 0x4 0x0
+#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2                   0x290 0x610 0x000 0x7 0x0
+#define MX53_PAD_PATA_DA_1__PATA_DA_1                           0x294 0x614 0x000 0x0 0x0
+#define MX53_PAD_PATA_DA_1__GPIO7_7                             0x294 0x614 0x000 0x1 0x0
+#define MX53_PAD_PATA_DA_1__ESDHC4_CMD                          0x294 0x614 0x000 0x2 0x0
+#define MX53_PAD_PATA_DA_1__UART3_CTS                           0x294 0x614 0x000 0x4 0x0
+#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3                   0x294 0x614 0x000 0x7 0x0
+#define MX53_PAD_PATA_DA_2__PATA_DA_2                           0x298 0x618 0x000 0x0 0x0
+#define MX53_PAD_PATA_DA_2__GPIO7_8                             0x298 0x618 0x000 0x1 0x0
+#define MX53_PAD_PATA_DA_2__ESDHC4_CLK                          0x298 0x618 0x000 0x2 0x0
+#define MX53_PAD_PATA_DA_2__UART3_RTS                           0x298 0x618 0x884 0x4 0x5
+#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4                   0x298 0x618 0x000 0x7 0x0
+#define MX53_PAD_PATA_CS_0__PATA_CS_0                           0x29c 0x61c 0x000 0x0 0x0
+#define MX53_PAD_PATA_CS_0__GPIO7_9                             0x29c 0x61c 0x000 0x1 0x0
+#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX                       0x29c 0x61c 0x000 0x4 0x0
+#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5                   0x29c 0x61c 0x000 0x7 0x0
+#define MX53_PAD_PATA_CS_1__PATA_CS_1                           0x2a0 0x620 0x000 0x0 0x0
+#define MX53_PAD_PATA_CS_1__GPIO7_10                            0x2a0 0x620 0x000 0x1 0x0
+#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX                       0x2a0 0x620 0x888 0x4 0x3
+#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6                   0x2a0 0x620 0x000 0x7 0x0
+#define MX53_PAD_PATA_DATA0__PATA_DATA_0                        0x2a4 0x628 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA0__GPIO2_0                            0x2a4 0x628 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0                      0x2a4 0x628 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4                        0x2a4 0x628 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0              0x2a4 0x628 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0                     0x2a4 0x628 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7                  0x2a4 0x628 0x000 0x7 0x0
+#define MX53_PAD_PATA_DATA1__PATA_DATA_1                        0x2a8 0x62c 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA1__GPIO2_1                            0x2a8 0x62c 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1                      0x2a8 0x62c 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5                        0x2a8 0x62c 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1              0x2a8 0x62c 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1                     0x2a8 0x62c 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA2__PATA_DATA_2                        0x2ac 0x630 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA2__GPIO2_2                            0x2ac 0x630 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2                      0x2ac 0x630 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6                        0x2ac 0x630 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2              0x2ac 0x630 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2                     0x2ac 0x630 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA3__PATA_DATA_3                        0x2b0 0x634 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA3__GPIO2_3                            0x2b0 0x634 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3                      0x2b0 0x634 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7                        0x2b0 0x634 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3              0x2b0 0x634 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3                     0x2b0 0x634 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA4__PATA_DATA_4                        0x2b4 0x638 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA4__GPIO2_4                            0x2b4 0x638 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4                      0x2b4 0x638 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4                        0x2b4 0x638 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4              0x2b4 0x638 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4                     0x2b4 0x638 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA5__PATA_DATA_5                        0x2b8 0x63c 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA5__GPIO2_5                            0x2b8 0x63c 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5                      0x2b8 0x63c 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5                        0x2b8 0x63c 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5              0x2b8 0x63c 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5                     0x2b8 0x63c 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA6__PATA_DATA_6                        0x2bc 0x640 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA6__GPIO2_6                            0x2bc 0x640 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6                      0x2bc 0x640 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6                        0x2bc 0x640 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6              0x2bc 0x640 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6                     0x2bc 0x640 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA7__PATA_DATA_7                        0x2c0 0x644 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA7__GPIO2_7                            0x2c0 0x644 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7                      0x2c0 0x644 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7                        0x2c0 0x644 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7              0x2c0 0x644 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7                     0x2c0 0x644 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA8__PATA_DATA_8                        0x2c4 0x648 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA8__GPIO2_8                            0x2c4 0x648 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4                        0x2c4 0x648 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8                      0x2c4 0x648 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0                        0x2c4 0x648 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8              0x2c4 0x648 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8                     0x2c4 0x648 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA9__PATA_DATA_9                        0x2c8 0x64c 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA9__GPIO2_9                            0x2c8 0x64c 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5                        0x2c8 0x64c 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9                      0x2c8 0x64c 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1                        0x2c8 0x64c 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9              0x2c8 0x64c 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9                     0x2c8 0x64c 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA10__PATA_DATA_10                      0x2cc 0x650 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA10__GPIO2_10                          0x2cc 0x650 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6                       0x2cc 0x650 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10                    0x2cc 0x650 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2                       0x2cc 0x650 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10            0x2cc 0x650 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10                   0x2cc 0x650 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA11__PATA_DATA_11                      0x2d0 0x654 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA11__GPIO2_11                          0x2d0 0x654 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7                       0x2d0 0x654 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11                    0x2d0 0x654 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3                       0x2d0 0x654 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11            0x2d0 0x654 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11                   0x2d0 0x654 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA12__PATA_DATA_12                      0x2d4 0x658 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA12__GPIO2_12                          0x2d4 0x658 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4                       0x2d4 0x658 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12                    0x2d4 0x658 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0                       0x2d4 0x658 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12            0x2d4 0x658 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12                   0x2d4 0x658 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA13__PATA_DATA_13                      0x2d8 0x65c 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA13__GPIO2_13                          0x2d8 0x65c 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5                       0x2d8 0x65c 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13                    0x2d8 0x65c 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1                       0x2d8 0x65c 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13            0x2d8 0x65c 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13                   0x2d8 0x65c 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA14__PATA_DATA_14                      0x2dc 0x660 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA14__GPIO2_14                          0x2dc 0x660 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6                       0x2dc 0x660 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14                    0x2dc 0x660 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2                       0x2dc 0x660 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14            0x2dc 0x660 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14                   0x2dc 0x660 0x000 0x6 0x0
+#define MX53_PAD_PATA_DATA15__PATA_DATA_15                      0x2e0 0x664 0x000 0x0 0x0
+#define MX53_PAD_PATA_DATA15__GPIO2_15                          0x2e0 0x664 0x000 0x1 0x0
+#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7                       0x2e0 0x664 0x000 0x2 0x0
+#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15                    0x2e0 0x664 0x000 0x3 0x0
+#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3                       0x2e0 0x664 0x000 0x4 0x0
+#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15            0x2e0 0x664 0x000 0x5 0x0
+#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15                   0x2e0 0x664 0x000 0x6 0x0
+#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0                         0x2e4 0x66c 0x000 0x0 0x0
+#define MX53_PAD_SD1_DATA0__GPIO1_16                            0x2e4 0x66c 0x000 0x1 0x0
+#define MX53_PAD_SD1_DATA0__GPT_CAPIN1                          0x2e4 0x66c 0x000 0x3 0x0
+#define MX53_PAD_SD1_DATA0__CSPI_MISO                           0x2e4 0x66c 0x784 0x5 0x2
+#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP                        0x2e4 0x66c 0x778 0x7 0x0
+#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1                         0x2e8 0x670 0x000 0x0 0x0
+#define MX53_PAD_SD1_DATA1__GPIO1_17                            0x2e8 0x670 0x000 0x1 0x0
+#define MX53_PAD_SD1_DATA1__GPT_CAPIN2                          0x2e8 0x670 0x000 0x3 0x0
+#define MX53_PAD_SD1_DATA1__CSPI_SS0                            0x2e8 0x670 0x78c 0x5 0x3
+#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP                        0x2e8 0x670 0x77c 0x7 0x1
+#define MX53_PAD_SD1_CMD__ESDHC1_CMD                            0x2ec 0x674 0x000 0x0 0x0
+#define MX53_PAD_SD1_CMD__GPIO1_18                              0x2ec 0x674 0x000 0x1 0x0
+#define MX53_PAD_SD1_CMD__GPT_CMPOUT1                           0x2ec 0x674 0x000 0x3 0x0
+#define MX53_PAD_SD1_CMD__CSPI_MOSI                             0x2ec 0x674 0x788 0x5 0x2
+#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP                          0x2ec 0x674 0x770 0x7 0x0
+#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2                         0x2f0 0x678 0x000 0x0 0x0
+#define MX53_PAD_SD1_DATA2__GPIO1_19                            0x2f0 0x678 0x000 0x1 0x0
+#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2                         0x2f0 0x678 0x000 0x2 0x0
+#define MX53_PAD_SD1_DATA2__PWM2_PWMO                           0x2f0 0x678 0x000 0x3 0x0
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B                        0x2f0 0x678 0x000 0x4 0x0
+#define MX53_PAD_SD1_DATA2__CSPI_SS1                            0x2f0 0x678 0x790 0x5 0x2
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB                0x2f0 0x678 0x000 0x6 0x0
+#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP                        0x2f0 0x678 0x774 0x7 0x0
+#define MX53_PAD_SD1_CLK__ESDHC1_CLK                            0x2f4 0x67c 0x000 0x0 0x0
+#define MX53_PAD_SD1_CLK__GPIO1_20                              0x2f4 0x67c 0x000 0x1 0x0
+#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT                        0x2f4 0x67c 0x000 0x2 0x0
+#define MX53_PAD_SD1_CLK__GPT_CLKIN                             0x2f4 0x67c 0x000 0x3 0x0
+#define MX53_PAD_SD1_CLK__CSPI_SCLK                             0x2f4 0x67c 0x780 0x5 0x2
+#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0                        0x2f4 0x67c 0x000 0x7 0x0
+#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3                         0x2f8 0x680 0x000 0x0 0x0
+#define MX53_PAD_SD1_DATA3__GPIO1_21                            0x2f8 0x680 0x000 0x1 0x0
+#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3                         0x2f8 0x680 0x000 0x2 0x0
+#define MX53_PAD_SD1_DATA3__PWM1_PWMO                           0x2f8 0x680 0x000 0x3 0x0
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B                        0x2f8 0x680 0x000 0x4 0x0
+#define MX53_PAD_SD1_DATA3__CSPI_SS2                            0x2f8 0x680 0x794 0x5 0x2
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB                0x2f8 0x680 0x000 0x6 0x0
+#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1                      0x2f8 0x680 0x000 0x7 0x0
+#define MX53_PAD_SD2_CLK__ESDHC2_CLK                            0x2fc 0x688 0x000 0x0 0x0
+#define MX53_PAD_SD2_CLK__GPIO1_10                              0x2fc 0x688 0x000 0x1 0x0
+#define MX53_PAD_SD2_CLK__KPP_COL_5                             0x2fc 0x688 0x840 0x2 0x2
+#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS                      0x2fc 0x688 0x73c 0x3 0x1
+#define MX53_PAD_SD2_CLK__CSPI_SCLK                             0x2fc 0x688 0x780 0x5 0x3
+#define MX53_PAD_SD2_CLK__SCC_RANDOM_V                          0x2fc 0x688 0x000 0x7 0x0
+#define MX53_PAD_SD2_CMD__ESDHC2_CMD                            0x300 0x68c 0x000 0x0 0x0
+#define MX53_PAD_SD2_CMD__GPIO1_11                              0x300 0x68c 0x000 0x1 0x0
+#define MX53_PAD_SD2_CMD__KPP_ROW_5                             0x300 0x68c 0x84c 0x2 0x1
+#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC                       0x300 0x68c 0x738 0x3 0x1
+#define MX53_PAD_SD2_CMD__CSPI_MOSI                             0x300 0x68c 0x788 0x5 0x3
+#define MX53_PAD_SD2_CMD__SCC_RANDOM                            0x300 0x68c 0x000 0x7 0x0
+#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3                         0x304 0x690 0x000 0x0 0x0
+#define MX53_PAD_SD2_DATA3__GPIO1_12                            0x304 0x690 0x000 0x1 0x0
+#define MX53_PAD_SD2_DATA3__KPP_COL_6                           0x304 0x690 0x844 0x2 0x1
+#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC                     0x304 0x690 0x740 0x3 0x1
+#define MX53_PAD_SD2_DATA3__CSPI_SS2                            0x304 0x690 0x794 0x5 0x3
+#define MX53_PAD_SD2_DATA3__SJC_DONE                            0x304 0x690 0x000 0x7 0x0
+#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2                         0x308 0x694 0x000 0x0 0x0
+#define MX53_PAD_SD2_DATA2__GPIO1_13                            0x308 0x694 0x000 0x1 0x0
+#define MX53_PAD_SD2_DATA2__KPP_ROW_6                           0x308 0x694 0x850 0x2 0x1
+#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD                     0x308 0x694 0x734 0x3 0x1
+#define MX53_PAD_SD2_DATA2__CSPI_SS1                            0x308 0x694 0x790 0x5 0x3
+#define MX53_PAD_SD2_DATA2__SJC_FAIL                            0x308 0x694 0x000 0x7 0x0
+#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1                         0x30c 0x698 0x000 0x0 0x0
+#define MX53_PAD_SD2_DATA1__GPIO1_14                            0x30c 0x698 0x000 0x1 0x0
+#define MX53_PAD_SD2_DATA1__KPP_COL_7                           0x30c 0x698 0x848 0x2 0x1
+#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS                    0x30c 0x698 0x744 0x3 0x1
+#define MX53_PAD_SD2_DATA1__CSPI_SS0                            0x30c 0x698 0x78c 0x5 0x4
+#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO                        0x30c 0x698 0x000 0x7 0x0
+#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0                         0x310 0x69c 0x000 0x0 0x0
+#define MX53_PAD_SD2_DATA0__GPIO1_15                            0x310 0x69c 0x000 0x1 0x0
+#define MX53_PAD_SD2_DATA0__KPP_ROW_7                           0x310 0x69c 0x854 0x2 0x1
+#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD                     0x310 0x69c 0x730 0x3 0x1
+#define MX53_PAD_SD2_DATA0__CSPI_MISO                           0x310 0x69c 0x784 0x5 0x3
+#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT                       0x310 0x69c 0x000 0x7 0x0
+#define MX53_PAD_GPIO_0__CCM_CLKO                               0x314 0x6a4 0x000 0x0 0x0
+#define MX53_PAD_GPIO_0__GPIO1_0                                0x314 0x6a4 0x000 0x1 0x0
+#define MX53_PAD_GPIO_0__KPP_COL_5                              0x314 0x6a4 0x840 0x2 0x3
+#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK                       0x314 0x6a4 0x000 0x3 0x0
+#define MX53_PAD_GPIO_0__EPIT1_EPITO                            0x314 0x6a4 0x000 0x4 0x0
+#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB                         0x314 0x6a4 0x000 0x5 0x0
+#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR                       0x314 0x6a4 0x000 0x6 0x0
+#define MX53_PAD_GPIO_0__CSU_TD                                 0x314 0x6a4 0x000 0x7 0x0
+#define MX53_PAD_GPIO_1__ESAI1_SCKR                             0x318 0x6a8 0x7dc 0x0 0x1
+#define MX53_PAD_GPIO_1__GPIO1_1                                0x318 0x6a8 0x000 0x1 0x0
+#define MX53_PAD_GPIO_1__KPP_ROW_5                              0x318 0x6a8 0x84c 0x2 0x2
+#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK                       0x318 0x6a8 0x000 0x3 0x0
+#define MX53_PAD_GPIO_1__PWM2_PWMO                              0x318 0x6a8 0x000 0x4 0x0
+#define MX53_PAD_GPIO_1__WDOG2_WDOG_B                           0x318 0x6a8 0x000 0x5 0x0
+#define MX53_PAD_GPIO_1__ESDHC1_CD                              0x318 0x6a8 0x000 0x6 0x0
+#define MX53_PAD_GPIO_1__SRC_TESTER_ACK                         0x318 0x6a8 0x000 0x7 0x0
+#define MX53_PAD_GPIO_9__ESAI1_FSR                              0x31c 0x6ac 0x7cc 0x0 0x1
+#define MX53_PAD_GPIO_9__GPIO1_9                                0x31c 0x6ac 0x000 0x1 0x0
+#define MX53_PAD_GPIO_9__KPP_COL_6                              0x31c 0x6ac 0x844 0x2 0x2
+#define MX53_PAD_GPIO_9__CCM_REF_EN_B                           0x31c 0x6ac 0x000 0x3 0x0
+#define MX53_PAD_GPIO_9__PWM1_PWMO                              0x31c 0x6ac 0x000 0x4 0x0
+#define MX53_PAD_GPIO_9__WDOG1_WDOG_B                           0x31c 0x6ac 0x000 0x5 0x0
+#define MX53_PAD_GPIO_9__ESDHC1_WP                              0x31c 0x6ac 0x7fc 0x6 0x1
+#define MX53_PAD_GPIO_9__SCC_FAIL_STATE                         0x31c 0x6ac 0x000 0x7 0x0
+#define MX53_PAD_GPIO_3__ESAI1_HCKR                             0x320 0x6b0 0x7d4 0x0 0x1
+#define MX53_PAD_GPIO_3__GPIO1_3                                0x320 0x6b0 0x000 0x1 0x0
+#define MX53_PAD_GPIO_3__I2C3_SCL                               0x320 0x6b0 0x824 0x2 0x1
+#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN                         0x320 0x6b0 0x000 0x3 0x0
+#define MX53_PAD_GPIO_3__CCM_CLKO2                              0x320 0x6b0 0x000 0x4 0x0
+#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0             0x320 0x6b0 0x000 0x5 0x0
+#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC                        0x320 0x6b0 0x8a0 0x6 0x1
+#define MX53_PAD_GPIO_3__MLB_MLBCLK                             0x320 0x6b0 0x858 0x7 0x2
+#define MX53_PAD_GPIO_6__ESAI1_SCKT                             0x324 0x6b4 0x7e0 0x0 0x1
+#define MX53_PAD_GPIO_6__GPIO1_6                                0x324 0x6b4 0x000 0x1 0x0
+#define MX53_PAD_GPIO_6__I2C3_SDA                               0x324 0x6b4 0x828 0x2 0x1
+#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0                          0x324 0x6b4 0x000 0x3 0x0
+#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB                        0x324 0x6b4 0x000 0x4 0x0
+#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1             0x324 0x6b4 0x000 0x5 0x0
+#define MX53_PAD_GPIO_6__ESDHC2_LCTL                            0x324 0x6b4 0x000 0x6 0x0
+#define MX53_PAD_GPIO_6__MLB_MLBSIG                             0x324 0x6b4 0x860 0x7 0x2
+#define MX53_PAD_GPIO_2__ESAI1_FST                              0x328 0x6b8 0x7d0 0x0 0x1
+#define MX53_PAD_GPIO_2__GPIO1_2                                0x328 0x6b8 0x000 0x1 0x0
+#define MX53_PAD_GPIO_2__KPP_ROW_6                              0x328 0x6b8 0x850 0x2 0x2
+#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1                          0x328 0x6b8 0x000 0x3 0x0
+#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0                    0x328 0x6b8 0x000 0x4 0x0
+#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2             0x328 0x6b8 0x000 0x5 0x0
+#define MX53_PAD_GPIO_2__ESDHC2_WP                              0x328 0x6b8 0x000 0x6 0x0
+#define MX53_PAD_GPIO_2__MLB_MLBDAT                             0x328 0x6b8 0x85c 0x7 0x2
+#define MX53_PAD_GPIO_4__ESAI1_HCKT                             0x32c 0x6bc 0x7d8 0x0 0x1
+#define MX53_PAD_GPIO_4__GPIO1_4                                0x32c 0x6bc 0x000 0x1 0x0
+#define MX53_PAD_GPIO_4__KPP_COL_7                              0x32c 0x6bc 0x848 0x2 0x2
+#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2                          0x32c 0x6bc 0x000 0x3 0x0
+#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1                    0x32c 0x6bc 0x000 0x4 0x0
+#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3             0x32c 0x6bc 0x000 0x5 0x0
+#define MX53_PAD_GPIO_4__ESDHC2_CD                              0x32c 0x6bc 0x000 0x6 0x0
+#define MX53_PAD_GPIO_4__SCC_SEC_STATE                          0x32c 0x6bc 0x000 0x7 0x0
+#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3                          0x330 0x6c0 0x7ec 0x0 0x1
+#define MX53_PAD_GPIO_5__GPIO1_5                                0x330 0x6c0 0x000 0x1 0x0
+#define MX53_PAD_GPIO_5__KPP_ROW_7                              0x330 0x6c0 0x854 0x2 0x2
+#define MX53_PAD_GPIO_5__CCM_CLKO                               0x330 0x6c0 0x000 0x3 0x0
+#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2                    0x330 0x6c0 0x000 0x4 0x0
+#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4             0x330 0x6c0 0x000 0x5 0x0
+#define MX53_PAD_GPIO_5__I2C3_SCL                               0x330 0x6c0 0x824 0x6 0x2
+#define MX53_PAD_GPIO_5__CCM_PLL1_BYP                           0x330 0x6c0 0x770 0x7 0x1
+#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1                          0x334 0x6c4 0x7f4 0x0 0x1
+#define MX53_PAD_GPIO_7__GPIO1_7                                0x334 0x6c4 0x000 0x1 0x0
+#define MX53_PAD_GPIO_7__EPIT1_EPITO                            0x334 0x6c4 0x000 0x2 0x0
+#define MX53_PAD_GPIO_7__CAN1_TXCAN                             0x334 0x6c4 0x000 0x3 0x0
+#define MX53_PAD_GPIO_7__UART2_TXD_MUX                          0x334 0x6c4 0x000 0x4 0x0
+#define MX53_PAD_GPIO_7__FIRI_RXD                               0x334 0x6c4 0x80c 0x5 0x1
+#define MX53_PAD_GPIO_7__SPDIF_PLOCK                            0x334 0x6c4 0x000 0x6 0x0
+#define MX53_PAD_GPIO_7__CCM_PLL2_BYP                           0x334 0x6c4 0x774 0x7 0x1
+#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0                          0x338 0x6c8 0x7f8 0x0 0x1
+#define MX53_PAD_GPIO_8__GPIO1_8                                0x338 0x6c8 0x000 0x1 0x0
+#define MX53_PAD_GPIO_8__EPIT2_EPITO                            0x338 0x6c8 0x000 0x2 0x0
+#define MX53_PAD_GPIO_8__CAN1_RXCAN                             0x338 0x6c8 0x760 0x3 0x2
+#define MX53_PAD_GPIO_8__UART2_RXD_MUX                          0x338 0x6c8 0x880 0x4 0x5
+#define MX53_PAD_GPIO_8__FIRI_TXD                               0x338 0x6c8 0x000 0x5 0x0
+#define MX53_PAD_GPIO_8__SPDIF_SRCLK                            0x338 0x6c8 0x000 0x6 0x0
+#define MX53_PAD_GPIO_8__CCM_PLL3_BYP                           0x338 0x6c8 0x778 0x7 0x1
+#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2                         0x33c 0x6cc 0x7f0 0x0 0x1
+#define MX53_PAD_GPIO_16__GPIO7_11                              0x33c 0x6cc 0x000 0x1 0x0
+#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT                      0x33c 0x6cc 0x000 0x2 0x0
+#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1                  0x33c 0x6cc 0x000 0x4 0x0
+#define MX53_PAD_GPIO_16__SPDIF_IN1                             0x33c 0x6cc 0x870 0x5 0x1
+#define MX53_PAD_GPIO_16__I2C3_SDA                              0x33c 0x6cc 0x828 0x6 0x2
+#define MX53_PAD_GPIO_16__SJC_DE_B                              0x33c 0x6cc 0x000 0x7 0x0
+#define MX53_PAD_GPIO_17__ESAI1_TX0                             0x340 0x6d0 0x7e4 0x0 0x1
+#define MX53_PAD_GPIO_17__GPIO7_12                              0x340 0x6d0 0x000 0x1 0x0
+#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0                      0x340 0x6d0 0x868 0x2 0x1
+#define MX53_PAD_GPIO_17__GPC_PMIC_RDY                          0x340 0x6d0 0x810 0x3 0x1
+#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG                   0x340 0x6d0 0x000 0x4 0x0
+#define MX53_PAD_GPIO_17__SPDIF_OUT1                            0x340 0x6d0 0x000 0x5 0x0
+#define MX53_PAD_GPIO_17__IPU_SNOOP2                            0x340 0x6d0 0x000 0x6 0x0
+#define MX53_PAD_GPIO_17__SJC_JTAG_ACT                          0x340 0x6d0 0x000 0x7 0x0
+#define MX53_PAD_GPIO_18__ESAI1_TX1                             0x344 0x6d4 0x7e8 0x0 0x1
+#define MX53_PAD_GPIO_18__GPIO7_13                              0x344 0x6d4 0x000 0x1 0x0
+#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1                      0x344 0x6d4 0x86c 0x2 0x1
+#define MX53_PAD_GPIO_18__OWIRE_LINE                            0x344 0x6d4 0x864 0x3 0x1
+#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG                0x344 0x6d4 0x000 0x4 0x0
+#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK                      0x344 0x6d4 0x768 0x5 0x1
+#define MX53_PAD_GPIO_18__ESDHC1_LCTL                           0x344 0x6d4 0x000 0x6 0x0
+#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST                        0x344 0x6d4 0x000 0x7 0x0
+
+#endif /* __DTS_IMX53_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 05cc5620436b..8f0e9ae0e3e6 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -11,7 +11,7 @@
  */
 
 /dts-v1/;
-/include/ "imx53.dtsi"
+#include "imx53.dtsi"
 
 / {
         model = "Freescale i.MX53 Quick Start Board";
@@ -110,21 +110,21 @@
         hog {
                 pinctrl_hog: hoggrp {
                         fsl,pins = <
-                                1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
-                                1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
-                                982  0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
-                                989  0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
-                                693  0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
-                                697  0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
-                                701  0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
-                                868  0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
-                                1149 0x80000000 /* MX53_PAD_GPIO_16__GPIO7_11 */
+                                MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
+                                MX53_PAD_GPIO_8__GPIO1_8          0x80000000
+                                MX53_PAD_PATA_DATA14__GPIO2_14    0x80000000
+                                MX53_PAD_PATA_DATA15__GPIO2_15    0x80000000
+                                MX53_PAD_EIM_DA11__GPIO3_11       0x80000000
+                                MX53_PAD_EIM_DA12__GPIO3_12       0x80000000
+                                MX53_PAD_EIM_DA13__GPIO3_13       0x80000000
+                                MX53_PAD_PATA_DA_0__GPIO7_6       0x80000000
+                                MX53_PAD_GPIO_16__GPIO7_11        0x80000000
                         >;
                 };
 
                 led_pin_gpio7_7: led_gpio7_7@0 {
                         fsl,pins = <
-                                873  0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
+                                MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
                         >;
                 };
         };
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 995554c324b8..a9b6e10de0a5 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -11,7 +11,7 @@
  */
 
 /dts-v1/;
-/include/ "imx53.dtsi"
+#include "imx53.dtsi"
 
 / {
         model = "Freescale i.MX53 Smart Mobile Reference Design Board";
@@ -107,13 +107,13 @@
         hog {
                 pinctrl_hog: hoggrp {
                         fsl,pins = <
-                                982  0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
-                                989  0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
-                                424  0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
-                                701  0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
-                                449  0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
-                                43   0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
-                                868  0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
+                                MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
+                                MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
+                                MX53_PAD_EIM_EB2__GPIO2_30     0x80000000
+                                MX53_PAD_EIM_DA13__GPIO3_13    0x80000000
+                                MX53_PAD_EIM_D19__GPIO3_19     0x80000000
+                                MX53_PAD_KEY_ROW2__GPIO4_11    0x80000000
+                                MX53_PAD_PATA_DA_0__GPIO7_6    0x80000000
                         >;
                 };
         };
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
index 8278ec5ec222..38bed3ed7c1a 100644
--- a/arch/arm/boot/dts/imx53-tqma53.dtsi
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -10,7 +10,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "imx53.dtsi"
+#include "imx53.dtsi"
 
 / {
         model = "TQ TQMa53";
@@ -72,11 +72,11 @@
         i2s {
                 pinctrl_i2s_1: i2s-grp1 {
                         fsl,pins = <
-                                 1   0x10000    /* I2S_MCLK */
-                                 10  0x10000    /* I2S_SCLK */
-                                 17  0x10000    /* I2S_DOUT */
-                                 23  0x10000    /* I2S_LRCLK*/
-                                 30  0x10000    /* I2S_DIN  */
+                                 MX53_PAD_GPIO_19__GPIO4_5           0x10000 /* I2S_MCLK */
+                                 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC  0x10000 /* I2S_SCLK */
+                                 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD  0x10000 /* I2S_DOUT */
+                                 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x10000 /* I2S_LRCLK */
+                                 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD  0x10000 /* I2S_DIN */
                         >;
                 };
         };
@@ -84,16 +84,16 @@
         hog {
                 pinctrl_hog: hoggrp {
                         fsl,pins = <
-                                 610  0x10000   /* MX53_PAD_EIM_CS1__IPU_DI1_PIN6 (VSYNC)*/
-                                 711  0x10000   /* MX53_PAD_EIM_DA15__IPU_DI1_PIN4 (HSYNC)*/
-                                 873  0x10000   /* MX53_PAD_PATA_DA_1__GPIO7_7 (LCD_BLT_EN)*/
-                                 878  0x10000   /* MX53_PAD_PATA_DA_2__GPIO7_8 (LCD_RESET)*/
-                                 922  0x10000   /* MX53_PAD_PATA_DATA5__GPIO2_5 (LCD_POWER)*/
-                                 928  0x10000   /* MX53_PAD_PATA_DATA6__GPIO2_6 (PMIC_INT)*/
-                                 982  0x10000   /* MX53_PAD_PATA_DATA14__GPIO2_14 (CSI_RST)*/
-                                 989  0x10000   /* MX53_PAD_PATA_DATA15__GPIO2_15 (CSI_PWDN)*/
-                                 1069 0x10000   /* MX53_PAD_GPIO_0__GPIO1_0 (SYSTEM_DOWN)*/
-                                 1093 0x10000   /* MX53_PAD_GPIO_3__GPIO1_3 */
+                                 MX53_PAD_EIM_CS1__IPU_DI1_PIN6  0x10000 /* VSYNC */
+                                 MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x10000 /* HSYNC */
+                                 MX53_PAD_PATA_DA_1__GPIO7_7     0x10000 /* LCD_BLT_EN */
+                                 MX53_PAD_PATA_DA_2__GPIO7_8     0x10000 /* LCD_RESET */
+                                 MX53_PAD_PATA_DATA5__GPIO2_5    0x10000 /* LCD_POWER */
+                                 MX53_PAD_PATA_DATA6__GPIO2_6    0x10000 /* PMIC_INT */
+                                 MX53_PAD_PATA_DATA14__GPIO2_14  0x10000 /* CSI_RST */
+                                 MX53_PAD_PATA_DATA15__GPIO2_15  0x10000 /* CSI_PWDN */
+                                 MX53_PAD_GPIO_0__GPIO1_0        0x10000 /* SYSTEM_DOWN */
+                                 MX53_PAD_GPIO_3__GPIO1_3        0x10000
                         >;
                 };
         };
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index d05aa215c7f9..845982eaac22 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -10,7 +10,8 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include "imx53-pinfunc.h"
 
 / {
         aliases {
@@ -72,6 +73,9 @@
                         compatible = "fsl,imx53-ipu";
                         reg = <0x18000000 0x080000000>;
                         interrupts = <11 10>;
+                        clocks = <&clks 59>, <&clks 110>, <&clks 61>;
+                        clock-names = "bus", "di0", "di1";
+                        resets = <&src 2>;
                 };
 
                 aips@50000000 { /* AIPS1 */
@@ -242,6 +246,14 @@
                                 status = "disabled";
                         };
 
+                        gpt: timer@53fa0000 {
+                                compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
+                                reg = <0x53fa0000 0x4000>;
+                                interrupts = <39>;
+                                clocks = <&clks 36>, <&clks 41>;
+                                clock-names = "ipg", "per";
+                        };
+
                         iomuxc: iomuxc@53fa8000 {
                                 compatible = "fsl,imx53-iomuxc";
                                 reg = <0x53fa8000 0x4000>;
@@ -249,10 +261,10 @@
                                 audmux {
                                         pinctrl_audmux_1: audmuxgrp-1 {
                                                 fsl,pins = <
-                                                        10 0x80000000   /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
-                                                        17 0x80000000   /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
-                                                        23 0x80000000   /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
-                                                        30 0x80000000   /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
+                                                        MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC  0x80000000
+                                                        MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD  0x80000000
+                                                        MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
+                                                        MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD  0x80000000
                                                 >;
                                         };
                                 };
@@ -260,16 +272,16 @@
                                 fec {
                                         pinctrl_fec_1: fecgrp-1 {
                                                 fsl,pins = <
-                                                        820 0x80000000  /* MX53_PAD_FEC_MDC__FEC_MDC */
-                                                        779 0x80000000  /* MX53_PAD_FEC_MDIO__FEC_MDIO */
-                                                        786 0x80000000  /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
-                                                        791 0x80000000  /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
-                                                        796 0x80000000  /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
-                                                        799 0x80000000  /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
-                                                        804 0x80000000  /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
-                                                        808 0x80000000  /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
-                                                        811 0x80000000  /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
-                                                        816 0x80000000  /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
+                                                        MX53_PAD_FEC_MDC__FEC_MDC        0x80000000
+                                                        MX53_PAD_FEC_MDIO__FEC_MDIO      0x80000000
+                                                        MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
+                                                        MX53_PAD_FEC_RX_ER__FEC_RX_ER    0x80000000
+                                                        MX53_PAD_FEC_CRS_DV__FEC_RX_DV   0x80000000
+                                                        MX53_PAD_FEC_RXD1__FEC_RDATA_1   0x80000000
+                                                        MX53_PAD_FEC_RXD0__FEC_RDATA_0   0x80000000
+                                                        MX53_PAD_FEC_TX_EN__FEC_TX_EN    0x80000000
+                                                        MX53_PAD_FEC_TXD1__FEC_TDATA_1   0x80000000
+                                                        MX53_PAD_FEC_TXD0__FEC_TDATA_0   0x80000000
                                                 >;
                                         };
                                 };
@@ -277,27 +289,27 @@
                                 csi {
                                         pinctrl_csi_1: csigrp-1 {
                                                 fsl,pins = <
-                                                        286 0x1d5       /* MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN */
-                                                        291 0x1d5       /* MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC */
-                                                        280 0x1d5       /* MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC */
-                                                        276 0x1d5       /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
-                                                        409 0x1d5       /* MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 */
-                                                        402 0x1d5       /* MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 */
-                                                        395 0x1d5       /* MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 */
-                                                        388 0x1d5       /* MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 */
-                                                        381 0x1d5       /* MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 */
-                                                        374 0x1d5       /* MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 */
-                                                        367 0x1d5       /* MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 */
-                                                        360 0x1d5       /* MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 */
-                                                        352 0x1d5       /* MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 */
-                                                        344 0x1d5       /* MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 */
-                                                        336 0x1d5       /* MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 */
-                                                        328 0x1d5       /* MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 */
-                                                        320 0x1d5       /* MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 */
-                                                        312 0x1d5       /* MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 */
-                                                        304 0x1d5       /* MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 */
-                                                        296 0x1d5       /* MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 */
-                                                        276 0x1d5       /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
+                                                        MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
+                                                        MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC     0x1d5
+                                                        MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC      0x1d5
+                                                        MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
+                                                        MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19      0x1d5
+                                                        MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18      0x1d5
+                                                        MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17      0x1d5
+                                                        MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16      0x1d5
+                                                        MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15      0x1d5
+                                                        MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14      0x1d5
+                                                        MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13      0x1d5
+                                                        MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12      0x1d5
+                                                        MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11      0x1d5
+                                                        MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10      0x1d5
+                                                        MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9        0x1d5
+                                                        MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8        0x1d5
+                                                        MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7        0x1d5
+                                                        MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6        0x1d5
+                                                        MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5        0x1d5
+                                                        MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4        0x1d5
+                                                        MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
                                                 >;
                                         };
                                 };
@@ -305,9 +317,9 @@
                                 cspi {
                                         pinctrl_cspi_1: cspigrp-1 {
                                                 fsl,pins = <
-                                                        998  0x1d5      /* MX53_PAD_SD1_DATA0__CSPI_MISO */
-                                                        1008 0x1d5      /* MX53_PAD_SD1_CMD__CSPI_MOSI */
-                                                        1022 0x1d5      /* MX53_PAD_SD1_CLK__CSPI_SCLK */
+                                                        MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
+                                                        MX53_PAD_SD1_CMD__CSPI_MOSI   0x1d5
+                                                        MX53_PAD_SD1_CLK__CSPI_SCLK   0x1d5
                                                 >;
                                         };
                                 };
@@ -315,9 +327,9 @@
                                 ecspi1 {
                                         pinctrl_ecspi1_1: ecspi1grp-1 {
                                                 fsl,pins = <
-                                                        433 0x80000000  /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
-                                                        439 0x80000000  /* MX53_PAD_EIM_D17__ECSPI1_MISO */
-                                                        445 0x80000000  /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
+                                                        MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
+                                                        MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
+                                                        MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
                                                 >;
                                         };
                                 };
@@ -325,27 +337,27 @@
                                 esdhc1 {
                                         pinctrl_esdhc1_1: esdhc1grp-1 {
                                                 fsl,pins = <
-                                                        995  0x1d5      /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
-                                                        1000 0x1d5      /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
-                                                        1010 0x1d5      /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
-                                                        1024 0x1d5      /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
-                                                        1005 0x1d5      /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
-                                                        1018 0x1d5      /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
+                                                        MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
+                                                        MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
+                                                        MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
+                                                        MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
+                                                        MX53_PAD_SD1_CMD__ESDHC1_CMD    0x1d5
+                                                        MX53_PAD_SD1_CLK__ESDHC1_CLK    0x1d5
                                                 >;
                                         };
 
                                         pinctrl_esdhc1_2: esdhc1grp-2 {
                                                 fsl,pins = <
-                                                        995  0x1d5      /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
-                                                        1000 0x1d5      /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
-                                                        1010 0x1d5      /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
-                                                        1024 0x1d5      /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
-                                                        941  0x1d5      /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
-                                                        948  0x1d5      /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
-                                                        955  0x1d5      /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
-                                                        962  0x1d5      /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
-                                                        1005 0x1d5      /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
-                                                        1018 0x1d5      /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
+                                                        MX53_PAD_SD1_DATA0__ESDHC1_DAT0   0x1d5
+                                                        MX53_PAD_SD1_DATA1__ESDHC1_DAT1   0x1d5
+                                                        MX53_PAD_SD1_DATA2__ESDHC1_DAT2   0x1d5
+                                                        MX53_PAD_SD1_DATA3__ESDHC1_DAT3   0x1d5
+                                                        MX53_PAD_PATA_DATA8__ESDHC1_DAT4  0x1d5
+                                                        MX53_PAD_PATA_DATA9__ESDHC1_DAT5  0x1d5
+                                                        MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
+                                                        MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
+                                                        MX53_PAD_SD1_CMD__ESDHC1_CMD      0x1d5
+                                                        MX53_PAD_SD1_CLK__ESDHC1_CLK      0x1d5
                                                 >;
                                         };
                                 };
@@ -353,12 +365,12 @@
                                 esdhc2 {
                                         pinctrl_esdhc2_1: esdhc2grp-1 {
                                                 fsl,pins = <
-                                                        1038 0x1d5      /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
-                                                        1032 0x1d5      /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
-                                                        1062 0x1d5      /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
-                                                        1056 0x1d5      /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
-                                                        1050 0x1d5      /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
-                                                        1044 0x1d5      /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
+                                                        MX53_PAD_SD2_CMD__ESDHC2_CMD    0x1d5
+                                                        MX53_PAD_SD2_CLK__ESDHC2_CLK    0x1d5
+                                                        MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
+                                                        MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
+                                                        MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
+                                                        MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
                                                 >;
                                         };
                                 };
@@ -366,16 +378,16 @@
                                 esdhc3 {
                                         pinctrl_esdhc3_1: esdhc3grp-1 {
                                                 fsl,pins = <
-                                                        943 0x1d5       /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
-                                                        950 0x1d5       /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
-                                                        957 0x1d5       /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
-                                                        964 0x1d5       /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
-                                                        893 0x1d5       /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
-                                                        900 0x1d5       /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
-                                                        906 0x1d5       /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
-                                                        912 0x1d5       /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
-                                                        857 0x1d5       /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
-                                                        863 0x1d5       /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
+                                                        MX53_PAD_PATA_DATA8__ESDHC3_DAT0  0x1d5
+                                                        MX53_PAD_PATA_DATA9__ESDHC3_DAT1  0x1d5
+                                                        MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
+                                                        MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
+                                                        MX53_PAD_PATA_DATA0__ESDHC3_DAT4  0x1d5
+                                                        MX53_PAD_PATA_DATA1__ESDHC3_DAT5  0x1d5
+                                                        MX53_PAD_PATA_DATA2__ESDHC3_DAT6  0x1d5
+                                                        MX53_PAD_PATA_DATA3__ESDHC3_DAT7  0x1d5
+                                                        MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
+                                                        MX53_PAD_PATA_IORDY__ESDHC3_CLK   0x1d5
                                                 >;
                                         };
                                 };
@@ -383,15 +395,15 @@
                                 can1 {
                                         pinctrl_can1_1: can1grp-1 {
                                                 fsl,pins = <
-                                                        847 0x80000000  /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
-                                                        853 0x80000000  /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
+                                                        MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
+                                                        MX53_PAD_PATA_DIOR__CAN1_RXCAN  0x80000000
                                                 >;
                                         };
 
                                         pinctrl_can1_2: can1grp-2 {
                                                 fsl,pins = <
-                                                        37  0x80000000  /* MX53_PAD_KEY_COL2__CAN1_TXCAN */
-                                                        44  0x80000000  /* MX53_PAD_KEY_ROW2__CAN1_RXCAN */
+                                                        MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
+                                                        MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
                                                 >;
                                         };
                                 };
@@ -399,8 +411,8 @@
                                 can2 {
                                         pinctrl_can2_1: can2grp-1 {
                                                 fsl,pins = <
-                                                        67  0x80000000  /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
-                                                        74  0x80000000  /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
+                                                        MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
+                                                        MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
                                                 >;
                                         };
                                 };
@@ -408,8 +420,8 @@
                                 i2c1 {
                                         pinctrl_i2c1_1: i2c1grp-1 {
                                                 fsl,pins = <
-                                                        333 0xc0000000  /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
-                                                        341 0xc0000000  /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
+                                                        MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
+                                                        MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
                                                 >;
                                         };
                                 };
@@ -417,8 +429,8 @@
                                 i2c2 {
                                         pinctrl_i2c2_1: i2c2grp-1 {
                                                 fsl,pins = <
-                                                        61 0xc0000000   /* MX53_PAD_KEY_ROW3__I2C2_SDA */
-                                                        53 0xc0000000   /* MX53_PAD_KEY_COL3__I2C2_SCL */
+                                                        MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
+                                                        MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
                                                 >;
                                         };
                                 };
@@ -426,8 +438,8 @@
                                 i2c3 {
                                         pinctrl_i2c3_1: i2c3grp-1 {
                                                 fsl,pins = <
-                                                        1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */
-                                                        1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */
+                                                        MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
+                                                        MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
                                                 >;
                                         };
                                 };
@@ -435,7 +447,7 @@
                                 owire {
                                         pinctrl_owire_1: owiregrp-1 {
                                                 fsl,pins = <
-                                                                1166 0x80000000 /* MX53_PAD_GPIO_18__OWIRE_LINE */
+                                                        MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
                                                 >;
                                         };
                                 };
@@ -443,15 +455,15 @@
                                 uart1 {
                                         pinctrl_uart1_1: uart1grp-1 {
                                                 fsl,pins = <
-                                                        346 0x1c5       /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
-                                                        354 0x1c5       /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
+                                                        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
+                                                        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
                                                 >;
                                         };
 
                                         pinctrl_uart1_2: uart1grp-2 {
                                                 fsl,pins = <
-                                                        828 0x1c5       /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
-                                                        832 0x1c5       /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
+                                                        MX53_PAD_PATA_DIOW__UART1_TXD_MUX  0x1c5
+                                                        MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
                                                 >;
                                         };
                                 };
@@ -459,8 +471,8 @@
                                 uart2 {
                                         pinctrl_uart2_1: uart2grp-1 {
                                                 fsl,pins = <
-                                                        841 0x1c5       /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
-                                                        836 0x1c5       /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
+                                                        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
+                                                        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX     0x1c5
                                                 >;
                                         };
                                 };
@@ -468,17 +480,17 @@
                                 uart3 {
                                         pinctrl_uart3_1: uart3grp-1 {
                                                 fsl,pins = <
-                                                        884 0x1c5       /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
-                                                        888 0x1c5       /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
-                                                        875 0x1c5       /* MX53_PAD_PATA_DA_1__UART3_CTS */
-                                                        880 0x1c5       /* MX53_PAD_PATA_DA_2__UART3_RTS */
+                                                        MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
+                                                        MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
+                                                        MX53_PAD_PATA_DA_1__UART3_CTS     0x1c5
+                                                        MX53_PAD_PATA_DA_2__UART3_RTS     0x1c5
                                                 >;
                                         };
 
                                         pinctrl_uart3_2: uart3grp-2 {
                                                 fsl,pins = <
-                                                        884 0x1c5       /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
-                                                        888 0x1c5       /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
+                                                        MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
+                                                        MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
                                                 >;
                                         };
 
@@ -487,8 +499,8 @@
                                 uart4 {
                                         pinctrl_uart4_1: uart4grp-1 {
                                                 fsl,pins = <
-                                                        11 0x1c5        /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
-                                                        18 0x1c5        /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
+                                                        MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
+                                                        MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
                                                 >;
                                         };
                                 };
@@ -496,14 +508,46 @@
                                 uart5 {
                                         pinctrl_uart5_1: uart5grp-1 {
                                                 fsl,pins = <
-                                                        24 0x1c5        /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
-                                                        31 0x1c5        /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
+                                                        MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
+                                                        MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
                                                 >;
                                         };
                                 };
 
                         };
 
+                        gpr: iomuxc-gpr@53fa8000 {
+                                compatible = "fsl,imx53-iomuxc-gpr", "syscon";
+                                reg = <0x53fa8000 0xc>;
+                        };
+
+                        ldb: ldb@53fa8008 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx53-ldb";
+                                reg = <0x53fa8008 0x4>;
+                                gpr = <&gpr>;
+                                clocks = <&clks 122>, <&clks 120>,
+                                         <&clks 115>, <&clks 116>,
+                                         <&clks 123>, <&clks 85>;
+                                clock-names = "di0_pll", "di1_pll",
+                                              "di0_sel", "di1_sel",
+                                              "di0", "di1";
+                                status = "disabled";
+
+                                lvds-channel@0 {
+                                        reg = <0>;
+                                        crtcs = <&ipu 0>;
+                                        status = "disabled";
+                                };
+
+                                lvds-channel@1 {
+                                        reg = <1>;
+                                        crtcs = <&ipu 1>;
+                                        status = "disabled";
+                                };
+                        };
+
                         pwm1: pwm@53fb4000 {
                                 #pwm-cells = <2>;
                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
@@ -558,6 +602,12 @@
                                 status = "disabled";
                         };
 
+                        src: src@53fd0000 {
+                                compatible = "fsl,imx53-src", "fsl,imx51-src";
+                                reg = <0x53fd0000 0x4000>;
+                                #reset-cells = <1>;
+                        };
+
                         clks: ccm@53fd4000{
                                 compatible = "fsl,imx53-ccm";
                                 reg = <0x53fd4000 0x4000>;
diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/imx6dl-pinfunc.h
new file mode 100644
index 000000000000..9aab950ec269
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-pinfunc.h
@@ -0,0 +1,1085 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6DL_PINFUNC_H
+#define __DTS_IMX6DL_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6DL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10     0x04c 0x360 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_DAT10__AUD3_RXC             0x04c 0x360 0x000 0x1 0x0
+#define MX6DL_PAD_CSI0_DAT10__ECSPI2_MISO          0x04c 0x360 0x7f8 0x2 0x0
+#define MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA        0x04c 0x360 0x000 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT10__UART1_RX_DATA        0x04c 0x360 0x8fc 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT10__GPIO5_IO28           0x04c 0x360 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_DAT10__ARM_TRACE07          0x04c 0x360 0x000 0x7 0x0
+#define MX6DL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11     0x050 0x364 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_DAT11__AUD3_RXFS            0x050 0x364 0x000 0x1 0x0
+#define MX6DL_PAD_CSI0_DAT11__ECSPI2_SS0           0x050 0x364 0x800 0x2 0x0
+#define MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA        0x050 0x364 0x8fc 0x3 0x1
+#define MX6DL_PAD_CSI0_DAT11__UART1_TX_DATA        0x050 0x364 0x000 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT11__GPIO5_IO29           0x050 0x364 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_DAT11__ARM_TRACE08          0x050 0x364 0x000 0x7 0x0
+#define MX6DL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12     0x054 0x368 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_DAT12__EIM_DATA08           0x054 0x368 0x000 0x1 0x0
+#define MX6DL_PAD_CSI0_DAT12__UART4_TX_DATA        0x054 0x368 0x000 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT12__UART4_RX_DATA        0x054 0x368 0x914 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT12__GPIO5_IO30           0x054 0x368 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_DAT12__ARM_TRACE09          0x054 0x368 0x000 0x7 0x0
+#define MX6DL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13     0x058 0x36c 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_DAT13__EIM_DATA09           0x058 0x36c 0x000 0x1 0x0
+#define MX6DL_PAD_CSI0_DAT13__UART4_RX_DATA        0x058 0x36c 0x914 0x3 0x1
+#define MX6DL_PAD_CSI0_DAT13__UART4_TX_DATA        0x058 0x36c 0x000 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT13__GPIO5_IO31           0x058 0x36c 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_DAT13__ARM_TRACE10          0x058 0x36c 0x000 0x7 0x0
+#define MX6DL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14     0x05c 0x370 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_DAT14__EIM_DATA10           0x05c 0x370 0x000 0x1 0x0
+#define MX6DL_PAD_CSI0_DAT14__UART5_TX_DATA        0x05c 0x370 0x000 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT14__UART5_RX_DATA        0x05c 0x370 0x91c 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT14__GPIO6_IO00           0x05c 0x370 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_DAT14__ARM_TRACE11          0x05c 0x370 0x000 0x7 0x0
+#define MX6DL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15     0x060 0x374 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_DAT15__EIM_DATA11           0x060 0x374 0x000 0x1 0x0
+#define MX6DL_PAD_CSI0_DAT15__UART5_RX_DATA        0x060 0x374 0x91c 0x3 0x1
+#define MX6DL_PAD_CSI0_DAT15__UART5_TX_DATA        0x060 0x374 0x000 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT15__GPIO6_IO01           0x060 0x374 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_DAT15__ARM_TRACE12          0x060 0x374 0x000 0x7 0x0
+#define MX6DL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16     0x064 0x378 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_DAT16__EIM_DATA12           0x064 0x378 0x000 0x1 0x0
+#define MX6DL_PAD_CSI0_DAT16__UART4_RTS_B          0x064 0x378 0x910 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT16__UART4_CTS_B          0x064 0x378 0x000 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT16__GPIO6_IO02           0x064 0x378 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_DAT16__ARM_TRACE13          0x064 0x378 0x000 0x7 0x0
+#define MX6DL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17     0x068 0x37c 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_DAT17__EIM_DATA13           0x068 0x37c 0x000 0x1 0x0
+#define MX6DL_PAD_CSI0_DAT17__UART4_CTS_B          0x068 0x37c 0x000 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT17__UART4_RTS_B          0x068 0x37c 0x910 0x3 0x1
+#define MX6DL_PAD_CSI0_DAT17__GPIO6_IO03           0x068 0x37c 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_DAT17__ARM_TRACE14          0x068 0x37c 0x000 0x7 0x0
+#define MX6DL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18     0x06c 0x380 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_DAT18__EIM_DATA14           0x06c 0x380 0x000 0x1 0x0
+#define MX6DL_PAD_CSI0_DAT18__UART5_RTS_B          0x06c 0x380 0x918 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT18__UART5_CTS_B          0x06c 0x380 0x000 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT18__GPIO6_IO04           0x06c 0x380 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_DAT18__ARM_TRACE15          0x06c 0x380 0x000 0x7 0x0
+#define MX6DL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19     0x070 0x384 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_DAT19__EIM_DATA15           0x070 0x384 0x000 0x1 0x0
+#define MX6DL_PAD_CSI0_DAT19__UART5_CTS_B          0x070 0x384 0x000 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT19__UART5_RTS_B          0x070 0x384 0x918 0x3 0x1
+#define MX6DL_PAD_CSI0_DAT19__GPIO6_IO05           0x070 0x384 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04      0x074 0x388 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_DAT4__EIM_DATA02            0x074 0x388 0x000 0x1 0x0
+#define MX6DL_PAD_CSI0_DAT4__ECSPI1_SCLK           0x074 0x388 0x7d8 0x2 0x0
+#define MX6DL_PAD_CSI0_DAT4__KEY_COL5              0x074 0x388 0x8c0 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT4__AUD3_TXC              0x074 0x388 0x000 0x4 0x0
+#define MX6DL_PAD_CSI0_DAT4__GPIO5_IO22            0x074 0x388 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_DAT4__ARM_TRACE01           0x074 0x388 0x000 0x7 0x0
+#define MX6DL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05      0x078 0x38c 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_DAT5__EIM_DATA03            0x078 0x38c 0x000 0x1 0x0
+#define MX6DL_PAD_CSI0_DAT5__ECSPI1_MOSI           0x078 0x38c 0x7e0 0x2 0x0
+#define MX6DL_PAD_CSI0_DAT5__KEY_ROW5              0x078 0x38c 0x8cc 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT5__AUD3_TXD              0x078 0x38c 0x000 0x4 0x0
+#define MX6DL_PAD_CSI0_DAT5__GPIO5_IO23            0x078 0x38c 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_DAT5__ARM_TRACE02           0x078 0x38c 0x000 0x7 0x0
+#define MX6DL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06      0x07c 0x390 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_DAT6__EIM_DATA04            0x07c 0x390 0x000 0x1 0x0
+#define MX6DL_PAD_CSI0_DAT6__ECSPI1_MISO           0x07c 0x390 0x7dc 0x2 0x0
+#define MX6DL_PAD_CSI0_DAT6__KEY_COL6              0x07c 0x390 0x8c4 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT6__AUD3_TXFS             0x07c 0x390 0x000 0x4 0x0
+#define MX6DL_PAD_CSI0_DAT6__GPIO5_IO24            0x07c 0x390 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_DAT6__ARM_TRACE03           0x07c 0x390 0x000 0x7 0x0
+#define MX6DL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07      0x080 0x394 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_DAT7__EIM_DATA05            0x080 0x394 0x000 0x1 0x0
+#define MX6DL_PAD_CSI0_DAT7__ECSPI1_SS0            0x080 0x394 0x7e4 0x2 0x0
+#define MX6DL_PAD_CSI0_DAT7__KEY_ROW6              0x080 0x394 0x8d0 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT7__AUD3_RXD              0x080 0x394 0x000 0x4 0x0
+#define MX6DL_PAD_CSI0_DAT7__GPIO5_IO25            0x080 0x394 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_DAT7__ARM_TRACE04           0x080 0x394 0x000 0x7 0x0
+#define MX6DL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08      0x084 0x398 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_DAT8__EIM_DATA06            0x084 0x398 0x000 0x1 0x0
+#define MX6DL_PAD_CSI0_DAT8__ECSPI2_SCLK           0x084 0x398 0x7f4 0x2 0x0
+#define MX6DL_PAD_CSI0_DAT8__KEY_COL7              0x084 0x398 0x8c8 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT8__I2C1_SDA              0x084 0x398 0x86c 0x4 0x0
+#define MX6DL_PAD_CSI0_DAT8__GPIO5_IO26            0x084 0x398 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_DAT8__ARM_TRACE05           0x084 0x398 0x000 0x7 0x0
+#define MX6DL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09      0x088 0x39c 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_DAT9__EIM_DATA07            0x088 0x39c 0x000 0x1 0x0
+#define MX6DL_PAD_CSI0_DAT9__ECSPI2_MOSI           0x088 0x39c 0x7fc 0x2 0x0
+#define MX6DL_PAD_CSI0_DAT9__KEY_ROW7              0x088 0x39c 0x8d4 0x3 0x0
+#define MX6DL_PAD_CSI0_DAT9__I2C1_SCL              0x088 0x39c 0x868 0x4 0x0
+#define MX6DL_PAD_CSI0_DAT9__GPIO5_IO27            0x088 0x39c 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_DAT9__ARM_TRACE06           0x088 0x39c 0x000 0x7 0x0
+#define MX6DL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN  0x08c 0x3a0 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_DATA_EN__EIM_DATA00         0x08c 0x3a0 0x000 0x1 0x0
+#define MX6DL_PAD_CSI0_DATA_EN__GPIO5_IO20         0x08c 0x3a0 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK      0x08c 0x3a0 0x000 0x7 0x0
+#define MX6DL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC       0x090 0x3a4 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_MCLK__CCM_CLKO1             0x090 0x3a4 0x000 0x3 0x0
+#define MX6DL_PAD_CSI0_MCLK__GPIO5_IO19            0x090 0x3a4 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_MCLK__ARM_TRACE_CTL         0x090 0x3a4 0x000 0x7 0x0
+#define MX6DL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK    0x094 0x3a8 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_PIXCLK__GPIO5_IO18          0x094 0x3a8 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_PIXCLK__ARM_EVENTO          0x094 0x3a8 0x000 0x7 0x0
+#define MX6DL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC      0x098 0x3ac 0x000 0x0 0x0
+#define MX6DL_PAD_CSI0_VSYNC__EIM_DATA01           0x098 0x3ac 0x000 0x1 0x0
+#define MX6DL_PAD_CSI0_VSYNC__GPIO5_IO21           0x098 0x3ac 0x000 0x5 0x0
+#define MX6DL_PAD_CSI0_VSYNC__ARM_TRACE00          0x098 0x3ac 0x000 0x7 0x0
+#define MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK  0x09c 0x3b0 0x000 0x0 0x0
+#define MX6DL_PAD_DI0_DISP_CLK__LCD_CLK            0x09c 0x3b0 0x000 0x1 0x0
+#define MX6DL_PAD_DI0_DISP_CLK__GPIO4_IO16         0x09c 0x3b0 0x000 0x5 0x0
+#define MX6DL_PAD_DI0_DISP_CLK__LCD_WR_RWN         0x09c 0x3b0 0x000 0x8 0x0
+#define MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15        0x0a0 0x3b4 0x000 0x0 0x0
+#define MX6DL_PAD_DI0_PIN15__LCD_ENABLE            0x0a0 0x3b4 0x000 0x1 0x0
+#define MX6DL_PAD_DI0_PIN15__AUD6_TXC              0x0a0 0x3b4 0x000 0x2 0x0
+#define MX6DL_PAD_DI0_PIN15__GPIO4_IO17            0x0a0 0x3b4 0x000 0x5 0x0
+#define MX6DL_PAD_DI0_PIN15__LCD_RD_E              0x0a0 0x3b4 0x000 0x8 0x0
+#define MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN02         0x0a4 0x3b8 0x000 0x0 0x0
+#define MX6DL_PAD_DI0_PIN2__LCD_HSYNC              0x0a4 0x3b8 0x8d8 0x1 0x0
+#define MX6DL_PAD_DI0_PIN2__AUD6_TXD               0x0a4 0x3b8 0x000 0x2 0x0
+#define MX6DL_PAD_DI0_PIN2__GPIO4_IO18             0x0a4 0x3b8 0x000 0x5 0x0
+#define MX6DL_PAD_DI0_PIN2__LCD_RS                 0x0a4 0x3b8 0x000 0x8 0x0
+#define MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN03         0x0a8 0x3bc 0x000 0x0 0x0
+#define MX6DL_PAD_DI0_PIN3__LCD_VSYNC              0x0a8 0x3bc 0x000 0x1 0x0
+#define MX6DL_PAD_DI0_PIN3__AUD6_TXFS              0x0a8 0x3bc 0x000 0x2 0x0
+#define MX6DL_PAD_DI0_PIN3__GPIO4_IO19             0x0a8 0x3bc 0x000 0x5 0x0
+#define MX6DL_PAD_DI0_PIN3__LCD_CS                 0x0a8 0x3bc 0x000 0x8 0x0
+#define MX6DL_PAD_DI0_PIN4__IPU1_DI0_PIN04         0x0ac 0x3c0 0x000 0x0 0x0
+#define MX6DL_PAD_DI0_PIN4__LCD_BUSY               0x0ac 0x3c0 0x8d8 0x1 0x1
+#define MX6DL_PAD_DI0_PIN4__AUD6_RXD               0x0ac 0x3c0 0x000 0x2 0x0
+#define MX6DL_PAD_DI0_PIN4__SD1_WP                 0x0ac 0x3c0 0x92c 0x3 0x0
+#define MX6DL_PAD_DI0_PIN4__GPIO4_IO20             0x0ac 0x3c0 0x000 0x5 0x0
+#define MX6DL_PAD_DI0_PIN4__LCD_RESET              0x0ac 0x3c0 0x000 0x8 0x0
+#define MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00    0x0b0 0x3c4 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT0__LCD_DATA00           0x0b0 0x3c4 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT0__ECSPI3_SCLK          0x0b0 0x3c4 0x000 0x2 0x0
+#define MX6DL_PAD_DISP0_DAT0__GPIO4_IO21           0x0b0 0x3c4 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01    0x0b4 0x3c8 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT1__LCD_DATA01           0x0b4 0x3c8 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT1__ECSPI3_MOSI          0x0b4 0x3c8 0x000 0x2 0x0
+#define MX6DL_PAD_DISP0_DAT1__GPIO4_IO22           0x0b4 0x3c8 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10   0x0b8 0x3cc 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT10__LCD_DATA10          0x0b8 0x3cc 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT10__GPIO4_IO31          0x0b8 0x3cc 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11   0x0bc 0x3d0 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT11__LCD_DATA11          0x0bc 0x3d0 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT11__GPIO5_IO05          0x0bc 0x3d0 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12   0x0c0 0x3d4 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT12__LCD_DATA12          0x0c0 0x3d4 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT12__GPIO5_IO06          0x0c0 0x3d4 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13   0x0c4 0x3d8 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT13__LCD_DATA13          0x0c4 0x3d8 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT13__AUD5_RXFS           0x0c4 0x3d8 0x7bc 0x3 0x0
+#define MX6DL_PAD_DISP0_DAT13__GPIO5_IO07          0x0c4 0x3d8 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14   0x0c8 0x3dc 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT14__LCD_DATA14          0x0c8 0x3dc 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT14__AUD5_RXC            0x0c8 0x3dc 0x7b8 0x3 0x0
+#define MX6DL_PAD_DISP0_DAT14__GPIO5_IO08          0x0c8 0x3dc 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15   0x0cc 0x3e0 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT15__LCD_DATA15          0x0cc 0x3e0 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT15__ECSPI1_SS1          0x0cc 0x3e0 0x7e8 0x2 0x0
+#define MX6DL_PAD_DISP0_DAT15__ECSPI2_SS1          0x0cc 0x3e0 0x804 0x3 0x0
+#define MX6DL_PAD_DISP0_DAT15__GPIO5_IO09          0x0cc 0x3e0 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16   0x0d0 0x3e4 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT16__LCD_DATA16          0x0d0 0x3e4 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT16__ECSPI2_MOSI         0x0d0 0x3e4 0x7fc 0x2 0x1
+#define MX6DL_PAD_DISP0_DAT16__AUD5_TXC            0x0d0 0x3e4 0x7c0 0x3 0x0
+#define MX6DL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0     0x0d0 0x3e4 0x8e8 0x4 0x0
+#define MX6DL_PAD_DISP0_DAT16__GPIO5_IO10          0x0d0 0x3e4 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17   0x0d4 0x3e8 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT17__LCD_DATA17          0x0d4 0x3e8 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT17__ECSPI2_MISO         0x0d4 0x3e8 0x7f8 0x2 0x1
+#define MX6DL_PAD_DISP0_DAT17__AUD5_TXD            0x0d4 0x3e8 0x7b4 0x3 0x0
+#define MX6DL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1     0x0d4 0x3e8 0x8ec 0x4 0x0
+#define MX6DL_PAD_DISP0_DAT17__GPIO5_IO11          0x0d4 0x3e8 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18   0x0d8 0x3ec 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT18__LCD_DATA18          0x0d8 0x3ec 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT18__ECSPI2_SS0          0x0d8 0x3ec 0x800 0x2 0x1
+#define MX6DL_PAD_DISP0_DAT18__AUD5_TXFS           0x0d8 0x3ec 0x7c4 0x3 0x0
+#define MX6DL_PAD_DISP0_DAT18__AUD4_RXFS           0x0d8 0x3ec 0x7a4 0x4 0x0
+#define MX6DL_PAD_DISP0_DAT18__GPIO5_IO12          0x0d8 0x3ec 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT18__EIM_CS2_B           0x0d8 0x3ec 0x000 0x7 0x0
+#define MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19   0x0dc 0x3f0 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT19__LCD_DATA19          0x0dc 0x3f0 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT19__ECSPI2_SCLK         0x0dc 0x3f0 0x7f4 0x2 0x1
+#define MX6DL_PAD_DISP0_DAT19__AUD5_RXD            0x0dc 0x3f0 0x7b0 0x3 0x0
+#define MX6DL_PAD_DISP0_DAT19__AUD4_RXC            0x0dc 0x3f0 0x7a0 0x4 0x0
+#define MX6DL_PAD_DISP0_DAT19__GPIO5_IO13          0x0dc 0x3f0 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT19__EIM_CS3_B           0x0dc 0x3f0 0x000 0x7 0x0
+#define MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02    0x0e0 0x3f4 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT2__LCD_DATA02           0x0e0 0x3f4 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT2__ECSPI3_MISO          0x0e0 0x3f4 0x000 0x2 0x0
+#define MX6DL_PAD_DISP0_DAT2__GPIO4_IO23           0x0e0 0x3f4 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20   0x0e4 0x3f8 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT20__LCD_DATA20          0x0e4 0x3f8 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT20__ECSPI1_SCLK         0x0e4 0x3f8 0x7d8 0x2 0x1
+#define MX6DL_PAD_DISP0_DAT20__AUD4_TXC            0x0e4 0x3f8 0x7a8 0x3 0x0
+#define MX6DL_PAD_DISP0_DAT20__GPIO5_IO14          0x0e4 0x3f8 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21   0x0e8 0x3fc 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT21__LCD_DATA21          0x0e8 0x3fc 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT21__ECSPI1_MOSI         0x0e8 0x3fc 0x7e0 0x2 0x1
+#define MX6DL_PAD_DISP0_DAT21__AUD4_TXD            0x0e8 0x3fc 0x79c 0x3 0x0
+#define MX6DL_PAD_DISP0_DAT21__GPIO5_IO15          0x0e8 0x3fc 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22   0x0ec 0x400 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT22__LCD_DATA22          0x0ec 0x400 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT22__ECSPI1_MISO         0x0ec 0x400 0x7dc 0x2 0x1
+#define MX6DL_PAD_DISP0_DAT22__AUD4_TXFS           0x0ec 0x400 0x7ac 0x3 0x0
+#define MX6DL_PAD_DISP0_DAT22__GPIO5_IO16          0x0ec 0x400 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23   0x0f0 0x404 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT23__LCD_DATA23          0x0f0 0x404 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT23__ECSPI1_SS0          0x0f0 0x404 0x7e4 0x2 0x1
+#define MX6DL_PAD_DISP0_DAT23__AUD4_RXD            0x0f0 0x404 0x798 0x3 0x0
+#define MX6DL_PAD_DISP0_DAT23__GPIO5_IO17          0x0f0 0x404 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03    0x0f4 0x408 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT3__LCD_DATA03           0x0f4 0x408 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT3__ECSPI3_SS0           0x0f4 0x408 0x000 0x2 0x0
+#define MX6DL_PAD_DISP0_DAT3__GPIO4_IO24           0x0f4 0x408 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04    0x0f8 0x40c 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT4__LCD_DATA04           0x0f8 0x40c 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT4__ECSPI3_SS1           0x0f8 0x40c 0x000 0x2 0x0
+#define MX6DL_PAD_DISP0_DAT4__GPIO4_IO25           0x0f8 0x40c 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05    0x0fc 0x410 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT5__LCD_DATA05           0x0fc 0x410 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT5__ECSPI3_SS2           0x0fc 0x410 0x000 0x2 0x0
+#define MX6DL_PAD_DISP0_DAT5__AUD6_RXFS            0x0fc 0x410 0x000 0x3 0x0
+#define MX6DL_PAD_DISP0_DAT5__GPIO4_IO26           0x0fc 0x410 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06    0x100 0x414 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT6__LCD_DATA06           0x100 0x414 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT6__ECSPI3_SS3           0x100 0x414 0x000 0x2 0x0
+#define MX6DL_PAD_DISP0_DAT6__AUD6_RXC             0x100 0x414 0x000 0x3 0x0
+#define MX6DL_PAD_DISP0_DAT6__GPIO4_IO27           0x100 0x414 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07    0x104 0x418 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT7__LCD_DATA07           0x104 0x418 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT7__ECSPI3_RDY           0x104 0x418 0x000 0x2 0x0
+#define MX6DL_PAD_DISP0_DAT7__GPIO4_IO28           0x104 0x418 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08    0x108 0x41c 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT8__LCD_DATA08           0x108 0x41c 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT8__PWM1_OUT             0x108 0x41c 0x000 0x2 0x0
+#define MX6DL_PAD_DISP0_DAT8__WDOG1_B              0x108 0x41c 0x000 0x3 0x0
+#define MX6DL_PAD_DISP0_DAT8__GPIO4_IO29           0x108 0x41c 0x000 0x5 0x0
+#define MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09    0x10c 0x420 0x000 0x0 0x0
+#define MX6DL_PAD_DISP0_DAT9__LCD_DATA09           0x10c 0x420 0x000 0x1 0x0
+#define MX6DL_PAD_DISP0_DAT9__PWM2_OUT             0x10c 0x420 0x000 0x2 0x0
+#define MX6DL_PAD_DISP0_DAT9__WDOG2_B              0x10c 0x420 0x000 0x3 0x0
+#define MX6DL_PAD_DISP0_DAT9__GPIO4_IO30           0x10c 0x420 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_A16__EIM_ADDR16              0x110 0x4e0 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_A16__IPU1_DI1_DISP_CLK       0x110 0x4e0 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_A16__IPU1_CSI1_PIXCLK        0x110 0x4e0 0x8b8 0x2 0x0
+#define MX6DL_PAD_EIM_A16__GPIO2_IO22              0x110 0x4e0 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_A16__SRC_BOOT_CFG16          0x110 0x4e0 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_A16__EPDC_DATA00             0x110 0x4e0 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_A17__EIM_ADDR17              0x114 0x4e4 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_A17__IPU1_DISP1_DATA12       0x114 0x4e4 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_A17__IPU1_CSI1_DATA12        0x114 0x4e4 0x890 0x2 0x0
+#define MX6DL_PAD_EIM_A17__GPIO2_IO21              0x114 0x4e4 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_A17__SRC_BOOT_CFG17          0x114 0x4e4 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_A17__EPDC_PWR_STAT           0x114 0x4e4 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_A18__EIM_ADDR18              0x118 0x4e8 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_A18__IPU1_DISP1_DATA13       0x118 0x4e8 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_A18__IPU1_CSI1_DATA13        0x118 0x4e8 0x894 0x2 0x0
+#define MX6DL_PAD_EIM_A18__GPIO2_IO20              0x118 0x4e8 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_A18__SRC_BOOT_CFG18          0x118 0x4e8 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_A18__EPDC_PWR_CTRL0          0x118 0x4e8 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_A19__EIM_ADDR19              0x11c 0x4ec 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_A19__IPU1_DISP1_DATA14       0x11c 0x4ec 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_A19__IPU1_CSI1_DATA14        0x11c 0x4ec 0x898 0x2 0x0
+#define MX6DL_PAD_EIM_A19__GPIO2_IO19              0x11c 0x4ec 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_A19__SRC_BOOT_CFG19          0x11c 0x4ec 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_A19__EPDC_PWR_CTRL1          0x11c 0x4ec 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_A20__EIM_ADDR20              0x120 0x4f0 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_A20__IPU1_DISP1_DATA15       0x120 0x4f0 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_A20__IPU1_CSI1_DATA15        0x120 0x4f0 0x89c 0x2 0x0
+#define MX6DL_PAD_EIM_A20__GPIO2_IO18              0x120 0x4f0 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_A20__SRC_BOOT_CFG20          0x120 0x4f0 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_A20__EPDC_PWR_CTRL2          0x120 0x4f0 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_A21__EIM_ADDR21              0x124 0x4f4 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_A21__IPU1_DISP1_DATA16       0x124 0x4f4 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_A21__IPU1_CSI1_DATA16        0x124 0x4f4 0x8a0 0x2 0x0
+#define MX6DL_PAD_EIM_A21__GPIO2_IO17              0x124 0x4f4 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_A21__SRC_BOOT_CFG21          0x124 0x4f4 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_A21__EPDC_GDCLK              0x124 0x4f4 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_A22__EIM_ADDR22              0x128 0x4f8 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_A22__IPU1_DISP1_DATA17       0x128 0x4f8 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_A22__IPU1_CSI1_DATA17        0x128 0x4f8 0x8a4 0x2 0x0
+#define MX6DL_PAD_EIM_A22__GPIO2_IO16              0x128 0x4f8 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_A22__SRC_BOOT_CFG22          0x128 0x4f8 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_A22__EPDC_GDSP               0x128 0x4f8 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_A23__EIM_ADDR23              0x12c 0x4fc 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_A23__IPU1_DISP1_DATA18       0x12c 0x4fc 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_A23__IPU1_CSI1_DATA18        0x12c 0x4fc 0x8a8 0x2 0x0
+#define MX6DL_PAD_EIM_A23__IPU1_SISG3              0x12c 0x4fc 0x000 0x4 0x0
+#define MX6DL_PAD_EIM_A23__GPIO6_IO06              0x12c 0x4fc 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_A23__SRC_BOOT_CFG23          0x12c 0x4fc 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_A23__EPDC_GDOE               0x12c 0x4fc 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_A24__EIM_ADDR24              0x130 0x500 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_A24__IPU1_DISP1_DATA19       0x130 0x500 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_A24__IPU1_CSI1_DATA19        0x130 0x500 0x8ac 0x2 0x0
+#define MX6DL_PAD_EIM_A24__IPU1_SISG2              0x130 0x500 0x000 0x4 0x0
+#define MX6DL_PAD_EIM_A24__GPIO5_IO04              0x130 0x500 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_A24__SRC_BOOT_CFG24          0x130 0x500 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_A24__EPDC_GDRL               0x130 0x500 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_A25__EIM_ADDR25              0x134 0x504 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_A25__ECSPI4_SS1              0x134 0x504 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_A25__ECSPI2_RDY              0x134 0x504 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_A25__IPU1_DI1_PIN12          0x134 0x504 0x000 0x3 0x0
+#define MX6DL_PAD_EIM_A25__IPU1_DI0_D1_CS          0x134 0x504 0x000 0x4 0x0
+#define MX6DL_PAD_EIM_A25__GPIO5_IO02              0x134 0x504 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_A25__HDMI_TX_CEC_LINE        0x134 0x504 0x85c 0x6 0x0
+#define MX6DL_PAD_EIM_A25__EPDC_DATA15             0x134 0x504 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_A25__EIM_ACLK_FREERUN        0x134 0x504 0x000 0x9 0x0
+#define MX6DL_PAD_EIM_BCLK__EIM_BCLK               0x138 0x508 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_BCLK__IPU1_DI1_PIN16         0x138 0x508 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_BCLK__GPIO6_IO31             0x138 0x508 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_BCLK__EPDC_SDCE9             0x138 0x508 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_CS0__EIM_CS0_B               0x13c 0x50c 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_CS0__IPU1_DI1_PIN05          0x13c 0x50c 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_CS0__ECSPI2_SCLK             0x13c 0x50c 0x7f4 0x2 0x2
+#define MX6DL_PAD_EIM_CS0__GPIO2_IO23              0x13c 0x50c 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_CS0__EPDC_DATA06             0x13c 0x50c 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_CS1__EIM_CS1_B               0x140 0x510 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_CS1__IPU1_DI1_PIN06          0x140 0x510 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_CS1__ECSPI2_MOSI             0x140 0x510 0x7fc 0x2 0x2
+#define MX6DL_PAD_EIM_CS1__GPIO2_IO24              0x140 0x510 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_CS1__EPDC_DATA08             0x140 0x510 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_D16__EIM_DATA16              0x144 0x514 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_D16__ECSPI1_SCLK             0x144 0x514 0x7d8 0x1 0x2
+#define MX6DL_PAD_EIM_D16__IPU1_DI0_PIN05          0x144 0x514 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_D16__IPU1_CSI1_DATA18        0x144 0x514 0x8a8 0x3 0x1
+#define MX6DL_PAD_EIM_D16__HDMI_TX_DDC_SDA         0x144 0x514 0x864 0x4 0x0
+#define MX6DL_PAD_EIM_D16__GPIO3_IO16              0x144 0x514 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_D16__I2C2_SDA                0x144 0x514 0x874 0x6 0x0
+#define MX6DL_PAD_EIM_D16__EPDC_DATA10             0x144 0x514 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_D17__EIM_DATA17              0x148 0x518 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_D17__ECSPI1_MISO             0x148 0x518 0x7dc 0x1 0x2
+#define MX6DL_PAD_EIM_D17__IPU1_DI0_PIN06          0x148 0x518 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_D17__IPU1_CSI1_PIXCLK        0x148 0x518 0x8b8 0x3 0x1
+#define MX6DL_PAD_EIM_D17__DCIC1_OUT               0x148 0x518 0x000 0x4 0x0
+#define MX6DL_PAD_EIM_D17__GPIO3_IO17              0x148 0x518 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_D17__I2C3_SCL                0x148 0x518 0x878 0x6 0x0
+#define MX6DL_PAD_EIM_D17__EPDC_VCOM0              0x148 0x518 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_D18__EIM_DATA18              0x14c 0x51c 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_D18__ECSPI1_MOSI             0x14c 0x51c 0x7e0 0x1 0x2
+#define MX6DL_PAD_EIM_D18__IPU1_DI0_PIN07          0x14c 0x51c 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_D18__IPU1_CSI1_DATA17        0x14c 0x51c 0x8a4 0x3 0x1
+#define MX6DL_PAD_EIM_D18__IPU1_DI1_D0_CS          0x14c 0x51c 0x000 0x4 0x0
+#define MX6DL_PAD_EIM_D18__GPIO3_IO18              0x14c 0x51c 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_D18__I2C3_SDA                0x14c 0x51c 0x87c 0x6 0x0
+#define MX6DL_PAD_EIM_D18__EPDC_VCOM1              0x14c 0x51c 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_D19__EIM_DATA19              0x150 0x520 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_D19__ECSPI1_SS1              0x150 0x520 0x7e8 0x1 0x1
+#define MX6DL_PAD_EIM_D19__IPU1_DI0_PIN08          0x150 0x520 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_D19__IPU1_CSI1_DATA16        0x150 0x520 0x8a0 0x3 0x1
+#define MX6DL_PAD_EIM_D19__UART1_CTS_B             0x150 0x520 0x000 0x4 0x0
+#define MX6DL_PAD_EIM_D19__UART1_RTS_B             0x150 0x520 0x8f8 0x4 0x0
+#define MX6DL_PAD_EIM_D19__GPIO3_IO19              0x150 0x520 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_D19__EPIT1_OUT               0x150 0x520 0x000 0x6 0x0
+#define MX6DL_PAD_EIM_D19__EPDC_DATA12             0x150 0x520 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_D20__EIM_DATA20              0x154 0x524 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_D20__ECSPI4_SS0              0x154 0x524 0x808 0x1 0x0
+#define MX6DL_PAD_EIM_D20__IPU1_DI0_PIN16          0x154 0x524 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_D20__IPU1_CSI1_DATA15        0x154 0x524 0x89c 0x3 0x1
+#define MX6DL_PAD_EIM_D20__UART1_RTS_B             0x154 0x524 0x8f8 0x4 0x1
+#define MX6DL_PAD_EIM_D20__UART1_CTS_B             0x154 0x524 0x000 0x4 0x0
+#define MX6DL_PAD_EIM_D20__GPIO3_IO20              0x154 0x524 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_D20__EPIT2_OUT               0x154 0x524 0x000 0x6 0x0
+#define MX6DL_PAD_EIM_D21__EIM_DATA21              0x158 0x528 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_D21__ECSPI4_SCLK             0x158 0x528 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_D21__IPU1_DI0_PIN17          0x158 0x528 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_D21__IPU1_CSI1_DATA11        0x158 0x528 0x88c 0x3 0x0
+#define MX6DL_PAD_EIM_D21__USB_OTG_OC              0x158 0x528 0x920 0x4 0x0
+#define MX6DL_PAD_EIM_D21__GPIO3_IO21              0x158 0x528 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_D21__I2C1_SCL                0x158 0x528 0x868 0x6 0x1
+#define MX6DL_PAD_EIM_D21__SPDIF_IN                0x158 0x528 0x8f0 0x7 0x0
+#define MX6DL_PAD_EIM_D22__EIM_DATA22              0x15c 0x52c 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_D22__ECSPI4_MISO             0x15c 0x52c 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_D22__IPU1_DI0_PIN01          0x15c 0x52c 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_D22__IPU1_CSI1_DATA10        0x15c 0x52c 0x888 0x3 0x0
+#define MX6DL_PAD_EIM_D22__USB_OTG_PWR             0x15c 0x52c 0x000 0x4 0x0
+#define MX6DL_PAD_EIM_D22__GPIO3_IO22              0x15c 0x52c 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_D22__SPDIF_OUT               0x15c 0x52c 0x000 0x6 0x0
+#define MX6DL_PAD_EIM_D22__EPDC_SDCE6              0x15c 0x52c 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_D23__EIM_DATA23              0x160 0x530 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_D23__IPU1_DI0_D0_CS          0x160 0x530 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_D23__UART3_CTS_B             0x160 0x530 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_D23__UART3_RTS_B             0x160 0x530 0x908 0x2 0x0
+#define MX6DL_PAD_EIM_D23__UART1_DCD_B             0x160 0x530 0x000 0x3 0x0
+#define MX6DL_PAD_EIM_D23__IPU1_CSI1_DATA_EN       0x160 0x530 0x8b0 0x4 0x0
+#define MX6DL_PAD_EIM_D23__GPIO3_IO23              0x160 0x530 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN02          0x160 0x530 0x000 0x6 0x0
+#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN14          0x160 0x530 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_D23__EPDC_DATA11             0x160 0x530 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_D24__EIM_DATA24              0x164 0x534 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_D24__ECSPI4_SS2              0x164 0x534 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_D24__UART3_TX_DATA           0x164 0x534 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_D24__UART3_RX_DATA           0x164 0x534 0x90c 0x2 0x0
+#define MX6DL_PAD_EIM_D24__ECSPI1_SS2              0x164 0x534 0x7ec 0x3 0x0
+#define MX6DL_PAD_EIM_D24__ECSPI2_SS2              0x164 0x534 0x000 0x4 0x0
+#define MX6DL_PAD_EIM_D24__GPIO3_IO24              0x164 0x534 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_D24__AUD5_RXFS               0x164 0x534 0x7bc 0x6 0x1
+#define MX6DL_PAD_EIM_D24__UART1_DTR_B             0x164 0x534 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_D24__EPDC_SDCE7              0x164 0x534 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_D25__EIM_DATA25              0x168 0x538 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_D25__ECSPI4_SS3              0x168 0x538 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_D25__UART3_RX_DATA           0x168 0x538 0x90c 0x2 0x1
+#define MX6DL_PAD_EIM_D25__UART3_TX_DATA           0x168 0x538 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_D25__ECSPI1_SS3              0x168 0x538 0x7f0 0x3 0x0
+#define MX6DL_PAD_EIM_D25__ECSPI2_SS3              0x168 0x538 0x000 0x4 0x0
+#define MX6DL_PAD_EIM_D25__GPIO3_IO25              0x168 0x538 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_D25__AUD5_RXC                0x168 0x538 0x7b8 0x6 0x1
+#define MX6DL_PAD_EIM_D25__UART1_DSR_B             0x168 0x538 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_D25__EPDC_SDCE8              0x168 0x538 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_D26__EIM_DATA26              0x16c 0x53c 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_D26__IPU1_DI1_PIN11          0x16c 0x53c 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_D26__IPU1_CSI0_DATA01        0x16c 0x53c 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_D26__IPU1_CSI1_DATA14        0x16c 0x53c 0x898 0x3 0x1
+#define MX6DL_PAD_EIM_D26__UART2_TX_DATA           0x16c 0x53c 0x000 0x4 0x0
+#define MX6DL_PAD_EIM_D26__UART2_RX_DATA           0x16c 0x53c 0x904 0x4 0x0
+#define MX6DL_PAD_EIM_D26__GPIO3_IO26              0x16c 0x53c 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_D26__IPU1_SISG2              0x16c 0x53c 0x000 0x6 0x0
+#define MX6DL_PAD_EIM_D26__IPU1_DISP1_DATA22       0x16c 0x53c 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_D26__EPDC_SDOED              0x16c 0x53c 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_D27__EIM_DATA27              0x170 0x540 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_D27__IPU1_DI1_PIN13          0x170 0x540 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_D27__IPU1_CSI0_DATA00        0x170 0x540 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_D27__IPU1_CSI1_DATA13        0x170 0x540 0x894 0x3 0x1
+#define MX6DL_PAD_EIM_D27__UART2_RX_DATA           0x170 0x540 0x904 0x4 0x1
+#define MX6DL_PAD_EIM_D27__UART2_TX_DATA           0x170 0x540 0x000 0x4 0x0
+#define MX6DL_PAD_EIM_D27__GPIO3_IO27              0x170 0x540 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_D27__IPU1_SISG3              0x170 0x540 0x000 0x6 0x0
+#define MX6DL_PAD_EIM_D27__IPU1_DISP1_DATA23       0x170 0x540 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_D27__EPDC_SDOE               0x170 0x540 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_D28__EIM_DATA28              0x174 0x544 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_D28__I2C1_SDA                0x174 0x544 0x86c 0x1 0x1
+#define MX6DL_PAD_EIM_D28__ECSPI4_MOSI             0x174 0x544 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_D28__IPU1_CSI1_DATA12        0x174 0x544 0x890 0x3 0x1
+#define MX6DL_PAD_EIM_D28__UART2_CTS_B             0x174 0x544 0x000 0x4 0x0
+#define MX6DL_PAD_EIM_D28__UART2_RTS_B             0x174 0x544 0x900 0x4 0x0
+#define MX6DL_PAD_EIM_D28__GPIO3_IO28              0x174 0x544 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_D28__IPU1_EXT_TRIG           0x174 0x544 0x000 0x6 0x0
+#define MX6DL_PAD_EIM_D28__IPU1_DI0_PIN13          0x174 0x544 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_D28__EPDC_PWR_CTRL3          0x174 0x544 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_D29__EIM_DATA29              0x178 0x548 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_D29__IPU1_DI1_PIN15          0x178 0x548 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_D29__ECSPI4_SS0              0x178 0x548 0x808 0x2 0x1
+#define MX6DL_PAD_EIM_D29__UART2_RTS_B             0x178 0x548 0x900 0x4 0x1
+#define MX6DL_PAD_EIM_D29__UART2_CTS_B             0x178 0x548 0x000 0x4 0x0
+#define MX6DL_PAD_EIM_D29__GPIO3_IO29              0x178 0x548 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_D29__IPU1_CSI1_VSYNC         0x178 0x548 0x8bc 0x6 0x0
+#define MX6DL_PAD_EIM_D29__IPU1_DI0_PIN14          0x178 0x548 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_D29__EPDC_PWR_WAKE           0x178 0x548 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_D30__EIM_DATA30              0x17c 0x54c 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_D30__IPU1_DISP1_DATA21       0x17c 0x54c 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_D30__IPU1_DI0_PIN11          0x17c 0x54c 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_D30__IPU1_CSI0_DATA03        0x17c 0x54c 0x000 0x3 0x0
+#define MX6DL_PAD_EIM_D30__UART3_CTS_B             0x17c 0x54c 0x000 0x4 0x0
+#define MX6DL_PAD_EIM_D30__UART3_RTS_B             0x17c 0x54c 0x908 0x4 0x1
+#define MX6DL_PAD_EIM_D30__GPIO3_IO30              0x17c 0x54c 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_D30__USB_H1_OC               0x17c 0x54c 0x924 0x6 0x0
+#define MX6DL_PAD_EIM_D30__EPDC_SDOEZ              0x17c 0x54c 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_D31__EIM_DATA31              0x180 0x550 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_D31__IPU1_DISP1_DATA20       0x180 0x550 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_D31__IPU1_DI0_PIN12          0x180 0x550 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_D31__IPU1_CSI0_DATA02        0x180 0x550 0x000 0x3 0x0
+#define MX6DL_PAD_EIM_D31__UART3_RTS_B             0x180 0x550 0x908 0x4 0x2
+#define MX6DL_PAD_EIM_D31__UART3_CTS_B             0x180 0x550 0x000 0x4 0x0
+#define MX6DL_PAD_EIM_D31__GPIO3_IO31              0x180 0x550 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_D31__USB_H1_PWR              0x180 0x550 0x000 0x6 0x0
+#define MX6DL_PAD_EIM_D31__EPDC_SDCLK_P            0x180 0x550 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_D31__EIM_ACLK_FREERUN        0x180 0x550 0x000 0x9 0x0
+#define MX6DL_PAD_EIM_DA0__EIM_AD00                0x184 0x554 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_DA0__IPU1_DISP1_DATA09       0x184 0x554 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_DA0__IPU1_CSI1_DATA09        0x184 0x554 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_DA0__GPIO3_IO00              0x184 0x554 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_DA0__SRC_BOOT_CFG00          0x184 0x554 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_DA0__EPDC_SDCLK_N            0x184 0x554 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_DA1__EIM_AD01                0x188 0x558 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_DA1__IPU1_DISP1_DATA08       0x188 0x558 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_DA1__IPU1_CSI1_DATA08        0x188 0x558 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_DA1__GPIO3_IO01              0x188 0x558 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_DA1__SRC_BOOT_CFG01          0x188 0x558 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_DA1__EPDC_SDLE               0x188 0x558 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_DA10__EIM_AD10               0x18c 0x55c 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_DA10__IPU1_DI1_PIN15         0x18c 0x55c 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN      0x18c 0x55c 0x8b0 0x2 0x1
+#define MX6DL_PAD_EIM_DA10__GPIO3_IO10             0x18c 0x55c 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_DA10__SRC_BOOT_CFG10         0x18c 0x55c 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_DA10__EPDC_DATA01            0x18c 0x55c 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_DA11__EIM_AD11               0x190 0x560 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_DA11__IPU1_DI1_PIN02         0x190 0x560 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_DA11__IPU1_CSI1_HSYNC        0x190 0x560 0x8b4 0x2 0x0
+#define MX6DL_PAD_EIM_DA11__GPIO3_IO11             0x190 0x560 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_DA11__SRC_BOOT_CFG11         0x190 0x560 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_DA11__EPDC_DATA03            0x190 0x560 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_DA12__EIM_AD12               0x194 0x564 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_DA12__IPU1_DI1_PIN03         0x194 0x564 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_DA12__IPU1_CSI1_VSYNC        0x194 0x564 0x8bc 0x2 0x1
+#define MX6DL_PAD_EIM_DA12__GPIO3_IO12             0x194 0x564 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_DA12__SRC_BOOT_CFG12         0x194 0x564 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_DA12__EPDC_DATA02            0x194 0x564 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_DA13__EIM_AD13               0x198 0x568 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_DA13__IPU1_DI1_D0_CS         0x198 0x568 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_DA13__GPIO3_IO13             0x198 0x568 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_DA13__SRC_BOOT_CFG13         0x198 0x568 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_DA13__EPDC_DATA13            0x198 0x568 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_DA14__EIM_AD14               0x19c 0x56c 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_DA14__IPU1_DI1_D1_CS         0x19c 0x56c 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_DA14__GPIO3_IO14             0x19c 0x56c 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_DA14__SRC_BOOT_CFG14         0x19c 0x56c 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_DA14__EPDC_DATA14            0x19c 0x56c 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_DA15__EIM_AD15               0x1a0 0x570 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN01         0x1a0 0x570 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN04         0x1a0 0x570 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_DA15__GPIO3_IO15             0x1a0 0x570 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_DA15__SRC_BOOT_CFG15         0x1a0 0x570 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_DA15__EPDC_DATA09            0x1a0 0x570 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_DA2__EIM_AD02                0x1a4 0x574 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_DA2__IPU1_DISP1_DATA07       0x1a4 0x574 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_DA2__IPU1_CSI1_DATA07        0x1a4 0x574 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_DA2__GPIO3_IO02              0x1a4 0x574 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_DA2__SRC_BOOT_CFG02          0x1a4 0x574 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_DA2__EPDC_BDR0               0x1a4 0x574 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_DA3__EIM_AD03                0x1a8 0x578 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_DA3__IPU1_DISP1_DATA06       0x1a8 0x578 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_DA3__IPU1_CSI1_DATA06        0x1a8 0x578 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_DA3__GPIO3_IO03              0x1a8 0x578 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_DA3__SRC_BOOT_CFG03          0x1a8 0x578 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_DA3__EPDC_BDR1               0x1a8 0x578 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_DA4__EIM_AD04                0x1ac 0x57c 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_DA4__IPU1_DISP1_DATA05       0x1ac 0x57c 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_DA4__IPU1_CSI1_DATA05        0x1ac 0x57c 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_DA4__GPIO3_IO04              0x1ac 0x57c 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_DA4__SRC_BOOT_CFG04          0x1ac 0x57c 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_DA4__EPDC_SDCE0              0x1ac 0x57c 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_DA5__EIM_AD05                0x1b0 0x580 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_DA5__IPU1_DISP1_DATA04       0x1b0 0x580 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_DA5__IPU1_CSI1_DATA04        0x1b0 0x580 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_DA5__GPIO3_IO05              0x1b0 0x580 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_DA5__SRC_BOOT_CFG05          0x1b0 0x580 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_DA5__EPDC_SDCE1              0x1b0 0x580 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_DA6__EIM_AD06                0x1b4 0x584 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_DA6__IPU1_DISP1_DATA03       0x1b4 0x584 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_DA6__IPU1_CSI1_DATA03        0x1b4 0x584 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_DA6__GPIO3_IO06              0x1b4 0x584 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_DA6__SRC_BOOT_CFG06          0x1b4 0x584 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_DA6__EPDC_SDCE2              0x1b4 0x584 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_DA7__EIM_AD07                0x1b8 0x588 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_DA7__IPU1_DISP1_DATA02       0x1b8 0x588 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_DA7__IPU1_CSI1_DATA02        0x1b8 0x588 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_DA7__GPIO3_IO07              0x1b8 0x588 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_DA7__SRC_BOOT_CFG07          0x1b8 0x588 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_DA7__EPDC_SDCE3              0x1b8 0x588 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_DA8__EIM_AD08                0x1bc 0x58c 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_DA8__IPU1_DISP1_DATA01       0x1bc 0x58c 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_DA8__IPU1_CSI1_DATA01        0x1bc 0x58c 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_DA8__GPIO3_IO08              0x1bc 0x58c 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_DA8__SRC_BOOT_CFG08          0x1bc 0x58c 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_DA8__EPDC_SDCE4              0x1bc 0x58c 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_DA9__EIM_AD09                0x1c0 0x590 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_DA9__IPU1_DISP1_DATA00       0x1c0 0x590 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_DA9__IPU1_CSI1_DATA00        0x1c0 0x590 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_DA9__GPIO3_IO09              0x1c0 0x590 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_DA9__SRC_BOOT_CFG09          0x1c0 0x590 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_DA9__EPDC_SDCE5              0x1c0 0x590 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_EB0__EIM_EB0_B               0x1c4 0x594 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_EB0__IPU1_DISP1_DATA11       0x1c4 0x594 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_EB0__IPU1_CSI1_DATA11        0x1c4 0x594 0x88c 0x2 0x1
+#define MX6DL_PAD_EIM_EB0__CCM_PMIC_READY          0x1c4 0x594 0x7d4 0x4 0x0
+#define MX6DL_PAD_EIM_EB0__GPIO2_IO28              0x1c4 0x594 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_EB0__SRC_BOOT_CFG27          0x1c4 0x594 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_EB0__EPDC_PWR_COM            0x1c4 0x594 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_EB1__EIM_EB1_B               0x1c8 0x598 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_EB1__IPU1_DISP1_DATA10       0x1c8 0x598 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_EB1__IPU1_CSI1_DATA10        0x1c8 0x598 0x888 0x2 0x1
+#define MX6DL_PAD_EIM_EB1__GPIO2_IO29              0x1c8 0x598 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_EB1__SRC_BOOT_CFG28          0x1c8 0x598 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_EB1__EPDC_SDSHR              0x1c8 0x598 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_EB2__EIM_EB2_B               0x1cc 0x59c 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_EB2__ECSPI1_SS0              0x1cc 0x59c 0x7e4 0x1 0x2
+#define MX6DL_PAD_EIM_EB2__IPU1_CSI1_DATA19        0x1cc 0x59c 0x8ac 0x3 0x1
+#define MX6DL_PAD_EIM_EB2__HDMI_TX_DDC_SCL         0x1cc 0x59c 0x860 0x4 0x0
+#define MX6DL_PAD_EIM_EB2__GPIO2_IO30              0x1cc 0x59c 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_EB2__I2C2_SCL                0x1cc 0x59c 0x870 0x6 0x0
+#define MX6DL_PAD_EIM_EB2__SRC_BOOT_CFG30          0x1cc 0x59c 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_EB2__EPDC_DATA05             0x1cc 0x59c 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_EB3__EIM_EB3_B               0x1d0 0x5a0 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_EB3__ECSPI4_RDY              0x1d0 0x5a0 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_EB3__UART3_RTS_B             0x1d0 0x5a0 0x908 0x2 0x3
+#define MX6DL_PAD_EIM_EB3__UART3_CTS_B             0x1d0 0x5a0 0x000 0x2 0x0
+#define MX6DL_PAD_EIM_EB3__UART1_RI_B              0x1d0 0x5a0 0x000 0x3 0x0
+#define MX6DL_PAD_EIM_EB3__IPU1_CSI1_HSYNC         0x1d0 0x5a0 0x8b4 0x4 0x1
+#define MX6DL_PAD_EIM_EB3__GPIO2_IO31              0x1d0 0x5a0 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_EB3__IPU1_DI1_PIN03          0x1d0 0x5a0 0x000 0x6 0x0
+#define MX6DL_PAD_EIM_EB3__SRC_BOOT_CFG31          0x1d0 0x5a0 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_EB3__EPDC_SDCE0              0x1d0 0x5a0 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_EB3__EIM_ACLK_FREERUN        0x1d0 0x5a0 0x000 0x9 0x0
+#define MX6DL_PAD_EIM_LBA__EIM_LBA_B               0x1d4 0x5a4 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_LBA__IPU1_DI1_PIN17          0x1d4 0x5a4 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_LBA__ECSPI2_SS1              0x1d4 0x5a4 0x804 0x2 0x1
+#define MX6DL_PAD_EIM_LBA__GPIO2_IO27              0x1d4 0x5a4 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_LBA__SRC_BOOT_CFG26          0x1d4 0x5a4 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_LBA__EPDC_DATA04             0x1d4 0x5a4 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_OE__EIM_OE_B                 0x1d8 0x5a8 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_OE__IPU1_DI1_PIN07           0x1d8 0x5a8 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_OE__ECSPI2_MISO              0x1d8 0x5a8 0x7f8 0x2 0x2
+#define MX6DL_PAD_EIM_OE__GPIO2_IO25               0x1d8 0x5a8 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_OE__EPDC_PWR_IRQ             0x1d8 0x5a8 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_RW__EIM_RW                   0x1dc 0x5ac 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_RW__IPU1_DI1_PIN08           0x1dc 0x5ac 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_RW__ECSPI2_SS0               0x1dc 0x5ac 0x800 0x2 0x2
+#define MX6DL_PAD_EIM_RW__GPIO2_IO26               0x1dc 0x5ac 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_RW__SRC_BOOT_CFG29           0x1dc 0x5ac 0x000 0x7 0x0
+#define MX6DL_PAD_EIM_RW__EPDC_DATA07              0x1dc 0x5ac 0x000 0x8 0x0
+#define MX6DL_PAD_EIM_WAIT__EIM_WAIT_B             0x1e0 0x5b0 0x000 0x0 0x0
+#define MX6DL_PAD_EIM_WAIT__EIM_DTACK_B            0x1e0 0x5b0 0x000 0x1 0x0
+#define MX6DL_PAD_EIM_WAIT__GPIO5_IO00             0x1e0 0x5b0 0x000 0x5 0x0
+#define MX6DL_PAD_EIM_WAIT__SRC_BOOT_CFG25         0x1e0 0x5b0 0x000 0x7 0x0
+#define MX6DL_PAD_ENET_CRS_DV__ENET_RX_EN          0x1e4 0x5b4 0x828 0x1 0x0
+#define MX6DL_PAD_ENET_CRS_DV__ESAI_TX_CLK         0x1e4 0x5b4 0x840 0x2 0x0
+#define MX6DL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK       0x1e4 0x5b4 0x8f4 0x3 0x0
+#define MX6DL_PAD_ENET_CRS_DV__GPIO1_IO25          0x1e4 0x5b4 0x000 0x5 0x0
+#define MX6DL_PAD_ENET_MDC__MLB_DATA               0x1e8 0x5b8 0x8e0 0x0 0x0
+#define MX6DL_PAD_ENET_MDC__ENET_MDC               0x1e8 0x5b8 0x000 0x1 0x0
+#define MX6DL_PAD_ENET_MDC__ESAI_TX5_RX0           0x1e8 0x5b8 0x858 0x2 0x0
+#define MX6DL_PAD_ENET_MDC__ENET_1588_EVENT1_IN    0x1e8 0x5b8 0x000 0x4 0x0
+#define MX6DL_PAD_ENET_MDC__GPIO1_IO31             0x1e8 0x5b8 0x000 0x5 0x0
+#define MX6DL_PAD_ENET_MDIO__ENET_MDIO             0x1ec 0x5bc 0x810 0x1 0x0
+#define MX6DL_PAD_ENET_MDIO__ESAI_RX_CLK           0x1ec 0x5bc 0x83c 0x2 0x0
+#define MX6DL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT  0x1ec 0x5bc 0x000 0x4 0x0
+#define MX6DL_PAD_ENET_MDIO__GPIO1_IO22            0x1ec 0x5bc 0x000 0x5 0x0
+#define MX6DL_PAD_ENET_MDIO__SPDIF_LOCK            0x1ec 0x5bc 0x000 0x6 0x0
+#define MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK        0x1f0 0x5c0 0x000 0x1 0x0
+#define MX6DL_PAD_ENET_REF_CLK__ESAI_RX_FS         0x1f0 0x5c0 0x82c 0x2 0x0
+#define MX6DL_PAD_ENET_REF_CLK__GPIO1_IO23         0x1f0 0x5c0 0x000 0x5 0x0
+#define MX6DL_PAD_ENET_REF_CLK__SPDIF_SR_CLK       0x1f0 0x5c0 0x000 0x6 0x0
+#define MX6DL_PAD_ENET_RX_ER__USB_OTG_ID           0x1f4 0x5c4 0x790 0x0 0x0
+#define MX6DL_PAD_ENET_RX_ER__ENET_RX_ER           0x1f4 0x5c4 0x000 0x1 0x0
+#define MX6DL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK       0x1f4 0x5c4 0x834 0x2 0x0
+#define MX6DL_PAD_ENET_RX_ER__SPDIF_IN             0x1f4 0x5c4 0x8f0 0x3 0x1
+#define MX6DL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0
+#define MX6DL_PAD_ENET_RX_ER__GPIO1_IO24           0x1f4 0x5c4 0x000 0x5 0x0
+#define MX6DL_PAD_ENET_RXD0__ENET_RX_DATA0         0x1f8 0x5c8 0x818 0x1 0x0
+#define MX6DL_PAD_ENET_RXD0__ESAI_TX_HF_CLK        0x1f8 0x5c8 0x838 0x2 0x0
+#define MX6DL_PAD_ENET_RXD0__SPDIF_OUT             0x1f8 0x5c8 0x000 0x3 0x0
+#define MX6DL_PAD_ENET_RXD0__GPIO1_IO27            0x1f8 0x5c8 0x000 0x5 0x0
+#define MX6DL_PAD_ENET_RXD1__MLB_SIG               0x1fc 0x5cc 0x8e4 0x0 0x0
+#define MX6DL_PAD_ENET_RXD1__ENET_RX_DATA1         0x1fc 0x5cc 0x81c 0x1 0x0
+#define MX6DL_PAD_ENET_RXD1__ESAI_TX_FS            0x1fc 0x5cc 0x830 0x2 0x0
+#define MX6DL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT  0x1fc 0x5cc 0x000 0x4 0x0
+#define MX6DL_PAD_ENET_RXD1__GPIO1_IO26            0x1fc 0x5cc 0x000 0x5 0x0
+#define MX6DL_PAD_ENET_TX_EN__ENET_TX_EN           0x200 0x5d0 0x000 0x1 0x0
+#define MX6DL_PAD_ENET_TX_EN__ESAI_TX3_RX2         0x200 0x5d0 0x850 0x2 0x0
+#define MX6DL_PAD_ENET_TX_EN__GPIO1_IO28           0x200 0x5d0 0x000 0x5 0x0
+#define MX6DL_PAD_ENET_TX_EN__I2C4_SCL             0x200 0x5d0 0x880 0x9 0x0
+#define MX6DL_PAD_ENET_TXD0__ENET_TX_DATA0         0x204 0x5d4 0x000 0x1 0x0
+#define MX6DL_PAD_ENET_TXD0__ESAI_TX4_RX1          0x204 0x5d4 0x854 0x2 0x0
+#define MX6DL_PAD_ENET_TXD0__GPIO1_IO30            0x204 0x5d4 0x000 0x5 0x0
+#define MX6DL_PAD_ENET_TXD1__MLB_CLK               0x208 0x5d8 0x8dc 0x0 0x0
+#define MX6DL_PAD_ENET_TXD1__ENET_TX_DATA1         0x208 0x5d8 0x000 0x1 0x0
+#define MX6DL_PAD_ENET_TXD1__ESAI_TX2_RX3          0x208 0x5d8 0x84c 0x2 0x0
+#define MX6DL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN   0x208 0x5d8 0x000 0x4 0x0
+#define MX6DL_PAD_ENET_TXD1__GPIO1_IO29            0x208 0x5d8 0x000 0x5 0x0
+#define MX6DL_PAD_ENET_TXD1__I2C4_SDA              0x208 0x5d8 0x884 0x9 0x0
+#define MX6DL_PAD_GPIO_0__CCM_CLKO1                0x20c 0x5dc 0x000 0x0 0x0
+#define MX6DL_PAD_GPIO_0__KEY_COL5                 0x20c 0x5dc 0x8c0 0x2 0x1
+#define MX6DL_PAD_GPIO_0__ASRC_EXT_CLK             0x20c 0x5dc 0x794 0x3 0x0
+#define MX6DL_PAD_GPIO_0__EPIT1_OUT                0x20c 0x5dc 0x000 0x4 0x0
+#define MX6DL_PAD_GPIO_0__GPIO1_IO00               0x20c 0x5dc 0x000 0x5 0x0
+#define MX6DL_PAD_GPIO_0__USB_H1_PWR               0x20c 0x5dc 0x000 0x6 0x0
+#define MX6DL_PAD_GPIO_0__SNVS_VIO_5               0x20c 0x5dc 0x000 0x7 0x0
+#define MX6DL_PAD_GPIO_1__ESAI_RX_CLK              0x210 0x5e0 0x83c 0x0 0x1
+#define MX6DL_PAD_GPIO_1__WDOG2_B                  0x210 0x5e0 0x000 0x1 0x0
+#define MX6DL_PAD_GPIO_1__KEY_ROW5                 0x210 0x5e0 0x8cc 0x2 0x1
+#define MX6DL_PAD_GPIO_1__USB_OTG_ID               0x210 0x5e0 0x790 0x3 0x1
+#define MX6DL_PAD_GPIO_1__PWM2_OUT                 0x210 0x5e0 0x000 0x4 0x0
+#define MX6DL_PAD_GPIO_1__GPIO1_IO01               0x210 0x5e0 0x000 0x5 0x0
+#define MX6DL_PAD_GPIO_1__SD1_CD_B                 0x210 0x5e0 0x000 0x6 0x0
+#define MX6DL_PAD_GPIO_16__ESAI_TX3_RX2            0x214 0x5e4 0x850 0x0 0x1
+#define MX6DL_PAD_GPIO_16__ENET_1588_EVENT2_IN     0x214 0x5e4 0x000 0x1 0x0
+#define MX6DL_PAD_GPIO_16__ENET_REF_CLK            0x214 0x5e4 0x80c 0x2 0x0
+#define MX6DL_PAD_GPIO_16__SD1_LCTL                0x214 0x5e4 0x000 0x3 0x0
+#define MX6DL_PAD_GPIO_16__SPDIF_IN                0x214 0x5e4 0x8f0 0x4 0x2
+#define MX6DL_PAD_GPIO_16__GPIO7_IO11              0x214 0x5e4 0x000 0x5 0x0
+#define MX6DL_PAD_GPIO_16__I2C3_SDA                0x214 0x5e4 0x87c 0x6 0x1
+#define MX6DL_PAD_GPIO_16__JTAG_DE_B               0x214 0x5e4 0x000 0x7 0x0
+#define MX6DL_PAD_GPIO_17__ESAI_TX0                0x218 0x5e8 0x844 0x0 0x0
+#define MX6DL_PAD_GPIO_17__ENET_1588_EVENT3_IN     0x218 0x5e8 0x000 0x1 0x0
+#define MX6DL_PAD_GPIO_17__CCM_PMIC_READY          0x218 0x5e8 0x7d4 0x2 0x1
+#define MX6DL_PAD_GPIO_17__SDMA_EXT_EVENT0         0x218 0x5e8 0x8e8 0x3 0x1
+#define MX6DL_PAD_GPIO_17__SPDIF_OUT               0x218 0x5e8 0x000 0x4 0x0
+#define MX6DL_PAD_GPIO_17__GPIO7_IO12              0x218 0x5e8 0x000 0x5 0x0
+#define MX6DL_PAD_GPIO_18__ESAI_TX1                0x21c 0x5ec 0x848 0x0 0x0
+#define MX6DL_PAD_GPIO_18__ENET_RX_CLK             0x21c 0x5ec 0x814 0x1 0x0
+#define MX6DL_PAD_GPIO_18__SD3_VSELECT             0x21c 0x5ec 0x000 0x2 0x0
+#define MX6DL_PAD_GPIO_18__SDMA_EXT_EVENT1         0x21c 0x5ec 0x8ec 0x3 0x1
+#define MX6DL_PAD_GPIO_18__ASRC_EXT_CLK            0x21c 0x5ec 0x794 0x4 0x1
+#define MX6DL_PAD_GPIO_18__GPIO7_IO13              0x21c 0x5ec 0x000 0x5 0x0
+#define MX6DL_PAD_GPIO_18__SNVS_VIO_5_CTL          0x21c 0x5ec 0x000 0x6 0x0
+#define MX6DL_PAD_GPIO_19__KEY_COL5                0x220 0x5f0 0x8c0 0x0 0x2
+#define MX6DL_PAD_GPIO_19__ENET_1588_EVENT0_OUT    0x220 0x5f0 0x000 0x1 0x0
+#define MX6DL_PAD_GPIO_19__SPDIF_OUT               0x220 0x5f0 0x000 0x2 0x0
+#define MX6DL_PAD_GPIO_19__CCM_CLKO1               0x220 0x5f0 0x000 0x3 0x0
+#define MX6DL_PAD_GPIO_19__ECSPI1_RDY              0x220 0x5f0 0x000 0x4 0x0
+#define MX6DL_PAD_GPIO_19__GPIO4_IO05              0x220 0x5f0 0x000 0x5 0x0
+#define MX6DL_PAD_GPIO_19__ENET_TX_ER              0x220 0x5f0 0x000 0x6 0x0
+#define MX6DL_PAD_GPIO_2__ESAI_TX_FS               0x224 0x5f4 0x830 0x0 0x1
+#define MX6DL_PAD_GPIO_2__KEY_ROW6                 0x224 0x5f4 0x8d0 0x2 0x1
+#define MX6DL_PAD_GPIO_2__GPIO1_IO02               0x224 0x5f4 0x000 0x5 0x0
+#define MX6DL_PAD_GPIO_2__SD2_WP                   0x224 0x5f4 0x000 0x6 0x0
+#define MX6DL_PAD_GPIO_2__MLB_DATA                 0x224 0x5f4 0x8e0 0x7 0x1
+#define MX6DL_PAD_GPIO_3__ESAI_RX_HF_CLK           0x228 0x5f8 0x834 0x0 0x1
+#define MX6DL_PAD_GPIO_3__I2C3_SCL                 0x228 0x5f8 0x878 0x2 0x1
+#define MX6DL_PAD_GPIO_3__XTALOSC_REF_CLK_24M      0x228 0x5f8 0x000 0x3 0x0
+#define MX6DL_PAD_GPIO_3__CCM_CLKO2                0x228 0x5f8 0x000 0x4 0x0
+#define MX6DL_PAD_GPIO_3__GPIO1_IO03               0x228 0x5f8 0x000 0x5 0x0
+#define MX6DL_PAD_GPIO_3__USB_H1_OC                0x228 0x5f8 0x924 0x6 0x1
+#define MX6DL_PAD_GPIO_3__MLB_CLK                  0x228 0x5f8 0x8dc 0x7 0x1
+#define MX6DL_PAD_GPIO_4__ESAI_TX_HF_CLK           0x22c 0x5fc 0x838 0x0 0x1
+#define MX6DL_PAD_GPIO_4__KEY_COL7                 0x22c 0x5fc 0x8c8 0x2 0x1
+#define MX6DL_PAD_GPIO_4__GPIO1_IO04               0x22c 0x5fc 0x000 0x5 0x0
+#define MX6DL_PAD_GPIO_4__SD2_CD_B                 0x22c 0x5fc 0x000 0x6 0x0
+#define MX6DL_PAD_GPIO_5__ESAI_TX2_RX3             0x230 0x600 0x84c 0x0 0x1
+#define MX6DL_PAD_GPIO_5__KEY_ROW7                 0x230 0x600 0x8d4 0x2 0x1
+#define MX6DL_PAD_GPIO_5__CCM_CLKO1                0x230 0x600 0x000 0x3 0x0
+#define MX6DL_PAD_GPIO_5__GPIO1_IO05               0x230 0x600 0x000 0x5 0x0
+#define MX6DL_PAD_GPIO_5__I2C3_SCL                 0x230 0x600 0x878 0x6 0x2
+#define MX6DL_PAD_GPIO_5__ARM_EVENTI               0x230 0x600 0x000 0x7 0x0
+#define MX6DL_PAD_GPIO_6__ESAI_TX_CLK              0x234 0x604 0x840 0x0 0x1
+#define MX6DL_PAD_GPIO_6__I2C3_SDA                 0x234 0x604 0x87c 0x2 0x2
+#define MX6DL_PAD_GPIO_6__GPIO1_IO06               0x234 0x604 0x000 0x5 0x0
+#define MX6DL_PAD_GPIO_6__SD2_LCTL                 0x234 0x604 0x000 0x6 0x0
+#define MX6DL_PAD_GPIO_6__MLB_SIG                  0x234 0x604 0x8e4 0x7 0x1
+#define MX6DL_PAD_GPIO_7__ESAI_TX4_RX1             0x238 0x608 0x854 0x0 0x1
+#define MX6DL_PAD_GPIO_7__EPIT1_OUT                0x238 0x608 0x000 0x2 0x0
+#define MX6DL_PAD_GPIO_7__FLEXCAN1_TX              0x238 0x608 0x000 0x3 0x0
+#define MX6DL_PAD_GPIO_7__UART2_TX_DATA            0x238 0x608 0x000 0x4 0x0
+#define MX6DL_PAD_GPIO_7__UART2_RX_DATA            0x238 0x608 0x904 0x4 0x2
+#define MX6DL_PAD_GPIO_7__GPIO1_IO07               0x238 0x608 0x000 0x5 0x0
+#define MX6DL_PAD_GPIO_7__SPDIF_LOCK               0x238 0x608 0x000 0x6 0x0
+#define MX6DL_PAD_GPIO_7__USB_OTG_HOST_MODE        0x238 0x608 0x000 0x7 0x0
+#define MX6DL_PAD_GPIO_7__I2C4_SCL                 0x238 0x608 0x880 0x8 0x1
+#define MX6DL_PAD_GPIO_8__ESAI_TX5_RX0             0x23c 0x60c 0x858 0x0 0x1
+#define MX6DL_PAD_GPIO_8__XTALOSC_REF_CLK_32K      0x23c 0x60c 0x000 0x1 0x0
+#define MX6DL_PAD_GPIO_8__EPIT2_OUT                0x23c 0x60c 0x000 0x2 0x0
+#define MX6DL_PAD_GPIO_8__FLEXCAN1_RX              0x23c 0x60c 0x7c8 0x3 0x0
+#define MX6DL_PAD_GPIO_8__UART2_RX_DATA            0x23c 0x60c 0x904 0x4 0x3
+#define MX6DL_PAD_GPIO_8__UART2_TX_DATA            0x23c 0x60c 0x000 0x4 0x0
+#define MX6DL_PAD_GPIO_8__GPIO1_IO08               0x23c 0x60c 0x000 0x5 0x0
+#define MX6DL_PAD_GPIO_8__SPDIF_SR_CLK             0x23c 0x60c 0x000 0x6 0x0
+#define MX6DL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE     0x23c 0x60c 0x000 0x7 0x0
+#define MX6DL_PAD_GPIO_8__I2C4_SDA                 0x23c 0x60c 0x884 0x8 0x1
+#define MX6DL_PAD_GPIO_9__ESAI_RX_FS               0x240 0x610 0x82c 0x0 0x1
+#define MX6DL_PAD_GPIO_9__WDOG1_B                  0x240 0x610 0x000 0x1 0x0
+#define MX6DL_PAD_GPIO_9__KEY_COL6                 0x240 0x610 0x8c4 0x2 0x1
+#define MX6DL_PAD_GPIO_9__CCM_REF_EN_B             0x240 0x610 0x000 0x3 0x0
+#define MX6DL_PAD_GPIO_9__PWM1_OUT                 0x240 0x610 0x000 0x4 0x0
+#define MX6DL_PAD_GPIO_9__GPIO1_IO09               0x240 0x610 0x000 0x5 0x0
+#define MX6DL_PAD_GPIO_9__SD1_WP                   0x240 0x610 0x92c 0x6 0x1
+#define MX6DL_PAD_KEY_COL0__ECSPI1_SCLK            0x244 0x62c 0x7d8 0x0 0x3
+#define MX6DL_PAD_KEY_COL0__ENET_RX_DATA3          0x244 0x62c 0x824 0x1 0x0
+#define MX6DL_PAD_KEY_COL0__AUD5_TXC               0x244 0x62c 0x7c0 0x2 0x1
+#define MX6DL_PAD_KEY_COL0__KEY_COL0               0x244 0x62c 0x000 0x3 0x0
+#define MX6DL_PAD_KEY_COL0__UART4_TX_DATA          0x244 0x62c 0x000 0x4 0x0
+#define MX6DL_PAD_KEY_COL0__UART4_RX_DATA          0x244 0x62c 0x914 0x4 0x2
+#define MX6DL_PAD_KEY_COL0__GPIO4_IO06             0x244 0x62c 0x000 0x5 0x0
+#define MX6DL_PAD_KEY_COL0__DCIC1_OUT              0x244 0x62c 0x000 0x6 0x0
+#define MX6DL_PAD_KEY_COL1__ECSPI1_MISO            0x248 0x630 0x7dc 0x0 0x3
+#define MX6DL_PAD_KEY_COL1__ENET_MDIO              0x248 0x630 0x810 0x1 0x1
+#define MX6DL_PAD_KEY_COL1__AUD5_TXFS              0x248 0x630 0x7c4 0x2 0x1
+#define MX6DL_PAD_KEY_COL1__KEY_COL1               0x248 0x630 0x000 0x3 0x0
+#define MX6DL_PAD_KEY_COL1__UART5_TX_DATA          0x248 0x630 0x000 0x4 0x0
+#define MX6DL_PAD_KEY_COL1__UART5_RX_DATA          0x248 0x630 0x91c 0x4 0x2
+#define MX6DL_PAD_KEY_COL1__GPIO4_IO08             0x248 0x630 0x000 0x5 0x0
+#define MX6DL_PAD_KEY_COL1__SD1_VSELECT            0x248 0x630 0x000 0x6 0x0
+#define MX6DL_PAD_KEY_COL2__ECSPI1_SS1             0x24c 0x634 0x7e8 0x0 0x2
+#define MX6DL_PAD_KEY_COL2__ENET_RX_DATA2          0x24c 0x634 0x820 0x1 0x0
+#define MX6DL_PAD_KEY_COL2__FLEXCAN1_TX            0x24c 0x634 0x000 0x2 0x0
+#define MX6DL_PAD_KEY_COL2__KEY_COL2               0x24c 0x634 0x000 0x3 0x0
+#define MX6DL_PAD_KEY_COL2__ENET_MDC               0x24c 0x634 0x000 0x4 0x0
+#define MX6DL_PAD_KEY_COL2__GPIO4_IO10             0x24c 0x634 0x000 0x5 0x0
+#define MX6DL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE    0x24c 0x634 0x000 0x6 0x0
+#define MX6DL_PAD_KEY_COL3__ECSPI1_SS3             0x250 0x638 0x7f0 0x0 0x1
+#define MX6DL_PAD_KEY_COL3__ENET_CRS               0x250 0x638 0x000 0x1 0x0
+#define MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL        0x250 0x638 0x860 0x2 0x1
+#define MX6DL_PAD_KEY_COL3__KEY_COL3               0x250 0x638 0x000 0x3 0x0
+#define MX6DL_PAD_KEY_COL3__I2C2_SCL               0x250 0x638 0x870 0x4 0x1
+#define MX6DL_PAD_KEY_COL3__GPIO4_IO12             0x250 0x638 0x000 0x5 0x0
+#define MX6DL_PAD_KEY_COL3__SPDIF_IN               0x250 0x638 0x8f0 0x6 0x3
+#define MX6DL_PAD_KEY_COL4__FLEXCAN2_TX            0x254 0x63c 0x000 0x0 0x0
+#define MX6DL_PAD_KEY_COL4__IPU1_SISG4             0x254 0x63c 0x000 0x1 0x0
+#define MX6DL_PAD_KEY_COL4__USB_OTG_OC             0x254 0x63c 0x920 0x2 0x1
+#define MX6DL_PAD_KEY_COL4__KEY_COL4               0x254 0x63c 0x000 0x3 0x0
+#define MX6DL_PAD_KEY_COL4__UART5_RTS_B            0x254 0x63c 0x918 0x4 0x2
+#define MX6DL_PAD_KEY_COL4__UART5_CTS_B            0x254 0x63c 0x000 0x4 0x0
+#define MX6DL_PAD_KEY_COL4__GPIO4_IO14             0x254 0x63c 0x000 0x5 0x0
+#define MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI            0x258 0x640 0x7e0 0x0 0x3
+#define MX6DL_PAD_KEY_ROW0__ENET_TX_DATA3          0x258 0x640 0x000 0x1 0x0
+#define MX6DL_PAD_KEY_ROW0__AUD5_TXD               0x258 0x640 0x7b4 0x2 0x1
+#define MX6DL_PAD_KEY_ROW0__KEY_ROW0               0x258 0x640 0x000 0x3 0x0
+#define MX6DL_PAD_KEY_ROW0__UART4_RX_DATA          0x258 0x640 0x914 0x4 0x3
+#define MX6DL_PAD_KEY_ROW0__UART4_TX_DATA          0x258 0x640 0x000 0x4 0x0
+#define MX6DL_PAD_KEY_ROW0__GPIO4_IO07             0x258 0x640 0x000 0x5 0x0
+#define MX6DL_PAD_KEY_ROW0__DCIC2_OUT              0x258 0x640 0x000 0x6 0x0
+#define MX6DL_PAD_KEY_ROW1__ECSPI1_SS0             0x25c 0x644 0x7e4 0x0 0x3
+#define MX6DL_PAD_KEY_ROW1__ENET_COL               0x25c 0x644 0x000 0x1 0x0
+#define MX6DL_PAD_KEY_ROW1__AUD5_RXD               0x25c 0x644 0x7b0 0x2 0x1
+#define MX6DL_PAD_KEY_ROW1__KEY_ROW1               0x25c 0x644 0x000 0x3 0x0
+#define MX6DL_PAD_KEY_ROW1__UART5_RX_DATA          0x25c 0x644 0x91c 0x4 0x3
+#define MX6DL_PAD_KEY_ROW1__UART5_TX_DATA          0x25c 0x644 0x000 0x4 0x0
+#define MX6DL_PAD_KEY_ROW1__GPIO4_IO09             0x25c 0x644 0x000 0x5 0x0
+#define MX6DL_PAD_KEY_ROW1__SD2_VSELECT            0x25c 0x644 0x000 0x6 0x0
+#define MX6DL_PAD_KEY_ROW2__ECSPI1_SS2             0x260 0x648 0x7ec 0x0 0x1
+#define MX6DL_PAD_KEY_ROW2__ENET_TX_DATA2          0x260 0x648 0x000 0x1 0x0
+#define MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX            0x260 0x648 0x7c8 0x2 0x1
+#define MX6DL_PAD_KEY_ROW2__KEY_ROW2               0x260 0x648 0x000 0x3 0x0
+#define MX6DL_PAD_KEY_ROW2__SD2_VSELECT            0x260 0x648 0x000 0x4 0x0
+#define MX6DL_PAD_KEY_ROW2__GPIO4_IO11             0x260 0x648 0x000 0x5 0x0
+#define MX6DL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE       0x260 0x648 0x85c 0x6 0x1
+#define MX6DL_PAD_KEY_ROW3__ASRC_EXT_CLK           0x264 0x64c 0x794 0x1 0x2
+#define MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA        0x264 0x64c 0x864 0x2 0x1
+#define MX6DL_PAD_KEY_ROW3__KEY_ROW3               0x264 0x64c 0x000 0x3 0x0
+#define MX6DL_PAD_KEY_ROW3__I2C2_SDA               0x264 0x64c 0x874 0x4 0x1
+#define MX6DL_PAD_KEY_ROW3__GPIO4_IO13             0x264 0x64c 0x000 0x5 0x0
+#define MX6DL_PAD_KEY_ROW3__SD1_VSELECT            0x264 0x64c 0x000 0x6 0x0
+#define MX6DL_PAD_KEY_ROW4__FLEXCAN2_RX            0x268 0x650 0x7cc 0x0 0x0
+#define MX6DL_PAD_KEY_ROW4__IPU1_SISG5             0x268 0x650 0x000 0x1 0x0
+#define MX6DL_PAD_KEY_ROW4__USB_OTG_PWR            0x268 0x650 0x000 0x2 0x0
+#define MX6DL_PAD_KEY_ROW4__KEY_ROW4               0x268 0x650 0x000 0x3 0x0
+#define MX6DL_PAD_KEY_ROW4__UART5_CTS_B            0x268 0x650 0x000 0x4 0x0
+#define MX6DL_PAD_KEY_ROW4__UART5_RTS_B            0x268 0x650 0x918 0x4 0x3
+#define MX6DL_PAD_KEY_ROW4__GPIO4_IO15             0x268 0x650 0x000 0x5 0x0
+#define MX6DL_PAD_NANDF_ALE__NAND_ALE              0x26c 0x654 0x000 0x0 0x0
+#define MX6DL_PAD_NANDF_ALE__SD4_RESET             0x26c 0x654 0x000 0x1 0x0
+#define MX6DL_PAD_NANDF_ALE__GPIO6_IO08            0x26c 0x654 0x000 0x5 0x0
+#define MX6DL_PAD_NANDF_CLE__NAND_CLE              0x270 0x658 0x000 0x0 0x0
+#define MX6DL_PAD_NANDF_CLE__GPIO6_IO07            0x270 0x658 0x000 0x5 0x0
+#define MX6DL_PAD_NANDF_CS0__NAND_CE0_B            0x274 0x65c 0x000 0x0 0x0
+#define MX6DL_PAD_NANDF_CS0__GPIO6_IO11            0x274 0x65c 0x000 0x5 0x0
+#define MX6DL_PAD_NANDF_CS1__NAND_CE1_B            0x278 0x660 0x000 0x0 0x0
+#define MX6DL_PAD_NANDF_CS1__SD4_VSELECT           0x278 0x660 0x000 0x1 0x0
+#define MX6DL_PAD_NANDF_CS1__SD3_VSELECT           0x278 0x660 0x000 0x2 0x0
+#define MX6DL_PAD_NANDF_CS1__GPIO6_IO14            0x278 0x660 0x000 0x5 0x0
+#define MX6DL_PAD_NANDF_CS2__NAND_CE2_B            0x27c 0x664 0x000 0x0 0x0
+#define MX6DL_PAD_NANDF_CS2__IPU1_SISG0            0x27c 0x664 0x000 0x1 0x0
+#define MX6DL_PAD_NANDF_CS2__ESAI_TX0              0x27c 0x664 0x844 0x2 0x1
+#define MX6DL_PAD_NANDF_CS2__EIM_CRE               0x27c 0x664 0x000 0x3 0x0
+#define MX6DL_PAD_NANDF_CS2__CCM_CLKO2             0x27c 0x664 0x000 0x4 0x0
+#define MX6DL_PAD_NANDF_CS2__GPIO6_IO15            0x27c 0x664 0x000 0x5 0x0
+#define MX6DL_PAD_NANDF_CS3__NAND_CE3_B            0x280 0x668 0x000 0x0 0x0
+#define MX6DL_PAD_NANDF_CS3__IPU1_SISG1            0x280 0x668 0x000 0x1 0x0
+#define MX6DL_PAD_NANDF_CS3__ESAI_TX1              0x280 0x668 0x848 0x2 0x1
+#define MX6DL_PAD_NANDF_CS3__EIM_ADDR26            0x280 0x668 0x000 0x3 0x0
+#define MX6DL_PAD_NANDF_CS3__GPIO6_IO16            0x280 0x668 0x000 0x5 0x0
+#define MX6DL_PAD_NANDF_CS3__I2C4_SDA              0x280 0x668 0x884 0x9 0x2
+#define MX6DL_PAD_NANDF_D0__NAND_DATA00            0x284 0x66c 0x000 0x0 0x0
+#define MX6DL_PAD_NANDF_D0__SD1_DATA4              0x284 0x66c 0x000 0x1 0x0
+#define MX6DL_PAD_NANDF_D0__GPIO2_IO00             0x284 0x66c 0x000 0x5 0x0
+#define MX6DL_PAD_NANDF_D1__NAND_DATA01            0x288 0x670 0x000 0x0 0x0
+#define MX6DL_PAD_NANDF_D1__SD1_DATA5              0x288 0x670 0x000 0x1 0x0
+#define MX6DL_PAD_NANDF_D1__GPIO2_IO01             0x288 0x670 0x000 0x5 0x0
+#define MX6DL_PAD_NANDF_D2__NAND_DATA02            0x28c 0x674 0x000 0x0 0x0
+#define MX6DL_PAD_NANDF_D2__SD1_DATA6              0x28c 0x674 0x000 0x1 0x0
+#define MX6DL_PAD_NANDF_D2__GPIO2_IO02             0x28c 0x674 0x000 0x5 0x0
+#define MX6DL_PAD_NANDF_D3__NAND_DATA03            0x290 0x678 0x000 0x0 0x0
+#define MX6DL_PAD_NANDF_D3__SD1_DATA7              0x290 0x678 0x000 0x1 0x0
+#define MX6DL_PAD_NANDF_D3__GPIO2_IO03             0x290 0x678 0x000 0x5 0x0
+#define MX6DL_PAD_NANDF_D4__NAND_DATA04            0x294 0x67c 0x000 0x0 0x0
+#define MX6DL_PAD_NANDF_D4__SD2_DATA4              0x294 0x67c 0x000 0x1 0x0
+#define MX6DL_PAD_NANDF_D4__GPIO2_IO04             0x294 0x67c 0x000 0x5 0x0
+#define MX6DL_PAD_NANDF_D5__NAND_DATA05            0x298 0x680 0x000 0x0 0x0
+#define MX6DL_PAD_NANDF_D5__SD2_DATA5              0x298 0x680 0x000 0x1 0x0
+#define MX6DL_PAD_NANDF_D5__GPIO2_IO05             0x298 0x680 0x000 0x5 0x0
+#define MX6DL_PAD_NANDF_D6__NAND_DATA06            0x29c 0x684 0x000 0x0 0x0
+#define MX6DL_PAD_NANDF_D6__SD2_DATA6              0x29c 0x684 0x000 0x1 0x0
+#define MX6DL_PAD_NANDF_D6__GPIO2_IO06             0x29c 0x684 0x000 0x5 0x0
+#define MX6DL_PAD_NANDF_D7__NAND_DATA07            0x2a0 0x688 0x000 0x0 0x0
+#define MX6DL_PAD_NANDF_D7__SD2_DATA7              0x2a0 0x688 0x000 0x1 0x0
+#define MX6DL_PAD_NANDF_D7__GPIO2_IO07             0x2a0 0x688 0x000 0x5 0x0
+#define MX6DL_PAD_NANDF_RB0__NAND_READY_B          0x2a4 0x68c 0x000 0x0 0x0
+#define MX6DL_PAD_NANDF_RB0__GPIO6_IO10            0x2a4 0x68c 0x000 0x5 0x0
+#define MX6DL_PAD_NANDF_WP_B__NAND_WP_B            0x2a8 0x690 0x000 0x0 0x0
+#define MX6DL_PAD_NANDF_WP_B__GPIO6_IO09           0x2a8 0x690 0x000 0x5 0x0
+#define MX6DL_PAD_NANDF_WP_B__I2C4_SCL             0x2a8 0x690 0x880 0x9 0x2
+#define MX6DL_PAD_RGMII_RD0__HSI_RX_READY          0x2ac 0x694 0x000 0x0 0x0
+#define MX6DL_PAD_RGMII_RD0__RGMII_RD0             0x2ac 0x694 0x818 0x1 0x1
+#define MX6DL_PAD_RGMII_RD0__GPIO6_IO25            0x2ac 0x694 0x000 0x5 0x0
+#define MX6DL_PAD_RGMII_RD1__HSI_TX_FLAG           0x2b0 0x698 0x000 0x0 0x0
+#define MX6DL_PAD_RGMII_RD1__RGMII_RD1             0x2b0 0x698 0x81c 0x1 0x1
+#define MX6DL_PAD_RGMII_RD1__GPIO6_IO27            0x2b0 0x698 0x000 0x5 0x0
+#define MX6DL_PAD_RGMII_RD2__HSI_TX_DATA           0x2b4 0x69c 0x000 0x0 0x0
+#define MX6DL_PAD_RGMII_RD2__RGMII_RD2             0x2b4 0x69c 0x820 0x1 0x1
+#define MX6DL_PAD_RGMII_RD2__GPIO6_IO28            0x2b4 0x69c 0x000 0x5 0x0
+#define MX6DL_PAD_RGMII_RD3__HSI_TX_WAKE           0x2b8 0x6a0 0x000 0x0 0x0
+#define MX6DL_PAD_RGMII_RD3__RGMII_RD3             0x2b8 0x6a0 0x824 0x1 0x1
+#define MX6DL_PAD_RGMII_RD3__GPIO6_IO29            0x2b8 0x6a0 0x000 0x5 0x0
+#define MX6DL_PAD_RGMII_RX_CTL__USB_H3_DATA        0x2bc 0x6a4 0x000 0x0 0x0
+#define MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL       0x2bc 0x6a4 0x828 0x1 0x1
+#define MX6DL_PAD_RGMII_RX_CTL__GPIO6_IO24         0x2bc 0x6a4 0x000 0x5 0x0
+#define MX6DL_PAD_RGMII_RXC__USB_H3_STROBE         0x2c0 0x6a8 0x000 0x0 0x0
+#define MX6DL_PAD_RGMII_RXC__RGMII_RXC             0x2c0 0x6a8 0x814 0x1 0x1
+#define MX6DL_PAD_RGMII_RXC__GPIO6_IO30            0x2c0 0x6a8 0x000 0x5 0x0
+#define MX6DL_PAD_RGMII_TD0__HSI_TX_READY          0x2c4 0x6ac 0x000 0x0 0x0
+#define MX6DL_PAD_RGMII_TD0__RGMII_TD0             0x2c4 0x6ac 0x000 0x1 0x0
+#define MX6DL_PAD_RGMII_TD0__GPIO6_IO20            0x2c4 0x6ac 0x000 0x5 0x0
+#define MX6DL_PAD_RGMII_TD1__HSI_RX_FLAG           0x2c8 0x6b0 0x000 0x0 0x0
+#define MX6DL_PAD_RGMII_TD1__RGMII_TD1             0x2c8 0x6b0 0x000 0x1 0x0
+#define MX6DL_PAD_RGMII_TD1__GPIO6_IO21            0x2c8 0x6b0 0x000 0x5 0x0
+#define MX6DL_PAD_RGMII_TD2__HSI_RX_DATA           0x2cc 0x6b4 0x000 0x0 0x0
+#define MX6DL_PAD_RGMII_TD2__RGMII_TD2             0x2cc 0x6b4 0x000 0x1 0x0
+#define MX6DL_PAD_RGMII_TD2__GPIO6_IO22            0x2cc 0x6b4 0x000 0x5 0x0
+#define MX6DL_PAD_RGMII_TD3__HSI_RX_WAKE           0x2d0 0x6b8 0x000 0x0 0x0
+#define MX6DL_PAD_RGMII_TD3__RGMII_TD3             0x2d0 0x6b8 0x000 0x1 0x0
+#define MX6DL_PAD_RGMII_TD3__GPIO6_IO23            0x2d0 0x6b8 0x000 0x5 0x0
+#define MX6DL_PAD_RGMII_TX_CTL__USB_H2_STROBE      0x2d4 0x6bc 0x000 0x0 0x0
+#define MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL       0x2d4 0x6bc 0x000 0x1 0x0
+#define MX6DL_PAD_RGMII_TX_CTL__GPIO6_IO26         0x2d4 0x6bc 0x000 0x5 0x0
+#define MX6DL_PAD_RGMII_TX_CTL__ENET_REF_CLK       0x2d4 0x6bc 0x80c 0x7 0x1
+#define MX6DL_PAD_RGMII_TXC__USB_H2_DATA           0x2d8 0x6c0 0x000 0x0 0x0
+#define MX6DL_PAD_RGMII_TXC__RGMII_TXC             0x2d8 0x6c0 0x000 0x1 0x0
+#define MX6DL_PAD_RGMII_TXC__SPDIF_EXT_CLK         0x2d8 0x6c0 0x8f4 0x2 0x1
+#define MX6DL_PAD_RGMII_TXC__GPIO6_IO19            0x2d8 0x6c0 0x000 0x5 0x0
+#define MX6DL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M   0x2d8 0x6c0 0x000 0x7 0x0
+#define MX6DL_PAD_SD1_CLK__SD1_CLK                 0x2dc 0x6c4 0x928 0x0 0x1
+#define MX6DL_PAD_SD1_CLK__GPT_CLKIN               0x2dc 0x6c4 0x000 0x3 0x0
+#define MX6DL_PAD_SD1_CLK__GPIO1_IO20              0x2dc 0x6c4 0x000 0x5 0x0
+#define MX6DL_PAD_SD1_CMD__SD1_CMD                 0x2e0 0x6c8 0x000 0x0 0x0
+#define MX6DL_PAD_SD1_CMD__PWM4_OUT                0x2e0 0x6c8 0x000 0x2 0x0
+#define MX6DL_PAD_SD1_CMD__GPT_COMPARE1            0x2e0 0x6c8 0x000 0x3 0x0
+#define MX6DL_PAD_SD1_CMD__GPIO1_IO18              0x2e0 0x6c8 0x000 0x5 0x0
+#define MX6DL_PAD_SD1_DAT0__SD1_DATA0              0x2e4 0x6cc 0x000 0x0 0x0
+#define MX6DL_PAD_SD1_DAT0__GPT_CAPTURE1           0x2e4 0x6cc 0x000 0x3 0x0
+#define MX6DL_PAD_SD1_DAT0__GPIO1_IO16             0x2e4 0x6cc 0x000 0x5 0x0
+#define MX6DL_PAD_SD1_DAT1__SD1_DATA1              0x2e8 0x6d0 0x000 0x0 0x0
+#define MX6DL_PAD_SD1_DAT1__PWM3_OUT               0x2e8 0x6d0 0x000 0x2 0x0
+#define MX6DL_PAD_SD1_DAT1__GPT_CAPTURE2           0x2e8 0x6d0 0x000 0x3 0x0
+#define MX6DL_PAD_SD1_DAT1__GPIO1_IO17             0x2e8 0x6d0 0x000 0x5 0x0
+#define MX6DL_PAD_SD1_DAT2__SD1_DATA2              0x2ec 0x6d4 0x000 0x0 0x0
+#define MX6DL_PAD_SD1_DAT2__GPT_COMPARE2           0x2ec 0x6d4 0x000 0x2 0x0
+#define MX6DL_PAD_SD1_DAT2__PWM2_OUT               0x2ec 0x6d4 0x000 0x3 0x0
+#define MX6DL_PAD_SD1_DAT2__WDOG1_B                0x2ec 0x6d4 0x000 0x4 0x0
+#define MX6DL_PAD_SD1_DAT2__GPIO1_IO19             0x2ec 0x6d4 0x000 0x5 0x0
+#define MX6DL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB      0x2ec 0x6d4 0x000 0x6 0x0
+#define MX6DL_PAD_SD1_DAT3__SD1_DATA3              0x2f0 0x6d8 0x000 0x0 0x0
+#define MX6DL_PAD_SD1_DAT3__GPT_COMPARE3           0x2f0 0x6d8 0x000 0x2 0x0
+#define MX6DL_PAD_SD1_DAT3__PWM1_OUT               0x2f0 0x6d8 0x000 0x3 0x0
+#define MX6DL_PAD_SD1_DAT3__WDOG2_B                0x2f0 0x6d8 0x000 0x4 0x0
+#define MX6DL_PAD_SD1_DAT3__GPIO1_IO21             0x2f0 0x6d8 0x000 0x5 0x0
+#define MX6DL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB      0x2f0 0x6d8 0x000 0x6 0x0
+#define MX6DL_PAD_SD2_CLK__SD2_CLK                 0x2f4 0x6dc 0x930 0x0 0x1
+#define MX6DL_PAD_SD2_CLK__KEY_COL5                0x2f4 0x6dc 0x8c0 0x2 0x3
+#define MX6DL_PAD_SD2_CLK__AUD4_RXFS               0x2f4 0x6dc 0x7a4 0x3 0x1
+#define MX6DL_PAD_SD2_CLK__GPIO1_IO10              0x2f4 0x6dc 0x000 0x5 0x0
+#define MX6DL_PAD_SD2_CMD__SD2_CMD                 0x2f8 0x6e0 0x000 0x0 0x0
+#define MX6DL_PAD_SD2_CMD__KEY_ROW5                0x2f8 0x6e0 0x8cc 0x2 0x2
+#define MX6DL_PAD_SD2_CMD__AUD4_RXC                0x2f8 0x6e0 0x7a0 0x3 0x1
+#define MX6DL_PAD_SD2_CMD__GPIO1_IO11              0x2f8 0x6e0 0x000 0x5 0x0
+#define MX6DL_PAD_SD2_DAT0__SD2_DATA0              0x2fc 0x6e4 0x000 0x0 0x0
+#define MX6DL_PAD_SD2_DAT0__AUD4_RXD               0x2fc 0x6e4 0x798 0x3 0x1
+#define MX6DL_PAD_SD2_DAT0__KEY_ROW7               0x2fc 0x6e4 0x8d4 0x4 0x2
+#define MX6DL_PAD_SD2_DAT0__GPIO1_IO15             0x2fc 0x6e4 0x000 0x5 0x0
+#define MX6DL_PAD_SD2_DAT0__DCIC2_OUT              0x2fc 0x6e4 0x000 0x6 0x0
+#define MX6DL_PAD_SD2_DAT1__SD2_DATA1              0x300 0x6e8 0x000 0x0 0x0
+#define MX6DL_PAD_SD2_DAT1__EIM_CS2_B              0x300 0x6e8 0x000 0x2 0x0
+#define MX6DL_PAD_SD2_DAT1__AUD4_TXFS              0x300 0x6e8 0x7ac 0x3 0x1
+#define MX6DL_PAD_SD2_DAT1__KEY_COL7               0x300 0x6e8 0x8c8 0x4 0x2
+#define MX6DL_PAD_SD2_DAT1__GPIO1_IO14             0x300 0x6e8 0x000 0x5 0x0
+#define MX6DL_PAD_SD2_DAT2__SD2_DATA2              0x304 0x6ec 0x000 0x0 0x0
+#define MX6DL_PAD_SD2_DAT2__EIM_CS3_B              0x304 0x6ec 0x000 0x2 0x0
+#define MX6DL_PAD_SD2_DAT2__AUD4_TXD               0x304 0x6ec 0x79c 0x3 0x1
+#define MX6DL_PAD_SD2_DAT2__KEY_ROW6               0x304 0x6ec 0x8d0 0x4 0x2
+#define MX6DL_PAD_SD2_DAT2__GPIO1_IO13             0x304 0x6ec 0x000 0x5 0x0
+#define MX6DL_PAD_SD2_DAT3__SD2_DATA3              0x308 0x6f0 0x000 0x0 0x0
+#define MX6DL_PAD_SD2_DAT3__KEY_COL6               0x308 0x6f0 0x8c4 0x2 0x2
+#define MX6DL_PAD_SD2_DAT3__AUD4_TXC               0x308 0x6f0 0x7a8 0x3 0x1
+#define MX6DL_PAD_SD2_DAT3__GPIO1_IO12             0x308 0x6f0 0x000 0x5 0x0
+#define MX6DL_PAD_SD3_CLK__SD3_CLK                 0x30c 0x6f4 0x934 0x0 0x1
+#define MX6DL_PAD_SD3_CLK__UART2_RTS_B             0x30c 0x6f4 0x900 0x1 0x2
+#define MX6DL_PAD_SD3_CLK__UART2_CTS_B             0x30c 0x6f4 0x000 0x1 0x0
+#define MX6DL_PAD_SD3_CLK__FLEXCAN1_RX             0x30c 0x6f4 0x7c8 0x2 0x2
+#define MX6DL_PAD_SD3_CLK__GPIO7_IO03              0x30c 0x6f4 0x000 0x5 0x0
+#define MX6DL_PAD_SD3_CMD__SD3_CMD                 0x310 0x6f8 0x000 0x0 0x0
+#define MX6DL_PAD_SD3_CMD__UART2_CTS_B             0x310 0x6f8 0x000 0x1 0x0
+#define MX6DL_PAD_SD3_CMD__UART2_RTS_B             0x310 0x6f8 0x900 0x1 0x3
+#define MX6DL_PAD_SD3_CMD__FLEXCAN1_TX             0x310 0x6f8 0x000 0x2 0x0
+#define MX6DL_PAD_SD3_CMD__GPIO7_IO02              0x310 0x6f8 0x000 0x5 0x0
+#define MX6DL_PAD_SD3_DAT0__SD3_DATA0              0x314 0x6fc 0x000 0x0 0x0
+#define MX6DL_PAD_SD3_DAT0__UART1_CTS_B            0x314 0x6fc 0x000 0x1 0x0
+#define MX6DL_PAD_SD3_DAT0__UART1_RTS_B            0x314 0x6fc 0x8f8 0x1 0x2
+#define MX6DL_PAD_SD3_DAT0__FLEXCAN2_TX            0x314 0x6fc 0x000 0x2 0x0
+#define MX6DL_PAD_SD3_DAT0__GPIO7_IO04             0x314 0x6fc 0x000 0x5 0x0
+#define MX6DL_PAD_SD3_DAT1__SD3_DATA1              0x318 0x700 0x000 0x0 0x0
+#define MX6DL_PAD_SD3_DAT1__UART1_RTS_B            0x318 0x700 0x8f8 0x1 0x3
+#define MX6DL_PAD_SD3_DAT1__UART1_CTS_B            0x318 0x700 0x000 0x1 0x0
+#define MX6DL_PAD_SD3_DAT1__FLEXCAN2_RX            0x318 0x700 0x7cc 0x2 0x1
+#define MX6DL_PAD_SD3_DAT1__GPIO7_IO05             0x318 0x700 0x000 0x5 0x0
+#define MX6DL_PAD_SD3_DAT2__SD3_DATA2              0x31c 0x704 0x000 0x0 0x0
+#define MX6DL_PAD_SD3_DAT2__GPIO7_IO06             0x31c 0x704 0x000 0x5 0x0
+#define MX6DL_PAD_SD3_DAT3__SD3_DATA3              0x320 0x708 0x000 0x0 0x0
+#define MX6DL_PAD_SD3_DAT3__UART3_CTS_B            0x320 0x708 0x000 0x1 0x0
+#define MX6DL_PAD_SD3_DAT3__UART3_RTS_B            0x320 0x708 0x908 0x1 0x4
+#define MX6DL_PAD_SD3_DAT3__GPIO7_IO07             0x320 0x708 0x000 0x5 0x0
+#define MX6DL_PAD_SD3_DAT4__SD3_DATA4              0x324 0x70c 0x000 0x0 0x0
+#define MX6DL_PAD_SD3_DAT4__UART2_RX_DATA          0x324 0x70c 0x904 0x1 0x4
+#define MX6DL_PAD_SD3_DAT4__UART2_TX_DATA          0x324 0x70c 0x000 0x1 0x0
+#define MX6DL_PAD_SD3_DAT4__GPIO7_IO01             0x324 0x70c 0x000 0x5 0x0
+#define MX6DL_PAD_SD3_DAT5__SD3_DATA5              0x328 0x710 0x000 0x0 0x0
+#define MX6DL_PAD_SD3_DAT5__UART2_TX_DATA          0x328 0x710 0x000 0x1 0x0
+#define MX6DL_PAD_SD3_DAT5__UART2_RX_DATA          0x328 0x710 0x904 0x1 0x5
+#define MX6DL_PAD_SD3_DAT5__GPIO7_IO00             0x328 0x710 0x000 0x5 0x0
+#define MX6DL_PAD_SD3_DAT6__SD3_DATA6              0x32c 0x714 0x000 0x0 0x0
+#define MX6DL_PAD_SD3_DAT6__UART1_RX_DATA          0x32c 0x714 0x8fc 0x1 0x2
+#define MX6DL_PAD_SD3_DAT6__UART1_TX_DATA          0x32c 0x714 0x000 0x1 0x0
+#define MX6DL_PAD_SD3_DAT6__GPIO6_IO18             0x32c 0x714 0x000 0x5 0x0
+#define MX6DL_PAD_SD3_DAT7__SD3_DATA7              0x330 0x718 0x000 0x0 0x0
+#define MX6DL_PAD_SD3_DAT7__UART1_TX_DATA          0x330 0x718 0x000 0x1 0x0
+#define MX6DL_PAD_SD3_DAT7__UART1_RX_DATA          0x330 0x718 0x8fc 0x1 0x3
+#define MX6DL_PAD_SD3_DAT7__GPIO6_IO17             0x330 0x718 0x000 0x5 0x0
+#define MX6DL_PAD_SD3_RST__SD3_RESET               0x334 0x71c 0x000 0x0 0x0
+#define MX6DL_PAD_SD3_RST__UART3_RTS_B             0x334 0x71c 0x908 0x1 0x5
+#define MX6DL_PAD_SD3_RST__UART3_CTS_B             0x334 0x71c 0x000 0x1 0x0
+#define MX6DL_PAD_SD3_RST__GPIO7_IO08              0x334 0x71c 0x000 0x5 0x0
+#define MX6DL_PAD_SD4_CLK__SD4_CLK                 0x338 0x720 0x938 0x0 0x1
+#define MX6DL_PAD_SD4_CLK__NAND_WE_B               0x338 0x720 0x000 0x1 0x0
+#define MX6DL_PAD_SD4_CLK__UART3_RX_DATA           0x338 0x720 0x90c 0x2 0x2
+#define MX6DL_PAD_SD4_CLK__UART3_TX_DATA           0x338 0x720 0x000 0x2 0x0
+#define MX6DL_PAD_SD4_CLK__GPIO7_IO10              0x338 0x720 0x000 0x5 0x0
+#define MX6DL_PAD_SD4_CMD__SD4_CMD                 0x33c 0x724 0x000 0x0 0x0
+#define MX6DL_PAD_SD4_CMD__NAND_RE_B               0x33c 0x724 0x000 0x1 0x0
+#define MX6DL_PAD_SD4_CMD__UART3_TX_DATA           0x33c 0x724 0x000 0x2 0x0
+#define MX6DL_PAD_SD4_CMD__UART3_RX_DATA           0x33c 0x724 0x90c 0x2 0x3
+#define MX6DL_PAD_SD4_CMD__GPIO7_IO09              0x33c 0x724 0x000 0x5 0x0
+#define MX6DL_PAD_SD4_DAT0__SD4_DATA0              0x340 0x728 0x000 0x1 0x0
+#define MX6DL_PAD_SD4_DAT0__NAND_DQS               0x340 0x728 0x000 0x2 0x0
+#define MX6DL_PAD_SD4_DAT0__GPIO2_IO08             0x340 0x728 0x000 0x5 0x0
+#define MX6DL_PAD_SD4_DAT1__SD4_DATA1              0x344 0x72c 0x000 0x1 0x0
+#define MX6DL_PAD_SD4_DAT1__PWM3_OUT               0x344 0x72c 0x000 0x2 0x0
+#define MX6DL_PAD_SD4_DAT1__GPIO2_IO09             0x344 0x72c 0x000 0x5 0x0
+#define MX6DL_PAD_SD4_DAT2__SD4_DATA2              0x348 0x730 0x000 0x1 0x0
+#define MX6DL_PAD_SD4_DAT2__PWM4_OUT               0x348 0x730 0x000 0x2 0x0
+#define MX6DL_PAD_SD4_DAT2__GPIO2_IO10             0x348 0x730 0x000 0x5 0x0
+#define MX6DL_PAD_SD4_DAT3__SD4_DATA3              0x34c 0x734 0x000 0x1 0x0
+#define MX6DL_PAD_SD4_DAT3__GPIO2_IO11             0x34c 0x734 0x000 0x5 0x0
+#define MX6DL_PAD_SD4_DAT4__SD4_DATA4              0x350 0x738 0x000 0x1 0x0
+#define MX6DL_PAD_SD4_DAT4__UART2_RX_DATA          0x350 0x738 0x904 0x2 0x6
+#define MX6DL_PAD_SD4_DAT4__UART2_TX_DATA          0x350 0x738 0x000 0x2 0x0
+#define MX6DL_PAD_SD4_DAT4__GPIO2_IO12             0x350 0x738 0x000 0x5 0x0
+#define MX6DL_PAD_SD4_DAT5__SD4_DATA5              0x354 0x73c 0x000 0x1 0x0
+#define MX6DL_PAD_SD4_DAT5__UART2_RTS_B            0x354 0x73c 0x900 0x2 0x4
+#define MX6DL_PAD_SD4_DAT5__UART2_CTS_B            0x354 0x73c 0x000 0x2 0x0
+#define MX6DL_PAD_SD4_DAT5__GPIO2_IO13             0x354 0x73c 0x000 0x5 0x0
+#define MX6DL_PAD_SD4_DAT6__SD4_DATA6              0x358 0x740 0x000 0x1 0x0
+#define MX6DL_PAD_SD4_DAT6__UART2_CTS_B            0x358 0x740 0x000 0x2 0x0
+#define MX6DL_PAD_SD4_DAT6__UART2_RTS_B            0x358 0x740 0x900 0x2 0x5
+#define MX6DL_PAD_SD4_DAT6__GPIO2_IO14             0x358 0x740 0x000 0x5 0x0
+#define MX6DL_PAD_SD4_DAT7__SD4_DATA7              0x35c 0x744 0x000 0x1 0x0
+#define MX6DL_PAD_SD4_DAT7__UART2_TX_DATA          0x35c 0x744 0x000 0x2 0x0
+#define MX6DL_PAD_SD4_DAT7__UART2_RX_DATA          0x35c 0x744 0x904 0x2 0x7
+#define MX6DL_PAD_SD4_DAT7__GPIO2_IO15             0x35c 0x744 0x000 0x5 0x0
+
+#endif /* __DTS_IMX6DL_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts
new file mode 100644
index 000000000000..7adcec360213
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-sabreauto.dtsi"
+
+/ {
+        model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
+        compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
+                                MX6DL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts
new file mode 100644
index 000000000000..7efb05db4783
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-sabresd.dts
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-sabresd.dtsi"
+
+/ {
+        model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
+        compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6DL_PAD_GPIO_4__GPIO1_IO04   0x80000000
+                                MX6DL_PAD_GPIO_5__GPIO1_IO05   0x80000000
+                                MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
+                                MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
+                                MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
+                                MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6dl-wandboard.dts b/arch/arm/boot/dts/imx6dl-wandboard.dts
new file mode 100644
index 000000000000..bfc59c3566a4
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+#include "imx6dl.dtsi"
+
+/ {
+        model = "Wandboard i.MX6 Dual Lite Board";
+        compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
+
+        memory {
+                reg = <0x10000000 0x40000000>;
+        };
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet_1>;
+        phy-mode = "rgmii";
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_1>;
+        status = "okay";
+};
+
+&usbh1 {
+        status = "okay";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3_2>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 63fafe2a606c..5bcdf3a90bb3 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -1,3 +1,4 @@
+
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
@@ -7,7 +8,8 @@
  *
  */
 
-/include/ "imx6qdl.dtsi"
+#include "imx6qdl.dtsi"
+#include "imx6dl-pinfunc.h"
 
 / {
         cpus {
@@ -29,6 +31,127 @@
 
         soc {
                 aips1: aips-bus@02000000 {
+                        iomuxc: iomuxc@020e0000 {
+                                compatible = "fsl,imx6dl-iomuxc";
+                                reg = <0x020e0000 0x4000>;
+
+                                enet {
+                                        pinctrl_enet_1: enetgrp-1 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+                                                        MX6DL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+                                                        MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+                                                        MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+                                                        MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+                                                        MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+                                                        MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+                                                        MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+                                                        MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+                                                        MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+                                                        MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+                                                        MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+                                                        MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+                                                        MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+                                                        MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+                                                        MX6DL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
+                                                >;
+                                        };
+
+                                        pinctrl_enet_2: enetgrp-2 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
+                                                        MX6DL_PAD_KEY_COL2__ENET_MDC         0x1b0b0
+                                                        MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+                                                        MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+                                                        MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+                                                        MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+                                                        MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+                                                        MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+                                                        MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+                                                        MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+                                                        MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+                                                        MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+                                                        MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+                                                        MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+                                                        MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+                                                >;
+                                        };
+                                };
+
+                                uart1 {
+                                        pinctrl_uart1_1: uart1grp-1 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+                                                        MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+                                                >;
+                                        };
+                                };
+
+                                uart4 {
+                                        pinctrl_uart4_1: uart4grp-1 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+                                                        MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+                                                >;
+                                        };
+                                };
+
+                                usbotg {
+                                        pinctrl_usbotg_2: usbotggrp-2 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+                                                >;
+                                        };
+                                };
+
+                                usdhc2 {
+                                        pinctrl_usdhc2_1: usdhc2grp-1 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_SD2_CMD__SD2_CMD    0x17059
+                                                        MX6DL_PAD_SD2_CLK__SD2_CLK    0x10059
+                                                        MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+                                                        MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+                                                        MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+                                                        MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+                                                        MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
+                                                        MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
+                                                        MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
+                                                        MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
+                                                >;
+                                        };
+                                };
+
+                                usdhc3 {
+                                        pinctrl_usdhc3_1: usdhc3grp-1 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
+                                                        MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
+                                                        MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+                                                        MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+                                                        MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+                                                        MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+                                                        MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+                                                        MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+                                                        MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+                                                        MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+                                                >;
+                                        };
+
+                                        pinctrl_usdhc3_2: usdhc3grp_2 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
+                                                        MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
+                                                        MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+                                                        MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+                                                        MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+                                                        MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+                                                >;
+                                        };
+                                };
+
+
+                        };
+
                         pxp: pxp@020f0000 {
                                 reg = <0x020f0000 0x4000>;
                                 interrupts = <0 98 0x04>;
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 53eb241fa5ad..4e54fde591bd 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -11,7 +11,7 @@
  */
 
 /dts-v1/;
-/include/ "imx6q.dtsi"
+#include "imx6q.dtsi"
 
 / {
         model = "Freescale i.MX6 Quad Armadillo2 Board";
@@ -57,7 +57,7 @@
         hog {
                 pinctrl_hog: hoggrp {
                         fsl,pins = <
-                                176  0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
+                                MX6Q_PAD_EIM_D25__GPIO3_IO25 0x80000000
                         >;
                 };
         };
@@ -65,8 +65,8 @@
         arm2 {
                 pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
                         fsl,pins = <
-                                1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
-                                1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
+                                MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
+                                MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
                         >;
                 };
         };
diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h
new file mode 100644
index 000000000000..faea6e1ada00
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-pinfunc.h
@@ -0,0 +1,1041 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6Q_PINFUNC_H
+#define __DTS_IMX6Q_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6Q_PAD_SD2_DAT1__SD2_DATA1              0x04c 0x360 0x000 0x0 0x0
+#define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0             0x04c 0x360 0x834 0x1 0x0
+#define MX6Q_PAD_SD2_DAT1__EIM_CS2_B              0x04c 0x360 0x000 0x2 0x0
+#define MX6Q_PAD_SD2_DAT1__AUD4_TXFS              0x04c 0x360 0x7c8 0x3 0x0
+#define MX6Q_PAD_SD2_DAT1__KEY_COL7               0x04c 0x360 0x8f0 0x4 0x0
+#define MX6Q_PAD_SD2_DAT1__GPIO1_IO14             0x04c 0x360 0x000 0x5 0x0
+#define MX6Q_PAD_SD2_DAT2__SD2_DATA2              0x050 0x364 0x000 0x0 0x0
+#define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1             0x050 0x364 0x838 0x1 0x0
+#define MX6Q_PAD_SD2_DAT2__EIM_CS3_B              0x050 0x364 0x000 0x2 0x0
+#define MX6Q_PAD_SD2_DAT2__AUD4_TXD               0x050 0x364 0x7b8 0x3 0x0
+#define MX6Q_PAD_SD2_DAT2__KEY_ROW6               0x050 0x364 0x8f8 0x4 0x0
+#define MX6Q_PAD_SD2_DAT2__GPIO1_IO13             0x050 0x364 0x000 0x5 0x0
+#define MX6Q_PAD_SD2_DAT0__SD2_DATA0              0x054 0x368 0x000 0x0 0x0
+#define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO            0x054 0x368 0x82c 0x1 0x0
+#define MX6Q_PAD_SD2_DAT0__AUD4_RXD               0x054 0x368 0x7b4 0x3 0x0
+#define MX6Q_PAD_SD2_DAT0__KEY_ROW7               0x054 0x368 0x8fc 0x4 0x0
+#define MX6Q_PAD_SD2_DAT0__GPIO1_IO15             0x054 0x368 0x000 0x5 0x0
+#define MX6Q_PAD_SD2_DAT0__DCIC2_OUT              0x054 0x368 0x000 0x6 0x0
+#define MX6Q_PAD_RGMII_TXC__USB_H2_DATA           0x058 0x36c 0x000 0x0 0x0
+#define MX6Q_PAD_RGMII_TXC__RGMII_TXC             0x058 0x36c 0x000 0x1 0x0
+#define MX6Q_PAD_RGMII_TXC__SPDIF_EXT_CLK         0x058 0x36c 0x918 0x2 0x0
+#define MX6Q_PAD_RGMII_TXC__GPIO6_IO19            0x058 0x36c 0x000 0x5 0x0
+#define MX6Q_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M   0x058 0x36c 0x000 0x7 0x0
+#define MX6Q_PAD_RGMII_TD0__HSI_TX_READY          0x05c 0x370 0x000 0x0 0x0
+#define MX6Q_PAD_RGMII_TD0__RGMII_TD0             0x05c 0x370 0x000 0x1 0x0
+#define MX6Q_PAD_RGMII_TD0__GPIO6_IO20            0x05c 0x370 0x000 0x5 0x0
+#define MX6Q_PAD_RGMII_TD1__HSI_RX_FLAG           0x060 0x374 0x000 0x0 0x0
+#define MX6Q_PAD_RGMII_TD1__RGMII_TD1             0x060 0x374 0x000 0x1 0x0
+#define MX6Q_PAD_RGMII_TD1__GPIO6_IO21            0x060 0x374 0x000 0x5 0x0
+#define MX6Q_PAD_RGMII_TD2__HSI_RX_DATA           0x064 0x378 0x000 0x0 0x0
+#define MX6Q_PAD_RGMII_TD2__RGMII_TD2             0x064 0x378 0x000 0x1 0x0
+#define MX6Q_PAD_RGMII_TD2__GPIO6_IO22            0x064 0x378 0x000 0x5 0x0
+#define MX6Q_PAD_RGMII_TD3__HSI_RX_WAKE           0x068 0x37c 0x000 0x0 0x0
+#define MX6Q_PAD_RGMII_TD3__RGMII_TD3             0x068 0x37c 0x000 0x1 0x0
+#define MX6Q_PAD_RGMII_TD3__GPIO6_IO23            0x068 0x37c 0x000 0x5 0x0
+#define MX6Q_PAD_RGMII_RX_CTL__USB_H3_DATA        0x06c 0x380 0x000 0x0 0x0
+#define MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL       0x06c 0x380 0x858 0x1 0x0
+#define MX6Q_PAD_RGMII_RX_CTL__GPIO6_IO24         0x06c 0x380 0x000 0x5 0x0
+#define MX6Q_PAD_RGMII_RD0__HSI_RX_READY          0x070 0x384 0x000 0x0 0x0
+#define MX6Q_PAD_RGMII_RD0__RGMII_RD0             0x070 0x384 0x848 0x1 0x0
+#define MX6Q_PAD_RGMII_RD0__GPIO6_IO25            0x070 0x384 0x000 0x5 0x0
+#define MX6Q_PAD_RGMII_TX_CTL__USB_H2_STROBE      0x074 0x388 0x000 0x0 0x0
+#define MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL       0x074 0x388 0x000 0x1 0x0
+#define MX6Q_PAD_RGMII_TX_CTL__GPIO6_IO26         0x074 0x388 0x000 0x5 0x0
+#define MX6Q_PAD_RGMII_TX_CTL__ENET_REF_CLK       0x074 0x388 0x83c 0x7 0x0
+#define MX6Q_PAD_RGMII_RD1__HSI_TX_FLAG           0x078 0x38c 0x000 0x0 0x0
+#define MX6Q_PAD_RGMII_RD1__RGMII_RD1             0x078 0x38c 0x84c 0x1 0x0
+#define MX6Q_PAD_RGMII_RD1__GPIO6_IO27            0x078 0x38c 0x000 0x5 0x0
+#define MX6Q_PAD_RGMII_RD2__HSI_TX_DATA           0x07c 0x390 0x000 0x0 0x0
+#define MX6Q_PAD_RGMII_RD2__RGMII_RD2             0x07c 0x390 0x850 0x1 0x0
+#define MX6Q_PAD_RGMII_RD2__GPIO6_IO28            0x07c 0x390 0x000 0x5 0x0
+#define MX6Q_PAD_RGMII_RD3__HSI_TX_WAKE           0x080 0x394 0x000 0x0 0x0
+#define MX6Q_PAD_RGMII_RD3__RGMII_RD3             0x080 0x394 0x854 0x1 0x0
+#define MX6Q_PAD_RGMII_RD3__GPIO6_IO29            0x080 0x394 0x000 0x5 0x0
+#define MX6Q_PAD_RGMII_RXC__USB_H3_STROBE         0x084 0x398 0x000 0x0 0x0
+#define MX6Q_PAD_RGMII_RXC__RGMII_RXC             0x084 0x398 0x844 0x1 0x0
+#define MX6Q_PAD_RGMII_RXC__GPIO6_IO30            0x084 0x398 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_A25__EIM_ADDR25              0x088 0x39c 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_A25__ECSPI4_SS1              0x088 0x39c 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_A25__ECSPI2_RDY              0x088 0x39c 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12          0x088 0x39c 0x000 0x3 0x0
+#define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS          0x088 0x39c 0x000 0x4 0x0
+#define MX6Q_PAD_EIM_A25__GPIO5_IO02              0x088 0x39c 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE        0x088 0x39c 0x88c 0x6 0x0
+#define MX6Q_PAD_EIM_EB2__EIM_EB2_B               0x08c 0x3a0 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_EB2__ECSPI1_SS0              0x08c 0x3a0 0x800 0x1 0x0
+#define MX6Q_PAD_EIM_EB2__IPU2_CSI1_DATA19        0x08c 0x3a0 0x8d4 0x3 0x0
+#define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL         0x08c 0x3a0 0x890 0x4 0x0
+#define MX6Q_PAD_EIM_EB2__GPIO2_IO30              0x08c 0x3a0 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_EB2__I2C2_SCL                0x08c 0x3a0 0x8a0 0x6 0x0
+#define MX6Q_PAD_EIM_EB2__SRC_BOOT_CFG30          0x08c 0x3a0 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_D16__EIM_DATA16              0x090 0x3a4 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK             0x090 0x3a4 0x7f4 0x1 0x0
+#define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN05          0x090 0x3a4 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_D16__IPU2_CSI1_DATA18        0x090 0x3a4 0x8d0 0x3 0x0
+#define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA         0x090 0x3a4 0x894 0x4 0x0
+#define MX6Q_PAD_EIM_D16__GPIO3_IO16              0x090 0x3a4 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_D16__I2C2_SDA                0x090 0x3a4 0x8a4 0x6 0x0
+#define MX6Q_PAD_EIM_D17__EIM_DATA17              0x094 0x3a8 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_D17__ECSPI1_MISO             0x094 0x3a8 0x7f8 0x1 0x0
+#define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN06          0x094 0x3a8 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK        0x094 0x3a8 0x8e0 0x3 0x0
+#define MX6Q_PAD_EIM_D17__DCIC1_OUT               0x094 0x3a8 0x000 0x4 0x0
+#define MX6Q_PAD_EIM_D17__GPIO3_IO17              0x094 0x3a8 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_D17__I2C3_SCL                0x094 0x3a8 0x8a8 0x6 0x0
+#define MX6Q_PAD_EIM_D18__EIM_DATA18              0x098 0x3ac 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI             0x098 0x3ac 0x7fc 0x1 0x0
+#define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN07          0x098 0x3ac 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_D18__IPU2_CSI1_DATA17        0x098 0x3ac 0x8cc 0x3 0x0
+#define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS          0x098 0x3ac 0x000 0x4 0x0
+#define MX6Q_PAD_EIM_D18__GPIO3_IO18              0x098 0x3ac 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_D18__I2C3_SDA                0x098 0x3ac 0x8ac 0x6 0x0
+#define MX6Q_PAD_EIM_D19__EIM_DATA19              0x09c 0x3b0 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_D19__ECSPI1_SS1              0x09c 0x3b0 0x804 0x1 0x0
+#define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN08          0x09c 0x3b0 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_D19__IPU2_CSI1_DATA16        0x09c 0x3b0 0x8c8 0x3 0x0
+#define MX6Q_PAD_EIM_D19__UART1_CTS_B             0x09c 0x3b0 0x000 0x4 0x0
+#define MX6Q_PAD_EIM_D19__UART1_RTS_B             0x09c 0x3b0 0x91c 0x4 0x0
+#define MX6Q_PAD_EIM_D19__GPIO3_IO19              0x09c 0x3b0 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_D19__EPIT1_OUT               0x09c 0x3b0 0x000 0x6 0x0
+#define MX6Q_PAD_EIM_D20__EIM_DATA20              0x0a0 0x3b4 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_D20__ECSPI4_SS0              0x0a0 0x3b4 0x824 0x1 0x0
+#define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16          0x0a0 0x3b4 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_D20__IPU2_CSI1_DATA15        0x0a0 0x3b4 0x8c4 0x3 0x0
+#define MX6Q_PAD_EIM_D20__UART1_RTS_B             0x0a0 0x3b4 0x91c 0x4 0x1
+#define MX6Q_PAD_EIM_D20__UART1_CTS_B             0x0a0 0x3b4 0x000 0x4 0x0
+#define MX6Q_PAD_EIM_D20__GPIO3_IO20              0x0a0 0x3b4 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_D20__EPIT2_OUT               0x0a0 0x3b4 0x000 0x6 0x0
+#define MX6Q_PAD_EIM_D21__EIM_DATA21              0x0a4 0x3b8 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_D21__ECSPI4_SCLK             0x0a4 0x3b8 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17          0x0a4 0x3b8 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_D21__IPU2_CSI1_DATA11        0x0a4 0x3b8 0x8b4 0x3 0x0
+#define MX6Q_PAD_EIM_D21__USB_OTG_OC              0x0a4 0x3b8 0x944 0x4 0x0
+#define MX6Q_PAD_EIM_D21__GPIO3_IO21              0x0a4 0x3b8 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_D21__I2C1_SCL                0x0a4 0x3b8 0x898 0x6 0x0
+#define MX6Q_PAD_EIM_D21__SPDIF_IN                0x0a4 0x3b8 0x914 0x7 0x0
+#define MX6Q_PAD_EIM_D22__EIM_DATA22              0x0a8 0x3bc 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_D22__ECSPI4_MISO             0x0a8 0x3bc 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN01          0x0a8 0x3bc 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_D22__IPU2_CSI1_DATA10        0x0a8 0x3bc 0x8b0 0x3 0x0
+#define MX6Q_PAD_EIM_D22__USB_OTG_PWR             0x0a8 0x3bc 0x000 0x4 0x0
+#define MX6Q_PAD_EIM_D22__GPIO3_IO22              0x0a8 0x3bc 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_D22__SPDIF_OUT               0x0a8 0x3bc 0x000 0x6 0x0
+#define MX6Q_PAD_EIM_D23__EIM_DATA23              0x0ac 0x3c0 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS          0x0ac 0x3c0 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_D23__UART3_CTS_B             0x0ac 0x3c0 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_D23__UART3_RTS_B             0x0ac 0x3c0 0x92c 0x2 0x0
+#define MX6Q_PAD_EIM_D23__UART1_DCD_B             0x0ac 0x3c0 0x000 0x3 0x0
+#define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN       0x0ac 0x3c0 0x8d8 0x4 0x0
+#define MX6Q_PAD_EIM_D23__GPIO3_IO23              0x0ac 0x3c0 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN02          0x0ac 0x3c0 0x000 0x6 0x0
+#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14          0x0ac 0x3c0 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_EB3__EIM_EB3_B               0x0b0 0x3c4 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_EB3__ECSPI4_RDY              0x0b0 0x3c4 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_EB3__UART3_RTS_B             0x0b0 0x3c4 0x92c 0x2 0x1
+#define MX6Q_PAD_EIM_EB3__UART3_CTS_B             0x0b0 0x3c4 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_EB3__UART1_RI_B              0x0b0 0x3c4 0x000 0x3 0x0
+#define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC         0x0b0 0x3c4 0x8dc 0x4 0x0
+#define MX6Q_PAD_EIM_EB3__GPIO2_IO31              0x0b0 0x3c4 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN03          0x0b0 0x3c4 0x000 0x6 0x0
+#define MX6Q_PAD_EIM_EB3__SRC_BOOT_CFG31          0x0b0 0x3c4 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_D24__EIM_DATA24              0x0b4 0x3c8 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_D24__ECSPI4_SS2              0x0b4 0x3c8 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_D24__UART3_TX_DATA           0x0b4 0x3c8 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_D24__UART3_RX_DATA           0x0b4 0x3c8 0x930 0x2 0x0
+#define MX6Q_PAD_EIM_D24__ECSPI1_SS2              0x0b4 0x3c8 0x808 0x3 0x0
+#define MX6Q_PAD_EIM_D24__ECSPI2_SS2              0x0b4 0x3c8 0x000 0x4 0x0
+#define MX6Q_PAD_EIM_D24__GPIO3_IO24              0x0b4 0x3c8 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_D24__AUD5_RXFS               0x0b4 0x3c8 0x7d8 0x6 0x0
+#define MX6Q_PAD_EIM_D24__UART1_DTR_B             0x0b4 0x3c8 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_D25__EIM_DATA25              0x0b8 0x3cc 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_D25__ECSPI4_SS3              0x0b8 0x3cc 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_D25__UART3_RX_DATA           0x0b8 0x3cc 0x930 0x2 0x1
+#define MX6Q_PAD_EIM_D25__UART3_TX_DATA           0x0b8 0x3cc 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_D25__ECSPI1_SS3              0x0b8 0x3cc 0x80c 0x3 0x0
+#define MX6Q_PAD_EIM_D25__ECSPI2_SS3              0x0b8 0x3cc 0x000 0x4 0x0
+#define MX6Q_PAD_EIM_D25__GPIO3_IO25              0x0b8 0x3cc 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_D25__AUD5_RXC                0x0b8 0x3cc 0x7d4 0x6 0x0
+#define MX6Q_PAD_EIM_D25__UART1_DSR_B             0x0b8 0x3cc 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_D26__EIM_DATA26              0x0bc 0x3d0 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11          0x0bc 0x3d0 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_D26__IPU1_CSI0_DATA01        0x0bc 0x3d0 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_D26__IPU2_CSI1_DATA14        0x0bc 0x3d0 0x8c0 0x3 0x0
+#define MX6Q_PAD_EIM_D26__UART2_TX_DATA           0x0bc 0x3d0 0x000 0x4 0x0
+#define MX6Q_PAD_EIM_D26__UART2_RX_DATA           0x0bc 0x3d0 0x928 0x4 0x0
+#define MX6Q_PAD_EIM_D26__GPIO3_IO26              0x0bc 0x3d0 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_D26__IPU1_SISG2              0x0bc 0x3d0 0x000 0x6 0x0
+#define MX6Q_PAD_EIM_D26__IPU1_DISP1_DATA22       0x0bc 0x3d0 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_D27__EIM_DATA27              0x0c0 0x3d4 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13          0x0c0 0x3d4 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_D27__IPU1_CSI0_DATA00        0x0c0 0x3d4 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_D27__IPU2_CSI1_DATA13        0x0c0 0x3d4 0x8bc 0x3 0x0
+#define MX6Q_PAD_EIM_D27__UART2_RX_DATA           0x0c0 0x3d4 0x928 0x4 0x1
+#define MX6Q_PAD_EIM_D27__UART2_TX_DATA           0x0c0 0x3d4 0x000 0x4 0x0
+#define MX6Q_PAD_EIM_D27__GPIO3_IO27              0x0c0 0x3d4 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_D27__IPU1_SISG3              0x0c0 0x3d4 0x000 0x6 0x0
+#define MX6Q_PAD_EIM_D27__IPU1_DISP1_DATA23       0x0c0 0x3d4 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_D28__EIM_DATA28              0x0c4 0x3d8 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_D28__I2C1_SDA                0x0c4 0x3d8 0x89c 0x1 0x0
+#define MX6Q_PAD_EIM_D28__ECSPI4_MOSI             0x0c4 0x3d8 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_D28__IPU2_CSI1_DATA12        0x0c4 0x3d8 0x8b8 0x3 0x0
+#define MX6Q_PAD_EIM_D28__UART2_CTS_B             0x0c4 0x3d8 0x000 0x4 0x0
+#define MX6Q_PAD_EIM_D28__UART2_RTS_B             0x0c4 0x3d8 0x924 0x4 0x0
+#define MX6Q_PAD_EIM_D28__GPIO3_IO28              0x0c4 0x3d8 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG           0x0c4 0x3d8 0x000 0x6 0x0
+#define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13          0x0c4 0x3d8 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_D29__EIM_DATA29              0x0c8 0x3dc 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15          0x0c8 0x3dc 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_D29__ECSPI4_SS0              0x0c8 0x3dc 0x824 0x2 0x1
+#define MX6Q_PAD_EIM_D29__UART2_RTS_B             0x0c8 0x3dc 0x924 0x4 0x1
+#define MX6Q_PAD_EIM_D29__UART2_CTS_B             0x0c8 0x3dc 0x000 0x4 0x0
+#define MX6Q_PAD_EIM_D29__GPIO3_IO29              0x0c8 0x3dc 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC         0x0c8 0x3dc 0x8e4 0x6 0x0
+#define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14          0x0c8 0x3dc 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_D30__EIM_DATA30              0x0cc 0x3e0 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_D30__IPU1_DISP1_DATA21       0x0cc 0x3e0 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11          0x0cc 0x3e0 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_D30__IPU1_CSI0_DATA03        0x0cc 0x3e0 0x000 0x3 0x0
+#define MX6Q_PAD_EIM_D30__UART3_CTS_B             0x0cc 0x3e0 0x000 0x4 0x0
+#define MX6Q_PAD_EIM_D30__UART3_RTS_B             0x0cc 0x3e0 0x92c 0x4 0x2
+#define MX6Q_PAD_EIM_D30__GPIO3_IO30              0x0cc 0x3e0 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_D30__USB_H1_OC               0x0cc 0x3e0 0x948 0x6 0x0
+#define MX6Q_PAD_EIM_D31__EIM_DATA31              0x0d0 0x3e4 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_D31__IPU1_DISP1_DATA20       0x0d0 0x3e4 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12          0x0d0 0x3e4 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_D31__IPU1_CSI0_DATA02        0x0d0 0x3e4 0x000 0x3 0x0
+#define MX6Q_PAD_EIM_D31__UART3_RTS_B             0x0d0 0x3e4 0x92c 0x4 0x3
+#define MX6Q_PAD_EIM_D31__UART3_CTS_B             0x0d0 0x3e4 0x000 0x4 0x0
+#define MX6Q_PAD_EIM_D31__GPIO3_IO31              0x0d0 0x3e4 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_D31__USB_H1_PWR              0x0d0 0x3e4 0x000 0x6 0x0
+#define MX6Q_PAD_EIM_A24__EIM_ADDR24              0x0d4 0x3e8 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_A24__IPU1_DISP1_DATA19       0x0d4 0x3e8 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_A24__IPU2_CSI1_DATA19        0x0d4 0x3e8 0x8d4 0x2 0x1
+#define MX6Q_PAD_EIM_A24__IPU2_SISG2              0x0d4 0x3e8 0x000 0x3 0x0
+#define MX6Q_PAD_EIM_A24__IPU1_SISG2              0x0d4 0x3e8 0x000 0x4 0x0
+#define MX6Q_PAD_EIM_A24__GPIO5_IO04              0x0d4 0x3e8 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_A24__SRC_BOOT_CFG24          0x0d4 0x3e8 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_A23__EIM_ADDR23              0x0d8 0x3ec 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_A23__IPU1_DISP1_DATA18       0x0d8 0x3ec 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_A23__IPU2_CSI1_DATA18        0x0d8 0x3ec 0x8d0 0x2 0x1
+#define MX6Q_PAD_EIM_A23__IPU2_SISG3              0x0d8 0x3ec 0x000 0x3 0x0
+#define MX6Q_PAD_EIM_A23__IPU1_SISG3              0x0d8 0x3ec 0x000 0x4 0x0
+#define MX6Q_PAD_EIM_A23__GPIO6_IO06              0x0d8 0x3ec 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_A23__SRC_BOOT_CFG23          0x0d8 0x3ec 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_A22__EIM_ADDR22              0x0dc 0x3f0 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_A22__IPU1_DISP1_DATA17       0x0dc 0x3f0 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_A22__IPU2_CSI1_DATA17        0x0dc 0x3f0 0x8cc 0x2 0x1
+#define MX6Q_PAD_EIM_A22__GPIO2_IO16              0x0dc 0x3f0 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_A22__SRC_BOOT_CFG22          0x0dc 0x3f0 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_A21__EIM_ADDR21              0x0e0 0x3f4 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_A21__IPU1_DISP1_DATA16       0x0e0 0x3f4 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_A21__IPU2_CSI1_DATA16        0x0e0 0x3f4 0x8c8 0x2 0x1
+#define MX6Q_PAD_EIM_A21__GPIO2_IO17              0x0e0 0x3f4 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_A21__SRC_BOOT_CFG21          0x0e0 0x3f4 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_A20__EIM_ADDR20              0x0e4 0x3f8 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_A20__IPU1_DISP1_DATA15       0x0e4 0x3f8 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_A20__IPU2_CSI1_DATA15        0x0e4 0x3f8 0x8c4 0x2 0x1
+#define MX6Q_PAD_EIM_A20__GPIO2_IO18              0x0e4 0x3f8 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_A20__SRC_BOOT_CFG20          0x0e4 0x3f8 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_A19__EIM_ADDR19              0x0e8 0x3fc 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_A19__IPU1_DISP1_DATA14       0x0e8 0x3fc 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_A19__IPU2_CSI1_DATA14        0x0e8 0x3fc 0x8c0 0x2 0x1
+#define MX6Q_PAD_EIM_A19__GPIO2_IO19              0x0e8 0x3fc 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_A19__SRC_BOOT_CFG19          0x0e8 0x3fc 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_A18__EIM_ADDR18              0x0ec 0x400 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_A18__IPU1_DISP1_DATA13       0x0ec 0x400 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_A18__IPU2_CSI1_DATA13        0x0ec 0x400 0x8bc 0x2 0x1
+#define MX6Q_PAD_EIM_A18__GPIO2_IO20              0x0ec 0x400 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_A18__SRC_BOOT_CFG18          0x0ec 0x400 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_A17__EIM_ADDR17              0x0f0 0x404 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_A17__IPU1_DISP1_DATA12       0x0f0 0x404 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_A17__IPU2_CSI1_DATA12        0x0f0 0x404 0x8b8 0x2 0x1
+#define MX6Q_PAD_EIM_A17__GPIO2_IO21              0x0f0 0x404 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_A17__SRC_BOOT_CFG17          0x0f0 0x404 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_A16__EIM_ADDR16              0x0f4 0x408 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK       0x0f4 0x408 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK        0x0f4 0x408 0x8e0 0x2 0x1
+#define MX6Q_PAD_EIM_A16__GPIO2_IO22              0x0f4 0x408 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_A16__SRC_BOOT_CFG16          0x0f4 0x408 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_CS0__EIM_CS0_B               0x0f8 0x40c 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN05          0x0f8 0x40c 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK             0x0f8 0x40c 0x810 0x2 0x0
+#define MX6Q_PAD_EIM_CS0__GPIO2_IO23              0x0f8 0x40c 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_CS1__EIM_CS1_B               0x0fc 0x410 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN06          0x0fc 0x410 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI             0x0fc 0x410 0x818 0x2 0x0
+#define MX6Q_PAD_EIM_CS1__GPIO2_IO24              0x0fc 0x410 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_OE__EIM_OE_B                 0x100 0x414 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN07           0x100 0x414 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_OE__ECSPI2_MISO              0x100 0x414 0x814 0x2 0x0
+#define MX6Q_PAD_EIM_OE__GPIO2_IO25               0x100 0x414 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_RW__EIM_RW                   0x104 0x418 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN08           0x104 0x418 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_RW__ECSPI2_SS0               0x104 0x418 0x81c 0x2 0x0
+#define MX6Q_PAD_EIM_RW__GPIO2_IO26               0x104 0x418 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_RW__SRC_BOOT_CFG29           0x104 0x418 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_LBA__EIM_LBA_B               0x108 0x41c 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17          0x108 0x41c 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_LBA__ECSPI2_SS1              0x108 0x41c 0x820 0x2 0x0
+#define MX6Q_PAD_EIM_LBA__GPIO2_IO27              0x108 0x41c 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_LBA__SRC_BOOT_CFG26          0x108 0x41c 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_EB0__EIM_EB0_B               0x10c 0x420 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DATA11       0x10c 0x420 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_EB0__IPU2_CSI1_DATA11        0x10c 0x420 0x8b4 0x2 0x1
+#define MX6Q_PAD_EIM_EB0__CCM_PMIC_READY          0x10c 0x420 0x7f0 0x4 0x0
+#define MX6Q_PAD_EIM_EB0__GPIO2_IO28              0x10c 0x420 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_EB0__SRC_BOOT_CFG27          0x10c 0x420 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_EB1__EIM_EB1_B               0x110 0x424 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DATA10       0x110 0x424 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_EB1__IPU2_CSI1_DATA10        0x110 0x424 0x8b0 0x2 0x1
+#define MX6Q_PAD_EIM_EB1__GPIO2_IO29              0x110 0x424 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_EB1__SRC_BOOT_CFG28          0x110 0x424 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_DA0__EIM_AD00                0x114 0x428 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DATA09       0x114 0x428 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_DA0__IPU2_CSI1_DATA09        0x114 0x428 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_DA0__GPIO3_IO00              0x114 0x428 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_DA0__SRC_BOOT_CFG00          0x114 0x428 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_DA1__EIM_AD01                0x118 0x42c 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DATA08       0x118 0x42c 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_DA1__IPU2_CSI1_DATA08        0x118 0x42c 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_DA1__GPIO3_IO01              0x118 0x42c 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_DA1__SRC_BOOT_CFG01          0x118 0x42c 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_DA2__EIM_AD02                0x11c 0x430 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DATA07       0x11c 0x430 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_DA2__IPU2_CSI1_DATA07        0x11c 0x430 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_DA2__GPIO3_IO02              0x11c 0x430 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_DA2__SRC_BOOT_CFG02          0x11c 0x430 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_DA3__EIM_AD03                0x120 0x434 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DATA06       0x120 0x434 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_DA3__IPU2_CSI1_DATA06        0x120 0x434 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_DA3__GPIO3_IO03              0x120 0x434 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_DA3__SRC_BOOT_CFG03          0x120 0x434 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_DA4__EIM_AD04                0x124 0x438 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DATA05       0x124 0x438 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_DA4__IPU2_CSI1_DATA05        0x124 0x438 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_DA4__GPIO3_IO04              0x124 0x438 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_DA4__SRC_BOOT_CFG04          0x124 0x438 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_DA5__EIM_AD05                0x128 0x43c 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DATA04       0x128 0x43c 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_DA5__IPU2_CSI1_DATA04        0x128 0x43c 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_DA5__GPIO3_IO05              0x128 0x43c 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_DA5__SRC_BOOT_CFG05          0x128 0x43c 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_DA6__EIM_AD06                0x12c 0x440 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DATA03       0x12c 0x440 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_DA6__IPU2_CSI1_DATA03        0x12c 0x440 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_DA6__GPIO3_IO06              0x12c 0x440 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_DA6__SRC_BOOT_CFG06          0x12c 0x440 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_DA7__EIM_AD07                0x130 0x444 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DATA02       0x130 0x444 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_DA7__IPU2_CSI1_DATA02        0x130 0x444 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_DA7__GPIO3_IO07              0x130 0x444 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_DA7__SRC_BOOT_CFG07          0x130 0x444 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_DA8__EIM_AD08                0x134 0x448 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DATA01       0x134 0x448 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_DA8__IPU2_CSI1_DATA01        0x134 0x448 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_DA8__GPIO3_IO08              0x134 0x448 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_DA8__SRC_BOOT_CFG08          0x134 0x448 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_DA9__EIM_AD09                0x138 0x44c 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DATA00       0x138 0x44c 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_DA9__IPU2_CSI1_DATA00        0x138 0x44c 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_DA9__GPIO3_IO09              0x138 0x44c 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_DA9__SRC_BOOT_CFG09          0x138 0x44c 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_DA10__EIM_AD10               0x13c 0x450 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15         0x13c 0x450 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN      0x13c 0x450 0x8d8 0x2 0x1
+#define MX6Q_PAD_EIM_DA10__GPIO3_IO10             0x13c 0x450 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_DA10__SRC_BOOT_CFG10         0x13c 0x450 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_DA11__EIM_AD11               0x140 0x454 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN02         0x140 0x454 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC        0x140 0x454 0x8dc 0x2 0x1
+#define MX6Q_PAD_EIM_DA11__GPIO3_IO11             0x140 0x454 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_DA11__SRC_BOOT_CFG11         0x140 0x454 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_DA12__EIM_AD12               0x144 0x458 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN03         0x144 0x458 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC        0x144 0x458 0x8e4 0x2 0x1
+#define MX6Q_PAD_EIM_DA12__GPIO3_IO12             0x144 0x458 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_DA12__SRC_BOOT_CFG12         0x144 0x458 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_DA13__EIM_AD13               0x148 0x45c 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS         0x148 0x45c 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_DA13__GPIO3_IO13             0x148 0x45c 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_DA13__SRC_BOOT_CFG13         0x148 0x45c 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_DA14__EIM_AD14               0x14c 0x460 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS         0x14c 0x460 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_DA14__GPIO3_IO14             0x14c 0x460 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_DA14__SRC_BOOT_CFG14         0x14c 0x460 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_DA15__EIM_AD15               0x150 0x464 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN01         0x150 0x464 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN04         0x150 0x464 0x000 0x2 0x0
+#define MX6Q_PAD_EIM_DA15__GPIO3_IO15             0x150 0x464 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_DA15__SRC_BOOT_CFG15         0x150 0x464 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_WAIT__EIM_WAIT_B             0x154 0x468 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_WAIT__EIM_DTACK_B            0x154 0x468 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_WAIT__GPIO5_IO00             0x154 0x468 0x000 0x5 0x0
+#define MX6Q_PAD_EIM_WAIT__SRC_BOOT_CFG25         0x154 0x468 0x000 0x7 0x0
+#define MX6Q_PAD_EIM_BCLK__EIM_BCLK               0x158 0x46c 0x000 0x0 0x0
+#define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16         0x158 0x46c 0x000 0x1 0x0
+#define MX6Q_PAD_EIM_BCLK__GPIO6_IO31             0x158 0x46c 0x000 0x5 0x0
+#define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK  0x15c 0x470 0x000 0x0 0x0
+#define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK  0x15c 0x470 0x000 0x1 0x0
+#define MX6Q_PAD_DI0_DISP_CLK__GPIO4_IO16         0x15c 0x470 0x000 0x5 0x0
+#define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15        0x160 0x474 0x000 0x0 0x0
+#define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15        0x160 0x474 0x000 0x1 0x0
+#define MX6Q_PAD_DI0_PIN15__AUD6_TXC              0x160 0x474 0x000 0x2 0x0
+#define MX6Q_PAD_DI0_PIN15__GPIO4_IO17            0x160 0x474 0x000 0x5 0x0
+#define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN02         0x164 0x478 0x000 0x0 0x0
+#define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN02         0x164 0x478 0x000 0x1 0x0
+#define MX6Q_PAD_DI0_PIN2__AUD6_TXD               0x164 0x478 0x000 0x2 0x0
+#define MX6Q_PAD_DI0_PIN2__GPIO4_IO18             0x164 0x478 0x000 0x5 0x0
+#define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN03         0x168 0x47c 0x000 0x0 0x0
+#define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN03         0x168 0x47c 0x000 0x1 0x0
+#define MX6Q_PAD_DI0_PIN3__AUD6_TXFS              0x168 0x47c 0x000 0x2 0x0
+#define MX6Q_PAD_DI0_PIN3__GPIO4_IO19             0x168 0x47c 0x000 0x5 0x0
+#define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN04         0x16c 0x480 0x000 0x0 0x0
+#define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN04         0x16c 0x480 0x000 0x1 0x0
+#define MX6Q_PAD_DI0_PIN4__AUD6_RXD               0x16c 0x480 0x000 0x2 0x0
+#define MX6Q_PAD_DI0_PIN4__SD1_WP                 0x16c 0x480 0x94c 0x3 0x0
+#define MX6Q_PAD_DI0_PIN4__GPIO4_IO20             0x16c 0x480 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DATA00    0x170 0x484 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DATA00    0x170 0x484 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK          0x170 0x484 0x000 0x2 0x0
+#define MX6Q_PAD_DISP0_DAT0__GPIO4_IO21           0x170 0x484 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DATA01    0x174 0x488 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DATA01    0x174 0x488 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI          0x174 0x488 0x000 0x2 0x0
+#define MX6Q_PAD_DISP0_DAT1__GPIO4_IO22           0x174 0x488 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DATA02    0x178 0x48c 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DATA02    0x178 0x48c 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO          0x178 0x48c 0x000 0x2 0x0
+#define MX6Q_PAD_DISP0_DAT2__GPIO4_IO23           0x178 0x48c 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DATA03    0x17c 0x490 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DATA03    0x17c 0x490 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0           0x17c 0x490 0x000 0x2 0x0
+#define MX6Q_PAD_DISP0_DAT3__GPIO4_IO24           0x17c 0x490 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DATA04    0x180 0x494 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DATA04    0x180 0x494 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1           0x180 0x494 0x000 0x2 0x0
+#define MX6Q_PAD_DISP0_DAT4__GPIO4_IO25           0x180 0x494 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DATA05    0x184 0x498 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DATA05    0x184 0x498 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2           0x184 0x498 0x000 0x2 0x0
+#define MX6Q_PAD_DISP0_DAT5__AUD6_RXFS            0x184 0x498 0x000 0x3 0x0
+#define MX6Q_PAD_DISP0_DAT5__GPIO4_IO26           0x184 0x498 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DATA06    0x188 0x49c 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DATA06    0x188 0x49c 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3           0x188 0x49c 0x000 0x2 0x0
+#define MX6Q_PAD_DISP0_DAT6__AUD6_RXC             0x188 0x49c 0x000 0x3 0x0
+#define MX6Q_PAD_DISP0_DAT6__GPIO4_IO27           0x188 0x49c 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DATA07    0x18c 0x4a0 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DATA07    0x18c 0x4a0 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY           0x18c 0x4a0 0x000 0x2 0x0
+#define MX6Q_PAD_DISP0_DAT7__GPIO4_IO28           0x18c 0x4a0 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DATA08    0x190 0x4a4 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DATA08    0x190 0x4a4 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT8__PWM1_OUT             0x190 0x4a4 0x000 0x2 0x0
+#define MX6Q_PAD_DISP0_DAT8__WDOG1_B              0x190 0x4a4 0x000 0x3 0x0
+#define MX6Q_PAD_DISP0_DAT8__GPIO4_IO29           0x190 0x4a4 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DATA09    0x194 0x4a8 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DATA09    0x194 0x4a8 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT9__PWM2_OUT             0x194 0x4a8 0x000 0x2 0x0
+#define MX6Q_PAD_DISP0_DAT9__WDOG2_B              0x194 0x4a8 0x000 0x3 0x0
+#define MX6Q_PAD_DISP0_DAT9__GPIO4_IO30           0x194 0x4a8 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DATA10   0x198 0x4ac 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DATA10   0x198 0x4ac 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT10__GPIO4_IO31          0x198 0x4ac 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DATA11   0x19c 0x4b0 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DATA11   0x19c 0x4b0 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT11__GPIO5_IO05          0x19c 0x4b0 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DATA12   0x1a0 0x4b4 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DATA12   0x1a0 0x4b4 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT12__GPIO5_IO06          0x1a0 0x4b4 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DATA13   0x1a4 0x4b8 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DATA13   0x1a4 0x4b8 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT13__AUD5_RXFS           0x1a4 0x4b8 0x7d8 0x3 0x1
+#define MX6Q_PAD_DISP0_DAT13__GPIO5_IO07          0x1a4 0x4b8 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DATA14   0x1a8 0x4bc 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DATA14   0x1a8 0x4bc 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT14__AUD5_RXC            0x1a8 0x4bc 0x7d4 0x3 0x1
+#define MX6Q_PAD_DISP0_DAT14__GPIO5_IO08          0x1a8 0x4bc 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DATA15   0x1ac 0x4c0 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DATA15   0x1ac 0x4c0 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1          0x1ac 0x4c0 0x804 0x2 0x1
+#define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1          0x1ac 0x4c0 0x820 0x3 0x1
+#define MX6Q_PAD_DISP0_DAT15__GPIO5_IO09          0x1ac 0x4c0 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DATA16   0x1b0 0x4c4 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DATA16   0x1b0 0x4c4 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI         0x1b0 0x4c4 0x818 0x2 0x1
+#define MX6Q_PAD_DISP0_DAT16__AUD5_TXC            0x1b0 0x4c4 0x7dc 0x3 0x0
+#define MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT0     0x1b0 0x4c4 0x90c 0x4 0x0
+#define MX6Q_PAD_DISP0_DAT16__GPIO5_IO10          0x1b0 0x4c4 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DATA17   0x1b4 0x4c8 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DATA17   0x1b4 0x4c8 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO         0x1b4 0x4c8 0x814 0x2 0x1
+#define MX6Q_PAD_DISP0_DAT17__AUD5_TXD            0x1b4 0x4c8 0x7d0 0x3 0x0
+#define MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT1     0x1b4 0x4c8 0x910 0x4 0x0
+#define MX6Q_PAD_DISP0_DAT17__GPIO5_IO11          0x1b4 0x4c8 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DATA18   0x1b8 0x4cc 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DATA18   0x1b8 0x4cc 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0          0x1b8 0x4cc 0x81c 0x2 0x1
+#define MX6Q_PAD_DISP0_DAT18__AUD5_TXFS           0x1b8 0x4cc 0x7e0 0x3 0x0
+#define MX6Q_PAD_DISP0_DAT18__AUD4_RXFS           0x1b8 0x4cc 0x7c0 0x4 0x0
+#define MX6Q_PAD_DISP0_DAT18__GPIO5_IO12          0x1b8 0x4cc 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT18__EIM_CS2_B           0x1b8 0x4cc 0x000 0x7 0x0
+#define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DATA19   0x1bc 0x4d0 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DATA19   0x1bc 0x4d0 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK         0x1bc 0x4d0 0x810 0x2 0x1
+#define MX6Q_PAD_DISP0_DAT19__AUD5_RXD            0x1bc 0x4d0 0x7cc 0x3 0x0
+#define MX6Q_PAD_DISP0_DAT19__AUD4_RXC            0x1bc 0x4d0 0x7bc 0x4 0x0
+#define MX6Q_PAD_DISP0_DAT19__GPIO5_IO13          0x1bc 0x4d0 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT19__EIM_CS3_B           0x1bc 0x4d0 0x000 0x7 0x0
+#define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DATA20   0x1c0 0x4d4 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DATA20   0x1c0 0x4d4 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK         0x1c0 0x4d4 0x7f4 0x2 0x1
+#define MX6Q_PAD_DISP0_DAT20__AUD4_TXC            0x1c0 0x4d4 0x7c4 0x3 0x0
+#define MX6Q_PAD_DISP0_DAT20__GPIO5_IO14          0x1c0 0x4d4 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DATA21   0x1c4 0x4d8 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DATA21   0x1c4 0x4d8 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI         0x1c4 0x4d8 0x7fc 0x2 0x1
+#define MX6Q_PAD_DISP0_DAT21__AUD4_TXD            0x1c4 0x4d8 0x7b8 0x3 0x1
+#define MX6Q_PAD_DISP0_DAT21__GPIO5_IO15          0x1c4 0x4d8 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DATA22   0x1c8 0x4dc 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DATA22   0x1c8 0x4dc 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO         0x1c8 0x4dc 0x7f8 0x2 0x1
+#define MX6Q_PAD_DISP0_DAT22__AUD4_TXFS           0x1c8 0x4dc 0x7c8 0x3 0x1
+#define MX6Q_PAD_DISP0_DAT22__GPIO5_IO16          0x1c8 0x4dc 0x000 0x5 0x0
+#define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DATA23   0x1cc 0x4e0 0x000 0x0 0x0
+#define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DATA23   0x1cc 0x4e0 0x000 0x1 0x0
+#define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0          0x1cc 0x4e0 0x800 0x2 0x1
+#define MX6Q_PAD_DISP0_DAT23__AUD4_RXD            0x1cc 0x4e0 0x7b4 0x3 0x1
+#define MX6Q_PAD_DISP0_DAT23__GPIO5_IO17          0x1cc 0x4e0 0x000 0x5 0x0
+#define MX6Q_PAD_ENET_MDIO__ENET_MDIO             0x1d0 0x4e4 0x840 0x1 0x0
+#define MX6Q_PAD_ENET_MDIO__ESAI_RX_CLK           0x1d0 0x4e4 0x86c 0x2 0x0
+#define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT  0x1d0 0x4e4 0x000 0x4 0x0
+#define MX6Q_PAD_ENET_MDIO__GPIO1_IO22            0x1d0 0x4e4 0x000 0x5 0x0
+#define MX6Q_PAD_ENET_MDIO__SPDIF_LOCK            0x1d0 0x4e4 0x000 0x6 0x0
+#define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK        0x1d4 0x4e8 0x000 0x1 0x0
+#define MX6Q_PAD_ENET_REF_CLK__ESAI_RX_FS         0x1d4 0x4e8 0x85c 0x2 0x0
+#define MX6Q_PAD_ENET_REF_CLK__GPIO1_IO23         0x1d4 0x4e8 0x000 0x5 0x0
+#define MX6Q_PAD_ENET_REF_CLK__SPDIF_SR_CLK       0x1d4 0x4e8 0x000 0x6 0x0
+#define MX6Q_PAD_ENET_RX_ER__USB_OTG_ID           0x1d8 0x4ec 0x000 0x0 0x0
+#define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER           0x1d8 0x4ec 0x000 0x1 0x0
+#define MX6Q_PAD_ENET_RX_ER__ESAI_RX_HF_CLK       0x1d8 0x4ec 0x864 0x2 0x0
+#define MX6Q_PAD_ENET_RX_ER__SPDIF_IN             0x1d8 0x4ec 0x914 0x3 0x1
+#define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0
+#define MX6Q_PAD_ENET_RX_ER__GPIO1_IO24           0x1d8 0x4ec 0x000 0x5 0x0
+#define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN          0x1dc 0x4f0 0x858 0x1 0x1
+#define MX6Q_PAD_ENET_CRS_DV__ESAI_TX_CLK         0x1dc 0x4f0 0x870 0x2 0x0
+#define MX6Q_PAD_ENET_CRS_DV__SPDIF_EXT_CLK       0x1dc 0x4f0 0x918 0x3 0x1
+#define MX6Q_PAD_ENET_CRS_DV__GPIO1_IO25          0x1dc 0x4f0 0x000 0x5 0x0
+#define MX6Q_PAD_ENET_RXD1__MLB_SIG               0x1e0 0x4f4 0x908 0x0 0x0
+#define MX6Q_PAD_ENET_RXD1__ENET_RX_DATA1         0x1e0 0x4f4 0x84c 0x1 0x1
+#define MX6Q_PAD_ENET_RXD1__ESAI_TX_FS            0x1e0 0x4f4 0x860 0x2 0x0
+#define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT  0x1e0 0x4f4 0x000 0x4 0x0
+#define MX6Q_PAD_ENET_RXD1__GPIO1_IO26            0x1e0 0x4f4 0x000 0x5 0x0
+#define MX6Q_PAD_ENET_RXD0__ENET_RX_DATA0         0x1e4 0x4f8 0x848 0x1 0x1
+#define MX6Q_PAD_ENET_RXD0__ESAI_TX_HF_CLK        0x1e4 0x4f8 0x868 0x2 0x0
+#define MX6Q_PAD_ENET_RXD0__SPDIF_OUT             0x1e4 0x4f8 0x000 0x3 0x0
+#define MX6Q_PAD_ENET_RXD0__GPIO1_IO27            0x1e4 0x4f8 0x000 0x5 0x0
+#define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN           0x1e8 0x4fc 0x000 0x1 0x0
+#define MX6Q_PAD_ENET_TX_EN__ESAI_TX3_RX2         0x1e8 0x4fc 0x880 0x2 0x0
+#define MX6Q_PAD_ENET_TX_EN__GPIO1_IO28           0x1e8 0x4fc 0x000 0x5 0x0
+#define MX6Q_PAD_ENET_TXD1__MLB_CLK               0x1ec 0x500 0x900 0x0 0x0
+#define MX6Q_PAD_ENET_TXD1__ENET_TX_DATA1         0x1ec 0x500 0x000 0x1 0x0
+#define MX6Q_PAD_ENET_TXD1__ESAI_TX2_RX3          0x1ec 0x500 0x87c 0x2 0x0
+#define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN   0x1ec 0x500 0x000 0x4 0x0
+#define MX6Q_PAD_ENET_TXD1__GPIO1_IO29            0x1ec 0x500 0x000 0x5 0x0
+#define MX6Q_PAD_ENET_TXD0__ENET_TX_DATA0         0x1f0 0x504 0x000 0x1 0x0
+#define MX6Q_PAD_ENET_TXD0__ESAI_TX4_RX1          0x1f0 0x504 0x884 0x2 0x0
+#define MX6Q_PAD_ENET_TXD0__GPIO1_IO30            0x1f0 0x504 0x000 0x5 0x0
+#define MX6Q_PAD_ENET_MDC__MLB_DATA               0x1f4 0x508 0x904 0x0 0x0
+#define MX6Q_PAD_ENET_MDC__ENET_MDC               0x1f4 0x508 0x000 0x1 0x0
+#define MX6Q_PAD_ENET_MDC__ESAI_TX5_RX0           0x1f4 0x508 0x888 0x2 0x0
+#define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN    0x1f4 0x508 0x000 0x4 0x0
+#define MX6Q_PAD_ENET_MDC__GPIO1_IO31             0x1f4 0x508 0x000 0x5 0x0
+#define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK            0x1f8 0x5c8 0x7f4 0x0 0x2
+#define MX6Q_PAD_KEY_COL0__ENET_RX_DATA3          0x1f8 0x5c8 0x854 0x1 0x1
+#define MX6Q_PAD_KEY_COL0__AUD5_TXC               0x1f8 0x5c8 0x7dc 0x2 0x1
+#define MX6Q_PAD_KEY_COL0__KEY_COL0               0x1f8 0x5c8 0x000 0x3 0x0
+#define MX6Q_PAD_KEY_COL0__UART4_TX_DATA          0x1f8 0x5c8 0x000 0x4 0x0
+#define MX6Q_PAD_KEY_COL0__UART4_RX_DATA          0x1f8 0x5c8 0x938 0x4 0x0
+#define MX6Q_PAD_KEY_COL0__GPIO4_IO06             0x1f8 0x5c8 0x000 0x5 0x0
+#define MX6Q_PAD_KEY_COL0__DCIC1_OUT              0x1f8 0x5c8 0x000 0x6 0x0
+#define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI            0x1fc 0x5cc 0x7fc 0x0 0x2
+#define MX6Q_PAD_KEY_ROW0__ENET_TX_DATA3          0x1fc 0x5cc 0x000 0x1 0x0
+#define MX6Q_PAD_KEY_ROW0__AUD5_TXD               0x1fc 0x5cc 0x7d0 0x2 0x1
+#define MX6Q_PAD_KEY_ROW0__KEY_ROW0               0x1fc 0x5cc 0x000 0x3 0x0
+#define MX6Q_PAD_KEY_ROW0__UART4_RX_DATA          0x1fc 0x5cc 0x938 0x4 0x1
+#define MX6Q_PAD_KEY_ROW0__UART4_TX_DATA          0x1fc 0x5cc 0x000 0x4 0x0
+#define MX6Q_PAD_KEY_ROW0__GPIO4_IO07             0x1fc 0x5cc 0x000 0x5 0x0
+#define MX6Q_PAD_KEY_ROW0__DCIC2_OUT              0x1fc 0x5cc 0x000 0x6 0x0
+#define MX6Q_PAD_KEY_COL1__ECSPI1_MISO            0x200 0x5d0 0x7f8 0x0 0x2
+#define MX6Q_PAD_KEY_COL1__ENET_MDIO              0x200 0x5d0 0x840 0x1 0x1
+#define MX6Q_PAD_KEY_COL1__AUD5_TXFS              0x200 0x5d0 0x7e0 0x2 0x1
+#define MX6Q_PAD_KEY_COL1__KEY_COL1               0x200 0x5d0 0x000 0x3 0x0
+#define MX6Q_PAD_KEY_COL1__UART5_TX_DATA          0x200 0x5d0 0x000 0x4 0x0
+#define MX6Q_PAD_KEY_COL1__UART5_RX_DATA          0x200 0x5d0 0x940 0x4 0x0
+#define MX6Q_PAD_KEY_COL1__GPIO4_IO08             0x200 0x5d0 0x000 0x5 0x0
+#define MX6Q_PAD_KEY_COL1__SD1_VSELECT            0x200 0x5d0 0x000 0x6 0x0
+#define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0             0x204 0x5d4 0x800 0x0 0x2
+#define MX6Q_PAD_KEY_ROW1__ENET_COL               0x204 0x5d4 0x000 0x1 0x0
+#define MX6Q_PAD_KEY_ROW1__AUD5_RXD               0x204 0x5d4 0x7cc 0x2 0x1
+#define MX6Q_PAD_KEY_ROW1__KEY_ROW1               0x204 0x5d4 0x000 0x3 0x0
+#define MX6Q_PAD_KEY_ROW1__UART5_RX_DATA          0x204 0x5d4 0x940 0x4 0x1
+#define MX6Q_PAD_KEY_ROW1__UART5_TX_DATA          0x204 0x5d4 0x000 0x4 0x0
+#define MX6Q_PAD_KEY_ROW1__GPIO4_IO09             0x204 0x5d4 0x000 0x5 0x0
+#define MX6Q_PAD_KEY_ROW1__SD2_VSELECT            0x204 0x5d4 0x000 0x6 0x0
+#define MX6Q_PAD_KEY_COL2__ECSPI1_SS1             0x208 0x5d8 0x804 0x0 0x2
+#define MX6Q_PAD_KEY_COL2__ENET_RX_DATA2          0x208 0x5d8 0x850 0x1 0x1
+#define MX6Q_PAD_KEY_COL2__FLEXCAN1_TX            0x208 0x5d8 0x000 0x2 0x0
+#define MX6Q_PAD_KEY_COL2__KEY_COL2               0x208 0x5d8 0x000 0x3 0x0
+#define MX6Q_PAD_KEY_COL2__ENET_MDC               0x208 0x5d8 0x000 0x4 0x0
+#define MX6Q_PAD_KEY_COL2__GPIO4_IO10             0x208 0x5d8 0x000 0x5 0x0
+#define MX6Q_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE    0x208 0x5d8 0x000 0x6 0x0
+#define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2             0x20c 0x5dc 0x808 0x0 0x1
+#define MX6Q_PAD_KEY_ROW2__ENET_TX_DATA2          0x20c 0x5dc 0x000 0x1 0x0
+#define MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX            0x20c 0x5dc 0x7e4 0x2 0x0
+#define MX6Q_PAD_KEY_ROW2__KEY_ROW2               0x20c 0x5dc 0x000 0x3 0x0
+#define MX6Q_PAD_KEY_ROW2__SD2_VSELECT            0x20c 0x5dc 0x000 0x4 0x0
+#define MX6Q_PAD_KEY_ROW2__GPIO4_IO11             0x20c 0x5dc 0x000 0x5 0x0
+#define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE       0x20c 0x5dc 0x88c 0x6 0x1
+#define MX6Q_PAD_KEY_COL3__ECSPI1_SS3             0x210 0x5e0 0x80c 0x0 0x1
+#define MX6Q_PAD_KEY_COL3__ENET_CRS               0x210 0x5e0 0x000 0x1 0x0
+#define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL        0x210 0x5e0 0x890 0x2 0x1
+#define MX6Q_PAD_KEY_COL3__KEY_COL3               0x210 0x5e0 0x000 0x3 0x0
+#define MX6Q_PAD_KEY_COL3__I2C2_SCL               0x210 0x5e0 0x8a0 0x4 0x1
+#define MX6Q_PAD_KEY_COL3__GPIO4_IO12             0x210 0x5e0 0x000 0x5 0x0
+#define MX6Q_PAD_KEY_COL3__SPDIF_IN               0x210 0x5e0 0x914 0x6 0x2
+#define MX6Q_PAD_KEY_ROW3__ASRC_EXT_CLK           0x214 0x5e4 0x7b0 0x1 0x0
+#define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA        0x214 0x5e4 0x894 0x2 0x1
+#define MX6Q_PAD_KEY_ROW3__KEY_ROW3               0x214 0x5e4 0x000 0x3 0x0
+#define MX6Q_PAD_KEY_ROW3__I2C2_SDA               0x214 0x5e4 0x8a4 0x4 0x1
+#define MX6Q_PAD_KEY_ROW3__GPIO4_IO13             0x214 0x5e4 0x000 0x5 0x0
+#define MX6Q_PAD_KEY_ROW3__SD1_VSELECT            0x214 0x5e4 0x000 0x6 0x0
+#define MX6Q_PAD_KEY_COL4__FLEXCAN2_TX            0x218 0x5e8 0x000 0x0 0x0
+#define MX6Q_PAD_KEY_COL4__IPU1_SISG4             0x218 0x5e8 0x000 0x1 0x0
+#define MX6Q_PAD_KEY_COL4__USB_OTG_OC             0x218 0x5e8 0x944 0x2 0x1
+#define MX6Q_PAD_KEY_COL4__KEY_COL4               0x218 0x5e8 0x000 0x3 0x0
+#define MX6Q_PAD_KEY_COL4__UART5_RTS_B            0x218 0x5e8 0x93c 0x4 0x0
+#define MX6Q_PAD_KEY_COL4__UART5_CTS_B            0x218 0x5e8 0x000 0x4 0x0
+#define MX6Q_PAD_KEY_COL4__GPIO4_IO14             0x218 0x5e8 0x000 0x5 0x0
+#define MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX            0x21c 0x5ec 0x7e8 0x0 0x0
+#define MX6Q_PAD_KEY_ROW4__IPU1_SISG5             0x21c 0x5ec 0x000 0x1 0x0
+#define MX6Q_PAD_KEY_ROW4__USB_OTG_PWR            0x21c 0x5ec 0x000 0x2 0x0
+#define MX6Q_PAD_KEY_ROW4__KEY_ROW4               0x21c 0x5ec 0x000 0x3 0x0
+#define MX6Q_PAD_KEY_ROW4__UART5_CTS_B            0x21c 0x5ec 0x000 0x4 0x0
+#define MX6Q_PAD_KEY_ROW4__UART5_RTS_B            0x21c 0x5ec 0x93c 0x4 0x1
+#define MX6Q_PAD_KEY_ROW4__GPIO4_IO15             0x21c 0x5ec 0x000 0x5 0x0
+#define MX6Q_PAD_GPIO_0__CCM_CLKO1                0x220 0x5f0 0x000 0x0 0x0
+#define MX6Q_PAD_GPIO_0__KEY_COL5                 0x220 0x5f0 0x8e8 0x2 0x0
+#define MX6Q_PAD_GPIO_0__ASRC_EXT_CLK             0x220 0x5f0 0x7b0 0x3 0x1
+#define MX6Q_PAD_GPIO_0__EPIT1_OUT                0x220 0x5f0 0x000 0x4 0x0
+#define MX6Q_PAD_GPIO_0__GPIO1_IO00               0x220 0x5f0 0x000 0x5 0x0
+#define MX6Q_PAD_GPIO_0__USB_H1_PWR               0x220 0x5f0 0x000 0x6 0x0
+#define MX6Q_PAD_GPIO_0__SNVS_VIO_5               0x220 0x5f0 0x000 0x7 0x0
+#define MX6Q_PAD_GPIO_1__ESAI_RX_CLK              0x224 0x5f4 0x86c 0x0 0x1
+#define MX6Q_PAD_GPIO_1__WDOG2_B                  0x224 0x5f4 0x000 0x1 0x0
+#define MX6Q_PAD_GPIO_1__KEY_ROW5                 0x224 0x5f4 0x8f4 0x2 0x0
+#define MX6Q_PAD_GPIO_1__USB_OTG_ID               0x224 0x5f4 0x000 0x3 0x0
+#define MX6Q_PAD_GPIO_1__PWM2_OUT                 0x224 0x5f4 0x000 0x4 0x0
+#define MX6Q_PAD_GPIO_1__GPIO1_IO01               0x224 0x5f4 0x000 0x5 0x0
+#define MX6Q_PAD_GPIO_1__SD1_CD_B                 0x224 0x5f4 0x000 0x6 0x0
+#define MX6Q_PAD_GPIO_9__ESAI_RX_FS               0x228 0x5f8 0x85c 0x0 0x1
+#define MX6Q_PAD_GPIO_9__WDOG1_B                  0x228 0x5f8 0x000 0x1 0x0
+#define MX6Q_PAD_GPIO_9__KEY_COL6                 0x228 0x5f8 0x8ec 0x2 0x0
+#define MX6Q_PAD_GPIO_9__CCM_REF_EN_B             0x228 0x5f8 0x000 0x3 0x0
+#define MX6Q_PAD_GPIO_9__PWM1_OUT                 0x228 0x5f8 0x000 0x4 0x0
+#define MX6Q_PAD_GPIO_9__GPIO1_IO09               0x228 0x5f8 0x000 0x5 0x0
+#define MX6Q_PAD_GPIO_9__SD1_WP                   0x228 0x5f8 0x94c 0x6 0x1
+#define MX6Q_PAD_GPIO_3__ESAI_RX_HF_CLK           0x22c 0x5fc 0x864 0x0 0x1
+#define MX6Q_PAD_GPIO_3__I2C3_SCL                 0x22c 0x5fc 0x8a8 0x2 0x1
+#define MX6Q_PAD_GPIO_3__XTALOSC_REF_CLK_24M      0x22c 0x5fc 0x000 0x3 0x0
+#define MX6Q_PAD_GPIO_3__CCM_CLKO2                0x22c 0x5fc 0x000 0x4 0x0
+#define MX6Q_PAD_GPIO_3__GPIO1_IO03               0x22c 0x5fc 0x000 0x5 0x0
+#define MX6Q_PAD_GPIO_3__USB_H1_OC                0x22c 0x5fc 0x948 0x6 0x1
+#define MX6Q_PAD_GPIO_3__MLB_CLK                  0x22c 0x5fc 0x900 0x7 0x1
+#define MX6Q_PAD_GPIO_6__ESAI_TX_CLK              0x230 0x600 0x870 0x0 0x1
+#define MX6Q_PAD_GPIO_6__I2C3_SDA                 0x230 0x600 0x8ac 0x2 0x1
+#define MX6Q_PAD_GPIO_6__GPIO1_IO06               0x230 0x600 0x000 0x5 0x0
+#define MX6Q_PAD_GPIO_6__SD2_LCTL                 0x230 0x600 0x000 0x6 0x0
+#define MX6Q_PAD_GPIO_6__MLB_SIG                  0x230 0x600 0x908 0x7 0x1
+#define MX6Q_PAD_GPIO_2__ESAI_TX_FS               0x234 0x604 0x860 0x0 0x1
+#define MX6Q_PAD_GPIO_2__KEY_ROW6                 0x234 0x604 0x8f8 0x2 0x1
+#define MX6Q_PAD_GPIO_2__GPIO1_IO02               0x234 0x604 0x000 0x5 0x0
+#define MX6Q_PAD_GPIO_2__SD2_WP                   0x234 0x604 0x000 0x6 0x0
+#define MX6Q_PAD_GPIO_2__MLB_DATA                 0x234 0x604 0x904 0x7 0x1
+#define MX6Q_PAD_GPIO_4__ESAI_TX_HF_CLK           0x238 0x608 0x868 0x0 0x1
+#define MX6Q_PAD_GPIO_4__KEY_COL7                 0x238 0x608 0x8f0 0x2 0x1
+#define MX6Q_PAD_GPIO_4__GPIO1_IO04               0x238 0x608 0x000 0x5 0x0
+#define MX6Q_PAD_GPIO_4__SD2_CD_B                 0x238 0x608 0x000 0x6 0x0
+#define MX6Q_PAD_GPIO_5__ESAI_TX2_RX3             0x23c 0x60c 0x87c 0x0 0x1
+#define MX6Q_PAD_GPIO_5__KEY_ROW7                 0x23c 0x60c 0x8fc 0x2 0x1
+#define MX6Q_PAD_GPIO_5__CCM_CLKO1                0x23c 0x60c 0x000 0x3 0x0
+#define MX6Q_PAD_GPIO_5__GPIO1_IO05               0x23c 0x60c 0x000 0x5 0x0
+#define MX6Q_PAD_GPIO_5__I2C3_SCL                 0x23c 0x60c 0x8a8 0x6 0x2
+#define MX6Q_PAD_GPIO_5__ARM_EVENTI               0x23c 0x60c 0x000 0x7 0x0
+#define MX6Q_PAD_GPIO_7__ESAI_TX4_RX1             0x240 0x610 0x884 0x0 0x1
+#define MX6Q_PAD_GPIO_7__ECSPI5_RDY               0x240 0x610 0x000 0x1 0x0
+#define MX6Q_PAD_GPIO_7__EPIT1_OUT                0x240 0x610 0x000 0x2 0x0
+#define MX6Q_PAD_GPIO_7__FLEXCAN1_TX              0x240 0x610 0x000 0x3 0x0
+#define MX6Q_PAD_GPIO_7__UART2_TX_DATA            0x240 0x610 0x000 0x4 0x0
+#define MX6Q_PAD_GPIO_7__UART2_RX_DATA            0x240 0x610 0x928 0x4 0x2
+#define MX6Q_PAD_GPIO_7__GPIO1_IO07               0x240 0x610 0x000 0x5 0x0
+#define MX6Q_PAD_GPIO_7__SPDIF_LOCK               0x240 0x610 0x000 0x6 0x0
+#define MX6Q_PAD_GPIO_7__USB_OTG_HOST_MODE        0x240 0x610 0x000 0x7 0x0
+#define MX6Q_PAD_GPIO_8__ESAI_TX5_RX0             0x244 0x614 0x888 0x0 0x1
+#define MX6Q_PAD_GPIO_8__XTALOSC_REF_CLK_32K      0x244 0x614 0x000 0x1 0x0
+#define MX6Q_PAD_GPIO_8__EPIT2_OUT                0x244 0x614 0x000 0x2 0x0
+#define MX6Q_PAD_GPIO_8__FLEXCAN1_RX              0x244 0x614 0x7e4 0x3 0x1
+#define MX6Q_PAD_GPIO_8__UART2_RX_DATA            0x244 0x614 0x928 0x4 0x3
+#define MX6Q_PAD_GPIO_8__UART2_TX_DATA            0x244 0x614 0x000 0x4 0x0
+#define MX6Q_PAD_GPIO_8__GPIO1_IO08               0x244 0x614 0x000 0x5 0x0
+#define MX6Q_PAD_GPIO_8__SPDIF_SR_CLK             0x244 0x614 0x000 0x6 0x0
+#define MX6Q_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE     0x244 0x614 0x000 0x7 0x0
+#define MX6Q_PAD_GPIO_16__ESAI_TX3_RX2            0x248 0x618 0x880 0x0 0x1
+#define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN     0x248 0x618 0x000 0x1 0x0
+#define MX6Q_PAD_GPIO_16__ENET_REF_CLK            0x248 0x618 0x83c 0x2 0x1
+#define MX6Q_PAD_GPIO_16__SD1_LCTL                0x248 0x618 0x000 0x3 0x0
+#define MX6Q_PAD_GPIO_16__SPDIF_IN                0x248 0x618 0x914 0x4 0x3
+#define MX6Q_PAD_GPIO_16__GPIO7_IO11              0x248 0x618 0x000 0x5 0x0
+#define MX6Q_PAD_GPIO_16__I2C3_SDA                0x248 0x618 0x8ac 0x6 0x2
+#define MX6Q_PAD_GPIO_16__JTAG_DE_B               0x248 0x618 0x000 0x7 0x0
+#define MX6Q_PAD_GPIO_17__ESAI_TX0                0x24c 0x61c 0x874 0x0 0x0
+#define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN     0x24c 0x61c 0x000 0x1 0x0
+#define MX6Q_PAD_GPIO_17__CCM_PMIC_READY          0x24c 0x61c 0x7f0 0x2 0x1
+#define MX6Q_PAD_GPIO_17__SDMA_EXT_EVENT0         0x24c 0x61c 0x90c 0x3 0x1
+#define MX6Q_PAD_GPIO_17__SPDIF_OUT               0x24c 0x61c 0x000 0x4 0x0
+#define MX6Q_PAD_GPIO_17__GPIO7_IO12              0x24c 0x61c 0x000 0x5 0x0
+#define MX6Q_PAD_GPIO_18__ESAI_TX1                0x250 0x620 0x878 0x0 0x0
+#define MX6Q_PAD_GPIO_18__ENET_RX_CLK             0x250 0x620 0x844 0x1 0x1
+#define MX6Q_PAD_GPIO_18__SD3_VSELECT             0x250 0x620 0x000 0x2 0x0
+#define MX6Q_PAD_GPIO_18__SDMA_EXT_EVENT1         0x250 0x620 0x910 0x3 0x1
+#define MX6Q_PAD_GPIO_18__ASRC_EXT_CLK            0x250 0x620 0x7b0 0x4 0x2
+#define MX6Q_PAD_GPIO_18__GPIO7_IO13              0x250 0x620 0x000 0x5 0x0
+#define MX6Q_PAD_GPIO_18__SNVS_VIO_5_CTL          0x250 0x620 0x000 0x6 0x0
+#define MX6Q_PAD_GPIO_19__KEY_COL5                0x254 0x624 0x8e8 0x0 0x1
+#define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT    0x254 0x624 0x000 0x1 0x0
+#define MX6Q_PAD_GPIO_19__SPDIF_OUT               0x254 0x624 0x000 0x2 0x0
+#define MX6Q_PAD_GPIO_19__CCM_CLKO1               0x254 0x624 0x000 0x3 0x0
+#define MX6Q_PAD_GPIO_19__ECSPI1_RDY              0x254 0x624 0x000 0x4 0x0
+#define MX6Q_PAD_GPIO_19__GPIO4_IO05              0x254 0x624 0x000 0x5 0x0
+#define MX6Q_PAD_GPIO_19__ENET_TX_ER              0x254 0x624 0x000 0x6 0x0
+#define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK    0x258 0x628 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_PIXCLK__GPIO5_IO18          0x258 0x628 0x000 0x5 0x0
+#define MX6Q_PAD_CSI0_PIXCLK__ARM_EVENTO          0x258 0x628 0x000 0x7 0x0
+#define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC       0x25c 0x62c 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_MCLK__CCM_CLKO1             0x25c 0x62c 0x000 0x3 0x0
+#define MX6Q_PAD_CSI0_MCLK__GPIO5_IO19            0x25c 0x62c 0x000 0x5 0x0
+#define MX6Q_PAD_CSI0_MCLK__ARM_TRACE_CTL         0x25c 0x62c 0x000 0x7 0x0
+#define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN  0x260 0x630 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_DATA_EN__EIM_DATA00         0x260 0x630 0x000 0x1 0x0
+#define MX6Q_PAD_CSI0_DATA_EN__GPIO5_IO20         0x260 0x630 0x000 0x5 0x0
+#define MX6Q_PAD_CSI0_DATA_EN__ARM_TRACE_CLK      0x260 0x630 0x000 0x7 0x0
+#define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC      0x264 0x634 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_VSYNC__EIM_DATA01           0x264 0x634 0x000 0x1 0x0
+#define MX6Q_PAD_CSI0_VSYNC__GPIO5_IO21           0x264 0x634 0x000 0x5 0x0
+#define MX6Q_PAD_CSI0_VSYNC__ARM_TRACE00          0x264 0x634 0x000 0x7 0x0
+#define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_DATA04      0x268 0x638 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_DAT4__EIM_DATA02            0x268 0x638 0x000 0x1 0x0
+#define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK           0x268 0x638 0x7f4 0x2 0x3
+#define MX6Q_PAD_CSI0_DAT4__KEY_COL5              0x268 0x638 0x8e8 0x3 0x2
+#define MX6Q_PAD_CSI0_DAT4__AUD3_TXC              0x268 0x638 0x000 0x4 0x0
+#define MX6Q_PAD_CSI0_DAT4__GPIO5_IO22            0x268 0x638 0x000 0x5 0x0
+#define MX6Q_PAD_CSI0_DAT4__ARM_TRACE01           0x268 0x638 0x000 0x7 0x0
+#define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_DATA05      0x26c 0x63c 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_DAT5__EIM_DATA03            0x26c 0x63c 0x000 0x1 0x0
+#define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI           0x26c 0x63c 0x7fc 0x2 0x3
+#define MX6Q_PAD_CSI0_DAT5__KEY_ROW5              0x26c 0x63c 0x8f4 0x3 0x1
+#define MX6Q_PAD_CSI0_DAT5__AUD3_TXD              0x26c 0x63c 0x000 0x4 0x0
+#define MX6Q_PAD_CSI0_DAT5__GPIO5_IO23            0x26c 0x63c 0x000 0x5 0x0
+#define MX6Q_PAD_CSI0_DAT5__ARM_TRACE02           0x26c 0x63c 0x000 0x7 0x0
+#define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_DATA06      0x270 0x640 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_DAT6__EIM_DATA04            0x270 0x640 0x000 0x1 0x0
+#define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO           0x270 0x640 0x7f8 0x2 0x3
+#define MX6Q_PAD_CSI0_DAT6__KEY_COL6              0x270 0x640 0x8ec 0x3 0x1
+#define MX6Q_PAD_CSI0_DAT6__AUD3_TXFS             0x270 0x640 0x000 0x4 0x0
+#define MX6Q_PAD_CSI0_DAT6__GPIO5_IO24            0x270 0x640 0x000 0x5 0x0
+#define MX6Q_PAD_CSI0_DAT6__ARM_TRACE03           0x270 0x640 0x000 0x7 0x0
+#define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_DATA07      0x274 0x644 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_DAT7__EIM_DATA05            0x274 0x644 0x000 0x1 0x0
+#define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0            0x274 0x644 0x800 0x2 0x3
+#define MX6Q_PAD_CSI0_DAT7__KEY_ROW6              0x274 0x644 0x8f8 0x3 0x2
+#define MX6Q_PAD_CSI0_DAT7__AUD3_RXD              0x274 0x644 0x000 0x4 0x0
+#define MX6Q_PAD_CSI0_DAT7__GPIO5_IO25            0x274 0x644 0x000 0x5 0x0
+#define MX6Q_PAD_CSI0_DAT7__ARM_TRACE04           0x274 0x644 0x000 0x7 0x0
+#define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_DATA08      0x278 0x648 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_DAT8__EIM_DATA06            0x278 0x648 0x000 0x1 0x0
+#define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK           0x278 0x648 0x810 0x2 0x2
+#define MX6Q_PAD_CSI0_DAT8__KEY_COL7              0x278 0x648 0x8f0 0x3 0x2
+#define MX6Q_PAD_CSI0_DAT8__I2C1_SDA              0x278 0x648 0x89c 0x4 0x1
+#define MX6Q_PAD_CSI0_DAT8__GPIO5_IO26            0x278 0x648 0x000 0x5 0x0
+#define MX6Q_PAD_CSI0_DAT8__ARM_TRACE05           0x278 0x648 0x000 0x7 0x0
+#define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_DATA09      0x27c 0x64c 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_DAT9__EIM_DATA07            0x27c 0x64c 0x000 0x1 0x0
+#define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI           0x27c 0x64c 0x818 0x2 0x2
+#define MX6Q_PAD_CSI0_DAT9__KEY_ROW7              0x27c 0x64c 0x8fc 0x3 0x2
+#define MX6Q_PAD_CSI0_DAT9__I2C1_SCL              0x27c 0x64c 0x898 0x4 0x1
+#define MX6Q_PAD_CSI0_DAT9__GPIO5_IO27            0x27c 0x64c 0x000 0x5 0x0
+#define MX6Q_PAD_CSI0_DAT9__ARM_TRACE06           0x27c 0x64c 0x000 0x7 0x0
+#define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_DATA10     0x280 0x650 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_DAT10__AUD3_RXC             0x280 0x650 0x000 0x1 0x0
+#define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO          0x280 0x650 0x814 0x2 0x2
+#define MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA        0x280 0x650 0x000 0x3 0x0
+#define MX6Q_PAD_CSI0_DAT10__UART1_RX_DATA        0x280 0x650 0x920 0x3 0x0
+#define MX6Q_PAD_CSI0_DAT10__GPIO5_IO28           0x280 0x650 0x000 0x5 0x0
+#define MX6Q_PAD_CSI0_DAT10__ARM_TRACE07          0x280 0x650 0x000 0x7 0x0
+#define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_DATA11     0x284 0x654 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_DAT11__AUD3_RXFS            0x284 0x654 0x000 0x1 0x0
+#define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0           0x284 0x654 0x81c 0x2 0x2
+#define MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA        0x284 0x654 0x920 0x3 0x1
+#define MX6Q_PAD_CSI0_DAT11__UART1_TX_DATA        0x284 0x654 0x000 0x3 0x0
+#define MX6Q_PAD_CSI0_DAT11__GPIO5_IO29           0x284 0x654 0x000 0x5 0x0
+#define MX6Q_PAD_CSI0_DAT11__ARM_TRACE08          0x284 0x654 0x000 0x7 0x0
+#define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_DATA12     0x288 0x658 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_DAT12__EIM_DATA08           0x288 0x658 0x000 0x1 0x0
+#define MX6Q_PAD_CSI0_DAT12__UART4_TX_DATA        0x288 0x658 0x000 0x3 0x0
+#define MX6Q_PAD_CSI0_DAT12__UART4_RX_DATA        0x288 0x658 0x938 0x3 0x2
+#define MX6Q_PAD_CSI0_DAT12__GPIO5_IO30           0x288 0x658 0x000 0x5 0x0
+#define MX6Q_PAD_CSI0_DAT12__ARM_TRACE09          0x288 0x658 0x000 0x7 0x0
+#define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_DATA13     0x28c 0x65c 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_DAT13__EIM_DATA09           0x28c 0x65c 0x000 0x1 0x0
+#define MX6Q_PAD_CSI0_DAT13__UART4_RX_DATA        0x28c 0x65c 0x938 0x3 0x3
+#define MX6Q_PAD_CSI0_DAT13__UART4_TX_DATA        0x28c 0x65c 0x000 0x3 0x0
+#define MX6Q_PAD_CSI0_DAT13__GPIO5_IO31           0x28c 0x65c 0x000 0x5 0x0
+#define MX6Q_PAD_CSI0_DAT13__ARM_TRACE10          0x28c 0x65c 0x000 0x7 0x0
+#define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_DATA14     0x290 0x660 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_DAT14__EIM_DATA10           0x290 0x660 0x000 0x1 0x0
+#define MX6Q_PAD_CSI0_DAT14__UART5_TX_DATA        0x290 0x660 0x000 0x3 0x0
+#define MX6Q_PAD_CSI0_DAT14__UART5_RX_DATA        0x290 0x660 0x940 0x3 0x2
+#define MX6Q_PAD_CSI0_DAT14__GPIO6_IO00           0x290 0x660 0x000 0x5 0x0
+#define MX6Q_PAD_CSI0_DAT14__ARM_TRACE11          0x290 0x660 0x000 0x7 0x0
+#define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_DATA15     0x294 0x664 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_DAT15__EIM_DATA11           0x294 0x664 0x000 0x1 0x0
+#define MX6Q_PAD_CSI0_DAT15__UART5_RX_DATA        0x294 0x664 0x940 0x3 0x3
+#define MX6Q_PAD_CSI0_DAT15__UART5_TX_DATA        0x294 0x664 0x000 0x3 0x0
+#define MX6Q_PAD_CSI0_DAT15__GPIO6_IO01           0x294 0x664 0x000 0x5 0x0
+#define MX6Q_PAD_CSI0_DAT15__ARM_TRACE12          0x294 0x664 0x000 0x7 0x0
+#define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_DATA16     0x298 0x668 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_DAT16__EIM_DATA12           0x298 0x668 0x000 0x1 0x0
+#define MX6Q_PAD_CSI0_DAT16__UART4_RTS_B          0x298 0x668 0x934 0x3 0x0
+#define MX6Q_PAD_CSI0_DAT16__UART4_CTS_B          0x298 0x668 0x000 0x3 0x0
+#define MX6Q_PAD_CSI0_DAT16__GPIO6_IO02           0x298 0x668 0x000 0x5 0x0
+#define MX6Q_PAD_CSI0_DAT16__ARM_TRACE13          0x298 0x668 0x000 0x7 0x0
+#define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_DATA17     0x29c 0x66c 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_DAT17__EIM_DATA13           0x29c 0x66c 0x000 0x1 0x0
+#define MX6Q_PAD_CSI0_DAT17__UART4_CTS_B          0x29c 0x66c 0x000 0x3 0x0
+#define MX6Q_PAD_CSI0_DAT17__UART4_RTS_B          0x29c 0x66c 0x934 0x3 0x1
+#define MX6Q_PAD_CSI0_DAT17__GPIO6_IO03           0x29c 0x66c 0x000 0x5 0x0
+#define MX6Q_PAD_CSI0_DAT17__ARM_TRACE14          0x29c 0x66c 0x000 0x7 0x0
+#define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_DATA18     0x2a0 0x670 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_DAT18__EIM_DATA14           0x2a0 0x670 0x000 0x1 0x0
+#define MX6Q_PAD_CSI0_DAT18__UART5_RTS_B          0x2a0 0x670 0x93c 0x3 0x2
+#define MX6Q_PAD_CSI0_DAT18__UART5_CTS_B          0x2a0 0x670 0x000 0x3 0x0
+#define MX6Q_PAD_CSI0_DAT18__GPIO6_IO04           0x2a0 0x670 0x000 0x5 0x0
+#define MX6Q_PAD_CSI0_DAT18__ARM_TRACE15          0x2a0 0x670 0x000 0x7 0x0
+#define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_DATA19     0x2a4 0x674 0x000 0x0 0x0
+#define MX6Q_PAD_CSI0_DAT19__EIM_DATA15           0x2a4 0x674 0x000 0x1 0x0
+#define MX6Q_PAD_CSI0_DAT19__UART5_CTS_B          0x2a4 0x674 0x000 0x3 0x0
+#define MX6Q_PAD_CSI0_DAT19__UART5_RTS_B          0x2a4 0x674 0x93c 0x3 0x3
+#define MX6Q_PAD_CSI0_DAT19__GPIO6_IO05           0x2a4 0x674 0x000 0x5 0x0
+#define MX6Q_PAD_SD3_DAT7__SD3_DATA7              0x2a8 0x690 0x000 0x0 0x0
+#define MX6Q_PAD_SD3_DAT7__UART1_TX_DATA          0x2a8 0x690 0x000 0x1 0x0
+#define MX6Q_PAD_SD3_DAT7__UART1_RX_DATA          0x2a8 0x690 0x920 0x1 0x2
+#define MX6Q_PAD_SD3_DAT7__GPIO6_IO17             0x2a8 0x690 0x000 0x5 0x0
+#define MX6Q_PAD_SD3_DAT6__SD3_DATA6              0x2ac 0x694 0x000 0x0 0x0
+#define MX6Q_PAD_SD3_DAT6__UART1_RX_DATA          0x2ac 0x694 0x920 0x1 0x3
+#define MX6Q_PAD_SD3_DAT6__UART1_TX_DATA          0x2ac 0x694 0x000 0x1 0x0
+#define MX6Q_PAD_SD3_DAT6__GPIO6_IO18             0x2ac 0x694 0x000 0x5 0x0
+#define MX6Q_PAD_SD3_DAT5__SD3_DATA5              0x2b0 0x698 0x000 0x0 0x0
+#define MX6Q_PAD_SD3_DAT5__UART2_TX_DATA          0x2b0 0x698 0x000 0x1 0x0
+#define MX6Q_PAD_SD3_DAT5__UART2_RX_DATA          0x2b0 0x698 0x928 0x1 0x4
+#define MX6Q_PAD_SD3_DAT5__GPIO7_IO00             0x2b0 0x698 0x000 0x5 0x0
+#define MX6Q_PAD_SD3_DAT4__SD3_DATA4              0x2b4 0x69c 0x000 0x0 0x0
+#define MX6Q_PAD_SD3_DAT4__UART2_RX_DATA          0x2b4 0x69c 0x928 0x1 0x5
+#define MX6Q_PAD_SD3_DAT4__UART2_TX_DATA          0x2b4 0x69c 0x000 0x1 0x0
+#define MX6Q_PAD_SD3_DAT4__GPIO7_IO01             0x2b4 0x69c 0x000 0x5 0x0
+#define MX6Q_PAD_SD3_CMD__SD3_CMD                 0x2b8 0x6a0 0x000 0x0 0x0
+#define MX6Q_PAD_SD3_CMD__UART2_CTS_B             0x2b8 0x6a0 0x000 0x1 0x0
+#define MX6Q_PAD_SD3_CMD__UART2_RTS_B             0x2b8 0x6a0 0x924 0x1 0x2
+#define MX6Q_PAD_SD3_CMD__FLEXCAN1_TX             0x2b8 0x6a0 0x000 0x2 0x0
+#define MX6Q_PAD_SD3_CMD__GPIO7_IO02              0x2b8 0x6a0 0x000 0x5 0x0
+#define MX6Q_PAD_SD3_CLK__SD3_CLK                 0x2bc 0x6a4 0x000 0x0 0x0
+#define MX6Q_PAD_SD3_CLK__UART2_RTS_B             0x2bc 0x6a4 0x924 0x1 0x3
+#define MX6Q_PAD_SD3_CLK__UART2_CTS_B             0x2bc 0x6a4 0x000 0x1 0x0
+#define MX6Q_PAD_SD3_CLK__FLEXCAN1_RX             0x2bc 0x6a4 0x7e4 0x2 0x2
+#define MX6Q_PAD_SD3_CLK__GPIO7_IO03              0x2bc 0x6a4 0x000 0x5 0x0
+#define MX6Q_PAD_SD3_DAT0__SD3_DATA0              0x2c0 0x6a8 0x000 0x0 0x0
+#define MX6Q_PAD_SD3_DAT0__UART1_CTS_B            0x2c0 0x6a8 0x000 0x1 0x0
+#define MX6Q_PAD_SD3_DAT0__UART1_RTS_B            0x2c0 0x6a8 0x91c 0x1 0x2
+#define MX6Q_PAD_SD3_DAT0__FLEXCAN2_TX            0x2c0 0x6a8 0x000 0x2 0x0
+#define MX6Q_PAD_SD3_DAT0__GPIO7_IO04             0x2c0 0x6a8 0x000 0x5 0x0
+#define MX6Q_PAD_SD3_DAT1__SD3_DATA1              0x2c4 0x6ac 0x000 0x0 0x0
+#define MX6Q_PAD_SD3_DAT1__UART1_RTS_B            0x2c4 0x6ac 0x91c 0x1 0x3
+#define MX6Q_PAD_SD3_DAT1__UART1_CTS_B            0x2c4 0x6ac 0x000 0x1 0x0
+#define MX6Q_PAD_SD3_DAT1__FLEXCAN2_RX            0x2c4 0x6ac 0x7e8 0x2 0x1
+#define MX6Q_PAD_SD3_DAT1__GPIO7_IO05             0x2c4 0x6ac 0x000 0x5 0x0
+#define MX6Q_PAD_SD3_DAT2__SD3_DATA2              0x2c8 0x6b0 0x000 0x0 0x0
+#define MX6Q_PAD_SD3_DAT2__GPIO7_IO06             0x2c8 0x6b0 0x000 0x5 0x0
+#define MX6Q_PAD_SD3_DAT3__SD3_DATA3              0x2cc 0x6b4 0x000 0x0 0x0
+#define MX6Q_PAD_SD3_DAT3__UART3_CTS_B            0x2cc 0x6b4 0x000 0x1 0x0
+#define MX6Q_PAD_SD3_DAT3__UART3_RTS_B            0x2cc 0x6b4 0x92c 0x1 0x4
+#define MX6Q_PAD_SD3_DAT3__GPIO7_IO07             0x2cc 0x6b4 0x000 0x5 0x0
+#define MX6Q_PAD_SD3_RST__SD3_RESET               0x2d0 0x6b8 0x000 0x0 0x0
+#define MX6Q_PAD_SD3_RST__UART3_RTS_B             0x2d0 0x6b8 0x92c 0x1 0x5
+#define MX6Q_PAD_SD3_RST__UART3_CTS_B             0x2d0 0x6b8 0x000 0x1 0x0
+#define MX6Q_PAD_SD3_RST__GPIO7_IO08              0x2d0 0x6b8 0x000 0x5 0x0
+#define MX6Q_PAD_NANDF_CLE__NAND_CLE              0x2d4 0x6bc 0x000 0x0 0x0
+#define MX6Q_PAD_NANDF_CLE__IPU2_SISG4            0x2d4 0x6bc 0x000 0x1 0x0
+#define MX6Q_PAD_NANDF_CLE__GPIO6_IO07            0x2d4 0x6bc 0x000 0x5 0x0
+#define MX6Q_PAD_NANDF_ALE__NAND_ALE              0x2d8 0x6c0 0x000 0x0 0x0
+#define MX6Q_PAD_NANDF_ALE__SD4_RESET             0x2d8 0x6c0 0x000 0x1 0x0
+#define MX6Q_PAD_NANDF_ALE__GPIO6_IO08            0x2d8 0x6c0 0x000 0x5 0x0
+#define MX6Q_PAD_NANDF_WP_B__NAND_WP_B            0x2dc 0x6c4 0x000 0x0 0x0
+#define MX6Q_PAD_NANDF_WP_B__IPU2_SISG5           0x2dc 0x6c4 0x000 0x1 0x0
+#define MX6Q_PAD_NANDF_WP_B__GPIO6_IO09           0x2dc 0x6c4 0x000 0x5 0x0
+#define MX6Q_PAD_NANDF_RB0__NAND_READY_B          0x2e0 0x6c8 0x000 0x0 0x0
+#define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN01        0x2e0 0x6c8 0x000 0x1 0x0
+#define MX6Q_PAD_NANDF_RB0__GPIO6_IO10            0x2e0 0x6c8 0x000 0x5 0x0
+#define MX6Q_PAD_NANDF_CS0__NAND_CE0_B            0x2e4 0x6cc 0x000 0x0 0x0
+#define MX6Q_PAD_NANDF_CS0__GPIO6_IO11            0x2e4 0x6cc 0x000 0x5 0x0
+#define MX6Q_PAD_NANDF_CS1__NAND_CE1_B            0x2e8 0x6d0 0x000 0x0 0x0
+#define MX6Q_PAD_NANDF_CS1__SD4_VSELECT           0x2e8 0x6d0 0x000 0x1 0x0
+#define MX6Q_PAD_NANDF_CS1__SD3_VSELECT           0x2e8 0x6d0 0x000 0x2 0x0
+#define MX6Q_PAD_NANDF_CS1__GPIO6_IO14            0x2e8 0x6d0 0x000 0x5 0x0
+#define MX6Q_PAD_NANDF_CS2__NAND_CE2_B            0x2ec 0x6d4 0x000 0x0 0x0
+#define MX6Q_PAD_NANDF_CS2__IPU1_SISG0            0x2ec 0x6d4 0x000 0x1 0x0
+#define MX6Q_PAD_NANDF_CS2__ESAI_TX0              0x2ec 0x6d4 0x874 0x2 0x1
+#define MX6Q_PAD_NANDF_CS2__EIM_CRE               0x2ec 0x6d4 0x000 0x3 0x0
+#define MX6Q_PAD_NANDF_CS2__CCM_CLKO2             0x2ec 0x6d4 0x000 0x4 0x0
+#define MX6Q_PAD_NANDF_CS2__GPIO6_IO15            0x2ec 0x6d4 0x000 0x5 0x0
+#define MX6Q_PAD_NANDF_CS2__IPU2_SISG0            0x2ec 0x6d4 0x000 0x6 0x0
+#define MX6Q_PAD_NANDF_CS3__NAND_CE3_B            0x2f0 0x6d8 0x000 0x0 0x0
+#define MX6Q_PAD_NANDF_CS3__IPU1_SISG1            0x2f0 0x6d8 0x000 0x1 0x0
+#define MX6Q_PAD_NANDF_CS3__ESAI_TX1              0x2f0 0x6d8 0x878 0x2 0x1
+#define MX6Q_PAD_NANDF_CS3__EIM_ADDR26            0x2f0 0x6d8 0x000 0x3 0x0
+#define MX6Q_PAD_NANDF_CS3__GPIO6_IO16            0x2f0 0x6d8 0x000 0x5 0x0
+#define MX6Q_PAD_NANDF_CS3__IPU2_SISG1            0x2f0 0x6d8 0x000 0x6 0x0
+#define MX6Q_PAD_SD4_CMD__SD4_CMD                 0x2f4 0x6dc 0x000 0x0 0x0
+#define MX6Q_PAD_SD4_CMD__NAND_RE_B               0x2f4 0x6dc 0x000 0x1 0x0
+#define MX6Q_PAD_SD4_CMD__UART3_TX_DATA           0x2f4 0x6dc 0x000 0x2 0x0
+#define MX6Q_PAD_SD4_CMD__UART3_RX_DATA           0x2f4 0x6dc 0x930 0x2 0x2
+#define MX6Q_PAD_SD4_CMD__GPIO7_IO09              0x2f4 0x6dc 0x000 0x5 0x0
+#define MX6Q_PAD_SD4_CLK__SD4_CLK                 0x2f8 0x6e0 0x000 0x0 0x0
+#define MX6Q_PAD_SD4_CLK__NAND_WE_B               0x2f8 0x6e0 0x000 0x1 0x0
+#define MX6Q_PAD_SD4_CLK__UART3_RX_DATA           0x2f8 0x6e0 0x930 0x2 0x3
+#define MX6Q_PAD_SD4_CLK__UART3_TX_DATA           0x2f8 0x6e0 0x000 0x2 0x0
+#define MX6Q_PAD_SD4_CLK__GPIO7_IO10              0x2f8 0x6e0 0x000 0x5 0x0
+#define MX6Q_PAD_NANDF_D0__NAND_DATA00            0x2fc 0x6e4 0x000 0x0 0x0
+#define MX6Q_PAD_NANDF_D0__SD1_DATA4              0x2fc 0x6e4 0x000 0x1 0x0
+#define MX6Q_PAD_NANDF_D0__GPIO2_IO00             0x2fc 0x6e4 0x000 0x5 0x0
+#define MX6Q_PAD_NANDF_D1__NAND_DATA01            0x300 0x6e8 0x000 0x0 0x0
+#define MX6Q_PAD_NANDF_D1__SD1_DATA5              0x300 0x6e8 0x000 0x1 0x0
+#define MX6Q_PAD_NANDF_D1__GPIO2_IO01             0x300 0x6e8 0x000 0x5 0x0
+#define MX6Q_PAD_NANDF_D2__NAND_DATA02            0x304 0x6ec 0x000 0x0 0x0
+#define MX6Q_PAD_NANDF_D2__SD1_DATA6              0x304 0x6ec 0x000 0x1 0x0
+#define MX6Q_PAD_NANDF_D2__GPIO2_IO02             0x304 0x6ec 0x000 0x5 0x0
+#define MX6Q_PAD_NANDF_D3__NAND_DATA03            0x308 0x6f0 0x000 0x0 0x0
+#define MX6Q_PAD_NANDF_D3__SD1_DATA7              0x308 0x6f0 0x000 0x1 0x0
+#define MX6Q_PAD_NANDF_D3__GPIO2_IO03             0x308 0x6f0 0x000 0x5 0x0
+#define MX6Q_PAD_NANDF_D4__NAND_DATA04            0x30c 0x6f4 0x000 0x0 0x0
+#define MX6Q_PAD_NANDF_D4__SD2_DATA4              0x30c 0x6f4 0x000 0x1 0x0
+#define MX6Q_PAD_NANDF_D4__GPIO2_IO04             0x30c 0x6f4 0x000 0x5 0x0
+#define MX6Q_PAD_NANDF_D5__NAND_DATA05            0x310 0x6f8 0x000 0x0 0x0
+#define MX6Q_PAD_NANDF_D5__SD2_DATA5              0x310 0x6f8 0x000 0x1 0x0
+#define MX6Q_PAD_NANDF_D5__GPIO2_IO05             0x310 0x6f8 0x000 0x5 0x0
+#define MX6Q_PAD_NANDF_D6__NAND_DATA06            0x314 0x6fc 0x000 0x0 0x0
+#define MX6Q_PAD_NANDF_D6__SD2_DATA6              0x314 0x6fc 0x000 0x1 0x0
+#define MX6Q_PAD_NANDF_D6__GPIO2_IO06             0x314 0x6fc 0x000 0x5 0x0
+#define MX6Q_PAD_NANDF_D7__NAND_DATA07            0x318 0x700 0x000 0x0 0x0
+#define MX6Q_PAD_NANDF_D7__SD2_DATA7              0x318 0x700 0x000 0x1 0x0
+#define MX6Q_PAD_NANDF_D7__GPIO2_IO07             0x318 0x700 0x000 0x5 0x0
+#define MX6Q_PAD_SD4_DAT0__SD4_DATA0              0x31c 0x704 0x000 0x1 0x0
+#define MX6Q_PAD_SD4_DAT0__NAND_DQS               0x31c 0x704 0x000 0x2 0x0
+#define MX6Q_PAD_SD4_DAT0__GPIO2_IO08             0x31c 0x704 0x000 0x5 0x0
+#define MX6Q_PAD_SD4_DAT1__SD4_DATA1              0x320 0x708 0x000 0x1 0x0
+#define MX6Q_PAD_SD4_DAT1__PWM3_OUT               0x320 0x708 0x000 0x2 0x0
+#define MX6Q_PAD_SD4_DAT1__GPIO2_IO09             0x320 0x708 0x000 0x5 0x0
+#define MX6Q_PAD_SD4_DAT2__SD4_DATA2              0x324 0x70c 0x000 0x1 0x0
+#define MX6Q_PAD_SD4_DAT2__PWM4_OUT               0x324 0x70c 0x000 0x2 0x0
+#define MX6Q_PAD_SD4_DAT2__GPIO2_IO10             0x324 0x70c 0x000 0x5 0x0
+#define MX6Q_PAD_SD4_DAT3__SD4_DATA3              0x328 0x710 0x000 0x1 0x0
+#define MX6Q_PAD_SD4_DAT3__GPIO2_IO11             0x328 0x710 0x000 0x5 0x0
+#define MX6Q_PAD_SD4_DAT4__SD4_DATA4              0x32c 0x714 0x000 0x1 0x0
+#define MX6Q_PAD_SD4_DAT4__UART2_RX_DATA          0x32c 0x714 0x928 0x2 0x6
+#define MX6Q_PAD_SD4_DAT4__UART2_TX_DATA          0x32c 0x714 0x000 0x2 0x0
+#define MX6Q_PAD_SD4_DAT4__GPIO2_IO12             0x32c 0x714 0x000 0x5 0x0
+#define MX6Q_PAD_SD4_DAT5__SD4_DATA5              0x330 0x718 0x000 0x1 0x0
+#define MX6Q_PAD_SD4_DAT5__UART2_RTS_B            0x330 0x718 0x924 0x2 0x4
+#define MX6Q_PAD_SD4_DAT5__UART2_CTS_B            0x330 0x718 0x000 0x2 0x0
+#define MX6Q_PAD_SD4_DAT5__GPIO2_IO13             0x330 0x718 0x000 0x5 0x0
+#define MX6Q_PAD_SD4_DAT6__SD4_DATA6              0x334 0x71c 0x000 0x1 0x0
+#define MX6Q_PAD_SD4_DAT6__UART2_CTS_B            0x334 0x71c 0x000 0x2 0x0
+#define MX6Q_PAD_SD4_DAT6__UART2_RTS_B            0x334 0x71c 0x924 0x2 0x5
+#define MX6Q_PAD_SD4_DAT6__GPIO2_IO14             0x334 0x71c 0x000 0x5 0x0
+#define MX6Q_PAD_SD4_DAT7__SD4_DATA7              0x338 0x720 0x000 0x1 0x0
+#define MX6Q_PAD_SD4_DAT7__UART2_TX_DATA          0x338 0x720 0x000 0x2 0x0
+#define MX6Q_PAD_SD4_DAT7__UART2_RX_DATA          0x338 0x720 0x928 0x2 0x7
+#define MX6Q_PAD_SD4_DAT7__GPIO2_IO15             0x338 0x720 0x000 0x5 0x0
+#define MX6Q_PAD_SD1_DAT1__SD1_DATA1              0x33c 0x724 0x000 0x0 0x0
+#define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0             0x33c 0x724 0x834 0x1 0x1
+#define MX6Q_PAD_SD1_DAT1__PWM3_OUT               0x33c 0x724 0x000 0x2 0x0
+#define MX6Q_PAD_SD1_DAT1__GPT_CAPTURE2           0x33c 0x724 0x000 0x3 0x0
+#define MX6Q_PAD_SD1_DAT1__GPIO1_IO17             0x33c 0x724 0x000 0x5 0x0
+#define MX6Q_PAD_SD1_DAT0__SD1_DATA0              0x340 0x728 0x000 0x0 0x0
+#define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO            0x340 0x728 0x82c 0x1 0x1
+#define MX6Q_PAD_SD1_DAT0__GPT_CAPTURE1           0x340 0x728 0x000 0x3 0x0
+#define MX6Q_PAD_SD1_DAT0__GPIO1_IO16             0x340 0x728 0x000 0x5 0x0
+#define MX6Q_PAD_SD1_DAT3__SD1_DATA3              0x344 0x72c 0x000 0x0 0x0
+#define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2             0x344 0x72c 0x000 0x1 0x0
+#define MX6Q_PAD_SD1_DAT3__GPT_COMPARE3           0x344 0x72c 0x000 0x2 0x0
+#define MX6Q_PAD_SD1_DAT3__PWM1_OUT               0x344 0x72c 0x000 0x3 0x0
+#define MX6Q_PAD_SD1_DAT3__WDOG2_B                0x344 0x72c 0x000 0x4 0x0
+#define MX6Q_PAD_SD1_DAT3__GPIO1_IO21             0x344 0x72c 0x000 0x5 0x0
+#define MX6Q_PAD_SD1_DAT3__WDOG2_RESET_B_DEB      0x344 0x72c 0x000 0x6 0x0
+#define MX6Q_PAD_SD1_CMD__SD1_CMD                 0x348 0x730 0x000 0x0 0x0
+#define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI             0x348 0x730 0x830 0x1 0x0
+#define MX6Q_PAD_SD1_CMD__PWM4_OUT                0x348 0x730 0x000 0x2 0x0
+#define MX6Q_PAD_SD1_CMD__GPT_COMPARE1            0x348 0x730 0x000 0x3 0x0
+#define MX6Q_PAD_SD1_CMD__GPIO1_IO18              0x348 0x730 0x000 0x5 0x0
+#define MX6Q_PAD_SD1_DAT2__SD1_DATA2              0x34c 0x734 0x000 0x0 0x0
+#define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1             0x34c 0x734 0x838 0x1 0x1
+#define MX6Q_PAD_SD1_DAT2__GPT_COMPARE2           0x34c 0x734 0x000 0x2 0x0
+#define MX6Q_PAD_SD1_DAT2__PWM2_OUT               0x34c 0x734 0x000 0x3 0x0
+#define MX6Q_PAD_SD1_DAT2__WDOG1_B                0x34c 0x734 0x000 0x4 0x0
+#define MX6Q_PAD_SD1_DAT2__GPIO1_IO19             0x34c 0x734 0x000 0x5 0x0
+#define MX6Q_PAD_SD1_DAT2__WDOG1_RESET_B_DEB      0x34c 0x734 0x000 0x6 0x0
+#define MX6Q_PAD_SD1_CLK__SD1_CLK                 0x350 0x738 0x000 0x0 0x0
+#define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK             0x350 0x738 0x828 0x1 0x0
+#define MX6Q_PAD_SD1_CLK__GPT_CLKIN               0x350 0x738 0x000 0x3 0x0
+#define MX6Q_PAD_SD1_CLK__GPIO1_IO20              0x350 0x738 0x000 0x5 0x0
+#define MX6Q_PAD_SD2_CLK__SD2_CLK                 0x354 0x73c 0x000 0x0 0x0
+#define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK             0x354 0x73c 0x828 0x1 0x1
+#define MX6Q_PAD_SD2_CLK__KEY_COL5                0x354 0x73c 0x8e8 0x2 0x3
+#define MX6Q_PAD_SD2_CLK__AUD4_RXFS               0x354 0x73c 0x7c0 0x3 0x1
+#define MX6Q_PAD_SD2_CLK__GPIO1_IO10              0x354 0x73c 0x000 0x5 0x0
+#define MX6Q_PAD_SD2_CMD__SD2_CMD                 0x358 0x740 0x000 0x0 0x0
+#define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI             0x358 0x740 0x830 0x1 0x1
+#define MX6Q_PAD_SD2_CMD__KEY_ROW5                0x358 0x740 0x8f4 0x2 0x2
+#define MX6Q_PAD_SD2_CMD__AUD4_RXC                0x358 0x740 0x7bc 0x3 0x1
+#define MX6Q_PAD_SD2_CMD__GPIO1_IO11              0x358 0x740 0x000 0x5 0x0
+#define MX6Q_PAD_SD2_DAT3__SD2_DATA3              0x35c 0x744 0x000 0x0 0x0
+#define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3             0x35c 0x744 0x000 0x1 0x0
+#define MX6Q_PAD_SD2_DAT3__KEY_COL6               0x35c 0x744 0x8ec 0x2 0x2
+#define MX6Q_PAD_SD2_DAT3__AUD4_TXC               0x35c 0x744 0x7c4 0x3 0x1
+#define MX6Q_PAD_SD2_DAT3__GPIO1_IO12             0x35c 0x744 0x000 0x5 0x0
+
+#endif /* __DTS_IMX6Q_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 656d489122fe..49d6f2831ec9 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -11,15 +11,13 @@
  */
 
 /dts-v1/;
-/include/ "imx6q.dtsi"
+
+#include "imx6q.dtsi"
+#include "imx6qdl-sabreauto.dtsi"
 
 / {
         model = "Freescale i.MX6 Quad SABRE Automotive Board";
         compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
-
-        memory {
-                reg = <0x10000000 0x80000000>;
-        };
 };
 
 &iomuxc {
@@ -29,30 +27,9 @@
         hog {
                 pinctrl_hog: hoggrp {
                         fsl,pins = <
-                                1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
-                                13   0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
+                                MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
+                                MX6Q_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
                         >;
                 };
         };
 };
-
-&uart4 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart4_1>;
-        status = "okay";
-};
-
-&fec {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet_2>;
-        phy-mode = "rgmii";
-        status = "okay";
-};
-
-&usdhc3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc3_1>;
-        cd-gpios = <&gpio6 15 0>;
-        wp-gpios = <&gpio1 13 0>;
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 2ce355cd05e5..6a000666c147 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -11,7 +11,7 @@
  */
 
 /dts-v1/;
-/include/ "imx6q.dtsi"
+#include "imx6q.dtsi"
 
 / {
         model = "Freescale i.MX6 Quad SABRE Lite Board";
@@ -91,14 +91,14 @@
         hog {
                 pinctrl_hog: hoggrp {
                         fsl,pins = <
-                                1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
-                                1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
-                                121  0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
-                                144  0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
-                                152  0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
-                                1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
-                                1270 0x1f0b0    /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
-                                953  0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
+                                MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x80000000
+                                MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x80000000
+                                MX6Q_PAD_EIM_D19__GPIO3_IO19  0x80000000
+                                MX6Q_PAD_EIM_D22__GPIO3_IO22  0x80000000
+                                MX6Q_PAD_EIM_D23__GPIO3_IO23  0x80000000
+                                MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
+                                MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
+                                MX6Q_PAD_GPIO_0__CCM_CLKO1    0x80000000
                         >;
                 };
         };
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 2dea304a7980..442051350225 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -11,37 +11,13 @@
  */
 
 /dts-v1/;
-/include/ "imx6q.dtsi"
+
+#include "imx6q.dtsi"
+#include "imx6qdl-sabresd.dtsi"
 
 / {
-        model = "Freescale i.MX6Q SABRE Smart Device Board";
+        model = "Freescale i.MX6 Quad SABRE Smart Device Board";
         compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
-
-        memory {
-                reg = <0x10000000 0x40000000>;
-        };
-
-        gpio-keys {
-                compatible = "gpio-keys";
-
-                volume-up {
-                        label = "Volume Up";
-                        gpios = <&gpio1 4 0>;
-                        linux,code = <115>; /* KEY_VOLUMEUP */
-                };
-
-                volume-down {
-                        label = "Volume Down";
-                        gpios = <&gpio1 5 0>;
-                        linux,code = <114>; /* KEY_VOLUMEDOWN */
-                };
-        };
-};
-
-&uart1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1_1>;
-        status = "okay";
 };
 
 &iomuxc {
@@ -51,36 +27,13 @@
         hog {
                 pinctrl_hog: hoggrp {
                         fsl,pins = <
-                                1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
-                                1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
-                                1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
-                                1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
-                                1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
-                                1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
+                                MX6Q_PAD_GPIO_4__GPIO1_IO04   0x80000000
+                                MX6Q_PAD_GPIO_5__GPIO1_IO05   0x80000000
+                                MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x80000000
+                                MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000
+                                MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000
+                                MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000
                         >;
                 };
         };
 };
-
-&fec {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet_1>;
-        phy-mode = "rgmii";
-        status = "okay";
-};
-
-&usdhc2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc2_1>;
-        cd-gpios = <&gpio2 2 0>;
-        wp-gpios = <&gpio2 3 0>;
-        status = "okay";
-};
-
-&usdhc3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc3_1>;
-        cd-gpios = <&gpio2 0 0>;
-        wp-gpios = <&gpio2 1 0>;
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/imx6q-sbc6x.dts b/arch/arm/boot/dts/imx6q-sbc6x.dts
new file mode 100644
index 000000000000..ee6addf149af
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-sbc6x.dts
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2013 Pavel Machek <pavel@denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License V2.
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+
+/ {
+        model = "MicroSys sbc6x board";
+        compatible = "microsys,sbc6x", "fsl,imx6q";
+
+        memory {
+                reg = <0x10000000 0x80000000>;
+        };
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet_1>;
+        phy-mode = "rgmii";
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_1>;
+        status = "okay";
+};
+
+&usbotg {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg_1>;
+        disable-over-current;
+        status = "okay";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3_2>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index cba021eb035e..21e675848bd1 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -8,7 +8,8 @@
  *
  */
 
-/include/ "imx6qdl.dtsi"
+#include "imx6qdl.dtsi"
+#include "imx6q-pinfunc.h"
 
 / {
         cpus {
@@ -78,10 +79,19 @@
                                 audmux {
                                         pinctrl_audmux_1: audmux-1 {
                                                 fsl,pins = <
-                                                        18   0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
-                                                        1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
-                                                        11   0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
-                                                        3    0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
+                                                        MX6Q_PAD_SD2_DAT0__AUD4_RXD  0x80000000
+                                                        MX6Q_PAD_SD2_DAT3__AUD4_TXC  0x80000000
+                                                        MX6Q_PAD_SD2_DAT2__AUD4_TXD  0x80000000
+                                                        MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
+                                                >;
+                                        };
+
+                                        pinctrl_audmux_2: audmux-2 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_CSI0_DAT7__AUD3_RXD  0x80000000
+                                                        MX6Q_PAD_CSI0_DAT4__AUD3_TXC  0x80000000
+                                                        MX6Q_PAD_CSI0_DAT5__AUD3_TXD  0x80000000
+                                                        MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
                                                 >;
                                         };
                                 };
@@ -89,9 +99,19 @@
                                 ecspi1 {
                                         pinctrl_ecspi1_1: ecspi1grp-1 {
                                                 fsl,pins = <
-                                                        101 0x100b1     /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
-                                                        109 0x100b1     /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
-                                                        94  0x100b1     /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+                                                        MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+                                                        MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+                                                        MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+                                                >;
+                                        };
+                                };
+
+                                ecspi3 {
+                                        pinctrl_ecspi3_1: ecspi3grp-1 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
+                                                        MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
+                                                        MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
                                                 >;
                                         };
                                 };
@@ -99,42 +119,42 @@
                                 enet {
                                         pinctrl_enet_1: enetgrp-1 {
                                                 fsl,pins = <
-                                                        695 0x1b0b0     /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
-                                                        756 0x1b0b0     /* MX6Q_PAD_ENET_MDC__ENET_MDC */
-                                                        24  0x1b0b0     /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
-                                                        30  0x1b0b0     /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
-                                                        34  0x1b0b0     /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
-                                                        39  0x1b0b0     /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
-                                                        44  0x1b0b0     /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
-                                                        56  0x1b0b0     /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
-                                                        702 0x1b0b0     /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
-                                                        74  0x1b0b0     /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
-                                                        52  0x1b0b0     /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
-                                                        61  0x1b0b0     /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
-                                                        66  0x1b0b0     /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
-                                                        70  0x1b0b0     /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
-                                                        48  0x1b0b0     /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
-                                                        1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/
+                                                        MX6Q_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+                                                        MX6Q_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+                                                        MX6Q_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+                                                        MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+                                                        MX6Q_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+                                                        MX6Q_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
                                                 >;
                                         };
 
                                         pinctrl_enet_2: enetgrp-2 {
                                                 fsl,pins = <
-                                                        890 0x1b0b0     /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
-                                                        909 0x1b0b0     /* MX6Q_PAD_KEY_COL2__ENET_MDC */
-                                                        24  0x1b0b0     /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
-                                                        30  0x1b0b0     /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
-                                                        34  0x1b0b0     /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
-                                                        39  0x1b0b0     /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
-                                                        44  0x1b0b0     /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
-                                                        56  0x1b0b0     /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
-                                                        702 0x1b0b0     /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
-                                                        74  0x1b0b0     /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
-                                                        52  0x1b0b0     /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
-                                                        61  0x1b0b0     /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
-                                                        66  0x1b0b0     /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
-                                                        70  0x1b0b0     /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
-                                                        48  0x1b0b0     /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+                                                        MX6Q_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
+                                                        MX6Q_PAD_KEY_COL2__ENET_MDC         0x1b0b0
+                                                        MX6Q_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+                                                        MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+                                                        MX6Q_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
                                                 >;
                                         };
                                 };
@@ -142,25 +162,25 @@
                                 gpmi-nand {
                                         pinctrl_gpmi_nand_1: gpmi-nand-1 {
                                                 fsl,pins = <
-                                                        1328 0xb0b1     /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
-                                                        1336 0xb0b1     /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
-                                                        1344 0xb0b1     /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
-                                                        1352 0xb000     /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
-                                                        1360 0xb0b1     /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
-                                                        1365 0xb0b1     /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
-                                                        1371 0xb0b1     /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
-                                                        1378 0xb0b1     /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
-                                                        1387 0xb0b1     /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
-                                                        1393 0xb0b1     /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
-                                                        1397 0xb0b1     /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
-                                                        1405 0xb0b1     /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
-                                                        1413 0xb0b1     /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
-                                                        1421 0xb0b1     /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
-                                                        1429 0xb0b1     /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
-                                                        1437 0xb0b1     /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
-                                                        1445 0xb0b1     /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
-                                                        1453 0xb0b1     /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
-                                                        1463 0x00b1     /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
+                                                        MX6Q_PAD_NANDF_CLE__NAND_CLE     0xb0b1
+                                                        MX6Q_PAD_NANDF_ALE__NAND_ALE     0xb0b1
+                                                        MX6Q_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
+                                                        MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
+                                                        MX6Q_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
+                                                        MX6Q_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
+                                                        MX6Q_PAD_NANDF_CS2__NAND_CE2_B   0xb0b1
+                                                        MX6Q_PAD_NANDF_CS3__NAND_CE3_B   0xb0b1
+                                                        MX6Q_PAD_SD4_CMD__NAND_RE_B      0xb0b1
+                                                        MX6Q_PAD_SD4_CLK__NAND_WE_B      0xb0b1
+                                                        MX6Q_PAD_NANDF_D0__NAND_DATA00   0xb0b1
+                                                        MX6Q_PAD_NANDF_D1__NAND_DATA01   0xb0b1
+                                                        MX6Q_PAD_NANDF_D2__NAND_DATA02   0xb0b1
+                                                        MX6Q_PAD_NANDF_D3__NAND_DATA03   0xb0b1
+                                                        MX6Q_PAD_NANDF_D4__NAND_DATA04   0xb0b1
+                                                        MX6Q_PAD_NANDF_D5__NAND_DATA05   0xb0b1
+                                                        MX6Q_PAD_NANDF_D6__NAND_DATA06   0xb0b1
+                                                        MX6Q_PAD_NANDF_D7__NAND_DATA07   0xb0b1
+                                                        MX6Q_PAD_SD4_DAT0__NAND_DQS      0x00b1
                                                 >;
                                         };
                                 };
@@ -168,8 +188,26 @@
                                 i2c1 {
                                         pinctrl_i2c1_1: i2c1grp-1 {
                                                 fsl,pins = <
-                                                        137 0x4001b8b1  /* MX6Q_PAD_EIM_D21__I2C1_SCL */
-                                                        196 0x4001b8b1  /* MX6Q_PAD_EIM_D28__I2C1_SDA */
+                                                        MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+                                                        MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+                                                >;
+                                        };
+                                };
+
+                                i2c2 {
+                                        pinctrl_i2c2_1: i2c2grp-1 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+                                                        MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
+                                                >;
+                                        };
+                                };
+
+                                i2c3 {
+                                        pinctrl_i2c3_1: i2c3grp-1 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
+                                                        MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
                                                 >;
                                         };
                                 };
@@ -177,8 +215,8 @@
                                 uart1 {
                                         pinctrl_uart1_1: uart1grp-1 {
                                                 fsl,pins = <
-                                                        1140 0x1b0b1    /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
-                                                        1148 0x1b0b1    /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
+                                                        MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+                                                        MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
                                                 >;
                                         };
                                 };
@@ -186,8 +224,8 @@
                                 uart2 {
                                         pinctrl_uart2_1: uart2grp-1 {
                                                 fsl,pins = <
-                                                        183 0x1b0b1     /* MX6Q_PAD_EIM_D26__UART2_TXD */
-                                                        191 0x1b0b1     /* MX6Q_PAD_EIM_D27__UART2_RXD */
+                                                        MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+                                                        MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
                                                 >;
                                         };
                                 };
@@ -195,8 +233,8 @@
                                 uart4 {
                                         pinctrl_uart4_1: uart4grp-1 {
                                                 fsl,pins = <
-                                                        877 0x1b0b1     /* MX6Q_PAD_KEY_COL0__UART4_TXD */
-                                                        885 0x1b0b1     /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
+                                                        MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+                                                        MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
                                                 >;
                                         };
                                 };
@@ -204,7 +242,13 @@
                                 usbotg {
                                         pinctrl_usbotg_1: usbotggrp-1 {
                                                 fsl,pins = <
-                                                        1592 0x17059    /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
+                                                        MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
+                                                >;
+                                        };
+
+                                        pinctrl_usbotg_2: usbotggrp-2 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
                                                 >;
                                         };
                                 };
@@ -212,16 +256,16 @@
                                 usdhc2 {
                                         pinctrl_usdhc2_1: usdhc2grp-1 {
                                                 fsl,pins = <
-                                                        1577 0x17059    /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
-                                                        1569 0x10059    /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
-                                                        16   0x17059    /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
-                                                        0    0x17059    /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
-                                                        8    0x17059    /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
-                                                        1583 0x17059    /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
-                                                        1430 0x17059    /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
-                                                        1438 0x17059    /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
-                                                        1446 0x17059    /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
-                                                        1454 0x17059    /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
+                                                        MX6Q_PAD_SD2_CMD__SD2_CMD    0x17059
+                                                        MX6Q_PAD_SD2_CLK__SD2_CLK    0x10059
+                                                        MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
+                                                        MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
+                                                        MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
+                                                        MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
+                                                        MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
+                                                        MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
+                                                        MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
+                                                        MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
                                                 >;
                                         };
                                 };
@@ -229,27 +273,27 @@
                                 usdhc3 {
                                         pinctrl_usdhc3_1: usdhc3grp-1 {
                                                 fsl,pins = <
-                                                        1273 0x17059    /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
-                                                        1281 0x10059    /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
-                                                        1289 0x17059    /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
-                                                        1297 0x17059    /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
-                                                        1305 0x17059    /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
-                                                        1312 0x17059    /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
-                                                        1265 0x17059    /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
-                                                        1257 0x17059    /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
-                                                        1249 0x17059    /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
-                                                        1241 0x17059    /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
+                                                        MX6Q_PAD_SD3_CMD__SD3_CMD    0x17059
+                                                        MX6Q_PAD_SD3_CLK__SD3_CLK    0x10059
+                                                        MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
+                                                        MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
+                                                        MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
+                                                        MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
+                                                        MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
+                                                        MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
+                                                        MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
+                                                        MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
                                                 >;
                                         };
 
                                         pinctrl_usdhc3_2: usdhc3grp-2 {
                                                 fsl,pins = <
-                                                        1273 0x17059    /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
-                                                        1281 0x10059    /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
-                                                        1289 0x17059    /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
-                                                        1297 0x17059    /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
-                                                        1305 0x17059    /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
-                                                        1312 0x17059    /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
+                                                        MX6Q_PAD_SD3_CMD__SD3_CMD    0x17059
+                                                        MX6Q_PAD_SD3_CLK__SD3_CLK    0x10059
+                                                        MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
+                                                        MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
+                                                        MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
+                                                        MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
                                                 >;
                                         };
                                 };
@@ -257,27 +301,27 @@
                                 usdhc4 {
                                         pinctrl_usdhc4_1: usdhc4grp-1 {
                                                 fsl,pins = <
-                                                        1386 0x17059    /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
-                                                        1392 0x10059    /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
-                                                        1462 0x17059    /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
-                                                        1470 0x17059    /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
-                                                        1478 0x17059    /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
-                                                        1486 0x17059    /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
-                                                        1493 0x17059    /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
-                                                        1501 0x17059    /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
-                                                        1509 0x17059    /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
-                                                        1517 0x17059    /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+                                                        MX6Q_PAD_SD4_CMD__SD4_CMD    0x17059
+                                                        MX6Q_PAD_SD4_CLK__SD4_CLK    0x10059
+                                                        MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
+                                                        MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
+                                                        MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
+                                                        MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
+                                                        MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
+                                                        MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
+                                                        MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
+                                                        MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
                                                 >;
                                         };
 
                                         pinctrl_usdhc4_2: usdhc4grp-2 {
                                                 fsl,pins = <
-                                                        1386 0x17059    /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
-                                                        1392 0x10059    /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
-                                                        1462 0x17059    /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
-                                                        1470 0x17059    /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
-                                                        1478 0x17059    /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
-                                                        1486 0x17059    /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+                                                        MX6Q_PAD_SD4_CMD__SD4_CMD    0x17059
+                                                        MX6Q_PAD_SD4_CLK__SD4_CLK    0x10059
+                                                        MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
+                                                        MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
+                                                        MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
+                                                        MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
                                                 >;
                                         };
                                 };
@@ -291,6 +335,24 @@
                         interrupts = <0 8 0x4 0 7 0x4>;
                         clocks = <&clks 133>, <&clks 134>, <&clks 137>;
                         clock-names = "bus", "di0", "di1";
+                        resets = <&src 4>;
                 };
         };
 };
+
+&ldb {
+        clocks = <&clks 33>, <&clks 34>,
+                 <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
+                 <&clks 135>, <&clks 136>;
+        clock-names = "di0_pll", "di1_pll",
+                      "di0_sel", "di1_sel", "di2_sel", "di3_sel",
+                      "di0", "di1";
+
+        lvds-channel@0 {
+                crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
+        };
+
+        lvds-channel@1 {
+                crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
new file mode 100644
index 000000000000..4d237cffcc41
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/ {
+        memory {
+                reg = <0x10000000 0x80000000>;
+        };
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet_2>;
+        phy-mode = "rgmii";
+        status = "okay";
+};
+
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart4_1>;
+        status = "okay";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3_1>;
+        cd-gpios = <&gpio6 15 0>;
+        wp-gpios = <&gpio1 13 0>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
new file mode 100644
index 000000000000..e21f6a89cf0f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/ {
+        memory {
+                reg = <0x10000000 0x40000000>;
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_usb_otg_vbus: usb_otg_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb_otg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 22 0>;
+                        enable-active-high;
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                volume-up {
+                        label = "Volume Up";
+                        gpios = <&gpio1 4 0>;
+                        linux,code = <115>; /* KEY_VOLUMEUP */
+                };
+
+                volume-down {
+                        label = "Volume Down";
+                        gpios = <&gpio1 5 0>;
+                        linux,code = <114>; /* KEY_VOLUMEDOWN */
+                };
+        };
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet_1>;
+        phy-mode = "rgmii";
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_1>;
+        status = "okay";
+};
+
+&usbh1 {
+        status = "okay";
+};
+
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg_2>;
+        disable-over-current;
+        status = "okay";
+};
+
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2_1>;
+        cd-gpios = <&gpio2 2 0>;
+        wp-gpios = <&gpio2 3 0>;
+        status = "okay";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3_1>;
+        cd-gpios = <&gpio2 0 0>;
+        wp-gpios = <&gpio2 1 0>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 281a223591ff..3cca7d39529d 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -10,7 +10,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
         aliases {
@@ -102,6 +102,11 @@
                         cache-level = <2>;
                 };
 
+                pmu {
+                        compatible = "arm,cortex-a9-pmu";
+                        interrupts = <0 94 0x04>;
+                };
+
                 aips-bus@02000000 { /* AIPS1 */
                         compatible = "fsl,aips-bus", "simple-bus";
                         #address-cells = <1>;
@@ -278,6 +283,8 @@
                                 compatible = "fsl,imx6q-gpt";
                                 reg = <0x02098000 0x4000>;
                                 interrupts = <0 55 0x04>;
+                                clocks = <&clks 119>, <&clks 120>;
+                                clock-names = "ipg", "per";
                         };
 
                         gpio1: gpio@0209c000 {
@@ -514,9 +521,10 @@
                         };
 
                         src: src@020d8000 {
-                                compatible = "fsl,imx6q-src";
+                                compatible = "fsl,imx6q-src", "fsl,imx51-src";
                                 reg = <0x020d8000 0x4000>;
                                 interrupts = <0 91 0x04 0 96 0x04>;
+                                #reset-cells = <1>;
                         };
 
                         gpc: gpc@020dc000 {
@@ -530,6 +538,26 @@
                                 reg = <0x020e0000 0x38>;
                         };
 
+                        ldb: ldb@020e0008 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
+                                gpr = <&gpr>;
+                                status = "disabled";
+
+                                lvds-channel@0 {
+                                        reg = <0>;
+                                        crtcs = <&ipu1 0>;
+                                        status = "disabled";
+                                };
+
+                                lvds-channel@1 {
+                                        reg = <1>;
+                                        crtcs = <&ipu1 1>;
+                                        status = "disabled";
+                                };
+                        };
+
                         dcic1: dcic@020e4000 {
                                 reg = <0x020e4000 0x4000>;
                                 interrupts = <0 124 0x04>;
@@ -796,6 +824,7 @@
                         interrupts = <0 6 0x4 0 5 0x4>;
                         clocks = <&clks 130>, <&clks 131>, <&clks 132>;
                         clock-names = "bus", "di0", "di1";
+                        resets = <&src 2>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/imx6sl-pinfunc.h b/arch/arm/boot/dts/imx6sl-pinfunc.h
new file mode 100644
index 000000000000..77b17bcc7b70
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-pinfunc.h
@@ -0,0 +1,1077 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_IMX6SL_PINFUNC_H
+#define __DTS_IMX6SL_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT          0x04c 0x2a4 0x000 0x0 0x0
+#define MX6SL_PAD_AUD_MCLK__PWM4_OUT               0x04c 0x2a4 0x000 0x1 0x0
+#define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY             0x04c 0x2a4 0x6b4 0x2 0x0
+#define MX6SL_PAD_AUD_MCLK__FEC_MDC                0x04c 0x2a4 0x000 0x3 0x0
+#define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB      0x04c 0x2a4 0x000 0x4 0x0
+#define MX6SL_PAD_AUD_MCLK__GPIO1_IO06             0x04c 0x2a4 0x000 0x5 0x0
+#define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK          0x04c 0x2a4 0x7f4 0x6 0x0
+#define MX6SL_PAD_AUD_RXC__AUD3_RXC                0x050 0x2a8 0x000 0x0 0x0
+#define MX6SL_PAD_AUD_RXC__I2C1_SDA                0x050 0x2a8 0x720 0x1 0x0
+#define MX6SL_PAD_AUD_RXC__UART3_TX_DATA           0x050 0x2a8 0x000 0x2 0x0
+#define MX6SL_PAD_AUD_RXC__UART3_RX_DATA           0x050 0x2a8 0x80c 0x2 0x0
+#define MX6SL_PAD_AUD_RXC__FEC_TX_CLK              0x050 0x2a8 0x70c 0x3 0x0
+#define MX6SL_PAD_AUD_RXC__I2C3_SDA                0x050 0x2a8 0x730 0x4 0x0
+#define MX6SL_PAD_AUD_RXC__GPIO1_IO01              0x050 0x2a8 0x000 0x5 0x0
+#define MX6SL_PAD_AUD_RXC__ECSPI3_SS1              0x050 0x2a8 0x6c4 0x6 0x0
+#define MX6SL_PAD_AUD_RXD__AUD3_RXD                0x054 0x2ac 0x000 0x0 0x0
+#define MX6SL_PAD_AUD_RXD__ECSPI3_MOSI             0x054 0x2ac 0x6bc 0x1 0x0
+#define MX6SL_PAD_AUD_RXD__UART4_RX_DATA           0x054 0x2ac 0x814 0x2 0x0
+#define MX6SL_PAD_AUD_RXD__UART4_TX_DATA           0x054 0x2ac 0x000 0x2 0x0
+#define MX6SL_PAD_AUD_RXD__FEC_RX_ER               0x054 0x2ac 0x708 0x3 0x0
+#define MX6SL_PAD_AUD_RXD__SD1_LCTL                0x054 0x2ac 0x000 0x4 0x0
+#define MX6SL_PAD_AUD_RXD__GPIO1_IO02              0x054 0x2ac 0x000 0x5 0x0
+#define MX6SL_PAD_AUD_RXFS__AUD3_RXFS              0x058 0x2b0 0x000 0x0 0x0
+#define MX6SL_PAD_AUD_RXFS__I2C1_SCL               0x058 0x2b0 0x71c 0x1 0x0
+#define MX6SL_PAD_AUD_RXFS__UART3_RX_DATA          0x058 0x2b0 0x80c 0x2 0x1
+#define MX6SL_PAD_AUD_RXFS__UART3_TX_DATA          0x058 0x2b0 0x000 0x2 0x0
+#define MX6SL_PAD_AUD_RXFS__FEC_MDIO               0x058 0x2b0 0x6f4 0x3 0x0
+#define MX6SL_PAD_AUD_RXFS__I2C3_SCL               0x058 0x2b0 0x72c 0x4 0x0
+#define MX6SL_PAD_AUD_RXFS__GPIO1_IO00             0x058 0x2b0 0x000 0x5 0x0
+#define MX6SL_PAD_AUD_RXFS__ECSPI3_SS0             0x058 0x2b0 0x6c0 0x6 0x0
+#define MX6SL_PAD_AUD_TXC__AUD3_TXC                0x05c 0x2b4 0x000 0x0 0x0
+#define MX6SL_PAD_AUD_TXC__ECSPI3_MISO             0x05c 0x2b4 0x6b8 0x1 0x0
+#define MX6SL_PAD_AUD_TXC__UART4_TX_DATA           0x05c 0x2b4 0x000 0x2 0x0
+#define MX6SL_PAD_AUD_TXC__UART4_RX_DATA           0x05c 0x2b4 0x814 0x2 0x1
+#define MX6SL_PAD_AUD_TXC__FEC_RX_DV               0x05c 0x2b4 0x704 0x3 0x0
+#define MX6SL_PAD_AUD_TXC__SD2_LCTL                0x05c 0x2b4 0x000 0x4 0x0
+#define MX6SL_PAD_AUD_TXC__GPIO1_IO03              0x05c 0x2b4 0x000 0x5 0x0
+#define MX6SL_PAD_AUD_TXD__AUD3_TXD                0x060 0x2b8 0x000 0x0 0x0
+#define MX6SL_PAD_AUD_TXD__ECSPI3_SCLK             0x060 0x2b8 0x6b0 0x1 0x0
+#define MX6SL_PAD_AUD_TXD__UART4_CTS_B             0x060 0x2b8 0x000 0x2 0x0
+#define MX6SL_PAD_AUD_TXD__UART4_RTS_B             0x060 0x2b8 0x810 0x2 0x0
+#define MX6SL_PAD_AUD_TXD__FEC_TX_DATA0            0x060 0x2b8 0x000 0x3 0x0
+#define MX6SL_PAD_AUD_TXD__SD4_LCTL                0x060 0x2b8 0x000 0x4 0x0
+#define MX6SL_PAD_AUD_TXD__GPIO1_IO05              0x060 0x2b8 0x000 0x5 0x0
+#define MX6SL_PAD_AUD_TXFS__AUD3_TXFS              0x064 0x2bc 0x000 0x0 0x0
+#define MX6SL_PAD_AUD_TXFS__PWM3_OUT               0x064 0x2bc 0x000 0x1 0x0
+#define MX6SL_PAD_AUD_TXFS__UART4_RTS_B            0x064 0x2bc 0x810 0x2 0x1
+#define MX6SL_PAD_AUD_TXFS__UART4_CTS_B            0x064 0x2bc 0x000 0x2 0x0
+#define MX6SL_PAD_AUD_TXFS__FEC_RX_DATA1           0x064 0x2bc 0x6fc 0x3 0x0
+#define MX6SL_PAD_AUD_TXFS__SD3_LCTL               0x064 0x2bc 0x000 0x4 0x0
+#define MX6SL_PAD_AUD_TXFS__GPIO1_IO04             0x064 0x2bc 0x000 0x5 0x0
+#define MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO         0x068 0x358 0x684 0x0 0x0
+#define MX6SL_PAD_ECSPI1_MISO__AUD4_TXFS           0x068 0x358 0x5f8 0x1 0x0
+#define MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B         0x068 0x358 0x818 0x2 0x0
+#define MX6SL_PAD_ECSPI1_MISO__UART5_CTS_B         0x068 0x358 0x000 0x2 0x0
+#define MX6SL_PAD_ECSPI1_MISO__EPDC_BDR0           0x068 0x358 0x000 0x3 0x0
+#define MX6SL_PAD_ECSPI1_MISO__SD2_WP              0x068 0x358 0x834 0x4 0x0
+#define MX6SL_PAD_ECSPI1_MISO__GPIO4_IO10          0x068 0x358 0x000 0x5 0x0
+#define MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI         0x06c 0x35c 0x688 0x0 0x0
+#define MX6SL_PAD_ECSPI1_MOSI__AUD4_TXC            0x06c 0x35c 0x5f4 0x1 0x0
+#define MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA       0x06c 0x35c 0x000 0x2 0x0
+#define MX6SL_PAD_ECSPI1_MOSI__UART5_RX_DATA       0x06c 0x35c 0x81c 0x2 0x0
+#define MX6SL_PAD_ECSPI1_MOSI__EPDC_VCOM1          0x06c 0x35c 0x000 0x3 0x0
+#define MX6SL_PAD_ECSPI1_MOSI__SD2_VSELECT         0x06c 0x35c 0x000 0x4 0x0
+#define MX6SL_PAD_ECSPI1_MOSI__GPIO4_IO09          0x06c 0x35c 0x000 0x5 0x0
+#define MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK         0x070 0x360 0x67c 0x0 0x0
+#define MX6SL_PAD_ECSPI1_SCLK__AUD4_TXD            0x070 0x360 0x5e8 0x1 0x0
+#define MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA       0x070 0x360 0x81c 0x2 0x1
+#define MX6SL_PAD_ECSPI1_SCLK__UART5_TX_DATA       0x070 0x360 0x000 0x2 0x0
+#define MX6SL_PAD_ECSPI1_SCLK__EPDC_VCOM0          0x070 0x360 0x000 0x3 0x0
+#define MX6SL_PAD_ECSPI1_SCLK__SD2_RESET           0x070 0x360 0x000 0x4 0x0
+#define MX6SL_PAD_ECSPI1_SCLK__GPIO4_IO08          0x070 0x360 0x000 0x5 0x0
+#define MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC         0x070 0x360 0x820 0x6 0x0
+#define MX6SL_PAD_ECSPI1_SS0__ECSPI1_SS0           0x074 0x364 0x68c 0x0 0x0
+#define MX6SL_PAD_ECSPI1_SS0__AUD4_RXD             0x074 0x364 0x5e4 0x1 0x0
+#define MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B          0x074 0x364 0x000 0x2 0x0
+#define MX6SL_PAD_ECSPI1_SS0__UART5_RTS_B          0x074 0x364 0x818 0x2 0x1
+#define MX6SL_PAD_ECSPI1_SS0__EPDC_BDR1            0x074 0x364 0x000 0x3 0x0
+#define MX6SL_PAD_ECSPI1_SS0__SD2_CD_B             0x074 0x364 0x830 0x4 0x0
+#define MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11           0x074 0x364 0x000 0x5 0x0
+#define MX6SL_PAD_ECSPI1_SS0__USB_OTG2_PWR         0x074 0x364 0x000 0x6 0x0
+#define MX6SL_PAD_ECSPI2_MISO__ECSPI2_MISO         0x078 0x368 0x6a0 0x0 0x0
+#define MX6SL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0     0x078 0x368 0x000 0x1 0x0
+#define MX6SL_PAD_ECSPI2_MISO__UART3_RTS_B         0x078 0x368 0x808 0x2 0x0
+#define MX6SL_PAD_ECSPI2_MISO__UART3_CTS_B         0x078 0x368 0x000 0x2 0x0
+#define MX6SL_PAD_ECSPI2_MISO__CSI_MCLK            0x078 0x368 0x000 0x3 0x0
+#define MX6SL_PAD_ECSPI2_MISO__SD1_WP              0x078 0x368 0x82c 0x4 0x0
+#define MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14          0x078 0x368 0x000 0x5 0x0
+#define MX6SL_PAD_ECSPI2_MISO__USB_OTG1_OC         0x078 0x368 0x824 0x6 0x0
+#define MX6SL_PAD_ECSPI2_MOSI__ECSPI2_MOSI         0x07c 0x36c 0x6a4 0x0 0x0
+#define MX6SL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1     0x07c 0x36c 0x000 0x1 0x0
+#define MX6SL_PAD_ECSPI2_MOSI__UART3_TX_DATA       0x07c 0x36c 0x000 0x2 0x0
+#define MX6SL_PAD_ECSPI2_MOSI__UART3_RX_DATA       0x07c 0x36c 0x80c 0x2 0x2
+#define MX6SL_PAD_ECSPI2_MOSI__CSI_HSYNC           0x07c 0x36c 0x670 0x3 0x0
+#define MX6SL_PAD_ECSPI2_MOSI__SD1_VSELECT         0x07c 0x36c 0x000 0x4 0x0
+#define MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13          0x07c 0x36c 0x000 0x5 0x0
+#define MX6SL_PAD_ECSPI2_SCLK__ECSPI2_SCLK         0x080 0x370 0x69c 0x0 0x0
+#define MX6SL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK       0x080 0x370 0x7f4 0x1 0x1
+#define MX6SL_PAD_ECSPI2_SCLK__UART3_RX_DATA       0x080 0x370 0x80c 0x2 0x3
+#define MX6SL_PAD_ECSPI2_SCLK__UART3_TX_DATA       0x080 0x370 0x000 0x2 0x0
+#define MX6SL_PAD_ECSPI2_SCLK__CSI_PIXCLK          0x080 0x370 0x674 0x3 0x0
+#define MX6SL_PAD_ECSPI2_SCLK__SD1_RESET           0x080 0x370 0x000 0x4 0x0
+#define MX6SL_PAD_ECSPI2_SCLK__GPIO4_IO12          0x080 0x370 0x000 0x5 0x0
+#define MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC         0x080 0x370 0x820 0x6 0x1
+#define MX6SL_PAD_ECSPI2_SS0__ECSPI2_SS0           0x084 0x374 0x6a8 0x0 0x0
+#define MX6SL_PAD_ECSPI2_SS0__ECSPI1_SS3           0x084 0x374 0x698 0x1 0x0
+#define MX6SL_PAD_ECSPI2_SS0__UART3_CTS_B          0x084 0x374 0x000 0x2 0x0
+#define MX6SL_PAD_ECSPI2_SS0__UART3_RTS_B          0x084 0x374 0x808 0x2 0x1
+#define MX6SL_PAD_ECSPI2_SS0__CSI_VSYNC            0x084 0x374 0x678 0x3 0x0
+#define MX6SL_PAD_ECSPI2_SS0__SD1_CD_B             0x084 0x374 0x828 0x4 0x0
+#define MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15           0x084 0x374 0x000 0x5 0x0
+#define MX6SL_PAD_ECSPI2_SS0__USB_OTG1_PWR         0x084 0x374 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_BDR0__EPDC_BDR0             0x088 0x378 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_BDR0__SD4_CLK               0x088 0x378 0x850 0x1 0x0
+#define MX6SL_PAD_EPDC_BDR0__UART3_RTS_B           0x088 0x378 0x808 0x2 0x2
+#define MX6SL_PAD_EPDC_BDR0__UART3_CTS_B           0x088 0x378 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_BDR0__EIM_ADDR26            0x088 0x378 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_BDR0__SPDC_RL               0x088 0x378 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_BDR0__GPIO2_IO05            0x088 0x378 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_BDR0__EPDC_SDCE7            0x088 0x378 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_BDR1__EPDC_BDR1             0x08c 0x37c 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_BDR1__SD4_CMD               0x08c 0x37c 0x858 0x1 0x0
+#define MX6SL_PAD_EPDC_BDR1__UART3_CTS_B           0x08c 0x37c 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_BDR1__UART3_RTS_B           0x08c 0x37c 0x808 0x2 0x3
+#define MX6SL_PAD_EPDC_BDR1__EIM_CRE               0x08c 0x37c 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_BDR1__SPDC_UD               0x08c 0x37c 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_BDR1__GPIO2_IO06            0x08c 0x37c 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_BDR1__EPDC_SDCE8            0x08c 0x37c 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_D0__EPDC_DATA00             0x090 0x380 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D0__ECSPI4_MOSI             0x090 0x380 0x6d8 0x1 0x0
+#define MX6SL_PAD_EPDC_D0__LCD_DATA24              0x090 0x380 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D0__CSI_DATA00              0x090 0x380 0x630 0x3 0x0
+#define MX6SL_PAD_EPDC_D0__SPDC_DATA00             0x090 0x380 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D0__GPIO1_IO07              0x090 0x380 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D1__EPDC_DATA01             0x094 0x384 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D1__ECSPI4_MISO             0x094 0x384 0x6d4 0x1 0x0
+#define MX6SL_PAD_EPDC_D1__LCD_DATA25              0x094 0x384 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D1__CSI_DATA01              0x094 0x384 0x634 0x3 0x0
+#define MX6SL_PAD_EPDC_D1__SPDC_DATA01             0x094 0x384 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D1__GPIO1_IO08              0x094 0x384 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D10__EPDC_DATA10            0x098 0x388 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D10__ECSPI3_SS0             0x098 0x388 0x6c0 0x1 0x1
+#define MX6SL_PAD_EPDC_D10__EPDC_PWR_CTRL2         0x098 0x388 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D10__EIM_ADDR18             0x098 0x388 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_D10__SPDC_DATA10            0x098 0x388 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D10__GPIO1_IO17             0x098 0x388 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D10__SD4_WP                 0x098 0x388 0x87c 0x6 0x0
+#define MX6SL_PAD_EPDC_D11__EPDC_DATA11            0x09c 0x38c 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D11__ECSPI3_SCLK            0x09c 0x38c 0x6b0 0x1 0x1
+#define MX6SL_PAD_EPDC_D11__EPDC_PWR_CTRL3         0x09c 0x38c 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D11__EIM_ADDR19             0x09c 0x38c 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_D11__SPDC_DATA11            0x09c 0x38c 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D11__GPIO1_IO18             0x09c 0x38c 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D11__SD4_CD_B               0x09c 0x38c 0x854 0x6 0x0
+#define MX6SL_PAD_EPDC_D12__EPDC_DATA12            0x0a0 0x390 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D12__UART2_RX_DATA          0x0a0 0x390 0x804 0x1 0x0
+#define MX6SL_PAD_EPDC_D12__UART2_TX_DATA          0x0a0 0x390 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_D12__EPDC_PWR_COM           0x0a0 0x390 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D12__EIM_ADDR20             0x0a0 0x390 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_D12__SPDC_DATA12            0x0a0 0x390 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D12__GPIO1_IO19             0x0a0 0x390 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D12__ECSPI3_SS1             0x0a0 0x390 0x6c4 0x6 0x1
+#define MX6SL_PAD_EPDC_D13__EPDC_DATA13            0x0a4 0x394 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D13__UART2_TX_DATA          0x0a4 0x394 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_D13__UART2_RX_DATA          0x0a4 0x394 0x804 0x1 0x1
+#define MX6SL_PAD_EPDC_D13__EPDC_PWR_IRQ           0x0a4 0x394 0x6e8 0x2 0x0
+#define MX6SL_PAD_EPDC_D13__EIM_ADDR21             0x0a4 0x394 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_D13__SPDC_DATA13            0x0a4 0x394 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D13__GPIO1_IO20             0x0a4 0x394 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D13__ECSPI3_SS2             0x0a4 0x394 0x6c8 0x6 0x0
+#define MX6SL_PAD_EPDC_D14__EPDC_DATA14            0x0a8 0x398 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D14__UART2_RTS_B            0x0a8 0x398 0x800 0x1 0x0
+#define MX6SL_PAD_EPDC_D14__UART2_CTS_B            0x0a8 0x398 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_D14__EPDC_PWR_STAT          0x0a8 0x398 0x6ec 0x2 0x0
+#define MX6SL_PAD_EPDC_D14__EIM_ADDR22             0x0a8 0x398 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_D14__SPDC_DATA14            0x0a8 0x398 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D14__GPIO1_IO21             0x0a8 0x398 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D14__ECSPI3_SS3             0x0a8 0x398 0x6cc 0x6 0x0
+#define MX6SL_PAD_EPDC_D15__EPDC_DATA15            0x0ac 0x39c 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D15__UART2_CTS_B            0x0ac 0x39c 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_D15__UART2_RTS_B            0x0ac 0x39c 0x800 0x1 0x1
+#define MX6SL_PAD_EPDC_D15__EPDC_PWR_WAKE          0x0ac 0x39c 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D15__EIM_ADDR23             0x0ac 0x39c 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_D15__SPDC_DATA15            0x0ac 0x39c 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D15__GPIO1_IO22             0x0ac 0x39c 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D15__ECSPI3_RDY             0x0ac 0x39c 0x6b4 0x6 0x1
+#define MX6SL_PAD_EPDC_D2__EPDC_DATA02             0x0b0 0x3a0 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D2__ECSPI4_SS0              0x0b0 0x3a0 0x6dc 0x1 0x0
+#define MX6SL_PAD_EPDC_D2__LCD_DATA26              0x0b0 0x3a0 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D2__CSI_DATA02              0x0b0 0x3a0 0x638 0x3 0x0
+#define MX6SL_PAD_EPDC_D2__SPDC_DATA02             0x0b0 0x3a0 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D2__GPIO1_IO09              0x0b0 0x3a0 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D3__EPDC_DATA03             0x0b4 0x3a4 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D3__ECSPI4_SCLK             0x0b4 0x3a4 0x6d0 0x1 0x0
+#define MX6SL_PAD_EPDC_D3__LCD_DATA27              0x0b4 0x3a4 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D3__CSI_DATA03              0x0b4 0x3a4 0x63c 0x3 0x0
+#define MX6SL_PAD_EPDC_D3__SPDC_DATA03             0x0b4 0x3a4 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D3__GPIO1_IO10              0x0b4 0x3a4 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D4__EPDC_DATA04             0x0b8 0x3a8 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D4__ECSPI4_SS1              0x0b8 0x3a8 0x6e0 0x1 0x0
+#define MX6SL_PAD_EPDC_D4__LCD_DATA28              0x0b8 0x3a8 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D4__CSI_DATA04              0x0b8 0x3a8 0x640 0x3 0x0
+#define MX6SL_PAD_EPDC_D4__SPDC_DATA04             0x0b8 0x3a8 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D4__GPIO1_IO11              0x0b8 0x3a8 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D5__EPDC_DATA05             0x0bc 0x3ac 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D5__ECSPI4_SS2              0x0bc 0x3ac 0x6e4 0x1 0x0
+#define MX6SL_PAD_EPDC_D5__LCD_DATA29              0x0bc 0x3ac 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D5__CSI_DATA05              0x0bc 0x3ac 0x644 0x3 0x0
+#define MX6SL_PAD_EPDC_D5__SPDC_DATA05             0x0bc 0x3ac 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D5__GPIO1_IO12              0x0bc 0x3ac 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D6__EPDC_DATA06             0x0c0 0x3b0 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D6__ECSPI4_SS3              0x0c0 0x3b0 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_D6__LCD_DATA30              0x0c0 0x3b0 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D6__CSI_DATA06              0x0c0 0x3b0 0x648 0x3 0x0
+#define MX6SL_PAD_EPDC_D6__SPDC_DATA06             0x0c0 0x3b0 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D6__GPIO1_IO13              0x0c0 0x3b0 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D7__EPDC_DATA07             0x0c4 0x3b4 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D7__ECSPI4_RDY              0x0c4 0x3b4 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_D7__LCD_DATA31              0x0c4 0x3b4 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D7__CSI_DATA07              0x0c4 0x3b4 0x64c 0x3 0x0
+#define MX6SL_PAD_EPDC_D7__SPDC_DATA07             0x0c4 0x3b4 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D7__GPIO1_IO14              0x0c4 0x3b4 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D8__EPDC_DATA08             0x0c8 0x3b8 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D8__ECSPI3_MOSI             0x0c8 0x3b8 0x6bc 0x1 0x1
+#define MX6SL_PAD_EPDC_D8__EPDC_PWR_CTRL0          0x0c8 0x3b8 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D8__EIM_ADDR16              0x0c8 0x3b8 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_D8__SPDC_DATA08             0x0c8 0x3b8 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D8__GPIO1_IO15              0x0c8 0x3b8 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D8__SD4_RESET               0x0c8 0x3b8 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_D9__EPDC_DATA09             0x0cc 0x3bc 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_D9__ECSPI3_MISO             0x0cc 0x3bc 0x6b8 0x1 0x1
+#define MX6SL_PAD_EPDC_D9__EPDC_PWR_CTRL1          0x0cc 0x3bc 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_D9__EIM_ADDR17              0x0cc 0x3bc 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_D9__SPDC_DATA09             0x0cc 0x3bc 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_D9__GPIO1_IO16              0x0cc 0x3bc 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_D9__SD4_VSELECT             0x0cc 0x3bc 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK           0x0d0 0x3c0 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_GDCLK__ECSPI2_SS2           0x0d0 0x3c0 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKR            0x0d0 0x3c0 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK           0x0d0 0x3c0 0x674 0x3 0x1
+#define MX6SL_PAD_EPDC_GDCLK__SPDC_YCKL            0x0d0 0x3c0 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_GDCLK__GPIO1_IO31           0x0d0 0x3c0 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_GDCLK__SD2_RESET            0x0d0 0x3c0 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_GDOE__EPDC_GDOE             0x0d4 0x3c4 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_GDOE__ECSPI2_SS3            0x0d4 0x3c4 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_GDOE__SPDC_YOER             0x0d4 0x3c4 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_GDOE__CSI_HSYNC             0x0d4 0x3c4 0x670 0x3 0x1
+#define MX6SL_PAD_EPDC_GDOE__SPDC_YOEL             0x0d4 0x3c4 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_GDOE__GPIO2_IO00            0x0d4 0x3c4 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_GDOE__SD2_VSELECT           0x0d4 0x3c4 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_GDRL__EPDC_GDRL             0x0d8 0x3c8 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_GDRL__ECSPI2_RDY            0x0d8 0x3c8 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUR           0x0d8 0x3c8 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_GDRL__CSI_MCLK              0x0d8 0x3c8 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_GDRL__SPDC_YDIOUL           0x0d8 0x3c8 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_GDRL__GPIO2_IO01            0x0d8 0x3c8 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_GDRL__SD2_WP                0x0d8 0x3c8 0x834 0x6 0x1
+#define MX6SL_PAD_EPDC_GDSP__EPDC_GDSP             0x0dc 0x3cc 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_GDSP__PWM4_OUT              0x0dc 0x3cc 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODR           0x0dc 0x3cc 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_GDSP__CSI_VSYNC             0x0dc 0x3cc 0x678 0x3 0x1
+#define MX6SL_PAD_EPDC_GDSP__SPDC_YDIODL           0x0dc 0x3cc 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_GDSP__GPIO2_IO02            0x0dc 0x3cc 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_GDSP__SD2_CD_B              0x0dc 0x3cc 0x830 0x6 0x1
+#define MX6SL_PAD_EPDC_PWRCOM__EPDC_PWR_COM        0x0e0 0x3d0 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_PWRCOM__SD4_DATA0           0x0e0 0x3d0 0x85c 0x1 0x0
+#define MX6SL_PAD_EPDC_PWRCOM__LCD_DATA20          0x0e0 0x3d0 0x7c8 0x2 0x0
+#define MX6SL_PAD_EPDC_PWRCOM__EIM_BCLK            0x0e0 0x3d0 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID         0x0e0 0x3d0 0x5dc 0x4 0x0
+#define MX6SL_PAD_EPDC_PWRCOM__GPIO2_IO11          0x0e0 0x3d0 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_PWRCOM__SD3_RESET           0x0e0 0x3d0 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL0__EPDC_PWR_CTRL0    0x0e4 0x3d4 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL0__AUD5_RXC          0x0e4 0x3d4 0x604 0x1 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL0__LCD_DATA16        0x0e4 0x3d4 0x7b8 0x2 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL0__EIM_RW            0x0e4 0x3d4 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL0__SPDC_YCKL         0x0e4 0x3d4 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07        0x0e4 0x3d4 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL0__SD4_RESET         0x0e4 0x3d4 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL1__EPDC_PWR_CTRL1    0x0e8 0x3d8 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL1__AUD5_TXFS         0x0e8 0x3d8 0x610 0x1 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL1__LCD_DATA17        0x0e8 0x3d8 0x7bc 0x2 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL1__EIM_OE_B          0x0e8 0x3d8 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL1__SPDC_YOEL         0x0e8 0x3d8 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08        0x0e8 0x3d8 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL1__SD4_VSELECT       0x0e8 0x3d8 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL2__EPDC_PWR_CTRL2    0x0ec 0x3dc 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL2__AUD5_TXD          0x0ec 0x3dc 0x600 0x1 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL2__LCD_DATA18        0x0ec 0x3dc 0x7c0 0x2 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL2__EIM_CS0_B         0x0ec 0x3dc 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL2__SPDC_YDIOUL       0x0ec 0x3dc 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09        0x0ec 0x3dc 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL2__SD4_WP            0x0ec 0x3dc 0x87c 0x6 0x1
+#define MX6SL_PAD_EPDC_PWRCTRL3__EPDC_PWR_CTRL3    0x0f0 0x3e0 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL3__AUD5_TXC          0x0f0 0x3e0 0x60c 0x1 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL3__LCD_DATA19        0x0f0 0x3e0 0x7c4 0x2 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL3__EIM_CS1_B         0x0f0 0x3e0 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL3__SPDC_YDIODL       0x0f0 0x3e0 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10        0x0f0 0x3e0 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_PWRCTRL3__SD4_CD_B          0x0f0 0x3e0 0x854 0x6 0x1
+#define MX6SL_PAD_EPDC_PWRINT__EPDC_PWR_IRQ        0x0f4 0x3e4 0x6e8 0x0 0x1
+#define MX6SL_PAD_EPDC_PWRINT__SD4_DATA1           0x0f4 0x3e4 0x860 0x1 0x0
+#define MX6SL_PAD_EPDC_PWRINT__LCD_DATA21          0x0f4 0x3e4 0x7cc 0x2 0x0
+#define MX6SL_PAD_EPDC_PWRINT__EIM_ACLK_FREERUN    0x0f4 0x3e4 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_PWRINT__USB_OTG2_ID         0x0f4 0x3e4 0x5e0 0x4 0x0
+#define MX6SL_PAD_EPDC_PWRINT__GPIO2_IO12          0x0f4 0x3e4 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_PWRINT__SD3_VSELECT         0x0f4 0x3e4 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_PWRSTAT__EPDC_PWR_STAT      0x0f8 0x3e8 0x6ec 0x0 0x1
+#define MX6SL_PAD_EPDC_PWRSTAT__SD4_DATA2          0x0f8 0x3e8 0x864 0x1 0x0
+#define MX6SL_PAD_EPDC_PWRSTAT__LCD_DATA22         0x0f8 0x3e8 0x7d0 0x2 0x0
+#define MX6SL_PAD_EPDC_PWRSTAT__EIM_WAIT_B         0x0f8 0x3e8 0x884 0x3 0x0
+#define MX6SL_PAD_EPDC_PWRSTAT__ARM_EVENTI         0x0f8 0x3e8 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13         0x0f8 0x3e8 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_PWRSTAT__SD3_WP             0x0f8 0x3e8 0x84c 0x6 0x0
+#define MX6SL_PAD_EPDC_PWRWAKEUP__EPDC_PWR_WAKE    0x0fc 0x3ec 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_PWRWAKEUP__SD4_DATA3        0x0fc 0x3ec 0x868 0x1 0x0
+#define MX6SL_PAD_EPDC_PWRWAKEUP__LCD_DATA23       0x0fc 0x3ec 0x7d4 0x2 0x0
+#define MX6SL_PAD_EPDC_PWRWAKEUP__EIM_DTACK_B      0x0fc 0x3ec 0x880 0x3 0x0
+#define MX6SL_PAD_EPDC_PWRWAKEUP__ARM_EVENTO       0x0fc 0x3ec 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14       0x0fc 0x3ec 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_PWRWAKEUP__SD3_CD_B         0x0fc 0x3ec 0x838 0x6 0x0
+#define MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0           0x100 0x3f0 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_SDCE0__ECSPI2_SS1           0x100 0x3f0 0x6ac 0x1 0x0
+#define MX6SL_PAD_EPDC_SDCE0__PWM3_OUT             0x100 0x3f0 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_SDCE0__EIM_CS2_B            0x100 0x3f0 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_SDCE0__SPDC_YCKR            0x100 0x3f0 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_SDCE0__GPIO1_IO27           0x100 0x3f0 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1           0x104 0x3f4 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_SDCE1__WDOG2_B              0x104 0x3f4 0x000 0x1 0x0
+#define MX6SL_PAD_EPDC_SDCE1__PWM4_OUT             0x104 0x3f4 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_SDCE1__EIM_LBA_B            0x104 0x3f4 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_SDCE1__SPDC_YOER            0x104 0x3f4 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_SDCE1__GPIO1_IO28           0x104 0x3f4 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2           0x108 0x3f8 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_SDCE2__I2C3_SCL             0x108 0x3f8 0x72c 0x1 0x1
+#define MX6SL_PAD_EPDC_SDCE2__PWM1_OUT             0x108 0x3f8 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_SDCE2__EIM_EB0_B            0x108 0x3f8 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_SDCE2__SPDC_YDIOUR          0x108 0x3f8 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_SDCE2__GPIO1_IO29           0x108 0x3f8 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_SDCE3__EPDC_SDCE3           0x10c 0x3fc 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_SDCE3__I2C3_SDA             0x10c 0x3fc 0x730 0x1 0x1
+#define MX6SL_PAD_EPDC_SDCE3__PWM2_OUT             0x10c 0x3fc 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_SDCE3__EIM_EB1_B            0x10c 0x3fc 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_SDCE3__SPDC_YDIODR          0x10c 0x3fc 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_SDCE3__GPIO1_IO30           0x10c 0x3fc 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P         0x110 0x400 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_SDCLK__ECSPI2_MOSI          0x110 0x400 0x6a4 0x1 0x1
+#define MX6SL_PAD_EPDC_SDCLK__I2C2_SCL             0x110 0x400 0x724 0x2 0x0
+#define MX6SL_PAD_EPDC_SDCLK__CSI_DATA08           0x110 0x400 0x650 0x3 0x0
+#define MX6SL_PAD_EPDC_SDCLK__SPDC_CL              0x110 0x400 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_SDCLK__GPIO1_IO23           0x110 0x400 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_SDLE__EPDC_SDLE             0x114 0x404 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_SDLE__ECSPI2_MISO           0x114 0x404 0x6a0 0x1 0x1
+#define MX6SL_PAD_EPDC_SDLE__I2C2_SDA              0x114 0x404 0x728 0x2 0x0
+#define MX6SL_PAD_EPDC_SDLE__CSI_DATA09            0x114 0x404 0x654 0x3 0x0
+#define MX6SL_PAD_EPDC_SDLE__SPDC_LD               0x114 0x404 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_SDLE__GPIO1_IO24            0x114 0x404 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_SDOE__EPDC_SDOE             0x118 0x408 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_SDOE__ECSPI2_SS0            0x118 0x408 0x6a8 0x1 0x1
+#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOR            0x118 0x408 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_SDOE__CSI_DATA10            0x118 0x408 0x658 0x3 0x0
+#define MX6SL_PAD_EPDC_SDOE__SPDC_XDIOL            0x118 0x408 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_SDOE__GPIO1_IO25            0x118 0x408 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR           0x11c 0x40c 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_SDSHR__ECSPI2_SCLK          0x11c 0x40c 0x69c 0x1 0x1
+#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDCE4           0x11c 0x40c 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_SDSHR__CSI_DATA11           0x11c 0x40c 0x65c 0x3 0x0
+#define MX6SL_PAD_EPDC_SDSHR__SPDC_XDIOR           0x11c 0x40c 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26           0x11c 0x40c 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_VCOM0__EPDC_VCOM0           0x120 0x410 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_VCOM0__AUD5_RXFS            0x120 0x410 0x608 0x1 0x0
+#define MX6SL_PAD_EPDC_VCOM0__UART3_RX_DATA        0x120 0x410 0x80c 0x2 0x4
+#define MX6SL_PAD_EPDC_VCOM0__UART3_TX_DATA        0x120 0x410 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_VCOM0__EIM_ADDR24           0x120 0x410 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_VCOM0__SPDC_VCOM0           0x120 0x410 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03           0x120 0x410 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_VCOM0__EPDC_SDCE5           0x120 0x410 0x000 0x6 0x0
+#define MX6SL_PAD_EPDC_VCOM1__EPDC_VCOM1           0x124 0x414 0x000 0x0 0x0
+#define MX6SL_PAD_EPDC_VCOM1__AUD5_RXD             0x124 0x414 0x5fc 0x1 0x0
+#define MX6SL_PAD_EPDC_VCOM1__UART3_TX_DATA        0x124 0x414 0x000 0x2 0x0
+#define MX6SL_PAD_EPDC_VCOM1__UART3_RX_DATA        0x124 0x414 0x80c 0x2 0x5
+#define MX6SL_PAD_EPDC_VCOM1__EIM_ADDR25           0x124 0x414 0x000 0x3 0x0
+#define MX6SL_PAD_EPDC_VCOM1__SPDC_VCOM1           0x124 0x414 0x000 0x4 0x0
+#define MX6SL_PAD_EPDC_VCOM1__GPIO2_IO04           0x124 0x414 0x000 0x5 0x0
+#define MX6SL_PAD_EPDC_VCOM1__EPDC_SDCE6           0x124 0x414 0x000 0x6 0x0
+#define MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV            0x128 0x418 0x704 0x0 0x1
+#define MX6SL_PAD_FEC_CRS_DV__SD4_DATA1            0x128 0x418 0x860 0x1 0x1
+#define MX6SL_PAD_FEC_CRS_DV__AUD6_TXC             0x128 0x418 0x624 0x2 0x0
+#define MX6SL_PAD_FEC_CRS_DV__ECSPI4_MISO          0x128 0x418 0x6d4 0x3 0x1
+#define MX6SL_PAD_FEC_CRS_DV__GPT_COMPARE2         0x128 0x418 0x000 0x4 0x0
+#define MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25           0x128 0x418 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_CRS_DV__ARM_TRACE31          0x128 0x418 0x000 0x6 0x0
+#define MX6SL_PAD_FEC_MDC__FEC_MDC                 0x12c 0x41c 0x000 0x0 0x0
+#define MX6SL_PAD_FEC_MDC__SD4_DATA4               0x12c 0x41c 0x86c 0x1 0x0
+#define MX6SL_PAD_FEC_MDC__AUDIO_CLK_OUT           0x12c 0x41c 0x000 0x2 0x0
+#define MX6SL_PAD_FEC_MDC__SD1_RESET               0x12c 0x41c 0x000 0x3 0x0
+#define MX6SL_PAD_FEC_MDC__SD3_RESET               0x12c 0x41c 0x000 0x4 0x0
+#define MX6SL_PAD_FEC_MDC__GPIO4_IO23              0x12c 0x41c 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_MDC__ARM_TRACE29             0x12c 0x41c 0x000 0x6 0x0
+#define MX6SL_PAD_FEC_MDIO__FEC_MDIO               0x130 0x420 0x6f4 0x0 0x1
+#define MX6SL_PAD_FEC_MDIO__SD4_CLK                0x130 0x420 0x850 0x1 0x1
+#define MX6SL_PAD_FEC_MDIO__AUD6_RXFS              0x130 0x420 0x620 0x2 0x0
+#define MX6SL_PAD_FEC_MDIO__ECSPI4_SS0             0x130 0x420 0x6dc 0x3 0x1
+#define MX6SL_PAD_FEC_MDIO__GPT_CAPTURE1           0x130 0x420 0x710 0x4 0x0
+#define MX6SL_PAD_FEC_MDIO__GPIO4_IO20             0x130 0x420 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_MDIO__ARM_TRACE26            0x130 0x420 0x000 0x6 0x0
+#define MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT         0x134 0x424 0x000 0x0 0x0
+#define MX6SL_PAD_FEC_REF_CLK__SD4_RESET           0x134 0x424 0x000 0x1 0x0
+#define MX6SL_PAD_FEC_REF_CLK__WDOG1_B             0x134 0x424 0x000 0x2 0x0
+#define MX6SL_PAD_FEC_REF_CLK__PWM4_OUT            0x134 0x424 0x000 0x3 0x0
+#define MX6SL_PAD_FEC_REF_CLK__CCM_PMIC_READY      0x134 0x424 0x62c 0x4 0x0
+#define MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26          0x134 0x424 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_REF_CLK__SPDIF_EXT_CLK       0x134 0x424 0x7f4 0x6 0x2
+#define MX6SL_PAD_FEC_RX_ER__FEC_RX_ER             0x138 0x428 0x708 0x0 0x1
+#define MX6SL_PAD_FEC_RX_ER__SD4_DATA0             0x138 0x428 0x85c 0x1 0x1
+#define MX6SL_PAD_FEC_RX_ER__AUD6_RXD              0x138 0x428 0x614 0x2 0x0
+#define MX6SL_PAD_FEC_RX_ER__ECSPI4_MOSI           0x138 0x428 0x6d8 0x3 0x1
+#define MX6SL_PAD_FEC_RX_ER__GPT_COMPARE1          0x138 0x428 0x000 0x4 0x0
+#define MX6SL_PAD_FEC_RX_ER__GPIO4_IO19            0x138 0x428 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_RX_ER__ARM_TRACE25           0x138 0x428 0x000 0x6 0x0
+#define MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0           0x13c 0x42c 0x6f8 0x0 0x0
+#define MX6SL_PAD_FEC_RXD0__SD4_DATA5              0x13c 0x42c 0x870 0x1 0x0
+#define MX6SL_PAD_FEC_RXD0__USB_OTG1_ID            0x13c 0x42c 0x5dc 0x2 0x1
+#define MX6SL_PAD_FEC_RXD0__SD1_VSELECT            0x13c 0x42c 0x000 0x3 0x0
+#define MX6SL_PAD_FEC_RXD0__SD3_VSELECT            0x13c 0x42c 0x000 0x4 0x0
+#define MX6SL_PAD_FEC_RXD0__GPIO4_IO17             0x13c 0x42c 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_RXD0__ARM_TRACE24            0x13c 0x42c 0x000 0x6 0x0
+#define MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1           0x140 0x430 0x6fc 0x0 0x1
+#define MX6SL_PAD_FEC_RXD1__SD4_DATA2              0x140 0x430 0x864 0x1 0x1
+#define MX6SL_PAD_FEC_RXD1__AUD6_TXFS              0x140 0x430 0x628 0x2 0x0
+#define MX6SL_PAD_FEC_RXD1__ECSPI4_SS1             0x140 0x430 0x6e0 0x3 0x1
+#define MX6SL_PAD_FEC_RXD1__GPT_COMPARE3           0x140 0x430 0x000 0x4 0x0
+#define MX6SL_PAD_FEC_RXD1__GPIO4_IO18             0x140 0x430 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_RXD1__FEC_COL                0x140 0x430 0x6f0 0x6 0x0
+#define MX6SL_PAD_FEC_TX_CLK__FEC_TX_CLK           0x144 0x434 0x70c 0x0 0x1
+#define MX6SL_PAD_FEC_TX_CLK__SD4_CMD              0x144 0x434 0x858 0x1 0x1
+#define MX6SL_PAD_FEC_TX_CLK__AUD6_RXC             0x144 0x434 0x61c 0x2 0x0
+#define MX6SL_PAD_FEC_TX_CLK__ECSPI4_SCLK          0x144 0x434 0x6d0 0x3 0x1
+#define MX6SL_PAD_FEC_TX_CLK__GPT_CAPTURE2         0x144 0x434 0x714 0x4 0x0
+#define MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21           0x144 0x434 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_TX_CLK__ARM_TRACE27          0x144 0x434 0x000 0x6 0x0
+#define MX6SL_PAD_FEC_TX_EN__FEC_TX_EN             0x148 0x438 0x000 0x0 0x0
+#define MX6SL_PAD_FEC_TX_EN__SD4_DATA6             0x148 0x438 0x874 0x1 0x0
+#define MX6SL_PAD_FEC_TX_EN__SPDIF_IN              0x148 0x438 0x7f0 0x2 0x0
+#define MX6SL_PAD_FEC_TX_EN__SD1_WP                0x148 0x438 0x82c 0x3 0x1
+#define MX6SL_PAD_FEC_TX_EN__SD3_WP                0x148 0x438 0x84c 0x4 0x1
+#define MX6SL_PAD_FEC_TX_EN__GPIO4_IO22            0x148 0x438 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_TX_EN__ARM_TRACE28           0x148 0x438 0x000 0x6 0x0
+#define MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0           0x14c 0x43c 0x000 0x0 0x0
+#define MX6SL_PAD_FEC_TXD0__SD4_DATA3              0x14c 0x43c 0x868 0x1 0x1
+#define MX6SL_PAD_FEC_TXD0__AUD6_TXD               0x14c 0x43c 0x618 0x2 0x0
+#define MX6SL_PAD_FEC_TXD0__ECSPI4_SS2             0x14c 0x43c 0x6e4 0x3 0x1
+#define MX6SL_PAD_FEC_TXD0__GPT_CLKIN              0x14c 0x43c 0x718 0x4 0x0
+#define MX6SL_PAD_FEC_TXD0__GPIO4_IO24             0x14c 0x43c 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_TXD0__ARM_TRACE30            0x14c 0x43c 0x000 0x6 0x0
+#define MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1           0x150 0x440 0x000 0x0 0x0
+#define MX6SL_PAD_FEC_TXD1__SD4_DATA7              0x150 0x440 0x878 0x1 0x0
+#define MX6SL_PAD_FEC_TXD1__SPDIF_OUT              0x150 0x440 0x000 0x2 0x0
+#define MX6SL_PAD_FEC_TXD1__SD1_CD_B               0x150 0x440 0x828 0x3 0x1
+#define MX6SL_PAD_FEC_TXD1__SD3_CD_B               0x150 0x440 0x838 0x4 0x1
+#define MX6SL_PAD_FEC_TXD1__GPIO4_IO16             0x150 0x440 0x000 0x5 0x0
+#define MX6SL_PAD_FEC_TXD1__FEC_RX_CLK             0x150 0x440 0x700 0x6 0x0
+#define MX6SL_PAD_HSIC_DAT__USB_H_DATA             0x154 0x444 0x000 0x0 0x0
+#define MX6SL_PAD_HSIC_DAT__I2C1_SCL               0x154 0x444 0x71c 0x1 0x1
+#define MX6SL_PAD_HSIC_DAT__PWM1_OUT               0x154 0x444 0x000 0x2 0x0
+#define MX6SL_PAD_HSIC_DAT__XTALOSC_REF_CLK_24M    0x154 0x444 0x000 0x3 0x0
+#define MX6SL_PAD_HSIC_DAT__GPIO3_IO19             0x154 0x444 0x000 0x5 0x0
+#define MX6SL_PAD_HSIC_STROBE__USB_H_STROBE        0x158 0x448 0x000 0x0 0x0
+#define MX6SL_PAD_HSIC_STROBE__I2C1_SDA            0x158 0x448 0x720 0x1 0x1
+#define MX6SL_PAD_HSIC_STROBE__PWM2_OUT            0x158 0x448 0x000 0x2 0x0
+#define MX6SL_PAD_HSIC_STROBE__XTALOSC_REF_CLK_32K 0x158 0x448 0x000 0x3 0x0
+#define MX6SL_PAD_HSIC_STROBE__GPIO3_IO20          0x158 0x448 0x000 0x5 0x0
+#define MX6SL_PAD_I2C1_SCL__I2C1_SCL               0x15c 0x44c 0x71c 0x0 0x2
+#define MX6SL_PAD_I2C1_SCL__UART1_RTS_B            0x15c 0x44c 0x7f8 0x1 0x0
+#define MX6SL_PAD_I2C1_SCL__UART1_CTS_B            0x15c 0x44c 0x000 0x1 0x0
+#define MX6SL_PAD_I2C1_SCL__ECSPI3_SS2             0x15c 0x44c 0x6c8 0x2 0x1
+#define MX6SL_PAD_I2C1_SCL__FEC_RX_DATA0           0x15c 0x44c 0x6f8 0x3 0x1
+#define MX6SL_PAD_I2C1_SCL__SD3_RESET              0x15c 0x44c 0x000 0x4 0x0
+#define MX6SL_PAD_I2C1_SCL__GPIO3_IO12             0x15c 0x44c 0x000 0x5 0x0
+#define MX6SL_PAD_I2C1_SCL__ECSPI1_SS1             0x15c 0x44c 0x690 0x6 0x0
+#define MX6SL_PAD_I2C1_SDA__I2C1_SDA               0x160 0x450 0x720 0x0 0x2
+#define MX6SL_PAD_I2C1_SDA__UART1_CTS_B            0x160 0x450 0x000 0x1 0x0
+#define MX6SL_PAD_I2C1_SDA__UART1_RTS_B            0x160 0x450 0x7f8 0x1 0x1
+#define MX6SL_PAD_I2C1_SDA__ECSPI3_SS3             0x160 0x450 0x6cc 0x2 0x1
+#define MX6SL_PAD_I2C1_SDA__FEC_TX_EN              0x160 0x450 0x000 0x3 0x0
+#define MX6SL_PAD_I2C1_SDA__SD3_VSELECT            0x160 0x450 0x000 0x4 0x0
+#define MX6SL_PAD_I2C1_SDA__GPIO3_IO13             0x160 0x450 0x000 0x5 0x0
+#define MX6SL_PAD_I2C1_SDA__ECSPI1_SS2             0x160 0x450 0x694 0x6 0x0
+#define MX6SL_PAD_I2C2_SCL__I2C2_SCL               0x164 0x454 0x724 0x0 0x1
+#define MX6SL_PAD_I2C2_SCL__AUD4_RXFS              0x164 0x454 0x5f0 0x1 0x0
+#define MX6SL_PAD_I2C2_SCL__SPDIF_IN               0x164 0x454 0x7f0 0x2 0x1
+#define MX6SL_PAD_I2C2_SCL__FEC_TX_DATA1           0x164 0x454 0x000 0x3 0x0
+#define MX6SL_PAD_I2C2_SCL__SD3_WP                 0x164 0x454 0x84c 0x4 0x2
+#define MX6SL_PAD_I2C2_SCL__GPIO3_IO14             0x164 0x454 0x000 0x5 0x0
+#define MX6SL_PAD_I2C2_SCL__ECSPI1_RDY             0x164 0x454 0x680 0x6 0x0
+#define MX6SL_PAD_I2C2_SDA__I2C2_SDA               0x168 0x458 0x728 0x0 0x1
+#define MX6SL_PAD_I2C2_SDA__AUD4_RXC               0x168 0x458 0x5ec 0x1 0x0
+#define MX6SL_PAD_I2C2_SDA__SPDIF_OUT              0x168 0x458 0x000 0x2 0x0
+#define MX6SL_PAD_I2C2_SDA__FEC_REF_OUT            0x168 0x458 0x000 0x3 0x0
+#define MX6SL_PAD_I2C2_SDA__SD3_CD_B               0x168 0x458 0x838 0x4 0x2
+#define MX6SL_PAD_I2C2_SDA__GPIO3_IO15             0x168 0x458 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_COL0__KEY_COL0               0x16c 0x474 0x734 0x0 0x0
+#define MX6SL_PAD_KEY_COL0__I2C2_SCL               0x16c 0x474 0x724 0x1 0x2
+#define MX6SL_PAD_KEY_COL0__LCD_DATA00             0x16c 0x474 0x778 0x2 0x0
+#define MX6SL_PAD_KEY_COL0__EIM_AD00               0x16c 0x474 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_COL0__SD1_CD_B               0x16c 0x474 0x828 0x4 0x2
+#define MX6SL_PAD_KEY_COL0__GPIO3_IO24             0x16c 0x474 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_COL1__KEY_COL1               0x170 0x478 0x738 0x0 0x0
+#define MX6SL_PAD_KEY_COL1__ECSPI4_MOSI            0x170 0x478 0x6d8 0x1 0x2
+#define MX6SL_PAD_KEY_COL1__LCD_DATA02             0x170 0x478 0x780 0x2 0x0
+#define MX6SL_PAD_KEY_COL1__EIM_AD02               0x170 0x478 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_COL1__SD3_DATA4              0x170 0x478 0x83c 0x4 0x0
+#define MX6SL_PAD_KEY_COL1__GPIO3_IO26             0x170 0x478 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_COL2__KEY_COL2               0x174 0x47c 0x73c 0x0 0x0
+#define MX6SL_PAD_KEY_COL2__ECSPI4_SS0             0x174 0x47c 0x6dc 0x1 0x2
+#define MX6SL_PAD_KEY_COL2__LCD_DATA04             0x174 0x47c 0x788 0x2 0x0
+#define MX6SL_PAD_KEY_COL2__EIM_AD04               0x174 0x47c 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_COL2__SD3_DATA6              0x174 0x47c 0x844 0x4 0x0
+#define MX6SL_PAD_KEY_COL2__GPIO3_IO28             0x174 0x47c 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_COL3__KEY_COL3               0x178 0x480 0x740 0x0 0x0
+#define MX6SL_PAD_KEY_COL3__AUD6_RXFS              0x178 0x480 0x620 0x1 0x1
+#define MX6SL_PAD_KEY_COL3__LCD_DATA06             0x178 0x480 0x790 0x2 0x0
+#define MX6SL_PAD_KEY_COL3__EIM_AD06               0x178 0x480 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_COL3__SD4_DATA6              0x178 0x480 0x874 0x4 0x1
+#define MX6SL_PAD_KEY_COL3__GPIO3_IO30             0x178 0x480 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_COL3__SD1_RESET              0x178 0x480 0x000 0x6 0x0
+#define MX6SL_PAD_KEY_COL4__KEY_COL4               0x17c 0x484 0x744 0x0 0x0
+#define MX6SL_PAD_KEY_COL4__AUD6_RXD               0x17c 0x484 0x614 0x1 0x1
+#define MX6SL_PAD_KEY_COL4__LCD_DATA08             0x17c 0x484 0x798 0x2 0x0
+#define MX6SL_PAD_KEY_COL4__EIM_AD08               0x17c 0x484 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_COL4__SD4_CLK                0x17c 0x484 0x850 0x4 0x2
+#define MX6SL_PAD_KEY_COL4__GPIO4_IO00             0x17c 0x484 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_COL4__USB_OTG1_PWR           0x17c 0x484 0x000 0x6 0x0
+#define MX6SL_PAD_KEY_COL5__KEY_COL5               0x180 0x488 0x748 0x0 0x0
+#define MX6SL_PAD_KEY_COL5__AUD6_TXFS              0x180 0x488 0x628 0x1 0x1
+#define MX6SL_PAD_KEY_COL5__LCD_DATA10             0x180 0x488 0x7a0 0x2 0x0
+#define MX6SL_PAD_KEY_COL5__EIM_AD10               0x180 0x488 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_COL5__SD4_DATA0              0x180 0x488 0x85c 0x4 0x2
+#define MX6SL_PAD_KEY_COL5__GPIO4_IO02             0x180 0x488 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_COL5__USB_OTG2_PWR           0x180 0x488 0x000 0x6 0x0
+#define MX6SL_PAD_KEY_COL6__KEY_COL6               0x184 0x48c 0x74c 0x0 0x0
+#define MX6SL_PAD_KEY_COL6__UART4_RX_DATA          0x184 0x48c 0x814 0x1 0x2
+#define MX6SL_PAD_KEY_COL6__UART4_TX_DATA          0x184 0x48c 0x000 0x1 0x0
+#define MX6SL_PAD_KEY_COL6__LCD_DATA12             0x184 0x48c 0x7a8 0x2 0x0
+#define MX6SL_PAD_KEY_COL6__EIM_AD12               0x184 0x48c 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_COL6__SD4_DATA2              0x184 0x48c 0x864 0x4 0x2
+#define MX6SL_PAD_KEY_COL6__GPIO4_IO04             0x184 0x48c 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_COL6__SD3_RESET              0x184 0x48c 0x000 0x6 0x0
+#define MX6SL_PAD_KEY_COL7__KEY_COL7               0x188 0x490 0x750 0x0 0x0
+#define MX6SL_PAD_KEY_COL7__UART4_RTS_B            0x188 0x490 0x810 0x1 0x2
+#define MX6SL_PAD_KEY_COL7__UART4_CTS_B            0x188 0x490 0x000 0x1 0x0
+#define MX6SL_PAD_KEY_COL7__LCD_DATA14             0x188 0x490 0x7b0 0x2 0x0
+#define MX6SL_PAD_KEY_COL7__EIM_AD14               0x188 0x490 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_COL7__SD4_DATA4              0x188 0x490 0x86c 0x4 0x1
+#define MX6SL_PAD_KEY_COL7__GPIO4_IO06             0x188 0x490 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_COL7__SD1_WP                 0x188 0x490 0x82c 0x6 0x2
+#define MX6SL_PAD_KEY_ROW0__KEY_ROW0               0x18c 0x494 0x754 0x0 0x0
+#define MX6SL_PAD_KEY_ROW0__I2C2_SDA               0x18c 0x494 0x728 0x1 0x2
+#define MX6SL_PAD_KEY_ROW0__LCD_DATA01             0x18c 0x494 0x77c 0x2 0x0
+#define MX6SL_PAD_KEY_ROW0__EIM_AD01               0x18c 0x494 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_ROW0__SD1_WP                 0x18c 0x494 0x82c 0x4 0x3
+#define MX6SL_PAD_KEY_ROW0__GPIO3_IO25             0x18c 0x494 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_ROW1__KEY_ROW1               0x190 0x498 0x758 0x0 0x0
+#define MX6SL_PAD_KEY_ROW1__ECSPI4_MISO            0x190 0x498 0x6d4 0x1 0x2
+#define MX6SL_PAD_KEY_ROW1__LCD_DATA03             0x190 0x498 0x784 0x2 0x0
+#define MX6SL_PAD_KEY_ROW1__EIM_AD03               0x190 0x498 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_ROW1__SD3_DATA5              0x190 0x498 0x840 0x4 0x0
+#define MX6SL_PAD_KEY_ROW1__GPIO3_IO27             0x190 0x498 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_ROW2__KEY_ROW2               0x194 0x49c 0x75c 0x0 0x0
+#define MX6SL_PAD_KEY_ROW2__ECSPI4_SCLK            0x194 0x49c 0x6d0 0x1 0x2
+#define MX6SL_PAD_KEY_ROW2__LCD_DATA05             0x194 0x49c 0x78c 0x2 0x0
+#define MX6SL_PAD_KEY_ROW2__EIM_AD05               0x194 0x49c 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_ROW2__SD3_DATA7              0x194 0x49c 0x848 0x4 0x0
+#define MX6SL_PAD_KEY_ROW2__GPIO3_IO29             0x194 0x49c 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_ROW3__KEY_ROW3               0x198 0x4a0 0x760 0x0 0x0
+#define MX6SL_PAD_KEY_ROW3__AUD6_RXC               0x198 0x4a0 0x61c 0x1 0x1
+#define MX6SL_PAD_KEY_ROW3__LCD_DATA07             0x198 0x4a0 0x794 0x2 0x0
+#define MX6SL_PAD_KEY_ROW3__EIM_AD07               0x198 0x4a0 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_ROW3__SD4_DATA7              0x198 0x4a0 0x878 0x4 0x1
+#define MX6SL_PAD_KEY_ROW3__GPIO3_IO31             0x198 0x4a0 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_ROW3__SD1_VSELECT            0x198 0x4a0 0x000 0x6 0x0
+#define MX6SL_PAD_KEY_ROW4__KEY_ROW4               0x19c 0x4a4 0x764 0x0 0x0
+#define MX6SL_PAD_KEY_ROW4__AUD6_TXC               0x19c 0x4a4 0x624 0x1 0x1
+#define MX6SL_PAD_KEY_ROW4__LCD_DATA09             0x19c 0x4a4 0x79c 0x2 0x0
+#define MX6SL_PAD_KEY_ROW4__EIM_AD09               0x19c 0x4a4 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_ROW4__SD4_CMD                0x19c 0x4a4 0x858 0x4 0x2
+#define MX6SL_PAD_KEY_ROW4__GPIO4_IO01             0x19c 0x4a4 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_ROW4__USB_OTG1_OC            0x19c 0x4a4 0x824 0x6 0x1
+#define MX6SL_PAD_KEY_ROW5__KEY_ROW5               0x1a0 0x4a8 0x768 0x0 0x0
+#define MX6SL_PAD_KEY_ROW5__AUD6_TXD               0x1a0 0x4a8 0x618 0x1 0x1
+#define MX6SL_PAD_KEY_ROW5__LCD_DATA11             0x1a0 0x4a8 0x7a4 0x2 0x0
+#define MX6SL_PAD_KEY_ROW5__EIM_AD11               0x1a0 0x4a8 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_ROW5__SD4_DATA1              0x1a0 0x4a8 0x860 0x4 0x2
+#define MX6SL_PAD_KEY_ROW5__GPIO4_IO03             0x1a0 0x4a8 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_ROW5__USB_OTG2_OC            0x1a0 0x4a8 0x820 0x6 0x2
+#define MX6SL_PAD_KEY_ROW6__KEY_ROW6               0x1a4 0x4ac 0x76c 0x0 0x0
+#define MX6SL_PAD_KEY_ROW6__UART4_TX_DATA          0x1a4 0x4ac 0x000 0x1 0x0
+#define MX6SL_PAD_KEY_ROW6__UART4_RX_DATA          0x1a4 0x4ac 0x814 0x1 0x3
+#define MX6SL_PAD_KEY_ROW6__LCD_DATA13             0x1a4 0x4ac 0x7ac 0x2 0x0
+#define MX6SL_PAD_KEY_ROW6__EIM_AD13               0x1a4 0x4ac 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_ROW6__SD4_DATA3              0x1a4 0x4ac 0x868 0x4 0x2
+#define MX6SL_PAD_KEY_ROW6__GPIO4_IO05             0x1a4 0x4ac 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_ROW6__SD3_VSELECT            0x1a4 0x4ac 0x000 0x6 0x0
+#define MX6SL_PAD_KEY_ROW7__KEY_ROW7               0x1a8 0x4b0 0x770 0x0 0x0
+#define MX6SL_PAD_KEY_ROW7__UART4_CTS_B            0x1a8 0x4b0 0x000 0x1 0x0
+#define MX6SL_PAD_KEY_ROW7__UART4_RTS_B            0x1a8 0x4b0 0x810 0x1 0x3
+#define MX6SL_PAD_KEY_ROW7__LCD_DATA15             0x1a8 0x4b0 0x7b4 0x2 0x0
+#define MX6SL_PAD_KEY_ROW7__EIM_AD15               0x1a8 0x4b0 0x000 0x3 0x0
+#define MX6SL_PAD_KEY_ROW7__SD4_DATA5              0x1a8 0x4b0 0x870 0x4 0x1
+#define MX6SL_PAD_KEY_ROW7__GPIO4_IO07             0x1a8 0x4b0 0x000 0x5 0x0
+#define MX6SL_PAD_KEY_ROW7__SD1_CD_B               0x1a8 0x4b0 0x828 0x6 0x3
+#define MX6SL_PAD_LCD_CLK__LCD_CLK                 0x1ac 0x4b4 0x000 0x0 0x0
+#define MX6SL_PAD_LCD_CLK__SD4_DATA4               0x1ac 0x4b4 0x86c 0x1 0x2
+#define MX6SL_PAD_LCD_CLK__LCD_WR_RWN              0x1ac 0x4b4 0x000 0x2 0x0
+#define MX6SL_PAD_LCD_CLK__EIM_RW                  0x1ac 0x4b4 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_CLK__PWM4_OUT                0x1ac 0x4b4 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_CLK__GPIO2_IO15              0x1ac 0x4b4 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT0__LCD_DATA00             0x1b0 0x4b8 0x778 0x0 0x1
+#define MX6SL_PAD_LCD_DAT0__ECSPI1_MOSI            0x1b0 0x4b8 0x688 0x1 0x1
+#define MX6SL_PAD_LCD_DAT0__USB_OTG2_ID            0x1b0 0x4b8 0x5e0 0x2 0x1
+#define MX6SL_PAD_LCD_DAT0__PWM1_OUT               0x1b0 0x4b8 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT0__UART5_DTR_B            0x1b0 0x4b8 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_DAT0__GPIO2_IO20             0x1b0 0x4b8 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT0__ARM_TRACE00            0x1b0 0x4b8 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT0__SRC_BOOT_CFG00         0x1b0 0x4b8 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT1__LCD_DATA01             0x1b4 0x4bc 0x77c 0x0 0x1
+#define MX6SL_PAD_LCD_DAT1__ECSPI1_MISO            0x1b4 0x4bc 0x684 0x1 0x1
+#define MX6SL_PAD_LCD_DAT1__USB_OTG1_ID            0x1b4 0x4bc 0x5dc 0x2 0x2
+#define MX6SL_PAD_LCD_DAT1__PWM2_OUT               0x1b4 0x4bc 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT1__AUD4_RXFS              0x1b4 0x4bc 0x5f0 0x4 0x1
+#define MX6SL_PAD_LCD_DAT1__GPIO2_IO21             0x1b4 0x4bc 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT1__ARM_TRACE01            0x1b4 0x4bc 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT1__SRC_BOOT_CFG01         0x1b4 0x4bc 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT10__LCD_DATA10            0x1b8 0x4c0 0x7a0 0x0 0x1
+#define MX6SL_PAD_LCD_DAT10__KEY_COL1              0x1b8 0x4c0 0x738 0x1 0x1
+#define MX6SL_PAD_LCD_DAT10__CSI_DATA07            0x1b8 0x4c0 0x64c 0x2 0x1
+#define MX6SL_PAD_LCD_DAT10__EIM_DATA04            0x1b8 0x4c0 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT10__ECSPI2_MISO           0x1b8 0x4c0 0x6a0 0x4 0x2
+#define MX6SL_PAD_LCD_DAT10__GPIO2_IO30            0x1b8 0x4c0 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT10__ARM_TRACE10           0x1b8 0x4c0 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT10__SRC_BOOT_CFG10        0x1b8 0x4c0 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT11__LCD_DATA11            0x1bc 0x4c4 0x7a4 0x0 0x1
+#define MX6SL_PAD_LCD_DAT11__KEY_ROW1              0x1bc 0x4c4 0x758 0x1 0x1
+#define MX6SL_PAD_LCD_DAT11__CSI_DATA06            0x1bc 0x4c4 0x648 0x2 0x1
+#define MX6SL_PAD_LCD_DAT11__EIM_DATA05            0x1bc 0x4c4 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT11__ECSPI2_SS1            0x1bc 0x4c4 0x6ac 0x4 0x1
+#define MX6SL_PAD_LCD_DAT11__GPIO2_IO31            0x1bc 0x4c4 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT11__ARM_TRACE11           0x1bc 0x4c4 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT11__SRC_BOOT_CFG11        0x1bc 0x4c4 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT12__LCD_DATA12            0x1c0 0x4c8 0x7a8 0x0 0x1
+#define MX6SL_PAD_LCD_DAT12__KEY_COL2              0x1c0 0x4c8 0x73c 0x1 0x1
+#define MX6SL_PAD_LCD_DAT12__CSI_DATA05            0x1c0 0x4c8 0x644 0x2 0x1
+#define MX6SL_PAD_LCD_DAT12__EIM_DATA06            0x1c0 0x4c8 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT12__UART5_RTS_B           0x1c0 0x4c8 0x818 0x4 0x2
+#define MX6SL_PAD_LCD_DAT12__UART5_CTS_B           0x1c0 0x4c8 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_DAT12__GPIO3_IO00            0x1c0 0x4c8 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT12__ARM_TRACE12           0x1c0 0x4c8 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT12__SRC_BOOT_CFG12        0x1c0 0x4c8 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT13__LCD_DATA13            0x1c4 0x4cc 0x7ac 0x0 0x1
+#define MX6SL_PAD_LCD_DAT13__KEY_ROW2              0x1c4 0x4cc 0x75c 0x1 0x1
+#define MX6SL_PAD_LCD_DAT13__CSI_DATA04            0x1c4 0x4cc 0x640 0x2 0x1
+#define MX6SL_PAD_LCD_DAT13__EIM_DATA07            0x1c4 0x4cc 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT13__UART5_CTS_B           0x1c4 0x4cc 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_DAT13__UART5_RTS_B           0x1c4 0x4cc 0x818 0x4 0x3
+#define MX6SL_PAD_LCD_DAT13__GPIO3_IO01            0x1c4 0x4cc 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT13__ARM_TRACE13           0x1c4 0x4cc 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT13__SRC_BOOT_CFG13        0x1c4 0x4cc 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT14__LCD_DATA14            0x1c8 0x4d0 0x7b0 0x0 0x1
+#define MX6SL_PAD_LCD_DAT14__KEY_COL3              0x1c8 0x4d0 0x740 0x1 0x1
+#define MX6SL_PAD_LCD_DAT14__CSI_DATA03            0x1c8 0x4d0 0x63c 0x2 0x1
+#define MX6SL_PAD_LCD_DAT14__EIM_DATA08            0x1c8 0x4d0 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT14__UART5_RX_DATA         0x1c8 0x4d0 0x81c 0x4 0x2
+#define MX6SL_PAD_LCD_DAT14__UART5_TX_DATA         0x1c8 0x4d0 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_DAT14__GPIO3_IO02            0x1c8 0x4d0 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT14__ARM_TRACE14           0x1c8 0x4d0 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT14__SRC_BOOT_CFG14        0x1c8 0x4d0 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT15__LCD_DATA15            0x1cc 0x4d4 0x7b4 0x0 0x1
+#define MX6SL_PAD_LCD_DAT15__KEY_ROW3              0x1cc 0x4d4 0x760 0x1 0x1
+#define MX6SL_PAD_LCD_DAT15__CSI_DATA02            0x1cc 0x4d4 0x638 0x2 0x1
+#define MX6SL_PAD_LCD_DAT15__EIM_DATA09            0x1cc 0x4d4 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT15__UART5_TX_DATA         0x1cc 0x4d4 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_DAT15__UART5_RX_DATA         0x1cc 0x4d4 0x81c 0x4 0x3
+#define MX6SL_PAD_LCD_DAT15__GPIO3_IO03            0x1cc 0x4d4 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT15__ARM_TRACE15           0x1cc 0x4d4 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT15__SRC_BOOT_CFG15        0x1cc 0x4d4 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT16__LCD_DATA16            0x1d0 0x4d8 0x7b8 0x0 0x1
+#define MX6SL_PAD_LCD_DAT16__KEY_COL4              0x1d0 0x4d8 0x744 0x1 0x1
+#define MX6SL_PAD_LCD_DAT16__CSI_DATA01            0x1d0 0x4d8 0x634 0x2 0x1
+#define MX6SL_PAD_LCD_DAT16__EIM_DATA10            0x1d0 0x4d8 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT16__I2C2_SCL              0x1d0 0x4d8 0x724 0x4 0x3
+#define MX6SL_PAD_LCD_DAT16__GPIO3_IO04            0x1d0 0x4d8 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT16__ARM_TRACE16           0x1d0 0x4d8 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT16__SRC_BOOT_CFG24        0x1d0 0x4d8 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT17__LCD_DATA17            0x1d4 0x4dc 0x7bc 0x0 0x1
+#define MX6SL_PAD_LCD_DAT17__KEY_ROW4              0x1d4 0x4dc 0x764 0x1 0x1
+#define MX6SL_PAD_LCD_DAT17__CSI_DATA00            0x1d4 0x4dc 0x630 0x2 0x1
+#define MX6SL_PAD_LCD_DAT17__EIM_DATA11            0x1d4 0x4dc 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT17__I2C2_SDA              0x1d4 0x4dc 0x728 0x4 0x3
+#define MX6SL_PAD_LCD_DAT17__GPIO3_IO05            0x1d4 0x4dc 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT17__ARM_TRACE17           0x1d4 0x4dc 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT17__SRC_BOOT_CFG25        0x1d4 0x4dc 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT18__LCD_DATA18            0x1d8 0x4e0 0x7c0 0x0 0x1
+#define MX6SL_PAD_LCD_DAT18__KEY_COL5              0x1d8 0x4e0 0x748 0x1 0x1
+#define MX6SL_PAD_LCD_DAT18__CSI_DATA15            0x1d8 0x4e0 0x66c 0x2 0x0
+#define MX6SL_PAD_LCD_DAT18__EIM_DATA12            0x1d8 0x4e0 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT18__GPT_CAPTURE1          0x1d8 0x4e0 0x710 0x4 0x1
+#define MX6SL_PAD_LCD_DAT18__GPIO3_IO06            0x1d8 0x4e0 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT18__ARM_TRACE18           0x1d8 0x4e0 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT18__SRC_BOOT_CFG26        0x1d8 0x4e0 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT19__LCD_DATA19            0x1dc 0x4e4 0x7c4 0x0 0x1
+#define MX6SL_PAD_LCD_DAT19__KEY_ROW5              0x1dc 0x4e4 0x768 0x1 0x1
+#define MX6SL_PAD_LCD_DAT19__CSI_DATA14            0x1dc 0x4e4 0x668 0x2 0x0
+#define MX6SL_PAD_LCD_DAT19__EIM_DATA13            0x1dc 0x4e4 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT19__GPT_CAPTURE2          0x1dc 0x4e4 0x714 0x4 0x1
+#define MX6SL_PAD_LCD_DAT19__GPIO3_IO07            0x1dc 0x4e4 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT19__ARM_TRACE19           0x1dc 0x4e4 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT19__SRC_BOOT_CFG27        0x1dc 0x4e4 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT2__LCD_DATA02             0x1e0 0x4e8 0x780 0x0 0x1
+#define MX6SL_PAD_LCD_DAT2__ECSPI1_SS0             0x1e0 0x4e8 0x68c 0x1 0x1
+#define MX6SL_PAD_LCD_DAT2__EPIT2_OUT              0x1e0 0x4e8 0x000 0x2 0x0
+#define MX6SL_PAD_LCD_DAT2__PWM3_OUT               0x1e0 0x4e8 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT2__AUD4_RXC               0x1e0 0x4e8 0x5ec 0x4 0x1
+#define MX6SL_PAD_LCD_DAT2__GPIO2_IO22             0x1e0 0x4e8 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT2__ARM_TRACE02            0x1e0 0x4e8 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT2__SRC_BOOT_CFG02         0x1e0 0x4e8 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT20__LCD_DATA20            0x1e4 0x4ec 0x7c8 0x0 0x1
+#define MX6SL_PAD_LCD_DAT20__KEY_COL6              0x1e4 0x4ec 0x74c 0x1 0x1
+#define MX6SL_PAD_LCD_DAT20__CSI_DATA13            0x1e4 0x4ec 0x664 0x2 0x0
+#define MX6SL_PAD_LCD_DAT20__EIM_DATA14            0x1e4 0x4ec 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT20__GPT_COMPARE1          0x1e4 0x4ec 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_DAT20__GPIO3_IO08            0x1e4 0x4ec 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT20__ARM_TRACE20           0x1e4 0x4ec 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT20__SRC_BOOT_CFG28        0x1e4 0x4ec 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT21__LCD_DATA21            0x1e8 0x4f0 0x7cc 0x0 0x1
+#define MX6SL_PAD_LCD_DAT21__KEY_ROW6              0x1e8 0x4f0 0x76c 0x1 0x1
+#define MX6SL_PAD_LCD_DAT21__CSI_DATA12            0x1e8 0x4f0 0x660 0x2 0x0
+#define MX6SL_PAD_LCD_DAT21__EIM_DATA15            0x1e8 0x4f0 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT21__GPT_COMPARE2          0x1e8 0x4f0 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_DAT21__GPIO3_IO09            0x1e8 0x4f0 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT21__ARM_TRACE21           0x1e8 0x4f0 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT21__SRC_BOOT_CFG29        0x1e8 0x4f0 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT22__LCD_DATA22            0x1ec 0x4f4 0x7d0 0x0 0x1
+#define MX6SL_PAD_LCD_DAT22__KEY_COL7              0x1ec 0x4f4 0x750 0x1 0x1
+#define MX6SL_PAD_LCD_DAT22__CSI_DATA11            0x1ec 0x4f4 0x65c 0x2 0x1
+#define MX6SL_PAD_LCD_DAT22__EIM_EB3_B             0x1ec 0x4f4 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT22__GPT_COMPARE3          0x1ec 0x4f4 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_DAT22__GPIO3_IO10            0x1ec 0x4f4 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT22__ARM_TRACE22           0x1ec 0x4f4 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT22__SRC_BOOT_CFG30        0x1ec 0x4f4 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT23__LCD_DATA23            0x1f0 0x4f8 0x7d4 0x0 0x1
+#define MX6SL_PAD_LCD_DAT23__KEY_ROW7              0x1f0 0x4f8 0x770 0x1 0x1
+#define MX6SL_PAD_LCD_DAT23__CSI_DATA10            0x1f0 0x4f8 0x658 0x2 0x1
+#define MX6SL_PAD_LCD_DAT23__EIM_EB2_B             0x1f0 0x4f8 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT23__GPT_CLKIN             0x1f0 0x4f8 0x718 0x4 0x1
+#define MX6SL_PAD_LCD_DAT23__GPIO3_IO11            0x1f0 0x4f8 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT23__ARM_TRACE23           0x1f0 0x4f8 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT23__SRC_BOOT_CFG31        0x1f0 0x4f8 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT3__LCD_DATA03             0x1f4 0x4fc 0x784 0x0 0x1
+#define MX6SL_PAD_LCD_DAT3__ECSPI1_SCLK            0x1f4 0x4fc 0x67c 0x1 0x1
+#define MX6SL_PAD_LCD_DAT3__UART5_DSR_B            0x1f4 0x4fc 0x000 0x2 0x0
+#define MX6SL_PAD_LCD_DAT3__PWM4_OUT               0x1f4 0x4fc 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT3__AUD4_RXD               0x1f4 0x4fc 0x5e4 0x4 0x1
+#define MX6SL_PAD_LCD_DAT3__GPIO2_IO23             0x1f4 0x4fc 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT3__ARM_TRACE03            0x1f4 0x4fc 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT3__SRC_BOOT_CFG03         0x1f4 0x4fc 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT4__LCD_DATA04             0x1f8 0x500 0x788 0x0 0x1
+#define MX6SL_PAD_LCD_DAT4__ECSPI1_SS1             0x1f8 0x500 0x690 0x1 0x1
+#define MX6SL_PAD_LCD_DAT4__CSI_VSYNC              0x1f8 0x500 0x678 0x2 0x2
+#define MX6SL_PAD_LCD_DAT4__WDOG2_RESET_B_DEB      0x1f8 0x500 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT4__AUD4_TXC               0x1f8 0x500 0x5f4 0x4 0x1
+#define MX6SL_PAD_LCD_DAT4__GPIO2_IO24             0x1f8 0x500 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT4__ARM_TRACE04            0x1f8 0x500 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT4__SRC_BOOT_CFG04         0x1f8 0x500 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT5__LCD_DATA05             0x1fc 0x504 0x78c 0x0 0x1
+#define MX6SL_PAD_LCD_DAT5__ECSPI1_SS2             0x1fc 0x504 0x694 0x1 0x1
+#define MX6SL_PAD_LCD_DAT5__CSI_HSYNC              0x1fc 0x504 0x670 0x2 0x2
+#define MX6SL_PAD_LCD_DAT5__EIM_CS3_B              0x1fc 0x504 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT5__AUD4_TXFS              0x1fc 0x504 0x5f8 0x4 0x1
+#define MX6SL_PAD_LCD_DAT5__GPIO2_IO25             0x1fc 0x504 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT5__ARM_TRACE05            0x1fc 0x504 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT5__SRC_BOOT_CFG05         0x1fc 0x504 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT6__LCD_DATA06             0x200 0x508 0x790 0x0 0x1
+#define MX6SL_PAD_LCD_DAT6__ECSPI1_SS3             0x200 0x508 0x698 0x1 0x1
+#define MX6SL_PAD_LCD_DAT6__CSI_PIXCLK             0x200 0x508 0x674 0x2 0x2
+#define MX6SL_PAD_LCD_DAT6__EIM_DATA00             0x200 0x508 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT6__AUD4_TXD               0x200 0x508 0x5e8 0x4 0x1
+#define MX6SL_PAD_LCD_DAT6__GPIO2_IO26             0x200 0x508 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT6__ARM_TRACE06            0x200 0x508 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT6__SRC_BOOT_CFG06         0x200 0x508 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT7__LCD_DATA07             0x204 0x50c 0x794 0x0 0x1
+#define MX6SL_PAD_LCD_DAT7__ECSPI1_RDY             0x204 0x50c 0x680 0x1 0x1
+#define MX6SL_PAD_LCD_DAT7__CSI_MCLK               0x204 0x50c 0x000 0x2 0x0
+#define MX6SL_PAD_LCD_DAT7__EIM_DATA01             0x204 0x50c 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT7__AUDIO_CLK_OUT          0x204 0x50c 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_DAT7__GPIO2_IO27             0x204 0x50c 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT7__ARM_TRACE07            0x204 0x50c 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT7__SRC_BOOT_CFG07         0x204 0x50c 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT8__LCD_DATA08             0x208 0x510 0x798 0x0 0x1
+#define MX6SL_PAD_LCD_DAT8__KEY_COL0               0x208 0x510 0x734 0x1 0x1
+#define MX6SL_PAD_LCD_DAT8__CSI_DATA09             0x208 0x510 0x654 0x2 0x1
+#define MX6SL_PAD_LCD_DAT8__EIM_DATA02             0x208 0x510 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT8__ECSPI2_SCLK            0x208 0x510 0x69c 0x4 0x2
+#define MX6SL_PAD_LCD_DAT8__GPIO2_IO28             0x208 0x510 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT8__ARM_TRACE08            0x208 0x510 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT8__SRC_BOOT_CFG08         0x208 0x510 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_DAT9__LCD_DATA09             0x20c 0x514 0x79c 0x0 0x1
+#define MX6SL_PAD_LCD_DAT9__KEY_ROW0               0x20c 0x514 0x754 0x1 0x1
+#define MX6SL_PAD_LCD_DAT9__CSI_DATA08             0x20c 0x514 0x650 0x2 0x1
+#define MX6SL_PAD_LCD_DAT9__EIM_DATA03             0x20c 0x514 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_DAT9__ECSPI2_MOSI            0x20c 0x514 0x6a4 0x4 0x2
+#define MX6SL_PAD_LCD_DAT9__GPIO2_IO29             0x20c 0x514 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_DAT9__ARM_TRACE09            0x20c 0x514 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_DAT9__SRC_BOOT_CFG09         0x20c 0x514 0x000 0x7 0x0
+#define MX6SL_PAD_LCD_ENABLE__LCD_ENABLE           0x210 0x518 0x000 0x0 0x0
+#define MX6SL_PAD_LCD_ENABLE__SD4_DATA5            0x210 0x518 0x870 0x1 0x2
+#define MX6SL_PAD_LCD_ENABLE__LCD_RD_E             0x210 0x518 0x000 0x2 0x0
+#define MX6SL_PAD_LCD_ENABLE__EIM_OE_B             0x210 0x518 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_ENABLE__UART2_RX_DATA        0x210 0x518 0x804 0x4 0x2
+#define MX6SL_PAD_LCD_ENABLE__UART2_TX_DATA        0x210 0x518 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_ENABLE__GPIO2_IO16           0x210 0x518 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_HSYNC__LCD_HSYNC             0x214 0x51c 0x774 0x0 0x0
+#define MX6SL_PAD_LCD_HSYNC__SD4_DATA6             0x214 0x51c 0x874 0x1 0x2
+#define MX6SL_PAD_LCD_HSYNC__LCD_CS                0x214 0x51c 0x000 0x2 0x0
+#define MX6SL_PAD_LCD_HSYNC__EIM_CS0_B             0x214 0x51c 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_HSYNC__UART2_TX_DATA         0x214 0x51c 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_HSYNC__UART2_RX_DATA         0x214 0x51c 0x804 0x4 0x3
+#define MX6SL_PAD_LCD_HSYNC__GPIO2_IO17            0x214 0x51c 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_HSYNC__ARM_TRACE_CLK         0x214 0x51c 0x000 0x6 0x0
+#define MX6SL_PAD_LCD_RESET__LCD_RESET             0x218 0x520 0x000 0x0 0x0
+#define MX6SL_PAD_LCD_RESET__EIM_DTACK_B           0x218 0x520 0x880 0x1 0x1
+#define MX6SL_PAD_LCD_RESET__LCD_BUSY              0x218 0x520 0x774 0x2 0x1
+#define MX6SL_PAD_LCD_RESET__EIM_WAIT_B            0x218 0x520 0x884 0x3 0x1
+#define MX6SL_PAD_LCD_RESET__UART2_CTS_B           0x218 0x520 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_RESET__UART2_RTS_B           0x218 0x520 0x800 0x4 0x2
+#define MX6SL_PAD_LCD_RESET__GPIO2_IO19            0x218 0x520 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_RESET__CCM_PMIC_READY        0x218 0x520 0x62c 0x6 0x1
+#define MX6SL_PAD_LCD_VSYNC__LCD_VSYNC             0x21c 0x524 0x000 0x0 0x0
+#define MX6SL_PAD_LCD_VSYNC__SD4_DATA7             0x21c 0x524 0x878 0x1 0x2
+#define MX6SL_PAD_LCD_VSYNC__LCD_RS                0x21c 0x524 0x000 0x2 0x0
+#define MX6SL_PAD_LCD_VSYNC__EIM_CS1_B             0x21c 0x524 0x000 0x3 0x0
+#define MX6SL_PAD_LCD_VSYNC__UART2_RTS_B           0x21c 0x524 0x800 0x4 0x3
+#define MX6SL_PAD_LCD_VSYNC__UART2_CTS_B           0x21c 0x524 0x000 0x4 0x0
+#define MX6SL_PAD_LCD_VSYNC__GPIO2_IO18            0x21c 0x524 0x000 0x5 0x0
+#define MX6SL_PAD_LCD_VSYNC__ARM_TRACE_CTL         0x21c 0x524 0x000 0x6 0x0
+#define MX6SL_PAD_PWM1__PWM1_OUT                   0x220 0x528 0x000 0x0 0x0
+#define MX6SL_PAD_PWM1__CCM_CLKO                   0x220 0x528 0x000 0x1 0x0
+#define MX6SL_PAD_PWM1__AUDIO_CLK_OUT              0x220 0x528 0x000 0x2 0x0
+#define MX6SL_PAD_PWM1__FEC_REF_OUT                0x220 0x528 0x000 0x3 0x0
+#define MX6SL_PAD_PWM1__CSI_MCLK                   0x220 0x528 0x000 0x4 0x0
+#define MX6SL_PAD_PWM1__GPIO3_IO23                 0x220 0x528 0x000 0x5 0x0
+#define MX6SL_PAD_PWM1__EPIT1_OUT                  0x220 0x528 0x000 0x6 0x0
+#define MX6SL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x224 0x52c 0x000 0x0 0x0
+#define MX6SL_PAD_REF_CLK_24M__I2C3_SCL            0x224 0x52c 0x72c 0x1 0x2
+#define MX6SL_PAD_REF_CLK_24M__PWM3_OUT            0x224 0x52c 0x000 0x2 0x0
+#define MX6SL_PAD_REF_CLK_24M__USB_OTG2_ID         0x224 0x52c 0x5e0 0x3 0x2
+#define MX6SL_PAD_REF_CLK_24M__CCM_PMIC_READY      0x224 0x52c 0x62c 0x4 0x2
+#define MX6SL_PAD_REF_CLK_24M__GPIO3_IO21          0x224 0x52c 0x000 0x5 0x0
+#define MX6SL_PAD_REF_CLK_24M__SD3_WP              0x224 0x52c 0x84c 0x6 0x3
+#define MX6SL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x228 0x530 0x000 0x0 0x0
+#define MX6SL_PAD_REF_CLK_32K__I2C3_SDA            0x228 0x530 0x730 0x1 0x2
+#define MX6SL_PAD_REF_CLK_32K__PWM4_OUT            0x228 0x530 0x000 0x2 0x0
+#define MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID         0x228 0x530 0x5dc 0x3 0x3
+#define MX6SL_PAD_REF_CLK_32K__SD1_LCTL            0x228 0x530 0x000 0x4 0x0
+#define MX6SL_PAD_REF_CLK_32K__GPIO3_IO22          0x228 0x530 0x000 0x5 0x0
+#define MX6SL_PAD_REF_CLK_32K__SD3_CD_B            0x228 0x530 0x838 0x6 0x3
+#define MX6SL_PAD_SD1_CLK__SD1_CLK                 0x22c 0x534 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_CLK__FEC_MDIO                0x22c 0x534 0x6f4 0x1 0x2
+#define MX6SL_PAD_SD1_CLK__KEY_COL0                0x22c 0x534 0x734 0x2 0x2
+#define MX6SL_PAD_SD1_CLK__EPDC_SDCE4              0x22c 0x534 0x000 0x3 0x0
+#define MX6SL_PAD_SD1_CLK__GPIO5_IO15              0x22c 0x534 0x000 0x5 0x0
+#define MX6SL_PAD_SD1_CMD__SD1_CMD                 0x230 0x538 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_CMD__FEC_TX_CLK              0x230 0x538 0x70c 0x1 0x2
+#define MX6SL_PAD_SD1_CMD__KEY_ROW0                0x230 0x538 0x754 0x2 0x2
+#define MX6SL_PAD_SD1_CMD__EPDC_SDCE5              0x230 0x538 0x000 0x3 0x0
+#define MX6SL_PAD_SD1_CMD__GPIO5_IO14              0x230 0x538 0x000 0x5 0x0
+#define MX6SL_PAD_SD1_DAT0__SD1_DATA0              0x234 0x53c 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_DAT0__FEC_RX_ER              0x234 0x53c 0x708 0x1 0x2
+#define MX6SL_PAD_SD1_DAT0__KEY_COL1               0x234 0x53c 0x738 0x2 0x2
+#define MX6SL_PAD_SD1_DAT0__EPDC_SDCE6             0x234 0x53c 0x000 0x3 0x0
+#define MX6SL_PAD_SD1_DAT0__GPIO5_IO11             0x234 0x53c 0x000 0x5 0x0
+#define MX6SL_PAD_SD1_DAT1__SD1_DATA1              0x238 0x540 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_DAT1__FEC_RX_DV              0x238 0x540 0x704 0x1 0x2
+#define MX6SL_PAD_SD1_DAT1__KEY_ROW1               0x238 0x540 0x758 0x2 0x2
+#define MX6SL_PAD_SD1_DAT1__EPDC_SDCE7             0x238 0x540 0x000 0x3 0x0
+#define MX6SL_PAD_SD1_DAT1__GPIO5_IO08             0x238 0x540 0x000 0x5 0x0
+#define MX6SL_PAD_SD1_DAT2__SD1_DATA2              0x23c 0x544 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_DAT2__FEC_RX_DATA1           0x23c 0x544 0x6fc 0x1 0x2
+#define MX6SL_PAD_SD1_DAT2__KEY_COL2               0x23c 0x544 0x73c 0x2 0x2
+#define MX6SL_PAD_SD1_DAT2__EPDC_SDCE8             0x23c 0x544 0x000 0x3 0x0
+#define MX6SL_PAD_SD1_DAT2__GPIO5_IO13             0x23c 0x544 0x000 0x5 0x0
+#define MX6SL_PAD_SD1_DAT3__SD1_DATA3              0x240 0x548 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_DAT3__FEC_TX_DATA0           0x240 0x548 0x000 0x1 0x0
+#define MX6SL_PAD_SD1_DAT3__KEY_ROW2               0x240 0x548 0x75c 0x2 0x2
+#define MX6SL_PAD_SD1_DAT3__EPDC_SDCE9             0x240 0x548 0x000 0x3 0x0
+#define MX6SL_PAD_SD1_DAT3__GPIO5_IO06             0x240 0x548 0x000 0x5 0x0
+#define MX6SL_PAD_SD1_DAT4__SD1_DATA4              0x244 0x54c 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_DAT4__FEC_MDC                0x244 0x54c 0x000 0x1 0x0
+#define MX6SL_PAD_SD1_DAT4__KEY_COL3               0x244 0x54c 0x740 0x2 0x2
+#define MX6SL_PAD_SD1_DAT4__EPDC_SDCLK_N           0x244 0x54c 0x000 0x3 0x0
+#define MX6SL_PAD_SD1_DAT4__UART4_RX_DATA          0x244 0x54c 0x814 0x4 0x4
+#define MX6SL_PAD_SD1_DAT4__UART4_TX_DATA          0x244 0x54c 0x000 0x4 0x0
+#define MX6SL_PAD_SD1_DAT4__GPIO5_IO12             0x244 0x54c 0x000 0x5 0x0
+#define MX6SL_PAD_SD1_DAT5__SD1_DATA5              0x248 0x550 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_DAT5__FEC_RX_DATA0           0x248 0x550 0x6f8 0x1 0x2
+#define MX6SL_PAD_SD1_DAT5__KEY_ROW3               0x248 0x550 0x760 0x2 0x2
+#define MX6SL_PAD_SD1_DAT5__EPDC_SDOED             0x248 0x550 0x000 0x3 0x0
+#define MX6SL_PAD_SD1_DAT5__UART4_TX_DATA          0x248 0x550 0x000 0x4 0x0
+#define MX6SL_PAD_SD1_DAT5__UART4_RX_DATA          0x248 0x550 0x814 0x4 0x5
+#define MX6SL_PAD_SD1_DAT5__GPIO5_IO09             0x248 0x550 0x000 0x5 0x0
+#define MX6SL_PAD_SD1_DAT6__SD1_DATA6              0x24c 0x554 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_DAT6__FEC_TX_EN              0x24c 0x554 0x000 0x1 0x0
+#define MX6SL_PAD_SD1_DAT6__KEY_COL4               0x24c 0x554 0x744 0x2 0x2
+#define MX6SL_PAD_SD1_DAT6__EPDC_SDOEZ             0x24c 0x554 0x000 0x3 0x0
+#define MX6SL_PAD_SD1_DAT6__UART4_RTS_B            0x24c 0x554 0x810 0x4 0x4
+#define MX6SL_PAD_SD1_DAT6__UART4_CTS_B            0x24c 0x554 0x000 0x4 0x0
+#define MX6SL_PAD_SD1_DAT6__GPIO5_IO07             0x24c 0x554 0x000 0x5 0x0
+#define MX6SL_PAD_SD1_DAT7__SD1_DATA7              0x250 0x558 0x000 0x0 0x0
+#define MX6SL_PAD_SD1_DAT7__FEC_TX_DATA1           0x250 0x558 0x000 0x1 0x0
+#define MX6SL_PAD_SD1_DAT7__KEY_ROW4               0x250 0x558 0x764 0x2 0x2
+#define MX6SL_PAD_SD1_DAT7__CCM_PMIC_READY         0x250 0x558 0x62c 0x3 0x3
+#define MX6SL_PAD_SD1_DAT7__UART4_CTS_B            0x250 0x558 0x000 0x4 0x0
+#define MX6SL_PAD_SD1_DAT7__UART4_RTS_B            0x250 0x558 0x810 0x4 0x5
+#define MX6SL_PAD_SD1_DAT7__GPIO5_IO10             0x250 0x558 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_CLK__SD2_CLK                 0x254 0x55c 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_CLK__AUD4_RXFS               0x254 0x55c 0x5f0 0x1 0x2
+#define MX6SL_PAD_SD2_CLK__ECSPI3_SCLK             0x254 0x55c 0x6b0 0x2 0x2
+#define MX6SL_PAD_SD2_CLK__CSI_DATA00              0x254 0x55c 0x630 0x3 0x2
+#define MX6SL_PAD_SD2_CLK__GPIO5_IO05              0x254 0x55c 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_CMD__SD2_CMD                 0x258 0x560 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_CMD__AUD4_RXC                0x258 0x560 0x5ec 0x1 0x2
+#define MX6SL_PAD_SD2_CMD__ECSPI3_SS0              0x258 0x560 0x6c0 0x2 0x2
+#define MX6SL_PAD_SD2_CMD__CSI_DATA01              0x258 0x560 0x634 0x3 0x2
+#define MX6SL_PAD_SD2_CMD__EPIT1_OUT               0x258 0x560 0x000 0x4 0x0
+#define MX6SL_PAD_SD2_CMD__GPIO5_IO04              0x258 0x560 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_DAT0__SD2_DATA0              0x25c 0x564 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_DAT0__AUD4_RXD               0x25c 0x564 0x5e4 0x1 0x2
+#define MX6SL_PAD_SD2_DAT0__ECSPI3_MOSI            0x25c 0x564 0x6bc 0x2 0x2
+#define MX6SL_PAD_SD2_DAT0__CSI_DATA02             0x25c 0x564 0x638 0x3 0x2
+#define MX6SL_PAD_SD2_DAT0__UART5_RTS_B            0x25c 0x564 0x818 0x4 0x4
+#define MX6SL_PAD_SD2_DAT0__UART5_CTS_B            0x25c 0x564 0x000 0x4 0x0
+#define MX6SL_PAD_SD2_DAT0__GPIO5_IO01             0x25c 0x564 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_DAT1__SD2_DATA1              0x260 0x568 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_DAT1__AUD4_TXC               0x260 0x568 0x5f4 0x1 0x2
+#define MX6SL_PAD_SD2_DAT1__ECSPI3_MISO            0x260 0x568 0x6b8 0x2 0x2
+#define MX6SL_PAD_SD2_DAT1__CSI_DATA03             0x260 0x568 0x63c 0x3 0x2
+#define MX6SL_PAD_SD2_DAT1__UART5_CTS_B            0x260 0x568 0x000 0x4 0x0
+#define MX6SL_PAD_SD2_DAT1__UART5_RTS_B            0x260 0x568 0x818 0x4 0x5
+#define MX6SL_PAD_SD2_DAT1__GPIO4_IO30             0x260 0x568 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_DAT2__SD2_DATA2              0x264 0x56c 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_DAT2__AUD4_TXFS              0x264 0x56c 0x5f8 0x1 0x2
+#define MX6SL_PAD_SD2_DAT2__FEC_COL                0x264 0x56c 0x6f0 0x2 0x1
+#define MX6SL_PAD_SD2_DAT2__CSI_DATA04             0x264 0x56c 0x640 0x3 0x2
+#define MX6SL_PAD_SD2_DAT2__UART5_RX_DATA          0x264 0x56c 0x81c 0x4 0x4
+#define MX6SL_PAD_SD2_DAT2__UART5_TX_DATA          0x264 0x56c 0x000 0x4 0x0
+#define MX6SL_PAD_SD2_DAT2__GPIO5_IO03             0x264 0x56c 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_DAT3__SD2_DATA3              0x268 0x570 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_DAT3__AUD4_TXD               0x268 0x570 0x5e8 0x1 0x2
+#define MX6SL_PAD_SD2_DAT3__FEC_RX_CLK             0x268 0x570 0x700 0x2 0x1
+#define MX6SL_PAD_SD2_DAT3__CSI_DATA05             0x268 0x570 0x644 0x3 0x2
+#define MX6SL_PAD_SD2_DAT3__UART5_TX_DATA          0x268 0x570 0x000 0x4 0x0
+#define MX6SL_PAD_SD2_DAT3__UART5_RX_DATA          0x268 0x570 0x81c 0x4 0x5
+#define MX6SL_PAD_SD2_DAT3__GPIO4_IO28             0x268 0x570 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_DAT4__SD2_DATA4              0x26c 0x574 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_DAT4__SD3_DATA4              0x26c 0x574 0x83c 0x1 0x1
+#define MX6SL_PAD_SD2_DAT4__UART2_RX_DATA          0x26c 0x574 0x804 0x2 0x4
+#define MX6SL_PAD_SD2_DAT4__UART2_TX_DATA          0x26c 0x574 0x000 0x2 0x0
+#define MX6SL_PAD_SD2_DAT4__CSI_DATA06             0x26c 0x574 0x648 0x3 0x2
+#define MX6SL_PAD_SD2_DAT4__SPDIF_OUT              0x26c 0x574 0x000 0x4 0x0
+#define MX6SL_PAD_SD2_DAT4__GPIO5_IO02             0x26c 0x574 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_DAT5__SD2_DATA5              0x270 0x578 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_DAT5__SD3_DATA5              0x270 0x578 0x840 0x1 0x1
+#define MX6SL_PAD_SD2_DAT5__UART2_TX_DATA          0x270 0x578 0x000 0x2 0x0
+#define MX6SL_PAD_SD2_DAT5__UART2_RX_DATA          0x270 0x578 0x804 0x2 0x5
+#define MX6SL_PAD_SD2_DAT5__CSI_DATA07             0x270 0x578 0x64c 0x3 0x2
+#define MX6SL_PAD_SD2_DAT5__SPDIF_IN               0x270 0x578 0x7f0 0x4 0x2
+#define MX6SL_PAD_SD2_DAT5__GPIO4_IO31             0x270 0x578 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_DAT6__SD2_DATA6              0x274 0x57c 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_DAT6__SD3_DATA6              0x274 0x57c 0x844 0x1 0x1
+#define MX6SL_PAD_SD2_DAT6__UART2_RTS_B            0x274 0x57c 0x800 0x2 0x4
+#define MX6SL_PAD_SD2_DAT6__UART2_CTS_B            0x274 0x57c 0x000 0x2 0x0
+#define MX6SL_PAD_SD2_DAT6__CSI_DATA08             0x274 0x57c 0x650 0x3 0x2
+#define MX6SL_PAD_SD2_DAT6__SD2_WP                 0x274 0x57c 0x834 0x4 0x2
+#define MX6SL_PAD_SD2_DAT6__GPIO4_IO29             0x274 0x57c 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_DAT7__SD2_DATA7              0x278 0x580 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_DAT7__SD3_DATA7              0x278 0x580 0x848 0x1 0x1
+#define MX6SL_PAD_SD2_DAT7__UART2_CTS_B            0x278 0x580 0x000 0x2 0x0
+#define MX6SL_PAD_SD2_DAT7__UART2_RTS_B            0x278 0x580 0x800 0x2 0x5
+#define MX6SL_PAD_SD2_DAT7__CSI_DATA09             0x278 0x580 0x654 0x3 0x2
+#define MX6SL_PAD_SD2_DAT7__SD2_CD_B               0x278 0x580 0x830 0x4 0x2
+#define MX6SL_PAD_SD2_DAT7__GPIO5_IO00             0x278 0x580 0x000 0x5 0x0
+#define MX6SL_PAD_SD2_RST__SD2_RESET               0x27c 0x584 0x000 0x0 0x0
+#define MX6SL_PAD_SD2_RST__FEC_REF_OUT             0x27c 0x584 0x000 0x1 0x0
+#define MX6SL_PAD_SD2_RST__WDOG2_B                 0x27c 0x584 0x000 0x2 0x0
+#define MX6SL_PAD_SD2_RST__SPDIF_OUT               0x27c 0x584 0x000 0x3 0x0
+#define MX6SL_PAD_SD2_RST__CSI_MCLK                0x27c 0x584 0x000 0x4 0x0
+#define MX6SL_PAD_SD2_RST__GPIO4_IO27              0x27c 0x584 0x000 0x5 0x0
+#define MX6SL_PAD_SD3_CLK__SD3_CLK                 0x280 0x588 0x000 0x0 0x0
+#define MX6SL_PAD_SD3_CLK__AUD5_RXFS               0x280 0x588 0x608 0x1 0x1
+#define MX6SL_PAD_SD3_CLK__KEY_COL5                0x280 0x588 0x748 0x2 0x2
+#define MX6SL_PAD_SD3_CLK__CSI_DATA10              0x280 0x588 0x658 0x3 0x2
+#define MX6SL_PAD_SD3_CLK__WDOG1_RESET_B_DEB       0x280 0x588 0x000 0x4 0x0
+#define MX6SL_PAD_SD3_CLK__GPIO5_IO18              0x280 0x588 0x000 0x5 0x0
+#define MX6SL_PAD_SD3_CLK__USB_OTG1_PWR            0x280 0x588 0x000 0x6 0x0
+#define MX6SL_PAD_SD3_CMD__SD3_CMD                 0x284 0x58c 0x000 0x0 0x0
+#define MX6SL_PAD_SD3_CMD__AUD5_RXC                0x284 0x58c 0x604 0x1 0x1
+#define MX6SL_PAD_SD3_CMD__KEY_ROW5                0x284 0x58c 0x768 0x2 0x2
+#define MX6SL_PAD_SD3_CMD__CSI_DATA11              0x284 0x58c 0x65c 0x3 0x2
+#define MX6SL_PAD_SD3_CMD__USB_OTG2_ID             0x284 0x58c 0x5e0 0x4 0x3
+#define MX6SL_PAD_SD3_CMD__GPIO5_IO21              0x284 0x58c 0x000 0x5 0x0
+#define MX6SL_PAD_SD3_CMD__USB_OTG2_PWR            0x284 0x58c 0x000 0x6 0x0
+#define MX6SL_PAD_SD3_DAT0__SD3_DATA0              0x288 0x590 0x000 0x0 0x0
+#define MX6SL_PAD_SD3_DAT0__AUD5_RXD               0x288 0x590 0x5fc 0x1 0x1
+#define MX6SL_PAD_SD3_DAT0__KEY_COL6               0x288 0x590 0x74c 0x2 0x2
+#define MX6SL_PAD_SD3_DAT0__CSI_DATA12             0x288 0x590 0x660 0x3 0x1
+#define MX6SL_PAD_SD3_DAT0__USB_OTG1_ID            0x288 0x590 0x5dc 0x4 0x4
+#define MX6SL_PAD_SD3_DAT0__GPIO5_IO19             0x288 0x590 0x000 0x5 0x0
+#define MX6SL_PAD_SD3_DAT1__SD3_DATA1              0x28c 0x594 0x000 0x0 0x0
+#define MX6SL_PAD_SD3_DAT1__AUD5_TXC               0x28c 0x594 0x60c 0x1 0x1
+#define MX6SL_PAD_SD3_DAT1__KEY_ROW6               0x28c 0x594 0x76c 0x2 0x2
+#define MX6SL_PAD_SD3_DAT1__CSI_DATA13             0x28c 0x594 0x664 0x3 0x1
+#define MX6SL_PAD_SD3_DAT1__SD1_VSELECT            0x28c 0x594 0x000 0x4 0x0
+#define MX6SL_PAD_SD3_DAT1__GPIO5_IO20             0x28c 0x594 0x000 0x5 0x0
+#define MX6SL_PAD_SD3_DAT1__JTAG_DE_B              0x28c 0x594 0x000 0x6 0x0
+#define MX6SL_PAD_SD3_DAT2__SD3_DATA2              0x290 0x598 0x000 0x0 0x0
+#define MX6SL_PAD_SD3_DAT2__AUD5_TXFS              0x290 0x598 0x610 0x1 0x1
+#define MX6SL_PAD_SD3_DAT2__KEY_COL7               0x290 0x598 0x750 0x2 0x2
+#define MX6SL_PAD_SD3_DAT2__CSI_DATA14             0x290 0x598 0x668 0x3 0x1
+#define MX6SL_PAD_SD3_DAT2__EPIT1_OUT              0x290 0x598 0x000 0x4 0x0
+#define MX6SL_PAD_SD3_DAT2__GPIO5_IO16             0x290 0x598 0x000 0x5 0x0
+#define MX6SL_PAD_SD3_DAT2__USB_OTG2_OC            0x290 0x598 0x820 0x6 0x3
+#define MX6SL_PAD_SD3_DAT3__SD3_DATA3              0x294 0x59c 0x000 0x0 0x0
+#define MX6SL_PAD_SD3_DAT3__AUD5_TXD               0x294 0x59c 0x600 0x1 0x1
+#define MX6SL_PAD_SD3_DAT3__KEY_ROW7               0x294 0x59c 0x770 0x2 0x2
+#define MX6SL_PAD_SD3_DAT3__CSI_DATA15             0x294 0x59c 0x66c 0x3 0x1
+#define MX6SL_PAD_SD3_DAT3__EPIT2_OUT              0x294 0x59c 0x000 0x4 0x0
+#define MX6SL_PAD_SD3_DAT3__GPIO5_IO17             0x294 0x59c 0x000 0x5 0x0
+#define MX6SL_PAD_SD3_DAT3__USB_OTG1_OC            0x294 0x59c 0x824 0x6 0x2
+#define MX6SL_PAD_UART1_RXD__UART1_RX_DATA         0x298 0x5a0 0x7fc 0x0 0x0
+#define MX6SL_PAD_UART1_RXD__UART1_TX_DATA         0x298 0x5a0 0x000 0x0 0x0
+#define MX6SL_PAD_UART1_RXD__PWM1_OUT              0x298 0x5a0 0x000 0x1 0x0
+#define MX6SL_PAD_UART1_RXD__UART4_RX_DATA         0x298 0x5a0 0x814 0x2 0x6
+#define MX6SL_PAD_UART1_RXD__UART4_TX_DATA         0x298 0x5a0 0x000 0x2 0x0
+#define MX6SL_PAD_UART1_RXD__FEC_COL               0x298 0x5a0 0x6f0 0x3 0x2
+#define MX6SL_PAD_UART1_RXD__UART5_RX_DATA         0x298 0x5a0 0x81c 0x4 0x6
+#define MX6SL_PAD_UART1_RXD__UART5_TX_DATA         0x298 0x5a0 0x000 0x4 0x0
+#define MX6SL_PAD_UART1_RXD__GPIO3_IO16            0x298 0x5a0 0x000 0x5 0x0
+#define MX6SL_PAD_UART1_TXD__UART1_TX_DATA         0x29c 0x5a4 0x000 0x0 0x0
+#define MX6SL_PAD_UART1_TXD__UART1_RX_DATA         0x29c 0x5a4 0x7fc 0x0 0x1
+#define MX6SL_PAD_UART1_TXD__PWM2_OUT              0x29c 0x5a4 0x000 0x1 0x0
+#define MX6SL_PAD_UART1_TXD__UART4_TX_DATA         0x29c 0x5a4 0x000 0x2 0x0
+#define MX6SL_PAD_UART1_TXD__UART4_RX_DATA         0x29c 0x5a4 0x814 0x2 0x7
+#define MX6SL_PAD_UART1_TXD__FEC_RX_CLK            0x29c 0x5a4 0x700 0x3 0x2
+#define MX6SL_PAD_UART1_TXD__UART5_TX_DATA         0x29c 0x5a4 0x000 0x4 0x0
+#define MX6SL_PAD_UART1_TXD__UART5_RX_DATA         0x29c 0x5a4 0x81c 0x4 0x7
+#define MX6SL_PAD_UART1_TXD__GPIO3_IO17            0x29c 0x5a4 0x000 0x5 0x0
+#define MX6SL_PAD_UART1_TXD__UART5_DCD_B           0x29c 0x5a4 0x000 0x7 0x0
+#define MX6SL_PAD_WDOG_B__WDOG1_B                  0x2a0 0x5a8 0x000 0x0 0x0
+#define MX6SL_PAD_WDOG_B__WDOG1_RESET_B_DEB        0x2a0 0x5a8 0x000 0x1 0x0
+#define MX6SL_PAD_WDOG_B__UART5_RI_B               0x2a0 0x5a8 0x000 0x2 0x0
+#define MX6SL_PAD_WDOG_B__GPIO3_IO18               0x2a0 0x5a8 0x000 0x5 0x0
+
+#endif /* __DTS_IMX6SL_PINFUNC_H */
diff --git a/arch/arm/boot/dts/include/dt-bindings b/arch/arm/boot/dts/include/dt-bindings
new file mode 120000
index 000000000000..08c00e4972fa
--- /dev/null
+++ b/arch/arm/boot/dts/include/dt-bindings
@@ -0,0 +1 @@
+../../../../../include/dt-bindings
\ No newline at end of file
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index 192cf76fbf93..23991e45bc55 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -49,6 +49,12 @@
                         };
                 };
 
+                thermal@10078 {
+                        compatible = "marvell,kirkwood-thermal";
+                        reg = <0x10078 0x4>;
+                        status = "okay";
+                };
+
                 i2c@11100 {
                         compatible = "marvell,mv64xxx-i2c";
                         reg = <0x11100 0x20>;
diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts
new file mode 100644
index 000000000000..5f21d4e427b0
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts
@@ -0,0 +1,89 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
+
+/ {
+        model = "LaCie CloudBox";
+        compatible = "lacie,cloudbox", "marvell,kirkwood-88f6702", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-0 = < &pmx_spi &pmx_uart0
+                                        &pmx_cloudbox_sata0 >;
+                        pinctrl-names = "default";
+
+                        pmx_cloudbox_sata0: pmx-cloudbox-sata0 {
+                                marvell,pins = "mpp15";
+                                marvell,function = "sata0";
+                        };
+                };
+
+                serial@12000 {
+                        clock-frequency = <166666667>;
+                        status = "okay";
+                };
+
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <1>;
+                };
+
+                spi@10600 {
+                        status = "okay";
+
+                        flash@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "mx25l4005a";
+                                reg = <0>;
+                                spi-max-frequency = <20000000>;
+                                mode = <0>;
+
+                                partition@0 {
+                                        reg = <0x0 0x80000>;
+                                        label = "u-boot";
+                                };
+                        };
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@1 {
+                        label = "Power push button";
+                        linux,code = <116>;
+                        gpios = <&gpio0 16 1>;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                red-fail {
+                        label = "cloudbox:red:fail";
+                        gpios = <&gpio0 14 0>;
+                };
+                blue-sata {
+                        label = "cloudbox:blue:sata";
+                        gpios = <&gpio0 15 0>;
+                };
+        };
+
+        gpio_poweroff {
+                compatible = "gpio-poweroff";
+                gpios = <&gpio0 17 0>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 9555a86297c2..44fd97dfc1f3 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -69,6 +69,10 @@
                         status = "okay";
                         nr-ports = <1>;
                 };
+
+                mvsdio@90000 {
+                        status = "okay";
+                };
         };
 
         gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
new file mode 100644
index 000000000000..1ca66ab83ad6
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -0,0 +1,180 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+/include/ "kirkwood-6282.dtsi"
+
+/ {
+        model = "NETGEAR ReadyNAS Duo v2";
+        compatible = "netgear,readynas-duo-v2", "netgear,readynas", "marvell,kirkwood-88f6282", "marvell,kirkwood";
+
+        memory { /* 256 MB */
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+
+                        pinctrl-0 = < &pmx_uart0
+                                      &pmx_button_power
+                                      &pmx_button_backup
+                                      &pmx_button_reset
+                                      &pmx_led_blue_power
+                                      &pmx_led_blue_activity
+                                      &pmx_led_blue_disk1
+                                      &pmx_led_blue_disk2
+                                      &pmx_led_blue_backup >;
+                        pinctrl-names = "default";
+
+                        pmx_button_power: pmx-button-power {
+                                marvell,pins = "mpp47";
+                                marvell,function = "gpio";
+                        };
+                        pmx_button_backup: pmx-button-backup {
+                                marvell,pins = "mpp45";
+                                marvell,function = "gpio";
+                        };
+                        pmx_button_reset: pmx-button-reset {
+                                marvell,pins = "mpp13";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_blue_power: pmx-led-blue-power {
+                                marvell,pins = "mpp31";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_blue_activity: pmx-led-blue-activity {
+                                marvell,pins = "mpp38";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_blue_disk1: pmx-led-blue-disk1 {
+                                marvell,pins = "mpp23";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_blue_disk2: pmx-led-blue-disk2 {
+                                marvell,pins = "mpp22";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_blue_backup: pmx-led-blue-backup {
+                                marvell,pins = "mpp29";
+                                marvell,function = "gpio";
+                        };
+                };
+
+                i2c@11000 {
+                        status = "okay";
+
+                        rs5c372a: rs5c372a@32 {
+                                compatible = "ricoh,rs5c372a";
+                                reg = <0x32>;
+                        };
+                };
+
+                serial@12000 {
+                        status = "okay";
+                };
+
+                nand@3000000 {
+                        status = "okay";
+
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0000000 0x180000>;
+                                read-only;
+                        };
+
+                        partition@180000 {
+                                label = "u-boot-env";
+                                reg = <0x180000 0x20000>;
+                        };
+
+                        partition@200000 {
+                                label = "uImage";
+                                reg = <0x0200000 0x600000>;
+                        };
+
+                        partition@800000 {
+                                label = "minirootfs";
+                                reg = <0x0800000 0x1000000>;
+                        };
+
+                        partition@1800000 {
+                                label = "jffs2";
+                                reg = <0x1800000 0x6800000>;
+                        };
+                };
+
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                power_led {
+                        label = "status:blue:power_led";
+                        gpios = <&gpio0 31 1>;   /* GPIO 31 Active Low */
+                        linux,default-trigger = "default-on";
+                };
+                activity_led {
+                        label = "status:blue:activity_led";
+                        gpios = <&gpio1 6 1>;    /* GPIO 38 Active Low */
+                };
+                disk1_led {
+                        label = "status:blue:disk1_led";
+                        gpios = <&gpio0 23 1>;   /* GPIO 23 Active Low */
+                };
+                disk2_led {
+                        label = "status:blue:disk2_led";
+                        gpios = <&gpio0 22 1>;   /* GPIO 22 Active Low */
+                };
+                backup_led {
+                        label = "status:blue:backup_led";
+                        gpios = <&gpio0 29 1>;   /* GPIO 29 Active Low*/
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button@1 {
+                        label = "Power Button";
+                        linux,code = <116>;     /* KEY_POWER */
+                        gpios = <&gpio1 15 1>;
+                };
+                button@2 {
+                        label = "Reset Button";
+                        linux,code = <0x198>;   /* KEY_RESTART */
+                        gpios = <&gpio0 13 1>;
+                };
+                button@3 {
+                        label = "Backup Button";
+                        linux,code = <133>;     /* KEY_COPY */
+                        gpios = <&gpio1 13 1>;
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                usb_power: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "USB 3.0 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio1 14 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts
index b79f5eb25589..adab1ab25733 100644
--- a/arch/arm/boot/dts/kirkwood-ns2mini.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts
@@ -3,6 +3,7 @@
 /include/ "kirkwood-ns2-common.dtsi"
 
 / {
+        /* This machine is embedded in the first LaCie CloudBox product. */
         model = "LaCie Network Space Mini v2";
         compatible = "lacie,netspace_mini_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood";
 
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
index 1429ac05b36d..4e8b08c628c7 100644
--- a/arch/arm/boot/dts/mmp2.dtsi
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -160,7 +160,7 @@
                         };
 
                         gpio@d4019000 {
-                                compatible = "mrvl,mmp-gpio";
+                                compatible = "marvell,mmp2-gpio";
                                 #address-cells = <1>;
                                 #size-cells = <1>;
                                 reg = <0xd4019000 0x1000>;
diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts
new file mode 100644
index 000000000000..317300875f34
--- /dev/null
+++ b/arch/arm/boot/dts/mpa1600.dts
@@ -0,0 +1,69 @@
+/*
+ * mpa1600.dts - Device Tree file for Phontech MPA 1600
+ *
+ *  Copyright (C) 2013 Joachim Eastwood <manabian@gmail.com>
+ *
+ * Licensed under GPLv2 only
+ */
+/dts-v1/;
+/include/ "at91rm9200.dtsi"
+
+/ {
+        model = "Phontech MPA 1600";
+        compatible = "phontech,mpa1600", "atmel,at91rm9200";
+
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <18432000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@fffbc000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        ssc0: ssc@fffd0000 {
+                                status = "okay";
+                        };
+
+                        ssc1: ssc@fffd4000 {
+                                status = "okay";
+                        };
+                };
+
+                usb0: ohci@00300000 {
+                        num-ports = <1>;
+                        status = "okay";
+                };
+        };
+
+        i2c@0 {
+                status = "okay";
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+
+                monitor_mute {
+                        label = "Monitor mute";
+                        gpios = <&pioC 1 1>;
+                        linux,code = <113>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
index 31f2157cd7d7..9bf49b3826ea 100644
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -16,19 +16,13 @@
         };
 
         timer@2000004 {
-                compatible = "qcom,msm-gpt", "qcom,msm-timer";
-                interrupts = <1 1 0x301>;
-                reg = <0x02000004 0x10>;
-                clock-frequency = <32768>;
-                cpu-offset = <0x40000>;
-        };
-
-        timer@2000024 {
-                compatible = "qcom,msm-dgt", "qcom,msm-timer";
-                interrupts = <1 0 0x301>;
-                reg = <0x02000024 0x10>,
-                      <0x02000034 0x4>;
-                clock-frequency = <6750000>;
+                compatible = "qcom,scss-timer", "qcom,msm-timer";
+                interrupts = <1 0 0x301>,
+                             <1 1 0x301>,
+                             <1 2 0x301>;
+                reg = <0x02000000 0x100>;
+                clock-frequency = <27000000>,
+                                  <32768>;
                 cpu-offset = <0x40000>;
         };
 
@@ -38,4 +32,10 @@
                       <0x19c00000 0x1000>;
                 interrupts = <0 195 0x0>;
         };
+
+        qcom,ssbi@500000 {
+                compatible = "qcom,ssbi";
+                reg = <0x500000 0x1000>;
+                qcom,controller-type = "pmic-arbiter";
+        };
 };
diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts
index 9e621b5ad3dd..2e4d87a125d6 100644
--- a/arch/arm/boot/dts/msm8960-cdp.dts
+++ b/arch/arm/boot/dts/msm8960-cdp.dts
@@ -15,20 +15,14 @@
                       < 0x02002000 0x1000 >;
         };
 
-        timer@200a004 {
-                compatible = "qcom,msm-gpt", "qcom,msm-timer";
-                interrupts = <1 2 0x301>;
-                reg = <0x0200a004 0x10>;
-                clock-frequency = <32768>;
-                cpu-offset = <0x80000>;
-        };
-
-        timer@200a024 {
-                compatible = "qcom,msm-dgt", "qcom,msm-timer";
-                interrupts = <1 1 0x301>;
-                reg = <0x0200a024 0x10>,
-                      <0x0200a034 0x4>;
-                clock-frequency = <6750000>;
+        timer@200a000 {
+                compatible = "qcom,kpss-timer", "qcom,msm-timer";
+                interrupts = <1 1 0x301>,
+                             <1 2 0x301>,
+                             <1 3 0x301>;
+                reg = <0x0200a000 0x100>;
+                clock-frequency = <27000000>,
+                                  <32768>;
                 cpu-offset = <0x80000>;
         };
 
@@ -38,4 +32,10 @@
                       <0x16400000 0x1000>;
                 interrupts = <0 154 0x0>;
         };
+
+        qcom,ssbi@500000 {
+                compatible = "qcom,ssbi";
+                reg = <0x500000 0x1000>;
+                qcom,controller-type = "pmic-arbiter";
+        };
 };
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index f624dc85d441..02d23f15fd86 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -38,6 +38,57 @@
                 };
         };
 
+        /* HS USB Port 2 RESET */
+        hsusb2_reset: hsusb2_reset_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb2_reset";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio5 19 0>;   /* gpio_147 */
+                startup-delay-us = <70000>;
+                enable-active-high;
+        };
+
+        /* HS USB Port 2 Power */
+        hsusb2_power: hsusb2_power_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb2_vbus";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&twl_gpio 18 0>;        /* GPIO LEDA */
+                startup-delay-us = <70000>;
+        };
+
+        /* HS USB Host PHY on PORT 2 */
+        hsusb2_phy: hsusb2_phy {
+                compatible = "usb-nop-xceiv";
+                reset-supply = <&hsusb2_reset>;
+                vcc-supply = <&hsusb2_power>;
+        };
+};
+
+&omap3_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &hsusbb2_pins
+        >;
+
+        hsusbb2_pins: pinmux_hsusbb2_pins {
+                pinctrl-single,pins = <
+                        0x5c0 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */
+                        0x5c2 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
+                        0x5c4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
+                        0x5c6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
+                        0x5c8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
+                        0x5cA 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
+                        0x1a4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
+                        0x1a6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
+                        0x1a8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
+                        0x1aa 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
+                        0x1ac 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
+                        0x1ae 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
+                >;
+        };
 };
 
 &i2c1 {
@@ -65,3 +116,23 @@
 &mmc3 {
         status = "disabled";
 };
+
+&usbhshost {
+        port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+        phys = <0 &hsusb2_phy>;
+};
+
+&twl_gpio {
+        ti,use-leds;
+        /* pullups: BIT(1) */
+        ti,pullups = <0x000002>;
+        /*
+         * pulldowns:
+         * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
+         * BIT(15), BIT(16), BIT(17)
+         */
+        ti,pulldowns = <0x03a1c4>;
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 1acc26148ffc..a14f74bbce7c 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -397,5 +397,36 @@
                         ti,timer-alwon;
                         ti,timer-secure;
                 };
+
+                usbhstll: usbhstll@48062000 {
+                        compatible = "ti,usbhs-tll";
+                        reg = <0x48062000 0x1000>;
+                        interrupts = <78>;
+                        ti,hwmods = "usb_tll_hs";
+                };
+
+                usbhshost: usbhshost@48064000 {
+                        compatible = "ti,usbhs-host";
+                        reg = <0x48064000 0x400>;
+                        ti,hwmods = "usb_host_hs";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        usbhsohci: ohci@48064400 {
+                                compatible = "ti,ohci-omap3", "usb-ohci";
+                                reg = <0x48064400 0x400>;
+                                interrupt-parent = <&intc>;
+                                interrupts = <76>;
+                        };
+
+                        usbhsehci: ehci@48064800 {
+                                compatible = "ti,ehci-omap", "usb-ehci";
+                                reg = <0x48064800 0x400>;
+                                interrupt-parent = <&intc>;
+                                interrupts = <77>;
+                        };
+                };
+
         };
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 739bb79e410e..b7db1a2b6ca7 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -529,5 +529,35 @@
                         ti,hwmods = "timer11";
                         ti,timer-pwm;
                 };
+
+                usbhstll: usbhstll@4a062000 {
+                        compatible = "ti,usbhs-tll";
+                        reg = <0x4a062000 0x1000>;
+                        interrupts = <0 78 0x4>;
+                        ti,hwmods = "usb_tll_hs";
+                };
+
+                usbhshost: usbhshost@4a064000 {
+                        compatible = "ti,usbhs-host";
+                        reg = <0x4a064000 0x800>;
+                        ti,hwmods = "usb_host_hs";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        usbhsohci: ohci@4a064800 {
+                                compatible = "ti,ohci-omap3", "usb-ohci";
+                                reg = <0x4a064800 0x400>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <0 76 0x4>;
+                        };
+
+                        usbhsehci: ehci@4a064c00 {
+                                compatible = "ti,ehci-omap", "usb-ehci";
+                                reg = <0x4a064c00 0x400>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <0 77 0x4>;
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index f7bec3b1ba32..892c64e3f1e1 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -74,6 +74,20 @@
                         status = "okay";
                 };
 
+                ehci@50000 {
+                        compatible = "marvell,orion-ehci";
+                        reg = <0x50000 0x1000>;
+                        interrupts = <17>;
+                        status = "disabled";
+                };
+
+                ehci@a0000 {
+                        compatible = "marvell,orion-ehci";
+                        reg = <0xa0000 0x1000>;
+                        interrupts = <12>;
+                        status = "disabled";
+                };
+
                 sata@80000 {
                         compatible = "marvell,orion-sata";
                         reg = <0x80000 0x5000>;
@@ -91,6 +105,25 @@
                         status = "disabled";
                 };
 
+                xor@60900 {
+                        compatible = "marvell,orion-xor";
+                        reg = <0x60900 0x100
+                               0x60b00 0x100>;
+                        status = "okay";
+
+                        xor00 {
+                              interrupts = <30>;
+                              dmacap,memcpy;
+                              dmacap,xor;
+                        };
+                        xor01 {
+                              interrupts = <31>;
+                              dmacap,memcpy;
+                              dmacap,xor;
+                              dmacap,memset;
+                        };
+                };
+
                 crypto@90000 {
                         compatible = "marvell,orion-crypto";
                         reg = <0x90000 0x10000>,
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
index 31a718696080..975dad21ac38 100644
--- a/arch/arm/boot/dts/pxa168.dtsi
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -77,7 +77,7 @@
                         };
 
                         gpio@d4019000 {
-                                compatible = "mrvl,mmp-gpio";
+                                compatible = "marvell,mmp-gpio";
                                 #address-cells = <1>;
                                 #size-cells = <1>;
                                 reg = <0xd4019000 0x1000>;
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
index 825aaca33034..0247c622f580 100644
--- a/arch/arm/boot/dts/pxa910.dtsi
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -89,7 +89,7 @@
                         };
 
                         gpio@d4019000 {
-                                compatible = "mrvl,mmp-gpio";
+                                compatible = "marvell,mmp-gpio";
                                 #address-cells = <1>;
                                 #size-cells = <1>;
                                 reg = <0xd4019000 0x1000>;
diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
new file mode 100644
index 000000000000..72be4c87cfb5
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
@@ -0,0 +1,47 @@
+/*
+ * Reference Device Tree Source for the Marzen board
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Simon Horman
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "r8a7779.dtsi"
+
+/ {
+        model = "marzen";
+        compatible = "renesas,marzen-reference", "renesas,r8a7779";
+
+        chosen {
+                bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x60000000 0x40000000>;
+        };
+
+        fixedregulator3v3: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        lan0@18000000 {
+                compatible = "smsc,lan9220", "smsc,lan9115";
+                reg = <0x18000000 0x100>;
+                phy-mode = "mii";
+                interrupt-parent = <&gic>;
+                interrupts = <0 28 0x4>;
+                reg-io-width = <4>;
+                vddvario-supply = <&fixedregulator3v3>;
+                vdd33a-supply = <&fixedregulator3v3>;
+        };
+};
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
new file mode 100644
index 000000000000..fe5c6f213271
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -0,0 +1,98 @@
+/*
+ * Device Tree Source for Renesas r8a7779
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Simon Horman
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "renesas,r8a7779";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                };
+                cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <2>;
+                };
+                cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <3>;
+                };
+        };
+
+        gic: interrupt-controller@f0001000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0xf0001000 0x1000>,
+                      <0xf0000100 0x100>;
+        };
+
+        i2c0: i2c@0xffc70000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xffc70000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 79 0x4>;
+        };
+
+        i2c1: i2c@0xffc71000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xffc71000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 82 0x4>;
+        };
+
+        i2c2: i2c@0xffc72000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xffc72000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 80 0x4>;
+        };
+
+        i2c3: i2c@0xffc73000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xffc73000 0x1000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 81 0x4>;
+        };
+
+        thermal@ffc48000 {
+                compatible = "renesas,rcar-thermal";
+                reg = <0xffc48000 0x38>;
+        };
+
+        sata: sata@fc600000 {
+                compatible = "renesas,rcar-sata";
+                reg = <0xfc600000 0x2000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 100 0x4>;
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
new file mode 100644
index 000000000000..39b0458d365a
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -0,0 +1,1031 @@
+/*
+ * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
+ *                applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        model = "Atmel SAMA5D3 family SoC";
+        compatible = "atmel,sama5d3", "atmel,sama5";
+        interrupt-parent = <&aic>;
+
+        aliases {
+                serial0 = &dbgu;
+                serial1 = &usart0;
+                serial2 = &usart1;
+                serial3 = &usart2;
+                serial4 = &usart3;
+                gpio0 = &pioA;
+                gpio1 = &pioB;
+                gpio2 = &pioC;
+                gpio3 = &pioD;
+                gpio4 = &pioE;
+                tcb0 = &tcb0;
+                tcb1 = &tcb1;
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                i2c2 = &i2c2;
+                ssc0 = &ssc0;
+                ssc1 = &ssc1;
+        };
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a5";
+                };
+        };
+
+        memory {
+                reg = <0x20000000 0x8000000>;
+        };
+
+        ahb {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                apb {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        mmc0: mmc@f0000000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xf0000000 0x600>;
+                                interrupts = <21 4 0>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
+                                status = "disabled";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        spi0: spi@f0004000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91sam9x5-spi";
+                                reg = <0xf0004000 0x100>;
+                                interrupts = <24 4 3>;
+                                cs-gpios = <&pioD 13 0
+                                            &pioD 14 0 /* conflicts with SCK0 and CANRX0 */
+                                            &pioD 15 0 /* conflicts with CTS0 and CANTX0 */
+                                            &pioD 16 0 /* conflicts with RTS0 and PWMFI3 */
+                                           >;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi0>;
+                                status = "disabled";
+                        };
+
+                        ssc0: ssc@f0008000 {
+                                compatible = "atmel,at91sam9g45-ssc";
+                                reg = <0xf0008000 0x4000>;
+                                interrupts = <38 4 4>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+                                status = "disabled";
+                        };
+
+                        can0: can@f000c000 {
+                                compatible = "atmel,at91sam9x5-can";
+                                reg = <0xf000c000 0x300>;
+                                interrupts = <40 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_can0_rx_tx>;
+                                status = "disabled";
+                        };
+
+                        tcb0: timer@f0010000 {
+                                compatible = "atmel,at91sam9x5-tcb";
+                                reg = <0xf0010000 0x100>;
+                                interrupts = <26 4 0>;
+                        };
+
+                        i2c0: i2c@f0014000 {
+                                compatible = "atmel,at91sam9x5-i2c";
+                                reg = <0xf0014000 0x4000>;
+                                interrupts = <18 4 6>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+
+                        i2c1: i2c@f0018000 {
+                                compatible = "atmel,at91sam9x5-i2c";
+                                reg = <0xf0018000 0x4000>;
+                                interrupts = <19 4 6>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c1>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+
+                        usart0: serial@f001c000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf001c000 0x100>;
+                                interrupts = <12 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart0>;
+                                status = "disabled";
+                        };
+
+                        usart1: serial@f0020000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf0020000 0x100>;
+                                interrupts = <13 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart1>;
+                                status = "disabled";
+                        };
+
+                        macb0: ethernet@f0028000 {
+                                compatible = "cnds,pc302-gem", "cdns,gem";
+                                reg = <0xf0028000 0x100>;
+                                interrupts = <34 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
+                                status = "disabled";
+                        };
+
+                        isi: isi@f0034000 {
+                                compatible = "atmel,at91sam9g45-isi";
+                                reg = <0xf0034000 0x4000>;
+                                interrupts = <37 4 5>;
+                                status = "disabled";
+                        };
+
+                        mmc1: mmc@f8000000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xf8000000 0x600>;
+                                interrupts = <22 4 0>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
+                                status = "disabled";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        mmc2: mmc@f8004000 {
+                                compatible = "atmel,hsmci";
+                                reg = <0xf8004000 0x600>;
+                                interrupts = <23 4 0>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
+                                status = "disabled";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        spi1: spi@f8008000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91sam9x5-spi";
+                                reg = <0xf8008000 0x100>;
+                                interrupts = <25 4 3>;
+                                cs-gpios = <&pioC 25 0
+                                            &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */
+                                            &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */
+                                            &pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */
+                                           >;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi1>;
+                                status = "disabled";
+                        };
+
+                        ssc1: ssc@f800c000 {
+                                compatible = "atmel,at91sam9g45-ssc";
+                                reg = <0xf800c000 0x4000>;
+                                interrupts = <39 4 4>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+                                status = "disabled";
+                        };
+
+                        can1: can@f8010000 {
+                                compatible = "atmel,at91sam9x5-can";
+                                reg = <0xf8010000 0x300>;
+                                interrupts = <41 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_can1_rx_tx>;
+                        };
+
+                        tcb1: timer@f8014000 {
+                                compatible = "atmel,at91sam9x5-tcb";
+                                reg = <0xf8014000 0x100>;
+                                interrupts = <27 4 0>;
+                        };
+
+                        adc0: adc@f8018000 {
+                                compatible = "atmel,at91sam9260-adc";
+                                reg = <0xf8018000 0x100>;
+                                interrupts = <29 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <
+                                        &pinctrl_adc0_adtrg
+                                        &pinctrl_adc0_ad0
+                                        &pinctrl_adc0_ad1
+                                        &pinctrl_adc0_ad2
+                                        &pinctrl_adc0_ad3
+                                        &pinctrl_adc0_ad4
+                                        &pinctrl_adc0_ad5
+                                        &pinctrl_adc0_ad6
+                                        &pinctrl_adc0_ad7
+                                        &pinctrl_adc0_ad8
+                                        &pinctrl_adc0_ad9
+                                        &pinctrl_adc0_ad10
+                                        &pinctrl_adc0_ad11
+                                        >;
+                                atmel,adc-channel-base = <0x50>;
+                                atmel,adc-channels-used = <0xfff>;
+                                atmel,adc-drdy-mask = <0x1000000>;
+                                atmel,adc-num-channels = <12>;
+                                atmel,adc-startup-time = <40>;
+                                atmel,adc-status-register = <0x30>;
+                                atmel,adc-trigger-register = <0xc0>;
+                                atmel,adc-use-external;
+                                atmel,adc-vref = <3000>;
+                                atmel,adc-res = <10 12>;
+                                atmel,adc-res-names = "lowres", "highres";
+                                status = "disabled";
+
+                                trigger@0 {
+                                        trigger-name = "external-rising";
+                                        trigger-value = <0x1>;
+                                        trigger-external;
+                                };
+                                trigger@1 {
+                                        trigger-name = "external-falling";
+                                        trigger-value = <0x2>;
+                                        trigger-external;
+                                };
+                                trigger@2 {
+                                        trigger-name = "external-any";
+                                        trigger-value = <0x3>;
+                                        trigger-external;
+                                };
+                                trigger@3 {
+                                        trigger-name = "continuous";
+                                        trigger-value = <0x6>;
+                                };
+                        };
+
+                        tsadcc: tsadcc@f8018000 {
+                                compatible = "atmel,at91sam9x5-tsadcc";
+                                reg = <0xf8018000 0x4000>;
+                                interrupts = <29 4 5>;
+                                atmel,tsadcc_clock = <300000>;
+                                atmel,filtering_average = <0x03>;
+                                atmel,pendet_debounce = <0x08>;
+                                atmel,pendet_sensitivity = <0x02>;
+                                atmel,ts_sample_hold_time = <0x0a>;
+                                status = "disabled";
+                        };
+
+                        i2c2: i2c@f801c000 {
+                                compatible = "atmel,at91sam9x5-i2c";
+                                reg = <0xf801c000 0x4000>;
+                                interrupts = <20 4 6>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+
+                        usart2: serial@f8020000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8020000 0x100>;
+                                interrupts = <14 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart2>;
+                                status = "disabled";
+                        };
+
+                        usart3: serial@f8024000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8024000 0x100>;
+                                interrupts = <15 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart3>;
+                                status = "disabled";
+                        };
+
+                        macb1: ethernet@f802c000 {
+                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                                reg = <0xf802c000 0x100>;
+                                interrupts = <35 4 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_macb1_rmii>;
+                                status = "disabled";
+                        };
+
+                        sha@f8034000 {
+                                compatible = "atmel,sam9g46-sha";
+                                reg = <0xf8034000 0x100>;
+                                interrupts = <42 4 0>;
+                        };
+
+                        aes@f8038000 {
+                                compatible = "atmel,sam9g46-aes";
+                                reg = <0xf8038000 0x100>;
+                                interrupts = <43 4 0>;
+                        };
+
+                        tdes@f803c000 {
+                                compatible = "atmel,sam9g46-tdes";
+                                reg = <0xf803c000 0x100>;
+                                interrupts = <44 4 0>;
+                        };
+
+                        dma0: dma-controller@ffffe600 {
+                                compatible = "atmel,at91sam9g45-dma";
+                                reg = <0xffffe600 0x200>;
+                                interrupts = <30 4 0>;
+                                #dma-cells = <1>;
+                        };
+
+                        dma1: dma-controller@ffffe800 {
+                                compatible = "atmel,at91sam9g45-dma";
+                                reg = <0xffffe800 0x200>;
+                                interrupts = <31 4 0>;
+                                #dma-cells = <1>;
+                        };
+
+                        ramc0: ramc@ffffea00 {
+                                compatible = "atmel,at91sam9g45-ddramc";
+                                reg = <0xffffea00 0x200>;
+                        };
+
+                        dbgu: serial@ffffee00 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xffffee00 0x200>;
+                                interrupts = <2 4 7>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_dbgu>;
+                                status = "disabled";
+                        };
+
+                        aic: interrupt-controller@fffff000 {
+                                #interrupt-cells = <3>;
+                                compatible = "atmel,sama5d3-aic";
+                                interrupt-controller;
+                                reg = <0xfffff000 0x200>;
+                                atmel,external-irqs = <47>;
+                        };
+
+                        pinctrl@fffff200 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
+                                ranges = <0xfffff200 0xfffff200 0xa00>;
+                                atmel,mux-mask = <
+                                        /*   A          B          C  */
+                                        0xffffffff 0xc0fc0000 0xc0ff0000        /* pioA */
+                                        0xffffffff 0x0ff8ffff 0x00000000        /* pioB */
+                                        0xffffffff 0xbc00f1ff 0x7c00fc00        /* pioC */
+                                        0xffffffff 0xc001c0e0 0x0001c1e0        /* pioD */
+                                        0xffffffff 0xbf9f8000 0x18000000        /* pioE */
+                                        >;
+
+                                /* shared pinctrl settings */
+                                adc0 {
+                                        pinctrl_adc0_adtrg: adc0_adtrg {
+                                                atmel,pins =
+                                                        <3 19 0x1 0x0>; /* PD19 periph A ADTRG */
+                                        };
+                                        pinctrl_adc0_ad0: adc0_ad0 {
+                                                atmel,pins =
+                                                        <3 20 0x1 0x0>; /* PD20 periph A AD0 */
+                                        };
+                                        pinctrl_adc0_ad1: adc0_ad1 {
+                                                atmel,pins =
+                                                        <3 21 0x1 0x0>; /* PD21 periph A AD1 */
+                                        };
+                                        pinctrl_adc0_ad2: adc0_ad2 {
+                                                atmel,pins =
+                                                        <3 22 0x1 0x0>; /* PD22 periph A AD2 */
+                                        };
+                                        pinctrl_adc0_ad3: adc0_ad3 {
+                                                atmel,pins =
+                                                        <3 23 0x1 0x0>; /* PD23 periph A AD3 */
+                                        };
+                                        pinctrl_adc0_ad4: adc0_ad4 {
+                                                atmel,pins =
+                                                        <3 24 0x1 0x0>; /* PD24 periph A AD4 */
+                                        };
+                                        pinctrl_adc0_ad5: adc0_ad5 {
+                                                atmel,pins =
+                                                        <3 25 0x1 0x0>; /* PD25 periph A AD5 */
+                                        };
+                                        pinctrl_adc0_ad6: adc0_ad6 {
+                                                atmel,pins =
+                                                        <3 26 0x1 0x0>; /* PD26 periph A AD6 */
+                                        };
+                                        pinctrl_adc0_ad7: adc0_ad7 {
+                                                atmel,pins =
+                                                        <3 27 0x1 0x0>; /* PD27 periph A AD7 */
+                                        };
+                                        pinctrl_adc0_ad8: adc0_ad8 {
+                                                atmel,pins =
+                                                        <3 28 0x1 0x0>; /* PD28 periph A AD8 */
+                                        };
+                                        pinctrl_adc0_ad9: adc0_ad9 {
+                                                atmel,pins =
+                                                        <3 29 0x1 0x0>; /* PD29 periph A AD9 */
+                                        };
+                                        pinctrl_adc0_ad10: adc0_ad10 {
+                                                atmel,pins =
+                                                        <3 30 0x1 0x0>; /* PD30 periph A AD10, conflicts with PCK0 */
+                                        };
+                                        pinctrl_adc0_ad11: adc0_ad11 {
+                                                atmel,pins =
+                                                        <3 31 0x1 0x0>; /* PD31 periph A AD11, conflicts with PCK1 */
+                                        };
+                                };
+
+                                can0 {
+                                        pinctrl_can0_rx_tx: can0_rx_tx {
+                                                atmel,pins =
+                                                        <3 14 0x3 0x0   /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
+                                                         3 15 0x3 0x0>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
+                                        };
+                                };
+
+                                can1 {
+                                        pinctrl_can1_rx_tx: can1_rx_tx {
+                                                atmel,pins =
+                                                        <1 14 0x2 0x0   /* PB14 periph B RX, conflicts with GCRS */
+                                                         1 15 0x2 0x0>; /* PB15 periph B TX, conflicts with GCOL */
+                                        };
+                                };
+
+                                dbgu {
+                                        pinctrl_dbgu: dbgu-0 {
+                                                atmel,pins =
+                                                        <1 30 0x1 0x0   /* PB30 periph A */
+                                                         1 31 0x1 0x1>; /* PB31 periph A with pullup */
+                                        };
+                                };
+
+                                i2c0 {
+                                        pinctrl_i2c0: i2c0-0 {
+                                                atmel,pins =
+                                                        <0 30 0x1 0x0   /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
+                                                         0 31 0x1 0x0>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
+                                        };
+                                };
+
+                                i2c1 {
+                                        pinctrl_i2c1: i2c1-0 {
+                                                atmel,pins =
+                                                        <2 26 0x2 0x0   /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
+                                                         2 27 0x2 0x0>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
+                                        };
+                                };
+
+                                isi {
+                                        pinctrl_isi: isi-0 {
+                                                atmel,pins =
+                                                        <0 16 0x3 0x0   /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
+                                                         0 17 0x3 0x0   /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
+                                                         0 18 0x3 0x0   /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
+                                                         0 19 0x3 0x0   /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
+                                                         0 20 0x3 0x0   /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
+                                                         0 21 0x3 0x0   /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
+                                                         0 22 0x3 0x0   /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
+                                                         0 23 0x3 0x0   /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
+                                                         2 30 0x3 0x0   /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
+                                                         0 31 0x3 0x0   /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
+                                                         0 30 0x3 0x0   /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
+                                                         2 29 0x3 0x0   /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
+                                                         2 28 0x3 0x0>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
+                                        };
+                                        pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
+                                                atmel,pins =
+                                                        <3 31 0x2 0x0>; /* PD31 periph B ISI_MCK */
+                                        };
+                                };
+
+                                lcd {
+                                        pinctrl_lcd: lcd-0 {
+                                                atmel,pins =
+                                                        <0 24 0x1 0x0   /* PA24 periph A LCDPWM */
+                                                         0 26 0x1 0x0   /* PA26 periph A LCDVSYNC */
+                                                         0 27 0x1 0x0   /* PA27 periph A LCDHSYNC */
+                                                         0 25 0x1 0x0   /* PA25 periph A LCDDISP */
+                                                         0 29 0x1 0x0   /* PA29 periph A LCDDEN */
+                                                         0 28 0x1 0x0   /* PA28 periph A LCDPCK */
+                                                         0 0 0x1 0x0    /* PA0 periph A LCDD0 pin */
+                                                         0 1 0x1 0x0    /* PA1 periph A LCDD1 pin */
+                                                         0 2 0x1 0x0    /* PA2 periph A LCDD2 pin */
+                                                         0 3 0x1 0x0    /* PA3 periph A LCDD3 pin */
+                                                         0 4 0x1 0x0    /* PA4 periph A LCDD4 pin */
+                                                         0 5 0x1 0x0    /* PA5 periph A LCDD5 pin */
+                                                         0 6 0x1 0x0    /* PA6 periph A LCDD6 pin */
+                                                         0 7 0x1 0x0    /* PA7 periph A LCDD7 pin */
+                                                         0 8 0x1 0x0    /* PA8 periph A LCDD8 pin */
+                                                         0 9 0x1 0x0    /* PA9 periph A LCDD9 pin */
+                                                         0 10 0x1 0x0   /* PA10 periph A LCDD10 pin */
+                                                         0 11 0x1 0x0   /* PA11 periph A LCDD11 pin */
+                                                         0 12 0x1 0x0   /* PA12 periph A LCDD12 pin */
+                                                         0 13 0x1 0x0   /* PA13 periph A LCDD13 pin */
+                                                         0 14 0x1 0x0   /* PA14 periph A LCDD14 pin */
+                                                         0 15 0x1 0x0   /* PA15 periph A LCDD15 pin */
+                                                         2 14 0x3 0x0   /* PC14 periph C LCDD16 pin */
+                                                         2 13 0x3 0x0   /* PC13 periph C LCDD17 pin */
+                                                         2 12 0x3 0x0   /* PC12 periph C LCDD18 pin */
+                                                         2 11 0x3 0x0   /* PC11 periph C LCDD19 pin */
+                                                         2 10 0x3 0x0   /* PC10 periph C LCDD20 pin */
+                                                         2 15 0x3 0x0   /* PC15 periph C LCDD21 pin */
+                                                         4 27 0x3 0x0   /* PE27 periph C LCDD22 pin */
+                                                         4 28 0x3 0x0>; /* PE28 periph C LCDD23 pin */
+                                        };
+                                };
+
+                                macb0 {
+                                        pinctrl_macb0_data_rgmii: macb0_data_rgmii {
+                                                atmel,pins =
+                                                        <1 0 0x1 0x0    /* PB0 periph A GTX0, conflicts with PWMH0 */
+                                                         1 1 0x1 0x0    /* PB1 periph A GTX1, conflicts with PWML0 */
+                                                         1 2 0x1 0x0    /* PB2 periph A GTX2, conflicts with TK1 */
+                                                         1 3 0x1 0x0    /* PB3 periph A GTX3, conflicts with TF1 */
+                                                         1 4 0x1 0x0    /* PB4 periph A GRX0, conflicts with PWMH1 */
+                                                         1 5 0x1 0x0    /* PB5 periph A GRX1, conflicts with PWML1 */
+                                                         1 6 0x1 0x0    /* PB6 periph A GRX2, conflicts with TD1 */
+                                                         1 7 0x1 0x0>;  /* PB7 periph A GRX3, conflicts with RK1 */
+                                        };
+                                        pinctrl_macb0_data_gmii: macb0_data_gmii {
+                                                atmel,pins =
+                                                        <1 19 0x2 0x0   /* PB19 periph B GTX4, conflicts with MCI1_CDA */
+                                                         1 20 0x2 0x0   /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
+                                                         1 21 0x2 0x0   /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
+                                                         1 22 0x2 0x0   /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
+                                                         1 23 0x2 0x0   /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
+                                                         1 24 0x2 0x0   /* PB24 periph B GRX5, conflicts with MCI1_CK */
+                                                         1 25 0x2 0x0   /* PB25 periph B GRX6, conflicts with SCK1 */
+                                                         1 26 0x2 0x0>; /* PB26 periph B GRX7, conflicts with CTS1 */
+                                        };
+                                        pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
+                                                atmel,pins =
+                                                        <1 8 0x1 0x0    /* PB8 periph A GTXCK, conflicts with PWMH2 */
+                                                         1 9 0x1 0x0    /* PB9 periph A GTXEN, conflicts with PWML2 */
+                                                         1 11 0x1 0x0   /* PB11 periph A GRXCK, conflicts with RD1 */
+                                                         1 13 0x1 0x0   /* PB13 periph A GRXER, conflicts with PWML3 */
+                                                         1 16 0x1 0x0   /* PB16 periph A GMDC */
+                                                         1 17 0x1 0x0   /* PB17 periph A GMDIO */
+                                                         1 18 0x1 0x0>; /* PB18 periph A G125CK */
+                                        };
+                                        pinctrl_macb0_signal_gmii: macb0_signal_gmii {
+                                                atmel,pins =
+                                                        <1 9 0x1 0x0    /* PB9 periph A GTXEN, conflicts with PWML2 */
+                                                         1 10 0x1 0x0   /* PB10 periph A GTXER, conflicts with RF1 */
+                                                         1 11 0x1 0x0   /* PB11 periph A GRXCK, conflicts with RD1 */
+                                                         1 12 0x1 0x0   /* PB12 periph A GRXDV, conflicts with PWMH3 */
+                                                         1 13 0x1 0x0   /* PB13 periph A GRXER, conflicts with PWML3 */
+                                                         1 14 0x1 0x0   /* PB14 periph A GCRS, conflicts with CANRX1 */
+                                                         1 15 0x1 0x0   /* PB15 periph A GCOL, conflicts with CANTX1 */
+                                                         1 16 0x1 0x0   /* PB16 periph A GMDC */
+                                                         1 17 0x1 0x0   /* PB17 periph A GMDIO */
+                                                         1 27 0x2 0x0>; /* PB27 periph B G125CKO */
+                                        };
+
+                                };
+
+                                macb1 {
+                                        pinctrl_macb1_rmii: macb1_rmii-0 {
+                                                atmel,pins =
+                                                        <2 0 0x1 0x0    /* PC0 periph A ETX0, conflicts with TIOA3 */
+                                                         2 1 0x1 0x0    /* PC1 periph A ETX1, conflicts with TIOB3 */
+                                                         2 2 0x1 0x0    /* PC2 periph A ERX0, conflicts with TCLK3 */
+                                                         2 3 0x1 0x0    /* PC3 periph A ERX1, conflicts with TIOA4 */
+                                                         2 4 0x1 0x0    /* PC4 periph A ETXEN, conflicts with TIOB4 */
+                                                         2 5 0x1 0x0    /* PC5 periph A ECRSDV,conflicts with TCLK4 */
+                                                         2 6 0x1 0x0    /* PC6 periph A ERXER, conflicts with TIOA5 */
+                                                         2 7 0x1 0x0    /* PC7 periph A EREFCK, conflicts with TIOB5 */
+                                                         2 8 0x1 0x0    /* PC8 periph A EMDC, conflicts with TCLK5 */
+                                                         2 9 0x1 0x0>;  /* PC9 periph A EMDIO  */
+                                        };
+                                };
+
+                                mmc0 {
+                                        pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
+                                                atmel,pins =
+                                                        <3 9 0x1 0x0    /* PD9 periph A MCI0_CK */
+                                                         3 0 0x1 0x1    /* PD0 periph A MCI0_CDA with pullup */
+                                                         3 1 0x1 0x1>;  /* PD1 periph A MCI0_DA0 with pullup */
+                                        };
+                                        pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
+                                                atmel,pins =
+                                                        <3 2 0x1 0x1    /* PD2 periph A MCI0_DA1 with pullup */
+                                                         3 3 0x1 0x1    /* PD3 periph A MCI0_DA2 with pullup */
+                                                         3 4 0x1 0x1>;  /* PD4 periph A MCI0_DA3 with pullup */
+                                        };
+                                        pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
+                                                atmel,pins =
+                                                        <3 5 0x1 0x1    /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
+                                                         3 6 0x1 0x1    /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
+                                                         3 7 0x1 0x1    /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
+                                                         3 8 0x1 0x1>;  /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
+                                        };
+                                };
+
+                                mmc1 {
+                                        pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
+                                                atmel,pins =
+                                                        <1 24 0x1 0x0   /* PB24 periph A MCI1_CK, conflicts with GRX5 */
+                                                         1 19 0x1 0x1   /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
+                                                         1 20 0x1 0x1>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
+                                        };
+                                        pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
+                                                atmel,pins =
+                                                        <1 21 0x1 0x1   /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
+                                                         1 22 0x1 0x1   /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
+                                                         1 23 0x1 0x1>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
+                                        };
+                                };
+
+                                mmc2 {
+                                        pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
+                                                atmel,pins =
+                                                        <2 15 0x1 0x0   /* PC15 periph A MCI2_CK, conflicts with PCK2 */
+                                                         2 10 0x1 0x1   /* PC10 periph A MCI2_CDA with pullup */
+                                                         2 11 0x1 0x1>; /* PC11 periph A MCI2_DA0 with pullup */
+                                        };
+                                        pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
+                                                atmel,pins =
+                                                        <2 12 0x1 0x0   /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
+                                                         2 13 0x1 0x0   /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
+                                                         2 14 0x1 0x0>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
+                                        };
+                                };
+
+                                nand0 {
+                                        pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
+                                                atmel,pins =
+                                                        <4 21 0x1 0x1   /* PE21 periph A with pullup */
+                                                         4 22 0x1 0x1>; /* PE22 periph A with pullup */
+                                        };
+                                };
+
+                                pioA: gpio@fffff200 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff200 0x100>;
+                                        interrupts = <6 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                pioB: gpio@fffff400 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff400 0x100>;
+                                        interrupts = <7 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                pioC: gpio@fffff600 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff600 0x100>;
+                                        interrupts = <8 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                pioD: gpio@fffff800 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff800 0x100>;
+                                        interrupts = <9 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                pioE: gpio@fffffa00 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffffa00 0x100>;
+                                        interrupts = <10 4 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                spi0 {
+                                        pinctrl_spi0: spi0-0 {
+                                                atmel,pins =
+                                                        <3 10 0x1 0x0   /* PD10 periph A SPI0_MISO pin */
+                                                         3 11 0x1 0x0   /* PD11 periph A SPI0_MOSI pin */
+                                                         3 12 0x1 0x0   /* PD12 periph A SPI0_SPCK pin */
+                                                         3 13 0x0 0x0>; /* PD13 GPIO SPI0_NPCS0 pin */
+                                        };
+                                };
+
+                                spi1 {
+                                        pinctrl_spi1: spi1-0 {
+                                                atmel,pins =
+                                                        <2 22 0x1 0x0   /* PC22 periph A SPI1_MISO pin */
+                                                         2 23 0x1 0x0   /* PC23 periph A SPI1_MOSI pin */
+                                                         2 24 0x1 0x0   /* PC24 periph A SPI1_SPCK pin */
+                                                         2 25 0x0 0x0>; /* PC25 GPIO SPI1_NPCS0 pin */
+                                        };
+                                };
+
+                                ssc0 {
+                                        pinctrl_ssc0_tx: ssc0_tx {
+                                                atmel,pins =
+                                                        <2 16 0x1 0x0   /* PC16 periph A TK0 */
+                                                         2 17 0x1 0x0   /* PC17 periph A TF0 */
+                                                         2 18 0x1 0x0>; /* PC18 periph A TD0 */
+                                        };
+
+                                        pinctrl_ssc0_rx: ssc0_rx {
+                                                atmel,pins =
+                                                        <2 19 0x1 0x0   /* PC19 periph A RK0 */
+                                                         2 20 0x1 0x0   /* PC20 periph A RF0 */
+                                                         2 21 0x1 0x0>; /* PC21 periph A RD0 */
+                                        };
+                                };
+
+                                ssc1 {
+                                        pinctrl_ssc1_tx: ssc1_tx {
+                                                atmel,pins =
+                                                        <1 2 0x2 0x0    /* PB2 periph B TK1, conflicts with GTX2 */
+                                                         1 3 0x2 0x0    /* PB3 periph B TF1, conflicts with GTX3 */
+                                                         1 6 0x2 0x0>;  /* PB6 periph B TD1, conflicts with TD1 */
+                                        };
+
+                                        pinctrl_ssc1_rx: ssc1_rx {
+                                                atmel,pins =
+                                                        <1 7 0x2 0x0    /* PB7 periph B RK1, conflicts with EREFCK */
+                                                         1 10 0x2 0x0   /* PB10 periph B RF1, conflicts with GTXER */
+                                                         1 11 0x2 0x0>; /* PB11 periph B RD1, conflicts with GRXCK */
+                                        };
+                                };
+
+                                uart0 {
+                                        pinctrl_uart0: uart0-0 {
+                                                atmel,pins =
+                                                        <2 29 0x1 0x0   /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
+                                                         2 30 0x1 0x1>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
+                                        };
+                                };
+
+                                uart1 {
+                                        pinctrl_uart1: uart1-0 {
+                                                atmel,pins =
+                                                        <0 30 0x2 0x0   /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
+                                                         0 31 0x2 0x1>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
+                                        };
+                                };
+
+                                usart0 {
+                                        pinctrl_usart0: usart0-0 {
+                                                atmel,pins =
+                                                        <3 17 0x1 0x0   /* PD17 periph A */
+                                                         3 18 0x1 0x1>; /* PD18 periph A with pullup */
+                                        };
+
+                                        pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
+                                                atmel,pins =
+                                                        <3 15 0x1 0x0   /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
+                                                         3 16 0x1 0x0>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
+                                        };
+                                };
+
+                                usart1 {
+                                        pinctrl_usart1: usart1-0 {
+                                                atmel,pins =
+                                                        <1 28 0x1 0x0   /* PB28 periph A */
+                                                         1 29 0x1 0x1>; /* PB29 periph A with pullup */
+                                        };
+
+                                        pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
+                                                atmel,pins =
+                                                        <1 26 0x1 0x0   /* PB26 periph A, conflicts with GRX7 */
+                                                         1 27 0x1 0x0>; /* PB27 periph A, conflicts with G125CKO */
+                                        };
+                                };
+
+                                usart2 {
+                                        pinctrl_usart2: usart2-0 {
+                                                atmel,pins =
+                                                        <4 25 0x2 0x0   /* PE25 periph B, conflicts with A25 */
+                                                         4 26 0x2 0x1>; /* PE26 periph B with pullup, conflicts NCS0 */
+                                        };
+
+                                        pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
+                                                atmel,pins =
+                                                        <4 23 0x2 0x0   /* PE23 periph B, conflicts with A23 */
+                                                         4 24 0x2 0x0>; /* PE24 periph B, conflicts with A24 */
+                                        };
+                                };
+
+                                usart3 {
+                                        pinctrl_usart3: usart3-0 {
+                                                atmel,pins =
+                                                        <4 18 0x2 0x0   /* PE18 periph B, conflicts with A18 */
+                                                         4 19 0x2 0x1>; /* PE19 periph B with pullup, conflicts with A19 */
+                                        };
+
+                                        pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
+                                                atmel,pins =
+                                                        <4 16 0x2 0x0   /* PE16 periph B, conflicts with A16 */
+                                                         4 17 0x2 0x0>; /* PE17 periph B, conflicts with A17 */
+                                        };
+                                };
+                        };
+
+                        pmc: pmc@fffffc00 {
+                                compatible = "atmel,at91rm9200-pmc";
+                                reg = <0xfffffc00 0x120>;
+                        };
+
+                        rstc@fffffe00 {
+                                compatible = "atmel,at91sam9g45-rstc";
+                                reg = <0xfffffe00 0x10>;
+                        };
+
+                        pit: timer@fffffe30 {
+                                compatible = "atmel,at91sam9260-pit";
+                                reg = <0xfffffe30 0xf>;
+                                interrupts = <3 4 5>;
+                        };
+
+                        watchdog@fffffe40 {
+                                compatible = "atmel,at91sam9260-wdt";
+                                reg = <0xfffffe40 0x10>;
+                                status = "disabled";
+                        };
+
+                        rtc@fffffeb0 {
+                                compatible = "atmel,at91rm9200-rtc";
+                                reg = <0xfffffeb0 0x30>;
+                                interrupts = <1 4 7>;
+                        };
+                };
+
+                usb0: gadget@00500000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "atmel,at91sam9rl-udc";
+                        reg = <0x00500000 0x100000
+                               0xf8030000 0x4000>;
+                        interrupts = <33 4 2>;
+                        status = "disabled";
+
+                        ep0 {
+                                reg = <0>;
+                                atmel,fifo-size = <64>;
+                                atmel,nb-banks = <1>;
+                        };
+
+                        ep1 {
+                                reg = <1>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <3>;
+                                atmel,can-dma;
+                                atmel,can-isoc;
+                        };
+
+                        ep2 {
+                                reg = <2>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <3>;
+                                atmel,can-dma;
+                                atmel,can-isoc;
+                        };
+
+                        ep3 {
+                                reg = <3>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                        };
+
+                        ep4 {
+                                reg = <4>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                        };
+
+                        ep5 {
+                                reg = <5>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                        };
+
+                        ep6 {
+                                reg = <6>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                        };
+
+                        ep7 {
+                                reg = <7>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                                atmel,can-dma;
+                        };
+
+                        ep8 {
+                                reg = <8>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep9 {
+                                reg = <9>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep10 {
+                                reg = <10>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep11 {
+                                reg = <11>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep12 {
+                                reg = <12>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep13 {
+                                reg = <13>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep14 {
+                                reg = <14>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+
+                        ep15 {
+                                reg = <15>;
+                                atmel,fifo-size = <1024>;
+                                atmel,nb-banks = <2>;
+                        };
+                };
+
+                usb1: ohci@00600000 {
+                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+                        reg = <0x00600000 0x100000>;
+                        interrupts = <32 4 2>;
+                        status = "disabled";
+                };
+
+                usb2: ehci@00700000 {
+                        compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+                        reg = <0x00700000 0x100000>;
+                        interrupts = <32 4 2>;
+                        status = "disabled";
+                };
+
+                nand0: nand@60000000 {
+                        compatible = "atmel,at91rm9200-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = < 0x60000000 0x01000000   /* EBI CS3 */
+                                0xffffc070 0x00000490   /* SMC PMECC regs */
+                                0xffffc500 0x00000100   /* SMC PMECC Error Location regs */
+                                0x00100000 0x00100000   /* ROM code */
+                                0x70000000 0x10000000   /* NFC Command Registers */
+                                0xffffc000 0x00000070   /* NFC HSMC regs */
+                                0x00200000 0x00100000   /* NFC SRAM banks */
+                                >;
+                        interrupts = <5 4 6>;
+                        atmel,nand-addr-offset = <21>;
+                        atmel,nand-cmd-offset = <22>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_nand0_ale_cle>;
+                        atmel,pmecc-lookup-table-offset = <0x10000 0x18000>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts
new file mode 100644
index 000000000000..fa5d216f1db7
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d31ek.dts
@@ -0,0 +1,51 @@
+/*
+ * sama5d31ek.dts - Device Tree file for SAMA5D31-EK board
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "sama5d3xmb.dtsi"
+/include/ "sama5d3xdm.dtsi"
+
+/ {
+        model = "Atmel SAMA5D31-EK";
+        compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
+
+        ahb {
+                apb {
+                        spi0: spi@f0004000 {
+                                status = "okay";
+                        };
+
+                        ssc0: ssc@f0008000 {
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@f0014000 {
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@f0018000 {
+                                status = "okay";
+                        };
+
+                        macb1: ethernet@f802c000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        leds {
+                d3 {
+                        label = "d3";
+                        gpios = <&pioE 24 0>;
+                };
+        };
+
+        sound {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts
new file mode 100644
index 000000000000..c38c9433d7a5
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d33ek.dts
@@ -0,0 +1,44 @@
+/*
+ * sama5d33ek.dts - Device Tree file for SAMA5D33-EK board
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "sama5d3xmb.dtsi"
+/include/ "sama5d3xdm.dtsi"
+
+/ {
+        model = "Atmel SAMA5D33-EK";
+        compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
+
+        ahb {
+                apb {
+                        spi0: spi@f0004000 {
+                                status = "okay";
+                        };
+
+                        ssc0: ssc@f0008000 {
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@f0014000 {
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@f0018000 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@f0028000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        sound {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts
new file mode 100644
index 000000000000..d2739f8d7ae9
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d34ek.dts
@@ -0,0 +1,61 @@
+/*
+ * sama5d34ek.dts - Device Tree file for SAMA5D34-EK board
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "sama5d3xmb.dtsi"
+/include/ "sama5d3xdm.dtsi"
+
+/ {
+        model = "Atmel SAMA5D34-EK";
+        compatible = "atmel,sama5d34ek", "atmel,sama5ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
+
+        ahb {
+                apb {
+                        spi0: spi@f0004000 {
+                                status = "okay";
+                        };
+
+                        ssc0: ssc@f0008000 {
+                                status = "okay";
+                        };
+
+                        can0: can@f000c000 {
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@f0014000 {
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@f0018000 {
+                                status = "okay";
+
+                                24c256@50 {
+                                        compatible = "24c256";
+                                        reg = <0x50>;
+                                        pagesize = <64>;
+                                };
+                        };
+
+                        macb0: ethernet@f0028000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        leds {
+                d3 {
+                        label = "d3";
+                        gpios = <&pioE 24 0>;
+                };
+        };
+
+        sound {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts
new file mode 100644
index 000000000000..a488fc4e9777
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d35ek.dts
@@ -0,0 +1,56 @@
+/*
+ * sama5d35ek.dts - Device Tree file for SAMA5D35-EK board
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "sama5d3xmb.dtsi"
+
+/ {
+        model = "Atmel SAMA5D35-EK";
+        compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
+
+        ahb {
+                apb {
+                        spi0: spi@f0004000 {
+                                status = "okay";
+                        };
+
+                        can0: can@f000c000 {
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@f0018000 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@f0028000 {
+                                status = "okay";
+                        };
+
+                        isi: isi@f0034000 {
+                                status = "okay";
+                        };
+
+                        macb1: ethernet@f802c000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                pb_user1 {
+                        label = "pb_user1";
+                        gpios = <&pioE 27 0>;
+                        linux,code = <0x100>;
+                        gpio-key,wakeup;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
new file mode 100644
index 000000000000..1f8ed404626c
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -0,0 +1,91 @@
+/*
+ * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/include/ "sama5d3.dtsi"
+
+/ {
+        compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs";
+        };
+
+        memory {
+                reg = <0x20000000 0x20000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        macb0: ethernet@f0028000 {
+                                phy-mode = "rgmii";
+                        };
+                };
+
+                nand0: nand@60000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "hw";
+                        atmel,has-pmecc;
+                        atmel,pmecc-cap = <4>;
+                        atmel,pmecc-sector-size = <512>;
+                        atmel,has-nfc;
+                        atmel,use-nfc-sram;
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x40000>;
+                        };
+
+                        bootloader@40000 {
+                                label = "bootloader";
+                                reg = <0x40000 0x80000>;
+                        };
+
+                        bootloaderenv@c0000 {
+                                label = "bootloader env";
+                                reg = <0xc0000 0xc0000>;
+                        };
+
+                        dtb@180000 {
+                                label = "device tree";
+                                reg = <0x180000 0x80000>;
+                        };
+
+                        kernel@200000 {
+                                label = "kernel";
+                                reg = <0x200000 0x600000>;
+                        };
+
+                        rootfs@800000 {
+                                label = "rootfs";
+                                reg = <0x800000 0x0f800000>;
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                d2 {
+                        label = "d2";
+                        gpios = <&pioE 25 1>;   /* PE25, conflicts with A25, RXD2 */
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi
new file mode 100644
index 000000000000..4b8830eb2060
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3xdm.dtsi
@@ -0,0 +1,42 @@
+/*
+ * sama5d3dm.dtsi - Device Tree file for SAMA5 display module
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/ {
+        ahb {
+                apb {
+                        i2c1: i2c@f0018000 {
+                                qt1070: keyboard@1b {
+                                        compatible = "qt1070";
+                                        reg = <0x1b>;
+                                        interrupt-parent = <&pioE>;
+                                        interrupts = <31 0x0>;
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_qt1070_irq>;
+                                };
+                        };
+
+                        adc0: adc@f8018000 {
+                                status = "disabled";
+                        };
+
+                        tsadcc: tsadcc@f8018000 {
+                                status = "okay";
+                        };
+
+                        pinctrl@fffff200 {
+                                board {
+                                        pinctrl_qt1070_irq: qt1070_irq {
+                                                atmel,pins =
+                                                        <4 31 0x0 0x5>; /* PE31 GPIO with pull up deglith */
+                                        };
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
new file mode 100644
index 000000000000..661d7ca9c309
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -0,0 +1,166 @@
+/*
+ * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/include/ "sama5d3xcm.dtsi"
+
+/ {
+        compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
+
+        ahb {
+                apb {
+                        mmc0: mmc@f0000000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioD 17 0>;
+                                };
+                        };
+
+                        spi0: spi@f0004000 {
+                                m25p80@0 {
+                                        compatible = "atmel,at25df321a";
+                                        spi-max-frequency = <50000000>;
+                                        reg = <0>;
+                                };
+                        };
+
+                        /*
+                         * i2c0 conflicts with ISI:
+                         * disable it to allow the use of ISI
+                         * can not enable audio when i2c0 disabled
+                         */
+                        i2c0: i2c@f0014000 {
+                                wm8904: wm8904@1a {
+                                        compatible = "wm8904";
+                                        reg = <0x1a>;
+                                };
+                        };
+
+                        usart1: serial@f0020000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
+                                status = "okay";
+                        };
+
+                        isi: isi@f0034000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_isi &pinctrl_isi_pck_as_mck &pinctrl_isi_power &pinctrl_isi_reset>;
+                        };
+
+                        mmc1: mmc@f8000000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioD 18 0>;
+                                };
+                        };
+
+                        adc0: adc@f8018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <
+                                        &pinctrl_adc0_adtrg
+                                        &pinctrl_adc0_ad0
+                                        &pinctrl_adc0_ad1
+                                        &pinctrl_adc0_ad2
+                                        &pinctrl_adc0_ad3
+                                        &pinctrl_adc0_ad4
+                                        >;
+                                status = "okay";
+                        };
+
+                        macb1: ethernet@f802c000 {
+                                phy-mode = "rmii";
+                        };
+
+                        pinctrl@fffff200 {
+                                board {
+                                        pinctrl_mmc0_cd: mmc0_cd {
+                                                atmel,pins =
+                                                        <3 17 0x0 0x5>; /* PD17 GPIO with pullup deglitch */
+                                        };
+
+                                        pinctrl_mmc1_cd: mmc1_cd {
+                                                atmel,pins =
+                                                        <3 18 0x0 0x5>; /* PD18 GPIO with pullup deglitch */
+                                        };
+
+                                        pinctrl_pck0_as_audio_mck: pck0_as_audio_mck {
+                                                atmel,pins =
+                                                        <3 30 0x2 0x0>; /* PD30 periph B */
+                                        };
+
+                                        pinctrl_isi_reset: isi_reset-0 {
+                                                atmel,pins =
+                                                        <4 24 0x0 0x0>;   /* PE24 gpio */
+                                        };
+
+                                        pinctrl_isi_power: isi_power-0 {
+                                                atmel,pins =
+                                                        <4 29 0x0 0x0>; /* PE29 gpio */
+                                        };
+
+                                        pinctrl_usba_vbus: usba_vbus {
+                                                atmel,pins =
+                                                        <3 29 0x0 0x4>; /* PD29 GPIO with deglitch */
+                                        };
+                                };
+                        };
+
+                        dbgu: serial@ffffee00 {
+                                status = "okay";
+                        };
+
+                        watchdog@fffffe40 {
+                                status = "okay";
+                        };
+                };
+
+                usb0: gadget@00500000 {
+                        atmel,vbus-gpio = <&pioD 29 0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usba_vbus>;
+                        status = "okay";
+                };
+
+                usb1: ohci@00600000 {
+                        num-ports = <3>;
+                        atmel,vbus-gpio = <&pioD 25 0
+                                           &pioD 26 1
+                                           &pioD 27 1
+                                          >;
+                        status = "okay";
+                };
+
+                usb2: ehci@00700000 {
+                        status = "okay";
+                };
+        };
+
+        sound {
+                compatible = "atmel,sama5d3ek-wm8904";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pck0_as_audio_mck>;
+
+                atmel,model = "wm8904 @ SAMA5D3EK";
+                atmel,audio-routing =
+                        "Headphone Jack", "HPOUTL",
+                        "Headphone Jack", "HPOUTR",
+                        "IN2L", "Line In Jack",
+                        "IN2R", "Line In Jack",
+                        "IN1L", "Mic";
+
+                atmel,ssc-controller = <&ssc0>;
+                atmel,audio-codec = <&wm8904>;
+        };
+};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
new file mode 100644
index 000000000000..f33b5ccb7446
--- /dev/null
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -0,0 +1,66 @@
+/*
+ * Device Tree Source for the KZM-A9-GT board
+ *
+ * Copyright (C) 2012 Horms Solutions Ltd.
+ *
+ * Based on sh73a0-kzm9g.dts
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "sh73a0.dtsi"
+
+/ {
+        model = "KZM-A9-GT";
+        compatible = "renesas,kzm9g-reference", "renesas,sh73a0";
+
+        chosen {
+                bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x41000000 0x1e800000>;
+        };
+
+        reg_1p8v: regulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-1.8V";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+        reg_3p3v: regulator@1 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+};
+
+&mmcif {
+        bus-width = <8>;
+        vmmc-supply = <&reg_1p8v>;
+        status = "okay";
+};
+
+&sdhi0 {
+        vmmc-supply = <&reg_3p3v>;
+        bus-width = <4>;
+        status = "okay";
+};
+
+&sdhi2 {
+        vmmc-supply = <&reg_3p3v>;
+        bus-width = <4>;
+        broken-cd;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/sh73a0-reference.dtsi b/arch/arm/boot/dts/sh73a0-reference.dtsi
deleted file mode 100644
index d4bb0125b2b2..000000000000
--- a/arch/arm/boot/dts/sh73a0-reference.dtsi
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Device Tree Source for the SH73A0 SoC
- *
- * Copyright (C) 2012 Renesas Solutions Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/include/ "sh73a0.dtsi"
-
-/ {
-        compatible = "renesas,sh73a0";
-
-        mmcif: mmcif@0x10010000 {
-                compatible = "renesas,sh-mmcif";
-                reg = <0xe6bd0000 0x100>;
-                interrupt-parent = <&gic>;
-                interrupts = <0 140 0x4
-                              0 141 0x4>;
-                reg-io-width = <4>;
-        };
-};
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 8a59465d0231..3e4d383ac6d9 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -97,4 +97,48 @@
                               0 189 0x4
                               0 190 0x4>;
         };
+
+        mmcif: mmcif@0x10010000 {
+                compatible = "renesas,sh-mmcif";
+                reg = <0xe6bd0000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 140 0x4
+                              0 141 0x4>;
+                reg-io-width = <4>;
+                status = "disabled";
+        };
+
+        sdhi0: sdhi@0xee100000 {
+                compatible = "renesas,r8a7740-sdhi";
+                reg = <0xee100000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 83 4
+                                0 84 4
+                                0 85 4>;
+                cap-sd-highspeed;
+                status = "disabled";
+        };
+
+        /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
+        sdhi1: sdhi@0xee120000 {
+                compatible = "renesas,r8a7740-sdhi";
+                reg = <0xee120000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 88 4
+                                0 89 4>;
+                toshiba,mmc-wrprotect-disable;
+                cap-sd-highspeed;
+                status = "disabled";
+        };
+
+        sdhi2: sdhi@0xee140000 {
+                compatible = "renesas,r8a7740-sdhi";
+                reg = <0xee140000 0x100>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 104 4
+                                0 105 4>;
+                toshiba,mmc-wrprotect-disable;
+                cap-sd-highspeed;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/skeleton64.dtsi b/arch/arm/boot/dts/skeleton64.dtsi
new file mode 100644
index 000000000000..15994158a998
--- /dev/null
+++ b/arch/arm/boot/dts/skeleton64.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Skeleton device tree in the 64 bits version; the bare minimum
+ * needed to boot; just include and add a compatible value.  The
+ * bootloader will typically populate the memory node.
+ */
+
+/ {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        chosen { };
+        aliases { };
+        memory { device_type = "memory"; reg = <0 0>; };
+};
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index d3ec32f6b790..db5db24fd544 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -299,6 +299,10 @@
                         };
 
                         ab8500 {
+                                ab8500-gpio {
+                                        compatible = "stericsson,ab8500-gpio";
+                                };
+
                                 ab8500-regulators {
                                         ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
                                                 regulator-name = "V-DISPLAY";
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 7e8769bd5977..16a6e13e08b4 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -81,6 +81,163 @@
                         };
                 };
 
+                clkmgr@ffd04000 {
+                                compatible = "altr,clk-mgr";
+                                reg = <0xffd04000 0x1000>;
+
+                                clocks {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        osc: osc1 {
+                                                #clock-cells = <0>;
+                                                compatible = "fixed-clock";
+                                        };
+
+                                        main_pll: main_pll {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-pll-clock";
+                                                clocks = <&osc>;
+                                                reg = <0x40>;
+
+                                                mpuclk: mpuclk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&main_pll>;
+                                                        fixed-divider = <2>;
+                                                        reg = <0x48>;
+                                                };
+
+                                                mainclk: mainclk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&main_pll>;
+                                                        fixed-divider = <4>;
+                                                        reg = <0x4C>;
+                                                };
+
+                                                dbg_base_clk: dbg_base_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&main_pll>;
+                                                        fixed-divider = <4>;
+                                                        reg = <0x50>;
+                                                };
+
+                                                main_qspi_clk: main_qspi_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&main_pll>;
+                                                        reg = <0x54>;
+                                                };
+
+                                                main_nand_sdmmc_clk: main_nand_sdmmc_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&main_pll>;
+                                                        reg = <0x58>;
+                                                };
+
+                                                cfg_s2f_usr0_clk: cfg_s2f_usr0_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&main_pll>;
+                                                        reg = <0x5C>;
+                                                };
+                                        };
+
+                                        periph_pll: periph_pll {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-pll-clock";
+                                                clocks = <&osc>;
+                                                reg = <0x80>;
+
+                                                emac0_clk: emac0_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&periph_pll>;
+                                                        reg = <0x88>;
+                                                };
+
+                                                emac1_clk: emac1_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&periph_pll>;
+                                                        reg = <0x8C>;
+                                                };
+
+                                                per_qspi_clk: per_qsi_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&periph_pll>;
+                                                        reg = <0x90>;
+                                                };
+
+                                                per_nand_mmc_clk: per_nand_mmc_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&periph_pll>;
+                                                        reg = <0x94>;
+                                                };
+
+                                                per_base_clk: per_base_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&periph_pll>;
+                                                        reg = <0x98>;
+                                                };
+
+                                                s2f_usr1_clk: s2f_usr1_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&periph_pll>;
+                                                        reg = <0x9C>;
+                                                };
+                                        };
+
+                                        sdram_pll: sdram_pll {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-pll-clock";
+                                                clocks = <&osc>;
+                                                reg = <0xC0>;
+
+                                                ddr_dqs_clk: ddr_dqs_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&sdram_pll>;
+                                                        reg = <0xC8>;
+                                                };
+
+                                                ddr_2x_dqs_clk: ddr_2x_dqs_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&sdram_pll>;
+                                                        reg = <0xCC>;
+                                                };
+
+                                                ddr_dq_clk: ddr_dq_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&sdram_pll>;
+                                                        reg = <0xD0>;
+                                                };
+
+                                                s2f_usr2_clk: s2f_usr2_clk {
+                                                        #clock-cells = <0>;
+                                                        compatible = "altr,socfpga-perip-clk";
+                                                        clocks = <&sdram_pll>;
+                                                        reg = <0xD4>;
+                                                };
+                                        };
+                                };
+                        };
+
                 gmac0: stmmac@ff700000 {
                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
                         reg = <0xff700000 0x2000>;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index 3ae8a83a0875..2495958f1016 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -33,6 +33,14 @@
         };
 
         soc {
+                clkmgr@ffd04000 {
+                        clocks {
+                                osc1 {
+                                        clock-frequency = <25000000>;
+                                };
+                        };
+                };
+
                 timer0@ffc08000 {
                         clock-frequency = <100000000>;
                 };
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 1036eba40bbf..0bf035d607f0 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -33,6 +33,14 @@
         };
 
         soc {
+                clkmgr@ffd04000 {
+                        clocks {
+                                osc1 {
+                                        clock-frequency = <10000000>;
+                                };
+                        };
+                };
+
                 timer0@ffc08000 {
                         clock-frequency = <7000000>;
                 };
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 1513c1927cc8..122ae94076c8 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -89,7 +89,7 @@
                 pinmux: pinmux@e0700000 {
                         compatible = "st,spear1310-pinmux";
                         reg = <0xe0700000 0x1000>;
-                        #gpio-range-cells = <2>;
+                        #gpio-range-cells = <3>;
                 };
 
                 apb {
@@ -212,7 +212,7 @@
                                 interrupt-controller;
                                 gpio-controller;
                                 #gpio-cells = <2>;
-                                gpio-ranges = <&pinmux 0 246>;
+                                gpio-ranges = <&pinmux 0 0 246>;
                                 status = "disabled";
 
                                 st-plgpio,ngpio = <246>;
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 34da11aa6795..c511c4772efd 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -63,7 +63,7 @@
                 pinmux: pinmux@e0700000 {
                         compatible = "st,spear1340-pinmux";
                         reg = <0xe0700000 0x1000>;
-                        #gpio-range-cells = <2>;
+                        #gpio-range-cells = <3>;
                 };
 
                 pwm: pwm@e0180000 {
@@ -127,7 +127,7 @@
                                 interrupt-controller;
                                 gpio-controller;
                                 #gpio-cells = <2>;
-                                gpio-ranges = <&pinmux 0 252>;
+                                gpio-ranges = <&pinmux 0 0 252>;
                                 status = "disabled";
 
                                 st-plgpio,ngpio = <250>;
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
index ab45b8c81982..95372080eea6 100644
--- a/arch/arm/boot/dts/spear310.dtsi
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -25,7 +25,7 @@
                 pinmux: pinmux@b4000000 {
                         compatible = "st,spear310-pinmux";
                         reg = <0xb4000000 0x1000>;
-                        #gpio-range-cells = <2>;
+                        #gpio-range-cells = <3>;
                 };
 
                 fsmc: flash@44000000 {
@@ -102,7 +102,7 @@
                                 interrupt-controller;
                                 gpio-controller;
                                 #gpio-cells = <2>;
-                                gpio-ranges = <&pinmux 0 102>;
+                                gpio-ranges = <&pinmux 0 0 102>;
                                 status = "disabled";
 
                                 st-plgpio,ngpio = <102>;
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
index caa5520b1fd4..ffea342aeec9 100644
--- a/arch/arm/boot/dts/spear320.dtsi
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -24,7 +24,7 @@
                 pinmux: pinmux@b3000000 {
                         compatible = "st,spear320-pinmux";
                         reg = <0xb3000000 0x1000>;
-                        #gpio-range-cells = <2>;
+                        #gpio-range-cells = <3>;
                 };
 
                 clcd@90000000 {
@@ -130,7 +130,7 @@
                                 interrupt-controller;
                                 gpio-controller;
                                 #gpio-cells = <2>;
-                                gpio-ranges = <&pinmux 0 102>;
+                                gpio-ranges = <&pinmux 0 0 102>;
                                 status = "disabled";
 
                                 st-plgpio,ngpio = <102>;
diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi
index 39446a247e79..615392a75676 100644
--- a/arch/arm/boot/dts/stuib.dtsi
+++ b/arch/arm/boot/dts/stuib.dtsi
@@ -15,7 +15,7 @@
                         stmpe1601: stmpe1601@40 {
                                 compatible = "st,stmpe1601";
                                 reg = <0x40>;
-                                interrupts = <26 0x1>;
+                                interrupts = <26 0x2>;
                                 interrupt-parent = <&gpio6>;
                                 interrupt-controller;
 
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 5cab82540437..b70fe0db6bb7 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -26,13 +26,37 @@
                 bootargs = "earlyprintk console=ttyS0,115200";
         };
 
-        soc {
-                uart0: uart@01c28000 {
-                        status = "okay";
+        soc@01c20000 {
+                pinctrl@01c20800 {
+                        led_pins_cubieboard: led_pins@0 {
+                                allwinner,pins = "PH20", "PH21";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <1>;
+                                allwinner,pull = <0>;
+                        };
                 };
 
-                uart1: uart@01c28400 {
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
                         status = "okay";
                 };
         };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_cubieboard>;
+
+                blue {
+                        label = "cubieboard::blue";
+                        gpios = <&pio 7 21 0>; /* LED1 */
+                };
+
+                green {
+                        label = "cubieboard::green";
+                        gpios = <&pio 7 20 0>; /* LED2 */
+                        linux,default-trigger = "heartbeat";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index f84549ad791e..b9efac100c85 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -22,8 +22,10 @@
                 bootargs = "earlyprintk console=ttyS0,115200";
         };
 
-        soc {
-                uart0: uart@01c28000 {
+        soc@01c20000 {
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
                         status = "okay";
                 };
         };
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
new file mode 100644
index 000000000000..4a7c35d6726a
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun4i-a10.dtsi"
+
+/ {
+        model = "PineRiver Mini X-Plus";
+        compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10";
+
+        chosen {
+                bootargs = "earlyprintk console=ttyS0,115200";
+        };
+
+        soc {
+                uart0: uart@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index f99f60dadf5d..e7ef619a70a2 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -10,19 +10,174 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "sunxi.dtsi"
+/include/ "skeleton.dtsi"
 
 / {
+        interrupt-parent = <&intc>;
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a8";
+                };
+        };
+
         memory {
                 reg = <0x40000000 0x80000000>;
         };
 
-        soc {
-                pinctrl@01c20800 {
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                /*
+                 * This is a dummy clock, to be used as placeholder on
+                 * other mux clocks when a specific parent clock is not
+                 * yet implemented. It should be dropped when the driver
+                 * is complete.
+                 */
+                dummy: dummy {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <0>;
+                };
+
+                osc24M: osc24M@01c20050 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-osc-clk";
+                        reg = <0x01c20050 0x4>;
+                        clock-frequency = <24000000>;
+                };
+
+                osc32k: osc32k {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+
+                pll1: pll1@01c20000 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20000 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                /* dummy is 200M */
+                cpu: cpu@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-cpu-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
+                };
+
+                axi: axi@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-axi-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&cpu>;
+                };
+
+                axi_gates: axi_gates@01c2005c {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-axi-gates-clk";
+                        reg = <0x01c2005c 0x4>;
+                        clocks = <&axi>;
+                        clock-output-names = "axi_dram";
+                };
+
+                ahb: ahb@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-ahb-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&axi>;
+                };
+
+                ahb_gates: ahb_gates@01c20060 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-ahb-gates-clk";
+                        reg = <0x01c20060 0x8>;
+                        clocks = <&ahb>;
+                        clock-output-names = "ahb_usb0", "ahb_ehci0",
+                                "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
+                                "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+                                "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
+                                "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
+                                "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
+                                "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
+                                "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
+                                "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
+                                "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+                                "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+                };
+
+                apb0: apb0@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb0-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&ahb>;
+                };
+
+                apb0_gates: apb0_gates@01c20068 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-apb0-gates-clk";
+                        reg = <0x01c20068 0x4>;
+                        clocks = <&apb0>;
+                        clock-output-names = "apb0_codec", "apb0_spdif",
+                                "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
+                                "apb0_ir1", "apb0_keypad";
+                };
+
+                /* dummy is pll62 */
+                apb1_mux: apb1_mux@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-mux-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                };
+
+                apb1: apb1@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&apb1_mux>;
+                };
+
+                apb1_gates: apb1_gates@01c2006c {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-apb1-gates-clk";
+                        reg = <0x01c2006c 0x4>;
+                        clocks = <&apb1>;
+                        clock-output-names = "apb1_i2c0", "apb1_i2c1",
+                                "apb1_i2c2", "apb1_can", "apb1_scr",
+                                "apb1_ps20", "apb1_ps21", "apb1_uart0",
+                                "apb1_uart1", "apb1_uart2", "apb1_uart3",
+                                "apb1_uart4", "apb1_uart5", "apb1_uart6",
+                                "apb1_uart7";
+                };
+        };
+
+        soc@01c20000 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x01c20000 0x300000>;
+                ranges;
+
+                intc: interrupt-controller@01c20400 {
+                        compatible = "allwinner,sun4i-ic";
+                        reg = <0x01c20400 0x400>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                pio: pinctrl@01c20800 {
                         compatible = "allwinner,sun4i-a10-pinctrl";
                         reg = <0x01c20800 0x400>;
+                        clocks = <&apb0_gates 5>;
+                        gpio-controller;
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        #gpio-cells = <3>;
 
                         uart0_pins_a: uart0@0 {
                                 allwinner,pins = "PB22", "PB23";
@@ -45,5 +200,97 @@
                                 allwinner,pull = <0>;
                         };
                 };
+
+                timer@01c20c00 {
+                        compatible = "allwinner,sun4i-timer";
+                        reg = <0x01c20c00 0x90>;
+                        interrupts = <22>;
+                        clocks = <&osc24M>;
+                };
+
+                wdt: watchdog@01c20c90 {
+                        compatible = "allwinner,sun4i-wdt";
+                        reg = <0x01c20c90 0x10>;
+                };
+
+                uart0: serial@01c28000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28000 0x400>;
+                        interrupts = <1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 16>;
+                        status = "disabled";
+                };
+
+                uart1: serial@01c28400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28400 0x400>;
+                        interrupts = <2>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 17>;
+                        status = "disabled";
+                };
+
+                uart2: serial@01c28800 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28800 0x400>;
+                        interrupts = <3>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 18>;
+                        status = "disabled";
+                };
+
+                uart3: serial@01c28c00 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28c00 0x400>;
+                        interrupts = <4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 19>;
+                        status = "disabled";
+                };
+
+                uart4: serial@01c29000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c29000 0x400>;
+                        interrupts = <17>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 20>;
+                        status = "disabled";
+                };
+
+                uart5: serial@01c29400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c29400 0x400>;
+                        interrupts = <18>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 21>;
+                        status = "disabled";
+                };
+
+                uart6: serial@01c29800 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c29800 0x400>;
+                        interrupts = <19>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 22>;
+                        status = "disabled";
+                };
+
+                uart7: serial@01c29c00 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c29c00 0x400>;
+                        interrupts = <20>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 23>;
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 4a1e45d4aace..3ca55067f868 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -22,11 +22,31 @@
                 bootargs = "earlyprintk console=ttyS0,115200";
         };
 
-        soc {
-                uart1: uart@01c28400 {
+        soc@01c20000 {
+                pinctrl@01c20800 {
+                        led_pins_olinuxino: led_pins@0 {
+                                allwinner,pins = "PG9";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <1>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                uart1: serial@01c28400 {
                         pinctrl-names = "default";
                         pinctrl-0 = <&uart1_pins_b>;
                         status = "okay";
                 };
         };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_olinuxino>;
+
+                power {
+                        gpios = <&pio 6 9 0>;
+                        default-state = "on";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index e1121890fb29..31fa38f8cc98 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -11,19 +11,174 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "sunxi.dtsi"
+/include/ "skeleton.dtsi"
 
 / {
+        interrupt-parent = <&intc>;
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a8";
+                };
+        };
+
         memory {
                 reg = <0x40000000 0x20000000>;
         };
 
-        soc {
-                pinctrl@01c20800 {
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                /*
+                 * This is a dummy clock, to be used as placeholder on
+                 * other mux clocks when a specific parent clock is not
+                 * yet implemented. It should be dropped when the driver
+                 * is complete.
+                 */
+                dummy: dummy {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <0>;
+                };
+
+                osc24M: osc24M@01c20050 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-osc-clk";
+                        reg = <0x01c20050 0x4>;
+                        clock-frequency = <24000000>;
+                };
+
+                osc32k: osc32k {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+
+                pll1: pll1@01c20000 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20000 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                /* dummy is 200M */
+                cpu: cpu@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-cpu-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
+                };
+
+                axi: axi@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-axi-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&cpu>;
+                };
+
+                axi_gates: axi_gates@01c2005c {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-axi-gates-clk";
+                        reg = <0x01c2005c 0x4>;
+                        clocks = <&axi>;
+                        clock-output-names = "axi_dram";
+                };
+
+                ahb: ahb@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-ahb-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&axi>;
+                };
+
+                ahb_gates: ahb_gates@01c20060 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-ahb-gates-clk";
+                        reg = <0x01c20060 0x8>;
+                        clocks = <&ahb>;
+                        clock-output-names = "ahb_usb0", "ahb_ehci0",
+                                "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
+                                "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+                                "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
+                                "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
+                                "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
+                                "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
+                                "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
+                                "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
+                                "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+                                "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+                };
+
+                apb0: apb0@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb0-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&ahb>;
+                };
+
+                apb0_gates: apb0_gates@01c20068 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-apb0-gates-clk";
+                        reg = <0x01c20068 0x4>;
+                        clocks = <&apb0>;
+                        clock-output-names = "apb0_codec", "apb0_spdif",
+                                "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
+                                "apb0_ir1", "apb0_keypad";
+                };
+
+                /* dummy is pll62 */
+                apb1_mux: apb1_mux@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-mux-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                };
+
+                apb1: apb1@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&apb1_mux>;
+                };
+
+                apb1_gates: apb1_gates@01c2006c {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-apb1-gates-clk";
+                        reg = <0x01c2006c 0x4>;
+                        clocks = <&apb1>;
+                        clock-output-names = "apb1_i2c0", "apb1_i2c1",
+                                "apb1_i2c2", "apb1_can", "apb1_scr",
+                                "apb1_ps20", "apb1_ps21", "apb1_uart0",
+                                "apb1_uart1", "apb1_uart2", "apb1_uart3",
+                                "apb1_uart4", "apb1_uart5", "apb1_uart6",
+                                "apb1_uart7";
+                };
+        };
+
+        soc@01c20000 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x01c20000 0x300000>;
+                ranges;
+
+                intc: interrupt-controller@01c20400 {
+                        compatible = "allwinner,sun4i-ic";
+                        reg = <0x01c20400 0x400>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                pio: pinctrl@01c20800 {
                         compatible = "allwinner,sun5i-a13-pinctrl";
                         reg = <0x01c20800 0x400>;
+                        clocks = <&apb0_gates 5>;
+                        gpio-controller;
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        #gpio-cells = <3>;
 
                         uart1_pins_a: uart1@0 {
                                 allwinner,pins = "PE10", "PE11";
@@ -39,5 +194,37 @@
                                 allwinner,pull = <0>;
                         };
                 };
+
+                timer@01c20c00 {
+                        compatible = "allwinner,sun4i-timer";
+                        reg = <0x01c20c00 0x90>;
+                        interrupts = <22>;
+                        clocks = <&osc24M>;
+                };
+
+                wdt: watchdog@01c20c90 {
+                        compatible = "allwinner,sun4i-wdt";
+                        reg = <0x01c20c90 0x10>;
+                };
+
+                uart1: serial@01c28400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28400 0x400>;
+                        interrupts = <2>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 17>;
+                        status = "disabled";
+                };
+
+                uart3: serial@01c28c00 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28c00 0x400>;
+                        interrupts = <4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 19>;
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi
deleted file mode 100644
index 8b36abea9f2e..000000000000
--- a/arch/arm/boot/dts/sunxi.dtsi
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright 2012 Maxime Ripard
- *
- * Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/include/ "skeleton.dtsi"
-
-/ {
-        interrupt-parent = <&intc>;
-
-        cpus {
-                cpu@0 {
-                        compatible = "arm,cortex-a8";
-                };
-        };
-
-        clocks {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                osc: oscillator {
-                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <24000000>;
-                };
-        };
-
-        soc {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                reg = <0x01c20000 0x300000>;
-                ranges;
-
-                timer@01c20c00 {
-                        compatible = "allwinner,sunxi-timer";
-                        reg = <0x01c20c00 0x90>;
-                        interrupts = <22>;
-                        clocks = <&osc>;
-                };
-
-                wdt: watchdog@01c20c90 {
-                        compatible = "allwinner,sunxi-wdt";
-                        reg = <0x01c20c90 0x10>;
-                };
-
-                intc: interrupt-controller@01c20400 {
-                        compatible = "allwinner,sunxi-ic";
-                        reg = <0x01c20400 0x400>;
-                        interrupt-controller;
-                        #interrupt-cells = <1>;
-                };
-
-                uart0: uart@01c28000 {
-                        compatible = "snps,dw-apb-uart";
-                        reg = <0x01c28000 0x400>;
-                        interrupts = <1>;
-                        reg-shift = <2>;
-                        reg-io-width = <4>;
-                        clock-frequency = <24000000>;
-                        status = "disabled";
-                };
-
-                uart1: uart@01c28400 {
-                        compatible = "snps,dw-apb-uart";
-                        reg = <0x01c28400 0x400>;
-                        interrupts = <2>;
-                        reg-shift = <2>;
-                        reg-io-width = <4>;
-                        clock-frequency = <24000000>;
-                        status = "disabled";
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index a30aca62658a..616990dc92db 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -12,10 +12,22 @@
 
         serial@70006300 {
                 status = "okay";
-                clock-frequency = <408000000>;
         };
 
         pmc {
                 nvidia,invert-interrupt;
         };
+
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
index 9bea8f57aa47..6bbc8efae9c0 100644
--- a/arch/arm/boot/dts/tegra114-pluto.dts
+++ b/arch/arm/boot/dts/tegra114-pluto.dts
@@ -12,10 +12,22 @@
 
         serial@70006300 {
                 status = "okay";
-                clock-frequency = <408000000>;
         };
 
         pmc {
                 nvidia,invert-interrupt;
         };
+
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 1dfaf2874c57..c1110a9b2a91 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -24,10 +24,11 @@
                               0 42 0x04
                               0 121 0x04
                               0 122 0x04>;
+                clocks = <&tegra_car 5>;
         };
 
         tegra_car: clock {
-                compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
+                compatible = "nvidia,tegra114-car";
                 reg = <0x60006000 0x1000>;
                 #clock-cells = <1>;
         };
@@ -66,6 +67,7 @@
                 reg-shift = <2>;
                 interrupts = <0 36 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 6>;
         };
 
         serial@70006040 {
@@ -74,6 +76,7 @@
                 reg-shift = <2>;
                 interrupts = <0 37 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 192>;
         };
 
         serial@70006200 {
@@ -82,6 +85,7 @@
                 reg-shift = <2>;
                 interrupts = <0 46 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 55>;
         };
 
         serial@70006300 {
@@ -90,17 +94,21 @@
                 reg-shift = <2>;
                 interrupts = <0 90 0x04>;
                 status = "disabled";
+                clocks = <&tegra_car 65>;
         };
 
         rtc {
                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <0 2 0x04>;
+                clocks = <&tegra_car 4>;
         };
 
         pmc {
-                compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
+                compatible = "nvidia,tegra114-pmc";
                 reg = <0x7000e400 0x400>;
+                clocks = <&tegra_car 261>, <&clk32k_in>;
+                clock-names = "pclk", "clk32k_in";
         };
 
         iommu {
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 444162090042..4e3afdef28a8 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -444,7 +444,20 @@
         };
 
         sdhci@c8000600 {
-                cd-gpios = <&gpio 23 0>; /* gpio PC7 */
+                cd-gpios = <&gpio 23 1>; /* gpio PC7 */
+        };
+
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
         };
 
         sound {
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 61d027f03617..ae9d5a20834e 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -437,7 +437,7 @@
 
         sdhci@c8000200 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
                 power-gpios = <&gpio 155 0>; /* gpio PT3 */
                 bus-width = <4>;
@@ -445,12 +445,25 @@
 
         sdhci@c8000600 {
                 status = "okay";
-                cd-gpios = <&gpio 58 0>; /* gpio PH2 */
+                cd-gpios = <&gpio 58 1>; /* gpio PH2 */
                 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
                 power-gpios = <&gpio 70 0>; /* gpio PI6 */
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         kbc {
                 status = "okay";
                 nvidia,debounce-delay-ms = <2>;
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 54d6fce00a59..fd60940e4063 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -436,7 +436,7 @@
 
         sdhci@c8000000 {
                 status = "okay";
-                cd-gpios = <&gpio 173 0>; /* gpio PV5 */
+                cd-gpios = <&gpio 173 1>; /* gpio PV5 */
                 wp-gpios = <&gpio 57 0>;  /* gpio PH1 */
                 power-gpios = <&gpio 169 0>; /* gpio PV1 */
                 bus-width = <4>;
@@ -447,6 +447,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         gpio-keys {
                 compatible = "gpio-keys";
 
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 37b3a57ec0f1..4ee700a33ca5 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -584,7 +584,7 @@
 
         sdhci@c8000400 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
                 power-gpios = <&gpio 70 0>; /* gpio PI6 */
                 bus-width = <4>;
@@ -595,6 +595,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         gpio-keys {
                 compatible = "gpio-keys";
 
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 4766abae7a72..c19025725918 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -465,12 +465,25 @@
         };
 
         sdhci@c8000600 {
-                cd-gpios = <&gpio 58 0>; /* gpio PH2 */
+                cd-gpios = <&gpio 58 1>; /* gpio PH2 */
                 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
                 bus-width = <4>;
                 status = "okay";
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
 
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 5d79e4fc49a6..a9f3f06580f5 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -325,11 +325,24 @@
 
         sdhci@c8000600 {
                 status = "okay";
-                cd-gpios = <&gpio 121 0>; /* gpio PP1 */
+                cd-gpios = <&gpio 121 1>; /* gpio PP1 */
                 wp-gpios = <&gpio 122 0>; /* gpio PP2 */
                 bus-width = <4>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         poweroff {
                 compatible = "gpio-poweroff";
                 gpios = <&gpio 191 1>; /* gpio PX7, active low */
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 425c89000c20..f544806e9618 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -520,7 +520,7 @@
 
         sdhci@c8000400 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
                 power-gpios = <&gpio 70 0>; /* gpio PI6 */
                 bus-width = <4>;
@@ -531,6 +531,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index ea57c0f6dcce..258cf945f515 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -510,6 +510,7 @@
 
         sdhci@c8000400 {
                 status = "okay";
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 173 0>; /* gpio PV5 */
                 bus-width = <8>;
         };
@@ -519,6 +520,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         kbc {
                 status = "okay";
                 nvidia,debounce-delay-ms = <20>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 3d3f64d2111a..fc7febc2b386 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -145,6 +145,7 @@
                               0 1 0x04
                               0 41 0x04
                               0 42 0x04>;
+                clocks = <&tegra_car 5>;
         };
 
         tegra_car: clock {
@@ -304,6 +305,7 @@
                 compatible = "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <0 2 0x04>;
+                clocks = <&tegra_car 4>;
         };
 
         i2c@7000c000 {
@@ -416,6 +418,8 @@
         pmc {
                 compatible = "nvidia,tegra20-pmc";
                 reg = <0x7000e400 0x400>;
+                clocks = <&tegra_car 110>, <&clk32k_in>;
+                clock-names = "pclk", "clk32k_in";
         };
 
         memory-controller@7000f000 {
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 8ff2ff20e4a3..6248b2445b32 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -257,7 +257,7 @@
 
         sdhci@78000000 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
                 power-gpios = <&gpio 31 0>; /* gpio PD7 */
                 bus-width = <4>;
@@ -268,6 +268,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 17499272a4ef..65bf2b63174e 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -311,7 +311,7 @@
 
         sdhci@78000000 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
                 power-gpios = <&gpio 31 0>; /* gpio PD7 */
                 bus-width = <4>;
@@ -322,6 +322,19 @@
                 bus-width = <8>;
         };
 
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index dbf46c272562..9fe7a92b4c85 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -148,6 +148,7 @@
                               0 42 0x04
                               0 121 0x04
                               0 122 0x04>;
+                clocks = <&tegra_car 5>;
         };
 
         tegra_car: clock {
@@ -291,6 +292,7 @@
                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <0 2 0x04>;
+                clocks = <&tegra_car 4>;
         };
 
         i2c@7000c000 {
@@ -423,8 +425,10 @@
         };
 
         pmc {
-                compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
+                compatible = "nvidia,tegra30-pmc";
                 reg = <0x7000e400 0x400>;
+                clocks = <&tegra_car 218>, <&clk32k_in>;
+                clock-names = "pclk", "clk32k_in";
         };
 
         memory-controller {
diff --git a/arch/arm/boot/dts/tps6507x.dtsi b/arch/arm/boot/dts/tps6507x.dtsi
new file mode 100644
index 000000000000..4c326e591e5a
--- /dev/null
+++ b/arch/arm/boot/dts/tps6507x.dtsi
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65070.pdf
+ */
+
+&tps {
+        compatible = "ti,tps6507x";
+
+        regulators {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vdcdc1_reg: regulator@0 {
+                        reg = <0>;
+                        regulator-compatible = "VDCDC1";
+                };
+
+                vdcdc2_reg: regulator@1 {
+                        reg = <1>;
+                        regulator-compatible = "VDCDC2";
+                };
+
+                vdcdc3_reg: regulator@2 {
+                        reg = <2>;
+                        regulator-compatible = "VDCDC3";
+                };
+
+                ldo1_reg: regulator@3 {
+                        reg = <3>;
+                        regulator-compatible = "LDO1";
+                };
+
+                ldo2_reg: regulator@4 {
+                        reg = <4>;
+                        regulator-compatible = "LDO2";
+                };
+
+        };
+};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index 73187173117c..9420053acc14 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -117,7 +117,7 @@
         };
 
         pmu {
-                compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
+                compatible = "arm,cortex-a15-pmu";
                 interrupts = <0 68 4>,
                              <0 69 4>;
         };
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index dfe371ec2749..d2803be4e1a8 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -134,7 +134,7 @@
         };
 
         pmu {
-                compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
+                compatible = "arm,cortex-a15-pmu";
                 interrupts = <0 68 4>,
                              <0 69 4>;
         };
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index 6328cbc71d30..c544a5504591 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -111,7 +111,7 @@
         };
 
         pmu {
-                compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu";
+                compatible = "arm,cortex-a5-pmu";
                 interrupts = <0 68 4>,
                              <0 69 4>;
         };
diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts
index 567cf4e8ab84..877b33afa7ed 100644
--- a/arch/arm/boot/dts/vt8500-bv07.dts
+++ b/arch/arm/boot/dts/vt8500-bv07.dts
@@ -11,26 +11,22 @@
 
 / {
         model = "Benign BV07 Netbook";
+};
 
-        /*
-         * Display node is based on Sascha Hauer's patch on dri-devel.
-         * Added a bpp property to calculate the size of the framebuffer
-         * until the binding is formalized.
-         */
-        display: display@0 {
-                modes {
-                        mode0: mode@0 {
-                                hactive = <800>;
-                                vactive = <480>;
-                                hback-porch = <88>;
-                                hfront-porch = <40>;
-                                hsync-len = <0>;
-                                vback-porch = <32>;
-                                vfront-porch = <11>;
-                                vsync-len = <1>;
-                                clock = <0>;    /* unused but required */
-                                bpp = <16>;     /* non-standard but required */
-                        };
+&fb {
+        bits-per-pixel = <16>;
+        display-timings {
+                native-mode = <&timing0>;
+                timing0: 800x480 {
+                        clock-frequency = <0>; /* unused but required */
+                        hactive = <800>;
+                        vactive = <480>;
+                        hfront-porch = <40>;
+                        hback-porch = <88>;
+                        hsync-len = <0>;
+                        vback-porch = <32>;
+                        vfront-porch = <11>;
+                        vsync-len = <1>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
index cf31ced46602..4a4b96f6827e 100644
--- a/arch/arm/boot/dts/vt8500.dtsi
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -25,11 +25,13 @@
                         #interrupt-cells = <1>;
                 };
 
-                gpio: gpio-controller@d8110000 {
-                        compatible = "via,vt8500-gpio";
-                        gpio-controller;
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "via,vt8500-pinctrl";
                         reg = <0xd8110000 0x10000>;
-                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
                 };
 
                 pmc@d8130000 {
@@ -98,12 +100,10 @@
                         interrupts = <43>;
                 };
 
-                fb@d800e400 {
+                fb: fb@d8050800 {
                         compatible = "via,vt8500-fb";
                         reg = <0xd800e400 0x400>;
                         interrupts = <12>;
-                        display = <&display>;
-                        default-mode = <&mode0>;
                 };
 
                 ge_rops@d8050400 {
diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts
index fd4e248074c6..edd2cec3d37f 100644
--- a/arch/arm/boot/dts/wm8505-ref.dts
+++ b/arch/arm/boot/dts/wm8505-ref.dts
@@ -11,26 +11,22 @@
 
 / {
         model = "Wondermedia WM8505 Netbook";
+};
 
-        /*
-         * Display node is based on Sascha Hauer's patch on dri-devel.
-         * Added a bpp property to calculate the size of the framebuffer
-         * until the binding is formalized.
-         */
-        display: display@0 {
-                modes {
-                        mode0: mode@0 {
-                                hactive = <800>;
-                                vactive = <480>;
-                                hback-porch = <88>;
-                                hfront-porch = <40>;
-                                hsync-len = <0>;
-                                vback-porch = <32>;
-                                vfront-porch = <11>;
-                                vsync-len = <1>;
-                                clock = <0>;    /* unused but required */
-                                bpp = <32>;     /* non-standard but required */
-                        };
+&fb {
+        bits-per-pixel = <32>;
+        display-timings {
+                native-mode = <&timing0>;
+                timing0: 800x480 {
+                        clock-frequency = <0>; /* unused but required */
+                        hactive = <800>;
+                        vactive = <480>;
+                        hfront-porch = <40>;
+                        hback-porch = <88>;
+                        hsync-len = <0>;
+                        vback-porch = <32>;
+                        vfront-porch = <11>;
+                        vsync-len = <1>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
index e74a1c0fb9a2..b2bf359e852f 100644
--- a/arch/arm/boot/dts/wm8505.dtsi
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -40,11 +40,13 @@
                         interrupts = <56 57 58 59 60 61 62 63>;
                 };
 
-                gpio: gpio-controller@d8110000 {
-                        compatible = "wm,wm8505-gpio";
-                        gpio-controller;
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "wm,wm8505-pinctrl";
                         reg = <0xd8110000 0x10000>;
-                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
                 };
 
                 pmc@d8130000 {
@@ -60,6 +62,19 @@
                                         clock-frequency = <24000000>;
                                 };
 
+                                ref25: ref25M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <25000000>;
+                                };
+
+                                pllb: pllb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x204>;
+                                };
+
                                 clkuart0: uart0 {
                                         #clock-cells = <0>;
                                         compatible = "via,vt8500-device-clock";
@@ -107,6 +122,16 @@
                                         enable-reg = <0x250>;
                                         enable-bit = <23>;
                                 };
+
+                                clksdhc: sdhc {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x328>;
+                                        divisor-mask = <0x3f>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <18>;
+                                };
                         };
                 };
 
@@ -128,11 +153,9 @@
                         interrupts = <0>;
                 };
 
-                fb@d8050800 {
+                fb: fb@d8050800 {
                         compatible = "wm,wm8505-fb";
                         reg = <0xd8050800 0x200>;
-                        display = <&display>;
-                        default-mode = <&mode0>;
                 };
 
                 ge_rops@d8050400 {
@@ -187,5 +210,13 @@
                         reg = <0xd8100000 0x10000>;
                         interrupts = <48>;
                 };
+
+                sdhc@d800a000 {
+                        compatible = "wm,wm8505-sdhc";
+                        reg = <0xd800a000 0x1000>;
+                        interrupts = <20 21>;
+                        clocks = <&clksdhc>;
+                        bus-width = <4>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts
index cefd938f842f..61671a0d9ede 100644
--- a/arch/arm/boot/dts/wm8650-mid.dts
+++ b/arch/arm/boot/dts/wm8650-mid.dts
@@ -11,26 +11,24 @@
 
 / {
         model = "Wondermedia WM8650-MID Tablet";
+};
+
+&fb {
+        bits-per-pixel = <16>;
 
-        /*
-         * Display node is based on Sascha Hauer's patch on dri-devel.
-         * Added a bpp property to calculate the size of the framebuffer
-         * until the binding is formalized.
-         */
-        display: display@0 {
-                modes {
-                        mode0: mode@0 {
-                                hactive = <800>;
-                                vactive = <480>;
-                                hback-porch = <88>;
-                                hfront-porch = <40>;
-                                hsync-len = <0>;
-                                vback-porch = <32>;
-                                vfront-porch = <11>;
-                                vsync-len = <1>;
-                                clock = <0>;    /* unused but required */
-                                bpp = <16>;     /* non-standard but required */
-                        };
+        display-timings {
+                native-mode = <&timing0>;
+                timing0: 800x480 {
+                        clock-frequency = <0>; /* unused but required */
+                        hactive = <800>;
+                        vactive = <480>;
+                        hfront-porch = <40>;
+                        hback-porch = <88>;
+                        hsync-len = <0>;
+                        vback-porch = <32>;
+                        vfront-porch = <11>;
+                        vsync-len = <1>;
                 };
         };
 };
+
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
index db3c0a12e052..dd8464eeb40d 100644
--- a/arch/arm/boot/dts/wm8650.dtsi
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -34,11 +34,13 @@
                         interrupts = <56 57 58 59 60 61 62 63>;
                 };
 
-                gpio: gpio-controller@d8110000 {
-                        compatible = "wm,wm8650-gpio";
-                        gpio-controller;
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "wm,wm8650-pinctrl";
                         reg = <0xd8110000 0x10000>;
-                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
                 };
 
                 pmc@d8130000 {
@@ -128,11 +130,9 @@
                         interrupts = <43>;
                 };
 
-                fb@d8050800 {
+                fb: fb@d8050800 {
                         compatible = "wm,wm8505-fb";
                         reg = <0xd8050800 0x200>;
-                        display = <&display>;
-                        default-mode = <&mode0>;
                 };
 
                 ge_rops@d8050400 {
diff --git a/arch/arm/boot/dts/wm8850-w70v2.dts b/arch/arm/boot/dts/wm8850-w70v2.dts
index fcc660c89540..32d22532cd6c 100644
--- a/arch/arm/boot/dts/wm8850-w70v2.dts
+++ b/arch/arm/boot/dts/wm8850-w70v2.dts
@@ -15,28 +15,6 @@
 / {
         model = "Wondermedia WM8850-W70v2 Tablet";
 
-        /*
-         * Display node is based on Sascha Hauer's patch on dri-devel.
-         * Added a bpp property to calculate the size of the framebuffer
-         * until the binding is formalized.
-         */
-        display: display@0 {
-                modes {
-                        mode0: mode@0 {
-                                hactive = <800>;
-                                vactive = <480>;
-                                hback-porch = <88>;
-                                hfront-porch = <40>;
-                                hsync-len = <0>;
-                                vback-porch = <32>;
-                                vfront-porch = <11>;
-                                vsync-len = <1>;
-                                clock = <0>;    /* unused but required */
-                                bpp = <16>;     /* non-standard but required */
-                        };
-                };
-        };
-
         backlight {
                 compatible = "pwm-backlight";
                 pwms = <&pwm 0 50000 1>;        /* duty inverted */
@@ -45,3 +23,21 @@
                 default-brightness-level = <5>;
         };
 };
+
+&fb {
+        bits-per-pixel = <16>;
+        display-timings {
+                native-mode = <&timing0>;
+                timing0: 800x480 {
+                        clock-frequency = <0>; /* unused but required */
+                        hactive = <800>;
+                        vactive = <480>;
+                        hfront-porch = <40>;
+                        hback-porch = <88>;
+                        hsync-len = <0>;
+                        vback-porch = <32>;
+                        vfront-porch = <11>;
+                        vsync-len = <1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi
index e8cbfdc87bba..fc790d0aee66 100644
--- a/arch/arm/boot/dts/wm8850.dtsi
+++ b/arch/arm/boot/dts/wm8850.dtsi
@@ -41,11 +41,13 @@
                         interrupts = <56 57 58 59 60 61 62 63>;
                 };
 
-                gpio: gpio-controller@d8110000 {
-                        compatible = "wm,wm8650-gpio";
-                        gpio-controller;
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "wm,wm8850-pinctrl";
                         reg = <0xd8110000 0x10000>;
-                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
                 };
 
                 pmc@d8130000 {
@@ -135,11 +137,9 @@
                         };
                 };
 
-                fb@d8051700 {
+                fb: fb@d8051700 {
                         compatible = "wm,wm8505-fb";
                         reg = <0xd8051700 0x200>;
-                        display = <&display>;
-                        default-mode = <&mode0>;
                 };
 
                 ge_rops@d8050400 {
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 5914b5654591..748fc347ed18 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -15,6 +15,13 @@
 / {
         compatible = "xlnx,zynq-7000";
 
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts = <0 5 4>, <0 6 4>;
+                interrupt-parent = <&intc>;
+                reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
+        };
+
         amba {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -111,56 +118,23 @@
                 };
 
                 ttc0: ttc0@f8001000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "xlnx,ttc";
+                        interrupt-parent = <&intc>;
+                        interrupts = < 0 10 4 0 11 4 0 12 4 >;
+                        compatible = "cdns,ttc";
                         reg = <0xF8001000 0x1000>;
                         clocks = <&cpu_clk 3>;
                         clock-names = "cpu_1x";
                         clock-ranges;
-
-                        ttc0_0: ttc0.0 {
-                                status = "disabled";
-                                reg = <0>;
-                                interrupts = <0 10 4>;
-                        };
-                        ttc0_1: ttc0.1 {
-                                status = "disabled";
-                                reg = <1>;
-                                interrupts = <0 11 4>;
-                        };
-                        ttc0_2: ttc0.2 {
-                                status = "disabled";
-                                reg = <2>;
-                                interrupts = <0 12 4>;
-                        };
                 };
 
                 ttc1: ttc1@f8002000 {
-                        #interrupt-parent = <&intc>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "xlnx,ttc";
+                        interrupt-parent = <&intc>;
+                        interrupts = < 0 37 4 0 38 4 0 39 4 >;
+                        compatible = "cdns,ttc";
                         reg = <0xF8002000 0x1000>;
                         clocks = <&cpu_clk 3>;
                         clock-names = "cpu_1x";
                         clock-ranges;
-
-                        ttc1_0: ttc1.0 {
-                                status = "disabled";
-                                reg = <0>;
-                                interrupts = <0 37 4>;
-                        };
-                        ttc1_1: ttc1.1 {
-                                status = "disabled";
-                                reg = <1>;
-                                interrupts = <0 38 4>;
-                        };
-                        ttc1_2: ttc1.2 {
-                                status = "disabled";
-                                reg = <2>;
-                                interrupts = <0 39 4>;
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index c772942a399a..86f44d5b0265 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -32,13 +32,3 @@
 &ps_clk {
         clock-frequency = <33333330>;
 };
-
-&ttc0_0 {
-        status = "ok";
-        compatible = "xlnx,ttc-counter-clocksource";
-};
-
-&ttc0_1 {
-        status = "ok";
-        compatible = "xlnx,ttc-counter-clockevent";
-};
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index dc8dd0de5c0f..48434cbe3e89 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -2,6 +2,8 @@
 # Makefile for the linux kernel.
 #
 
+obj-y                           += firmware.o
+
 obj-$(CONFIG_ICST)              += icst.o
 obj-$(CONFIG_SA1111)            += sa1111.o
 obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o
@@ -11,3 +13,6 @@ obj-$(CONFIG_SHARP_PARAM)	+= sharpsl_param.o
 obj-$(CONFIG_SHARP_SCOOP)       += scoop.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
 obj-$(CONFIG_ARM_TIMER_SP804)   += timer-sp.o
+obj-$(CONFIG_MCPM)              += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
+AFLAGS_mcpm_head.o              := -march=armv7-a
+AFLAGS_vlock.o                  := -march=armv7-a
diff --git a/arch/arm/common/firmware.c b/arch/arm/common/firmware.c
new file mode 100644
index 000000000000..27ddccb1131f
--- /dev/null
+++ b/arch/arm/common/firmware.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics.
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Tomasz Figa <t.figa@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+
+#include <asm/firmware.h>
+
+static const struct firmware_ops default_firmware_ops;
+
+const struct firmware_ops *firmware_ops = &default_firmware_ops;
diff --git a/arch/arm/common/mcpm_entry.c b/arch/arm/common/mcpm_entry.c
new file mode 100644
index 000000000000..370236dd1a03
--- /dev/null
+++ b/arch/arm/common/mcpm_entry.c
@@ -0,0 +1,263 @@
+/*
+ * arch/arm/common/mcpm_entry.c -- entry point for multi-cluster PM
+ *
+ * Created by:  Nicolas Pitre, March 2012
+ * Copyright:   (C) 2012-2013  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irqflags.h>
+
+#include <asm/mcpm.h>
+#include <asm/cacheflush.h>
+#include <asm/idmap.h>
+#include <asm/cputype.h>
+
+extern unsigned long mcpm_entry_vectors[MAX_NR_CLUSTERS][MAX_CPUS_PER_CLUSTER];
+
+void mcpm_set_entry_vector(unsigned cpu, unsigned cluster, void *ptr)
+{
+        unsigned long val = ptr ? virt_to_phys(ptr) : 0;
+        mcpm_entry_vectors[cluster][cpu] = val;
+        sync_cache_w(&mcpm_entry_vectors[cluster][cpu]);
+}
+
+static const struct mcpm_platform_ops *platform_ops;
+
+int __init mcpm_platform_register(const struct mcpm_platform_ops *ops)
+{
+        if (platform_ops)
+                return -EBUSY;
+        platform_ops = ops;
+        return 0;
+}
+
+int mcpm_cpu_power_up(unsigned int cpu, unsigned int cluster)
+{
+        if (!platform_ops)
+                return -EUNATCH; /* try not to shadow power_up errors */
+        might_sleep();
+        return platform_ops->power_up(cpu, cluster);
+}
+
+typedef void (*phys_reset_t)(unsigned long);
+
+void mcpm_cpu_power_down(void)
+{
+        phys_reset_t phys_reset;
+
+        BUG_ON(!platform_ops);
+        BUG_ON(!irqs_disabled());
+
+        /*
+         * Do this before calling into the power_down method,
+         * as it might not always be safe to do afterwards.
+         */
+        setup_mm_for_reboot();
+
+        platform_ops->power_down();
+
+        /*
+         * It is possible for a power_up request to happen concurrently
+         * with a power_down request for the same CPU. In this case the
+         * power_down method might not be able to actually enter a
+         * powered down state with the WFI instruction if the power_up
+         * method has removed the required reset condition.  The
+         * power_down method is then allowed to return. We must perform
+         * a re-entry in the kernel as if the power_up method just had
+         * deasserted reset on the CPU.
+         *
+         * To simplify race issues, the platform specific implementation
+         * must accommodate for the possibility of unordered calls to
+         * power_down and power_up with a usage count. Therefore, if a
+         * call to power_up is issued for a CPU that is not down, then
+         * the next call to power_down must not attempt a full shutdown
+         * but only do the minimum (normally disabling L1 cache and CPU
+         * coherency) and return just as if a concurrent power_up request
+         * had happened as described above.
+         */
+
+        phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
+        phys_reset(virt_to_phys(mcpm_entry_point));
+
+        /* should never get here */
+        BUG();
+}
+
+void mcpm_cpu_suspend(u64 expected_residency)
+{
+        phys_reset_t phys_reset;
+
+        BUG_ON(!platform_ops);
+        BUG_ON(!irqs_disabled());
+
+        /* Very similar to mcpm_cpu_power_down() */
+        setup_mm_for_reboot();
+        platform_ops->suspend(expected_residency);
+        phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
+        phys_reset(virt_to_phys(mcpm_entry_point));
+        BUG();
+}
+
+int mcpm_cpu_powered_up(void)
+{
+        if (!platform_ops)
+                return -EUNATCH;
+        if (platform_ops->powered_up)
+                platform_ops->powered_up();
+        return 0;
+}
+
+struct sync_struct mcpm_sync;
+
+/*
+ * __mcpm_cpu_going_down: Indicates that the cpu is being torn down.
+ *    This must be called at the point of committing to teardown of a CPU.
+ *    The CPU cache (SCTRL.C bit) is expected to still be active.
+ */
+void __mcpm_cpu_going_down(unsigned int cpu, unsigned int cluster)
+{
+        mcpm_sync.clusters[cluster].cpus[cpu].cpu = CPU_GOING_DOWN;
+        sync_cache_w(&mcpm_sync.clusters[cluster].cpus[cpu].cpu);
+}
+
+/*
+ * __mcpm_cpu_down: Indicates that cpu teardown is complete and that the
+ *    cluster can be torn down without disrupting this CPU.
+ *    To avoid deadlocks, this must be called before a CPU is powered down.
+ *    The CPU cache (SCTRL.C bit) is expected to be off.
+ *    However L2 cache might or might not be active.
+ */
+void __mcpm_cpu_down(unsigned int cpu, unsigned int cluster)
+{
+        dmb();
+        mcpm_sync.clusters[cluster].cpus[cpu].cpu = CPU_DOWN;
+        sync_cache_w(&mcpm_sync.clusters[cluster].cpus[cpu].cpu);
+        dsb_sev();
+}
+
+/*
+ * __mcpm_outbound_leave_critical: Leave the cluster teardown critical section.
+ * @state: the final state of the cluster:
+ *     CLUSTER_UP: no destructive teardown was done and the cluster has been
+ *         restored to the previous state (CPU cache still active); or
+ *     CLUSTER_DOWN: the cluster has been torn-down, ready for power-off
+ *         (CPU cache disabled, L2 cache either enabled or disabled).
+ */
+void __mcpm_outbound_leave_critical(unsigned int cluster, int state)
+{
+        dmb();
+        mcpm_sync.clusters[cluster].cluster = state;
+        sync_cache_w(&mcpm_sync.clusters[cluster].cluster);
+        dsb_sev();
+}
+
+/*
+ * __mcpm_outbound_enter_critical: Enter the cluster teardown critical section.
+ * This function should be called by the last man, after local CPU teardown
+ * is complete.  CPU cache expected to be active.
+ *
+ * Returns:
+ *     false: the critical section was not entered because an inbound CPU was
+ *         observed, or the cluster is already being set up;
+ *     true: the critical section was entered: it is now safe to tear down the
+ *         cluster.
+ */
+bool __mcpm_outbound_enter_critical(unsigned int cpu, unsigned int cluster)
+{
+        unsigned int i;
+        struct mcpm_sync_struct *c = &mcpm_sync.clusters[cluster];
+
+        /* Warn inbound CPUs that the cluster is being torn down: */
+        c->cluster = CLUSTER_GOING_DOWN;
+        sync_cache_w(&c->cluster);
+
+        /* Back out if the inbound cluster is already in the critical region: */
+        sync_cache_r(&c->inbound);
+        if (c->inbound == INBOUND_COMING_UP)
+                goto abort;
+
+        /*
+         * Wait for all CPUs to get out of the GOING_DOWN state, so that local
+         * teardown is complete on each CPU before tearing down the cluster.
+         *
+         * If any CPU has been woken up again from the DOWN state, then we
+         * shouldn't be taking the cluster down at all: abort in that case.
+         */
+        sync_cache_r(&c->cpus);
+        for (i = 0; i < MAX_CPUS_PER_CLUSTER; i++) {
+                int cpustate;
+
+                if (i == cpu)
+                        continue;
+
+                while (1) {
+                        cpustate = c->cpus[i].cpu;
+                        if (cpustate != CPU_GOING_DOWN)
+                                break;
+
+                        wfe();
+                        sync_cache_r(&c->cpus[i].cpu);
+                }
+
+                switch (cpustate) {
+                case CPU_DOWN:
+                        continue;
+
+                default:
+                        goto abort;
+                }
+        }
+
+        return true;
+
+abort:
+        __mcpm_outbound_leave_critical(cluster, CLUSTER_UP);
+        return false;
+}
+
+int __mcpm_cluster_state(unsigned int cluster)
+{
+        sync_cache_r(&mcpm_sync.clusters[cluster].cluster);
+        return mcpm_sync.clusters[cluster].cluster;
+}
+
+extern unsigned long mcpm_power_up_setup_phys;
+
+int __init mcpm_sync_init(
+        void (*power_up_setup)(unsigned int affinity_level))
+{
+        unsigned int i, j, mpidr, this_cluster;
+
+        BUILD_BUG_ON(MCPM_SYNC_CLUSTER_SIZE * MAX_NR_CLUSTERS != sizeof mcpm_sync);
+        BUG_ON((unsigned long)&mcpm_sync & (__CACHE_WRITEBACK_GRANULE - 1));
+
+        /*
+         * Set initial CPU and cluster states.
+         * Only one cluster is assumed to be active at this point.
+         */
+        for (i = 0; i < MAX_NR_CLUSTERS; i++) {
+                mcpm_sync.clusters[i].cluster = CLUSTER_DOWN;
+                mcpm_sync.clusters[i].inbound = INBOUND_NOT_COMING_UP;
+                for (j = 0; j < MAX_CPUS_PER_CLUSTER; j++)
+                        mcpm_sync.clusters[i].cpus[j].cpu = CPU_DOWN;
+        }
+        mpidr = read_cpuid_mpidr();
+        this_cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+        for_each_online_cpu(i)
+                mcpm_sync.clusters[this_cluster].cpus[i].cpu = CPU_UP;
+        mcpm_sync.clusters[this_cluster].cluster = CLUSTER_UP;
+        sync_cache_w(&mcpm_sync);
+
+        if (power_up_setup) {
+                mcpm_power_up_setup_phys = virt_to_phys(power_up_setup);
+                sync_cache_w(&mcpm_power_up_setup_phys);
+        }
+
+        return 0;
+}
diff --git a/arch/arm/common/mcpm_head.S b/arch/arm/common/mcpm_head.S
new file mode 100644
index 000000000000..8178705c4b24
--- /dev/null
+++ b/arch/arm/common/mcpm_head.S
@@ -0,0 +1,219 @@
+/*
+ * arch/arm/common/mcpm_head.S -- kernel entry point for multi-cluster PM
+ *
+ * Created by:  Nicolas Pitre, March 2012
+ * Copyright:   (C) 2012-2013  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ * Refer to Documentation/arm/cluster-pm-race-avoidance.txt
+ * for details of the synchronisation algorithms used here.
+ */
+
+#include <linux/linkage.h>
+#include <asm/mcpm.h>
+
+#include "vlock.h"
+
+.if MCPM_SYNC_CLUSTER_CPUS
+.error "cpus must be the first member of struct mcpm_sync_struct"
+.endif
+
+        .macro  pr_dbg  string
+#if defined(CONFIG_DEBUG_LL) && defined(DEBUG)
+        b       1901f
+1902:   .asciz  "CPU"
+1903:   .asciz  " cluster"
+1904:   .asciz  ": \string"
+        .align
+1901:   adr     r0, 1902b
+        bl      printascii
+        mov     r0, r9
+        bl      printhex8
+        adr     r0, 1903b
+        bl      printascii
+        mov     r0, r10
+        bl      printhex8
+        adr     r0, 1904b
+        bl      printascii
+#endif
+        .endm
+
+        .arm
+        .align
+
+ENTRY(mcpm_entry_point)
+
+ THUMB( adr     r12, BSYM(1f)   )
+ THUMB( bx      r12             )
+ THUMB( .thumb                  )
+1:
+        mrc     p15, 0, r0, c0, c0, 5           @ MPIDR
+        ubfx    r9, r0, #0, #8                  @ r9 = cpu
+        ubfx    r10, r0, #8, #8                 @ r10 = cluster
+        mov     r3, #MAX_CPUS_PER_CLUSTER
+        mla     r4, r3, r10, r9                 @ r4 = canonical CPU index
+        cmp     r4, #(MAX_CPUS_PER_CLUSTER * MAX_NR_CLUSTERS)
+        blo     2f
+
+        /* We didn't expect this CPU.  Try to cheaply make it quiet. */
+1:      wfi
+        wfe
+        b       1b
+
+2:      pr_dbg  "kernel mcpm_entry_point\n"
+
+        /*
+         * MMU is off so we need to get to various variables in a
+         * position independent way.
+         */
+        adr     r5, 3f
+        ldmia   r5, {r6, r7, r8, r11}
+        add     r6, r5, r6                      @ r6 = mcpm_entry_vectors
+        ldr     r7, [r5, r7]                    @ r7 = mcpm_power_up_setup_phys
+        add     r8, r5, r8                      @ r8 = mcpm_sync
+        add     r11, r5, r11                    @ r11 = first_man_locks
+
+        mov     r0, #MCPM_SYNC_CLUSTER_SIZE
+        mla     r8, r0, r10, r8                 @ r8 = sync cluster base
+
+        @ Signal that this CPU is coming UP:
+        mov     r0, #CPU_COMING_UP
+        mov     r5, #MCPM_SYNC_CPU_SIZE
+        mla     r5, r9, r5, r8                  @ r5 = sync cpu address
+        strb    r0, [r5]
+
+        @ At this point, the cluster cannot unexpectedly enter the GOING_DOWN
+        @ state, because there is at least one active CPU (this CPU).
+
+        mov     r0, #VLOCK_SIZE
+        mla     r11, r0, r10, r11               @ r11 = cluster first man lock
+        mov     r0, r11
+        mov     r1, r9                          @ cpu
+        bl      vlock_trylock                   @ implies DMB
+
+        cmp     r0, #0                          @ failed to get the lock?
+        bne     mcpm_setup_wait         @ wait for cluster setup if so
+
+        ldrb    r0, [r8, #MCPM_SYNC_CLUSTER_CLUSTER]
+        cmp     r0, #CLUSTER_UP                 @ cluster already up?
+        bne     mcpm_setup                      @ if not, set up the cluster
+
+        @ Otherwise, release the first man lock and skip setup:
+        mov     r0, r11
+        bl      vlock_unlock
+        b       mcpm_setup_complete
+
+mcpm_setup:
+        @ Control dependency implies strb not observable before previous ldrb.
+
+        @ Signal that the cluster is being brought up:
+        mov     r0, #INBOUND_COMING_UP
+        strb    r0, [r8, #MCPM_SYNC_CLUSTER_INBOUND]
+        dmb
+
+        @ Any CPU trying to take the cluster into CLUSTER_GOING_DOWN from this
+        @ point onwards will observe INBOUND_COMING_UP and abort.
+
+        @ Wait for any previously-pending cluster teardown operations to abort
+        @ or complete:
+mcpm_teardown_wait:
+        ldrb    r0, [r8, #MCPM_SYNC_CLUSTER_CLUSTER]
+        cmp     r0, #CLUSTER_GOING_DOWN
+        bne     first_man_setup
+        wfe
+        b       mcpm_teardown_wait
+
+first_man_setup:
+        dmb
+
+        @ If the outbound gave up before teardown started, skip cluster setup:
+
+        cmp     r0, #CLUSTER_UP
+        beq     mcpm_setup_leave
+
+        @ power_up_setup is now responsible for setting up the cluster:
+
+        cmp     r7, #0
+        mov     r0, #1          @ second (cluster) affinity level
+        blxne   r7              @ Call power_up_setup if defined
+        dmb
+
+        mov     r0, #CLUSTER_UP
+        strb    r0, [r8, #MCPM_SYNC_CLUSTER_CLUSTER]
+        dmb
+
+mcpm_setup_leave:
+        @ Leave the cluster setup critical section:
+
+        mov     r0, #INBOUND_NOT_COMING_UP
+        strb    r0, [r8, #MCPM_SYNC_CLUSTER_INBOUND]
+        dsb
+        sev
+
+        mov     r0, r11
+        bl      vlock_unlock    @ implies DMB
+        b       mcpm_setup_complete
+
+        @ In the contended case, non-first men wait here for cluster setup
+        @ to complete:
+mcpm_setup_wait:
+        ldrb    r0, [r8, #MCPM_SYNC_CLUSTER_CLUSTER]
+        cmp     r0, #CLUSTER_UP
+        wfene
+        bne     mcpm_setup_wait
+        dmb
+
+mcpm_setup_complete:
+        @ If a platform-specific CPU setup hook is needed, it is
+        @ called from here.
+
+        cmp     r7, #0
+        mov     r0, #0          @ first (CPU) affinity level
+        blxne   r7              @ Call power_up_setup if defined
+        dmb
+
+        @ Mark the CPU as up:
+
+        mov     r0, #CPU_UP
+        strb    r0, [r5]
+
+        @ Observability order of CPU_UP and opening of the gate does not matter.
+
+mcpm_entry_gated:
+        ldr     r5, [r6, r4, lsl #2]            @ r5 = CPU entry vector
+        cmp     r5, #0
+        wfeeq
+        beq     mcpm_entry_gated
+        dmb
+
+        pr_dbg  "released\n"
+        bx      r5
+
+        .align  2
+
+3:      .word   mcpm_entry_vectors - .
+        .word   mcpm_power_up_setup_phys - 3b
+        .word   mcpm_sync - 3b
+        .word   first_man_locks - 3b
+
+ENDPROC(mcpm_entry_point)
+
+        .bss
+
+        .align  CACHE_WRITEBACK_ORDER
+        .type   first_man_locks, #object
+first_man_locks:
+        .space  VLOCK_SIZE * MAX_NR_CLUSTERS
+        .align  CACHE_WRITEBACK_ORDER
+
+        .type   mcpm_entry_vectors, #object
+ENTRY(mcpm_entry_vectors)
+        .space  4 * MAX_NR_CLUSTERS * MAX_CPUS_PER_CLUSTER
+
+        .type   mcpm_power_up_setup_phys, #object
+ENTRY(mcpm_power_up_setup_phys)
+        .space  4               @ set by mcpm_sync_init()
diff --git a/arch/arm/common/mcpm_platsmp.c b/arch/arm/common/mcpm_platsmp.c
new file mode 100644
index 000000000000..52b88d81b7bb
--- /dev/null
+++ b/arch/arm/common/mcpm_platsmp.c
@@ -0,0 +1,92 @@
+/*
+ * linux/arch/arm/mach-vexpress/mcpm_platsmp.c
+ *
+ * Created by:  Nicolas Pitre, November 2012
+ * Copyright:   (C) 2012-2013  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Code to handle secondary CPU bringup and hotplug for the cluster power API.
+ */
+
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/spinlock.h>
+
+#include <linux/irqchip/arm-gic.h>
+
+#include <asm/mcpm.h>
+#include <asm/smp.h>
+#include <asm/smp_plat.h>
+
+static void __init simple_smp_init_cpus(void)
+{
+}
+
+static int __cpuinit mcpm_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        unsigned int mpidr, pcpu, pcluster, ret;
+        extern void secondary_startup(void);
+
+        mpidr = cpu_logical_map(cpu);
+        pcpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        pcluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+        pr_debug("%s: logical CPU %d is physical CPU %d cluster %d\n",
+                 __func__, cpu, pcpu, pcluster);
+
+        mcpm_set_entry_vector(pcpu, pcluster, NULL);
+        ret = mcpm_cpu_power_up(pcpu, pcluster);
+        if (ret)
+                return ret;
+        mcpm_set_entry_vector(pcpu, pcluster, secondary_startup);
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+        dsb_sev();
+        return 0;
+}
+
+static void __cpuinit mcpm_secondary_init(unsigned int cpu)
+{
+        mcpm_cpu_powered_up();
+        gic_secondary_init(0);
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+
+static int mcpm_cpu_disable(unsigned int cpu)
+{
+        /*
+         * We assume all CPUs may be shut down.
+         * This would be the hook to use for eventual Secure
+         * OS migration requests as described in the PSCI spec.
+         */
+        return 0;
+}
+
+static void mcpm_cpu_die(unsigned int cpu)
+{
+        unsigned int mpidr, pcpu, pcluster;
+        mpidr = read_cpuid_mpidr();
+        pcpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        pcluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+        mcpm_set_entry_vector(pcpu, pcluster, NULL);
+        mcpm_cpu_power_down();
+}
+
+#endif
+
+static struct smp_operations __initdata mcpm_smp_ops = {
+        .smp_init_cpus          = simple_smp_init_cpus,
+        .smp_boot_secondary     = mcpm_boot_secondary,
+        .smp_secondary_init     = mcpm_secondary_init,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_disable            = mcpm_cpu_disable,
+        .cpu_die                = mcpm_cpu_die,
+#endif
+};
+
+void __init mcpm_smp_set_ops(void)
+{
+        smp_set_ops(&mcpm_smp_ops);
+}
diff --git a/arch/arm/common/vlock.S b/arch/arm/common/vlock.S
new file mode 100644
index 000000000000..ff198583f683
--- /dev/null
+++ b/arch/arm/common/vlock.S
@@ -0,0 +1,108 @@
+/*
+ * vlock.S - simple voting lock implementation for ARM
+ *
+ * Created by:  Dave Martin, 2012-08-16
+ * Copyright:   (C) 2012-2013  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *
+ * This algorithm is described in more detail in
+ * Documentation/arm/vlocks.txt.
+ */
+
+#include <linux/linkage.h>
+#include "vlock.h"
+
+/* Select different code if voting flags  can fit in a single word. */
+#if VLOCK_VOTING_SIZE > 4
+#define FEW(x...)
+#define MANY(x...) x
+#else
+#define FEW(x...) x
+#define MANY(x...)
+#endif
+
+@ voting lock for first-man coordination
+
+.macro voting_begin rbase:req, rcpu:req, rscratch:req
+        mov     \rscratch, #1
+        strb    \rscratch, [\rbase, \rcpu]
+        dmb
+.endm
+
+.macro voting_end rbase:req, rcpu:req, rscratch:req
+        dmb
+        mov     \rscratch, #0
+        strb    \rscratch, [\rbase, \rcpu]
+        dsb
+        sev
+.endm
+
+/*
+ * The vlock structure must reside in Strongly-Ordered or Device memory.
+ * This implementation deliberately eliminates most of the barriers which
+ * would be required for other memory types, and assumes that independent
+ * writes to neighbouring locations within a cacheline do not interfere
+ * with one another.
+ */
+
+@ r0: lock structure base
+@ r1: CPU ID (0-based index within cluster)
+ENTRY(vlock_trylock)
+        add     r1, r1, #VLOCK_VOTING_OFFSET
+
+        voting_begin    r0, r1, r2
+
+        ldrb    r2, [r0, #VLOCK_OWNER_OFFSET]   @ check whether lock is held
+        cmp     r2, #VLOCK_OWNER_NONE
+        bne     trylock_fail                    @ fail if so
+
+        @ Control dependency implies strb not observable before previous ldrb.
+
+        strb    r1, [r0, #VLOCK_OWNER_OFFSET]   @ submit my vote
+
+        voting_end      r0, r1, r2              @ implies DMB
+
+        @ Wait for the current round of voting to finish:
+
+ MANY(  mov     r3, #VLOCK_VOTING_OFFSET                        )
+0:
+ MANY(  ldr     r2, [r0, r3]                                    )
+ FEW(   ldr     r2, [r0, #VLOCK_VOTING_OFFSET]                  )
+        cmp     r2, #0
+        wfene
+        bne     0b
+ MANY(  add     r3, r3, #4                                      )
+ MANY(  cmp     r3, #VLOCK_VOTING_OFFSET + VLOCK_VOTING_SIZE    )
+ MANY(  bne     0b                                              )
+
+        @ Check who won:
+
+        dmb
+        ldrb    r2, [r0, #VLOCK_OWNER_OFFSET]
+        eor     r0, r1, r2                      @ zero if I won, else nonzero
+        bx      lr
+
+trylock_fail:
+        voting_end      r0, r1, r2
+        mov     r0, #1                          @ nonzero indicates that I lost
+        bx      lr
+ENDPROC(vlock_trylock)
+
+@ r0: lock structure base
+ENTRY(vlock_unlock)
+        dmb
+        mov     r1, #VLOCK_OWNER_NONE
+        strb    r1, [r0, #VLOCK_OWNER_OFFSET]
+        dsb
+        sev
+        bx      lr
+ENDPROC(vlock_unlock)
diff --git a/arch/arm/common/vlock.h b/arch/arm/common/vlock.h
new file mode 100644
index 000000000000..3b441475a59b
--- /dev/null
+++ b/arch/arm/common/vlock.h
@@ -0,0 +1,29 @@
+/*
+ * vlock.h - simple voting lock implementation
+ *
+ * Created by:  Dave Martin, 2012-08-16
+ * Copyright:   (C) 2012-2013  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __VLOCK_H
+#define __VLOCK_H
+
+#include <asm/mcpm.h>
+
+/* Offsets and sizes are rounded to a word (4 bytes) */
+#define VLOCK_OWNER_OFFSET      0
+#define VLOCK_VOTING_OFFSET     4
+#define VLOCK_VOTING_SIZE       ((MAX_CPUS_PER_CLUSTER + 3) / 4 * 4)
+#define VLOCK_SIZE              (VLOCK_VOTING_OFFSET + VLOCK_VOTING_SIZE)
+#define VLOCK_OWNER_NONE        0
+
+#endif /* ! __VLOCK_H */
diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig
new file mode 100644
index 000000000000..dab5a7dfadc6
--- /dev/null
+++ b/arch/arm/configs/ape6evm_defconfig
@@ -0,0 +1,95 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+CONFIG_SLAB=y
+# CONFIG_BLOCK is not set
+CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_R8A73A4=y
+CONFIG_MACH_APE6EVM=y
+# CONFIG_ARM_THUMB is not set
+CONFIG_CPU_BPREDICT_DISABLE=y
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_SMP=y
+CONFIG_SCHED_MC=y
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_NR_CPUS=8
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+# CONFIG_HW_PERF_EVENTS is not set
+# CONFIG_COMPACTION is not set
+# CONFIG_CROSS_MEMORY_ATTACH is not set
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6_SIT is not set
+CONFIG_NETFILTER=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_FW_LOADER_USER_HELPER is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CADENCE is not set
+CONFIG_SMC91X=y
+CONFIG_SMSC911X=y
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=12
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_GPIO_SH_PFC=y
+CONFIG_GPIOLIB=y
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_RCAR_THERMAL=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+# CONFIG_HID is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_ROOT_NFS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_ENABLE_DEFAULT_TRACERS=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index 0b98100d2ae7..0f2d80da7378 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -20,15 +20,19 @@ CONFIG_ARCH_R8A7740=y
 CONFIG_MACH_ARMADILLO800EVA=y
 # CONFIG_SH_TIMER_TMU is not set
 CONFIG_ARM_THUMB=y
-CONFIG_CPU_BPREDICT_DISABLE=y
 CONFIG_CACHE_L2X0=y
 CONFIG_ARM_ERRATA_430973=y
 CONFIG_ARM_ERRATA_458693=y
 CONFIG_ARM_ERRATA_460075=y
+CONFIG_PL310_ERRATA_588369=y
 CONFIG_ARM_ERRATA_720789=y
+CONFIG_PL310_ERRATA_727915=y
 CONFIG_ARM_ERRATA_743622=y
 CONFIG_ARM_ERRATA_751472=y
+CONFIG_PL310_ERRATA_753970=y
 CONFIG_ARM_ERRATA_754322=y
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_ARM_ERRATA_775420=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
 CONFIG_FORCE_MAX_ZONEORDER=13
@@ -37,6 +41,7 @@ CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_KEXEC=y
 CONFIG_VFP=y
+CONFIG_NEON=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
@@ -88,6 +93,7 @@ CONFIG_I2C=y
 CONFIG_I2C_GPIO=y
 CONFIG_I2C_SH_MOBILE=y
 # CONFIG_HWMON is not set
+CONFIG_REGULATOR=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_VIDEO_DEV=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 1ea959019fcd..047f2a415309 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -20,7 +20,7 @@ CONFIG_SOC_AT91SAM9263=y
 CONFIG_SOC_AT91SAM9G45=y
 CONFIG_SOC_AT91SAM9X5=y
 CONFIG_SOC_AT91SAM9N12=y
-CONFIG_MACH_AT91SAM_DT=y
+CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AT91_TIMER_HZ=128
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/at91sam9260_defconfig b/arch/arm/configs/at91sam9260_defconfig
index 0ea5d2c97fc4..05618eb694f8 100644
--- a/arch/arm/configs/at91sam9260_defconfig
+++ b/arch/arm/configs/at91sam9260_defconfig
@@ -22,7 +22,7 @@ CONFIG_MACH_QIL_A9260=y
 CONFIG_MACH_CPU9260=y
 CONFIG_MACH_FLEXIBITY=y
 CONFIG_MACH_SNAPPER_9260=y
-CONFIG_MACH_AT91SAM_DT=y
+CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9g20_defconfig
index 3b1881033ad8..892e8287ed73 100644
--- a/arch/arm/configs/at91sam9g20_defconfig
+++ b/arch/arm/configs/at91sam9g20_defconfig
@@ -22,7 +22,7 @@ CONFIG_MACH_PCONTROL_G20=y
 CONFIG_MACH_GSIA18S=y
 CONFIG_MACH_USB_A9G20=y
 CONFIG_MACH_SNAPPER_9260=y
-CONFIG_MACH_AT91SAM_DT=y
+CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig
index 606d48f3b8f8..18964cdacd68 100644
--- a/arch/arm/configs/at91sam9g45_defconfig
+++ b/arch/arm/configs/at91sam9g45_defconfig
@@ -18,7 +18,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9G45=y
 CONFIG_MACH_AT91SAM9M10G45EK=y
-CONFIG_MACH_AT91SAM_DT=y
+CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AT91_SLOW_CLOCK=y
 CONFIG_AEABI=y
@@ -173,7 +173,6 @@ CONFIG_MMC=y
 # CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_SDIO_UART=m
 CONFIG_MMC_ATMELMCI=y
-CONFIG_MMC_ATMELMCI_DMA=y
 CONFIG_LEDS_ATMEL_PWM=y
 CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGER_TIMER=y
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index af472e4ed451..ce987211a609 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -29,6 +29,8 @@ CONFIG_EMBEDDED=y
 CONFIG_PROFILING=y
 CONFIG_OPROFILE=y
 CONFIG_JUMP_LABEL=y
+CONFIG_ARCH_MULTI_V6=y
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_BCM2835=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
@@ -59,10 +61,13 @@ CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_TTY_PRINTK=y
-# CONFIG_HW_RANDOM is not set
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_BCM2835=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_BCM2835=y
+CONFIG_SPI=y
+CONFIG_SPI_BCM2835=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
 # CONFIG_USB_SUPPORT is not set
@@ -108,9 +113,5 @@ CONFIG_TEST_KSTRTOX=y
 CONFIG_STRICT_DEVMEM=y
 CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
-# CONFIG_XZ_DEC_X86 is not set
-# CONFIG_XZ_DEC_POWERPC is not set
-# CONFIG_XZ_DEC_IA64 is not set
 # CONFIG_XZ_DEC_ARM is not set
 # CONFIG_XZ_DEC_ARMTHUMB is not set
-# CONFIG_XZ_DEC_SPARC is not set
diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig
index 313627adf46c..b1ff5cdba9a1 100644
--- a/arch/arm/configs/cns3420vb_defconfig
+++ b/arch/arm/configs/cns3420vb_defconfig
@@ -19,8 +19,11 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_IOSCHED_CFQ=m
+CONFIG_ARCH_MULTI_V6=y
+#CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_CNS3XXX=y
 CONFIG_MACH_CNS3420VB=y
+CONFIG_DEBUG_CNS3XXX=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig
index 9aaad36a1728..7c868139bdb0 100644
--- a/arch/arm/configs/da8xx_omapl_defconfig
+++ b/arch/arm/configs/da8xx_omapl_defconfig
@@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 CONFIG_MODULES=y
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index 3edc78a40b66..c86fd75e181a 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -5,6 +5,7 @@ CONFIG_POSIX_MQUEUE=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 CONFIG_MODULES=y
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
index 3fe8dae8d32d..4364eff5b01e 100644
--- a/arch/arm/configs/dove_defconfig
+++ b/arch/arm/configs/dove_defconfig
@@ -75,6 +75,8 @@ CONFIG_I2C_MV64XXX=y
 CONFIG_SPI=y
 CONFIG_SPI_ORION=y
 # CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_DOVE_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
diff --git a/arch/arm/configs/h7201_defconfig b/arch/arm/configs/h7201_defconfig
deleted file mode 100644
index bee94d29655e..000000000000
--- a/arch/arm/configs/h7201_defconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_ARCH_H720X=y
-CONFIG_ARCH_H7201=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_FPE_NWFPE=y
-CONFIG_MTD=y
-CONFIG_MTD_DEBUG=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=m
-CONFIG_EXT2_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/h7202_defconfig b/arch/arm/configs/h7202_defconfig
deleted file mode 100644
index e16d3f372e2a..000000000000
--- a/arch/arm/configs/h7202_defconfig
+++ /dev/null
@@ -1,47 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_MODULES=y
-CONFIG_ARCH_H720X=y
-CONFIG_ARCH_H7202=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,19200"
-CONFIG_FPE_NWFPE=y
-CONFIG_FPE_NWFPE_XP=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_H720X=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_USB_GADGET=m
-CONFIG_USB_ZERO=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_EXT2_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index e36b01025321..088d6c11a0fa 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -188,6 +188,7 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
 CONFIG_USB_CHIPIDEA=y
 CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_PHY=y
 CONFIG_USB_MXS_PHY=y
 CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 13482ea58b09..a1d8252e9ec7 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -10,45 +10,48 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_KIRKWOOD=y
+CONFIG_MACH_D2NET_V2=y
 CONFIG_MACH_DB88F6281_BP=y
+CONFIG_MACH_DOCKSTAR=y
+CONFIG_MACH_ESATA_SHEEVAPLUG=y
+CONFIG_MACH_GURUPLUG=y
+CONFIG_MACH_INETSPACE_V2=y
+CONFIG_MACH_MV88F6281GTW_GE=y
+CONFIG_MACH_NET2BIG_V2=y
+CONFIG_MACH_NET5BIG_V2=y
+CONFIG_MACH_NETSPACE_MAX_V2=y
+CONFIG_MACH_NETSPACE_V2=y
+CONFIG_MACH_OPENRD_BASE=y
+CONFIG_MACH_OPENRD_CLIENT=y
+CONFIG_MACH_OPENRD_ULTIMATE=y
 CONFIG_MACH_RD88F6192_NAS=y
 CONFIG_MACH_RD88F6281=y
-CONFIG_MACH_MV88F6281GTW_GE=y
 CONFIG_MACH_SHEEVAPLUG=y
-CONFIG_MACH_ESATA_SHEEVAPLUG=y
-CONFIG_MACH_GURUPLUG=y
-CONFIG_MACH_DREAMPLUG_DT=y
-CONFIG_MACH_ICONNECT_DT=y
+CONFIG_MACH_T5325=y
+CONFIG_MACH_TS219=y
+CONFIG_MACH_TS41X=y
+CONFIG_MACH_CLOUDBOX_DT=y
 CONFIG_MACH_DLINK_KIRKWOOD_DT=y
-CONFIG_MACH_IB62X0_DT=y
-CONFIG_MACH_TS219_DT=y
 CONFIG_MACH_DOCKSTAR_DT=y
+CONFIG_MACH_DREAMPLUG_DT=y
 CONFIG_MACH_GOFLEXNET_DT=y
-CONFIG_MACH_LSXL_DT=y
+CONFIG_MACH_GURUPLUG_DT=y
+CONFIG_MACH_IB62X0_DT=y
+CONFIG_MACH_ICONNECT_DT=y
+CONFIG_MACH_INETSPACE_V2_DT=y
 CONFIG_MACH_IOMEGA_IX2_200_DT=y
 CONFIG_MACH_KM_KIRKWOOD_DT=y
-CONFIG_MACH_INETSPACE_V2_DT=y
+CONFIG_MACH_LSXL_DT=y
 CONFIG_MACH_MPLCEC4_DT=y
-CONFIG_MACH_NETSPACE_V2_DT=y
-CONFIG_MACH_NETSPACE_MAX_V2_DT=y
 CONFIG_MACH_NETSPACE_LITE_V2_DT=y
+CONFIG_MACH_NETSPACE_MAX_V2_DT=y
 CONFIG_MACH_NETSPACE_MINI_V2_DT=y
+CONFIG_MACH_NETSPACE_V2_DT=y
+CONFIG_MACH_NSA310_DT=y
 CONFIG_MACH_OPENBLOCKS_A6_DT=y
+CONFIG_MACH_READYNAS_DT=y
 CONFIG_MACH_TOPKICK_DT=y
-CONFIG_MACH_TS219=y
-CONFIG_MACH_TS41X=y
-CONFIG_MACH_DOCKSTAR=y
-CONFIG_MACH_OPENRD_BASE=y
-CONFIG_MACH_OPENRD_CLIENT=y
-CONFIG_MACH_OPENRD_ULTIMATE=y
-CONFIG_MACH_NETSPACE_V2=y
-CONFIG_MACH_INETSPACE_V2=y
-CONFIG_MACH_NETSPACE_MAX_V2=y
-CONFIG_MACH_D2NET_V2=y
-CONFIG_MACH_NET2BIG_V2=y
-CONFIG_MACH_NET5BIG_V2=y
-CONFIG_MACH_T5325=y
-CONFIG_MACH_NSA310_DT=y
+CONFIG_MACH_TS219_DT=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
@@ -56,7 +59,6 @@ CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_KIRKWOOD=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -119,6 +121,8 @@ CONFIG_SPI=y
 CONFIG_SPI_ORION=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_KIRKWOOD_THERMAL=y
 CONFIG_WATCHDOG=y
 CONFIG_ORION_WATCHDOG=y
 CONFIG_HID_DRAGONRISE=y
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index 670c3b60f936..f6e585b353a4 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -33,7 +33,6 @@ CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
 CONFIG_SCHED_MC=y
-CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
 CONFIG_HIGHMEM=y
@@ -86,7 +85,6 @@ CONFIG_I2C_SH_MOBILE=y
 CONFIG_GPIO_PCF857X=y
 # CONFIG_HWMON is not set
 CONFIG_REGULATOR=y
-CONFIG_REGULATOR_DUMMY=y
 CONFIG_FB=y
 CONFIG_FB_SH_MOBILE_LCDC=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index 92386b20bd09..398a367ffce8 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -18,6 +17,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_LPC32XX=y
+CONFIG_GPIO_PCA953X=y
 CONFIG_KEYBOARD_GPIO_POLLED=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
@@ -48,6 +48,8 @@ CONFIG_IPV6=y
 CONFIG_IPV6_PRIVACY=y
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
@@ -55,7 +57,6 @@ CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_MUSEUM_IDS=y
 CONFIG_MTD_NAND_SLC_LPC32XX=y
 CONFIG_MTD_NAND_MLC_LPC32XX=y
 CONFIG_BLK_DEV_LOOP=y
@@ -70,7 +71,6 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_NETDEVICES=y
 CONFIG_MII=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
 # CONFIG_NET_VENDOR_CIRRUS is not set
 # CONFIG_NET_VENDOR_FARADAY is not set
 # CONFIG_NET_VENDOR_INTEL is not set
@@ -84,7 +84,6 @@ CONFIG_LPC_ENET=y
 # CONFIG_NET_VENDOR_STMICRO is not set
 CONFIG_SMSC_PHY=y
 # CONFIG_WLAN is not set
-CONFIG_INPUT_MATRIXKMAP=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
@@ -108,6 +107,19 @@ CONFIG_I2C_PNX=y
 CONFIG_SPI=y
 CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_EM=y
+CONFIG_GPIO_PL061=y
+CONFIG_GPIO_MAX7300=y
+CONFIG_GPIO_MAX732X=y
+CONFIG_GPIO_PCF857X=y
+CONFIG_GPIO_SX150X=y
+CONFIG_GPIO_ADP5588=y
+CONFIG_GPIO_ADNP=y
+CONFIG_GPIO_MAX7301=y
+CONFIG_GPIO_MCP23S08=y
+CONFIG_GPIO_MC33880=y
+CONFIG_GPIO_74X164=y
 CONFIG_SENSORS_DS620=y
 CONFIG_SENSORS_MAX6639=y
 CONFIG_WATCHDOG=y
@@ -134,6 +146,7 @@ CONFIG_SND_DEBUG_VERBOSE=y
 # CONFIG_SND_SPI is not set
 CONFIG_SND_SOC=y
 CONFIG_USB=y
+CONFIG_USB_PHY=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
@@ -143,6 +156,7 @@ CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
 # CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_SPI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_PCA9532=y
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
index 7594b3aff259..9fb11895b2e2 100644
--- a/arch/arm/configs/mackerel_defconfig
+++ b/arch/arm/configs/mackerel_defconfig
@@ -75,6 +75,7 @@ CONFIG_I2C=y
 CONFIG_I2C_SH_MOBILE=y
 # CONFIG_HWMON is not set
 # CONFIG_MFD_SUPPORT is not set
+CONFIG_REGULATOR=y
 CONFIG_FB=y
 CONFIG_FB_MODE_HELPERS=y
 CONFIG_FB_SH_MOBILE_LCDC=y
@@ -94,6 +95,9 @@ CONFIG_USB_RENESAS_USBHS=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_RENESAS_USBHS_UDC=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHI=y
+CONFIG_MMC_SH_MMCIF=y
 CONFIG_DMADEVICES=y
 CONFIG_SH_DMAE=y
 CONFIG_EXT2_FS=y
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index afb17d630d44..494e70aeb9e1 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -49,6 +49,10 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FW_LOADER is not set
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
+CONFIG_ATA=y
+CONFIG_ATA_SFF=y
+CONFIG_ATA_BMDMA=y
+CONFIG_SATA_RCAR=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
 # CONFIG_NET_VENDOR_FARADAY is not set
@@ -75,6 +79,7 @@ CONFIG_I2C_RCAR=y
 CONFIG_SPI=y
 CONFIG_SPI_SH_HSPI=y
 CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_RCAR=y
 # CONFIG_HWMON is not set
 CONFIG_THERMAL=y
 CONFIG_RCAR_THERMAL=y
@@ -88,6 +93,9 @@ CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_HCD_PLATFORM=y
 CONFIG_USB_EHCI_HCD_PLATFORM=y
 CONFIG_USB_STORAGE=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV_GENIRQ=y
 # CONFIG_IOMMU_SUPPORT is not set
diff --git a/arch/arm/configs/msm_defconfig b/arch/arm/configs/msm_defconfig
index 2b8f7affc1eb..690b5f9c7462 100644
--- a/arch/arm/configs/msm_defconfig
+++ b/arch/arm/configs/msm_defconfig
@@ -1,72 +1,137 @@
-CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_MSM=y
-CONFIG_MACH_HALIBUT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
+CONFIG_ARCH_MSM8X60=y
+CONFIG_ARCH_MSM8960=y
+CONFIG_SMP=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyMSM,115200n8"
-CONFIG_PM=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_CLEANCACHE=y
+CONFIG_CC_STACKPROTECTOR=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_NET=y
+CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
+# CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
+CONFIG_CFG80211=y
+CONFIG_RFKILL=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_SCSI=y
+CONFIG_SCSI_TGT=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-CONFIG_PPP=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_PHYLIB=y
+CONFIG_SLIP=y
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLIP_MODE_SLIP6=y
+CONFIG_USB_USBNET=y
+# CONFIG_USB_NET_AX8817X is not set
+# CONFIG_USB_NET_ZAURUS is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
+# CONFIG_MOUSE_PS2 is not set
+CONFIG_INPUT_JOYSTICK=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_MSM=y
 CONFIG_SERIAL_MSM_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
+CONFIG_HW_RANDOM=y
 CONFIG_I2C=y
-# CONFIG_HWMON is not set
-CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_SPI=y
+CONFIG_SSBI=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_THERMAL=y
+CONFIG_REGULATOR=y
+CONFIG_MEDIA_SUPPORT=y
 CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_TILEBLITTING=y
-CONFIG_FB_MSM=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_HID_BATTERY_STRENGTH=y
+CONFIG_USB=y
+CONFIG_USB_PHY=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_MON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MSM=y
+CONFIG_USB_ACM=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_VBUS_DRAW=500
 CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_INOTIFY=y
+CONFIG_RTC_CLASS=y
+CONFIG_STAGING=y
+CONFIG_MSM_IOMMU=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_CIFS=y
+CONFIG_PRINTK_TIME=y
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_SCHEDSTATS=y
-CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
+CONFIG_LOCKUP_DETECTOR=y
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_TIMER_STATS=y
 CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL=y
+CONFIG_DYNAMIC_DEBUG=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index e31d442343c8..2e67a272df70 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -3,13 +3,19 @@ CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
+CONFIG_ARCH_SIRF=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_ARCH_HIGHBANK=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_WM8850=y
 # CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set
 CONFIG_ARCH_ZYNQ=y
 CONFIG_ARM_ERRATA_754322=y
+CONFIG_PLAT_SPEAR=y
+CONFIG_ARCH_SPEAR13XX=y
+CONFIG_MACH_SPEAR1310=y
+CONFIG_MACH_SPEAR1340=y
 CONFIG_SMP=y
 CONFIG_ARM_ARCH_TIMER=y
 CONFIG_AEABI=y
@@ -23,6 +29,7 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
 CONFIG_SATA_HIGHBANK=y
 CONFIG_SATA_MV=y
+CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_NETDEVICES=y
 CONFIG_NET_CALXEDA_XGMAC=y
 CONFIG_SMSC911X=y
@@ -31,17 +38,26 @@ CONFIG_SERIO_AMBAKMI=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_DW=y
+CONFIG_KEYBOARD_SPEAR=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_SIRFSOC=y
+CONFIG_SERIAL_SIRFSOC_CONSOLE=y
+CONFIG_SERIAL_VT8500=y
+CONFIG_SERIAL_VT8500_CONSOLE=y
 CONFIG_IPMI_HANDLER=y
 CONFIG_IPMI_SI=y
 CONFIG_I2C=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_SIRF=y
 CONFIG_SPI=y
 CONFIG_SPI_PL022=y
+CONFIG_SPI_SIRF=y
+CONFIG_GPIO_PL061=y
 CONFIG_FB=y
 CONFIG_FB_ARMCLCD=y
+CONFIG_FB_WM8505=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_USB=y
 CONFIG_USB_ISP1760_HCD=y
@@ -50,11 +66,18 @@ CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_SPEAR=y
+CONFIG_MMC_WMT=y
 CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_EDAC_HIGHBANK_MC=y
 CONFIG_EDAC_HIGHBANK_L2=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_PL031=y
+CONFIG_RTC_DRV_VT8500=y
+CONFIG_PWM=y
+CONFIG_PWM_VT8500=y
 CONFIG_DMADEVICES=y
 CONFIG_PL330_DMA=y
+CONFIG_SIRF_DMA=y
+CONFIG_DW_DMAC=y
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 2ec8119cff73..f3e8ae001ff1 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -46,9 +46,16 @@ CONFIG_I2C_MV64XXX=y
 CONFIG_MTD=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_SERIAL_8250_DW=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
+CONFIG_THERMAL=y
+CONFIG_ARMADA_THERMAL=y
 CONFIG_USB_SUPPORT=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
@@ -65,6 +72,8 @@ CONFIG_RTC_DRV_S35390A=y
 CONFIG_RTC_DRV_MV=y
 CONFIG_DMADEVICES=y
 CONFIG_MV_XOR=y
+CONFIG_MEMORY=y
+CONFIG_MVEBU_DEVBUS=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 6a99e30f81d2..1d6d8fb7f4a1 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -22,8 +22,8 @@ CONFIG_MODVERSIONS=y
 CONFIG_BLK_DEV_INTEGRITY=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_MXS=y
-CONFIG_MACH_MXS_DT=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
@@ -75,7 +75,7 @@ CONFIG_REALTEK_PHY=y
 CONFIG_MICREL_PHY=y
 # CONFIG_WLAN is not set
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=m
+CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
@@ -99,6 +99,8 @@ CONFIG_SPI_MXS=y
 CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_STMP3XXX_RTC_WATCHDOG=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_FB=y
@@ -120,8 +122,10 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_CHIPIDEA=y
 CONFIG_USB_CHIPIDEA_HOST=y
 CONFIG_USB_STORAGE=y
+CONFIG_USB_PHY=y
 CONFIG_USB_MXS_PHY=y
 CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_MXS=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index 86cfd2959c47..b01e7632ed2e 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -1,11 +1,9 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 CONFIG_KALLSYMS_ALL=y
@@ -13,6 +11,7 @@ CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_NOMADIK=y
 CONFIG_MACH_NOMADIK_8815NHK=y
 CONFIG_PREEMPT=y
@@ -20,7 +19,6 @@ CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -32,14 +30,10 @@ CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 CONFIG_NET_IPIP=y
-CONFIG_NET_IPGRE=y
-CONFIG_NET_IPGRE_BROADCAST=y
 CONFIG_IP_MROUTE=y
 # CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
 CONFIG_BT_RFCOMM=m
 CONFIG_BT_RFCOMM_TTY=y
 CONFIG_BT_BNEP=m
@@ -53,14 +47,16 @@ CONFIG_BT_HCIVHCI=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_TESTS=m
+CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ECC_SMC=y
+CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_FSMC=y
 CONFIG_MTD_ONENAND=y
 CONFIG_MTD_ONENAND_VERIFY_WRITE=y
 CONFIG_MTD_ONENAND_GENERIC=y
+CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=y
 CONFIG_BLK_DEV_RAM=y
@@ -72,47 +68,48 @@ CONFIG_SCSI_CONSTANTS=y
 CONFIG_SCSI_LOGGING=y
 CONFIG_SCSI_SCAN_ASYNC=y
 CONFIG_NETDEVICES=y
+CONFIG_NETCONSOLE=m
 CONFIG_TUN=y
-CONFIG_NET_ETHERNET=y
 CONFIG_SMC91X=y
 CONFIG_PPP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
 CONFIG_PPP_MPPE=m
 CONFIG_PPPOE=m
-CONFIG_NETCONSOLE=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
 # CONFIG_MOUSE_PS2 is not set
 # CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_NOMADIK=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
+CONFIG_I2C_NOMADIK=y
 CONFIG_DEBUG_GPIO=y
-CONFIG_PINCTRL_NOMADIK=y
 # CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
+CONFIG_MMC=y
+CONFIG_MMC_CLKGATE=y
+CONFIG_MMC_ARMMMCI=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
 CONFIG_FUSE_FS=y
 CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_ROOT_NFS=y
-CONFIG_SMB_FS=m
 CONFIG_CIFS=m
 CONFIG_CIFS_WEAK_PW_HASH=y
 CONFIG_NLS_CODEPAGE_437=y
@@ -120,12 +117,11 @@ CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=y
 # CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_FS=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_SHA1=y
 CONFIG_CRYPTO_DES=y
diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
index 42eab9a2a0fd..7e0ebb64a7f9 100644
--- a/arch/arm/configs/omap1_defconfig
+++ b/arch/arm/configs/omap1_defconfig
@@ -195,6 +195,7 @@ CONFIG_SND_SOC=y
 CONFIG_SND_OMAP_SOC=y
 # CONFIG_USB_HID is not set
 CONFIG_USB=y
+CONFIG_USB_PHY=y
 CONFIG_USB_DEBUG=y
 CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index bd07864f14a0..33903ca0d879 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -93,6 +93,7 @@ CONFIG_BLK_DEV_RAM_SIZE=16384
 CONFIG_SENSORS_LIS3LV02D=m
 CONFIG_SENSORS_TSL2550=m
 CONFIG_SENSORS_LIS3_I2C=m
+CONFIG_BMP085_I2C=m
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
new file mode 100644
index 000000000000..4d0dc3c16063
--- /dev/null
+++ b/arch/arm/configs/sama5_defconfig
@@ -0,0 +1,181 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_AT91=y
+CONFIG_SOC_SAM_V7=y
+CONFIG_SOC_SAMA5D3=y
+CONFIG_MACH_SAMA5_DT=y
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_UACCESS_WITH_MEMCPY=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_VFP=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_ADVANCED_DEBUG=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_IPV6=y
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET6_XFRM_MODE_BEET is not set
+CONFIG_IPV6_SIT_6RD=y
+CONFIG_CAN=y
+CONFIG_CAN_AT91=y
+CONFIG_CFG80211=y
+CONFIG_MAC80211=y
+CONFIG_MAC80211_LEDS=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=4
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_SSC=y
+CONFIG_EEPROM_AT24=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_MICREL_PHY=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_QT1070=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=y
+CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y
+# CONFIG_SERIO is not set
+CONFIG_LEGACY_PTY_COUNT=4
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
+CONFIG_SPI=y
+CONFIG_SPI_ATMEL=y
+CONFIG_SPI_GPIO=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_SSB=m
+CONFIG_FB=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_HID_GENERIC is not set
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ACM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_AT91=y
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_MMC=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+CONFIG_MMC_ATMELMCI=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AT91RM9200=y
+CONFIG_DMADEVICES=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_IIO=y
+CONFIG_AT91_ADC=y
+CONFIG_EXT2_FS=y
+CONFIG_FANOTIFY=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+CONFIG_CRYPTO_DEV_ATMEL_AES=y
+CONFIG_CRYPTO_DEV_ATMEL_TDES=y
+CONFIG_CRYPTO_DEV_ATMEL_SHA=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC_ITU_T=m
diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
index 865980c5f212..7ff23a077f5d 100644
--- a/arch/arm/configs/spear3xx_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -6,7 +6,9 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_PLAT_SPEAR=y
+CONFIG_ARCH_SPEAR3XX=y
 CONFIG_MACH_SPEAR300=y
 CONFIG_MACH_SPEAR310=y
 CONFIG_MACH_SPEAR320=y
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
index a2a1265f86b6..7822980d7d55 100644
--- a/arch/arm/configs/spear6xx_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -6,6 +6,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_PLAT_SPEAR=y
 CONFIG_ARCH_SPEAR6XX=y
 CONFIG_BINFMT_MISC=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index aba4881d20e5..a5f0485133cf 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
@@ -20,15 +19,14 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
-CONFIG_EFI_PARTITION=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_TEGRA=y
 CONFIG_GPIO_PCA953X=y
 CONFIG_ARCH_TEGRA_2x_SOC=y
 CONFIG_ARCH_TEGRA_3x_SOC=y
+CONFIG_ARCH_TEGRA_114_SOC=y
 CONFIG_TEGRA_PCI=y
-CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA=y
 CONFIG_TEGRA_EMC_SCALING_ENABLE=y
 CONFIG_SMP=y
 CONFIG_PREEMPT=y
@@ -37,8 +35,8 @@ CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_AUTO_ZRELADDR=y
 CONFIG_KEXEC=y
+CONFIG_AUTO_ZRELADDR=y
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_IDLE=y
@@ -108,6 +106,7 @@ CONFIG_RT2X00=y
 CONFIG_RT2800USB=m
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_TEGRA=y
+CONFIG_KEYBOARD_GPIO=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MPU3050=y
 # CONFIG_LEGACY_PTYS is not set
@@ -117,7 +116,6 @@ CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_TEGRA=y
 CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
 CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PINCTRL=y
@@ -126,6 +124,7 @@ CONFIG_SPI=y
 CONFIG_SPI_TEGRA20_SFLASH=y
 CONFIG_SPI_TEGRA20_SLINK=y
 CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_PALMAS=y
 CONFIG_GPIO_TPS6586X=y
 CONFIG_GPIO_TPS65910=y
 CONFIG_POWER_SUPPLY=y
@@ -136,12 +135,17 @@ CONFIG_SENSORS_LM90=y
 CONFIG_MFD_TPS6586X=y
 CONFIG_MFD_TPS65910=y
 CONFIG_MFD_MAX8907=y
+CONFIG_MFD_TPS65090=y
+CONFIG_MFD_PALMAS=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
 CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_MAX8907=y
+CONFIG_REGULATOR_PALMAS=y
+CONFIG_REGULATOR_TPS51632=y
 CONFIG_REGULATOR_TPS62360=y
+CONFIG_REGULATOR_TPS65090=y
 CONFIG_REGULATOR_TPS6586X=y
 CONFIG_REGULATOR_TPS65910=y
 CONFIG_MEDIA_SUPPORT=y
@@ -187,10 +191,8 @@ CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
 CONFIG_RTC_DRV_MAX8907=y
+CONFIG_RTC_DRV_PALMAS=y
 CONFIG_RTC_DRV_TPS6586X=y
 CONFIG_RTC_DRV_TPS65910=y
 CONFIG_RTC_DRV_EM3027=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 426270fe080d..c037aa1065b7 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -5,7 +5,6 @@ CONFIG_BLK_DEV_INITRD=y
 CONFIG_KALLSYMS_ALL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_U8500=y
 CONFIG_MACH_HREFV60=y
@@ -90,6 +89,8 @@ CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_LM3530=y
 CONFIG_LEDS_LP5521=y
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AB8500=y
 CONFIG_RTC_DRV_PL031=y
@@ -103,6 +104,7 @@ CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
 CONFIG_EXT2_FS_SECURITY=y
 CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index c79f61faa3a5..da1c77d39327 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -243,6 +243,29 @@ typedef struct {
 
 #define ATOMIC64_INIT(i) { (i) }
 
+#ifdef CONFIG_ARM_LPAE
+static inline u64 atomic64_read(const atomic64_t *v)
+{
+        u64 result;
+
+        __asm__ __volatile__("@ atomic64_read\n"
+"       ldrd    %0, %H0, [%1]"
+        : "=&r" (result)
+        : "r" (&v->counter), "Qo" (v->counter)
+        );
+
+        return result;
+}
+
+static inline void atomic64_set(atomic64_t *v, u64 i)
+{
+        __asm__ __volatile__("@ atomic64_set\n"
+"       strd    %2, %H2, [%1]"
+        : "=Qo" (v->counter)
+        : "r" (&v->counter), "r" (i)
+        );
+}
+#else
 static inline u64 atomic64_read(const atomic64_t *v)
 {
         u64 result;
@@ -269,6 +292,7 @@ static inline void atomic64_set(atomic64_t *v, u64 i)
         : "r" (&v->counter), "r" (i)
         : "cc");
 }
+#endif
 
 static inline void atomic64_add(u64 i, atomic64_t *v)
 {
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index e1489c54cd12..bff71388e72a 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -363,4 +363,79 @@ static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
                 flush_cache_all();
 }
 
+/*
+ * Memory synchronization helpers for mixed cached vs non cached accesses.
+ *
+ * Some synchronization algorithms have to set states in memory with the
+ * cache enabled or disabled depending on the code path.  It is crucial
+ * to always ensure proper cache maintenance to update main memory right
+ * away in that case.
+ *
+ * Any cached write must be followed by a cache clean operation.
+ * Any cached read must be preceded by a cache invalidate operation.
+ * Yet, in the read case, a cache flush i.e. atomic clean+invalidate
+ * operation is needed to avoid discarding possible concurrent writes to the
+ * accessed memory.
+ *
+ * Also, in order to prevent a cached writer from interfering with an
+ * adjacent non-cached writer, each state variable must be located to
+ * a separate cache line.
+ */
+
+/*
+ * This needs to be >= the max cache writeback size of all
+ * supported platforms included in the current kernel configuration.
+ * This is used to align state variables to their own cache lines.
+ */
+#define __CACHE_WRITEBACK_ORDER 6  /* guessed from existing platforms */
+#define __CACHE_WRITEBACK_GRANULE (1 << __CACHE_WRITEBACK_ORDER)
+
+/*
+ * There is no __cpuc_clean_dcache_area but we use it anyway for
+ * code intent clarity, and alias it to __cpuc_flush_dcache_area.
+ */
+#define __cpuc_clean_dcache_area __cpuc_flush_dcache_area
+
+/*
+ * Ensure preceding writes to *p by this CPU are visible to
+ * subsequent reads by other CPUs:
+ */
+static inline void __sync_cache_range_w(volatile void *p, size_t size)
+{
+        char *_p = (char *)p;
+
+        __cpuc_clean_dcache_area(_p, size);
+        outer_clean_range(__pa(_p), __pa(_p + size));
+}
+
+/*
+ * Ensure preceding writes to *p by other CPUs are visible to
+ * subsequent reads by this CPU.  We must be careful not to
+ * discard data simultaneously written by another CPU, hence the
+ * usage of flush rather than invalidate operations.
+ */
+static inline void __sync_cache_range_r(volatile void *p, size_t size)
+{
+        char *_p = (char *)p;
+
+#ifdef CONFIG_OUTER_CACHE
+        if (outer_cache.flush_range) {
+                /*
+                 * Ensure dirty data migrated from other CPUs into our cache
+                 * are cleaned out safely before the outer cache is cleaned:
+                 */
+                __cpuc_clean_dcache_area(_p, size);
+
+                /* Clean and invalidate stale data for *p from outer ... */
+                outer_flush_range(__pa(_p), __pa(_p + size));
+        }
+#endif
+
+        /* ... and inner cache: */
+        __cpuc_flush_dcache_area(_p, size);
+}
+
+#define sync_cache_w(ptr) __sync_cache_range_w(ptr, sizeof *(ptr))
+#define sync_cache_r(ptr) __sync_cache_range_r(ptr, sizeof *(ptr))
+
 #endif
diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
index 5ef4d8015a60..1f3262e99d81 100644
--- a/arch/arm/include/asm/cp15.h
+++ b/arch/arm/include/asm/cp15.h
@@ -42,6 +42,8 @@
 #define vectors_high()  (0)
 #endif
 
+#ifdef CONFIG_CPU_CP15
+
 extern unsigned long cr_no_alignment;   /* defined in entry-armv.S */
 extern unsigned long cr_alignment;      /* defined in entry-armv.S */
 
@@ -82,6 +84,18 @@ static inline void set_copro_access(unsigned int val)
         isb();
 }
 
-#endif
+#else /* ifdef CONFIG_CPU_CP15 */
+
+/*
+ * cr_alignment and cr_no_alignment are tightly coupled to cp15 (at least in the
+ * minds of the developers). Yielding 0 for machines without a cp15 (and making
+ * it read-only) is fine for most cases and saves quite some #ifdeffery.
+ */
+#define cr_no_alignment UL(0)
+#define cr_alignment    UL(0)
+
+#endif /* ifdef CONFIG_CPU_CP15 / else */
+
+#endif /* ifndef __ASSEMBLY__ */
 
 #endif
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index ad41ec2471e8..7652712d1d14 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -38,6 +38,24 @@
 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
         ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
 
+#define ARM_CPU_IMP_ARM                 0x41
+#define ARM_CPU_IMP_INTEL               0x69
+
+#define ARM_CPU_PART_ARM1136            0xB360
+#define ARM_CPU_PART_ARM1156            0xB560
+#define ARM_CPU_PART_ARM1176            0xB760
+#define ARM_CPU_PART_ARM11MPCORE        0xB020
+#define ARM_CPU_PART_CORTEX_A8          0xC080
+#define ARM_CPU_PART_CORTEX_A9          0xC090
+#define ARM_CPU_PART_CORTEX_A5          0xC050
+#define ARM_CPU_PART_CORTEX_A15         0xC0F0
+#define ARM_CPU_PART_CORTEX_A7          0xC070
+
+#define ARM_CPU_XSCALE_ARCH_MASK        0xe000
+#define ARM_CPU_XSCALE_ARCH_V1          0x2000
+#define ARM_CPU_XSCALE_ARCH_V2          0x4000
+#define ARM_CPU_XSCALE_ARCH_V3          0x6000
+
 extern unsigned int processor_id;
 
 #ifdef CONFIG_CPU_CP15
@@ -50,6 +68,7 @@ extern unsigned int processor_id;
                     : "cc");                                            \
                 __val;                                                  \
         })
+
 #define read_cpuid_ext(ext_reg)                                         \
         ({                                                              \
                 unsigned int __val;                                     \
@@ -59,29 +78,24 @@ extern unsigned int processor_id;
                     : "cc");                                            \
                 __val;                                                  \
         })
-#else
-#define read_cpuid(reg) (processor_id)
-#define read_cpuid_ext(reg) 0
-#endif
 
-#define ARM_CPU_IMP_ARM                 0x41
-#define ARM_CPU_IMP_INTEL               0x69
+#else /* ifdef CONFIG_CPU_CP15 */
 
-#define ARM_CPU_PART_ARM1136            0xB360
-#define ARM_CPU_PART_ARM1156            0xB560
-#define ARM_CPU_PART_ARM1176            0xB760
-#define ARM_CPU_PART_ARM11MPCORE        0xB020
-#define ARM_CPU_PART_CORTEX_A8          0xC080
-#define ARM_CPU_PART_CORTEX_A9          0xC090
-#define ARM_CPU_PART_CORTEX_A5          0xC050
-#define ARM_CPU_PART_CORTEX_A15         0xC0F0
-#define ARM_CPU_PART_CORTEX_A7          0xC070
+/*
+ * read_cpuid and read_cpuid_ext should only ever be called on machines that
+ * have cp15 so warn on other usages.
+ */
+#define read_cpuid(reg)                                                 \
+        ({                                                              \
+                WARN_ON_ONCE(1);                                        \
+                0;                                                      \
+        })
 
-#define ARM_CPU_XSCALE_ARCH_MASK        0xe000
-#define ARM_CPU_XSCALE_ARCH_V1          0x2000
-#define ARM_CPU_XSCALE_ARCH_V2          0x4000
-#define ARM_CPU_XSCALE_ARCH_V3          0x6000
+#define read_cpuid_ext(reg) read_cpuid(reg)
+
+#endif /* ifdef CONFIG_CPU_CP15 / else */
 
+#ifdef CONFIG_CPU_CP15
 /*
  * The CPU ID never changes at run time, so we might as well tell the
  * compiler that it's constant.  Use this function to read the CPU ID
@@ -92,6 +106,15 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
         return read_cpuid(CPUID_ID);
 }
 
+#else /* ifdef CONFIG_CPU_CP15 */
+
+static inline unsigned int __attribute_const__ read_cpuid_id(void)
+{
+        return processor_id;
+}
+
+#endif /* ifdef CONFIG_CPU_CP15 / else */
+
 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
 {
         return (read_cpuid_id() & 0xFF000000) >> 24;
diff --git a/arch/arm/include/asm/firmware.h b/arch/arm/include/asm/firmware.h
new file mode 100644
index 000000000000..15631300c238
--- /dev/null
+++ b/arch/arm/include/asm/firmware.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics.
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Tomasz Figa <t.figa@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_FIRMWARE_H
+#define __ASM_ARM_FIRMWARE_H
+
+#include <linux/bug.h>
+
+/*
+ * struct firmware_ops
+ *
+ * A structure to specify available firmware operations.
+ *
+ * A filled up structure can be registered with register_firmware_ops().
+ */
+struct firmware_ops {
+        /*
+         * Enters CPU idle mode
+         */
+        int (*do_idle)(void);
+        /*
+         * Sets boot address of specified physical CPU
+         */
+        int (*set_cpu_boot_addr)(int cpu, unsigned long boot_addr);
+        /*
+         * Boots specified physical CPU
+         */
+        int (*cpu_boot)(int cpu);
+        /*
+         * Initializes L2 cache
+         */
+        int (*l2x0_init)(void);
+};
+
+/* Global pointer for current firmware_ops structure, can't be NULL. */
+extern const struct firmware_ops *firmware_ops;
+
+/*
+ * call_firmware_op(op, ...)
+ *
+ * Checks if firmware operation is present and calls it,
+ * otherwise returns -ENOSYS
+ */
+#define call_firmware_op(op, ...)                                       \
+        ((firmware_ops->op) ? firmware_ops->op(__VA_ARGS__) : (-ENOSYS))
+
+/*
+ * register_firmware_ops(ops)
+ *
+ * A function to register platform firmware_ops struct.
+ */
+static inline void register_firmware_ops(const struct firmware_ops *ops)
+{
+        BUG_ON(!ops);
+
+        firmware_ops = ops;
+}
+
+#endif
diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h
index 8cacbcda76da..b6e9f2c108b5 100644
--- a/arch/arm/include/asm/glue-df.h
+++ b/arch/arm/include/asm/glue-df.h
@@ -18,12 +18,12 @@
  *      ================
  *
  *      We have the following to choose from:
- *        arm6          - ARM6 style
  *        arm7          - ARM7 style
  *        v4_early      - ARMv4 without Thumb early abort handler
  *        v4t_late      - ARMv4 with Thumb late abort handler
  *        v4t_early     - ARMv4 with Thumb early abort handler
- *        v5tej_early   - ARMv5 with Thumb and Java early abort handler
+ *        v5t_early     - ARMv5 with Thumb early abort handler
+ *        v5tj_early    - ARMv5 with Thumb and Java early abort handler
  *        xscale        - ARMv5 with Thumb with Xscale extensions
  *        v6_early      - ARMv6 generic early abort handler
  *        v7_early      - ARMv7 generic early abort handler
@@ -39,19 +39,19 @@
 # endif
 #endif
 
-#ifdef CONFIG_CPU_ABRT_LV4T
+#ifdef CONFIG_CPU_ABRT_EV4
 # ifdef CPU_DABORT_HANDLER
 #  define MULTI_DABORT 1
 # else
-#  define CPU_DABORT_HANDLER v4t_late_abort
+#  define CPU_DABORT_HANDLER v4_early_abort
 # endif
 #endif
 
-#ifdef CONFIG_CPU_ABRT_EV4
+#ifdef CONFIG_CPU_ABRT_LV4T
 # ifdef CPU_DABORT_HANDLER
 #  define MULTI_DABORT 1
 # else
-#  define CPU_DABORT_HANDLER v4_early_abort
+#  define CPU_DABORT_HANDLER v4t_late_abort
 # endif
 #endif
 
@@ -63,19 +63,19 @@
 # endif
 #endif
 
-#ifdef CONFIG_CPU_ABRT_EV5TJ
+#ifdef CONFIG_CPU_ABRT_EV5T
 # ifdef CPU_DABORT_HANDLER
 #  define MULTI_DABORT 1
 # else
-#  define CPU_DABORT_HANDLER v5tj_early_abort
+#  define CPU_DABORT_HANDLER v5t_early_abort
 # endif
 #endif
 
-#ifdef CONFIG_CPU_ABRT_EV5T
+#ifdef CONFIG_CPU_ABRT_EV5TJ
 # ifdef CPU_DABORT_HANDLER
 #  define MULTI_DABORT 1
 # else
-#  define CPU_DABORT_HANDLER v5t_early_abort
+#  define CPU_DABORT_HANDLER v5tj_early_abort
 # endif
 #endif
 
diff --git a/arch/arm/include/asm/idmap.h b/arch/arm/include/asm/idmap.h
index 1a66f907e5cc..bf863edb517d 100644
--- a/arch/arm/include/asm/idmap.h
+++ b/arch/arm/include/asm/idmap.h
@@ -8,7 +8,6 @@
 #define __idmap __section(.idmap.text) noinline notrace
 
 extern pgd_t *idmap_pgd;
-extern pgd_t *hyp_pgd;
 
 void setup_mm_for_reboot(void);
 
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index 35c21c375d81..53c15dec7af6 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -30,6 +30,11 @@ extern void asm_do_IRQ(unsigned int, struct pt_regs *);
 void handle_IRQ(unsigned int, struct pt_regs *);
 void init_IRQ(void);
 
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+extern void (*handle_arch_irq)(struct pt_regs *);
+extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
+#endif
+
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
index 7c3d813e15df..124623e5ef14 100644
--- a/arch/arm/include/asm/kvm_arm.h
+++ b/arch/arm/include/asm/kvm_arm.h
@@ -211,4 +211,8 @@
 
 #define HSR_HVC_IMM_MASK        ((1UL << 16) - 1)
 
+#define HSR_DABT_S1PTW          (1U << 7)
+#define HSR_DABT_CM             (1U << 8)
+#define HSR_DABT_EA             (1U << 9)
+
 #endif /* __ARM_KVM_ARM_H__ */
diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h
index e4956f4e23e1..18d50322a9e2 100644
--- a/arch/arm/include/asm/kvm_asm.h
+++ b/arch/arm/include/asm/kvm_asm.h
@@ -75,7 +75,7 @@ extern char __kvm_hyp_code_end[];
 extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
 
 extern void __kvm_flush_vm_context(void);
-extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
+extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
 
 extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
 #endif
diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h
index fd611996bfb5..82b4babead2c 100644
--- a/arch/arm/include/asm/kvm_emulate.h
+++ b/arch/arm/include/asm/kvm_emulate.h
@@ -22,11 +22,12 @@
 #include <linux/kvm_host.h>
 #include <asm/kvm_asm.h>
 #include <asm/kvm_mmio.h>
+#include <asm/kvm_arm.h>
 
-u32 *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num);
-u32 *vcpu_spsr(struct kvm_vcpu *vcpu);
+unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num);
+unsigned long *vcpu_spsr(struct kvm_vcpu *vcpu);
 
-int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run);
+bool kvm_condition_valid(struct kvm_vcpu *vcpu);
 void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr);
 void kvm_inject_undefined(struct kvm_vcpu *vcpu);
 void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
@@ -37,14 +38,14 @@ static inline bool vcpu_mode_is_32bit(struct kvm_vcpu *vcpu)
         return 1;
 }
 
-static inline u32 *vcpu_pc(struct kvm_vcpu *vcpu)
+static inline unsigned long *vcpu_pc(struct kvm_vcpu *vcpu)
 {
-        return (u32 *)&vcpu->arch.regs.usr_regs.ARM_pc;
+        return &vcpu->arch.regs.usr_regs.ARM_pc;
 }
 
-static inline u32 *vcpu_cpsr(struct kvm_vcpu *vcpu)
+static inline unsigned long *vcpu_cpsr(struct kvm_vcpu *vcpu)
 {
-        return (u32 *)&vcpu->arch.regs.usr_regs.ARM_cpsr;
+        return &vcpu->arch.regs.usr_regs.ARM_cpsr;
 }
 
 static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
@@ -69,4 +70,96 @@ static inline bool kvm_vcpu_reg_is_pc(struct kvm_vcpu *vcpu, int reg)
         return reg == 15;
 }
 
+static inline u32 kvm_vcpu_get_hsr(struct kvm_vcpu *vcpu)
+{
+        return vcpu->arch.fault.hsr;
+}
+
+static inline unsigned long kvm_vcpu_get_hfar(struct kvm_vcpu *vcpu)
+{
+        return vcpu->arch.fault.hxfar;
+}
+
+static inline phys_addr_t kvm_vcpu_get_fault_ipa(struct kvm_vcpu *vcpu)
+{
+        return ((phys_addr_t)vcpu->arch.fault.hpfar & HPFAR_MASK) << 8;
+}
+
+static inline unsigned long kvm_vcpu_get_hyp_pc(struct kvm_vcpu *vcpu)
+{
+        return vcpu->arch.fault.hyp_pc;
+}
+
+static inline bool kvm_vcpu_dabt_isvalid(struct kvm_vcpu *vcpu)
+{
+        return kvm_vcpu_get_hsr(vcpu) & HSR_ISV;
+}
+
+static inline bool kvm_vcpu_dabt_iswrite(struct kvm_vcpu *vcpu)
+{
+        return kvm_vcpu_get_hsr(vcpu) & HSR_WNR;
+}
+
+static inline bool kvm_vcpu_dabt_issext(struct kvm_vcpu *vcpu)
+{
+        return kvm_vcpu_get_hsr(vcpu) & HSR_SSE;
+}
+
+static inline int kvm_vcpu_dabt_get_rd(struct kvm_vcpu *vcpu)
+{
+        return (kvm_vcpu_get_hsr(vcpu) & HSR_SRT_MASK) >> HSR_SRT_SHIFT;
+}
+
+static inline bool kvm_vcpu_dabt_isextabt(struct kvm_vcpu *vcpu)
+{
+        return kvm_vcpu_get_hsr(vcpu) & HSR_DABT_EA;
+}
+
+static inline bool kvm_vcpu_dabt_iss1tw(struct kvm_vcpu *vcpu)
+{
+        return kvm_vcpu_get_hsr(vcpu) & HSR_DABT_S1PTW;
+}
+
+/* Get Access Size from a data abort */
+static inline int kvm_vcpu_dabt_get_as(struct kvm_vcpu *vcpu)
+{
+        switch ((kvm_vcpu_get_hsr(vcpu) >> 22) & 0x3) {
+        case 0:
+                return 1;
+        case 1:
+                return 2;
+        case 2:
+                return 4;
+        default:
+                kvm_err("Hardware is weird: SAS 0b11 is reserved\n");
+                return -EFAULT;
+        }
+}
+
+/* This one is not specific to Data Abort */
+static inline bool kvm_vcpu_trap_il_is32bit(struct kvm_vcpu *vcpu)
+{
+        return kvm_vcpu_get_hsr(vcpu) & HSR_IL;
+}
+
+static inline u8 kvm_vcpu_trap_get_class(struct kvm_vcpu *vcpu)
+{
+        return kvm_vcpu_get_hsr(vcpu) >> HSR_EC_SHIFT;
+}
+
+static inline bool kvm_vcpu_trap_is_iabt(struct kvm_vcpu *vcpu)
+{
+        return kvm_vcpu_trap_get_class(vcpu) == HSR_EC_IABT;
+}
+
+static inline u8 kvm_vcpu_trap_get_fault(struct kvm_vcpu *vcpu)
+{
+        return kvm_vcpu_get_hsr(vcpu) & HSR_FSC_TYPE;
+}
+
+static inline u32 kvm_vcpu_hvc_get_imm(struct kvm_vcpu *vcpu)
+{
+        return kvm_vcpu_get_hsr(vcpu) & HSR_HVC_IMM_MASK;
+}
+
 #endif /* __ARM_KVM_EMULATE_H__ */
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index d1736a53b12d..57cb786a6203 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -80,6 +80,15 @@ struct kvm_mmu_memory_cache {
         void *objects[KVM_NR_MEM_OBJS];
 };
 
+struct kvm_vcpu_fault_info {
+        u32 hsr;                /* Hyp Syndrome Register */
+        u32 hxfar;              /* Hyp Data/Inst. Fault Address Register */
+        u32 hpfar;              /* Hyp IPA Fault Address Register */
+        u32 hyp_pc;             /* PC when exception was taken from Hyp mode */
+};
+
+typedef struct vfp_hard_struct kvm_cpu_context_t;
+
 struct kvm_vcpu_arch {
         struct kvm_regs regs;
 
@@ -93,13 +102,13 @@ struct kvm_vcpu_arch {
         u32 midr;
 
         /* Exception Information */
-        u32 hsr;                /* Hyp Syndrome Register */
-        u32 hxfar;              /* Hyp Data/Inst Fault Address Register */
-        u32 hpfar;              /* Hyp IPA Fault Address Register */
+        struct kvm_vcpu_fault_info fault;
 
         /* Floating point registers (VFP and Advanced SIMD/NEON) */
         struct vfp_hard_struct vfp_guest;
-        struct vfp_hard_struct *vfp_host;
+
+        /* Host FP context */
+        kvm_cpu_context_t *host_cpu_context;
 
         /* VGIC state */
         struct vgic_cpu vgic_cpu;
@@ -122,9 +131,6 @@ struct kvm_vcpu_arch {
         /* Interrupt related fields */
         u32 irq_lines;          /* IRQ and FIQ levels */
 
-        /* Hyp exception information */
-        u32 hyp_pc;             /* PC when exception was taken from Hyp mode */
-
         /* Cache some mmu pages needed inside spinlock regions */
         struct kvm_mmu_memory_cache mmu_page_cache;
 
@@ -181,4 +187,41 @@ struct kvm_one_reg;
 int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
 int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
 
+int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
+                int exception_index);
+
+static inline void __cpu_init_hyp_mode(unsigned long long boot_pgd_ptr,
+                                       unsigned long long pgd_ptr,
+                                       unsigned long hyp_stack_ptr,
+                                       unsigned long vector_ptr)
+{
+        /*
+         * Call initialization code, and switch to the full blown HYP
+         * code. The init code doesn't need to preserve these
+         * registers as r0-r3 are already callee saved according to
+         * the AAPCS.
+         * Note that we slightly misuse the prototype by casing the
+         * stack pointer to a void *.
+         *
+         * We don't have enough registers to perform the full init in
+         * one go.  Install the boot PGD first, and then install the
+         * runtime PGD, stack pointer and vectors. The PGDs are always
+         * passed as the third argument, in order to be passed into
+         * r2-r3 to the init code (yes, this is compliant with the
+         * PCS!).
+         */
+
+        kvm_call_hyp(NULL, 0, boot_pgd_ptr);
+
+        kvm_call_hyp((void*)hyp_stack_ptr, vector_ptr, pgd_ptr);
+}
+
+static inline int kvm_arch_dev_ioctl_check_extension(long ext)
+{
+        return 0;
+}
+
+int kvm_perf_init(void);
+int kvm_perf_teardown(void);
+
 #endif /* __ARM_KVM_HOST_H__ */
diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
index 421a20b34874..472ac7091003 100644
--- a/arch/arm/include/asm/kvm_mmu.h
+++ b/arch/arm/include/asm/kvm_mmu.h
@@ -19,9 +19,33 @@
 #ifndef __ARM_KVM_MMU_H__
 #define __ARM_KVM_MMU_H__
 
+#include <asm/memory.h>
+#include <asm/page.h>
+
+/*
+ * We directly use the kernel VA for the HYP, as we can directly share
+ * the mapping (HTTBR "covers" TTBR1).
+ */
+#define HYP_PAGE_OFFSET_MASK    UL(~0)
+#define HYP_PAGE_OFFSET         PAGE_OFFSET
+#define KERN_TO_HYP(kva)        (kva)
+
+/*
+ * Our virtual mapping for the boot-time MMU-enable code. Must be
+ * shared across all the page-tables. Conveniently, we use the vectors
+ * page, where no kernel data will ever be shared with HYP.
+ */
+#define TRAMPOLINE_VA           UL(CONFIG_VECTORS_BASE)
+
+#ifndef __ASSEMBLY__
+
+#include <asm/cacheflush.h>
+#include <asm/pgalloc.h>
+
 int create_hyp_mappings(void *from, void *to);
 int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
-void free_hyp_pmds(void);
+void free_boot_hyp_pgd(void);
+void free_hyp_pgds(void);
 
 int kvm_alloc_stage2_pgd(struct kvm *kvm);
 void kvm_free_stage2_pgd(struct kvm *kvm);
@@ -33,9 +57,21 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
 void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
 
 phys_addr_t kvm_mmu_get_httbr(void);
+phys_addr_t kvm_mmu_get_boot_httbr(void);
+phys_addr_t kvm_get_idmap_vector(void);
 int kvm_mmu_init(void);
 void kvm_clear_hyp_idmap(void);
 
+static inline void kvm_set_pte(pte_t *pte, pte_t new_pte)
+{
+        pte_val(*pte) = new_pte;
+        /*
+         * flush_pmd_entry just takes a void pointer and cleans the necessary
+         * cache entries, so we can reuse the function for ptes.
+         */
+        flush_pmd_entry(pte);
+}
+
 static inline bool kvm_is_write_fault(unsigned long hsr)
 {
         unsigned long hsr_ec = hsr >> HSR_EC_SHIFT;
@@ -47,4 +83,53 @@ static inline bool kvm_is_write_fault(unsigned long hsr)
                 return true;
 }
 
+static inline void kvm_clean_pgd(pgd_t *pgd)
+{
+        clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
+}
+
+static inline void kvm_clean_pmd_entry(pmd_t *pmd)
+{
+        clean_pmd_entry(pmd);
+}
+
+static inline void kvm_clean_pte(pte_t *pte)
+{
+        clean_pte_table(pte);
+}
+
+static inline void kvm_set_s2pte_writable(pte_t *pte)
+{
+        pte_val(*pte) |= L_PTE_S2_RDWR;
+}
+
+struct kvm;
+
+static inline void coherent_icache_guest_page(struct kvm *kvm, gfn_t gfn)
+{
+        /*
+         * If we are going to insert an instruction page and the icache is
+         * either VIPT or PIPT, there is a potential problem where the host
+         * (or another VM) may have used the same page as this guest, and we
+         * read incorrect data from the icache.  If we're using a PIPT cache,
+         * we can invalidate just that page, but if we are using a VIPT cache
+         * we need to invalidate the entire icache - damn shame - as written
+         * in the ARM ARM (DDI 0406C.b - Page B3-1393).
+         *
+         * VIVT caches are tagged using both the ASID and the VMID and doesn't
+         * need any kind of flushing (DDI 0406C.b - Page B3-1392).
+         */
+        if (icache_is_pipt()) {
+                unsigned long hva = gfn_to_hva(kvm, gfn);
+                __cpuc_coherent_user_range(hva, hva + PAGE_SIZE);
+        } else if (!icache_is_vivt_asid_tagged()) {
+                /* any kind of VIPT cache */
+                __flush_icache_all();
+        }
+}
+
+#define kvm_flush_dcache_to_poc(a,l)    __cpuc_flush_dcache_area((a), (l))
+
+#endif  /* !__ASSEMBLY__ */
+
 #endif /* __ARM_KVM_MMU_H__ */
diff --git a/arch/arm/include/asm/kvm_vgic.h b/arch/arm/include/asm/kvm_vgic.h
index ab97207d9cd3..343744e4809c 100644
--- a/arch/arm/include/asm/kvm_vgic.h
+++ b/arch/arm/include/asm/kvm_vgic.h
@@ -21,7 +21,6 @@
 
 #include <linux/kernel.h>
 #include <linux/kvm.h>
-#include <linux/kvm_host.h>
 #include <linux/irqreturn.h>
 #include <linux/spinlock.h>
 #include <linux/types.h>
diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index 18c883023339..2092ee1e1300 100644
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -20,11 +20,6 @@ struct seq_file;
 extern void init_FIQ(int);
 extern int show_fiq_list(struct seq_file *, int);
 
-#ifdef CONFIG_MULTI_IRQ_HANDLER
-extern void (*handle_arch_irq)(struct pt_regs *);
-extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
-#endif
-
 /*
  * This is for easy migration, but should be changed in the source
  */
@@ -35,35 +30,4 @@ do {							\
         raw_spin_unlock(&desc->lock);                   \
 } while(0)
 
-#ifndef __ASSEMBLY__
-/*
- * Entry/exit functions for chained handlers where the primary IRQ chip
- * may implement either fasteoi or level-trigger flow control.
- */
-static inline void chained_irq_enter(struct irq_chip *chip,
-                                     struct irq_desc *desc)
-{
-        /* FastEOI controllers require no action on entry. */
-        if (chip->irq_eoi)
-                return;
-
-        if (chip->irq_mask_ack) {
-                chip->irq_mask_ack(&desc->irq_data);
-        } else {
-                chip->irq_mask(&desc->irq_data);
-                if (chip->irq_ack)
-                        chip->irq_ack(&desc->irq_data);
-        }
-}
-
-static inline void chained_irq_exit(struct irq_chip *chip,
-                                    struct irq_desc *desc)
-{
-        if (chip->irq_eoi)
-                chip->irq_eoi(&desc->irq_data);
-        else
-                chip->irq_unmask(&desc->irq_data);
-}
-#endif
-
 #endif
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 5cf2e979b4be..7d2c3c843801 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -30,6 +30,11 @@ struct hw_pci {
         void            (*postinit)(void);
         u8              (*swizzle)(struct pci_dev *dev, u8 *pin);
         int             (*map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
+        resource_size_t (*align_resource)(struct pci_dev *dev,
+                                          const struct resource *res,
+                                          resource_size_t start,
+                                          resource_size_t size,
+                                          resource_size_t align);
 };
 
 /*
@@ -51,6 +56,12 @@ struct pci_sys_data {
         u8              (*swizzle)(struct pci_dev *, u8 *);
                                         /* IRQ mapping                          */
         int             (*map_irq)(const struct pci_dev *, u8, u8);
+                                        /* Resource alignement requirements     */
+        resource_size_t (*align_resource)(struct pci_dev *dev,
+                                          const struct resource *res,
+                                          resource_size_t start,
+                                          resource_size_t size,
+                                          resource_size_t align);
         void            *private_data;  /* platform controller private data     */
 };
 
diff --git a/arch/arm/include/asm/mcpm.h b/arch/arm/include/asm/mcpm.h
new file mode 100644
index 000000000000..0f7b7620e9a5
--- /dev/null
+++ b/arch/arm/include/asm/mcpm.h
@@ -0,0 +1,209 @@
+/*
+ * arch/arm/include/asm/mcpm.h
+ *
+ * Created by:  Nicolas Pitre, April 2012
+ * Copyright:   (C) 2012-2013  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef MCPM_H
+#define MCPM_H
+
+/*
+ * Maximum number of possible clusters / CPUs per cluster.
+ *
+ * This should be sufficient for quite a while, while keeping the
+ * (assembly) code simpler.  When this starts to grow then we'll have
+ * to consider dynamic allocation.
+ */
+#define MAX_CPUS_PER_CLUSTER    4
+#define MAX_NR_CLUSTERS         2
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+#include <asm/cacheflush.h>
+
+/*
+ * Platform specific code should use this symbol to set up secondary
+ * entry location for processors to use when released from reset.
+ */
+extern void mcpm_entry_point(void);
+
+/*
+ * This is used to indicate where the given CPU from given cluster should
+ * branch once it is ready to re-enter the kernel using ptr, or NULL if it
+ * should be gated.  A gated CPU is held in a WFE loop until its vector
+ * becomes non NULL.
+ */
+void mcpm_set_entry_vector(unsigned cpu, unsigned cluster, void *ptr);
+
+/*
+ * CPU/cluster power operations API for higher subsystems to use.
+ */
+
+/**
+ * mcpm_cpu_power_up - make given CPU in given cluster runable
+ *
+ * @cpu: CPU number within given cluster
+ * @cluster: cluster number for the CPU
+ *
+ * The identified CPU is brought out of reset.  If the cluster was powered
+ * down then it is brought up as well, taking care not to let the other CPUs
+ * in the cluster run, and ensuring appropriate cluster setup.
+ *
+ * Caller must ensure the appropriate entry vector is initialized with
+ * mcpm_set_entry_vector() prior to calling this.
+ *
+ * This must be called in a sleepable context.  However, the implementation
+ * is strongly encouraged to return early and let the operation happen
+ * asynchronously, especially when significant delays are expected.
+ *
+ * If the operation cannot be performed then an error code is returned.
+ */
+int mcpm_cpu_power_up(unsigned int cpu, unsigned int cluster);
+
+/**
+ * mcpm_cpu_power_down - power the calling CPU down
+ *
+ * The calling CPU is powered down.
+ *
+ * If this CPU is found to be the "last man standing" in the cluster
+ * then the cluster is prepared for power-down too.
+ *
+ * This must be called with interrupts disabled.
+ *
+ * This does not return.  Re-entry in the kernel is expected via
+ * mcpm_entry_point.
+ */
+void mcpm_cpu_power_down(void);
+
+/**
+ * mcpm_cpu_suspend - bring the calling CPU in a suspended state
+ *
+ * @expected_residency: duration in microseconds the CPU is expected
+ *                      to remain suspended, or 0 if unknown/infinity.
+ *
+ * The calling CPU is suspended.  The expected residency argument is used
+ * as a hint by the platform specific backend to implement the appropriate
+ * sleep state level according to the knowledge it has on wake-up latency
+ * for the given hardware.
+ *
+ * If this CPU is found to be the "last man standing" in the cluster
+ * then the cluster may be prepared for power-down too, if the expected
+ * residency makes it worthwhile.
+ *
+ * This must be called with interrupts disabled.
+ *
+ * This does not return.  Re-entry in the kernel is expected via
+ * mcpm_entry_point.
+ */
+void mcpm_cpu_suspend(u64 expected_residency);
+
+/**
+ * mcpm_cpu_powered_up - housekeeping workafter a CPU has been powered up
+ *
+ * This lets the platform specific backend code perform needed housekeeping
+ * work.  This must be called by the newly activated CPU as soon as it is
+ * fully operational in kernel space, before it enables interrupts.
+ *
+ * If the operation cannot be performed then an error code is returned.
+ */
+int mcpm_cpu_powered_up(void);
+
+/*
+ * Platform specific methods used in the implementation of the above API.
+ */
+struct mcpm_platform_ops {
+        int (*power_up)(unsigned int cpu, unsigned int cluster);
+        void (*power_down)(void);
+        void (*suspend)(u64);
+        void (*powered_up)(void);
+};
+
+/**
+ * mcpm_platform_register - register platform specific power methods
+ *
+ * @ops: mcpm_platform_ops structure to register
+ *
+ * An error is returned if the registration has been done previously.
+ */
+int __init mcpm_platform_register(const struct mcpm_platform_ops *ops);
+
+/* Synchronisation structures for coordinating safe cluster setup/teardown: */
+
+/*
+ * When modifying this structure, make sure you update the MCPM_SYNC_ defines
+ * to match.
+ */
+struct mcpm_sync_struct {
+        /* individual CPU states */
+        struct {
+                s8 cpu __aligned(__CACHE_WRITEBACK_GRANULE);
+        } cpus[MAX_CPUS_PER_CLUSTER];
+
+        /* cluster state */
+        s8 cluster __aligned(__CACHE_WRITEBACK_GRANULE);
+
+        /* inbound-side state */
+        s8 inbound __aligned(__CACHE_WRITEBACK_GRANULE);
+};
+
+struct sync_struct {
+        struct mcpm_sync_struct clusters[MAX_NR_CLUSTERS];
+};
+
+extern unsigned long sync_phys; /* physical address of *mcpm_sync */
+
+void __mcpm_cpu_going_down(unsigned int cpu, unsigned int cluster);
+void __mcpm_cpu_down(unsigned int cpu, unsigned int cluster);
+void __mcpm_outbound_leave_critical(unsigned int cluster, int state);
+bool __mcpm_outbound_enter_critical(unsigned int this_cpu, unsigned int cluster);
+int __mcpm_cluster_state(unsigned int cluster);
+
+int __init mcpm_sync_init(
+        void (*power_up_setup)(unsigned int affinity_level));
+
+void __init mcpm_smp_set_ops(void);
+
+#else
+
+/* 
+ * asm-offsets.h causes trouble when included in .c files, and cacheflush.h
+ * cannot be included in asm files.  Let's work around the conflict like this.
+ */
+#include <asm/asm-offsets.h>
+#define __CACHE_WRITEBACK_GRANULE CACHE_WRITEBACK_GRANULE
+
+#endif /* ! __ASSEMBLY__ */
+
+/* Definitions for mcpm_sync_struct */
+#define CPU_DOWN                0x11
+#define CPU_COMING_UP           0x12
+#define CPU_UP                  0x13
+#define CPU_GOING_DOWN          0x14
+
+#define CLUSTER_DOWN            0x21
+#define CLUSTER_UP              0x22
+#define CLUSTER_GOING_DOWN      0x23
+
+#define INBOUND_NOT_COMING_UP   0x31
+#define INBOUND_COMING_UP       0x32
+
+/*
+ * Offsets for the mcpm_sync_struct members, for use in asm.
+ * We don't want to make them global to the kernel via asm-offsets.c.
+ */
+#define MCPM_SYNC_CLUSTER_CPUS  0
+#define MCPM_SYNC_CPU_SIZE      __CACHE_WRITEBACK_GRANULE
+#define MCPM_SYNC_CLUSTER_CLUSTER \
+        (MCPM_SYNC_CLUSTER_CPUS + MCPM_SYNC_CPU_SIZE * MAX_CPUS_PER_CLUSTER)
+#define MCPM_SYNC_CLUSTER_INBOUND \
+        (MCPM_SYNC_CLUSTER_CLUSTER + __CACHE_WRITEBACK_GRANULE)
+#define MCPM_SYNC_CLUSTER_SIZE \
+        (MCPM_SYNC_CLUSTER_INBOUND + __CACHE_WRITEBACK_GRANULE)
+
+#endif
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 80d6fc4dbe4a..9bcd262a9008 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -61,6 +61,15 @@ extern void __pgd_error(const char *file, int line, pgd_t);
 #define FIRST_USER_ADDRESS      PAGE_SIZE
 
 /*
+ * Use TASK_SIZE as the ceiling argument for free_pgtables() and
+ * free_pgd_range() to avoid freeing the modules pmd when LPAE is enabled (pmd
+ * page shared between user and kernel).
+ */
+#ifdef CONFIG_ARM_LPAE
+#define USER_PGTABLES_CEILING   TASK_SIZE
+#endif
+
+/*
  * The pgprot_* and protection_map entries will be fixed up in runtime
  * to include the cachable and bufferable bits based on memory policy,
  * as well as any architecture dependent bits like global/ASID and SMP
diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h
index 0f01f4677bd2..7b2899c2f7fc 100644
--- a/arch/arm/include/asm/smp_twd.h
+++ b/arch/arm/include/asm/smp_twd.h
@@ -34,12 +34,4 @@ struct twd_local_timer name __initdata = {	\
 
 int twd_local_timer_register(struct twd_local_timer *);
 
-#ifdef CONFIG_HAVE_ARM_TWD
-void twd_local_timer_of_register(void);
-#else
-static inline void twd_local_timer_of_register(void)
-{
-}
-#endif
-
 #endif
diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h
index 5a85f148b607..21a23e378bbe 100644
--- a/arch/arm/include/asm/system_misc.h
+++ b/arch/arm/include/asm/system_misc.h
@@ -21,9 +21,6 @@ extern void (*arm_pm_idle)(void);
 
 extern unsigned int user_debug;
 
-extern void disable_hlt(void);
-extern void enable_hlt(void);
-
 #endif /* !__ASSEMBLY__ */
 
 #endif /* __ASM_ARM_SYSTEM_MISC_H */
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index cddda1f41f0f..1995d1a84060 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -152,6 +152,7 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
 #define TIF_SYSCALL_AUDIT       9
 #define TIF_SYSCALL_TRACEPOINT  10
 #define TIF_SECCOMP             11      /* seccomp syscall filtering active */
+#define TIF_NOHZ                12      /* in adaptive nohz mode */
 #define TIF_USING_IWMMXT        17
 #define TIF_MEMDIE              18      /* is terminating due to OOM killer */
 #define TIF_RESTORE_SIGMASK     20
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index ab865e65a84c..a3625d141c1d 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -166,7 +166,7 @@
 # define v6wbi_always_flags     (-1UL)
 #endif
 
-#define v7wbi_tlb_flags_smp     (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
+#define v7wbi_tlb_flags_smp     (TLB_WB | TLB_BARRIER | \
                                  TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | \
                                  TLB_V7_UIS_ASID | TLB_V7_UIS_BP)
 #define v7wbi_tlb_flags_up      (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index e4ddfb39ca34..141baa3f9a72 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -44,14 +44,6 @@
 #define __ARCH_WANT_SYS_CLONE
 
 /*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
-
-/*
  * Unimplemented (or alternatively implemented) syscalls
  */
 #define __IGNORE_fadvise64_64
diff --git a/arch/arm/mach-bcm2835/include/mach/debug-macro.S b/arch/arm/include/debug/bcm2835.S
index 8a161e44ae28..aed9199bd847 100644
--- a/arch/arm/mach-bcm2835/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/bcm2835.S
@@ -11,7 +11,8 @@
  *
  */
 
-#include <mach/bcm2835_soc.h>
+#define BCM2835_DEBUG_PHYS 0x20201000
+#define BCM2835_DEBUG_VIRT 0xf0201000
 
         .macro  addruart, rp, rv, tmp
         ldr     \rp, =BCM2835_DEBUG_PHYS
diff --git a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S b/arch/arm/include/debug/cns3xxx.S
index d04c150baa1c..d04c150baa1c 100644
--- a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/cns3xxx.S
diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/include/debug/exynos.S
index e0c86ea475e7..b17fdb7fbd34 100644
--- a/arch/arm/mach-exynos/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/exynos.S
@@ -1,10 +1,7 @@
-/* linux/arch/arm/mach-exynos4/include/mach/debug-macro.S
- *
+/*
  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
- * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
@@ -12,7 +9,10 @@
 
 /* pull in the relevant register and map files. */
 
-#include <mach/map.h>
+#define S3C_ADDR_BASE   0xF6000000
+#define S3C_VA_UART     S3C_ADDR_BASE + 0x01000000
+#define EXYNOS4_PA_UART 0x13800000
+#define EXYNOS5_PA_UART 0x12C00000
 
         /* note, for the boot process to work we have to keep the UART
          * virtual address aligned to an 1MiB boundary for the L1
@@ -36,4 +36,4 @@
 #define fifo_full fifo_full_s5pv210
 #define fifo_level fifo_level_s5pv210
 
-#include <plat/debug-macro.S>
+#include <debug/samsung.S>
diff --git a/arch/arm/mach-mxs/include/mach/debug-macro.S b/arch/arm/include/debug/mxs.S
index 90c6b7836ad3..d86951551ca1 100644
--- a/arch/arm/mach-mxs/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/mxs.S
@@ -11,16 +11,13 @@
  *
  */
 
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-
 #ifdef CONFIG_DEBUG_IMX23_UART
-#define UART_PADDR      MX23_DUART_BASE_ADDR
+#define UART_PADDR      0x80070000
 #elif defined (CONFIG_DEBUG_IMX28_UART)
-#define UART_PADDR      MX28_DUART_BASE_ADDR
+#define UART_PADDR      0x80074000
 #endif
 
-#define UART_VADDR      MXS_IO_ADDRESS(UART_PADDR)
+#define UART_VADDR      0xfe100000
 
                 .macro  addruart, rp, rv, tmp
                 ldr     \rp, =UART_PADDR        @ physical
diff --git a/arch/arm/mach-nomadik/include/mach/debug-macro.S b/arch/arm/include/debug/nomadik.S
index 735417922ce2..735417922ce2 100644
--- a/arch/arm/mach-nomadik/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/nomadik.S
diff --git a/arch/arm/include/debug/pxa.S b/arch/arm/include/debug/pxa.S
new file mode 100644
index 000000000000..e1e795aa3d7f
--- /dev/null
+++ b/arch/arm/include/debug/pxa.S
@@ -0,0 +1,33 @@
+/*
+ * Early serial output macro for Marvell PXA/MMP SoC
+ *
+ * Copyright (C) 1994-1999 Russell King
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * Copyright (C) 2013 Haojian Zhuang
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#if defined(CONFIG_DEBUG_PXA_UART1)
+#define PXA_UART_REG_PHYS_BASE  0x40100000
+#define PXA_UART_REG_VIRT_BASE  0xf2100000
+#elif defined(CONFIG_DEBUG_MMP_UART2)
+#define PXA_UART_REG_PHYS_BASE  0xd4017000
+#define PXA_UART_REG_VIRT_BASE  0xfe017000
+#elif defined(CONFIG_DEBUG_MMP_UART3)
+#define PXA_UART_REG_PHYS_BASE  0xd4018000
+#define PXA_UART_REG_VIRT_BASE  0xfe018000
+#else
+#error "Select uart for DEBUG_LL"
+#endif
+
+        .macro  addruart, rp, rv, tmp
+        ldr     \rp, =PXA_UART_REG_PHYS_BASE
+        ldr     \rv, =PXA_UART_REG_VIRT_BASE
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/plat-samsung/include/plat/debug-macro.S b/arch/arm/include/debug/samsung.S
index f3a9cff6d5d4..f3a9cff6d5d4 100644
--- a/arch/arm/plat-samsung/include/plat/debug-macro.S
+++ b/arch/arm/include/debug/samsung.S
diff --git a/arch/arm/mach-prima2/include/mach/uart.h b/arch/arm/include/debug/sirf.S
index c10510d01a44..dbf250cf18e6 100644
--- a/arch/arm/mach-prima2/include/mach/uart.h
+++ b/arch/arm/include/debug/sirf.S
@@ -1,15 +1,11 @@
 /*
- * arch/arm/mach-prima2/include/mach/uart.h
+ * arch/arm/mach-prima2/include/mach/debug-macro.S
  *
  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
  *
  * Licensed under GPLv2 or later.
  */
 
-#ifndef __MACH_PRIMA2_SIRFSOC_UART_H
-#define __MACH_PRIMA2_SIRFSOC_UART_H
-
-/* UART-1: used as serial debug port */
 #if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
 #define SIRFSOC_UART1_PA_BASE          0xb0060000
 #elif defined(CONFIG_DEBUG_SIRFMARCO_UART1)
@@ -17,8 +13,8 @@
 #else
 #define SIRFSOC_UART1_PA_BASE          0
 #endif
-#define SIRFSOC_UART1_VA_BASE          SIRFSOC_VA(0x060000)
-#define SIRFSOC_UART1_SIZE              SZ_4K
+
+#define SIRFSOC_UART1_VA_BASE           0xFEC60000
 
 #define SIRFSOC_UART_TXFIFO_STATUS      0x0114
 #define SIRFSOC_UART_TXFIFO_DATA        0x0118
@@ -26,4 +22,21 @@
 #define SIRFSOC_UART1_TXFIFO_FULL                       (1 << 5)
 #define SIRFSOC_UART1_TXFIFO_EMPTY                      (1 << 6)
 
-#endif
+        .macro  addruart, rp, rv, tmp
+        ldr     \rp, =SIRFSOC_UART1_PA_BASE             @ physical
+        ldr     \rv, =SIRFSOC_UART1_VA_BASE             @ virtual
+        .endm
+
+        .macro  senduart,rd,rx
+        str     \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA]
+        .endm
+
+        .macro  busyuart,rd,rx
+        .endm
+
+        .macro  waituart,rd,rx
+1001:   ldr     \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS]
+        tst     \rd, #SIRFSOC_UART1_TXFIFO_EMPTY
+        beq     1001b
+        .endm
+
diff --git a/arch/arm/include/debug/uncompress.h b/arch/arm/include/debug/uncompress.h
new file mode 100644
index 000000000000..0e2949b0fae9
--- /dev/null
+++ b/arch/arm/include/debug/uncompress.h
@@ -0,0 +1,7 @@
+#ifdef CONFIG_DEBUG_UNCOMPRESS
+extern void putc(int c);
+#else
+static inline void putc(int c) {}
+#endif
+static inline void flush(void) {}
+static inline void arch_decomp_setup(void) {}
diff --git a/arch/arm/include/debug/ux500.S b/arch/arm/include/debug/ux500.S
new file mode 100644
index 000000000000..2848857f5b62
--- /dev/null
+++ b/arch/arm/include/debug/ux500.S
@@ -0,0 +1,48 @@
+/*
+ * Debugging macro include header
+ *
+ *  Copyright (C) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+
+#if CONFIG_UX500_DEBUG_UART > 2
+#error Invalid Ux500 debug UART
+#endif
+
+/*
+ * DEBUG_LL only works if only one SOC is built in.  We don't use #else below
+ * in order to get "__UX500_UART redefined" warnings if more than one SOC is
+ * built, so that there's some hint during the build that something is wrong.
+ */
+
+#ifdef CONFIG_UX500_SOC_DB8500
+#define U8500_UART0_PHYS_BASE   (0x80120000)
+#define U8500_UART1_PHYS_BASE   (0x80121000)
+#define U8500_UART2_PHYS_BASE   (0x80007000)
+#define U8500_UART0_VIRT_BASE   (0xa8120000)
+#define U8500_UART1_VIRT_BASE   (0xa8121000)
+#define U8500_UART2_VIRT_BASE   (0xa8007000)
+#define __UX500_PHYS_UART(n)    U8500_UART##n##_PHYS_BASE
+#define __UX500_VIRT_UART(n)    U8500_UART##n##_VIRT_BASE
+#endif
+
+#if !defined(__UX500_PHYS_UART) || !defined(__UX500_VIRT_UART)
+#error Unknown SOC
+#endif
+
+#define UX500_PHYS_UART(n)      __UX500_PHYS_UART(n)
+#define UX500_VIRT_UART(n)      __UX500_VIRT_UART(n)
+#define UART_PHYS_BASE  UX500_PHYS_UART(CONFIG_UX500_DEBUG_UART)
+#define UART_VIRT_BASE  UX500_VIRT_UART(CONFIG_UX500_DEBUG_UART)
+
+        .macro  addruart, rp, rv, tmp
+        ldr     \rp, =UART_PHYS_BASE            @ no, physical address
+        ldr     \rv, =UART_VIRT_BASE            @ yes, virtual address
+        .endm
+
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h
index 023bfeb367bf..c1ee007523d7 100644
--- a/arch/arm/include/uapi/asm/kvm.h
+++ b/arch/arm/include/uapi/asm/kvm.h
@@ -53,12 +53,12 @@
 #define KVM_ARM_FIQ_spsr        fiq_regs[7]
 
 struct kvm_regs {
-        struct pt_regs usr_regs;/* R0_usr - R14_usr, PC, CPSR */
-        __u32 svc_regs[3];      /* SP_svc, LR_svc, SPSR_svc */
-        __u32 abt_regs[3];      /* SP_abt, LR_abt, SPSR_abt */
-        __u32 und_regs[3];      /* SP_und, LR_und, SPSR_und */
-        __u32 irq_regs[3];      /* SP_irq, LR_irq, SPSR_irq */
-        __u32 fiq_regs[8];      /* R8_fiq - R14_fiq, SPSR_fiq */
+        struct pt_regs usr_regs;        /* R0_usr - R14_usr, PC, CPSR */
+        unsigned long svc_regs[3];      /* SP_svc, LR_svc, SPSR_svc */
+        unsigned long abt_regs[3];      /* SP_abt, LR_abt, SPSR_abt */
+        unsigned long und_regs[3];      /* SP_und, LR_und, SPSR_und */
+        unsigned long irq_regs[3];      /* SP_irq, LR_irq, SPSR_irq */
+        unsigned long fiq_regs[8];      /* R8_fiq - R14_fiq, SPSR_fiq */
 };
 
 /* Supported Processor Types */
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 923eec7105cf..ee68cce6b48e 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -149,12 +149,16 @@ int main(void)
   DEFINE(DMA_BIDIRECTIONAL,     DMA_BIDIRECTIONAL);
   DEFINE(DMA_TO_DEVICE,         DMA_TO_DEVICE);
   DEFINE(DMA_FROM_DEVICE,       DMA_FROM_DEVICE);
+  BLANK();
+  DEFINE(CACHE_WRITEBACK_ORDER, __CACHE_WRITEBACK_ORDER);
+  DEFINE(CACHE_WRITEBACK_GRANULE, __CACHE_WRITEBACK_GRANULE);
+  BLANK();
 #ifdef CONFIG_KVM_ARM_HOST
   DEFINE(VCPU_KVM,              offsetof(struct kvm_vcpu, kvm));
   DEFINE(VCPU_MIDR,             offsetof(struct kvm_vcpu, arch.midr));
   DEFINE(VCPU_CP15,             offsetof(struct kvm_vcpu, arch.cp15));
   DEFINE(VCPU_VFP_GUEST,        offsetof(struct kvm_vcpu, arch.vfp_guest));
-  DEFINE(VCPU_VFP_HOST,         offsetof(struct kvm_vcpu, arch.vfp_host));
+  DEFINE(VCPU_VFP_HOST,         offsetof(struct kvm_vcpu, arch.host_cpu_context));
   DEFINE(VCPU_REGS,             offsetof(struct kvm_vcpu, arch.regs));
   DEFINE(VCPU_USR_REGS,         offsetof(struct kvm_vcpu, arch.regs.usr_regs));
   DEFINE(VCPU_SVC_REGS,         offsetof(struct kvm_vcpu, arch.regs.svc_regs));
@@ -165,10 +169,10 @@ int main(void)
   DEFINE(VCPU_PC,               offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_pc));
   DEFINE(VCPU_CPSR,             offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_cpsr));
   DEFINE(VCPU_IRQ_LINES,        offsetof(struct kvm_vcpu, arch.irq_lines));
-  DEFINE(VCPU_HSR,              offsetof(struct kvm_vcpu, arch.hsr));
-  DEFINE(VCPU_HxFAR,            offsetof(struct kvm_vcpu, arch.hxfar));
-  DEFINE(VCPU_HPFAR,            offsetof(struct kvm_vcpu, arch.hpfar));
-  DEFINE(VCPU_HYP_PC,           offsetof(struct kvm_vcpu, arch.hyp_pc));
+  DEFINE(VCPU_HSR,              offsetof(struct kvm_vcpu, arch.fault.hsr));
+  DEFINE(VCPU_HxFAR,            offsetof(struct kvm_vcpu, arch.fault.hxfar));
+  DEFINE(VCPU_HPFAR,            offsetof(struct kvm_vcpu, arch.fault.hpfar));
+  DEFINE(VCPU_HYP_PC,           offsetof(struct kvm_vcpu, arch.fault.hyp_pc));
 #ifdef CONFIG_KVM_ARM_VGIC
   DEFINE(VCPU_VGIC_CPU,         offsetof(struct kvm_vcpu, arch.vgic_cpu));
   DEFINE(VGIC_CPU_HCR,          offsetof(struct vgic_cpu, vgic_hcr));
diff --git a/arch/arm/kernel/atags_proc.c b/arch/arm/kernel/atags_proc.c
index 42a1a1415fa6..c7ff8073416f 100644
--- a/arch/arm/kernel/atags_proc.c
+++ b/arch/arm/kernel/atags_proc.c
@@ -9,24 +9,18 @@ struct buffer {
         char data[];
 };
 
-static int
-read_buffer(char* page, char** start, off_t off, int count,
-        int* eof, void* data)
+static ssize_t atags_read(struct file *file, char __user *buf,
+                          size_t count, loff_t *ppos)
 {
-        struct buffer *buffer = (struct buffer *)data;
-
-        if (off >= buffer->size) {
-                *eof = 1;
-                return 0;
-        }
-
-        count = min((int) (buffer->size - off), count);
-
-        memcpy(page, &buffer->data[off], count);
-
-        return count;
+        struct buffer *b = PDE_DATA(file_inode(file));
+        return simple_read_from_buffer(buf, count, ppos, b->data, b->size);
 }
 
+static const struct file_operations atags_fops = {
+        .read = atags_read,
+        .llseek = default_llseek,
+};
+
 #define BOOT_PARAMS_SIZE 1536
 static char __initdata atags_copy[BOOT_PARAMS_SIZE];
 
@@ -66,9 +60,7 @@ static int __init init_atags_procfs(void)
         b->size = size;
         memcpy(b->data, atags_copy, size);
 
-        tags_entry = create_proc_read_entry("atags", 0400,
-                        NULL, read_buffer, b);
-
+        tags_entry = proc_create_data("atags", 0400, NULL, &atags_fops, b);
         if (!tags_entry)
                 goto nomem;
 
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index a1f73b502ef0..b2ed73c45489 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -462,6 +462,7 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
                 sys->busnr   = busnr;
                 sys->swizzle = hw->swizzle;
                 sys->map_irq = hw->map_irq;
+                sys->align_resource = hw->align_resource;
                 INIT_LIST_HEAD(&sys->resources);
 
                 if (hw->private_data)
@@ -574,6 +575,8 @@ char * __init pcibios_setup(char *str)
 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
                                 resource_size_t size, resource_size_t align)
 {
+        struct pci_dev *dev = data;
+        struct pci_sys_data *sys = dev->sysdata;
         resource_size_t start = res->start;
 
         if (res->flags & IORESOURCE_IO && start & 0x300)
@@ -581,6 +584,9 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
 
         start = (start + align - 1) & ~(align - 1);
 
+        if (sys->align_resource)
+                return sys->align_resource(dev, res, start, size, align);
+
         return start;
 }
 
diff --git a/arch/arm/kernel/early_printk.c b/arch/arm/kernel/early_printk.c
index 85aa2b292692..43076536965c 100644
--- a/arch/arm/kernel/early_printk.c
+++ b/arch/arm/kernel/early_printk.c
@@ -29,28 +29,17 @@ static void early_console_write(struct console *con, const char *s, unsigned n)
         early_write(s, n);
 }
 
-static struct console early_console = {
+static struct console early_console_dev = {
         .name =         "earlycon",
         .write =        early_console_write,
         .flags =        CON_PRINTBUFFER | CON_BOOT,
         .index =        -1,
 };
 
-asmlinkage void early_printk(const char *fmt, ...)
-{
-        char buf[512];
-        int n;
-        va_list ap;
-
-        va_start(ap, fmt);
-        n = vscnprintf(buf, sizeof(buf), fmt, ap);
-        early_write(buf, n);
-        va_end(ap);
-}
-
 static int __init setup_early_printk(char *buf)
 {
-        register_console(&early_console);
+        early_console = &early_console_dev;
+        register_console(&early_console_dev);
         return 0;
 }
 
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 0f82098c9bfe..582b405befc5 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -192,18 +192,6 @@ __dabt_svc:
         svc_entry
         mov     r2, sp
         dabt_helper
-
-        @
-        @ IRQs off again before pulling preserved data off the stack
-        @
-        disable_irq_notrace
-
-#ifdef CONFIG_TRACE_IRQFLAGS
-        tst     r5, #PSR_I_BIT
-        bleq    trace_hardirqs_on
-        tst     r5, #PSR_I_BIT
-        blne    trace_hardirqs_off
-#endif
         svc_exit r5                             @ return from exception
  UNWIND(.fnend          )
 ENDPROC(__dabt_svc)
@@ -223,12 +211,7 @@ __irq_svc:
         blne    svc_preempt
 #endif
 
-#ifdef CONFIG_TRACE_IRQFLAGS
-        @ The parent context IRQs must have been enabled to get here in
-        @ the first place, so there's no point checking the PSR I bit.
-        bl      trace_hardirqs_on
-#endif
-        svc_exit r5                             @ return from exception
+        svc_exit r5, irq = 1                    @ return from exception
  UNWIND(.fnend          )
 ENDPROC(__irq_svc)
 
@@ -295,22 +278,8 @@ __und_svc_fault:
         mov     r0, sp                          @ struct pt_regs *regs
         bl      __und_fault
 
-        @
-        @ IRQs off again before pulling preserved data off the stack
-        @
 __und_svc_finish:
-        disable_irq_notrace
-
-        @
-        @ restore SPSR and restart the instruction
-        @
         ldr     r5, [sp, #S_PSR]                @ Get SVC cpsr
-#ifdef CONFIG_TRACE_IRQFLAGS
-        tst     r5, #PSR_I_BIT
-        bleq    trace_hardirqs_on
-        tst     r5, #PSR_I_BIT
-        blne    trace_hardirqs_off
-#endif
         svc_exit r5                             @ return from exception
  UNWIND(.fnend          )
 ENDPROC(__und_svc)
@@ -320,18 +289,6 @@ __pabt_svc:
         svc_entry
         mov     r2, sp                          @ regs
         pabt_helper
-
-        @
-        @ IRQs off again before pulling preserved data off the stack
-        @
-        disable_irq_notrace
-
-#ifdef CONFIG_TRACE_IRQFLAGS
-        tst     r5, #PSR_I_BIT
-        bleq    trace_hardirqs_on
-        tst     r5, #PSR_I_BIT
-        blne    trace_hardirqs_off
-#endif
         svc_exit r5                             @ return from exception
  UNWIND(.fnend          )
 ENDPROC(__pabt_svc)
@@ -396,6 +353,7 @@ ENDPROC(__pabt_svc)
 #ifdef CONFIG_IRQSOFF_TRACER
         bl      trace_hardirqs_off
 #endif
+        ct_user_exit save = 0
         .endm
 
         .macro  kuser_cmpxchg_check
@@ -562,21 +520,21 @@ ENDPROC(__und_usr)
         @ Fall-through from Thumb-2 __und_usr
         @
 #ifdef CONFIG_NEON
+        get_thread_info r10                     @ get current thread
         adr     r6, .LCneon_thumb_opcodes
         b       2f
 #endif
 call_fpe:
+        get_thread_info r10                     @ get current thread
 #ifdef CONFIG_NEON
         adr     r6, .LCneon_arm_opcodes
-2:
-        ldr     r7, [r6], #4                    @ mask value
-        cmp     r7, #0                          @ end mask?
-        beq     1f
-        and     r8, r0, r7
+2:      ldr     r5, [r6], #4                    @ mask value
         ldr     r7, [r6], #4                    @ opcode bits matching in mask
+        cmp     r5, #0                          @ end mask?
+        beq     1f
+        and     r8, r0, r5
         cmp     r8, r7                          @ NEON instruction?
         bne     2b
-        get_thread_info r10
         mov     r7, #1
         strb    r7, [r10, #TI_USED_CP + 10]     @ mark CP#10 as used
         strb    r7, [r10, #TI_USED_CP + 11]     @ mark CP#11 as used
@@ -586,7 +544,6 @@ call_fpe:
         tst     r0, #0x08000000                 @ only CDP/CPRT/LDC/STC have bit 27
         tstne   r0, #0x04000000                 @ bit 26 set on both ARM and Thumb-2
         moveq   pc, lr
-        get_thread_info r10                     @ get current thread
         and     r8, r0, #0x00000f00             @ mask out CP number
  THUMB( lsr     r8, r8, #8              )
         mov     r7, #1
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index fefd7f971437..bc5bc0a97131 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -35,12 +35,11 @@ ret_fast_syscall:
         ldr     r1, [tsk, #TI_FLAGS]
         tst     r1, #_TIF_WORK_MASK
         bne     fast_work_pending
-#if defined(CONFIG_IRQSOFF_TRACER)
         asm_trace_hardirqs_on
-#endif
 
         /* perform architecture specific actions before user return */
         arch_ret_to_user r1, lr
+        ct_user_enter
 
         restore_user_regs fast = 1, offset = S_OFF
  UNWIND(.fnend          )
@@ -71,11 +70,11 @@ ENTRY(ret_to_user_from_irq)
         tst     r1, #_TIF_WORK_MASK
         bne     work_pending
 no_work_pending:
-#if defined(CONFIG_IRQSOFF_TRACER)
         asm_trace_hardirqs_on
-#endif
+
         /* perform architecture specific actions before user return */
         arch_ret_to_user r1, lr
+        ct_user_enter save = 0
 
         restore_user_regs fast = 0, offset = 0
 ENDPROC(ret_to_user_from_irq)
@@ -406,6 +405,7 @@ ENTRY(vector_swi)
         mcr     p15, 0, ip, c1, c0              @ update control register
 #endif
         enable_irq
+        ct_user_exit
 
         get_thread_info tsk
         adr     tbl, sys_call_table             @ load syscall table pointer
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 9a8531eadd3d..160f3376ba6d 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -74,7 +74,24 @@
         .endm
 
 #ifndef CONFIG_THUMB2_KERNEL
-        .macro  svc_exit, rpsr
+        .macro  svc_exit, rpsr, irq = 0
+        .if     \irq != 0
+        @ IRQs already off
+#ifdef CONFIG_TRACE_IRQFLAGS
+        @ The parent context IRQs must have been enabled to get here in
+        @ the first place, so there's no point checking the PSR I bit.
+        bl      trace_hardirqs_on
+#endif
+        .else
+        @ IRQs off again before pulling preserved data off the stack
+        disable_irq_notrace
+#ifdef CONFIG_TRACE_IRQFLAGS
+        tst     \rpsr, #PSR_I_BIT
+        bleq    trace_hardirqs_on
+        tst     \rpsr, #PSR_I_BIT
+        blne    trace_hardirqs_off
+#endif
+        .endif
         msr     spsr_cxsf, \rpsr
 #if defined(CONFIG_CPU_V6)
         ldr     r0, [sp]
@@ -120,7 +137,24 @@
         mov     pc, \reg
         .endm
 #else   /* CONFIG_THUMB2_KERNEL */
-        .macro  svc_exit, rpsr
+        .macro  svc_exit, rpsr, irq = 0
+        .if     \irq != 0
+        @ IRQs already off
+#ifdef CONFIG_TRACE_IRQFLAGS
+        @ The parent context IRQs must have been enabled to get here in
+        @ the first place, so there's no point checking the PSR I bit.
+        bl      trace_hardirqs_on
+#endif
+        .else
+        @ IRQs off again before pulling preserved data off the stack
+        disable_irq_notrace
+#ifdef CONFIG_TRACE_IRQFLAGS
+        tst     \rpsr, #PSR_I_BIT
+        bleq    trace_hardirqs_on
+        tst     \rpsr, #PSR_I_BIT
+        blne    trace_hardirqs_off
+#endif
+        .endif
         ldr     lr, [sp, #S_SP]                 @ top of the stack
         ldrd    r0, r1, [sp, #S_LR]             @ calling lr and pc
         clrex                                   @ clear the exclusive monitor
@@ -164,6 +198,34 @@
 #endif  /* !CONFIG_THUMB2_KERNEL */
 
 /*
+ * Context tracking subsystem.  Used to instrument transitions
+ * between user and kernel mode.
+ */
+        .macro ct_user_exit, save = 1
+#ifdef CONFIG_CONTEXT_TRACKING
+        .if     \save
+        stmdb   sp!, {r0-r3, ip, lr}
+        bl      user_exit
+        ldmia   sp!, {r0-r3, ip, lr}
+        .else
+        bl      user_exit
+        .endif
+#endif
+        .endm
+
+        .macro ct_user_enter, save = 1
+#ifdef CONFIG_CONTEXT_TRACKING
+        .if     \save
+        stmdb   sp!, {r0-r3, ip, lr}
+        bl      user_enter
+        ldmia   sp!, {r0-r3, ip, lr}
+        .else
+        bl      user_enter
+        .endif
+#endif
+        .endm
+
+/*
  * These are the registers used in the syscall handler, and allow us to
  * have in theory up to 7 arguments to a function - r0 to r6.
  *
diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c
index 9b6de8c988f3..8ff0ecdc637f 100644
--- a/arch/arm/kernel/etm.c
+++ b/arch/arm/kernel/etm.c
@@ -254,7 +254,7 @@ static void sysrq_etm_dump(int key)
 
 static struct sysrq_key_op sysrq_etm_op = {
         .handler = sysrq_etm_dump,
-        .help_msg = "ETM buffer dump",
+        .help_msg = "etm-buffer-dump(v)",
         .action_msg = "etm",
 };
 
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index 854bd22380d3..5b391a689b47 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -98,8 +98,9 @@ __mmap_switched:
         str     r9, [r4]                        @ Save processor ID
         str     r1, [r5]                        @ Save machine type
         str     r2, [r6]                        @ Save atags pointer
-        bic     r4, r0, #CR_A                   @ Clear 'A' bit
-        stmia   r7, {r0, r4}                    @ Save control register values
+        cmp     r7, #0
+        bicne   r4, r0, #CR_A                   @ Clear 'A' bit
+        stmneia r7, {r0, r4}                    @ Save control register values
         b       start_kernel
 ENDPROC(__mmap_switched)
 
@@ -113,7 +114,11 @@ __mmap_switched_data:
         .long   processor_id                    @ r4
         .long   __machine_arch_type             @ r5
         .long   __atags_pointer                 @ r6
+#ifdef CONFIG_CPU_CP15
         .long   cr_alignment                    @ r7
+#else
+        .long   0                               @ r7
+#endif
         .long   init_thread_union + THREAD_START_SP @ sp
         .size   __mmap_switched_data, . - __mmap_switched_data
 
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 2c228a07e58c..6a2e09c952c7 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -32,15 +32,21 @@
  * numbers for r1.
  *
  */
-        .arm
 
         __HEAD
+
+#ifdef CONFIG_CPU_THUMBONLY
+        .thumb
+ENTRY(stext)
+#else
+        .arm
 ENTRY(stext)
 
  THUMB( adr     r9, BSYM(1f)    )       @ Kernel is always entered in ARM.
  THUMB( bx      r9              )       @ If this is a Thumb-2 kernel,
  THUMB( .thumb                  )       @ switch to Thumb now.
  THUMB(1:                       )
+#endif
 
         setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
                                                 @ and irqs disabled
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 8e4ef4c83a74..9723d17b8f38 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -26,6 +26,7 @@
 #include <linux/ioport.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/irqchip.h>
 #include <linux/random.h>
 #include <linux/smp.h>
 #include <linux/init.h>
@@ -114,7 +115,10 @@ EXPORT_SYMBOL_GPL(set_irq_flags);
 
 void __init init_IRQ(void)
 {
-        machine_desc->init_irq();
+        if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq)
+                irqchip_init();
+        else
+                machine_desc->init_irq();
 }
 
 #ifdef CONFIG_MULTI_IRQ_HANDLER
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 047d3e40e470..f21970316836 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -57,38 +57,6 @@ static const char *isa_modes[] = {
   "ARM" , "Thumb" , "Jazelle", "ThumbEE"
 };
 
-static volatile int hlt_counter;
-
-void disable_hlt(void)
-{
-        hlt_counter++;
-}
-
-EXPORT_SYMBOL(disable_hlt);
-
-void enable_hlt(void)
-{
-        hlt_counter--;
-        BUG_ON(hlt_counter < 0);
-}
-
-EXPORT_SYMBOL(enable_hlt);
-
-static int __init nohlt_setup(char *__unused)
-{
-        hlt_counter = 1;
-        return 1;
-}
-
-static int __init hlt_setup(char *__unused)
-{
-        hlt_counter = 0;
-        return 1;
-}
-
-__setup("nohlt", nohlt_setup);
-__setup("hlt", hlt_setup);
-
 extern void call_with_stack(void (*fn)(void *), void *arg, void *sp);
 typedef void (*phys_reset_t)(unsigned long);
 
@@ -172,54 +140,38 @@ static void default_idle(void)
         local_irq_enable();
 }
 
-/*
- * The idle thread.
- * We always respect 'hlt_counter' to prevent low power idle.
- */
-void cpu_idle(void)
+void arch_cpu_idle_prepare(void)
 {
         local_fiq_enable();
+}
 
-        /* endless idle loop with no priority at all */
-        while (1) {
-                tick_nohz_idle_enter();
-                rcu_idle_enter();
-                ledtrig_cpu(CPU_LED_IDLE_START);
-                while (!need_resched()) {
-#ifdef CONFIG_HOTPLUG_CPU
-                        if (cpu_is_offline(smp_processor_id()))
-                                cpu_die();
+void arch_cpu_idle_enter(void)
+{
+        ledtrig_cpu(CPU_LED_IDLE_START);
+#ifdef CONFIG_PL310_ERRATA_769419
+        wmb();
 #endif
+}
 
-                        /*
-                         * We need to disable interrupts here
-                         * to ensure we don't miss a wakeup call.
-                         */
-                        local_irq_disable();
-#ifdef CONFIG_PL310_ERRATA_769419
-                        wmb();
+void arch_cpu_idle_exit(void)
+{
+        ledtrig_cpu(CPU_LED_IDLE_END);
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+void arch_cpu_idle_dead(void)
+{
+        cpu_die();
+}
 #endif
-                        if (hlt_counter) {
-                                local_irq_enable();
-                                cpu_relax();
-                        } else if (!need_resched()) {
-                                stop_critical_timings();
-                                if (cpuidle_idle_call())
-                                        default_idle();
-                                start_critical_timings();
-                                /*
-                                 * default_idle functions must always
-                                 * return with IRQs enabled.
-                                 */
-                                WARN_ON(irqs_disabled());
-                        } else
-                                local_irq_enable();
-                }
-                ledtrig_cpu(CPU_LED_IDLE_END);
-                rcu_idle_exit();
-                tick_nohz_idle_exit();
-                schedule_preempt_disabled();
-        }
+
+/*
+ * Called from the core idle loop.
+ */
+void arch_cpu_idle(void)
+{
+        if (cpuidle_idle_call())
+                default_idle();
 }
 
 static char reboot_mode = 'h';
@@ -273,11 +225,8 @@ void __show_regs(struct pt_regs *regs)
         unsigned long flags;
         char buf[64];
 
-        printk("CPU: %d    %s  (%s %.*s)\n",
-                raw_smp_processor_id(), print_tainted(),
-                init_utsname()->release,
-                (int)strcspn(init_utsname()->version, " "),
-                init_utsname()->version);
+        show_regs_print_info(KERN_DEFAULT);
+
         print_symbol("PC is at %s\n", instruction_pointer(regs));
         print_symbol("LR is at %s\n", regs->ARM_lr);
         printk("pc : [<%08lx>]    lr : [<%08lx>]    psr: %08lx\n"
@@ -332,7 +281,6 @@ void __show_regs(struct pt_regs *regs)
 void show_regs(struct pt_regs * regs)
 {
         printk("\n");
-        printk("Pid: %d, comm: %20s\n", task_pid_nr(current), current->comm);
         __show_regs(regs);
         dump_stack();
 }
@@ -459,15 +407,16 @@ unsigned long arch_randomize_brk(struct mm_struct *mm)
  * atomic helpers and the signal restart code. Insert it into the
  * gate_vma so that it is visible through ptrace and /proc/<pid>/mem.
  */
-static struct vm_area_struct gate_vma;
+static struct vm_area_struct gate_vma = {
+        .vm_start       = 0xffff0000,
+        .vm_end         = 0xffff0000 + PAGE_SIZE,
+        .vm_flags       = VM_READ | VM_EXEC | VM_MAYREAD | VM_MAYEXEC,
+        .vm_mm          = &init_mm,
+};
 
 static int __init gate_vma_init(void)
 {
-        gate_vma.vm_start       = 0xffff0000;
-        gate_vma.vm_end         = 0xffff0000 + PAGE_SIZE;
-        gate_vma.vm_page_prot   = PAGE_READONLY_EXEC;
-        gate_vma.vm_flags       = VM_READ | VM_EXEC |
-                                  VM_MAYREAD | VM_MAYEXEC;
+        gate_vma.vm_page_prot = PAGE_READONLY_EXEC;
         return 0;
 }
 arch_initcall(gate_vma_init);
diff --git a/arch/arm/kernel/return_address.c b/arch/arm/kernel/return_address.c
index 8085417555dd..fafedd86885d 100644
--- a/arch/arm/kernel/return_address.c
+++ b/arch/arm/kernel/return_address.c
@@ -26,7 +26,7 @@ static int save_return_addr(struct stackframe *frame, void *d)
         struct return_address_data *data = d;
 
         if (!data->level) {
-                data->addr = (void *)frame->lr;
+                data->addr = (void *)frame->pc;
 
                 return 1;
         } else {
@@ -41,7 +41,8 @@ void *return_address(unsigned int level)
         struct stackframe frame;
         register unsigned long current_sp asm ("sp");
 
-        data.level = level + 1;
+        data.level = level + 2;
+        data.addr = NULL;
 
         frame.fp = (unsigned long)__builtin_frame_address(0);
         frame.sp = current_sp;
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 234e339196c0..728007c4a2b7 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -290,10 +290,10 @@ static int cpu_has_aliasing_icache(unsigned int arch)
 
 static void __init cacheid_init(void)
 {
-        unsigned int cachetype = read_cpuid_cachetype();
         unsigned int arch = cpu_architecture();
 
         if (arch >= CPU_ARCH_ARMv6) {
+                unsigned int cachetype = read_cpuid_cachetype();
                 if ((cachetype & (7 << 29)) == 4 << 29) {
                         /* ARMv7 register format */
                         arch = CPU_ARCH_ARMv7;
@@ -389,7 +389,7 @@ static void __init feat_v6_fixup(void)
  *
  * cpu_init sets up the per-CPU stacks.
  */
-void cpu_init(void)
+void notrace cpu_init(void)
 {
         unsigned int cpu = smp_processor_id();
         struct stack *stk = &stacks[cpu];
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 1f2ccccaf009..47ab90563bf4 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -211,6 +211,13 @@ void __cpuinit __cpu_die(unsigned int cpu)
         }
         printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
 
+        /*
+         * platform_cpu_kill() is generally expected to do the powering off
+         * and/or cutting of clocks to the dying CPU.  Optionally, this may
+         * be done by the CPU which is dying in preference to supporting
+         * this call, but that means there is _no_ synchronisation between
+         * the requesting CPU and the dying CPU actually losing power.
+         */
         if (!platform_cpu_kill(cpu))
                 printk("CPU%u: unable to kill\n", cpu);
 }
@@ -230,14 +237,41 @@ void __ref cpu_die(void)
         idle_task_exit();
 
         local_irq_disable();
-        mb();
 
-        /* Tell __cpu_die() that this CPU is now safe to dispose of */
+        /*
+         * Flush the data out of the L1 cache for this CPU.  This must be
+         * before the completion to ensure that data is safely written out
+         * before platform_cpu_kill() gets called - which may disable
+         * *this* CPU and power down its cache.
+         */
+        flush_cache_louis();
+
+        /*
+         * Tell __cpu_die() that this CPU is now safe to dispose of.  Once
+         * this returns, power and/or clocks can be removed at any point
+         * from this CPU and its cache by platform_cpu_kill().
+         */
         RCU_NONIDLE(complete(&cpu_died));
 
         /*
-         * actual CPU shutdown procedure is at least platform (if not
-         * CPU) specific.
+         * Ensure that the cache lines associated with that completion are
+         * written out.  This covers the case where _this_ CPU is doing the
+         * powering down, to ensure that the completion is visible to the
+         * CPU waiting for this one.
+         */
+        flush_cache_louis();
+
+        /*
+         * The actual CPU shutdown procedure is at least platform (if not
+         * CPU) specific.  This may remove power, or it may simply spin.
+         *
+         * Platforms are generally expected *NOT* to return from this call,
+         * although there are some which do because they have no way to
+         * power down the CPU.  These platforms are the _only_ reason we
+         * have a return path which uses the fragment of assembly below.
+         *
+         * The return path should not be used for platforms which can
+         * power off the CPU.
          */
         if (smp_ops.cpu_die)
                 smp_ops.cpu_die(cpu);
@@ -336,7 +370,7 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
         /*
          * OK, it's off to the idle thread for us
          */
-        cpu_idle();
+        cpu_startup_entry(CPUHP_ONLINE);
 }
 
 void __init smp_cpus_done(unsigned int max_cpus)
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index 45eac87ed66a..5bc1a63284e3 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -41,7 +41,7 @@ void scu_enable(void __iomem *scu_base)
 
 #ifdef CONFIG_ARM_ERRATA_764369
         /* Cortex-A9 only */
-        if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
+        if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc090) {
                 scu_ctrl = __raw_readl(scu_base + 0x30);
                 if (!(scu_ctrl & 1))
                         __raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c
index e82e1d248772..9a52a07aa40e 100644
--- a/arch/arm/kernel/smp_tlb.c
+++ b/arch/arm/kernel/smp_tlb.c
@@ -98,21 +98,21 @@ static void broadcast_tlb_a15_erratum(void)
                 return;
 
         dummy_flush_tlb_a15_erratum();
-        smp_call_function_many(cpu_online_mask, ipi_flush_tlb_a15_erratum,
-                               NULL, 1);
+        smp_call_function(ipi_flush_tlb_a15_erratum, NULL, 1);
 }
 
 static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
 {
-        int cpu;
+        int cpu, this_cpu;
         cpumask_t mask = { CPU_BITS_NONE };
 
         if (!erratum_a15_798181())
                 return;
 
         dummy_flush_tlb_a15_erratum();
+        this_cpu = get_cpu();
         for_each_online_cpu(cpu) {
-                if (cpu == smp_processor_id())
+                if (cpu == this_cpu)
                         continue;
                 /*
                  * We only need to send an IPI if the other CPUs are running
@@ -127,6 +127,7 @@ static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
                         cpumask_set_cpu(cpu, &mask);
         }
         smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1);
+        put_cpu();
 }
 
 void flush_tlb_all(void)
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 3f2565037480..90525d9d290b 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -362,25 +362,13 @@ int __init twd_local_timer_register(struct twd_local_timer *tlt)
 }
 
 #ifdef CONFIG_OF
-const static struct of_device_id twd_of_match[] __initconst = {
-        { .compatible = "arm,cortex-a9-twd-timer",      },
-        { .compatible = "arm,cortex-a5-twd-timer",      },
-        { .compatible = "arm,arm11mp-twd-timer",        },
-        { },
-};
-
-void __init twd_local_timer_of_register(void)
+static void __init twd_local_timer_of_register(struct device_node *np)
 {
-        struct device_node *np;
         int err;
 
         if (!is_smp() || !setup_max_cpus)
                 return;
 
-        np = of_find_matching_node(NULL, twd_of_match);
-        if (!np)
-                return;
-
         twd_ppi = irq_of_parse_and_map(np, 0);
         if (!twd_ppi) {
                 err = -EINVAL;
@@ -398,4 +386,7 @@ void __init twd_local_timer_of_register(void)
 out:
         WARN(err, "twd_local_timer_of_register failed (%d)\n", err);
 }
+CLOCKSOURCE_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register);
+CLOCKSOURCE_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register);
+CLOCKSOURCE_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register);
 #endif
diff --git a/arch/arm/kernel/swp_emulate.c b/arch/arm/kernel/swp_emulate.c
index ab1017bd1667..b1b89882b113 100644
--- a/arch/arm/kernel/swp_emulate.c
+++ b/arch/arm/kernel/swp_emulate.c
@@ -21,6 +21,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/proc_fs.h>
+#include <linux/seq_file.h>
 #include <linux/sched.h>
 #include <linux/syscalls.h>
 #include <linux/perf_event.h>
@@ -79,27 +80,27 @@ static unsigned long abtcounter;
 static pid_t         previous_pid;
 
 #ifdef CONFIG_PROC_FS
-static int proc_read_status(char *page, char **start, off_t off, int count,
-                            int *eof, void *data)
+static int proc_status_show(struct seq_file *m, void *v)
 {
-        char *p = page;
-        int len;
-
-        p += sprintf(p, "Emulated SWP:\t\t%lu\n", swpcounter);
-        p += sprintf(p, "Emulated SWPB:\t\t%lu\n", swpbcounter);
-        p += sprintf(p, "Aborted SWP{B}:\t\t%lu\n", abtcounter);
+        seq_printf(m, "Emulated SWP:\t\t%lu\n", swpcounter);
+        seq_printf(m, "Emulated SWPB:\t\t%lu\n", swpbcounter);
+        seq_printf(m, "Aborted SWP{B}:\t\t%lu\n", abtcounter);
         if (previous_pid != 0)
-                p += sprintf(p, "Last process:\t\t%d\n", previous_pid);
-
-        len = (p - page) - off;
-        if (len < 0)
-                len = 0;
-
-        *eof = (len <= count) ? 1 : 0;
-        *start = page + off;
+                seq_printf(m, "Last process:\t\t%d\n", previous_pid);
+        return 0;
+}
 
-        return len;
+static int proc_status_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, proc_status_show, PDE_DATA(inode));
 }
+
+static const struct file_operations proc_status_fops = {
+        .open           = proc_status_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
 #endif
 
 /*
@@ -266,14 +267,8 @@ static struct undef_hook swp_hook = {
 static int __init swp_emulation_init(void)
 {
 #ifdef CONFIG_PROC_FS
-        struct proc_dir_entry *res;
-
-        res = create_proc_entry("cpu/swp_emulation", S_IRUGO, NULL);
-
-        if (!res)
+        if (!proc_create("cpu/swp_emulation", S_IRUGO, NULL, &proc_status_fops))
                 return -ENOMEM;
-
-        res->read_proc = proc_read_status;
 #endif /* CONFIG_PROC_FS */
 
         printk(KERN_NOTICE "Registering SWP/SWPB emulation handler\n");
diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
index 79282ebcd939..f10316b4ecdc 100644
--- a/arch/arm/kernel/topology.c
+++ b/arch/arm/kernel/topology.c
@@ -100,7 +100,7 @@ static void __init parse_dt_topology(void)
         int alloc_size, cpu = 0;
 
         alloc_size = nr_cpu_ids * sizeof(struct cpu_capacity);
-        cpu_capacity = (struct cpu_capacity *)kzalloc(alloc_size, GFP_NOWAIT);
+        cpu_capacity = kzalloc(alloc_size, GFP_NOWAIT);
 
         while ((cn = of_find_node_by_type(cn, "cpu"))) {
                 const u32 *rate, *reg;
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 1c089119b2d7..18b32e8e4497 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -204,13 +204,6 @@ static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
 }
 #endif
 
-void dump_stack(void)
-{
-        dump_backtrace(NULL, NULL);
-}
-
-EXPORT_SYMBOL(dump_stack);
-
 void show_stack(struct task_struct *tsk, unsigned long *sp)
 {
         dump_backtrace(NULL, tsk);
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b571484e9f03..a871b8e00fca 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -20,7 +20,7 @@
         VMLINUX_SYMBOL(__idmap_text_start) = .;                         \
         *(.idmap.text)                                                  \
         VMLINUX_SYMBOL(__idmap_text_end) = .;                           \
-        ALIGN_FUNCTION();                                               \
+        . = ALIGN(32);                                                  \
         VMLINUX_SYMBOL(__hyp_idmap_text_start) = .;                     \
         *(.hyp.idmap.text)                                              \
         VMLINUX_SYMBOL(__hyp_idmap_text_end) = .;
@@ -315,3 +315,8 @@ SECTIONS
  */
 ASSERT((__proc_info_end - __proc_info_begin), "missing CPU support")
 ASSERT((__arch_info_end - __arch_info_begin), "no machine record defined")
+/*
+ * The HYP init code can't be more than a page long.
+ * The above comment applies as well.
+ */
+ASSERT(((__hyp_idmap_text_end - __hyp_idmap_text_start) <= PAGE_SIZE), "HYP init code too big")
diff --git a/arch/arm/kvm/Kconfig b/arch/arm/kvm/Kconfig
index 49dd64e579c2..370e1a8af6ac 100644
--- a/arch/arm/kvm/Kconfig
+++ b/arch/arm/kvm/Kconfig
@@ -41,9 +41,9 @@ config KVM_ARM_HOST
           Provides host support for ARM processors.
 
 config KVM_ARM_MAX_VCPUS
-        int "Number maximum supported virtual CPUs per VM"
-        depends on KVM_ARM_HOST
-        default 4
+        int "Number maximum supported virtual CPUs per VM" if KVM_ARM_HOST
+        default 4 if KVM_ARM_HOST
+        default 0
         help
           Static number of max supported virtual CPUs per VM.
 
diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
index fc96ce6f2357..53c5ed83d16f 100644
--- a/arch/arm/kvm/Makefile
+++ b/arch/arm/kvm/Makefile
@@ -17,7 +17,7 @@ AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
 kvm-arm-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o)
 
 obj-y += kvm-arm.o init.o interrupts.o
-obj-y += arm.o guest.o mmu.o emulate.o reset.o
-obj-y += coproc.o coproc_a15.o mmio.o psci.o
+obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
+obj-y += coproc.o coproc_a15.o mmio.o psci.o perf.o
 obj-$(CONFIG_KVM_ARM_VGIC) += vgic.o
 obj-$(CONFIG_KVM_ARM_TIMER) += arch_timer.o
diff --git a/arch/arm/kvm/arch_timer.c b/arch/arm/kvm/arch_timer.c
index 6ac938d46297..c55b6089e923 100644
--- a/arch/arm/kvm/arch_timer.c
+++ b/arch/arm/kvm/arch_timer.c
@@ -22,6 +22,7 @@
 #include <linux/kvm_host.h>
 #include <linux/interrupt.h>
 
+#include <clocksource/arm_arch_timer.h>
 #include <asm/arch_timer.h>
 
 #include <asm/kvm_vgic.h>
@@ -64,7 +65,7 @@ static void kvm_timer_inject_irq(struct kvm_vcpu *vcpu)
 {
         struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
 
-        timer->cntv_ctl |= 1 << 1; /* Mask the interrupt in the guest */
+        timer->cntv_ctl |= ARCH_TIMER_CTRL_IT_MASK;
         kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id,
                             vcpu->arch.timer_cpu.irq->irq,
                             vcpu->arch.timer_cpu.irq->level);
@@ -133,8 +134,8 @@ void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu)
         cycle_t cval, now;
         u64 ns;
 
-        /* Check if the timer is enabled and unmasked first */
-        if ((timer->cntv_ctl & 3) != 1)
+        if ((timer->cntv_ctl & ARCH_TIMER_CTRL_IT_MASK) ||
+                !(timer->cntv_ctl & ARCH_TIMER_CTRL_ENABLE))
                 return;
 
         cval = timer->cntv_cval;
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index c1fe498983ac..37d216d814cd 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -16,6 +16,7 @@
  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  */
 
+#include <linux/cpu.h>
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/kvm_host.h>
@@ -30,11 +31,9 @@
 #define CREATE_TRACE_POINTS
 #include "trace.h"
 
-#include <asm/unified.h>
 #include <asm/uaccess.h>
 #include <asm/ptrace.h>
 #include <asm/mman.h>
-#include <asm/cputype.h>
 #include <asm/tlbflush.h>
 #include <asm/cacheflush.h>
 #include <asm/virt.h>
@@ -44,14 +43,13 @@
 #include <asm/kvm_emulate.h>
 #include <asm/kvm_coproc.h>
 #include <asm/kvm_psci.h>
-#include <asm/opcodes.h>
 
 #ifdef REQUIRES_VIRT
 __asm__(".arch_extension        virt");
 #endif
 
 static DEFINE_PER_CPU(unsigned long, kvm_arm_hyp_stack_page);
-static struct vfp_hard_struct __percpu *kvm_host_vfp_state;
+static kvm_cpu_context_t __percpu *kvm_host_cpu_state;
 static unsigned long hyp_default_vectors;
 
 /* Per-CPU variable containing the currently running vcpu. */
@@ -209,7 +207,7 @@ int kvm_dev_ioctl_check_extension(long ext)
                 r = KVM_MAX_VCPUS;
                 break;
         default:
-                r = 0;
+                r = kvm_arch_dev_ioctl_check_extension(ext);
                 break;
         }
         return r;
@@ -221,27 +219,18 @@ long kvm_arch_dev_ioctl(struct file *filp,
         return -EINVAL;
 }
 
-int kvm_arch_set_memory_region(struct kvm *kvm,
-                               struct kvm_userspace_memory_region *mem,
-                               struct kvm_memory_slot old,
-                               int user_alloc)
-{
-        return 0;
-}
-
 int kvm_arch_prepare_memory_region(struct kvm *kvm,
                                    struct kvm_memory_slot *memslot,
-                                   struct kvm_memory_slot old,
                                    struct kvm_userspace_memory_region *mem,
-                                   bool user_alloc)
+                                   enum kvm_mr_change change)
 {
         return 0;
 }
 
 void kvm_arch_commit_memory_region(struct kvm *kvm,
                                    struct kvm_userspace_memory_region *mem,
-                                   struct kvm_memory_slot old,
-                                   bool user_alloc)
+                                   const struct kvm_memory_slot *old,
+                                   enum kvm_mr_change change)
 {
 }
 
@@ -304,22 +293,6 @@ int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
         return 0;
 }
 
-int __attribute_const__ kvm_target_cpu(void)
-{
-        unsigned long implementor = read_cpuid_implementor();
-        unsigned long part_number = read_cpuid_part_number();
-
-        if (implementor != ARM_CPU_IMP_ARM)
-                return -EINVAL;
-
-        switch (part_number) {
-        case ARM_CPU_PART_CORTEX_A15:
-                return KVM_ARM_TARGET_CORTEX_A15;
-        default:
-                return -EINVAL;
-        }
-}
-
 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
 {
         int ret;
@@ -345,7 +318,7 @@ void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 {
         vcpu->cpu = cpu;
-        vcpu->arch.vfp_host = this_cpu_ptr(kvm_host_vfp_state);
+        vcpu->arch.host_cpu_context = this_cpu_ptr(kvm_host_cpu_state);
 
         /*
          * Check whether this vcpu requires the cache to be flushed on
@@ -482,163 +455,6 @@ static void update_vttbr(struct kvm *kvm)
         spin_unlock(&kvm_vmid_lock);
 }
 
-static int handle_svc_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
-        /* SVC called from Hyp mode should never get here */
-        kvm_debug("SVC called from Hyp mode shouldn't go here\n");
-        BUG();
-        return -EINVAL; /* Squash warning */
-}
-
-static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
-        trace_kvm_hvc(*vcpu_pc(vcpu), *vcpu_reg(vcpu, 0),
-                      vcpu->arch.hsr & HSR_HVC_IMM_MASK);
-
-        if (kvm_psci_call(vcpu))
-                return 1;
-
-        kvm_inject_undefined(vcpu);
-        return 1;
-}
-
-static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
-        if (kvm_psci_call(vcpu))
-                return 1;
-
-        kvm_inject_undefined(vcpu);
-        return 1;
-}
-
-static int handle_pabt_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
-        /* The hypervisor should never cause aborts */
-        kvm_err("Prefetch Abort taken from Hyp mode at %#08x (HSR: %#08x)\n",
-                vcpu->arch.hxfar, vcpu->arch.hsr);
-        return -EFAULT;
-}
-
-static int handle_dabt_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
-        /* This is either an error in the ws. code or an external abort */
-        kvm_err("Data Abort taken from Hyp mode at %#08x (HSR: %#08x)\n",
-                vcpu->arch.hxfar, vcpu->arch.hsr);
-        return -EFAULT;
-}
-
-typedef int (*exit_handle_fn)(struct kvm_vcpu *, struct kvm_run *);
-static exit_handle_fn arm_exit_handlers[] = {
-        [HSR_EC_WFI]            = kvm_handle_wfi,
-        [HSR_EC_CP15_32]        = kvm_handle_cp15_32,
-        [HSR_EC_CP15_64]        = kvm_handle_cp15_64,
-        [HSR_EC_CP14_MR]        = kvm_handle_cp14_access,
-        [HSR_EC_CP14_LS]        = kvm_handle_cp14_load_store,
-        [HSR_EC_CP14_64]        = kvm_handle_cp14_access,
-        [HSR_EC_CP_0_13]        = kvm_handle_cp_0_13_access,
-        [HSR_EC_CP10_ID]        = kvm_handle_cp10_id,
-        [HSR_EC_SVC_HYP]        = handle_svc_hyp,
-        [HSR_EC_HVC]            = handle_hvc,
-        [HSR_EC_SMC]            = handle_smc,
-        [HSR_EC_IABT]           = kvm_handle_guest_abort,
-        [HSR_EC_IABT_HYP]       = handle_pabt_hyp,
-        [HSR_EC_DABT]           = kvm_handle_guest_abort,
-        [HSR_EC_DABT_HYP]       = handle_dabt_hyp,
-};
-
-/*
- * A conditional instruction is allowed to trap, even though it
- * wouldn't be executed.  So let's re-implement the hardware, in
- * software!
- */
-static bool kvm_condition_valid(struct kvm_vcpu *vcpu)
-{
-        unsigned long cpsr, cond, insn;
-
-        /*
-         * Exception Code 0 can only happen if we set HCR.TGE to 1, to
-         * catch undefined instructions, and then we won't get past
-         * the arm_exit_handlers test anyway.
-         */
-        BUG_ON(((vcpu->arch.hsr & HSR_EC) >> HSR_EC_SHIFT) == 0);
-
-        /* Top two bits non-zero?  Unconditional. */
-        if (vcpu->arch.hsr >> 30)
-                return true;
-
-        cpsr = *vcpu_cpsr(vcpu);
-
-        /* Is condition field valid? */
-        if ((vcpu->arch.hsr & HSR_CV) >> HSR_CV_SHIFT)
-                cond = (vcpu->arch.hsr & HSR_COND) >> HSR_COND_SHIFT;
-        else {
-                /* This can happen in Thumb mode: examine IT state. */
-                unsigned long it;
-
-                it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3);
-
-                /* it == 0 => unconditional. */
-                if (it == 0)
-                        return true;
-
-                /* The cond for this insn works out as the top 4 bits. */
-                cond = (it >> 4);
-        }
-
-        /* Shift makes it look like an ARM-mode instruction */
-        insn = cond << 28;
-        return arm_check_condition(insn, cpsr) != ARM_OPCODE_CONDTEST_FAIL;
-}
-
-/*
- * Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on
- * proper exit to QEMU.
- */
-static int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
-                       int exception_index)
-{
-        unsigned long hsr_ec;
-
-        switch (exception_index) {
-        case ARM_EXCEPTION_IRQ:
-                return 1;
-        case ARM_EXCEPTION_UNDEFINED:
-                kvm_err("Undefined exception in Hyp mode at: %#08x\n",
-                        vcpu->arch.hyp_pc);
-                BUG();
-                panic("KVM: Hypervisor undefined exception!\n");
-        case ARM_EXCEPTION_DATA_ABORT:
-        case ARM_EXCEPTION_PREF_ABORT:
-        case ARM_EXCEPTION_HVC:
-                hsr_ec = (vcpu->arch.hsr & HSR_EC) >> HSR_EC_SHIFT;
-
-                if (hsr_ec >= ARRAY_SIZE(arm_exit_handlers)
-                    || !arm_exit_handlers[hsr_ec]) {
-                        kvm_err("Unkown exception class: %#08lx, "
-                                "hsr: %#08x\n", hsr_ec,
-                                (unsigned int)vcpu->arch.hsr);
-                        BUG();
-                }
-
-                /*
-                 * See ARM ARM B1.14.1: "Hyp traps on instructions
-                 * that fail their condition code check"
-                 */
-                if (!kvm_condition_valid(vcpu)) {
-                        bool is_wide = vcpu->arch.hsr & HSR_IL;
-                        kvm_skip_instr(vcpu, is_wide);
-                        return 1;
-                }
-
-                return arm_exit_handlers[hsr_ec](vcpu, run);
-        default:
-                kvm_pr_unimpl("Unsupported exception type: %d",
-                              exception_index);
-                run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
-                return 0;
-        }
-}
-
 static int kvm_vcpu_first_run_init(struct kvm_vcpu *vcpu)
 {
         if (likely(vcpu->arch.has_run_once))
@@ -815,7 +631,8 @@ static int vcpu_interrupt_line(struct kvm_vcpu *vcpu, int number, bool level)
         return 0;
 }
 
-int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_level)
+int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_level,
+                          bool line_status)
 {
         u32 irq = irq_level->irq;
         unsigned int irq_type, vcpu_idx, irq_num;
@@ -970,40 +787,48 @@ long kvm_arch_vm_ioctl(struct file *filp,
         }
 }
 
-static void cpu_init_hyp_mode(void *vector)
+static void cpu_init_hyp_mode(void *dummy)
 {
+        unsigned long long boot_pgd_ptr;
         unsigned long long pgd_ptr;
-        unsigned long pgd_low, pgd_high;
         unsigned long hyp_stack_ptr;
         unsigned long stack_page;
         unsigned long vector_ptr;
 
         /* Switch from the HYP stub to our own HYP init vector */
-        __hyp_set_vectors((unsigned long)vector);
+        __hyp_set_vectors(kvm_get_idmap_vector());
 
+        boot_pgd_ptr = (unsigned long long)kvm_mmu_get_boot_httbr();
         pgd_ptr = (unsigned long long)kvm_mmu_get_httbr();
-        pgd_low = (pgd_ptr & ((1ULL << 32) - 1));
-        pgd_high = (pgd_ptr >> 32ULL);
         stack_page = __get_cpu_var(kvm_arm_hyp_stack_page);
         hyp_stack_ptr = stack_page + PAGE_SIZE;
         vector_ptr = (unsigned long)__kvm_hyp_vector;
 
-        /*
-         * Call initialization code, and switch to the full blown
-         * HYP code. The init code doesn't need to preserve these registers as
-         * r1-r3 and r12 are already callee save according to the AAPCS.
-         * Note that we slightly misuse the prototype by casing the pgd_low to
-         * a void *.
-         */
-        kvm_call_hyp((void *)pgd_low, pgd_high, hyp_stack_ptr, vector_ptr);
+        __cpu_init_hyp_mode(boot_pgd_ptr, pgd_ptr, hyp_stack_ptr, vector_ptr);
+}
+
+static int hyp_init_cpu_notify(struct notifier_block *self,
+                               unsigned long action, void *cpu)
+{
+        switch (action) {
+        case CPU_STARTING:
+        case CPU_STARTING_FROZEN:
+                cpu_init_hyp_mode(NULL);
+                break;
+        }
+
+        return NOTIFY_OK;
 }
 
+static struct notifier_block hyp_init_cpu_nb = {
+        .notifier_call = hyp_init_cpu_notify,
+};
+
 /**
  * Inits Hyp-mode on all online CPUs
  */
 static int init_hyp_mode(void)
 {
-        phys_addr_t init_phys_addr;
         int cpu;
         int err = 0;
 
@@ -1036,24 +861,6 @@ static int init_hyp_mode(void)
         }
 
         /*
-         * Execute the init code on each CPU.
-         *
-         * Note: The stack is not mapped yet, so don't do anything else than
-         * initializing the hypervisor mode on each CPU using a local stack
-         * space for temporary storage.
-         */
-        init_phys_addr = virt_to_phys(__kvm_hyp_init);
-        for_each_online_cpu(cpu) {
-                smp_call_function_single(cpu, cpu_init_hyp_mode,
-                                         (void *)(long)init_phys_addr, 1);
-        }
-
-        /*
-         * Unmap the identity mapping
-         */
-        kvm_clear_hyp_idmap();
-
-        /*
          * Map the Hyp-code called directly from the host
          */
         err = create_hyp_mappings(__kvm_hyp_code_start, __kvm_hyp_code_end);
@@ -1076,33 +883,38 @@ static int init_hyp_mode(void)
         }
 
         /*
-         * Map the host VFP structures
+         * Map the host CPU structures
          */
-        kvm_host_vfp_state = alloc_percpu(struct vfp_hard_struct);
-        if (!kvm_host_vfp_state) {
+        kvm_host_cpu_state = alloc_percpu(kvm_cpu_context_t);
+        if (!kvm_host_cpu_state) {
                 err = -ENOMEM;
-                kvm_err("Cannot allocate host VFP state\n");
+                kvm_err("Cannot allocate host CPU state\n");
                 goto out_free_mappings;
         }
 
         for_each_possible_cpu(cpu) {
-                struct vfp_hard_struct *vfp;
+                kvm_cpu_context_t *cpu_ctxt;
 
-                vfp = per_cpu_ptr(kvm_host_vfp_state, cpu);
-                err = create_hyp_mappings(vfp, vfp + 1);
+                cpu_ctxt = per_cpu_ptr(kvm_host_cpu_state, cpu);
+                err = create_hyp_mappings(cpu_ctxt, cpu_ctxt + 1);
 
                 if (err) {
-                        kvm_err("Cannot map host VFP state: %d\n", err);
-                        goto out_free_vfp;
+                        kvm_err("Cannot map host CPU state: %d\n", err);
+                        goto out_free_context;
                 }
         }
 
         /*
+         * Execute the init code on each CPU.
+         */
+        on_each_cpu(cpu_init_hyp_mode, NULL, 1);
+
+        /*
          * Init HYP view of VGIC
          */
         err = kvm_vgic_hyp_init();
         if (err)
-                goto out_free_vfp;
+                goto out_free_context;
 
 #ifdef CONFIG_KVM_ARM_VGIC
                 vgic_present = true;
@@ -1115,12 +927,19 @@ static int init_hyp_mode(void)
         if (err)
                 goto out_free_mappings;
 
+#ifndef CONFIG_HOTPLUG_CPU
+        free_boot_hyp_pgd();
+#endif
+
+        kvm_perf_init();
+
         kvm_info("Hyp mode initialized successfully\n");
+
         return 0;
-out_free_vfp:
-        free_percpu(kvm_host_vfp_state);
+out_free_context:
+        free_percpu(kvm_host_cpu_state);
 out_free_mappings:
-        free_hyp_pmds();
+        free_hyp_pgds();
 out_free_stack_pages:
         for_each_possible_cpu(cpu)
                 free_page(per_cpu(kvm_arm_hyp_stack_page, cpu));
@@ -1129,27 +948,42 @@ out_err:
         return err;
 }
 
+static void check_kvm_target_cpu(void *ret)
+{
+        *(int *)ret = kvm_target_cpu();
+}
+
 /**
  * Initialize Hyp-mode and memory mappings on all CPUs.
  */
 int kvm_arch_init(void *opaque)
 {
         int err;
+        int ret, cpu;
 
         if (!is_hyp_mode_available()) {
                 kvm_err("HYP mode not available\n");
                 return -ENODEV;
         }
 
-        if (kvm_target_cpu() < 0) {
-                kvm_err("Target CPU not supported!\n");
-                return -ENODEV;
+        for_each_online_cpu(cpu) {
+                smp_call_function_single(cpu, check_kvm_target_cpu, &ret, 1);
+                if (ret < 0) {
+                        kvm_err("Error, CPU %d not supported!\n", cpu);
+                        return -ENODEV;
+                }
         }
 
         err = init_hyp_mode();
         if (err)
                 goto out_err;
 
+        err = register_cpu_notifier(&hyp_init_cpu_nb);
+        if (err) {
+                kvm_err("Cannot register HYP init CPU notifier (%d)\n", err);
+                goto out_err;
+        }
+
         kvm_coproc_table_init();
         return 0;
 out_err:
@@ -1159,6 +993,7 @@ out_err:
 /* NOP: Compiling as a module not supported */
 void kvm_arch_exit(void)
 {
+        kvm_perf_teardown();
 }
 
 static int arm_init(void)
diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
index 7bed7556077a..8eea97be1ed5 100644
--- a/arch/arm/kvm/coproc.c
+++ b/arch/arm/kvm/coproc.c
@@ -76,7 +76,7 @@ static bool access_dcsw(struct kvm_vcpu *vcpu,
                         const struct coproc_params *p,
                         const struct coproc_reg *r)
 {
-        u32 val;
+        unsigned long val;
         int cpu;
 
         if (!p->is_write)
@@ -293,12 +293,12 @@ static int emulate_cp15(struct kvm_vcpu *vcpu,
 
                 if (likely(r->access(vcpu, params, r))) {
                         /* Skip instruction, since it was emulated */
-                        kvm_skip_instr(vcpu, (vcpu->arch.hsr >> 25) & 1);
+                        kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
                         return 1;
                 }
                 /* If access function fails, it should complain. */
         } else {
-                kvm_err("Unsupported guest CP15 access at: %08x\n",
+                kvm_err("Unsupported guest CP15 access at: %08lx\n",
                         *vcpu_pc(vcpu));
                 print_cp_instr(params);
         }
@@ -315,14 +315,14 @@ int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
         struct coproc_params params;
 
-        params.CRm = (vcpu->arch.hsr >> 1) & 0xf;
-        params.Rt1 = (vcpu->arch.hsr >> 5) & 0xf;
-        params.is_write = ((vcpu->arch.hsr & 1) == 0);
+        params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
+        params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
+        params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
         params.is_64bit = true;
 
-        params.Op1 = (vcpu->arch.hsr >> 16) & 0xf;
+        params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 16) & 0xf;
         params.Op2 = 0;
-        params.Rt2 = (vcpu->arch.hsr >> 10) & 0xf;
+        params.Rt2 = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
         params.CRn = 0;
 
         return emulate_cp15(vcpu, &params);
@@ -347,14 +347,14 @@ int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
         struct coproc_params params;
 
-        params.CRm = (vcpu->arch.hsr >> 1) & 0xf;
-        params.Rt1 = (vcpu->arch.hsr >> 5) & 0xf;
-        params.is_write = ((vcpu->arch.hsr & 1) == 0);
+        params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
+        params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
+        params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
         params.is_64bit = false;
 
-        params.CRn = (vcpu->arch.hsr >> 10) & 0xf;
-        params.Op1 = (vcpu->arch.hsr >> 14) & 0x7;
-        params.Op2 = (vcpu->arch.hsr >> 17) & 0x7;
+        params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
+        params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 14) & 0x7;
+        params.Op2 = (kvm_vcpu_get_hsr(vcpu) >> 17) & 0x7;
         params.Rt2 = 0;
 
         return emulate_cp15(vcpu, &params);
diff --git a/arch/arm/kvm/coproc.h b/arch/arm/kvm/coproc.h
index 992adfafa2ff..b7301d3e4799 100644
--- a/arch/arm/kvm/coproc.h
+++ b/arch/arm/kvm/coproc.h
@@ -84,7 +84,7 @@ static inline bool read_zero(struct kvm_vcpu *vcpu,
 static inline bool write_to_read_only(struct kvm_vcpu *vcpu,
                                       const struct coproc_params *params)
 {
-        kvm_debug("CP15 write to read-only register at: %08x\n",
+        kvm_debug("CP15 write to read-only register at: %08lx\n",
                   *vcpu_pc(vcpu));
         print_cp_instr(params);
         return false;
@@ -93,7 +93,7 @@ static inline bool write_to_read_only(struct kvm_vcpu *vcpu,
 static inline bool read_from_write_only(struct kvm_vcpu *vcpu,
                                         const struct coproc_params *params)
 {
-        kvm_debug("CP15 read to write-only register at: %08x\n",
+        kvm_debug("CP15 read to write-only register at: %08lx\n",
                   *vcpu_pc(vcpu));
         print_cp_instr(params);
         return false;
diff --git a/arch/arm/kvm/emulate.c b/arch/arm/kvm/emulate.c
index d61450ac6665..bdede9e7da51 100644
--- a/arch/arm/kvm/emulate.c
+++ b/arch/arm/kvm/emulate.c
@@ -20,6 +20,7 @@
 #include <linux/kvm_host.h>
 #include <asm/kvm_arm.h>
 #include <asm/kvm_emulate.h>
+#include <asm/opcodes.h>
 #include <trace/events/kvm.h>
 
 #include "trace.h"
@@ -109,10 +110,10 @@ static const unsigned long vcpu_reg_offsets[VCPU_NR_MODES][15] = {
  * Return a pointer to the register number valid in the current mode of
  * the virtual CPU.
  */
-u32 *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num)
+unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num)
 {
-        u32 *reg_array = (u32 *)&vcpu->arch.regs;
-        u32 mode = *vcpu_cpsr(vcpu) & MODE_MASK;
+        unsigned long *reg_array = (unsigned long *)&vcpu->arch.regs;
+        unsigned long mode = *vcpu_cpsr(vcpu) & MODE_MASK;
 
         switch (mode) {
         case USR_MODE...SVC_MODE:
@@ -141,9 +142,9 @@ u32 *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num)
 /*
  * Return the SPSR for the current mode of the virtual CPU.
  */
-u32 *vcpu_spsr(struct kvm_vcpu *vcpu)
+unsigned long *vcpu_spsr(struct kvm_vcpu *vcpu)
 {
-        u32 mode = *vcpu_cpsr(vcpu) & MODE_MASK;
+        unsigned long mode = *vcpu_cpsr(vcpu) & MODE_MASK;
         switch (mode) {
         case SVC_MODE:
                 return &vcpu->arch.regs.KVM_ARM_SVC_spsr;
@@ -160,20 +161,48 @@ u32 *vcpu_spsr(struct kvm_vcpu *vcpu)
         }
 }
 
-/**
- * kvm_handle_wfi - handle a wait-for-interrupts instruction executed by a guest
- * @vcpu:       the vcpu pointer
- * @run:        the kvm_run structure pointer
- *
- * Simply sets the wait_for_interrupts flag on the vcpu structure, which will
- * halt execution of world-switches and schedule other host processes until
- * there is an incoming IRQ or FIQ to the VM.
+/*
+ * A conditional instruction is allowed to trap, even though it
+ * wouldn't be executed.  So let's re-implement the hardware, in
+ * software!
  */
-int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run)
+bool kvm_condition_valid(struct kvm_vcpu *vcpu)
 {
-        trace_kvm_wfi(*vcpu_pc(vcpu));
-        kvm_vcpu_block(vcpu);
-        return 1;
+        unsigned long cpsr, cond, insn;
+
+        /*
+         * Exception Code 0 can only happen if we set HCR.TGE to 1, to
+         * catch undefined instructions, and then we won't get past
+         * the arm_exit_handlers test anyway.
+         */
+        BUG_ON(!kvm_vcpu_trap_get_class(vcpu));
+
+        /* Top two bits non-zero?  Unconditional. */
+        if (kvm_vcpu_get_hsr(vcpu) >> 30)
+                return true;
+
+        cpsr = *vcpu_cpsr(vcpu);
+
+        /* Is condition field valid? */
+        if ((kvm_vcpu_get_hsr(vcpu) & HSR_CV) >> HSR_CV_SHIFT)
+                cond = (kvm_vcpu_get_hsr(vcpu) & HSR_COND) >> HSR_COND_SHIFT;
+        else {
+                /* This can happen in Thumb mode: examine IT state. */
+                unsigned long it;
+
+                it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3);
+
+                /* it == 0 => unconditional. */
+                if (it == 0)
+                        return true;
+
+                /* The cond for this insn works out as the top 4 bits. */
+                cond = (it >> 4);
+        }
+
+        /* Shift makes it look like an ARM-mode instruction */
+        insn = cond << 28;
+        return arm_check_condition(insn, cpsr) != ARM_OPCODE_CONDTEST_FAIL;
 }
 
 /**
@@ -257,9 +286,9 @@ static u32 exc_vector_base(struct kvm_vcpu *vcpu)
  */
 void kvm_inject_undefined(struct kvm_vcpu *vcpu)
 {
-        u32 new_lr_value;
-        u32 new_spsr_value;
-        u32 cpsr = *vcpu_cpsr(vcpu);
+        unsigned long new_lr_value;
+        unsigned long new_spsr_value;
+        unsigned long cpsr = *vcpu_cpsr(vcpu);
         u32 sctlr = vcpu->arch.cp15[c1_SCTLR];
         bool is_thumb = (cpsr & PSR_T_BIT);
         u32 vect_offset = 4;
@@ -291,9 +320,9 @@ void kvm_inject_undefined(struct kvm_vcpu *vcpu)
  */
 static void inject_abt(struct kvm_vcpu *vcpu, bool is_pabt, unsigned long addr)
 {
-        u32 new_lr_value;
-        u32 new_spsr_value;
-        u32 cpsr = *vcpu_cpsr(vcpu);
+        unsigned long new_lr_value;
+        unsigned long new_spsr_value;
+        unsigned long cpsr = *vcpu_cpsr(vcpu);
         u32 sctlr = vcpu->arch.cp15[c1_SCTLR];
         bool is_thumb = (cpsr & PSR_T_BIT);
         u32 vect_offset;
diff --git a/arch/arm/kvm/guest.c b/arch/arm/kvm/guest.c
index 2339d9609d36..152d03612181 100644
--- a/arch/arm/kvm/guest.c
+++ b/arch/arm/kvm/guest.c
@@ -22,6 +22,7 @@
 #include <linux/module.h>
 #include <linux/vmalloc.h>
 #include <linux/fs.h>
+#include <asm/cputype.h>
 #include <asm/uaccess.h>
 #include <asm/kvm.h>
 #include <asm/kvm_asm.h>
@@ -180,6 +181,22 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
         return -EINVAL;
 }
 
+int __attribute_const__ kvm_target_cpu(void)
+{
+        unsigned long implementor = read_cpuid_implementor();
+        unsigned long part_number = read_cpuid_part_number();
+
+        if (implementor != ARM_CPU_IMP_ARM)
+                return -EINVAL;
+
+        switch (part_number) {
+        case ARM_CPU_PART_CORTEX_A15:
+                return KVM_ARM_TARGET_CORTEX_A15;
+        default:
+                return -EINVAL;
+        }
+}
+
 int kvm_vcpu_set_target(struct kvm_vcpu *vcpu,
                         const struct kvm_vcpu_init *init)
 {
diff --git a/arch/arm/kvm/handle_exit.c b/arch/arm/kvm/handle_exit.c
new file mode 100644
index 000000000000..3d74a0be47db
--- /dev/null
+++ b/arch/arm/kvm/handle_exit.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kvm.h>
+#include <linux/kvm_host.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_coproc.h>
+#include <asm/kvm_mmu.h>
+#include <asm/kvm_psci.h>
+#include <trace/events/kvm.h>
+
+#include "trace.h"
+
+#include "trace.h"
+
+typedef int (*exit_handle_fn)(struct kvm_vcpu *, struct kvm_run *);
+
+static int handle_svc_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        /* SVC called from Hyp mode should never get here */
+        kvm_debug("SVC called from Hyp mode shouldn't go here\n");
+        BUG();
+        return -EINVAL; /* Squash warning */
+}
+
+static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        trace_kvm_hvc(*vcpu_pc(vcpu), *vcpu_reg(vcpu, 0),
+                      kvm_vcpu_hvc_get_imm(vcpu));
+
+        if (kvm_psci_call(vcpu))
+                return 1;
+
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+
+static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        if (kvm_psci_call(vcpu))
+                return 1;
+
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+
+static int handle_pabt_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        /* The hypervisor should never cause aborts */
+        kvm_err("Prefetch Abort taken from Hyp mode at %#08lx (HSR: %#08x)\n",
+                kvm_vcpu_get_hfar(vcpu), kvm_vcpu_get_hsr(vcpu));
+        return -EFAULT;
+}
+
+static int handle_dabt_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        /* This is either an error in the ws. code or an external abort */
+        kvm_err("Data Abort taken from Hyp mode at %#08lx (HSR: %#08x)\n",
+                kvm_vcpu_get_hfar(vcpu), kvm_vcpu_get_hsr(vcpu));
+        return -EFAULT;
+}
+
+/**
+ * kvm_handle_wfi - handle a wait-for-interrupts instruction executed by a guest
+ * @vcpu:       the vcpu pointer
+ * @run:        the kvm_run structure pointer
+ *
+ * Simply sets the wait_for_interrupts flag on the vcpu structure, which will
+ * halt execution of world-switches and schedule other host processes until
+ * there is an incoming IRQ or FIQ to the VM.
+ */
+static int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        trace_kvm_wfi(*vcpu_pc(vcpu));
+        kvm_vcpu_block(vcpu);
+        return 1;
+}
+
+static exit_handle_fn arm_exit_handlers[] = {
+        [HSR_EC_WFI]            = kvm_handle_wfi,
+        [HSR_EC_CP15_32]        = kvm_handle_cp15_32,
+        [HSR_EC_CP15_64]        = kvm_handle_cp15_64,
+        [HSR_EC_CP14_MR]        = kvm_handle_cp14_access,
+        [HSR_EC_CP14_LS]        = kvm_handle_cp14_load_store,
+        [HSR_EC_CP14_64]        = kvm_handle_cp14_access,
+        [HSR_EC_CP_0_13]        = kvm_handle_cp_0_13_access,
+        [HSR_EC_CP10_ID]        = kvm_handle_cp10_id,
+        [HSR_EC_SVC_HYP]        = handle_svc_hyp,
+        [HSR_EC_HVC]            = handle_hvc,
+        [HSR_EC_SMC]            = handle_smc,
+        [HSR_EC_IABT]           = kvm_handle_guest_abort,
+        [HSR_EC_IABT_HYP]       = handle_pabt_hyp,
+        [HSR_EC_DABT]           = kvm_handle_guest_abort,
+        [HSR_EC_DABT_HYP]       = handle_dabt_hyp,
+};
+
+static exit_handle_fn kvm_get_exit_handler(struct kvm_vcpu *vcpu)
+{
+        u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
+
+        if (hsr_ec >= ARRAY_SIZE(arm_exit_handlers) ||
+            !arm_exit_handlers[hsr_ec]) {
+                kvm_err("Unknown exception class: hsr: %#08x\n",
+                        (unsigned int)kvm_vcpu_get_hsr(vcpu));
+                BUG();
+        }
+
+        return arm_exit_handlers[hsr_ec];
+}
+
+/*
+ * Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on
+ * proper exit to userspace.
+ */
+int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
+                       int exception_index)
+{
+        exit_handle_fn exit_handler;
+
+        switch (exception_index) {
+        case ARM_EXCEPTION_IRQ:
+                return 1;
+        case ARM_EXCEPTION_UNDEFINED:
+                kvm_err("Undefined exception in Hyp mode at: %#08lx\n",
+                        kvm_vcpu_get_hyp_pc(vcpu));
+                BUG();
+                panic("KVM: Hypervisor undefined exception!\n");
+        case ARM_EXCEPTION_DATA_ABORT:
+        case ARM_EXCEPTION_PREF_ABORT:
+        case ARM_EXCEPTION_HVC:
+                /*
+                 * See ARM ARM B1.14.1: "Hyp traps on instructions
+                 * that fail their condition code check"
+                 */
+                if (!kvm_condition_valid(vcpu)) {
+                        kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
+                        return 1;
+                }
+
+                exit_handler = kvm_get_exit_handler(vcpu);
+
+                return exit_handler(vcpu, run);
+        default:
+                kvm_pr_unimpl("Unsupported exception type: %d",
+                              exception_index);
+                run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
+                return 0;
+        }
+}
diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S
index 9f37a79b880b..f048338135f7 100644
--- a/arch/arm/kvm/init.S
+++ b/arch/arm/kvm/init.S
@@ -21,13 +21,33 @@
 #include <asm/asm-offsets.h>
 #include <asm/kvm_asm.h>
 #include <asm/kvm_arm.h>
+#include <asm/kvm_mmu.h>
 
 /********************************************************************
  * Hypervisor initialization
  *   - should be called with:
- *       r0,r1 = Hypervisor pgd pointer
- *       r2 = top of Hyp stack (kernel VA)
- *       r3 = pointer to hyp vectors
+ *       r0 = top of Hyp stack (kernel VA)
+ *       r1 = pointer to hyp vectors
+ *       r2,r3 = Hypervisor pgd pointer
+ *
+ * The init scenario is:
+ * - We jump in HYP with four parameters: boot HYP pgd, runtime HYP pgd,
+ *   runtime stack, runtime vectors
+ * - Enable the MMU with the boot pgd
+ * - Jump to a target into the trampoline page (remember, this is the same
+ *   physical page!)
+ * - Now switch to the runtime pgd (same VA, and still the same physical
+ *   page!)
+ * - Invalidate TLBs
+ * - Set stack and vectors
+ * - Profit! (or eret, if you only care about the code).
+ *
+ * As we only have four registers available to pass parameters (and we
+ * need six), we split the init in two phases:
+ * - Phase 1: r0 = 0, r1 = 0, r2,r3 contain the boot PGD.
+ *   Provides the basic HYP init, and enable the MMU.
+ * - Phase 2: r0 = ToS, r1 = vectors, r2,r3 contain the runtime PGD.
+ *   Switches to the runtime PGD, set stack and vectors.
  */
 
         .text
@@ -47,22 +67,25 @@ __kvm_hyp_init:
         W(b)    .
 
 __do_hyp_init:
+        cmp     r0, #0                  @ We have a SP?
+        bne     phase2                  @ Yes, second stage init
+
         @ Set the HTTBR to point to the hypervisor PGD pointer passed
-        mcrr    p15, 4, r0, r1, c2
+        mcrr    p15, 4, r2, r3, c2
 
         @ Set the HTCR and VTCR to the same shareability and cacheability
         @ settings as the non-secure TTBCR and with T0SZ == 0.
         mrc     p15, 4, r0, c2, c0, 2   @ HTCR
-        ldr     r12, =HTCR_MASK
-        bic     r0, r0, r12
+        ldr     r2, =HTCR_MASK
+        bic     r0, r0, r2
         mrc     p15, 0, r1, c2, c0, 2   @ TTBCR
         and     r1, r1, #(HTCR_MASK & ~TTBCR_T0SZ)
         orr     r0, r0, r1
         mcr     p15, 4, r0, c2, c0, 2   @ HTCR
 
         mrc     p15, 4, r1, c2, c1, 2   @ VTCR
-        ldr     r12, =VTCR_MASK
-        bic     r1, r1, r12
+        ldr     r2, =VTCR_MASK
+        bic     r1, r1, r2
         bic     r0, r0, #(~VTCR_HTCR_SH)        @ clear non-reusable HTCR bits
         orr     r1, r0, r1
         orr     r1, r1, #(KVM_VTCR_SL0 | KVM_VTCR_T0SZ | KVM_VTCR_S)
@@ -85,24 +108,41 @@ __do_hyp_init:
         @  - Memory alignment checks: enabled
         @  - MMU: enabled (this code must be run from an identity mapping)
         mrc     p15, 4, r0, c1, c0, 0   @ HSCR
-        ldr     r12, =HSCTLR_MASK
-        bic     r0, r0, r12
+        ldr     r2, =HSCTLR_MASK
+        bic     r0, r0, r2
         mrc     p15, 0, r1, c1, c0, 0   @ SCTLR
-        ldr     r12, =(HSCTLR_EE | HSCTLR_FI | HSCTLR_I | HSCTLR_C)
-        and     r1, r1, r12
- ARM(   ldr     r12, =(HSCTLR_M | HSCTLR_A)                     )
- THUMB( ldr     r12, =(HSCTLR_M | HSCTLR_A | HSCTLR_TE)         )
-        orr     r1, r1, r12
+        ldr     r2, =(HSCTLR_EE | HSCTLR_FI | HSCTLR_I | HSCTLR_C)
+        and     r1, r1, r2
+ ARM(   ldr     r2, =(HSCTLR_M | HSCTLR_A)                      )
+ THUMB( ldr     r2, =(HSCTLR_M | HSCTLR_A | HSCTLR_TE)          )
+        orr     r1, r1, r2
         orr     r0, r0, r1
         isb
         mcr     p15, 4, r0, c1, c0, 0   @ HSCR
-        isb
 
-        @ Set stack pointer and return to the kernel
-        mov     sp, r2
+        @ End of init phase-1
+        eret
+
+phase2:
+        @ Set stack pointer
+        mov     sp, r0
 
         @ Set HVBAR to point to the HYP vectors
-        mcr     p15, 4, r3, c12, c0, 0  @ HVBAR
+        mcr     p15, 4, r1, c12, c0, 0  @ HVBAR
+
+        @ Jump to the trampoline page
+        ldr     r0, =TRAMPOLINE_VA
+        adr     r1, target
+        bfi     r0, r1, #0, #PAGE_SHIFT
+        mov     pc, r0
+
+target: @ We're now in the trampoline code, switch page tables
+        mcrr    p15, 4, r2, r3, c2
+        isb
+
+        @ Invalidate the old TLBs
+        mcr     p15, 4, r0, c8, c7, 0   @ TLBIALLH
+        dsb
 
         eret
 
diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
index 8ca87ab0919d..f7793df62f58 100644
--- a/arch/arm/kvm/interrupts.S
+++ b/arch/arm/kvm/interrupts.S
@@ -35,15 +35,18 @@ __kvm_hyp_code_start:
 /********************************************************************
  * Flush per-VMID TLBs
  *
- * void __kvm_tlb_flush_vmid(struct kvm *kvm);
+ * void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
  *
  * We rely on the hardware to broadcast the TLB invalidation to all CPUs
  * inside the inner-shareable domain (which is the case for all v7
  * implementations).  If we come across a non-IS SMP implementation, we'll
  * have to use an IPI based mechanism. Until then, we stick to the simple
  * hardware assisted version.
+ *
+ * As v7 does not support flushing per IPA, just nuke the whole TLB
+ * instead, ignoring the ipa value.
  */
-ENTRY(__kvm_tlb_flush_vmid)
+ENTRY(__kvm_tlb_flush_vmid_ipa)
         push    {r2, r3}
 
         add     r0, r0, #KVM_VTTBR
@@ -60,7 +63,7 @@ ENTRY(__kvm_tlb_flush_vmid)
 
         pop     {r2, r3}
         bx      lr
-ENDPROC(__kvm_tlb_flush_vmid)
+ENDPROC(__kvm_tlb_flush_vmid_ipa)
 
 /********************************************************************
  * Flush TLBs and instruction caches of all CPUs inside the inner-shareable
@@ -235,9 +238,9 @@ ENTRY(kvm_call_hyp)
  * instruction is issued since all traps are disabled when running the host
  * kernel as per the Hyp-mode initialization at boot time.
  *
- * HVC instructions cause a trap to the vector page + offset 0x18 (see hyp_hvc
+ * HVC instructions cause a trap to the vector page + offset 0x14 (see hyp_hvc
  * below) when the HVC instruction is called from SVC mode (i.e. a guest or the
- * host kernel) and they cause a trap to the vector page + offset 0xc when HVC
+ * host kernel) and they cause a trap to the vector page + offset 0x8 when HVC
  * instructions are called from within Hyp-mode.
  *
  * Hyp-ABI: Calling HYP-mode functions from host (in SVC mode):
diff --git a/arch/arm/kvm/mmio.c b/arch/arm/kvm/mmio.c
index 98a870ff1a5c..72a12f2171b2 100644
--- a/arch/arm/kvm/mmio.c
+++ b/arch/arm/kvm/mmio.c
@@ -33,16 +33,16 @@
  */
 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
-        __u32 *dest;
+        unsigned long *dest;
         unsigned int len;
         int mask;
 
         if (!run->mmio.is_write) {
                 dest = vcpu_reg(vcpu, vcpu->arch.mmio_decode.rt);
-                memset(dest, 0, sizeof(int));
+                *dest = 0;
 
                 len = run->mmio.len;
-                if (len > 4)
+                if (len > sizeof(unsigned long))
                         return -EINVAL;
 
                 memcpy(dest, run->mmio.data, len);
@@ -50,7 +50,8 @@ int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
                 trace_kvm_mmio(KVM_TRACE_MMIO_READ, len, run->mmio.phys_addr,
                                 *((u64 *)run->mmio.data));
 
-                if (vcpu->arch.mmio_decode.sign_extend && len < 4) {
+                if (vcpu->arch.mmio_decode.sign_extend &&
+                    len < sizeof(unsigned long)) {
                         mask = 1U << ((len * 8) - 1);
                         *dest = (*dest ^ mask) - mask;
                 }
@@ -65,40 +66,29 @@ static int decode_hsr(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
         unsigned long rt, len;
         bool is_write, sign_extend;
 
-        if ((vcpu->arch.hsr >> 8) & 1) {
+        if (kvm_vcpu_dabt_isextabt(vcpu)) {
                 /* cache operation on I/O addr, tell guest unsupported */
-                kvm_inject_dabt(vcpu, vcpu->arch.hxfar);
+                kvm_inject_dabt(vcpu, kvm_vcpu_get_hfar(vcpu));
                 return 1;
         }
 
-        if ((vcpu->arch.hsr >> 7) & 1) {
+        if (kvm_vcpu_dabt_iss1tw(vcpu)) {
                 /* page table accesses IO mem: tell guest to fix its TTBR */
-                kvm_inject_dabt(vcpu, vcpu->arch.hxfar);
+                kvm_inject_dabt(vcpu, kvm_vcpu_get_hfar(vcpu));
                 return 1;
         }
 
-        switch ((vcpu->arch.hsr >> 22) & 0x3) {
-        case 0:
-                len = 1;
-                break;
-        case 1:
-                len = 2;
-                break;
-        case 2:
-                len = 4;
-                break;
-        default:
-                kvm_err("Hardware is weird: SAS 0b11 is reserved\n");
-                return -EFAULT;
-        }
+        len = kvm_vcpu_dabt_get_as(vcpu);
+        if (unlikely(len < 0))
+                return len;
 
-        is_write = vcpu->arch.hsr & HSR_WNR;
-        sign_extend = vcpu->arch.hsr & HSR_SSE;
-        rt = (vcpu->arch.hsr & HSR_SRT_MASK) >> HSR_SRT_SHIFT;
+        is_write = kvm_vcpu_dabt_iswrite(vcpu);
+        sign_extend = kvm_vcpu_dabt_issext(vcpu);
+        rt = kvm_vcpu_dabt_get_rd(vcpu);
 
         if (kvm_vcpu_reg_is_pc(vcpu, rt)) {
                 /* IO memory trying to read/write pc */
-                kvm_inject_pabt(vcpu, vcpu->arch.hxfar);
+                kvm_inject_pabt(vcpu, kvm_vcpu_get_hfar(vcpu));
                 return 1;
         }
 
@@ -112,7 +102,7 @@ static int decode_hsr(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
          * The MMIO instruction is emulated and should not be re-executed
          * in the guest.
          */
-        kvm_skip_instr(vcpu, (vcpu->arch.hsr >> 25) & 1);
+        kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
         return 0;
 }
 
@@ -130,7 +120,7 @@ int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run,
          * space do its magic.
          */
 
-        if (vcpu->arch.hsr & HSR_ISV) {
+        if (kvm_vcpu_dabt_isvalid(vcpu)) {
                 ret = decode_hsr(vcpu, fault_ipa, &mmio);
                 if (ret)
                         return ret;
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 99e07c7dd745..965706578f13 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -20,7 +20,6 @@
 #include <linux/kvm_host.h>
 #include <linux/io.h>
 #include <trace/events/kvm.h>
-#include <asm/idmap.h>
 #include <asm/pgalloc.h>
 #include <asm/cacheflush.h>
 #include <asm/kvm_arm.h>
@@ -28,28 +27,23 @@
 #include <asm/kvm_mmio.h>
 #include <asm/kvm_asm.h>
 #include <asm/kvm_emulate.h>
-#include <asm/mach/map.h>
-#include <trace/events/kvm.h>
 
 #include "trace.h"
 
 extern char  __hyp_idmap_text_start[], __hyp_idmap_text_end[];
 
+static pgd_t *boot_hyp_pgd;
+static pgd_t *hyp_pgd;
 static DEFINE_MUTEX(kvm_hyp_pgd_mutex);
 
-static void kvm_tlb_flush_vmid(struct kvm *kvm)
-{
-        kvm_call_hyp(__kvm_tlb_flush_vmid, kvm);
-}
+static void *init_bounce_page;
+static unsigned long hyp_idmap_start;
+static unsigned long hyp_idmap_end;
+static phys_addr_t hyp_idmap_vector;
 
-static void kvm_set_pte(pte_t *pte, pte_t new_pte)
+static void kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
 {
-        pte_val(*pte) = new_pte;
-        /*
-         * flush_pmd_entry just takes a void pointer and cleans the necessary
-         * cache entries, so we can reuse the function for ptes.
-         */
-        flush_pmd_entry(pte);
+        kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, kvm, ipa);
 }
 
 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
@@ -84,88 +78,165 @@ static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
         return p;
 }
 
-static void free_ptes(pmd_t *pmd, unsigned long addr)
+static void clear_pud_entry(pud_t *pud)
 {
-        pte_t *pte;
-        unsigned int i;
+        pmd_t *pmd_table = pmd_offset(pud, 0);
+        pud_clear(pud);
+        pmd_free(NULL, pmd_table);
+        put_page(virt_to_page(pud));
+}
 
-        for (i = 0; i < PTRS_PER_PMD; i++, addr += PMD_SIZE) {
-                if (!pmd_none(*pmd) && pmd_table(*pmd)) {
-                        pte = pte_offset_kernel(pmd, addr);
-                        pte_free_kernel(NULL, pte);
-                }
-                pmd++;
+static void clear_pmd_entry(pmd_t *pmd)
+{
+        pte_t *pte_table = pte_offset_kernel(pmd, 0);
+        pmd_clear(pmd);
+        pte_free_kernel(NULL, pte_table);
+        put_page(virt_to_page(pmd));
+}
+
+static bool pmd_empty(pmd_t *pmd)
+{
+        struct page *pmd_page = virt_to_page(pmd);
+        return page_count(pmd_page) == 1;
+}
+
+static void clear_pte_entry(pte_t *pte)
+{
+        if (pte_present(*pte)) {
+                kvm_set_pte(pte, __pte(0));
+                put_page(virt_to_page(pte));
         }
 }
 
-/**
- * free_hyp_pmds - free a Hyp-mode level-2 tables and child level-3 tables
- *
- * Assumes this is a page table used strictly in Hyp-mode and therefore contains
- * only mappings in the kernel memory area, which is above PAGE_OFFSET.
- */
-void free_hyp_pmds(void)
+static bool pte_empty(pte_t *pte)
+{
+        struct page *pte_page = virt_to_page(pte);
+        return page_count(pte_page) == 1;
+}
+
+static void unmap_range(pgd_t *pgdp, unsigned long long start, u64 size)
 {
         pgd_t *pgd;
         pud_t *pud;
         pmd_t *pmd;
-        unsigned long addr;
+        pte_t *pte;
+        unsigned long long addr = start, end = start + size;
+        u64 range;
 
-        mutex_lock(&kvm_hyp_pgd_mutex);
-        for (addr = PAGE_OFFSET; addr != 0; addr += PGDIR_SIZE) {
-                pgd = hyp_pgd + pgd_index(addr);
+        while (addr < end) {
+                pgd = pgdp + pgd_index(addr);
                 pud = pud_offset(pgd, addr);
-
-                if (pud_none(*pud))
+                if (pud_none(*pud)) {
+                        addr += PUD_SIZE;
                         continue;
-                BUG_ON(pud_bad(*pud));
+                }
 
                 pmd = pmd_offset(pud, addr);
-                free_ptes(pmd, addr);
-                pmd_free(NULL, pmd);
-                pud_clear(pud);
+                if (pmd_none(*pmd)) {
+                        addr += PMD_SIZE;
+                        continue;
+                }
+
+                pte = pte_offset_kernel(pmd, addr);
+                clear_pte_entry(pte);
+                range = PAGE_SIZE;
+
+                /* If we emptied the pte, walk back up the ladder */
+                if (pte_empty(pte)) {
+                        clear_pmd_entry(pmd);
+                        range = PMD_SIZE;
+                        if (pmd_empty(pmd)) {
+                                clear_pud_entry(pud);
+                                range = PUD_SIZE;
+                        }
+                }
+
+                addr += range;
+        }
+}
+
+/**
+ * free_boot_hyp_pgd - free HYP boot page tables
+ *
+ * Free the HYP boot page tables. The bounce page is also freed.
+ */
+void free_boot_hyp_pgd(void)
+{
+        mutex_lock(&kvm_hyp_pgd_mutex);
+
+        if (boot_hyp_pgd) {
+                unmap_range(boot_hyp_pgd, hyp_idmap_start, PAGE_SIZE);
+                unmap_range(boot_hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
+                kfree(boot_hyp_pgd);
+                boot_hyp_pgd = NULL;
         }
+
+        if (hyp_pgd)
+                unmap_range(hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
+
+        kfree(init_bounce_page);
+        init_bounce_page = NULL;
+
         mutex_unlock(&kvm_hyp_pgd_mutex);
 }
 
-static void create_hyp_pte_mappings(pmd_t *pmd, unsigned long start,
-                                    unsigned long end)
+/**
+ * free_hyp_pgds - free Hyp-mode page tables
+ *
+ * Assumes hyp_pgd is a page table used strictly in Hyp-mode and
+ * therefore contains either mappings in the kernel memory area (above
+ * PAGE_OFFSET), or device mappings in the vmalloc range (from
+ * VMALLOC_START to VMALLOC_END).
+ *
+ * boot_hyp_pgd should only map two pages for the init code.
+ */
+void free_hyp_pgds(void)
 {
-        pte_t *pte;
         unsigned long addr;
-        struct page *page;
 
-        for (addr = start & PAGE_MASK; addr < end; addr += PAGE_SIZE) {
-                pte = pte_offset_kernel(pmd, addr);
-                BUG_ON(!virt_addr_valid(addr));
-                page = virt_to_page(addr);
-                kvm_set_pte(pte, mk_pte(page, PAGE_HYP));
+        free_boot_hyp_pgd();
+
+        mutex_lock(&kvm_hyp_pgd_mutex);
+
+        if (hyp_pgd) {
+                for (addr = PAGE_OFFSET; virt_addr_valid(addr); addr += PGDIR_SIZE)
+                        unmap_range(hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
+                for (addr = VMALLOC_START; is_vmalloc_addr((void*)addr); addr += PGDIR_SIZE)
+                        unmap_range(hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
+                kfree(hyp_pgd);
+                hyp_pgd = NULL;
         }
+
+        mutex_unlock(&kvm_hyp_pgd_mutex);
 }
 
-static void create_hyp_io_pte_mappings(pmd_t *pmd, unsigned long start,
-                                       unsigned long end,
-                                       unsigned long *pfn_base)
+static void create_hyp_pte_mappings(pmd_t *pmd, unsigned long start,
+                                    unsigned long end, unsigned long pfn,
+                                    pgprot_t prot)
 {
         pte_t *pte;
         unsigned long addr;
 
-        for (addr = start & PAGE_MASK; addr < end; addr += PAGE_SIZE) {
+        addr = start;
+        do {
                 pte = pte_offset_kernel(pmd, addr);
-                BUG_ON(pfn_valid(*pfn_base));
-                kvm_set_pte(pte, pfn_pte(*pfn_base, PAGE_HYP_DEVICE));
-                (*pfn_base)++;
-        }
+                kvm_set_pte(pte, pfn_pte(pfn, prot));
+                get_page(virt_to_page(pte));
+                kvm_flush_dcache_to_poc(pte, sizeof(*pte));
+                pfn++;
+        } while (addr += PAGE_SIZE, addr != end);
 }
 
 static int create_hyp_pmd_mappings(pud_t *pud, unsigned long start,
-                                   unsigned long end, unsigned long *pfn_base)
+                                   unsigned long end, unsigned long pfn,
+                                   pgprot_t prot)
 {
         pmd_t *pmd;
         pte_t *pte;
         unsigned long addr, next;
 
-        for (addr = start; addr < end; addr = next) {
+        addr = start;
+        do {
                 pmd = pmd_offset(pud, addr);
 
                 BUG_ON(pmd_sect(*pmd));
@@ -177,42 +248,34 @@ static int create_hyp_pmd_mappings(pud_t *pud, unsigned long start,
                                 return -ENOMEM;
                         }
                         pmd_populate_kernel(NULL, pmd, pte);
+                        get_page(virt_to_page(pmd));
+                        kvm_flush_dcache_to_poc(pmd, sizeof(*pmd));
                 }
 
                 next = pmd_addr_end(addr, end);
 
-                /*
-                 * If pfn_base is NULL, we map kernel pages into HYP with the
-                 * virtual address. Otherwise, this is considered an I/O
-                 * mapping and we map the physical region starting at
-                 * *pfn_base to [start, end[.
-                 */
-                if (!pfn_base)
-                        create_hyp_pte_mappings(pmd, addr, next);
-                else
-                        create_hyp_io_pte_mappings(pmd, addr, next, pfn_base);
-        }
+                create_hyp_pte_mappings(pmd, addr, next, pfn, prot);
+                pfn += (next - addr) >> PAGE_SHIFT;
+        } while (addr = next, addr != end);
 
         return 0;
 }
 
-static int __create_hyp_mappings(void *from, void *to, unsigned long *pfn_base)
+static int __create_hyp_mappings(pgd_t *pgdp,
+                                 unsigned long start, unsigned long end,
+                                 unsigned long pfn, pgprot_t prot)
 {
-        unsigned long start = (unsigned long)from;
-        unsigned long end = (unsigned long)to;
         pgd_t *pgd;
         pud_t *pud;
         pmd_t *pmd;
         unsigned long addr, next;
         int err = 0;
 
-        BUG_ON(start > end);
-        if (start < PAGE_OFFSET)
-                return -EINVAL;
-
         mutex_lock(&kvm_hyp_pgd_mutex);
-        for (addr = start; addr < end; addr = next) {
-                pgd = hyp_pgd + pgd_index(addr);
+        addr = start & PAGE_MASK;
+        end = PAGE_ALIGN(end);
+        do {
+                pgd = pgdp + pgd_index(addr);
                 pud = pud_offset(pgd, addr);
 
                 if (pud_none_or_clear_bad(pud)) {
@@ -223,43 +286,64 @@ static int __create_hyp_mappings(void *from, void *to, unsigned long *pfn_base)
                                 goto out;
                         }
                         pud_populate(NULL, pud, pmd);
+                        get_page(virt_to_page(pud));
+                        kvm_flush_dcache_to_poc(pud, sizeof(*pud));
                 }
 
                 next = pgd_addr_end(addr, end);
-                err = create_hyp_pmd_mappings(pud, addr, next, pfn_base);
+                err = create_hyp_pmd_mappings(pud, addr, next, pfn, prot);
                 if (err)
                         goto out;
-        }
+                pfn += (next - addr) >> PAGE_SHIFT;
+        } while (addr = next, addr != end);
 out:
         mutex_unlock(&kvm_hyp_pgd_mutex);
         return err;
 }
 
 /**
- * create_hyp_mappings - map a kernel virtual address range in Hyp mode
+ * create_hyp_mappings - duplicate a kernel virtual address range in Hyp mode
  * @from:       The virtual kernel start address of the range
  * @to:         The virtual kernel end address of the range (exclusive)
  *
- * The same virtual address as the kernel virtual address is also used in
- * Hyp-mode mapping to the same underlying physical pages.
- *
- * Note: Wrapping around zero in the "to" address is not supported.
+ * The same virtual address as the kernel virtual address is also used
+ * in Hyp-mode mapping (modulo HYP_PAGE_OFFSET) to the same underlying
+ * physical pages.
  */
 int create_hyp_mappings(void *from, void *to)
 {
-        return __create_hyp_mappings(from, to, NULL);
+        unsigned long phys_addr = virt_to_phys(from);
+        unsigned long start = KERN_TO_HYP((unsigned long)from);
+        unsigned long end = KERN_TO_HYP((unsigned long)to);
+
+        /* Check for a valid kernel memory mapping */
+        if (!virt_addr_valid(from) || !virt_addr_valid(to - 1))
+                return -EINVAL;
+
+        return __create_hyp_mappings(hyp_pgd, start, end,
+                                     __phys_to_pfn(phys_addr), PAGE_HYP);
 }
 
 /**
- * create_hyp_io_mappings - map a physical IO range in Hyp mode
- * @from:       The virtual HYP start address of the range
- * @to:         The virtual HYP end address of the range (exclusive)
- * @addr:       The physical start address which gets mapped
+ * create_hyp_io_mappings - duplicate a kernel IO mapping into Hyp mode
+ * @from:       The kernel start VA of the range
+ * @to:         The kernel end VA of the range (exclusive)
+ * @phys_addr:  The physical start address which gets mapped
+ *
+ * The resulting HYP VA is the same as the kernel VA, modulo
+ * HYP_PAGE_OFFSET.
  */
-int create_hyp_io_mappings(void *from, void *to, phys_addr_t addr)
+int create_hyp_io_mappings(void *from, void *to, phys_addr_t phys_addr)
 {
-        unsigned long pfn = __phys_to_pfn(addr);
-        return __create_hyp_mappings(from, to, &pfn);
+        unsigned long start = KERN_TO_HYP((unsigned long)from);
+        unsigned long end = KERN_TO_HYP((unsigned long)to);
+
+        /* Check for a valid kernel IO mapping */
+        if (!is_vmalloc_addr(from) || !is_vmalloc_addr(to - 1))
+                return -EINVAL;
+
+        return __create_hyp_mappings(hyp_pgd, start, end,
+                                     __phys_to_pfn(phys_addr), PAGE_HYP_DEVICE);
 }
 
 /**
@@ -290,48 +374,12 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm)
         VM_BUG_ON((unsigned long)pgd & (S2_PGD_SIZE - 1));
 
         memset(pgd, 0, PTRS_PER_S2_PGD * sizeof(pgd_t));
-        clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
+        kvm_clean_pgd(pgd);
         kvm->arch.pgd = pgd;
 
         return 0;
 }
 
-static void clear_pud_entry(pud_t *pud)
-{
-        pmd_t *pmd_table = pmd_offset(pud, 0);
-        pud_clear(pud);
-        pmd_free(NULL, pmd_table);
-        put_page(virt_to_page(pud));
-}
-
-static void clear_pmd_entry(pmd_t *pmd)
-{
-        pte_t *pte_table = pte_offset_kernel(pmd, 0);
-        pmd_clear(pmd);
-        pte_free_kernel(NULL, pte_table);
-        put_page(virt_to_page(pmd));
-}
-
-static bool pmd_empty(pmd_t *pmd)
-{
-        struct page *pmd_page = virt_to_page(pmd);
-        return page_count(pmd_page) == 1;
-}
-
-static void clear_pte_entry(pte_t *pte)
-{
-        if (pte_present(*pte)) {
-                kvm_set_pte(pte, __pte(0));
-                put_page(virt_to_page(pte));
-        }
-}
-
-static bool pte_empty(pte_t *pte)
-{
-        struct page *pte_page = virt_to_page(pte);
-        return page_count(pte_page) == 1;
-}
-
 /**
  * unmap_stage2_range -- Clear stage2 page table entries to unmap a range
  * @kvm:   The VM pointer
@@ -345,43 +393,7 @@ static bool pte_empty(pte_t *pte)
  */
 static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size)
 {
-        pgd_t *pgd;
-        pud_t *pud;
-        pmd_t *pmd;
-        pte_t *pte;
-        phys_addr_t addr = start, end = start + size;
-        u64 range;
-
-        while (addr < end) {
-                pgd = kvm->arch.pgd + pgd_index(addr);
-                pud = pud_offset(pgd, addr);
-                if (pud_none(*pud)) {
-                        addr += PUD_SIZE;
-                        continue;
-                }
-
-                pmd = pmd_offset(pud, addr);
-                if (pmd_none(*pmd)) {
-                        addr += PMD_SIZE;
-                        continue;
-                }
-
-                pte = pte_offset_kernel(pmd, addr);
-                clear_pte_entry(pte);
-                range = PAGE_SIZE;
-
-                /* If we emptied the pte, walk back up the ladder */
-                if (pte_empty(pte)) {
-                        clear_pmd_entry(pmd);
-                        range = PMD_SIZE;
-                        if (pmd_empty(pmd)) {
-                                clear_pud_entry(pud);
-                                range = PUD_SIZE;
-                        }
-                }
-
-                addr += range;
-        }
+        unmap_range(kvm->arch.pgd, start, size);
 }
 
 /**
@@ -422,22 +434,22 @@ static int stage2_set_pte(struct kvm *kvm, struct kvm_mmu_memory_cache *cache,
                         return 0; /* ignore calls from kvm_set_spte_hva */
                 pmd = mmu_memory_cache_alloc(cache);
                 pud_populate(NULL, pud, pmd);
-                pmd += pmd_index(addr);
                 get_page(virt_to_page(pud));
-        } else
-                pmd = pmd_offset(pud, addr);
+        }
+
+        pmd = pmd_offset(pud, addr);
 
         /* Create 2nd stage page table mapping - Level 2 */
         if (pmd_none(*pmd)) {
                 if (!cache)
                         return 0; /* ignore calls from kvm_set_spte_hva */
                 pte = mmu_memory_cache_alloc(cache);
-                clean_pte_table(pte);
+                kvm_clean_pte(pte);
                 pmd_populate_kernel(NULL, pmd, pte);
-                pte += pte_index(addr);
                 get_page(virt_to_page(pmd));
-        } else
-                pte = pte_offset_kernel(pmd, addr);
+        }
+
+        pte = pte_offset_kernel(pmd, addr);
 
         if (iomap && pte_present(*pte))
                 return -EFAULT;
@@ -446,7 +458,7 @@ static int stage2_set_pte(struct kvm *kvm, struct kvm_mmu_memory_cache *cache,
         old_pte = *pte;
         kvm_set_pte(pte, *new_pte);
         if (pte_present(old_pte))
-                kvm_tlb_flush_vmid(kvm);
+                kvm_tlb_flush_vmid_ipa(kvm, addr);
         else
                 get_page(virt_to_page(pte));
 
@@ -473,7 +485,8 @@ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
         pfn = __phys_to_pfn(pa);
 
         for (addr = guest_ipa; addr < end; addr += PAGE_SIZE) {
-                pte_t pte = pfn_pte(pfn, PAGE_S2_DEVICE | L_PTE_S2_RDWR);
+                pte_t pte = pfn_pte(pfn, PAGE_S2_DEVICE);
+                kvm_set_s2pte_writable(&pte);
 
                 ret = mmu_topup_memory_cache(&cache, 2, 2);
                 if (ret)
@@ -492,29 +505,6 @@ out:
         return ret;
 }
 
-static void coherent_icache_guest_page(struct kvm *kvm, gfn_t gfn)
-{
-        /*
-         * If we are going to insert an instruction page and the icache is
-         * either VIPT or PIPT, there is a potential problem where the host
-         * (or another VM) may have used the same page as this guest, and we
-         * read incorrect data from the icache.  If we're using a PIPT cache,
-         * we can invalidate just that page, but if we are using a VIPT cache
-         * we need to invalidate the entire icache - damn shame - as written
-         * in the ARM ARM (DDI 0406C.b - Page B3-1393).
-         *
-         * VIVT caches are tagged using both the ASID and the VMID and doesn't
-         * need any kind of flushing (DDI 0406C.b - Page B3-1392).
-         */
-        if (icache_is_pipt()) {
-                unsigned long hva = gfn_to_hva(kvm, gfn);
-                __cpuc_coherent_user_range(hva, hva + PAGE_SIZE);
-        } else if (!icache_is_vivt_asid_tagged()) {
-                /* any kind of VIPT cache */
-                __flush_icache_all();
-        }
-}
-
 static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
                           gfn_t gfn, struct kvm_memory_slot *memslot,
                           unsigned long fault_status)
@@ -526,7 +516,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
         unsigned long mmu_seq;
         struct kvm_mmu_memory_cache *memcache = &vcpu->arch.mmu_page_cache;
 
-        write_fault = kvm_is_write_fault(vcpu->arch.hsr);
+        write_fault = kvm_is_write_fault(kvm_vcpu_get_hsr(vcpu));
         if (fault_status == FSC_PERM && !write_fault) {
                 kvm_err("Unexpected L2 read permission error\n");
                 return -EFAULT;
@@ -560,7 +550,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
         if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
                 goto out_unlock;
         if (writable) {
-                pte_val(new_pte) |= L_PTE_S2_RDWR;
+                kvm_set_s2pte_writable(&new_pte);
                 kvm_set_pfn_dirty(pfn);
         }
         stage2_set_pte(vcpu->kvm, memcache, fault_ipa, &new_pte, false);
@@ -585,7 +575,6 @@ out_unlock:
  */
 int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
-        unsigned long hsr_ec;
         unsigned long fault_status;
         phys_addr_t fault_ipa;
         struct kvm_memory_slot *memslot;
@@ -593,18 +582,17 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
         gfn_t gfn;
         int ret, idx;
 
-        hsr_ec = vcpu->arch.hsr >> HSR_EC_SHIFT;
-        is_iabt = (hsr_ec == HSR_EC_IABT);
-        fault_ipa = ((phys_addr_t)vcpu->arch.hpfar & HPFAR_MASK) << 8;
+        is_iabt = kvm_vcpu_trap_is_iabt(vcpu);
+        fault_ipa = kvm_vcpu_get_fault_ipa(vcpu);
 
-        trace_kvm_guest_fault(*vcpu_pc(vcpu), vcpu->arch.hsr,
-                              vcpu->arch.hxfar, fault_ipa);
+        trace_kvm_guest_fault(*vcpu_pc(vcpu), kvm_vcpu_get_hsr(vcpu),
+                              kvm_vcpu_get_hfar(vcpu), fault_ipa);
 
         /* Check the stage-2 fault is trans. fault or write fault */
-        fault_status = (vcpu->arch.hsr & HSR_FSC_TYPE);
+        fault_status = kvm_vcpu_trap_get_fault(vcpu);
         if (fault_status != FSC_FAULT && fault_status != FSC_PERM) {
-                kvm_err("Unsupported fault status: EC=%#lx DFCS=%#lx\n",
-                        hsr_ec, fault_status);
+                kvm_err("Unsupported fault status: EC=%#x DFCS=%#lx\n",
+                        kvm_vcpu_trap_get_class(vcpu), fault_status);
                 return -EFAULT;
         }
 
@@ -614,7 +602,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
         if (!kvm_is_visible_gfn(vcpu->kvm, gfn)) {
                 if (is_iabt) {
                         /* Prefetch Abort on I/O address */
-                        kvm_inject_pabt(vcpu, vcpu->arch.hxfar);
+                        kvm_inject_pabt(vcpu, kvm_vcpu_get_hfar(vcpu));
                         ret = 1;
                         goto out_unlock;
                 }
@@ -626,8 +614,13 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
                         goto out_unlock;
                 }
 
-                /* Adjust page offset */
-                fault_ipa |= vcpu->arch.hxfar & ~PAGE_MASK;
+                /*
+                 * The IPA is reported as [MAX:12], so we need to
+                 * complement it with the bottom 12 bits from the
+                 * faulting VA. This is always 12 bits, irrespective
+                 * of the page size.
+                 */
+                fault_ipa |= kvm_vcpu_get_hfar(vcpu) & ((1 << 12) - 1);
                 ret = io_mem_abort(vcpu, run, fault_ipa);
                 goto out_unlock;
         }
@@ -682,7 +675,7 @@ static void handle_hva_to_gpa(struct kvm *kvm,
 static void kvm_unmap_hva_handler(struct kvm *kvm, gpa_t gpa, void *data)
 {
         unmap_stage2_range(kvm, gpa, PAGE_SIZE);
-        kvm_tlb_flush_vmid(kvm);
+        kvm_tlb_flush_vmid_ipa(kvm, gpa);
 }
 
 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
@@ -736,47 +729,105 @@ void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu)
 
 phys_addr_t kvm_mmu_get_httbr(void)
 {
-        VM_BUG_ON(!virt_addr_valid(hyp_pgd));
         return virt_to_phys(hyp_pgd);
 }
 
+phys_addr_t kvm_mmu_get_boot_httbr(void)
+{
+        return virt_to_phys(boot_hyp_pgd);
+}
+
+phys_addr_t kvm_get_idmap_vector(void)
+{
+        return hyp_idmap_vector;
+}
+
 int kvm_mmu_init(void)
 {
-        if (!hyp_pgd) {
+        int err;
+
+        hyp_idmap_start = virt_to_phys(__hyp_idmap_text_start);
+        hyp_idmap_end = virt_to_phys(__hyp_idmap_text_end);
+        hyp_idmap_vector = virt_to_phys(__kvm_hyp_init);
+
+        if ((hyp_idmap_start ^ hyp_idmap_end) & PAGE_MASK) {
+                /*
+                 * Our init code is crossing a page boundary. Allocate
+                 * a bounce page, copy the code over and use that.
+                 */
+                size_t len = __hyp_idmap_text_end - __hyp_idmap_text_start;
+                phys_addr_t phys_base;
+
+                init_bounce_page = kmalloc(PAGE_SIZE, GFP_KERNEL);
+                if (!init_bounce_page) {
+                        kvm_err("Couldn't allocate HYP init bounce page\n");
+                        err = -ENOMEM;
+                        goto out;
+                }
+
+                memcpy(init_bounce_page, __hyp_idmap_text_start, len);
+                /*
+                 * Warning: the code we just copied to the bounce page
+                 * must be flushed to the point of coherency.
+                 * Otherwise, the data may be sitting in L2, and HYP
+                 * mode won't be able to observe it as it runs with
+                 * caches off at that point.
+                 */
+                kvm_flush_dcache_to_poc(init_bounce_page, len);
+
+                phys_base = virt_to_phys(init_bounce_page);
+                hyp_idmap_vector += phys_base - hyp_idmap_start;
+                hyp_idmap_start = phys_base;
+                hyp_idmap_end = phys_base + len;
+
+                kvm_info("Using HYP init bounce page @%lx\n",
+                         (unsigned long)phys_base);
+        }
+
+        hyp_pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
+        boot_hyp_pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
+        if (!hyp_pgd || !boot_hyp_pgd) {
                 kvm_err("Hyp mode PGD not allocated\n");
-                return -ENOMEM;
+                err = -ENOMEM;
+                goto out;
         }
 
-        return 0;
-}
+        /* Create the idmap in the boot page tables */
+        err =   __create_hyp_mappings(boot_hyp_pgd,
+                                      hyp_idmap_start, hyp_idmap_end,
+                                      __phys_to_pfn(hyp_idmap_start),
+                                      PAGE_HYP);
 
-/**
- * kvm_clear_idmap - remove all idmaps from the hyp pgd
- *
- * Free the underlying pmds for all pgds in range and clear the pgds (but
- * don't free them) afterwards.
- */
-void kvm_clear_hyp_idmap(void)
-{
-        unsigned long addr, end;
-        unsigned long next;
-        pgd_t *pgd = hyp_pgd;
-        pud_t *pud;
-        pmd_t *pmd;
+        if (err) {
+                kvm_err("Failed to idmap %lx-%lx\n",
+                        hyp_idmap_start, hyp_idmap_end);
+                goto out;
+        }
 
-        addr = virt_to_phys(__hyp_idmap_text_start);
-        end = virt_to_phys(__hyp_idmap_text_end);
+        /* Map the very same page at the trampoline VA */
+        err =   __create_hyp_mappings(boot_hyp_pgd,
+                                      TRAMPOLINE_VA, TRAMPOLINE_VA + PAGE_SIZE,
+                                      __phys_to_pfn(hyp_idmap_start),
+                                      PAGE_HYP);
+        if (err) {
+                kvm_err("Failed to map trampoline @%lx into boot HYP pgd\n",
+                        TRAMPOLINE_VA);
+                goto out;
+        }
 
-        pgd += pgd_index(addr);
-        do {
-                next = pgd_addr_end(addr, end);
-                if (pgd_none_or_clear_bad(pgd))
-                        continue;
-                pud = pud_offset(pgd, addr);
-                pmd = pmd_offset(pud, addr);
+        /* Map the same page again into the runtime page tables */
+        err =   __create_hyp_mappings(hyp_pgd,
+                                      TRAMPOLINE_VA, TRAMPOLINE_VA + PAGE_SIZE,
+                                      __phys_to_pfn(hyp_idmap_start),
+                                      PAGE_HYP);
+        if (err) {
+                kvm_err("Failed to map trampoline @%lx into runtime HYP pgd\n",
+                        TRAMPOLINE_VA);
+                goto out;
+        }
 
-                pud_clear(pud);
-                clean_pmd_entry(pmd);
-                pmd_free(NULL, (pmd_t *)((unsigned long)pmd & PAGE_MASK));
-        } while (pgd++, addr = next, addr < end);
+        return 0;
+out:
+        free_hyp_pgds();
+        return err;
 }
diff --git a/arch/arm/kvm/perf.c b/arch/arm/kvm/perf.c
new file mode 100644
index 000000000000..1a3849da0b4b
--- /dev/null
+++ b/arch/arm/kvm/perf.c
@@ -0,0 +1,68 @@
+/*
+ * Based on the x86 implementation.
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/perf_event.h>
+#include <linux/kvm_host.h>
+
+#include <asm/kvm_emulate.h>
+
+static int kvm_is_in_guest(void)
+{
+        return kvm_arm_get_running_vcpu() != NULL;
+}
+
+static int kvm_is_user_mode(void)
+{
+        struct kvm_vcpu *vcpu;
+
+        vcpu = kvm_arm_get_running_vcpu();
+
+        if (vcpu)
+                return !vcpu_mode_priv(vcpu);
+
+        return 0;
+}
+
+static unsigned long kvm_get_guest_ip(void)
+{
+        struct kvm_vcpu *vcpu;
+
+        vcpu = kvm_arm_get_running_vcpu();
+
+        if (vcpu)
+                return *vcpu_pc(vcpu);
+
+        return 0;
+}
+
+static struct perf_guest_info_callbacks kvm_guest_cbs = {
+        .is_in_guest    = kvm_is_in_guest,
+        .is_user_mode   = kvm_is_user_mode,
+        .get_guest_ip   = kvm_get_guest_ip,
+};
+
+int kvm_perf_init(void)
+{
+        return perf_register_guest_info_callbacks(&kvm_guest_cbs);
+}
+
+int kvm_perf_teardown(void)
+{
+        return perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
+}
diff --git a/arch/arm/kvm/vgic.c b/arch/arm/kvm/vgic.c
index 0e4cfe123b38..17c5ac7d10ed 100644
--- a/arch/arm/kvm/vgic.c
+++ b/arch/arm/kvm/vgic.c
@@ -1477,7 +1477,7 @@ int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
         if (addr & ~KVM_PHYS_MASK)
                 return -E2BIG;
 
-        if (addr & ~PAGE_MASK)
+        if (addr & (SZ_4K - 1))
                 return -EINVAL;
 
         mutex_lock(&kvm->lock);
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 6071f4c3d654..02802386b894 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,14 +1,15 @@
 if ARCH_AT91
 
-config HAVE_AT91_DATAFLASH_CARD
-        bool
-
 config HAVE_AT91_DBGU0
         bool
 
 config HAVE_AT91_DBGU1
         bool
 
+config AT91_PMC_UNIT
+        bool
+        default !ARCH_AT91X40
+
 config AT91_SAM9_ALT_RESET
         bool
         default !ARCH_AT91X40
@@ -17,17 +18,59 @@ config AT91_SAM9G45_RESET
         bool
         default !ARCH_AT91X40
 
+config AT91_SAM9_TIME
+        bool
+
 config SOC_AT91SAM9
         bool
+        select AT91_SAM9_TIME
         select CPU_ARM926T
         select GENERIC_CLOCKEVENTS
         select MULTI_IRQ_HANDLER
         select SPARSE_IRQ
 
+config SOC_SAMA5
+        bool
+        select AT91_SAM9_TIME
+        select CPU_V7
+        select GENERIC_CLOCKEVENTS
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
+
 menu "Atmel AT91 System-on-Chip"
 
+choice
+
+        prompt "Core type"
+
+config SOC_SAM_V4_V5
+        bool "ARM7/ARM9"
+        help
+          Select this if you are using one of Atmel's AT91SAM9, AT91RM9200
+          or AT91X40 SoC.
+
+config SOC_SAM_V7
+        bool "Cortex A5"
+        help
+          Select this if you are using one of Atmel's SAMA5D3 SoC.
+
+endchoice
+
 comment "Atmel AT91 Processor"
 
+if SOC_SAM_V7
+config SOC_SAMA5D3
+        bool "SAMA5D3 family"
+        depends on SOC_SAM_V7
+        select SOC_SAMA5
+        select HAVE_FB_ATMEL
+        select HAVE_AT91_DBGU1
+        help
+          Select this if you are using one of Atmel's SAMA5D3 family SoC.
+          This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35.
+endif
+
+if SOC_SAM_V4_V5
 config SOC_AT91RM9200
         bool "AT91RM9200"
         select CPU_ARM920T
@@ -93,394 +136,10 @@ config SOC_AT91SAM9N12
         help
           Select this if you are using Atmel's AT91SAM9N12 SoC.
 
-choice
-        prompt "Atmel AT91 Processor Devices for non DT boards"
-
-config ARCH_AT91_NONE
-        bool "None"
-
-config ARCH_AT91RM9200
-        bool "AT91RM9200"
-        select SOC_AT91RM9200
-
-config ARCH_AT91SAM9260
-        bool "AT91SAM9260 or AT91SAM9XE"
-        select SOC_AT91SAM9260
-
-config ARCH_AT91SAM9261
-        bool "AT91SAM9261"
-        select SOC_AT91SAM9261
-
-config ARCH_AT91SAM9G10
-        bool "AT91SAM9G10"
-        select SOC_AT91SAM9261
-
-config ARCH_AT91SAM9263
-        bool "AT91SAM9263"
-        select SOC_AT91SAM9263
-
-config ARCH_AT91SAM9RL
-        bool "AT91SAM9RL"
-        select SOC_AT91SAM9RL
-
-config ARCH_AT91SAM9G20
-        bool "AT91SAM9G20"
-        select SOC_AT91SAM9260
-
-config ARCH_AT91SAM9G45
-        bool "AT91SAM9G45"
-        select SOC_AT91SAM9G45
-
-config ARCH_AT91X40
-        bool "AT91x40"
-        depends on !MMU
-        select ARCH_USES_GETTIMEOFFSET
-        select MULTI_IRQ_HANDLER
-        select SPARSE_IRQ
-
-endchoice
-
-config AT91_PMC_UNIT
-        bool
-        default !ARCH_AT91X40
-
-# ----------------------------------------------------------
-
-if ARCH_AT91RM9200
-
-comment "AT91RM9200 Board Type"
-
-config MACH_ONEARM
-        bool "Ajeco 1ARM Single Board Computer"
-        help
-          Select this if you are using Ajeco's 1ARM Single Board Computer.
-          <http://www.ajeco.fi/>
-
-config ARCH_AT91RM9200DK
-        bool "Atmel AT91RM9200-DK Development board"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91RM9200-DK Development board.
-          (Discontinued)
-
-config MACH_AT91RM9200EK
-        bool "Atmel AT91RM9200-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507>
-
-config MACH_CSB337
-        bool "Cogent CSB337"
-        help
-          Select this if you are using Cogent's CSB337 board.
-          <http://www.cogcomp.com/csb_csb337.htm>
-
-config MACH_CSB637
-        bool "Cogent CSB637"
-        help
-          Select this if you are using Cogent's CSB637 board.
-          <http://www.cogcomp.com/csb_csb637.htm>
-
-config MACH_CARMEVA
-        bool "Conitec ARM&EVA"
-        help
-          Select this if you are using Conitec's AT91RM9200-MCU-Module.
-          <http://www.conitec.net/english/linuxboard.php>
-
-config MACH_ATEB9200
-        bool "Embest ATEB9200"
-        help
-          Select this if you are using Embest's ATEB9200 board.
-          <http://www.embedinfo.com/english/product/ATEB9200.asp>
-
-config MACH_KB9200
-        bool "KwikByte KB920x"
-        help
-          Select this if you are using KwikByte's KB920x board.
-          <http://www.kwikbyte.com/KB9202.html>
-
-config MACH_PICOTUX2XX
-        bool "picotux 200"
-        help
-          Select this if you are using a picotux 200.
-          <http://www.picotux.com/>
-
-config MACH_KAFA
-        bool "Sperry-Sun KAFA board"
-        help
-          Select this if you are using Sperry-Sun's KAFA board.
-
-config MACH_ECBAT91
-        bool "emQbit ECB_AT91 SBC"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using emQbit's ECB_AT91 board.
-          <http://wiki.emqbit.com/free-ecb-at91>
-
-config MACH_YL9200
-        bool "ucDragon YL-9200"
-        help
-          Select this if you are using the ucDragon YL-9200 board.
-
-config MACH_CPUAT91
-        bool "Eukrea CPUAT91"
-        help
-          Select this if you are using the Eukrea Electromatique's
-          CPUAT91 board <http://www.eukrea.com/>.
-
-config MACH_ECO920
-        bool "eco920"
-        help
-          Select this if you are using the eco920 board
-
-config MACH_RSI_EWS
-        bool "RSI Embedded Webserver"
-        depends on ARCH_AT91RM9200
-        help
-          Select this if you are using RSIs EWS board.
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9260
-
-comment "AT91SAM9260 Variants"
-
-comment "AT91SAM9260 / AT91SAM9XE Board Type"
-
-config MACH_AT91SAM9260EK
-        bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
-
-config MACH_CAM60
-        bool "KwikByte KB9260 (CAM60) board"
-        help
-          Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260.
-          <http://www.kwikbyte.com/KB9260.html>
-
-config MACH_SAM9_L9260
-        bool "Olimex SAM9-L9260 board"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260.
-          <http://www.olimex.com/dev/sam9-L9260.html>
-
-config MACH_AFEB9260
-        bool "Custom afeb9260 board v1"
-        help
-          Select this if you are using custom afeb9260 board based on
-          open hardware design. Select this for revision 1 of the board.
-          <svn://194.85.238.22/home/users/george/svn/arm9eb>
-          <http://groups.google.com/group/arm9fpga-evolution-board>
-
-config MACH_USB_A9260
-        bool "CALAO USB-A9260"
-        help
-          Select this if you are using a Calao Systems USB-A9260.
-          <http://www.calao-systems.com>
-
-config MACH_QIL_A9260
-        bool "CALAO QIL-A9260 board"
-        help
-          Select this if you are using a Calao Systems QIL-A9260 Board.
-          <http://www.calao-systems.com>
-
-config MACH_CPU9260
-        bool "Eukrea CPU9260 board"
-        help
-          Select this if you are using a Eukrea Electromatique's
-          CPU9260 Board <http://www.eukrea.com/>
-
-config MACH_FLEXIBITY
-        bool "Flexibity Connect board"
-        help
-          Select this if you are using Flexibity Connect board
-          <http://www.flexibity.com>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9261
-
-comment "AT91SAM9261 Board Type"
-
-config MACH_AT91SAM9261EK
-        bool "Atmel AT91SAM9261-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9G10
-
-comment "AT91SAM9G10 Board Type"
-
-config MACH_AT91SAM9G10EK
-        bool "Atmel AT91SAM9G10-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9263
-
-comment "AT91SAM9263 Board Type"
-
-config MACH_AT91SAM9263EK
-        bool "Atmel AT91SAM9263-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
-
-config MACH_USB_A9263
-        bool "CALAO USB-A9263"
-        help
-          Select this if you are using a Calao Systems USB-A9263.
-          <http://www.calao-systems.com>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9RL
-
-comment "AT91SAM9RL Board Type"
-
-config MACH_AT91SAM9RLEK
-        bool "Atmel AT91SAM9RL-EK Evaluation Kit"
-        help
-          Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
-
-endif
-
 # ----------------------------------------------------------
 
-if ARCH_AT91SAM9G20
-
-comment "AT91SAM9G20 Board Type"
-
-config MACH_AT91SAM9G20EK
-        bool "Atmel AT91SAM9G20-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit
-          that embeds only one SD/MMC slot.
-
-config MACH_AT91SAM9G20EK_2MMC
-        depends on MACH_AT91SAM9G20EK
-        bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots"
-        help
-          Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit
-          with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and
-          onwards.
-          <http://www.atmel.com/tools/SAM9G20-EK.aspx>
-
-config MACH_CPU9G20
-        bool "Eukrea CPU9G20 board"
-        help
-          Select this if you are using a Eukrea Electromatique's
-          CPU9G20 Board <http://www.eukrea.com/>
-
-config MACH_ACMENETUSFOXG20
-        bool "Acme Systems srl FOX Board G20"
-        help
-          Select this if you are using Acme Systems
-          FOX Board G20 <http://www.acmesystems.it>
-
-config MACH_PORTUXG20
-        bool "taskit PortuxG20"
-        help
-          Select this if you are using taskit's PortuxG20.
-          <http://www.taskit.de/en/>
-
-config MACH_STAMP9G20
-        bool "taskit Stamp9G20 CPU module"
-        help
-          Select this if you are using taskit's Stamp9G20 CPU module on its
-          evaluation board.
-          <http://www.taskit.de/en/>
-
-config MACH_PCONTROL_G20
-        bool "PControl G20 CPU module"
-        help
-          Select this if you are using taskit's Stamp9G20 CPU module on this
-          carrier board, beeing the decentralized unit of a building automation
-          system; featuring nvram, eth-switch, iso-rs485, display, io
-
-config MACH_GSIA18S
-        bool "GS_IA18_S board"
-        help
-          This enables support for the GS_IA18_S board
-          produced by GeoSIG Ltd company. This is an internet accelerograph.
-          <http://www.geosig.com>
-
-config MACH_USB_A9G20
-        bool "CALAO USB-A9G20"
-        depends on ARCH_AT91SAM9G20
-        help
-          Select this if you are using a Calao Systems USB-A9G20.
-          <http://www.calao-systems.com>
-
-endif
-
-if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
-comment "AT91SAM9260/AT91SAM9G20 boards"
-
-config MACH_SNAPPER_9260
-        bool "Bluewater Systems Snapper 9260/9G20 module"
-        help
-          Select this if you are using the Bluewater Systems Snapper 9260 or
-          Snapper 9G20 modules.
-          <http://www.bluewatersys.com/>
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9G45
-
-comment "AT91SAM9G45 Board Type"
-
-config MACH_AT91SAM9M10G45EK
-        bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
-        help
-          Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit.
-          Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10
-          families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
-          <http://www.atmel.com/tools/SAM9M10-G45-EK.aspx>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91X40
-
-comment "AT91X40 Board Type"
-
-config MACH_AT91EB01
-        bool "Atmel AT91EB01 Evaluation Kit"
-        help
-          Select this if you are using Atmel's AT91EB01 Evaluation Kit.
-          It is also a popular target for simulators such as GDB's
-          ARM simulator (commonly known as the ARMulator) and the
-          Skyeye simulator.
-
-endif
-
-# ----------------------------------------------------------
+source arch/arm/mach-at91/Kconfig.non_dt
+endif # SOC_SAM_V4_V5
 
 comment "Generic Board Type"
 
@@ -492,7 +151,7 @@ config MACH_AT91RM9200_DT
           Select this if you want to experiment device-tree with
           an Atmel RM9200 Evaluation Kit.
 
-config MACH_AT91SAM_DT
+config MACH_AT91SAM9_DT
         bool "Atmel AT91SAM Evaluation Kits with device-tree support"
         depends on SOC_AT91SAM9
         select USE_OF
@@ -500,15 +159,13 @@ config MACH_AT91SAM_DT
           Select this if you want to experiment device-tree with
           an Atmel Evaluation Kit.
 
-# ----------------------------------------------------------
-
-comment "AT91 Board Options"
-
-config MTD_AT91_DATAFLASH_CARD
-        bool "Enable DataFlash Card support"
-        depends on HAVE_AT91_DATAFLASH_CARD
+config MACH_SAMA5_DT
+        bool "Atmel SAMA5 Evaluation Kits with device-tree support"
+        depends on SOC_SAMA5
+        select USE_OF
         help
-          Enable support for the DataFlash card.
+          Select this if you want to experiment device-tree with
+          an Atmel Evaluation Kit.
 
 # ----------------------------------------------------------
 
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
new file mode 100644
index 000000000000..6c24985515a2
--- /dev/null
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -0,0 +1,399 @@
+menu "Atmel Non-DT world"
+
+config HAVE_AT91_DATAFLASH_CARD
+        bool
+
+choice
+        prompt "Atmel AT91 Processor Devices for non DT boards"
+
+config ARCH_AT91_NONE
+        bool "None"
+
+config ARCH_AT91RM9200
+        bool "AT91RM9200"
+        select SOC_AT91RM9200
+
+config ARCH_AT91SAM9260
+        bool "AT91SAM9260 or AT91SAM9XE"
+        select SOC_AT91SAM9260
+
+config ARCH_AT91SAM9261
+        bool "AT91SAM9261"
+        select SOC_AT91SAM9261
+
+config ARCH_AT91SAM9G10
+        bool "AT91SAM9G10"
+        select SOC_AT91SAM9261
+
+config ARCH_AT91SAM9263
+        bool "AT91SAM9263"
+        select SOC_AT91SAM9263
+
+config ARCH_AT91SAM9RL
+        bool "AT91SAM9RL"
+        select SOC_AT91SAM9RL
+
+config ARCH_AT91SAM9G20
+        bool "AT91SAM9G20"
+        select SOC_AT91SAM9260
+
+config ARCH_AT91SAM9G45
+        bool "AT91SAM9G45"
+        select SOC_AT91SAM9G45
+
+config ARCH_AT91X40
+        bool "AT91x40"
+        depends on !MMU
+        select ARCH_USES_GETTIMEOFFSET
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
+
+endchoice
+
+# ----------------------------------------------------------
+
+if ARCH_AT91RM9200
+
+comment "AT91RM9200 Board Type"
+
+config MACH_ONEARM
+        bool "Ajeco 1ARM Single Board Computer"
+        help
+          Select this if you are using Ajeco's 1ARM Single Board Computer.
+          <http://www.ajeco.fi/>
+
+config ARCH_AT91RM9200DK
+        bool "Atmel AT91RM9200-DK Development board"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91RM9200-DK Development board.
+          (Discontinued)
+
+config MACH_AT91RM9200EK
+        bool "Atmel AT91RM9200-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507>
+
+config MACH_CSB337
+        bool "Cogent CSB337"
+        help
+          Select this if you are using Cogent's CSB337 board.
+          <http://www.cogcomp.com/csb_csb337.htm>
+
+config MACH_CSB637
+        bool "Cogent CSB637"
+        help
+          Select this if you are using Cogent's CSB637 board.
+          <http://www.cogcomp.com/csb_csb637.htm>
+
+config MACH_CARMEVA
+        bool "Conitec ARM&EVA"
+        help
+          Select this if you are using Conitec's AT91RM9200-MCU-Module.
+          <http://www.conitec.net/english/linuxboard.php>
+
+config MACH_ATEB9200
+        bool "Embest ATEB9200"
+        help
+          Select this if you are using Embest's ATEB9200 board.
+          <http://www.embedinfo.com/english/product/ATEB9200.asp>
+
+config MACH_KB9200
+        bool "KwikByte KB920x"
+        help
+          Select this if you are using KwikByte's KB920x board.
+          <http://www.kwikbyte.com/KB9202.html>
+
+config MACH_PICOTUX2XX
+        bool "picotux 200"
+        help
+          Select this if you are using a picotux 200.
+          <http://www.picotux.com/>
+
+config MACH_KAFA
+        bool "Sperry-Sun KAFA board"
+        help
+          Select this if you are using Sperry-Sun's KAFA board.
+
+config MACH_ECBAT91
+        bool "emQbit ECB_AT91 SBC"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using emQbit's ECB_AT91 board.
+          <http://wiki.emqbit.com/free-ecb-at91>
+
+config MACH_YL9200
+        bool "ucDragon YL-9200"
+        help
+          Select this if you are using the ucDragon YL-9200 board.
+
+config MACH_CPUAT91
+        bool "Eukrea CPUAT91"
+        help
+          Select this if you are using the Eukrea Electromatique's
+          CPUAT91 board <http://www.eukrea.com/>.
+
+config MACH_ECO920
+        bool "eco920"
+        help
+          Select this if you are using the eco920 board
+
+config MACH_RSI_EWS
+        bool "RSI Embedded Webserver"
+        depends on ARCH_AT91RM9200
+        help
+          Select this if you are using RSIs EWS board.
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9260
+
+comment "AT91SAM9260 Variants"
+
+comment "AT91SAM9260 / AT91SAM9XE Board Type"
+
+config MACH_AT91SAM9260EK
+        bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
+
+config MACH_CAM60
+        bool "KwikByte KB9260 (CAM60) board"
+        help
+          Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260.
+          <http://www.kwikbyte.com/KB9260.html>
+
+config MACH_SAM9_L9260
+        bool "Olimex SAM9-L9260 board"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260.
+          <http://www.olimex.com/dev/sam9-L9260.html>
+
+config MACH_AFEB9260
+        bool "Custom afeb9260 board v1"
+        help
+          Select this if you are using custom afeb9260 board based on
+          open hardware design. Select this for revision 1 of the board.
+          <svn://194.85.238.22/home/users/george/svn/arm9eb>
+          <http://groups.google.com/group/arm9fpga-evolution-board>
+
+config MACH_USB_A9260
+        bool "CALAO USB-A9260"
+        help
+          Select this if you are using a Calao Systems USB-A9260.
+          <http://www.calao-systems.com>
+
+config MACH_QIL_A9260
+        bool "CALAO QIL-A9260 board"
+        help
+          Select this if you are using a Calao Systems QIL-A9260 Board.
+          <http://www.calao-systems.com>
+
+config MACH_CPU9260
+        bool "Eukrea CPU9260 board"
+        help
+          Select this if you are using a Eukrea Electromatique's
+          CPU9260 Board <http://www.eukrea.com/>
+
+config MACH_FLEXIBITY
+        bool "Flexibity Connect board"
+        help
+          Select this if you are using Flexibity Connect board
+          <http://www.flexibity.com>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9261
+
+comment "AT91SAM9261 Board Type"
+
+config MACH_AT91SAM9261EK
+        bool "Atmel AT91SAM9261-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9G10
+
+comment "AT91SAM9G10 Board Type"
+
+config MACH_AT91SAM9G10EK
+        bool "Atmel AT91SAM9G10-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9263
+
+comment "AT91SAM9263 Board Type"
+
+config MACH_AT91SAM9263EK
+        bool "Atmel AT91SAM9263-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
+
+config MACH_USB_A9263
+        bool "CALAO USB-A9263"
+        help
+          Select this if you are using a Calao Systems USB-A9263.
+          <http://www.calao-systems.com>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9RL
+
+comment "AT91SAM9RL Board Type"
+
+config MACH_AT91SAM9RLEK
+        bool "Atmel AT91SAM9RL-EK Evaluation Kit"
+        help
+          Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9G20
+
+comment "AT91SAM9G20 Board Type"
+
+config MACH_AT91SAM9G20EK
+        bool "Atmel AT91SAM9G20-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit
+          that embeds only one SD/MMC slot.
+
+config MACH_AT91SAM9G20EK_2MMC
+        depends on MACH_AT91SAM9G20EK
+        bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots"
+        help
+          Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit
+          with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and
+          onwards.
+          <http://www.atmel.com/tools/SAM9G20-EK.aspx>
+
+config MACH_CPU9G20
+        bool "Eukrea CPU9G20 board"
+        help
+          Select this if you are using a Eukrea Electromatique's
+          CPU9G20 Board <http://www.eukrea.com/>
+
+config MACH_ACMENETUSFOXG20
+        bool "Acme Systems srl FOX Board G20"
+        help
+          Select this if you are using Acme Systems
+          FOX Board G20 <http://www.acmesystems.it>
+
+config MACH_PORTUXG20
+        bool "taskit PortuxG20"
+        help
+          Select this if you are using taskit's PortuxG20.
+          <http://www.taskit.de/en/>
+
+config MACH_STAMP9G20
+        bool "taskit Stamp9G20 CPU module"
+        help
+          Select this if you are using taskit's Stamp9G20 CPU module on its
+          evaluation board.
+          <http://www.taskit.de/en/>
+
+config MACH_PCONTROL_G20
+        bool "PControl G20 CPU module"
+        help
+          Select this if you are using taskit's Stamp9G20 CPU module on this
+          carrier board, beeing the decentralized unit of a building automation
+          system; featuring nvram, eth-switch, iso-rs485, display, io
+
+config MACH_GSIA18S
+        bool "GS_IA18_S board"
+        help
+          This enables support for the GS_IA18_S board
+          produced by GeoSIG Ltd company. This is an internet accelerograph.
+          <http://www.geosig.com>
+
+config MACH_USB_A9G20
+        bool "CALAO USB-A9G20"
+        depends on ARCH_AT91SAM9G20
+        help
+          Select this if you are using a Calao Systems USB-A9G20.
+          <http://www.calao-systems.com>
+
+endif
+
+if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
+comment "AT91SAM9260/AT91SAM9G20 boards"
+
+config MACH_SNAPPER_9260
+        bool "Bluewater Systems Snapper 9260/9G20 module"
+        help
+          Select this if you are using the Bluewater Systems Snapper 9260 or
+          Snapper 9G20 modules.
+          <http://www.bluewatersys.com/>
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9G45
+
+comment "AT91SAM9G45 Board Type"
+
+config MACH_AT91SAM9M10G45EK
+        bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
+        help
+          Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit.
+          Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10
+          families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
+          <http://www.atmel.com/tools/SAM9M10-G45-EK.aspx>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91X40
+
+comment "AT91X40 Board Type"
+
+config MACH_AT91EB01
+        bool "Atmel AT91EB01 Evaluation Kit"
+        help
+          Select this if you are using Atmel's AT91EB01 Evaluation Kit.
+          It is also a popular target for simulators such as GDB's
+          ARM simulator (commonly known as the ARMulator) and the
+          Skyeye simulator.
+
+endif
+
+# ----------------------------------------------------------
+
+comment "AT91 Board Options"
+
+config MTD_AT91_DATAFLASH_CARD
+        bool "Enable DataFlash Card support"
+        depends on HAVE_AT91_DATAFLASH_CARD
+        help
+          Enable support for the DataFlash card.
+
+endmenu
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 39218ca6d8e8..788562dccb43 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -10,7 +10,8 @@ obj-		:=
 obj-$(CONFIG_AT91_PMC_UNIT)     += clock.o
 obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
 obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
-obj-$(CONFIG_SOC_AT91SAM9)      += at91sam926x_time.o sam9_smc.o
+obj-$(CONFIG_AT91_SAM9_TIME)    += at91sam926x_time.o
+obj-$(CONFIG_SOC_AT91SAM9)      += sam9_smc.o
 
 # CPU-specific support
 obj-$(CONFIG_SOC_AT91RM9200)    += at91rm9200.o at91rm9200_time.o
@@ -21,6 +22,7 @@ obj-$(CONFIG_SOC_AT91SAM9G45)	+= at91sam9g45.o
 obj-$(CONFIG_SOC_AT91SAM9N12)   += at91sam9n12.o
 obj-$(CONFIG_SOC_AT91SAM9X5)    += at91sam9x5.o
 obj-$(CONFIG_SOC_AT91SAM9RL)    += at91sam9rl.o
+obj-$(CONFIG_SOC_SAMA5D3)       += sama5d3.o
 
 obj-$(CONFIG_ARCH_AT91RM9200)   += at91rm9200_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9260)  += at91sam9260_devices.o
@@ -87,8 +89,11 @@ obj-$(CONFIG_MACH_SNAPPER_9260)	+= board-snapper9260.o
 obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
 
 # AT91SAM board with device-tree
-obj-$(CONFIG_MACH_AT91RM9200_DT) += board-rm9200-dt.o
-obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
+obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o
+obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o
+
+# SAMA5 board with device-tree
+obj-$(CONFIG_MACH_SAMA5_DT) += board-dt-sama5.o
 
 # AT91X40 board-specific support
 obj-$(CONFIG_MACH_AT91EB01)     += board-eb01.o
diff --git a/arch/arm/mach-at91/at91_rstc.h b/arch/arm/mach-at91/at91_rstc.h
index 875fa336800b..a600e6992920 100644
--- a/arch/arm/mach-at91/at91_rstc.h
+++ b/arch/arm/mach-at91/at91_rstc.h
@@ -23,7 +23,7 @@ extern void __iomem *at91_rstc_base;
         __raw_readl(at91_rstc_base + field)
 
 #define at91_rstc_write(field, value) \
-        __raw_writel(value, at91_rstc_base + field);
+        __raw_writel(value, at91_rstc_base + field)
 #else
 .extern at91_rstc_base
 #endif
diff --git a/arch/arm/mach-at91/at91_shdwc.h b/arch/arm/mach-at91/at91_shdwc.h
index 60478ea8bd46..9e29f31ec9a6 100644
--- a/arch/arm/mach-at91/at91_shdwc.h
+++ b/arch/arm/mach-at91/at91_shdwc.h
@@ -23,7 +23,7 @@ extern void __iomem *at91_shdwc_base;
         __raw_readl(at91_shdwc_base + field)
 
 #define at91_shdwc_write(field, value) \
-        __raw_writel(value, at91_shdwc_base + field);
+        __raw_writel(value, at91_shdwc_base + field)
 #endif
 
 #define AT91_SHDW_CR            0x00                    /* Shut Down Control Register */
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 9706c000f294..d193a409bc45 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -212,6 +212,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
         CLKDEV_CON_DEV_ID("mci_clk", "fffb4000.mmc", &mmc_clk),
         CLKDEV_CON_DEV_ID("emac_clk", "fffbc000.ethernet", &ether_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffb8000.i2c", &twi_clk),
         CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
         CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
         CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
@@ -384,7 +385,7 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0       /* Advanced Interrupt Controller (IRQ6) */
 };
 
-AT91_SOC_START(rm9200)
+AT91_SOC_START(at91rm9200)
         .map_io = at91rm9200_map_io,
         .default_irq_priority = at91rm9200_default_irq_priority,
         .ioremap_registers = at91rm9200_ioremap_registers,
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index b67cd5374117..a8ce24538da6 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -232,6 +232,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
         CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
         CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
         /* fake hclk clock */
         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
         CLKDEV_CON_ID("pioA", &pioA_clk),
@@ -395,7 +397,7 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller */
 };
 
-AT91_SOC_START(sam9260)
+AT91_SOC_START(at91sam9260)
         .map_io = at91sam9260_map_io,
         .default_irq_priority = at91sam9260_default_irq_priority,
         .ioremap_registers = at91sam9260_ioremap_registers,
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 2998a08afc2d..25efb5ac30f1 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -169,6 +169,8 @@ static struct clk *periph_clocks[] __initdata = {
 };
 
 static struct clk_lookup periph_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
@@ -337,7 +339,7 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller */
 };
 
-AT91_SOC_START(sam9261)
+AT91_SOC_START(at91sam9261)
         .map_io = at91sam9261_map_io,
         .default_irq_priority = at91sam9261_default_irq_priority,
         .ioremap_registers = at91sam9261_ioremap_registers,
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 92e0f861084a..629ea5fc95cf 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -488,7 +488,6 @@ static struct resource lcdc_resources[] = {
 };
 
 static struct platform_device at91_lcdc_device = {
-        .name           = "atmel_lcdfb",
         .id             = 0,
         .dev            = {
                                 .dma_mask               = &lcdc_dmamask,
@@ -505,6 +504,11 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
                 return;
         }
 
+        if (cpu_is_at91sam9g10())
+                at91_lcdc_device.name = "at91sam9g10-lcdfb";
+        else
+                at91_lcdc_device.name = "at91sam9261-lcdfb";
+
 #if defined(CONFIG_FB_ATMEL_STN)
         at91_set_A_periph(AT91_PIN_PB0, 0);     /* LCDVSYNC */
         at91_set_A_periph(AT91_PIN_PB1, 0);     /* LCDHSYNC */
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index b9fc60d1b33a..f44ffd2105a7 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -190,6 +190,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
         CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
         CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
         CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
         CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
@@ -374,7 +375,7 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller (IRQ1) */
 };
 
-AT91_SOC_START(sam9263)
+AT91_SOC_START(at91sam9263)
         .map_io = at91sam9263_map_io,
         .default_irq_priority = at91sam9263_default_irq_priority,
         .ioremap_registers = at91sam9263_ioremap_registers,
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index ed666f5cb01d..858c8aac2daf 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -848,7 +848,7 @@ static struct resource lcdc_resources[] = {
 };
 
 static struct platform_device at91_lcdc_device = {
-        .name           = "atmel_lcdfb",
+        .name           = "at91sam9263-lcdfb",
         .id             = 0,
         .dev            = {
                                 .dma_mask               = &lcdc_dmamask,
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index d3addee43d8d..8b7fce067652 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -228,6 +228,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_ID("hclk", &macb_clk),
         /* One additional fake clock for ohci */
         CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
         CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
@@ -262,6 +264,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
         CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
         CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
         /* fake hclk clock */
         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
         CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
@@ -418,7 +422,7 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller (IRQ0) */
 };
 
-AT91_SOC_START(sam9g45)
+AT91_SOC_START(at91sam9g45)
         .map_io = at91sam9g45_map_io,
         .default_irq_priority = at91sam9g45_default_irq_priority,
         .ioremap_registers = at91sam9g45_ioremap_registers,
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 827c9f2a70fb..acb703e13331 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -18,7 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/i2c-gpio.h>
 #include <linux/atmel-mci.h>
-#include <linux/platform_data/atmel-aes.h>
+#include <linux/platform_data/crypto-atmel.h>
 
 #include <linux/platform_data/at91_adc.h>
 
@@ -981,7 +981,6 @@ static struct resource lcdc_resources[] = {
 };
 
 static struct platform_device at91_lcdc_device = {
-        .name           = "atmel_lcdfb",
         .id             = 0,
         .dev            = {
                                 .dma_mask               = &lcdc_dmamask,
@@ -997,6 +996,11 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
         if (!data)
                 return;
 
+        if (cpu_is_at91sam9g45es())
+                at91_lcdc_device.name = "at91sam9g45es-lcdfb";
+        else
+                at91_lcdc_device.name = "at91sam9g45-lcdfb";
+
         at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
 
         at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
@@ -1900,7 +1904,8 @@ static void __init at91_add_device_tdes(void) {}
  * -------------------------------------------------------------------- */
 
 #if defined(CONFIG_CRYPTO_DEV_ATMEL_AES) || defined(CONFIG_CRYPTO_DEV_ATMEL_AES_MODULE)
-static struct aes_platform_data aes_data;
+static struct crypto_platform_data aes_data;
+static struct crypto_dma_data alt_atslave;
 static u64 aes_dmamask = DMA_BIT_MASK(32);
 
 static struct resource aes_resources[] = {
@@ -1931,23 +1936,20 @@ static struct platform_device at91sam9g45_aes_device = {
 static void __init at91_add_device_aes(void)
 {
         struct at_dma_slave     *atslave;
-        struct aes_dma_data     *alt_atslave;
-
-        alt_atslave = kzalloc(sizeof(struct aes_dma_data), GFP_KERNEL);
 
         /* DMA TX slave channel configuration */
-        atslave = &alt_atslave->txdata;
+        atslave = &alt_atslave.txdata;
         atslave->dma_dev = &at_hdmac_device.dev;
         atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE  | ATC_SRC_H2SEL_HW |
                                                 ATC_SRC_PER(AT_DMA_ID_AES_RX);
 
         /* DMA RX slave channel configuration */
-        atslave = &alt_atslave->rxdata;
+        atslave = &alt_atslave.rxdata;
         atslave->dma_dev = &at_hdmac_device.dev;
         atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE  | ATC_DST_H2SEL_HW |
                                                 ATC_DST_PER(AT_DMA_ID_AES_TX);
 
-        aes_data.dma_slave = alt_atslave;
+        aes_data.dma_slave = &alt_atslave;
         platform_device_register(&at91sam9g45_aes_device);
 }
 #else
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 5dfc8fd87103..13cdbcd48f51 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -172,6 +172,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
         CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
         CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
         CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
         CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
         CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
@@ -226,7 +228,7 @@ void __init at91sam9n12_initialize(void)
         at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0);
 }
 
-AT91_SOC_START(sam9n12)
+AT91_SOC_START(at91sam9n12)
         .map_io = at91sam9n12_map_io,
         .register_clocks = at91sam9n12_register_clocks,
         .init = at91sam9n12_initialize,
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index eb98704db2d9..f77fae5591bc 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -179,6 +179,7 @@ static struct clk *periph_clocks[] __initdata = {
 };
 
 static struct clk_lookup periph_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
@@ -340,7 +341,7 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
         0,      /* Advanced Interrupt Controller */
 };
 
-AT91_SOC_START(sam9rl)
+AT91_SOC_START(at91sam9rl)
         .map_io = at91sam9rl_map_io,
         .default_irq_priority = at91sam9rl_default_irq_priority,
         .ioremap_registers = at91sam9rl_ioremap_registers,
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index ddf223ff35c4..352468f265a9 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -514,7 +514,7 @@ static struct resource lcdc_resources[] = {
 };
 
 static struct platform_device at91_lcdc_device = {
-        .name           = "atmel_lcdfb",
+        .name           = "at91sam9rl-lcdfb",
         .id             = 0,
         .dev            = {
                                 .dma_mask               = &lcdc_dmamask,
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 44a9a62dcc13..e631fec040ce 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -237,6 +237,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
         CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
         CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
         CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
         CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
         CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
@@ -320,7 +322,7 @@ static void __init at91sam9x5_map_io(void)
  *  Interrupt initialization
  * -------------------------------------------------------------------- */
 
-AT91_SOC_START(sam9x5)
+AT91_SOC_START(at91sam9x5)
         .map_io = at91sam9x5_map_io,
         .register_clocks = at91sam9x5_register_clocks,
 AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index 0c07a4459cb2..2919eba41ff4 100644
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -33,7 +33,7 @@
         __raw_readl(AT91_IO_P2V(AT91_TC) + field)
 
 #define at91_tc_write(field, value) \
-        __raw_writel(value, AT91_IO_P2V(AT91_TC) + field);
+        __raw_writel(value, AT91_IO_P2V(AT91_TC) + field)
 
 /*
  *      3 counter/timer units present.
diff --git a/arch/arm/mach-at91/board-rm9200-dt.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 3fcb6623a33e..3fcb6623a33e 100644
--- a/arch/arm/mach-at91/board-rm9200-dt.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt-sam9.c
index 8db30132abed..8db30132abed 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
new file mode 100644
index 000000000000..705305e62bbc
--- /dev/null
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -0,0 +1,86 @@
+/*
+ *  Setup code for SAMA5 Evaluation Kits with Device Tree support
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/micrel_phy.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/phy.h>
+
+#include <asm/setup.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include "at91_aic.h"
+#include "generic.h"
+
+
+static const struct of_device_id irq_of_match[] __initconst = {
+
+        { .compatible = "atmel,sama5d3-aic", .data = at91_aic5_of_init },
+        { /*sentinel*/ }
+};
+
+static void __init at91_dt_init_irq(void)
+{
+        of_irq_init(irq_of_match);
+}
+
+static int ksz9021rn_phy_fixup(struct phy_device *phy)
+{
+        int value;
+
+#define GMII_RCCPSR     260
+#define GMII_RRDPSR     261
+#define GMII_ERCR       11
+#define GMII_ERDWR      12
+
+        /* Set delay values */
+        value = GMII_RCCPSR | 0x8000;
+        phy_write(phy, GMII_ERCR, value);
+        value = 0xF2F4;
+        phy_write(phy, GMII_ERDWR, value);
+        value = GMII_RRDPSR | 0x8000;
+        phy_write(phy, GMII_ERCR, value);
+        value = 0x2222;
+        phy_write(phy, GMII_ERDWR, value);
+
+        return 0;
+}
+
+static void __init sama5_dt_device_init(void)
+{
+        if (of_machine_is_compatible("atmel,sama5d3xcm"))
+                phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
+                        ksz9021rn_phy_fixup);
+
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char *sama5_dt_board_compat[] __initdata = {
+        "atmel,sama5",
+        NULL
+};
+
+DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
+        /* Maintainer: Atmel */
+        .init_time      = at91sam926x_pit_init,
+        .map_io         = at91_map_io,
+        .handle_irq     = at91_aic5_handle_irq,
+        .init_early     = at91_dt_initialize,
+        .init_irq       = at91_dt_init_irq,
+        .init_machine   = sama5_dt_device_init,
+        .dt_compat      = sama5_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 33361505c0cd..da841885d01c 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -54,7 +54,10 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
  */
 #define cpu_has_utmi()          (  cpu_is_at91sam9rl() \
                                 || cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5())
+                                || cpu_is_at91sam9x5() \
+                                || cpu_is_sama5d3())
+
+#define cpu_has_1056M_plla()    (cpu_is_sama5d3())
 
 #define cpu_has_800M_plla()     (  cpu_is_at91sam9g20() \
                                 || cpu_is_at91sam9g45() \
@@ -75,7 +78,8 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
                                 || cpu_is_at91sam9n12()))
 
 #define cpu_has_upll()          (cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5())
+                                || cpu_is_at91sam9x5() \
+                                || cpu_is_sama5d3())
 
 /* USB host HS & FS */
 #define cpu_has_uhp()           (!cpu_is_at91sam9rl())
@@ -83,18 +87,22 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
 /* USB device FS only */
 #define cpu_has_udpfs()         (!(cpu_is_at91sam9rl() \
                                 || cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5()))
+                                || cpu_is_at91sam9x5() \
+                                || cpu_is_sama5d3()))
 
 #define cpu_has_plladiv2()      (cpu_is_at91sam9g45() \
                                 || cpu_is_at91sam9x5() \
-                                || cpu_is_at91sam9n12())
+                                || cpu_is_at91sam9n12() \
+                                || cpu_is_sama5d3())
 
 #define cpu_has_mdiv3()         (cpu_is_at91sam9g45() \
                                 || cpu_is_at91sam9x5() \
-                                || cpu_is_at91sam9n12())
+                                || cpu_is_at91sam9n12() \
+                                || cpu_is_sama5d3())
 
 #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
-                                || cpu_is_at91sam9n12())
+                                || cpu_is_at91sam9n12() \
+                                || cpu_is_sama5d3())
 
 static LIST_HEAD(clocks);
 static DEFINE_SPINLOCK(clk_lock);
@@ -210,10 +218,26 @@ struct clk mck = {
 
 static void pmc_periph_mode(struct clk *clk, int is_on)
 {
-        if (is_on)
-                at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
-        else
-                at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
+        u32 regval = 0;
+
+        /*
+         * With sama5d3 devices, we are managing clock division so we have to
+         * use the Peripheral Control Register introduced from at91sam9x5
+         * devices.
+         */
+        if (cpu_is_sama5d3()) {
+                regval |= AT91_PMC_PCR_CMD; /* write command */
+                regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */
+                regval |= AT91_PMC_PCR_DIV(clk->div);
+                if (is_on)
+                        regval |= AT91_PMC_PCR_EN; /* enable clock */
+                at91_pmc_write(AT91_PMC_PCR, regval);
+        } else {
+                if (is_on)
+                        at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
+                else
+                        at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
+        }
 }
 
 static struct clk __init *at91_css_to_clk(unsigned long css)
@@ -443,14 +467,18 @@ static void __init init_programmable_clock(struct clk *clk)
 
 static int at91_clk_show(struct seq_file *s, void *unused)
 {
-        u32             scsr, pcsr, uckr = 0, sr;
+        u32             scsr, pcsr, pcsr1 = 0, uckr = 0, sr;
         struct clk      *clk;
 
         scsr = at91_pmc_read(AT91_PMC_SCSR);
         pcsr = at91_pmc_read(AT91_PMC_PCSR);
+        if (cpu_is_sama5d3())
+                pcsr1 = at91_pmc_read(AT91_PMC_PCSR1);
         sr = at91_pmc_read(AT91_PMC_SR);
         seq_printf(s, "SCSR = %8x\n", scsr);
         seq_printf(s, "PCSR = %8x\n", pcsr);
+        if (cpu_is_sama5d3())
+                seq_printf(s, "PCSR1 = %8x\n", pcsr1);
         seq_printf(s, "MOR  = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
         seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
         seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
@@ -470,20 +498,30 @@ static int at91_clk_show(struct seq_file *s, void *unused)
         list_for_each_entry(clk, &clocks, node) {
                 char    *state;
 
-                if (clk->mode == pmc_sys_mode)
+                if (clk->mode == pmc_sys_mode) {
                         state = (scsr & clk->pmc_mask) ? "on" : "off";
-                else if (clk->mode == pmc_periph_mode)
-                        state = (pcsr & clk->pmc_mask) ? "on" : "off";
-                else if (clk->mode == pmc_uckr_mode)
+                } else if (clk->mode == pmc_periph_mode) {
+                        if (cpu_is_sama5d3()) {
+                                u32 pmc_mask = 1 << (clk->pid % 32);
+
+                                if (clk->pid > 31)
+                                        state = (pcsr1 & pmc_mask) ? "on" : "off";
+                                else
+                                        state = (pcsr & pmc_mask) ? "on" : "off";
+                        } else {
+                                state = (pcsr & clk->pmc_mask) ? "on" : "off";
+                        }
+                } else if (clk->mode == pmc_uckr_mode) {
                         state = (uckr & clk->pmc_mask) ? "on" : "off";
-                else if (clk->pmc_mask)
+                } else if (clk->pmc_mask) {
                         state = (sr & clk->pmc_mask) ? "on" : "off";
-                else if (clk == &clk32k || clk == &main_clk)
+                } else if (clk == &clk32k || clk == &main_clk) {
                         state = "on";
-                else
+                } else {
                         state = "";
+                }
 
-                seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
+                seq_printf(s, "%-10s users=%2d %-3s %9lu Hz %s\n",
                         clk->name, clk->users, state, clk_get_rate(clk),
                         clk->parent ? clk->parent->name : "");
         }
@@ -530,6 +568,9 @@ int __init clk_register(struct clk *clk)
         if (clk_is_peripheral(clk)) {
                 if (!clk->parent)
                         clk->parent = &mck;
+                if (cpu_is_sama5d3())
+                        clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz,
+                                                    1 << clk->div);
                 clk->mode = pmc_periph_mode;
         }
         else if (clk_is_sys(clk)) {
@@ -555,7 +596,11 @@ static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
         unsigned mul, div;
 
         div = reg & 0xff;
-        mul = (reg >> 16) & 0x7ff;
+        if (cpu_is_sama5d3())
+                mul = AT91_PMC3_MUL_GET(reg);
+        else
+                mul = AT91_PMC_MUL_GET(reg);
+
         if (div && mul) {
                 freq /= div;
                 freq *= mul + 1;
@@ -706,12 +751,15 @@ static int __init at91_pmc_init(unsigned long main_clock)
 
         /* report if PLLA is more than mildly overclocked */
         plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
-        if (cpu_has_300M_plla()) {
-                if (plla.rate_hz > 300000000)
+        if (cpu_has_1056M_plla()) {
+                if (plla.rate_hz > 1056000000)
                         pll_overclock = true;
         } else if (cpu_has_800M_plla()) {
                 if (plla.rate_hz > 800000000)
                         pll_overclock = true;
+        } else if (cpu_has_300M_plla()) {
+                if (plla.rate_hz > 300000000)
+                        pll_overclock = true;
         } else if (cpu_has_240M_plla()) {
                 if (plla.rate_hz > 240000000)
                         pll_overclock = true;
@@ -872,6 +920,7 @@ int __init at91_clock_init(unsigned long main_clock)
 static int __init at91_clock_reset(void)
 {
         unsigned long pcdr = 0;
+        unsigned long pcdr1 = 0;
         unsigned long scdr = 0;
         struct clk *clk;
 
@@ -879,8 +928,17 @@ static int __init at91_clock_reset(void)
                 if (clk->users > 0)
                         continue;
 
-                if (clk->mode == pmc_periph_mode)
-                        pcdr |= clk->pmc_mask;
+                if (clk->mode == pmc_periph_mode) {
+                        if (cpu_is_sama5d3()) {
+                                u32 pmc_mask = 1 << (clk->pid % 32);
+
+                                if (clk->pid > 31)
+                                        pcdr1 |= pmc_mask;
+                                else
+                                        pcdr |= pmc_mask;
+                        } else
+                                pcdr |= clk->pmc_mask;
+                }
 
                 if (clk->mode == pmc_sys_mode)
                         scdr |= clk->pmc_mask;
@@ -888,8 +946,9 @@ static int __init at91_clock_reset(void)
                 pr_debug("Clocks: disable unused %s\n", clk->name);
         }
 
-        at91_pmc_write(AT91_PMC_PCDR, pcdr);
         at91_pmc_write(AT91_PMC_SCDR, scdr);
+        if (cpu_is_sama5d3())
+                at91_pmc_write(AT91_PMC_PCDR1, pcdr1);
 
         return 0;
 }
diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h
index c2e63e47dcbe..a98a39bbd883 100644
--- a/arch/arm/mach-at91/clock.h
+++ b/arch/arm/mach-at91/clock.h
@@ -20,7 +20,9 @@ struct clk {
         const char      *name;          /* unique clock name */
         struct clk_lookup cl;
         unsigned long   rate_hz;
+        unsigned        div;            /* parent clock divider */
         struct clk      *parent;
+        unsigned        pid;            /* peripheral ID */
         u32             pmc_mask;
         void            (*mode)(struct clk *, int);
         unsigned        id:3;           /* PCK0..4, or 32k/main/a/b */
diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c
index 0c6381516a5a..48f1228c611c 100644
--- a/arch/arm/mach-at91/cpuidle.c
+++ b/arch/arm/mach-at91/cpuidle.c
@@ -27,8 +27,6 @@
 
 #define AT91_MAX_STATES 2
 
-static DEFINE_PER_CPU(struct cpuidle_device, at91_cpuidle_device);
-
 /* Actual code that puts the SoC in different idle states */
 static int at91_enter_idle(struct cpuidle_device *dev,
                         struct cpuidle_driver *drv,
@@ -47,7 +45,6 @@ static int at91_enter_idle(struct cpuidle_device *dev,
 static struct cpuidle_driver at91_idle_driver = {
         .name                   = "at91_idle",
         .owner                  = THIS_MODULE,
-        .en_core_tk_irqen       = 1,
         .states[0]              = ARM_CPUIDLE_WFI_STATE,
         .states[1]              = {
                 .enter                  = at91_enter_idle,
@@ -61,20 +58,9 @@ static struct cpuidle_driver at91_idle_driver = {
 };
 
 /* Initialize CPU idle by registering the idle states */
-static int at91_init_cpuidle(void)
+static int __init at91_init_cpuidle(void)
 {
-        struct cpuidle_device *device;
-
-        device = &per_cpu(at91_cpuidle_device, smp_processor_id());
-        device->state_count = AT91_MAX_STATES;
-
-        cpuidle_register_driver(&at91_idle_driver);
-
-        if (cpuidle_register_device(device)) {
-                printk(KERN_ERR "at91_init_cpuidle: Failed registering\n");
-                return -EIO;
-        }
-        return 0;
+        return cpuidle_register(&at91_idle_driver, NULL);
 }
 
 device_initcall(at91_init_cpuidle);
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index c5d7e1e9d757..a5afcf76550e 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -22,10 +22,9 @@
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/of_address.h>
 
-#include <asm/mach/irq.h>
-
 #include <mach/hardware.h>
 #include <mach/at91_pio.h>
 
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h
index 2aa0c5e13495..3b5948566e52 100644
--- a/arch/arm/mach-at91/include/mach/at91_dbgu.h
+++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h
@@ -16,9 +16,6 @@
 #ifndef AT91_DBGU_H
 #define AT91_DBGU_H
 
-#define dbgu_readl(dbgu, field) \
-        __raw_readl(AT91_VA_BASE_SYS + dbgu + AT91_DBGU_ ## field)
-
 #if !defined(CONFIG_ARCH_AT91X40)
 #define AT91_DBGU_CR            (0x00)  /* Control Register */
 #define AT91_DBGU_MR            (0x04)  /* Mode Register */
diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach/at91_matrix.h
index 02fae9de746b..f8996c954131 100644
--- a/arch/arm/mach-at91/include/mach/at91_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91_matrix.h
@@ -14,7 +14,7 @@ extern void __iomem *at91_matrix_base;
         __raw_readl(at91_matrix_base + field)
 
 #define at91_matrix_write(field, value) \
-        __raw_writel(value, at91_matrix_base + field);
+        __raw_writel(value, at91_matrix_base + field)
 
 #else
 .extern at91_matrix_base
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index ea2c57a86ca6..31df12029c4e 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -75,6 +75,9 @@ extern void __iomem *at91_pmc_base;
 #define         AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
 #define         AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
 #define         AT91_PMC_MUL            (0x7ff << 16)           /* PLL Multiplier */
+#define         AT91_PMC_MUL_GET(n)     ((n) >> 16 & 0x7ff)
+#define         AT91_PMC3_MUL           (0x7f  << 18)           /* PLL Multiplier [SAMA5 only] */
+#define         AT91_PMC3_MUL_GET(n)    ((n) >> 18 & 0x7f)
 #define         AT91_PMC_USBDIV         (3     << 28)           /* USB Divisor (PLLB only) */
 #define                 AT91_PMC_USBDIV_1               (0 << 28)
 #define                 AT91_PMC_USBDIV_2               (1 << 28)
@@ -167,11 +170,18 @@ extern void __iomem *at91_pmc_base;
 #define         AT91_PMC_WPVS           (0x1  <<  0)            /* Write Protect Violation Status */
 #define         AT91_PMC_WPVSRC         (0xffff  <<  8)         /* Write Protect Violation Source */
 
-#define AT91_PMC_PCR            0x10c                   /* Peripheral Control Register [some SAM9] */
+#define AT91_PMC_PCER1          0x100                   /* Peripheral Clock Enable Register 1 [SAMA5 only]*/
+#define AT91_PMC_PCDR1          0x104                   /* Peripheral Clock Enable Register 1 */
+#define AT91_PMC_PCSR1          0x108                   /* Peripheral Clock Enable Register 1 */
+
+#define AT91_PMC_PCR            0x10c                   /* Peripheral Control Register [some SAM9 and SAMA5] */
 #define         AT91_PMC_PCR_PID        (0x3f  <<  0)           /* Peripheral ID */
-#define         AT91_PMC_PCR_CMD        (0x1  <<  12)           /* Command */
-#define         AT91_PMC_PCR_DIV        (0x3  <<  16)           /* Divisor Value */
-#define         AT91_PMC_PCRDIV(n)      (((n) <<  16) & AT91_PMC_PCR_DIV)
+#define         AT91_PMC_PCR_CMD        (0x1  <<  12)           /* Command (read=0, write=1) */
+#define         AT91_PMC_PCR_DIV(n)     ((n)  <<  16)           /* Divisor Value */
+#define                 AT91_PMC_PCR_DIV0       0x0                     /* Peripheral clock is MCK */
+#define                 AT91_PMC_PCR_DIV2       0x2                     /* Peripheral clock is MCK/2 */
+#define                 AT91_PMC_PCR_DIV4       0x4                     /* Peripheral clock is MCK/4 */
+#define                 AT91_PMC_PCR_DIV8       0x8                     /* Peripheral clock is MCK/8 */
 #define         AT91_PMC_PCR_EN         (0x1  <<  28)           /* Enable */
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach/at91_st.h
index 969aac27109f..67fdbd13c3ed 100644
--- a/arch/arm/mach-at91/include/mach/at91_st.h
+++ b/arch/arm/mach-at91/include/mach/at91_st.h
@@ -23,7 +23,7 @@ extern void __iomem *at91_st_base;
         __raw_readl(at91_st_base + field)
 
 #define at91_st_write(field, value) \
-        __raw_writel(value, at91_st_base + field);
+        __raw_writel(value, at91_st_base + field)
 #else
 .extern at91_st_base
 #endif
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index b6504c19d55c..0f3379fe645f 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -36,6 +36,8 @@
 #define ARCH_ID_AT91M40807      0x14080745
 #define ARCH_ID_AT91R40008      0x44000840
 
+#define ARCH_ID_SAMA5D3         0x8A5C07C0
+
 #define ARCH_EXID_AT91SAM9M11   0x00000001
 #define ARCH_EXID_AT91SAM9M10   0x00000002
 #define ARCH_EXID_AT91SAM9G46   0x00000003
@@ -47,6 +49,11 @@
 #define ARCH_EXID_AT91SAM9G25   0x00000003
 #define ARCH_EXID_AT91SAM9X25   0x00000004
 
+#define ARCH_EXID_SAMA5D31      0x00444300
+#define ARCH_EXID_SAMA5D33      0x00414300
+#define ARCH_EXID_SAMA5D34      0x00414301
+#define ARCH_EXID_SAMA5D35      0x00584300
+
 #define ARCH_FAMILY_AT91X92     0x09200000
 #define ARCH_FAMILY_AT91SAM9    0x01900000
 #define ARCH_FAMILY_AT91SAM9XE  0x02900000
@@ -75,6 +82,9 @@ enum at91_soc_type {
         /* SAM9N12 */
         AT91_SOC_SAM9N12,
 
+        /* SAMA5D3 */
+        AT91_SOC_SAMA5D3,
+
         /* Unknown type */
         AT91_SOC_NONE
 };
@@ -93,6 +103,10 @@ enum at91_soc_subtype {
         AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35,
         AT91_SOC_SAM9G25, AT91_SOC_SAM9X25,
 
+        /* SAMA5D3 */
+        AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
+        AT91_SOC_SAMA5D35,
+
         /* Unknown subtype */
         AT91_SOC_SUBTYPE_NONE
 };
@@ -187,6 +201,12 @@ static inline int at91_soc_is_detected(void)
 #define cpu_is_at91sam9n12()    (0)
 #endif
 
+#ifdef CONFIG_SOC_SAMA5D3
+#define cpu_is_sama5d3()        (at91_soc_initdata.type == AT91_SOC_SAMA5D3)
+#else
+#define cpu_is_sama5d3()        (0)
+#endif
+
 /*
  * Since this is ARM, we will never run on any AVR32 CPU. But these
  * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
new file mode 100644
index 000000000000..6dc81ee38048
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -0,0 +1,73 @@
+/*
+ * Chip-specific header file for the SAMA5D3 family
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Common definitions.
+ * Based on SAMA5D3 datasheet.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef SAMA5D3_H
+#define SAMA5D3_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ              0      /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS              1      /* System Peripherals */
+#define SAMA5D3_ID_DBGU          2      /* debug Unit (usually no special interrupt line) */
+#define AT91_ID_PIT              3      /* PIT */
+#define SAMA5D3_ID_WDT           4      /* Watchdog Timer Interrupt */
+#define SAMA5D3_ID_HSMC          5      /* Static Memory Controller */
+#define SAMA5D3_ID_PIOA          6      /* PIOA */
+#define SAMA5D3_ID_PIOB          7      /* PIOB */
+#define SAMA5D3_ID_PIOC          8      /* PIOC */
+#define SAMA5D3_ID_PIOD          9      /* PIOD */
+#define SAMA5D3_ID_PIOE         10      /* PIOE */
+#define SAMA5D3_ID_SMD          11      /* SMD Soft Modem */
+#define SAMA5D3_ID_USART0       12      /* USART0 */
+#define SAMA5D3_ID_USART1       13      /* USART1 */
+#define SAMA5D3_ID_USART2       14      /* USART2 */
+#define SAMA5D3_ID_USART3       15      /* USART3 */
+#define SAMA5D3_ID_UART0        16      /* UART 0 */
+#define SAMA5D3_ID_UART1        17      /* UART 1 */
+#define SAMA5D3_ID_TWI0         18      /* Two-Wire Interface 0 */
+#define SAMA5D3_ID_TWI1         19      /* Two-Wire Interface 1 */
+#define SAMA5D3_ID_TWI2         20      /* Two-Wire Interface 2 */
+#define SAMA5D3_ID_HSMCI0       21      /* MCI */
+#define SAMA5D3_ID_HSMCI1       22      /* MCI */
+#define SAMA5D3_ID_HSMCI2       23      /* MCI */
+#define SAMA5D3_ID_SPI0         24      /* Serial Peripheral Interface 0 */
+#define SAMA5D3_ID_SPI1         25      /* Serial Peripheral Interface 1 */
+#define SAMA5D3_ID_TC0          26      /* Timer Counter 0 */
+#define SAMA5D3_ID_TC1          27      /* Timer Counter 2 */
+#define SAMA5D3_ID_PWM          28      /* Pulse Width Modulation Controller */
+#define SAMA5D3_ID_ADC          29      /* Touch Screen ADC Controller */
+#define SAMA5D3_ID_DMA0         30      /* DMA Controller 0 */
+#define SAMA5D3_ID_DMA1         31      /* DMA Controller 1 */
+#define SAMA5D3_ID_UHPHS        32      /* USB Host High Speed */
+#define SAMA5D3_ID_UDPHS        33      /* USB Device High Speed */
+#define SAMA5D3_ID_GMAC         34      /* Gigabit Ethernet MAC */
+#define SAMA5D3_ID_EMAC         35      /* Ethernet MAC */
+#define SAMA5D3_ID_LCDC         36      /* LCD Controller */
+#define SAMA5D3_ID_ISI          37      /* Image Sensor Interface */
+#define SAMA5D3_ID_SSC0         38      /* Synchronous Serial Controller 0 */
+#define SAMA5D3_ID_SSC1         39      /* Synchronous Serial Controller 1 */
+#define SAMA5D3_ID_CAN0         40      /* CAN Controller 0 */
+#define SAMA5D3_ID_CAN1         41      /* CAN Controller 1 */
+#define SAMA5D3_ID_SHA          42      /* Secure Hash Algorithm */
+#define SAMA5D3_ID_AES          43      /* Advanced Encryption Standard */
+#define SAMA5D3_ID_TDES         44      /* Triple Data Encryption Standard */
+#define SAMA5D3_ID_TRNG         45      /* True Random Generator Number */
+#define SAMA5D3_ID_IRQ0         47      /* Advanced Interrupt Controller (IRQ0) */
+
+/*
+ * Internal Memory
+ */
+#define SAMA5D3_SRAM_BASE       0x00300000      /* Internal SRAM base address */
+#define SAMA5D3_SRAM_SIZE       (128 * SZ_1K)   /* Internal SRAM size (128Kb) */
+
+#endif
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
new file mode 100644
index 000000000000..401279715ab1
--- /dev/null
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -0,0 +1,377 @@
+/*
+ *  Chip-specific setup code for the SAMA5D3 family
+ *
+ *  Copyright (C) 2013 Atmel,
+ *                2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/sama5d3.h>
+#include <mach/at91_pmc.h>
+#include <mach/cpu.h>
+
+#include "soc.h"
+#include "generic.h"
+#include "clock.h"
+#include "sam9_smc.h"
+
+/* --------------------------------------------------------------------
+ *  Clocks
+ * -------------------------------------------------------------------- */
+
+/*
+ * The peripheral clocks.
+ */
+
+static struct clk pioA_clk = {
+        .name           = "pioA_clk",
+        .pid            = SAMA5D3_ID_PIOA,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioB_clk = {
+        .name           = "pioB_clk",
+        .pid            = SAMA5D3_ID_PIOB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioC_clk = {
+        .name           = "pioC_clk",
+        .pid            = SAMA5D3_ID_PIOC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioD_clk = {
+        .name           = "pioD_clk",
+        .pid            = SAMA5D3_ID_PIOD,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioE_clk = {
+        .name           = "pioE_clk",
+        .pid            = SAMA5D3_ID_PIOE,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart0_clk = {
+        .name           = "usart0_clk",
+        .pid            = SAMA5D3_ID_USART0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk usart1_clk = {
+        .name           = "usart1_clk",
+        .pid            = SAMA5D3_ID_USART1,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk usart2_clk = {
+        .name           = "usart2_clk",
+        .pid            = SAMA5D3_ID_USART2,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk usart3_clk = {
+        .name           = "usart3_clk",
+        .pid            = SAMA5D3_ID_USART3,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk uart0_clk = {
+        .name           = "uart0_clk",
+        .pid            = SAMA5D3_ID_UART0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk uart1_clk = {
+        .name           = "uart1_clk",
+        .pid            = SAMA5D3_ID_UART1,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk twi0_clk = {
+        .name           = "twi0_clk",
+        .pid            = SAMA5D3_ID_TWI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk twi1_clk = {
+        .name           = "twi1_clk",
+        .pid            = SAMA5D3_ID_TWI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk twi2_clk = {
+        .name           = "twi2_clk",
+        .pid            = SAMA5D3_ID_TWI2,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk mmc0_clk = {
+        .name           = "mci0_clk",
+        .pid            = SAMA5D3_ID_HSMCI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc1_clk = {
+        .name           = "mci1_clk",
+        .pid            = SAMA5D3_ID_HSMCI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc2_clk = {
+        .name           = "mci2_clk",
+        .pid            = SAMA5D3_ID_HSMCI2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi0_clk = {
+        .name           = "spi0_clk",
+        .pid            = SAMA5D3_ID_SPI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi1_clk = {
+        .name           = "spi1_clk",
+        .pid            = SAMA5D3_ID_SPI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tcb0_clk = {
+        .name           = "tcb0_clk",
+        .pid            = SAMA5D3_ID_TC0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk tcb1_clk = {
+        .name           = "tcb1_clk",
+        .pid            = SAMA5D3_ID_TC1,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk adc_clk = {
+        .name           = "adc_clk",
+        .pid            = SAMA5D3_ID_ADC,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk adc_op_clk = {
+        .name           = "adc_op_clk",
+        .type           = CLK_TYPE_PERIPHERAL,
+        .rate_hz        = 5000000,
+};
+static struct clk dma0_clk = {
+        .name           = "dma0_clk",
+        .pid            = SAMA5D3_ID_DMA0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk dma1_clk = {
+        .name           = "dma1_clk",
+        .pid            = SAMA5D3_ID_DMA1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uhphs_clk = {
+        .name           = "uhphs",
+        .pid            = SAMA5D3_ID_UHPHS,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk udphs_clk = {
+        .name           = "udphs_clk",
+        .pid            = SAMA5D3_ID_UDPHS,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* gmac only for sama5d33, sama5d34, sama5d35 */
+static struct clk macb0_clk = {
+        .name           = "macb0_clk",
+        .pid            = SAMA5D3_ID_GMAC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* emac only for sama5d31, sama5d35 */
+static struct clk macb1_clk = {
+        .name           = "macb1_clk",
+        .pid            = SAMA5D3_ID_EMAC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* lcd only for sama5d31, sama5d33, sama5d34 */
+static struct clk lcdc_clk = {
+        .name           = "lcdc_clk",
+        .pid            = SAMA5D3_ID_LCDC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* isi only for sama5d33, sama5d35 */
+static struct clk isi_clk = {
+        .name           = "isi_clk",
+        .pid            = SAMA5D3_ID_ISI,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk can0_clk = {
+        .name           = "can0_clk",
+        .pid            = SAMA5D3_ID_CAN0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk can1_clk = {
+        .name           = "can1_clk",
+        .pid            = SAMA5D3_ID_CAN1,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk ssc0_clk = {
+        .name           = "ssc0_clk",
+        .pid            = SAMA5D3_ID_SSC0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk ssc1_clk = {
+        .name           = "ssc1_clk",
+        .pid            = SAMA5D3_ID_SSC1,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV2,
+};
+static struct clk sha_clk = {
+        .name           = "sha_clk",
+        .pid            = SAMA5D3_ID_SHA,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .div            = AT91_PMC_PCR_DIV8,
+};
+static struct clk aes_clk = {
+        .name           = "aes_clk",
+        .pid            = SAMA5D3_ID_AES,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tdes_clk = {
+        .name           = "tdes_clk",
+        .pid            = SAMA5D3_ID_TDES,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+
+static struct clk *periph_clocks[] __initdata = {
+        &pioA_clk,
+        &pioB_clk,
+        &pioC_clk,
+        &pioD_clk,
+        &pioE_clk,
+        &usart0_clk,
+        &usart1_clk,
+        &usart2_clk,
+        &usart3_clk,
+        &uart0_clk,
+        &uart1_clk,
+        &twi0_clk,
+        &twi1_clk,
+        &twi2_clk,
+        &mmc0_clk,
+        &mmc1_clk,
+        &mmc2_clk,
+        &spi0_clk,
+        &spi1_clk,
+        &tcb0_clk,
+        &tcb1_clk,
+        &adc_clk,
+        &adc_op_clk,
+        &dma0_clk,
+        &dma1_clk,
+        &uhphs_clk,
+        &udphs_clk,
+        &macb0_clk,
+        &macb1_clk,
+        &lcdc_clk,
+        &isi_clk,
+        &can0_clk,
+        &can1_clk,
+        &ssc0_clk,
+        &ssc1_clk,
+        &sha_clk,
+        &aes_clk,
+        &tdes_clk,
+};
+
+static struct clk pck0 = {
+        .name           = "pck0",
+        .pmc_mask       = AT91_PMC_PCK0,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 0,
+};
+
+static struct clk pck1 = {
+        .name           = "pck1",
+        .pmc_mask       = AT91_PMC_PCK1,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 1,
+};
+
+static struct clk pck2 = {
+        .name           = "pck2",
+        .pmc_mask       = AT91_PMC_PCK2,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 2,
+};
+
+static struct clk_lookup periph_clocks_lookups[] = {
+        /* lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
+        CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk),
+        CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk),
+        CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk),
+        CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk),
+        CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk),
+        CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk),
+        CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk),
+        CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk),
+        CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk),
+        CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
+        CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
+        CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk),
+        CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk),
+        CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk),
+        CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk),
+        CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk),
+        CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk),
+        CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk),
+        CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk),
+};
+
+static void __init sama5d3_register_clocks(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
+                clk_register(periph_clocks[i]);
+
+        clkdev_add_table(periph_clocks_lookups,
+                         ARRAY_SIZE(periph_clocks_lookups));
+
+        clk_register(&pck0);
+        clk_register(&pck1);
+        clk_register(&pck2);
+}
+
+/* --------------------------------------------------------------------
+ *  AT91SAM9x5 processor initialization
+ * -------------------------------------------------------------------- */
+
+static void __init sama5d3_map_io(void)
+{
+        at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE);
+}
+
+AT91_SOC_START(sama5d3)
+        .map_io = sama5d3_map_io,
+        .register_clocks = sama5d3_register_clocks,
+AT91_SOC_END
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 4b678478cf95..e8491e77b1f7 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -151,6 +151,11 @@ static void __init soc_detect(u32 dbgu_base)
                 at91_soc_initdata.type = AT91_SOC_SAM9N12;
                 at91_boot_soc = at91sam9n12_soc;
                 break;
+
+        case ARCH_ID_SAMA5D3:
+                at91_soc_initdata.type = AT91_SOC_SAMA5D3;
+                at91_boot_soc = sama5d3_soc;
+                break;
         }
 
         /* at91sam9g10 */
@@ -206,6 +211,23 @@ static void __init soc_detect(u32 dbgu_base)
                         break;
                 }
         }
+
+        if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
+                switch (at91_soc_initdata.exid) {
+                case ARCH_EXID_SAMA5D31:
+                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
+                        break;
+                case ARCH_EXID_SAMA5D33:
+                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
+                        break;
+                case ARCH_EXID_SAMA5D34:
+                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
+                        break;
+                case ARCH_EXID_SAMA5D35:
+                        at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
+                        break;
+                }
+        }
 }
 
 static const char *soc_name[] = {
@@ -219,6 +241,7 @@ static const char *soc_name[] = {
         [AT91_SOC_SAM9RL]       = "at91sam9rl",
         [AT91_SOC_SAM9X5]       = "at91sam9x5",
         [AT91_SOC_SAM9N12]      = "at91sam9n12",
+        [AT91_SOC_SAMA5D3]      = "sama5d3",
         [AT91_SOC_NONE]         = "Unknown"
 };
 
@@ -241,6 +264,10 @@ static const char *soc_subtype_name[] = {
         [AT91_SOC_SAM9X35]      = "at91sam9x35",
         [AT91_SOC_SAM9G25]      = "at91sam9g25",
         [AT91_SOC_SAM9X25]      = "at91sam9x25",
+        [AT91_SOC_SAMA5D31]     = "sama5d31",
+        [AT91_SOC_SAMA5D33]     = "sama5d33",
+        [AT91_SOC_SAMA5D34]     = "sama5d34",
+        [AT91_SOC_SAMA5D35]     = "sama5d35",
         [AT91_SOC_SUBTYPE_NONE] = "Unknown"
 };
 
@@ -333,7 +360,7 @@ static void at91_dt_rstc(void)
 
         of_id = of_match_node(rstc_ids, np);
         if (!of_id)
-                panic("AT91: rtsc no restart function availlable\n");
+                panic("AT91: rtsc no restart function available\n");
 
         arm_pm_restart = of_id->data;
 
@@ -353,7 +380,7 @@ static void at91_dt_ramc(void)
 
         np = of_find_matching_node(NULL, ramc_ids);
         if (!np)
-                panic("unable to find compatible ram conroller node in dtb\n");
+                panic("unable to find compatible ram controller node in dtb\n");
 
         at91_ramc_base[0] = of_iomap(np, 0);
         if (!at91_ramc_base[0])
@@ -403,7 +430,7 @@ static void at91_dt_shdwc(void)
 
         np = of_find_matching_node(NULL, shdwc_ids);
         if (!np) {
-                pr_debug("AT91: unable to find compatible shutdown (shdwc) conroller node in dtb\n");
+                pr_debug("AT91: unable to find compatible shutdown (shdwc) controller node in dtb\n");
                 return;
         }
 
@@ -419,7 +446,7 @@ static void at91_dt_shdwc(void)
 
         if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) {
                 if (reg > AT91_SHDW_CPTWK0_MAX) {
-                        pr_warn("AT91: shdwc wakeup conter 0x%x > 0x%x reduce it to 0x%x\n",
+                        pr_warn("AT91: shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n",
                                 reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
                         reg = AT91_SHDW_CPTWK0_MAX;
                 }
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index 9c6d3d4f9a23..43a225f9e713 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -22,9 +22,10 @@ extern struct at91_init_soc at91sam9g45_soc;
 extern struct at91_init_soc at91sam9rl_soc;
 extern struct at91_init_soc at91sam9x5_soc;
 extern struct at91_init_soc at91sam9n12_soc;
+extern struct at91_init_soc sama5d3_soc;
 
 #define AT91_SOC_START(_name)                           \
-struct at91_init_soc __initdata at91##_name##_soc       \
+struct at91_init_soc __initdata _name##_soc             \
  __used                                                 \
                                                 = {     \
         .builtin        = 1,                            \
@@ -68,3 +69,7 @@ static inline int at91_soc_is_enabled(void)
 #if !defined(CONFIG_SOC_AT91SAM9N12)
 #define at91sam9n12_soc at91_boot_soc
 #endif
+
+#if !defined(CONFIG_SOC_SAMA5D3)
+#define sama5d3_soc     at91_boot_soc
+#endif
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index bf02471d7e7c..f11289519c39 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -6,6 +6,7 @@ config ARCH_BCM
         select ARM_ERRATA_764369 if SMP
         select ARM_GIC
         select CPU_V7
+        select CLKSRC_OF
         select GENERIC_CLOCKEVENTS
         select GENERIC_TIME
         select GPIO_BCM
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index bbf412261e5e..6adb6aecf48f 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -10,4 +10,6 @@
 # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 
-obj-$(CONFIG_ARCH_BCM) := board_bcm.o
+obj-$(CONFIG_ARCH_BCM)          := board_bcm.o bcm_kona_smc.o bcm_kona_smc_asm.o
+plus_sec := $(call as-instr,.arch_extension sec,+sec)
+AFLAGS_bcm_kona_smc_asm.o       :=-Wa,-march=armv7-a$(plus_sec)
diff --git a/arch/arm/mach-bcm/bcm_kona_smc.c b/arch/arm/mach-bcm/bcm_kona_smc.c
new file mode 100644
index 000000000000..56d9d19b2470
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm_kona_smc.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdarg.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+
+#include <asm/cacheflush.h>
+#include <linux/of_address.h>
+
+#include "bcm_kona_smc.h"
+
+struct secure_bridge_data {
+        void __iomem *bounce;           /* virtual address */
+        u32 __iomem buffer_addr;        /* physical address */
+        int initialized;
+} bridge_data;
+
+struct bcm_kona_smc_data {
+        unsigned service_id;
+        unsigned arg0;
+        unsigned arg1;
+        unsigned arg2;
+        unsigned arg3;
+};
+
+static const struct of_device_id bcm_kona_smc_ids[] __initconst = {
+        {.compatible = "bcm,kona-smc"},
+        {},
+};
+
+/* Map in the bounce area */
+void __init bcm_kona_smc_init(void)
+{
+        struct device_node *node;
+
+        /* Read buffer addr and size from the device tree node */
+        node = of_find_matching_node(NULL, bcm_kona_smc_ids);
+        BUG_ON(!node);
+
+        /* Don't care about size or flags of the DT node */
+        bridge_data.buffer_addr =
+                be32_to_cpu(*of_get_address(node, 0, NULL, NULL));
+        BUG_ON(!bridge_data.buffer_addr);
+
+        bridge_data.bounce = of_iomap(node, 0);
+        BUG_ON(!bridge_data.bounce);
+
+        bridge_data.initialized = 1;
+
+        pr_info("Secure API initialized!\n");
+}
+
+/* __bcm_kona_smc() should only run on CPU 0, with pre-emption disabled */
+static void __bcm_kona_smc(void *info)
+{
+        struct bcm_kona_smc_data *data = info;
+        u32 *args = bridge_data.bounce;
+        int rc = 0;
+
+        /* Must run on CPU 0 */
+        BUG_ON(smp_processor_id() != 0);
+
+        /* Check map in the bounce area */
+        BUG_ON(!bridge_data.initialized);
+
+        /* Copy one 32 bit word into the bounce area */
+        args[0] = data->arg0;
+        args[1] = data->arg1;
+        args[2] = data->arg2;
+        args[3] = data->arg3;
+
+        /* Flush caches for input data passed to Secure Monitor */
+        if (data->service_id != SSAPI_BRCM_START_VC_CORE)
+                flush_cache_all();
+
+        /* Trap into Secure Monitor */
+        rc = bcm_kona_smc_asm(data->service_id, bridge_data.buffer_addr);
+
+        if (rc != SEC_ROM_RET_OK)
+                pr_err("Secure Monitor call failed (0x%x)!\n", rc);
+}
+
+unsigned bcm_kona_smc(unsigned service_id, unsigned arg0, unsigned arg1,
+                  unsigned arg2, unsigned arg3)
+{
+        struct bcm_kona_smc_data data;
+
+        data.service_id = service_id;
+        data.arg0 = arg0;
+        data.arg1 = arg1;
+        data.arg2 = arg2;
+        data.arg3 = arg3;
+
+        /*
+         * Due to a limitation of the secure monitor, we must use the SMP
+         * infrastructure to forward all secure monitor calls to Core 0.
+         */
+        if (get_cpu() != 0)
+                smp_call_function_single(0, __bcm_kona_smc, (void *)&data, 1);
+        else
+                __bcm_kona_smc(&data);
+
+        put_cpu();
+
+        return 0;
+}
diff --git a/arch/arm/mach-bcm/bcm_kona_smc.h b/arch/arm/mach-bcm/bcm_kona_smc.h
new file mode 100644
index 000000000000..3bedbed1c21b
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm_kona_smc.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef BCM_KONA_SMC_H
+#define BCM_KONA_SMC_H
+
+#include <linux/types.h>
+#define FLAGS   (SEC_ROM_ICACHE_ENABLE_MASK | SEC_ROM_DCACHE_ENABLE_MASK | \
+                        SEC_ROM_IRQ_ENABLE_MASK | SEC_ROM_FIQ_ENABLE_MASK)
+
+/*!
+ * Definitions for IRQ & FIQ Mask for ARM
+ */
+
+#define FIQ_IRQ_MASK                                            0xC0
+#define FIQ_MASK                                                0x40
+#define IRQ_MASK                                                0x80
+
+/*!
+ * Secure Mode FLAGs
+ */
+
+/* When set, enables ICache within the secure mode */
+#define SEC_ROM_ICACHE_ENABLE_MASK                        0x00000001
+
+/* When set, enables DCache within the secure mode */
+#define SEC_ROM_DCACHE_ENABLE_MASK                        0x00000002
+
+/* When set, enables IRQ within the secure mode */
+#define SEC_ROM_IRQ_ENABLE_MASK                           0x00000004
+
+/* When set, enables FIQ within the secure mode */
+#define SEC_ROM_FIQ_ENABLE_MASK                           0x00000008
+
+/* When set, enables Unified L2 cache within the secure mode */
+#define SEC_ROM_UL2_CACHE_ENABLE_MASK                     0x00000010
+
+/* Broadcom Secure Service API Service IDs */
+#define SSAPI_DORMANT_ENTRY_SERV                          0x01000000
+#define SSAPI_PUBLIC_OTP_SERV                             0x01000001
+#define SSAPI_ENABLE_L2_CACHE                             0x01000002
+#define SSAPI_DISABLE_L2_CACHE                            0x01000003
+#define SSAPI_WRITE_SCU_STATUS                            0x01000004
+#define SSAPI_WRITE_PWR_GATE                              0x01000005
+
+/* Broadcom Secure Service API Return Codes */
+#define SEC_ROM_RET_OK                  0x00000001
+#define SEC_ROM_RET_FAIL                0x00000009
+
+#define SSAPI_RET_FROM_INT_SERV         0x4
+#define SEC_EXIT_NORMAL                 0x1
+
+#define SSAPI_ROW_AES                   0x0E000006
+#define SSAPI_BRCM_START_VC_CORE        0x0E000008
+
+#ifndef __ASSEMBLY__
+extern void bcm_kona_smc_init(void);
+
+extern unsigned bcm_kona_smc(unsigned service_id,
+                             unsigned arg0,
+                             unsigned arg1,
+                             unsigned arg2,
+                             unsigned arg3);
+
+extern int bcm_kona_smc_asm(u32 service_id,
+                            u32 buffer_addr);
+
+#endif  /* __ASSEMBLY__ */
+
+#endif /* BCM_KONA_SMC_H */
diff --git a/arch/arm/mach-bcm/bcm_kona_smc_asm.S b/arch/arm/mach-bcm/bcm_kona_smc_asm.S
new file mode 100644
index 000000000000..a1608480d60d
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm_kona_smc_asm.S
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/linkage.h>
+#include "bcm_kona_smc.h"
+
+/*
+ * int bcm_kona_smc_asm(u32 service_id, u32 buffer_addr)
+ */
+
+ENTRY(bcm_kona_smc_asm)
+        stmfd   sp!, {r4-r12, lr}
+        mov     r4, r0          @ service_id
+        mov     r5, #3          @ Keep IRQ and FIQ off in SM
+        /*
+         * Since interrupts are disabled in the open mode, we must keep
+         * interrupts disabled in secure mode by setting R5=0x3. If interrupts
+         * are enabled in open mode, we can set R5=0x0 to allow interrupts in
+         * secure mode.  If we did this, the secure monitor would return back
+         * control to the open mode to handle the interrupt prior to completing
+         * the secure service. If this happened, R12 would not be
+         * SEC_EXIT_NORMAL and we would need to call SMC again after resetting
+         * R5 (it gets clobbered by the secure monitor) and setting R4 to
+         * SSAPI_RET_FROM_INT_SERV to indicate that we want the secure monitor
+         * to finish up the previous uncompleted secure service.
+         */
+        mov     r6, r1          @ buffer_addr
+        smc     #0
+        /* Check r12 for SEC_EXIT_NORMAL here if interrupts are enabled */
+        ldmfd   sp!, {r4-r12, pc}
+ENDPROC(bcm_kona_smc_asm)
diff --git a/arch/arm/mach-bcm/board_bcm.c b/arch/arm/mach-bcm/board_bcm.c
index f0f9abafad29..22e8421b1df3 100644
--- a/arch/arm/mach-bcm/board_bcm.c
+++ b/arch/arm/mach-bcm/board_bcm.c
@@ -16,26 +16,46 @@
 #include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/irqchip.h>
+#include <linux/clocksource.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include <asm/hardware/cache-l2x0.h>
 
-static void timer_init(void)
+
+#include "bcm_kona_smc.h"
+
+static int __init kona_l2_cache_init(void)
 {
-}
+        if (!IS_ENABLED(CONFIG_CACHE_L2X0))
+                return 0;
+
+        bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0);
 
+        /*
+         * The aux_val and aux_mask have no effect since L2 cache is already
+         * enabled.  Pass 0s for aux_val and 1s for aux_mask for default value.
+         */
+        l2x0_of_init(0, ~0);
+
+        return 0;
+}
 
 static void __init board_init(void)
 {
         of_platform_populate(NULL, of_default_bus_match_table, NULL,
                 &platform_bus);
+
+        bcm_kona_smc_init();
+
+        kona_l2_cache_init();
 }
 
 static const char * const bcm11351_dt_compat[] = { "bcm,bcm11351", NULL, };
 
 DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor")
         .init_irq = irqchip_init,
-        .init_time = timer_init,
+        .init_time = clocksource_of_init,
         .init_machine = board_init,
         .dt_compat = bcm11351_dt_compat,
 MACHINE_END
diff --git a/arch/arm/mach-bcm2835/Kconfig b/arch/arm/mach-bcm2835/Kconfig
new file mode 100644
index 000000000000..560045cafc34
--- /dev/null
+++ b/arch/arm/mach-bcm2835/Kconfig
@@ -0,0 +1,15 @@
+config ARCH_BCM2835
+        bool "Broadcom BCM2835 family" if ARCH_MULTI_V6
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_AMBA
+        select ARM_ERRATA_411920
+        select ARM_TIMER_SP804
+        select CLKDEV_LOOKUP
+        select CLKSRC_OF
+        select CPU_V6
+        select GENERIC_CLOCKEVENTS
+        select PINCTRL
+        select PINCTRL_BCM2835
+        help
+          This enables support for the Broadcom BCM2835 SoC. This SoC is
+          use in the Raspberry Pi, and Roku 2 devices.
diff --git a/arch/arm/mach-bcm2835/Makefile.boot b/arch/arm/mach-bcm2835/Makefile.boot
deleted file mode 100644
index b3271754e9fd..000000000000
--- a/arch/arm/mach-bcm2835/Makefile.boot
+++ /dev/null
@@ -1 +0,0 @@
-zreladdr-y := 0x00008000
diff --git a/arch/arm/mach-bcm2835/bcm2835.c b/arch/arm/mach-bcm2835/bcm2835.c
index 6f5785985dd1..740fa9ebe249 100644
--- a/arch/arm/mach-bcm2835/bcm2835.c
+++ b/arch/arm/mach-bcm2835/bcm2835.c
@@ -23,8 +23,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <mach/bcm2835_soc.h>
-
 #define PM_RSTC                         0x1c
 #define PM_RSTS                         0x20
 #define PM_WDOG                         0x24
@@ -34,6 +32,10 @@
 #define PM_RSTC_WRCFG_FULL_RESET        0x00000020
 #define PM_RSTS_HADWRH_SET              0x00000040
 
+#define BCM2835_PERIPH_PHYS     0x20000000
+#define BCM2835_PERIPH_VIRT     0xf0000000
+#define BCM2835_PERIPH_SIZE     SZ_16M
+
 static void __iomem *wdt_regs;
 
 /*
diff --git a/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h b/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h
deleted file mode 100644
index d4dfcf7a9cda..000000000000
--- a/arch/arm/mach-bcm2835/include/mach/bcm2835_soc.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (C) 2012 Stephen Warren
- *
- * Derived from code:
- * Copyright (C) 2010 Broadcom
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_BCM2835_BCM2835_SOC_H__
-#define __MACH_BCM2835_BCM2835_SOC_H__
-
-#include <asm/sizes.h>
-
-#define BCM2835_PERIPH_PHYS     0x20000000
-#define BCM2835_PERIPH_VIRT     0xf0000000
-#define BCM2835_PERIPH_SIZE     SZ_16M
-#define BCM2835_DEBUG_PHYS      0x20201000
-#define BCM2835_DEBUG_VIRT      0xf0201000
-
-#endif
diff --git a/arch/arm/mach-bcm2835/include/mach/gpio.h b/arch/arm/mach-bcm2835/include/mach/gpio.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-bcm2835/include/mach/gpio.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-bcm2835/include/mach/timex.h b/arch/arm/mach-bcm2835/include/mach/timex.h
deleted file mode 100644
index 6d021e136ae3..000000000000
--- a/arch/arm/mach-bcm2835/include/mach/timex.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- *  BCM2835 system clock frequency
- *
- *  Copyright (C) 2010 Broadcom
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-
-#define CLOCK_TICK_RATE         (1000000)
-
-#endif
diff --git a/arch/arm/mach-bcm2835/include/mach/uncompress.h b/arch/arm/mach-bcm2835/include/mach/uncompress.h
deleted file mode 100644
index bf86dca3bf71..000000000000
--- a/arch/arm/mach-bcm2835/include/mach/uncompress.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (C) 2010 Broadcom
- * Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/io.h>
-#include <linux/amba/serial.h>
-#include <mach/bcm2835_soc.h>
-
-#define UART0_BASE BCM2835_DEBUG_PHYS
-
-#define BCM2835_UART_DR IOMEM(UART0_BASE + UART01x_DR)
-#define BCM2835_UART_FR IOMEM(UART0_BASE + UART01x_FR)
-#define BCM2835_UART_CR IOMEM(UART0_BASE + UART011_CR)
-
-static inline void putc(int c)
-{
-        while (__raw_readl(BCM2835_UART_FR) & UART01x_FR_TXFF)
-                barrier();
-
-        __raw_writel(c, BCM2835_UART_DR);
-}
-
-static inline void flush(void)
-{
-        int fr;
-
-        do {
-                fr = __raw_readl(BCM2835_UART_FR);
-                barrier();
-        } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
-}
-
-#define arch_decomp_setup()
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig
index 9ebfcc46feb1..dbf0df8bb0ac 100644
--- a/arch/arm/mach-cns3xxx/Kconfig
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -1,8 +1,20 @@
+config ARCH_CNS3XXX
+        bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
+        select ARM_GIC
+        select CPU_V6K
+        select GENERIC_CLOCKEVENTS
+        select MIGHT_HAVE_CACHE_L2X0
+        select MIGHT_HAVE_PCI
+        select PCI_DOMAINS if PCI
+        help
+          Support for Cavium Networks CNS3XXX platform.
+
 menu "CNS3XXX platform type"
         depends on ARCH_CNS3XXX
 
 config MACH_CNS3420VB
         bool "Support for CNS3420 Validation Board"
+        depends on ATAGS
         help
           Include support for the Cavium Networks CNS3420 MPCore Platform
           Baseboard.
diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile
index 11033f1c2e23..a1ff10848698 100644
--- a/arch/arm/mach-cns3xxx/Makefile
+++ b/arch/arm/mach-cns3xxx/Makefile
@@ -1,3 +1,5 @@
-obj-$(CONFIG_ARCH_CNS3XXX)              += core.o pm.o devices.o
-obj-$(CONFIG_PCI)                       += pcie.o
-obj-$(CONFIG_MACH_CNS3420VB)            += cns3420vb.o
+obj-$(CONFIG_ARCH_CNS3XXX)              += cns3xxx.o
+cns3xxx-y                               += core.o pm.o
+cns3xxx-$(CONFIG_ATAGS)                 += devices.o
+cns3xxx-$(CONFIG_PCI)                   += pcie.o
+cns3xxx-$(CONFIG_MACH_CNS3420VB)        += cns3420vb.o
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index a71867e1d8d6..ce096d678aa4 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -31,9 +31,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <mach/cns3xxx.h>
-#include <mach/irqs.h>
-#include <mach/pm.h>
+#include "cns3xxx.h"
+#include "pm.h"
 #include "core.h"
 #include "devices.h"
 
@@ -247,6 +246,7 @@ static void __init cns3420_map_io(void)
 
 MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
         .atag_offset    = 0x100,
+        .nr_irqs        = NR_IRQS_CNS3XXX,
         .map_io         = cns3420_map_io,
         .init_irq       = cns3xxx_init_irq,
         .init_time      = cns3xxx_timer_init,
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/cns3xxx.h
index b1021aafa481..a0f5b60662ae 100644
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+++ b/arch/arm/mach-cns3xxx/cns3xxx.h
@@ -20,22 +20,16 @@
 #define CNS3XXX_SPI_FLASH_BASE                  0x60000000      /* SPI Serial Flash Memory */
 
 #define CNS3XXX_SWITCH_BASE                     0x70000000      /* Switch and HNAT Control */
-#define CNS3XXX_SWITCH_BASE_VIRT                0xFFF00000
 
 #define CNS3XXX_PPE_BASE                        0x70001000      /* HANT */
-#define CNS3XXX_PPE_BASE_VIRT                   0xFFF50000
 
 #define CNS3XXX_EMBEDDED_SRAM_BASE              0x70002000      /* HANT Embedded SRAM */
-#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT         0xFFF60000
 
 #define CNS3XXX_SSP_BASE                        0x71000000      /* Synchronous Serial Port - SPI/PCM/I2C */
-#define CNS3XXX_SSP_BASE_VIRT                   0xFFF01000
 
 #define CNS3XXX_DMC_BASE                        0x72000000      /* DMC Control (DDR2 SDRAM) */
-#define CNS3XXX_DMC_BASE_VIRT                   0xFFF02000
 
 #define CNS3XXX_SMC_BASE                        0x73000000      /* SMC Control */
-#define CNS3XXX_SMC_BASE_VIRT                   0xFFF03000
 
 #define SMC_MEMC_STATUS_OFFSET                  0x000
 #define SMC_MEMIF_CFG_OFFSET                    0x004
@@ -74,13 +68,10 @@
 #define SMC_PCELL_ID_3_OFFSET                   0xFFC
 
 #define CNS3XXX_GPIOA_BASE                      0x74000000      /* GPIO port A */
-#define CNS3XXX_GPIOA_BASE_VIRT                 0xFFF04000
 
 #define CNS3XXX_GPIOB_BASE                      0x74800000      /* GPIO port B */
-#define CNS3XXX_GPIOB_BASE_VIRT                 0xFFF05000
 
 #define CNS3XXX_RTC_BASE                        0x75000000      /* Real Time Clock */
-#define CNS3XXX_RTC_BASE_VIRT                   0xFFF06000
 
 #define RTC_SEC_OFFSET                          0x00
 #define RTC_MIN_OFFSET                          0x04
@@ -112,22 +103,16 @@
 #define CNS3XXX_UART0_BASE_VIRT                 0xFB002000
 
 #define CNS3XXX_UART1_BASE                      0x78400000      /* UART 1 */
-#define CNS3XXX_UART1_BASE_VIRT                 0xFFF0A000
 
 #define CNS3XXX_UART2_BASE                      0x78800000      /* UART 2 */
-#define CNS3XXX_UART2_BASE_VIRT                 0xFFF0B000
 
 #define CNS3XXX_DMAC_BASE                       0x79000000      /* Generic DMA Control */
-#define CNS3XXX_DMAC_BASE_VIRT                  0xFFF0D000
 
 #define CNS3XXX_CORESIGHT_BASE                  0x7A000000      /* CoreSight */
-#define CNS3XXX_CORESIGHT_BASE_VIRT             0xFFF0E000
 
 #define CNS3XXX_CRYPTO_BASE                     0x7B000000      /* Crypto */
-#define CNS3XXX_CRYPTO_BASE_VIRT                0xFFF0F000
 
 #define CNS3XXX_I2S_BASE                        0x7C000000      /* I2S */
-#define CNS3XXX_I2S_BASE_VIRT                   0xFFF10000
 
 #define CNS3XXX_TIMER1_2_3_BASE                 0x7C800000      /* Timer */
 #define CNS3XXX_TIMER1_2_3_BASE_VIRT            0xFB003000
@@ -150,42 +135,31 @@
 #define TIMER_FREERUN_CONTROL_OFFSET            0x44
 
 #define CNS3XXX_HCIE_BASE                       0x7D000000      /* HCIE Control */
-#define CNS3XXX_HCIE_BASE_VIRT                  0xFFF30000
 
 #define CNS3XXX_RAID_BASE                       0x7E000000      /* RAID Control */
-#define CNS3XXX_RAID_BASE_VIRT                  0xFFF12000
 
 #define CNS3XXX_AXI_IXC_BASE                    0x7F000000      /* AXI IXC */
-#define CNS3XXX_AXI_IXC_BASE_VIRT               0xFFF13000
 
 #define CNS3XXX_CLCD_BASE                       0x80000000      /* LCD Control */
-#define CNS3XXX_CLCD_BASE_VIRT                  0xFFF14000
 
 #define CNS3XXX_USBOTG_BASE                     0x81000000      /* USB OTG Control */
-#define CNS3XXX_USBOTG_BASE_VIRT                0xFFF15000
 
 #define CNS3XXX_USB_BASE                        0x82000000      /* USB Host Control */
 
 #define CNS3XXX_SATA2_BASE                      0x83000000      /* SATA */
 #define CNS3XXX_SATA2_SIZE                      SZ_16M
-#define CNS3XXX_SATA2_BASE_VIRT                 0xFFF17000
 
 #define CNS3XXX_CAMERA_BASE                     0x84000000      /* Camera Interface */
-#define CNS3XXX_CAMERA_BASE_VIRT                0xFFF18000
 
 #define CNS3XXX_SDIO_BASE                       0x85000000      /* SDIO */
-#define CNS3XXX_SDIO_BASE_VIRT                  0xFFF19000
 
 #define CNS3XXX_I2S_TDM_BASE                    0x86000000      /* I2S TDM */
-#define CNS3XXX_I2S_TDM_BASE_VIRT               0xFFF1A000
 
 #define CNS3XXX_2DG_BASE                        0x87000000      /* 2D Graphic Control */
-#define CNS3XXX_2DG_BASE_VIRT                   0xFFF1B000
 
 #define CNS3XXX_USB_OHCI_BASE                   0x88000000      /* USB OHCI */
 
 #define CNS3XXX_L2C_BASE                        0x92000000      /* L2 Cache Control */
-#define CNS3XXX_L2C_BASE_VIRT                   0xFFF27000
 
 #define CNS3XXX_PCIE0_MEM_BASE                  0xA0000000      /* PCIe Port 0 IO/Memory Space */
 #define CNS3XXX_PCIE0_MEM_BASE_VIRT             0xE0000000
@@ -239,7 +213,6 @@
 #define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT       (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
 
 #define CNS3XXX_TC11MP_L220_BASE                0x92002000      /* L220 registers */
-#define CNS3XXX_TC11MP_L220_BASE_VIRT           0xFF002000
 
 /*
  * Misc block
@@ -553,6 +526,8 @@ int cns3xxx_cpu_clock(void);
 /*
  * ARM11 MPCore interrupt sources (primary GIC)
  */
+#define IRQ_TC11MP_GIC_START    32
+
 #define IRQ_CNS3XXX_PMU                 (IRQ_TC11MP_GIC_START + 0)
 #define IRQ_CNS3XXX_SDIO                (IRQ_TC11MP_GIC_START + 1)
 #define IRQ_CNS3XXX_L2CC                (IRQ_TC11MP_GIC_START + 2)
@@ -624,9 +599,4 @@ int cns3xxx_cpu_clock(void);
 
 #define NR_IRQS_CNS3XXX                 (IRQ_TC11MP_GIC_START + 64)
 
-#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX)
-#undef NR_IRQS
-#define NR_IRQS                         NR_IRQS_CNS3XXX
-#endif
-
 #endif  /* __MACH_BOARD_CNS3XXX_H */
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index 52e4bb5cf12d..e38b279f402c 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -13,12 +13,18 @@
 #include <linux/clockchips.h>
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/usb/ehci_pdriver.h>
+#include <linux/usb/ohci_pdriver.h>
+#include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <mach/cns3xxx.h>
+#include "cns3xxx.h"
 #include "core.h"
+#include "pm.h"
 
 static struct map_desc cns3xxx_io_desc[] __initdata = {
         {
@@ -32,16 +38,6 @@ static struct map_desc cns3xxx_io_desc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = CNS3XXX_GPIOA_BASE_VIRT,
-                .pfn            = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = CNS3XXX_GPIOB_BASE_VIRT,
-                .pfn            = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
                 .virtual        = CNS3XXX_MISC_BASE_VIRT,
                 .pfn            = __phys_to_pfn(CNS3XXX_MISC_BASE),
                 .length         = SZ_4K,
@@ -266,3 +262,116 @@ void __init cns3xxx_l2x0_init(void)
 }
 
 #endif /* CONFIG_CACHE_L2X0 */
+
+static int csn3xxx_usb_power_on(struct platform_device *pdev)
+{
+        /*
+         * EHCI and OHCI share the same clock and power,
+         * resetting twice would cause the 1st controller been reset.
+         * Therefore only do power up  at the first up device, and
+         * power down at the last down device.
+         *
+         * Set USB AHB INCR length to 16
+         */
+        if (atomic_inc_return(&usb_pwr_ref) == 1) {
+                cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
+                cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
+                cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
+                __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
+                        MISC_CHIP_CONFIG_REG);
+        }
+
+        return 0;
+}
+
+static void csn3xxx_usb_power_off(struct platform_device *pdev)
+{
+        /*
+         * EHCI and OHCI share the same clock and power,
+         * resetting twice would cause the 1st controller been reset.
+         * Therefore only do power up  at the first up device, and
+         * power down at the last down device.
+         */
+        if (atomic_dec_return(&usb_pwr_ref) == 0)
+                cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
+}
+
+static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
+        .power_on       = csn3xxx_usb_power_on,
+        .power_off      = csn3xxx_usb_power_off,
+};
+
+static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
+        .num_ports      = 1,
+        .power_on       = csn3xxx_usb_power_on,
+        .power_off      = csn3xxx_usb_power_off,
+};
+
+static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
+        { "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata },
+        { "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata },
+        { "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL },
+        { "cavium,cns3420-sdhci", CNS3XXX_SDIO_BASE, "ahci", NULL },
+        {},
+};
+
+static void __init cns3xxx_init(void)
+{
+        struct device_node *dn;
+
+        cns3xxx_l2x0_init();
+
+        dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci");
+        if (of_device_is_available(dn)) {
+                u32 tmp;
+        
+                tmp = __raw_readl(MISC_SATA_POWER_MODE);
+                tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
+                tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
+                __raw_writel(tmp, MISC_SATA_POWER_MODE);
+        
+                /* Enable SATA PHY */
+                cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
+                cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
+        
+                /* Enable SATA Clock */
+                cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
+        
+                /* De-Asscer SATA Reset */
+                cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
+        }
+
+        dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci");
+        if (of_device_is_available(dn)) {
+                u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
+                u32 gpioa_pins = __raw_readl(gpioa);
+        
+                /* MMC/SD pins share with GPIOA */
+                gpioa_pins |= 0x1fff0004;
+                __raw_writel(gpioa_pins, gpioa);
+        
+                cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
+                cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
+        }
+
+        pm_power_off = cns3xxx_power_off;
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        cns3xxx_auxdata, NULL);
+}
+
+static const char *cns3xxx_dt_compat[] __initdata = {
+        "cavium,cns3410",
+        "cavium,cns3420",
+        NULL,
+};
+
+DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx")
+        .dt_compat      = cns3xxx_dt_compat,
+        .nr_irqs        = NR_IRQS_CNS3XXX,
+        .map_io         = cns3xxx_map_io,
+        .init_irq       = cns3xxx_init_irq,
+        .init_time      = cns3xxx_timer_init,
+        .init_machine   = cns3xxx_init,
+        .restart        = cns3xxx_restart,
+MACHINE_END
diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
index 1e40c99b015f..7da78a2451f1 100644
--- a/arch/arm/mach-cns3xxx/devices.c
+++ b/arch/arm/mach-cns3xxx/devices.c
@@ -16,9 +16,8 @@
 #include <linux/compiler.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
-#include <mach/cns3xxx.h>
-#include <mach/irqs.h>
-#include <mach/pm.h>
+#include "cns3xxx.h"
+#include "pm.h"
 #include "core.h"
 #include "devices.h"
 
diff --git a/arch/arm/mach-cns3xxx/include/mach/irqs.h b/arch/arm/mach-cns3xxx/include/mach/irqs.h
deleted file mode 100644
index 2ab96f8085c8..000000000000
--- a/arch/arm/mach-cns3xxx/include/mach/irqs.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2000 Deep Blue Solutions Ltd.
- * Copyright 2003 ARM Limited
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-
-#define IRQ_LOCALTIMER          29
-#define IRQ_LOCALWDOG           30
-#define IRQ_TC11MP_GIC_START    32
-
-#include <mach/cns3xxx.h>
-
-#ifndef NR_IRQS
-#error "NR_IRQS not defined by the board-specific files"
-#endif
-
-#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/timex.h b/arch/arm/mach-cns3xxx/include/mach/timex.h
deleted file mode 100644
index 1fd04217cacb..000000000000
--- a/arch/arm/mach-cns3xxx/include/mach/timex.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Cavium Networks architecture timex specifications
- *
- * Copyright 2003 ARM Limited
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/arch/arm/mach-cns3xxx/include/mach/uncompress.h b/arch/arm/mach-cns3xxx/include/mach/uncompress.h
deleted file mode 100644
index 7a030b99df84..000000000000
--- a/arch/arm/mach-cns3xxx/include/mach/uncompress.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright 2003 ARM Limited
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#include <asm/mach-types.h>
-#include <mach/cns3xxx.h>
-
-#define AMBA_UART_DR(base)      (*(volatile unsigned char *)((base) + 0x00))
-#define AMBA_UART_LCRH(base)    (*(volatile unsigned char *)((base) + 0x2c))
-#define AMBA_UART_CR(base)      (*(volatile unsigned char *)((base) + 0x30))
-#define AMBA_UART_FR(base)      (*(volatile unsigned char *)((base) + 0x18))
-
-/*
- * Return the UART base address
- */
-static inline unsigned long get_uart_base(void)
-{
-        if (machine_is_cns3420vb())
-                return CNS3XXX_UART0_BASE;
-        else
-                return 0;
-}
-
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
-        unsigned long base = get_uart_base();
-
-        while (AMBA_UART_FR(base) & (1 << 5))
-                barrier();
-
-        AMBA_UART_DR(base) = c;
-}
-
-static inline void flush(void)
-{
-        unsigned long base = get_uart_base();
-
-        while (AMBA_UART_FR(base) & (1 << 3))
-                barrier();
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index 311328314163..c7b204bff386 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -20,7 +20,7 @@
 #include <linux/interrupt.h>
 #include <linux/ptrace.h>
 #include <asm/mach/map.h>
-#include <mach/cns3xxx.h>
+#include "cns3xxx.h"
 #include "core.h"
 
 enum cns3xxx_access_type {
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 36458080332a..79e3d47aad65 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -11,8 +11,8 @@
 #include <linux/io.h>
 #include <linux/delay.h>
 #include <linux/atomic.h>
-#include <mach/cns3xxx.h>
-#include <mach/pm.h>
+#include "cns3xxx.h"
+#include "pm.h"
 #include "core.h"
 
 void cns3xxx_pwr_clk_en(unsigned int block)
diff --git a/arch/arm/mach-cns3xxx/include/mach/pm.h b/arch/arm/mach-cns3xxx/pm.h
index c2588cc991d1..c2588cc991d1 100644
--- a/arch/arm/mach-cns3xxx/include/mach/pm.h
+++ b/arch/arm/mach-cns3xxx/pm.h
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index fb5c1aa98a63..dd1ffccc75e9 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -37,7 +37,6 @@ obj-$(CONFIG_MACH_MITYOMAPL138)		+= board-mityomapl138.o
 obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD)   += board-omapl138-hawk.o
 
 # Power Management
-obj-$(CONFIG_CPU_FREQ)                  += cpufreq.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
 obj-$(CONFIG_SUSPEND)                   += pm.o sleep.o
 obj-$(CONFIG_HAVE_CLK)                  += pm_domain.o
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 6da25eebf911..1332de8c52c9 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -246,7 +246,6 @@ static struct davinci_mmc_config da830_evm_mmc_config = {
         .wires                  = 8,
         .max_freq               = 50000000,
         .caps                   = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .version                = MMC_CTLR_VERSION_2,
 };
 
 static inline void da830_evm_init_mmc(void)
@@ -298,11 +297,7 @@ static const short da830_evm_emif25_pins[] = {
         -1
 };
 
-#if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE)
-#define HAS_MMC 1
-#else
-#define HAS_MMC 0
-#endif
+#define HAS_MMC         IS_ENABLED(CONFIG_MMC_DAVINCI)
 
 #ifdef CONFIG_DA830_UI_NAND
 static struct mtd_partition da830_evm_nand_partitions[] = {
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index c2dfe06563df..8a24b6c6339f 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -335,12 +335,7 @@ static const short da850_evm_nor_pins[] = {
         -1
 };
 
-#if defined(CONFIG_MMC_DAVINCI) || \
-    defined(CONFIG_MMC_DAVINCI_MODULE)
-#define HAS_MMC 1
-#else
-#define HAS_MMC 0
-#endif
+#define HAS_MMC         IS_ENABLED(CONFIG_MMC_DAVINCI)
 
 static inline void da850_evm_setup_nor_nand(void)
 {
@@ -401,7 +396,7 @@ enum da850_evm_ui_exp_pins {
         DA850_EVM_UI_EXP_PB1,
 };
 
-static const char const *da850_evm_ui_exp[] = {
+static const char * const da850_evm_ui_exp[] = {
         [DA850_EVM_UI_EXP_SEL_C]        = "sel_c",
         [DA850_EVM_UI_EXP_SEL_B]        = "sel_b",
         [DA850_EVM_UI_EXP_SEL_A]        = "sel_a",
@@ -565,7 +560,7 @@ enum da850_evm_bb_exp_pins {
         DA850_EVM_BB_EXP_USER_SW8
 };
 
-static const char const *da850_evm_bb_exp[] = {
+static const char * const da850_evm_bb_exp[] = {
         [DA850_EVM_BB_EXP_DEEP_SLEEP_EN]        = "deep_sleep_en",
         [DA850_EVM_BB_EXP_SW_RST]               = "sw_rst",
         [DA850_EVM_BB_EXP_TP_23]                = "tp_23",
@@ -802,7 +797,6 @@ static struct davinci_mmc_config da850_mmc_config = {
         .wires          = 4,
         .max_freq       = 50000000,
         .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .version        = MMC_CTLR_VERSION_2,
 };
 
 static const short da850_evm_mmcsd0_pins[] __initconst = {
@@ -1372,7 +1366,6 @@ static struct davinci_mmc_config da850_wl12xx_mmc_config = {
         .max_freq       = 25000000,
         .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_NONREMOVABLE |
                           MMC_CAP_POWER_OFF_CARD,
-        .version        = MMC_CTLR_VERSION_2,
 };
 
 static const short da850_wl12xx_pins[] __initconst = {
@@ -1579,6 +1572,11 @@ static __init void da850_evm_init(void)
                 pr_warn("%s: SATA registration failed: %d\n", __func__, ret);
 
         da850_evm_setup_mac_addr();
+
+        ret = da8xx_register_rproc();
+        if (ret)
+                pr_warn("%s: dsp/rproc registration failed: %d\n",
+                        __func__, ret);
 }
 
 #ifdef CONFIG_SERIAL_8250_CONSOLE
@@ -1606,4 +1604,5 @@ MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
         .init_late      = davinci_init_late,
         .dma_zone_size  = SZ_128M,
         .restart        = da8xx_restart,
+        .reserve        = da8xx_rproc_reserve_cma,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 147b8e1a4407..c2a0a67d09e0 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -242,6 +242,73 @@ static struct vpfe_config vpfe_cfg = {
         .ccdc = "DM355 CCDC",
 };
 
+/* venc standards timings */
+static struct vpbe_enc_mode_info dm355evm_enc_preset_timing[] = {
+        {
+                .name           = "ntsc",
+                .timings_type   = VPBE_ENC_STD,
+                .std_id         = V4L2_STD_NTSC,
+                .interlaced     = 1,
+                .xres           = 720,
+                .yres           = 480,
+                .aspect         = {11, 10},
+                .fps            = {30000, 1001},
+                .left_margin    = 0x79,
+                .upper_margin   = 0x10,
+        },
+        {
+                .name           = "pal",
+                .timings_type   = VPBE_ENC_STD,
+                .std_id         = V4L2_STD_PAL,
+                .interlaced     = 1,
+                .xres           = 720,
+                .yres           = 576,
+                .aspect         = {54, 59},
+                .fps            = {25, 1},
+                .left_margin    = 0x7E,
+                .upper_margin   = 0x16
+        },
+};
+
+#define VENC_STD_ALL    (V4L2_STD_NTSC | V4L2_STD_PAL)
+
+/*
+ * The outputs available from VPBE + ecnoders. Keep the
+ * the order same as that of encoders. First those from venc followed by that
+ * from encoders. Index in the output refers to index on a particular encoder.
+ * Driver uses this index to pass it to encoder when it supports more than
+ * one output. Application uses index of the array to set an output.
+ */
+static struct vpbe_output dm355evm_vpbe_outputs[] = {
+        {
+                .output         = {
+                        .index          = 0,
+                        .name           = "Composite",
+                        .type           = V4L2_OUTPUT_TYPE_ANALOG,
+                        .std            = VENC_STD_ALL,
+                        .capabilities   = V4L2_OUT_CAP_STD,
+                },
+                .subdev_name    = DM355_VPBE_VENC_SUBDEV_NAME,
+                .default_mode   = "ntsc",
+                .num_modes      = ARRAY_SIZE(dm355evm_enc_preset_timing),
+                .modes          = dm355evm_enc_preset_timing,
+                .if_params      = V4L2_MBUS_FMT_FIXED,
+        },
+};
+
+static struct vpbe_config dm355evm_display_cfg = {
+        .module_name    = "dm355-vpbe-display",
+        .i2c_adapter_id = 1,
+        .osd            = {
+                .module_name    = DM355_VPBE_OSD_SUBDEV_NAME,
+        },
+        .venc           = {
+                .module_name    = DM355_VPBE_VENC_SUBDEV_NAME,
+        },
+        .num_outputs    = ARRAY_SIZE(dm355evm_vpbe_outputs),
+        .outputs        = dm355evm_vpbe_outputs,
+};
+
 static struct platform_device *davinci_evm_devices[] __initdata = {
         &dm355evm_dm9000,
         &davinci_nand_device,
@@ -253,8 +320,6 @@ static struct davinci_uart_config uart_config __initdata = {
 
 static void __init dm355_evm_map_io(void)
 {
-        /* setup input configuration for VPFE input devices */
-        dm355_set_vpfe_config(&vpfe_cfg);
         dm355_init();
 }
 
@@ -280,7 +345,6 @@ static struct davinci_mmc_config dm355evm_mmc_config = {
         .wires          = 4,
         .max_freq       = 50000000,
         .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .version        = MMC_CTLR_VERSION_1,
 };
 
 /* Don't connect anything to J10 unless you're only using USB host
@@ -344,6 +408,8 @@ static __init void dm355_evm_init(void)
         davinci_setup_mmc(0, &dm355evm_mmc_config);
         davinci_setup_mmc(1, &dm355evm_mmc_config);
 
+        dm355_init_video(&vpfe_cfg, &dm355evm_display_cfg);
+
         dm355_init_spi0(BIT(0), dm355_evm_spi_info,
                         ARRAY_SIZE(dm355_evm_spi_info));
 
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index c2d4958a0cb6..fd38c8d22e3c 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -27,6 +27,7 @@
 #include <linux/input.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/eeprom.h>
+#include <linux/v4l2-dv-timings.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -39,6 +40,7 @@
 #include <linux/platform_data/mtd-davinci.h>
 #include <linux/platform_data/keyscan-davinci.h>
 
+#include <media/ths7303.h>
 #include <media/tvp514x.h>
 
 #include "davinci.h"
@@ -253,7 +255,6 @@ static struct davinci_mmc_config dm365evm_mmc_config = {
         .wires          = 4,
         .max_freq       = 50000000,
         .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .version        = MMC_CTLR_VERSION_2,
 };
 
 static void dm365evm_emac_configure(void)
@@ -374,6 +375,166 @@ static struct vpfe_config vpfe_cfg = {
         .ccdc = "ISIF",
 };
 
+/* venc standards timings */
+static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = {
+        {
+                .name           = "ntsc",
+                .timings_type   = VPBE_ENC_STD,
+                .std_id         = V4L2_STD_NTSC,
+                .interlaced     = 1,
+                .xres           = 720,
+                .yres           = 480,
+                .aspect         = {11, 10},
+                .fps            = {30000, 1001},
+                .left_margin    = 0x79,
+                .upper_margin   = 0x10,
+        },
+        {
+                .name           = "pal",
+                .timings_type   = VPBE_ENC_STD,
+                .std_id         = V4L2_STD_PAL,
+                .interlaced     = 1,
+                .xres           = 720,
+                .yres           = 576,
+                .aspect         = {54, 59},
+                .fps            = {25, 1},
+                .left_margin    = 0x7E,
+                .upper_margin   = 0x16,
+        },
+};
+
+/* venc dv timings */
+static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = {
+        {
+                .name           = "480p59_94",
+                .timings_type   = VPBE_ENC_DV_TIMINGS,
+                .dv_timings     = V4L2_DV_BT_CEA_720X480P59_94,
+                .interlaced     = 0,
+                .xres           = 720,
+                .yres           = 480,
+                .aspect         = {1, 1},
+                .fps            = {5994, 100},
+                .left_margin    = 0x8F,
+                .upper_margin   = 0x2D,
+        },
+        {
+                .name           = "576p50",
+                .timings_type   = VPBE_ENC_DV_TIMINGS,
+                .dv_timings     = V4L2_DV_BT_CEA_720X576P50,
+                .interlaced     = 0,
+                .xres           = 720,
+                .yres           = 576,
+                .aspect         = {1, 1},
+                .fps            = {50, 1},
+                .left_margin    = 0x8C,
+                .upper_margin   = 0x36,
+        },
+        {
+                .name           = "720p60",
+                .timings_type   = VPBE_ENC_DV_TIMINGS,
+                .dv_timings     = V4L2_DV_BT_CEA_1280X720P60,
+                .interlaced     = 0,
+                .xres           = 1280,
+                .yres           = 720,
+                .aspect         = {1, 1},
+                .fps            = {60, 1},
+                .left_margin    = 0x117,
+                .right_margin   = 70,
+                .upper_margin   = 38,
+                .lower_margin   = 3,
+                .hsync_len      = 80,
+                .vsync_len      = 5,
+        },
+        {
+                .name           = "1080i60",
+                .timings_type   = VPBE_ENC_DV_TIMINGS,
+                .dv_timings     = V4L2_DV_BT_CEA_1920X1080I60,
+                .interlaced     = 1,
+                .xres           = 1920,
+                .yres           = 1080,
+                .aspect         = {1, 1},
+                .fps            = {30, 1},
+                .left_margin    = 0xc9,
+                .right_margin   = 80,
+                .upper_margin   = 30,
+                .lower_margin   = 3,
+                .hsync_len      = 88,
+                .vsync_len      = 5,
+        },
+};
+
+#define VENC_STD_ALL    (V4L2_STD_NTSC | V4L2_STD_PAL)
+
+/*
+ * The outputs available from VPBE + ecnoders. Keep the
+ * the order same as that of encoders. First those from venc followed by that
+ * from encoders. Index in the output refers to index on a particular
+ * encoder.Driver uses this index to pass it to encoder when it supports more
+ * than one output. Application uses index of the array to set an output.
+ */
+static struct vpbe_output dm365evm_vpbe_outputs[] = {
+        {
+                .output         = {
+                        .index          = 0,
+                        .name           = "Composite",
+                        .type           = V4L2_OUTPUT_TYPE_ANALOG,
+                        .std            = VENC_STD_ALL,
+                        .capabilities   = V4L2_OUT_CAP_STD,
+                },
+                .subdev_name    = DM365_VPBE_VENC_SUBDEV_NAME,
+                .default_mode   = "ntsc",
+                .num_modes      = ARRAY_SIZE(dm365evm_enc_std_timing),
+                .modes          = dm365evm_enc_std_timing,
+                .if_params      = V4L2_MBUS_FMT_FIXED,
+        },
+        {
+                .output         = {
+                        .index          = 1,
+                        .name           = "Component",
+                        .type           = V4L2_OUTPUT_TYPE_ANALOG,
+                        .capabilities   = V4L2_OUT_CAP_DV_TIMINGS,
+                },
+                .subdev_name    = DM365_VPBE_VENC_SUBDEV_NAME,
+                .default_mode   = "480p59_94",
+                .num_modes      = ARRAY_SIZE(dm365evm_enc_preset_timing),
+                .modes          = dm365evm_enc_preset_timing,
+                .if_params      = V4L2_MBUS_FMT_FIXED,
+        },
+};
+
+/*
+ * Amplifiers on the board
+ */
+struct ths7303_platform_data ths7303_pdata = {
+        .ch_1 = 3,
+        .ch_2 = 3,
+        .ch_3 = 3,
+        .init_enable = 1,
+};
+
+static struct amp_config_info vpbe_amp = {
+        .module_name    = "ths7303",
+        .is_i2c         = 1,
+        .board_info     = {
+                I2C_BOARD_INFO("ths7303", 0x2c),
+                .platform_data = &ths7303_pdata,
+        }
+};
+
+static struct vpbe_config dm365evm_display_cfg = {
+        .module_name    = "dm365-vpbe-display",
+        .i2c_adapter_id = 1,
+        .amp            = &vpbe_amp,
+        .osd            = {
+                .module_name    = DM365_VPBE_OSD_SUBDEV_NAME,
+        },
+        .venc           = {
+                .module_name    = DM365_VPBE_VENC_SUBDEV_NAME,
+        },
+        .num_outputs    = ARRAY_SIZE(dm365evm_vpbe_outputs),
+        .outputs        = dm365evm_vpbe_outputs,
+};
+
 static void __init evm_init_i2c(void)
 {
         davinci_init_i2c(&i2c_pdata);
@@ -564,8 +725,6 @@ static struct davinci_uart_config uart_config __initdata = {
 
 static void __init dm365_evm_map_io(void)
 {
-        /* setup input configuration for VPFE input devices */
-        dm365_set_vpfe_config(&vpfe_cfg);
         dm365_init();
 }
 
@@ -597,6 +756,8 @@ static __init void dm365_evm_init(void)
 
         davinci_setup_mmc(0, &dm365evm_mmc_config);
 
+        dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg);
+
         /* maybe setup mmc1/etc ... _after_ mmc0 */
         evm_init_cpld();
 
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 71735e7797cc..a33686a6fbb2 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -570,7 +570,6 @@ static struct davinci_mmc_config dm6446evm_mmc_config = {
         .get_cd         = dm6444evm_mmc_get_cd,
         .get_ro         = dm6444evm_mmc_get_ro,
         .wires          = 4,
-        .version        = MMC_CTLR_VERSION_1
 };
 
 static struct i2c_board_info __initdata i2c_info[] =  {
@@ -622,7 +621,7 @@ static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
         {
                 .name           = "ntsc",
                 .timings_type   = VPBE_ENC_STD,
-                .std_id         = V4L2_STD_525_60,
+                .std_id         = V4L2_STD_NTSC,
                 .interlaced     = 1,
                 .xres           = 720,
                 .yres           = 480,
@@ -634,7 +633,7 @@ static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
         {
                 .name           = "pal",
                 .timings_type   = VPBE_ENC_STD,
-                .std_id         = V4L2_STD_625_50,
+                .std_id         = V4L2_STD_PAL,
                 .interlaced     = 1,
                 .xres           = 720,
                 .yres           = 576,
@@ -649,7 +648,7 @@ static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
 static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {
         {
                 .name           = "480p59_94",
-                .timings_type   = VPBE_ENC_CUSTOM_TIMINGS,
+                .timings_type   = VPBE_ENC_DV_TIMINGS,
                 .dv_timings     = V4L2_DV_BT_CEA_720X480P59_94,
                 .interlaced     = 0,
                 .xres           = 720,
@@ -661,7 +660,7 @@ static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {
         },
         {
                 .name           = "576p50",
-                .timings_type   = VPBE_ENC_CUSTOM_TIMINGS,
+                .timings_type   = VPBE_ENC_DV_TIMINGS,
                 .dv_timings     = V4L2_DV_BT_CEA_720X576P50,
                 .interlaced     = 0,
                 .xres           = 720,
@@ -750,26 +749,11 @@ static int davinci_phy_fixup(struct phy_device *phydev)
         return 0;
 }
 
-#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
-    defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
-#define HAS_ATA 1
-#else
-#define HAS_ATA 0
-#endif
-
-#if defined(CONFIG_MTD_PHYSMAP) || \
-    defined(CONFIG_MTD_PHYSMAP_MODULE)
-#define HAS_NOR 1
-#else
-#define HAS_NOR 0
-#endif
-
-#if defined(CONFIG_MTD_NAND_DAVINCI) || \
-    defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
-#define HAS_NAND 1
-#else
-#define HAS_NAND 0
-#endif
+#define HAS_ATA         IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710)
+
+#define HAS_NOR         IS_ENABLED(CONFIG_MTD_PHYSMAP)
+
+#define HAS_NAND        IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
 
 static __init void davinci_evm_init(void)
 {
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index de7adff324dc..fbb8e5ab1dc1 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -117,12 +117,7 @@ static struct platform_device davinci_nand_device = {
         },
 };
 
-#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
-    defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
-#define HAS_ATA 1
-#else
-#define HAS_ATA 0
-#endif
+#define HAS_ATA         IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710)
 
 /* CPLD Register 0 bits to control ATA */
 #define DM646X_EVM_ATA_RST              BIT(0)
@@ -514,7 +509,7 @@ static const struct vpif_output dm6467_ch0_outputs[] = {
                         .index = 1,
                         .name = "Component",
                         .type = V4L2_OUTPUT_TYPE_ANALOG,
-                        .capabilities = V4L2_OUT_CAP_CUSTOM_TIMINGS,
+                        .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
                 },
                 .subdev_name = "adv7343",
                 .output_route = ADV7343_COMPONENT_ID,
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 1c98107527fa..2bc112adf565 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -164,23 +164,11 @@ static void __init davinci_ntosd2_map_io(void)
 
 static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
         .wires          = 4,
-        .version        = MMC_CTLR_VERSION_1
 };
 
+#define HAS_ATA         IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710)
 
-#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
-        defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
-#define HAS_ATA 1
-#else
-#define HAS_ATA 0
-#endif
-
-#if defined(CONFIG_MTD_NAND_DAVINCI) || \
-        defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
-#define HAS_NAND 1
-#else
-#define HAS_NAND 0
-#endif
+#define HAS_NAND        IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
 
 static __init void davinci_ntosd2_init(void)
 {
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index 5a2bd44da54d..b8c20de10ca2 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -136,7 +136,6 @@ static struct davinci_mmc_config da850_mmc_config = {
         .wires          = 4,
         .max_freq       = 50000000,
         .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .version        = MMC_CTLR_VERSION_2,
 };
 
 static __init void omapl138_hawk_mmc_init(void)
@@ -311,6 +310,11 @@ static __init void omapl138_hawk_init(void)
         if (ret)
                 pr_warn("%s: watchdog registration failed: %d\n",
                         __func__, ret);
+
+        ret = da8xx_register_rproc();
+        if (ret)
+                pr_warn("%s: dsp/rproc registration failed: %d\n",
+                        __func__, ret);
 }
 
 #ifdef CONFIG_SERIAL_8250_CONSOLE
@@ -338,4 +342,5 @@ MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard")
         .init_late      = davinci_init_late,
         .dma_zone_size  = SZ_128M,
         .restart        = da8xx_restart,
+        .reserve        = da8xx_rproc_reserve_cma,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index 4f416023d4e2..ba798370fc96 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -85,7 +85,6 @@ static struct davinci_mmc_config mmc_config = {
         .wires          = 4,
         .max_freq       = 50000000,
         .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .version        = MMC_CTLR_VERSION_1,
 };
 
 static const short sdio1_pins[] __initconst = {
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index d458558ee84a..dc9a470ff9c5 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -35,19 +35,26 @@ static void __clk_enable(struct clk *clk)
 {
         if (clk->parent)
                 __clk_enable(clk->parent);
-        if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
-                davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
-                                true, clk->flags);
+        if (clk->usecount++ == 0) {
+                if (clk->flags & CLK_PSC)
+                        davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
+                                           true, clk->flags);
+                else if (clk->clk_enable)
+                        clk->clk_enable(clk);
+        }
 }
 
 static void __clk_disable(struct clk *clk)
 {
         if (WARN_ON(clk->usecount == 0))
                 return;
-        if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
-            (clk->flags & CLK_PSC))
-                davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
-                                false, clk->flags);
+        if (--clk->usecount == 0) {
+                if (!(clk->flags & CLK_PLL) && (clk->flags & CLK_PSC))
+                        davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
+                                           false, clk->flags);
+                else if (clk->clk_disable)
+                        clk->clk_disable(clk);
+        }
         if (clk->parent)
                 __clk_disable(clk->parent);
 }
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 8694b395fc92..1e4e836173a1 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -104,6 +104,8 @@ struct clk {
         int (*set_rate) (struct clk *clk, unsigned long rate);
         int (*round_rate) (struct clk *clk, unsigned long rate);
         int (*reset) (struct clk *clk, bool reset);
+        void (*clk_enable) (struct clk *clk);
+        void (*clk_disable) (struct clk *clk);
 };
 
 /* Clock flags: SoC-specific flags start at BIT(16) */
diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c
deleted file mode 100644
index 4729eaab0f40..000000000000
--- a/arch/arm/mach-davinci/cpufreq.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * CPU frequency scaling for DaVinci
- *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Based on linux/arch/arm/plat-omap/cpu-omap.c. Original Copyright follows:
- *
- *  Copyright (C) 2005 Nokia Corporation
- *  Written by Tony Lindgren <tony@atomide.com>
- *
- *  Based on cpu-sa1110.c, Copyright (C) 2001 Russell King
- *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Updated to support OMAP3
- * Rajendra Nayak <rnayak@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/types.h>
-#include <linux/cpufreq.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/export.h>
-
-#include <mach/hardware.h>
-#include <mach/cpufreq.h>
-#include <mach/common.h>
-
-#include "clock.h"
-
-struct davinci_cpufreq {
-        struct device *dev;
-        struct clk *armclk;
-        struct clk *asyncclk;
-        unsigned long asyncrate;
-};
-static struct davinci_cpufreq cpufreq;
-
-static int davinci_verify_speed(struct cpufreq_policy *policy)
-{
-        struct davinci_cpufreq_config *pdata = cpufreq.dev->platform_data;
-        struct cpufreq_frequency_table *freq_table = pdata->freq_table;
-        struct clk *armclk = cpufreq.armclk;
-
-        if (freq_table)
-                return cpufreq_frequency_table_verify(policy, freq_table);
-
-        if (policy->cpu)
-                return -EINVAL;
-
-        cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
-                                     policy->cpuinfo.max_freq);
-
-        policy->min = clk_round_rate(armclk, policy->min * 1000) / 1000;
-        policy->max = clk_round_rate(armclk, policy->max * 1000) / 1000;
-        cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
-                                                policy->cpuinfo.max_freq);
-        return 0;
-}
-
-static unsigned int davinci_getspeed(unsigned int cpu)
-{
-        if (cpu)
-                return 0;
-
-        return clk_get_rate(cpufreq.armclk) / 1000;
-}
-
-static int davinci_target(struct cpufreq_policy *policy,
-                                unsigned int target_freq, unsigned int relation)
-{
-        int ret = 0;
-        unsigned int idx;
-        struct cpufreq_freqs freqs;
-        struct davinci_cpufreq_config *pdata = cpufreq.dev->platform_data;
-        struct clk *armclk = cpufreq.armclk;
-
-        /*
-         * Ensure desired rate is within allowed range.  Some govenors
-         * (ondemand) will just pass target_freq=0 to get the minimum.
-         */
-        if (target_freq < policy->cpuinfo.min_freq)
-                target_freq = policy->cpuinfo.min_freq;
-        if (target_freq > policy->cpuinfo.max_freq)
-                target_freq = policy->cpuinfo.max_freq;
-
-        freqs.old = davinci_getspeed(0);
-        freqs.new = clk_round_rate(armclk, target_freq * 1000) / 1000;
-        freqs.cpu = 0;
-
-        if (freqs.old == freqs.new)
-                return ret;
-
-        dev_dbg(cpufreq.dev, "transition: %u --> %u\n", freqs.old, freqs.new);
-
-        ret = cpufreq_frequency_table_target(policy, pdata->freq_table,
-                                                freqs.new, relation, &idx);
-        if (ret)
-                return -EINVAL;
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
-        /* if moving to higher frequency, up the voltage beforehand */
-        if (pdata->set_voltage && freqs.new > freqs.old) {
-                ret = pdata->set_voltage(idx);
-                if (ret)
-                        goto out;
-        }
-
-        ret = clk_set_rate(armclk, idx);
-        if (ret)
-                goto out;
-
-        if (cpufreq.asyncclk) {
-                ret = clk_set_rate(cpufreq.asyncclk, cpufreq.asyncrate);
-                if (ret)
-                        goto out;
-        }
-
-        /* if moving to lower freq, lower the voltage after lowering freq */
-        if (pdata->set_voltage && freqs.new < freqs.old)
-                pdata->set_voltage(idx);
-
-out:
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
-        return ret;
-}
-
-static int davinci_cpu_init(struct cpufreq_policy *policy)
-{
-        int result = 0;
-        struct davinci_cpufreq_config *pdata = cpufreq.dev->platform_data;
-        struct cpufreq_frequency_table *freq_table = pdata->freq_table;
-
-        if (policy->cpu != 0)
-                return -EINVAL;
-
-        /* Finish platform specific initialization */
-        if (pdata->init) {
-                result = pdata->init();
-                if (result)
-                        return result;
-        }
-
-        policy->cur = policy->min = policy->max = davinci_getspeed(0);
-
-        if (freq_table) {
-                result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
-                if (!result)
-                        cpufreq_frequency_table_get_attr(freq_table,
-                                                        policy->cpu);
-        } else {
-                policy->cpuinfo.min_freq = policy->min;
-                policy->cpuinfo.max_freq = policy->max;
-        }
-
-        policy->min = policy->cpuinfo.min_freq;
-        policy->max = policy->cpuinfo.max_freq;
-        policy->cur = davinci_getspeed(0);
-
-        /*
-         * Time measurement across the target() function yields ~1500-1800us
-         * time taken with no drivers on notification list.
-         * Setting the latency to 2000 us to accommodate addition of drivers
-         * to pre/post change notification list.
-         */
-        policy->cpuinfo.transition_latency = 2000 * 1000;
-        return 0;
-}
-
-static int davinci_cpu_exit(struct cpufreq_policy *policy)
-{
-        cpufreq_frequency_table_put_attr(policy->cpu);
-        return 0;
-}
-
-static struct freq_attr *davinci_cpufreq_attr[] = {
-        &cpufreq_freq_attr_scaling_available_freqs,
-        NULL,
-};
-
-static struct cpufreq_driver davinci_driver = {
-        .flags          = CPUFREQ_STICKY,
-        .verify         = davinci_verify_speed,
-        .target         = davinci_target,
-        .get            = davinci_getspeed,
-        .init           = davinci_cpu_init,
-        .exit           = davinci_cpu_exit,
-        .name           = "davinci",
-        .attr           = davinci_cpufreq_attr,
-};
-
-static int __init davinci_cpufreq_probe(struct platform_device *pdev)
-{
-        struct davinci_cpufreq_config *pdata = pdev->dev.platform_data;
-        struct clk *asyncclk;
-
-        if (!pdata)
-                return -EINVAL;
-        if (!pdata->freq_table)
-                return -EINVAL;
-
-        cpufreq.dev = &pdev->dev;
-
-        cpufreq.armclk = clk_get(NULL, "arm");
-        if (IS_ERR(cpufreq.armclk)) {
-                dev_err(cpufreq.dev, "Unable to get ARM clock\n");
-                return PTR_ERR(cpufreq.armclk);
-        }
-
-        asyncclk = clk_get(cpufreq.dev, "async");
-        if (!IS_ERR(asyncclk)) {
-                cpufreq.asyncclk = asyncclk;
-                cpufreq.asyncrate = clk_get_rate(asyncclk);
-        }
-
-        return cpufreq_register_driver(&davinci_driver);
-}
-
-static int __exit davinci_cpufreq_remove(struct platform_device *pdev)
-{
-        clk_put(cpufreq.armclk);
-
-        if (cpufreq.asyncclk)
-                clk_put(cpufreq.asyncclk);
-
-        return cpufreq_unregister_driver(&davinci_driver);
-}
-
-static struct platform_driver davinci_cpufreq_driver = {
-        .driver = {
-                .name    = "cpufreq-davinci",
-                .owner   = THIS_MODULE,
-        },
-        .remove = __exit_p(davinci_cpufreq_remove),
-};
-
-int __init davinci_cpufreq_init(void)
-{
-        return platform_driver_probe(&davinci_cpufreq_driver,
-                                                        davinci_cpufreq_probe);
-}
-
diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
index 5ac9e9384b15..36aef3a7dedb 100644
--- a/arch/arm/mach-davinci/cpuidle.c
+++ b/arch/arm/mach-davinci/cpuidle.c
@@ -25,7 +25,6 @@
 
 #define DAVINCI_CPUIDLE_MAX_STATES      2
 
-static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
 static void __iomem *ddr2_reg_base;
 static bool ddr2_pdown;
 
@@ -50,14 +49,10 @@ static void davinci_save_ddr_power(int enter, bool pdown)
 
 /* Actual code that puts the SoC in different idle states */
 static int davinci_enter_idle(struct cpuidle_device *dev,
-                                struct cpuidle_driver *drv,
-                                                int index)
+                              struct cpuidle_driver *drv, int index)
 {
         davinci_save_ddr_power(1, ddr2_pdown);
-
-        index = cpuidle_wrap_enter(dev, drv, index,
-                                arm_cpuidle_simple_enter);
-
+        cpu_do_idle();
         davinci_save_ddr_power(0, ddr2_pdown);
 
         return index;
@@ -66,7 +61,6 @@ static int davinci_enter_idle(struct cpuidle_device *dev,
 static struct cpuidle_driver davinci_idle_driver = {
         .name                   = "cpuidle-davinci",
         .owner                  = THIS_MODULE,
-        .en_core_tk_irqen       = 1,
         .states[0]              = ARM_CPUIDLE_WFI_STATE,
         .states[1]              = {
                 .enter                  = davinci_enter_idle,
@@ -81,12 +75,8 @@ static struct cpuidle_driver davinci_idle_driver = {
 
 static int __init davinci_cpuidle_probe(struct platform_device *pdev)
 {
-        int ret;
-        struct cpuidle_device *device;
         struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
 
-        device = &per_cpu(davinci_cpuidle_device, smp_processor_id());
-
         if (!pdata) {
                 dev_err(&pdev->dev, "cannot get platform data\n");
                 return -ENOENT;
@@ -96,20 +86,7 @@ static int __init davinci_cpuidle_probe(struct platform_device *pdev)
 
         ddr2_pdown = pdata->ddr2_pdown;
 
-        ret = cpuidle_register_driver(&davinci_idle_driver);
-        if (ret) {
-                dev_err(&pdev->dev, "failed to register driver\n");
-                return ret;
-        }
-
-        ret = cpuidle_register_device(device);
-        if (ret) {
-                dev_err(&pdev->dev, "failed to register device\n");
-                cpuidle_unregister_driver(&davinci_idle_driver);
-                return ret;
-        }
-
-        return 0;
+        return cpuidle_register(&davinci_idle_driver, NULL);
 }
 
 static struct platform_driver davinci_cpuidle_driver = {
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 678a54a64dae..abbaf0270be6 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -394,7 +394,7 @@ static struct clk_lookup da830_clks[] = {
         CLK(NULL,               "tpcc",         &tpcc_clk),
         CLK(NULL,               "tptc0",        &tptc0_clk),
         CLK(NULL,               "tptc1",        &tptc1_clk),
-        CLK("davinci_mmc.0",    NULL,           &mmcsd_clk),
+        CLK("da830-mmc.0",      NULL,           &mmcsd_clk),
         CLK(NULL,               "uart0",        &uart0_clk),
         CLK(NULL,               "uart1",        &uart1_clk),
         CLK(NULL,               "uart2",        &uart2_clk),
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 0c4a26ddebba..4d6933848abf 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -383,6 +383,49 @@ static struct clk dsp_clk = {
         .flags          = PSC_LRST | PSC_FORCE,
 };
 
+static struct clk ehrpwm_clk = {
+        .name           = "ehrpwm",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_PWM,
+        .gpsc           = 1,
+        .flags          = DA850_CLK_ASYNC3,
+};
+
+#define DA8XX_EHRPWM_TBCLKSYNC  BIT(12)
+
+static void ehrpwm_tblck_enable(struct clk *clk)
+{
+        u32 val;
+
+        val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
+        val |= DA8XX_EHRPWM_TBCLKSYNC;
+        writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
+}
+
+static void ehrpwm_tblck_disable(struct clk *clk)
+{
+        u32 val;
+
+        val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
+        val &= ~DA8XX_EHRPWM_TBCLKSYNC;
+        writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
+}
+
+static struct clk ehrpwm_tbclk = {
+        .name           = "ehrpwm_tbclk",
+        .parent         = &ehrpwm_clk,
+        .clk_enable     = ehrpwm_tblck_enable,
+        .clk_disable    = ehrpwm_tblck_disable,
+};
+
+static struct clk ecap_clk = {
+        .name           = "ecap",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_ECAP,
+        .gpsc           = 1,
+        .flags          = DA850_CLK_ASYNC3,
+};
+
 static struct clk_lookup da850_clks[] = {
         CLK(NULL,               "ref",          &ref_clk),
         CLK(NULL,               "pll0",         &pll0_clk),
@@ -420,8 +463,8 @@ static struct clk_lookup da850_clks[] = {
         CLK("davinci_emac.1",   NULL,           &emac_clk),
         CLK("davinci-mcasp.0",  NULL,           &mcasp_clk),
         CLK("da8xx_lcdc.0",     "fck",          &lcdc_clk),
-        CLK("davinci_mmc.0",    NULL,           &mmcsd0_clk),
-        CLK("davinci_mmc.1",    NULL,           &mmcsd1_clk),
+        CLK("da830-mmc.0",      NULL,           &mmcsd0_clk),
+        CLK("da830-mmc.1",      NULL,           &mmcsd1_clk),
         CLK(NULL,               "aemif",        &aemif_clk),
         CLK(NULL,               "usb11",        &usb11_clk),
         CLK(NULL,               "usb20",        &usb20_clk),
@@ -430,6 +473,9 @@ static struct clk_lookup da850_clks[] = {
         CLK("vpif",             NULL,           &vpif_clk),
         CLK("ahci",             NULL,           &sata_clk),
         CLK("davinci-rproc.0",  NULL,           &dsp_clk),
+        CLK("ehrpwm",           "fck",          &ehrpwm_clk),
+        CLK("ehrpwm",           "tbclk",        &ehrpwm_tbclk),
+        CLK("ecap",             "fck",          &ecap_clk),
         CLK(NULL,               NULL,           NULL),
 };
 
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index 6b7a0a27fbd1..b1c0a5958275 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -20,7 +20,7 @@
 
 #define DA8XX_NUM_UARTS 3
 
-void __init da8xx_uart_clk_enable(void)
+static void __init da8xx_uart_clk_enable(void)
 {
         int i;
         for (i = 0; i < DA8XX_NUM_UARTS; i++)
@@ -37,9 +37,10 @@ static void __init da8xx_init_irq(void)
         of_irq_init(da8xx_irq_match);
 }
 
-struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
+static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("ti,davinci-i2c", 0x01c22000, "i2c_davinci.1", NULL),
         OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "watchdog", NULL),
+        OF_DEV_AUXDATA("ti,da830-mmc", 0x01c40000, "da830-mmc.0", NULL),
         {}
 };
 
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index 12d544befcfa..1ab3df423dac 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -36,12 +36,19 @@
 #include <media/davinci/vpbe_osd.h>
 
 #define DAVINCI_SYSTEM_MODULE_BASE      0x01c40000
+#define SYSMOD_VDAC_CONFIG              0x2c
 #define SYSMOD_VIDCLKCTL                0x38
 #define SYSMOD_VPSS_CLKCTL              0x44
 #define SYSMOD_VDD3P3VPWDN              0x48
 #define SYSMOD_VSCLKDIS                 0x6c
 #define SYSMOD_PUPDCTL1                 0x7c
 
+/* VPSS CLKCTL bit definitions */
+#define VPSS_MUXSEL_EXTCLK_ENABLE       BIT(1)
+#define VPSS_VENCCLKEN_ENABLE           BIT(3)
+#define VPSS_DACCLKEN_ENABLE            BIT(4)
+#define VPSS_PLLC2SYSCLK5_ENABLE        BIT(5)
+
 extern void __iomem *davinci_sysmod_base;
 #define DAVINCI_SYSMOD_VIRT(x)  (davinci_sysmod_base + (x))
 void davinci_map_sysmod(void);
@@ -74,7 +81,7 @@ void __init dm355_init(void);
 void dm355_init_spi0(unsigned chipselect_mask,
                 const struct spi_board_info *info, unsigned len);
 void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata);
-void dm355_set_vpfe_config(struct vpfe_config *cfg);
+int dm355_init_video(struct vpfe_config *, struct vpbe_config *);
 
 /* DM365 function declarations */
 void __init dm365_init(void);
@@ -84,7 +91,7 @@ void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
 void __init dm365_init_rtc(void);
 void dm365_init_spi0(unsigned chipselect_mask,
                         const struct spi_board_info *info, unsigned len);
-void dm365_set_vpfe_config(struct vpfe_config *cfg);
+int dm365_init_video(struct vpfe_config *, struct vpbe_config *);
 
 /* DM644x function declarations */
 void __init dm644x_init(void);
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index fc50243b1481..bf572525175d 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -12,7 +12,7 @@
  */
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
+#include <linux/dma-contiguous.h>
 #include <linux/serial_8250.h>
 #include <linux/ahci_platform.h>
 #include <linux/clk.h>
@@ -664,7 +664,7 @@ static struct resource da8xx_mmcsd0_resources[] = {
 };
 
 static struct platform_device da8xx_mmcsd0_device = {
-        .name           = "davinci_mmc",
+        .name           = "da830-mmc",
         .id             = 0,
         .num_resources  = ARRAY_SIZE(da8xx_mmcsd0_resources),
         .resource       = da8xx_mmcsd0_resources,
@@ -701,7 +701,7 @@ static struct resource da850_mmcsd1_resources[] = {
 };
 
 static struct platform_device da850_mmcsd1_device = {
-        .name           = "davinci_mmc",
+        .name           = "da830-mmc",
         .id             = 1,
         .num_resources  = ARRAY_SIZE(da850_mmcsd1_resources),
         .resource       = da850_mmcsd1_resources,
@@ -714,6 +714,92 @@ int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
 }
 #endif
 
+static struct resource da8xx_rproc_resources[] = {
+        { /* DSP boot address */
+                .start          = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
+                .end            = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
+                .flags          = IORESOURCE_MEM,
+        },
+        { /* DSP interrupt registers */
+                .start          = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
+                .end            = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
+                .flags          = IORESOURCE_MEM,
+        },
+        { /* dsp irq */
+                .start          = IRQ_DA8XX_CHIPINT0,
+                .end            = IRQ_DA8XX_CHIPINT0,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device da8xx_dsp = {
+        .name   = "davinci-rproc",
+        .dev    = {
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(da8xx_rproc_resources),
+        .resource       = da8xx_rproc_resources,
+};
+
+#if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
+
+static phys_addr_t rproc_base __initdata;
+static unsigned long rproc_size __initdata;
+
+static int __init early_rproc_mem(char *p)
+{
+        char *endp;
+
+        if (p == NULL)
+                return 0;
+
+        rproc_size = memparse(p, &endp);
+        if (*endp == '@')
+                rproc_base = memparse(endp + 1, NULL);
+
+        return 0;
+}
+early_param("rproc_mem", early_rproc_mem);
+
+void __init da8xx_rproc_reserve_cma(void)
+{
+        int ret;
+
+        if (!rproc_base || !rproc_size) {
+                pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
+                       "    'nn' and 'address' must both be non-zero\n",
+                       __func__);
+
+                return;
+        }
+
+        pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
+                __func__, rproc_size, (unsigned long)rproc_base);
+
+        ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
+        if (ret)
+                pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
+}
+
+#else
+
+void __init da8xx_rproc_reserve_cma(void)
+{
+}
+
+#endif
+
+int __init da8xx_register_rproc(void)
+{
+        int ret;
+
+        ret = platform_device_register(&da8xx_dsp);
+        if (ret)
+                pr_err("%s: can't register DSP device: %d\n", __func__, ret);
+
+        return ret;
+};
+
 static struct resource da8xx_rtc_resources[] = {
         {
                 .start          = DA8XX_RTC_BASE,
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index 773ab07a71a0..cfb194df18ed 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -218,7 +218,7 @@ static u64 mmc1_dma_mask = DMA_BIT_MASK(32);
 
 static struct platform_device mmc_devices[2] = {
         {
-                .name           = "davinci_mmc",
+                .name           = "dm6441-mmc",
                 .id             = 0,
                 .dev            = {
                         .dma_mask               = &mmc0_dma_mask,
@@ -228,7 +228,7 @@ static struct platform_device mmc_devices[2] = {
                 .resource       = mmc0_resources
         },
         {
-                .name           = "davinci_mmc",
+                .name           = "dm6441-mmc",
                 .id             = 1,
                 .dev            = {
                         .dma_mask               = &mmc1_dma_mask,
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 4c48a36ee567..a7068a3aa9d3 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -119,7 +119,7 @@ void __init davinci_init_ide(void)
         platform_device_register(&ide_device);
 }
 
-#if     defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE)
+#if IS_ENABLED(CONFIG_MMC_DAVINCI)
 
 static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32);
 
@@ -150,7 +150,7 @@ static struct resource mmcsd0_resources[] = {
 };
 
 static struct platform_device davinci_mmcsd0_device = {
-        .name = "davinci_mmc",
+        .name = "dm6441-mmc",
         .id = 0,
         .dev = {
                 .dma_mask = &mmcsd0_dma_mask,
@@ -187,7 +187,7 @@ static struct resource mmcsd1_resources[] = {
 };
 
 static struct platform_device davinci_mmcsd1_device = {
-        .name = "davinci_mmc",
+        .name = "dm6441-mmc",
         .id = 1,
         .dev = {
                 .dma_mask = &mmcsd1_dma_mask,
@@ -235,6 +235,7 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
                         mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
                                                         SZ_4K - 1;
                         mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1;
+                        davinci_mmcsd1_device.name = "da830-mmc";
                 } else
                         break;
 
@@ -256,6 +257,7 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
                         mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
                                                         SZ_4K - 1;
                         mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0;
+                        davinci_mmcsd0_device.name = "da830-mmc";
                 } else if (cpu_is_davinci_dm644x()) {
                         /* REVISIT: should this be in board-init code? */
                         /* Power-on 3.3V IO cells */
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index b49c3b77d55e..a11034a358f1 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -35,6 +35,8 @@
 #include "asp.h"
 
 #define DM355_UART2_BASE        (IO_PHYS + 0x206000)
+#define DM355_OSD_BASE          (IO_PHYS + 0x70200)
+#define DM355_VENC_BASE         (IO_PHYS + 0x70400)
 
 /*
  * Device specific clocks
@@ -345,8 +347,8 @@ static struct clk_lookup dm355_clks[] = {
         CLK(NULL, "pll1_aux", &pll1_aux_clk),
         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
         CLK(NULL, "vpss_dac", &vpss_dac_clk),
-        CLK(NULL, "vpss_master", &vpss_master_clk),
-        CLK(NULL, "vpss_slave", &vpss_slave_clk),
+        CLK("vpss", "master", &vpss_master_clk),
+        CLK("vpss", "slave", &vpss_slave_clk),
         CLK(NULL, "clkout1", &clkout1_clk),
         CLK(NULL, "clkout2", &clkout2_clk),
         CLK(NULL, "pll2", &pll2_clk),
@@ -361,8 +363,8 @@ static struct clk_lookup dm355_clks[] = {
         CLK("i2c_davinci.1", NULL, &i2c_clk),
         CLK("davinci-mcbsp.0", NULL, &asp0_clk),
         CLK("davinci-mcbsp.1", NULL, &asp1_clk),
-        CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
-        CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
+        CLK("dm6441-mmc.0", NULL, &mmcsd0_clk),
+        CLK("dm6441-mmc.1", NULL, &mmcsd1_clk),
         CLK("spi_davinci.0", NULL, &spi0_clk),
         CLK("spi_davinci.1", NULL, &spi1_clk),
         CLK("spi_davinci.2", NULL, &spi2_clk),
@@ -744,11 +746,146 @@ static struct platform_device vpfe_capture_dev = {
         },
 };
 
-void dm355_set_vpfe_config(struct vpfe_config *cfg)
+static struct resource dm355_osd_resources[] = {
+        {
+                .start  = DM355_OSD_BASE,
+                .end    = DM355_OSD_BASE + 0x17f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device dm355_osd_dev = {
+        .name           = DM355_VPBE_OSD_SUBDEV_NAME,
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(dm355_osd_resources),
+        .resource       = dm355_osd_resources,
+        .dev            = {
+                .dma_mask               = &vpfe_capture_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+static struct resource dm355_venc_resources[] = {
+        {
+                .start  = IRQ_VENCINT,
+                .end    = IRQ_VENCINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        /* venc registers io space */
+        {
+                .start  = DM355_VENC_BASE,
+                .end    = DM355_VENC_BASE + 0x17f,
+                .flags  = IORESOURCE_MEM,
+        },
+        /* VDAC config register io space */
+        {
+                .start  = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
+                .end    = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct resource dm355_v4l2_disp_resources[] = {
+        {
+                .start  = IRQ_VENCINT,
+                .end    = IRQ_VENCINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        /* venc registers io space */
+        {
+                .start  = DM355_VENC_BASE,
+                .end    = DM355_VENC_BASE + 0x17f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static int dm355_vpbe_setup_pinmux(enum v4l2_mbus_pixelcode if_type,
+                            int field)
+{
+        switch (if_type) {
+        case V4L2_MBUS_FMT_SGRBG8_1X8:
+                davinci_cfg_reg(DM355_VOUT_FIELD_G70);
+                break;
+        case V4L2_MBUS_FMT_YUYV10_1X20:
+                if (field)
+                        davinci_cfg_reg(DM355_VOUT_FIELD);
+                else
+                        davinci_cfg_reg(DM355_VOUT_FIELD_G70);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        davinci_cfg_reg(DM355_VOUT_COUTL_EN);
+        davinci_cfg_reg(DM355_VOUT_COUTH_EN);
+
+        return 0;
+}
+
+static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type,
+                                   unsigned int pclock)
 {
-        vpfe_capture_dev.dev.platform_data = cfg;
+        void __iomem *vpss_clk_ctrl_reg;
+
+        vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
+
+        switch (type) {
+        case VPBE_ENC_STD:
+                writel(VPSS_DACCLKEN_ENABLE | VPSS_VENCCLKEN_ENABLE,
+                       vpss_clk_ctrl_reg);
+                break;
+        case VPBE_ENC_DV_TIMINGS:
+                if (pclock > 27000000)
+                        /*
+                         * For HD, use external clock source since we cannot
+                         * support HD mode with internal clocks.
+                         */
+                        writel(VPSS_MUXSEL_EXTCLK_ENABLE, vpss_clk_ctrl_reg);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
 }
 
+static struct platform_device dm355_vpbe_display = {
+        .name           = "vpbe-v4l2",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(dm355_v4l2_disp_resources),
+        .resource       = dm355_v4l2_disp_resources,
+        .dev            = {
+                .dma_mask               = &vpfe_capture_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+struct venc_platform_data dm355_venc_pdata = {
+        .setup_pinmux   = dm355_vpbe_setup_pinmux,
+        .setup_clock    = dm355_venc_setup_clock,
+};
+
+static struct platform_device dm355_venc_dev = {
+        .name           = DM355_VPBE_VENC_SUBDEV_NAME,
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(dm355_venc_resources),
+        .resource       = dm355_venc_resources,
+        .dev            = {
+                .dma_mask               = &vpfe_capture_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = (void *)&dm355_venc_pdata,
+        },
+};
+
+static struct platform_device dm355_vpbe_dev = {
+        .name           = "vpbe_controller",
+        .id             = -1,
+        .dev            = {
+                .dma_mask               = &vpfe_capture_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
 /*----------------------------------------------------------------------*/
 
 static struct map_desc dm355_io_desc[] = {
@@ -868,19 +1005,36 @@ void __init dm355_init(void)
         davinci_map_sysmod();
 }
 
+int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
+                                struct vpbe_config *vpbe_cfg)
+{
+        if (vpfe_cfg || vpbe_cfg)
+                platform_device_register(&dm355_vpss_device);
+
+        if (vpfe_cfg) {
+                vpfe_capture_dev.dev.platform_data = vpfe_cfg;
+                platform_device_register(&dm355_ccdc_dev);
+                platform_device_register(&vpfe_capture_dev);
+        }
+
+        if (vpbe_cfg) {
+                dm355_vpbe_dev.dev.platform_data = vpbe_cfg;
+                platform_device_register(&dm355_osd_dev);
+                platform_device_register(&dm355_venc_dev);
+                platform_device_register(&dm355_vpbe_dev);
+                platform_device_register(&dm355_vpbe_display);
+        }
+
+        return 0;
+}
+
 static int __init dm355_init_devices(void)
 {
         if (!cpu_is_davinci_dm355())
                 return 0;
 
-        /* Add ccdc clock aliases */
-        clk_add_alias("master", dm355_ccdc_dev.name, "vpss_master", NULL);
-        clk_add_alias("slave", dm355_ccdc_dev.name, "vpss_master", NULL);
         davinci_cfg_reg(DM355_INT_EDMA_CC);
         platform_device_register(&dm355_edma_device);
-        platform_device_register(&dm355_vpss_device);
-        platform_device_register(&dm355_ccdc_dev);
-        platform_device_register(&vpfe_capture_dev);
 
         return 0;
 }
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 6c3980540be0..40fa4fee9331 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -39,16 +39,13 @@
 #include "asp.h"
 
 #define DM365_REF_FREQ          24000000        /* 24 MHz on the DM365 EVM */
-
-/* Base of key scan register bank */
-#define DM365_KEYSCAN_BASE              0x01c69400
-
 #define DM365_RTC_BASE                  0x01c69000
-
+#define DM365_KEYSCAN_BASE              0x01c69400
+#define DM365_OSD_BASE                  0x01c71c00
+#define DM365_VENC_BASE                 0x01c71e00
 #define DAVINCI_DM365_VC_BASE           0x01d0c000
 #define DAVINCI_DMA_VC_TX               2
 #define DAVINCI_DMA_VC_RX               3
-
 #define DM365_EMAC_BASE                 0x01d07000
 #define DM365_EMAC_MDIO_BASE            (DM365_EMAC_BASE + 0x4000)
 #define DM365_EMAC_CNTRL_OFFSET         0x0000
@@ -257,6 +254,12 @@ static struct clk vpss_master_clk = {
         .flags          = CLK_PSC,
 };
 
+static struct clk vpss_slave_clk = {
+        .name           = "vpss_slave",
+        .parent         = &pll1_sysclk5,
+        .lpsc           = DAVINCI_LPSC_VPSSSLV,
+};
+
 static struct clk arm_clk = {
         .name           = "arm_clk",
         .parent         = &pll2_sysclk2,
@@ -449,13 +452,14 @@ static struct clk_lookup dm365_clks[] = {
         CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
         CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
         CLK(NULL, "vpss_dac", &vpss_dac_clk),
-        CLK(NULL, "vpss_master", &vpss_master_clk),
+        CLK("vpss", "master", &vpss_master_clk),
+        CLK("vpss", "slave", &vpss_slave_clk),
         CLK(NULL, "arm", &arm_clk),
         CLK(NULL, "uart0", &uart0_clk),
         CLK(NULL, "uart1", &uart1_clk),
         CLK("i2c_davinci.1", NULL, &i2c_clk),
-        CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
-        CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
+        CLK("da830-mmc.0", NULL, &mmcsd0_clk),
+        CLK("da830-mmc.1", NULL, &mmcsd1_clk),
         CLK("spi_davinci.0", NULL, &spi0_clk),
         CLK("spi_davinci.1", NULL, &spi1_clk),
         CLK("spi_davinci.2", NULL, &spi2_clk),
@@ -1226,6 +1230,173 @@ static struct platform_device dm365_isif_dev = {
         },
 };
 
+static struct resource dm365_osd_resources[] = {
+        {
+                .start = DM365_OSD_BASE,
+                .end   = DM365_OSD_BASE + 0xff,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device dm365_osd_dev = {
+        .name           = DM365_VPBE_OSD_SUBDEV_NAME,
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(dm365_osd_resources),
+        .resource       = dm365_osd_resources,
+        .dev            = {
+                .dma_mask               = &dm365_video_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+static struct resource dm365_venc_resources[] = {
+        {
+                .start = IRQ_VENCINT,
+                .end   = IRQ_VENCINT,
+                .flags = IORESOURCE_IRQ,
+        },
+        /* venc registers io space */
+        {
+                .start = DM365_VENC_BASE,
+                .end   = DM365_VENC_BASE + 0x177,
+                .flags = IORESOURCE_MEM,
+        },
+        /* vdaccfg registers io space */
+        {
+                .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
+                .end   = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+static struct resource dm365_v4l2_disp_resources[] = {
+        {
+                .start = IRQ_VENCINT,
+                .end   = IRQ_VENCINT,
+                .flags = IORESOURCE_IRQ,
+        },
+        /* venc registers io space */
+        {
+                .start = DM365_VENC_BASE,
+                .end   = DM365_VENC_BASE + 0x177,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+static int dm365_vpbe_setup_pinmux(enum v4l2_mbus_pixelcode if_type,
+                            int field)
+{
+        switch (if_type) {
+        case V4L2_MBUS_FMT_SGRBG8_1X8:
+                davinci_cfg_reg(DM365_VOUT_FIELD_G81);
+                davinci_cfg_reg(DM365_VOUT_COUTL_EN);
+                davinci_cfg_reg(DM365_VOUT_COUTH_EN);
+                break;
+        case V4L2_MBUS_FMT_YUYV10_1X20:
+                if (field)
+                        davinci_cfg_reg(DM365_VOUT_FIELD);
+                else
+                        davinci_cfg_reg(DM365_VOUT_FIELD_G81);
+                davinci_cfg_reg(DM365_VOUT_COUTL_EN);
+                davinci_cfg_reg(DM365_VOUT_COUTH_EN);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
+                                  unsigned int pclock)
+{
+        void __iomem *vpss_clkctl_reg;
+        u32 val;
+
+        vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
+
+        switch (type) {
+        case VPBE_ENC_STD:
+                val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
+                break;
+        case VPBE_ENC_DV_TIMINGS:
+                if (pclock <= 27000000) {
+                        val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
+                } else {
+                        /* set sysclk4 to output 74.25 MHz from pll1 */
+                        val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
+                              VPSS_VENCCLKEN_ENABLE;
+                }
+                break;
+        default:
+                return -EINVAL;
+        }
+        writel(val, vpss_clkctl_reg);
+
+        return 0;
+}
+
+static struct platform_device dm365_vpbe_display = {
+        .name           = "vpbe-v4l2",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(dm365_v4l2_disp_resources),
+        .resource       = dm365_v4l2_disp_resources,
+        .dev            = {
+                .dma_mask               = &dm365_video_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+struct venc_platform_data dm365_venc_pdata = {
+        .setup_pinmux   = dm365_vpbe_setup_pinmux,
+        .setup_clock    = dm365_venc_setup_clock,
+};
+
+static struct platform_device dm365_venc_dev = {
+        .name           = DM365_VPBE_VENC_SUBDEV_NAME,
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(dm365_venc_resources),
+        .resource       = dm365_venc_resources,
+        .dev            = {
+                .dma_mask               = &dm365_video_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = (void *)&dm365_venc_pdata,
+        },
+};
+
+static struct platform_device dm365_vpbe_dev = {
+        .name           = "vpbe_controller",
+        .id             = -1,
+        .dev            = {
+                .dma_mask               = &dm365_video_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
+                                struct vpbe_config *vpbe_cfg)
+{
+        if (vpfe_cfg || vpbe_cfg)
+                platform_device_register(&dm365_vpss_device);
+
+        if (vpfe_cfg) {
+                vpfe_capture_dev.dev.platform_data = vpfe_cfg;
+                platform_device_register(&dm365_isif_dev);
+                platform_device_register(&vpfe_capture_dev);
+        }
+        if (vpbe_cfg) {
+                dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
+                platform_device_register(&dm365_osd_dev);
+                platform_device_register(&dm365_venc_dev);
+                platform_device_register(&dm365_vpbe_dev);
+                platform_device_register(&dm365_vpbe_display);
+        }
+
+        return 0;
+}
+
 static int __init dm365_init_devices(void)
 {
         if (!cpu_is_davinci_dm365())
@@ -1239,16 +1410,6 @@ static int __init dm365_init_devices(void)
         clk_add_alias(NULL, dev_name(&dm365_mdio_device.dev),
                       NULL, &dm365_emac_device.dev);
 
-        /* Add isif clock alias */
-        clk_add_alias("master", dm365_isif_dev.name, "vpss_master", NULL);
-        platform_device_register(&dm365_vpss_device);
-        platform_device_register(&dm365_isif_dev);
-        platform_device_register(&vpfe_capture_dev);
         return 0;
 }
 postcore_initcall(dm365_init_devices);
-
-void dm365_set_vpfe_config(struct vpfe_config *cfg)
-{
-       vpfe_capture_dev.dev.platform_data = cfg;
-}
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index db1dd92e00af..4d37d3e2a193 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -300,8 +300,8 @@ static struct clk_lookup dm644x_clks[] = {
         CLK(NULL, "dsp", &dsp_clk),
         CLK(NULL, "arm", &arm_clk),
         CLK(NULL, "vicp", &vicp_clk),
-        CLK(NULL, "vpss_master", &vpss_master_clk),
-        CLK(NULL, "vpss_slave", &vpss_slave_clk),
+        CLK("vpss", "master", &vpss_master_clk),
+        CLK("vpss", "slave", &vpss_slave_clk),
         CLK(NULL, "arm", &arm_clk),
         CLK(NULL, "uart0", &uart0_clk),
         CLK(NULL, "uart1", &uart1_clk),
@@ -310,7 +310,7 @@ static struct clk_lookup dm644x_clks[] = {
         CLK("i2c_davinci.1", NULL, &i2c_clk),
         CLK("palm_bk3710", NULL, &ide_clk),
         CLK("davinci-mcbsp", NULL, &asp_clk),
-        CLK("davinci_mmc.0", NULL, &mmcsd_clk),
+        CLK("dm6441-mmc.0", NULL, &mmcsd_clk),
         CLK(NULL, "spi", &spi_clk),
         CLK(NULL, "gpio", &gpio_clk),
         CLK(NULL, "usb", &usb_clk),
@@ -706,7 +706,7 @@ static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
                 v |= DM644X_VPSS_DACCLKEN;
                 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
                 break;
-        case VPBE_ENC_CUSTOM_TIMINGS:
+        case VPBE_ENC_DV_TIMINGS:
                 if (pclock <= 27000000) {
                         v |= DM644X_VPSS_DACCLKEN;
                         writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
@@ -901,11 +901,6 @@ int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
                 dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
                 platform_device_register(&dm644x_ccdc_dev);
                 platform_device_register(&dm644x_vpfe_dev);
-                /* Add ccdc clock aliases */
-                clk_add_alias("master", dm644x_ccdc_dev.name,
-                              "vpss_master", NULL);
-                clk_add_alias("slave", dm644x_ccdc_dev.name,
-                              "vpss_slave", NULL);
         }
 
         if (vpbe_cfg) {
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index de439b7b9af1..2e1c9eae0a58 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -54,7 +54,10 @@ extern unsigned int da850_max_speed;
 #define DA8XX_SYSCFG0_BASE      (IO_PHYS + 0x14000)
 #define DA8XX_SYSCFG0_VIRT(x)   (da8xx_syscfg0_base + (x))
 #define DA8XX_JTAG_ID_REG       0x18
+#define DA8XX_HOST1CFG_REG      0x44
+#define DA8XX_CHIPSIG_REG       0x174
 #define DA8XX_CFGCHIP0_REG      0x17c
+#define DA8XX_CFGCHIP1_REG      0x180
 #define DA8XX_CFGCHIP2_REG      0x184
 #define DA8XX_CFGCHIP3_REG      0x188
 
@@ -104,6 +107,8 @@ int __init da850_register_vpif_display
 int __init da850_register_vpif_capture
                         (struct vpif_capture_config *capture_config);
 void da8xx_restart(char mode, const char *cmd);
+void da8xx_rproc_reserve_cma(void);
+int da8xx_register_rproc(void);
 
 extern struct platform_device da8xx_serial_device;
 extern struct emac_platform_data da8xx_emac_pdata;
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index 34290d14754b..b18b8ebc6508 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -24,8 +24,6 @@
 
 #if defined(CONFIG_DEBUG_DAVINCI_DMx_UART0)
 #define UART_BASE       DAVINCI_UART0_BASE
-#elif defined(CONFIG_DEBUG_DAVINCI_DA8XX_UART0)
-#define UART_BASE       DA8XX_UART0_BASE
 #elif defined(CONFIG_DEBUG_DAVINCI_DA8XX_UART1)
 #define UART_BASE       DA8XX_UART1_BASE
 #elif defined(CONFIG_DEBUG_DAVINCI_DA8XX_UART2)
diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c
index eb8360b33aa9..a508fe587af7 100644
--- a/arch/arm/mach-davinci/pm.c
+++ b/arch/arm/mach-davinci/pm.c
@@ -19,6 +19,7 @@
 #include <asm/delay.h>
 #include <asm/io.h>
 
+#include <mach/common.h>
 #include <mach/da8xx.h>
 #include <mach/sram.h>
 #include <mach/pm.h>
diff --git a/arch/arm/mach-davinci/pm_domain.c b/arch/arm/mach-davinci/pm_domain.c
index c90250e3bef8..6b98413cebd6 100644
--- a/arch/arm/mach-davinci/pm_domain.c
+++ b/arch/arm/mach-davinci/pm_domain.c
@@ -53,7 +53,7 @@ static struct dev_pm_domain davinci_pm_domain = {
 
 static struct pm_clk_notifier_block platform_bus_notifier = {
         .pm_domain = &davinci_pm_domain,
-        .con_ids = { "fck", NULL, },
+        .con_ids = { "fck", "master", "slave", NULL },
 };
 
 static int __init davinci_pm_runtime_init(void)
diff --git a/arch/arm/mach-davinci/sram.c b/arch/arm/mach-davinci/sram.c
index c5f7ee5cc80a..f18928b073f5 100644
--- a/arch/arm/mach-davinci/sram.c
+++ b/arch/arm/mach-davinci/sram.c
@@ -62,7 +62,7 @@ static int __init sram_init(void)
         phys_addr_t phys = davinci_soc_info.sram_dma;
         unsigned len = davinci_soc_info.sram_len;
         int status = 0;
-        void *addr;
+        void __iomem *addr;
 
         if (len) {
                 len = min_t(unsigned, len, SRAM_SIZE);
@@ -75,7 +75,7 @@ static int __init sram_init(void)
                 addr = ioremap(phys, len);
                 if (!addr)
                         return -ENOMEM;
-                status = gen_pool_add_virt(sram_pool, (unsigned)addr,
+                status = gen_pool_add_virt(sram_pool, (unsigned long) addr,
                                            phys, len, -1);
                 if (status < 0)
                         iounmap(addr);
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index dc1a209b9b66..3b2a70d43efa 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -272,7 +272,7 @@ static struct clk_lookup clks[] = {
         CLK("tnetv107x-keypad.0", NULL,                 &clk_keypad),
         CLK(NULL,               "clk_gpio",             &clk_gpio),
         CLK(NULL,               "clk_mdio",             &clk_mdio),
-        CLK("davinci_mmc.0",    NULL,                   &clk_sdio0),
+        CLK("dm6441-mmc.0",     NULL,                   &clk_sdio0),
         CLK(NULL,               "uart0",                &clk_uart0),
         CLK(NULL,               "uart1",                &clk_uart1),
         CLK(NULL,               "timer0",               &clk_timer0),
@@ -292,7 +292,7 @@ static struct clk_lookup clks[] = {
         CLK(NULL,               "clk_system",           &clk_system),
         CLK(NULL,               "clk_imcop",            &clk_imcop),
         CLK(NULL,               "clk_spare",            &clk_spare),
-        CLK("davinci_mmc.1",    NULL,                   &clk_sdio1),
+        CLK("dm6441-mmc.1",     NULL,                   &clk_sdio1),
         CLK(NULL,               "clk_ddr2_vrst",        &clk_ddr2_vrst),
         CLK(NULL,               "clk_ddr2_vctl_rst",    &clk_ddr2_vctl_rst),
         CLK(NULL,               NULL,                   NULL),
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
index 34509ffba221..b0a6b522575f 100644
--- a/arch/arm/mach-davinci/usb.c
+++ b/arch/arm/mach-davinci/usb.c
@@ -10,6 +10,7 @@
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/cputype.h>
+#include <mach/da8xx.h>
 #include <linux/platform_data/usb-davinci.h>
 
 #define DAVINCI_USB_OTG_BASE    0x01c64000
@@ -17,7 +18,7 @@
 #define DA8XX_USB0_BASE         0x01e00000
 #define DA8XX_USB1_BASE         0x01e25000
 
-#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
 static struct musb_hdrc_eps_bits musb_eps[] = {
         { "ep1_tx", 8, },
         { "ep1_rx", 8, },
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 70f94c87479d..d19edff0ea6e 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -14,6 +14,7 @@ menu "SAMSUNG EXYNOS SoCs Support"
 config ARCH_EXYNOS4
         bool "SAMSUNG EXYNOS4"
         default y
+        select HAVE_ARM_SCU if SMP
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
         help
@@ -21,6 +22,7 @@ config ARCH_EXYNOS4
 
 config ARCH_EXYNOS5
         bool "SAMSUNG EXYNOS5"
+        select HAVE_ARM_SCU if SMP
         select HAVE_SMP
         help
           Samsung EXYNOS5 (Cortex-A15) SoC based systems
@@ -61,6 +63,7 @@ config SOC_EXYNOS5250
         bool "SAMSUNG EXYNOS5250"
         default y
         depends on ARCH_EXYNOS5
+        select PM_GENERIC_DOMAINS if PM
         select S5P_PM if PM
         select S5P_SLEEP if PM
         select S5P_DEV_MFC
@@ -72,18 +75,27 @@ config SOC_EXYNOS5440
         bool "SAMSUNG EXYNOS5440"
         default y
         depends on ARCH_EXYNOS5
+        select ARCH_HAS_OPP
         select ARM_ARCH_TIMER
         select AUTO_ZRELADDR
         select PINCTRL
         select PINCTRL_EXYNOS5440
+        select PM_OPP
         help
           Enable EXYNOS5440 SoC support
 
-config EXYNOS4_MCT
-        bool
+config EXYNOS_ATAGS
+        bool "ATAGS based boot for EXYNOS (deprecated)"
+        depends on !ARCH_MULTIPLATFORM
+        depends on ATAGS
         default y
         help
-          Use MCT (Multi Core Timer) as kernel timers
+          The EXYNOS platform is moving towards being completely probed
+          through device tree. This enables support for board files using
+          the traditional ATAGS boot format.
+          Note that this option is not available for multiplatform builds.
+
+if EXYNOS_ATAGS
 
 config EXYNOS_DEV_DMA
         bool
@@ -95,11 +107,6 @@ config EXYNOS4_DEV_AHCI
         help
           Compile in platform device definitions for AHCI
 
-config EXYNOS_DEV_DRM
-        bool
-        help
-          Compile in platform device definitions for core DRM device
-
 config EXYNOS4_SETUP_FIMD0
         bool
         help
@@ -199,7 +206,6 @@ config MACH_SMDKV310
         select EXYNOS4_SETUP_SDHCI
         select EXYNOS4_SETUP_USB_PHY
         select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_DRM
         select EXYNOS_DEV_SYSMMU
         select S3C24XX_PWM
         select S3C_DEV_HSMMC
@@ -253,9 +259,7 @@ config MACH_UNIVERSAL_C210
         select EXYNOS4_SETUP_SDHCI
         select EXYNOS4_SETUP_USB_PHY
         select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_DRM
         select EXYNOS_DEV_SYSMMU
-        select HAVE_SCHED_CLOCK
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC2
         select S3C_DEV_HSMMC3
@@ -276,8 +280,8 @@ config MACH_UNIVERSAL_C210
         select S5P_DEV_ONENAND
         select S5P_DEV_TV
         select S5P_GPIO_INT
-        select S5P_HRT
         select S5P_SETUP_MIPIPHY
+        select SAMSUNG_HRT
         help
           Machine support for Samsung Mobile Universal S5PC210 Reference
           Board.
@@ -294,7 +298,6 @@ config MACH_NURI
         select EXYNOS4_SETUP_SDHCI
         select EXYNOS4_SETUP_USB_PHY
         select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_DRM
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC2
         select S3C_DEV_HSMMC3
@@ -330,7 +333,6 @@ config MACH_ORIGEN
         select EXYNOS4_SETUP_SDHCI
         select EXYNOS4_SETUP_USB_PHY
         select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_DRM
         select EXYNOS_DEV_SYSMMU
         select S3C24XX_PWM
         select S3C_DEV_HSMMC
@@ -366,7 +368,6 @@ config MACH_SMDK4212
         select EXYNOS4_SETUP_SDHCI
         select EXYNOS4_SETUP_USB_PHY
         select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_DRM
         select EXYNOS_DEV_SYSMMU
         select S3C24XX_PWM
         select S3C_DEV_HSMMC2
@@ -400,16 +401,20 @@ config MACH_SMDK4412
           Machine support for Samsung SMDK4412
 endif
 
+endif
+
 comment "Flattened Device Tree based board for EXYNOS SoCs"
 
 config MACH_EXYNOS4_DT
         bool "Samsung Exynos4 Machine using device tree"
         depends on ARCH_EXYNOS4
         select ARM_AMBA
+        select CLKSRC_OF
         select CPU_EXYNOS4210
-        select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
+        select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
         select PINCTRL
         select PINCTRL_EXYNOS
+        select S5P_DEV_MFC
         select USE_OF
         help
           Machine support for Samsung Exynos4 machine with device tree enabled.
@@ -422,6 +427,7 @@ config MACH_EXYNOS5_DT
         default y
         depends on ARCH_EXYNOS5
         select ARM_AMBA
+        select CLKSRC_OF
         select USE_OF
         help
           Machine support for Samsung EXYNOS5 machine with device tree enabled.
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 435757e57bb4..b09b027178f3 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -13,10 +13,6 @@ obj-				:=
 # Core
 
 obj-$(CONFIG_ARCH_EXYNOS)       += common.o
-obj-$(CONFIG_ARCH_EXYNOS4)      += clock-exynos4.o
-obj-$(CONFIG_CPU_EXYNOS4210)    += clock-exynos4210.o
-obj-$(CONFIG_SOC_EXYNOS4212)    += clock-exynos4212.o
-obj-$(CONFIG_SOC_EXYNOS5250)    += clock-exynos5.o
 
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
@@ -26,10 +22,14 @@ obj-$(CONFIG_ARCH_EXYNOS)	+= pmu.o
 
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 
-obj-$(CONFIG_EXYNOS4_MCT)       += mct.o
-
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
 
+obj-$(CONFIG_ARCH_EXYNOS)       += exynos-smc.o
+obj-$(CONFIG_ARCH_EXYNOS)       += firmware.o
+
+plus_sec := $(call as-instr,.arch_extension sec,+sec)
+AFLAGS_exynos-smc.o             :=-Wa,-march=armv7-a$(plus_sec)
+
 # machine support
 
 obj-$(CONFIG_MACH_SMDKC210)             += mach-smdkv310.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
deleted file mode 100644
index 8a8468d83c8c..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ /dev/null
@@ -1,1601 +0,0 @@
-/*
- * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-#include "clock-exynos4.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4_clock_save[] = {
-        SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
-        SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
-        SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
-        SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
-        SAVE_ITEM(EXYNOS4_CLKSRC_TV),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
-        SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
-        SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
-        SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
-        SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
-        SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
-        SAVE_ITEM(EXYNOS4_CLKDIV_TV),
-        SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
-        SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
-        SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
-        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
-        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
-        SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
-        SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
-        SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
-        SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
-        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
-        SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
-        SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
-        SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
-        SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
-        SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
-        SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
-        SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
-        SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
-};
-#endif
-
-static struct clk exynos4_clk_sclk_hdmi27m = {
-        .name           = "sclk_hdmi27m",
-        .rate           = 27000000,
-};
-
-static struct clk exynos4_clk_sclk_hdmiphy = {
-        .name           = "sclk_hdmiphy",
-};
-
-static struct clk exynos4_clk_sclk_usbphy0 = {
-        .name           = "sclk_usbphy0",
-        .rate           = 27000000,
-};
-
-static struct clk exynos4_clk_sclk_usbphy1 = {
-        .name           = "sclk_usbphy1",
-};
-
-static struct clk dummy_apb_pclk = {
-        .name           = "apb_pclk",
-        .id             = -1,
-};
-
-static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
-}
-
-static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
-}
-
-static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
-}
-
-int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
-}
-
-static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
-}
-
-static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
-}
-
-static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
-}
-
-static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
-}
-
-static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
-}
-
-int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
-}
-
-static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
-}
-
-int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
-}
-
-int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
-}
-
-static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
-}
-
-static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
-}
-
-int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
-}
-
-static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
-}
-
-static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
-}
-
-/* Core list of CMU_CPU side */
-
-static struct clksrc_clk exynos4_clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-        },
-        .sources = &clk_src_apll,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_apll = {
-        .clk    = {
-                .name           = "sclk_apll",
-                .parent         = &exynos4_clk_mout_apll.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-        },
-        .sources = &clk_src_epll,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
-};
-
-struct clksrc_clk exynos4_clk_mout_mpll = {
-        .clk    = {
-                .name           = "mout_mpll",
-        },
-        .sources = &clk_src_mpll,
-
-        /* reg_src will be added in each SoCs' clock */
-};
-
-static struct clk *exynos4_clkset_moutcore_list[] = {
-        [0] = &exynos4_clk_mout_apll.clk,
-        [1] = &exynos4_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_moutcore = {
-        .sources        = exynos4_clkset_moutcore_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_moutcore_list),
-};
-
-static struct clksrc_clk exynos4_clk_moutcore = {
-        .clk    = {
-                .name           = "moutcore",
-        },
-        .sources = &exynos4_clkset_moutcore,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_coreclk = {
-        .clk    = {
-                .name           = "core_clk",
-                .parent         = &exynos4_clk_moutcore.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_armclk = {
-        .clk    = {
-                .name           = "armclk",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_corem0 = {
-        .clk    = {
-                .name           = "aclk_corem0",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_cores = {
-        .clk    = {
-                .name           = "aclk_cores",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_corem1 = {
-        .clk    = {
-                .name           = "aclk_corem1",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_periphclk = {
-        .clk    = {
-                .name           = "periphclk",
-                .parent         = &exynos4_clk_coreclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
-};
-
-/* Core list of CMU_CORE side */
-
-static struct clk *exynos4_clkset_corebus_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_mout_corebus = {
-        .sources        = exynos4_clkset_corebus_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_corebus_list),
-};
-
-static struct clksrc_clk exynos4_clk_mout_corebus = {
-        .clk    = {
-                .name           = "mout_corebus",
-        },
-        .sources = &exynos4_clkset_mout_corebus,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_dmc = {
-        .clk    = {
-                .name           = "sclk_dmc",
-                .parent         = &exynos4_clk_mout_corebus.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_cored = {
-        .clk    = {
-                .name           = "aclk_cored",
-                .parent         = &exynos4_clk_sclk_dmc.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_corep = {
-        .clk    = {
-                .name           = "aclk_corep",
-                .parent         = &exynos4_clk_aclk_cored.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_acp = {
-        .clk    = {
-                .name           = "aclk_acp",
-                .parent         = &exynos4_clk_mout_corebus.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_pclk_acp = {
-        .clk    = {
-                .name           = "pclk_acp",
-                .parent         = &exynos4_clk_aclk_acp.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
-};
-
-/* Core list of CMU_TOP side */
-
-struct clk *exynos4_clkset_aclk_top_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_aclk = {
-        .sources        = exynos4_clkset_aclk_top_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
-};
-
-static struct clksrc_clk exynos4_clk_aclk_200 = {
-        .clk    = {
-                .name           = "aclk_200",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_100 = {
-        .clk    = {
-                .name           = "aclk_100",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_aclk_160 = {
-        .clk    = {
-                .name           = "aclk_160",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
-};
-
-struct clksrc_clk exynos4_clk_aclk_133 = {
-        .clk    = {
-                .name           = "aclk_133",
-        },
-        .sources = &exynos4_clkset_aclk,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
-};
-
-static struct clk *exynos4_clkset_vpllsrc_list[] = {
-        [0] = &clk_fin_vpll,
-        [1] = &exynos4_clk_sclk_hdmi27m,
-};
-
-static struct clksrc_sources exynos4_clkset_vpllsrc = {
-        .sources        = exynos4_clkset_vpllsrc_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
-};
-
-static struct clksrc_clk exynos4_clk_vpllsrc = {
-        .clk    = {
-                .name           = "vpll_src",
-                .enable         = exynos4_clksrc_mask_top_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos4_clkset_vpllsrc,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_sclk_vpll_list[] = {
-        [0] = &exynos4_clk_vpllsrc.clk,
-        [1] = &clk_fout_vpll,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_vpll = {
-        .sources        = exynos4_clkset_sclk_vpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_vpll = {
-        .clk    = {
-                .name           = "sclk_vpll",
-        },
-        .sources = &exynos4_clkset_sclk_vpll,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
-};
-
-static struct clk exynos4_init_clocks_off[] = {
-        {
-                .name           = "timers",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1<<24),
-        }, {
-                .name           = "csis",
-                .devname        = "s5p-mipi-csis.0",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "csis",
-                .devname        = "s5p-mipi-csis.1",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "jpeg",
-                .id             = 0,
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.0",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.1",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.2",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.3",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "tsi",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.0",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.1",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.2",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "exynos4-sdhci.3",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "biu",
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "onenand",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "nfcon",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "dac",
-                .devname        = "s5p-sdo",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "mixer",
-                .devname        = "s5p-mixer",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "vp",
-                .devname        = "s5p-mixer",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "hdmi",
-                .devname        = "exynos4-hdmi",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "hdmiphy",
-                .devname        = "exynos4-hdmi",
-                .enable         = exynos4_clk_hdmiphy_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "dacphy",
-                .devname        = "s5p-sdo",
-                .enable         = exynos4_clk_dac_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "adc",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "tmu_apbif",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "keypad",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "rtc",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "watchdog",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "usbhost",
-                .enable         = exynos4_clk_ip_fsys_ctrl ,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "otg",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 23),
-        }, {
-                .name           = "slimbus",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 25),
-        }, {
-                .name           = "spdif",
-                .devname        = "samsung-spdif",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 26),
-        }, {
-                .name           = "ac97",
-                .devname        = "samsung-ac97",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 27),
-        }, {
-                .name           = "mfc",
-                .devname        = "s5p-mfc",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.0",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.1",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.2",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.3",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.4",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.5",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.6",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.7",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-hdmiphy-i2c",
-                .parent         = &exynos4_clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.0",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.1",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.2",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.3",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.4",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.5",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.6",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.7",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.8",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.10",
-                .enable         = exynos4_clk_ip_lcd0_ctrl,
-                .ctrlbit        = (1 << 4),
-        }
-};
-
-static struct clk exynos4_init_clocks_on[] = {
-        {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.3",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.4",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.5",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 5),
-        }
-};
-
-static struct clk exynos4_clk_pdma0 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.0",
-        .enable         = exynos4_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 0),
-};
-
-static struct clk exynos4_clk_pdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.1",
-        .enable         = exynos4_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 1),
-};
-
-static struct clk exynos4_clk_mdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.2",
-        .enable         = exynos4_clk_ip_image_ctrl,
-        .ctrlbit        = ((1 << 8) | (1 << 5) | (1 << 2)),
-};
-
-static struct clk exynos4_clk_fimd0 = {
-        .name           = "fimd",
-        .devname        = "exynos4-fb.0",
-        .enable         = exynos4_clk_ip_lcd0_ctrl,
-        .ctrlbit        = (1 << 0),
-};
-
-struct clk *exynos4_clkset_group_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &clk_xusbxti,
-        [2] = &exynos4_clk_sclk_hdmi27m,
-        [3] = &exynos4_clk_sclk_usbphy0,
-        [4] = &exynos4_clk_sclk_usbphy1,
-        [5] = &exynos4_clk_sclk_hdmiphy,
-        [6] = &exynos4_clk_mout_mpll.clk,
-        [7] = &exynos4_clk_mout_epll.clk,
-        [8] = &exynos4_clk_sclk_vpll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_group = {
-        .sources        = exynos4_clkset_group_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_group_list),
-};
-
-static struct clk *exynos4_clkset_mout_g2d0_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_mout_g2d0 = {
-        .sources        = exynos4_clkset_mout_g2d0_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
-};
-
-static struct clk *exynos4_clkset_mout_g2d1_list[] = {
-        [0] = &exynos4_clk_mout_epll.clk,
-        [1] = &exynos4_clk_sclk_vpll.clk,
-};
-
-struct clksrc_sources exynos4_clkset_mout_g2d1 = {
-        .sources        = exynos4_clkset_mout_g2d1_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
-};
-
-static struct clk *exynos4_clkset_mout_mfc0_list[] = {
-        [0] = &exynos4_clk_mout_mpll.clk,
-        [1] = &exynos4_clk_sclk_apll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
-        .sources        = exynos4_clkset_mout_mfc0_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
-};
-
-static struct clksrc_clk exynos4_clk_mout_mfc0 = {
-        .clk    = {
-                .name           = "mout_mfc0",
-        },
-        .sources = &exynos4_clkset_mout_mfc0,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_mout_mfc1_list[] = {
-        [0] = &exynos4_clk_mout_epll.clk,
-        [1] = &exynos4_clk_sclk_vpll.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
-        .sources        = exynos4_clkset_mout_mfc1_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
-};
-
-static struct clksrc_clk exynos4_clk_mout_mfc1 = {
-        .clk    = {
-                .name           = "mout_mfc1",
-        },
-        .sources = &exynos4_clkset_mout_mfc1,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_mout_mfc_list[] = {
-        [0] = &exynos4_clk_mout_mfc0.clk,
-        [1] = &exynos4_clk_mout_mfc1.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_mout_mfc = {
-        .sources        = exynos4_clkset_mout_mfc_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
-};
-
-static struct clk *exynos4_clkset_sclk_dac_list[] = {
-        [0] = &exynos4_clk_sclk_vpll.clk,
-        [1] = &exynos4_clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_dac = {
-        .sources        = exynos4_clkset_sclk_dac_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_dac = {
-        .clk            = {
-                .name           = "sclk_dac",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &exynos4_clkset_sclk_dac,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_pixel = {
-        .clk            = {
-                .name           = "sclk_pixel",
-                .parent         = &exynos4_clk_sclk_vpll.clk,
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
-};
-
-static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
-        [0] = &exynos4_clk_sclk_pixel.clk,
-        [1] = &exynos4_clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
-        .sources        = exynos4_clkset_sclk_hdmi_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_hdmi = {
-        .clk            = {
-                .name           = "sclk_hdmi",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos4_clkset_sclk_hdmi,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_sclk_mixer_list[] = {
-        [0] = &exynos4_clk_sclk_dac.clk,
-        [1] = &exynos4_clk_sclk_hdmi.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_sclk_mixer = {
-        .sources        = exynos4_clkset_sclk_mixer_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mixer = {
-        .clk    = {
-                .name           = "sclk_mixer",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &exynos4_clkset_sclk_mixer,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk *exynos4_sclk_tv[] = {
-        &exynos4_clk_sclk_dac,
-        &exynos4_clk_sclk_pixel,
-        &exynos4_clk_sclk_hdmi,
-        &exynos4_clk_sclk_mixer,
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc0 = {
-        .clk    = {
-                .name           = "dout_mmc0",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc1 = {
-        .clk    = {
-                .name           = "dout_mmc1",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc2 = {
-        .clk    = {
-                .name           = "dout_mmc2",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc3 = {
-        .clk    = {
-                .name           = "dout_mmc3",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_dout_mmc4 = {
-        .clk            = {
-                .name           = "dout_mmc4",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "sclk_pwm",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_csis",
-                        .devname        = "s5p-mipi-csis.0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_csis",
-                        .devname        = "s5p-mipi-csis.1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 28),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 20),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 4),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.2",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 8),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.3",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 12),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimd",
-                        .devname        = "exynos4-fb.0",
-                        .enable         = exynos4_clksrc_mask_lcd0_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mfc",
-                        .devname        = "s5p-mfc",
-                },
-                .sources = &exynos4_clkset_mout_mfc,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "ciu",
-                        .parent         = &exynos4_clk_dout_mmc4.clk,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
-        }
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart0 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.0",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart1 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.1",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart2 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.2",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_uart3 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.3",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.0",
-                .parent         = &exynos4_clk_dout_mmc0.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.1",
-                .parent         = &exynos4_clk_dout_mmc1.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.2",
-                .parent         = &exynos4_clk_dout_mmc2.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
-        .clk    = {
-                .name           = "sclk_mmc",
-                .devname        = "exynos4-sdhci.3",
-                .parent         = &exynos4_clk_dout_mmc3.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_mdout_spi0 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.0",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_mdout_spi1 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.1",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_mdout_spi2 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.2",
-        },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_spi0 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.0",
-                .parent         = &exynos4_clk_mdout_spi0.clk,
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit        = (1 << 16),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_spi1 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.1",
-                .parent         = &exynos4_clk_mdout_spi1.clk,
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit        = (1 << 20),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos4_clk_sclk_spi2 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.2",
-                .parent         = &exynos4_clk_mdout_spi2.clk,
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit        = (1 << 24),
-        },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
-};
-
-/* Clock initialization code */
-static struct clksrc_clk *exynos4_sysclks[] = {
-        &exynos4_clk_mout_apll,
-        &exynos4_clk_sclk_apll,
-        &exynos4_clk_mout_epll,
-        &exynos4_clk_mout_mpll,
-        &exynos4_clk_moutcore,
-        &exynos4_clk_coreclk,
-        &exynos4_clk_armclk,
-        &exynos4_clk_aclk_corem0,
-        &exynos4_clk_aclk_cores,
-        &exynos4_clk_aclk_corem1,
-        &exynos4_clk_periphclk,
-        &exynos4_clk_mout_corebus,
-        &exynos4_clk_sclk_dmc,
-        &exynos4_clk_aclk_cored,
-        &exynos4_clk_aclk_corep,
-        &exynos4_clk_aclk_acp,
-        &exynos4_clk_pclk_acp,
-        &exynos4_clk_vpllsrc,
-        &exynos4_clk_sclk_vpll,
-        &exynos4_clk_aclk_200,
-        &exynos4_clk_aclk_100,
-        &exynos4_clk_aclk_160,
-        &exynos4_clk_aclk_133,
-        &exynos4_clk_dout_mmc0,
-        &exynos4_clk_dout_mmc1,
-        &exynos4_clk_dout_mmc2,
-        &exynos4_clk_dout_mmc3,
-        &exynos4_clk_dout_mmc4,
-        &exynos4_clk_mout_mfc0,
-        &exynos4_clk_mout_mfc1,
-};
-
-static struct clk *exynos4_clk_cdev[] = {
-        &exynos4_clk_pdma0,
-        &exynos4_clk_pdma1,
-        &exynos4_clk_mdma1,
-        &exynos4_clk_fimd0,
-};
-
-static struct clksrc_clk *exynos4_clksrc_cdev[] = {
-        &exynos4_clk_sclk_uart0,
-        &exynos4_clk_sclk_uart1,
-        &exynos4_clk_sclk_uart2,
-        &exynos4_clk_sclk_uart3,
-        &exynos4_clk_sclk_mmc0,
-        &exynos4_clk_sclk_mmc1,
-        &exynos4_clk_sclk_mmc2,
-        &exynos4_clk_sclk_mmc3,
-        &exynos4_clk_sclk_spi0,
-        &exynos4_clk_sclk_spi1,
-        &exynos4_clk_sclk_spi2,
-        &exynos4_clk_mdout_spi0,
-        &exynos4_clk_mdout_spi1,
-        &exynos4_clk_mdout_spi2,
-};
-
-static struct clk_lookup exynos4_clk_lookup[] = {
-        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
-        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
-        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
-        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
-        CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
-        CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
-        CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
-        CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
-        CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
-        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
-        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
-        CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
-        CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
-        CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
-        CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
-};
-
-static int xtal_rate;
-
-static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
-{
-        if (soc_is_exynos4210())
-                return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
-                                        pll_4508);
-        else if (soc_is_exynos4212() || soc_is_exynos4412())
-                return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
-        else
-                return 0;
-}
-
-static struct clk_ops exynos4_fout_apll_ops = {
-        .get_rate = exynos4_fout_apll_get_rate,
-};
-
-static u32 exynos4_vpll_div[][8] = {
-        {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
-        { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
-};
-
-static unsigned long exynos4_vpll_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-
-static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int vpll_con0, vpll_con1 = 0;
-        unsigned int i;
-
-        /* Return if nothing changed */
-        if (clk->rate == rate)
-                return 0;
-
-        vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
-        vpll_con0 &= ~(0x1 << 27 |                                      \
-                        PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
-                        PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
-                        PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
-
-        vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
-        vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
-                        PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
-                        PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
-
-        for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
-                if (exynos4_vpll_div[i][0] == rate) {
-                        vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
-                        vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
-                        vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
-                        vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
-                        vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
-                        vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
-                        vpll_con0 |= exynos4_vpll_div[i][7] << 27;
-                        break;
-                }
-        }
-
-        if (i == ARRAY_SIZE(exynos4_vpll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
-                                __func__);
-                return -EINVAL;
-        }
-
-        __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
-        __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
-
-        /* Wait for VPLL lock */
-        while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
-                continue;
-
-        clk->rate = rate;
-        return 0;
-}
-
-static struct clk_ops exynos4_vpll_ops = {
-        .get_rate = exynos4_vpll_get_rate,
-        .set_rate = exynos4_vpll_set_rate,
-};
-
-void __init_or_cpufreq exynos4_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-        unsigned long apll = 0;
-        unsigned long mpll = 0;
-        unsigned long epll = 0;
-        unsigned long vpll = 0;
-        unsigned long vpllsrc;
-        unsigned long xtal;
-        unsigned long armclk;
-        unsigned long sclk_dmc;
-        unsigned long aclk_200;
-        unsigned long aclk_100;
-        unsigned long aclk_160;
-        unsigned long aclk_133;
-        unsigned int ptr;
-
-        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
-        xtal_clk = clk_get(NULL, "xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-
-        xtal = clk_get_rate(xtal_clk);
-
-        xtal_rate = xtal;
-
-        clk_put(xtal_clk);
-
-        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
-        if (soc_is_exynos4210()) {
-                apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
-                                        pll_4508);
-                mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
-                                        pll_4508);
-                epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
-                                        __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
-
-                vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
-                vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
-                                        __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
-        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-                apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
-                mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
-                epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
-                                        __raw_readl(EXYNOS4_EPLL_CON1));
-
-                vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
-                vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
-                                        __raw_readl(EXYNOS4_VPLL_CON1));
-        } else {
-                /* nothing */
-        }
-
-        clk_fout_apll.ops = &exynos4_fout_apll_ops;
-        clk_fout_mpll.rate = mpll;
-        clk_fout_epll.rate = epll;
-        clk_fout_vpll.ops = &exynos4_vpll_ops;
-        clk_fout_vpll.rate = vpll;
-
-        printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
-                        apll, mpll, epll, vpll);
-
-        armclk = clk_get_rate(&exynos4_clk_armclk.clk);
-        sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
-
-        aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
-        aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
-        aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
-        aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
-
-        printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
-                         "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
-                        armclk, sclk_dmc, aclk_200,
-                        aclk_100, aclk_160, aclk_133);
-
-        clk_f.rate = armclk;
-        clk_h.rate = sclk_dmc;
-        clk_p.rate = aclk_100;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
-                s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
-}
-
-static struct clk *exynos4_clks[] __initdata = {
-        &exynos4_clk_sclk_hdmi27m,
-        &exynos4_clk_sclk_hdmiphy,
-        &exynos4_clk_sclk_usbphy0,
-        &exynos4_clk_sclk_usbphy1,
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-        return 0;
-}
-
-static void exynos4_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-}
-
-#else
-#define exynos4_clock_suspend NULL
-#define exynos4_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos4_clock_syscore_ops = {
-        .suspend        = exynos4_clock_suspend,
-        .resume         = exynos4_clock_resume,
-};
-
-void __init exynos4_register_clocks(void)
-{
-        int ptr;
-
-        s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
-                s3c_register_clksrc(exynos4_sysclks[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
-                s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
-                s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
-
-        s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
-        s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
-
-        s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
-                s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
-
-        s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
-        s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
-        clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
-
-        register_syscore_ops(&exynos4_clock_syscore_ops);
-        s3c24xx_register_clock(&dummy_apb_pclk);
-
-        s3c_pwmclk_init();
-}
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
deleted file mode 100644
index bd12d5f8b63d..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Header file for exynos4 clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H __FILE__
-
-#include <linux/clk.h>
-
-extern struct clksrc_clk exynos4_clk_aclk_133;
-extern struct clksrc_clk exynos4_clk_mout_mpll;
-
-extern struct clksrc_sources exynos4_clkset_mout_corebus;
-extern struct clksrc_sources exynos4_clkset_group;
-
-extern struct clk *exynos4_clkset_aclk_top_list[];
-extern struct clk *exynos4_clkset_group_list[];
-
-extern struct clksrc_sources exynos4_clkset_mout_g2d0;
-extern struct clksrc_sources exynos4_clkset_mout_g2d1;
-
-extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
-
-#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
deleted file mode 100644
index 19af9f783c56..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4210 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-#include "clock-exynos4.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4210_clock_save[] = {
-        SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
-        SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
-        SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
-        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
-        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
-};
-#endif
-
-static struct clksrc_clk *sysclks[] = {
-        /* nothing here yet */
-};
-
-static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
-        .clk    = {
-                .name           = "mout_g2d0",
-        },
-        .sources = &exynos4_clkset_mout_g2d0,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
-};
-
-static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
-        .clk    = {
-                .name           = "mout_g2d1",
-        },
-        .sources = &exynos4_clkset_mout_g2d1,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
-};
-
-static struct clk *exynos4210_clkset_mout_g2d_list[] = {
-        [0] = &exynos4210_clk_mout_g2d0.clk,
-        [1] = &exynos4210_clk_mout_g2d1.clk,
-};
-
-static struct clksrc_sources exynos4210_clkset_mout_g2d = {
-        .sources        = exynos4210_clkset_mout_g2d_list,
-        .nr_sources     = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
-};
-
-static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
-}
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk            = {
-                        .name           = "sclk_sata",
-                        .id             = -1,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos4_clkset_mout_corebus,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimd",
-                        .devname        = "exynos4-fb.1",
-                        .enable         = exynos4_clksrc_mask_lcd1_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
-                .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_fimg2d",
-                },
-                .sources = &exynos4210_clkset_mout_g2d,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
-        },
-};
-
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "sataphy",
-                .id             = -1,
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "sata",
-                .id             = -1,
-                .parent         = &exynos4_clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "fimd",
-                .devname        = "exynos4-fb.1",
-                .enable         = exynos4_clk_ip_lcd1_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.9",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.11",
-                .enable         = exynos4_clk_ip_lcd1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "fimg2d",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4210_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
-
-        return 0;
-}
-
-static void exynos4210_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
-}
-
-#else
-#define exynos4210_clock_suspend NULL
-#define exynos4210_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos4210_clock_syscore_ops = {
-        .suspend        = exynos4210_clock_suspend,
-        .resume         = exynos4210_clock_resume,
-};
-
-void __init exynos4210_register_clocks(void)
-{
-        int ptr;
-
-        exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
-        exynos4_clk_mout_mpll.reg_src.shift = 8;
-        exynos4_clk_mout_mpll.reg_src.size = 1;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-                s3c_register_clksrc(sysclks[ptr], 1);
-
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-
-        register_syscore_ops(&exynos4210_clock_syscore_ops);
-}
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
deleted file mode 100644
index 529476f8ec71..000000000000
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4212 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-#include "clock-exynos4.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4212_clock_save[] = {
-        SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
-        SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
-        SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
-        SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
-};
-#endif
-
-static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
-}
-
-static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
-}
-
-static struct clk *clk_src_mpll_user_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos4_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources clk_src_mpll_user = {
-        .sources        = clk_src_mpll_user_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_mpll_user_list),
-};
-
-static struct clksrc_clk clk_mout_mpll_user = {
-        .clk = {
-                .name           = "mout_mpll_user",
-        },
-        .sources        = &clk_src_mpll_user,
-        .reg_src        = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
-};
-
-static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
-        .clk    = {
-                .name           = "mout_g2d0",
-        },
-        .sources = &exynos4_clkset_mout_g2d0,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
-};
-
-static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
-        .clk    = {
-                .name           = "mout_g2d1",
-        },
-        .sources = &exynos4_clkset_mout_g2d1,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
-};
-
-static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
-        [0] = &exynos4x12_clk_mout_g2d0.clk,
-        [1] = &exynos4x12_clk_mout_g2d1.clk,
-};
-
-static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
-        .sources        = exynos4x12_clkset_mout_g2d_list,
-        .nr_sources     = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
-};
-
-static struct clksrc_clk *sysclks[] = {
-        &clk_mout_mpll_user,
-};
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "sclk_fimg2d",
-                },
-                .sources = &exynos4x12_clkset_mout_g2d,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
-        },
-};
-
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.9",
-                .enable         = exynos4_clk_ip_dmc_ctrl,
-                .ctrlbit        = (1 << 24),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.12",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (7 << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.13",
-                .enable         = exynos4212_clk_ip_isp1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.14",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.15",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "flite",
-                .devname        = "exynos-fimc-lite.0",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "flite",
-                .devname        = "exynos-fimc-lite.1",
-                .enable         = exynos4212_clk_ip_isp0_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "fimg2d",
-                .enable         = exynos4_clk_ip_dmc_ctrl,
-                .ctrlbit        = (1 << 23),
-        },
-};
-
-#ifdef CONFIG_PM_SLEEP
-static int exynos4212_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
-
-        return 0;
-}
-
-static void exynos4212_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
-}
-
-#else
-#define exynos4212_clock_suspend NULL
-#define exynos4212_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos4212_clock_syscore_ops = {
-        .suspend        = exynos4212_clock_suspend,
-        .resume         = exynos4212_clock_resume,
-};
-
-void __init exynos4212_register_clocks(void)
-{
-        int ptr;
-
-        /* usbphy1 is removed */
-        exynos4_clkset_group_list[4] = NULL;
-
-        /* mout_mpll_user is used */
-        exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
-        exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
-
-        exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
-        exynos4_clk_mout_mpll.reg_src.shift = 12;
-        exynos4_clk_mout_mpll.reg_src.size = 1;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-                s3c_register_clksrc(sysclks[ptr], 1);
-
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-
-        register_syscore_ops(&exynos4212_clock_syscore_ops);
-}
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
deleted file mode 100644
index b0ea31fc9fb8..000000000000
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ /dev/null
@@ -1,1645 +0,0 @@
-/*
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Clock support for EXYNOS5 SoCs
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include "common.h"
-
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos5_clock_save[] = {
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
-        SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
-        SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
-        SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
-        SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
-        SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
-        SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
-        SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
-        SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
-        SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
-        SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
-        SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
-        SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
-        SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
-        SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
-        SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
-        SAVE_ITEM(EXYNOS5_EPLL_CON0),
-        SAVE_ITEM(EXYNOS5_EPLL_CON1),
-        SAVE_ITEM(EXYNOS5_EPLL_CON2),
-        SAVE_ITEM(EXYNOS5_VPLL_CON0),
-        SAVE_ITEM(EXYNOS5_VPLL_CON1),
-        SAVE_ITEM(EXYNOS5_VPLL_CON2),
-        SAVE_ITEM(EXYNOS5_PWR_CTRL1),
-        SAVE_ITEM(EXYNOS5_PWR_CTRL2),
-};
-#endif
-
-static struct clk exynos5_clk_sclk_dptxphy = {
-        .name           = "sclk_dptx",
-};
-
-static struct clk exynos5_clk_sclk_hdmi24m = {
-        .name           = "sclk_hdmi24m",
-        .rate           = 24000000,
-};
-
-static struct clk exynos5_clk_sclk_hdmi27m = {
-        .name           = "sclk_hdmi27m",
-        .rate           = 27000000,
-};
-
-static struct clk exynos5_clk_sclk_hdmiphy = {
-        .name           = "sclk_hdmiphy",
-};
-
-static struct clk exynos5_clk_sclk_usbphy = {
-        .name           = "sclk_usbphy",
-        .rate           = 48000000,
-};
-
-static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
-}
-
-static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
-}
-
-static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
-}
-
-static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
-}
-
-static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
-}
-
-static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
-}
-
-static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
-}
-
-static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
-}
-
-static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
-}
-
-static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
-}
-
-static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
-}
-
-static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
-}
-
-static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
-}
-
-static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
-}
-
-static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
-}
-
-static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
-}
-
-static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
-}
-
-static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
-}
-
-static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
-}
-
-/* Core list of CMU_CPU side */
-
-static struct clksrc_clk exynos5_clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-        },
-        .sources = &clk_src_apll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_apll = {
-        .clk    = {
-                .name           = "sclk_apll",
-                .parent         = &exynos5_clk_mout_apll.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
-        .clk    = {
-                .name           = "mout_bpll_fout",
-        },
-        .sources = &clk_src_bpll_fout,
-        .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_bpll_list[] = {
-        [0] = &clk_fin_bpll,
-        [1] = &exynos5_clk_mout_bpll_fout.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_bpll = {
-        .sources        = exynos5_clk_src_bpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_bpll = {
-        .clk    = {
-                .name           = "mout_bpll",
-        },
-        .sources = &exynos5_clk_src_bpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_bpll_user_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos5_clk_mout_bpll.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_bpll_user = {
-        .sources        = exynos5_clk_src_bpll_user_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_bpll_user = {
-        .clk    = {
-                .name           = "mout_bpll_user",
-        },
-        .sources = &exynos5_clk_src_bpll_user,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_cpll = {
-        .clk    = {
-                .name           = "mout_cpll",
-        },
-        .sources = &clk_src_cpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-        },
-        .sources = &clk_src_epll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
-        .clk    = {
-                .name           = "mout_mpll_fout",
-        },
-        .sources = &clk_src_mpll_fout,
-        .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_mpll_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos5_clk_mout_mpll_fout.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_mpll = {
-        .sources        = exynos5_clk_src_mpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_mpll = {
-        .clk = {
-                .name           = "mout_mpll",
-        },
-        .sources = &exynos5_clk_src_mpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
-};
-
-static struct clk *exynos_clkset_vpllsrc_list[] = {
-        [0] = &clk_fin_vpll,
-        [1] = &exynos5_clk_sclk_hdmi27m,
-};
-
-static struct clksrc_sources exynos5_clkset_vpllsrc = {
-        .sources        = exynos_clkset_vpllsrc_list,
-        .nr_sources     = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
-};
-
-static struct clksrc_clk exynos5_clk_vpllsrc = {
-        .clk    = {
-                .name           = "vpll_src",
-                .enable         = exynos5_clksrc_mask_top_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos5_clkset_vpllsrc,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_sclk_vpll_list[] = {
-        [0] = &exynos5_clk_vpllsrc.clk,
-        [1] = &clk_fout_vpll,
-};
-
-static struct clksrc_sources exynos5_clkset_sclk_vpll = {
-        .sources        = exynos5_clkset_sclk_vpll_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
-};
-
-static struct clksrc_clk exynos5_clk_sclk_vpll = {
-        .clk    = {
-                .name           = "sclk_vpll",
-        },
-        .sources = &exynos5_clkset_sclk_vpll,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_pixel = {
-        .clk    = {
-                .name           = "sclk_pixel",
-                .parent         = &exynos5_clk_sclk_vpll.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
-};
-
-static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
-        [0] = &exynos5_clk_sclk_pixel.clk,
-        [1] = &exynos5_clk_sclk_hdmiphy,
-};
-
-static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
-        .sources        = exynos5_clkset_sclk_hdmi_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
-};
-
-static struct clksrc_clk exynos5_clk_sclk_hdmi = {
-        .clk    = {
-                .name           = "sclk_hdmi",
-                .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
-                .ctrlbit        = (1 << 20),
-        },
-        .sources = &exynos5_clkset_sclk_hdmi,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
-};
-
-static struct clksrc_clk *exynos5_sclk_tv[] = {
-        &exynos5_clk_sclk_pixel,
-        &exynos5_clk_sclk_hdmi,
-};
-
-static struct clk *exynos5_clk_src_mpll_user_list[] = {
-        [0] = &clk_fin_mpll,
-        [1] = &exynos5_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_mpll_user = {
-        .sources        = exynos5_clk_src_mpll_user_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_mpll_user = {
-        .clk    = {
-                .name           = "mout_mpll_user",
-        },
-        .sources = &exynos5_clk_src_mpll_user,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_mout_cpu_list[] = {
-        [0] = &exynos5_clk_mout_apll.clk,
-        [1] = &exynos5_clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_mout_cpu = {
-        .sources        = exynos5_clkset_mout_cpu_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_cpu = {
-        .clk    = {
-                .name           = "mout_cpu",
-        },
-        .sources = &exynos5_clkset_mout_cpu,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_armclk = {
-        .clk    = {
-                .name           = "dout_armclk",
-                .parent         = &exynos5_clk_mout_cpu.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_arm2clk = {
-        .clk    = {
-                .name           = "dout_arm2clk",
-                .parent         = &exynos5_clk_dout_armclk.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
-};
-
-static struct clk exynos5_clk_armclk = {
-        .name           = "armclk",
-        .parent         = &exynos5_clk_dout_arm2clk.clk,
-};
-
-/* Core list of CMU_CDREX side */
-
-static struct clk *exynos5_clkset_cdrex_list[] = {
-        [0] = &exynos5_clk_mout_mpll.clk,
-        [1] = &exynos5_clk_mout_bpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_cdrex = {
-        .sources        = exynos5_clkset_cdrex_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_cdrex_list),
-};
-
-static struct clksrc_clk exynos5_clk_cdrex = {
-        .clk    = {
-                .name           = "clk_cdrex",
-        },
-        .sources = &exynos5_clkset_cdrex,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_acp = {
-        .clk    = {
-                .name           = "aclk_acp",
-                .parent         = &exynos5_clk_mout_mpll.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_pclk_acp = {
-        .clk    = {
-                .name           = "pclk_acp",
-                .parent         = &exynos5_clk_aclk_acp.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
-};
-
-/* Core list of CMU_TOP side */
-
-static struct clk *exynos5_clkset_aclk_top_list[] = {
-        [0] = &exynos5_clk_mout_mpll_user.clk,
-        [1] = &exynos5_clk_mout_bpll_user.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk = {
-        .sources        = exynos5_clkset_aclk_top_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
-};
-
-static struct clksrc_clk exynos5_clk_aclk_400 = {
-        .clk    = {
-                .name           = "aclk_400",
-        },
-        .sources = &exynos5_clkset_aclk,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
-};
-
-static struct clk *exynos5_clkset_aclk_333_166_list[] = {
-        [0] = &exynos5_clk_mout_cpll.clk,
-        [1] = &exynos5_clk_mout_mpll_user.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk_333_166 = {
-        .sources        = exynos5_clkset_aclk_333_166_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
-};
-
-static struct clksrc_clk exynos5_clk_aclk_333 = {
-        .clk    = {
-                .name           = "aclk_333",
-        },
-        .sources = &exynos5_clkset_aclk_333_166,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_166 = {
-        .clk    = {
-                .name           = "aclk_166",
-        },
-        .sources = &exynos5_clkset_aclk_333_166,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_266 = {
-        .clk    = {
-                .name           = "aclk_266",
-                .parent         = &exynos5_clk_mout_mpll_user.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_200 = {
-        .clk    = {
-                .name           = "aclk_200",
-        },
-        .sources = &exynos5_clkset_aclk,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_66_pre = {
-        .clk    = {
-                .name           = "aclk_66_pre",
-                .parent         = &exynos5_clk_mout_mpll_user.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_aclk_66 = {
-        .clk    = {
-                .name           = "aclk_66",
-                .parent         = &exynos5_clk_aclk_66_pre.clk,
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
-};
-
-static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
-        .clk    = {
-                .name           = "mout_aclk_300_gscl_mid",
-        },
-        .sources = &exynos5_clkset_aclk,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
-        [0] = &exynos5_clk_sclk_vpll.clk,
-        [1] = &exynos5_clk_mout_cpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
-        .sources        = exynos5_clkset_aclk_300_mid1_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
-        .clk    = {
-                .name           = "mout_aclk_300_gscl_mid1",
-        },
-        .sources = &exynos5_clkset_aclk_300_gscl_mid1,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
-};
-
-static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
-        [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
-        [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
-        .sources        = exynos5_clkset_aclk_300_gscl_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
-};
-
-static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
-        .clk    = {
-                .name           = "mout_aclk_300_gscl",
-        },
-        .sources = &exynos5_clkset_aclk_300_gscl,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
-};
-
-static struct clk *exynos5_clk_src_gscl_300_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
-};
-
-static struct clksrc_sources exynos5_clk_src_gscl_300 = {
-        .sources        = exynos5_clk_src_gscl_300_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
-};
-
-static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
-        .clk    = {
-                .name           = "aclk_300_gscl",
-        },
-        .sources = &exynos5_clk_src_gscl_300,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
-};
-
-static struct clk exynos5_init_clocks_off[] = {
-        {
-                .name           = "timers",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 24),
-        }, {
-                .name           = "tmu_apbif",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peris_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "rtc",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peris_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "watchdog",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peris_ctrl,
-                .ctrlbit        = (1 << 19),
-        }, {
-                .name           = "biu",        /* bus interface unit clock */
-                .devname        = "dw_mmc.0",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "biu",
-                .devname        = "dw_mmc.1",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "biu",
-                .devname        = "dw_mmc.2",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "biu",
-                .devname        = "dw_mmc.3",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "sata",
-                .devname        = "exynos5-sata",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "sata-phy",
-                .devname        = "exynos5-sata-phy",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 24),
-        }, {
-                .name           = "i2c",
-                .devname        = "exynos5-sata-phy-i2c",
-                .parent         = &exynos5_clk_aclk_200.clk,
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 25),
-        }, {
-                .name           = "mfc",
-                .devname        = "s5p-mfc-v6",
-                .enable         = exynos5_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "hdmi",
-                .devname        = "exynos5-hdmi",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "hdmiphy",
-                .devname        = "exynos5-hdmi",
-                .enable         = exynos5_clk_hdmiphy_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "mixer",
-                .devname        = "exynos5-mixer",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "dp",
-                .devname        = "exynos-dp",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "jpeg",
-                .enable         = exynos5_clk_ip_gen_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "dsim0",
-                .enable         = exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.1",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.2",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.1",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "pcm",
-                .devname        = "samsung-pcm.2",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 23),
-        }, {
-                .name           = "spdif",
-                .devname        = "samsung-spdif",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 26),
-        }, {
-                .name           = "ac97",
-                .devname        = "samsung-ac97",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 27),
-        }, {
-                .name           = "usbhost",
-                .enable         = exynos5_clk_ip_fsys_ctrl ,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "usbotg",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "nfcon",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "iop",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = ((1 << 30) | (1 << 26) | (1 << 23)),
-        }, {
-                .name           = "core_iop",
-                .enable         = exynos5_clk_ip_core_ctrl,
-                .ctrlbit        = ((1 << 21) | (1 << 3)),
-        }, {
-                .name           = "mcu_iop",
-                .enable         = exynos5_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.0",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.1",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.2",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.3",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.4",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.5",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.6",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.7",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-hdmiphy-i2c",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.0",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.1",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "spi",
-                .devname        = "exynos4210-spi.2",
-                .parent         = &exynos5_clk_aclk_66.clk,
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.0",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.1",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.2",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "gscl",
-                .devname        = "exynos-gsc.3",
-                .enable         = exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.1",
-                .enable         = &exynos5_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.0",
-                .enable         = &exynos5_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.2",
-                .enable         = &exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 9)
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.3",
-                .enable         = &exynos5_clk_ip_gen_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.4",
-                .enable         = &exynos5_clk_ip_gen_ctrl,
-                .ctrlbit        = (1 << 6)
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.5",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.6",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.7",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.8",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.9",
-                .enable         = &exynos5_clk_ip_isp0_ctrl,
-                .ctrlbit        = (0x3F << 8),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.10",
-                .enable         = &exynos5_clk_ip_isp1_ctrl,
-                .ctrlbit        = (0xF << 4),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.11",
-                .enable         = &exynos5_clk_ip_disp1_ctrl,
-                .ctrlbit        = (1 << 8)
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.12",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.13",
-                .enable         = &exynos5_clk_ip_gscl_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "sysmmu",
-                .devname        = "exynos-sysmmu.14",
-                .enable         = &exynos5_clk_ip_acp_ctrl,
-                .ctrlbit        = (1 << 7)
-        }
-};
-
-static struct clk exynos5_init_clocks_on[] = {
-        {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.0",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.1",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.2",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.3",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.4",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.5",
-                .enable         = exynos5_clk_ip_peric_ctrl,
-                .ctrlbit        = (1 << 5),
-        }
-};
-
-static struct clk exynos5_clk_pdma0 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.0",
-        .enable         = exynos5_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 1),
-};
-
-static struct clk exynos5_clk_pdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.1",
-        .enable         = exynos5_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 2),
-};
-
-static struct clk exynos5_clk_mdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.2",
-        .enable         = exynos5_clk_ip_gen_ctrl,
-        .ctrlbit        = (1 << 4),
-};
-
-static struct clk exynos5_clk_fimd1 = {
-        .name           = "fimd",
-        .devname        = "exynos5-fb.1",
-        .enable         = exynos5_clk_ip_disp1_ctrl,
-        .ctrlbit        = (1 << 0),
-};
-
-static struct clk *exynos5_clkset_group_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = NULL,
-        [2] = &exynos5_clk_sclk_hdmi24m,
-        [3] = &exynos5_clk_sclk_dptxphy,
-        [4] = &exynos5_clk_sclk_usbphy,
-        [5] = &exynos5_clk_sclk_hdmiphy,
-        [6] = &exynos5_clk_mout_mpll_user.clk,
-        [7] = &exynos5_clk_mout_epll.clk,
-        [8] = &exynos5_clk_sclk_vpll.clk,
-        [9] = &exynos5_clk_mout_cpll.clk,
-};
-
-static struct clksrc_sources exynos5_clkset_group = {
-        .sources        = exynos5_clkset_group_list,
-        .nr_sources     = ARRAY_SIZE(exynos5_clkset_group_list),
-};
-
-/* Possible clock sources for aclk_266_gscl_sub Mux */
-static struct clk *clk_src_gscl_266_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &exynos5_clk_aclk_266.clk,
-};
-
-static struct clksrc_sources clk_src_gscl_266 = {
-        .sources        = clk_src_gscl_266_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_gscl_266_list),
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc0 = {
-        .clk            = {
-                .name           = "dout_mmc0",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc1 = {
-        .clk            = {
-                .name           = "dout_mmc1",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc2 = {
-        .clk            = {
-                .name           = "dout_mmc2",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc3 = {
-        .clk            = {
-                .name           = "dout_mmc3",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_dout_mmc4 = {
-        .clk            = {
-                .name           = "dout_mmc4",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart0 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.0",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart1 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.1",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart2 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.2",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_uart3 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.3",
-                .enable         = exynos5_clksrc_mask_peric0_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
-        .clk    = {
-                .name           = "ciu",        /* card interface unit clock */
-                .devname        = "dw_mmc.0",
-                .parent         = &exynos5_clk_dout_mmc0.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
-        .clk    = {
-                .name           = "ciu",
-                .devname        = "dw_mmc.1",
-                .parent         = &exynos5_clk_dout_mmc1.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
-        .clk    = {
-                .name           = "ciu",
-                .devname        = "dw_mmc.2",
-                .parent         = &exynos5_clk_dout_mmc2.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
-        .clk    = {
-                .name           = "ciu",
-                .devname        = "dw_mmc.3",
-                .parent         = &exynos5_clk_dout_mmc3.clk,
-                .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_mdout_spi0 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.0",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_mdout_spi1 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.1",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_mdout_spi2 = {
-        .clk    = {
-                .name           = "mdout_spi",
-                .devname        = "exynos4210-spi.2",
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_spi0 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.0",
-                .parent         = &exynos5_clk_mdout_spi0.clk,
-                .enable         = exynos5_clksrc_mask_peric1_ctrl,
-                .ctrlbit        = (1 << 16),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_spi1 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.1",
-                .parent         = &exynos5_clk_mdout_spi1.clk,
-                .enable         = exynos5_clksrc_mask_peric1_ctrl,
-                .ctrlbit        = (1 << 20),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_spi2 = {
-        .clk    = {
-                .name           = "sclk_spi",
-                .devname        = "exynos4210-spi.2",
-                .parent         = &exynos5_clk_mdout_spi2.clk,
-                .enable         = exynos5_clksrc_mask_peric1_ctrl,
-                .ctrlbit        = (1 << 24),
-        },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
-};
-
-static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
-        .clk    = {
-                .name           = "sclk_fimd",
-                .devname        = "exynos5-fb.1",
-                .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &exynos5_clkset_group,
-        .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
-        .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
-};
-
-static struct clksrc_clk exynos5_clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "aclk_266_gscl",
-                },
-                .sources = &clk_src_gscl_266,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_g3d",
-                        .devname        = "mali-t604.0",
-                        .enable         = exynos5_clk_block_ctrl,
-                        .ctrlbit        = (1 << 1),
-                },
-                .sources = &exynos5_clkset_aclk,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_sata",
-                        .devname        = "exynos5-sata",
-                        .enable         = exynos5_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos5_clkset_aclk,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_gscl_wrap",
-                        .devname        = "s5p-mipi-csis.0",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_gscl_wrap",
-                        .devname        = "s5p-mipi-csis.1",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 28),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam0",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_cam1",
-                        .enable         = exynos5_clksrc_mask_gscl_ctrl,
-                        .ctrlbit        = (1 << 20),
-                },
-                .sources = &exynos5_clkset_group,
-                .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_jpeg",
-                        .parent         = &exynos5_clk_mout_cpll.clk,
-                },
-                .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
-        },
-};
-
-/* Clock initialization code */
-static struct clksrc_clk *exynos5_sysclks[] = {
-        &exynos5_clk_mout_apll,
-        &exynos5_clk_sclk_apll,
-        &exynos5_clk_mout_bpll,
-        &exynos5_clk_mout_bpll_fout,
-        &exynos5_clk_mout_bpll_user,
-        &exynos5_clk_mout_cpll,
-        &exynos5_clk_mout_epll,
-        &exynos5_clk_mout_mpll,
-        &exynos5_clk_mout_mpll_fout,
-        &exynos5_clk_mout_mpll_user,
-        &exynos5_clk_vpllsrc,
-        &exynos5_clk_sclk_vpll,
-        &exynos5_clk_mout_cpu,
-        &exynos5_clk_dout_armclk,
-        &exynos5_clk_dout_arm2clk,
-        &exynos5_clk_cdrex,
-        &exynos5_clk_aclk_400,
-        &exynos5_clk_aclk_333,
-        &exynos5_clk_aclk_266,
-        &exynos5_clk_aclk_200,
-        &exynos5_clk_aclk_166,
-        &exynos5_clk_aclk_300_gscl,
-        &exynos5_clk_mout_aclk_300_gscl,
-        &exynos5_clk_mout_aclk_300_gscl_mid,
-        &exynos5_clk_mout_aclk_300_gscl_mid1,
-        &exynos5_clk_aclk_66_pre,
-        &exynos5_clk_aclk_66,
-        &exynos5_clk_dout_mmc0,
-        &exynos5_clk_dout_mmc1,
-        &exynos5_clk_dout_mmc2,
-        &exynos5_clk_dout_mmc3,
-        &exynos5_clk_dout_mmc4,
-        &exynos5_clk_aclk_acp,
-        &exynos5_clk_pclk_acp,
-        &exynos5_clk_sclk_spi0,
-        &exynos5_clk_sclk_spi1,
-        &exynos5_clk_sclk_spi2,
-        &exynos5_clk_mdout_spi0,
-        &exynos5_clk_mdout_spi1,
-        &exynos5_clk_mdout_spi2,
-        &exynos5_clk_sclk_fimd1,
-};
-
-static struct clk *exynos5_clk_cdev[] = {
-        &exynos5_clk_pdma0,
-        &exynos5_clk_pdma1,
-        &exynos5_clk_mdma1,
-        &exynos5_clk_fimd1,
-};
-
-static struct clksrc_clk *exynos5_clksrc_cdev[] = {
-        &exynos5_clk_sclk_uart0,
-        &exynos5_clk_sclk_uart1,
-        &exynos5_clk_sclk_uart2,
-        &exynos5_clk_sclk_uart3,
-        &exynos5_clk_sclk_mmc0,
-        &exynos5_clk_sclk_mmc1,
-        &exynos5_clk_sclk_mmc2,
-        &exynos5_clk_sclk_mmc3,
-};
-
-static struct clk_lookup exynos5_clk_lookup[] = {
-        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
-        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
-        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
-        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
-        CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
-        CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
-        CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
-        CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
-        CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
-        CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
-        CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
-        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
-        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
-        CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
-        CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
-};
-
-static unsigned long exynos5_epll_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-
-static struct clk *exynos5_clks[] __initdata = {
-        &exynos5_clk_sclk_hdmi27m,
-        &exynos5_clk_sclk_hdmiphy,
-        &clk_fout_bpll,
-        &clk_fout_bpll_div2,
-        &clk_fout_cpll,
-        &clk_fout_mpll_div2,
-        &exynos5_clk_armclk,
-};
-
-static u32 epll_div[][6] = {
-        { 192000000, 0, 48, 3, 1, 0 },
-        { 180000000, 0, 45, 3, 1, 0 },
-        {  73728000, 1, 73, 3, 3, 47710 },
-        {  67737600, 1, 90, 4, 3, 20762 },
-        {  49152000, 0, 49, 3, 3, 9961 },
-        {  45158400, 0, 45, 3, 3, 10381 },
-        { 180633600, 0, 45, 3, 1, 10381 },
-};
-
-static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int epll_con, epll_con_k;
-        unsigned int i;
-        unsigned int tmp;
-        unsigned int epll_rate;
-        unsigned int locktime;
-        unsigned int lockcnt;
-
-        /* Return if nothing changed */
-        if (clk->rate == rate)
-                return 0;
-
-        if (clk->parent)
-                epll_rate = clk_get_rate(clk->parent);
-        else
-                epll_rate = clk_ext_xtal_mux.rate;
-
-        if (epll_rate != 24000000) {
-                pr_err("Invalid Clock : recommended clock is 24MHz.\n");
-                return -EINVAL;
-        }
-
-        epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
-        epll_con &= ~(0x1 << 27 | \
-                        PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
-                        PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
-                        PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
-
-        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
-                if (epll_div[i][0] == rate) {
-                        epll_con_k = epll_div[i][5] << 0;
-                        epll_con |= epll_div[i][1] << 27;
-                        epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
-                        epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
-                        epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
-                        break;
-                }
-        }
-
-        if (i == ARRAY_SIZE(epll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
-                                __func__);
-                return -EINVAL;
-        }
-
-        epll_rate /= 1000000;
-
-        /* 3000 max_cycls : specification data */
-        locktime = 3000 / epll_rate * epll_div[i][3];
-        lockcnt = locktime * 10000 / (10000 / epll_rate);
-
-        __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
-
-        __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
-        __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
-
-        do {
-                tmp = __raw_readl(EXYNOS5_EPLL_CON0);
-        } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
-
-        clk->rate = rate;
-
-        return 0;
-}
-
-static struct clk_ops exynos5_epll_ops = {
-        .get_rate = exynos5_epll_get_rate,
-        .set_rate = exynos5_epll_set_rate,
-};
-
-static int xtal_rate;
-
-static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
-{
-        return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
-}
-
-static struct clk_ops exynos5_fout_apll_ops = {
-        .get_rate = exynos5_fout_apll_get_rate,
-};
-
-#ifdef CONFIG_PM
-static int exynos5_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
-
-        return 0;
-}
-
-static void exynos5_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
-}
-#else
-#define exynos5_clock_suspend NULL
-#define exynos5_clock_resume NULL
-#endif
-
-static struct syscore_ops exynos5_clock_syscore_ops = {
-        .suspend        = exynos5_clock_suspend,
-        .resume         = exynos5_clock_resume,
-};
-
-void __init_or_cpufreq exynos5_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-        unsigned long apll;
-        unsigned long bpll;
-        unsigned long cpll;
-        unsigned long mpll;
-        unsigned long epll;
-        unsigned long vpll;
-        unsigned long vpllsrc;
-        unsigned long xtal;
-        unsigned long armclk;
-        unsigned long mout_cdrex;
-        unsigned long aclk_400;
-        unsigned long aclk_333;
-        unsigned long aclk_266;
-        unsigned long aclk_200;
-        unsigned long aclk_166;
-        unsigned long aclk_66;
-        unsigned int ptr;
-
-        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
-        xtal_clk = clk_get(NULL, "xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-
-        xtal = clk_get_rate(xtal_clk);
-
-        xtal_rate = xtal;
-
-        clk_put(xtal_clk);
-
-        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
-        apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
-        bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
-        cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
-        mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
-        epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
-                        __raw_readl(EXYNOS5_EPLL_CON1));
-
-        vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
-        vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
-                        __raw_readl(EXYNOS5_VPLL_CON1));
-
-        clk_fout_apll.ops = &exynos5_fout_apll_ops;
-        clk_fout_bpll.rate = bpll;
-        clk_fout_bpll_div2.rate = bpll >> 1;
-        clk_fout_cpll.rate = cpll;
-        clk_fout_mpll.rate = mpll;
-        clk_fout_mpll_div2.rate = mpll >> 1;
-        clk_fout_epll.rate = epll;
-        clk_fout_vpll.rate = vpll;
-
-        printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
-                        "M=%ld, E=%ld V=%ld",
-                        apll, bpll, cpll, mpll, epll, vpll);
-
-        armclk = clk_get_rate(&exynos5_clk_armclk);
-        mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
-
-        aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
-        aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
-        aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
-        aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
-        aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
-        aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
-
-        printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
-                        "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
-                        "ACLK166=%ld, ACLK66=%ld\n",
-                        armclk, mout_cdrex, aclk_400,
-                        aclk_333, aclk_266, aclk_200,
-                        aclk_166, aclk_66);
-
-
-        clk_fout_epll.ops = &exynos5_epll_ops;
-
-        if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
-                printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
-                                clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
-
-        clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
-        clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
-
-        clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
-        clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
-                s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
-}
-
-void __init exynos5_register_clocks(void)
-{
-        int ptr;
-
-        s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
-                s3c_register_clksrc(exynos5_sysclks[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
-                s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
-                s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
-
-        s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
-        s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
-
-        s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
-        for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
-                s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
-
-        s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
-        s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
-        clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
-
-        register_syscore_ops(&exynos5_clock_syscore_ops);
-        s3c_pwmclk_init();
-}
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index d63d399c7bae..46089fe24705 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -23,9 +23,11 @@
 #include <linux/of_irq.h>
 #include <linux/export.h>
 #include <linux/irqdomain.h>
-#include <linux/irqchip.h>
 #include <linux/of_address.h>
+#include <linux/clocksource.h>
+#include <linux/clk-provider.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/irqchip/chained_irq.h>
 
 #include <asm/proc-fns.h>
 #include <asm/exception.h>
@@ -37,9 +39,9 @@
 #include <mach/regs-irq.h>
 #include <mach/regs-pmu.h>
 #include <mach/regs-gpio.h>
+#include <mach/irqs.h>
 
 #include <plat/cpu.h>
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
 #include <plat/sdhci.h>
@@ -65,17 +67,16 @@ static const char name_exynos5440[] = "EXYNOS5440";
 static void exynos4_map_io(void);
 static void exynos5_map_io(void);
 static void exynos5440_map_io(void);
-static void exynos4_init_clocks(int xtal);
-static void exynos5_init_clocks(int xtal);
 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
 
+unsigned long xxti_f = 0, xusbxti_f = 0;
+
 static struct cpu_table cpu_ids[] __initdata = {
         {
                 .idcode         = EXYNOS4210_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_clocks    = exynos4_init_clocks,
                 .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4210,
@@ -83,7 +84,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = EXYNOS4212_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_clocks    = exynos4_init_clocks,
                 .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4212,
@@ -91,7 +91,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = EXYNOS4412_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_clocks    = exynos4_init_clocks,
                 .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4412,
@@ -99,7 +98,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .idcode         = EXYNOS5250_SOC_ID,
                 .idmask         = EXYNOS5_SOC_MASK,
                 .map_io         = exynos5_map_io,
-                .init_clocks    = exynos5_init_clocks,
                 .init           = exynos_init,
                 .name           = name_exynos5250,
         }, {
@@ -235,6 +233,33 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
         },
 };
 
+static struct map_desc exynos4210_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
+                .pfn            = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+
+static struct map_desc exynos4x12_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
+                .pfn            = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+
+static struct map_desc exynos5250_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
+                .pfn            = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+
 static struct map_desc exynos5_iodesc[] __initdata = {
         {
                 .virtual        = (unsigned long)S3C_VA_SYS,
@@ -257,11 +282,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
-                .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
                 .length         = SZ_4K,
@@ -368,6 +388,11 @@ static void __init exynos4_map_io(void)
         else
                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 
+        if (soc_is_exynos4210())
+                iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
+        if (soc_is_exynos4212() || soc_is_exynos4412())
+                iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
+
         /* initialize device information early */
         exynos4_default_sdhci0();
         exynos4_default_sdhci1();
@@ -400,22 +425,9 @@ static void __init exynos4_map_io(void)
 static void __init exynos5_map_io(void)
 {
         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
-}
-
-static void __init exynos4_init_clocks(int xtal)
-{
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-
-        if (soc_is_exynos4210())
-                exynos4210_register_clocks();
-        else if (soc_is_exynos4212() || soc_is_exynos4412())
-                exynos4212_register_clocks();
 
-        exynos4_register_clocks();
-        exynos4_setup_clocks();
+        if (soc_is_exynos5250())
+                iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
 }
 
 static void __init exynos5440_map_io(void)
@@ -423,22 +435,21 @@ static void __init exynos5440_map_io(void)
         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 }
 
-static void __init exynos5_init_clocks(int xtal)
+void __init exynos_init_time(void)
 {
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-
-        /* EXYNOS5440 can support only common clock framework */
-
-        if (soc_is_exynos5440())
-                return;
-
-#ifdef CONFIG_SOC_EXYNOS5250
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-
-        exynos5_register_clocks();
-        exynos5_setup_clocks();
+        if (of_have_populated_dt()) {
+#ifdef CONFIG_OF
+                of_clk_init(NULL);
+                clocksource_of_init();
+#endif
+        } else {
+                /* todo: remove after migrating legacy E4 platforms to dt */
+#ifdef CONFIG_ARCH_EXYNOS4
+                exynos4_clk_init(NULL);
+                exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
 #endif
+                mct_init();
+        }
 }
 
 void __init exynos4_init_irq(void)
@@ -463,6 +474,8 @@ void __init exynos4_init_irq(void)
          * uses GIC instead of VIC.
          */
         s5p_init_irq(NULL, 0);
+
+        gic_arch_extn.irq_set_wake = s3c_irq_wake;
 }
 
 void __init exynos5_init_irq(void)
@@ -822,6 +835,7 @@ static int __init exynos_init_irq_eint(void)
         static const struct of_device_id exynos_pinctrl_ids[] = {
                 { .compatible = "samsung,exynos4210-pinctrl", },
                 { .compatible = "samsung,exynos4x12-pinctrl", },
+                { .compatible = "samsung,exynos5250-pinctrl", },
         };
         struct device_node *pctrl_np, *wkup_np;
         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
@@ -875,3 +889,30 @@ static int __init exynos_init_irq_eint(void)
         return 0;
 }
 arch_initcall(exynos_init_irq_eint);
+
+static struct resource exynos4_pmu_resource[] = {
+        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
+        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
+#if defined(CONFIG_SOC_EXYNOS4412)
+        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
+        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
+#endif
+};
+
+static struct platform_device exynos4_device_pmu = {
+        .name           = "arm-pmu",
+        .num_resources  = ARRAY_SIZE(exynos4_pmu_resource),
+        .resource       = exynos4_pmu_resource,
+};
+
+static int __init exynos_armpmu_init(void)
+{
+        if (!of_have_populated_dt()) {
+                if (soc_is_exynos4210() || soc_is_exynos4212())
+                        exynos4_device_pmu.num_resources = 2;
+                platform_device_register(&exynos4_device_pmu);
+        }
+
+        return 0;
+}
+arch_initcall(exynos_armpmu_init);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 9339bb8954be..b17448c1a164 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -12,7 +12,11 @@
 #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
 #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
 
-extern void exynos4_timer_init(void);
+#include <linux/of.h>
+
+extern void mct_init(void);
+void exynos_init_time(void);
+extern unsigned long xxti_f, xusbxti_f;
 
 struct map_desc;
 void exynos_init_io(struct map_desc *mach_desc, int size);
@@ -22,6 +26,12 @@ void exynos4_restart(char mode, const char *cmd);
 void exynos5_restart(char mode, const char *cmd);
 void exynos_init_late(void);
 
+/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
+void exynos4_clk_init(struct device_node *np);
+void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
+
+void exynos_firmware_init(void);
+
 #ifdef CONFIG_PM_GENERIC_DOMAINS
 int exynos_pm_late_initcall(void);
 #else
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index fcfe0251aa3e..17a18ff3d71e 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -41,24 +41,24 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev,
                                 struct cpuidle_driver *drv,
                                 int index);
 
-static struct cpuidle_state exynos4_cpuidle_set[] __initdata = {
-        [0] = ARM_CPUIDLE_WFI_STATE,
-        [1] = {
-                .enter                  = exynos4_enter_lowpower,
-                .exit_latency           = 300,
-                .target_residency       = 100000,
-                .flags                  = CPUIDLE_FLAG_TIME_VALID,
-                .name                   = "C1",
-                .desc                   = "ARM power down",
-        },
-};
-
 static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
 
 static struct cpuidle_driver exynos4_idle_driver = {
         .name                   = "exynos4_idle",
         .owner                  = THIS_MODULE,
-        .en_core_tk_irqen       = 1,
+        .states = {
+                [0] = ARM_CPUIDLE_WFI_STATE,
+                [1] = {
+                        .enter                  = exynos4_enter_lowpower,
+                        .exit_latency           = 300,
+                        .target_residency       = 100000,
+                        .flags                  = CPUIDLE_FLAG_TIME_VALID,
+                        .name                   = "C1",
+                        .desc                   = "ARM power down",
+                },
+        },
+        .state_count = 2,
+        .safe_state_index = 0,
 };
 
 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
@@ -193,37 +193,30 @@ static void __init exynos5_core_down_clk(void)
 
 static int __init exynos4_init_cpuidle(void)
 {
-        int i, max_cpuidle_state, cpu_id;
+        int cpu_id, ret;
         struct cpuidle_device *device;
-        struct cpuidle_driver *drv = &exynos4_idle_driver;
 
         if (soc_is_exynos5250())
                 exynos5_core_down_clk();
 
-        /* Setup cpuidle driver */
-        drv->state_count = (sizeof(exynos4_cpuidle_set) /
-                                       sizeof(struct cpuidle_state));
-        max_cpuidle_state = drv->state_count;
-        for (i = 0; i < max_cpuidle_state; i++) {
-                memcpy(&drv->states[i], &exynos4_cpuidle_set[i],
-                                sizeof(struct cpuidle_state));
+        ret = cpuidle_register_driver(&exynos4_idle_driver);
+        if (ret) {
+                printk(KERN_ERR "CPUidle failed to register driver\n");
+                return ret;
         }
-        drv->safe_state_index = 0;
-        cpuidle_register_driver(&exynos4_idle_driver);
 
-        for_each_cpu(cpu_id, cpu_online_mask) {
+        for_each_online_cpu(cpu_id) {
                 device = &per_cpu(exynos4_cpuidle_device, cpu_id);
                 device->cpu = cpu_id;
 
-                if (cpu_id == 0)
-                        device->state_count = (sizeof(exynos4_cpuidle_set) /
-                                               sizeof(struct cpuidle_state));
-                else
-                        device->state_count = 1;        /* Support IDLE only */
+                /* Support IDLE only */
+                if (cpu_id != 0)
+                        device->state_count = 1;
 
-                if (cpuidle_register_device(device)) {
-                        printk(KERN_ERR "CPUidle register device failed\n,");
-                        return -EIO;
+                ret = cpuidle_register_device(device);
+                if (ret) {
+                        printk(KERN_ERR "CPUidle register device failed\n");
+                        return ret;
                 }
         }
 
diff --git a/arch/arm/mach-exynos/dev-ohci.c b/arch/arm/mach-exynos/dev-ohci.c
index 4244d02dafbd..d5bc129e6bb7 100644
--- a/arch/arm/mach-exynos/dev-ohci.c
+++ b/arch/arm/mach-exynos/dev-ohci.c
@@ -12,7 +12,7 @@
 
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
-#include <linux/platform_data/usb-exynos.h>
+#include <linux/platform_data/usb-ohci-exynos.h>
 
 #include <mach/irqs.h>
 #include <mach/map.h>
diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c
index 7c42f4b7c8be..c48aff02c786 100644
--- a/arch/arm/mach-exynos/dev-uart.c
+++ b/arch/arm/mach-exynos/dev-uart.c
@@ -20,6 +20,7 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
 #include <mach/map.h>
+#include <mach/irqs.h>
 
 #include <plat/devs.h>
 
diff --git a/arch/arm/mach-exynos/exynos-smc.S b/arch/arm/mach-exynos/exynos-smc.S
new file mode 100644
index 000000000000..2e27aa3813fd
--- /dev/null
+++ b/arch/arm/mach-exynos/exynos-smc.S
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics.
+ *
+ * Copied from omap-smc.S Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+
+/*
+ * Function signature: void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3)
+ */
+
+ENTRY(exynos_smc)
+        stmfd   sp!, {r4-r11, lr}
+        dsb
+        smc     #0
+        ldmfd   sp!, {r4-r11, pc}
+ENDPROC(exynos_smc)
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
new file mode 100644
index 000000000000..ed11f100d479
--- /dev/null
+++ b/arch/arm/mach-exynos/firmware.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics.
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Tomasz Figa <t.figa@samsung.com>
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <asm/firmware.h>
+
+#include <mach/map.h>
+
+#include "smc.h"
+
+static int exynos_do_idle(void)
+{
+        exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
+        return 0;
+}
+
+static int exynos_cpu_boot(int cpu)
+{
+        exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
+        return 0;
+}
+
+static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
+{
+        void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c + 4*cpu;
+
+        __raw_writel(boot_addr, boot_reg);
+        return 0;
+}
+
+static const struct firmware_ops exynos_firmware_ops = {
+        .do_idle                = exynos_do_idle,
+        .set_cpu_boot_addr      = exynos_set_cpu_boot_addr,
+        .cpu_boot               = exynos_cpu_boot,
+};
+
+void __init exynos_firmware_init(void)
+{
+        if (of_have_populated_dt()) {
+                struct device_node *nd;
+                const __be32 *addr;
+
+                nd = of_find_compatible_node(NULL, NULL,
+                                                "samsung,secure-firmware");
+                if (!nd)
+                        return;
+
+                addr = of_get_address(nd, 0, NULL, NULL);
+                if (!addr) {
+                        pr_err("%s: No address specified.\n", __func__);
+                        return;
+                }
+        }
+
+        pr_info("Running under secure firmware.\n");
+
+        register_firmware_ops(&exynos_firmware_ops);
+}
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index c3f825b27947..af90cfa2f826 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -28,7 +28,6 @@ static inline void cpu_enter_lowpower_a9(void)
 {
         unsigned int v;
 
-        flush_cache_all();
         asm volatile(
         "       mcr     p15, 0, %1, c7, c5, 0\n"
         "       mcr     p15, 0, %1, c7, c10, 4\n"
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 1f4dc35cd4b9..c72f59d91fce 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -30,8 +30,6 @@
 
 /* For EXYNOS4 and EXYNOS5 */
 
-#define EXYNOS_IRQ_MCT_LOCALTIMER       IRQ_PPI(12)
-
 #define EXYNOS_IRQ_EINT16_31            IRQ_SPI(32)
 
 /* For EXYNOS4 SoCs */
@@ -128,7 +126,7 @@
 #define EXYNOS4_IRQ_ADC1                IRQ_SPI(107)
 #define EXYNOS4_IRQ_PEN1                IRQ_SPI(108)
 #define EXYNOS4_IRQ_KEYPAD              IRQ_SPI(109)
-#define EXYNOS4_IRQ_PMU                 IRQ_SPI(110)
+#define EXYNOS4_IRQ_POWER_PMU           IRQ_SPI(110)
 #define EXYNOS4_IRQ_GPS                 IRQ_SPI(111)
 #define EXYNOS4_IRQ_INTFEEDCTRL_SSS     IRQ_SPI(112)
 #define EXYNOS4_IRQ_SLIMBUS             IRQ_SPI(113)
@@ -136,6 +134,11 @@
 #define EXYNOS4_IRQ_TSI                 IRQ_SPI(115)
 #define EXYNOS4_IRQ_SATA                IRQ_SPI(116)
 
+#define EXYNOS4_IRQ_PMU                 COMBINER_IRQ(2, 2)
+#define EXYNOS4_IRQ_PMU_CPU1            COMBINER_IRQ(3, 2)
+#define EXYNOS4_IRQ_PMU_CPU2            COMBINER_IRQ(18, 2)
+#define EXYNOS4_IRQ_PMU_CPU3            COMBINER_IRQ(19, 2)
+
 #define EXYNOS4_IRQ_TMU_TRIG0           COMBINER_IRQ(2, 4)
 #define EXYNOS4_IRQ_TMU_TRIG1           COMBINER_IRQ(3, 4)
 
@@ -168,7 +171,10 @@
 #define EXYNOS4_IRQ_FIMD0_VSYNC         COMBINER_IRQ(11, 1)
 #define EXYNOS4_IRQ_FIMD0_SYSTEM        COMBINER_IRQ(11, 2)
 
-#define EXYNOS4_MAX_COMBINER_NR         16
+#define EXYNOS4210_MAX_COMBINER_NR      16
+#define EXYNOS4212_MAX_COMBINER_NR      18
+#define EXYNOS4412_MAX_COMBINER_NR      20
+#define EXYNOS4_MAX_COMBINER_NR         EXYNOS4412_MAX_COMBINER_NR
 
 #define EXYNOS4_IRQ_GPIO1_NR_GROUPS     16
 #define EXYNOS4_IRQ_GPIO2_NR_GROUPS     9
@@ -233,7 +239,6 @@
 #define IRQ_TC                          EXYNOS4_IRQ_PEN0
 
 #define IRQ_KEYPAD                      EXYNOS4_IRQ_KEYPAD
-#define IRQ_PMU                         EXYNOS4_IRQ_PMU
 
 #define IRQ_FIMD0_FIFO                  EXYNOS4_IRQ_FIMD0_FIFO
 #define IRQ_FIMD0_VSYNC                 EXYNOS4_IRQ_FIMD0_VSYNC
@@ -323,8 +328,6 @@
 #define EXYNOS5_IRQ_CEC                 IRQ_SPI(114)
 #define EXYNOS5_IRQ_SATA                IRQ_SPI(115)
 
-#define EXYNOS5_IRQ_MCT_L0              IRQ_SPI(120)
-#define EXYNOS5_IRQ_MCT_L1              IRQ_SPI(121)
 #define EXYNOS5_IRQ_MMC44               IRQ_SPI(123)
 #define EXYNOS5_IRQ_MDMA1               IRQ_SPI(124)
 #define EXYNOS5_IRQ_FIMC_LITE0          IRQ_SPI(125)
@@ -419,8 +422,6 @@
 #define EXYNOS5_IRQ_PMU_CPU1            COMBINER_IRQ(22, 4)
 
 #define EXYNOS5_IRQ_EINT0               COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_G0              COMBINER_IRQ(23, 3)
-#define EXYNOS5_IRQ_MCT_G1              COMBINER_IRQ(23, 4)
 
 #define EXYNOS5_IRQ_EINT1               COMBINER_IRQ(24, 0)
 #define EXYNOS5_IRQ_SYSMMU_LITE1_0      COMBINER_IRQ(24, 1)
@@ -466,7 +467,10 @@
 #define IRQ_TIMER_BASE                  (IRQ_GPIO_END + 64)
 
 /* Set the default NR_IRQS */
+#define EXYNOS_NR_IRQS                  (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
 
-#define NR_IRQS                         (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
+#ifndef CONFIG_SPARSE_IRQ
+#define NR_IRQS                         EXYNOS_NR_IRQS
+#endif
 
 #endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 1df6abbf53b8..99e0a79f3b1f 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -26,6 +26,9 @@
 #define EXYNOS4_PA_SYSRAM0              0x02025000
 #define EXYNOS4_PA_SYSRAM1              0x02020000
 #define EXYNOS5_PA_SYSRAM               0x02020000
+#define EXYNOS4210_PA_SYSRAM_NS         0x0203F000
+#define EXYNOS4x12_PA_SYSRAM_NS         0x0204F000
+#define EXYNOS5250_PA_SYSRAM_NS         0x0204F000
 
 #define EXYNOS4_PA_FIMC0                0x11800000
 #define EXYNOS4_PA_FIMC1                0x11810000
@@ -65,7 +68,6 @@
 #define EXYNOS5_PA_CMU                  0x10010000
 
 #define EXYNOS4_PA_SYSTIMER             0x10050000
-#define EXYNOS5_PA_SYSTIMER             0x101C0000
 
 #define EXYNOS4_PA_WATCHDOG             0x10060000
 #define EXYNOS5_PA_WATCHDOG             0x101D0000
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
index a67ecfaf1216..7dbbfec13ea5 100644
--- a/arch/arm/mach-exynos/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos/include/mach/pm-core.h
@@ -27,13 +27,8 @@ static inline void s3c_pm_debug_init_uart(void)
 
 static inline void s3c_pm_arch_prepare_irqs(void)
 {
-        unsigned int tmp;
-        tmp = __raw_readl(S5P_WAKEUP_MASK);
-        tmp &= ~(1 << 31);
-        __raw_writel(tmp, S5P_WAKEUP_MASK);
-
-        __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
-        __raw_writel(s3c_irqwake_eintmask & 0xFFFFFFFE, S5P_EINT_WAKEUP_MASK);
+        __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
+        __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 }
 
 static inline void s3c_pm_arch_stop_clocks(void)
diff --git a/arch/arm/mach-exynos/include/mach/regs-mct.h b/arch/arm/mach-exynos/include/mach/regs-mct.h
deleted file mode 100644
index 80dd02ad6d61..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-mct.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* arch/arm/mach-exynos4/include/mach/regs-mct.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 MCT configutation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_MCT_H
-#define __ASM_ARCH_REGS_MCT_H __FILE__
-
-#include <mach/map.h>
-
-#define EXYNOS4_MCTREG(x)               (S5P_VA_SYSTIMER + (x))
-
-#define EXYNOS4_MCT_G_CNT_L             EXYNOS4_MCTREG(0x100)
-#define EXYNOS4_MCT_G_CNT_U             EXYNOS4_MCTREG(0x104)
-#define EXYNOS4_MCT_G_CNT_WSTAT         EXYNOS4_MCTREG(0x110)
-
-#define EXYNOS4_MCT_G_COMP0_L           EXYNOS4_MCTREG(0x200)
-#define EXYNOS4_MCT_G_COMP0_U           EXYNOS4_MCTREG(0x204)
-#define EXYNOS4_MCT_G_COMP0_ADD_INCR    EXYNOS4_MCTREG(0x208)
-
-#define EXYNOS4_MCT_G_TCON              EXYNOS4_MCTREG(0x240)
-
-#define EXYNOS4_MCT_G_INT_CSTAT         EXYNOS4_MCTREG(0x244)
-#define EXYNOS4_MCT_G_INT_ENB           EXYNOS4_MCTREG(0x248)
-#define EXYNOS4_MCT_G_WSTAT             EXYNOS4_MCTREG(0x24C)
-
-#define _EXYNOS4_MCT_L_BASE             EXYNOS4_MCTREG(0x300)
-#define EXYNOS4_MCT_L_BASE(x)           (_EXYNOS4_MCT_L_BASE + (0x100 * x))
-#define EXYNOS4_MCT_L_MASK              (0xffffff00)
-
-#define MCT_L_TCNTB_OFFSET              (0x00)
-#define MCT_L_ICNTB_OFFSET              (0x08)
-#define MCT_L_TCON_OFFSET               (0x20)
-#define MCT_L_INT_CSTAT_OFFSET          (0x30)
-#define MCT_L_INT_ENB_OFFSET            (0x34)
-#define MCT_L_WSTAT_OFFSET              (0x40)
-
-#define MCT_G_TCON_START                (1 << 8)
-#define MCT_G_TCON_COMP0_AUTO_INC       (1 << 1)
-#define MCT_G_TCON_COMP0_ENABLE         (1 << 0)
-
-#define MCT_L_TCON_INTERVAL_MODE        (1 << 2)
-#define MCT_L_TCON_INT_START            (1 << 1)
-#define MCT_L_TCON_TIMER_START          (1 << 0)
-
-#endif /* __ASM_ARCH_REGS_MCT_H */
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index 685f29173afa..5f0f55701374 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -25,6 +25,7 @@
 #include <plat/regs-srom.h>
 #include <plat/sdhci.h>
 
+#include <mach/irqs.h>
 #include <mach/map.h>
 
 #include "common.h"
@@ -177,7 +178,6 @@ static void __init armlex4210_smsc911x_init(void)
 static void __init armlex4210_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(armlex4210_uartcfgs,
                            ARRAY_SIZE(armlex4210_uartcfgs));
 }
@@ -202,6 +202,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
         .map_io         = armlex4210_map_io,
         .init_machine   = armlex4210_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 3358088c822a..b9ed834a7eee 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -11,121 +11,26 @@
  * published by the Free Software Foundation.
 */
 
+#include <linux/kernel.h>
 #include <linux/of_platform.h>
+#include <linux/of_fdt.h>
 #include <linux/serial_core.h>
+#include <linux/memblock.h>
+#include <linux/clocksource.h>
 
 #include <asm/mach/arch.h>
-#include <mach/map.h>
-
-#include <plat/cpu.h>
-#include <plat/regs-serial.h>
+#include <plat/mfc.h>
 
 #include "common.h"
 
-/*
- * The following lookup table is used to override device names when devices
- * are registered from device tree. This is temporarily added to enable
- * device tree support addition for the Exynos4 architecture.
- *
- * For drivers that require platform data to be provided from the machine
- * file, a platform data pointer can also be supplied along with the
- * devices names. Usually, the platform data elements that cannot be parsed
- * from the device tree by the drivers (example: function pointers) are
- * supplied. But it should be noted that this is a temporary mechanism and
- * at some point, the drivers should be capable of parsing all the platform
- * data from the device tree.
- */
-static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
-                                "exynos4210-uart.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
-                                "exynos4210-uart.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
-                                "exynos4210-uart.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
-                                "exynos4210-uart.3", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
-                                "exynos4-sdhci.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1),
-                                "exynos4-sdhci.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2),
-                                "exynos4-sdhci.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3),
-                                "exynos4-sdhci.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
-                                "s3c2440-i2c.0", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1),
-                                "s3c2440-i2c.1", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(2),
-                                "s3c2440-i2c.2", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(3),
-                                "s3c2440-i2c.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(4),
-                                "s3c2440-i2c.4", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(5),
-                                "s3c2440-i2c.5", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(6),
-                                "s3c2440-i2c.6", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(7),
-                                "s3c2440-i2c.7", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
-                                "exynos4210-spi.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
-                                "exynos4210-spi.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
-                                "exynos4210-spi.2", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
-                                "exynos-tmu", NULL),
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13620000,
-                        "exynos-sysmmu.0", NULL), /* MFC_L */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13630000,
-                        "exynos-sysmmu.1", NULL), /* MFC_R */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E20000,
-                        "exynos-sysmmu.2", NULL), /* TV */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A60000,
-                        "exynos-sysmmu.3", NULL), /* JPEG */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A30000,
-                        "exynos-sysmmu.4", NULL), /* ROTATOR */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A20000,
-                        "exynos-sysmmu.5", NULL), /* FIMC0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A30000,
-                        "exynos-sysmmu.6", NULL), /* FIMC1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A40000,
-                        "exynos-sysmmu.7", NULL), /* FIMC2 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A50000,
-                        "exynos-sysmmu.8", NULL), /* FIMC3 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A20000,
-                        "exynos-sysmmu.9", NULL), /* G2D(4210) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A40000,
-                        "exynos-sysmmu.9", NULL), /* G2D(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11E20000,
-                        "exynos-sysmmu.10", NULL), /* FIMD0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12220000,
-                        "exynos-sysmmu.11", NULL), /* FIMD1(4210) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12260000,
-                        "exynos-sysmmu.12", NULL), /* IS0(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x122B0000,
-                        "exynos-sysmmu.13", NULL), /* IS1(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123B0000,
-                        "exynos-sysmmu.14", NULL), /* FIMC-LITE0(4x12) */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123C0000,
-                        "exynos-sysmmu.15", NULL), /* FIMC-LITE1(4x12) */
-        {},
-};
-
 static void __init exynos4_dt_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
 }
 
 static void __init exynos4_dt_machine_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table,
-                                exynos4_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static char const *exynos4_dt_compat[] __initdata = {
@@ -135,14 +40,28 @@ static char const *exynos4_dt_compat[] __initdata = {
         NULL
 };
 
+static void __init exynos4_reserve(void)
+{
+#ifdef CONFIG_S5P_DEV_MFC
+        struct s5p_mfc_dt_meminfo mfc_mem;
+
+        /* Reserve memory for MFC only if it's available */
+        mfc_mem.compatible = "samsung,mfc-v5";
+        if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
+                s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
+                                mfc_mem.lsize);
+#endif
+}
 DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
         /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
         .smp            = smp_ops(exynos_smp_ops),
         .init_irq       = exynos4_init_irq,
         .map_io         = exynos4_dt_map_io,
+        .init_early     = exynos_firmware_init,
         .init_machine   = exynos4_dt_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .dt_compat      = exynos4_dt_compat,
         .restart        = exynos4_restart,
+        .reserve        = exynos4_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index acaeb14db54b..753b94f3fca7 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -11,151 +11,21 @@
 
 #include <linux/of_platform.h>
 #include <linux/of_fdt.h>
-#include <linux/serial_core.h>
 #include <linux/memblock.h>
 #include <linux/io.h>
+#include <linux/clocksource.h>
 
 #include <asm/mach/arch.h>
-#include <mach/map.h>
 #include <mach/regs-pmu.h>
 
 #include <plat/cpu.h>
-#include <plat/regs-serial.h>
 #include <plat/mfc.h>
 
 #include "common.h"
 
-/*
- * The following lookup table is used to override device names when devices
- * are registered from device tree. This is temporarily added to enable
- * device tree support addition for the EXYNOS5 architecture.
- *
- * For drivers that require platform data to be provided from the machine
- * file, a platform data pointer can also be supplied along with the
- * devices names. Usually, the platform data elements that cannot be parsed
- * from the device tree by the drivers (example: function pointers) are
- * supplied. But it should be noted that this is a temporary mechanism and
- * at some point, the drivers should be capable of parsing all the platform
- * data from the device tree.
- */
-static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
-                                "exynos4210-uart.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
-                                "exynos4210-uart.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
-                                "exynos4210-uart.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
-                                "exynos4210-uart.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
-                                "s3c2440-i2c.0", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
-                                "s3c2440-i2c.1", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
-                                "s3c2440-i2c.2", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
-                                "s3c2440-i2c.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
-                                "s3c2440-i2c.4", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
-                                "s3c2440-i2c.5", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
-                                "s3c2440-i2c.6", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
-                                "s3c2440-i2c.7", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8),
-                                "s3c2440-hdmiphy-i2c", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
-                                "dw_mmc.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
-                                "dw_mmc.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI2,
-                                "dw_mmc.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI3,
-                                "dw_mmc.3", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
-                                "exynos4210-spi.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
-                                "exynos4210-spi.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
-                                "exynos4210-spi.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
-                                "exynos5-sata", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000,
-                                "exynos5-sata-phy", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
-                                "exynos5-sata-phy-i2c", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0,
-                                "exynos-gsc.0", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1,
-                                "exynos-gsc.1", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2,
-                                "exynos-gsc.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
-                                "exynos-gsc.3", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
-                                "exynos5-hdmi", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000,
-                                "exynos5-mixer", NULL),
-        OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
-        OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
-                                "exynos-tmu", NULL),
-        OF_DEV_AUXDATA("samsung,i2s-v5", 0x03830000,
-                                "samsung-i2s.0", NULL),
-        OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D60000,
-                                "samsung-i2s.1", NULL),
-        OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D70000,
-                                "samsung-i2s.2", NULL),
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11210000,
-                        "exynos-sysmmu.0", "mfc"), /* MFC_L */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11200000,
-                        "exynos-sysmmu.1", "mfc"), /* MFC_R */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14650000,
-                        "exynos-sysmmu.2", NULL), /* TV */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11F20000,
-                        "exynos-sysmmu.3", "jpeg"), /* JPEG */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11D40000,
-                        "exynos-sysmmu.4", NULL), /* ROTATOR */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E80000,
-                        "exynos-sysmmu.5", "gscl"), /* GSCL0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E90000,
-                        "exynos-sysmmu.6", "gscl"), /* GSCL1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EA0000,
-                        "exynos-sysmmu.7", "gscl"), /* GSCL2 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EB0000,
-                        "exynos-sysmmu.8", "gscl"), /* GSCL3 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13260000,
-                        "exynos-sysmmu.9", NULL), /* FIMC-IS0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x132C0000,
-                        "exynos-sysmmu.10", NULL), /* FIMC-IS1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14640000,
-                        "exynos-sysmmu.11", NULL), /* FIMD1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C40000,
-                        "exynos-sysmmu.12", NULL), /* FIMC-LITE0 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C50000,
-                        "exynos-sysmmu.13", NULL), /* FIMC-LITE1 */
-        OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A60000,
-                        "exynos-sysmmu.14", NULL), /* G2D */
-        {},
-};
-
-static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0,
-                                "exynos4210-uart.0", NULL),
-        {},
-};
-
 static void __init exynos5_dt_map_io(void)
 {
-        unsigned long root = of_get_flat_dt_root();
-
         exynos_init_io(NULL, 0);
-
-        if (of_flat_dt_is_compatible(root, "samsung,exynos5250"))
-                s3c24xx_init_clocks(24000000);
 }
 
 static void __init exynos5_dt_machine_init(void)
@@ -182,12 +52,7 @@ static void __init exynos5_dt_machine_init(void)
                 }
         }
 
-        if (of_machine_is_compatible("samsung,exynos5250"))
-                of_platform_populate(NULL, of_default_bus_match_table,
-                                     exynos5250_auxdata_lookup, NULL);
-        else if (of_machine_is_compatible("samsung,exynos5440"))
-                of_platform_populate(NULL, of_default_bus_match_table,
-                                     exynos5440_auxdata_lookup, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static char const *exynos5_dt_compat[] __initdata = {
@@ -216,7 +81,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
         .map_io         = exynos5_dt_map_io,
         .init_machine   = exynos5_dt_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .dt_compat      = exynos5_dt_compat,
         .restart        = exynos5_restart,
         .reserve        = exynos5_reserve,
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 1ea79730187f..5c8b2878dbbd 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -53,6 +53,7 @@
 #include <plat/fimc-core.h>
 #include <plat/camport.h>
 
+#include <mach/irqs.h>
 #include <mach/map.h>
 
 #include "common.h"
@@ -1251,7 +1252,7 @@ static void __init nuri_camera_init(void)
         }
 
         m5mols_board_info.irq = s5p_register_gpio_interrupt(GPIO_CAM_8M_ISP_INT);
-        if (!IS_ERR_VALUE(m5mols_board_info.irq))
+        if (m5mols_board_info.irq >= 0)
                 s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xF));
         else
                 pr_err("%s: Failed to configure 8M_ISP_INT GPIO\n", __func__);
@@ -1330,8 +1331,9 @@ static struct platform_device *nuri_devices[] __initdata = {
 static void __init nuri_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
+        xxti_f = 0;
+        xusbxti_f = 24000000;
 }
 
 static void __init nuri_reserve(void)
@@ -1380,7 +1382,7 @@ MACHINE_START(NURI, "NURI")
         .map_io         = nuri_map_io,
         .init_machine   = nuri_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .reserve        = &nuri_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 579d2d171daa..27f03ed5d067 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -26,7 +26,7 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <linux/platform_data/s3c-hsotg.h>
 #include <linux/platform_data/usb-ehci-s5p.h>
-#include <linux/platform_data/usb-exynos.h>
+#include <linux/platform_data/usb-ohci-exynos.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -46,6 +46,7 @@
 #include <plat/hdmi.h>
 
 #include <mach/map.h>
+#include <mach/irqs.h>
 
 #include <drm/exynos_drm.h>
 #include "common.h"
@@ -754,8 +755,9 @@ static void s5p_tv_setup(void)
 static void __init origen_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
+        xxti_f = 0;
+        xusbxti_f = 24000000;
 }
 
 static void __init origen_power_init(void)
@@ -815,7 +817,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
         .map_io         = origen_map_io,
         .init_machine   = origen_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .reserve        = &origen_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index fe6149624b84..2c8af9617920 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -39,6 +39,7 @@
 #include <plat/regs-serial.h>
 #include <plat/sdhci.h>
 
+#include <mach/irqs.h>
 #include <mach/map.h>
 
 #include <drm/exynos_drm.h>
@@ -322,7 +323,6 @@ static struct platform_device *smdk4x12_devices[] __initdata = {
 static void __init smdk4x12_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
 }
 
@@ -376,7 +376,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
         .init_irq       = exynos4_init_irq,
         .map_io         = smdk4x12_map_io,
         .init_machine   = smdk4x12_machine_init,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .restart        = exynos4_restart,
         .reserve        = &smdk4x12_reserve,
 MACHINE_END
@@ -390,7 +390,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
         .map_io         = smdk4x12_map_io,
         .init_machine   = smdk4x12_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .restart        = exynos4_restart,
         .reserve        = &smdk4x12_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index d71672922b19..d95b8cf85253 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -23,7 +23,7 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <linux/platform_data/s3c-hsotg.h>
 #include <linux/platform_data/usb-ehci-s5p.h>
-#include <linux/platform_data/usb-exynos.h>
+#include <linux/platform_data/usb-ohci-exynos.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -43,6 +43,7 @@
 #include <plat/clock.h>
 #include <plat/hdmi.h>
 
+#include <mach/irqs.h>
 #include <mach/map.h>
 
 #include <drm/exynos_drm.h>
@@ -371,8 +372,9 @@ static void s5p_tv_setup(void)
 static void __init smdkv310_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
+        xxti_f = 12000000;
+        xusbxti_f = 24000000;
 }
 
 static void __init smdkv310_reserve(void)
@@ -423,7 +425,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
         .init_irq       = exynos4_init_irq,
         .map_io         = smdkv310_map_io,
         .init_machine   = smdkv310_machine_init,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .reserve        = &smdkv310_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
@@ -436,7 +438,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
         .map_io         = smdkv310_map_io,
         .init_machine   = smdkv310_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = exynos4_timer_init,
+        .init_time      = exynos_init_time,
         .reserve        = &smdkv310_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 497fcb793dc1..327d50d4681d 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -41,7 +41,7 @@
 #include <plat/mfc.h>
 #include <plat/sdhci.h>
 #include <plat/fimc-core.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/camport.h>
 
 #include <mach/map.h>
@@ -97,6 +97,19 @@ static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
 static struct regulator_consumer_supply max8952_consumer =
         REGULATOR_SUPPLY("vdd_arm", NULL);
 
+static struct regulator_init_data universal_max8952_reg_data = {
+        .constraints    = {
+                .name           = "VARM_1.2V",
+                .min_uV         = 770000,
+                .max_uV         = 1400000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .always_on      = 1,
+                .boot_on        = 1,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &max8952_consumer,
+};
+
 static struct max8952_platform_data universal_max8952_pdata __initdata = {
         .gpio_vid0      = EXYNOS4_GPX0(3),
         .gpio_vid1      = EXYNOS4_GPX0(4),
@@ -105,19 +118,7 @@ static struct max8952_platform_data universal_max8952_pdata __initdata = {
         .dvs_mode       = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */
         .sync_freq      = 0, /* default: fastest */
         .ramp_speed     = 0, /* default: fastest */
-
-        .reg_data       = {
-                .constraints    = {
-                        .name           = "VARM_1.2V",
-                        .min_uV         = 770000,
-                        .max_uV         = 1400000,
-                        .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                        .always_on      = 1,
-                        .boot_on        = 1,
-                },
-                .num_consumer_supplies  = 1,
-                .consumer_supplies      = &max8952_consumer,
-        },
+        .reg_data       = &universal_max8952_reg_data,
 };
 
 static struct regulator_consumer_supply lp3974_buck1_consumer =
@@ -1092,9 +1093,10 @@ static struct platform_device *universal_devices[] __initdata = {
 static void __init universal_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
-        s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
+        xxti_f = 0;
+        xusbxti_f = 24000000;
 }
 
 static void s5p_tv_setup(void)
@@ -1152,7 +1154,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
         .map_io         = universal_map_io,
         .init_machine   = universal_machine_init,
         .init_late      = exynos_init_late,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .reserve        = &universal_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
deleted file mode 100644
index c9d6650f9b5d..000000000000
--- a/arch/arm/mach-exynos/mct.c
+++ /dev/null
@@ -1,485 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mct.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 MCT(Multi-Core Timer) support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/clockchips.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/percpu.h>
-#include <linux/of.h>
-
-#include <asm/arch_timer.h>
-#include <asm/localtimer.h>
-
-#include <plat/cpu.h>
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/regs-mct.h>
-#include <asm/mach/time.h>
-
-#define TICK_BASE_CNT   1
-
-enum {
-        MCT_INT_SPI,
-        MCT_INT_PPI
-};
-
-static unsigned long clk_rate;
-static unsigned int mct_int_type;
-
-struct mct_clock_event_device {
-        struct clock_event_device *evt;
-        void __iomem *base;
-        char name[10];
-};
-
-static void exynos4_mct_write(unsigned int value, void *addr)
-{
-        void __iomem *stat_addr;
-        u32 mask;
-        u32 i;
-
-        __raw_writel(value, addr);
-
-        if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
-                u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
-                switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
-                case (u32) MCT_L_TCON_OFFSET:
-                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
-                        mask = 1 << 3;          /* L_TCON write status */
-                        break;
-                case (u32) MCT_L_ICNTB_OFFSET:
-                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
-                        mask = 1 << 1;          /* L_ICNTB write status */
-                        break;
-                case (u32) MCT_L_TCNTB_OFFSET:
-                        stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
-                        mask = 1 << 0;          /* L_TCNTB write status */
-                        break;
-                default:
-                        return;
-                }
-        } else {
-                switch ((u32) addr) {
-                case (u32) EXYNOS4_MCT_G_TCON:
-                        stat_addr = EXYNOS4_MCT_G_WSTAT;
-                        mask = 1 << 16;         /* G_TCON write status */
-                        break;
-                case (u32) EXYNOS4_MCT_G_COMP0_L:
-                        stat_addr = EXYNOS4_MCT_G_WSTAT;
-                        mask = 1 << 0;          /* G_COMP0_L write status */
-                        break;
-                case (u32) EXYNOS4_MCT_G_COMP0_U:
-                        stat_addr = EXYNOS4_MCT_G_WSTAT;
-                        mask = 1 << 1;          /* G_COMP0_U write status */
-                        break;
-                case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
-                        stat_addr = EXYNOS4_MCT_G_WSTAT;
-                        mask = 1 << 2;          /* G_COMP0_ADD_INCR w status */
-                        break;
-                case (u32) EXYNOS4_MCT_G_CNT_L:
-                        stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
-                        mask = 1 << 0;          /* G_CNT_L write status */
-                        break;
-                case (u32) EXYNOS4_MCT_G_CNT_U:
-                        stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
-                        mask = 1 << 1;          /* G_CNT_U write status */
-                        break;
-                default:
-                        return;
-                }
-        }
-
-        /* Wait maximum 1 ms until written values are applied */
-        for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
-                if (__raw_readl(stat_addr) & mask) {
-                        __raw_writel(mask, stat_addr);
-                        return;
-                }
-
-        panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
-}
-
-/* Clocksource handling */
-static void exynos4_mct_frc_start(u32 hi, u32 lo)
-{
-        u32 reg;
-
-        exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
-        exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
-
-        reg = __raw_readl(EXYNOS4_MCT_G_TCON);
-        reg |= MCT_G_TCON_START;
-        exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
-}
-
-static cycle_t exynos4_frc_read(struct clocksource *cs)
-{
-        unsigned int lo, hi;
-        u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
-
-        do {
-                hi = hi2;
-                lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
-                hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
-        } while (hi != hi2);
-
-        return ((cycle_t)hi << 32) | lo;
-}
-
-static void exynos4_frc_resume(struct clocksource *cs)
-{
-        exynos4_mct_frc_start(0, 0);
-}
-
-struct clocksource mct_frc = {
-        .name           = "mct-frc",
-        .rating         = 400,
-        .read           = exynos4_frc_read,
-        .mask           = CLOCKSOURCE_MASK(64),
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-        .resume         = exynos4_frc_resume,
-};
-
-static void __init exynos4_clocksource_init(void)
-{
-        exynos4_mct_frc_start(0, 0);
-
-        if (clocksource_register_hz(&mct_frc, clk_rate))
-                panic("%s: can't register clocksource\n", mct_frc.name);
-}
-
-static void exynos4_mct_comp0_stop(void)
-{
-        unsigned int tcon;
-
-        tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
-        tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
-
-        exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
-        exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
-}
-
-static void exynos4_mct_comp0_start(enum clock_event_mode mode,
-                                    unsigned long cycles)
-{
-        unsigned int tcon;
-        cycle_t comp_cycle;
-
-        tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
-
-        if (mode == CLOCK_EVT_MODE_PERIODIC) {
-                tcon |= MCT_G_TCON_COMP0_AUTO_INC;
-                exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
-        }
-
-        comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
-        exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
-        exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
-
-        exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
-
-        tcon |= MCT_G_TCON_COMP0_ENABLE;
-        exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
-}
-
-static int exynos4_comp_set_next_event(unsigned long cycles,
-                                       struct clock_event_device *evt)
-{
-        exynos4_mct_comp0_start(evt->mode, cycles);
-
-        return 0;
-}
-
-static void exynos4_comp_set_mode(enum clock_event_mode mode,
-                                  struct clock_event_device *evt)
-{
-        unsigned long cycles_per_jiffy;
-        exynos4_mct_comp0_stop();
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                cycles_per_jiffy =
-                        (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
-                exynos4_mct_comp0_start(mode, cycles_per_jiffy);
-                break;
-
-        case CLOCK_EVT_MODE_ONESHOT:
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_RESUME:
-                break;
-        }
-}
-
-static struct clock_event_device mct_comp_device = {
-        .name           = "mct-comp",
-        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .rating         = 250,
-        .set_next_event = exynos4_comp_set_next_event,
-        .set_mode       = exynos4_comp_set_mode,
-};
-
-static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
-{
-        struct clock_event_device *evt = dev_id;
-
-        exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
-
-        evt->event_handler(evt);
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction mct_comp_event_irq = {
-        .name           = "mct_comp_irq",
-        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = exynos4_mct_comp_isr,
-        .dev_id         = &mct_comp_device,
-};
-
-static void exynos4_clockevent_init(void)
-{
-        mct_comp_device.cpumask = cpumask_of(0);
-        clockevents_config_and_register(&mct_comp_device, clk_rate,
-                                        0xf, 0xffffffff);
-
-        if (soc_is_exynos5250())
-                setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
-        else
-                setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
-}
-
-#ifdef CONFIG_LOCAL_TIMERS
-
-static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
-
-/* Clock event handling */
-static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
-{
-        unsigned long tmp;
-        unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
-        void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
-
-        tmp = __raw_readl(addr);
-        if (tmp & mask) {
-                tmp &= ~mask;
-                exynos4_mct_write(tmp, addr);
-        }
-}
-
-static void exynos4_mct_tick_start(unsigned long cycles,
-                                   struct mct_clock_event_device *mevt)
-{
-        unsigned long tmp;
-
-        exynos4_mct_tick_stop(mevt);
-
-        tmp = (1 << 31) | cycles;       /* MCT_L_UPDATE_ICNTB */
-
-        /* update interrupt count buffer */
-        exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
-
-        /* enable MCT tick interrupt */
-        exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
-
-        tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
-        tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
-               MCT_L_TCON_INTERVAL_MODE;
-        exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
-}
-
-static int exynos4_tick_set_next_event(unsigned long cycles,
-                                       struct clock_event_device *evt)
-{
-        struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
-
-        exynos4_mct_tick_start(cycles, mevt);
-
-        return 0;
-}
-
-static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
-                                         struct clock_event_device *evt)
-{
-        struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
-        unsigned long cycles_per_jiffy;
-
-        exynos4_mct_tick_stop(mevt);
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                cycles_per_jiffy =
-                        (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
-                exynos4_mct_tick_start(cycles_per_jiffy, mevt);
-                break;
-
-        case CLOCK_EVT_MODE_ONESHOT:
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_RESUME:
-                break;
-        }
-}
-
-static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
-{
-        struct clock_event_device *evt = mevt->evt;
-
-        /*
-         * This is for supporting oneshot mode.
-         * Mct would generate interrupt periodically
-         * without explicit stopping.
-         */
-        if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
-                exynos4_mct_tick_stop(mevt);
-
-        /* Clear the MCT tick interrupt */
-        if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
-                exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
-                return 1;
-        } else {
-                return 0;
-        }
-}
-
-static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
-{
-        struct mct_clock_event_device *mevt = dev_id;
-        struct clock_event_device *evt = mevt->evt;
-
-        exynos4_mct_tick_clear(mevt);
-
-        evt->event_handler(evt);
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction mct_tick0_event_irq = {
-        .name           = "mct_tick0_irq",
-        .flags          = IRQF_TIMER | IRQF_NOBALANCING,
-        .handler        = exynos4_mct_tick_isr,
-};
-
-static struct irqaction mct_tick1_event_irq = {
-        .name           = "mct_tick1_irq",
-        .flags          = IRQF_TIMER | IRQF_NOBALANCING,
-        .handler        = exynos4_mct_tick_isr,
-};
-
-static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
-{
-        struct mct_clock_event_device *mevt;
-        unsigned int cpu = smp_processor_id();
-        int mct_lx_irq;
-
-        mevt = this_cpu_ptr(&percpu_mct_tick);
-        mevt->evt = evt;
-
-        mevt->base = EXYNOS4_MCT_L_BASE(cpu);
-        sprintf(mevt->name, "mct_tick%d", cpu);
-
-        evt->name = mevt->name;
-        evt->cpumask = cpumask_of(cpu);
-        evt->set_next_event = exynos4_tick_set_next_event;
-        evt->set_mode = exynos4_tick_set_mode;
-        evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
-        evt->rating = 450;
-        clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
-                                        0xf, 0x7fffffff);
-
-        exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
-
-        if (mct_int_type == MCT_INT_SPI) {
-                if (cpu == 0) {
-                        mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
-                                                EXYNOS5_IRQ_MCT_L0;
-                        mct_tick0_event_irq.dev_id = mevt;
-                        evt->irq = mct_lx_irq;
-                        setup_irq(mct_lx_irq, &mct_tick0_event_irq);
-                } else {
-                        mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
-                                                EXYNOS5_IRQ_MCT_L1;
-                        mct_tick1_event_irq.dev_id = mevt;
-                        evt->irq = mct_lx_irq;
-                        setup_irq(mct_lx_irq, &mct_tick1_event_irq);
-                        irq_set_affinity(mct_lx_irq, cpumask_of(1));
-                }
-        } else {
-                enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
-        }
-
-        return 0;
-}
-
-static void exynos4_local_timer_stop(struct clock_event_device *evt)
-{
-        unsigned int cpu = smp_processor_id();
-        evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
-        if (mct_int_type == MCT_INT_SPI)
-                if (cpu == 0)
-                        remove_irq(evt->irq, &mct_tick0_event_irq);
-                else
-                        remove_irq(evt->irq, &mct_tick1_event_irq);
-        else
-                disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
-}
-
-static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
-        .setup  = exynos4_local_timer_setup,
-        .stop   = exynos4_local_timer_stop,
-};
-#endif /* CONFIG_LOCAL_TIMERS */
-
-static void __init exynos4_timer_resources(void)
-{
-        struct clk *mct_clk;
-        mct_clk = clk_get(NULL, "xtal");
-
-        clk_rate = clk_get_rate(mct_clk);
-
-#ifdef CONFIG_LOCAL_TIMERS
-        if (mct_int_type == MCT_INT_PPI) {
-                int err;
-
-                err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
-                                         exynos4_mct_tick_isr, "MCT",
-                                         &percpu_mct_tick);
-                WARN(err, "MCT: can't request IRQ %d (%d)\n",
-                     EXYNOS_IRQ_MCT_LOCALTIMER, err);
-        }
-
-        local_timer_register(&exynos4_mct_tick_ops);
-#endif /* CONFIG_LOCAL_TIMERS */
-}
-
-void __init exynos4_timer_init(void)
-{
-        if (soc_is_exynos5440()) {
-                arch_timer_of_register();
-                return;
-        }
-
-        if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
-                mct_int_type = MCT_INT_SPI;
-        else
-                mct_int_type = MCT_INT_PPI;
-
-        exynos4_timer_resources();
-        exynos4_clocksource_init();
-        exynos4_clockevent_init();
-}
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 60f7c5be057d..a0e8ff7758a4 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -20,11 +20,11 @@
 #include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
 
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
+#include <asm/firmware.h>
 
 #include <mach/hardware.h>
 #include <mach/regs-clock.h>
@@ -76,13 +76,6 @@ static DEFINE_SPINLOCK(boot_lock);
 static void __cpuinit exynos_secondary_init(unsigned int cpu)
 {
         /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-
-        /*
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
@@ -145,10 +138,21 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
 
         timeout = jiffies + (1 * HZ);
         while (time_before(jiffies, timeout)) {
+                unsigned long boot_addr;
+
                 smp_rmb();
 
-                __raw_writel(virt_to_phys(exynos4_secondary_startup),
-                                                        cpu_boot_reg(phys_cpu));
+                boot_addr = virt_to_phys(exynos4_secondary_startup);
+
+                /*
+                 * Try to set boot address using firmware first
+                 * and fall back to boot register if it fails.
+                 */
+                if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr))
+                        __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
+
+                call_firmware_op(cpu_boot, phys_cpu);
+
                 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 
                 if (pen_release == -1)
@@ -204,10 +208,20 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
          * system-wide flags register. The boot monitor waits
          * until it receives a soft interrupt, and then the
          * secondary CPU branches to this address.
+         *
+         * Try using firmware operation first and fall back to
+         * boot register if it fails.
          */
-        for (i = 1; i < max_cpus; ++i)
-                __raw_writel(virt_to_phys(exynos4_secondary_startup),
-                                        cpu_boot_reg(cpu_logical_map(i)));
+        for (i = 1; i < max_cpus; ++i) {
+                unsigned long phys_cpu;
+                unsigned long boot_addr;
+
+                phys_cpu = cpu_logical_map(i);
+                boot_addr = virt_to_phys(exynos4_secondary_startup);
+
+                if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr))
+                        __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
+        }
 }
 
 struct smp_operations exynos_smp_ops __initdata = {
diff --git a/arch/arm/mach-exynos/setup-sdhci-gpio.c b/arch/arm/mach-exynos/setup-sdhci-gpio.c
index e8d08bf8965a..d5b98c866738 100644
--- a/arch/arm/mach-exynos/setup-sdhci-gpio.c
+++ b/arch/arm/mach-exynos/setup-sdhci-gpio.c
@@ -19,8 +19,8 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/card.h>
 
+#include <mach/gpio.h>
 #include <plat/gpio-cfg.h>
-#include <plat/regs-sdhci.h>
 #include <plat/sdhci.h>
 
 void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index b81cc569a8dd..6af40662a449 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -204,9 +204,9 @@ static int exynos4210_usb_phy1_exit(struct platform_device *pdev)
 
 int s5p_usb_phy_init(struct platform_device *pdev, int type)
 {
-        if (type == S5P_USB_PHY_DEVICE)
+        if (type == USB_PHY_TYPE_DEVICE)
                 return exynos4210_usb_phy0_init(pdev);
-        else if (type == S5P_USB_PHY_HOST)
+        else if (type == USB_PHY_TYPE_HOST)
                 return exynos4210_usb_phy1_init(pdev);
 
         return -EINVAL;
@@ -214,9 +214,9 @@ int s5p_usb_phy_init(struct platform_device *pdev, int type)
 
 int s5p_usb_phy_exit(struct platform_device *pdev, int type)
 {
-        if (type == S5P_USB_PHY_DEVICE)
+        if (type == USB_PHY_TYPE_DEVICE)
                 return exynos4210_usb_phy0_exit(pdev);
-        else if (type == S5P_USB_PHY_HOST)
+        else if (type == USB_PHY_TYPE_HOST)
                 return exynos4210_usb_phy1_exit(pdev);
 
         return -EINVAL;
diff --git a/arch/arm/mach-exynos/smc.h b/arch/arm/mach-exynos/smc.h
new file mode 100644
index 000000000000..13a1dc8ecbf2
--- /dev/null
+++ b/arch/arm/mach-exynos/smc.h
@@ -0,0 +1,31 @@
+/*
+ *  Copyright (c) 2012 Samsung Electronics.
+ *
+ * EXYNOS - SMC Call
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_SMC_H
+#define __ASM_ARCH_EXYNOS_SMC_H
+
+#define SMC_CMD_INIT            (-1)
+#define SMC_CMD_INFO            (-2)
+/* For Power Management */
+#define SMC_CMD_SLEEP           (-3)
+#define SMC_CMD_CPU1BOOT        (-4)
+#define SMC_CMD_CPU0AFTR        (-5)
+/* For CP15 Access */
+#define SMC_CMD_C15RESUME       (-11)
+/* For L2 Cache Access */
+#define SMC_CMD_L2X0CTRL        (-21)
+#define SMC_CMD_L2X0SETUP1      (-22)
+#define SMC_CMD_L2X0SETUP2      (-23)
+#define SMC_CMD_L2X0INVALL      (-24)
+#define SMC_CMD_L2X0DEBUG       (-25)
+
+extern void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3);
+
+#endif
diff --git a/arch/arm/mach-gemini/Makefile b/arch/arm/mach-gemini/Makefile
index 7355c0bbcb5e..7963a77be637 100644
--- a/arch/arm/mach-gemini/Makefile
+++ b/arch/arm/mach-gemini/Makefile
@@ -4,7 +4,7 @@
 
 # Object file lists.
 
-obj-y                   := irq.o mm.o time.o devices.o gpio.o idle.o
+obj-y                   := irq.o mm.o time.o devices.o gpio.o idle.o reset.o
 
 # Board-specific support
 obj-$(CONFIG_MACH_NAS4220B)     += board-nas4220b.o
diff --git a/arch/arm/mach-gemini/board-nas4220b.c b/arch/arm/mach-gemini/board-nas4220b.c
index 08bd650c42f3..ca8a25bb3521 100644
--- a/arch/arm/mach-gemini/board-nas4220b.c
+++ b/arch/arm/mach-gemini/board-nas4220b.c
@@ -103,4 +103,5 @@ MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
         .init_irq       = gemini_init_irq,
         .init_time      = gemini_timer_init,
         .init_machine   = ib4220b_init,
+        .restart        = gemini_restart,
 MACHINE_END
diff --git a/arch/arm/mach-gemini/board-rut1xx.c b/arch/arm/mach-gemini/board-rut1xx.c
index fa0a36337f4d..7a675f88ffd6 100644
--- a/arch/arm/mach-gemini/board-rut1xx.c
+++ b/arch/arm/mach-gemini/board-rut1xx.c
@@ -14,6 +14,7 @@
 #include <linux/leds.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
+#include <linux/sizes.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -87,4 +88,5 @@ MACHINE_START(RUT100, "Teltonika RUT100")
         .init_irq       = gemini_init_irq,
         .init_time      = gemini_timer_init,
         .init_machine   = rut1xx_init,
+        .restart        = gemini_restart,
 MACHINE_END
diff --git a/arch/arm/mach-gemini/board-wbd111.c b/arch/arm/mach-gemini/board-wbd111.c
index 3321cd6cc1f3..418188cd1712 100644
--- a/arch/arm/mach-gemini/board-wbd111.c
+++ b/arch/arm/mach-gemini/board-wbd111.c
@@ -130,4 +130,5 @@ MACHINE_START(WBD111, "Wiliboard WBD-111")
         .init_irq       = gemini_init_irq,
         .init_time      = gemini_timer_init,
         .init_machine   = wbd111_init,
+        .restart        = gemini_restart,
 MACHINE_END
diff --git a/arch/arm/mach-gemini/board-wbd222.c b/arch/arm/mach-gemini/board-wbd222.c
index fe33c825fdaf..266b265090cd 100644
--- a/arch/arm/mach-gemini/board-wbd222.c
+++ b/arch/arm/mach-gemini/board-wbd222.c
@@ -130,4 +130,5 @@ MACHINE_START(WBD222, "Wiliboard WBD-222")
         .init_irq       = gemini_init_irq,
         .init_time      = gemini_timer_init,
         .init_machine   = wbd222_init,
+        .restart        = gemini_restart,
 MACHINE_END
diff --git a/arch/arm/mach-gemini/common.h b/arch/arm/mach-gemini/common.h
index 7670c39acb2f..38a45260a7c8 100644
--- a/arch/arm/mach-gemini/common.h
+++ b/arch/arm/mach-gemini/common.h
@@ -26,4 +26,6 @@ extern int platform_register_pflash(unsigned int size,
                                     struct mtd_partition *parts,
                                     unsigned int nr_parts);
 
+extern void gemini_restart(char mode, const char *cmd);
+
 #endif /* __GEMINI_COMMON_H__ */
diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c
index fdc7ef1391d3..70bfa571b24b 100644
--- a/arch/arm/mach-gemini/gpio.c
+++ b/arch/arm/mach-gemini/gpio.c
@@ -21,6 +21,7 @@
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
+#include <mach/gpio.h>
 
 #define GPIO_BASE(x)            IO_ADDRESS(GEMINI_GPIO_BASE(x))
 
@@ -44,7 +45,7 @@
 
 #define GPIO_PORT_NUM           3
 
-static void _set_gpio_irqenable(unsigned int base, unsigned int index,
+static void _set_gpio_irqenable(void __iomem *base, unsigned int index,
                                 int enable)
 {
         unsigned int reg;
@@ -57,7 +58,7 @@ static void _set_gpio_irqenable(unsigned int base, unsigned int index,
 static void gpio_ack_irq(struct irq_data *d)
 {
         unsigned int gpio = irq_to_gpio(d->irq);
-        unsigned int base = GPIO_BASE(gpio / 32);
+        void __iomem *base = GPIO_BASE(gpio / 32);
 
         __raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR);
 }
@@ -65,7 +66,7 @@ static void gpio_ack_irq(struct irq_data *d)
 static void gpio_mask_irq(struct irq_data *d)
 {
         unsigned int gpio = irq_to_gpio(d->irq);
-        unsigned int base = GPIO_BASE(gpio / 32);
+        void __iomem *base = GPIO_BASE(gpio / 32);
 
         _set_gpio_irqenable(base, gpio % 32, 0);
 }
@@ -73,7 +74,7 @@ static void gpio_mask_irq(struct irq_data *d)
 static void gpio_unmask_irq(struct irq_data *d)
 {
         unsigned int gpio = irq_to_gpio(d->irq);
-        unsigned int base = GPIO_BASE(gpio / 32);
+        void __iomem *base = GPIO_BASE(gpio / 32);
 
         _set_gpio_irqenable(base, gpio % 32, 1);
 }
@@ -82,7 +83,7 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type)
 {
         unsigned int gpio = irq_to_gpio(d->irq);
         unsigned int gpio_mask = 1 << (gpio % 32);
-        unsigned int base = GPIO_BASE(gpio / 32);
+        void __iomem *base = GPIO_BASE(gpio / 32);
         unsigned int reg_both, reg_level, reg_type;
 
         reg_type = __raw_readl(base + GPIO_INT_TYPE);
@@ -120,7 +121,7 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type)
         __raw_writel(reg_level, base + GPIO_INT_LEVEL);
         __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE);
 
-        gpio_ack_irq(d->irq);
+        gpio_ack_irq(d);
 
         return 0;
 }
@@ -153,7 +154,7 @@ static struct irq_chip gpio_irq_chip = {
 static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
                                 int dir)
 {
-        unsigned int base = GPIO_BASE(offset / 32);
+        void __iomem *base = GPIO_BASE(offset / 32);
         unsigned int reg;
 
         reg = __raw_readl(base + GPIO_DIR);
@@ -166,7 +167,7 @@ static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
 
 static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
-        unsigned int base = GPIO_BASE(offset / 32);
+        void __iomem *base = GPIO_BASE(offset / 32);
 
         if (value)
                 __raw_writel(1 << (offset % 32), base + GPIO_DATA_SET);
@@ -176,7 +177,7 @@ static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 
 static int gemini_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-        unsigned int base = GPIO_BASE(offset / 32);
+        void __iomem *base = GPIO_BASE(offset / 32);
 
         return (__raw_readl(base + GPIO_DATA_IN) >> (offset % 32)) & 1;
 }
diff --git a/arch/arm/mach-gemini/idle.c b/arch/arm/mach-gemini/idle.c
index 92bbd6bb600a..87dff4f5059e 100644
--- a/arch/arm/mach-gemini/idle.c
+++ b/arch/arm/mach-gemini/idle.c
@@ -13,9 +13,11 @@ static void gemini_idle(void)
          * will never wakeup... Acctualy it is not very good to enable
          * interrupts first since scheduler can miss a tick, but there is
          * no other way around this. Platforms that needs it for power saving
-         * should call enable_hlt() in init code, since by default it is
+         * should enable it in init code, since by default it is
          * disabled.
          */
+
+        /* FIXME: Enabling interrupts here is racy! */
         local_irq_enable();
         cpu_do_idle();
 }
diff --git a/arch/arm/mach-gemini/include/mach/hardware.h b/arch/arm/mach-gemini/include/mach/hardware.h
index 8c950e1d06be..98e7b0f286bf 100644
--- a/arch/arm/mach-gemini/include/mach/hardware.h
+++ b/arch/arm/mach-gemini/include/mach/hardware.h
@@ -69,6 +69,6 @@
 /*
  * macro to get at IO space when running virtually
  */
-#define IO_ADDRESS(x)   ((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)
+#define IO_ADDRESS(x)   IOMEM((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)
 
 #endif
diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c
index 020852d3bdd8..44f50dcb616d 100644
--- a/arch/arm/mach-gemini/irq.c
+++ b/arch/arm/mach-gemini/irq.c
@@ -15,6 +15,8 @@
 #include <linux/stddef.h>
 #include <linux/list.h>
 #include <linux/sched.h>
+#include <linux/cpu.h>
+
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/system_misc.h>
@@ -65,8 +67,8 @@ static struct irq_chip gemini_irq_chip = {
 
 static struct resource irq_resource = {
         .name   = "irq_handler",
-        .start  = IO_ADDRESS(GEMINI_INTERRUPT_BASE),
-        .end    = IO_ADDRESS(FIQ_STATUS(GEMINI_INTERRUPT_BASE)) + 4,
+        .start  = GEMINI_INTERRUPT_BASE,
+        .end    = FIQ_STATUS(GEMINI_INTERRUPT_BASE) + 4,
 };
 
 void __init gemini_init_irq(void)
@@ -77,7 +79,7 @@ void __init gemini_init_irq(void)
          * Disable the idle handler by default since it is buggy
          * For more info see arch/arm/mach-gemini/idle.c
          */
-        disable_hlt();
+        cpu_idle_poll_ctrl(true);
 
         request_resource(&iomem_resource, &irq_resource);
 
diff --git a/arch/arm/mach-gemini/mm.c b/arch/arm/mach-gemini/mm.c
index 51948242ec09..2c2cd284bb6a 100644
--- a/arch/arm/mach-gemini/mm.c
+++ b/arch/arm/mach-gemini/mm.c
@@ -19,57 +19,57 @@
 /* Page table mapping for I/O region */
 static struct map_desc gemini_io_desc[] __initdata = {
         {
-                .virtual        = IO_ADDRESS(GEMINI_GLOBAL_BASE),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_GLOBAL_BASE),
                 .pfn            =__phys_to_pfn(GEMINI_GLOBAL_BASE),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_UART_BASE),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_UART_BASE),
                 .pfn            = __phys_to_pfn(GEMINI_UART_BASE),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_TIMER_BASE),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_TIMER_BASE),
                 .pfn            = __phys_to_pfn(GEMINI_TIMER_BASE),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_INTERRUPT_BASE),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_INTERRUPT_BASE),
                 .pfn            = __phys_to_pfn(GEMINI_INTERRUPT_BASE),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_POWER_CTRL_BASE),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_POWER_CTRL_BASE),
                 .pfn            = __phys_to_pfn(GEMINI_POWER_CTRL_BASE),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_GPIO_BASE(0)),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(0)),
                 .pfn            = __phys_to_pfn(GEMINI_GPIO_BASE(0)),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_GPIO_BASE(1)),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(1)),
                 .pfn            = __phys_to_pfn(GEMINI_GPIO_BASE(1)),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_GPIO_BASE(2)),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(2)),
                 .pfn            = __phys_to_pfn(GEMINI_GPIO_BASE(2)),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
                 .pfn            = __phys_to_pfn(GEMINI_FLASH_CTRL_BASE),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_DRAM_CTRL_BASE),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_DRAM_CTRL_BASE),
                 .pfn            = __phys_to_pfn(GEMINI_DRAM_CTRL_BASE),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_GENERAL_DMA_BASE),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_GENERAL_DMA_BASE),
                 .pfn            = __phys_to_pfn(GEMINI_GENERAL_DMA_BASE),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
diff --git a/arch/arm/mach-gemini/include/mach/system.h b/arch/arm/mach-gemini/reset.c
index a33b5a1f8ab4..b26659759e27 100644
--- a/arch/arm/mach-gemini/include/mach/system.h
+++ b/arch/arm/mach-gemini/reset.c
@@ -14,7 +14,7 @@
 #include <mach/hardware.h>
 #include <mach/global_reg.h>
 
-static inline void arch_reset(char mode, const char *cmd)
+void gemini_restart(char mode, const char *cmd)
 {
         __raw_writel(RESET_GLOBAL | RESET_CPU1,
                      IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET);
diff --git a/arch/arm/mach-h720x/Kconfig b/arch/arm/mach-h720x/Kconfig
deleted file mode 100644
index 6bb755bcb6f5..000000000000
--- a/arch/arm/mach-h720x/Kconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-if ARCH_H720X
-
-menu "h720x Implementations"
-
-config ARCH_H7201
-        bool "gms30c7201"
-        depends on ARCH_H720X
-        select CPU_H7201
-        select ZONE_DMA
-        help
-          Say Y here if you are using the Hynix GMS30C7201 Reference Board
-
-config ARCH_H7202
-        bool "hms30c7202"
-        depends on ARCH_H720X
-        select CPU_H7202
-        select ZONE_DMA
-        help
-          Say Y here if you are using the Hynix HMS30C7202 Reference Board
-
-endmenu
-
-config CPU_H7201
-        bool
-        help
-          Select code specific to h7201 variants
-
-config CPU_H7202
-        bool
-        help
-          Select code specific to h7202 variants
-config H7202_SERIAL23
-        depends on CPU_H7202
-        bool "Use serial ports 2+3"
-        help
-          Say Y here if you wish to use serial ports 2+3. They share their
-          pins with the keyboard matrix controller, so you have to decide.
-
-
-endif
diff --git a/arch/arm/mach-h720x/Makefile b/arch/arm/mach-h720x/Makefile
deleted file mode 100644
index e4cf728948eb..000000000000
--- a/arch/arm/mach-h720x/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Common support
-obj-y := common.o
-obj-m :=
-obj-n :=
-obj-  :=
-
-# Specific board support
-
-obj-$(CONFIG_ARCH_H7201)                += h7201-eval.o
-obj-$(CONFIG_ARCH_H7202)                += h7202-eval.o
-obj-$(CONFIG_CPU_H7201)                 += cpu-h7201.o
-obj-$(CONFIG_CPU_H7202)                 += cpu-h7202.o
diff --git a/arch/arm/mach-h720x/Makefile.boot b/arch/arm/mach-h720x/Makefile.boot
deleted file mode 100644
index d875a7094dfe..000000000000
--- a/arch/arm/mach-h720x/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
-   zreladdr-$(CONFIG_ARCH_H720X)        += 0x40008000
-
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
deleted file mode 100644
index 17ef91fa3d56..000000000000
--- a/arch/arm/mach-h720x/common.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * linux/arch/arm/mach-h720x/common.c
- *
- * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *               2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *               2004 Sascha Hauer    <s.hauer@pengutronix.de>
- *
- * common stuff for Hynix h720x processors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/sched.h>
-#include <linux/mman.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/dma.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/system_misc.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/map.h>
-#include <mach/irqs.h>
-
-#include <asm/mach/dma.h>
-
-#if 0
-#define IRQDBG(args...) printk(args)
-#else
-#define IRQDBG(args...) do {} while(0)
-#endif
-
-void __init arch_dma_init(dma_t *dma)
-{
-}
-
-/*
- * Return nsecs since last timer reload
- * (timercount * (usecs perjiffie)) / (ticks per jiffie)
- */
-u32 h720x_gettimeoffset(void)
-{
-        return ((CPU_REG(TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH) * 1000;
-}
-
-/*
- * mask Global irq's
- */
-static void mask_global_irq(struct irq_data *d)
-{
-        CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << d->irq);
-}
-
-/*
- * unmask Global irq's
- */
-static void unmask_global_irq(struct irq_data *d)
-{
-        CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << d->irq);
-}
-
-
-/*
- * ack GPIO irq's
- * Ack only for edge triggered int's valid
- */
-static void inline ack_gpio_irq(struct irq_data *d)
-{
-        u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
-        u32 bit = IRQ_TO_BIT(d->irq);
-        if ( (CPU_REG (reg_base, GPIO_EDGE) & bit))
-                CPU_REG (reg_base, GPIO_CLR) = bit;
-}
-
-/*
- * mask GPIO irq's
- */
-static void inline mask_gpio_irq(struct irq_data *d)
-{
-        u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
-        u32 bit = IRQ_TO_BIT(d->irq);
-        CPU_REG (reg_base, GPIO_MASK) &= ~bit;
-}
-
-/*
- * unmask GPIO irq's
- */
-static void inline unmask_gpio_irq(struct irq_data *d)
-{
-        u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
-        u32 bit = IRQ_TO_BIT(d->irq);
-        CPU_REG (reg_base, GPIO_MASK) |= bit;
-}
-
-static void
-h720x_gpio_handler(unsigned int mask, unsigned int irq,
-                 struct irq_desc *desc)
-{
-        IRQDBG("%s irq: %d\n", __func__, irq);
-        while (mask) {
-                if (mask & 1) {
-                        IRQDBG("handling irq %d\n", irq);
-                        generic_handle_irq(irq);
-                }
-                irq++;
-                mask >>= 1;
-        }
-}
-
-static void
-h720x_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
-{
-        unsigned int mask, irq;
-
-        mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT);
-        irq = IRQ_CHAINED_GPIOA(0);
-        IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
-        h720x_gpio_handler(mask, irq, desc);
-}
-
-static void
-h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
-{
-        unsigned int mask, irq;
-        mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
-        irq = IRQ_CHAINED_GPIOB(0);
-        IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
-        h720x_gpio_handler(mask, irq, desc);
-}
-
-static void
-h720x_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
-{
-        unsigned int mask, irq;
-
-        mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT);
-        irq = IRQ_CHAINED_GPIOC(0);
-        IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
-        h720x_gpio_handler(mask, irq, desc);
-}
-
-static void
-h720x_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
-{
-        unsigned int mask, irq;
-
-        mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT);
-        irq = IRQ_CHAINED_GPIOD(0);
-        IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
-        h720x_gpio_handler(mask, irq, desc);
-}
-
-#ifdef CONFIG_CPU_H7202
-static void
-h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
-{
-        unsigned int mask, irq;
-
-        mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT);
-        irq = IRQ_CHAINED_GPIOE(0);
-        IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
-        h720x_gpio_handler(mask, irq, desc);
-}
-#endif
-
-static struct irq_chip h720x_global_chip = {
-        .irq_ack = mask_global_irq,
-        .irq_mask = mask_global_irq,
-        .irq_unmask = unmask_global_irq,
-};
-
-static struct irq_chip h720x_gpio_chip = {
-        .irq_ack = ack_gpio_irq,
-        .irq_mask = mask_gpio_irq,
-        .irq_unmask = unmask_gpio_irq,
-};
-
-/*
- * Initialize IRQ's, mask all, enable multiplexed irq's
- */
-void __init h720x_init_irq (void)
-{
-        int     irq;
-
-        /* Mask global irq's */
-        CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0;
-
-        /* Mask all multiplexed irq's */
-        CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0;
-        CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0;
-        CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0;
-        CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0;
-
-        /* Initialize global IRQ's, fast path */
-        for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
-                irq_set_chip_and_handler(irq, &h720x_global_chip,
-                                         handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-        }
-
-        /* Initialize multiplexed IRQ's, slow path */
-        for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
-                irq_set_chip_and_handler(irq, &h720x_gpio_chip,
-                                         handle_edge_irq);
-                set_irq_flags(irq, IRQF_VALID );
-        }
-        irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
-        irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
-        irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
-        irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
-
-#ifdef CONFIG_CPU_H7202
-        for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
-                irq_set_chip_and_handler(irq, &h720x_gpio_chip,
-                                         handle_edge_irq);
-                set_irq_flags(irq, IRQF_VALID );
-        }
-        irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
-#endif
-
-        /* Enable multiplexed irq's */
-        CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX;
-}
-
-static struct map_desc h720x_io_desc[] __initdata = {
-        {
-                .virtual        = IO_VIRT,
-                .pfn            = __phys_to_pfn(IO_PHYS),
-                .length         = IO_SIZE,
-                .type           = MT_DEVICE
-        },
-};
-
-/* Initialize io tables */
-void __init h720x_map_io(void)
-{
-        iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc));
-}
-
-void h720x_restart(char mode, const char *cmd)
-{
-        CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
-}
-
-static void h720x__idle(void)
-{
-        CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
-        nop();
-        nop();
-        CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN;
-        nop();
-        nop();
-}
-
-static int __init h720x_idle_init(void)
-{
-        arm_pm_idle = h720x__idle;
-        return 0;
-}
-
-arch_initcall(h720x_idle_init);
diff --git a/arch/arm/mach-h720x/common.h b/arch/arm/mach-h720x/common.h
deleted file mode 100644
index 7e738410ca93..000000000000
--- a/arch/arm/mach-h720x/common.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * linux/arch/arm/mach-h720x/common.h
- *
- * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *               2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *               2004 Sascha Hauer    <s.hauer@pengutronix.de>
- *
- * Architecture specific stuff for Hynix GMS30C7201 development board
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-extern u32 h720x_gettimeoffset(void);
-extern void __init h720x_init_irq(void);
-extern void __init h720x_map_io(void);
-extern void h720x_restart(char, const char *);
-
-#ifdef CONFIG_ARCH_H7202
-extern void h7202_timer_init(void);
-extern void __init init_hw_h7202(void);
-extern void __init h7202_init_irq(void);
-extern void __init h7202_init_time(void);
-#endif
-
-#ifdef CONFIG_ARCH_H7201
-extern void h7201_timer_init(void);
-#endif
diff --git a/arch/arm/mach-h720x/cpu-h7201.c b/arch/arm/mach-h720x/cpu-h7201.c
deleted file mode 100644
index 13c741215387..000000000000
--- a/arch/arm/mach-h720x/cpu-h7201.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * linux/arch/arm/mach-h720x/cpu-h7201.c
- *
- * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *               2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *               2004 Sascha Hauer    <s.hauer@pengutronix.de>
- *
- * processor specific stuff for the Hynix h7201
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <asm/types.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <mach/irqs.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/time.h>
-#include "common.h"
-/*
- * Timer interrupt handler
- */
-static irqreturn_t
-h7201_timer_interrupt(int irq, void *dev_id)
-{
-        CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
-        timer_tick();
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction h7201_timer_irq = {
-        .name           = "h7201 Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = h7201_timer_interrupt,
-};
-
-/*
- * Setup TIMER0 as system timer
- */
-void __init h7201_timer_init(void)
-{
-        arch_gettimeoffset = h720x_gettimeoffset;
-
-        CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
-        CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
-        CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
-        CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;
-
-        setup_irq(IRQ_TIMER0, &h7201_timer_irq);
-}
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c
deleted file mode 100644
index e2ae7e898f9d..000000000000
--- a/arch/arm/mach-h720x/cpu-h7202.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * linux/arch/arm/mach-h720x/cpu-h7202.c
- *
- * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *               2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *               2004 Sascha Hauer    <s.hauer@pengutronix.de>
- *
- * processor specific stuff for the Hynix h7202
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <asm/types.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <mach/irqs.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/time.h>
-#include <linux/device.h>
-#include <linux/serial_8250.h>
-#include "common.h"
-
-static struct resource h7202ps2_resources[] = {
-        [0] = {
-                .start  = 0x8002c000,
-                .end    = 0x8002c040,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_PS2,
-                .end    = IRQ_PS2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device h7202ps2_device = {
-        .name           = "h7202ps2",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(h7202ps2_resources),
-        .resource       = h7202ps2_resources,
-};
-
-static struct plat_serial8250_port serial_platform_data[] = {
-        {
-                .membase        = (void*)SERIAL0_VIRT,
-                .mapbase        = SERIAL0_BASE,
-                .irq            = IRQ_UART0,
-                .uartclk        = 2*1843200,
-                .regshift       = 2,
-                .iotype         = UPIO_MEM,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-        },
-        {
-                .membase        = (void*)SERIAL1_VIRT,
-                .mapbase        = SERIAL1_BASE,
-                .irq            = IRQ_UART1,
-                .uartclk        = 2*1843200,
-                .regshift       = 2,
-                .iotype         = UPIO_MEM,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-        },
-#ifdef CONFIG_H7202_SERIAL23
-        {
-                .membase        = (void*)SERIAL2_VIRT,
-                .mapbase        = SERIAL2_BASE,
-                .irq            = IRQ_UART2,
-                .uartclk        = 2*1843200,
-                .regshift       = 2,
-                .iotype         = UPIO_MEM,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-        },
-        {
-                .membase        = (void*)SERIAL3_VIRT,
-                .mapbase        = SERIAL3_BASE,
-                .irq            = IRQ_UART3,
-                .uartclk        = 2*1843200,
-                .regshift       = 2,
-                .iotype         = UPIO_MEM,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-        },
-#endif
-        { },
-};
-
-static struct platform_device serial_device = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = serial_platform_data,
-        },
-};
-
-static struct platform_device *devices[] __initdata = {
-        &h7202ps2_device,
-        &serial_device,
-};
-
-/* Although we have two interrupt lines for the timers, we only have one
- * status register which clears all pending timer interrupts on reading. So
- * we have to handle all timer interrupts in one place.
- */
-static void
-h7202_timerx_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
-{
-        unsigned int mask, irq;
-
-        mask = CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
-
-        if ( mask & TSTAT_T0INT ) {
-                timer_tick();
-                if( mask == TSTAT_T0INT )
-                        return;
-        }
-
-        mask >>= 1;
-        irq = IRQ_TIMER1;
-        while (mask) {
-                if (mask & 1)
-                        generic_handle_irq(irq);
-                irq++;
-                mask >>= 1;
-        }
-}
-
-/*
- * Timer interrupt handler
- */
-static irqreturn_t
-h7202_timer_interrupt(int irq, void *dev_id)
-{
-        h7202_timerx_demux_handler(0, NULL);
-        return IRQ_HANDLED;
-}
-
-/*
- * mask multiplexed timer IRQs
- */
-static void inline __mask_timerx_irq(unsigned int irq)
-{
-        unsigned int bit;
-        bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
-        CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit;
-}
-
-static void inline mask_timerx_irq(struct irq_data *d)
-{
-        __mask_timerx_irq(d->irq);
-}
-
-/*
- * unmask multiplexed timer IRQs
- */
-static void inline unmask_timerx_irq(struct irq_data *d)
-{
-        unsigned int bit;
-        bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1));
-        CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit;
-}
-
-static struct irq_chip h7202_timerx_chip = {
-        .irq_ack = mask_timerx_irq,
-        .irq_mask = mask_timerx_irq,
-        .irq_unmask = unmask_timerx_irq,
-};
-
-static struct irqaction h7202_timer_irq = {
-        .name           = "h7202 Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = h7202_timer_interrupt,
-};
-
-/*
- * Setup TIMER0 as system timer
- */
-void __init h7202_timer_init(void)
-{
-        arch_gettimeoffset = h720x_gettimeoffset;
-
-        CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
-        CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
-        CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
-        CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;
-
-        setup_irq(IRQ_TIMER0, &h7202_timer_irq);
-}
-
-void __init h7202_init_irq (void)
-{
-        int     irq;
-
-        CPU_REG (GPIO_E_VIRT, GPIO_MASK) = 0x0;
-
-        for (irq = IRQ_TIMER1;
-                          irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
-                __mask_timerx_irq(irq);
-                irq_set_chip_and_handler(irq, &h7202_timerx_chip,
-                                         handle_edge_irq);
-                set_irq_flags(irq, IRQF_VALID );
-        }
-        irq_set_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
-
-        h720x_init_irq();
-}
-
-void __init init_hw_h7202(void)
-{
-        /* Enable clocks */
-        CPU_REG (PMU_BASE, PMU_PLL_CTRL) |= PLL_2_EN | PLL_1_EN | PLL_3_MUTE;
-
-        CPU_REG (SERIAL0_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
-        CPU_REG (SERIAL1_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
-#ifdef CONFIG_H7202_SERIAL23
-        CPU_REG (SERIAL2_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
-        CPU_REG (SERIAL3_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
-        CPU_IO (GPIO_AMULSEL) = AMULSEL_USIN2 | AMULSEL_USOUT2 |
-                                AMULSEL_USIN3 | AMULSEL_USOUT3;
-#endif
-        (void) platform_add_devices(devices, ARRAY_SIZE(devices));
-}
diff --git a/arch/arm/mach-h720x/h7201-eval.c b/arch/arm/mach-h720x/h7201-eval.c
deleted file mode 100644
index 4fdeb686c0a9..000000000000
--- a/arch/arm/mach-h720x/h7201-eval.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * linux/arch/arm/mach-h720x/h7201-eval.c
- *
- * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *               2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *               2004 Sascha Hauer    <s.hauer@pengutronix.de>
- *
- * Architecture specific stuff for Hynix GMS30C7201 development board
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/device.h>
-
-#include <asm/setup.h>
-#include <asm/types.h>
-#include <asm/mach-types.h>
-#include <asm/page.h>
-#include <asm/mach/arch.h>
-#include <mach/hardware.h>
-#include "common.h"
-
-MACHINE_START(H7201, "Hynix GMS30C7201")
-        /* Maintainer: Robert Schwebel, Pengutronix */
-        .atag_offset    = 0x1000,
-        .map_io         = h720x_map_io,
-        .init_irq       = h720x_init_irq,
-        .init_time      = h7201_timer_init,
-        .dma_zone_size  = SZ_256M,
-        .restart        = h720x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-h720x/h7202-eval.c b/arch/arm/mach-h720x/h7202-eval.c
deleted file mode 100644
index f68e967a2062..000000000000
--- a/arch/arm/mach-h720x/h7202-eval.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * linux/arch/arm/mach-h720x/h7202-eval.c
- *
- * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *               2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *               2004 Sascha Hauer <s.hauer@pengutronix.de>
- *
- * Architecture specific stuff for Hynix HMS30C7202 development board
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/platform_device.h>
-
-#include <asm/setup.h>
-#include <asm/types.h>
-#include <asm/mach-types.h>
-#include <asm/page.h>
-#include <asm/mach/arch.h>
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include "common.h"
-
-static struct resource cirrus_resources[] = {
-        [0] = {
-                .start  = ETH0_PHYS + 0x300,
-                .end    = ETH0_PHYS + 0x300 + 0x10,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_CHAINED_GPIOB(8),
-                .end    = IRQ_CHAINED_GPIOB(8),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device cirrus_device = {
-        .name           = "cirrus-cs89x0",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(cirrus_resources),
-        .resource       = cirrus_resources,
-};
-
-static struct platform_device *devices[] __initdata = {
-        &cirrus_device,
-};
-
-/*
- * Hardware init. This is called early in initcalls
- * Place pin inits here. So you avoid adding ugly
- * #ifdef stuff to common drivers.
- * Use this only, if your bootloader is not able
- * to initialize the pins proper.
- */
-static void __init init_eval_h7202(void)
-{
-        init_hw_h7202();
-        (void) platform_add_devices(devices, ARRAY_SIZE(devices));
-
-        /* Enable interrupt on portb bit 8 (ethernet) */
-        CPU_REG (GPIO_B_VIRT, GPIO_POL) &= ~(1 << 8);
-        CPU_REG (GPIO_B_VIRT, GPIO_EN) |= (1 << 8);
-}
-
-MACHINE_START(H7202, "Hynix HMS30C7202")
-        /* Maintainer: Robert Schwebel, Pengutronix */
-        .atag_offset    = 0x100,
-        .map_io         = h720x_map_io,
-        .init_irq       = h7202_init_irq,
-        .init_time      = h7202_timer_init,
-        .init_machine   = init_eval_h7202,
-        .dma_zone_size  = SZ_256M,
-        .restart        = h720x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-h720x/include/mach/boards.h b/arch/arm/mach-h720x/include/mach/boards.h
deleted file mode 100644
index 38b8e0d61fbf..000000000000
--- a/arch/arm/mach-h720x/include/mach/boards.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/boards.h
- *
- * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *
- * This file contains the board specific defines for various devices
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_INCMACH_H
-#error Do not include this file directly. Include asm/hardware.h instead !
-#endif
-
-/* Hynix H7202 developer board specific device defines */
-#ifdef CONFIG_ARCH_H7202
-
-/* FLASH */
-#define H720X_FLASH_VIRT        0xd0000000
-#define H720X_FLASH_PHYS        0x00000000
-#define H720X_FLASH_SIZE        0x02000000
-
-/* onboard LAN controller */
-# define ETH0_PHYS              0x08000000
-
-/* Touch screen defines */
-/* GPIO Port */
-#define PEN_GPIO                GPIO_B_VIRT
-/* Bitmask for pen down interrupt */
-#define PEN_INT_BIT             (1<<7)
-/* Bitmask for pen up interrupt */
-#define PEN_ENA_BIT             (1<<6)
-/* pen up interrupt */
-#define IRQ_PEN                 IRQ_MUX_GPIOB(7)
-
-#endif
-
-/* Hynix H7201 developer board specific device defines */
-#if defined (CONFIG_ARCH_H7201)
-/* ROM DISK SPACE */
-#define ROM_DISK_BASE           0xc1800000
-#define ROM_DISK_START          0x41800000
-#define ROM_DISK_SIZE           0x00700000
-
-/* SRAM DISK SPACE */
-#define SRAM_DISK_BASE          0xf1000000
-#define SRAM_DISK_START         0x04000000
-#define SRAM_DISK_SIZE          0x00400000
-#endif
-
diff --git a/arch/arm/mach-h720x/include/mach/debug-macro.S b/arch/arm/mach-h720x/include/mach/debug-macro.S
deleted file mode 100644
index 8a46157b0582..000000000000
--- a/arch/arm/mach-h720x/include/mach/debug-macro.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/* arch/arm/mach-h720x/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#include <mach/hardware.h>
-
-                .equ    io_virt, IO_VIRT
-                .equ    io_phys, IO_PHYS
-
-                .macro  addruart, rp, rv, tmp
-                mov     \rp, #0x00020000        @ UART1
-                add     \rv, \rp, #io_virt      @ virtual address
-                add     \rp, \rp, #io_phys      @ physical base address
-                .endm
-
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #0x0]        @ UARTDR
-
-                .endm
-
-                .macro  waituart,rd,rx
-1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
-                tst     \rd, #1 << 5           @ UARTFLGUTXFF - 1 when full
-                bne     1001b
-                .endm
-
-                .macro  busyuart,rd,rx
-1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
-                tst     \rd, #1 << 3           @ UARTFLGUBUSY - 1 when busy
-                bne     1001b
-                .endm
diff --git a/arch/arm/mach-h720x/include/mach/entry-macro.S b/arch/arm/mach-h720x/include/mach/entry-macro.S
deleted file mode 100644
index 75267fad7012..000000000000
--- a/arch/arm/mach-h720x/include/mach/entry-macro.S
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for Hynix HMS720x based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-#if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202)
-                @ we could use the id register on H7202, but this is not
-                @ properly updated when we come back from asm_do_irq
-                @ without a previous return from interrupt
-                @ (see loops below in irq_svc, irq_usr)
-                @ We see unmasked pending ints only, as the masked pending ints
-                @ are not visible here
-
-                mov     \base, #0xf0000000             @ base register
-                orr     \base, \base, #0x24000         @ irqbase
-                ldr     \irqstat, [\base, #0x04]        @ get interrupt status
-#if defined (CONFIG_CPU_H7201)
-                ldr     \tmp, =0x001fffff
-#else
-                mvn     \tmp, #0xc0000000
-#endif
-                and     \irqstat, \irqstat, \tmp        @ mask out unused ints
-                mov     \irqnr, #0
-
-                mov     \tmp, #0xff00
-                orr     \tmp, \tmp, #0xff
-                tst     \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #16
-                moveq   \irqstat, \irqstat, lsr #16
-                tst     \irqstat, #255
-                addeq   \irqnr, \irqnr, #8
-                moveq   \irqstat, \irqstat, lsr #8
-                tst     \irqstat, #15
-                addeq   \irqnr, \irqnr, #4
-                moveq   \irqstat, \irqstat, lsr #4
-                tst     \irqstat, #3
-                addeq   \irqnr, \irqnr, #2
-                moveq   \irqstat, \irqstat, lsr #2
-                tst     \irqstat, #1
-                addeq   \irqnr, \irqnr, #1
-                moveq   \irqstat, \irqstat, lsr #1
-                tst     \irqstat, #1                   @ bit 0 should be set
-                .endm
-
-#else
-#error hynix processor selection missmatch
-#endif
-
diff --git a/arch/arm/mach-h720x/include/mach/h7201-regs.h b/arch/arm/mach-h720x/include/mach/h7201-regs.h
deleted file mode 100644
index 611b4947ccfc..000000000000
--- a/arch/arm/mach-h720x/include/mach/h7201-regs.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/h7201-regs.h
- *
- * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
- *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *           (C) 2004 Sascha Hauer    <s.hauer@pengutronix.de>
- *
- * This file contains the hardware definitions of the h720x processors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Do not add implementations specific defines here. This files contains
- * only defines of the onchip peripherals. Add those defines to boards.h,
- * which is included by this file.
- */
-
-#define SERIAL2_VIRT            (IO_VIRT + 0x50100)
-#define SERIAL3_VIRT            (IO_VIRT + 0x50200)
-
-/*
- * PCMCIA
- */
-#define PCMCIA0_ATT_BASE        0xe5000000
-#define PCMCIA0_ATT_SIZE        0x00200000
-#define PCMCIA0_ATT_START       0x20000000
-#define PCMCIA0_MEM_BASE        0xe5200000
-#define PCMCIA0_MEM_SIZE        0x00200000
-#define PCMCIA0_MEM_START       0x24000000
-#define PCMCIA0_IO_BASE         0xe5400000
-#define PCMCIA0_IO_SIZE         0x00200000
-#define PCMCIA0_IO_START        0x28000000
-
-#define PCMCIA1_ATT_BASE        0xe5600000
-#define PCMCIA1_ATT_SIZE        0x00200000
-#define PCMCIA1_ATT_START       0x30000000
-#define PCMCIA1_MEM_BASE        0xe5800000
-#define PCMCIA1_MEM_SIZE        0x00200000
-#define PCMCIA1_MEM_START       0x34000000
-#define PCMCIA1_IO_BASE         0xe5a00000
-#define PCMCIA1_IO_SIZE         0x00200000
-#define PCMCIA1_IO_START        0x38000000
-
-#define PRIME3C_BASE            0xf0050000
-#define PRIME3C_SIZE            0x00001000
-#define PRIME3C_START           0x10000000
-
-/* VGA Controller */
-#define VGA_RAMBASE             0x50
-#define VGA_TIMING0             0x60
-#define VGA_TIMING1             0x64
-#define VGA_TIMING2             0x68
-#define VGA_TIMING3             0x6c
-
-#define LCD_CTRL_VGA_ENABLE     0x00000100
-#define LCD_CTRL_VGA_BPP_MASK   0x00000600
-#define LCD_CTRL_VGA_4BPP       0x00000000
-#define LCD_CTRL_VGA_8BPP       0x00000200
-#define LCD_CTRL_VGA_16BPP      0x00000300
-#define LCD_CTRL_SHARE_DMA      0x00000800
-#define LCD_CTRL_VDE            0x00100000
-#define LCD_CTRL_LPE            0x00400000      /* LCD Power enable */
-#define LCD_CTRL_BLE            0x00800000      /* LCD backlight enable */
-
-#define VGA_PALETTE_BASE        (IO_VIRT + 0x10800)
diff --git a/arch/arm/mach-h720x/include/mach/h7202-regs.h b/arch/arm/mach-h720x/include/mach/h7202-regs.h
deleted file mode 100644
index 17c12eb34995..000000000000
--- a/arch/arm/mach-h720x/include/mach/h7202-regs.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/h7202-regs.h
- *
- * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
- *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *           (C) 2004 Sascha Hauer    <s.hauer@pengutronix.de>
- *
- * This file contains the hardware definitions of the h720x processors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Do not add implementations specific defines here. This files contains
- * only defines of the onchip peripherals. Add those defines to boards.h,
- * which is included by this file.
- */
-
-#define SERIAL2_OFS             0x2d000
-#define SERIAL2_BASE            (IO_PHYS + SERIAL2_OFS)
-#define SERIAL2_VIRT            (IO_VIRT + SERIAL2_OFS)
-#define SERIAL3_OFS             0x2e000
-#define SERIAL3_BASE            (IO_PHYS + SERIAL3_OFS)
-#define SERIAL3_VIRT            (IO_VIRT + SERIAL3_OFS)
-
-/* Matrix Keyboard Controller */
-#define KBD_VIRT                (IO_VIRT + 0x22000)
-#define KBD_KBCR                0x00
-#define KBD_KBSC                0x04
-#define KBD_KBTR                0x08
-#define KBD_KBVR0               0x0C
-#define KBD_KBVR1               0x10
-#define KBD_KBSR                0x18
-
-#define KBD_KBCR_SCANENABLE     (1 << 7)
-#define KBD_KBCR_NPOWERDOWN     (1 << 2)
-#define KBD_KBCR_CLKSEL_MASK    (3)
-#define KBD_KBCR_CLKSEL_PCLK2   0x0
-#define KBD_KBCR_CLKSEL_PCLK128 0x1
-#define KBD_KBCR_CLKSEL_PCLK256 0x2
-#define KBD_KBCR_CLKSEL_PCLK512 0x3
-
-#define KBD_KBSR_INTR           (1 << 0)
-#define KBD_KBSR_WAKEUP         (1 << 1)
-
-/* USB device controller */
-
-#define USBD_BASE               (IO_VIRT + 0x12000)
-#define USBD_LENGTH             0x3C
-
-#define USBD_GCTRL              0x00
-#define USBD_EPCTRL             0x04
-#define USBD_INTMASK            0x08
-#define USBD_INTSTAT            0x0C
-#define USBD_PWR                0x10
-#define USBD_DMARXTX            0x14
-#define USBD_DEVID              0x18
-#define USBD_DEVCLASS           0x1C
-#define USBD_INTCLASS           0x20
-#define USBD_SETUP0             0x24
-#define USBD_SETUP1             0x28
-#define USBD_ENDP0RD            0x2C
-#define USBD_ENDP0WT            0x30
-#define USBD_ENDP1RD            0x34
-#define USBD_ENDP2WT            0x38
-
-/* PS/2 port */
-#define PSDATA 0x00
-#define PSSTAT 0x04
-#define PSSTAT_TXEMPTY (1<<0)
-#define PSSTAT_TXBUSY (1<<1)
-#define PSSTAT_RXFULL (1<<2)
-#define PSSTAT_RXBUSY (1<<3)
-#define PSSTAT_CLKIN (1<<4)
-#define PSSTAT_DATAIN (1<<5)
-#define PSSTAT_PARITY (1<<6)
-
-#define PSCONF 0x08
-#define PSCONF_ENABLE (1<<0)
-#define PSCONF_TXINTEN (1<<2)
-#define PSCONF_RXINTEN (1<<3)
-#define PSCONF_FORCECLKLOW (1<<4)
-#define PSCONF_FORCEDATLOW (1<<5)
-#define PSCONF_LCE (1<<6)
-
-#define PSINTR 0x0C
-#define PSINTR_TXINT (1<<0)
-#define PSINTR_RXINT (1<<1)
-#define PSINTR_PAR (1<<2)
-#define PSINTR_RXTO (1<<3)
-#define PSINTR_TXTO (1<<4)
-
-#define PSTDLO 0x10 /* clk low before start transmission */
-#define PSTPRI 0x14 /* PRI clock */
-#define PSTXMT 0x18 /* maximum transmission time */
-#define PSTREC 0x20 /* maximum receive time */
-#define PSPWDN 0x3c
-
-/* ADC converter */
-#define ADC_BASE                (IO_VIRT + 0x29000)
-#define ADC_CR                  0x00
-#define ADC_TSCTRL              0x04
-#define ADC_BT_CTRL             0x08
-#define ADC_MC_CTRL             0x0C
-#define ADC_STATUS              0x10
-
-/* ADC control register bits */
-#define ADC_CR_PW_CTRL          0x80
-#define ADC_CR_DIRECTC          0x04
-#define ADC_CR_CONTIME_NO       0x00
-#define ADC_CR_CONTIME_2        0x04
-#define ADC_CR_CONTIME_4        0x08
-#define ADC_CR_CONTIME_ADE      0x0c
-#define ADC_CR_LONGCALTIME      0x01
-
-/* ADC touch panel register bits */
-#define ADC_TSCTRL_ENABLE       0x80
-#define ADC_TSCTRL_INTR         0x40
-#define ADC_TSCTRL_SWBYPSS      0x20
-#define ADC_TSCTRL_SWINVT       0x10
-#define ADC_TSCTRL_S400         0x03
-#define ADC_TSCTRL_S200         0x02
-#define ADC_TSCTRL_S100         0x01
-#define ADC_TSCTRL_S50          0x00
-
-/* ADC Interrupt Status Register bits */
-#define ADC_STATUS_TS_BIT       0x80
-#define ADC_STATUS_MBT_BIT      0x40
-#define ADC_STATUS_BBT_BIT      0x20
-#define ADC_STATUS_MIC_BIT      0x10
-
-/* Touch data registers */
-#define ADC_TS_X0X1             0x30
-#define ADC_TS_X2X3             0x34
-#define ADC_TS_Y0Y1             0x38
-#define ADC_TS_Y2Y3             0x3c
-#define ADC_TS_X4X5             0x40
-#define ADC_TS_X6X7             0x44
-#define ADC_TS_Y4Y5             0x48
-#define ADC_TS_Y6Y7             0x50
-
-/* battery data */
-#define ADC_MB_DATA             0x54
-#define ADC_BB_DATA             0x58
-
-/* Sound data register */
-#define ADC_SD_DAT0             0x60
-#define ADC_SD_DAT1             0x64
-#define ADC_SD_DAT2             0x68
-#define ADC_SD_DAT3             0x6c
-#define ADC_SD_DAT4             0x70
-#define ADC_SD_DAT5             0x74
-#define ADC_SD_DAT6             0x78
-#define ADC_SD_DAT7             0x7c
diff --git a/arch/arm/mach-h720x/include/mach/hardware.h b/arch/arm/mach-h720x/include/mach/hardware.h
deleted file mode 100644
index c55a52c6541d..000000000000
--- a/arch/arm/mach-h720x/include/mach/hardware.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/hardware.h
- *
- * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
- *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *
- * This file contains the hardware definitions of the h720x processors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Do not add implementations specific defines here. This files contains
- * only defines of the onchip peripherals. Add those defines to boards.h,
- * which is included by this file.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#define IOCLK (3686400L)
-
-/* Onchip peripherals */
-
-#define IO_VIRT                 0xf0000000      /* IO peripherals */
-#define IO_PHYS                 0x80000000
-#define IO_SIZE                 0x00050000
-
-#ifdef CONFIG_CPU_H7202
-#include "h7202-regs.h"
-#elif defined CONFIG_CPU_H7201
-#include "h7201-regs.h"
-#else
-#error machine definition mismatch
-#endif
-
-/* Macro to access the CPU IO */
-#define CPU_IO(x) (*(volatile u32*)(x))
-
-/* Macro to access general purpose regs (base, offset) */
-#define CPU_REG(x,y) CPU_IO(x+y)
-
-/* Macro to access irq related regs */
-#define IRQ_REG(x) CPU_REG(IRQC_VIRT,x)
-
-/* CPU registers */
-/* general purpose I/O */
-#define GPIO_VIRT(x)            (IO_VIRT + 0x23000 + ((x)<<5))
-#define GPIO_A_VIRT             (GPIO_VIRT(0))
-#define GPIO_B_VIRT             (GPIO_VIRT(1))
-#define GPIO_C_VIRT             (GPIO_VIRT(2))
-#define GPIO_D_VIRT             (GPIO_VIRT(3))
-#define GPIO_E_VIRT             (GPIO_VIRT(4))
-#define GPIO_AMULSEL            (GPIO_VIRT(0) + 0xA4)
-
-#define AMULSEL_USIN2   (1<<5)
-#define AMULSEL_USOUT2  (1<<6)
-#define AMULSEL_USIN3   (1<<13)
-#define AMULSEL_USOUT3  (1<<14)
-#define AMULSEL_IRDIN   (1<<15)
-#define AMULSEL_IRDOUT  (1<<7)
-
-/* Register offsets general purpose I/O */
-#define GPIO_DATA               0x00
-#define GPIO_DIR                0x04
-#define GPIO_MASK               0x08
-#define GPIO_STAT               0x0C
-#define GPIO_EDGE               0x10
-#define GPIO_CLR                0x14
-#define GPIO_POL                0x18
-#define GPIO_EN                 0x1C
-
-/*interrupt controller */
-#define IRQC_VIRT               (IO_VIRT + 0x24000)
-/* register offset interrupt controller */
-#define IRQC_IER                0x00
-#define IRQC_ISR                0x04
-
-/* timer unit */
-#define TIMER_VIRT              (IO_VIRT + 0x25000)
-/* Register offsets timer unit */
-#define TM0_PERIOD              0x00
-#define TM0_COUNT               0x08
-#define TM0_CTRL                0x10
-#define TM1_PERIOD              0x20
-#define TM1_COUNT               0x28
-#define TM1_CTRL                0x30
-#define TM2_PERIOD              0x40
-#define TM2_COUNT               0x48
-#define TM2_CTRL                0x50
-#define TIMER_TOPCTRL           0x60
-#define TIMER_TOPSTAT           0x64
-#define T64_COUNTL              0x80
-#define T64_COUNTH              0x84
-#define T64_CTRL                0x88
-#define T64_BASEL               0x94
-#define T64_BASEH               0x98
-/* Bitmaks timer unit TOPSTAT reg */
-#define TSTAT_T0INT             0x1
-#define TSTAT_T1INT             0x2
-#define TSTAT_T2INT             0x4
-#define TSTAT_T3INT             0x8
-/* Bit description of TMx_CTRL register */
-#define TM_START                0x1
-#define TM_REPEAT               0x2
-#define TM_RESET                0x4
-/* Bit description of TIMER_CTRL register */
-#define ENABLE_TM0_INTR         0x1
-#define ENABLE_TM1_INTR         0x2
-#define ENABLE_TM2_INTR         0x4
-#define TIMER_ENABLE_BIT        0x8
-#define ENABLE_TIMER64          0x10
-#define ENABLE_TIMER64_INT      0x20
-
-/* PMU & PLL */
-#define PMU_BASE                (IO_VIRT + 0x1000)
-#define PMU_MODE                0x00
-#define PMU_STAT                0x20
-#define PMU_PLL_CTRL            0x28
-
-/* PMU Mode bits */
-#define PMU_MODE_SLOW           0x00
-#define PMU_MODE_RUN            0x01
-#define PMU_MODE_IDLE           0x02
-#define PMU_MODE_SLEEP          0x03
-#define PMU_MODE_INIT           0x04
-#define PMU_MODE_DEEPSLEEP      0x07
-#define PMU_MODE_WAKEUP         0x08
-
-/* PMU ... */
-#define PLL_2_EN                0x8000
-#define PLL_1_EN                0x4000
-#define PLL_3_MUTE              0x0080
-
-/* Control bits for PMU/ PLL */
-#define PMU_WARMRESET           0x00010000
-#define PLL_CTRL_MASK23         0x000080ff
-
-/* LCD Controller */
-#define LCD_BASE                (IO_VIRT + 0x10000)
-#define LCD_CTRL                0x00
-#define LCD_STATUS              0x04
-#define LCD_STATUS_M            0x08
-#define LCD_INTERRUPT           0x0C
-#define LCD_DBAR                0x10
-#define LCD_DCAR                0x14
-#define LCD_TIMING0             0x20
-#define LCD_TIMING1             0x24
-#define LCD_TIMING2             0x28
-#define LCD_TEST                0x40
-
-/* LCD Control Bits */
-#define LCD_CTRL_LCD_ENABLE     0x00000001
-/* Bits per pixel */
-#define LCD_CTRL_LCD_BPP_MASK   0x00000006
-#define LCD_CTRL_LCD_4BPP       0x00000000
-#define LCD_CTRL_LCD_8BPP       0x00000002
-#define LCD_CTRL_LCD_16BPP      0x00000004
-#define LCD_CTRL_LCD_BW         0x00000008
-#define LCD_CTRL_LCD_TFT        0x00000010
-#define LCD_CTRL_BGR            0x00001000
-#define LCD_CTRL_LCD_VCOMP      0x00080000
-#define LCD_CTRL_LCD_MONO8      0x00200000
-#define LCD_CTRL_LCD_PWR        0x00400000
-#define LCD_CTRL_LCD_BLE        0x00800000
-#define LCD_CTRL_LDBUSEN        0x01000000
-
-/* Palette */
-#define LCD_PALETTE_BASE        (IO_VIRT + 0x10400)
-
-/* Serial ports */
-#define SERIAL0_OFS             0x20000
-#define SERIAL0_VIRT            (IO_VIRT + SERIAL0_OFS)
-#define SERIAL0_BASE            (IO_PHYS + SERIAL0_OFS)
-
-#define SERIAL1_OFS             0x21000
-#define SERIAL1_VIRT            (IO_VIRT + SERIAL1_OFS)
-#define SERIAL1_BASE            (IO_PHYS + SERIAL1_OFS)
-
-#define SERIAL_ENABLE           0x30
-#define SERIAL_ENABLE_EN        (1<<0)
-
-/* General defines to pacify gcc */
-
-#define __ASM_ARCH_HARDWARE_INCMACH_H
-#include "boards.h"
-#undef __ASM_ARCH_HARDWARE_INCMACH_H
-
-#endif                          /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-h720x/include/mach/irqs.h b/arch/arm/mach-h720x/include/mach/irqs.h
deleted file mode 100644
index 430a92b492f1..000000000000
--- a/arch/arm/mach-h720x/include/mach/irqs.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/irqs.h
- *
- * Copyright (C) 2000 Jungjun Kim
- *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#if defined (CONFIG_CPU_H7201)
-
-#define IRQ_PMU         0               /* 0x000001 */
-#define IRQ_DMA         1               /* 0x000002 */
-#define IRQ_LCD         2               /* 0x000004 */
-#define IRQ_VGA         3               /* 0x000008 */
-#define IRQ_PCMCIA1     4               /* 0x000010 */
-#define IRQ_PCMCIA2     5               /* 0x000020 */
-#define IRQ_AFE         6               /* 0x000040 */
-#define IRQ_AIC         7               /* 0x000080 */
-#define IRQ_KEYBOARD    8               /* 0x000100 */
-#define IRQ_TIMER0      9               /* 0x000200 */
-#define IRQ_RTC         10              /* 0x000400 */
-#define IRQ_SOUND       11              /* 0x000800 */
-#define IRQ_USB         12              /* 0x001000 */
-#define IRQ_IrDA        13              /* 0x002000 */
-#define IRQ_UART0       14              /* 0x004000 */
-#define IRQ_UART1       15              /* 0x008000 */
-#define IRQ_SPI         16              /* 0x010000 */
-#define IRQ_GPIOA       17              /* 0x020000 */
-#define IRQ_GPIOB       18              /* 0x040000 */
-#define IRQ_GPIOC       19              /* 0x080000 */
-#define IRQ_GPIOD       20              /* 0x100000 */
-#define IRQ_CommRX      21              /* 0x200000 */
-#define IRQ_CommTX      22              /* 0x400000 */
-#define IRQ_Soft        23              /* 0x800000 */
-
-#define NR_GLBL_IRQS    24
-
-#define IRQ_CHAINED_GPIOA(x)  (NR_GLBL_IRQS + x)
-#define IRQ_CHAINED_GPIOB(x)  (IRQ_CHAINED_GPIOA(32) + x)
-#define IRQ_CHAINED_GPIOC(x)  (IRQ_CHAINED_GPIOB(32) + x)
-#define IRQ_CHAINED_GPIOD(x)  (IRQ_CHAINED_GPIOC(32) + x)
-#define NR_IRQS               IRQ_CHAINED_GPIOD(32)
-
-/* Enable mask for multiplexed interrupts */
-#define IRQ_ENA_MUX     (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) \
-                        | (1<<IRQ_GPIOC) | (1<<IRQ_GPIOD)
-
-
-#elif defined (CONFIG_CPU_H7202)
-
-#define IRQ_PMU         0               /* 0x00000001 */
-#define IRQ_DMA         1               /* 0x00000002 */
-#define IRQ_LCD         2               /* 0x00000004 */
-#define IRQ_SOUND       3               /* 0x00000008 */
-#define IRQ_I2S         4               /* 0x00000010 */
-#define IRQ_USB         5               /* 0x00000020 */
-#define IRQ_MMC         6               /* 0x00000040 */
-#define IRQ_RTC         7               /* 0x00000080 */
-#define IRQ_UART0       8               /* 0x00000100 */
-#define IRQ_UART1       9               /* 0x00000200 */
-#define IRQ_UART2       10              /* 0x00000400 */
-#define IRQ_UART3       11              /* 0x00000800 */
-#define IRQ_KBD         12              /* 0x00001000 */
-#define IRQ_PS2         13              /* 0x00002000 */
-#define IRQ_AIC         14              /* 0x00004000 */
-#define IRQ_TIMER0      15              /* 0x00008000 */
-#define IRQ_TIMERX      16              /* 0x00010000 */
-#define IRQ_WDT         17              /* 0x00020000 */
-#define IRQ_CAN0        18              /* 0x00040000 */
-#define IRQ_CAN1        19              /* 0x00080000 */
-#define IRQ_EXT0        20              /* 0x00100000 */
-#define IRQ_EXT1        21              /* 0x00200000 */
-#define IRQ_GPIOA       22              /* 0x00400000 */
-#define IRQ_GPIOB       23              /* 0x00800000 */
-#define IRQ_GPIOC       24              /* 0x01000000 */
-#define IRQ_GPIOD       25              /* 0x02000000 */
-#define IRQ_GPIOE       26              /* 0x04000000 */
-#define IRQ_COMMRX      27              /* 0x08000000 */
-#define IRQ_COMMTX      28              /* 0x10000000 */
-#define IRQ_SMC         29              /* 0x20000000 */
-#define IRQ_Soft        30              /* 0x40000000 */
-#define IRQ_RESERVED1   31              /* 0x80000000 */
-#define NR_GLBL_IRQS    32
-
-#define NR_TIMERX_IRQS  3
-
-#define IRQ_CHAINED_GPIOA(x)  (NR_GLBL_IRQS + x)
-#define IRQ_CHAINED_GPIOB(x)  (IRQ_CHAINED_GPIOA(32) + x)
-#define IRQ_CHAINED_GPIOC(x)  (IRQ_CHAINED_GPIOB(32) + x)
-#define IRQ_CHAINED_GPIOD(x)  (IRQ_CHAINED_GPIOC(32) + x)
-#define IRQ_CHAINED_GPIOE(x)  (IRQ_CHAINED_GPIOD(32) + x)
-#define IRQ_CHAINED_TIMERX(x) (IRQ_CHAINED_GPIOE(32) + x)
-#define IRQ_TIMER1            (IRQ_CHAINED_TIMERX(0))
-#define IRQ_TIMER2            (IRQ_CHAINED_TIMERX(1))
-#define IRQ_TIMER64B          (IRQ_CHAINED_TIMERX(2))
-
-#define NR_IRQS         (IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS))
-
-/* Enable mask for multiplexed interrupts */
-#define IRQ_ENA_MUX     (1<<IRQ_TIMERX) | (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) | \
-                        (1<<IRQ_GPIOC)  | (1<<IRQ_GPIOD) | (1<<IRQ_GPIOE) | \
-                        (1<<IRQ_TIMERX)
-
-#else
-#error cpu definition mismatch
-#endif
-
-/* decode irq number to register number */
-#define IRQ_TO_REGNO(irq) ((irq - NR_GLBL_IRQS) >> 5)
-#define IRQ_TO_BIT(irq) (1 << ((irq - NR_GLBL_IRQS) % 32))
-
-#endif
diff --git a/arch/arm/mach-h720x/include/mach/isa-dma.h b/arch/arm/mach-h720x/include/mach/isa-dma.h
deleted file mode 100644
index 3eafb3f163c0..000000000000
--- a/arch/arm/mach-h720x/include/mach/isa-dma.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/isa-dma.h
- *
- * Architecture DMA routes
- *
- * Copyright (C) 1997.1998 Russell King
- */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-#if defined (CONFIG_CPU_H7201)
-#define MAX_DMA_CHANNELS        3
-#elif defined (CONFIG_CPU_H7202)
-#define MAX_DMA_CHANNELS        4
-#else
-#error processor definition missmatch
-#endif
-
-#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-h720x/include/mach/uncompress.h b/arch/arm/mach-h720x/include/mach/uncompress.h
deleted file mode 100644
index 43e343c4b50a..000000000000
--- a/arch/arm/mach-h720x/include/mach/uncompress.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/uncompress.h
- *
- * Copyright (C) 2001-2002 Jungjun Kim
- */
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#include <mach/hardware.h>
-
-#define LSR     0x14
-#define TEMPTY  0x40
-
-static inline void putc(int c)
-{
-        volatile unsigned char *p = (volatile unsigned char *)(IO_PHYS+0x20000);
-
-        /* wait until transmit buffer is empty */
-        while((p[LSR] & TEMPTY) == 0x0)
-                barrier();
-
-        /* write next character */
-        *p = c;
-}
-
-static inline void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-
-#endif
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index 44b12f9c1584..cd9fcb1cd7ab 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -12,6 +12,7 @@ config ARCH_HIGHBANK
         select CPU_V7
         select GENERIC_CLOCKEVENTS
         select HAVE_ARM_SCU
+        select HAVE_ARM_TWD if LOCAL_TIMERS
         select HAVE_SMP
         select MAILBOX
         select PL320_MBOX
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index a4f9f50247d4..76c1170b3528 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -32,7 +32,6 @@
 #include <asm/cacheflush.h>
 #include <asm/cputype.h>
 #include <asm/smp_plat.h>
-#include <asm/smp_twd.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/timer-sp.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -119,10 +118,10 @@ static void __init highbank_timer_init(void)
         sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1");
         sp804_clockevents_init(timer_base, irq, "timer0");
 
-        twd_local_timer_of_register();
-
         arch_timer_of_register();
         arch_timer_sched_clock_init();
+
+        clocksource_of_init();
 }
 
 static void highbank_power_off(void)
diff --git a/arch/arm/mach-highbank/hotplug.c b/arch/arm/mach-highbank/hotplug.c
index 890cae23c12a..a019e4e86e51 100644
--- a/arch/arm/mach-highbank/hotplug.c
+++ b/arch/arm/mach-highbank/hotplug.c
@@ -14,7 +14,6 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #include <linux/kernel.h>
-
 #include <asm/cacheflush.h>
 
 #include "core.h"
diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c
index 8797a7001720..a984573e0d02 100644
--- a/arch/arm/mach-highbank/platsmp.c
+++ b/arch/arm/mach-highbank/platsmp.c
@@ -17,7 +17,6 @@
 #include <linux/init.h>
 #include <linux/smp.h>
 #include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
 
 #include <asm/smp_scu.h>
 
@@ -25,11 +24,6 @@
 
 extern void secondary_startup(void);
 
-static void __cpuinit highbank_secondary_init(unsigned int cpu)
-{
-        gic_secondary_init(0);
-}
-
 static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         highbank_set_cpu_jump(cpu, secondary_startup);
@@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
 struct smp_operations highbank_smp_ops __initdata = {
         .smp_init_cpus          = highbank_smp_init_cpus,
         .smp_prepare_cpus       = highbank_smp_prepare_cpus,
-        .smp_secondary_init     = highbank_secondary_init,
         .smp_boot_secondary     = highbank_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_die                = highbank_cpu_die,
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 4c9c6f9d2c55..2ebc97e16b91 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -83,24 +83,12 @@ config ARCH_MXC_IOMUX_V3
 config ARCH_MX1
         bool
 
-config MACH_MX21
-        bool
-
 config ARCH_MX25
         bool
 
 config MACH_MX27
         bool
 
-config ARCH_MX5
-        bool
-
-config ARCH_MX51
-        bool
-
-config ARCH_MX53
-        bool
-
 config SOC_IMX1
         bool
         select ARCH_MX1
@@ -114,7 +102,6 @@ config SOC_IMX21
         select COMMON_CLK
         select CPU_ARM926T
         select IMX_HAVE_IOMUX_V1
-        select MACH_MX21
         select MXC_AVIC
 
 config SOC_IMX25
@@ -155,7 +142,6 @@ config SOC_IMX35
 config SOC_IMX5
         bool
         select ARCH_HAS_CPUFREQ
-        select ARCH_MX5
         select ARCH_MXC_IOMUX_V3
         select COMMON_CLK
         select CPU_V7
@@ -163,8 +149,7 @@ config SOC_IMX5
 
 config  SOC_IMX51
         bool
-        select ARCH_MX5
-        select ARCH_MX51
+        select HAVE_IMX_SRC
         select PINCTRL
         select PINCTRL_IMX51
         select SOC_IMX5
@@ -481,8 +466,6 @@ config MACH_MX31ADS_WM1133_EV1
         depends on MACH_MX31ADS
         depends on MFD_WM8350_I2C
         depends on REGULATOR_WM8350 = y
-        select MFD_WM8350_CONFIG_MODE_0
-        select MFD_WM8352_CONFIG_MODE_0
         help
           Include support for the Wolfson Microelectronics 1133-EV1 PMU
           and audio module for the MX31ADS platform.
@@ -789,9 +772,8 @@ comment "Device tree only"
 
 config  SOC_IMX53
         bool "i.MX53 support"
-        select ARCH_MX5
-        select ARCH_MX53
         select HAVE_CAN_FLEXCAN if CAN
+        select HAVE_IMX_SRC
         select IMX_HAVE_PLATFORM_IMX2_WDT
         select PINCTRL
         select PINCTRL_IMX53
@@ -811,7 +793,8 @@ config SOC_IMX6Q
         select ARM_GIC
         select COMMON_CLK
         select CPU_V7
-        select HAVE_ARM_SCU
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
         select HAVE_CAN_FLEXCAN if CAN
         select HAVE_IMX_GPC
         select HAVE_IMX_MMDC
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index c4ce0906d76a..fbe60a145344 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-
 obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
 
 imx5-pm-$(CONFIG_PM) += pm-imx5.o
-obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o
+obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y)
 
 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
                             clk-pfd.o clk-busy.o clk.o
@@ -27,10 +27,9 @@ obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
-obj-$(CONFIG_CPU_FREQ_IMX)    += cpufreq.o
 
 ifeq ($(CONFIG_CPU_IDLE),y)
-obj-y += cpuidle.o
+obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
 obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
 endif
 
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
deleted file mode 100644
index 41ba1bb0437b..000000000000
--- a/arch/arm/mach-imx/Makefile.boot
+++ /dev/null
@@ -1,35 +0,0 @@
-zreladdr-$(CONFIG_SOC_IMX1)     += 0x08008000
-params_phys-$(CONFIG_SOC_IMX1)  := 0x08000100
-initrd_phys-$(CONFIG_SOC_IMX1)  := 0x08800000
-
-zreladdr-$(CONFIG_SOC_IMX21)    += 0xC0008000
-params_phys-$(CONFIG_SOC_IMX21) := 0xC0000100
-initrd_phys-$(CONFIG_SOC_IMX21) := 0xC0800000
-
-zreladdr-$(CONFIG_SOC_IMX25)    += 0x80008000
-params_phys-$(CONFIG_SOC_IMX25) := 0x80000100
-initrd_phys-$(CONFIG_SOC_IMX25) := 0x80800000
-
-zreladdr-$(CONFIG_SOC_IMX27)    += 0xA0008000
-params_phys-$(CONFIG_SOC_IMX27) := 0xA0000100
-initrd_phys-$(CONFIG_SOC_IMX27) := 0xA0800000
-
-zreladdr-$(CONFIG_SOC_IMX31)    += 0x80008000
-params_phys-$(CONFIG_SOC_IMX31) := 0x80000100
-initrd_phys-$(CONFIG_SOC_IMX31) := 0x80800000
-
-zreladdr-$(CONFIG_SOC_IMX35)    += 0x80008000
-params_phys-$(CONFIG_SOC_IMX35) := 0x80000100
-initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000
-
-zreladdr-$(CONFIG_SOC_IMX51)    += 0x90008000
-params_phys-$(CONFIG_SOC_IMX51) := 0x90000100
-initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000
-
-zreladdr-$(CONFIG_SOC_IMX53)    += 0x70008000
-params_phys-$(CONFIG_SOC_IMX53) := 0x70000100
-initrd_phys-$(CONFIG_SOC_IMX53) := 0x70800000
-
-zreladdr-$(CONFIG_SOC_IMX6Q)    += 0x10008000
-params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
-initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c
index 0eff23ed92b9..e163ec7a8441 100644
--- a/arch/arm/mach-imx/avic.c
+++ b/arch/arm/mach-imx/avic.c
@@ -51,11 +51,9 @@
 
 #define AVIC_NUM_IRQS 64
 
-void __iomem *avic_base;
+static void __iomem *avic_base;
 static struct irq_domain *domain;
 
-static u32 avic_saved_mask_reg[2];
-
 #ifdef CONFIG_MXC_IRQ_PRIOR
 static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
 {
@@ -113,6 +111,8 @@ static struct mxc_extra_irq avic_extra_irq = {
 };
 
 #ifdef CONFIG_PM
+static u32 avic_saved_mask_reg[2];
+
 static void avic_irq_suspend(struct irq_data *d)
 {
         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
diff --git a/arch/arm/mach-imx/clk-busy.c b/arch/arm/mach-imx/clk-busy.c
index 1ab91b5209e6..4bb1bc419b79 100644
--- a/arch/arm/mach-imx/clk-busy.c
+++ b/arch/arm/mach-imx/clk-busy.c
@@ -147,7 +147,7 @@ static int clk_busy_mux_set_parent(struct clk_hw *hw, u8 index)
         return ret;
 }
 
-struct clk_ops clk_busy_mux_ops = {
+static struct clk_ops clk_busy_mux_ops = {
         .get_parent = clk_busy_mux_get_parent,
         .set_parent = clk_busy_mux_set_parent,
 };
@@ -169,7 +169,7 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
 
         busy->mux.reg = reg;
         busy->mux.shift = shift;
-        busy->mux.width = width;
+        busy->mux.mask = BIT(width) - 1;
         busy->mux.lock = &imx_ccm_lock;
         busy->mux_ops = &clk_mux_ops;
 
diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c
index cc49c7ae186e..a63e415609a8 100644
--- a/arch/arm/mach-imx/clk-gate2.c
+++ b/arch/arm/mach-imx/clk-gate2.c
@@ -15,6 +15,7 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/string.h>
+#include "clk.h"
 
 /**
  * DOC: basic gatable clock which can gate and ungate it's ouput
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 30b3242a7d49..c3cfa4116dc0 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -86,10 +86,12 @@ enum mx27_clks {
 };
 
 static struct clk *clk[clk_max];
+static struct clk_onecell_data clk_data;
 
 int __init mx27_clocks_init(unsigned long fref)
 {
         int i;
+        struct device_node *np;
 
         clk[dummy] = imx_clk_fixed("dummy", 0);
         clk[ckih] = imx_clk_fixed("ckih", fref);
@@ -198,6 +200,13 @@ int __init mx27_clocks_init(unsigned long fref)
                         pr_err("i.MX27 clk %d: register failed with %ld\n",
                                 i, PTR_ERR(clk[i]));
 
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
+        if (np) {
+                clk_data.clks = clk;
+                clk_data.clk_num = ARRAY_SIZE(clk);
+                of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+        }
+
         clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
         clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0");
         clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
@@ -276,10 +285,8 @@ int __init mx27_clocks_init(unsigned long fref)
         clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);
         clk_register_clkdev(clk[rtc_ipg_gate], NULL, "imx21-rtc");
         clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
-        clk_register_clkdev(clk[cpu_div], "cpu", NULL);
+        clk_register_clkdev(clk[cpu_div], NULL, "cpufreq-cpu0.0");
         clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
-        clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0");
-        clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1");
 
         mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
 
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 0f39f8c93b94..2bc623b414c1 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -281,7 +281,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL);
         clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL);
         clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
-        clk_register_clkdev(clk[cpu_podf], "cpu", NULL);
+        clk_register_clkdev(clk[cpu_podf], NULL, "cpufreq-cpu0.0");
         clk_register_clkdev(clk[iim_gate], "iim", NULL);
         clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
         clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
@@ -362,9 +362,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
         clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
         clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
-        clk_register_clkdev(clk[ipu_gate], "bus", "40000000.ipu");
-        clk_register_clkdev(clk[ipu_di0_gate], "di0", "40000000.ipu");
-        clk_register_clkdev(clk[ipu_di1_gate], "di1", "40000000.ipu");
         clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0");
         clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0");
         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0");
@@ -471,10 +468,6 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
         clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
         clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0");
-        clk_register_clkdev(clk[ipu_gate], "bus", "18000000.ipu");
-        clk_register_clkdev(clk[ipu_di0_gate], "di0", "18000000.ipu");
-        clk_register_clkdev(clk[ipu_di1_gate], "di1", "18000000.ipu");
-        clk_register_clkdev(clk[ipu_gate], "hsp", "18000000.ipu");
         clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0");
         clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0");
         clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0");
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
index abff350ba24c..c1eaee346954 100644
--- a/arch/arm/mach-imx/clk-pllv1.c
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -78,7 +78,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
         return ll;
 }
 
-struct clk_ops clk_pllv1_ops = {
+static struct clk_ops clk_pllv1_ops = {
         .recalc_rate = clk_pllv1_recalc_rate,
 };
 
diff --git a/arch/arm/mach-imx/clk-pllv2.c b/arch/arm/mach-imx/clk-pllv2.c
index 0440379e3628..20889d59b44d 100644
--- a/arch/arm/mach-imx/clk-pllv2.c
+++ b/arch/arm/mach-imx/clk-pllv2.c
@@ -229,7 +229,7 @@ static void clk_pllv2_unprepare(struct clk_hw *hw)
         __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
 }
 
-struct clk_ops clk_pllv2_ops = {
+static struct clk_ops clk_pllv2_ops = {
         .prepare = clk_pllv2_prepare,
         .unprepare = clk_pllv2_unprepare,
         .recalc_rate = clk_pllv2_recalc_rate,
diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c
index f5e8be8e7f11..37e884ed1cd4 100644
--- a/arch/arm/mach-imx/clk.c
+++ b/arch/arm/mach-imx/clk.c
@@ -1,3 +1,4 @@
 #include <linux/spinlock.h>
+#include "clk.h"
 
 DEFINE_SPINLOCK(imx_ccm_lock);
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 5bf4a97ab241..9fea2522d7a3 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -113,7 +113,6 @@ extern void imx_set_cpu_jump(int cpu, void *jump_addr);
 extern u32 imx_get_cpu_arg(int cpu);
 extern void imx_set_cpu_arg(int cpu, u32 arg);
 extern void v7_cpu_resume(void);
-extern u32 *pl310_get_save_ptr(void);
 #ifdef CONFIG_SMP
 extern void v7_secondary_startup(void);
 extern void imx_scu_map_io(void);
@@ -124,8 +123,6 @@ static inline void imx_scu_map_io(void) {}
 static inline void imx_smp_prepare(void) {}
 static inline void imx_scu_standby_enable(void) {}
 #endif
-extern void imx_enable_cpu(int cpu, bool enable);
-extern void imx_set_cpu_jump(int cpu, void *jump_addr);
 extern void imx_src_init(void);
 extern void imx_src_prepare_restart(void);
 extern void imx_gpc_init(void);
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c
index d7ce72252a4e..c1c99a72c6a1 100644
--- a/arch/arm/mach-imx/cpu-imx5.c
+++ b/arch/arm/mach-imx/cpu-imx5.c
@@ -18,6 +18,7 @@
 #include <linux/io.h>
 
 #include "hardware.h"
+#include "common.h"
 
 static int mx5_cpu_rev = -1;
 
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 03fcbd082593..e70e3acbf9bd 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -3,6 +3,7 @@
 #include <linux/io.h>
 
 #include "hardware.h"
+#include "common.h"
 
 unsigned int __mxc_cpu_type;
 EXPORT_SYMBOL(__mxc_cpu_type);
diff --git a/arch/arm/mach-imx/cpu_op-mx51.c b/arch/arm/mach-imx/cpu_op-mx51.c
deleted file mode 100644
index b9ef692b61a2..000000000000
--- a/arch/arm/mach-imx/cpu_op-mx51.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/bug.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-
-#include "hardware.h"
-
-static struct cpu_op mx51_cpu_op[] = {
-        {
-        .cpu_rate = 160000000,},
-        {
-        .cpu_rate = 800000000,},
-};
-
-struct cpu_op *mx51_get_cpu_op(int *op)
-{
-        *op = ARRAY_SIZE(mx51_cpu_op);
-        return mx51_cpu_op;
-}
diff --git a/arch/arm/mach-imx/cpu_op-mx51.h b/arch/arm/mach-imx/cpu_op-mx51.h
deleted file mode 100644
index 97477fecb469..000000000000
--- a/arch/arm/mach-imx/cpu_op-mx51.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-extern struct cpu_op *mx51_get_cpu_op(int *op);
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c
deleted file mode 100644
index d8c75c3c925d..000000000000
--- a/arch/arm/mach-imx/cpufreq.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/*
- * A driver for the Freescale Semiconductor i.MXC CPUfreq module.
- * The CPUFREQ driver is for controlling CPU frequency. It allows you to change
- * the CPU clock speed on the fly.
- */
-
-#include <linux/module.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/slab.h>
-
-#include "hardware.h"
-
-#define CLK32_FREQ      32768
-#define NANOSECOND      (1000 * 1000 * 1000)
-
-struct cpu_op *(*get_cpu_op)(int *op);
-
-static int cpu_freq_khz_min;
-static int cpu_freq_khz_max;
-
-static struct clk *cpu_clk;
-static struct cpufreq_frequency_table *imx_freq_table;
-
-static int cpu_op_nr;
-static struct cpu_op *cpu_op_tbl;
-
-static int set_cpu_freq(int freq)
-{
-        int ret = 0;
-        int org_cpu_rate;
-
-        org_cpu_rate = clk_get_rate(cpu_clk);
-        if (org_cpu_rate == freq)
-                return ret;
-
-        ret = clk_set_rate(cpu_clk, freq);
-        if (ret != 0) {
-                printk(KERN_DEBUG "cannot set CPU clock rate\n");
-                return ret;
-        }
-
-        return ret;
-}
-
-static int mxc_verify_speed(struct cpufreq_policy *policy)
-{
-        if (policy->cpu != 0)
-                return -EINVAL;
-
-        return cpufreq_frequency_table_verify(policy, imx_freq_table);
-}
-
-static unsigned int mxc_get_speed(unsigned int cpu)
-{
-        if (cpu)
-                return 0;
-
-        return clk_get_rate(cpu_clk) / 1000;
-}
-
-static int mxc_set_target(struct cpufreq_policy *policy,
-                          unsigned int target_freq, unsigned int relation)
-{
-        struct cpufreq_freqs freqs;
-        int freq_Hz;
-        int ret = 0;
-        unsigned int index;
-
-        cpufreq_frequency_table_target(policy, imx_freq_table,
-                        target_freq, relation, &index);
-        freq_Hz = imx_freq_table[index].frequency * 1000;
-
-        freqs.old = clk_get_rate(cpu_clk) / 1000;
-        freqs.new = freq_Hz / 1000;
-        freqs.cpu = 0;
-        freqs.flags = 0;
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
-        ret = set_cpu_freq(freq_Hz);
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
-        return ret;
-}
-
-static int mxc_cpufreq_init(struct cpufreq_policy *policy)
-{
-        int ret;
-        int i;
-
-        printk(KERN_INFO "i.MXC CPU frequency driver\n");
-
-        if (policy->cpu != 0)
-                return -EINVAL;
-
-        if (!get_cpu_op)
-                return -EINVAL;
-
-        cpu_clk = clk_get(NULL, "cpu_clk");
-        if (IS_ERR(cpu_clk)) {
-                printk(KERN_ERR "%s: failed to get cpu clock\n", __func__);
-                return PTR_ERR(cpu_clk);
-        }
-
-        cpu_op_tbl = get_cpu_op(&cpu_op_nr);
-
-        cpu_freq_khz_min = cpu_op_tbl[0].cpu_rate / 1000;
-        cpu_freq_khz_max = cpu_op_tbl[0].cpu_rate / 1000;
-
-        imx_freq_table = kmalloc(
-                sizeof(struct cpufreq_frequency_table) * (cpu_op_nr + 1),
-                        GFP_KERNEL);
-        if (!imx_freq_table) {
-                ret = -ENOMEM;
-                goto err1;
-        }
-
-        for (i = 0; i < cpu_op_nr; i++) {
-                imx_freq_table[i].index = i;
-                imx_freq_table[i].frequency = cpu_op_tbl[i].cpu_rate / 1000;
-
-                if ((cpu_op_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min)
-                        cpu_freq_khz_min = cpu_op_tbl[i].cpu_rate / 1000;
-
-                if ((cpu_op_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max)
-                        cpu_freq_khz_max = cpu_op_tbl[i].cpu_rate / 1000;
-        }
-
-        imx_freq_table[i].index = i;
-        imx_freq_table[i].frequency = CPUFREQ_TABLE_END;
-
-        policy->cur = clk_get_rate(cpu_clk) / 1000;
-        policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min;
-        policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max;
-
-        /* Manual states, that PLL stabilizes in two CLK32 periods */
-        policy->cpuinfo.transition_latency = 2 * NANOSECOND / CLK32_FREQ;
-
-        ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table);
-
-        if (ret < 0) {
-                printk(KERN_ERR "%s: failed to register i.MXC CPUfreq with error code %d\n",
-                       __func__, ret);
-                goto err;
-        }
-
-        cpufreq_frequency_table_get_attr(imx_freq_table, policy->cpu);
-        return 0;
-err:
-        kfree(imx_freq_table);
-err1:
-        clk_put(cpu_clk);
-        return ret;
-}
-
-static int mxc_cpufreq_exit(struct cpufreq_policy *policy)
-{
-        cpufreq_frequency_table_put_attr(policy->cpu);
-
-        set_cpu_freq(cpu_freq_khz_max * 1000);
-        clk_put(cpu_clk);
-        kfree(imx_freq_table);
-        return 0;
-}
-
-static struct cpufreq_driver mxc_driver = {
-        .flags = CPUFREQ_STICKY,
-        .verify = mxc_verify_speed,
-        .target = mxc_set_target,
-        .get = mxc_get_speed,
-        .init = mxc_cpufreq_init,
-        .exit = mxc_cpufreq_exit,
-        .name = "imx",
-};
-
-static int mxc_cpufreq_driver_init(void)
-{
-        return cpufreq_register_driver(&mxc_driver);
-}
-
-static void mxc_cpufreq_driver_exit(void)
-{
-        cpufreq_unregister_driver(&mxc_driver);
-}
-
-module_init(mxc_cpufreq_driver_init);
-module_exit(mxc_cpufreq_driver_exit);
-
-MODULE_AUTHOR("Freescale Semiconductor Inc. Yong Shen <yong.shen@linaro.org>");
-MODULE_DESCRIPTION("CPUfreq driver for i.MX");
-MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-imx/cpuidle-imx5.c b/arch/arm/mach-imx/cpuidle-imx5.c
new file mode 100644
index 000000000000..5a47e3c6172f
--- /dev/null
+++ b/arch/arm/mach-imx/cpuidle-imx5.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/cpuidle.h>
+#include <linux/module.h>
+#include <asm/system_misc.h>
+
+static int imx5_cpuidle_enter(struct cpuidle_device *dev,
+                              struct cpuidle_driver *drv, int index)
+{
+        arm_pm_idle();
+        return index;
+}
+
+static struct cpuidle_driver imx5_cpuidle_driver = {
+        .name             = "imx5_cpuidle",
+        .owner            = THIS_MODULE,
+        .states[0] = {
+                .enter            = imx5_cpuidle_enter,
+                .exit_latency     = 2,
+                .target_residency = 1,
+                .flags            = CPUIDLE_FLAG_TIME_VALID,
+                .name             = "IMX5 SRPG",
+                .desc             = "CPU state retained,powered off",
+        },
+        .state_count = 1,
+};
+
+int __init imx5_cpuidle_init(void)
+{
+        return cpuidle_register(&imx5_cpuidle_driver, NULL);
+}
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
index d533e2695f0e..23ddfb693b2d 100644
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -6,7 +6,6 @@
  * published by the Free Software Foundation.
  */
 
-#include <linux/clockchips.h>
 #include <linux/cpuidle.h>
 #include <linux/module.h>
 #include <asm/cpuidle.h>
@@ -21,10 +20,6 @@ static DEFINE_SPINLOCK(master_lock);
 static int imx6q_enter_wait(struct cpuidle_device *dev,
                             struct cpuidle_driver *drv, int index)
 {
-        int cpu = dev->cpu;
-
-        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
-
         if (atomic_inc_return(&master) == num_online_cpus()) {
                 /*
                  * With this lock, we prevent other cpu to exit and enter
@@ -43,26 +38,13 @@ idle:
         cpu_do_idle();
 done:
         atomic_dec(&master);
-        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 
         return index;
 }
 
-/*
- * For each cpu, setup the broadcast timer because local timer
- * stops for the states other than WFI.
- */
-static void imx6q_setup_broadcast_timer(void *arg)
-{
-        int cpu = smp_processor_id();
-
-        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
-}
-
 static struct cpuidle_driver imx6q_cpuidle_driver = {
         .name = "imx6q_cpuidle",
         .owner = THIS_MODULE,
-        .en_core_tk_irqen = 1,
         .states = {
                 /* WFI */
                 ARM_CPUIDLE_WFI_STATE,
@@ -70,7 +52,8 @@ static struct cpuidle_driver imx6q_cpuidle_driver = {
                 {
                         .exit_latency = 50,
                         .target_residency = 75,
-                        .flags = CPUIDLE_FLAG_TIME_VALID,
+                        .flags = CPUIDLE_FLAG_TIME_VALID |
+                                 CPUIDLE_FLAG_TIMER_STOP,
                         .enter = imx6q_enter_wait,
                         .name = "WAIT",
                         .desc = "Clock off",
@@ -88,8 +71,5 @@ int __init imx6q_cpuidle_init(void)
         /* Set chicken bit to get a reliable WAIT mode support */
         imx6q_set_chicken_bit();
 
-        /* Configure the broadcast timer on each cpu */
-        on_each_cpu(imx6q_setup_broadcast_timer, NULL, 1);
-
-        return imx_cpuidle_init(&imx6q_cpuidle_driver);
+        return cpuidle_register(&imx6q_cpuidle_driver, NULL);
 }
diff --git a/arch/arm/mach-imx/cpuidle.c b/arch/arm/mach-imx/cpuidle.c
deleted file mode 100644
index d4cb511a44a8..000000000000
--- a/arch/arm/mach-imx/cpuidle.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- * Copyright 2012 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/cpuidle.h>
-#include <linux/err.h>
-#include <linux/hrtimer.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-
-static struct cpuidle_device __percpu * imx_cpuidle_devices;
-
-static void __init imx_cpuidle_devices_uninit(void)
-{
-        int cpu_id;
-        struct cpuidle_device *dev;
-
-        for_each_possible_cpu(cpu_id) {
-                dev = per_cpu_ptr(imx_cpuidle_devices, cpu_id);
-                cpuidle_unregister_device(dev);
-        }
-
-        free_percpu(imx_cpuidle_devices);
-}
-
-int __init imx_cpuidle_init(struct cpuidle_driver *drv)
-{
-        struct cpuidle_device *dev;
-        int cpu_id, ret;
-
-        if (drv->state_count > CPUIDLE_STATE_MAX) {
-                pr_err("%s: state_count exceeds maximum\n", __func__);
-                return -EINVAL;
-        }
-
-        ret = cpuidle_register_driver(drv);
-        if (ret) {
-                pr_err("%s: Failed to register cpuidle driver with error: %d\n",
-                         __func__, ret);
-                return ret;
-        }
-
-        imx_cpuidle_devices = alloc_percpu(struct cpuidle_device);
-        if (imx_cpuidle_devices == NULL) {
-                ret = -ENOMEM;
-                goto unregister_drv;
-        }
-
-        /* initialize state data for each cpuidle_device */
-        for_each_possible_cpu(cpu_id) {
-                dev = per_cpu_ptr(imx_cpuidle_devices, cpu_id);
-                dev->cpu = cpu_id;
-                dev->state_count = drv->state_count;
-
-                ret = cpuidle_register_device(dev);
-                if (ret) {
-                        pr_err("%s: Failed to register cpu %u, error: %d\n",
-                                __func__, cpu_id, ret);
-                        goto uninit;
-                }
-        }
-
-        return 0;
-
-uninit:
-        imx_cpuidle_devices_uninit();
-
-unregister_drv:
-        cpuidle_unregister_driver(drv);
-        return ret;
-}
diff --git a/arch/arm/mach-imx/cpuidle.h b/arch/arm/mach-imx/cpuidle.h
index e092d1359d94..786f98ecc145 100644
--- a/arch/arm/mach-imx/cpuidle.h
+++ b/arch/arm/mach-imx/cpuidle.h
@@ -10,18 +10,16 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <linux/cpuidle.h>
-
 #ifdef CONFIG_CPU_IDLE
-extern int imx_cpuidle_init(struct cpuidle_driver *drv);
+extern int imx5_cpuidle_init(void);
 extern int imx6q_cpuidle_init(void);
 #else
-static inline int imx_cpuidle_init(struct cpuidle_driver *drv)
+static inline int imx5_cpuidle_init(void)
 {
-        return -ENODEV;
+        return 0;
 }
 static inline int imx6q_cpuidle_init(void)
 {
-        return -ENODEV;
+        return 0;
 }
 #endif
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index 9b9ba1f4ffe1..3dd2b1b041d1 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -86,7 +86,3 @@ config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
 
 config IMX_HAVE_PLATFORM_SPI_IMX
         bool
-
-config IMX_HAVE_PLATFORM_AHCI
-        bool
-        default y if ARCH_MX53
diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile
index 6acf37e0c119..67416fb1dc69 100644
--- a/arch/arm/mach-imx/devices/Makefile
+++ b/arch/arm/mach-imx/devices/Makefile
@@ -29,5 +29,4 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) +=  platform-spi_imx.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_AHCI) +=  platform-ahci-imx.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_EMMA) += platform-mx2-emma.o
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
index 9bd5777ff0e7..453e20bc2657 100644
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -344,13 +344,3 @@ struct platform_device *imx_add_imx_dma(char *name, resource_size_t iobase,
                                         int irq, int irq_err);
 struct platform_device *imx_add_imx_sdma(char *name,
         resource_size_t iobase, int irq, struct sdma_platform_data *pdata);
-
-#include <linux/ahci_platform.h>
-struct imx_ahci_imx_data {
-        const char *devid;
-        resource_size_t iobase;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_ahci_imx(
-                const struct imx_ahci_imx_data *data,
-                const struct ahci_platform_data *pdata);
diff --git a/arch/arm/mach-imx/devices/devices.c b/arch/arm/mach-imx/devices/devices.c
index 1b37482407f9..1b4366a0e7c0 100644
--- a/arch/arm/mach-imx/devices/devices.c
+++ b/arch/arm/mach-imx/devices/devices.c
@@ -37,7 +37,7 @@ int __init mxc_device_init(void)
         int ret;
 
         ret = device_register(&mxc_aips_bus);
-        if (IS_ERR_VALUE(ret))
+        if (ret < 0)
                 goto done;
 
         ret = device_register(&mxc_ahb_bus);
diff --git a/arch/arm/mach-imx/devices/platform-ahci-imx.c b/arch/arm/mach-imx/devices/platform-ahci-imx.c
deleted file mode 100644
index 3d87dd9c284a..000000000000
--- a/arch/arm/mach-imx/devices/platform-ahci-imx.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <asm/sizes.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_ahci_imx_data_entry_single(soc, _devid)             \
-        {                                                               \
-                .devid = _devid,                                        \
-                .iobase = soc ## _SATA_BASE_ADDR,                       \
-                .irq = soc ## _INT_SATA,                                \
-        }
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_ahci_imx_data imx53_ahci_imx_data __initconst =
-        imx_ahci_imx_data_entry_single(MX53, "imx53-ahci");
-#endif
-
-enum {
-        HOST_CAP = 0x00,
-        HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
-        HOST_PORTS_IMPL = 0x0c,
-        HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
-};
-
-static struct clk *sata_clk, *sata_ref_clk;
-
-/* AHCI module Initialization, if return 0, initialization is successful. */
-static int imx_sata_init(struct device *dev, void __iomem *addr)
-{
-        u32 tmpdata;
-        int ret = 0;
-        struct clk *clk;
-
-        sata_clk = clk_get(dev, "ahci");
-        if (IS_ERR(sata_clk)) {
-                dev_err(dev, "no sata clock.\n");
-                return PTR_ERR(sata_clk);
-        }
-        ret = clk_prepare_enable(sata_clk);
-        if (ret) {
-                dev_err(dev, "can't prepare/enable sata clock.\n");
-                goto put_sata_clk;
-        }
-
-        /* Get the AHCI SATA PHY CLK */
-        sata_ref_clk = clk_get(dev, "ahci_phy");
-        if (IS_ERR(sata_ref_clk)) {
-                dev_err(dev, "no sata ref clock.\n");
-                ret = PTR_ERR(sata_ref_clk);
-                goto release_sata_clk;
-        }
-        ret = clk_prepare_enable(sata_ref_clk);
-        if (ret) {
-                dev_err(dev, "can't prepare/enable sata ref clock.\n");
-                goto put_sata_ref_clk;
-        }
-
-        /* Get the AHB clock rate, and configure the TIMER1MS reg later */
-        clk = clk_get(dev, "ahci_dma");
-        if (IS_ERR(clk)) {
-                dev_err(dev, "no dma clock.\n");
-                ret = PTR_ERR(clk);
-                goto release_sata_ref_clk;
-        }
-        tmpdata = clk_get_rate(clk) / 1000;
-        clk_put(clk);
-
-        writel(tmpdata, addr + HOST_TIMER1MS);
-
-        tmpdata = readl(addr + HOST_CAP);
-        if (!(tmpdata & HOST_CAP_SSS)) {
-                tmpdata |= HOST_CAP_SSS;
-                writel(tmpdata, addr + HOST_CAP);
-        }
-
-        if (!(readl(addr + HOST_PORTS_IMPL) & 0x1))
-                writel((readl(addr + HOST_PORTS_IMPL) | 0x1),
-                        addr + HOST_PORTS_IMPL);
-
-        return 0;
-
-release_sata_ref_clk:
-        clk_disable_unprepare(sata_ref_clk);
-put_sata_ref_clk:
-        clk_put(sata_ref_clk);
-release_sata_clk:
-        clk_disable_unprepare(sata_clk);
-put_sata_clk:
-        clk_put(sata_clk);
-
-        return ret;
-}
-
-static void imx_sata_exit(struct device *dev)
-{
-        clk_disable_unprepare(sata_ref_clk);
-        clk_put(sata_ref_clk);
-
-        clk_disable_unprepare(sata_clk);
-        clk_put(sata_clk);
-
-}
-struct platform_device *__init imx_add_ahci_imx(
-                const struct imx_ahci_imx_data *data,
-                const struct ahci_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return imx_add_platform_device_dmamask(data->devid, 0,
-                        res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata),  DMA_BIT_MASK(32));
-}
-
-struct platform_device *__init imx53_add_ahci_imx(void)
-{
-        struct ahci_platform_data pdata = {
-                .init = imx_sata_init,
-                .exit = imx_sata_exit,
-        };
-
-        return imx_add_ahci_imx(&imx53_ahci_imx_data, &pdata);
-}
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index b4c70028d359..b2f08bfbbdd3 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -46,7 +46,7 @@ static const int eukrea_mbimx27_pins[] __initconst = {
         PE10_PF_UART3_CTS,
         PE11_PF_UART3_RTS,
         /* UART4 */
-#if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
+#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
         PB26_AF_UART4_RTS,
         PB28_AF_UART4_TXD,
         PB29_AF_UART4_CTS,
@@ -306,7 +306,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
 
         imx27_add_imx_uart1(&uart_pdata);
         imx27_add_imx_uart2(&uart_pdata);
-#if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
+#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
         imx27_add_imx_uart3(&uart_pdata);
 #endif
 
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index a96ccc7f5012..02b61cdf39b9 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -16,6 +16,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/irqchip/arm-gic.h>
+#include "common.h"
 
 #define GPC_IMR1                0x008
 #define GPC_PGC_CPU_PDN         0x2a0
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index 911e9b31b03f..356131f7b591 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -102,7 +102,6 @@
 
 #include "mxc.h"
 
-#include "mx6q.h"
 #include "mx51.h"
 #include "mx53.h"
 #include "mx3x.h"
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index 361a253e2b63..5e91112dcbee 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -11,7 +11,6 @@
  */
 
 #include <linux/errno.h>
-#include <asm/cacheflush.h>
 #include <asm/cp15.h>
 
 #include "common.h"
@@ -20,7 +19,6 @@ static inline void cpu_enter_lowpower(void)
 {
         unsigned int v;
 
-        flush_cache_all();
         asm volatile(
                 "mcr    p15, 0, %1, c7, c5, 0\n"
         "       mcr     p15, 0, %1, c7, c10, 4\n"
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index c915a490a11c..4aaead0a77ff 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -18,25 +18,13 @@
 #include "common.h"
 #include "mx27.h"
 
-static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART1_BASE_ADDR, "imx21-uart.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART2_BASE_ADDR, "imx21-uart.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-uart", MX27_UART3_BASE_ADDR, "imx21-uart.2", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-fec", MX27_FEC_BASE_ADDR, "imx27-fec.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C1_BASE_ADDR, "imx21-i2c.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-i2c", MX27_I2C2_BASE_ADDR, "imx21-i2c.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI1_BASE_ADDR, "imx27-cspi.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI2_BASE_ADDR, "imx27-cspi.1", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI3_BASE_ADDR, "imx27-cspi.2", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-wdt", MX27_WDOG_BASE_ADDR, "imx2-wdt.0", NULL),
-        OF_DEV_AUXDATA("fsl,imx27-nand", MX27_NFC_BASE_ADDR, "imx27-nand.0", NULL),
-        { /* sentinel */ }
-};
-
 static void __init imx27_dt_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table,
-                             imx27_auxdata_lookup, NULL);
+        struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
+
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+
+        platform_device_register_full(&devinfo);
 }
 
 static const char * const imx27_dt_board_compat[] __initconst = {
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index e2926a8863f8..ab24cc322111 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -21,7 +21,10 @@
 
 static void __init imx51_dt_init(void)
 {
+        struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
+
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        platform_device_register_full(&devinfo);
 }
 
 static const char *imx51_dt_board_compat[] __initdata = {
diff --git a/arch/arm/mach-imx/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c
index cabefbc5e7c1..7c66805d2cc0 100644
--- a/arch/arm/mach-imx/iomux-imx31.c
+++ b/arch/arm/mach-imx/iomux-imx31.c
@@ -40,7 +40,7 @@ static DEFINE_SPINLOCK(gpio_mux_lock);
 
 #define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
 
-unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
+static unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
 /*
  * set the mode for a IOMUX pin.
  */
diff --git a/arch/arm/mach-imx/irq-common.c b/arch/arm/mach-imx/irq-common.c
index b6e11458e5ae..4b34f52dc46b 100644
--- a/arch/arm/mach-imx/irq-common.c
+++ b/arch/arm/mach-imx/irq-common.c
@@ -21,25 +21,6 @@
 
 #include "irq-common.h"
 
-int imx_irq_set_priority(unsigned char irq, unsigned char prio)
-{
-        struct irq_chip_generic *gc;
-        struct mxc_extra_irq *exirq;
-        int ret;
-
-        ret = -ENOSYS;
-
-        gc = irq_get_chip_data(irq);
-        if (gc && gc->private) {
-                exirq = gc->private;
-                if (exirq->set_priority)
-                        ret = exirq->set_priority(irq, prio);
-        }
-
-        return ret;
-}
-EXPORT_SYMBOL(imx_irq_set_priority);
-
 int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
 {
         struct irq_chip_generic *gc;
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 146559311bd2..ea50870bda80 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -48,7 +48,7 @@ static const int eukrea_cpuimx27_pins[] __initconst = {
         PE14_PF_UART1_CTS,
         PE15_PF_UART1_RTS,
         /* UART4 */
-#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
+#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
         PB26_AF_UART4_RTS,
         PB28_AF_UART4_TXD,
         PB29_AF_UART4_CTS,
@@ -272,7 +272,7 @@ static void __init eukrea_cpuimx27_init(void)
         /* SDHC2 can be used for Wifi */
         imx27_add_mxc_mmc(1, NULL);
 #endif
-#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
+#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
         /* in which case UART4 is also used for Bluetooth */
         imx27_add_imx_uart3(&uart_pdata);
 #endif
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
index 9b7393234f6f..9b5ddf5bbd33 100644
--- a/arch/arm/mach-imx/mach-cpuimx51sd.c
+++ b/arch/arm/mach-imx/mach-cpuimx51sd.c
@@ -33,7 +33,6 @@
 
 #include "common.h"
 #include "devices-imx51.h"
-#include "cpu_op-mx51.h"
 #include "eukrea-baseboards.h"
 #include "hardware.h"
 #include "iomux-mx51.h"
@@ -285,10 +284,6 @@ static void __init eukrea_cpuimx51sd_init(void)
         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
                                         ARRAY_SIZE(eukrea_cpuimx51sd_pads));
 
-#if defined(CONFIG_CPU_FREQ_IMX)
-        get_cpu_op = mx51_get_cpu_op;
-#endif
-
         imx51_add_imx_uart(0, &uart_pdata);
         imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
         imx51_add_imx2_wdt(0);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 9ffd103b27e4..99502eeefdf7 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -12,6 +12,7 @@
 
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/clocksource.h>
 #include <linux/cpu.h>
 #include <linux/delay.h>
 #include <linux/export.h>
@@ -28,11 +29,9 @@
 #include <linux/regmap.h>
 #include <linux/micrel_phy.h>
 #include <linux/mfd/syscon.h>
-#include <asm/smp_twd.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/mach/time.h>
 #include <asm/system_misc.h>
 
 #include "common.h"
@@ -73,7 +72,7 @@ static int imx6q_revision(void)
         }
 }
 
-void imx6q_restart(char mode, const char *cmd)
+static void imx6q_restart(char mode, const char *cmd)
 {
         struct device_node *np;
         void __iomem *wdog_base;
@@ -256,7 +255,7 @@ put_node:
         of_node_put(np);
 }
 
-struct platform_device imx6q_cpufreq_pdev = {
+static struct platform_device imx6q_cpufreq_pdev = {
         .name = "imx6q-cpufreq",
 };
 
@@ -292,7 +291,7 @@ static void __init imx6q_init_irq(void)
 static void __init imx6q_timer_init(void)
 {
         mx6q_clocks_init();
-        twd_local_timer_of_register();
+        clocksource_of_init();
         imx_print_silicon_rev("i.MX6Q", imx6q_revision());
 }
 
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
index 6c4d7feb4520..f3d264a636fa 100644
--- a/arch/arm/mach-imx/mach-mx51_babbage.c
+++ b/arch/arm/mach-imx/mach-mx51_babbage.c
@@ -27,7 +27,6 @@
 
 #include "common.h"
 #include "devices-imx51.h"
-#include "cpu_op-mx51.h"
 #include "hardware.h"
 #include "iomux-mx51.h"
 
@@ -371,9 +370,6 @@ static void __init mx51_babbage_init(void)
 
         imx51_soc_init();
 
-#if defined(CONFIG_CPU_FREQ_IMX)
-        get_cpu_op = mx51_get_cpu_op;
-#endif
         imx51_babbage_common_init();
 
         imx51_add_imx_uart(0, &uart_pdata);
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index cefa047c4053..e0e69a682174 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -82,7 +82,7 @@ static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
         return __arm_ioremap_caller(phys_addr, size, mtype, caller);
 }
 
-void __init imx3_init_l2x0(void)
+static void __init imx3_init_l2x0(void)
 {
 #ifdef CONFIG_CACHE_L2X0
         void __iomem *l2x0_base;
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index cf34994cfe28..b7c4e70e5081 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -84,6 +84,7 @@ void __init imx51_init_early(void)
         mxc_set_cpu_type(MXC_CPU_MX51);
         mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
         mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
+        imx_src_init();
 }
 
 void __init imx53_init_early(void)
@@ -91,6 +92,7 @@ void __init imx53_init_early(void)
         mxc_set_cpu_type(MXC_CPU_MX53);
         mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
         mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
+        imx_src_init();
 }
 
 void __init mx51_init_irq(void)
diff --git a/arch/arm/mach-imx/mx6q.h b/arch/arm/mach-imx/mx6q.h
deleted file mode 100644
index 19d3f54db5af..000000000000
--- a/arch/arm/mach-imx/mx6q.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __MACH_MX6Q_H__
-#define __MACH_MX6Q_H__
-
-#define MX6Q_IO_P2V(x)                  IMX_IO_P2V(x)
-#define MX6Q_IO_ADDRESS(x)              IOMEM(MX6Q_IO_P2V(x))
-
-/*
- * The following are the blocks that need to be statically mapped.
- * For other blocks, the base address really should be retrieved from
- * device tree.
- */
-#define MX6Q_SCU_BASE_ADDR              0x00a00000
-#define MX6Q_SCU_SIZE                   0x1000
-#define MX6Q_CCM_BASE_ADDR              0x020c4000
-#define MX6Q_CCM_SIZE                   0x4000
-#define MX6Q_ANATOP_BASE_ADDR           0x020c8000
-#define MX6Q_ANATOP_SIZE                0x1000
-
-#endif  /* __MACH_MX6Q_H__ */
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 7c0b03f67b05..77e9a25ed0f6 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -12,7 +12,6 @@
 
 #include <linux/init.h>
 #include <linux/smp.h>
-#include <linux/irqchip/arm-gic.h>
 #include <asm/page.h>
 #include <asm/smp_scu.h>
 #include <asm/mach/map.h>
@@ -52,16 +51,6 @@ void imx_scu_standby_enable(void)
         writel_relaxed(val, scu_base);
 }
 
-static void __cpuinit imx_secondary_init(unsigned int cpu)
-{
-        /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-}
-
 static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         imx_set_cpu_jump(cpu, v7_secondary_startup);
@@ -96,7 +85,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
 struct smp_operations  imx_smp_ops __initdata = {
         .smp_init_cpus          = imx_smp_init_cpus,
         .smp_prepare_cpus       = imx_smp_prepare_cpus,
-        .smp_secondary_init     = imx_secondary_init,
         .smp_boot_secondary     = imx_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_die                = imx_cpu_die,
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c
index f67fd7ee8127..82e79c658eb2 100644
--- a/arch/arm/mach-imx/pm-imx5.c
+++ b/arch/arm/mach-imx/pm-imx5.c
@@ -149,33 +149,6 @@ static void imx5_pm_idle(void)
         imx5_cpu_do_idle();
 }
 
-static int imx5_cpuidle_enter(struct cpuidle_device *dev,
-                                struct cpuidle_driver *drv, int idx)
-{
-        int ret;
-
-        ret = imx5_cpu_do_idle();
-        if (ret < 0)
-                return ret;
-
-        return idx;
-}
-
-static struct cpuidle_driver imx5_cpuidle_driver = {
-        .name                   = "imx5_cpuidle",
-        .owner                  = THIS_MODULE,
-        .en_core_tk_irqen       = 1,
-        .states[0]      = {
-                .enter                  = imx5_cpuidle_enter,
-                .exit_latency           = 2,
-                .target_residency       = 1,
-                .flags                  = CPUIDLE_FLAG_TIME_VALID,
-                .name                   = "IMX5 SRPG",
-                .desc                   = "CPU state retained,powered off",
-        },
-        .state_count            = 1,
-};
-
 static int __init imx5_pm_common_init(void)
 {
         int ret;
@@ -193,8 +166,7 @@ static int __init imx5_pm_common_init(void)
         /* Set the registers to the default cpu idle state. */
         mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE);
 
-        imx_cpuidle_init(&imx5_cpuidle_driver);
-        return 0;
+        return imx5_cpuidle_init();
 }
 
 void __init imx51_pm_init(void)
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index 09a742f8c7ab..97d086889481 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -16,6 +16,7 @@
 #include <linux/of_address.h>
 #include <linux/smp.h>
 #include <asm/smp_plat.h>
+#include "common.h"
 
 #define SRC_SCR                         0x000
 #define SRC_GPR1                        0x020
@@ -73,7 +74,9 @@ void __init imx_src_init(void)
         struct device_node *np;
         u32 val;
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src");
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx51-src");
+        if (!np)
+                return;
         src_base = of_iomap(np, 0);
         WARN_ON(!src_base);
 
diff --git a/arch/arm/mach-imx/tzic.c b/arch/arm/mach-imx/tzic.c
index 9721161f208f..8183178d5aa3 100644
--- a/arch/arm/mach-imx/tzic.c
+++ b/arch/arm/mach-imx/tzic.c
@@ -49,7 +49,7 @@
 #define TZIC_SWINT      0x0F00  /* Software Interrupt Rigger Register */
 #define TZIC_ID0        0x0FD0  /* Indentification Register 0 */
 
-void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
+static void __iomem *tzic_base;
 static struct irq_domain *domain;
 
 #define TZIC_NUM_IRQS 128
diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index 5521d18bf19a..d14d6b76f4c2 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -9,5 +9,4 @@ obj-$(CONFIG_ARCH_INTEGRATOR_AP)	+= integrator_ap.o
 obj-$(CONFIG_ARCH_INTEGRATOR_CP)        += integrator_cp.o
 
 obj-$(CONFIG_PCI)                       += pci_v3.o pci.o
-obj-$(CONFIG_CPU_FREQ_INTEGRATOR)       += cpu.o
 obj-$(CONFIG_INTEGRATOR_IMPD1)          += impd1.o
diff --git a/arch/arm/mach-integrator/cpu.c b/arch/arm/mach-integrator/cpu.c
deleted file mode 100644
index 590c192cdf4d..000000000000
--- a/arch/arm/mach-integrator/cpu.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- *  linux/arch/arm/mach-integrator/cpu.c
- *
- *  Copyright (C) 2001-2002 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * CPU support functions
- */
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/cpufreq.h>
-#include <linux/sched.h>
-#include <linux/smp.h>
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include <asm/mach-types.h>
-#include <asm/hardware/icst.h>
-
-static struct cpufreq_driver integrator_driver;
-
-#define CM_ID   __io_address(INTEGRATOR_HDR_ID)
-#define CM_OSC  __io_address(INTEGRATOR_HDR_OSC)
-#define CM_STAT __io_address(INTEGRATOR_HDR_STAT)
-#define CM_LOCK __io_address(INTEGRATOR_HDR_LOCK)
-
-static const struct icst_params lclk_params = {
-        .ref            = 24000000,
-        .vco_max        = ICST525_VCO_MAX_5V,
-        .vco_min        = ICST525_VCO_MIN,
-        .vd_min         = 8,
-        .vd_max         = 132,
-        .rd_min         = 24,
-        .rd_max         = 24,
-        .s2div          = icst525_s2div,
-        .idx2s          = icst525_idx2s,
-};
-
-static const struct icst_params cclk_params = {
-        .ref            = 24000000,
-        .vco_max        = ICST525_VCO_MAX_5V,
-        .vco_min        = ICST525_VCO_MIN,
-        .vd_min         = 12,
-        .vd_max         = 160,
-        .rd_min         = 24,
-        .rd_max         = 24,
-        .s2div          = icst525_s2div,
-        .idx2s          = icst525_idx2s,
-};
-
-/*
- * Validate the speed policy.
- */
-static int integrator_verify_policy(struct cpufreq_policy *policy)
-{
-        struct icst_vco vco;
-
-        cpufreq_verify_within_limits(policy, 
-                                     policy->cpuinfo.min_freq, 
-                                     policy->cpuinfo.max_freq);
-
-        vco = icst_hz_to_vco(&cclk_params, policy->max * 1000);
-        policy->max = icst_hz(&cclk_params, vco) / 1000;
-
-        vco = icst_hz_to_vco(&cclk_params, policy->min * 1000);
-        policy->min = icst_hz(&cclk_params, vco) / 1000;
-
-        cpufreq_verify_within_limits(policy, 
-                                     policy->cpuinfo.min_freq, 
-                                     policy->cpuinfo.max_freq);
-
-        return 0;
-}
-
-
-static int integrator_set_target(struct cpufreq_policy *policy,
-                                 unsigned int target_freq,
-                                 unsigned int relation)
-{
-        cpumask_t cpus_allowed;
-        int cpu = policy->cpu;
-        struct icst_vco vco;
-        struct cpufreq_freqs freqs;
-        u_int cm_osc;
-
-        /*
-         * Save this threads cpus_allowed mask.
-         */
-        cpus_allowed = current->cpus_allowed;
-
-        /*
-         * Bind to the specified CPU.  When this call returns,
-         * we should be running on the right CPU.
-         */
-        set_cpus_allowed(current, cpumask_of_cpu(cpu));
-        BUG_ON(cpu != smp_processor_id());
-
-        /* get current setting */
-        cm_osc = __raw_readl(CM_OSC);
-
-        if (machine_is_integrator()) {
-                vco.s = (cm_osc >> 8) & 7;
-        } else if (machine_is_cintegrator()) {
-                vco.s = 1;
-        }
-        vco.v = cm_osc & 255;
-        vco.r = 22;
-        freqs.old = icst_hz(&cclk_params, vco) / 1000;
-
-        /* icst_hz_to_vco rounds down -- so we need the next
-         * larger freq in case of CPUFREQ_RELATION_L.
-         */
-        if (relation == CPUFREQ_RELATION_L)
-                target_freq += 999;
-        if (target_freq > policy->max)
-                target_freq = policy->max;
-        vco = icst_hz_to_vco(&cclk_params, target_freq * 1000);
-        freqs.new = icst_hz(&cclk_params, vco) / 1000;
-
-        freqs.cpu = policy->cpu;
-
-        if (freqs.old == freqs.new) {
-                set_cpus_allowed(current, cpus_allowed);
-                return 0;
-        }
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
-        cm_osc = __raw_readl(CM_OSC);
-
-        if (machine_is_integrator()) {
-                cm_osc &= 0xfffff800;
-                cm_osc |= vco.s << 8;
-        } else if (machine_is_cintegrator()) {
-                cm_osc &= 0xffffff00;
-        }
-        cm_osc |= vco.v;
-
-        __raw_writel(0xa05f, CM_LOCK);
-        __raw_writel(cm_osc, CM_OSC);
-        __raw_writel(0, CM_LOCK);
-
-        /*
-         * Restore the CPUs allowed mask.
-         */
-        set_cpus_allowed(current, cpus_allowed);
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
-        return 0;
-}
-
-static unsigned int integrator_get(unsigned int cpu)
-{
-        cpumask_t cpus_allowed;
-        unsigned int current_freq;
-        u_int cm_osc;
-        struct icst_vco vco;
-
-        cpus_allowed = current->cpus_allowed;
-
-        set_cpus_allowed(current, cpumask_of_cpu(cpu));
-        BUG_ON(cpu != smp_processor_id());
-
-        /* detect memory etc. */
-        cm_osc = __raw_readl(CM_OSC);
-
-        if (machine_is_integrator()) {
-                vco.s = (cm_osc >> 8) & 7;
-        } else {
-                vco.s = 1;
-        }
-        vco.v = cm_osc & 255;
-        vco.r = 22;
-
-        current_freq = icst_hz(&cclk_params, vco) / 1000; /* current freq */
-
-        set_cpus_allowed(current, cpus_allowed);
-
-        return current_freq;
-}
-
-static int integrator_cpufreq_init(struct cpufreq_policy *policy)
-{
-
-        /* set default policy and cpuinfo */
-        policy->cpuinfo.max_freq = 160000;
-        policy->cpuinfo.min_freq = 12000;
-        policy->cpuinfo.transition_latency = 1000000; /* 1 ms, assumed */
-        policy->cur = policy->min = policy->max = integrator_get(policy->cpu);
-
-        return 0;
-}
-
-static struct cpufreq_driver integrator_driver = {
-        .verify         = integrator_verify_policy,
-        .target         = integrator_set_target,
-        .get            = integrator_get,
-        .init           = integrator_cpufreq_init,
-        .name           = "integrator",
-};
-
-static int __init integrator_cpu_init(void)
-{
-        return cpufreq_register_driver(&integrator_driver);
-}
-
-static void __exit integrator_cpu_exit(void)
-{
-        cpufreq_unregister_driver(&integrator_driver);
-}
-
-MODULE_AUTHOR ("Russell M. King");
-MODULE_DESCRIPTION ("cpufreq driver for ARM Integrator CPUs");
-MODULE_LICENSE ("GPL");
-
-module_init(integrator_cpu_init);
-module_exit(integrator_cpu_exit);
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index ea961445e0e9..b23c8e4f28e8 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -536,16 +536,14 @@ static void __init ap_init_of(void)
                                            'A' + (ap_sc_id & 0x0f));
 
         soc_dev = soc_device_register(soc_dev_attr);
-        if (IS_ERR_OR_NULL(soc_dev)) {
+        if (IS_ERR(soc_dev)) {
                 kfree(soc_dev_attr->revision);
                 kfree(soc_dev_attr);
                 return;
         }
 
         parent = soc_device_to_device(soc_dev);
-
-        if (!IS_ERR_OR_NULL(parent))
-                integrator_init_sysfs(parent, ap_sc_id);
+        integrator_init_sysfs(parent, ap_sc_id);
 
         of_platform_populate(root, of_default_bus_match_table,
                         ap_auxdata_lookup, parent);
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 2b0db82a5381..da1091be0887 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -360,17 +360,14 @@ static void __init intcp_init_of(void)
                                            'A' + (intcp_sc_id & 0x0f));
 
         soc_dev = soc_device_register(soc_dev_attr);
-        if (IS_ERR_OR_NULL(soc_dev)) {
+        if (IS_ERR(soc_dev)) {
                 kfree(soc_dev_attr->revision);
                 kfree(soc_dev_attr);
                 return;
         }
 
         parent = soc_device_to_device(soc_dev);
-
-        if (!IS_ERR_OR_NULL(parent))
-                integrator_init_sysfs(parent, intcp_sc_id);
-
+        integrator_init_sysfs(parent, intcp_sc_id);
         of_platform_populate(root, of_default_bus_match_table,
                         intcp_auxdata_lookup, parent);
 }
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 1dbeb7c99d58..6600cff6bd92 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -29,6 +29,7 @@
 #include <linux/io.h>
 #include <linux/export.h>
 #include <linux/gpio.h>
+#include <linux/cpu.h>
 
 #include <mach/udc.h>
 #include <mach/hardware.h>
@@ -239,7 +240,7 @@ void __init ixp4xx_init_irq(void)
          * ixp4xx does not implement the XScale PWRMODE register
          * so it must not call cpu_do_idle().
          */
-        disable_hlt();
+        cpu_idle_poll_ctrl(true);
 
         /* Route all sources to IRQ instead of FIQ */
         *IXP4XX_ICLR = 0x0;
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 7b6a64bc5f40..7509a89af967 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -2,23 +2,41 @@ if ARCH_KIRKWOOD
 
 menu "Marvell Kirkwood Implementations"
 
+config MACH_D2NET_V2
+        bool "LaCie d2 Network v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie d2 Network v2 NAS.
+
 config MACH_DB88F6281_BP
         bool "Marvell DB-88F6281-BP Development Board"
         help
           Say 'Y' here if you want your kernel to support the
           Marvell DB-88F6281-BP Development Board.
 
-config MACH_RD88F6192_NAS
-        bool "Marvell RD-88F6192-NAS Reference Board"
+config MACH_DOCKSTAR
+        bool "Seagate FreeAgent DockStar"
         help
           Say 'Y' here if you want your kernel to support the
-          Marvell RD-88F6192-NAS Reference Board.
+          Seagate FreeAgent DockStar.
 
-config MACH_RD88F6281
-        bool "Marvell RD-88F6281 Reference Board"
+config MACH_ESATA_SHEEVAPLUG
+        bool "Marvell eSATA SheevaPlug Reference Board"
         help
           Say 'Y' here if you want your kernel to support the
-          Marvell RD-88F6281 Reference Board.
+          Marvell eSATA SheevaPlug Reference Board.
+
+config MACH_GURUPLUG
+        bool "Marvell GuruPlug Reference Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell GuruPlug Reference Board.
+
+config MACH_INETSPACE_V2
+        bool "LaCie Internet Space v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie Internet Space v2 NAS.
 
 config MACH_MV88F6281GTW_GE
         bool "Marvell 88F6281 GTW GE Board"
@@ -26,23 +44,93 @@ config MACH_MV88F6281GTW_GE
           Say 'Y' here if you want your kernel to support the
           Marvell 88F6281 GTW GE Board.
 
+config MACH_NET2BIG_V2
+        bool "LaCie 2Big Network v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie 2Big Network v2 NAS.
+
+config MACH_NET5BIG_V2
+        bool "LaCie 5Big Network v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie 5Big Network v2 NAS.
+
+config MACH_NETSPACE_MAX_V2
+        bool "LaCie Network Space Max v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie Network Space Max v2 NAS.
+
+config MACH_NETSPACE_V2
+        bool "LaCie Network Space v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie Network Space v2 NAS.
+
+config MACH_OPENRD
+        bool
+
+config MACH_OPENRD_BASE
+        bool "Marvell OpenRD Base Board"
+        select MACH_OPENRD
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell OpenRD Base Board.
+
+config MACH_OPENRD_CLIENT
+        bool "Marvell OpenRD Client Board"
+        select MACH_OPENRD
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell OpenRD Client Board.
+
+config MACH_OPENRD_ULTIMATE
+        bool "Marvell OpenRD Ultimate Board"
+        select MACH_OPENRD
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell OpenRD Ultimate Board.
+
+config MACH_RD88F6192_NAS
+        bool "Marvell RD-88F6192-NAS Reference Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell RD-88F6192-NAS Reference Board.
+
+config MACH_RD88F6281
+        bool "Marvell RD-88F6281 Reference Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell RD-88F6281 Reference Board.
+
 config MACH_SHEEVAPLUG
         bool "Marvell SheevaPlug Reference Board"
         help
           Say 'Y' here if you want your kernel to support the
           Marvell SheevaPlug Reference Board.
 
-config MACH_ESATA_SHEEVAPLUG
-        bool "Marvell eSATA SheevaPlug Reference Board"
+config MACH_T5325
+        bool "HP t5325 Thin Client"
         help
           Say 'Y' here if you want your kernel to support the
-          Marvell eSATA SheevaPlug Reference Board.
+          HP t5325 Thin Client.
 
-config MACH_GURUPLUG
-        bool "Marvell GuruPlug Reference Board"
+config MACH_TS219
+        bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
         help
           Say 'Y' here if you want your kernel to support the
-          Marvell GuruPlug Reference Board.
+          QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
+          TS-219P+ Turbo NAS devices.
+
+config MACH_TS41X
+        bool "QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo NAS"
+        help
+          Say 'Y' here if you want your kernel to support the
+          QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo
+          NAS devices.
+
+comment "Device tree entries"
 
 config ARCH_KIRKWOOD_DT
         bool "Marvell Kirkwood Flattened Device Tree"
@@ -58,12 +146,27 @@ config ARCH_KIRKWOOD_DT
           Say 'Y' here if you want your kernel to support the
           Marvell Kirkwood using flattened device tree.
 
-config MACH_GURUPLUG_DT
-        bool "Marvell GuruPlug Reference Board (Flattened Device Tree)"
+config MACH_CLOUDBOX_DT
+        bool "LaCie CloudBox NAS (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the LaCie
+          CloudBox NAS, using Flattened Device Tree.
+
+config MACH_DLINK_KIRKWOOD_DT
+        bool "D-Link Kirkwood-based NAS (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
         help
           Say 'Y' here if you want your kernel to support the
-          Marvell GuruPlug Reference Board (Flattened Device Tree).
+          Kirkwood-based D-Link NASes such as DNS-320 & DNS-325,
+          using Flattened Device Tree.
+
+config MACH_DOCKSTAR_DT
+        bool "Seagate FreeAgent Dockstar (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Seagate FreeAgent Dockstar (Flattened Device Tree).
 
 config MACH_DREAMPLUG_DT
         bool "Marvell DreamPlug (Flattened Device Tree)"
@@ -72,19 +175,19 @@ config MACH_DREAMPLUG_DT
           Say 'Y' here if you want your kernel to support the
           Marvell DreamPlug (Flattened Device Tree).
 
-config MACH_ICONNECT_DT
-        bool "Iomega Iconnect (Flattened Device Tree)"
+config MACH_GOFLEXNET_DT
+        bool "Seagate GoFlex Net (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
         help
-          Say 'Y' here to enable Iomega Iconnect support.
+          Say 'Y' here if you want your kernel to support the
+          Seagate GoFlex Net (Flattened Device Tree).
 
-config MACH_DLINK_KIRKWOOD_DT
-        bool "D-Link Kirkwood-based NAS (Flattened Device Tree)"
+config MACH_GURUPLUG_DT
+        bool "Marvell GuruPlug Reference Board (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
         help
           Say 'Y' here if you want your kernel to support the
-          Kirkwood-based D-Link NASes such as DNS-320 & DNS-325,
-          using Flattened Device Tree.
+          Marvell GuruPlug Reference Board (Flattened Device Tree).
 
 config MACH_IB62X0_DT
         bool "RaidSonic IB-NAS6210, IB-NAS6220 (Flattened Device Tree)"
@@ -94,41 +197,18 @@ config MACH_IB62X0_DT
           RaidSonic IB-NAS6210 & IB-NAS6220 devices, using
           Flattened Device Tree.
 
-config MACH_TS219_DT
-        bool "Device Tree for QNAP TS-11X, TS-21X NAS"
-        select ARCH_KIRKWOOD_DT
-        select ARM_APPENDED_DTB
-        select ARM_ATAG_DTB_COMPAT
-        help
-          Say 'Y' here if you want your kernel to support the QNAP
-          TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
-          TS-219P+ Turbo NAS devices using Fattened Device Tree.
-          There are two different Device Tree descriptions, depending
-          on if the device is based on an if the board uses the MV6281
-          or MV6282. If you have the wrong one, the buttons will not
-          work.
-
-config MACH_DOCKSTAR_DT
-        bool "Seagate FreeAgent Dockstar (Flattened Device Tree)"
-        select ARCH_KIRKWOOD_DT
-        help
-          Say 'Y' here if you want your kernel to support the
-          Seagate FreeAgent Dockstar (Flattened Device Tree).
-
-config MACH_GOFLEXNET_DT
-        bool "Seagate GoFlex Net (Flattened Device Tree)"
+config MACH_ICONNECT_DT
+        bool "Iomega Iconnect (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
         help
-          Say 'Y' here if you want your kernel to support the
-          Seagate GoFlex Net (Flattened Device Tree).
+          Say 'Y' here to enable Iomega Iconnect support.
 
-config MACH_LSXL_DT
-        bool "Buffalo Linkstation LS-XHL, LS-CHLv2 (Flattened Device Tree)"
+config MACH_INETSPACE_V2_DT
+        bool "LaCie Internet Space v2 NAS (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
         help
-          Say 'Y' here if you want your kernel to support the
-          Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
-          Flattened Device Tree.
+          Say 'Y' here if you want your kernel to support the LaCie
+          Internet Space v2 NAS, using Flattened Device Tree.
 
 config MACH_IOMEGA_IX2_200_DT
         bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
@@ -144,12 +224,13 @@ config MACH_KM_KIRKWOOD_DT
           Say 'Y' here if you want your kernel to support the
           Keymile Kirkwood Reference Desgin, using Flattened Device Tree.
 
-config MACH_INETSPACE_V2_DT
-        bool "LaCie Internet Space v2 NAS (Flattened Device Tree)"
+config MACH_LSXL_DT
+        bool "Buffalo Linkstation LS-XHL, LS-CHLv2 (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
         help
-          Say 'Y' here if you want your kernel to support the LaCie
-          Internet Space v2 NAS, using Flattened Device Tree.
+          Say 'Y' here if you want your kernel to support the
+          Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
+          Flattened Device Tree.
 
 config MACH_MPLCEC4_DT
         bool "MPL CEC4 (Flattened Device Tree)"
@@ -158,12 +239,12 @@ config MACH_MPLCEC4_DT
           Say 'Y' here if you want your kernel to support the
           MPL CEC4 (Flattened Device Tree).
 
-config MACH_NETSPACE_V2_DT
-        bool "LaCie Network Space v2 NAS (Flattened Device Tree)"
+config MACH_NETSPACE_LITE_V2_DT
+        bool "LaCie Network Space Lite v2 NAS (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
         help
           Say 'Y' here if you want your kernel to support the LaCie
-          Network Space v2 NAS, using Flattened Device Tree.
+          Network Space Lite v2 NAS, using Flattened Device Tree.
 
 config MACH_NETSPACE_MAX_V2_DT
         bool "LaCie Network Space Max v2 NAS (Flattened Device Tree)"
@@ -172,128 +253,69 @@ config MACH_NETSPACE_MAX_V2_DT
           Say 'Y' here if you want your kernel to support the LaCie
           Network Space Max v2 NAS, using Flattened Device Tree.
 
-config MACH_NETSPACE_LITE_V2_DT
-        bool "LaCie Network Space Lite v2 NAS (Flattened Device Tree)"
-        select ARCH_KIRKWOOD_DT
-        help
-          Say 'Y' here if you want your kernel to support the LaCie
-          Network Space Lite v2 NAS, using Flattened Device Tree.
-
 config MACH_NETSPACE_MINI_V2_DT
         bool "LaCie Network Space Mini v2 NAS (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
         help
           Say 'Y' here if you want your kernel to support the LaCie
-          Network Space Mini v2 NAS (aka SafeBox), using Flattened
-          Device Tree.
+          Network Space Mini v2 NAS using Flattened Device Tree.
 
-config MACH_OPENBLOCKS_A6_DT
-        bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)"
-        select ARCH_KIRKWOOD_DT
-        help
-          Say 'Y' here if you want your kernel to support the
-          Plat'Home OpenBlocks A6 (Flattened Device Tree).
+          This board is embedded in a product named CloudBox, which
+          provides automatic backup on a 100GB cloud storage. This
+          should not confused with a more recent LaCie NAS also named
+          CloudBox. For this last, the disk capacity is 1TB or above.
 
-config MACH_TOPKICK_DT
-        bool "USI Topkick (Flattened Device Tree)"
+config MACH_NETSPACE_V2_DT
+        bool "LaCie Network Space v2 NAS (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
         help
-          Say 'Y' here if you want your kernel to support the
-          USI Topkick, using Flattened Device Tree
-
-config MACH_TS219
-        bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
-        help
-          Say 'Y' here if you want your kernel to support the
-          QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
-          TS-219P+ Turbo NAS devices.
-
-config MACH_TS41X
-        bool "QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo NAS"
-        help
-          Say 'Y' here if you want your kernel to support the
-          QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo
-          NAS devices.
-
-config MACH_DOCKSTAR
-        bool "Seagate FreeAgent DockStar"
-        help
-          Say 'Y' here if you want your kernel to support the
-          Seagate FreeAgent DockStar.
-
-config MACH_OPENRD
-        bool
-
-config MACH_OPENRD_BASE
-        bool "Marvell OpenRD Base Board"
-        select MACH_OPENRD
-        help
-          Say 'Y' here if you want your kernel to support the
-          Marvell OpenRD Base Board.
-
-config MACH_OPENRD_CLIENT
-        bool "Marvell OpenRD Client Board"
-        select MACH_OPENRD
-        help
-          Say 'Y' here if you want your kernel to support the
-          Marvell OpenRD Client Board.
-
-config MACH_OPENRD_ULTIMATE
-        bool "Marvell OpenRD Ultimate Board"
-        select MACH_OPENRD
-        help
-          Say 'Y' here if you want your kernel to support the
-          Marvell OpenRD Ultimate Board.
-
-config MACH_NETSPACE_V2
-        bool "LaCie Network Space v2 NAS Board"
-        help
-          Say 'Y' here if you want your kernel to support the
-          LaCie Network Space v2 NAS.
-
-config MACH_INETSPACE_V2
-        bool "LaCie Internet Space v2 NAS Board"
-        help
-          Say 'Y' here if you want your kernel to support the
-          LaCie Internet Space v2 NAS.
-
-config MACH_NETSPACE_MAX_V2
-        bool "LaCie Network Space Max v2 NAS Board"
-        help
-          Say 'Y' here if you want your kernel to support the
-          LaCie Network Space Max v2 NAS.
+          Say 'Y' here if you want your kernel to support the LaCie
+          Network Space v2 NAS, using Flattened Device Tree.
 
-config MACH_D2NET_V2
-        bool "LaCie d2 Network v2 NAS Board"
+config MACH_NSA310_DT
+        bool "ZyXEL NSA-310 (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        select ARM_ATAG_DTB_COMPAT
         help
           Say 'Y' here if you want your kernel to support the
-          LaCie d2 Network v2 NAS.
+          ZyXEL NSA-310 board (Flattened Device Tree).
 
-config MACH_NET2BIG_V2
-        bool "LaCie 2Big Network v2 NAS Board"
+config MACH_OPENBLOCKS_A6_DT
+        bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
         help
           Say 'Y' here if you want your kernel to support the
-          LaCie 2Big Network v2 NAS.
+          Plat'Home OpenBlocks A6 (Flattened Device Tree).
 
-config MACH_NET5BIG_V2
-        bool "LaCie 5Big Network v2 NAS Board"
+config MACH_READYNAS_DT
+        bool "NETGEAR ReadyNAS Duo v2 (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        select ARM_APPENDED_DTB
+        select ARM_ATAG_DTB_COMPAT
         help
           Say 'Y' here if you want your kernel to support the
-          LaCie 5Big Network v2 NAS.
+          NETGEAR ReadyNAS Duo v2 using Fattened Device Tree.
 
-config MACH_T5325
-        bool "HP t5325 Thin Client"
+config MACH_TOPKICK_DT
+        bool "USI Topkick (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
         help
           Say 'Y' here if you want your kernel to support the
-          HP t5325 Thin Client.
+          USI Topkick, using Flattened Device Tree
 
-config MACH_NSA310_DT
-        bool "ZyXEL NSA-310 (Flattened Device Tree)"
+config MACH_TS219_DT
+        bool "Device Tree for QNAP TS-11X, TS-21X NAS"
         select ARCH_KIRKWOOD_DT
+        select ARM_APPENDED_DTB
         select ARM_ATAG_DTB_COMPAT
         help
-          Say 'Y' here if you want your kernel to support the
-          ZyXEL NSA-310 board (Flattened Device Tree).
+          Say 'Y' here if you want your kernel to support the QNAP
+          TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
+          TS-219P+ Turbo NAS devices using Fattened Device Tree.
+          There are two different Device Tree descriptions, depending
+          on if the device is based on an if the board uses the MV6281
+          or MV6282. If you have the wrong one, the buttons will not
+          work.
 
 endmenu
 
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 4cc4bee4d0cf..cdbca328a412 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -1,42 +1,44 @@
 obj-y                           += common.o addr-map.o irq.o pcie.o mpp.o
 
+obj-$(CONFIG_MACH_D2NET_V2)             += d2net_v2-setup.o lacie_v2-common.o
 obj-$(CONFIG_MACH_DB88F6281_BP)         += db88f6281-bp-setup.o
-obj-$(CONFIG_MACH_RD88F6192_NAS)        += rd88f6192-nas-setup.o
-obj-$(CONFIG_MACH_RD88F6281)            += rd88f6281-setup.o
-obj-$(CONFIG_MACH_MV88F6281GTW_GE)      += mv88f6281gtw_ge-setup.o
-obj-$(CONFIG_MACH_SHEEVAPLUG)           += sheevaplug-setup.o
+obj-$(CONFIG_MACH_DOCKSTAR)             += dockstar-setup.o
 obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG)     += sheevaplug-setup.o
 obj-$(CONFIG_MACH_GURUPLUG)             += guruplug-setup.o
-obj-$(CONFIG_MACH_DOCKSTAR)             += dockstar-setup.o
-obj-$(CONFIG_MACH_TS219)                += ts219-setup.o tsx1x-common.o
-obj-$(CONFIG_MACH_TS41X)                += ts41x-setup.o tsx1x-common.o
-obj-$(CONFIG_MACH_OPENRD)               += openrd-setup.o
-obj-$(CONFIG_MACH_NETSPACE_V2)          += netspace_v2-setup.o lacie_v2-common.o
 obj-$(CONFIG_MACH_INETSPACE_V2)         += netspace_v2-setup.o lacie_v2-common.o
-obj-$(CONFIG_MACH_NETSPACE_MAX_V2)      += netspace_v2-setup.o lacie_v2-common.o
-obj-$(CONFIG_MACH_D2NET_V2)             += d2net_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_MV88F6281GTW_GE)      += mv88f6281gtw_ge-setup.o
 obj-$(CONFIG_MACH_NET2BIG_V2)           += netxbig_v2-setup.o lacie_v2-common.o
 obj-$(CONFIG_MACH_NET5BIG_V2)           += netxbig_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_NETSPACE_MAX_V2)      += netspace_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_NETSPACE_V2)          += netspace_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_OPENRD)               += openrd-setup.o
+obj-$(CONFIG_MACH_RD88F6192_NAS)        += rd88f6192-nas-setup.o
+obj-$(CONFIG_MACH_RD88F6281)            += rd88f6281-setup.o
+obj-$(CONFIG_MACH_SHEEVAPLUG)           += sheevaplug-setup.o
 obj-$(CONFIG_MACH_T5325)                += t5325-setup.o
+obj-$(CONFIG_MACH_TS219)                += ts219-setup.o tsx1x-common.o
+obj-$(CONFIG_MACH_TS41X)                += ts41x-setup.o tsx1x-common.o
 
 obj-$(CONFIG_ARCH_KIRKWOOD_DT)          += board-dt.o
-obj-$(CONFIG_MACH_DREAMPLUG_DT)         += board-dreamplug.o
-obj-$(CONFIG_MACH_GURUPLUG_DT)          += board-guruplug.o
-obj-$(CONFIG_MACH_ICONNECT_DT)          += board-iconnect.o
+obj-$(CONFIG_MACH_CLOUDBOX_DT)          += board-ns2.o
 obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT)    += board-dnskw.o
-obj-$(CONFIG_MACH_IB62X0_DT)            += board-ib62x0.o
-obj-$(CONFIG_MACH_TS219_DT)             += board-ts219.o tsx1x-common.o
 obj-$(CONFIG_MACH_DOCKSTAR_DT)          += board-dockstar.o
+obj-$(CONFIG_MACH_DREAMPLUG_DT)         += board-dreamplug.o
 obj-$(CONFIG_MACH_GOFLEXNET_DT)         += board-goflexnet.o
-obj-$(CONFIG_MACH_LSXL_DT)              += board-lsxl.o
+obj-$(CONFIG_MACH_GURUPLUG_DT)          += board-guruplug.o
+obj-$(CONFIG_MACH_IB62X0_DT)            += board-ib62x0.o
+obj-$(CONFIG_MACH_ICONNECT_DT)          += board-iconnect.o
+obj-$(CONFIG_MACH_INETSPACE_V2_DT)      += board-ns2.o
 obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT)    += board-iomega_ix2_200.o
 obj-$(CONFIG_MACH_KM_KIRKWOOD_DT)       += board-km_kirkwood.o
-obj-$(CONFIG_MACH_INETSPACE_V2_DT)      += board-ns2.o
+obj-$(CONFIG_MACH_LSXL_DT)              += board-lsxl.o
 obj-$(CONFIG_MACH_MPLCEC4_DT)           += board-mplcec4.o
-obj-$(CONFIG_MACH_NETSPACE_V2_DT)       += board-ns2.o
-obj-$(CONFIG_MACH_NETSPACE_MAX_V2_DT)   += board-ns2.o
 obj-$(CONFIG_MACH_NETSPACE_LITE_V2_DT)  += board-ns2.o
+obj-$(CONFIG_MACH_NETSPACE_MAX_V2_DT)   += board-ns2.o
 obj-$(CONFIG_MACH_NETSPACE_MINI_V2_DT)  += board-ns2.o
+obj-$(CONFIG_MACH_NETSPACE_V2_DT)       += board-ns2.o
 obj-$(CONFIG_MACH_NSA310_DT)            += board-nsa310.o
 obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT)     += board-openblocks_a6.o
+obj-$(CONFIG_MACH_READYNAS_DT)          += board-readynas.o
 obj-$(CONFIG_MACH_TOPKICK_DT)           += board-usi_topkick.o
+obj-$(CONFIG_MACH_TS219_DT)             += board-ts219.o tsx1x-common.o
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index d367aa6b47bb..7904758e771f 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -139,16 +139,20 @@ static void __init kirkwood_dt_init(void)
         if (of_machine_is_compatible("keymile,km_kirkwood"))
                 km_kirkwood_init();
 
-        if (of_machine_is_compatible("lacie,inetspace_v2") ||
-            of_machine_is_compatible("lacie,netspace_v2") ||
-            of_machine_is_compatible("lacie,netspace_max_v2") ||
+        if (of_machine_is_compatible("lacie,cloudbox") ||
+            of_machine_is_compatible("lacie,inetspace_v2") ||
             of_machine_is_compatible("lacie,netspace_lite_v2") ||
-            of_machine_is_compatible("lacie,netspace_mini_v2"))
+            of_machine_is_compatible("lacie,netspace_max_v2") ||
+            of_machine_is_compatible("lacie,netspace_mini_v2") ||
+            of_machine_is_compatible("lacie,netspace_v2"))
                 ns2_init();
 
         if (of_machine_is_compatible("mpl,cec4"))
                 mplcec4_init();
 
+        if (of_machine_is_compatible("netgear,readynas-duo-v2"))
+                netgear_readynas_init();
+
         if (of_machine_is_compatible("plathome,openblocks-a6"))
                 openblocks_a6_init();
 
@@ -171,12 +175,14 @@ static const char * const kirkwood_dt_board_compat[] = {
         "buffalo,lsxl",
         "iom,ix2-200",
         "keymile,km_kirkwood",
+        "lacie,cloudbox",
         "lacie,inetspace_v2",
-        "lacie,netspace_max_v2",
-        "lacie,netspace_v2",
         "lacie,netspace_lite_v2",
+        "lacie,netspace_max_v2",
         "lacie,netspace_mini_v2",
+        "lacie,netspace_v2",
         "mpl,cec4",
+        "netgear,readynas-duo-v2",
         "plathome,openblocks-a6",
         "usi,topkick",
         "zyxel,nsa310",
diff --git a/arch/arm/mach-kirkwood/board-guruplug.c b/arch/arm/mach-kirkwood/board-guruplug.c
index 0a0df4554d8b..a857163954a5 100644
--- a/arch/arm/mach-kirkwood/board-guruplug.c
+++ b/arch/arm/mach-kirkwood/board-guruplug.c
@@ -13,7 +13,6 @@
 #include <linux/init.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
-#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 
 static struct mv643xx_eth_platform_data guruplug_ge00_data = {
@@ -24,10 +23,6 @@ static struct mv643xx_eth_platform_data guruplug_ge01_data = {
         .phy_addr       = MV643XX_ETH_PHY_ADDR(1),
 };
 
-static struct mvsdio_platform_data guruplug_mvsdio_data = {
-        /* unfortunately the CD signal has not been connected */
-};
-
 void __init guruplug_dt_init(void)
 {
         /*
@@ -35,5 +30,4 @@ void __init guruplug_dt_init(void)
          */
         kirkwood_ge00_init(&guruplug_ge00_data);
         kirkwood_ge01_init(&guruplug_ge01_data);
-        kirkwood_sdio_init(&guruplug_mvsdio_data);
 }
diff --git a/arch/arm/mach-kirkwood/board-ns2.c b/arch/arm/mach-kirkwood/board-ns2.c
index f2ea3b7ad726..f8f660525ace 100644
--- a/arch/arm/mach-kirkwood/board-ns2.c
+++ b/arch/arm/mach-kirkwood/board-ns2.c
@@ -27,7 +27,8 @@ void __init ns2_init(void)
         /*
          * Basic setup. Needs to be called early.
          */
-        if (of_machine_is_compatible("lacie,netspace_lite_v2") ||
+        if (of_machine_is_compatible("lacie,cloudbox") ||
+            of_machine_is_compatible("lacie,netspace_lite_v2") ||
             of_machine_is_compatible("lacie,netspace_mini_v2"))
                 ns2_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
         kirkwood_ge00_init(&ns2_ge00_data);
diff --git a/arch/arm/mach-kirkwood/board-readynas.c b/arch/arm/mach-kirkwood/board-readynas.c
new file mode 100644
index 000000000000..fb42c20e273f
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-readynas.c
@@ -0,0 +1,28 @@
+/*
+ * NETGEAR ReadyNAS Duo v2 Board setup for drivers not already
+ * converted to DT.
+ *
+ * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mv643xx_eth.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+
+static struct mv643xx_eth_platform_data netgear_readynas_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+void __init netgear_readynas_init(void)
+{
+        kirkwood_ge00_init(&netgear_readynas_ge00_data);
+        kirkwood_pcie_init(KW_PCIE0);
+}
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 5ed70565c843..3147be2f34da 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -141,12 +141,24 @@ void openblocks_a6_init(void);
 static inline void openblocks_a6_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_READYNAS_DT
+void netgear_readynas_init(void);
+#else
+static inline void netgear_readynas_init(void) {};
+#endif
+
 #ifdef CONFIG_MACH_TOPKICK_DT
 void usi_topkick_init(void);
 #else
 static inline void usi_topkick_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_CLOUDBOX_DT
+void cloudbox_init(void);
+#else
+static inline void cloudbox_init(void) {};
+#endif
+
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
diff --git a/arch/arm/mach-l7200/include/mach/debug-macro.S b/arch/arm/mach-l7200/include/mach/debug-macro.S
deleted file mode 100644
index 0b4e760159b9..000000000000
--- a/arch/arm/mach-l7200/include/mach/debug-macro.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/* arch/arm/mach-l7200/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-                .equ    io_virt, IO_BASE
-                .equ    io_phys, IO_START
-
-                .macro  addruart, rp, rv, tmp
-                mov     \rp, #0x00044000        @ UART1
-@               mov     \rp, #0x00045000        @ UART2
-                add     \rv, \rp, #io_virt      @ virtual address
-                add     \rp, \rp, #io_phys      @ physical base address
-                .endm
-
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #0x0]        @ UARTDR
-                .endm
-
-                .macro  waituart,rd,rx
-1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
-                tst     \rd, #1 << 5            @ UARTFLGUTXFF - 1 when full
-                bne     1001b
-                .endm
-
-                .macro  busyuart,rd,rx
-1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
-                tst     \rd, #1 << 3            @ UARTFLGUBUSY - 1 when busy
-                bne     1001b
-                .endm
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 9f64d5632e07..5b660ec09ef5 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -9,6 +9,7 @@
  *  publishhed by the Free Software Foundation.
  */
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
@@ -110,6 +111,10 @@ static unsigned long common_pin_config[] __initdata = {
         GPIO121_KP_MKIN4,
 };
 
+static struct pxa_gpio_platform_data pxa168_gpio_pdata = {
+        .irq_base       = MMP_GPIO_TO_IRQ(0),
+};
+
 static struct smc91x_platdata smc91x_info = {
         .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
 };
@@ -223,13 +228,7 @@ static struct pxa27x_keypad_platform_data aspenite_keypad_info __initdata = {
 };
 
 #if defined(CONFIG_USB_EHCI_MV)
-static char *pxa168_sph_clock_name[] = {
-        [0] = "PXA168-USBCLK",
-};
-
 static struct mv_usb_platform_data pxa168_sph_pdata = {
-        .clknum         = 1,
-        .clkname        = pxa168_sph_clock_name,
         .mode           = MV_USB_MODE_HOST,
         .phy_init       = pxa_usb_phy_init,
         .phy_deinit     = pxa_usb_phy_deinit,
@@ -248,6 +247,8 @@ static void __init common_init(void)
         pxa168_add_nand(&aspenite_nand_info);
         pxa168_add_fb(&aspenite_lcd_info);
         pxa168_add_keypad(&aspenite_keypad_info);
+        platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata,
+                                 sizeof(struct pxa_gpio_platform_data));
         platform_device_register(&pxa168_device_gpio);
 
         /* off-chip devices */
diff --git a/arch/arm/mach-mmp/avengers_lite.c b/arch/arm/mach-mmp/avengers_lite.c
index 1f94957b56ae..a451a0f4d512 100644
--- a/arch/arm/mach-mmp/avengers_lite.c
+++ b/arch/arm/mach-mmp/avengers_lite.c
@@ -12,6 +12,7 @@
 
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/gpio-pxa.h>
 #include <linux/platform_device.h>
 
 #include <asm/mach-types.h>
@@ -32,12 +33,18 @@ static unsigned long avengers_lite_pin_config_V16F[] __initdata = {
         GPIO89_UART2_RXD,
 };
 
+static struct pxa_gpio_platform_data pxa168_gpio_pdata = {
+        .irq_base       = MMP_GPIO_TO_IRQ(0),
+};
+
 static void __init avengers_lite_init(void)
 {
         mfp_config(ARRAY_AND_SIZE(avengers_lite_pin_config_V16F));
 
         /* on-chip devices */
         pxa168_add_uart(2);
+        platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata,
+                                 sizeof(struct pxa_gpio_platform_data));
         platform_device_register(&pxa168_device_gpio);
 }
 
diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c
index 2358011c7d8e..ac25544b8cdb 100644
--- a/arch/arm/mach-mmp/brownstone.c
+++ b/arch/arm/mach-mmp/brownstone.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/gpio-pxa.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/max8649.h>
 #include <linux/regulator/fixed.h>
@@ -104,6 +105,10 @@ static unsigned long brownstone_pin_config[] __initdata = {
         GPIO89_GPIO,
 };
 
+static struct pxa_gpio_platform_data mmp2_gpio_pdata = {
+        .irq_base       = MMP_GPIO_TO_IRQ(0),
+};
+
 static struct regulator_consumer_supply max8649_supply[] = {
         REGULATOR_SUPPLY("vcc_core", NULL),
 };
@@ -202,6 +207,8 @@ static void __init brownstone_init(void)
         /* on-chip devices */
         mmp2_add_uart(1);
         mmp2_add_uart(3);
+        platform_device_add_data(&mmp2_device_gpio, &mmp2_gpio_pdata,
+                                 sizeof(struct pxa_gpio_platform_data));
         platform_device_register(&mmp2_device_gpio);
         mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info));
         mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
diff --git a/arch/arm/mach-mmp/clock-mmp2.c b/arch/arm/mach-mmp/clock-mmp2.c
index 21d22002cd19..53d77cbd6000 100644
--- a/arch/arm/mach-mmp/clock-mmp2.c
+++ b/arch/arm/mach-mmp/clock-mmp2.c
@@ -98,7 +98,7 @@ static struct clk_lookup mmp2_clkregs[] = {
         INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
         INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
-        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_gpio, "mmp2-gpio", NULL),
         INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
         INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
         INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
diff --git a/arch/arm/mach-mmp/clock-pxa168.c b/arch/arm/mach-mmp/clock-pxa168.c
index 5e6c18ccebd4..c572f219ae26 100644
--- a/arch/arm/mach-mmp/clock-pxa168.c
+++ b/arch/arm/mach-mmp/clock-pxa168.c
@@ -78,7 +78,7 @@ static struct clk_lookup pxa168_clkregs[] = {
         INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
         INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
-        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_gpio, "mmp-gpio", NULL),
         INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
         INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
         INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
diff --git a/arch/arm/mach-mmp/clock-pxa910.c b/arch/arm/mach-mmp/clock-pxa910.c
index 933ea71d0b56..379e1df61c70 100644
--- a/arch/arm/mach-mmp/clock-pxa910.c
+++ b/arch/arm/mach-mmp/clock-pxa910.c
@@ -56,7 +56,7 @@ static struct clk_lookup pxa910_clkregs[] = {
         INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
         INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
-        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_gpio, "mmp-gpio", NULL),
         INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
         INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
 };
diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c
index 754c352dd02b..6291c33d83e2 100644
--- a/arch/arm/mach-mmp/flint.c
+++ b/arch/arm/mach-mmp/flint.c
@@ -16,6 +16,7 @@
 #include <linux/smc91x.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/interrupt.h>
 
 #include <asm/mach-types.h>
@@ -77,6 +78,10 @@ static unsigned long flint_pin_config[] __initdata = {
         GPIO160_ND_RDY1,
 };
 
+static struct pxa_gpio_platform_data mmp2_gpio_pdata = {
+        .irq_base       = MMP_GPIO_TO_IRQ(0),
+};
+
 static struct smc91x_platdata flint_smc91x_info = {
         .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
 };
@@ -111,6 +116,8 @@ static void __init flint_init(void)
         /* on-chip devices */
         mmp2_add_uart(1);
         mmp2_add_uart(2);
+        platform_device_add_data(&mmp2_device_gpio, &mmp2_gpio_pdata,
+                                 sizeof(struct pxa_gpio_platform_data));
         platform_device_register(&mmp2_device_gpio);
 
         /* off-chip devices */
diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c
index f62b68d926f4..d81b2475e67e 100644
--- a/arch/arm/mach-mmp/gplugd.c
+++ b/arch/arm/mach-mmp/gplugd.c
@@ -11,6 +11,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -128,6 +129,10 @@ static unsigned long gplugd_pin_config[] __initdata = {
         GPIO116_I2S_TXD
 };
 
+static struct pxa_gpio_platform_data pxa168_gpio_pdata = {
+        .irq_base       = MMP_GPIO_TO_IRQ(0),
+};
+
 static struct i2c_board_info gplugd_i2c_board_info[] = {
         {
                 .type = "isl1208",
@@ -186,6 +191,8 @@ static void __init gplugd_init(void)
         pxa168_add_uart(3);
         pxa168_add_ssp(1);
         pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(gplugd_i2c_board_info));
+        platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata,
+                                 sizeof(struct pxa_gpio_platform_data));
         platform_device_register(&pxa168_device_gpio);
 
         pxa168_add_eth(&gplugd_eth_platform_data);
diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S
deleted file mode 100644
index 5c3cc29688ab..000000000000
--- a/arch/arm/mach-mmp/include/mach/debug-macro.S
+++ /dev/null
@@ -1,30 +0,0 @@
-/* arch/arm/mach-mmp/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copied from arch/arm/mach-pxa/include/mach/debug.S
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#if defined(CONFIG_DEBUG_MMP_UART2)
-#define MMP_UART_OFFSET 0x00017000
-#elif defined(CONFIG_DEBUG_MMP_UART3)
-#define MMP_UART_OFFSET 0x00018000
-#else
-#error "Select uart for DEBUG_LL"
-#endif
-
-#include <mach/addr-map.h>
-
-                .macro  addruart, rp, rv, tmp
-                ldr     \rp, =APB_PHYS_BASE             @ physical
-                ldr     \rv, =APB_VIRT_BASE             @ virtual
-                orr     \rp, \rp, #MMP_UART_OFFSET
-                orr     \rv, \rv, #MMP_UART_OFFSET
-                .endm
-
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c
index 66634fd0ecb0..0e9e5c05b37c 100644
--- a/arch/arm/mach-mmp/jasper.c
+++ b/arch/arm/mach-mmp/jasper.c
@@ -12,6 +12,7 @@
 
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/gpio-pxa.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/regulator/machine.h>
@@ -99,6 +100,10 @@ static unsigned long jasper_pin_config[] __initdata = {
         GPIO151_MMC3_CLK,
 };
 
+static struct pxa_gpio_platform_data mmp2_gpio_pdata = {
+        .irq_base       = MMP_GPIO_TO_IRQ(0),
+};
+
 static struct regulator_consumer_supply max8649_supply[] = {
         REGULATOR_SUPPLY("vcc_core", NULL),
 };
@@ -165,6 +170,9 @@ static void __init jasper_init(void)
         mmp2_add_uart(1);
         mmp2_add_uart(3);
         mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info));
+        platform_device_add_data(&mmp2_device_gpio, &mmp2_gpio_pdata,
+                                 sizeof(struct pxa_gpio_platform_data));
+        platform_device_register(&mmp2_device_gpio);
         mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
 
         regulator_has_full_constraints();
diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
index d063efa0a4f1..b37915dc4470 100644
--- a/arch/arm/mach-mmp/mmp-dt.c
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -28,7 +28,7 @@ static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
         OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4026000, "pxa2xx-uart.2", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
+        OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp-gpio", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
         {}
 };
@@ -39,7 +39,7 @@ static const struct of_dev_auxdata pxa910_auxdata_lookup[] __initconst = {
         OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4036000, "pxa2xx-uart.2", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4037000, "pxa2xx-i2c.1", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
+        OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp-gpio", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
         {}
 };
diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c
index fad431aa6e09..4ac256720f7d 100644
--- a/arch/arm/mach-mmp/mmp2-dt.c
+++ b/arch/arm/mach-mmp/mmp2-dt.c
@@ -31,7 +31,7 @@ static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
         OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4016000, "pxa2xx-uart.3", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
-        OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
+        OF_DEV_AUXDATA("marvell,mmp-gpio", 0xd4019000, "mmp2-gpio", NULL),
         OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
         {}
 };
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index d94d114eef7b..c7592f168bbd 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -164,7 +164,7 @@ struct resource mmp2_resource_gpio[] = {
 };
 
 struct platform_device mmp2_device_gpio = {
-        .name           = "pxa-gpio",
+        .name           = "mmp2-gpio",
         .id             = -1,
         .num_resources  = ARRAY_SIZE(mmp2_resource_gpio),
         .resource       = mmp2_resource_gpio,
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 9bc7b86a86a7..a30dcf3b7d9e 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -125,7 +125,7 @@ struct resource pxa168_resource_gpio[] = {
 };
 
 struct platform_device pxa168_device_gpio = {
-        .name           = "pxa-gpio",
+        .name           = "mmp-gpio",
         .id             = -1,
         .num_resources  = ARRAY_SIZE(pxa168_resource_gpio),
         .resource       = pxa168_resource_gpio,
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 36cb321a3d70..ce6393acad86 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -152,7 +152,7 @@ struct resource pxa910_resource_gpio[] = {
 };
 
 struct platform_device pxa910_device_gpio = {
-        .name           = "pxa-gpio",
+        .name           = "mmp-gpio",
         .id             = -1,
         .num_resources  = ARRAY_SIZE(pxa910_resource_gpio),
         .resource       = pxa910_resource_gpio,
diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c
index 4c127d23955d..cdfc9bfee1a4 100644
--- a/arch/arm/mach-mmp/tavorevb.c
+++ b/arch/arm/mach-mmp/tavorevb.c
@@ -8,6 +8,7 @@
  *  publishhed by the Free Software Foundation.
  */
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
@@ -60,6 +61,10 @@ static unsigned long tavorevb_pin_config[] __initdata = {
         DF_RDY0_DF_RDY0,
 };
 
+static struct pxa_gpio_platform_data pxa910_gpio_pdata = {
+        .irq_base       = MMP_GPIO_TO_IRQ(0),
+};
+
 static struct smc91x_platdata tavorevb_smc91x_info = {
         .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
 };
@@ -93,6 +98,8 @@ static void __init tavorevb_init(void)
 
         /* on-chip devices */
         pxa910_add_uart(1);
+        platform_device_add_data(&pxa910_device_gpio, &pxa910_gpio_pdata,
+                                 sizeof(struct pxa_gpio_platform_data));
         platform_device_register(&pxa910_device_gpio);
 
         /* off-chip devices */
diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c
index 8609967975ed..e4d95b4c6bb2 100644
--- a/arch/arm/mach-mmp/teton_bga.c
+++ b/arch/arm/mach-mmp/teton_bga.c
@@ -16,6 +16,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/input.h>
 #include <linux/platform_data/keypad-pxa27x.h>
 #include <linux/i2c.h>
@@ -49,6 +50,10 @@ static unsigned long teton_bga_pin_config[] __initdata = {
         GPIO78_GPIO,
 };
 
+static struct pxa_gpio_platform_data pxa168_gpio_pdata = {
+        .irq_base       = MMP_GPIO_TO_IRQ(0),
+};
+
 static unsigned int teton_bga_matrix_key_map[] = {
         KEY(0, 6, KEY_ESC),
         KEY(0, 7, KEY_ENTER),
@@ -79,6 +84,8 @@ static void __init teton_bga_init(void)
         pxa168_add_uart(1);
         pxa168_add_keypad(&teton_bga_keypad_info);
         pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(teton_bga_i2c_info));
+        platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata,
+                                 sizeof(struct pxa_gpio_platform_data));
         platform_device_register(&pxa168_device_gpio);
 }
 
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index 22a9058f9f4d..8483906d4308 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -17,6 +17,7 @@
 #include <linux/interrupt.h>
 #include <linux/i2c/pca953x.h>
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/mfd/88pm860x.h>
 #include <linux/platform_data/mv_usb.h>
 #include <linux/spi/spi.h>
@@ -75,6 +76,10 @@ static unsigned long ttc_dkb_pin_config[] __initdata = {
         DF_RDY0_DF_RDY0,
 };
 
+static struct pxa_gpio_platform_data pxa910_gpio_pdata = {
+        .irq_base       = MMP_GPIO_TO_IRQ(0),
+};
+
 static struct mtd_partition ttc_dkb_onenand_partitions[] = {
         {
                 .name           = "bootloader",
@@ -162,13 +167,7 @@ static struct i2c_board_info ttc_dkb_i2c_info[] = {
 #ifdef CONFIG_USB_SUPPORT
 #if defined(CONFIG_USB_MV_UDC) || defined(CONFIG_USB_EHCI_MV_U2O)
 
-static char *pxa910_usb_clock_name[] = {
-        [0] = "U2OCLK",
-};
-
 static struct mv_usb_platform_data ttc_usb_pdata = {
-        .clknum         = 1,
-        .clkname        = pxa910_usb_clock_name,
         .vbus           = NULL,
         .mode           = MV_USB_MODE_OTG,
         .otg_force_a_bus_req = 1,
@@ -284,6 +283,8 @@ static void __init ttc_dkb_init(void)
 
         /* off-chip devices */
         pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info));
+        platform_device_add_data(&pxa910_device_gpio, &pxa910_gpio_pdata,
+                                 sizeof(struct pxa_gpio_platform_data));
         platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices));
 
 #ifdef CONFIG_USB_MV_UDC
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index b61908594b47..fceb093b9494 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -44,10 +44,10 @@ endchoice
 
 config ARCH_MSM8X60
         bool "MSM8X60"
-        select ARCH_MSM_SCORPIONMP
         select ARM_GIC
         select CPU_V7
         select GPIO_MSM_V2
+        select HAVE_SMP
         select MSM_GPIOMUX
         select MSM_SCM if SMP
         select MSM_V2_TLMM
@@ -55,9 +55,9 @@ config ARCH_MSM8X60
 
 config ARCH_MSM8960
         bool "MSM8960"
-        select ARCH_MSM_SCORPIONMP
         select ARM_GIC
         select CPU_V7
+        select HAVE_SMP
         select MSM_GPIOMUX
         select MSM_SCM if SMP
         select MSM_V2_TLMM
@@ -68,9 +68,6 @@ config MSM_HAS_DEBUG_UART_HS
 
 config MSM_SOC_REV_A
         bool
-config  ARCH_MSM_SCORPIONMP
-        bool
-        select HAVE_SMP
 
 config  ARCH_MSM_ARM11
         bool
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 84d720af34ab..82eaf88d2026 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -59,6 +59,7 @@ static struct platform_device smc91x_device = {
 };
 
 static struct platform_device *devices[] __initdata = {
+        &msm_device_gpio_7201,
         &msm_device_uart3,
         &msm_device_smd,
         &msm_device_nand,
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index 7bc3f82e3ec9..520c141acd03 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -89,6 +89,7 @@ struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
 };
 
 static struct platform_device *devices[] __initdata = {
+        &msm_device_gpio_7x30,
 #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
         &msm_device_uart2,
 #endif
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 686e7949a73a..38a532d6937c 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -89,6 +89,7 @@ static struct msm_otg_platform_data msm_otg_pdata = {
 };
 
 static struct platform_device *devices[] __initdata = {
+        &msm_device_gpio_8x50,
         &msm_device_uart3,
         &msm_device_smd,
         &msm_device_otg,
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 919bfa32871a..80fe1c5ff5c1 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -36,6 +36,7 @@
 extern int trout_init_mmc(unsigned int);
 
 static struct platform_device *devices[] __initdata = {
+        &msm_device_gpio_7201,
         &msm_device_uart3,
         &msm_device_smd,
         &msm_device_nand,
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c
index f66ee6ea8720..1a0a2306b115 100644
--- a/arch/arm/mach-msm/devices-msm7x00.c
+++ b/arch/arm/mach-msm/devices-msm7x00.c
@@ -29,6 +29,37 @@
 #include "clock-pcom.h"
 #include <linux/platform_data/mmc-msm_sdcc.h>
 
+static struct resource msm_gpio_resources[] = {
+        {
+                .start  = 32 + 0,
+                .end    = 32 + 0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = 32 + 1,
+                .end    = 32 + 1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = 0xa9200800,
+                .end    = 0xa9200800 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+                .name  = "gpio1"
+        },
+        {
+                .start  = 0xa9300C00,
+                .end    = 0xa9300C00 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+                .name  = "gpio2"
+        },
+};
+
+struct platform_device msm_device_gpio_7201 = {
+        .name   = "gpio-msm-7201",
+        .num_resources  = ARRAY_SIZE(msm_gpio_resources),
+        .resource       = msm_gpio_resources,
+};
+
 static struct resource resources_uart1[] = {
         {
                 .start  = INT_UART1,
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index e90ab5938c5f..12f482c07740 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -33,6 +33,37 @@
 
 #include <linux/platform_data/mmc-msm_sdcc.h>
 
+static struct resource msm_gpio_resources[] = {
+        {
+                .start  = 32 + 18,
+                .end    = 32 + 18,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = 32 + 19,
+                .end    = 32 + 19,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = 0xac001000,
+                .end    = 0xac001000 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+                .name  = "gpio1"
+        },
+        {
+                .start  = 0xac101400,
+                .end    = 0xac101400 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+                .name  = "gpio2"
+        },
+};
+
+struct platform_device msm_device_gpio_7x30 = {
+        .name   = "gpio-msm-7x30",
+        .num_resources  = ARRAY_SIZE(msm_gpio_resources),
+        .resource       = msm_gpio_resources,
+};
+
 static struct resource resources_uart2[] = {
         {
                 .start  = INT_UART2,
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 4db61d5fe317..2e1b3ec9dfc7 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -30,6 +30,37 @@
 #include <linux/platform_data/mmc-msm_sdcc.h>
 #include "clock-pcom.h"
 
+static struct resource msm_gpio_resources[] = {
+        {
+                .start  = 64 + 165 + 9,
+                .end    = 64 + 165 + 9,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = 64 + 165 + 10,
+                .end    = 64 + 165 + 10,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = 0xa9000800,
+                .end    = 0xa9000800 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+                .name  = "gpio1"
+        },
+        {
+                .start  = 0xa9100C00,
+                .end    = 0xa9100C00 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+                .name  = "gpio2"
+        },
+};
+
+struct platform_device msm_device_gpio_8x50 = {
+        .name   = "gpio-msm-8x50",
+        .num_resources  = ARRAY_SIZE(msm_gpio_resources),
+        .resource       = msm_gpio_resources,
+};
+
 static struct resource resources_uart3[] = {
         {
                 .start  = INT_UART3,
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index 9545c196c6e8..da902cf51161 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -20,6 +20,10 @@
 
 #include "clock.h"
 
+extern struct platform_device msm_device_gpio_7201;
+extern struct platform_device msm_device_gpio_7x30;
+extern struct platform_device msm_device_gpio_8x50;
+
 extern struct platform_device msm_device_uart1;
 extern struct platform_device msm_device_uart2;
 extern struct platform_device msm_device_uart3;
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c
index 354b91d4c3ac..b279fd8a31b1 100644
--- a/arch/arm/mach-msm/dma.c
+++ b/arch/arm/mach-msm/dma.c
@@ -19,9 +19,35 @@
 #include <linux/interrupt.h>
 #include <linux/completion.h>
 #include <mach/dma.h>
+#include <mach/msm_iomap.h>
 
 #define MSM_DMOV_CHANNEL_COUNT 16
 
+#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
+#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2))
+#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2))
+#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2))
+
+#if defined(CONFIG_ARCH_MSM7X30)
+#define DMOV_SD_AARM DMOV_SD2
+#else
+#define DMOV_SD_AARM DMOV_SD3
+#endif
+
+#define DMOV_CMD_PTR(ch)      DMOV_SD_AARM(0x000, ch)
+#define DMOV_RSLT(ch)         DMOV_SD_AARM(0x040, ch)
+#define DMOV_FLUSH0(ch)       DMOV_SD_AARM(0x080, ch)
+#define DMOV_FLUSH1(ch)       DMOV_SD_AARM(0x0C0, ch)
+#define DMOV_FLUSH2(ch)       DMOV_SD_AARM(0x100, ch)
+#define DMOV_FLUSH3(ch)       DMOV_SD_AARM(0x140, ch)
+#define DMOV_FLUSH4(ch)       DMOV_SD_AARM(0x180, ch)
+#define DMOV_FLUSH5(ch)       DMOV_SD_AARM(0x1C0, ch)
+
+#define DMOV_STATUS(ch)       DMOV_SD_AARM(0x200, ch)
+#define DMOV_ISR              DMOV_SD_AARM(0x380, 0)
+
+#define DMOV_CONFIG(ch)       DMOV_SD_AARM(0x300, ch)
+
 enum {
         MSM_DMOV_PRINT_ERRORS = 1,
         MSM_DMOV_PRINT_IO = 2,
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c
index 750446feb444..326a87261f9a 100644
--- a/arch/arm/mach-msm/hotplug.c
+++ b/arch/arm/mach-msm/hotplug.c
@@ -10,16 +10,12 @@
 #include <linux/errno.h>
 #include <linux/smp.h>
 
-#include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 
 #include "common.h"
 
 static inline void cpu_enter_lowpower(void)
 {
-        /* Just flush the cache. Changing the coherency is not yet
-         * available on msm. */
-        flush_cache_all();
 }
 
 static inline void cpu_leave_lowpower(void)
diff --git a/arch/arm/mach-msm/include/mach/cpu.h b/arch/arm/mach-msm/include/mach/cpu.h
deleted file mode 100644
index a9481b08d5c7..000000000000
--- a/arch/arm/mach-msm/include/mach/cpu.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-
-#ifndef __ARCH_ARM_MACH_MSM_CPU_H__
-#define __ARCH_ARM_MACH_MSM_CPU_H__
-
-/* TODO: For now, only one CPU can be compiled at a time. */
-
-#define cpu_is_msm7x01()        0
-#define cpu_is_msm7x30()        0
-#define cpu_is_qsd8x50()        0
-#define cpu_is_msm8x60()        0
-#define cpu_is_msm8960()        0
-
-#ifdef CONFIG_ARCH_MSM7X00A
-# undef cpu_is_msm7x01
-# define cpu_is_msm7x01()       1
-#endif
-
-#ifdef CONFIG_ARCH_MSM7X30
-# undef cpu_is_msm7x30
-# define cpu_is_msm7x30()       1
-#endif
-
-#ifdef CONFIG_ARCH_QSD8X50
-# undef cpu_is_qsd8x50
-# define cpu_is_qsd8x50()       1
-#endif
-
-#ifdef CONFIG_ARCH_MSM8X60
-# undef cpu_is_msm8x60
-# define cpu_is_msm8x60()       1
-#endif
-
-#ifdef CONFIG_ARCH_MSM8960
-# undef cpu_is_msm8960
-# define cpu_is_msm8960()       1
-#endif
-
-#endif
diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
index 05583f569524..a72d48d42342 100644
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ b/arch/arm/mach-msm/include/mach/dma.h
@@ -16,7 +16,6 @@
 #ifndef __ASM_ARCH_MSM_DMA_H
 
 #include <linux/list.h>
-#include <mach/msm_iomap.h>
 
 struct msm_dmov_errdata {
         uint32_t flush[6];
@@ -45,48 +44,23 @@ static inline
 int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) { return -EIO; }
 #endif
 
-
-#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
-#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2))
-#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2))
-#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2))
-
-#if defined(CONFIG_ARCH_MSM7X30)
-#define DMOV_SD_AARM DMOV_SD2
-#else
-#define DMOV_SD_AARM DMOV_SD3
-#endif
-
-#define DMOV_CMD_PTR(ch)      DMOV_SD_AARM(0x000, ch)
 #define DMOV_CMD_LIST         (0 << 29) /* does not work */
 #define DMOV_CMD_PTR_LIST     (1 << 29) /* works */
 #define DMOV_CMD_INPUT_CFG    (2 << 29) /* untested */
 #define DMOV_CMD_OUTPUT_CFG   (3 << 29) /* untested */
 #define DMOV_CMD_ADDR(addr)   ((addr) >> 3)
 
-#define DMOV_RSLT(ch)         DMOV_SD_AARM(0x040, ch)
 #define DMOV_RSLT_VALID       (1 << 31) /* 0 == host has empties result fifo */
 #define DMOV_RSLT_ERROR       (1 << 3)
 #define DMOV_RSLT_FLUSH       (1 << 2)
 #define DMOV_RSLT_DONE        (1 << 1)  /* top pointer done */
 #define DMOV_RSLT_USER        (1 << 0)  /* command with FR force result */
 
-#define DMOV_FLUSH0(ch)       DMOV_SD_AARM(0x080, ch)
-#define DMOV_FLUSH1(ch)       DMOV_SD_AARM(0x0C0, ch)
-#define DMOV_FLUSH2(ch)       DMOV_SD_AARM(0x100, ch)
-#define DMOV_FLUSH3(ch)       DMOV_SD_AARM(0x140, ch)
-#define DMOV_FLUSH4(ch)       DMOV_SD_AARM(0x180, ch)
-#define DMOV_FLUSH5(ch)       DMOV_SD_AARM(0x1C0, ch)
-
-#define DMOV_STATUS(ch)       DMOV_SD_AARM(0x200, ch)
 #define DMOV_STATUS_RSLT_COUNT(n)    (((n) >> 29))
 #define DMOV_STATUS_CMD_COUNT(n)     (((n) >> 27) & 3)
 #define DMOV_STATUS_RSLT_VALID       (1 << 1)
 #define DMOV_STATUS_CMD_PTR_RDY      (1 << 0)
 
-#define DMOV_ISR              DMOV_SD_AARM(0x380, 0)
-  
-#define DMOV_CONFIG(ch)       DMOV_SD_AARM(0x300, ch)
 #define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2)
 #define DMOV_CONFIG_FORCE_FLUSH_RSLT   (1 << 1)
 #define DMOV_CONFIG_IRQ_EN             (1 << 0)
diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h
index fa97a10d8695..94324870fb04 100644
--- a/arch/arm/mach-msm/include/mach/uncompress.h
+++ b/arch/arm/mach-msm/include/mach/uncompress.h
@@ -37,7 +37,7 @@ static void putc(int c)
          * Wait for TX_READY to be set; but skip it if we have a
          * TX underrun.
          */
-        if (UART_DM_SR & 0x08)
+        if (!(UART_DM_SR & 0x08))
                 while (!(UART_DM_ISR & 0x80))
                         cpu_relax();
 
diff --git a/arch/arm/mach-msm/last_radio_log.c b/arch/arm/mach-msm/last_radio_log.c
index 1e243f46a969..7777767ee89a 100644
--- a/arch/arm/mach-msm/last_radio_log.c
+++ b/arch/arm/mach-msm/last_radio_log.c
@@ -31,20 +31,8 @@ extern void *smem_item(unsigned id, unsigned *size);
 static ssize_t last_radio_log_read(struct file *file, char __user *buf,
                         size_t len, loff_t *offset)
 {
-        loff_t pos = *offset;
-        ssize_t count;
-
-        if (pos >= radio_log_size)
-                return 0;
-
-        count = min(len, (size_t)(radio_log_size - pos));
-        if (copy_to_user(buf, radio_log_base + pos, count)) {
-                pr_err("%s: copy to user failed\n", __func__);
-                return -EFAULT;
-        }
-
-        *offset += count;
-        return count;
+        return simple_read_from_buffer(buf, len, offset,
+                                radio_log_base, radio_log_size);
 }
 
 static struct file_operations last_radio_log_fops = {
@@ -67,7 +55,8 @@ void msm_init_last_radio_log(struct module *owner)
                 return;
         }
 
-        entry = create_proc_entry("last_radio_log", S_IFREG | S_IRUGO, NULL);
+        entry = proc_create("last_radio_log", S_IRUGO, NULL,
+                                &last_radio_log_fops);
         if (!entry) {
                 pr_err("%s: could not create proc entry for radio log\n",
                                 __func__);
@@ -77,7 +66,6 @@ void msm_init_last_radio_log(struct module *owner)
         pr_err("%s: last radio log is %d bytes long\n", __func__,
                 radio_log_size);
         last_radio_log_fops.owner = owner;
-        entry->proc_fops = &last_radio_log_fops;
         entry->size = radio_log_size;
 }
 EXPORT_SYMBOL(msm_init_last_radio_log);
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 42932865416a..00cdb0a5dac8 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -15,7 +15,6 @@
 #include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
 
 #include <asm/cacheflush.h>
 #include <asm/cputype.h>
@@ -42,13 +41,6 @@ static inline int get_core_count(void)
 static void __cpuinit msm_secondary_init(unsigned int cpu)
 {
         /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-
-        /*
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index f9fd77e8f1f5..284313f3e02c 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -30,19 +30,22 @@
 
 #include "common.h"
 
-#define TIMER_MATCH_VAL         0x0000
-#define TIMER_COUNT_VAL         0x0004
-#define TIMER_ENABLE            0x0008
-#define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
-#define TIMER_ENABLE_EN                 BIT(0)
-#define TIMER_CLEAR             0x000C
-#define DGT_CLK_CTL_DIV_4       0x3
+#define TIMER_MATCH_VAL                 0x0000
+#define TIMER_COUNT_VAL                 0x0004
+#define TIMER_ENABLE                    0x0008
+#define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
+#define TIMER_ENABLE_EN                 BIT(0)
+#define TIMER_CLEAR                     0x000C
+#define DGT_CLK_CTL                     0x10
+#define DGT_CLK_CTL_DIV_4               0x3
+#define TIMER_STS_GPT0_CLR_PEND         BIT(10)
 
 #define GPT_HZ 32768
 
 #define MSM_DGT_SHIFT 5
 
 static void __iomem *event_base;
+static void __iomem *sts_base;
 
 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
 {
@@ -67,6 +70,11 @@ static int msm_timer_set_next_event(unsigned long cycles,
 
         writel_relaxed(ctrl, event_base + TIMER_CLEAR);
         writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
+
+        if (sts_base)
+                while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
+                        cpu_relax();
+
         writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
         return 0;
 }
@@ -137,9 +145,6 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
         if (!smp_processor_id())
                 return 0;
 
-        writel_relaxed(0, event_base + TIMER_ENABLE);
-        writel_relaxed(0, event_base + TIMER_CLEAR);
-        writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
         evt->irq = msm_clockevent.irq;
         evt->name = "local_timer";
         evt->features = msm_clockevent.features;
@@ -177,9 +182,6 @@ static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
         struct clocksource *cs = &msm_clocksource;
         int res;
 
-        writel_relaxed(0, event_base + TIMER_ENABLE);
-        writel_relaxed(0, event_base + TIMER_CLEAR);
-        writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
         ce->cpumask = cpumask_of(0);
         ce->irq = irq;
 
@@ -217,13 +219,9 @@ err:
 }
 
 #ifdef CONFIG_OF
-static const struct of_device_id msm_dgt_match[] __initconst = {
-        { .compatible = "qcom,msm-dgt" },
-        { },
-};
-
-static const struct of_device_id msm_gpt_match[] __initconst = {
-        { .compatible = "qcom,msm-gpt" },
+static const struct of_device_id msm_timer_match[] __initconst = {
+        { .compatible = "qcom,kpss-timer" },
+        { .compatible = "qcom,scss-timer" },
         { },
 };
 
@@ -234,33 +232,29 @@ void __init msm_dt_timer_init(void)
         int irq;
         struct resource res;
         u32 percpu_offset;
-        void __iomem *dgt_clk_ctl;
+        void __iomem *base;
+        void __iomem *cpu0_base;
 
-        np = of_find_matching_node(NULL, msm_gpt_match);
+        np = of_find_matching_node(NULL, msm_timer_match);
         if (!np) {
-                pr_err("Can't find GPT DT node\n");
+                pr_err("Can't find msm timer DT node\n");
                 return;
         }
 
-        event_base = of_iomap(np, 0);
-        if (!event_base) {
+        base = of_iomap(np, 0);
+        if (!base) {
                 pr_err("Failed to map event base\n");
                 return;
         }
 
-        irq = irq_of_parse_and_map(np, 0);
+        /* We use GPT0 for the clockevent */
+        irq = irq_of_parse_and_map(np, 1);
         if (irq <= 0) {
                 pr_err("Can't get irq\n");
                 return;
         }
-        of_node_put(np);
-
-        np = of_find_matching_node(NULL, msm_dgt_match);
-        if (!np) {
-                pr_err("Can't find DGT DT node\n");
-                return;
-        }
 
+        /* We use CPU0's DGT for the clocksource */
         if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
                 percpu_offset = 0;
 
@@ -269,45 +263,43 @@ void __init msm_dt_timer_init(void)
                 return;
         }
 
-        source_base = ioremap(res.start + percpu_offset, resource_size(&res));
-        if (!source_base) {
+        cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
+        if (!cpu0_base) {
                 pr_err("Failed to map source base\n");
                 return;
         }
 
-        if (!of_address_to_resource(np, 1, &res)) {
-                dgt_clk_ctl = ioremap(res.start + percpu_offset,
-                                      resource_size(&res));
-                if (!dgt_clk_ctl) {
-                        pr_err("Failed to map DGT control base\n");
-                        return;
-                }
-                writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl);
-                iounmap(dgt_clk_ctl);
-        }
-
         if (of_property_read_u32(np, "clock-frequency", &freq)) {
                 pr_err("Unknown frequency\n");
                 return;
         }
         of_node_put(np);
 
+        event_base = base + 0x4;
+        sts_base = base + 0x88;
+        source_base = cpu0_base + 0x24;
+        freq /= 4;
+        writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
+
         msm_timer_init(freq, 32, irq, !!percpu_offset);
 }
 #endif
 
-static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
+static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
+                                u32 sts)
 {
-        event_base = ioremap(event, SZ_64);
-        if (!event_base) {
-                pr_err("Failed to map event base\n");
-                return 1;
-        }
-        source_base = ioremap(source, SZ_64);
-        if (!source_base) {
-                pr_err("Failed to map source base\n");
-                return 1;
+        void __iomem *base;
+
+        base = ioremap(addr, SZ_256);
+        if (!base) {
+                pr_err("Failed to map timer base\n");
+                return -ENOMEM;
         }
+        event_base = base + event;
+        source_base = base + source;
+        if (sts)
+                sts_base = base + sts;
+
         return 0;
 }
 
@@ -315,7 +307,7 @@ void __init msm7x01_timer_init(void)
 {
         struct clocksource *cs = &msm_clocksource;
 
-        if (msm_timer_map(0xc0100000, 0xc0100010))
+        if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
                 return;
         cs->read = msm_read_timer_count_shift;
         cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
@@ -326,14 +318,14 @@ void __init msm7x01_timer_init(void)
 
 void __init msm7x30_timer_init(void)
 {
-        if (msm_timer_map(0xc0100004, 0xc0100024))
+        if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
                 return;
         msm_timer_init(24576000 / 4, 32, 1, false);
 }
 
 void __init qsd8x50_timer_init(void)
 {
-        if (msm_timer_map(0xAC100000, 0xAC100010))
+        if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
                 return;
         msm_timer_init(19200000 / 4, 32, 7, false);
 }
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
index d5970f5a1e8d..830139a3e2ba 100644
--- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -57,7 +57,7 @@ static struct irq_domain *armada_370_xp_mpic_domain;
 /*
  * In SMP mode:
  * For shared global interrupts, mask/unmask global enable bit
- * For CPU interrtups, mask/unmask the calling CPU's bit
+ * For CPU interrupts, mask/unmask the calling CPU's bit
  */
 static void armada_370_xp_irq_mask(struct irq_data *d)
 {
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index ecc431909d6f..4dc2fbba0ecd 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -1,8 +1,7 @@
-if ARCH_MXS
-
 config SOC_IMX23
         bool
         select ARM_AMBA
+        select ARM_CPU_SUSPEND if PM
         select CPU_ARM926T
         select HAVE_PWM
         select PINCTRL_IMX23
@@ -10,19 +9,24 @@ config SOC_IMX23
 config SOC_IMX28
         bool
         select ARM_AMBA
+        select ARM_CPU_SUSPEND if PM
         select CPU_ARM926T
         select HAVE_CAN_FLEXCAN if CAN
         select HAVE_PWM
         select PINCTRL_IMX28
 
-comment "MXS platforms:"
-
-config MACH_MXS_DT
-        bool "Support MXS platforms from device tree"
+config ARCH_MXS
+        bool "Freescale MXS (i.MX23, i.MX28) support"
+        depends on ARCH_MULTI_V5
+        select ARCH_REQUIRE_GPIOLIB
+        select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
+        select CLKSRC_OF
+        select GENERIC_CLOCKEVENTS
+        select HAVE_CLK_PREPARE
+        select PINCTRL
         select SOC_IMX23
         select SOC_IMX28
+        select STMP_DEVICE
         help
-          Include support for Freescale MXS platforms(i.MX23 and i.MX28)
-          using the device tree for discovery
-
-endif
+          Support for Freescale MXS-based family of processors
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 3d3c8a973062..cc2bf6748ade 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,6 +1,2 @@
-# Common support
-obj-y := icoll.o ocotp.o system.o timer.o mm.o
-
 obj-$(CONFIG_PM) += pm.o
-
-obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
+obj-$(CONFIG_ARCH_MXS) += mach-mxs.o
diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot
deleted file mode 100644
index 07b11fe6453f..000000000000
--- a/arch/arm/mach-mxs/Makefile.boot
+++ /dev/null
@@ -1 +0,0 @@
-zreladdr-y += 0x40008000
diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c
deleted file mode 100644
index e26eeba46598..000000000000
--- a/arch/arm/mach-mxs/icoll.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_irq.h>
-#include <asm/exception.h>
-#include <mach/mxs.h>
-#include <mach/common.h>
-
-#define HW_ICOLL_VECTOR                         0x0000
-#define HW_ICOLL_LEVELACK                       0x0010
-#define HW_ICOLL_CTRL                           0x0020
-#define HW_ICOLL_STAT_OFFSET                    0x0070
-#define HW_ICOLL_INTERRUPTn_SET(n)              (0x0124 + (n) * 0x10)
-#define HW_ICOLL_INTERRUPTn_CLR(n)              (0x0128 + (n) * 0x10)
-#define BM_ICOLL_INTERRUPTn_ENABLE              0x00000004
-#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0   0x1
-
-#define ICOLL_NUM_IRQS          128
-
-static void __iomem *icoll_base = MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR);
-static struct irq_domain *icoll_domain;
-
-static void icoll_ack_irq(struct irq_data *d)
-{
-        /*
-         * The Interrupt Collector is able to prioritize irqs.
-         * Currently only level 0 is used. So acking can use
-         * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally.
-         */
-        __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0,
-                        icoll_base + HW_ICOLL_LEVELACK);
-}
-
-static void icoll_mask_irq(struct irq_data *d)
-{
-        __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
-                        icoll_base + HW_ICOLL_INTERRUPTn_CLR(d->hwirq));
-}
-
-static void icoll_unmask_irq(struct irq_data *d)
-{
-        __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
-                        icoll_base + HW_ICOLL_INTERRUPTn_SET(d->hwirq));
-}
-
-static struct irq_chip mxs_icoll_chip = {
-        .irq_ack = icoll_ack_irq,
-        .irq_mask = icoll_mask_irq,
-        .irq_unmask = icoll_unmask_irq,
-};
-
-asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
-{
-        u32 irqnr;
-
-        do {
-                irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET);
-                if (irqnr != 0x7f) {
-                        __raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR);
-                        irqnr = irq_find_mapping(icoll_domain, irqnr);
-                        handle_IRQ(irqnr, regs);
-                        continue;
-                }
-                break;
-        } while (1);
-}
-
-static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
-                                irq_hw_number_t hw)
-{
-        irq_set_chip_and_handler(virq, &mxs_icoll_chip, handle_level_irq);
-        set_irq_flags(virq, IRQF_VALID);
-
-        return 0;
-}
-
-static struct irq_domain_ops icoll_irq_domain_ops = {
-        .map = icoll_irq_domain_map,
-        .xlate = irq_domain_xlate_onecell,
-};
-
-static void __init icoll_of_init(struct device_node *np,
-                          struct device_node *interrupt_parent)
-{
-        /*
-         * Interrupt Collector reset, which initializes the priority
-         * for each irq to level 0.
-         */
-        mxs_reset_block(icoll_base + HW_ICOLL_CTRL);
-
-        icoll_domain = irq_domain_add_linear(np, ICOLL_NUM_IRQS,
-                                             &icoll_irq_domain_ops, NULL);
-        WARN_ON(!icoll_domain);
-}
-
-static const struct of_device_id icoll_of_match[] __initconst = {
-        {.compatible = "fsl,icoll", .data = icoll_of_init},
-        { /* sentinel */ }
-};
-
-void __init icoll_init_irq(void)
-{
-        of_irq_init(icoll_of_match);
-}
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
deleted file mode 100644
index be5a9c93cb2a..000000000000
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_MXS_COMMON_H__
-#define __MACH_MXS_COMMON_H__
-
-extern const u32 *mxs_get_ocotp(void);
-extern int mxs_reset_block(void __iomem *);
-extern void mxs_timer_init(void);
-extern void mxs_restart(char, const char *);
-extern int mxs_saif_clkmux_select(unsigned int clkmux);
-
-extern int mx23_clocks_init(void);
-extern void mx23_map_io(void);
-
-extern int mx28_clocks_init(void);
-extern void mx28_map_io(void);
-
-extern void icoll_init_irq(void);
-extern void icoll_handle_irq(struct pt_regs *);
-
-#endif /* __MACH_MXS_COMMON_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/digctl.h b/arch/arm/mach-mxs/include/mach/digctl.h
deleted file mode 100644
index 17964066303f..000000000000
--- a/arch/arm/mach-mxs/include/mach/digctl.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_DIGCTL_H__
-#define __MACH_DIGCTL_H__
-
-/* MXS DIGCTL SAIF CLKMUX */
-#define MXS_DIGCTL_SAIF_CLKMUX_DIRECT           0x0
-#define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT       0x1
-#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0         0x2
-#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1         0x3
-
-#define HW_DIGCTL_CTRL                  0x0
-#define  BP_DIGCTL_CTRL_SAIF_CLKMUX     10
-#define  BM_DIGCTL_CTRL_SAIF_CLKMUX     (0x3 << 10)
-#define HW_DIGCTL_CHIPID                0x310
-#endif
diff --git a/arch/arm/mach-mxs/include/mach/hardware.h b/arch/arm/mach-mxs/include/mach/hardware.h
deleted file mode 100644
index 4c0e8a64d8c7..000000000000
--- a/arch/arm/mach-mxs/include/mach/hardware.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#ifndef __MACH_MXS_HARDWARE_H__
-#define __MACH_MXS_HARDWARE_H__
-
-#endif /* __MACH_MXS_HARDWARE_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h
deleted file mode 100644
index 599094bc99de..000000000000
--- a/arch/arm/mach-mxs/include/mach/mx23.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef __MACH_MX23_H__
-#define __MACH_MX23_H__
-
-#include <mach/mxs.h>
-
-/*
- * OCRAM
- */
-#define MX23_OCRAM_BASE_ADDR            0x00000000
-#define MX23_OCRAM_SIZE                 SZ_32K
-
-/*
- * IO
- */
-#define MX23_IO_BASE_ADDR               0x80000000
-#define MX23_IO_SIZE                    SZ_1M
-
-#define MX23_ICOLL_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x000000)
-#define MX23_APBH_DMA_BASE_ADDR         (MX23_IO_BASE_ADDR + 0x004000)
-#define MX23_BCH_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x00a000)
-#define MX23_GPMI_BASE_ADDR             (MX23_IO_BASE_ADDR + 0x00c000)
-#define MX23_SSP1_BASE_ADDR             (MX23_IO_BASE_ADDR + 0x010000)
-#define MX23_PINCTRL_BASE_ADDR          (MX23_IO_BASE_ADDR + 0x018000)
-#define MX23_DIGCTL_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x01c000)
-#define MX23_ETM_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x020000)
-#define MX23_APBX_DMA_BASE_ADDR         (MX23_IO_BASE_ADDR + 0x024000)
-#define MX23_DCP_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x028000)
-#define MX23_PXP_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x02a000)
-#define MX23_OCOTP_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x02c000)
-#define MX23_AXI_AHB0_BASE_ADDR         (MX23_IO_BASE_ADDR + 0x02e000)
-#define MX23_LCDIF_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x030000)
-#define MX23_SSP2_BASE_ADDR             (MX23_IO_BASE_ADDR + 0x034000)
-#define MX23_TVENC_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x038000)
-#define MX23_CLKCTRL_BASE_ADDR          (MX23_IO_BASE_ADDR + 0x040000)
-#define MX23_SAIF0_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x042000)
-#define MX23_POWER_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x044000)
-#define MX23_SAIF1_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x046000)
-#define MX23_AUDIOOUT_BASE_ADDR         (MX23_IO_BASE_ADDR + 0x048000)
-#define MX23_AUDIOIN_BASE_ADDR          (MX23_IO_BASE_ADDR + 0x04c000)
-#define MX23_LRADC_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x050000)
-#define MX23_SPDIF_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x054000)
-#define MX23_I2C_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x058000)
-#define MX23_RTC_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x05c000)
-#define MX23_PWM_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x064000)
-#define MX23_TIMROT_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x068000)
-#define MX23_AUART1_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x06c000)
-#define MX23_AUART2_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x06e000)
-#define MX23_DUART_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x070000)
-#define MX23_USBPHY_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x07c000)
-#define MX23_USBCTRL_BASE_ADDR          (MX23_IO_BASE_ADDR + 0x080000)
-#define MX23_DRAM_BASE_ADDR             (MX23_IO_BASE_ADDR + 0x0e0000)
-
-#define MX23_IO_P2V(x)                  MXS_IO_P2V(x)
-#define MX23_IO_ADDRESS(x)              IOMEM(MX23_IO_P2V(x))
-
-/*
- * IRQ
- */
-#define MX23_INT_DUART                  0
-#define MX23_INT_COMMS_RX               1
-#define MX23_INT_COMMS_TX               1
-#define MX23_INT_SSP2_ERROR             2
-#define MX23_INT_VDD5V                  3
-#define MX23_INT_HEADPHONE_SHORT        4
-#define MX23_INT_DAC_DMA                5
-#define MX23_INT_DAC_ERROR              6
-#define MX23_INT_ADC_DMA                7
-#define MX23_INT_ADC_ERROR              8
-#define MX23_INT_SPDIF_DMA              9
-#define MX23_INT_SAIF2_DMA              9
-#define MX23_INT_SPDIF_ERROR            10
-#define MX23_INT_SAIF1_IRQ              10
-#define MX23_INT_SAIF2_IRQ              10
-#define MX23_INT_USB_CTRL               11
-#define MX23_INT_USB_WAKEUP             12
-#define MX23_INT_GPMI_DMA               13
-#define MX23_INT_SSP1_DMA               14
-#define MX23_INT_SSP1_ERROR             15
-#define MX23_INT_GPIO0                  16
-#define MX23_INT_GPIO1                  17
-#define MX23_INT_GPIO2                  18
-#define MX23_INT_SAIF1_DMA              19
-#define MX23_INT_SSP2_DMA               20
-#define MX23_INT_ECC8_IRQ               21
-#define MX23_INT_RTC_ALARM              22
-#define MX23_INT_AUART1_TX_DMA          23
-#define MX23_INT_AUART1                 24
-#define MX23_INT_AUART1_RX_DMA          25
-#define MX23_INT_I2C_DMA                26
-#define MX23_INT_I2C_ERROR              27
-#define MX23_INT_TIMER0                 28
-#define MX23_INT_TIMER1                 29
-#define MX23_INT_TIMER2                 30
-#define MX23_INT_TIMER3                 31
-#define MX23_INT_BATT_BRNOUT            32
-#define MX23_INT_VDDD_BRNOUT            33
-#define MX23_INT_VDDIO_BRNOUT           34
-#define MX23_INT_VDD18_BRNOUT           35
-#define MX23_INT_TOUCH_DETECT           36
-#define MX23_INT_LRADC_CH0              37
-#define MX23_INT_LRADC_CH1              38
-#define MX23_INT_LRADC_CH2              39
-#define MX23_INT_LRADC_CH3              40
-#define MX23_INT_LRADC_CH4              41
-#define MX23_INT_LRADC_CH5              42
-#define MX23_INT_LRADC_CH6              43
-#define MX23_INT_LRADC_CH7              44
-#define MX23_INT_LCDIF_DMA              45
-#define MX23_INT_LCDIF_ERROR            46
-#define MX23_INT_DIGCTL_DEBUG_TRAP      47
-#define MX23_INT_RTC_1MSEC              48
-#define MX23_INT_DRI_DMA                49
-#define MX23_INT_DRI_ATTENTION          50
-#define MX23_INT_GPMI_ATTENTION         51
-#define MX23_INT_IR                     52
-#define MX23_INT_DCP_VMI                53
-#define MX23_INT_DCP                    54
-#define MX23_INT_BCH                    56
-#define MX23_INT_PXP                    57
-#define MX23_INT_AUART2_TX_DMA          58
-#define MX23_INT_AUART2                 59
-#define MX23_INT_AUART2_RX_DMA          60
-#define MX23_INT_VDAC_DETECT            61
-#define MX23_INT_VDD5V_DROOP            64
-#define MX23_INT_DCDC4P2_BO             65
-
-/*
- * APBH DMA
- */
-#define MX23_DMA_SSP1                   1
-#define MX23_DMA_SSP2                   2
-#define MX23_DMA_GPMI0                  4
-#define MX23_DMA_GPMI1                  5
-#define MX23_DMA_GPMI2                  6
-#define MX23_DMA_GPMI3                  7
-
-/*
- * APBX DMA
- */
-#define MX23_DMA_ADC                    0
-#define MX23_DMA_DAC                    1
-#define MX23_DMA_SPDIF                  2
-#define MX23_DMA_I2C                    3
-#define MX23_DMA_SAIF0                  4
-#define MX23_DMA_UART0_RX               6
-#define MX23_DMA_UART0_TX               7
-#define MX23_DMA_UART1_RX               8
-#define MX23_DMA_UART1_TX               9
-#define MX23_DMA_SAIF1                  10
-
-#endif /* __MACH_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mx28.h b/arch/arm/mach-mxs/include/mach/mx28.h
deleted file mode 100644
index 30c7990f3c01..000000000000
--- a/arch/arm/mach-mxs/include/mach/mx28.h
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef __MACH_MX28_H__
-#define __MACH_MX28_H__
-
-#include <mach/mxs.h>
-
-/*
- * OCRAM
- */
-#define MX28_OCRAM_BASE_ADDR            0x00000000
-#define MX28_OCRAM_SIZE                 SZ_128K
-
-/*
- * IO
- */
-#define MX28_IO_BASE_ADDR               0x80000000
-#define MX28_IO_SIZE                    SZ_1M
-
-#define MX28_ICOLL_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x000000)
-#define MX28_HSADC_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x002000)
-#define MX28_APBH_DMA_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x004000)
-#define MX28_PERFMON_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x006000)
-#define MX28_BCH_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x00a000)
-#define MX28_GPMI_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x00c000)
-#define MX28_SSP0_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x010000)
-#define MX28_SSP1_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x012000)
-#define MX28_SSP2_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x014000)
-#define MX28_SSP3_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x016000)
-#define MX28_PINCTRL_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x018000)
-#define MX28_DIGCTL_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x01c000)
-#define MX28_ETM_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x022000)
-#define MX28_APBX_DMA_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x024000)
-#define MX28_DCP_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x028000)
-#define MX28_PXP_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x02a000)
-#define MX28_OCOTP_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x02c000)
-#define MX28_AXI_AHB0_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x02e000)
-#define MX28_LCDIF_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x030000)
-#define MX28_CAN0_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x032000)
-#define MX28_CAN1_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x034000)
-#define MX28_SIMDBG_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x03c000)
-#define MX28_SIMGPMISEL_BASE_ADDR       (MX28_IO_BASE_ADDR + 0x03c200)
-#define MX28_SIMSSPSEL_BASE_ADDR        (MX28_IO_BASE_ADDR + 0x03c300)
-#define MX28_SIMMEMSEL_BASE_ADDR        (MX28_IO_BASE_ADDR + 0x03c400)
-#define MX28_GPIOMON_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x03c500)
-#define MX28_SIMENET_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x03c700)
-#define MX28_ARMJTAG_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x03c800)
-#define MX28_CLKCTRL_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x040000)
-#define MX28_SAIF0_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x042000)
-#define MX28_POWER_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x044000)
-#define MX28_SAIF1_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x046000)
-#define MX28_LRADC_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x050000)
-#define MX28_SPDIF_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x054000)
-#define MX28_RTC_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x056000)
-#define MX28_I2C0_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x058000)
-#define MX28_I2C1_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x05a000)
-#define MX28_PWM_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x064000)
-#define MX28_TIMROT_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x068000)
-#define MX28_AUART0_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x06a000)
-#define MX28_AUART1_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x06c000)
-#define MX28_AUART2_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x06e000)
-#define MX28_AUART3_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x070000)
-#define MX28_AUART4_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x072000)
-#define MX28_DUART_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x074000)
-#define MX28_USBPHY0_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x07C000)
-#define MX28_USBPHY1_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x07e000)
-#define MX28_USBCTRL0_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x080000)
-#define MX28_USBCTRL1_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x090000)
-#define MX28_DFLPT_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x0c0000)
-#define MX28_DRAM_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x0e0000)
-#define MX28_ENET_MAC0_BASE_ADDR        (MX28_IO_BASE_ADDR + 0x0f0000)
-#define MX28_ENET_MAC1_BASE_ADDR        (MX28_IO_BASE_ADDR + 0x0f4000)
-
-#define MX28_IO_P2V(x)                  MXS_IO_P2V(x)
-#define MX28_IO_ADDRESS(x)              IOMEM(MX28_IO_P2V(x))
-
-/*
- * IRQ
- */
-#define MX28_INT_BATT_BRNOUT            0
-#define MX28_INT_VDDD_BRNOUT            1
-#define MX28_INT_VDDIO_BRNOUT           2
-#define MX28_INT_VDDA_BRNOUT            3
-#define MX28_INT_VDD5V_DROOP            4
-#define MX28_INT_DCDC4P2_BRNOUT         5
-#define MX28_INT_VDD5V                  6
-#define MX28_INT_CAN0                   8
-#define MX28_INT_CAN1                   9
-#define MX28_INT_LRADC_TOUCH            10
-#define MX28_INT_HSADC                  13
-#define MX28_INT_LRADC_THRESH0          14
-#define MX28_INT_LRADC_THRESH1          15
-#define MX28_INT_LRADC_CH0              16
-#define MX28_INT_LRADC_CH1              17
-#define MX28_INT_LRADC_CH2              18
-#define MX28_INT_LRADC_CH3              19
-#define MX28_INT_LRADC_CH4              20
-#define MX28_INT_LRADC_CH5              21
-#define MX28_INT_LRADC_CH6              22
-#define MX28_INT_LRADC_CH7              23
-#define MX28_INT_LRADC_BUTTON0          24
-#define MX28_INT_LRADC_BUTTON1          25
-#define MX28_INT_PERFMON                27
-#define MX28_INT_RTC_1MSEC              28
-#define MX28_INT_RTC_ALARM              29
-#define MX28_INT_COMMS                  31
-#define MX28_INT_EMI_ERR                32
-#define MX28_INT_LCDIF                  38
-#define MX28_INT_PXP                    39
-#define MX28_INT_BCH                    41
-#define MX28_INT_GPMI                   42
-#define MX28_INT_SPDIF_ERROR            45
-#define MX28_INT_DUART                  47
-#define MX28_INT_TIMER0                 48
-#define MX28_INT_TIMER1                 49
-#define MX28_INT_TIMER2                 50
-#define MX28_INT_TIMER3                 51
-#define MX28_INT_DCP_VMI                52
-#define MX28_INT_DCP                    53
-#define MX28_INT_DCP_SECURE             54
-#define MX28_INT_SAIF1                  58
-#define MX28_INT_SAIF0                  59
-#define MX28_INT_SPDIF_DMA              66
-#define MX28_INT_I2C0_DMA               68
-#define MX28_INT_I2C1_DMA               69
-#define MX28_INT_AUART0_RX_DMA          70
-#define MX28_INT_AUART0_TX_DMA          71
-#define MX28_INT_AUART1_RX_DMA          72
-#define MX28_INT_AUART1_TX_DMA          73
-#define MX28_INT_AUART2_RX_DMA          74
-#define MX28_INT_AUART2_TX_DMA          75
-#define MX28_INT_AUART3_RX_DMA          76
-#define MX28_INT_AUART3_TX_DMA          77
-#define MX28_INT_AUART4_RX_DMA          78
-#define MX28_INT_AUART4_TX_DMA          79
-#define MX28_INT_SAIF0_DMA              80
-#define MX28_INT_SAIF1_DMA              81
-#define MX28_INT_SSP0_DMA               82
-#define MX28_INT_SSP1_DMA               83
-#define MX28_INT_SSP2_DMA               84
-#define MX28_INT_SSP3_DMA               85
-#define MX28_INT_LCDIF_DMA              86
-#define MX28_INT_HSADC_DMA              87
-#define MX28_INT_GPMI_DMA               88
-#define MX28_INT_DIGCTL_DEBUG_TRAP      89
-#define MX28_INT_USB1                   92
-#define MX28_INT_USB0                   93
-#define MX28_INT_USB1_WAKEUP            94
-#define MX28_INT_USB0_WAKEUP            95
-#define MX28_INT_SSP0_ERROR             96
-#define MX28_INT_SSP1_ERROR             97
-#define MX28_INT_SSP2_ERROR             98
-#define MX28_INT_SSP3_ERROR             99
-#define MX28_INT_ENET_SWI               100
-#define MX28_INT_ENET_MAC0              101
-#define MX28_INT_ENET_MAC1              102
-#define MX28_INT_ENET_MAC0_1588         103
-#define MX28_INT_ENET_MAC1_1588         104
-#define MX28_INT_I2C1_ERROR             110
-#define MX28_INT_I2C0_ERROR             111
-#define MX28_INT_AUART0                 112
-#define MX28_INT_AUART1                 113
-#define MX28_INT_AUART2                 114
-#define MX28_INT_AUART3                 115
-#define MX28_INT_AUART4                 116
-#define MX28_INT_GPIO4                  123
-#define MX28_INT_GPIO3                  124
-#define MX28_INT_GPIO2                  125
-#define MX28_INT_GPIO1                  126
-#define MX28_INT_GPIO0                  127
-
-/*
- * APBH DMA
- */
-#define MX28_DMA_SSP0                   0
-#define MX28_DMA_SSP1                   1
-#define MX28_DMA_SSP2                   2
-#define MX28_DMA_SSP3                   3
-#define MX28_DMA_GPMI0                  4
-#define MX28_DMA_GPMI1                  5
-#define MX28_DMA_GPMI2                  6
-#define MX28_DMA_GPMI3                  7
-#define MX28_DMA_GPMI4                  8
-#define MX28_DMA_GPMI5                  9
-#define MX28_DMA_GPMI6                  10
-#define MX28_DMA_GPMI7                  11
-#define MX28_DMA_HSADC                  12
-#define MX28_DMA_LCDIF                  13
-
-/*
- * APBX DMA
- */
-#define MX28_DMA_AUART4_RX              0
-#define MX28_DMA_AUART4_TX              1
-#define MX28_DMA_SPDIF_TX               2
-#define MX28_DMA_SAIF0                  4
-#define MX28_DMA_SAIF1                  5
-#define MX28_DMA_I2C0                   6
-#define MX28_DMA_I2C1                   7
-#define MX28_DMA_AUART0_RX              8
-#define MX28_DMA_AUART0_TX              9
-#define MX28_DMA_AUART1_RX              10
-#define MX28_DMA_AUART1_TX              11
-#define MX28_DMA_AUART2_RX              12
-#define MX28_DMA_AUART2_TX              13
-#define MX28_DMA_AUART3_RX              14
-#define MX28_DMA_AUART3_TX              15
-
-#endif /* __MACH_MX28_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h
deleted file mode 100644
index 7d4fb6d0afda..000000000000
--- a/arch/arm/mach-mxs/include/mach/mxs.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef __MACH_MXS_H__
-#define __MACH_MXS_H__
-
-#ifndef __ASSEMBLER__
-#include <linux/io.h>
-#endif
-#include <asm/mach-types.h>
-#include <mach/digctl.h>
-#include <mach/hardware.h>
-
-/*
- * IO addresses common to MXS-based
- */
-#define MXS_IO_BASE_ADDR                0x80000000
-#define MXS_IO_SIZE                     SZ_1M
-
-#define MXS_ICOLL_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x000000)
-#define MXS_APBH_DMA_BASE_ADDR          (MXS_IO_BASE_ADDR + 0x004000)
-#define MXS_BCH_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x00a000)
-#define MXS_GPMI_BASE_ADDR              (MXS_IO_BASE_ADDR + 0x00c000)
-#define MXS_PINCTRL_BASE_ADDR           (MXS_IO_BASE_ADDR + 0x018000)
-#define MXS_DIGCTL_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x01c000)
-#define MXS_APBX_DMA_BASE_ADDR          (MXS_IO_BASE_ADDR + 0x024000)
-#define MXS_DCP_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x028000)
-#define MXS_PXP_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x02a000)
-#define MXS_OCOTP_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x02c000)
-#define MXS_AXI_AHB0_BASE_ADDR          (MXS_IO_BASE_ADDR + 0x02e000)
-#define MXS_LCDIF_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x030000)
-#define MXS_CLKCTRL_BASE_ADDR           (MXS_IO_BASE_ADDR + 0x040000)
-#define MXS_SAIF0_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x042000)
-#define MXS_POWER_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x044000)
-#define MXS_SAIF1_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x046000)
-#define MXS_LRADC_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x050000)
-#define MXS_SPDIF_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x054000)
-#define MXS_I2C0_BASE_ADDR              (MXS_IO_BASE_ADDR + 0x058000)
-#define MXS_PWM_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x064000)
-#define MXS_TIMROT_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x068000)
-#define MXS_AUART1_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x06c000)
-#define MXS_AUART2_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x06e000)
-#define MXS_DRAM_BASE_ADDR              (MXS_IO_BASE_ADDR + 0x0e0000)
-
-/*
- * It maps the whole address space to [0xf4000000, 0xf50fffff].
- *
- *      OCRAM   0x00000000+0x020000     ->      0xf4000000+0x020000
- *      IO      0x80000000+0x100000     ->      0xf5000000+0x100000
- */
-#define MXS_IO_P2V(x)   (0xf4000000 +                                   \
-                        (((x) & 0x80000000) >> 7) +                     \
-                        (((x) & 0x000fffff)))
-
-#define MXS_IO_ADDRESS(x)       IOMEM(MXS_IO_P2V(x))
-
-#define mxs_map_entry(soc, name, _type) {                               \
-        .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR),      \
-        .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR),           \
-        .length = soc ## _ ## name ## _SIZE,                            \
-        .type = _type,                                                  \
-}
-
-#define MXS_GPIO_NR(bank, nr)   ((bank) * 32 + (nr))
-
-#define MXS_SET_ADDR            0x4
-#define MXS_CLR_ADDR            0x8
-#define MXS_TOG_ADDR            0xc
-
-#ifndef __ASSEMBLER__
-static inline void __mxs_setl(u32 mask, void __iomem *reg)
-{
-        __raw_writel(mask, reg + MXS_SET_ADDR);
-}
-
-static inline void __mxs_clrl(u32 mask, void __iomem *reg)
-{
-        __raw_writel(mask, reg + MXS_CLR_ADDR);
-}
-
-static inline void __mxs_togl(u32 mask, void __iomem *reg)
-{
-        __raw_writel(mask, reg + MXS_TOG_ADDR);
-}
-
-/*
- * MXS CPU types
- */
-#define MXS_CHIPID (MXS_IO_ADDRESS(MXS_DIGCTL_BASE_ADDR) + HW_DIGCTL_CHIPID)
-
-static inline int cpu_is_mx23(void)
-{
-        return ((__raw_readl(MXS_CHIPID) >> 16) == 0x3780);
-}
-
-static inline int cpu_is_mx28(void)
-{
-        return ((__raw_readl(MXS_CHIPID) >> 16) == 0x2800);
-}
-#endif
-
-#endif /* __MACH_MXS_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/timex.h b/arch/arm/mach-mxs/include/mach/timex.h
deleted file mode 100644
index 734ce8984a64..000000000000
--- a/arch/arm/mach-mxs/include/mach/timex.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  Copyright (C) 1999 ARM Limited
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_MXS_TIMEX_H__
-#define __MACH_MXS_TIMEX_H__
-
-#define CLOCK_TICK_RATE         32000   /* 32K */
-
-#endif /* __MACH_MXS_TIMEX_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
deleted file mode 100644
index 533f5186e200..000000000000
--- a/arch/arm/mach-mxs/include/mach/uncompress.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- *  arch/arm/mach-mxs/include/mach/uncompress.h
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) Shane Nay (shane@minirl.com)
- *  Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_MXS_UNCOMPRESS_H__
-#define __MACH_MXS_UNCOMPRESS_H__
-
-unsigned long mxs_duart_base;
-
-#define MXS_DUART(x)    (*(volatile unsigned long *)(mxs_duart_base + (x)))
-
-#define MXS_DUART_DR            0x00
-#define MXS_DUART_FR            0x18
-#define MXS_DUART_FR_TXFE       (1 << 7)
-#define MXS_DUART_CR            0x30
-#define MXS_DUART_CR_UARTEN     (1 << 0)
-
-/*
- * The following code assumes the serial port has already been
- * initialized by the bootloader. If it's not, the output is
- * simply discarded.
- */
-
-static void putc(int ch)
-{
-        if (!mxs_duart_base)
-                return;
-        if (!(MXS_DUART(MXS_DUART_CR) & MXS_DUART_CR_UARTEN))
-                return;
-
-        while (!(MXS_DUART(MXS_DUART_FR) & MXS_DUART_FR_TXFE))
-                barrier();
-
-        MXS_DUART(MXS_DUART_DR) = ch;
-}
-
-static inline void flush(void)
-{
-}
-
-#define MX23_DUART_BASE_ADDR    0x80070000
-#define MX28_DUART_BASE_ADDR    0x80074000
-#define MXS_DIGCTL_CHIPID       0x8001c310
-
-static inline void __arch_decomp_setup(unsigned long arch_id)
-{
-        u16 chipid = (*(volatile unsigned long *) MXS_DIGCTL_CHIPID) >> 16;
-
-        switch (chipid) {
-        case 0x3780:
-                mxs_duart_base = MX23_DUART_BASE_ADDR;
-                break;
-        case 0x2800:
-                mxs_duart_base = MX28_DUART_BASE_ADDR;
-                break;
-        default:
-                break;
-        }
-}
-
-#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
-
-#endif /* __MACH_MXS_UNCOMPRESS_H__ */
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index e7b781d3788f..b5c1bdd3dcdf 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -11,22 +11,55 @@
  */
 
 #include <linux/clk.h>
+#include <linux/clk/mxs.h>
 #include <linux/clkdev.h>
+#include <linux/clocksource.h>
 #include <linux/can/platform/flexcan.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/mxs.h>
 #include <linux/micrel_phy.h>
 #include <linux/mxsfb.h>
+#include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/phy.h>
 #include <linux/pinctrl/consumer.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <mach/common.h>
-#include <mach/digctl.h>
-#include <mach/mxs.h>
+#include <asm/system_misc.h>
+
+#include "pm.h"
+
+/* MXS DIGCTL SAIF CLKMUX */
+#define MXS_DIGCTL_SAIF_CLKMUX_DIRECT           0x0
+#define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT       0x1
+#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0         0x2
+#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1         0x3
+
+#define MXS_GPIO_NR(bank, nr)   ((bank) * 32 + (nr))
+
+#define MXS_SET_ADDR            0x4
+#define MXS_CLR_ADDR            0x8
+#define MXS_TOG_ADDR            0xc
+
+static inline void __mxs_setl(u32 mask, void __iomem *reg)
+{
+        __raw_writel(mask, reg + MXS_SET_ADDR);
+}
+
+static inline void __mxs_clrl(u32 mask, void __iomem *reg)
+{
+        __raw_writel(mask, reg + MXS_CLR_ADDR);
+}
+
+static inline void __mxs_togl(u32 mask, void __iomem *reg)
+{
+        __raw_writel(mask, reg + MXS_TOG_ADDR);
+}
 
 static struct fb_videomode mx23evk_video_modes[] = {
         {
@@ -165,14 +198,80 @@ static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = {
         { /* sentinel */ }
 };
 
-static void __init imx23_timer_init(void)
-{
-        mx23_clocks_init();
-}
+#define OCOTP_WORD_OFFSET               0x20
+#define OCOTP_WORD_COUNT                0x20
+
+#define BM_OCOTP_CTRL_BUSY              (1 << 8)
+#define BM_OCOTP_CTRL_ERROR             (1 << 9)
+#define BM_OCOTP_CTRL_RD_BANK_OPEN      (1 << 12)
 
-static void __init imx28_timer_init(void)
+static DEFINE_MUTEX(ocotp_mutex);
+static u32 ocotp_words[OCOTP_WORD_COUNT];
+
+static const u32 *mxs_get_ocotp(void)
 {
-        mx28_clocks_init();
+        struct device_node *np;
+        void __iomem *ocotp_base;
+        int timeout = 0x400;
+        size_t i;
+        static int once;
+
+        if (once)
+                return ocotp_words;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,ocotp");
+        ocotp_base = of_iomap(np, 0);
+        WARN_ON(!ocotp_base);
+
+        mutex_lock(&ocotp_mutex);
+
+        /*
+         * clk_enable(hbus_clk) for ocotp can be skipped
+         * as it must be on when system is running.
+         */
+
+        /* try to clear ERROR bit */
+        __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
+
+        /* check both BUSY and ERROR cleared */
+        while ((__raw_readl(ocotp_base) &
+                (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
+                cpu_relax();
+
+        if (unlikely(!timeout))
+                goto error_unlock;
+
+        /* open OCOTP banks for read */
+        __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
+
+        /* approximately wait 32 hclk cycles */
+        udelay(1);
+
+        /* poll BUSY bit becoming cleared */
+        timeout = 0x400;
+        while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout)
+                cpu_relax();
+
+        if (unlikely(!timeout))
+                goto error_unlock;
+
+        for (i = 0; i < OCOTP_WORD_COUNT; i++)
+                ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET +
+                                                i * 0x10);
+
+        /* close banks for power saving */
+        __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
+
+        once = 1;
+
+        mutex_unlock(&ocotp_mutex);
+
+        return ocotp_words;
+
+error_unlock:
+        mutex_unlock(&ocotp_mutex);
+        pr_err("%s: timeout in reading OCOTP\n", __func__);
+        return NULL;
 }
 
 enum mac_oui {
@@ -454,32 +553,63 @@ static void __init mxs_machine_init(void)
                 imx28_evk_post_init();
 }
 
-static const char *imx23_dt_compat[] __initdata = {
-        "fsl,imx23",
-        NULL,
-};
+#define MX23_CLKCTRL_RESET_OFFSET       0x120
+#define MX28_CLKCTRL_RESET_OFFSET       0x1e0
+#define MXS_CLKCTRL_RESET_CHIP          (1 << 1)
+
+/*
+ * Reset the system. It is called by machine_restart().
+ */
+static void mxs_restart(char mode, const char *cmd)
+{
+        struct device_node *np;
+        void __iomem *reset_addr;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl");
+        reset_addr = of_iomap(np, 0);
+        if (!reset_addr)
+                goto soft;
+
+        if (of_device_is_compatible(np, "fsl,imx23-clkctrl"))
+                reset_addr += MX23_CLKCTRL_RESET_OFFSET;
+        else
+                reset_addr += MX28_CLKCTRL_RESET_OFFSET;
 
-static const char *imx28_dt_compat[] __initdata = {
+        /* reset the chip */
+        __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr);
+
+        pr_err("Failed to assert the chip reset\n");
+
+        /* Delay to allow the serial port to show the message */
+        mdelay(50);
+
+soft:
+        /* We'll take a jump through zero as a poor second */
+        soft_restart(0);
+}
+
+static void __init mxs_timer_init(void)
+{
+        if (of_machine_is_compatible("fsl,imx23"))
+                mx23_clocks_init();
+        else
+                mx28_clocks_init();
+        clocksource_of_init();
+}
+
+static const char *mxs_dt_compat[] __initdata = {
         "fsl,imx28",
+        "fsl,imx23",
         NULL,
 };
 
-DT_MACHINE_START(IMX23, "Freescale i.MX23 (Device Tree)")
-        .map_io         = mx23_map_io,
-        .init_irq       = icoll_init_irq,
-        .handle_irq     = icoll_handle_irq,
-        .init_time      = imx23_timer_init,
-        .init_machine   = mxs_machine_init,
-        .dt_compat      = imx23_dt_compat,
-        .restart        = mxs_restart,
-MACHINE_END
-
-DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
-        .map_io         = mx28_map_io,
-        .init_irq       = icoll_init_irq,
+DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)")
+        .map_io         = debug_ll_io_init,
+        .init_irq       = irqchip_init,
         .handle_irq     = icoll_handle_irq,
-        .init_time      = imx28_timer_init,
+        .init_time      = mxs_timer_init,
         .init_machine   = mxs_machine_init,
-        .dt_compat      = imx28_dt_compat,
+        .init_late      = mxs_pm_init,
+        .dt_compat      = mxs_dt_compat,
         .restart        = mxs_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mxs/mm.c b/arch/arm/mach-mxs/mm.c
deleted file mode 100644
index e63b7d87acbd..000000000000
--- a/arch/arm/mach-mxs/mm.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License.  You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- *
- * Create static mapping between physical to virtual memory.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/common.h>
-
-/*
- * Define the MX23 memory map.
- */
-static struct map_desc mx23_io_desc[] __initdata = {
-        mxs_map_entry(MX23, OCRAM, MT_DEVICE),
-        mxs_map_entry(MX23, IO, MT_DEVICE),
-};
-
-/*
- * Define the MX28 memory map.
- */
-static struct map_desc mx28_io_desc[] __initdata = {
-        mxs_map_entry(MX28, OCRAM, MT_DEVICE),
-        mxs_map_entry(MX28, IO, MT_DEVICE),
-};
-
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory mappings
- * for the IO modules.
- */
-void __init mx23_map_io(void)
-{
-        iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc));
-}
-
-void __init mx28_map_io(void)
-{
-        iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc));
-}
diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c
deleted file mode 100644
index 1dff46703753..000000000000
--- a/arch/arm/mach-mxs/ocotp.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/mutex.h>
-
-#include <asm/processor.h>      /* for cpu_relax() */
-
-#include <mach/mxs.h>
-#include <mach/common.h>
-
-#define OCOTP_WORD_OFFSET               0x20
-#define OCOTP_WORD_COUNT                0x20
-
-#define BM_OCOTP_CTRL_BUSY              (1 << 8)
-#define BM_OCOTP_CTRL_ERROR             (1 << 9)
-#define BM_OCOTP_CTRL_RD_BANK_OPEN      (1 << 12)
-
-static DEFINE_MUTEX(ocotp_mutex);
-static u32 ocotp_words[OCOTP_WORD_COUNT];
-
-const u32 *mxs_get_ocotp(void)
-{
-        void __iomem *ocotp_base = MXS_IO_ADDRESS(MXS_OCOTP_BASE_ADDR);
-        int timeout = 0x400;
-        size_t i;
-        static int once = 0;
-
-        if (once)
-                return ocotp_words;
-
-        mutex_lock(&ocotp_mutex);
-
-        /*
-         * clk_enable(hbus_clk) for ocotp can be skipped
-         * as it must be on when system is running.
-         */
-
-        /* try to clear ERROR bit */
-        __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
-
-        /* check both BUSY and ERROR cleared */
-        while ((__raw_readl(ocotp_base) &
-                (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
-                cpu_relax();
-
-        if (unlikely(!timeout))
-                goto error_unlock;
-
-        /* open OCOTP banks for read */
-        __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
-
-        /* approximately wait 32 hclk cycles */
-        udelay(1);
-
-        /* poll BUSY bit becoming cleared */
-        timeout = 0x400;
-        while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout)
-                cpu_relax();
-
-        if (unlikely(!timeout))
-                goto error_unlock;
-
-        for (i = 0; i < OCOTP_WORD_COUNT; i++)
-                ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET +
-                                                i * 0x10);
-
-        /* close banks for power saving */
-        __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
-
-        once = 1;
-
-        mutex_unlock(&ocotp_mutex);
-
-        return ocotp_words;
-
-error_unlock:
-        mutex_unlock(&ocotp_mutex);
-        pr_err("%s: timeout in reading OCOTP\n", __func__);
-        return NULL;
-}
diff --git a/arch/arm/mach-mxs/pm.c b/arch/arm/mach-mxs/pm.c
index a9b4bbcdafb4..b2494d2db2c4 100644
--- a/arch/arm/mach-mxs/pm.c
+++ b/arch/arm/mach-mxs/pm.c
@@ -34,9 +34,7 @@ static struct platform_suspend_ops mxs_suspend_ops = {
         .valid = suspend_valid_only_mem,
 };
 
-static int __init mxs_pm_init(void)
+void __init mxs_pm_init(void)
 {
         suspend_set_ops(&mxs_suspend_ops);
-        return 0;
 }
-device_initcall(mxs_pm_init);
diff --git a/arch/arm/mach-h720x/include/mach/timex.h b/arch/arm/mach-mxs/pm.h
index 3f2f447ff36b..f57e7cdece2e 100644
--- a/arch/arm/mach-h720x/include/mach/timex.h
+++ b/arch/arm/mach-mxs/pm.h
@@ -1,15 +1,14 @@
 /*
- * arch/arm/mach-h720x/include/mach/timex.h
- * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 
-#ifndef __ASM_ARCH_TIMEX
-#define __ASM_ARCH_TIMEX
+#ifndef __ARCH_MXS_PM_H
+#define __ARCH_MXS_PM_H
 
-#define CLOCK_TICK_RATE         3686400
+void mxs_pm_init(void);
 
 #endif
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
deleted file mode 100644
index 30042e23bfa7..000000000000
--- a/arch/arm/mach-mxs/system.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Copyright (C) 1999 ARM Limited
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/module.h>
-
-#include <asm/proc-fns.h>
-#include <asm/system_misc.h>
-
-#include <mach/mxs.h>
-#include <mach/common.h>
-
-#define MX23_CLKCTRL_RESET_OFFSET       0x120
-#define MX28_CLKCTRL_RESET_OFFSET       0x1e0
-#define MXS_CLKCTRL_RESET_CHIP          (1 << 1)
-
-#define MXS_MODULE_CLKGATE              (1 << 30)
-#define MXS_MODULE_SFTRST               (1 << 31)
-
-static void __iomem *mxs_clkctrl_reset_addr;
-
-/*
- * Reset the system. It is called by machine_restart().
- */
-void mxs_restart(char mode, const char *cmd)
-{
-        /* reset the chip */
-        __mxs_setl(MXS_CLKCTRL_RESET_CHIP, mxs_clkctrl_reset_addr);
-
-        pr_err("Failed to assert the chip reset\n");
-
-        /* Delay to allow the serial port to show the message */
-        mdelay(50);
-
-        /* We'll take a jump through zero as a poor second */
-        soft_restart(0);
-}
-
-static int __init mxs_arch_reset_init(void)
-{
-        struct clk *clk;
-
-        mxs_clkctrl_reset_addr = MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR) +
-                                (cpu_is_mx23() ? MX23_CLKCTRL_RESET_OFFSET :
-                                                 MX28_CLKCTRL_RESET_OFFSET);
-
-        clk = clk_get_sys("rtc", NULL);
-        if (!IS_ERR(clk))
-                clk_prepare_enable(clk);
-
-        return 0;
-}
-core_initcall(mxs_arch_reset_init);
-
-/*
- * Clear the bit and poll it cleared.  This is usually called with
- * a reset address and mask being either SFTRST(bit 31) or CLKGATE
- * (bit 30).
- */
-static int clear_poll_bit(void __iomem *addr, u32 mask)
-{
-        int timeout = 0x400;
-
-        /* clear the bit */
-        __mxs_clrl(mask, addr);
-
-        /*
-         * SFTRST needs 3 GPMI clocks to settle, the reference manual
-         * recommends to wait 1us.
-         */
-        udelay(1);
-
-        /* poll the bit becoming clear */
-        while ((__raw_readl(addr) & mask) && --timeout)
-                /* nothing */;
-
-        return !timeout;
-}
-
-int mxs_reset_block(void __iomem *reset_addr)
-{
-        int ret;
-        int timeout = 0x400;
-
-        /* clear and poll SFTRST */
-        ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST);
-        if (unlikely(ret))
-                goto error;
-
-        /* clear CLKGATE */
-        __mxs_clrl(MXS_MODULE_CLKGATE, reset_addr);
-
-        /* set SFTRST to reset the block */
-        __mxs_setl(MXS_MODULE_SFTRST, reset_addr);
-        udelay(1);
-
-        /* poll CLKGATE becoming set */
-        while ((!(__raw_readl(reset_addr) & MXS_MODULE_CLKGATE)) && --timeout)
-                /* nothing */;
-        if (unlikely(!timeout))
-                goto error;
-
-        /* clear and poll SFTRST */
-        ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST);
-        if (unlikely(ret))
-                goto error;
-
-        /* clear and poll CLKGATE */
-        ret = clear_poll_bit(reset_addr, MXS_MODULE_CLKGATE);
-        if (unlikely(ret))
-                goto error;
-
-        return 0;
-
-error:
-        pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
-        return -ETIMEDOUT;
-}
-EXPORT_SYMBOL(mxs_reset_block);
diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c
deleted file mode 100644
index 421020498a1b..000000000000
--- a/arch/arm/mach-mxs/timer.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- *  Copyright (C) 2000-2001 Deep Blue Solutions
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
- *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *  Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/err.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clockchips.h>
-#include <linux/clk.h>
-#include <linux/of.h>
-#include <linux/of_irq.h>
-
-#include <asm/mach/time.h>
-#include <asm/sched_clock.h>
-#include <mach/mxs.h>
-#include <mach/common.h>
-
-/*
- * There are 2 versions of the timrot on Freescale MXS-based SoCs.
- * The v1 on MX23 only gets 16 bits counter, while v2 on MX28
- * extends the counter to 32 bits.
- *
- * The implementation uses two timers, one for clock_event and
- * another for clocksource. MX28 uses timrot 0 and 1, while MX23
- * uses 0 and 2.
- */
-
-#define MX23_TIMROT_VERSION_OFFSET      0x0a0
-#define MX28_TIMROT_VERSION_OFFSET      0x120
-#define BP_TIMROT_MAJOR_VERSION         24
-#define BV_TIMROT_VERSION_1             0x01
-#define BV_TIMROT_VERSION_2             0x02
-#define timrot_is_v1()  (timrot_major_version == BV_TIMROT_VERSION_1)
-
-/*
- * There are 4 registers for each timrotv2 instance, and 2 registers
- * for each timrotv1. So address step 0x40 in macros below strides
- * one instance of timrotv2 while two instances of timrotv1.
- *
- * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
- * on MX28 while timrot2 on MX23.
- */
-/* common between v1 and v2 */
-#define HW_TIMROT_ROTCTRL               0x00
-#define HW_TIMROT_TIMCTRLn(n)           (0x20 + (n) * 0x40)
-/* v1 only */
-#define HW_TIMROT_TIMCOUNTn(n)          (0x30 + (n) * 0x40)
-/* v2 only */
-#define HW_TIMROT_RUNNING_COUNTn(n)     (0x30 + (n) * 0x40)
-#define HW_TIMROT_FIXED_COUNTn(n)       (0x40 + (n) * 0x40)
-
-#define BM_TIMROT_TIMCTRLn_RELOAD       (1 << 6)
-#define BM_TIMROT_TIMCTRLn_UPDATE       (1 << 7)
-#define BM_TIMROT_TIMCTRLn_IRQ_EN       (1 << 14)
-#define BM_TIMROT_TIMCTRLn_IRQ          (1 << 15)
-#define BP_TIMROT_TIMCTRLn_SELECT       0
-#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL         0x8
-#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL         0xb
-#define BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS        0xf
-
-static struct clock_event_device mxs_clockevent_device;
-static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;
-
-static void __iomem *mxs_timrot_base = MXS_IO_ADDRESS(MXS_TIMROT_BASE_ADDR);
-static u32 timrot_major_version;
-
-static inline void timrot_irq_disable(void)
-{
-        __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN,
-                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
-}
-
-static inline void timrot_irq_enable(void)
-{
-        __mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN,
-                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
-}
-
-static void timrot_irq_acknowledge(void)
-{
-        __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ,
-                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
-}
-
-static cycle_t timrotv1_get_cycles(struct clocksource *cs)
-{
-        return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
-                        & 0xffff0000) >> 16);
-}
-
-static int timrotv1_set_next_event(unsigned long evt,
-                                        struct clock_event_device *dev)
-{
-        /* timrot decrements the count */
-        __raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));
-
-        return 0;
-}
-
-static int timrotv2_set_next_event(unsigned long evt,
-                                        struct clock_event_device *dev)
-{
-        /* timrot decrements the count */
-        __raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));
-
-        return 0;
-}
-
-static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
-{
-        struct clock_event_device *evt = dev_id;
-
-        timrot_irq_acknowledge();
-        evt->event_handler(evt);
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction mxs_timer_irq = {
-        .name           = "MXS Timer Tick",
-        .dev_id         = &mxs_clockevent_device,
-        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = mxs_timer_interrupt,
-};
-
-#ifdef DEBUG
-static const char *clock_event_mode_label[] const = {
-        [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
-        [CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
-        [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
-        [CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED"
-};
-#endif /* DEBUG */
-
-static void mxs_set_mode(enum clock_event_mode mode,
-                                struct clock_event_device *evt)
-{
-        /* Disable interrupt in timer module */
-        timrot_irq_disable();
-
-        if (mode != mxs_clockevent_mode) {
-                /* Set event time into the furthest future */
-                if (timrot_is_v1())
-                        __raw_writel(0xffff,
-                                mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
-                else
-                        __raw_writel(0xffffffff,
-                                mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
-
-                /* Clear pending interrupt */
-                timrot_irq_acknowledge();
-        }
-
-#ifdef DEBUG
-        pr_info("%s: changing mode from %s to %s\n", __func__,
-                clock_event_mode_label[mxs_clockevent_mode],
-                clock_event_mode_label[mode]);
-#endif /* DEBUG */
-
-        /* Remember timer mode */
-        mxs_clockevent_mode = mode;
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                pr_err("%s: Periodic mode is not implemented\n", __func__);
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-                timrot_irq_enable();
-                break;
-        case CLOCK_EVT_MODE_SHUTDOWN:
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_RESUME:
-                /* Left event sources disabled, no more interrupts appear */
-                break;
-        }
-}
-
-static struct clock_event_device mxs_clockevent_device = {
-        .name           = "mxs_timrot",
-        .features       = CLOCK_EVT_FEAT_ONESHOT,
-        .set_mode       = mxs_set_mode,
-        .set_next_event = timrotv2_set_next_event,
-        .rating         = 200,
-};
-
-static int __init mxs_clockevent_init(struct clk *timer_clk)
-{
-        if (timrot_is_v1())
-                mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
-        mxs_clockevent_device.cpumask = cpumask_of(0);
-        clockevents_config_and_register(&mxs_clockevent_device,
-                                        clk_get_rate(timer_clk),
-                                        timrot_is_v1() ? 0xf : 0x2,
-                                        timrot_is_v1() ? 0xfffe : 0xfffffffe);
-
-        return 0;
-}
-
-static struct clocksource clocksource_mxs = {
-        .name           = "mxs_timer",
-        .rating         = 200,
-        .read           = timrotv1_get_cycles,
-        .mask           = CLOCKSOURCE_MASK(16),
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static u32 notrace mxs_read_sched_clock_v2(void)
-{
-        return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
-}
-
-static int __init mxs_clocksource_init(struct clk *timer_clk)
-{
-        unsigned int c = clk_get_rate(timer_clk);
-
-        if (timrot_is_v1())
-                clocksource_register_hz(&clocksource_mxs, c);
-        else {
-                clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
-                        "mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
-                setup_sched_clock(mxs_read_sched_clock_v2, 32, c);
-        }
-
-        return 0;
-}
-
-void __init mxs_timer_init(void)
-{
-        struct device_node *np;
-        struct clk *timer_clk;
-        int irq;
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,timrot");
-        if (!np) {
-                pr_err("%s: failed find timrot node\n", __func__);
-                return;
-        }
-
-        timer_clk = clk_get_sys("timrot", NULL);
-        if (IS_ERR(timer_clk)) {
-                pr_err("%s: failed to get clk\n", __func__);
-                return;
-        }
-
-        clk_prepare_enable(timer_clk);
-
-        /*
-         * Initialize timers to a known state
-         */
-        mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
-
-        /* get timrot version */
-        timrot_major_version = __raw_readl(mxs_timrot_base +
-                                (cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET :
-                                                MX28_TIMROT_VERSION_OFFSET));
-        timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
-
-        /* one for clock_event */
-        __raw_writel((timrot_is_v1() ?
-                        BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
-                        BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
-                        BM_TIMROT_TIMCTRLn_UPDATE |
-                        BM_TIMROT_TIMCTRLn_IRQ_EN,
-                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
-
-        /* another for clocksource */
-        __raw_writel((timrot_is_v1() ?
-                        BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
-                        BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
-                        BM_TIMROT_TIMCTRLn_RELOAD,
-                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
-
-        /* set clocksource timer fixed count to the maximum */
-        if (timrot_is_v1())
-                __raw_writel(0xffff,
-                        mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
-        else
-                __raw_writel(0xffffffff,
-                        mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
-
-        /* init and register the timer to the framework */
-        mxs_clocksource_init(timer_clk);
-        mxs_clockevent_init(timer_clk);
-
-        /* Make irqs happen */
-        irq = irq_of_parse_and_map(np, 0);
-        setup_irq(irq, &mxs_timer_irq);
-}
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 82226a5d60ef..9b9d105f194c 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -1,5 +1,24 @@
-if ARCH_NOMADIK
+config ARCH_NOMADIK
+        bool "ST-Ericsson Nomadik"
+        depends on ARCH_MULTI_V5
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_AMBA
+        select ARM_VIC
+        select CLKSRC_NOMADIK_MTU
+        select CLKSRC_NOMADIK_MTU_SCHED_CLOCK
+        select COMMON_CLK
+        select CPU_ARM926T
+        select GENERIC_CLOCKEVENTS
+        select MIGHT_HAVE_CACHE_L2X0
+        select PINCTRL
+        select PINCTRL_NOMADIK
+        select PINCTRL_STN8815
+        select SPARSE_IRQ
+        select USE_OF
+        help
+          Support for the Nomadik platform by ST-Ericsson
 
+if ARCH_NOMADIK
 menu "Nomadik boards"
 
 config MACH_NOMADIK_8815NHK
@@ -9,8 +28,8 @@ config MACH_NOMADIK_8815NHK
         select I2C_ALGOBIT
 
 endmenu
+endif
 
 config NOMADIK_8815
+        depends on ARCH_NOMADIK
         bool
-
-endif
diff --git a/arch/arm/mach-nomadik/Makefile.boot b/arch/arm/mach-nomadik/Makefile.boot
deleted file mode 100644
index ff0a4b5b0a82..000000000000
--- a/arch/arm/mach-nomadik/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
-   zreladdr-y   += 0x00008000
-params_phys-y   := 0x00000100
-initrd_phys-y   := 0x00800000
-
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 21c1aa512640..59f6ff5c9bae 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -38,7 +38,6 @@
 #include <linux/gpio.h>
 #include <linux/amba/mmci.h>
 
-#include <mach/irqs.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
diff --git a/arch/arm/mach-nomadik/include/mach/irqs.h b/arch/arm/mach-nomadik/include/mach/irqs.h
deleted file mode 100644
index 90ac965a92fe..000000000000
--- a/arch/arm/mach-nomadik/include/mach/irqs.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *  mach-nomadik/include/mach/irqs.h
- *
- *  Copyright (C) ST Microelectronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#define IRQ_VIC_START           32      /* first VIC interrupt is 1 */
-
-/*
- * Interrupt numbers generic for all Nomadik Chip cuts
- */
-#define IRQ_WATCHDOG                    (IRQ_VIC_START+0)
-#define IRQ_SOFTINT                     (IRQ_VIC_START+1)
-#define IRQ_CRYPTO                      (IRQ_VIC_START+2)
-#define IRQ_OWM                         (IRQ_VIC_START+3)
-#define IRQ_MTU0                        (IRQ_VIC_START+4)
-#define IRQ_MTU1                        (IRQ_VIC_START+5)
-#define IRQ_GPIO0                       (IRQ_VIC_START+6)
-#define IRQ_GPIO1                       (IRQ_VIC_START+7)
-#define IRQ_GPIO2                       (IRQ_VIC_START+8)
-#define IRQ_GPIO3                       (IRQ_VIC_START+9)
-#define IRQ_RTC_RTT                     (IRQ_VIC_START+10)
-#define IRQ_SSP                         (IRQ_VIC_START+11)
-#define IRQ_UART0                       (IRQ_VIC_START+12)
-#define IRQ_DMA1                        (IRQ_VIC_START+13)
-#define IRQ_CLCD_MDIF                   (IRQ_VIC_START+14)
-#define IRQ_DMA0                        (IRQ_VIC_START+15)
-#define IRQ_PWRFAIL                     (IRQ_VIC_START+16)
-#define IRQ_UART1                       (IRQ_VIC_START+17)
-#define IRQ_FIRDA                       (IRQ_VIC_START+18)
-#define IRQ_MSP0                        (IRQ_VIC_START+19)
-#define IRQ_I2C0                        (IRQ_VIC_START+20)
-#define IRQ_I2C1                        (IRQ_VIC_START+21)
-#define IRQ_SDMMC                       (IRQ_VIC_START+22)
-#define IRQ_USBOTG                      (IRQ_VIC_START+23)
-#define IRQ_SVA_IT0                     (IRQ_VIC_START+24)
-#define IRQ_SVA_IT1                     (IRQ_VIC_START+25)
-#define IRQ_SAA_IT0                     (IRQ_VIC_START+26)
-#define IRQ_SAA_IT1                     (IRQ_VIC_START+27)
-#define IRQ_UART2                       (IRQ_VIC_START+28)
-#define IRQ_MSP2                        (IRQ_VIC_START+29)
-#define IRQ_L2CC                        (IRQ_VIC_START+30)
-#define IRQ_HPI                         (IRQ_VIC_START+31)
-#define IRQ_SKE                         (IRQ_VIC_START+32)
-#define IRQ_KP                          (IRQ_VIC_START+33)
-#define IRQ_MEMST                       (IRQ_VIC_START+34)
-#define IRQ_SGA_IT                      (IRQ_VIC_START+35)
-#define IRQ_USBM                        (IRQ_VIC_START+36)
-#define IRQ_MSP1                        (IRQ_VIC_START+37)
-
-#define NOMADIK_GPIO_OFFSET             (IRQ_VIC_START+64)
-
-/* After chip-specific IRQ numbers we have the GPIO ones */
-#define NOMADIK_NR_GPIO                 128 /* last 4 not wired to pins */
-#define NOMADIK_GPIO_TO_IRQ(gpio)       ((gpio) + NOMADIK_GPIO_OFFSET)
-#define NOMADIK_IRQ_TO_GPIO(irq)        ((irq) - NOMADIK_GPIO_OFFSET)
-#define NOMADIK_NR_IRQS                 NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
-
-/* Following two are used by entry_macro.S, to access our dual-vic */
-#define VIC_REG_IRQSR0          0
-#define VIC_REG_IRQSR1          0x20
-
-#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-nomadik/include/mach/timex.h b/arch/arm/mach-nomadik/include/mach/timex.h
deleted file mode 100644
index 318b8896ce96..000000000000
--- a/arch/arm/mach-nomadik/include/mach/timex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-
-#define CLOCK_TICK_RATE         2400000
-
-#endif
diff --git a/arch/arm/mach-nomadik/include/mach/uncompress.h b/arch/arm/mach-nomadik/include/mach/uncompress.h
deleted file mode 100644
index 106fccca2021..000000000000
--- a/arch/arm/mach-nomadik/include/mach/uncompress.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- *  Copyright (C) 2008 STMicroelectronics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#include <asm/setup.h>
-#include <asm/io.h>
-
-/* we need the constants in amba/serial.h, but it refers to amba_device */
-struct amba_device;
-#include <linux/amba/serial.h>
-
-#define NOMADIK_UART_DR         (void __iomem *)0x101FB000
-#define NOMADIK_UART_LCRH       (void __iomem *)0x101FB02c
-#define NOMADIK_UART_CR         (void __iomem *)0x101FB030
-#define NOMADIK_UART_FR         (void __iomem *)0x101FB018
-
-static void putc(const char c)
-{
-        /* Do nothing if the UART is not enabled. */
-        if (!(readb(NOMADIK_UART_CR) & UART01x_CR_UARTEN))
-                return;
-
-        if (c == '\n')
-                putc('\r');
-
-        while (readb(NOMADIK_UART_FR) & UART01x_FR_TXFF)
-                barrier();
-        writeb(c, NOMADIK_UART_DR);
-}
-
-static void flush(void)
-{
-        if (!(readb(NOMADIK_UART_CR) & UART01x_CR_UARTEN))
-                return;
-        while (readb(NOMADIK_UART_FR) & UART01x_FR_BUSY)
-                barrier();
-}
-
-static inline void arch_decomp_setup(void)
-{
-}
-
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 903da8eb886c..cdd05f2e67ee 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -55,12 +55,6 @@ config MACH_OMAP_H3
           TI OMAP 1710 H3 board support. Say Y here if you have such
           a board.
 
-config MACH_OMAP_HTCWIZARD
-        bool "HTC Wizard"
-        depends on ARCH_OMAP850
-        help
-          HTC Wizard smartphone support (AKA QTEK 9100, ...)
-
 config MACH_HERALD
         bool "HTC Herald"
         depends on ARCH_OMAP850
diff --git a/arch/arm/mach-omap1/dma.h b/arch/arm/mach-omap1/dma.h
index da6345dab03f..d05909c96715 100644
--- a/arch/arm/mach-omap1/dma.h
+++ b/arch/arm/mach-omap1/dma.h
@@ -21,21 +21,10 @@
 
 /* DMA channels for omap1 */
 #define OMAP_DMA_NO_DEVICE              0
-#define OMAP_DMA_MCSI1_TX               1
-#define OMAP_DMA_MCSI1_RX               2
-#define OMAP_DMA_I2C_RX                 3
-#define OMAP_DMA_I2C_TX                 4
-#define OMAP_DMA_EXT_NDMA_REQ           5
-#define OMAP_DMA_EXT_NDMA_REQ2          6
-#define OMAP_DMA_UWIRE_TX               7
 #define OMAP_DMA_MCBSP1_TX              8
 #define OMAP_DMA_MCBSP1_RX              9
 #define OMAP_DMA_MCBSP3_TX              10
 #define OMAP_DMA_MCBSP3_RX              11
-#define OMAP_DMA_UART1_TX               12
-#define OMAP_DMA_UART1_RX               13
-#define OMAP_DMA_UART2_TX               14
-#define OMAP_DMA_UART2_RX               15
 #define OMAP_DMA_MCBSP2_TX              16
 #define OMAP_DMA_MCBSP2_RX              17
 #define OMAP_DMA_UART3_TX               18
@@ -43,41 +32,11 @@
 #define OMAP_DMA_CAMERA_IF_RX           20
 #define OMAP_DMA_MMC_TX                 21
 #define OMAP_DMA_MMC_RX                 22
-#define OMAP_DMA_NAND                   23
-#define OMAP_DMA_IRQ_LCD_LINE           24
-#define OMAP_DMA_MEMORY_STICK           25
 #define OMAP_DMA_USB_W2FC_RX0           26
-#define OMAP_DMA_USB_W2FC_RX1           27
-#define OMAP_DMA_USB_W2FC_RX2           28
 #define OMAP_DMA_USB_W2FC_TX0           29
-#define OMAP_DMA_USB_W2FC_TX1           30
-#define OMAP_DMA_USB_W2FC_TX2           31
 
 /* These are only for 1610 */
-#define OMAP_DMA_CRYPTO_DES_IN          32
-#define OMAP_DMA_SPI_TX                 33
-#define OMAP_DMA_SPI_RX                 34
-#define OMAP_DMA_CRYPTO_HASH            35
-#define OMAP_DMA_CCP_ATTN               36
-#define OMAP_DMA_CCP_FIFO_NOT_EMPTY     37
-#define OMAP_DMA_CMT_APE_TX_CHAN_0      38
-#define OMAP_DMA_CMT_APE_RV_CHAN_0      39
-#define OMAP_DMA_CMT_APE_TX_CHAN_1      40
-#define OMAP_DMA_CMT_APE_RV_CHAN_1      41
-#define OMAP_DMA_CMT_APE_TX_CHAN_2      42
-#define OMAP_DMA_CMT_APE_RV_CHAN_2      43
-#define OMAP_DMA_CMT_APE_TX_CHAN_3      44
-#define OMAP_DMA_CMT_APE_RV_CHAN_3      45
-#define OMAP_DMA_CMT_APE_TX_CHAN_4      46
-#define OMAP_DMA_CMT_APE_RV_CHAN_4      47
-#define OMAP_DMA_CMT_APE_TX_CHAN_5      48
-#define OMAP_DMA_CMT_APE_RV_CHAN_5      49
-#define OMAP_DMA_CMT_APE_TX_CHAN_6      50
-#define OMAP_DMA_CMT_APE_RV_CHAN_6      51
-#define OMAP_DMA_CMT_APE_TX_CHAN_7      52
-#define OMAP_DMA_CMT_APE_RV_CHAN_7      53
 #define OMAP_DMA_MMC2_TX                54
 #define OMAP_DMA_MMC2_RX                55
-#define OMAP_DMA_CRYPTO_DES_OUT         56
 
 #endif /* __OMAP1_DMA_CHANNEL_H */
diff --git a/arch/arm/mach-omap1/include/mach/usb.h b/arch/arm/mach-omap1/include/mach/usb.h
index 753cd5ce6949..45e5ac707cbb 100644
--- a/arch/arm/mach-omap1/include/mach/usb.h
+++ b/arch/arm/mach-omap1/include/mach/usb.h
@@ -2,7 +2,7 @@
  * FIXME correct answer depends on hmc_mode,
  * as does (on omap1) any nonzero value for config->otg port number
  */
-#ifdef  CONFIG_USB_GADGET_OMAP
+#if IS_ENABLED(CONFIG_USB_OMAP)
 #define is_usb0_device(config)  1
 #else
 #define is_usb0_device(config)  0
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 7a7690ab6cb8..358b82cb9f78 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -37,12 +37,14 @@
 
 #include <linux/suspend.h>
 #include <linux/sched.h>
-#include <linux/proc_fs.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
 #include <linux/interrupt.h>
 #include <linux/sysfs.h>
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/atomic.h>
+#include <linux/cpu.h>
 
 #include <asm/fncpy.h>
 #include <asm/system_misc.h>
@@ -422,23 +424,12 @@ void omap1_pm_suspend(void)
                 omap_rev());
 }
 
-#if defined(DEBUG) && defined(CONFIG_PROC_FS)
-static int g_read_completed;
-
+#ifdef CONFIG_DEBUG_FS
 /*
  * Read system PM registers for debugging
  */
-static int omap_pm_read_proc(
-        char *page_buffer,
-        char **my_first_byte,
-        off_t virtual_start,
-        int length,
-        int *eof,
-        void *data)
+static int omap_pm_debug_show(struct seq_file *m, void *v)
 {
-        int my_buffer_offset = 0;
-        char * const my_base = page_buffer;
-
         ARM_SAVE(ARM_CKCTL);
         ARM_SAVE(ARM_IDLECT1);
         ARM_SAVE(ARM_IDLECT2);
@@ -479,10 +470,7 @@ static int omap_pm_read_proc(
                 MPUI1610_SAVE(EMIFS_CONFIG);
         }
 
-        if (virtual_start == 0) {
-                g_read_completed = 0;
-
-                my_buffer_offset += sprintf(my_base + my_buffer_offset,
+        seq_printf(m,
                    "ARM_CKCTL_REG:            0x%-8x     \n"
                    "ARM_IDLECT1_REG:          0x%-8x     \n"
                    "ARM_IDLECT2_REG:          0x%-8x     \n"
@@ -512,8 +500,8 @@ static int omap_pm_read_proc(
                    ULPD_SHOW(ULPD_STATUS_REQ),
                    ULPD_SHOW(ULPD_POWER_CTRL));
 
-                if (cpu_is_omap7xx()) {
-                        my_buffer_offset += sprintf(my_base + my_buffer_offset,
+        if (cpu_is_omap7xx()) {
+                seq_printf(m,
                            "MPUI7XX_CTRL_REG         0x%-8x \n"
                            "MPUI7XX_DSP_STATUS_REG:      0x%-8x \n"
                            "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
@@ -526,8 +514,8 @@ static int omap_pm_read_proc(
                            MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
                            MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
                            MPUI7XX_SHOW(EMIFS_CONFIG));
-                } else if (cpu_is_omap15xx()) {
-                        my_buffer_offset += sprintf(my_base + my_buffer_offset,
+        } else if (cpu_is_omap15xx()) {
+                seq_printf(m,
                            "MPUI1510_CTRL_REG             0x%-8x \n"
                            "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
                            "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
@@ -540,8 +528,8 @@ static int omap_pm_read_proc(
                            MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
                            MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
                            MPUI1510_SHOW(EMIFS_CONFIG));
-                } else if (cpu_is_omap16xx()) {
-                        my_buffer_offset += sprintf(my_base + my_buffer_offset,
+        } else if (cpu_is_omap16xx()) {
+                seq_printf(m,
                            "MPUI1610_CTRL_REG             0x%-8x \n"
                            "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
                            "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
@@ -554,28 +542,37 @@ static int omap_pm_read_proc(
                            MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
                            MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
                            MPUI1610_SHOW(EMIFS_CONFIG));
-                }
-
-                g_read_completed++;
-        } else if (g_read_completed >= 1) {
-                 *eof = 1;
-                 return 0;
         }
-        g_read_completed++;
 
-        *my_first_byte = page_buffer;
-        return  my_buffer_offset;
+        return 0;
 }
 
-static void omap_pm_init_proc(void)
+static int omap_pm_debug_open(struct inode *inode, struct file *file)
 {
-        /* XXX Appears to leak memory */
-        create_proc_read_entry("driver/omap_pm",
-                               S_IWUSR | S_IRUGO, NULL,
-                               omap_pm_read_proc, NULL);
+        return single_open(file, omap_pm_debug_show,
+                                &inode->i_private);
 }
 
-#endif /* DEBUG && CONFIG_PROC_FS */
+static const struct file_operations omap_pm_debug_fops = {
+        .open           = omap_pm_debug_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static void omap_pm_init_debugfs(void)
+{
+        struct dentry *d;
+
+        d = debugfs_create_dir("pm_debug", NULL);
+        if (!d)
+                return;
+
+        (void) debugfs_create_file("omap_pm", S_IWUSR | S_IRUGO,
+                                        d, NULL, &omap_pm_debug_fops);
+}
+
+#endif /* CONFIG_DEBUG_FS */
 
 /*
  *      omap_pm_prepare - Do preliminary suspend work.
@@ -584,8 +581,7 @@ static void omap_pm_init_proc(void)
 static int omap_pm_prepare(void)
 {
         /* We cannot sleep in idle until we have resumed */
-        disable_hlt();
-
+        cpu_idle_poll_ctrl(true);
         return 0;
 }
 
@@ -621,7 +617,7 @@ static int omap_pm_enter(suspend_state_t state)
 
 static void omap_pm_finish(void)
 {
-        enable_hlt();
+        cpu_idle_poll_ctrl(false);
 }
 
 
@@ -701,8 +697,8 @@ static int __init omap_pm_init(void)
 
         suspend_set_ops(&omap_pm_ops);
 
-#if defined(DEBUG) && defined(CONFIG_PROC_FS)
-        omap_pm_init_proc();
+#ifdef CONFIG_DEBUG_FS
+        omap_pm_init_debugfs();
 #endif
 
 #ifdef CONFIG_OMAP_32K_TIMER
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c
index 1a1db5971cd9..4118db50d5e8 100644
--- a/arch/arm/mach-omap1/usb.c
+++ b/arch/arm/mach-omap1/usb.c
@@ -123,7 +123,7 @@ omap_otg_init(struct omap_usb_config *config)
         syscon = omap_readl(OTG_SYSCON_1);
         syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
 
-#ifdef  CONFIG_USB_GADGET_OMAP
+#if IS_ENABLED(CONFIG_USB_OMAP)
         if (config->otg || config->register_dev) {
                 struct platform_device *udc_device = config->udc_device;
                 int status;
@@ -169,7 +169,7 @@ omap_otg_init(struct omap_usb_config *config)
 void omap_otg_init(struct omap_usb_config *config) {}
 #endif
 
-#ifdef  CONFIG_USB_GADGET_OMAP
+#if IS_ENABLED(CONFIG_USB_OMAP)
 
 static struct resource udc_resources[] = {
         /* order is significant! */
@@ -600,7 +600,7 @@ static void __init omap_1510_usb_init(struct omap_usb_config *config)
         while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
                 cpu_relax();
 
-#ifdef  CONFIG_USB_GADGET_OMAP
+#if IS_ENABLED(CONFIG_USB_OMAP)
         if (config->register_dev) {
                 int status;
 
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 8111cd9ff3e5..857b1f097fd8 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -15,6 +15,7 @@ config ARCH_OMAP2PLUS
         select OMAP_DM_TIMER
         select PINCTRL
         select PROC_DEVICETREE if PROC_FS
+        select SOC_BUS
         select SPARSE_IRQ
         select USE_OF
         help
@@ -55,6 +56,7 @@ config SOC_HAS_REALTIME_COUNTER
 config ARCH_OMAP2
         bool "TI OMAP2"
         depends on ARCH_OMAP2PLUS
+        depends on ARCH_MULTI_V6
         default y
         select CPU_V6
         select MULTI_IRQ_HANDLER
@@ -64,6 +66,7 @@ config ARCH_OMAP2
 config ARCH_OMAP3
         bool "TI OMAP3"
         depends on ARCH_OMAP2PLUS
+        depends on ARCH_MULTI_V7
         default y
         select ARCH_HAS_OPP
         select ARM_CPU_SUSPEND if PM
@@ -80,6 +83,7 @@ config ARCH_OMAP4
         bool "TI OMAP4"
         default y
         depends on ARCH_OMAP2PLUS
+        depends on ARCH_MULTI_V7
         select ARCH_HAS_OPP
         select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
         select ARM_CPU_SUSPEND if PM
@@ -87,6 +91,8 @@ config ARCH_OMAP4
         select ARM_GIC
         select CACHE_L2X0
         select CPU_V7
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
         select HAVE_SMP
         select LOCAL_TIMERS if SMP
         select OMAP_INTERCONNECT
@@ -96,9 +102,12 @@ config ARCH_OMAP4
         select PM_RUNTIME if CPU_IDLE
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
         select COMMON_CLK
+        select ARM_ERRATA_754322
+        select ARM_ERRATA_775420
 
 config SOC_OMAP5
         bool "TI OMAP5"
+        depends on ARCH_MULTI_V7
         select ARM_CPU_SUSPEND if PM
         select ARM_GIC
         select CPU_V7
@@ -135,6 +144,7 @@ config SOC_TI81XX
 
 config SOC_AM33XX
         bool "AM33XX support"
+        depends on ARCH_MULTI_V7
         default y
         select ARM_CPU_SUSPEND if PM
         select CPU_V7
@@ -408,7 +418,7 @@ config OMAP3_SDRC_AC_TIMING
 
 config OMAP4_ERRATA_I688
         bool "OMAP4 errata: Async Bridge Corruption"
-        depends on ARCH_OMAP4 && !ARCH_MULTIPLATFORM
+        depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM
         select ARCH_HAS_BARRIERS
         help
           If a data is stalled inside asynchronous bridge because of back
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b068b7fe99ef..62bb352c2d37 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -229,7 +229,6 @@ obj-$(CONFIG_MACH_DEVKIT8000)     	+= board-devkit8000.o
 obj-$(CONFIG_MACH_OMAP_LDP)             += board-ldp.o
 obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o
 obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o
-obj-$(CONFIG_MACH_ENCORE)               += board-omap3encore.o
 obj-$(CONFIG_MACH_OVERO)                += board-overo.o
 obj-$(CONFIG_MACH_OMAP3EVM)             += board-omap3evm.o
 obj-$(CONFIG_MACH_OMAP3_PANDORA)        += board-omap3pandora.o
@@ -255,8 +254,6 @@ obj-$(CONFIG_MACH_TOUCHBOOK)		+= board-omap3touchbook.o
 obj-$(CONFIG_MACH_OMAP_4430SDP)         += board-4430sdp.o
 obj-$(CONFIG_MACH_OMAP4_PANDA)          += board-omap4panda.o
 
-obj-$(CONFIG_MACH_PCM049)               += board-omap4pcm049.o
-
 obj-$(CONFIG_MACH_OMAP3517EVM)          += board-am3517evm.o
 
 obj-$(CONFIG_MACH_CRANEBOARD)           += board-am3517crane.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index a3e0aaa4886b..5b86423c89fa 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -38,7 +38,7 @@
 #include "gpmc-smc91x.h"
 
 #include <video/omapdss.h>
-#include <video/omap-panel-generic-dpi.h>
+#include <video/omap-panel-data.h>
 
 #include "mux.h"
 #include "hsmmc.h"
@@ -166,7 +166,7 @@ static void __init sdp2430_display_init(void)
         omap_display_init(&sdp2430_dss_data);
 }
 
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
 
 static struct omap_smc91x_platform_data board_smc91x_data = {
         .cs             = 5,
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index ce812decfaca..a4d4664894e1 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -35,7 +35,7 @@
 #include "common.h"
 #include <linux/omap-dma.h>
 #include <video/omapdss.h>
-#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-data.h>
 
 #include "gpmc.h"
 #include "gpmc-smc91x.h"
@@ -445,16 +445,23 @@ static void enable_board_wakeup_source(void)
                 OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = 57,
+                .vcc_gpio = -EINVAL,
+        },
+        {
+                .port = 2,
+                .reset_gpio = 61,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
 
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = 57,
-        .reset_gpio_port[1]  = 61,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -606,6 +613,8 @@ static void __init omap_3430sdp_init(void)
         board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
         sdp3430_display_init();
         enable_board_wakeup_source();
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
 }
 
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 67447bd4564f..20d6d8189240 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -53,16 +53,23 @@ static void enable_board_wakeup_source(void)
                 OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = 126,
+                .vcc_gpio = -EINVAL,
+        },
+        {
+                .port = 2,
+                .reset_gpio = 61,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
 
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = 126,
-        .reset_gpio_port[1]  = 61,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -199,6 +206,8 @@ static void __init omap_sdp_init(void)
         board_smc91x_init();
         board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
         enable_board_wakeup_source();
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
 }
 
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 35f3ad0cb7c7..00d72902ef4f 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -291,6 +291,10 @@ static struct platform_device sdp4430_leds_pwm = {
         },
 };
 
+/* Dummy regulator for pwm-backlight driver */
+static struct regulator_consumer_supply backlight_supply =
+        REGULATOR_SUPPLY("enable", "pwm-backlight");
+
 static struct platform_pwm_backlight_data sdp4430_backlight_data = {
         .max_brightness = 127,
         .dft_brightness = 127,
@@ -718,6 +722,8 @@ static void __init omap_4430sdp_init(void)
 
         omap4_i2c_init();
         omap_sfh7741prox_init();
+        regulator_register_always_on(0, "backlight-enable",
+                                     &backlight_supply, 1, 0);
         platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
         omap_serial_init();
         omap_sdrc_init(NULL, NULL);
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 7d3358b2e593..fc53911d0d13 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -47,15 +47,17 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = GPIO_USB_NRESET,
+                .vcc_gpio = GPIO_USB_POWER,
+                .vcc_polarity = 1,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = GPIO_USB_NRESET,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 static struct mtd_partition crane_nand_partitions[] = {
@@ -131,13 +133,7 @@ static void __init am3517_crane_init(void)
                 return;
         }
 
-        ret = gpio_request_one(GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH,
-                               "usb_ehci_enable");
-        if (ret < 0) {
-                pr_err("Can not request GPIO %d\n", GPIO_USB_POWER);
-                return;
-        }
-
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
 }
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 9fb85908a61e..c29d2e743688 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -35,8 +35,7 @@
 
 #include "common.h"
 #include <video/omapdss.h>
-#include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-data.h>
 
 #include "am35xx-emac.h"
 #include "mux.h"
@@ -274,6 +273,14 @@ static __init void am3517_evm_mcbsp1_init(void)
         omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = 57,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
 #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
@@ -282,12 +289,6 @@ static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
 #else
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
 #endif
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = 57,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -349,7 +350,6 @@ static struct omap2_hsmmc_info mmc[] = {
         {}      /* Terminator */
 };
 
-
 static void __init am3517_evm_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@@ -361,6 +361,8 @@ static void __init am3517_evm_init(void)
 
         /* Configure GPIO for EHCI port */
         omap_mux_init_gpio(57, OMAP_PIN_OUTPUT);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         am3517_evm_hecc_init(&am3517_evm_hecc_pdata);
         /* DSS */
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index af2bb219e214..e0ed8c07fc54 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -41,8 +41,7 @@
 
 #include <linux/platform_data/mtd-nand-omap2.h>
 #include <video/omapdss.h>
-#include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-data.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 
 #include "common.h"
@@ -419,15 +418,22 @@ static struct omap2_hsmmc_info mmc[] = {
         {}      /* Terminator */
 };
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = OMAP_MAX_GPIO_LINES + 6,
+                .vcc_gpio = -EINVAL,
+        },
+        {
+                .port = 2,
+                .reset_gpio = OMAP_MAX_GPIO_LINES + 7,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = OMAP_MAX_GPIO_LINES + 6,
-        .reset_gpio_port[1]  = OMAP_MAX_GPIO_LINES + 7,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 static void  __init cm_t35_init_usbh(void)
@@ -444,6 +450,7 @@ static void  __init cm_t35_init_usbh(void)
                 msleep(1);
         }
 
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
 }
 
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index a66da808cc4a..4eb5e6f2f7f5 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -188,15 +188,22 @@ static inline void cm_t3517_init_rtc(void) {}
 #define HSUSB2_RESET_GPIO       (147)
 #define USB_HUB_RESET_GPIO      (152)
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = HSUSB1_RESET_GPIO,
+                .vcc_gpio = -EINVAL,
+        },
+        {
+                .port = 2,
+                .reset_gpio = HSUSB2_RESET_GPIO,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data cm_t3517_ehci_pdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = HSUSB1_RESET_GPIO,
-        .reset_gpio_port[1]  = HSUSB2_RESET_GPIO,
-        .reset_gpio_port[2]  = -EINVAL,
 };
 
 static int __init cm_t3517_init_usbh(void)
@@ -213,6 +220,7 @@ static int __init cm_t3517_init_usbh(void)
                 msleep(1);
         }
 
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&cm_t3517_ehci_pdata);
 
         return 0;
@@ -324,6 +332,6 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
         .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = cm_t3517_init,
         .init_late      = am35xx_init_late,
-        .init_time      = omap3_gp_gptimer_timer_init,
+        .init_time      = omap3_gptimer_timer_init,
         .restart        = omap3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 53056c3b0836..e44b804f75ae 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -43,8 +43,7 @@
 #include "gpmc.h"
 #include <linux/platform_data/mtd-nand-omap2.h>
 #include <video/omapdss.h>
-#include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-data.h>
 
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/input/matrix_keypad.h>
@@ -437,15 +436,7 @@ static struct platform_device *devkit8000_devices[] __initdata = {
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index e54a48060198..78813b397209 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -140,7 +140,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
         .init_irq       = omap_intc_of_init,
         .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap_generic_init,
-        .init_time      = omap3_am33xx_gptimer_timer_init,
+        .init_time      = omap3_gptimer_timer_init,
         .dt_compat      = am33xx_boards_compat,
         .restart        = am33xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 812c829fa46f..69c0acf5aa63 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -34,7 +34,7 @@
 #include <asm/mach/map.h>
 
 #include <video/omapdss.h>
-#include <video/omap-panel-generic-dpi.h>
+#include <video/omap-panel-data.h>
 
 #include "common.h"
 #include "mux.h"
@@ -246,7 +246,7 @@ static u32 is_gpmc_muxed(void)
                 return 0;
 }
 
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
 
 static struct omap_smc91x_platform_data board_smc91x_data = {
         .cs             = 1,
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index bf92678a01d0..b54562d1235e 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -31,7 +31,7 @@
 #include <asm/mach/arch.h>
 
 #include <video/omapdss.h>
-#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-data.h>
 #include <linux/platform_data/mtd-onenand-omap2.h>
 
 #include "common.h"
@@ -527,26 +527,28 @@ static void __init igep_i2c_init(void)
         omap3_pmic_init("twl4030", &igep_twldata);
 }
 
+static struct usbhs_phy_data igep2_phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = IGEP2_GPIO_USBH_NRESET,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
+static struct usbhs_phy_data igep3_phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = IGEP3_GPIO_USBH_NRESET,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data igep2_usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset = true,
-        .reset_gpio_port[0] = IGEP2_GPIO_USBH_NRESET,
-        .reset_gpio_port[1] = -EINVAL,
-        .reset_gpio_port[2] = -EINVAL,
 };
 
 static struct usbhs_omap_platform_data igep3_usbhs_bdata __initdata = {
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset = true,
-        .reset_gpio_port[0] = -EINVAL,
-        .reset_gpio_port[1] = IGEP3_GPIO_USBH_NRESET,
-        .reset_gpio_port[2] = -EINVAL,
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -642,8 +644,10 @@ static void __init igep_init(void)
         if (machine_is_igep0020()) {
                 omap_display_init(&igep2_dss_data);
                 igep2_init_smsc911x();
+                usbhs_init_phys(igep2_phy_data, ARRAY_SIZE(igep2_phy_data));
                 usbhs_init(&igep2_usbhs_bdata);
         } else {
+                usbhs_init_phys(igep3_phy_data, ARRAY_SIZE(igep3_phy_data));
                 usbhs_init(&igep3_usbhs_bdata);
         }
 }
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index b12fe966a7b9..8a8e505a0e90 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -41,7 +41,7 @@
 #include "gpmc-smsc911x.h"
 
 #include <video/omapdss.h>
-#include <video/omap-panel-generic-dpi.h>
+#include <video/omap-panel-data.h>
 
 #include "board-flash.h"
 #include "mux.h"
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index c3558f93d42c..6de78605c0af 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -33,6 +33,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mmc/host.h>
 #include <linux/usb/phy.h>
+#include <linux/usb/nop-usb-xceiv.h>
 
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
@@ -43,7 +44,7 @@
 #include <asm/mach/flash.h>
 
 #include <video/omapdss.h>
-#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-data.h>
 #include <linux/platform_data/mtd-nand-omap2.h>
 
 #include "common.h"
@@ -277,6 +278,21 @@ static struct regulator_consumer_supply beagle_vsim_supply[] = {
 
 static struct gpio_led gpio_leds[];
 
+/* PHY's VCC regulator might be added later, so flag that we need it */
+static struct nop_usb_xceiv_platform_data hsusb2_phy_data = {
+        .needs_vcc = true,
+};
+
+static struct usbhs_phy_data phy_data[] = {
+        {
+                .port = 2,
+                .reset_gpio = 147,
+                .vcc_gpio = -1,         /* updated in beagle_twl_gpio_setup */
+                .vcc_polarity = 1,      /* updated in beagle_twl_gpio_setup */
+                .platform_data = &hsusb2_phy_data,
+        },
+};
+
 static int beagle_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
@@ -318,9 +334,11 @@ static int beagle_twl_gpio_setup(struct device *dev,
         }
         dvi_panel.power_down_gpio = beagle_config.dvi_pd_gpio;
 
-        gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level,
-                        "nEN_USB_PWR");
+        /* TWL4030_GPIO_MAX i.e. LED_GPO controls HS USB Port 2 power */
+        phy_data[0].vcc_gpio = gpio + TWL4030_GPIO_MAX;
+        phy_data[0].vcc_polarity = beagle_config.usb_pwr_level;
 
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         return 0;
 }
 
@@ -453,15 +471,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = {
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = 147,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -479,7 +489,7 @@ static int __init beagle_opp_init(void)
 
         /* Initialize the omap3 opp table if not already created. */
         r = omap3_opp_init();
-        if (IS_ERR_VALUE(r) && (r != -EEXIST)) {
+        if (r < 0 && (r != -EEXIST)) {
                 pr_err("%s: opp default init failed\n", __func__);
                 return r;
         }
@@ -543,7 +553,9 @@ static void __init omap3_beagle_init(void)
 
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
+
         usbhs_init(&usbhs_bdata);
+
         board_nand_init(omap3beagle_nand_partitions,
                         ARRAY_SIZE(omap3beagle_nand_partitions), NAND_CS,
                         NAND_BUSWIDTH_16, NULL);
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 48789e0bb915..4f1bbc3cc29b 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -51,7 +51,7 @@
 #include "common.h"
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <video/omapdss.h>
-#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-data.h>
 
 #include "soc.h"
 #include "mux.h"
@@ -496,7 +496,7 @@ struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
 static struct regulator_consumer_supply omap3evm_vaux2_supplies[] = {
         REGULATOR_SUPPLY("VDD_CSIPHY1", "omap3isp"),    /* OMAP ISP */
         REGULATOR_SUPPLY("VDD_CSIPHY2", "omap3isp"),    /* OMAP ISP */
-        REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"),
+        REGULATOR_SUPPLY("vcc", "nop_usb_xceiv.2"),     /* hsusb port 2 */
         REGULATOR_SUPPLY("vaux2", NULL),
 };
 
@@ -539,17 +539,16 @@ static int __init omap3_evm_i2c_init(void)
         return 0;
 }
 
-static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = -1,       /* set at runtime */
+                .vcc_gpio = -EINVAL,
+        },
+};
 
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        /* PHY reset GPIO will be runtime programmed based on EVM version */
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -725,7 +724,7 @@ static void __init omap3_evm_init(void)
 
                 /* setup EHCI phy reset config */
                 omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
-                usbhs_bdata.reset_gpio_port[1] = 21;
+                phy_data[0].reset_gpio = 21;
 
                 /* EVM REV >= E can supply 500mA with EXTVBUS programming */
                 musb_board_data.power = 500;
@@ -733,10 +732,12 @@ static void __init omap3_evm_init(void)
         } else {
                 /* setup EHCI phy reset on MDC */
                 omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
-                usbhs_bdata.reset_gpio_port[1] = 135;
+                phy_data[0].reset_gpio = 135;
         }
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(&musb_board_data);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         board_nand_init(omap3evm_nand_partitions,
                         ARRAY_SIZE(omap3evm_nand_partitions), NAND_CS,
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 2bba362148a0..1004d2aaa68f 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -346,7 +346,7 @@ static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = {
 };
 
 static struct regulator_consumer_supply pandora_usb_phy_supply[] = {
-        REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"),
+        REGULATOR_SUPPLY("vcc", "nop_usb_xceiv.2"),     /* hsusb port 2 */
 };
 
 /* ads7846 on SPI and 2 nub controllers on I2C */
@@ -561,6 +561,14 @@ fail:
         printk(KERN_ERR "wl1251 board initialisation failed\n");
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = 16,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct platform_device *omap3pandora_devices[] __initdata = {
         &pandora_leds_gpio,
         &pandora_keys_gpio,
@@ -569,15 +577,7 @@ static struct platform_device *omap3pandora_devices[] __initdata = {
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = 16,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -601,7 +601,10 @@ static void __init omap3pandora_init(void)
         spi_register_board_info(omap3pandora_spi_board_info,
                         ARRAY_SIZE(omap3pandora_spi_board_info));
         omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
+
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
         gpmc_nand_init(&pandora_nand_data, NULL);
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 95c10b3aa678..8afbba0923d6 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -44,8 +44,7 @@
 #include "gpmc.h"
 #include <linux/platform_data/mtd-nand-omap2.h>
 #include <video/omapdss.h>
-#include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-data.h>
 
 #include <linux/platform_data/spi-omap2-mcspi.h>
 
@@ -358,19 +357,20 @@ static int __init omap3_stalker_i2c_init(void)
 
 #define OMAP3_STALKER_TS_GPIO   175
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = 21,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct platform_device *omap3_stalker_devices[] __initdata = {
         &keys_gpio,
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset = true,
-        .reset_gpio_port[0] = -EINVAL,
-        .reset_gpio_port[1] = 21,
-        .reset_gpio_port[2] = -EINVAL,
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -407,6 +407,8 @@ static void __init omap3_stalker_init(void)
         omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         omap_ads7846_init(1, OMAP3_STALKER_TS_GPIO, 310, NULL);
 
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index bcd44fbcd877..7da48bc42bbf 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -305,21 +305,22 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = 147,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct platform_device *omap3_touchbook_devices[] __initdata = {
         &leds_gpio,
         &keys_gpio,
 };
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = 147,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 static void omap3_touchbook_poweroff(void)
@@ -368,6 +369,8 @@ static void __init omap3_touchbook_init(void)
         omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         board_nand_init(omap3touchbook_nand_partitions,
                         ARRAY_SIZE(omap3touchbook_nand_partitions), NAND_CS,
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index b02c2f00609b..a71ad345f20d 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -31,6 +31,7 @@
 #include <linux/ti_wilink_st.h>
 #include <linux/usb/musb.h>
 #include <linux/usb/phy.h>
+#include <linux/usb/nop-usb-xceiv.h>
 #include <linux/wl12xx.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/omap-abe-twl6040.h>
@@ -132,6 +133,22 @@ static struct platform_device btwilink_device = {
         .id     = -1,
 };
 
+/* PHY device on HS USB Port 1 i.e. nop_usb_xceiv.1 */
+static struct nop_usb_xceiv_platform_data hsusb1_phy_data = {
+        /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
+        .clk_rate = 19200000,
+};
+
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 1,
+                .reset_gpio = GPIO_HUB_NRESET,
+                .vcc_gpio = GPIO_HUB_POWER,
+                .vcc_polarity = 1,
+                .platform_data = &hsusb1_phy_data,
+        },
+};
+
 static struct platform_device *panda_devices[] __initdata = {
         &leds_gpio,
         &wl1271_device,
@@ -142,49 +159,19 @@ static struct platform_device *panda_devices[] __initdata = {
 
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .phy_reset  = false,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = -EINVAL,
-        .reset_gpio_port[2]  = -EINVAL
-};
-
-static struct gpio panda_ehci_gpios[] __initdata = {
-        { GPIO_HUB_POWER,       GPIOF_OUT_INIT_LOW,  "hub_power"  },
-        { GPIO_HUB_NRESET,      GPIOF_OUT_INIT_LOW,  "hub_nreset" },
 };
 
 static void __init omap4_ehci_init(void)
 {
         int ret;
-        struct clk *phy_ref_clk;
 
         /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
-        phy_ref_clk = clk_get(NULL, "auxclk3_ck");
-        if (IS_ERR(phy_ref_clk)) {
-                pr_err("Cannot request auxclk3\n");
-                return;
-        }
-        clk_set_rate(phy_ref_clk, 19200000);
-        clk_prepare_enable(phy_ref_clk);
-
-        /* disable the power to the usb hub prior to init and reset phy+hub */
-        ret = gpio_request_array(panda_ehci_gpios,
-                                 ARRAY_SIZE(panda_ehci_gpios));
-        if (ret) {
-                pr_err("Unable to initialize EHCI power/reset\n");
-                return;
-        }
-
-        gpio_export(GPIO_HUB_POWER, 0);
-        gpio_export(GPIO_HUB_NRESET, 0);
-        gpio_set_value(GPIO_HUB_NRESET, 1);
+        ret = clk_add_alias("main_clk", "nop_usb_xceiv.1", "auxclk3_ck", NULL);
+        if (ret)
+                pr_err("Failed to add main_clk alias to auxclk3_ck\n");
 
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
-
-        /* enable power to hub */
-        gpio_set_value(GPIO_HUB_POWER, 1);
 }
 
 static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 86bab51154ee..f9101407cd56 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -47,8 +47,7 @@
 #include <asm/mach/map.h>
 
 #include <video/omapdss.h>
-#include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-tfp410.h>
+#include <video/omap-panel-data.h>
 
 #include "common.h"
 #include "mux.h"
@@ -458,14 +457,16 @@ static int __init overo_spi_init(void)
         return 0;
 }
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = OVERO_GPIO_USBH_NRESET,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = OVERO_GPIO_USBH_NRESET,
-        .reset_gpio_port[2]  = -EINVAL
 };
 
 #ifdef CONFIG_OMAP_MUX
@@ -502,6 +503,8 @@ static void __init overo_init(void)
                         ARRAY_SIZE(overo_nand_partitions), NAND_CS, 0, NULL);
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
+
+        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
         usbhs_init(&usbhs_bdata);
         overo_spi_init();
         overo_init_smsc911x();
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 3a077df6b8df..1a884670a6c4 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -547,12 +547,16 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = {
         REGULATOR_SUPPLY("DVDD", "2-0019"),
         /* Si4713 IO supply */
         REGULATOR_SUPPLY("vio", "2-0063"),
+        /* lis3lv02d */
+        REGULATOR_SUPPLY("Vdd_IO", "3-001d"),
 };
 
 static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
         REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
         /* Si4713 supply */
         REGULATOR_SUPPLY("vdd", "2-0063"),
+        /* lis3lv02d */
+        REGULATOR_SUPPLY("Vdd", "3-001d"),
 };
 
 static struct regulator_init_data rx51_vaux1 = {
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index 8cef477d6b00..9a7174faac51 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -12,7 +12,6 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
-#include <linux/i2c/twl.h>
 #include <linux/spi/spi.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <video/omapdss.h>
@@ -49,59 +48,6 @@ static void zoom_panel_disable_lcd(struct omap_dss_device *dssdev)
 {
 }
 
-/* Register offsets in TWL4030_MODULE_INTBR */
-#define TWL_INTBR_PMBR1 0xD
-#define TWL_INTBR_GPBR1 0xC
-
-/* Register offsets in TWL_MODULE_PWM */
-#define TWL_LED_PWMON   0x3
-#define TWL_LED_PWMOFF  0x4
-
-static int zoom_set_bl_intensity(struct omap_dss_device *dssdev, int level)
-{
-#ifdef CONFIG_TWL4030_CORE
-        unsigned char c;
-        u8 mux_pwm, enb_pwm;
-
-        if (level > 100)
-                return -1;
-
-        twl_i2c_read_u8(TWL4030_MODULE_INTBR, &mux_pwm, TWL_INTBR_PMBR1);
-        twl_i2c_read_u8(TWL4030_MODULE_INTBR, &enb_pwm, TWL_INTBR_GPBR1);
-
-        if (level == 0) {
-                /* disable pwm1 output and clock */
-                enb_pwm = enb_pwm & 0xF5;
-                /* change pwm1 pin to gpio pin */
-                mux_pwm = mux_pwm & 0xCF;
-                twl_i2c_write_u8(TWL4030_MODULE_INTBR,
-                                        enb_pwm, TWL_INTBR_GPBR1);
-                twl_i2c_write_u8(TWL4030_MODULE_INTBR,
-                                        mux_pwm, TWL_INTBR_PMBR1);
-                return 0;
-        }
-
-        if (!((enb_pwm & 0xA) && (mux_pwm & 0x30))) {
-                /* change gpio pin to pwm1 pin */
-                mux_pwm = mux_pwm | 0x30;
-                /* enable pwm1 output and clock*/
-                enb_pwm = enb_pwm | 0x0A;
-                twl_i2c_write_u8(TWL4030_MODULE_INTBR,
-                                        mux_pwm, TWL_INTBR_PMBR1);
-                twl_i2c_write_u8(TWL4030_MODULE_INTBR,
-                                        enb_pwm, TWL_INTBR_GPBR1);
-        }
-
-        c = ((50 * (100 - level)) / 100) + 1;
-        twl_i2c_write_u8(TWL_MODULE_PWM, 0x7F, TWL_LED_PWMOFF);
-        twl_i2c_write_u8(TWL_MODULE_PWM, c, TWL_LED_PWMON);
-#else
-        pr_warn("Backlight not enabled\n");
-#endif
-
-        return 0;
-}
-
 static struct omap_dss_device zoom_lcd_device = {
         .name                   = "lcd",
         .driver_name            = "NEC_8048_panel",
@@ -109,8 +55,6 @@ static struct omap_dss_device zoom_lcd_device = {
         .phy.dpi.data_lines     = 24,
         .platform_enable        = zoom_panel_enable_lcd,
         .platform_disable       = zoom_panel_disable_lcd,
-        .max_backlight_level    = 100,
-        .set_backlight          = zoom_set_bl_intensity,
 };
 
 static struct omap_dss_device *zoom_dss_devices[] = {
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index cdc0c1021863..a90375d5b2b6 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -22,6 +22,9 @@
 #include <linux/platform_data/gpio-omap.h>
 #include <linux/platform_data/omap-twl4030.h>
 #include <linux/usb/phy.h>
+#include <linux/pwm.h>
+#include <linux/leds_pwm.h>
+#include <linux/pwm_backlight.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -193,6 +196,53 @@ static struct platform_device omap_vwlan_device = {
         },
 };
 
+static struct pwm_lookup zoom_pwm_lookup[] = {
+        PWM_LOOKUP("twl-pwm", 0, "leds_pwm", "zoom::keypad"),
+        PWM_LOOKUP("twl-pwm", 1, "pwm-backlight", "backlight"),
+};
+
+static struct led_pwm zoom_pwm_leds[] = {
+        {
+                .name           = "zoom::keypad",
+                .max_brightness = 127,
+                .pwm_period_ns  = 7812500,
+        },
+};
+
+static struct led_pwm_platform_data zoom_pwm_data = {
+        .num_leds       = ARRAY_SIZE(zoom_pwm_leds),
+        .leds           = zoom_pwm_leds,
+};
+
+static struct platform_device zoom_leds_pwm = {
+        .name   = "leds_pwm",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &zoom_pwm_data,
+        },
+};
+
+static struct platform_pwm_backlight_data zoom_backlight_data = {
+        .pwm_id = 1,
+        .max_brightness = 127,
+        .dft_brightness = 127,
+        .pwm_period_ns = 7812500,
+};
+
+static struct platform_device zoom_backlight_pwm = {
+        .name   = "pwm-backlight",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &zoom_backlight_data,
+        },
+};
+
+static struct platform_device *zoom_devices[] __initdata = {
+        &omap_vwlan_device,
+        &zoom_leds_pwm,
+        &zoom_backlight_pwm,
+};
+
 static struct wl12xx_platform_data omap_zoom_wlan_data __initdata = {
         .board_ref_clock = WL12XX_REFCLOCK_26, /* 26 MHz */
 };
@@ -301,7 +351,8 @@ void __init zoom_peripherals_init(void)
 
         omap_hsmmc_init(mmc);
         omap_i2c_init();
-        platform_device_register(&omap_vwlan_device);
+        pwm_add_table(zoom_pwm_lookup, ARRAY_SIZE(zoom_pwm_lookup));
+        platform_add_devices(zoom_devices, ARRAY_SIZE(zoom_devices));
         usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
         usb_musb_init(NULL);
         enable_board_wakeup_source();
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 5e4d4c9fe61a..1a3dd865d8eb 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -92,14 +92,16 @@ static struct mtd_partition zoom_nand_partitions[] = {
         },
 };
 
+static struct usbhs_phy_data phy_data[] __initdata = {
+        {
+                .port = 2,
+                .reset_gpio = ZOOM3_EHCI_RESET_GPIO,
+                .vcc_gpio = -EINVAL,
+        },
+};
+
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-        .port_mode[0]           = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1]           = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2]           = OMAP_USBHS_PORT_MODE_UNUSED,
-        .phy_reset              = true,
-        .reset_gpio_port[0]     = -EINVAL,
-        .reset_gpio_port[1]     = ZOOM3_EHCI_RESET_GPIO,
-        .reset_gpio_port[2]     = -EINVAL,
 };
 
 static void __init omap_zoom_init(void)
@@ -109,6 +111,8 @@ static void __init omap_zoom_init(void)
         } else if (machine_is_omap_zoom3()) {
                 omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
                 omap_mux_init_gpio(ZOOM3_EHCI_RESET_GPIO, OMAP_PIN_OUTPUT);
+
+                usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
                 usbhs_init(&usbhs_bdata);
         }
 
diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c
index 0f0a97c1fcc0..3662f4d4c8ea 100644
--- a/arch/arm/mach-omap2/cclock2420_data.c
+++ b/arch/arm/mach-omap2/cclock2420_data.c
@@ -1739,153 +1739,153 @@ DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
 
 static struct omap_clk omap2420_clks[] = {
         /* external root sources */
-        CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_242X),
-        CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_242X),
-        CLK(NULL,       "osc_ck",       &osc_ck,        CK_242X),
-        CLK(NULL,       "sys_ck",       &sys_ck,        CK_242X),
-        CLK(NULL,       "alt_ck",       &alt_ck,        CK_242X),
-        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_242X),
+        CLK(NULL,       "func_32k_ck",  &func_32k_ck),
+        CLK(NULL,       "secure_32k_ck", &secure_32k_ck),
+        CLK(NULL,       "osc_ck",       &osc_ck),
+        CLK(NULL,       "sys_ck",       &sys_ck),
+        CLK(NULL,       "alt_ck",       &alt_ck),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks),
         /* internal analog sources */
-        CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_242X),
-        CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_242X),
-        CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_242X),
+        CLK(NULL,       "dpll_ck",      &dpll_ck),
+        CLK(NULL,       "apll96_ck",    &apll96_ck),
+        CLK(NULL,       "apll54_ck",    &apll54_ck),
         /* internal prcm root sources */
-        CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_242X),
-        CLK(NULL,       "core_ck",      &core_ck,       CK_242X),
-        CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_242X),
-        CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_242X),
-        CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_242X),
-        CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_242X),
-        CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_242X),
-        CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src, CK_242X),
-        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_242X),
-        CLK(NULL,       "emul_ck",      &emul_ck,       CK_242X),
+        CLK(NULL,       "func_54m_ck",  &func_54m_ck),
+        CLK(NULL,       "core_ck",      &core_ck),
+        CLK(NULL,       "func_96m_ck",  &func_96m_ck),
+        CLK(NULL,       "func_48m_ck",  &func_48m_ck),
+        CLK(NULL,       "func_12m_ck",  &func_12m_ck),
+        CLK(NULL,       "sys_clkout_src", &sys_clkout_src),
+        CLK(NULL,       "sys_clkout",   &sys_clkout),
+        CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src),
+        CLK(NULL,       "sys_clkout2",  &sys_clkout2),
+        CLK(NULL,       "emul_ck",      &emul_ck),
         /* mpu domain clocks */
-        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_242X),
+        CLK(NULL,       "mpu_ck",       &mpu_ck),
         /* dsp domain clocks */
-        CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_242X),
-        CLK(NULL,       "dsp_ick",      &dsp_ick,       CK_242X),
-        CLK(NULL,       "iva1_ifck",    &iva1_ifck,     CK_242X),
-        CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
+        CLK(NULL,       "dsp_fck",      &dsp_fck),
+        CLK(NULL,       "dsp_ick",      &dsp_ick),
+        CLK(NULL,       "iva1_ifck",    &iva1_ifck),
+        CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck),
         /* GFX domain clocks */
-        CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_242X),
-        CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_242X),
-        CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_242X),
+        CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck),
+        CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck),
+        CLK(NULL,       "gfx_ick",      &gfx_ick),
         /* DSS domain clocks */
-        CLK("omapdss_dss",      "ick",          &dss_ick,       CK_242X),
-        CLK(NULL,       "dss_ick",              &dss_ick,       CK_242X),
-        CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_242X),
-        CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_242X),
-        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_242X),
+        CLK("omapdss_dss",      "ick",          &dss_ick),
+        CLK(NULL,       "dss_ick",              &dss_ick),
+        CLK(NULL,       "dss1_fck",             &dss1_fck),
+        CLK(NULL,       "dss2_fck",     &dss2_fck),
+        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck),
         /* L3 domain clocks */
-        CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_242X),
-        CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_242X),
-        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_242X),
+        CLK(NULL,       "core_l3_ck",   &core_l3_ck),
+        CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck),
+        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick),
         /* L4 domain clocks */
-        CLK(NULL,       "l4_ck",        &l4_ck,         CK_242X),
-        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_242X),
+        CLK(NULL,       "l4_ck",        &l4_ck),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick),
         /* virtual meta-group clock */
-        CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_242X),
+        CLK(NULL,       "virt_prcm_set", &virt_prcm_set),
         /* general l4 interface ck, multi-parent functional clk */
-        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_242X),
-        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_242X),
-        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_242X),
-        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_242X),
-        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_242X),
-        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_242X),
-        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_242X),
-        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_242X),
-        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_242X),
-        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_242X),
-        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_242X),
-        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_242X),
-        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_242X),
-        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_242X),
-        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_242X),
-        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_242X),
-        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_242X),
-        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_242X),
-        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_242X),
-        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_242X),
-        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_242X),
-        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_242X),
-        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_242X),
-        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_242X),
-        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_242X),
-        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_242X),
-        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_242X),
-        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_242X),
-        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick,    CK_242X),
-        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_242X),
-        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_242X),
-        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_242X),
-        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_242X),
-        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_242X),
-        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_242X),
-        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_242X),
-        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_242X),
-        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_242X),
-        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_242X),
-        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_242X),
-        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_242X),
-        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_242X),
-        CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_242X),
-        CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_242X),
-        CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_242X),
-        CLK(NULL,       "mpu_wdt_ick",          &mpu_wdt_ick,   CK_242X),
-        CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_242X),
-        CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_242X),
-        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_242X),
-        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_242X),
-        CLK("omap24xxcam", "fck",       &cam_fck,       CK_242X),
-        CLK(NULL,       "cam_fck",      &cam_fck,       CK_242X),
-        CLK("omap24xxcam", "ick",       &cam_ick,       CK_242X),
-        CLK(NULL,       "cam_ick",      &cam_ick,       CK_242X),
-        CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_242X),
-        CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_242X),
-        CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_242X),
-        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_242X),
-        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_242X),
-        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_242X),
-        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_242X),
-        CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
-        CLK(NULL,       "mmc_ick",      &mmc_ick,       CK_242X),
-        CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
-        CLK(NULL,       "mmc_fck",      &mmc_fck,       CK_242X),
-        CLK(NULL,       "fac_ick",      &fac_ick,       CK_242X),
-        CLK(NULL,       "fac_fck",      &fac_fck,       CK_242X),
-        CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
-        CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
-        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_242X),
-        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_242X),
-        CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_242X),
-        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_242X),
-        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_242X),
-        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_242X),
-        CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_242X),
-        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_242X),
-        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_242X),
-        CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_242X),
-        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_242X),
-        CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_242X),
-        CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_242X),
-        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_242X),
-        CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
-        CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
-        CLK(NULL,       "des_ick",      &des_ick,       CK_242X),
-        CLK("omap-sham",        "ick",  &sha_ick,       CK_242X),
-        CLK(NULL,       "sha_ick",      &sha_ick,       CK_242X),
-        CLK("omap_rng", "ick",          &rng_ick,       CK_242X),
-        CLK(NULL,       "rng_ick",              &rng_ick,       CK_242X),
-        CLK("omap-aes", "ick",  &aes_ick,       CK_242X),
-        CLK(NULL,       "aes_ick",      &aes_ick,       CK_242X),
-        CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),
-        CLK(NULL,       "usb_fck",      &usb_fck,       CK_242X),
-        CLK("musb-hdrc",        "fck",  &osc_ck,        CK_242X),
-        CLK(NULL,       "timer_32k_ck", &func_32k_ck,   CK_242X),
-        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_242X),
-        CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_242X),
-        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set, CK_242X),
+        CLK(NULL,       "gpt1_ick",     &gpt1_ick),
+        CLK(NULL,       "gpt1_fck",     &gpt1_fck),
+        CLK(NULL,       "gpt2_ick",     &gpt2_ick),
+        CLK(NULL,       "gpt2_fck",     &gpt2_fck),
+        CLK(NULL,       "gpt3_ick",     &gpt3_ick),
+        CLK(NULL,       "gpt3_fck",     &gpt3_fck),
+        CLK(NULL,       "gpt4_ick",     &gpt4_ick),
+        CLK(NULL,       "gpt4_fck",     &gpt4_fck),
+        CLK(NULL,       "gpt5_ick",     &gpt5_ick),
+        CLK(NULL,       "gpt5_fck",     &gpt5_fck),
+        CLK(NULL,       "gpt6_ick",     &gpt6_ick),
+        CLK(NULL,       "gpt6_fck",     &gpt6_fck),
+        CLK(NULL,       "gpt7_ick",     &gpt7_ick),
+        CLK(NULL,       "gpt7_fck",     &gpt7_fck),
+        CLK(NULL,       "gpt8_ick",     &gpt8_ick),
+        CLK(NULL,       "gpt8_fck",     &gpt8_fck),
+        CLK(NULL,       "gpt9_ick",     &gpt9_ick),
+        CLK(NULL,       "gpt9_fck",     &gpt9_fck),
+        CLK(NULL,       "gpt10_ick",    &gpt10_ick),
+        CLK(NULL,       "gpt10_fck",    &gpt10_fck),
+        CLK(NULL,       "gpt11_ick",    &gpt11_ick),
+        CLK(NULL,       "gpt11_fck",    &gpt11_fck),
+        CLK(NULL,       "gpt12_ick",    &gpt12_ick),
+        CLK(NULL,       "gpt12_fck",    &gpt12_fck),
+        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick),
+        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck),
+        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick),
+        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck),
+        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick),
+        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck),
+        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick),
+        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck),
+        CLK(NULL,       "uart1_ick",    &uart1_ick),
+        CLK(NULL,       "uart1_fck",    &uart1_fck),
+        CLK(NULL,       "uart2_ick",    &uart2_ick),
+        CLK(NULL,       "uart2_fck",    &uart2_fck),
+        CLK(NULL,       "uart3_ick",    &uart3_ick),
+        CLK(NULL,       "uart3_fck",    &uart3_fck),
+        CLK(NULL,       "gpios_ick",    &gpios_ick),
+        CLK(NULL,       "gpios_fck",    &gpios_fck),
+        CLK("omap_wdt", "ick",          &mpu_wdt_ick),
+        CLK(NULL,       "mpu_wdt_ick",          &mpu_wdt_ick),
+        CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck),
+        CLK(NULL,       "sync_32k_ick", &sync_32k_ick),
+        CLK(NULL,       "wdt1_ick",     &wdt1_ick),
+        CLK(NULL,       "omapctrl_ick", &omapctrl_ick),
+        CLK("omap24xxcam", "fck",       &cam_fck),
+        CLK(NULL,       "cam_fck",      &cam_fck),
+        CLK("omap24xxcam", "ick",       &cam_ick),
+        CLK(NULL,       "cam_ick",      &cam_ick),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick),
+        CLK(NULL,       "wdt4_ick",     &wdt4_ick),
+        CLK(NULL,       "wdt4_fck",     &wdt4_fck),
+        CLK(NULL,       "wdt3_ick",     &wdt3_ick),
+        CLK(NULL,       "wdt3_fck",     &wdt3_fck),
+        CLK(NULL,       "mspro_ick",    &mspro_ick),
+        CLK(NULL,       "mspro_fck",    &mspro_fck),
+        CLK("mmci-omap.0", "ick",       &mmc_ick),
+        CLK(NULL,       "mmc_ick",      &mmc_ick),
+        CLK("mmci-omap.0", "fck",       &mmc_fck),
+        CLK(NULL,       "mmc_fck",      &mmc_fck),
+        CLK(NULL,       "fac_ick",      &fac_ick),
+        CLK(NULL,       "fac_fck",      &fac_fck),
+        CLK(NULL,       "eac_ick",      &eac_ick),
+        CLK(NULL,       "eac_fck",      &eac_fck),
+        CLK("omap_hdq.0", "ick",        &hdq_ick),
+        CLK(NULL,       "hdq_ick",      &hdq_ick),
+        CLK("omap_hdq.0", "fck",        &hdq_fck),
+        CLK(NULL,       "hdq_fck",      &hdq_fck),
+        CLK("omap_i2c.1", "ick",        &i2c1_ick),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick),
+        CLK(NULL,       "i2c1_fck",     &i2c1_fck),
+        CLK("omap_i2c.2", "ick",        &i2c2_ick),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick),
+        CLK(NULL,       "i2c2_fck",     &i2c2_fck),
+        CLK(NULL,       "gpmc_fck",     &gpmc_fck),
+        CLK(NULL,       "sdma_fck",     &sdma_fck),
+        CLK(NULL,       "sdma_ick",     &sdma_ick),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick),
+        CLK(NULL,       "vlynq_ick",    &vlynq_ick),
+        CLK(NULL,       "vlynq_fck",    &vlynq_fck),
+        CLK(NULL,       "des_ick",      &des_ick),
+        CLK("omap-sham",        "ick",  &sha_ick),
+        CLK(NULL,       "sha_ick",      &sha_ick),
+        CLK("omap_rng", "ick",          &rng_ick),
+        CLK(NULL,       "rng_ick",              &rng_ick),
+        CLK("omap-aes", "ick",  &aes_ick),
+        CLK(NULL,       "aes_ick",      &aes_ick),
+        CLK(NULL,       "pka_ick",      &pka_ick),
+        CLK(NULL,       "usb_fck",      &usb_fck),
+        CLK("musb-hdrc",        "fck",  &osc_ck),
+        CLK(NULL,       "timer_32k_ck", &func_32k_ck),
+        CLK(NULL,       "timer_sys_ck", &sys_ck),
+        CLK(NULL,       "timer_ext_ck", &alt_ck),
+        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set),
 };
 
 
@@ -1904,8 +1904,6 @@ static const char *enable_init_clks[] = {
 
 int __init omap2420_clk_init(void)
 {
-        struct omap_clk *c;
-
         prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
         cpu_mask = RATE_IN_242X;
         rate_table = omap2420_rate_table;
@@ -1914,12 +1912,7 @@ int __init omap2420_clk_init(void)
 
         omap2xxx_clkt_vps_check_bootloader_rates();
 
-        for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
-             c++) {
-                clkdev_add(&c->lk);
-                if (!__clk_init(NULL, c->lk.clk))
-                        omap2_init_clk_hw_omap_clocks(c->lk.clk);
-        }
+        omap_clocks_register(omap2420_clks, ARRAY_SIZE(omap2420_clks));
 
         omap2xxx_clkt_vps_late_init();
 
diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c
index aed8f74ca076..5e4b037bb24c 100644
--- a/arch/arm/mach-omap2/cclock2430_data.c
+++ b/arch/arm/mach-omap2/cclock2430_data.c
@@ -1840,168 +1840,170 @@ DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
 
 static struct omap_clk omap2430_clks[] = {
         /* external root sources */
-        CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_243X),
-        CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_243X),
-        CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X),
-        CLK("twl",      "fck",          &osc_ck,        CK_243X),
-        CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X),
-        CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X),
-        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_243X),
+        CLK(NULL,       "func_32k_ck",  &func_32k_ck),
+        CLK(NULL,       "secure_32k_ck", &secure_32k_ck),
+        CLK(NULL,       "osc_ck",       &osc_ck),
+        CLK("twl",      "fck",          &osc_ck),
+        CLK(NULL,       "sys_ck",       &sys_ck),
+        CLK(NULL,       "alt_ck",       &alt_ck),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks),
         /* internal analog sources */
-        CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X),
-        CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_243X),
-        CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_243X),
+        CLK(NULL,       "dpll_ck",      &dpll_ck),
+        CLK(NULL,       "apll96_ck",    &apll96_ck),
+        CLK(NULL,       "apll54_ck",    &apll54_ck),
         /* internal prcm root sources */
-        CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X),
-        CLK(NULL,       "core_ck",      &core_ck,       CK_243X),
-        CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X),
-        CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X),
-        CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X),
-        CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_243X),
-        CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_243X),
-        CLK(NULL,       "emul_ck",      &emul_ck,       CK_243X),
+        CLK(NULL,       "func_54m_ck",  &func_54m_ck),
+        CLK(NULL,       "core_ck",      &core_ck),
+        CLK(NULL,       "func_96m_ck",  &func_96m_ck),
+        CLK(NULL,       "func_48m_ck",  &func_48m_ck),
+        CLK(NULL,       "func_12m_ck",  &func_12m_ck),
+        CLK(NULL,       "sys_clkout_src", &sys_clkout_src),
+        CLK(NULL,       "sys_clkout",   &sys_clkout),
+        CLK(NULL,       "emul_ck",      &emul_ck),
         /* mpu domain clocks */
-        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_243X),
+        CLK(NULL,       "mpu_ck",       &mpu_ck),
         /* dsp domain clocks */
-        CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_243X),
-        CLK(NULL,       "iva2_1_ick",   &iva2_1_ick,    CK_243X),
+        CLK(NULL,       "dsp_fck",      &dsp_fck),
+        CLK(NULL,       "iva2_1_ick",   &iva2_1_ick),
         /* GFX domain clocks */
-        CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_243X),
-        CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_243X),
-        CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_243X),
+        CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck),
+        CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck),
+        CLK(NULL,       "gfx_ick",      &gfx_ick),
         /* Modem domain clocks */
-        CLK(NULL,       "mdm_ick",      &mdm_ick,       CK_243X),
-        CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
+        CLK(NULL,       "mdm_ick",      &mdm_ick),
+        CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck),
         /* DSS domain clocks */
-        CLK("omapdss_dss",      "ick",          &dss_ick,       CK_243X),
-        CLK(NULL,       "dss_ick",              &dss_ick,       CK_243X),
-        CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_243X),
-        CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_243X),
-        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_243X),
+        CLK("omapdss_dss",      "ick",          &dss_ick),
+        CLK(NULL,       "dss_ick",              &dss_ick),
+        CLK(NULL,       "dss1_fck",             &dss1_fck),
+        CLK(NULL,       "dss2_fck",     &dss2_fck),
+        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck),
         /* L3 domain clocks */
-        CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_243X),
-        CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_243X),
-        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_243X),
+        CLK(NULL,       "core_l3_ck",   &core_l3_ck),
+        CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck),
+        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick),
         /* L4 domain clocks */
-        CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X),
-        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X),
+        CLK(NULL,       "l4_ck",        &l4_ck),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick),
         /* virtual meta-group clock */
-        CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X),
+        CLK(NULL,       "virt_prcm_set", &virt_prcm_set),
         /* general l4 interface ck, multi-parent functional clk */
-        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_243X),
-        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_243X),
-        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_243X),
-        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_243X),
-        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_243X),
-        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_243X),
-        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_243X),
-        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_243X),
-        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_243X),
-        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_243X),
-        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_243X),
-        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_243X),
-        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_243X),
-        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_243X),
-        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_243X),
-        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_243X),
-        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_243X),
-        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_243X),
-        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_243X),
-        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_243X),
-        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_243X),
-        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_243X),
-        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X),
-        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X),
-        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X),
-        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_243X),
-        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_243X),
-        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X),
-        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick,    CK_243X),
-        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_243X),
-        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
-        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick,    CK_243X),
-        CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_243X),
-        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
-        CLK(NULL,       "mcbsp4_ick",   &mcbsp4_ick,    CK_243X),
-        CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_243X),
-        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
-        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick,    CK_243X),
-        CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_243X),
-        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X),
-        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_243X),
-        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_243X),
-        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X),
-        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_243X),
-        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_243X),
-        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
-        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick,    CK_243X),
-        CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_243X),
-        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X),
-        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X),
-        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_243X),
-        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_243X),
-        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_243X),
-        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_243X),
-        CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X),
-        CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X),
-        CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X),
-        CLK(NULL,       "mpu_wdt_ick",  &mpu_wdt_ick,   CK_243X),
-        CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_243X),
-        CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X),
-        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X),
-        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X),
-        CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
-        CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X),
-        CLK(NULL,       "cam_fck",      &cam_fck,       CK_243X),
-        CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X),
-        CLK(NULL,       "cam_ick",      &cam_ick,       CK_243X),
-        CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X),
-        CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X),
-        CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X),
-        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_243X),
-        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_243X),
-        CLK(NULL,       "fac_ick",      &fac_ick,       CK_243X),
-        CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X),
-        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X),
-        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_243X),
-        CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X),
-        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_243X),
-        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_243X),
-        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_243X),
-        CLK(NULL,       "i2chs1_fck",   &i2chs1_fck,    CK_243X),
-        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_243X),
-        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_243X),
-        CLK(NULL,       "i2chs2_fck",   &i2chs2_fck,    CK_243X),
-        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X),
-        CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X),
-        CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_243X),
-        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_243X),
-        CLK(NULL,       "des_ick",      &des_ick,       CK_243X),
-        CLK("omap-sham",        "ick",  &sha_ick,       CK_243X),
-        CLK("omap_rng", "ick",          &rng_ick,       CK_243X),
-        CLK(NULL,       "rng_ick",      &rng_ick,       CK_243X),
-        CLK("omap-aes", "ick",  &aes_ick,       CK_243X),
-        CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X),
-        CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X),
-        CLK("musb-omap2430",    "ick",  &usbhs_ick,     CK_243X),
-        CLK(NULL,       "usbhs_ick",    &usbhs_ick,     CK_243X),
-        CLK("omap_hsmmc.0", "ick",      &mmchs1_ick,    CK_243X),
-        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick,    CK_243X),
-        CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_243X),
-        CLK("omap_hsmmc.1", "ick",      &mmchs2_ick,    CK_243X),
-        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick,    CK_243X),
-        CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_243X),
-        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
-        CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
-        CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
-        CLK("omap_hsmmc.0", "mmchsdb_fck",      &mmchsdb1_fck,  CK_243X),
-        CLK(NULL,        "mmchsdb1_fck",        &mmchsdb1_fck,  CK_243X),
-        CLK("omap_hsmmc.1", "mmchsdb_fck",      &mmchsdb2_fck,  CK_243X),
-        CLK(NULL,        "mmchsdb2_fck",        &mmchsdb2_fck,  CK_243X),
-        CLK(NULL,       "timer_32k_ck",  &func_32k_ck,   CK_243X),
-        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_243X),
-        CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_243X),
-        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set, CK_243X),
+        CLK(NULL,       "gpt1_ick",     &gpt1_ick),
+        CLK(NULL,       "gpt1_fck",     &gpt1_fck),
+        CLK(NULL,       "gpt2_ick",     &gpt2_ick),
+        CLK(NULL,       "gpt2_fck",     &gpt2_fck),
+        CLK(NULL,       "gpt3_ick",     &gpt3_ick),
+        CLK(NULL,       "gpt3_fck",     &gpt3_fck),
+        CLK(NULL,       "gpt4_ick",     &gpt4_ick),
+        CLK(NULL,       "gpt4_fck",     &gpt4_fck),
+        CLK(NULL,       "gpt5_ick",     &gpt5_ick),
+        CLK(NULL,       "gpt5_fck",     &gpt5_fck),
+        CLK(NULL,       "gpt6_ick",     &gpt6_ick),
+        CLK(NULL,       "gpt6_fck",     &gpt6_fck),
+        CLK(NULL,       "gpt7_ick",     &gpt7_ick),
+        CLK(NULL,       "gpt7_fck",     &gpt7_fck),
+        CLK(NULL,       "gpt8_ick",     &gpt8_ick),
+        CLK(NULL,       "gpt8_fck",     &gpt8_fck),
+        CLK(NULL,       "gpt9_ick",     &gpt9_ick),
+        CLK(NULL,       "gpt9_fck",     &gpt9_fck),
+        CLK(NULL,       "gpt10_ick",    &gpt10_ick),
+        CLK(NULL,       "gpt10_fck",    &gpt10_fck),
+        CLK(NULL,       "gpt11_ick",    &gpt11_ick),
+        CLK(NULL,       "gpt11_fck",    &gpt11_fck),
+        CLK(NULL,       "gpt12_ick",    &gpt12_ick),
+        CLK(NULL,       "gpt12_fck",    &gpt12_fck),
+        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick),
+        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck),
+        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick),
+        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck),
+        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick),
+        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick),
+        CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck),
+        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick),
+        CLK(NULL,       "mcbsp4_ick",   &mcbsp4_ick),
+        CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck),
+        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick),
+        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick),
+        CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck),
+        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick),
+        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck),
+        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick),
+        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck),
+        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick),
+        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick),
+        CLK(NULL,       "mcspi3_fck",   &mcspi3_fck),
+        CLK(NULL,       "uart1_ick",    &uart1_ick),
+        CLK(NULL,       "uart1_fck",    &uart1_fck),
+        CLK(NULL,       "uart2_ick",    &uart2_ick),
+        CLK(NULL,       "uart2_fck",    &uart2_fck),
+        CLK(NULL,       "uart3_ick",    &uart3_ick),
+        CLK(NULL,       "uart3_fck",    &uart3_fck),
+        CLK(NULL,       "gpios_ick",    &gpios_ick),
+        CLK(NULL,       "gpios_fck",    &gpios_fck),
+        CLK("omap_wdt", "ick",          &mpu_wdt_ick),
+        CLK(NULL,       "mpu_wdt_ick",  &mpu_wdt_ick),
+        CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck),
+        CLK(NULL,       "sync_32k_ick", &sync_32k_ick),
+        CLK(NULL,       "wdt1_ick",     &wdt1_ick),
+        CLK(NULL,       "omapctrl_ick", &omapctrl_ick),
+        CLK(NULL,       "icr_ick",      &icr_ick),
+        CLK("omap24xxcam", "fck",       &cam_fck),
+        CLK(NULL,       "cam_fck",      &cam_fck),
+        CLK("omap24xxcam", "ick",       &cam_ick),
+        CLK(NULL,       "cam_ick",      &cam_ick),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick),
+        CLK(NULL,       "wdt4_ick",     &wdt4_ick),
+        CLK(NULL,       "wdt4_fck",     &wdt4_fck),
+        CLK(NULL,       "mspro_ick",    &mspro_ick),
+        CLK(NULL,       "mspro_fck",    &mspro_fck),
+        CLK(NULL,       "fac_ick",      &fac_ick),
+        CLK(NULL,       "fac_fck",      &fac_fck),
+        CLK("omap_hdq.0", "ick",        &hdq_ick),
+        CLK(NULL,       "hdq_ick",      &hdq_ick),
+        CLK("omap_hdq.1", "fck",        &hdq_fck),
+        CLK(NULL,       "hdq_fck",      &hdq_fck),
+        CLK("omap_i2c.1", "ick",        &i2c1_ick),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick),
+        CLK(NULL,       "i2chs1_fck",   &i2chs1_fck),
+        CLK("omap_i2c.2", "ick",        &i2c2_ick),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick),
+        CLK(NULL,       "i2chs2_fck",   &i2chs2_fck),
+        CLK(NULL,       "gpmc_fck",     &gpmc_fck),
+        CLK(NULL,       "sdma_fck",     &sdma_fck),
+        CLK(NULL,       "sdma_ick",     &sdma_ick),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick),
+        CLK(NULL,       "des_ick",      &des_ick),
+        CLK("omap-sham",        "ick",  &sha_ick),
+        CLK(NULL,       "sha_ick",      &sha_ick),
+        CLK("omap_rng", "ick",          &rng_ick),
+        CLK(NULL,       "rng_ick",      &rng_ick),
+        CLK("omap-aes", "ick",  &aes_ick),
+        CLK(NULL,       "aes_ick",      &aes_ick),
+        CLK(NULL,       "pka_ick",      &pka_ick),
+        CLK(NULL,       "usb_fck",      &usb_fck),
+        CLK("musb-omap2430",    "ick",  &usbhs_ick),
+        CLK(NULL,       "usbhs_ick",    &usbhs_ick),
+        CLK("omap_hsmmc.0", "ick",      &mmchs1_ick),
+        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick),
+        CLK(NULL,       "mmchs1_fck",   &mmchs1_fck),
+        CLK("omap_hsmmc.1", "ick",      &mmchs2_ick),
+        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick),
+        CLK(NULL,       "mmchs2_fck",   &mmchs2_fck),
+        CLK(NULL,       "gpio5_ick",    &gpio5_ick),
+        CLK(NULL,       "gpio5_fck",    &gpio5_fck),
+        CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick),
+        CLK("omap_hsmmc.0", "mmchsdb_fck",      &mmchsdb1_fck),
+        CLK(NULL,        "mmchsdb1_fck",        &mmchsdb1_fck),
+        CLK("omap_hsmmc.1", "mmchsdb_fck",      &mmchsdb2_fck),
+        CLK(NULL,        "mmchsdb2_fck",        &mmchsdb2_fck),
+        CLK(NULL,       "timer_32k_ck",  &func_32k_ck),
+        CLK(NULL,       "timer_sys_ck", &sys_ck),
+        CLK(NULL,       "timer_ext_ck", &alt_ck),
+        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set),
 };
 
 static const char *enable_init_clks[] = {
@@ -2019,8 +2021,6 @@ static const char *enable_init_clks[] = {
 
 int __init omap2430_clk_init(void)
 {
-        struct omap_clk *c;
-
         prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
         cpu_mask = RATE_IN_243X;
         rate_table = omap2430_rate_table;
@@ -2029,12 +2029,7 @@ int __init omap2430_clk_init(void)
 
         omap2xxx_clkt_vps_check_bootloader_rates();
 
-        for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
-             c++) {
-                clkdev_add(&c->lk);
-                if (!__clk_init(NULL, c->lk.clk))
-                        omap2_init_clk_hw_omap_clocks(c->lk.clk);
-        }
+        omap_clocks_register(omap2430_clks, ARRAY_SIZE(omap2430_clks));
 
         omap2xxx_clkt_vps_late_init();
 
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index 476b82066cb6..6ebc7803bc3e 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -413,6 +413,14 @@ static struct clk smartreflex1_fck;
 DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
 DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
 
+static struct clk sha0_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
+DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
+
+static struct clk aes0_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
+DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
+
 /*
  * Modules clock nodes
  *
@@ -838,80 +846,82 @@ DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
  * clkdev
  */
 static struct omap_clk am33xx_clks[] = {
-        CLK(NULL,       "clk_32768_ck",         &clk_32768_ck,  CK_AM33XX),
-        CLK(NULL,       "clk_rc32k_ck",         &clk_rc32k_ck,  CK_AM33XX),
-        CLK(NULL,       "virt_19200000_ck",     &virt_19200000_ck,      CK_AM33XX),
-        CLK(NULL,       "virt_24000000_ck",     &virt_24000000_ck,      CK_AM33XX),
-        CLK(NULL,       "virt_25000000_ck",     &virt_25000000_ck,      CK_AM33XX),
-        CLK(NULL,       "virt_26000000_ck",     &virt_26000000_ck,      CK_AM33XX),
-        CLK(NULL,       "sys_clkin_ck",         &sys_clkin_ck,  CK_AM33XX),
-        CLK(NULL,       "tclkin_ck",            &tclkin_ck,     CK_AM33XX),
-        CLK(NULL,       "dpll_core_ck",         &dpll_core_ck,  CK_AM33XX),
-        CLK(NULL,       "dpll_core_x2_ck",      &dpll_core_x2_ck,       CK_AM33XX),
-        CLK(NULL,       "dpll_core_m4_ck",      &dpll_core_m4_ck,       CK_AM33XX),
-        CLK(NULL,       "dpll_core_m5_ck",      &dpll_core_m5_ck,       CK_AM33XX),
-        CLK(NULL,       "dpll_core_m6_ck",      &dpll_core_m6_ck,       CK_AM33XX),
-        CLK(NULL,       "dpll_mpu_ck",          &dpll_mpu_ck,   CK_AM33XX),
-        CLK("cpu0",     NULL,                   &dpll_mpu_ck,   CK_AM33XX),
-        CLK(NULL,       "dpll_mpu_m2_ck",       &dpll_mpu_m2_ck,        CK_AM33XX),
-        CLK(NULL,       "dpll_ddr_ck",          &dpll_ddr_ck,   CK_AM33XX),
-        CLK(NULL,       "dpll_ddr_m2_ck",       &dpll_ddr_m2_ck,        CK_AM33XX),
-        CLK(NULL,       "dpll_ddr_m2_div2_ck",  &dpll_ddr_m2_div2_ck,   CK_AM33XX),
-        CLK(NULL,       "dpll_disp_ck",         &dpll_disp_ck,  CK_AM33XX),
-        CLK(NULL,       "dpll_disp_m2_ck",      &dpll_disp_m2_ck,       CK_AM33XX),
-        CLK(NULL,       "dpll_per_ck",          &dpll_per_ck,   CK_AM33XX),
-        CLK(NULL,       "dpll_per_m2_ck",       &dpll_per_m2_ck,        CK_AM33XX),
-        CLK(NULL,       "dpll_per_m2_div4_wkupdm_ck",   &dpll_per_m2_div4_wkupdm_ck,    CK_AM33XX),
-        CLK(NULL,       "dpll_per_m2_div4_ck",  &dpll_per_m2_div4_ck,   CK_AM33XX),
-        CLK(NULL,       "adc_tsc_fck",          &adc_tsc_fck,   CK_AM33XX),
-        CLK(NULL,       "cefuse_fck",           &cefuse_fck,    CK_AM33XX),
-        CLK(NULL,       "clkdiv32k_ck",         &clkdiv32k_ck,  CK_AM33XX),
-        CLK(NULL,       "clkdiv32k_ick",        &clkdiv32k_ick, CK_AM33XX),
-        CLK(NULL,       "dcan0_fck",            &dcan0_fck,     CK_AM33XX),
-        CLK("481cc000.d_can",   NULL,           &dcan0_fck,     CK_AM33XX),
-        CLK(NULL,       "dcan1_fck",            &dcan1_fck,     CK_AM33XX),
-        CLK("481d0000.d_can",   NULL,           &dcan1_fck,     CK_AM33XX),
-        CLK(NULL,       "debugss_ick",          &debugss_ick,   CK_AM33XX),
-        CLK(NULL,       "pruss_ocp_gclk",       &pruss_ocp_gclk,        CK_AM33XX),
-        CLK(NULL,       "mcasp0_fck",           &mcasp0_fck,    CK_AM33XX),
-        CLK(NULL,       "mcasp1_fck",           &mcasp1_fck,    CK_AM33XX),
-        CLK(NULL,       "mmu_fck",              &mmu_fck,       CK_AM33XX),
-        CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck,      CK_AM33XX),
-        CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck,      CK_AM33XX),
-        CLK(NULL,       "timer1_fck",           &timer1_fck,    CK_AM33XX),
-        CLK(NULL,       "timer2_fck",           &timer2_fck,    CK_AM33XX),
-        CLK(NULL,       "timer3_fck",           &timer3_fck,    CK_AM33XX),
-        CLK(NULL,       "timer4_fck",           &timer4_fck,    CK_AM33XX),
-        CLK(NULL,       "timer5_fck",           &timer5_fck,    CK_AM33XX),
-        CLK(NULL,       "timer6_fck",           &timer6_fck,    CK_AM33XX),
-        CLK(NULL,       "timer7_fck",           &timer7_fck,    CK_AM33XX),
-        CLK(NULL,       "usbotg_fck",           &usbotg_fck,    CK_AM33XX),
-        CLK(NULL,       "ieee5000_fck",         &ieee5000_fck,  CK_AM33XX),
-        CLK(NULL,       "wdt1_fck",             &wdt1_fck,      CK_AM33XX),
-        CLK(NULL,       "l4_rtc_gclk",          &l4_rtc_gclk,   CK_AM33XX),
-        CLK(NULL,       "l3_gclk",              &l3_gclk,       CK_AM33XX),
-        CLK(NULL,       "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,  CK_AM33XX),
-        CLK(NULL,       "l4hs_gclk",            &l4hs_gclk,     CK_AM33XX),
-        CLK(NULL,       "l3s_gclk",             &l3s_gclk,      CK_AM33XX),
-        CLK(NULL,       "l4fw_gclk",            &l4fw_gclk,     CK_AM33XX),
-        CLK(NULL,       "l4ls_gclk",            &l4ls_gclk,     CK_AM33XX),
-        CLK(NULL,       "clk_24mhz",            &clk_24mhz,     CK_AM33XX),
-        CLK(NULL,       "sysclk_div_ck",        &sysclk_div_ck, CK_AM33XX),
-        CLK(NULL,       "cpsw_125mhz_gclk",     &cpsw_125mhz_gclk,      CK_AM33XX),
-        CLK(NULL,       "cpsw_cpts_rft_clk",    &cpsw_cpts_rft_clk,     CK_AM33XX),
-        CLK(NULL,       "gpio0_dbclk_mux_ck",   &gpio0_dbclk_mux_ck,    CK_AM33XX),
-        CLK(NULL,       "gpio0_dbclk",          &gpio0_dbclk,   CK_AM33XX),
-        CLK(NULL,       "gpio1_dbclk",          &gpio1_dbclk,   CK_AM33XX),
-        CLK(NULL,       "gpio2_dbclk",          &gpio2_dbclk,   CK_AM33XX),
-        CLK(NULL,       "gpio3_dbclk",          &gpio3_dbclk,   CK_AM33XX),
-        CLK(NULL,       "lcd_gclk",             &lcd_gclk,      CK_AM33XX),
-        CLK(NULL,       "mmc_clk",              &mmc_clk,       CK_AM33XX),
-        CLK(NULL,       "gfx_fclk_clksel_ck",   &gfx_fclk_clksel_ck,    CK_AM33XX),
-        CLK(NULL,       "gfx_fck_div_ck",       &gfx_fck_div_ck,        CK_AM33XX),
-        CLK(NULL,       "sysclkout_pre_ck",     &sysclkout_pre_ck,      CK_AM33XX),
-        CLK(NULL,       "clkout2_div_ck",       &clkout2_div_ck,        CK_AM33XX),
-        CLK(NULL,       "timer_32k_ck",         &clkdiv32k_ick, CK_AM33XX),
-        CLK(NULL,       "timer_sys_ck",         &sys_clkin_ck,  CK_AM33XX),
+        CLK(NULL,       "clk_32768_ck",         &clk_32768_ck),
+        CLK(NULL,       "clk_rc32k_ck",         &clk_rc32k_ck),
+        CLK(NULL,       "virt_19200000_ck",     &virt_19200000_ck),
+        CLK(NULL,       "virt_24000000_ck",     &virt_24000000_ck),
+        CLK(NULL,       "virt_25000000_ck",     &virt_25000000_ck),
+        CLK(NULL,       "virt_26000000_ck",     &virt_26000000_ck),
+        CLK(NULL,       "sys_clkin_ck",         &sys_clkin_ck),
+        CLK(NULL,       "tclkin_ck",            &tclkin_ck),
+        CLK(NULL,       "dpll_core_ck",         &dpll_core_ck),
+        CLK(NULL,       "dpll_core_x2_ck",      &dpll_core_x2_ck),
+        CLK(NULL,       "dpll_core_m4_ck",      &dpll_core_m4_ck),
+        CLK(NULL,       "dpll_core_m5_ck",      &dpll_core_m5_ck),
+        CLK(NULL,       "dpll_core_m6_ck",      &dpll_core_m6_ck),
+        CLK(NULL,       "dpll_mpu_ck",          &dpll_mpu_ck),
+        CLK("cpu0",     NULL,                   &dpll_mpu_ck),
+        CLK(NULL,       "dpll_mpu_m2_ck",       &dpll_mpu_m2_ck),
+        CLK(NULL,       "dpll_ddr_ck",          &dpll_ddr_ck),
+        CLK(NULL,       "dpll_ddr_m2_ck",       &dpll_ddr_m2_ck),
+        CLK(NULL,       "dpll_ddr_m2_div2_ck",  &dpll_ddr_m2_div2_ck),
+        CLK(NULL,       "dpll_disp_ck",         &dpll_disp_ck),
+        CLK(NULL,       "dpll_disp_m2_ck",      &dpll_disp_m2_ck),
+        CLK(NULL,       "dpll_per_ck",          &dpll_per_ck),
+        CLK(NULL,       "dpll_per_m2_ck",       &dpll_per_m2_ck),
+        CLK(NULL,       "dpll_per_m2_div4_wkupdm_ck",   &dpll_per_m2_div4_wkupdm_ck),
+        CLK(NULL,       "dpll_per_m2_div4_ck",  &dpll_per_m2_div4_ck),
+        CLK(NULL,       "adc_tsc_fck",          &adc_tsc_fck),
+        CLK(NULL,       "cefuse_fck",           &cefuse_fck),
+        CLK(NULL,       "clkdiv32k_ck",         &clkdiv32k_ck),
+        CLK(NULL,       "clkdiv32k_ick",        &clkdiv32k_ick),
+        CLK(NULL,       "dcan0_fck",            &dcan0_fck),
+        CLK("481cc000.d_can",   NULL,           &dcan0_fck),
+        CLK(NULL,       "dcan1_fck",            &dcan1_fck),
+        CLK("481d0000.d_can",   NULL,           &dcan1_fck),
+        CLK(NULL,       "debugss_ick",          &debugss_ick),
+        CLK(NULL,       "pruss_ocp_gclk",       &pruss_ocp_gclk),
+        CLK(NULL,       "mcasp0_fck",           &mcasp0_fck),
+        CLK(NULL,       "mcasp1_fck",           &mcasp1_fck),
+        CLK(NULL,       "mmu_fck",              &mmu_fck),
+        CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck),
+        CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck),
+        CLK(NULL,       "sha0_fck",             &sha0_fck),
+        CLK(NULL,       "aes0_fck",             &aes0_fck),
+        CLK(NULL,       "timer1_fck",           &timer1_fck),
+        CLK(NULL,       "timer2_fck",           &timer2_fck),
+        CLK(NULL,       "timer3_fck",           &timer3_fck),
+        CLK(NULL,       "timer4_fck",           &timer4_fck),
+        CLK(NULL,       "timer5_fck",           &timer5_fck),
+        CLK(NULL,       "timer6_fck",           &timer6_fck),
+        CLK(NULL,       "timer7_fck",           &timer7_fck),
+        CLK(NULL,       "usbotg_fck",           &usbotg_fck),
+        CLK(NULL,       "ieee5000_fck",         &ieee5000_fck),
+        CLK(NULL,       "wdt1_fck",             &wdt1_fck),
+        CLK(NULL,       "l4_rtc_gclk",          &l4_rtc_gclk),
+        CLK(NULL,       "l3_gclk",              &l3_gclk),
+        CLK(NULL,       "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck),
+        CLK(NULL,       "l4hs_gclk",            &l4hs_gclk),
+        CLK(NULL,       "l3s_gclk",             &l3s_gclk),
+        CLK(NULL,       "l4fw_gclk",            &l4fw_gclk),
+        CLK(NULL,       "l4ls_gclk",            &l4ls_gclk),
+        CLK(NULL,       "clk_24mhz",            &clk_24mhz),
+        CLK(NULL,       "sysclk_div_ck",        &sysclk_div_ck),
+        CLK(NULL,       "cpsw_125mhz_gclk",     &cpsw_125mhz_gclk),
+        CLK(NULL,       "cpsw_cpts_rft_clk",    &cpsw_cpts_rft_clk),
+        CLK(NULL,       "gpio0_dbclk_mux_ck",   &gpio0_dbclk_mux_ck),
+        CLK(NULL,       "gpio0_dbclk",          &gpio0_dbclk),
+        CLK(NULL,       "gpio1_dbclk",          &gpio1_dbclk),
+        CLK(NULL,       "gpio2_dbclk",          &gpio2_dbclk),
+        CLK(NULL,       "gpio3_dbclk",          &gpio3_dbclk),
+        CLK(NULL,       "lcd_gclk",             &lcd_gclk),
+        CLK(NULL,       "mmc_clk",              &mmc_clk),
+        CLK(NULL,       "gfx_fclk_clksel_ck",   &gfx_fclk_clksel_ck),
+        CLK(NULL,       "gfx_fck_div_ck",       &gfx_fck_div_ck),
+        CLK(NULL,       "sysclkout_pre_ck",     &sysclkout_pre_ck),
+        CLK(NULL,       "clkout2_div_ck",       &clkout2_div_ck),
+        CLK(NULL,       "timer_32k_ck",         &clkdiv32k_ick),
+        CLK(NULL,       "timer_sys_ck",         &sys_clkin_ck),
 };
 
 
@@ -926,21 +936,10 @@ static const char *enable_init_clks[] = {
 
 int __init am33xx_clk_init(void)
 {
-        struct omap_clk *c;
-        u32 cpu_clkflg;
-
-        if (soc_is_am33xx()) {
+        if (soc_is_am33xx())
                 cpu_mask = RATE_IN_AM33XX;
-                cpu_clkflg = CK_AM33XX;
-        }
 
-        for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) {
-                if (c->cpu & cpu_clkflg) {
-                        clkdev_add(&c->lk);
-                        if (!__clk_init(NULL, c->lk.clk))
-                                omap2_init_clk_hw_omap_clocks(c->lk.clk);
-                }
-        }
+        omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
 
         omap2_clk_disable_autoidle_all();
 
@@ -958,6 +957,14 @@ int __init am33xx_clk_init(void)
 
         clk_set_parent(&timer3_fck, &sys_clkin_ck);
         clk_set_parent(&timer6_fck, &sys_clkin_ck);
+        /*
+         * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
+         * the design/spec, so as a result, for example, timer which supposed
+         * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
+         * not expected by any use-case, so change WDT1 clock source to PRCM
+         * 32KHz clock.
+         */
+        clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 4579c3c5338f..45cd26430d1f 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -3219,289 +3219,327 @@ static struct clk_hw_omap wdt3_ick_hw = {
 DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
 
 /*
- * clkdev
+ * clocks specific to omap3430es1
+ */
+static struct omap_clk omap3430es1_clks[] = {
+        CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck),
+        CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck),
+        CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick),
+        CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck),
+        CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck),
+        CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck),
+        CLK(NULL,       "fshostusb_fck", &fshostusb_fck),
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1),
+        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1),
+        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es1),
+        CLK(NULL,       "fac_ick",      &fac_ick),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1),
+        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick),
+        CLK(NULL,       "dss1_alwon_fck",       &dss1_alwon_fck_3430es1),
+        CLK("omapdss_dss",      "ick",          &dss_ick_3430es1),
+        CLK(NULL,       "dss_ick",              &dss_ick_3430es1),
+};
+
+/*
+ * clocks specific to am35xx
+ */
+static struct omap_clk am35xx_clks[] = {
+        CLK(NULL,       "ipss_ick",     &ipss_ick),
+        CLK(NULL,       "rmii_ck",      &rmii_ck),
+        CLK(NULL,       "pclk_ck",      &pclk_ck),
+        CLK(NULL,       "emac_ick",     &emac_ick),
+        CLK(NULL,       "emac_fck",     &emac_fck),
+        CLK("davinci_emac.0",   NULL,   &emac_ick),
+        CLK("davinci_mdio.0",   NULL,   &emac_fck),
+        CLK("vpfe-capture",     "master",       &vpfe_ick),
+        CLK("vpfe-capture",     "slave",        &vpfe_fck),
+        CLK(NULL,       "hsotgusb_ick",         &hsotgusb_ick_am35xx),
+        CLK(NULL,       "hsotgusb_fck",         &hsotgusb_fck_am35xx),
+        CLK(NULL,       "hecc_ck",      &hecc_ck),
+        CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx),
+        CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx),
+};
+
+/*
+ * clocks specific to omap36xx
+ */
+static struct omap_clk omap36xx_clks[] = {
+        CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck),
+        CLK(NULL,       "uart4_fck",    &uart4_fck),
+};
+
+/*
+ * clocks common to omap36xx omap34xx
+ */
+static struct omap_clk omap34xx_omap36xx_clks[] = {
+        CLK(NULL,       "aes1_ick",     &aes1_ick),
+        CLK("omap_rng", "ick",          &rng_ick),
+        CLK(NULL,       "sha11_ick",    &sha11_ick),
+        CLK(NULL,       "des1_ick",     &des1_ick),
+        CLK(NULL,       "cam_mclk",     &cam_mclk),
+        CLK(NULL,       "cam_ick",      &cam_ick),
+        CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck),
+        CLK(NULL,       "security_l3_ick", &security_l3_ick),
+        CLK(NULL,       "pka_ick",      &pka_ick),
+        CLK(NULL,       "icr_ick",      &icr_ick),
+        CLK("omap-aes", "ick",  &aes2_ick),
+        CLK("omap-sham",        "ick",  &sha12_ick),
+        CLK(NULL,       "des2_ick",     &des2_ick),
+        CLK(NULL,       "mspro_ick",    &mspro_ick),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick),
+        CLK(NULL,       "sr1_fck",      &sr1_fck),
+        CLK(NULL,       "sr2_fck",      &sr2_fck),
+        CLK(NULL,       "sr_l4_ick",    &sr_l4_ick),
+        CLK(NULL,       "security_l4_ick2", &security_l4_ick2),
+        CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick),
+        CLK(NULL,       "dpll2_fck",    &dpll2_fck),
+        CLK(NULL,       "iva2_ck",      &iva2_ck),
+        CLK(NULL,       "modem_fck",    &modem_fck),
+        CLK(NULL,       "sad2d_ick",    &sad2d_ick),
+        CLK(NULL,       "mad2d_ick",    &mad2d_ick),
+        CLK(NULL,       "mspro_fck",    &mspro_fck),
+        CLK(NULL,       "dpll2_ck",     &dpll2_ck),
+        CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck),
+};
+
+/*
+ * clocks common to omap36xx and omap3430es2plus
+ */
+static struct omap_clk omap36xx_omap3430es2plus_clks[] = {
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2),
+        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2),
+        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es2),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2),
+        CLK(NULL,       "usim_fck",     &usim_fck),
+        CLK(NULL,       "usim_ick",     &usim_ick),
+};
+
+/*
+ * clocks common to am35xx omap36xx and omap3430es2plus
+ */
+static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
+        CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck),
+        CLK(NULL,       "dpll5_ck",     &dpll5_ck),
+        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck),
+        CLK(NULL,       "sgx_fck",      &sgx_fck),
+        CLK(NULL,       "sgx_ick",      &sgx_ick),
+        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck),
+        CLK(NULL,       "ts_fck",       &ts_fck),
+        CLK(NULL,       "usbtll_fck",   &usbtll_fck),
+        CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck),
+        CLK("usbhs_tll",        "usbtll_fck",   &usbtll_fck),
+        CLK(NULL,       "usbtll_ick",   &usbtll_ick),
+        CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick),
+        CLK("usbhs_tll",        "usbtll_ick",   &usbtll_ick),
+        CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick),
+        CLK(NULL,       "mmchs3_ick",   &mmchs3_ick),
+        CLK(NULL,       "mmchs3_fck",   &mmchs3_fck),
+        CLK(NULL,       "dss1_alwon_fck",       &dss1_alwon_fck_3430es2),
+        CLK("omapdss_dss",      "ick",          &dss_ick_3430es2),
+        CLK(NULL,       "dss_ick",              &dss_ick_3430es2),
+        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck),
+        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck),
+        CLK(NULL,       "usbhost_ick",  &usbhost_ick),
+        CLK("usbhs_omap",       "usbhost_ick",  &usbhost_ick),
+};
+
+/*
+ * common clocks
  */
 static struct omap_clk omap3xxx_clks[] = {
-        CLK(NULL,       "apb_pclk",     &dummy_apb_pclk,        CK_3XXX),
-        CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
-        CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
-        CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),
-        CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX  | CK_36XX),
-        CLK(NULL,       "virt_19200000_ck", &virt_19200000_ck, CK_3XXX),
-        CLK(NULL,       "virt_26000000_ck", &virt_26000000_ck, CK_3XXX),
-        CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
-        CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
-        CLK("twl",      "fck",          &osc_sys_ck,    CK_3XXX),
-        CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
-        CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
-        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
-        CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_3XXX),
-        CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
-        CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_3XXX),
-        CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
-        CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_34XX | CK_36XX),
-        CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_34XX | CK_36XX),
-        CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_3XXX),
-        CLK(NULL,       "core_ck",      &core_ck,       CK_3XXX),
-        CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_3XXX),
-        CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_3XXX),
-        CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
-        CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_3XXX),
-        CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
-        CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
-        CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_3XXX),
-        CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_3XXX),
-        CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
-        CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
-        CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_3XXX),
-        CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_3XXX),
-        CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_3XXX),
-        CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_3XXX),
-        CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_3XXX),
-        CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_3XXX),
-        CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
-        CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_3XXX),
-        CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
-        CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_3XXX),
-        CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
-        CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_3XXX),
-        CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
-        CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
-        CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
-        CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
-        CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
-        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_3XXX),
-        CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_3XXX),
-        CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_3XXX),
-        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
-        CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
-        CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
-        CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_34XX | CK_36XX),
-        CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_34XX | CK_36XX),
-        CLK(NULL,       "l3_ick",       &l3_ick,        CK_3XXX),
-        CLK(NULL,       "l4_ick",       &l4_ick,        CK_3XXX),
-        CLK(NULL,       "rm_ick",       &rm_ick,        CK_3XXX),
-        CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
-        CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
-        CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
-        CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
-        CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
-        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
-        CLK(NULL,       "modem_fck",    &modem_fck,     CK_34XX | CK_36XX),
-        CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_34XX | CK_36XX),
-        CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_34XX | CK_36XX),
-        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_3XXX),
-        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_3XXX),
-        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs_tll",        "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
-        CLK(NULL,       "mmchs3_fck",   &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_3XXX),
-        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_34XX | CK_36XX),
-        CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_3XXX),
-        CLK(NULL,       "i2c3_fck",     &i2c3_fck,      CK_3XXX),
-        CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_3XXX),
-        CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_3XXX),
-        CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_3XXX),
-        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_3XXX),
-        CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_3XXX),
-        CLK(NULL,       "mcspi4_fck",   &mcspi4_fck,    CK_3XXX),
-        CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_3XXX),
-        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_3XXX),
-        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_3XXX),
-        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_3XXX),
-        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_3XXX),
-        CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
-        CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
-        CLK("omap_hdq.0",       "fck",  &hdq_fck,       CK_3XXX),
-        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_3XXX),
-        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
-        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
-        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
-        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
-        CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
-        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
-        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
-        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es1,  CK_3430ES1),
-        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
-        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
-        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
-        CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
-        CLK(NULL,       "pka_ick",      &pka_ick,       CK_34XX | CK_36XX),
-        CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
-        CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs_tll",        "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "mmchs3_ick",   &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "icr_ick",      &icr_ick,       CK_34XX | CK_36XX),
-        CLK("omap-aes", "ick",  &aes2_ick,      CK_34XX | CK_36XX),
-        CLK("omap-sham",        "ick",  &sha12_ick,     CK_34XX | CK_36XX),
-        CLK(NULL,       "des2_ick",     &des2_ick,      CK_34XX | CK_36XX),
-        CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick,    CK_3XXX),
-        CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick,    CK_3XXX),
-        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick,    CK_3XXX),
-        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick,    CK_3XXX),
-        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_34XX | CK_36XX),
-        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
-        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_3XXX),
-        CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
-        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
-        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
-        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
-        CLK(NULL,       "mcspi4_ick",   &mcspi4_ick,    CK_3XXX),
-        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick,    CK_3XXX),
-        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_3XXX),
-        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_3XXX),
-        CLK("omap_i2c.3", "ick",        &i2c3_ick,      CK_3XXX),
-        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_3XXX),
-        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_3XXX),
-        CLK(NULL,       "i2c3_ick",     &i2c3_ick,      CK_3XXX),
-        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_3XXX),
-        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_3XXX),
-        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
-        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
-        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
-        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_3XXX),
-        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
-        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
-        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick,    CK_3XXX),
-        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_3XXX),
-        CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
-        CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
-        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
-        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_34XX | CK_36XX),
-        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
-        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2PLUS | CK_36XX),
-        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
-        CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
-        CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_34XX | CK_36XX),
-        CLK("omap_rng", "ick",          &rng_ick,       CK_34XX | CK_36XX),
-        CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_34XX | CK_36XX),
-        CLK(NULL,       "des1_ick",     &des1_ick,      CK_34XX | CK_36XX),
-        CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es1, CK_3430ES1),
-        CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "dss_tv_fck",   &dss_tv_fck,    CK_3XXX),
-        CLK(NULL,       "dss_96m_fck",  &dss_96m_fck,   CK_3XXX),
-        CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck, CK_3XXX),
-        CLK("omapdss_dss",      "ick",          &dss_ick_3430es1,       CK_3430ES1),
-        CLK(NULL,       "dss_ick",              &dss_ick_3430es1,       CK_3430ES1),
-        CLK("omapdss_dss",      "ick",          &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "dss_ick",              &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_34XX | CK_36XX),
-        CLK(NULL,       "cam_ick",      &cam_ick,       CK_34XX | CK_36XX),
-        CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_34XX | CK_36XX),
-        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs_omap",       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "utmi_p1_gfclk",        &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "utmi_p2_gfclk",        &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "xclk60mhsp1_ck",       &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "xclk60mhsp2_ck",       &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
-        CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs_tll",        "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs_tll",        "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "init_60m_fclk",        &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
-        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
-        CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
-        CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_3XXX),
-        CLK(NULL,       "wdt2_fck",             &wdt2_fck,      CK_3XXX),
-        CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_34XX | CK_36XX),
-        CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2PLUS | CK_36XX),
-        CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
-        CLK(NULL,       "wdt2_ick",     &wdt2_ick,      CK_3XXX),
-        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
-        CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
-        CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
-        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_3XXX),
-        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_3XXX),
-        CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_3XXX),
-        CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
-        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
-        CLK(NULL,       "uart4_fck",    &uart4_fck,     CK_36XX),
-        CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx, CK_AM35XX),
-        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
-        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
-        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
-        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_3XXX),
-        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_3XXX),
-        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_3XXX),
-        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_3XXX),
-        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_3XXX),
-        CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
-        CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_3XXX),
-        CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_3XXX),
-        CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_3XXX),
-        CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_3XXX),
-        CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_3XXX),
-        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_3XXX),
-        CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_3XXX),
-        CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_3XXX),
-        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_3XXX),
-        CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_3XXX),
-        CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_3XXX),
-        CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_3XXX),
-        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_3XXX),
-        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_3XXX),
-        CLK(NULL,       "uart4_ick",    &uart4_ick,     CK_36XX),
-        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_3XXX),
-        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_3XXX),
-        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_3XXX),
-        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_3XXX),
-        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_3XXX),
-        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_3XXX),
-        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_3XXX),
-        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_3XXX),
-        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_3XXX),
-        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_3XXX),
-        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_3XXX),
-        CLK(NULL,       "mcbsp4_ick",   &mcbsp2_ick,    CK_3XXX),
-        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick,    CK_3XXX),
-        CLK(NULL,       "mcbsp2_ick",   &mcbsp4_ick,    CK_3XXX),
-        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_3XXX),
-        CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_3XXX),
-        CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_3XXX),
-        CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_3XXX),
-        CLK(NULL,       "emu_src_ck",   &emu_src_ck,    CK_3XXX),
-        CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_3XXX),
-        CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_3XXX),
-        CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_3XXX),
-        CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
-        CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_3XXX),
-        CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_34XX | CK_36XX),
-        CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_34XX | CK_36XX),
-        CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_34XX | CK_36XX),
-        CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_3XXX),
-        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_3XXX),
-        CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_3XXX),
-        CLK(NULL,       "ipss_ick",     &ipss_ick,      CK_AM35XX),
-        CLK(NULL,       "rmii_ck",      &rmii_ck,       CK_AM35XX),
-        CLK(NULL,       "pclk_ck",      &pclk_ck,       CK_AM35XX),
-        CLK(NULL,       "emac_ick",     &emac_ick,      CK_AM35XX),
-        CLK(NULL,       "emac_fck",     &emac_fck,      CK_AM35XX),
-        CLK("davinci_emac.0",   NULL,   &emac_ick,      CK_AM35XX),
-        CLK("davinci_mdio.0",   NULL,   &emac_fck,      CK_AM35XX),
-        CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
-        CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
-        CLK(NULL,       "hsotgusb_ick",         &hsotgusb_ick_am35xx,   CK_AM35XX),
-        CLK(NULL,       "hsotgusb_fck",         &hsotgusb_fck_am35xx,   CK_AM35XX),
-        CLK(NULL,       "hecc_ck",      &hecc_ck,       CK_AM35XX),
-        CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
-        CLK(NULL,       "timer_32k_ck", &omap_32k_fck,  CK_3XXX),
-        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_3XXX),
-        CLK(NULL,       "cpufreq_ck",   &dpll1_ck,      CK_3XXX),
+        CLK(NULL,       "apb_pclk",     &dummy_apb_pclk),
+        CLK(NULL,       "omap_32k_fck", &omap_32k_fck),
+        CLK(NULL,       "virt_12m_ck",  &virt_12m_ck),
+        CLK(NULL,       "virt_13m_ck",  &virt_13m_ck),
+        CLK(NULL,       "virt_19200000_ck", &virt_19200000_ck),
+        CLK(NULL,       "virt_26000000_ck", &virt_26000000_ck),
+        CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck),
+        CLK(NULL,       "osc_sys_ck",   &osc_sys_ck),
+        CLK("twl",      "fck",          &osc_sys_ck),
+        CLK(NULL,       "sys_ck",       &sys_ck),
+        CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck),
+        CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck),
+        CLK(NULL,       "sys_altclk",   &sys_altclk),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks),
+        CLK(NULL,       "sys_clkout1",  &sys_clkout1),
+        CLK(NULL,       "dpll1_ck",     &dpll1_ck),
+        CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck),
+        CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck),
+        CLK(NULL,       "dpll3_ck",     &dpll3_ck),
+        CLK(NULL,       "core_ck",      &core_ck),
+        CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck),
+        CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck),
+        CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck),
+        CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck),
+        CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck),
+        CLK(NULL,       "dpll4_ck",     &dpll4_ck),
+        CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck),
+        CLK(NULL,       "omap_96m_fck", &omap_96m_fck),
+        CLK(NULL,       "cm_96m_fck",   &cm_96m_fck),
+        CLK(NULL,       "omap_54m_fck", &omap_54m_fck),
+        CLK(NULL,       "omap_48m_fck", &omap_48m_fck),
+        CLK(NULL,       "omap_12m_fck", &omap_12m_fck),
+        CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck),
+        CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck),
+        CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck),
+        CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck),
+        CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck),
+        CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck),
+        CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck),
+        CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck),
+        CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck),
+        CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck),
+        CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck),
+        CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck),
+        CLK(NULL,       "sys_clkout2",  &sys_clkout2),
+        CLK(NULL,       "corex2_fck",   &corex2_fck),
+        CLK(NULL,       "dpll1_fck",    &dpll1_fck),
+        CLK(NULL,       "mpu_ck",       &mpu_ck),
+        CLK(NULL,       "arm_fck",      &arm_fck),
+        CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
+        CLK(NULL,       "l3_ick",       &l3_ick),
+        CLK(NULL,       "l4_ick",       &l4_ick),
+        CLK(NULL,       "rm_ick",       &rm_ick),
+        CLK(NULL,       "gpt10_fck",    &gpt10_fck),
+        CLK(NULL,       "gpt11_fck",    &gpt11_fck),
+        CLK(NULL,       "core_96m_fck", &core_96m_fck),
+        CLK(NULL,       "mmchs2_fck",   &mmchs2_fck),
+        CLK(NULL,       "mmchs1_fck",   &mmchs1_fck),
+        CLK(NULL,       "i2c3_fck",     &i2c3_fck),
+        CLK(NULL,       "i2c2_fck",     &i2c2_fck),
+        CLK(NULL,       "i2c1_fck",     &i2c1_fck),
+        CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck),
+        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck),
+        CLK(NULL,       "core_48m_fck", &core_48m_fck),
+        CLK(NULL,       "mcspi4_fck",   &mcspi4_fck),
+        CLK(NULL,       "mcspi3_fck",   &mcspi3_fck),
+        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck),
+        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck),
+        CLK(NULL,       "uart2_fck",    &uart2_fck),
+        CLK(NULL,       "uart1_fck",    &uart1_fck),
+        CLK(NULL,       "core_12m_fck", &core_12m_fck),
+        CLK("omap_hdq.0",       "fck",  &hdq_fck),
+        CLK(NULL,       "hdq_fck",      &hdq_fck),
+        CLK(NULL,       "core_l3_ick",  &core_l3_ick),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick),
+        CLK(NULL,       "gpmc_fck",     &gpmc_fck),
+        CLK(NULL,       "core_l4_ick",  &core_l4_ick),
+        CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick),
+        CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick),
+        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick),
+        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick),
+        CLK("omap_hdq.0", "ick",        &hdq_ick),
+        CLK(NULL,       "hdq_ick",      &hdq_ick),
+        CLK("omap2_mcspi.4", "ick",     &mcspi4_ick),
+        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick),
+        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick),
+        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick),
+        CLK(NULL,       "mcspi4_ick",   &mcspi4_ick),
+        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick),
+        CLK("omap_i2c.3", "ick",        &i2c3_ick),
+        CLK("omap_i2c.2", "ick",        &i2c2_ick),
+        CLK("omap_i2c.1", "ick",        &i2c1_ick),
+        CLK(NULL,       "i2c3_ick",     &i2c3_ick),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick),
+        CLK(NULL,       "uart2_ick",    &uart2_ick),
+        CLK(NULL,       "uart1_ick",    &uart1_ick),
+        CLK(NULL,       "gpt11_ick",    &gpt11_ick),
+        CLK(NULL,       "gpt10_ick",    &gpt10_ick),
+        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick),
+        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick),
+        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick),
+        CLK(NULL,       "omapctrl_ick", &omapctrl_ick),
+        CLK(NULL,       "dss_tv_fck",   &dss_tv_fck),
+        CLK(NULL,       "dss_96m_fck",  &dss_96m_fck),
+        CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck),
+        CLK(NULL,       "utmi_p1_gfclk",        &dummy_ck),
+        CLK(NULL,       "utmi_p2_gfclk",        &dummy_ck),
+        CLK(NULL,       "xclk60mhsp1_ck",       &dummy_ck),
+        CLK(NULL,       "xclk60mhsp2_ck",       &dummy_ck),
+        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &dummy_ck),
+        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &dummy_ck),
+        CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck),
+        CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck),
+        CLK("usbhs_tll",        "usb_tll_hs_usb_ch0_clk",       &dummy_ck),
+        CLK("usbhs_tll",        "usb_tll_hs_usb_ch1_clk",       &dummy_ck),
+        CLK(NULL,       "init_60m_fclk",        &dummy_ck),
+        CLK(NULL,       "gpt1_fck",     &gpt1_fck),
+        CLK(NULL,       "aes2_ick",     &aes2_ick),
+        CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck),
+        CLK(NULL,       "gpio1_dbck",   &gpio1_dbck),
+        CLK(NULL,       "sha12_ick",    &sha12_ick),
+        CLK(NULL,       "wdt2_fck",             &wdt2_fck),
+        CLK("omap_wdt", "ick",          &wdt2_ick),
+        CLK(NULL,       "wdt2_ick",     &wdt2_ick),
+        CLK(NULL,       "wdt1_ick",     &wdt1_ick),
+        CLK(NULL,       "gpio1_ick",    &gpio1_ick),
+        CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick),
+        CLK(NULL,       "gpt12_ick",    &gpt12_ick),
+        CLK(NULL,       "gpt1_ick",     &gpt1_ick),
+        CLK(NULL,       "per_96m_fck",  &per_96m_fck),
+        CLK(NULL,       "per_48m_fck",  &per_48m_fck),
+        CLK(NULL,       "uart3_fck",    &uart3_fck),
+        CLK(NULL,       "gpt2_fck",     &gpt2_fck),
+        CLK(NULL,       "gpt3_fck",     &gpt3_fck),
+        CLK(NULL,       "gpt4_fck",     &gpt4_fck),
+        CLK(NULL,       "gpt5_fck",     &gpt5_fck),
+        CLK(NULL,       "gpt6_fck",     &gpt6_fck),
+        CLK(NULL,       "gpt7_fck",     &gpt7_fck),
+        CLK(NULL,       "gpt8_fck",     &gpt8_fck),
+        CLK(NULL,       "gpt9_fck",     &gpt9_fck),
+        CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck),
+        CLK(NULL,       "gpio6_dbck",   &gpio6_dbck),
+        CLK(NULL,       "gpio5_dbck",   &gpio5_dbck),
+        CLK(NULL,       "gpio4_dbck",   &gpio4_dbck),
+        CLK(NULL,       "gpio3_dbck",   &gpio3_dbck),
+        CLK(NULL,       "gpio2_dbck",   &gpio2_dbck),
+        CLK(NULL,       "wdt3_fck",     &wdt3_fck),
+        CLK(NULL,       "per_l4_ick",   &per_l4_ick),
+        CLK(NULL,       "gpio6_ick",    &gpio6_ick),
+        CLK(NULL,       "gpio5_ick",    &gpio5_ick),
+        CLK(NULL,       "gpio4_ick",    &gpio4_ick),
+        CLK(NULL,       "gpio3_ick",    &gpio3_ick),
+        CLK(NULL,       "gpio2_ick",    &gpio2_ick),
+        CLK(NULL,       "wdt3_ick",     &wdt3_ick),
+        CLK(NULL,       "uart3_ick",    &uart3_ick),
+        CLK(NULL,       "uart4_ick",    &uart4_ick),
+        CLK(NULL,       "gpt9_ick",     &gpt9_ick),
+        CLK(NULL,       "gpt8_ick",     &gpt8_ick),
+        CLK(NULL,       "gpt7_ick",     &gpt7_ick),
+        CLK(NULL,       "gpt6_ick",     &gpt6_ick),
+        CLK(NULL,       "gpt5_ick",     &gpt5_ick),
+        CLK(NULL,       "gpt4_ick",     &gpt4_ick),
+        CLK(NULL,       "gpt3_ick",     &gpt3_ick),
+        CLK(NULL,       "gpt2_ick",     &gpt2_ick),
+        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick),
+        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick),
+        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick),
+        CLK(NULL,       "mcbsp4_ick",   &mcbsp2_ick),
+        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp4_ick),
+        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck),
+        CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck),
+        CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck),
+        CLK("etb",      "emu_src_ck",   &emu_src_ck),
+        CLK(NULL,       "emu_src_ck",   &emu_src_ck),
+        CLK(NULL,       "pclk_fck",     &pclk_fck),
+        CLK(NULL,       "pclkx2_fck",   &pclkx2_fck),
+        CLK(NULL,       "atclk_fck",    &atclk_fck),
+        CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck),
+        CLK(NULL,       "traceclk_fck", &traceclk_fck),
+        CLK(NULL,       "secure_32k_fck", &secure_32k_fck),
+        CLK(NULL,       "gpt12_fck",    &gpt12_fck),
+        CLK(NULL,       "wdt1_fck",     &wdt1_fck),
+        CLK(NULL,       "timer_32k_ck", &omap_32k_fck),
+        CLK(NULL,       "timer_sys_ck", &sys_ck),
+        CLK(NULL,       "cpufreq_ck",   &dpll1_ck),
 };
 
 static const char *enable_init_clks[] = {
@@ -3512,8 +3550,27 @@ static const char *enable_init_clks[] = {
 
 int __init omap3xxx_clk_init(void)
 {
-        struct omap_clk *c;
-        u32 cpu_clkflg = 0;
+        if (omap3_has_192mhz_clk())
+                omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
+
+        if (cpu_is_omap3630()) {
+                dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
+                dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
+                dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
+                dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
+                dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
+                dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
+        }
+
+        /*
+         * XXX This type of dynamic rewriting of the clock tree is
+         * deprecated and should be revised soon.
+         */
+        if (cpu_is_omap3630())
+                dpll4_dd = dpll4_dd_3630;
+        else
+                dpll4_dd = dpll4_dd_34xx;
+
 
         /*
          * 3505 must be tested before 3517, since 3517 returns true
@@ -3523,13 +3580,20 @@ int __init omap3xxx_clk_init(void)
          */
         if (soc_is_am35xx()) {
                 cpu_mask = RATE_IN_34XX;
-                cpu_clkflg = CK_AM35XX;
+                omap_clocks_register(am35xx_clks, ARRAY_SIZE(am35xx_clks));
+                omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
+                                     ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
+                omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
         } else if (cpu_is_omap3630()) {
                 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
-                cpu_clkflg = CK_36XX;
-        } else if (cpu_is_ti816x()) {
-                cpu_mask = RATE_IN_TI816X;
-                cpu_clkflg = CK_TI816X;
+                omap_clocks_register(omap36xx_clks, ARRAY_SIZE(omap36xx_clks));
+                omap_clocks_register(omap36xx_omap3430es2plus_clks,
+                                     ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
+                omap_clocks_register(omap34xx_omap36xx_clks,
+                                     ARRAY_SIZE(omap34xx_omap36xx_clks));
+                omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
+                                     ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
+                omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
         } else if (soc_is_am33xx()) {
                 cpu_mask = RATE_IN_AM33XX;
         } else if (cpu_is_ti814x()) {
@@ -3537,49 +3601,32 @@ int __init omap3xxx_clk_init(void)
         } else if (cpu_is_omap34xx()) {
                 if (omap_rev() == OMAP3430_REV_ES1_0) {
                         cpu_mask = RATE_IN_3430ES1;
-                        cpu_clkflg = CK_3430ES1;
+                        omap_clocks_register(omap3430es1_clks,
+                                             ARRAY_SIZE(omap3430es1_clks));
+                        omap_clocks_register(omap34xx_omap36xx_clks,
+                                             ARRAY_SIZE(omap34xx_omap36xx_clks));
+                        omap_clocks_register(omap3xxx_clks,
+                                             ARRAY_SIZE(omap3xxx_clks));
                 } else {
                         /*
                          * Assume that anything that we haven't matched yet
                          * has 3430ES2-type clocks.
                          */
                         cpu_mask = RATE_IN_3430ES2PLUS;
-                        cpu_clkflg = CK_3430ES2PLUS;
+                        omap_clocks_register(omap34xx_omap36xx_clks,
+                                             ARRAY_SIZE(omap34xx_omap36xx_clks));
+                        omap_clocks_register(omap36xx_omap3430es2plus_clks,
+                                             ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
+                        omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
+                                             ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
+                        omap_clocks_register(omap3xxx_clks,
+                                             ARRAY_SIZE(omap3xxx_clks));
                 }
         } else {
                 WARN(1, "clock: could not identify OMAP3 variant\n");
         }
 
-        if (omap3_has_192mhz_clk())
-                omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
-
-        if (cpu_is_omap3630()) {
-                dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
-                dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
-                dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
-                dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
-                dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
-                dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
-        }
-
-        /*
-         * XXX This type of dynamic rewriting of the clock tree is
-         * deprecated and should be revised soon.
-         */
-        if (cpu_is_omap3630())
-                dpll4_dd = dpll4_dd_3630;
-        else
-                dpll4_dd = dpll4_dd_34xx;
-
-        for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
-             c++)
-                if (c->cpu & cpu_clkflg) {
-                        clkdev_add(&c->lk);
-                        if (!__clk_init(NULL, c->lk.clk))
-                                omap2_init_clk_hw_omap_clocks(c->lk.clk);
-                }
-
-        omap2_clk_disable_autoidle_all();
+                omap2_clk_disable_autoidle_all();
 
         omap2_clk_enable_init_clocks(enable_init_clks,
                                      ARRAY_SIZE(enable_init_clks));
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index 0c6834ae1fc4..88e37a474334 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -1424,284 +1424,285 @@ DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
                0x0, NULL);
 
 /*
- * clkdev
+ * clocks specific to omap4460
  */
+static struct omap_clk omap446x_clks[] = {
+        CLK(NULL,       "div_ts_ck",                    &div_ts_ck),
+        CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk),
+};
+
+/*
+ * clocks specific to omap4430
+ */
+static struct omap_clk omap443x_clks[] = {
+        CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk),
+};
 
+/*
+ * clocks common to omap44xx
+ */
 static struct omap_clk omap44xx_clks[] = {
-        CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
-        CLK(NULL,       "pad_clks_src_ck",              &pad_clks_src_ck,       CK_443X),
-        CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
-        CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
-        CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
-        CLK(NULL,       "slimbus_src_clk",              &slimbus_src_clk,       CK_443X),
-        CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
-        CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
-        CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
-        CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
-        CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
-        CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
-        CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
-        CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
-        CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
-        CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
-        CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
-        CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
-        CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
-        CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
-        CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
-        CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
-        CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
-        CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
-        CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
-        CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
-        CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
-        CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
-        CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
-        CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
-        CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
-        CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
-        CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
-        CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
-        CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
-        CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
-        CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
-        CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
-        CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
-        CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
-        CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
-        CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
-        CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
-        CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
-        CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
-        CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
-        CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
-        CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
-        CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
-        CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
-        CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
-        CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
-        CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
-        CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
-        CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
-        CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
-        CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
-        CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
-        CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
-        CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
-        CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
-        CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
-        CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
-        CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
-        CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
-        CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
-        CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
-        CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
-        CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
-        CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
-        CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
-        CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
-        CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
-        CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
-        CLK("smp_twd",  NULL,                           &mpu_periphclk, CK_443X),
-        CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
-        CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
-        CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
-        CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
-        CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
-        CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
-        CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
-        CLK(NULL,       "div_ts_ck",                    &div_ts_ck,     CK_446X),
-        CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk,       CK_446X),
-        CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
-        CLK(NULL,       "func_dmic_abe_gfclk",                  &func_dmic_abe_gfclk,   CK_443X),
-        CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
-        CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
-        CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
-        CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
-        CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
-        CLK("omapdss_dss",      "ick",                  &dss_fck,       CK_443X),
-        CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
-        CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
-        CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
-        CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
-        CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
-        CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
-        CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
-        CLK(NULL,       "sgx_clk_mux",                  &sgx_clk_mux,   CK_443X),
-        CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
-        CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
-        CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
-        CLK(NULL,       "func_mcasp_abe_gfclk",                 &func_mcasp_abe_gfclk,  CK_443X),
-        CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
-        CLK(NULL,       "func_mcbsp1_gfclk",                    &func_mcbsp1_gfclk,     CK_443X),
-        CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
-        CLK(NULL,       "func_mcbsp2_gfclk",                    &func_mcbsp2_gfclk,     CK_443X),
-        CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
-        CLK(NULL,       "func_mcbsp3_gfclk",                    &func_mcbsp3_gfclk,     CK_443X),
-        CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
-        CLK(NULL,       "per_mcbsp4_gfclk",                     &per_mcbsp4_gfclk,      CK_443X),
-        CLK(NULL,       "hsmmc1_fclk",                  &hsmmc1_fclk,   CK_443X),
-        CLK(NULL,       "hsmmc2_fclk",                  &hsmmc2_fclk,   CK_443X),
-        CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
-        CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
-        CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
-        CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
-        CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
-        CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
-        CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
-        CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
-        CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
-        CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
-        CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
-        CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
-        CLK(NULL,       "dmt1_clk_mux",                 &dmt1_clk_mux,  CK_443X),
-        CLK(NULL,       "cm2_dm10_mux",                 &cm2_dm10_mux,  CK_443X),
-        CLK(NULL,       "cm2_dm11_mux",                 &cm2_dm11_mux,  CK_443X),
-        CLK(NULL,       "cm2_dm2_mux",                  &cm2_dm2_mux,   CK_443X),
-        CLK(NULL,       "cm2_dm3_mux",                  &cm2_dm3_mux,   CK_443X),
-        CLK(NULL,       "cm2_dm4_mux",                  &cm2_dm4_mux,   CK_443X),
-        CLK(NULL,       "timer5_sync_mux",              &timer5_sync_mux,       CK_443X),
-        CLK(NULL,       "timer6_sync_mux",                      &timer6_sync_mux,       CK_443X),
-        CLK(NULL,       "timer7_sync_mux",                      &timer7_sync_mux,       CK_443X),
-        CLK(NULL,       "timer8_sync_mux",                      &timer8_sync_mux,       CK_443X),
-        CLK(NULL,       "cm2_dm9_mux",                  &cm2_dm9_mux,   CK_443X),
-        CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
-        CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck,       CK_443X),
-        CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
-        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
-        CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
-        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
-        CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
-        CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
-        CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
-        CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
-        CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
-        CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
-        CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
-        CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck,       CK_443X),
-        CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
-        CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
-        CLK(NULL,       "usb_otg_hs_ick",               &usb_otg_hs_ick,        CK_443X),
-        CLK("musb-omap2430",    "ick",                  &usb_otg_hs_ick,        CK_443X),
-        CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
-        CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
-        CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
-        CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
-        CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
-        CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
-        CLK("usbhs_tll",        "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
-        CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
-        CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
-        CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
-        CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
-        CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
-        CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
-        CLK(NULL,       "auxclk0_src_ck",               &auxclk0_src_ck,        CK_443X),
-        CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
-        CLK(NULL,       "auxclk1_src_ck",               &auxclk1_src_ck,        CK_443X),
-        CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
-        CLK(NULL,       "auxclk2_src_ck",               &auxclk2_src_ck,        CK_443X),
-        CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
-        CLK(NULL,       "auxclk3_src_ck",               &auxclk3_src_ck,        CK_443X),
-        CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
-        CLK(NULL,       "auxclk4_src_ck",               &auxclk4_src_ck,        CK_443X),
-        CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
-        CLK(NULL,       "auxclk5_src_ck",               &auxclk5_src_ck,        CK_443X),
-        CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
-        CLK("omap-gpmc",        "fck",                  &dummy_ck,      CK_443X),
-        CLK("omap_i2c.1",       "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap_i2c.2",       "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap_i2c.3",       "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap_i2c.4",       "ick",                  &dummy_ck,      CK_443X),
-        CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
-        CLK("omap_hsmmc.0",     "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap_hsmmc.1",     "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap_hsmmc.2",     "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap_hsmmc.3",     "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap_hsmmc.4",     "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap-mcbsp.1",     "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap-mcbsp.2",     "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap-mcbsp.3",     "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap-mcbsp.4",     "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.1",    "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.2",    "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.3",    "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.4",    "ick",                  &dummy_ck,      CK_443X),
-        CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
-        CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
-        CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
-        CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
-        CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck,              CK_443X),
-        CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck,      CK_443X),
-        CLK("usbhs_tll",        "usbtll_fck",           &dummy_ck,      CK_443X),
-        CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
-        CLK(NULL,       "timer_32k_ck", &sys_32k_ck,    CK_443X),
+        CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck),
+        CLK(NULL,       "pad_clks_src_ck",              &pad_clks_src_ck),
+        CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck),
+        CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck),
+        CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck),
+        CLK(NULL,       "slimbus_src_clk",              &slimbus_src_clk),
+        CLK(NULL,       "slimbus_clk",                  &slimbus_clk),
+        CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck),
+        CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck),
+        CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck),
+        CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck),
+        CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck),
+        CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck),
+        CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck),
+        CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck),
+        CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck),
+        CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck),
+        CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck),
+        CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck),
+        CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck),
+        CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck),
+        CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck),
+        CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck),
+        CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck),
+        CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck),
+        CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck),
+        CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk),
+        CLK(NULL,       "abe_clk",                      &abe_clk),
+        CLK(NULL,       "aess_fclk",                    &aess_fclk),
+        CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck),
+        CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck),
+        CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck),
+        CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck),
+        CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck),
+        CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck),
+        CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck),
+        CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck),
+        CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck),
+        CLK(NULL,       "div_core_ck",                  &div_core_ck),
+        CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk),
+        CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk),
+        CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck),
+        CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck),
+        CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck),
+        CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck),
+        CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck),
+        CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck),
+        CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck),
+        CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck),
+        CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck),
+        CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck),
+        CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck),
+        CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck),
+        CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck),
+        CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck),
+        CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck),
+        CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck),
+        CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck),
+        CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck),
+        CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck),
+        CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck),
+        CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck),
+        CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck),
+        CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck),
+        CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck),
+        CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck),
+        CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck),
+        CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck),
+        CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck),
+        CLK(NULL,       "func_12m_fclk",                &func_12m_fclk),
+        CLK(NULL,       "func_24m_clk",                 &func_24m_clk),
+        CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk),
+        CLK(NULL,       "func_48m_fclk",                &func_48m_fclk),
+        CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk),
+        CLK(NULL,       "func_64m_fclk",                &func_64m_fclk),
+        CLK(NULL,       "func_96m_fclk",                &func_96m_fclk),
+        CLK(NULL,       "init_60m_fclk",                &init_60m_fclk),
+        CLK(NULL,       "l3_div_ck",                    &l3_div_ck),
+        CLK(NULL,       "l4_div_ck",                    &l4_div_ck),
+        CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck),
+        CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck),
+        CLK("smp_twd",  NULL,                           &mpu_periphclk),
+        CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk),
+        CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk),
+        CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk),
+        CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck),
+        CLK(NULL,       "aes1_fck",                     &aes1_fck),
+        CLK(NULL,       "aes2_fck",                     &aes2_fck),
+        CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck),
+        CLK(NULL,       "func_dmic_abe_gfclk",          &func_dmic_abe_gfclk),
+        CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk),
+        CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk),
+        CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk),
+        CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk),
+        CLK(NULL,       "dss_fck",                      &dss_fck),
+        CLK("omapdss_dss",      "ick",                  &dss_fck),
+        CLK(NULL,       "fdif_fck",                     &fdif_fck),
+        CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk),
+        CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk),
+        CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk),
+        CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk),
+        CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk),
+        CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk),
+        CLK(NULL,       "sgx_clk_mux",                  &sgx_clk_mux),
+        CLK(NULL,       "hsi_fck",                      &hsi_fck),
+        CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk),
+        CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck),
+        CLK(NULL,       "func_mcasp_abe_gfclk",         &func_mcasp_abe_gfclk),
+        CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck),
+        CLK(NULL,       "func_mcbsp1_gfclk",            &func_mcbsp1_gfclk),
+        CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck),
+        CLK(NULL,       "func_mcbsp2_gfclk",            &func_mcbsp2_gfclk),
+        CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck),
+        CLK(NULL,       "func_mcbsp3_gfclk",            &func_mcbsp3_gfclk),
+        CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck),
+        CLK(NULL,       "per_mcbsp4_gfclk",             &per_mcbsp4_gfclk),
+        CLK(NULL,       "hsmmc1_fclk",                  &hsmmc1_fclk),
+        CLK(NULL,       "hsmmc2_fclk",                  &hsmmc2_fclk),
+        CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m),
+        CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck),
+        CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1),
+        CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0),
+        CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2),
+        CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk),
+        CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1),
+        CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0),
+        CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk),
+        CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck),
+        CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck),
+        CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck),
+        CLK(NULL,       "dmt1_clk_mux",                 &dmt1_clk_mux),
+        CLK(NULL,       "cm2_dm10_mux",                 &cm2_dm10_mux),
+        CLK(NULL,       "cm2_dm11_mux",                 &cm2_dm11_mux),
+        CLK(NULL,       "cm2_dm2_mux",                  &cm2_dm2_mux),
+        CLK(NULL,       "cm2_dm3_mux",                  &cm2_dm3_mux),
+        CLK(NULL,       "cm2_dm4_mux",                  &cm2_dm4_mux),
+        CLK(NULL,       "timer5_sync_mux",              &timer5_sync_mux),
+        CLK(NULL,       "timer6_sync_mux",              &timer6_sync_mux),
+        CLK(NULL,       "timer7_sync_mux",              &timer7_sync_mux),
+        CLK(NULL,       "timer8_sync_mux",              &timer8_sync_mux),
+        CLK(NULL,       "cm2_dm9_mux",                  &cm2_dm9_mux),
+        CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck),
+        CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck),
+        CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk),
+        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk),
+        CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk),
+        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk),
+        CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk),
+        CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk),
+        CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk),
+        CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk),
+        CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk),
+        CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk),
+        CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck),
+        CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck),
+        CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk),
+        CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk),
+        CLK(NULL,       "usb_otg_hs_ick",               &usb_otg_hs_ick),
+        CLK("musb-omap2430",    "ick",                  &usb_otg_hs_ick),
+        CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k),
+        CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk),
+        CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk),
+        CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk),
+        CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick),
+        CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick),
+        CLK("usbhs_tll",        "usbtll_ick",           &usb_tll_hs_ick),
+        CLK(NULL,       "usim_ck",                      &usim_ck),
+        CLK(NULL,       "usim_fclk",                    &usim_fclk),
+        CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck),
+        CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck),
+        CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck),
+        CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck),
+        CLK(NULL,       "auxclk0_src_ck",               &auxclk0_src_ck),
+        CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck),
+        CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck),
+        CLK(NULL,       "auxclk1_src_ck",               &auxclk1_src_ck),
+        CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck),
+        CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck),
+        CLK(NULL,       "auxclk2_src_ck",               &auxclk2_src_ck),
+        CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck),
+        CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck),
+        CLK(NULL,       "auxclk3_src_ck",               &auxclk3_src_ck),
+        CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck),
+        CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck),
+        CLK(NULL,       "auxclk4_src_ck",               &auxclk4_src_ck),
+        CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck),
+        CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck),
+        CLK(NULL,       "auxclk5_src_ck",               &auxclk5_src_ck),
+        CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck),
+        CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck),
+        CLK("omap-gpmc",        "fck",                  &dummy_ck),
+        CLK("omap_i2c.1",       "ick",                  &dummy_ck),
+        CLK("omap_i2c.2",       "ick",                  &dummy_ck),
+        CLK("omap_i2c.3",       "ick",                  &dummy_ck),
+        CLK("omap_i2c.4",       "ick",                  &dummy_ck),
+        CLK(NULL,       "mailboxes_ick",                &dummy_ck),
+        CLK("omap_hsmmc.0",     "ick",                  &dummy_ck),
+        CLK("omap_hsmmc.1",     "ick",                  &dummy_ck),
+        CLK("omap_hsmmc.2",     "ick",                  &dummy_ck),
+        CLK("omap_hsmmc.3",     "ick",                  &dummy_ck),
+        CLK("omap_hsmmc.4",     "ick",                  &dummy_ck),
+        CLK("omap-mcbsp.1",     "ick",                  &dummy_ck),
+        CLK("omap-mcbsp.2",     "ick",                  &dummy_ck),
+        CLK("omap-mcbsp.3",     "ick",                  &dummy_ck),
+        CLK("omap-mcbsp.4",     "ick",                  &dummy_ck),
+        CLK("omap2_mcspi.1",    "ick",                  &dummy_ck),
+        CLK("omap2_mcspi.2",    "ick",                  &dummy_ck),
+        CLK("omap2_mcspi.3",    "ick",                  &dummy_ck),
+        CLK("omap2_mcspi.4",    "ick",                  &dummy_ck),
+        CLK(NULL,       "uart1_ick",                    &dummy_ck),
+        CLK(NULL,       "uart2_ick",                    &dummy_ck),
+        CLK(NULL,       "uart3_ick",                    &dummy_ck),
+        CLK(NULL,       "uart4_ick",                    &dummy_ck),
+        CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck),
+        CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck),
+        CLK("usbhs_tll",        "usbtll_fck",           &dummy_ck),
+        CLK("omap_wdt", "ick",                          &dummy_ck),
+        CLK(NULL,       "timer_32k_ck", &sys_32k_ck),
         /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
-        CLK("omap_timer.1",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.2",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.3",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.4",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.9",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.10",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.11",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.5",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("omap_timer.6",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("omap_timer.7",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("omap_timer.8",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("4a318000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("48032000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("48034000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("48036000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("4803e000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("48086000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("48088000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("40138000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("4013a000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("4013c000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("4013e000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck,   CK_443X),
+        CLK("omap_timer.1",     "timer_sys_ck", &sys_clkin_ck),
+        CLK("omap_timer.2",     "timer_sys_ck", &sys_clkin_ck),
+        CLK("omap_timer.3",     "timer_sys_ck", &sys_clkin_ck),
+        CLK("omap_timer.4",     "timer_sys_ck", &sys_clkin_ck),
+        CLK("omap_timer.9",     "timer_sys_ck", &sys_clkin_ck),
+        CLK("omap_timer.10",    "timer_sys_ck", &sys_clkin_ck),
+        CLK("omap_timer.11",    "timer_sys_ck", &sys_clkin_ck),
+        CLK("omap_timer.5",     "timer_sys_ck", &syc_clk_div_ck),
+        CLK("omap_timer.6",     "timer_sys_ck", &syc_clk_div_ck),
+        CLK("omap_timer.7",     "timer_sys_ck", &syc_clk_div_ck),
+        CLK("omap_timer.8",     "timer_sys_ck", &syc_clk_div_ck),
+        CLK("4a318000.timer",   "timer_sys_ck", &sys_clkin_ck),
+        CLK("48032000.timer",   "timer_sys_ck", &sys_clkin_ck),
+        CLK("48034000.timer",   "timer_sys_ck", &sys_clkin_ck),
+        CLK("48036000.timer",   "timer_sys_ck", &sys_clkin_ck),
+        CLK("4803e000.timer",   "timer_sys_ck", &sys_clkin_ck),
+        CLK("48086000.timer",   "timer_sys_ck", &sys_clkin_ck),
+        CLK("48088000.timer",   "timer_sys_ck", &sys_clkin_ck),
+        CLK("40138000.timer",   "timer_sys_ck", &syc_clk_div_ck),
+        CLK("4013a000.timer",   "timer_sys_ck", &syc_clk_div_ck),
+        CLK("4013c000.timer",   "timer_sys_ck", &syc_clk_div_ck),
+        CLK("4013e000.timer",   "timer_sys_ck", &syc_clk_div_ck),
+        CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck),
 };
 
 int __init omap4xxx_clk_init(void)
 {
-        u32 cpu_clkflg;
-        struct omap_clk *c;
         int rc;
 
         if (cpu_is_omap443x()) {
                 cpu_mask = RATE_IN_4430;
-                cpu_clkflg = CK_443X;
+                omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks));
         } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
                 cpu_mask = RATE_IN_4460 | RATE_IN_4430;
-                cpu_clkflg = CK_446X | CK_443X;
-
+                omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks));
                 if (cpu_is_omap447x())
                         pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
         } else {
                 return 0;
         }
 
-        for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
-                                                                        c++) {
-                if (c->cpu & cpu_clkflg) {
-                        clkdev_add(&c->lk);
-                        if (!__clk_init(NULL, c->lk.clk))
-                                omap2_init_clk_hw_omap_clocks(c->lk.clk);
-                }
-        }
+        omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
 
         omap2_clk_disable_autoidle_all();
 
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index e4ec3a69ee2e..0c38ca96c840 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -23,7 +23,7 @@
 #include <linux/clk-provider.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
-
+#include <linux/clk-private.h>
 #include <asm/cpu.h>
 
 
@@ -569,6 +569,21 @@ const struct clk_hw_omap_ops clkhwops_wait = {
 };
 
 /**
+ * omap_clocks_register - register an array of omap_clk
+ * @ocs: pointer to an array of omap_clk to register
+ */
+void __init omap_clocks_register(struct omap_clk oclks[], int cnt)
+{
+        struct omap_clk *c;
+
+        for (c = oclks; c < oclks + cnt; c++) {
+                clkdev_add(&c->lk);
+                if (!__clk_init(NULL, c->lk.clk))
+                        omap2_init_clk_hw_omap_clocks(c->lk.clk);
+        }
+}
+
+/**
  * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
  * @mpurate_ck_name: clk name of the clock to change rate
  *
@@ -596,7 +611,7 @@ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name)
                 return -ENOENT;
 
         r = clk_set_rate(mpurate_ck, mpurate);
-        if (IS_ERR_VALUE(r)) {
+        if (r < 0) {
                 WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
                      mpurate_ck_name, mpurate, r);
                 clk_put(mpurate_ck);
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 60ddd8612b4d..7aa32cd292f9 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -27,9 +27,8 @@ struct omap_clk {
         struct clk_lookup               lk;
 };
 
-#define CLK(dev, con, ck, cp)           \
+#define CLK(dev, con, ck)               \
         {                               \
-                 .cpu = cp,             \
                 .lk = {                 \
                         .dev_id = dev,  \
                         .con_id = con,  \
@@ -37,22 +36,6 @@ struct omap_clk {
                 },                      \
         }
 
-/* Platform flags for the clkdev-OMAP integration code */
-#define CK_242X         (1 << 0)
-#define CK_243X         (1 << 1)        /* 243x, 253x */
-#define CK_3430ES1      (1 << 2)        /* 34xxES1 only */
-#define CK_3430ES2PLUS  (1 << 3)        /* 34xxES2, ES3, non-Sitara 35xx only */
-#define CK_AM35XX       (1 << 4)        /* Sitara AM35xx */
-#define CK_36XX         (1 << 5)        /* 36xx/37xx-specific clocks */
-#define CK_443X         (1 << 6)
-#define CK_TI816X       (1 << 7)
-#define CK_446X         (1 << 8)
-#define CK_AM33XX       (1 << 9)        /* AM33xx specific clocks */
-
-
-#define CK_34XX         (CK_3430ES1 | CK_3430ES2PLUS)
-#define CK_3XXX         (CK_34XX | CK_AM35XX | CK_36XX)
-
 struct clockdomain;
 #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
 
@@ -480,4 +463,5 @@ extern int am33xx_clk_init(void);
 extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
 extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
 
+extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
 #endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index d6ba13e1c540..d555cf2459e1 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -82,8 +82,7 @@ extern void omap2_init_common_infrastructure(void);
 extern void omap2_sync32k_timer_init(void);
 extern void omap3_sync32k_timer_init(void);
 extern void omap3_secure_sync32k_timer_init(void);
-extern void omap3_gp_gptimer_timer_init(void);
-extern void omap3_am33xx_gptimer_timer_init(void);
+extern void omap3_gptimer_timer_init(void);
 extern void omap4_local_timer_init(void);
 extern void omap5_realtime_timer_init(void);
 
@@ -110,6 +109,14 @@ void am35xx_init_late(void);
 void ti81xx_init_late(void);
 int omap2_common_pm_late_init(void);
 
+#ifdef CONFIG_SOC_BUS
+void omap_soc_device_init(void);
+#else
+static inline void omap_soc_device_init(void)
+{
+}
+#endif
+
 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
 void omap2xxx_restart(char mode, const char *cmd);
 #else
@@ -249,7 +256,6 @@ extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
 extern int omap4_finish_suspend(unsigned long cpu_state);
 extern void omap4_cpu_resume(void);
 extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
-extern u32 omap4_mpuss_read_prev_context_state(void);
 #else
 static inline int omap4_enter_lowpower(unsigned int cpu,
                                         unsigned int power_state)
@@ -277,10 +283,6 @@ static inline int omap4_finish_suspend(unsigned long cpu_state)
 static inline void omap4_cpu_resume(void)
 {}
 
-static inline u32 omap4_mpuss_read_prev_context_state(void)
-{
-        return 0;
-}
 #endif
 
 struct omap_sdrc_params;
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 80392fca86c6..e18709d3b95d 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -26,6 +26,7 @@
 #include <linux/cpuidle.h>
 #include <linux/export.h>
 #include <linux/cpu_pm.h>
+#include <asm/cpuidle.h>
 
 #include "powerdomain.h"
 #include "clockdomain.h"
@@ -99,16 +100,18 @@ static struct omap3_idle_statedata omap3_idle_data[] = {
         },
 };
 
-/* Private functions */
-
-static int __omap3_enter_idle(struct cpuidle_device *dev,
-                                struct cpuidle_driver *drv,
-                                int index)
+/**
+ * omap3_enter_idle - Programs OMAP3 to enter the specified state
+ * @dev: cpuidle device
+ * @drv: cpuidle driver
+ * @index: the index of state to be entered
+ */
+static int omap3_enter_idle(struct cpuidle_device *dev,
+                            struct cpuidle_driver *drv,
+                            int index)
 {
         struct omap3_idle_statedata *cx = &omap3_idle_data[index];
 
-        local_fiq_disable();
-
         if (omap_irq_pending() || need_resched())
                 goto return_sleep_time;
 
@@ -143,28 +146,11 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
                 clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
 
 return_sleep_time:
-        local_fiq_enable();
 
         return index;
 }
 
 /**
- * omap3_enter_idle - Programs OMAP3 to enter the specified state
- * @dev: cpuidle device
- * @drv: cpuidle driver
- * @index: the index of state to be entered
- *
- * Called from the CPUidle framework to program the device to the
- * specified target state selected by the governor.
- */
-static inline int omap3_enter_idle(struct cpuidle_device *dev,
-                                struct cpuidle_driver *drv,
-                                int index)
-{
-        return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
-}
-
-/**
  * next_valid_state - Find next valid C-state
  * @dev: cpuidle device
  * @drv: cpuidle driver
@@ -271,11 +257,9 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
         return ret;
 }
 
-static DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
-
 static struct cpuidle_driver omap3_idle_driver = {
-        .name =         "omap3_idle",
-        .owner =        THIS_MODULE,
+        .name             = "omap3_idle",
+        .owner            = THIS_MODULE,
         .states = {
                 {
                         .enter            = omap3_enter_idle_bm,
@@ -348,8 +332,6 @@ static struct cpuidle_driver omap3_idle_driver = {
  */
 int __init omap3_idle_init(void)
 {
-        struct cpuidle_device *dev;
-
         mpu_pd = pwrdm_lookup("mpu_pwrdm");
         core_pd = pwrdm_lookup("core_pwrdm");
         per_pd = pwrdm_lookup("per_pwrdm");
@@ -358,16 +340,5 @@ int __init omap3_idle_init(void)
         if (!mpu_pd || !core_pd || !per_pd || !cam_pd)
                 return -ENODEV;
 
-        cpuidle_register_driver(&omap3_idle_driver);
-
-        dev = &per_cpu(omap3_idle_dev, smp_processor_id());
-        dev->cpu = 0;
-
-        if (cpuidle_register_device(dev)) {
-                printk(KERN_ERR "%s: CPUidle register device failed\n",
-                       __func__);
-                return -EIO;
-        }
-
-        return 0;
+        return cpuidle_register(&omap3_idle_driver, NULL);
 }
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index d639aef0deda..c443f2e97e10 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -1,7 +1,7 @@
 /*
- * OMAP4 CPU idle Routines
+ * OMAP4+ CPU idle Routines
  *
- * Copyright (C) 2011 Texas Instruments, Inc.
+ * Copyright (C) 2011-2013 Texas Instruments, Inc.
  * Santosh Shilimkar <santosh.shilimkar@ti.com>
  * Rajendra Nayak <rnayak@ti.com>
  *
@@ -14,8 +14,8 @@
 #include <linux/cpuidle.h>
 #include <linux/cpu_pm.h>
 #include <linux/export.h>
-#include <linux/clockchips.h>
 
+#include <asm/cpuidle.h>
 #include <asm/proc-fns.h>
 
 #include "common.h"
@@ -24,13 +24,13 @@
 #include "clockdomain.h"
 
 /* Machine specific information */
-struct omap4_idle_statedata {
+struct idle_statedata {
         u32 cpu_state;
         u32 mpu_logic_state;
         u32 mpu_state;
 };
 
-static struct omap4_idle_statedata omap4_idle_data[] = {
+static struct idle_statedata omap4_idle_data[] = {
         {
                 .cpu_state = PWRDM_POWER_ON,
                 .mpu_state = PWRDM_POWER_ON,
@@ -53,11 +53,12 @@ static struct clockdomain *cpu_clkdm[NR_CPUS];
 
 static atomic_t abort_barrier;
 static bool cpu_done[NR_CPUS];
+static struct idle_statedata *state_ptr = &omap4_idle_data[0];
 
 /* Private functions */
 
 /**
- * omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions
+ * omap_enter_idle_[simple/coupled] - OMAP4PLUS cpuidle entry functions
  * @dev: cpuidle device
  * @drv: cpuidle driver
  * @index: the index of state to be entered
@@ -66,25 +67,19 @@ static bool cpu_done[NR_CPUS];
  * specified low power state selected by the governor.
  * Returns the amount of time spent in the low power state.
  */
-static int omap4_enter_idle_simple(struct cpuidle_device *dev,
+static int omap_enter_idle_simple(struct cpuidle_device *dev,
                         struct cpuidle_driver *drv,
                         int index)
 {
-        local_fiq_disable();
         omap_do_wfi();
-        local_fiq_enable();
-
         return index;
 }
 
-static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
+static int omap_enter_idle_coupled(struct cpuidle_device *dev,
                         struct cpuidle_driver *drv,
                         int index)
 {
-        struct omap4_idle_statedata *cx = &omap4_idle_data[index];
-        int cpu_id = smp_processor_id();
-
-        local_fiq_disable();
+        struct idle_statedata *cx = state_ptr + index;
 
         /*
          * CPU0 has to wait and stay ON until CPU1 is OFF state.
@@ -109,8 +104,6 @@ static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
                 }
         }
 
-        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
-
         /*
          * Call idle CPU PM enter notifier chain so that
          * VFP and per CPU interrupt context is saved.
@@ -136,6 +129,7 @@ static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
         /* Wakeup CPU1 only if it is not offlined */
         if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
                 clkdm_wakeup(cpu_clkdm[1]);
+                omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON);
                 clkdm_allow_idle(cpu_clkdm[1]);
         }
 
@@ -149,63 +143,49 @@ static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
          * Call idle CPU cluster PM exit notifier chain
          * to restore GIC and wakeupgen context.
          */
-        if (omap4_mpuss_read_prev_context_state())
+        if ((cx->mpu_state == PWRDM_POWER_RET) &&
+                (cx->mpu_logic_state == PWRDM_POWER_OFF))
                 cpu_cluster_pm_exit();
 
-        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
-
 fail:
         cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
         cpu_done[dev->cpu] = false;
 
-        local_fiq_enable();
-
         return index;
 }
 
-/*
- * For each cpu, setup the broadcast timer because local timers
- * stops for the states above C1.
- */
-static void omap_setup_broadcast_timer(void *arg)
-{
-        int cpu = smp_processor_id();
-        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
-}
-
-static DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
-
 static struct cpuidle_driver omap4_idle_driver = {
         .name                           = "omap4_idle",
         .owner                          = THIS_MODULE,
-        .en_core_tk_irqen               = 1,
         .states = {
                 {
                         /* C1 - CPU0 ON + CPU1 ON + MPU ON */
                         .exit_latency = 2 + 2,
                         .target_residency = 5,
                         .flags = CPUIDLE_FLAG_TIME_VALID,
-                        .enter = omap4_enter_idle_simple,
+                        .enter = omap_enter_idle_simple,
                         .name = "C1",
-                        .desc = "MPUSS ON"
+                        .desc = "CPUx ON, MPUSS ON"
                 },
                 {
                         /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
                         .exit_latency = 328 + 440,
                         .target_residency = 960,
-                        .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
-                        .enter = omap4_enter_idle_coupled,
+                        .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED |
+                                 CPUIDLE_FLAG_TIMER_STOP,
+                        .enter = omap_enter_idle_coupled,
                         .name = "C2",
-                        .desc = "MPUSS CSWR",
+                        .desc = "CPUx OFF, MPUSS CSWR",
                 },
                 {
                         /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
                         .exit_latency = 460 + 518,
                         .target_residency = 1100,
-                        .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
-                        .enter = omap4_enter_idle_coupled,
+                        .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED |
+                                 CPUIDLE_FLAG_TIMER_STOP,
+                        .enter = omap_enter_idle_coupled,
                         .name = "C3",
-                        .desc = "MPUSS OSWR",
+                        .desc = "CPUx OFF, MPUSS OSWR",
                 },
         },
         .state_count = ARRAY_SIZE(omap4_idle_data),
@@ -215,16 +195,13 @@ static struct cpuidle_driver omap4_idle_driver = {
 /* Public functions */
 
 /**
- * omap4_idle_init - Init routine for OMAP4 idle
+ * omap4_idle_init - Init routine for OMAP4+ idle
  *
- * Registers the OMAP4 specific cpuidle driver to the cpuidle
+ * Registers the OMAP4+ specific cpuidle driver to the cpuidle
  * framework with the valid set of states.
  */
 int __init omap4_idle_init(void)
 {
-        struct cpuidle_device *dev;
-        unsigned int cpu_id = 0;
-
         mpu_pd = pwrdm_lookup("mpu_pwrdm");
         cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
         cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
@@ -236,22 +213,5 @@ int __init omap4_idle_init(void)
         if (!cpu_clkdm[0] || !cpu_clkdm[1])
                 return -ENODEV;
 
-        /* Configure the broadcast timer on each cpu */
-        on_each_cpu(omap_setup_broadcast_timer, NULL, 1);
-
-        for_each_cpu(cpu_id, cpu_online_mask) {
-                dev = &per_cpu(omap4_idle_dev, cpu_id);
-                dev->cpu = cpu_id;
-#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
-                dev->coupled_cpus = *cpu_online_mask;
-#endif
-                cpuidle_register_driver(&omap4_idle_driver);
-
-                if (cpuidle_register_device(dev)) {
-                        pr_err("%s: CPUidle register failed\n", __func__);
-                        return -EIO;
-                }
-        }
-
-        return 0;
+        return cpuidle_register(&omap4_idle_driver, cpu_online_mask);
 }
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 1ec7f0597710..4269fc145698 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -504,140 +504,31 @@ static void omap_init_rng(void)
         WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
 }
 
-#if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
-
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_sham_resources[] = {
-        {
-                .start  = OMAP24XX_SEC_SHA1MD5_BASE,
-                .end    = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = 51 + OMAP_INTC_START,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
-#else
-#define omap2_sham_resources            NULL
-#define omap2_sham_resources_sz         0
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_sham_resources[] = {
-        {
-                .start  = OMAP34XX_SEC_SHA1MD5_BASE,
-                .end    = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = 49 + OMAP_INTC_START,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = OMAP34XX_DMA_SHA1MD5_RX,
-                .flags  = IORESOURCE_DMA,
-        }
-};
-static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
-#else
-#define omap3_sham_resources            NULL
-#define omap3_sham_resources_sz         0
-#endif
-
-static struct platform_device sham_device = {
-        .name           = "omap-sham",
-        .id             = -1,
-};
-
-static void omap_init_sham(void)
+static void __init omap_init_sham(void)
 {
-        if (cpu_is_omap24xx()) {
-                sham_device.resource = omap2_sham_resources;
-                sham_device.num_resources = omap2_sham_resources_sz;
-        } else if (cpu_is_omap34xx()) {
-                sham_device.resource = omap3_sham_resources;
-                sham_device.num_resources = omap3_sham_resources_sz;
-        } else {
-                pr_err("%s: platform not supported\n", __func__);
-                return;
-        }
-        platform_device_register(&sham_device);
-}
-#else
-static inline void omap_init_sham(void) { }
-#endif
-
-#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
-
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_aes_resources[] = {
-        {
-                .start  = OMAP24XX_SEC_AES_BASE,
-                .end    = OMAP24XX_SEC_AES_BASE + 0x4C,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = OMAP24XX_DMA_AES_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        {
-                .start  = OMAP24XX_DMA_AES_RX,
-                .flags  = IORESOURCE_DMA,
-        }
-};
-static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
-#else
-#define omap2_aes_resources             NULL
-#define omap2_aes_resources_sz          0
-#endif
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
 
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_aes_resources[] = {
-        {
-                .start  = OMAP34XX_SEC_AES_BASE,
-                .end    = OMAP34XX_SEC_AES_BASE + 0x4C,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = OMAP34XX_DMA_AES2_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        {
-                .start  = OMAP34XX_DMA_AES2_RX,
-                .flags  = IORESOURCE_DMA,
-        }
-};
-static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
-#else
-#define omap3_aes_resources             NULL
-#define omap3_aes_resources_sz          0
-#endif
+        oh = omap_hwmod_lookup("sham");
+        if (!oh)
+                return;
 
-static struct platform_device aes_device = {
-        .name           = "omap-aes",
-        .id             = -1,
-};
+        pdev = omap_device_build("omap-sham", -1, oh, NULL, 0);
+        WARN(IS_ERR(pdev), "Can't build omap_device for omap-sham\n");
+}
 
-static void omap_init_aes(void)
+static void __init omap_init_aes(void)
 {
-        if (cpu_is_omap24xx()) {
-                aes_device.resource = omap2_aes_resources;
-                aes_device.num_resources = omap2_aes_resources_sz;
-        } else if (cpu_is_omap34xx()) {
-                aes_device.resource = omap3_aes_resources;
-                aes_device.num_resources = omap3_aes_resources_sz;
-        } else {
-                pr_err("%s: platform not supported\n", __func__);
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
+
+        oh = omap_hwmod_lookup("aes");
+        if (!oh)
                 return;
-        }
-        platform_device_register(&aes_device);
-}
 
-#else
-static inline void omap_init_aes(void) { }
-#endif
+        pdev = omap_device_build("omap-aes", -1, oh, NULL, 0);
+        WARN(IS_ERR(pdev), "Can't build omap_device for omap-aes\n");
+}
 
 /*-------------------------------------------------------------------------*/
 
@@ -764,11 +655,11 @@ static int __init omap2_init_devices(void)
                 omap_init_dmic();
                 omap_init_mcpdm();
                 omap_init_mcspi();
+                omap_init_sham();
+                omap_init_aes();
         }
         omap_init_sti();
         omap_init_rng();
-        omap_init_sham();
-        omap_init_aes();
         omap_init_vout();
         omap_init_ocp2scp();
 
diff --git a/arch/arm/mach-omap2/dma.h b/arch/arm/mach-omap2/dma.h
index eba80dbc5218..65f80cacf178 100644
--- a/arch/arm/mach-omap2/dma.h
+++ b/arch/arm/mach-omap2/dma.h
@@ -22,69 +22,20 @@
 
 /* DMA channels for 24xx */
 #define OMAP24XX_DMA_NO_DEVICE          0
-#define OMAP24XX_DMA_XTI_DMA            1       /* S_DMA_0 */
 #define OMAP24XX_DMA_EXT_DMAREQ0        2       /* S_DMA_1 */
 #define OMAP24XX_DMA_EXT_DMAREQ1        3       /* S_DMA_2 */
 #define OMAP24XX_DMA_GPMC               4       /* S_DMA_3 */
-#define OMAP24XX_DMA_GFX                5       /* S_DMA_4 */
-#define OMAP24XX_DMA_DSS                6       /* S_DMA_5 */
-#define OMAP242X_DMA_VLYNQ_TX           7       /* S_DMA_6 */
-#define OMAP24XX_DMA_EXT_DMAREQ2        7       /* S_DMA_6 */
-#define OMAP24XX_DMA_CWT                8       /* S_DMA_7 */
 #define OMAP24XX_DMA_AES_TX             9       /* S_DMA_8 */
 #define OMAP24XX_DMA_AES_RX             10      /* S_DMA_9 */
-#define OMAP24XX_DMA_DES_TX             11      /* S_DMA_10 */
-#define OMAP24XX_DMA_DES_RX             12      /* S_DMA_11 */
-#define OMAP24XX_DMA_SHA1MD5_RX         13      /* S_DMA_12 */
-#define OMAP34XX_DMA_SHA2MD5_RX         13      /* S_DMA_12 */
 #define OMAP242X_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
 #define OMAP242X_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
 #define OMAP242X_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
-#define OMAP242X_DMA_EAC_AC_RD          17      /* S_DMA_16 */
-#define OMAP242X_DMA_EAC_AC_WR          18      /* S_DMA_17 */
-#define OMAP242X_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
-#define OMAP242X_DMA_EAC_MD_UL_WR       20      /* S_DMA_19 */
-#define OMAP242X_DMA_EAC_MD_DL_RD       21      /* S_DMA_20 */
-#define OMAP242X_DMA_EAC_MD_DL_WR       22      /* S_DMA_21 */
-#define OMAP242X_DMA_EAC_BT_UL_RD       23      /* S_DMA_22 */
-#define OMAP242X_DMA_EAC_BT_UL_WR       24      /* S_DMA_23 */
-#define OMAP242X_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
-#define OMAP242X_DMA_EAC_BT_DL_WR       26      /* S_DMA_25 */
-#define OMAP243X_DMA_EXT_DMAREQ3        14      /* S_DMA_13 */
-#define OMAP24XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
-#define OMAP24XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
-#define OMAP24XX_DMA_MCBSP3_TX          17      /* S_DMA_16 */
-#define OMAP24XX_DMA_MCBSP3_RX          18      /* S_DMA_17 */
-#define OMAP24XX_DMA_MCBSP4_TX          19      /* S_DMA_18 */
-#define OMAP24XX_DMA_MCBSP4_RX          20      /* S_DMA_19 */
-#define OMAP24XX_DMA_MCBSP5_TX          21      /* S_DMA_20 */
-#define OMAP24XX_DMA_MCBSP5_RX          22      /* S_DMA_21 */
-#define OMAP24XX_DMA_SPI3_TX1           23      /* S_DMA_22 */
-#define OMAP24XX_DMA_SPI3_RX1           24      /* S_DMA_23 */
-#define OMAP243X_DMA_EXT_DMAREQ4        25      /* S_DMA_24 */
-#define OMAP243X_DMA_EXT_DMAREQ5        26      /* S_DMA_25 */
 #define OMAP34XX_DMA_I2C3_TX            25      /* S_DMA_24 */
 #define OMAP34XX_DMA_I2C3_RX            26      /* S_DMA_25 */
 #define OMAP24XX_DMA_I2C1_TX            27      /* S_DMA_26 */
 #define OMAP24XX_DMA_I2C1_RX            28      /* S_DMA_27 */
 #define OMAP24XX_DMA_I2C2_TX            29      /* S_DMA_28 */
 #define OMAP24XX_DMA_I2C2_RX            30      /* S_DMA_29 */
-#define OMAP24XX_DMA_MCBSP1_TX          31      /* S_DMA_30 */
-#define OMAP24XX_DMA_MCBSP1_RX          32      /* S_DMA_31 */
-#define OMAP24XX_DMA_MCBSP2_TX          33      /* S_DMA_32 */
-#define OMAP24XX_DMA_MCBSP2_RX          34      /* S_DMA_33 */
-#define OMAP24XX_DMA_SPI1_TX0           35      /* S_DMA_34 */
-#define OMAP24XX_DMA_SPI1_RX0           36      /* S_DMA_35 */
-#define OMAP24XX_DMA_SPI1_TX1           37      /* S_DMA_36 */
-#define OMAP24XX_DMA_SPI1_RX1           38      /* S_DMA_37 */
-#define OMAP24XX_DMA_SPI1_TX2           39      /* S_DMA_38 */
-#define OMAP24XX_DMA_SPI1_RX2           40      /* S_DMA_39 */
-#define OMAP24XX_DMA_SPI1_TX3           41      /* S_DMA_40 */
-#define OMAP24XX_DMA_SPI1_RX3           42      /* S_DMA_41 */
-#define OMAP24XX_DMA_SPI2_TX0           43      /* S_DMA_42 */
-#define OMAP24XX_DMA_SPI2_RX0           44      /* S_DMA_43 */
-#define OMAP24XX_DMA_SPI2_TX1           45      /* S_DMA_44 */
-#define OMAP24XX_DMA_SPI2_RX1           46      /* S_DMA_45 */
 #define OMAP24XX_DMA_MMC2_TX            47      /* S_DMA_46 */
 #define OMAP24XX_DMA_MMC2_RX            48      /* S_DMA_47 */
 #define OMAP24XX_DMA_UART1_TX           49      /* S_DMA_48 */
@@ -93,33 +44,12 @@
 #define OMAP24XX_DMA_UART2_RX           52      /* S_DMA_51 */
 #define OMAP24XX_DMA_UART3_TX           53      /* S_DMA_52 */
 #define OMAP24XX_DMA_UART3_RX           54      /* S_DMA_53 */
-#define OMAP24XX_DMA_USB_W2FC_TX0       55      /* S_DMA_54 */
-#define OMAP24XX_DMA_USB_W2FC_RX0       56      /* S_DMA_55 */
-#define OMAP24XX_DMA_USB_W2FC_TX1       57      /* S_DMA_56 */
-#define OMAP24XX_DMA_USB_W2FC_RX1       58      /* S_DMA_57 */
-#define OMAP24XX_DMA_USB_W2FC_TX2       59      /* S_DMA_58 */
-#define OMAP24XX_DMA_USB_W2FC_RX2       60      /* S_DMA_59 */
 #define OMAP24XX_DMA_MMC1_TX            61      /* S_DMA_60 */
 #define OMAP24XX_DMA_MMC1_RX            62      /* S_DMA_61 */
-#define OMAP24XX_DMA_MS                 63      /* S_DMA_62 */
 #define OMAP242X_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
-#define OMAP243X_DMA_EXT_DMAREQ6        64      /* S_DMA_63 */
-#define OMAP34XX_DMA_EXT_DMAREQ3        64      /* S_DMA_63 */
 #define OMAP34XX_DMA_AES2_TX            65      /* S_DMA_64 */
 #define OMAP34XX_DMA_AES2_RX            66      /* S_DMA_65 */
-#define OMAP34XX_DMA_DES2_TX            67      /* S_DMA_66 */
-#define OMAP34XX_DMA_DES2_RX            68      /* S_DMA_67 */
 #define OMAP34XX_DMA_SHA1MD5_RX         69      /* S_DMA_68 */
-#define OMAP34XX_DMA_SPI4_TX0           70      /* S_DMA_69 */
-#define OMAP34XX_DMA_SPI4_RX0           71      /* S_DMA_70 */
-#define OMAP34XX_DSS_DMA0               72      /* S_DMA_71 */
-#define OMAP34XX_DSS_DMA1               73      /* S_DMA_72 */
-#define OMAP34XX_DSS_DMA2               74      /* S_DMA_73 */
-#define OMAP34XX_DSS_DMA3               75      /* S_DMA_74 */
-#define OMAP34XX_DMA_MMC3_TX            77      /* S_DMA_76 */
-#define OMAP34XX_DMA_MMC3_RX            78      /* S_DMA_77 */
-#define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
-#define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
 
 #define OMAP36XX_DMA_UART4_TX           81      /* S_DMA_80 */
 #define OMAP36XX_DMA_UART4_RX           82      /* S_DMA_81 */
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 3aed4b0b9563..3a0296cfcace 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -307,10 +307,10 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
         _omap3_noncore_dpll_bypass(clk);
 
         /*
-         * Set jitter correction. No jitter correction for OMAP4 and 3630
-         * since freqsel field is no longer present
+         * Set jitter correction. Jitter correction applicable for OMAP343X
+         * only since freqsel field is no longer present on other devices.
          */
-        if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
+        if (cpu_is_omap343x()) {
                 v = __raw_readl(dd->control_reg);
                 v &= ~dd->freqsel_mask;
                 v |= freqsel << __ffs(dd->freqsel_mask);
@@ -480,29 +480,30 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
         if (!dd)
                 return -EINVAL;
 
-        __clk_prepare(dd->clk_bypass);
-        clk_enable(dd->clk_bypass);
-        __clk_prepare(dd->clk_ref);
-        clk_enable(dd->clk_ref);
-
         if (__clk_get_rate(dd->clk_bypass) == rate &&
             (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
                 pr_debug("%s: %s: set rate: entering bypass.\n",
                          __func__, __clk_get_name(hw->clk));
 
+                __clk_prepare(dd->clk_bypass);
+                clk_enable(dd->clk_bypass);
                 ret = _omap3_noncore_dpll_bypass(clk);
                 if (!ret)
                         new_parent = dd->clk_bypass;
+                clk_disable(dd->clk_bypass);
+                __clk_unprepare(dd->clk_bypass);
         } else {
+                __clk_prepare(dd->clk_ref);
+                clk_enable(dd->clk_ref);
+
                 if (dd->last_rounded_rate != rate)
                         rate = __clk_round_rate(hw->clk, rate);
 
                 if (dd->last_rounded_rate == 0)
                         return -EINVAL;
 
-                /* No freqsel on AM335x, OMAP4 and OMAP3630 */
-                if (!soc_is_am33xx() && !cpu_is_omap44xx() &&
-                    !cpu_is_omap3630()) {
+                /* Freqsel is available only on OMAP343X devices */
+                if (cpu_is_omap343x()) {
                         freqsel = _omap3_dpll_compute_freqsel(clk,
                                                 dd->last_rounded_n);
                         WARN_ON(!freqsel);
@@ -514,6 +515,8 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
                 ret = omap3_noncore_dpll_program(clk, freqsel);
                 if (!ret)
                         new_parent = dd->clk_ref;
+                clk_disable(dd->clk_ref);
+                __clk_unprepare(dd->clk_ref);
         }
         /*
         * FIXME - this is all wrong.  common code handles reparenting and
@@ -525,11 +528,6 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
         if (!ret)
                 __clk_reparent(hw->clk, new_parent);
 
-        clk_disable(dd->clk_ref);
-        __clk_unprepare(dd->clk_ref);
-        clk_disable(dd->clk_bypass);
-        __clk_unprepare(dd->clk_bypass);
-
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index b155500e84a8..b8208b4b1bd9 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -26,7 +26,7 @@
 #include "control.h"
 #include "cm2xxx_3xxx.h"
 #include "prm2xxx_3xxx.h"
-#ifdef CONFIG_BRIDGE_DVFS
+#ifdef CONFIG_TIDSPBRIDGE_DVFS
 #include "omap-pm.h"
 #endif
 
@@ -35,7 +35,7 @@
 static struct platform_device *omap_dsp_pdev;
 
 static struct omap_dsp_platform_data omap_dsp_pdata __initdata = {
-#ifdef CONFIG_BRIDGE_DVFS
+#ifdef CONFIG_TIDSPBRIDGE_DVFS
         .dsp_set_min_opp = omap_pm_dsp_set_min_opp,
         .dsp_get_opp = omap_pm_dsp_get_opp,
         .cpu_set_freq = omap_pm_cpu_set_freq,
diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c
index 4be5cfc81ab8..9c49bbe825f7 100644
--- a/arch/arm/mach-omap2/dss-common.c
+++ b/arch/arm/mach-omap2/dss-common.c
@@ -27,9 +27,7 @@
 #include <linux/gpio.h>
 
 #include <video/omapdss.h>
-#include <video/omap-panel-tfp410.h>
-#include <video/omap-panel-nokia-dsi.h>
-#include <video/omap-panel-picodlp.h>
+#include <video/omap-panel-data.h>
 
 #include "soc.h"
 #include "dss-common.h"
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index afc1e8c32d6c..d9c27195caf0 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -74,14 +74,6 @@ static int omap2_nand_gpmc_retime(
         t.cs_wr_off = gpmc_t->cs_wr_off;
         t.wr_cycle = gpmc_t->wr_cycle;
 
-        /* Configure GPMC */
-        if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
-                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);
-        else
-                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
-        gpmc_cs_configure(gpmc_nand_data->cs,
-                        GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
-        gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_WP, 0);
         err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
         if (err)
                 return err;
@@ -115,14 +107,18 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
                    struct gpmc_timings *gpmc_t)
 {
         int err = 0;
+        struct gpmc_settings s;
         struct device *dev = &gpmc_nand_device.dev;
 
+        memset(&s, 0, sizeof(struct gpmc_settings));
+
         gpmc_nand_device.dev.platform_data = gpmc_nand_data;
 
         err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
                                 (unsigned long *)&gpmc_nand_resource[0].start);
         if (err < 0) {
-                dev_err(dev, "Cannot request GPMC CS\n");
+                dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
+                        gpmc_nand_data->cs, err);
                 return err;
         }
 
@@ -140,11 +136,31 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
                         dev_err(dev, "Unable to set gpmc timings: %d\n", err);
                         return err;
                 }
-        }
 
-        /* Enable RD PIN Monitoring Reg */
-        if (gpmc_nand_data->dev_ready) {
-                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1);
+                if (gpmc_nand_data->of_node) {
+                        gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
+                } else {
+                        s.device_nand = true;
+
+                        /* Enable RD PIN Monitoring Reg */
+                        if (gpmc_nand_data->dev_ready) {
+                                s.wait_on_read = true;
+                                s.wait_on_write = true;
+                        }
+                }
+
+                if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
+                        s.device_width = GPMC_DEVWIDTH_16BIT;
+                else
+                        s.device_width = GPMC_DEVWIDTH_8BIT;
+
+                err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
+                if (err < 0)
+                        goto out_free_cs;
+
+                err = gpmc_configure(GPMC_CONFIG_WP, 0);
+                if (err < 0)
+                        goto out_free_cs;
         }
 
         gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index fadd87435cd0..64b5a8346982 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -47,11 +47,23 @@ static struct platform_device gpmc_onenand_device = {
         .resource       = &gpmc_onenand_resource,
 };
 
-static struct gpmc_timings omap2_onenand_calc_async_timings(void)
+static struct gpmc_settings onenand_async = {
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+};
+
+static struct gpmc_settings onenand_sync = {
+        .burst_read     = true,
+        .burst_wrap     = true,
+        .burst_len      = GPMC_BURST_16,
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+        .wait_pin       = 0,
+};
+
+static void omap2_onenand_calc_async_timings(struct gpmc_timings *t)
 {
         struct gpmc_device_timings dev_t;
-        struct gpmc_timings t;
-
         const int t_cer = 15;
         const int t_avdp = 12;
         const int t_aavdh = 7;
@@ -64,7 +76,6 @@ static struct gpmc_timings omap2_onenand_calc_async_timings(void)
 
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
         dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
         dev_t.t_avdp_w = dev_t.t_avdp_r;
         dev_t.t_aavdh = t_aavdh * 1000;
@@ -76,19 +87,7 @@ static struct gpmc_timings omap2_onenand_calc_async_timings(void)
         dev_t.t_wpl = t_wpl * 1000;
         dev_t.t_wph = t_wph * 1000;
 
-        gpmc_calc_timings(&t, &dev_t);
-
-        return t;
-}
-
-static int gpmc_set_async_mode(int cs, struct gpmc_timings *t)
-{
-        /* Configure GPMC for asynchronous read */
-        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_DEVICESIZE_16 |
-                          GPMC_CONFIG1_MUXADDDATA);
-
-        return gpmc_cs_set_timings(cs, t);
+        gpmc_calc_timings(t, &onenand_async, &dev_t);
 }
 
 static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
@@ -158,12 +157,11 @@ static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
         return freq;
 }
 
-static struct gpmc_timings
-omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
-                                int freq)
+static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
+                                            unsigned int flags,
+                                            int freq)
 {
         struct gpmc_device_timings dev_t;
-        struct gpmc_timings t;
         const int t_cer  = 15;
         const int t_avdp = 12;
         const int t_cez  = 20; /* max of t_cez, t_oez */
@@ -172,9 +170,9 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
         int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
         int div, gpmc_clk_ns;
 
-        if (cfg->flags & ONENAND_SYNC_READ)
+        if (flags & ONENAND_SYNC_READ)
                 onenand_flags = ONENAND_FLAG_SYNCREAD;
-        else if (cfg->flags & ONENAND_SYNC_READWRITE)
+        else if (flags & ONENAND_SYNC_READWRITE)
                 onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
 
         switch (freq) {
@@ -239,10 +237,11 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
         /* Set synchronous read timings */
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
-        dev_t.sync_read = true;
+        if (onenand_flags & ONENAND_FLAG_SYNCREAD)
+                onenand_sync.sync_read = true;
         if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
-                dev_t.sync_write = true;
+                onenand_sync.sync_write = true;
+                onenand_sync.burst_write = true;
         } else {
                 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
                 dev_t.t_wpl = t_wpl * 1000;
@@ -265,32 +264,7 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,
         dev_t.cyc_aavdh_oe = 1;
         dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
 
-        gpmc_calc_timings(&t, &dev_t);
-
-        return t;
-}
-
-static int gpmc_set_sync_mode(int cs, struct gpmc_timings *t)
-{
-        unsigned sync_read = onenand_flags & ONENAND_FLAG_SYNCREAD;
-        unsigned sync_write = onenand_flags & ONENAND_FLAG_SYNCWRITE;
-
-        /* Configure GPMC for synchronous read */
-        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_WRAPBURST_SUPP |
-                          GPMC_CONFIG1_READMULTIPLE_SUPP |
-                          (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |
-                          (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
-                          (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
-                          GPMC_CONFIG1_PAGE_LEN(2) |
-                          (cpu_is_omap34xx() ? 0 :
-                                (GPMC_CONFIG1_WAIT_READ_MON |
-                                 GPMC_CONFIG1_WAIT_PIN_SEL(0))) |
-                          GPMC_CONFIG1_DEVICESIZE_16 |
-                          GPMC_CONFIG1_DEVICETYPE_NOR |
-                          GPMC_CONFIG1_MUXADDDATA);
-
-        return gpmc_cs_set_timings(cs, t);
+        gpmc_calc_timings(t, &onenand_sync, &dev_t);
 }
 
 static int omap2_onenand_setup_async(void __iomem *onenand_base)
@@ -298,12 +272,20 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base)
         struct gpmc_timings t;
         int ret;
 
+        if (gpmc_onenand_data->of_node)
+                gpmc_read_settings_dt(gpmc_onenand_data->of_node,
+                                      &onenand_async);
+
         omap2_onenand_set_async_mode(onenand_base);
 
-        t = omap2_onenand_calc_async_timings();
+        omap2_onenand_calc_async_timings(&t);
+
+        ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
+        if (ret < 0)
+                return ret;
 
-        ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t);
-        if (IS_ERR_VALUE(ret))
+        ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
+        if (ret < 0)
                 return ret;
 
         omap2_onenand_set_async_mode(onenand_base);
@@ -322,10 +304,26 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
                 set_onenand_cfg(onenand_base);
         }
 
-        t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq);
+        if (gpmc_onenand_data->of_node) {
+                gpmc_read_settings_dt(gpmc_onenand_data->of_node,
+                                      &onenand_sync);
+        } else {
+                /*
+                 * FIXME: Appears to be legacy code from initial ONENAND commit.
+                 * Unclear what boards this is for and if this can be removed.
+                 */
+                if (!cpu_is_omap34xx())
+                        onenand_sync.wait_on_read = true;
+        }
+
+        omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);
 
-        ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t);
-        if (IS_ERR_VALUE(ret))
+        ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync);
+        if (ret < 0)
+                return ret;
+
+        ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
+        if (ret < 0)
                 return ret;
 
         set_onenand_cfg(onenand_base);
@@ -359,6 +357,7 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
 void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
 {
         int err;
+        struct device *dev = &gpmc_onenand_device.dev;
 
         gpmc_onenand_data = _onenand_data;
         gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
@@ -366,7 +365,7 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
 
         if (cpu_is_omap24xx() &&
                         (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
-                printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n");
+                dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
                 gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
                 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
         }
@@ -379,7 +378,8 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
         err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
                                 (unsigned long *)&gpmc_onenand_resource.start);
         if (err < 0) {
-                pr_err("%s: Cannot request GPMC CS\n", __func__);
+                dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
+                        gpmc_onenand_data->cs, err);
                 return;
         }
 
@@ -387,7 +387,7 @@ void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
                                                         ONENAND_IO_SIZE - 1;
 
         if (platform_device_register(&gpmc_onenand_device) < 0) {
-                pr_err("%s: Unable to register OneNAND device\n", __func__);
+                dev_err(dev, "Unable to register OneNAND device\n");
                 gpmc_cs_free(gpmc_onenand_data->cs);
                 return;
         }
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index 11d0b756f098..61a063595e66 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -49,6 +49,10 @@ static struct platform_device gpmc_smc91x_device = {
         .resource       = gpmc_smc91x_resources,
 };
 
+static struct gpmc_settings smc91x_settings = {
+        .device_width = GPMC_DEVWIDTH_16BIT,
+};
+
 /*
  * Set the gpmc timings for smc91c96. The timings are taken
  * from the data sheet available at:
@@ -67,18 +71,6 @@ static int smc91c96_gpmc_retime(void)
         const int t7 = 5;       /* Figure 12.4 write */
         const int t8 = 5;       /* Figure 12.4 write */
         const int t20 = 185;    /* Figure 12.2 read and 12.4 write */
-        u32 l;
-
-        l = GPMC_CONFIG1_DEVICESIZE_16;
-        if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
-                l |= GPMC_CONFIG1_MUXADDDATA;
-        if (gpmc_cfg->flags & GPMC_READ_MON)
-                l |= GPMC_CONFIG1_WAIT_READ_MON;
-        if (gpmc_cfg->flags & GPMC_WRITE_MON)
-                l |= GPMC_CONFIG1_WAIT_WRITE_MON;
-        if (gpmc_cfg->wait_pin)
-                l |= GPMC_CONFIG1_WAIT_PIN_SEL(gpmc_cfg->wait_pin);
-        gpmc_cs_write_reg(gpmc_cfg->cs, GPMC_CS_CONFIG1, l);
 
         /*
          * FIXME: Calculate the address and data bus muxed timings.
@@ -104,7 +96,7 @@ static int smc91c96_gpmc_retime(void)
         dev_t.t_cez_w = t4_w * 1000;
         dev_t.t_wr_cycle = (t20 - t3) * 1000;
 
-        gpmc_calc_timings(&t, &dev_t);
+        gpmc_calc_timings(&t, &smc91x_settings, &dev_t);
 
         return gpmc_cs_set_timings(gpmc_cfg->cs, &t);
 }
@@ -133,6 +125,18 @@ void __init gpmc_smc91x_init(struct omap_smc91x_platform_data *board_data)
         gpmc_smc91x_resources[0].end = cs_mem_base + 0x30f;
         gpmc_smc91x_resources[1].flags |= (gpmc_cfg->flags & IRQF_TRIGGER_MASK);
 
+        if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
+                smc91x_settings.mux_add_data = GPMC_MUX_AD;
+        if (gpmc_cfg->flags & GPMC_READ_MON)
+                smc91x_settings.wait_on_read = true;
+        if (gpmc_cfg->flags & GPMC_WRITE_MON)
+                smc91x_settings.wait_on_write = true;
+        if (gpmc_cfg->wait_pin)
+                smc91x_settings.wait_pin = gpmc_cfg->wait_pin;
+        ret = gpmc_cs_program_settings(gpmc_cfg->cs, &smc91x_settings);
+        if (ret < 0)
+                goto free1;
+
         if (gpmc_cfg->retime) {
                 ret = gpmc_cfg->retime();
                 if (ret != 0)
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 410e1bac7815..ed946df5ad8a 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -26,6 +26,7 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/of_mtd.h>
 #include <linux/of_device.h>
 #include <linux/mtd/nand.h>
@@ -91,9 +92,7 @@
 #define GPMC_CS_SIZE            0x30
 #define GPMC_BCH_SIZE           0x10
 
-#define GPMC_MEM_START          0x00000000
 #define GPMC_MEM_END            0x3FFFFFFF
-#define BOOT_ROM_SPACE          0x100000        /* 1MB */
 
 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
@@ -107,6 +106,9 @@
 
 #define GPMC_HAS_WR_ACCESS              0x1
 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
+#define GPMC_HAS_MUX_AAD                0x4
+
+#define GPMC_NR_WAITPINS                4
 
 /* XXX: Only NAND irq has been considered,currently these are the only ones used
  */
@@ -153,6 +155,7 @@ static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
 /* Define chip-selects as reserved by default until probe completes */
 static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
+static unsigned int gpmc_nr_waitpins;
 static struct device *gpmc_dev;
 static int gpmc_irq;
 static resource_size_t phys_base, mem_size;
@@ -181,7 +184,7 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val)
         __raw_writel(val, reg_addr);
 }
 
-u32 gpmc_cs_read_reg(int cs, int idx)
+static u32 gpmc_cs_read_reg(int cs, int idx)
 {
         void __iomem *reg_addr;
 
@@ -190,7 +193,7 @@ u32 gpmc_cs_read_reg(int cs, int idx)
 }
 
 /* TODO: Add support for gpmc_fck to clock framework and use it */
-unsigned long gpmc_get_fclk_period(void)
+static unsigned long gpmc_get_fclk_period(void)
 {
         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 
@@ -205,7 +208,7 @@ unsigned long gpmc_get_fclk_period(void)
         return rate;
 }
 
-unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
+static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 {
         unsigned long tick_ps;
 
@@ -215,7 +218,7 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 }
 
-unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
+static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 {
         unsigned long tick_ps;
 
@@ -230,13 +233,6 @@ unsigned int gpmc_ticks_to_ns(unsigned int ticks)
         return ticks * gpmc_get_fclk_period() / 1000;
 }
 
-unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
-{
-        unsigned long ticks = gpmc_ns_to_ticks(time_ns);
-
-        return ticks * gpmc_get_fclk_period() / 1000;
-}
-
 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 {
         return ticks * gpmc_get_fclk_period();
@@ -405,11 +401,18 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
         return 0;
 }
 
-static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
+static int gpmc_cs_enable_mem(int cs, u32 base, u32 size)
 {
         u32 l;
         u32 mask;
 
+        /*
+         * Ensure that base address is aligned on a
+         * boundary equal to or greater than size.
+         */
+        if (base & (size - 1))
+                return -EINVAL;
+
         mask = (1 << GPMC_SECTION_SHIFT) - size;
         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
         l &= ~0x3f;
@@ -418,6 +421,8 @@ static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
         l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
         l |= GPMC_CONFIG7_CSVALID;
         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
+
+        return 0;
 }
 
 static void gpmc_cs_disable_mem(int cs)
@@ -448,22 +453,14 @@ static int gpmc_cs_mem_enabled(int cs)
         return l & GPMC_CONFIG7_CSVALID;
 }
 
-int gpmc_cs_set_reserved(int cs, int reserved)
+static void gpmc_cs_set_reserved(int cs, int reserved)
 {
-        if (cs > GPMC_CS_NUM)
-                return -ENODEV;
-
         gpmc_cs_map &= ~(1 << cs);
         gpmc_cs_map |= (reserved ? 1 : 0) << cs;
-
-        return 0;
 }
 
-int gpmc_cs_reserved(int cs)
+static bool gpmc_cs_reserved(int cs)
 {
-        if (cs > GPMC_CS_NUM)
-                return -ENODEV;
-
         return gpmc_cs_map & (1 << cs);
 }
 
@@ -510,6 +507,39 @@ static int gpmc_cs_delete_mem(int cs)
         return r;
 }
 
+/**
+ * gpmc_cs_remap - remaps a chip-select physical base address
+ * @cs:         chip-select to remap
+ * @base:       physical base address to re-map chip-select to
+ *
+ * Re-maps a chip-select to a new physical base address specified by
+ * "base". Returns 0 on success and appropriate negative error code
+ * on failure.
+ */
+static int gpmc_cs_remap(int cs, u32 base)
+{
+        int ret;
+        u32 old_base, size;
+
+        if (cs > GPMC_CS_NUM)
+                return -ENODEV;
+        gpmc_cs_get_memconf(cs, &old_base, &size);
+        if (base == old_base)
+                return 0;
+        gpmc_cs_disable_mem(cs);
+        ret = gpmc_cs_delete_mem(cs);
+        if (ret < 0)
+                return ret;
+        ret = gpmc_cs_insert_mem(cs, base, size);
+        if (ret < 0)
+                return ret;
+        ret = gpmc_cs_enable_mem(cs, base, size);
+        if (ret < 0)
+                return ret;
+
+        return 0;
+}
+
 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 {
         struct resource *res = &gpmc_cs_mem[cs];
@@ -535,7 +565,12 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
         if (r < 0)
                 goto out;
 
-        gpmc_cs_enable_mem(cs, res->start, resource_size(res));
+        r = gpmc_cs_enable_mem(cs, res->start, resource_size(res));
+        if (r < 0) {
+                release_resource(res);
+                goto out;
+        }
+
         *base = res->start;
         gpmc_cs_set_reserved(cs, 1);
 out:
@@ -561,16 +596,14 @@ void gpmc_cs_free(int cs)
 EXPORT_SYMBOL(gpmc_cs_free);
 
 /**
- * gpmc_cs_configure - write request to configure gpmc
- * @cs: chip select number
+ * gpmc_configure - write request to configure gpmc
  * @cmd: command type
  * @wval: value to write
  * @return status of the operation
  */
-int gpmc_cs_configure(int cs, int cmd, int wval)
+int gpmc_configure(int cmd, int wval)
 {
-        int err = 0;
-        u32 regval = 0;
+        u32 regval;
 
         switch (cmd) {
         case GPMC_ENABLE_IRQ:
@@ -590,43 +623,14 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
                 gpmc_write_reg(GPMC_CONFIG, regval);
                 break;
 
-        case GPMC_CONFIG_RDY_BSY:
-                regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-                if (wval)
-                        regval |= WR_RD_PIN_MONITORING;
-                else
-                        regval &= ~WR_RD_PIN_MONITORING;
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
-                break;
-
-        case GPMC_CONFIG_DEV_SIZE:
-                regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-                /* clear 2 target bits */
-                regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
-
-                /* set the proper value */
-                regval |= GPMC_CONFIG1_DEVICESIZE(wval);
-
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
-                break;
-
-        case GPMC_CONFIG_DEV_TYPE:
-                regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-                regval |= GPMC_CONFIG1_DEVICETYPE(wval);
-                if (wval == GPMC_DEVICETYPE_NOR)
-                        regval |= GPMC_CONFIG1_MUXADDDATA;
-                gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
-                break;
-
         default:
-                printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
-                err = -EINVAL;
+                pr_err("%s: command not supported\n", __func__);
+                return -EINVAL;
         }
 
-        return err;
+        return 0;
 }
-EXPORT_SYMBOL(gpmc_cs_configure);
+EXPORT_SYMBOL(gpmc_configure);
 
 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
 {
@@ -716,7 +720,7 @@ static int gpmc_setup_irq(void)
                 return -EINVAL;
 
         gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
-        if (IS_ERR_VALUE(gpmc_irq_start)) {
+        if (gpmc_irq_start < 0) {
                 pr_err("irq_alloc_descs failed\n");
                 return gpmc_irq_start;
         }
@@ -781,16 +785,16 @@ static void gpmc_mem_exit(void)
 
 }
 
-static int gpmc_mem_init(void)
+static void gpmc_mem_init(void)
 {
-        int cs, rc;
-        unsigned long boot_rom_space = 0;
+        int cs;
 
-        /* never allocate the first page, to facilitate bug detection;
-         * even if we didn't boot from ROM.
+        /*
+         * The first 1MB of GPMC address space is typically mapped to
+         * the internal ROM. Never allocate the first page, to
+         * facilitate bug detection; even if we didn't boot from ROM.
          */
-        boot_rom_space = BOOT_ROM_SPACE;
-        gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
+        gpmc_mem_root.start = SZ_1M;
         gpmc_mem_root.end = GPMC_MEM_END;
 
         /* Reserve all regions that has been set up by bootloader */
@@ -800,16 +804,12 @@ static int gpmc_mem_init(void)
                 if (!gpmc_cs_mem_enabled(cs))
                         continue;
                 gpmc_cs_get_memconf(cs, &base, &size);
-                rc = gpmc_cs_insert_mem(cs, base, size);
-                if (IS_ERR_VALUE(rc)) {
-                        while (--cs >= 0)
-                                if (gpmc_cs_mem_enabled(cs))
-                                        gpmc_cs_delete_mem(cs);
-                        return rc;
+                if (gpmc_cs_insert_mem(cs, base, size)) {
+                        pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
+                                __func__, cs, base, base + size);
+                        gpmc_cs_disable_mem(cs);
                 }
         }
-
-        return 0;
 }
 
 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
@@ -825,9 +825,9 @@ static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
 
 /* XXX: can the cycles be avoided ? */
 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                       struct gpmc_device_timings *dev_t,
+                                       bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_rd_off */
@@ -880,9 +880,9 @@ static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                        struct gpmc_device_timings *dev_t,
+                                        bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_wr_off */
@@ -942,9 +942,9 @@ static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                        struct gpmc_device_timings *dev_t,
+                                        bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_rd_off */
@@ -982,9 +982,9 @@ static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t)
+                                         struct gpmc_device_timings *dev_t,
+                                         bool mux)
 {
-        bool mux = dev_t->mux;
         u32 temp;
 
         /* adv_wr_off */
@@ -1054,7 +1054,8 @@ static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
 }
 
 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
-                        struct gpmc_device_timings *dev_t)
+                                    struct gpmc_device_timings *dev_t,
+                                    bool sync)
 {
         u32 temp;
 
@@ -1068,7 +1069,7 @@ static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
                                 gpmc_t->cs_on + dev_t->t_ce_avd);
         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
 
-        if (dev_t->sync_write || dev_t->sync_read)
+        if (sync)
                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
 
         return 0;
@@ -1103,21 +1104,29 @@ static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
 }
 
 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
-                        struct gpmc_device_timings *dev_t)
+                      struct gpmc_settings *gpmc_s,
+                      struct gpmc_device_timings *dev_t)
 {
+        bool mux = false, sync = false;
+
+        if (gpmc_s) {
+                mux = gpmc_s->mux_add_data ? true : false;
+                sync = (gpmc_s->sync_read || gpmc_s->sync_write);
+        }
+
         memset(gpmc_t, 0, sizeof(*gpmc_t));
 
-        gpmc_calc_common_timings(gpmc_t, dev_t);
+        gpmc_calc_common_timings(gpmc_t, dev_t, sync);
 
-        if (dev_t->sync_read)
-                gpmc_calc_sync_read_timings(gpmc_t, dev_t);
+        if (gpmc_s && gpmc_s->sync_read)
+                gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
         else
-                gpmc_calc_async_read_timings(gpmc_t, dev_t);
+                gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
 
-        if (dev_t->sync_write)
-                gpmc_calc_sync_write_timings(gpmc_t, dev_t);
+        if (gpmc_s && gpmc_s->sync_write)
+                gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
         else
-                gpmc_calc_async_write_timings(gpmc_t, dev_t);
+                gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
 
         /* TODO: remove, see function definition */
         gpmc_convert_ps_to_ns(gpmc_t);
@@ -1125,6 +1134,90 @@ int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
         return 0;
 }
 
+/**
+ * gpmc_cs_program_settings - programs non-timing related settings
+ * @cs:         GPMC chip-select to program
+ * @p:          pointer to GPMC settings structure
+ *
+ * Programs non-timing related settings for a GPMC chip-select, such as
+ * bus-width, burst configuration, etc. Function should be called once
+ * for each chip-select that is being used and must be called before
+ * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
+ * register will be initialised to zero by this function. Returns 0 on
+ * success and appropriate negative error code on failure.
+ */
+int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
+{
+        u32 config1;
+
+        if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
+                pr_err("%s: invalid width %d!", __func__, p->device_width);
+                return -EINVAL;
+        }
+
+        /* Address-data multiplexing not supported for NAND devices */
+        if (p->device_nand && p->mux_add_data) {
+                pr_err("%s: invalid configuration!\n", __func__);
+                return -EINVAL;
+        }
+
+        if ((p->mux_add_data > GPMC_MUX_AD) ||
+            ((p->mux_add_data == GPMC_MUX_AAD) &&
+             !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
+                pr_err("%s: invalid multiplex configuration!\n", __func__);
+                return -EINVAL;
+        }
+
+        /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
+        if (p->burst_read || p->burst_write) {
+                switch (p->burst_len) {
+                case GPMC_BURST_4:
+                case GPMC_BURST_8:
+                case GPMC_BURST_16:
+                        break;
+                default:
+                        pr_err("%s: invalid page/burst-length (%d)\n",
+                               __func__, p->burst_len);
+                        return -EINVAL;
+                }
+        }
+
+        if ((p->wait_on_read || p->wait_on_write) &&
+            (p->wait_pin > gpmc_nr_waitpins)) {
+                pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
+                return -EINVAL;
+        }
+
+        config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
+
+        if (p->sync_read)
+                config1 |= GPMC_CONFIG1_READTYPE_SYNC;
+        if (p->sync_write)
+                config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
+        if (p->wait_on_read)
+                config1 |= GPMC_CONFIG1_WAIT_READ_MON;
+        if (p->wait_on_write)
+                config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
+        if (p->wait_on_read || p->wait_on_write)
+                config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
+        if (p->device_nand)
+                config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
+        if (p->mux_add_data)
+                config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
+        if (p->burst_read)
+                config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
+        if (p->burst_write)
+                config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
+        if (p->burst_read || p->burst_write) {
+                config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
+                config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
+        }
+
+        gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
+
+        return 0;
+}
+
 #ifdef CONFIG_OF
 static struct of_device_id gpmc_dt_ids[] = {
         { .compatible = "ti,omap2420-gpmc" },
@@ -1136,70 +1229,110 @@ static struct of_device_id gpmc_dt_ids[] = {
 };
 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
 
+/**
+ * gpmc_read_settings_dt - read gpmc settings from device-tree
+ * @np:         pointer to device-tree node for a gpmc child device
+ * @p:          pointer to gpmc settings structure
+ *
+ * Reads the GPMC settings for a GPMC child device from device-tree and
+ * stores them in the GPMC settings structure passed. The GPMC settings
+ * structure is initialised to zero by this function and so any
+ * previously stored settings will be cleared.
+ */
+void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
+{
+        memset(p, 0, sizeof(struct gpmc_settings));
+
+        p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
+        p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
+        p->device_nand = of_property_read_bool(np, "gpmc,device-nand");
+        of_property_read_u32(np, "gpmc,device-width", &p->device_width);
+        of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
+
+        if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
+                p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
+                p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
+                p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
+                if (!p->burst_read && !p->burst_write)
+                        pr_warn("%s: page/burst-length set but not used!\n",
+                                __func__);
+        }
+
+        if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
+                p->wait_on_read = of_property_read_bool(np,
+                                                        "gpmc,wait-on-read");
+                p->wait_on_write = of_property_read_bool(np,
+                                                         "gpmc,wait-on-write");
+                if (!p->wait_on_read && !p->wait_on_write)
+                        pr_warn("%s: read/write wait monitoring not enabled!\n",
+                                __func__);
+        }
+}
+
 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
                                                 struct gpmc_timings *gpmc_t)
 {
-        u32 val;
+        struct gpmc_bool_timings *p;
+
+        if (!np || !gpmc_t)
+                return;
 
         memset(gpmc_t, 0, sizeof(*gpmc_t));
 
         /* minimum clock period for syncronous mode */
-        if (!of_property_read_u32(np, "gpmc,sync-clk", &val))
-                gpmc_t->sync_clk = val;
+        of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
 
         /* chip select timtings */
-        if (!of_property_read_u32(np, "gpmc,cs-on", &val))
-                gpmc_t->cs_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val))
-                gpmc_t->cs_rd_off = val;
-
-        if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val))
-                gpmc_t->cs_wr_off = val;
+        of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
+        of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
+        of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
 
         /* ADV signal timings */
-        if (!of_property_read_u32(np, "gpmc,adv-on", &val))
-                gpmc_t->adv_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val))
-                gpmc_t->adv_rd_off = val;
-
-        if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val))
-                gpmc_t->adv_wr_off = val;
+        of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
+        of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
+        of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
 
         /* WE signal timings */
-        if (!of_property_read_u32(np, "gpmc,we-on", &val))
-                gpmc_t->we_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,we-off", &val))
-                gpmc_t->we_off = val;
+        of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
+        of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
 
         /* OE signal timings */
-        if (!of_property_read_u32(np, "gpmc,oe-on", &val))
-                gpmc_t->oe_on = val;
-
-        if (!of_property_read_u32(np, "gpmc,oe-off", &val))
-                gpmc_t->oe_off = val;
+        of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
+        of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
 
         /* access and cycle timings */
-        if (!of_property_read_u32(np, "gpmc,page-burst-access", &val))
-                gpmc_t->page_burst_access = val;
-
-        if (!of_property_read_u32(np, "gpmc,access", &val))
-                gpmc_t->access = val;
-
-        if (!of_property_read_u32(np, "gpmc,rd-cycle", &val))
-                gpmc_t->rd_cycle = val;
-
-        if (!of_property_read_u32(np, "gpmc,wr-cycle", &val))
-                gpmc_t->wr_cycle = val;
-
-        /* only for OMAP3430 */
-        if (!of_property_read_u32(np, "gpmc,wr-access", &val))
-                gpmc_t->wr_access = val;
-
-        if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val))
-                gpmc_t->wr_data_mux_bus = val;
+        of_property_read_u32(np, "gpmc,page-burst-access-ns",
+                             &gpmc_t->page_burst_access);
+        of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
+        of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
+        of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
+        of_property_read_u32(np, "gpmc,bus-turnaround-ns",
+                             &gpmc_t->bus_turnaround);
+        of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
+                             &gpmc_t->cycle2cycle_delay);
+        of_property_read_u32(np, "gpmc,wait-monitoring-ns",
+                             &gpmc_t->wait_monitoring);
+        of_property_read_u32(np, "gpmc,clk-activation-ns",
+                             &gpmc_t->clk_activation);
+
+        /* only applicable to OMAP3+ */
+        of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
+        of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
+                             &gpmc_t->wr_data_mux_bus);
+
+        /* bool timing parameters */
+        p = &gpmc_t->bool_timings;
+
+        p->cycle2cyclediffcsen =
+                of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
+        p->cycle2cyclesamecsen =
+                of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
+        p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
+        p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
+        p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
+        p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
+        p->time_para_granularity =
+                of_property_read_bool(np, "gpmc,time-para-granularity");
 }
 
 #ifdef CONFIG_MTD_NAND
@@ -1295,6 +1428,81 @@ static int gpmc_probe_onenand_child(struct platform_device *pdev,
 }
 #endif
 
+/**
+ * gpmc_probe_generic_child - configures the gpmc for a child device
+ * @pdev:       pointer to gpmc platform device
+ * @child:      pointer to device-tree node for child device
+ *
+ * Allocates and configures a GPMC chip-select for a child device.
+ * Returns 0 on success and appropriate negative error code on failure.
+ */
+static int gpmc_probe_generic_child(struct platform_device *pdev,
+                                struct device_node *child)
+{
+        struct gpmc_settings gpmc_s;
+        struct gpmc_timings gpmc_t;
+        struct resource res;
+        unsigned long base;
+        int ret, cs;
+
+        if (of_property_read_u32(child, "reg", &cs) < 0) {
+                dev_err(&pdev->dev, "%s has no 'reg' property\n",
+                        child->full_name);
+                return -ENODEV;
+        }
+
+        if (of_address_to_resource(child, 0, &res) < 0) {
+                dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
+                        child->full_name);
+                return -ENODEV;
+        }
+
+        ret = gpmc_cs_request(cs, resource_size(&res), &base);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
+                return ret;
+        }
+
+        /*
+         * FIXME: gpmc_cs_request() will map the CS to an arbitary
+         * location in the gpmc address space. When booting with
+         * device-tree we want the NOR flash to be mapped to the
+         * location specified in the device-tree blob. So remap the
+         * CS to this location. Once DT migration is complete should
+         * just make gpmc_cs_request() map a specific address.
+         */
+        ret = gpmc_cs_remap(cs, res.start);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "cannot remap GPMC CS %d to 0x%x\n",
+                        cs, res.start);
+                goto err;
+        }
+
+        gpmc_read_settings_dt(child, &gpmc_s);
+
+        ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
+        if (ret < 0)
+                goto err;
+
+        ret = gpmc_cs_program_settings(cs, &gpmc_s);
+        if (ret < 0)
+                goto err;
+
+        gpmc_read_timings_dt(child, &gpmc_t);
+        gpmc_cs_set_timings(cs, &gpmc_t);
+
+        if (of_platform_device_create(child, NULL, &pdev->dev))
+                return 0;
+
+        dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
+        ret = -ENODEV;
+
+err:
+        gpmc_cs_free(cs);
+
+        return ret;
+}
+
 static int gpmc_probe_dt(struct platform_device *pdev)
 {
         int ret;
@@ -1305,6 +1513,13 @@ static int gpmc_probe_dt(struct platform_device *pdev)
         if (!of_id)
                 return 0;
 
+        ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
+                                   &gpmc_nr_waitpins);
+        if (ret < 0) {
+                pr_err("%s: number of wait pins not found!\n", __func__);
+                return ret;
+        }
+
         for_each_node_by_name(child, "nand") {
                 ret = gpmc_probe_nand_child(pdev, child);
                 if (ret < 0) {
@@ -1320,6 +1535,23 @@ static int gpmc_probe_dt(struct platform_device *pdev)
                         return ret;
                 }
         }
+
+        for_each_node_by_name(child, "nor") {
+                ret = gpmc_probe_generic_child(pdev, child);
+                if (ret < 0) {
+                        of_node_put(child);
+                        return ret;
+                }
+        }
+
+        for_each_node_by_name(child, "ethernet") {
+                ret = gpmc_probe_generic_child(pdev, child);
+                if (ret < 0) {
+                        of_node_put(child);
+                        return ret;
+                }
+        }
+
         return 0;
 }
 #else
@@ -1364,25 +1596,37 @@ static int gpmc_probe(struct platform_device *pdev)
         gpmc_dev = &pdev->dev;
 
         l = gpmc_read_reg(GPMC_REVISION);
+
+        /*
+         * FIXME: Once device-tree migration is complete the below flags
+         * should be populated based upon the device-tree compatible
+         * string. For now just use the IP revision. OMAP3+ devices have
+         * the wr_access and wr_data_mux_bus register fields. OMAP4+
+         * devices support the addr-addr-data multiplex protocol.
+         *
+         * GPMC IP revisions:
+         * - OMAP24xx                   = 2.0
+         * - OMAP3xxx                   = 5.0
+         * - OMAP44xx/54xx/AM335x       = 6.0
+         */
         if (GPMC_REVISION_MAJOR(l) > 0x4)
                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
+        if (GPMC_REVISION_MAJOR(l) > 0x5)
+                gpmc_capability |= GPMC_HAS_MUX_AAD;
         dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
                  GPMC_REVISION_MINOR(l));
 
-        rc = gpmc_mem_init();
-        if (IS_ERR_VALUE(rc)) {
-                clk_disable_unprepare(gpmc_l3_clk);
-                clk_put(gpmc_l3_clk);
-                dev_err(gpmc_dev, "failed to reserve memory\n");
-                return rc;
-        }
+        gpmc_mem_init();
 
-        if (IS_ERR_VALUE(gpmc_setup_irq()))
+        if (gpmc_setup_irq() < 0)
                 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
 
         /* Now the GPMC is initialised, unreserve the chip-selects */
         gpmc_cs_map = 0;
 
+        if (!pdev->dev.of_node)
+                gpmc_nr_waitpins = GPMC_NR_WAITPINS;
+
         rc = gpmc_probe_dt(pdev);
         if (rc < 0) {
                 clk_disable_unprepare(gpmc_l3_clk);
diff --git a/arch/arm/mach-omap2/gpmc.h b/arch/arm/mach-omap2/gpmc.h
index fe0a844d5007..707f6d58edd5 100644
--- a/arch/arm/mach-omap2/gpmc.h
+++ b/arch/arm/mach-omap2/gpmc.h
@@ -58,7 +58,7 @@
 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
-#define GPMC_CONFIG1_MUXADDDATA         (1 << 9)
+#define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
@@ -73,6 +73,13 @@
 #define GPMC_IRQ_FIFOEVENTENABLE        0x01
 #define GPMC_IRQ_COUNT_EVENT            0x02
 
+#define GPMC_BURST_4                    4       /* 4 word burst */
+#define GPMC_BURST_8                    8       /* 8 word burst */
+#define GPMC_BURST_16                   16      /* 16 word burst */
+#define GPMC_DEVWIDTH_8BIT              1       /* 8-bit device width */
+#define GPMC_DEVWIDTH_16BIT             2       /* 16-bit device width */
+#define GPMC_MUX_AAD                    1       /* Addr-Addr-Data multiplex */
+#define GPMC_MUX_AD                     2       /* Addr-Data multiplex */
 
 /* bool type time settings */
 struct gpmc_bool_timings {
@@ -178,10 +185,6 @@ struct gpmc_device_timings {
         u8 cyc_wpl;     /* write deassertion time in cycles */
         u32 cyc_iaa;    /* initial access time in cycles */
 
-        bool mux;       /* address & data muxed */
-        bool sync_write;/* synchronous write */
-        bool sync_read; /* synchronous read */
-
         /* extra delays */
         bool ce_xdelay;
         bool avd_xdelay;
@@ -189,28 +192,40 @@ struct gpmc_device_timings {
         bool we_xdelay;
 };
 
+struct gpmc_settings {
+        bool burst_wrap;        /* enables wrap bursting */
+        bool burst_read;        /* enables read page/burst mode */
+        bool burst_write;       /* enables write page/burst mode */
+        bool device_nand;       /* device is NAND */
+        bool sync_read;         /* enables synchronous reads */
+        bool sync_write;        /* enables synchronous writes */
+        bool wait_on_read;      /* monitor wait on reads */
+        bool wait_on_write;     /* monitor wait on writes */
+        u32 burst_len;          /* page/burst length */
+        u32 device_width;       /* device bus width (8 or 16 bit) */
+        u32 mux_add_data;       /* multiplex address & data */
+        u32 wait_pin;           /* wait-pin to be used */
+};
+
 extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
-                                struct gpmc_device_timings *dev_t);
+                             struct gpmc_settings *gpmc_s,
+                             struct gpmc_device_timings *dev_t);
 
 extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
 extern int gpmc_get_client_irq(unsigned irq_config);
 
-extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
-extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
 extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
-extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
-extern unsigned long gpmc_get_fclk_period(void);
 
 extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
-extern u32 gpmc_cs_read_reg(int cs, int idx);
 extern int gpmc_calc_divider(unsigned int sync_clk);
 extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
+extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
 extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 extern void gpmc_cs_free(int cs);
-extern int gpmc_cs_set_reserved(int cs, int reserved);
-extern int gpmc_cs_reserved(int cs);
 extern void omap3_gpmc_save_context(void);
 extern void omap3_gpmc_restore_context(void);
-extern int gpmc_cs_configure(int cs, int cmd, int wval);
+extern int gpmc_configure(int cmd, int wval);
+extern void gpmc_read_settings_dt(struct device_node *np,
+                                  struct gpmc_settings *p);
 
 #endif
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 8a68f1ec66b9..0f4c18e6e60c 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -18,6 +18,11 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/slab.h>
+
+#ifdef CONFIG_SOC_BUS
+#include <linux/sys_soc.h>
+#endif
 
 #include <asm/cputype.h>
 
@@ -31,8 +36,11 @@
 #define OMAP4_SILICON_TYPE_STANDARD             0x01
 #define OMAP4_SILICON_TYPE_PERFORMANCE          0x02
 
+#define OMAP_SOC_MAX_NAME_LENGTH                16
+
 static unsigned int omap_revision;
-static const char *cpu_rev;
+static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
+static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
 u32 omap_features;
 
 unsigned int omap_rev(void)
@@ -169,9 +177,12 @@ void __init omap2xxx_check_revision(void)
                 j = i;
         }
 
-        pr_info("OMAP%04x", omap_rev() >> 16);
+        sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
+        sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
+
+        pr_info("%s", soc_name);
         if ((omap_rev() >> 8) & 0x0f)
-                pr_info("ES%x", (omap_rev() >> 12) & 0xf);
+                pr_info("%s", soc_rev);
         pr_info("\n");
 }
 
@@ -211,8 +222,10 @@ static void __init omap3_cpuinfo(void)
                 cpu_name = "OMAP3503";
         }
 
+        sprintf(soc_name, "%s", cpu_name);
+
         /* Print verbose information */
-        pr_info("%s ES%s (", cpu_name, cpu_rev);
+        pr_info("%s %s (", soc_name, soc_rev);
 
         OMAP3_SHOW_FEATURE(l2cache);
         OMAP3_SHOW_FEATURE(iva);
@@ -291,6 +304,7 @@ void __init ti81xx_check_features(void)
 
 void __init omap3xxx_check_revision(void)
 {
+        const char *cpu_rev;
         u32 cpuid, idcode;
         u16 hawkeye;
         u8 rev;
@@ -300,7 +314,7 @@ void __init omap3xxx_check_revision(void)
          * If the processor type is Cortex-A8 and the revision is 0x0
          * it means its Cortex r0p0 which is 3430 ES1.0.
          */
-        cpuid = read_cpuid(CPUID_ID);
+        cpuid = read_cpuid_id();
         if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
                 omap_revision = OMAP3430_REV_ES1_0;
                 cpu_rev = "1.0";
@@ -438,6 +452,7 @@ void __init omap3xxx_check_revision(void)
                 cpu_rev = "1.2";
                 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
         }
+        sprintf(soc_rev, "ES%s", cpu_rev);
 }
 
 void __init omap4xxx_check_revision(void)
@@ -460,7 +475,7 @@ void __init omap4xxx_check_revision(void)
          * Use ARM register to detect the correct ES version
          */
         if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
-                idcode = read_cpuid(CPUID_ID);
+                idcode = read_cpuid_id();
                 rev = (idcode & 0xf) - 1;
         }
 
@@ -512,8 +527,10 @@ void __init omap4xxx_check_revision(void)
                 omap_revision = OMAP4430_REV_ES2_3;
         }
 
-        pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
-                ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
+        sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
+        sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
+                                                (omap_rev() >> 8) & 0xf);
+        pr_info("%s %s\n", soc_name, soc_rev);
 }
 
 void __init omap5xxx_check_revision(void)
@@ -529,26 +546,34 @@ void __init omap5xxx_check_revision(void)
         case 0xb942:
                 switch (rev) {
                 case 0:
-                default:
                         omap_revision = OMAP5430_REV_ES1_0;
+                        break;
+                case 1:
+                default:
+                        omap_revision = OMAP5430_REV_ES2_0;
                 }
                 break;
 
         case 0xb998:
                 switch (rev) {
                 case 0:
-                default:
                         omap_revision = OMAP5432_REV_ES1_0;
+                        break;
+                case 1:
+                default:
+                        omap_revision = OMAP5432_REV_ES2_0;
                 }
                 break;
 
         default:
                 /* Unknown default to latest silicon rev as default*/
-                omap_revision = OMAP5430_REV_ES1_0;
+                omap_revision = OMAP5430_REV_ES2_0;
         }
 
-        pr_info("OMAP%04x ES%d.0\n",
-                        omap_rev() >> 16, ((omap_rev() >> 12) & 0xf));
+        sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
+        sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
+
+        pr_info("%s %s\n", soc_name, soc_rev);
 }
 
 /*
@@ -569,3 +594,63 @@ void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
         else
                 tap_prod_id = 0x0208;
 }
+
+#ifdef CONFIG_SOC_BUS
+
+static const char const *omap_types[] = {
+        [OMAP2_DEVICE_TYPE_TEST]        = "TST",
+        [OMAP2_DEVICE_TYPE_EMU]         = "EMU",
+        [OMAP2_DEVICE_TYPE_SEC]         = "HS",
+        [OMAP2_DEVICE_TYPE_GP]          = "GP",
+        [OMAP2_DEVICE_TYPE_BAD]         = "BAD",
+};
+
+static const char * __init omap_get_family(void)
+{
+        if (cpu_is_omap24xx())
+                return kasprintf(GFP_KERNEL, "OMAP2");
+        else if (cpu_is_omap34xx())
+                return kasprintf(GFP_KERNEL, "OMAP3");
+        else if (cpu_is_omap44xx())
+                return kasprintf(GFP_KERNEL, "OMAP4");
+        else if (soc_is_omap54xx())
+                return kasprintf(GFP_KERNEL, "OMAP5");
+        else
+                return kasprintf(GFP_KERNEL, "Unknown");
+}
+
+static ssize_t omap_get_type(struct device *dev,
+                                        struct device_attribute *attr,
+                                        char *buf)
+{
+        return sprintf(buf, "%s\n", omap_types[omap_type()]);
+}
+
+static struct device_attribute omap_soc_attr =
+        __ATTR(type,  S_IRUGO, omap_get_type,  NULL);
+
+void __init omap_soc_device_init(void)
+{
+        struct device *parent;
+        struct soc_device *soc_dev;
+        struct soc_device_attribute *soc_dev_attr;
+
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                return;
+
+        soc_dev_attr->machine  = soc_name;
+        soc_dev_attr->family   = omap_get_family();
+        soc_dev_attr->revision = soc_rev;
+
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR_OR_NULL(soc_dev)) {
+                kfree(soc_dev_attr);
+                return;
+        }
+
+        parent = soc_device_to_device(soc_dev);
+        if (!IS_ERR_OR_NULL(parent))
+                device_create_file(parent, &omap_soc_attr);
+}
+#endif /* CONFIG_SOC_BUS */
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 5c445ca1e271..09abf99e9e57 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -277,6 +277,14 @@ static struct map_desc omap54xx_io_desc[] __initdata = {
                 .length         = L4_PER_54XX_SIZE,
                 .type           = MT_DEVICE,
         },
+#ifdef CONFIG_OMAP4_ERRATA_I688
+        {
+                .virtual        = OMAP4_SRAM_VA,
+                .pfn            = __phys_to_pfn(OMAP4_SRAM_PA),
+                .length         = PAGE_SIZE,
+                .type           = MT_MEMORY_SO,
+        },
+#endif
 };
 #endif
 
@@ -329,6 +337,7 @@ void __init omap4_map_io(void)
 void __init omap5_map_io(void)
 {
         iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
+        omap_barriers_init();
 }
 #endif
 /*
@@ -385,6 +394,13 @@ static void __init omap_hwmod_init_postsetup(void)
         omap_pm_if_early_init();
 }
 
+static void __init omap_common_late_init(void)
+{
+        omap_mux_late_init();
+        omap2_common_pm_late_init();
+        omap_soc_device_init();
+}
+
 #ifdef CONFIG_SOC_OMAP2420
 void __init omap2420_init_early(void)
 {
@@ -408,8 +424,7 @@ void __init omap2420_init_early(void)
 
 void __init omap2420_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap2_pm_init();
         omap2_clk_enable_autoidle_all();
 }
@@ -438,8 +453,7 @@ void __init omap2430_init_early(void)
 
 void __init omap2430_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap2_pm_init();
         omap2_clk_enable_autoidle_all();
 }
@@ -511,48 +525,42 @@ void __init ti81xx_init_early(void)
 
 void __init omap3_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap3_pm_init();
         omap2_clk_enable_autoidle_all();
 }
 
 void __init omap3430_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap3_pm_init();
         omap2_clk_enable_autoidle_all();
 }
 
 void __init omap35xx_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap3_pm_init();
         omap2_clk_enable_autoidle_all();
 }
 
 void __init omap3630_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap3_pm_init();
         omap2_clk_enable_autoidle_all();
 }
 
 void __init am35xx_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap3_pm_init();
         omap2_clk_enable_autoidle_all();
 }
 
 void __init ti81xx_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap3_pm_init();
         omap2_clk_enable_autoidle_all();
 }
@@ -604,8 +612,7 @@ void __init omap4430_init_early(void)
 
 void __init omap4430_init_late(void)
 {
-        omap_mux_late_init();
-        omap2_common_pm_late_init();
+        omap_common_late_init();
         omap4_pm_init();
         omap2_clk_enable_autoidle_all();
 }
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index e712d1725a8b..458f72f9dc8f 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -19,11 +19,8 @@
 #include <linux/smp.h>
 #include <linux/io.h>
 
-#include <asm/cacheflush.h>
 #include "omap-wakeupgen.h"
-
 #include "common.h"
-
 #include "powerdomain.h"
 
 /*
@@ -35,9 +32,6 @@ void __ref omap4_cpu_die(unsigned int cpu)
         unsigned int boot_cpu = 0;
         void __iomem *base = omap_get_wakeupgen_base();
 
-        flush_cache_all();
-        dsb();
-
         /*
          * we're ready for shutdown now, so do it
          */
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 8bcb64bcdcdb..e80327b6c81f 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -139,20 +139,6 @@ static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
         }
 }
 
-/**
- * omap4_mpuss_read_prev_context_state:
- * Function returns the MPUSS previous context state
- */
-u32 omap4_mpuss_read_prev_context_state(void)
-{
-        u32 reg;
-
-        reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
-                OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
-        reg &= OMAP4430_LOSTCONTEXT_DFF_MASK;
-        return reg;
-}
-
 /*
  * Store the CPU cluster state for L2X0 low power operations.
  */
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index d9727218dd0a..2a551f997aea 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -21,7 +21,6 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 
-#include <asm/cacheflush.h>
 #include <asm/smp_scu.h>
 
 #include "omap-secure.h"
@@ -67,13 +66,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
                                                         4, 0, 0, 0, 0, 0);
 
         /*
-         * If any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-
-        /*
          * Synchronise with the boot thread.
          */
         spin_lock(&boot_lock);
@@ -84,6 +76,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
 {
         static struct clockdomain *cpu1_clkdm;
         static bool booted;
+        static struct powerdomain *cpu1_pwrdm;
         void __iomem *base = omap_get_wakeupgen_base();
 
         /*
@@ -103,11 +96,10 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
         else
                 __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
 
-        flush_cache_all();
-        smp_wmb();
-
-        if (!cpu1_clkdm)
+        if (!cpu1_clkdm && !cpu1_pwrdm) {
                 cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
+                cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm");
+        }
 
         /*
          * The SGI(Software Generated Interrupts) are not wakeup capable
@@ -120,7 +112,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
          * Section :
          *      4.3.4.2 Power States of CPU0 and CPU1
          */
-        if (booted) {
+        if (booted && cpu1_pwrdm && cpu1_clkdm) {
                 /*
                  * GIC distributor control register has changed between
                  * CortexA9 r1pX and r2pX. The Control Register secure
@@ -141,7 +133,12 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
                         gic_dist_disable();
                 }
 
+                /*
+                 * Ensure that CPU power state is set to ON to avoid CPU
+                 * powerdomain transition on wfi
+                 */
                 clkdm_wakeup(cpu1_clkdm);
+                omap_set_pwrdm_state(cpu1_pwrdm, PWRDM_POWER_ON);
                 clkdm_allow_idle(cpu1_clkdm);
 
                 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
@@ -168,38 +165,6 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
         return 0;
 }
 
-static void __init wakeup_secondary(void)
-{
-        void *startup_addr = omap_secondary_startup;
-        void __iomem *base = omap_get_wakeupgen_base();
-
-        if (cpu_is_omap446x()) {
-                startup_addr = omap_secondary_startup_4460;
-                pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
-        }
-
-        /*
-         * Write the address of secondary startup routine into the
-         * AuxCoreBoot1 where ROM code will jump and start executing
-         * on secondary core once out of WFE
-         * A barrier is added to ensure that write buffer is drained
-         */
-        if (omap_secure_apis_support())
-                omap_auxcoreboot_addr(virt_to_phys(startup_addr));
-        else
-                __raw_writel(virt_to_phys(omap5_secondary_startup),
-                                                base + OMAP_AUX_CORE_BOOT_1);
-
-        smp_wmb();
-
-        /*
-         * Send a 'sev' to wake the secondary core from WFE.
-         * Drain the outstanding writes to memory
-         */
-        dsb_sev();
-        mb();
-}
-
 /*
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
@@ -209,7 +174,7 @@ static void __init omap4_smp_init_cpus(void)
         unsigned int i = 0, ncores = 1, cpu_id;
 
         /* Use ARM cpuid check here, as SoC detection will not work so early */
-        cpu_id = read_cpuid(CPUID_ID) & CPU_MASK;
+        cpu_id = read_cpuid_id() & CPU_MASK;
         if (cpu_id == CPU_CORTEX_A9) {
                 /*
                  * Currently we can't call ioremap here because
@@ -235,6 +200,8 @@ static void __init omap4_smp_init_cpus(void)
 
 static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
 {
+        void *startup_addr = omap_secondary_startup;
+        void __iomem *base = omap_get_wakeupgen_base();
 
         /*
          * Initialise the SCU and wake up the secondary core using
@@ -242,7 +209,24 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
          */
         if (scu_base)
                 scu_enable(scu_base);
-        wakeup_secondary();
+
+        if (cpu_is_omap446x()) {
+                startup_addr = omap_secondary_startup_4460;
+                pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
+        }
+
+        /*
+         * Write the address of secondary startup routine into the
+         * AuxCoreBoot1 where ROM code will jump and start executing
+         * on secondary core once out of WFE
+         * A barrier is added to ensure that write buffer is drained
+         */
+        if (omap_secure_apis_support())
+                omap_auxcoreboot_addr(virt_to_phys(startup_addr));
+        else
+                __raw_writel(virt_to_phys(omap5_secondary_startup),
+                                                base + OMAP_AUX_CORE_BOOT_1);
+
 }
 
 struct smp_operations omap4_smp_ops __initdata = {
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 708bb115a27f..13b27ffaf45e 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -22,6 +22,7 @@
 #include <linux/of_platform.h>
 #include <linux/export.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/of_address.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
@@ -240,15 +241,21 @@ void __iomem *omap4_get_sar_ram_base(void)
  */
 static int __init omap4_sar_ram_init(void)
 {
+        unsigned long sar_base;
+
         /*
          * To avoid code running on other OMAPs in
          * multi-omap builds
          */
-        if (!cpu_is_omap44xx())
+        if (cpu_is_omap44xx())
+                sar_base = OMAP44XX_SAR_RAM_BASE;
+        else if (soc_is_omap54xx())
+                sar_base = OMAP54XX_SAR_RAM_BASE;
+        else
                 return -ENOMEM;
 
         /* Static mapping, never released */
-        sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
+        sar_ram_base = ioremap(sar_base, SZ_16K);
         if (WARN_ON(!sar_ram_base))
                 return -ENOMEM;
 
@@ -258,6 +265,21 @@ omap_early_initcall(omap4_sar_ram_init);
 
 void __init omap_gic_of_init(void)
 {
+        struct device_node *np;
+
+        /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
+        if (!cpu_is_omap446x())
+                goto skip_errata_init;
+
+        np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
+        gic_dist_base_addr = of_iomap(np, 0);
+        WARN_ON(!gic_dist_base_addr);
+
+        np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
+        twd_base = of_iomap(np, 0);
+        WARN_ON(!twd_base);
+
+skip_errata_init:
         omap_wakeupgen_init();
         irqchip_init();
 }
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index e170fe803b04..792b1069f724 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -20,13 +20,13 @@
 #define SAR_BANK4_OFFSET                0x3000
 
 /* Scratch pad memory offsets from SAR_BANK1 */
-#define SCU_OFFSET0                             0xd00
-#define SCU_OFFSET1                             0xd04
-#define OMAP_TYPE_OFFSET                        0xd10
-#define L2X0_SAVE_OFFSET0                       0xd14
-#define L2X0_SAVE_OFFSET1                       0xd18
-#define L2X0_AUXCTRL_OFFSET                     0xd1c
-#define L2X0_PREFETCH_CTRL_OFFSET               0xd20
+#define SCU_OFFSET0                             0xfe4
+#define SCU_OFFSET1                             0xfe8
+#define OMAP_TYPE_OFFSET                        0xfec
+#define L2X0_SAVE_OFFSET0                       0xff0
+#define L2X0_SAVE_OFFSET1                       0xff4
+#define L2X0_AUXCTRL_OFFSET                     0xff8
+#define L2X0_PREFETCH_CTRL_OFFSET               0xffc
 
 /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
 #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET           0xa04
@@ -48,13 +48,13 @@
 #define SAR_BACKUP_STATUS_WAKEUPGEN             0x10
 
 /* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */
-#define OMAP5_WAKEUPGENENB_OFFSET_CPU0          (SAR_BANK3_OFFSET + 0x8d4)
-#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0   (SAR_BANK3_OFFSET + 0x8e8)
-#define OMAP5_WAKEUPGENENB_OFFSET_CPU1          (SAR_BANK3_OFFSET + 0x8fc)
-#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1   (SAR_BANK3_OFFSET + 0x910)
-#define OMAP5_AUXCOREBOOT0_OFFSET               (SAR_BANK3_OFFSET + 0x924)
-#define OMAP5_AUXCOREBOOT1_OFFSET               (SAR_BANK3_OFFSET + 0x928)
-#define OMAP5_AMBA_IF_MODE_OFFSET               (SAR_BANK3_OFFSET + 0x92c)
+#define OMAP5_WAKEUPGENENB_OFFSET_CPU0          (SAR_BANK3_OFFSET + 0x9dc)
+#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0   (SAR_BANK3_OFFSET + 0x9f0)
+#define OMAP5_WAKEUPGENENB_OFFSET_CPU1          (SAR_BANK3_OFFSET + 0xa04)
+#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1   (SAR_BANK3_OFFSET + 0xa18)
+#define OMAP5_AUXCOREBOOT0_OFFSET               (SAR_BANK3_OFFSET + 0xa2c)
+#define OMAP5_AUXCOREBOOT1_OFFSET               (SAR_BANK3_OFFSET + 0x930)
+#define OMAP5_AMBA_IF_MODE_OFFSET               (SAR_BANK3_OFFSET + 0xa34)
 #define OMAP5_SAR_BACKUP_STATUS_OFFSET          (SAR_BANK3_OFFSET + 0x800)
 
 #endif
diff --git a/arch/arm/mach-omap2/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h
index a2582bb3cab3..a086ba15868b 100644
--- a/arch/arm/mach-omap2/omap54xx.h
+++ b/arch/arm/mach-omap2/omap54xx.h
@@ -28,5 +28,6 @@
 #define OMAP54XX_PRCM_MPU_BASE          0x48243000
 #define OMAP54XX_SCM_BASE               0x4a002000
 #define OMAP54XX_CTRL_BASE              0x4a002800
+#define OMAP54XX_SAR_RAM_BASE           0x4ae26000
 
 #endif /* __ASM_SOC_OMAP555554XX_H */
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index 381be7ac0c17..eeea4fa28fbc 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -131,7 +131,7 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
         int oh_cnt, i, ret = 0;
 
         oh_cnt = of_property_count_strings(node, "ti,hwmods");
-        if (!oh_cnt || IS_ERR_VALUE(oh_cnt)) {
+        if (oh_cnt <= 0) {
                 dev_dbg(&pdev->dev, "No 'hwmods' to build omap_device\n");
                 return -ENODEV;
         }
@@ -815,20 +815,17 @@ struct device *omap_device_get_by_hwmod_name(const char *oh_name)
         }
 
         oh = omap_hwmod_lookup(oh_name);
-        if (IS_ERR_OR_NULL(oh)) {
+        if (!oh) {
                 WARN(1, "%s: no hwmod for %s\n", __func__,
                         oh_name);
-                return ERR_PTR(oh ? PTR_ERR(oh) : -ENODEV);
+                return ERR_PTR(-ENODEV);
         }
-        if (IS_ERR_OR_NULL(oh->od)) {
+        if (!oh->od) {
                 WARN(1, "%s: no omap_device for %s\n", __func__,
                         oh_name);
-                return ERR_PTR(oh->od ? PTR_ERR(oh->od) : -ENODEV);
+                return ERR_PTR(-ENODEV);
         }
 
-        if (IS_ERR_OR_NULL(oh->od->pdev))
-                return ERR_PTR(oh->od->pdev ? PTR_ERR(oh->od->pdev) : -ENODEV);
-
         return &oh->od->pdev->dev;
 }
 
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index a202a4785104..93f213b6a784 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -138,6 +138,7 @@
 #include <linux/spinlock.h>
 #include <linux/slab.h>
 #include <linux/bootmem.h>
+#include <linux/cpu.h>
 
 #include <asm/system_misc.h>
 
@@ -610,8 +611,6 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
 
         /* XXX test pwrdm_get_wken for this hwmod's subsystem */
 
-        oh->_int_flags |= _HWMOD_WAKEUP_ENABLED;
-
         return 0;
 }
 
@@ -645,8 +644,6 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
 
         /* XXX test pwrdm_get_wken for this hwmod's subsystem */
 
-        oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED;
-
         return 0;
 }
 
@@ -1666,7 +1663,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
                 return -ENOSYS;
 
         ret = _lookup_hardreset(oh, name, &ohri);
-        if (IS_ERR_VALUE(ret))
+        if (ret < 0)
                 return ret;
 
         if (oh->clkdm) {
@@ -2157,7 +2154,7 @@ static int _enable(struct omap_hwmod *oh)
         if (soc_ops.enable_module)
                 soc_ops.enable_module(oh);
         if (oh->flags & HWMOD_BLOCK_WFI)
-                disable_hlt();
+                cpu_idle_poll_ctrl(true);
 
         if (soc_ops.update_context_lost)
                 soc_ops.update_context_lost(oh);
@@ -2221,7 +2218,7 @@ static int _idle(struct omap_hwmod *oh)
         _del_initiator_dep(oh, mpu_oh);
 
         if (oh->flags & HWMOD_BLOCK_WFI)
-                enable_hlt();
+                cpu_idle_poll_ctrl(false);
         if (soc_ops.disable_module)
                 soc_ops.disable_module(oh);
 
@@ -2331,7 +2328,7 @@ static int _shutdown(struct omap_hwmod *oh)
                 _del_initiator_dep(oh, mpu_oh);
                 /* XXX what about the other system initiators here? dma, dsp */
                 if (oh->flags & HWMOD_BLOCK_WFI)
-                        enable_hlt();
+                        cpu_idle_poll_ctrl(false);
                 if (soc_ops.disable_module)
                         soc_ops.disable_module(oh);
                 _disable_clocks(oh);
@@ -2416,7 +2413,7 @@ static int __init _init(struct omap_hwmod *oh, void *data)
         _init_mpu_rt_base(oh, NULL);
 
         r = _init_clocks(oh, NULL);
-        if (IS_ERR_VALUE(r)) {
+        if (r < 0) {
                 WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name);
                 return -EINVAL;
         }
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index d5dc935f6060..fe5962921f07 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -482,15 +482,13 @@ struct omap_hwmod_omap4_prcm {
  * These are for internal use only and are managed by the omap_hwmod code.
  *
  * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
- * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
  * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
  * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) -
  *     causes the first call to _enable() to only update the pinmux
  */
 #define _HWMOD_NO_MPU_PORT                      (1 << 0)
-#define _HWMOD_WAKEUP_ENABLED                   (1 << 1)
-#define _HWMOD_SYSCONFIG_LOADED                 (1 << 2)
-#define _HWMOD_SKIP_ENABLE                      (1 << 3)
+#define _HWMOD_SYSCONFIG_LOADED                 (1 << 1)
+#define _HWMOD_SKIP_ENABLE                      (1 << 2)
 
 /*
  * omap_hwmod._state definitions
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 6a764af6c6d3..5137cc84b504 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -610,6 +610,8 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
         &omap2420_l4_core__mcbsp2,
         &omap2420_l4_core__msdi1,
         &omap2xxx_l4_core__rng,
+        &omap2xxx_l4_core__sham,
+        &omap2xxx_l4_core__aes,
         &omap2420_l4_core__hdq1w,
         &omap2420_l4_wkup__counter_32k,
         &omap2420_l3__gpmc,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index d2d3840557c3..4ce999ee3ee9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -963,6 +963,8 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
         &omap2430_l4_core__mcbsp5,
         &omap2430_l4_core__hdq1w,
         &omap2xxx_l4_core__rng,
+        &omap2xxx_l4_core__sham,
+        &omap2xxx_l4_core__aes,
         &omap2430_l4_wkup__counter_32k,
         &omap2430_l3__gpmc,
         NULL,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 47901a5e76de..5fd40d4a989e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -138,6 +138,24 @@ static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
         { }
 };
 
+static struct omap_hwmod_addr_space omap2xxx_sham_addrs[] = {
+        {
+                .pa_start       = 0x480a4000,
+                .pa_end         = 0x480a4000 + 0x64 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_addr_space omap2xxx_aes_addrs[] = {
+        {
+                .pa_start       = 0x480a6000,
+                .pa_end         = 0x480a6000 + 0x50 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
 /*
  * Common interconnect data
  */
@@ -389,3 +407,21 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
         .addr           = omap2_rng_addr_space,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
+
+/* l4 core -> sham interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_sham_hwmod,
+        .clk            = "sha_ick",
+        .addr           = omap2xxx_sham_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4 core -> aes interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_aes_hwmod,
+        .clk            = "aes_ick",
+        .addr           = omap2xxx_aes_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index e596117004d4..c8c64b3e1acc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -864,3 +864,84 @@ struct omap_hwmod omap2xxx_rng_hwmod = {
         .flags          = HWMOD_INIT_NO_RESET,
         .class          = &omap2_rng_hwmod_class,
 };
+
+/* SHAM */
+
+static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
+        .rev_offs       = 0x5c,
+        .sysc_offs      = 0x60,
+        .syss_offs      = 0x64,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                           SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2xxx_sham_class = {
+        .name   = "sham",
+        .sysc   = &omap2_sham_sysc,
+};
+
+static struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = {
+        { .irq = 51 + OMAP_INTC_START, },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap2_sham_sdma_chs[] = {
+        { .name = "rx", .dma_req = 13 },
+        { .dma_req = -1 }
+};
+
+struct omap_hwmod omap2xxx_sham_hwmod = {
+        .name           = "sham",
+        .mpu_irqs       = omap2_sham_mpu_irqs,
+        .sdma_reqs      = omap2_sham_sdma_chs,
+        .main_clk       = "l4_ck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 4,
+                        .module_bit = OMAP24XX_EN_SHA_SHIFT,
+                        .idlest_reg_id = 4,
+                        .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
+                },
+        },
+        .class          = &omap2xxx_sham_class,
+};
+
+/* AES */
+
+static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
+        .rev_offs       = 0x44,
+        .sysc_offs      = 0x48,
+        .syss_offs      = 0x4c,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                           SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2xxx_aes_class = {
+        .name   = "aes",
+        .sysc   = &omap2_aes_sysc,
+};
+
+static struct omap_hwmod_dma_info omap2_aes_sdma_chs[] = {
+        { .name = "tx", .dma_req = 9 },
+        { .name = "rx", .dma_req = 10 },
+        { .dma_req = -1 }
+};
+
+struct omap_hwmod omap2xxx_aes_hwmod = {
+        .name           = "aes",
+        .sdma_reqs      = omap2_aes_sdma_chs,
+        .main_clk       = "l4_ck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 4,
+                        .module_bit = OMAP24XX_EN_AES_SHIFT,
+                        .idlest_reg_id = 4,
+                        .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
+                },
+        },
+        .class          = &omap2xxx_aes_class,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 26eee4a556ad..01d8f324450a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -28,6 +28,7 @@
 #include "prm-regbits-33xx.h"
 #include "i2c.h"
 #include "mmc.h"
+#include "wd_timer.h"
 
 /*
  * IP blocks
@@ -417,8 +418,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
  *    - clkdiv32k
  *    - debugss
  *    - ocp watch point
- *    - aes0
- *    - sha0
  */
 #if 0
 /*
@@ -499,25 +498,41 @@ static struct omap_hwmod am33xx_ocpwp_hwmod = {
                 },
         },
 };
+#endif
 
 /*
- * 'aes' class
+ * 'aes0' class
  */
-static struct omap_hwmod_class am33xx_aes_hwmod_class = {
-        .name           = "aes",
+static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
+        .rev_offs       = 0x80,
+        .sysc_offs      = 0x84,
+        .syss_offs      = 0x88,
+        .sysc_flags     = SYSS_HAS_RESET_STATUS,
+};
+
+static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
+        .name           = "aes0",
+        .sysc           = &am33xx_aes0_sysc,
 };
 
 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
-        { .irq = 102 + OMAP_INTC_START, },
+        { .irq = 103 + OMAP_INTC_START, },
         { .irq = -1 },
 };
 
+static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = {
+        { .name = "tx", .dma_req = 6, },
+        { .name = "rx", .dma_req = 5, },
+        { .dma_req = -1 }
+};
+
 static struct omap_hwmod am33xx_aes0_hwmod = {
-        .name           = "aes0",
-        .class          = &am33xx_aes_hwmod_class,
+        .name           = "aes",
+        .class          = &am33xx_aes0_hwmod_class,
         .clkdm_name     = "l3_clkdm",
         .mpu_irqs       = am33xx_aes0_irqs,
-        .main_clk       = "l3_gclk",
+        .sdma_reqs      = am33xx_aes0_edma_reqs,
+        .main_clk       = "aes0_fck",
         .prcm           = {
                 .omap4  = {
                         .clkctrl_offs   = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
@@ -526,21 +541,35 @@ static struct omap_hwmod am33xx_aes0_hwmod = {
         },
 };
 
-/* sha0 */
+/* sha0 HIB2 (the 'P' (public) device) */
+static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
+        .rev_offs       = 0x100,
+        .sysc_offs      = 0x110,
+        .syss_offs      = 0x114,
+        .sysc_flags     = SYSS_HAS_RESET_STATUS,
+};
+
 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
         .name           = "sha0",
+        .sysc           = &am33xx_sha0_sysc,
 };
 
 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
-        { .irq = 108 + OMAP_INTC_START, },
+        { .irq = 109 + OMAP_INTC_START, },
         { .irq = -1 },
 };
 
+static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = {
+        { .name = "rx", .dma_req = 36, },
+        { .dma_req = -1 }
+};
+
 static struct omap_hwmod am33xx_sha0_hwmod = {
-        .name           = "sha0",
+        .name           = "sham",
         .class          = &am33xx_sha0_hwmod_class,
         .clkdm_name     = "l3_clkdm",
         .mpu_irqs       = am33xx_sha0_irqs,
+        .sdma_reqs      = am33xx_sha0_edma_reqs,
         .main_clk       = "l3_gclk",
         .prcm           = {
                 .omap4  = {
@@ -550,8 +579,6 @@ static struct omap_hwmod am33xx_sha0_hwmod = {
         },
 };
 
-#endif
-
 /* ocmcram */
 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
         .name = "ocmcram",
@@ -2087,8 +2114,21 @@ static struct omap_hwmod am33xx_uart6_hwmod = {
 };
 
 /* 'wd_timer' class */
+static struct omap_hwmod_class_sysconfig wdt_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x10,
+        .syss_offs      = 0x14,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+                        SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                        SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
         .name           = "wd_timer",
+        .sysc           = &wdt_sysc,
+        .pre_shutdown   = &omap2_wd_timer_disable,
 };
 
 /*
@@ -2099,6 +2139,7 @@ static struct omap_hwmod am33xx_wd_timer1_hwmod = {
         .name           = "wd_timer2",
         .class          = &am33xx_wd_timer_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE,
         .main_clk       = "wdt1_fck",
         .prcm           = {
                 .omap4  = {
@@ -3434,6 +3475,42 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l3 main -> sha0 HIB2 */
+static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
+        {
+                .pa_start       = 0x53100000,
+                .pa_end         = 0x53100000 + SZ_512 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_sha0_hwmod,
+        .clk            = "sha0_fck",
+        .addr           = am33xx_sha0_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3 main -> AES0 HIB2 */
+static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
+        {
+                .pa_start       = 0x53500000,
+                .pa_end         = 0x53500000 + SZ_1M - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_aes0_hwmod,
+        .clk            = "aes0_fck",
+        .addr           = am33xx_aes0_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
         &am33xx_l4_fw__emif_fw,
         &am33xx_l3_main__emif,
@@ -3514,6 +3591,8 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
         &am33xx_l3_s__usbss,
         &am33xx_l4_hs__cpgmac0,
         &am33xx_cpgmac0__mdio,
+        &am33xx_l3_main__sha0,
+        &am33xx_l3_main__aes0,
         NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 5112d04e7b79..4083606ea1da 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3550,6 +3550,132 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
+static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
+        .sidle_shift    = 4,
+        .srst_shift     = 1,
+        .autoidle_shift = 0,
+};
+
+static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
+        .rev_offs       = 0x5c,
+        .sysc_offs      = 0x60,
+        .syss_offs      = 0x64,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap3_sham_sysc_fields,
+};
+
+static struct omap_hwmod_class omap3xxx_sham_class = {
+        .name   = "sham",
+        .sysc   = &omap3_sham_sysc,
+};
+
+static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
+        { .irq = 49 + OMAP_INTC_START, },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
+        { .name = "rx", .dma_req = OMAP34XX_DMA_SHA1MD5_RX, },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod omap3xxx_sham_hwmod = {
+        .name           = "sham",
+        .mpu_irqs       = omap3_sham_mpu_irqs,
+        .sdma_reqs      = omap3_sham_sdma_reqs,
+        .main_clk       = "sha12_ick",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_SHA12_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
+                },
+        },
+        .class          = &omap3xxx_sham_class,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
+        {
+                .pa_start       = 0x480c3000,
+                .pa_end         = 0x480c3000 + 0x64 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_sham_hwmod,
+        .clk            = "sha12_ick",
+        .addr           = omap3xxx_sham_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> AES */
+static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
+        .sidle_shift    = 6,
+        .srst_shift     = 1,
+        .autoidle_shift = 0,
+};
+
+static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
+        .rev_offs       = 0x44,
+        .sysc_offs      = 0x48,
+        .syss_offs      = 0x4c,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap3xxx_aes_sysc_fields,
+};
+
+static struct omap_hwmod_class omap3xxx_aes_class = {
+        .name   = "aes",
+        .sysc   = &omap3_aes_sysc,
+};
+
+static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP34XX_DMA_AES2_TX, },
+        { .name = "rx", .dma_req = OMAP34XX_DMA_AES2_RX, },
+        { .dma_req = -1 }
+};
+
+static struct omap_hwmod omap3xxx_aes_hwmod = {
+        .name           = "aes",
+        .sdma_reqs      = omap3_aes_sdma_reqs,
+        .main_clk       = "aes2_ick",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_AES2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
+                },
+        },
+        .class          = &omap3xxx_aes_class,
+};
+
+static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = {
+        {
+                .pa_start       = 0x480c5000,
+                .pa_end         = 0x480c5000 + 0x50 - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_aes_hwmod,
+        .clk            = "aes2_ick",
+        .addr           = omap3xxx_aes_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
         &omap3xxx_l3_main__l4_core,
         &omap3xxx_l3_main__l4_per,
@@ -3601,8 +3727,32 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
 };
 
 /* GP-only hwmod links */
-static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
+static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
         &omap3xxx_l4_sec__timer12,
+        &omap3xxx_l4_core__sham,
+        &omap3xxx_l4_core__aes,
+        NULL
+};
+
+static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
+        &omap3xxx_l4_sec__timer12,
+        &omap3xxx_l4_core__sham,
+        &omap3xxx_l4_core__aes,
+        NULL
+};
+
+static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
+        &omap3xxx_l4_sec__timer12,
+        /*
+         * Apparently the SHA/MD5 and AES accelerator IP blocks are
+         * only present on some AM35xx chips, and no one knows which
+         * ones.  See
+         * http://www.spinics.net/lists/arm-kernel/msg215466.html So
+         * if you need these IP blocks on an AM35xx, try uncommenting
+         * the following lines.
+         */
+        /* &omap3xxx_l4_core__sham, */
+        /* &omap3xxx_l4_core__aes, */
         NULL
 };
 
@@ -3709,7 +3859,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
 int __init omap3xxx_hwmod_init(void)
 {
         int r;
-        struct omap_hwmod_ocp_if **h = NULL;
+        struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL;
         unsigned int rev;
 
         omap_hwmod_init();
@@ -3719,13 +3869,6 @@ int __init omap3xxx_hwmod_init(void)
         if (r < 0)
                 return r;
 
-        /* Register GP-only hwmod links. */
-        if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
-                r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
-                if (r < 0)
-                        return r;
-        }
-
         rev = omap_rev();
 
         /*
@@ -3737,11 +3880,14 @@ int __init omap3xxx_hwmod_init(void)
             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
                 h = omap34xx_hwmod_ocp_ifs;
+                h_gp = omap34xx_gp_hwmod_ocp_ifs;
         } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
                 h = am35xx_hwmod_ocp_ifs;
+                h_gp = am35xx_gp_hwmod_ocp_ifs;
         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
                    rev == OMAP3630_REV_ES1_2) {
                 h = omap36xx_hwmod_ocp_ifs;
+                h_gp = omap36xx_gp_hwmod_ocp_ifs;
         } else {
                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
                 return -EINVAL;
@@ -3751,6 +3897,14 @@ int __init omap3xxx_hwmod_init(void)
         if (r < 0)
                 return r;
 
+        /* Register GP-only hwmod links. */
+        if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
+                r = omap_hwmod_register_links(h_gp);
+                if (r < 0)
+                        return r;
+        }
+
+
         /*
          * Register hwmod links specific to certain ES levels of a
          * particular family of silicon (e.g., 34xx ES1.0)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 9e0576569e07..eaba9dc91a0d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -2714,16 +2714,22 @@ static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
         { }
 };
 
-static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
-        { .role = "48mhz", .clk = "ocp2scp_usb_phy_phy_48m" },
-};
-
 /* ocp2scp_usb_phy */
 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
         .name           = "ocp2scp_usb_phy",
         .class          = &omap44xx_ocp2scp_hwmod_class,
         .clkdm_name     = "l3_init_clkdm",
-        .main_clk       = "func_48m_fclk",
+        /*
+         * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
+         * block as an "optional clock," and normally should never be
+         * specified as the main_clk for an OMAP IP block.  However it
+         * turns out that this clock is actually the main clock for
+         * the ocp2scp_usb_phy IP block:
+         * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
+         * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
+         * to be the best workaround.
+         */
+        .main_clk       = "ocp2scp_usb_phy_phy_48m",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
@@ -2732,8 +2738,6 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
                 },
         },
         .dev_attr       = ocp2scp_dev_attr,
-        .opt_clks       = ocp2scp_usb_phy_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
 };
 
 /*
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index cfcce299177c..6e04ff7065e1 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -78,6 +78,8 @@ extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
 extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
 extern struct omap_hwmod omap2xxx_gpmc_hwmod;
 extern struct omap_hwmod omap2xxx_rng_hwmod;
+extern struct omap_hwmod omap2xxx_sham_hwmod;
+extern struct omap_hwmod omap2xxx_aes_hwmod;
 
 /* Common interface data across OMAP2xxx */
 extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
@@ -105,6 +107,8 @@ extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__sham;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__aes;
 
 /* Common IP block data */
 extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 1edd000a8143..0b339861d751 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -217,7 +217,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir)
                 return 0;
 
         d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir);
-        if (!(IS_ERR_OR_NULL(d)))
+        if (d)
                 (void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d,
                         (void *)pwrdm, &pwrdm_suspend_fops);
 
@@ -261,8 +261,8 @@ static int __init pm_dbg_init(void)
                 return 0;
 
         d = debugfs_create_dir("pm_debug", NULL);
-        if (IS_ERR_OR_NULL(d))
-                return PTR_ERR(d);
+        if (!d)
+                return -EINVAL;
 
         (void) debugfs_create_file("count", S_IRUGO,
                 d, (void *)DEBUG_FILE_COUNTERS, &debug_fops);
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 673a4c1d1d76..e742118fcfd2 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -218,7 +218,7 @@ static int omap_pm_enter(suspend_state_t suspend_state)
 
 static int omap_pm_begin(suspend_state_t state)
 {
-        disable_hlt();
+        cpu_idle_poll_ctrl(true);
         if (cpu_is_omap34xx())
                 omap_prcm_irq_prepare();
         return 0;
@@ -226,8 +226,7 @@ static int omap_pm_begin(suspend_state_t state)
 
 static void omap_pm_end(void)
 {
-        enable_hlt();
-        return;
+        cpu_idle_poll_ctrl(false);
 }
 
 static void omap_pm_finish(void)
@@ -265,6 +264,12 @@ static void __init omap4_init_voltages(void)
         omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva");
 }
 
+static inline void omap_init_cpufreq(void)
+{
+        struct platform_device_info devinfo = { .name = "omap-cpufreq", };
+        platform_device_register_full(&devinfo);
+}
+
 static int __init omap2_common_pm_init(void)
 {
         if (!of_have_populated_dt())
@@ -294,6 +299,9 @@ int __init omap2_common_pm_late_init(void)
 
                 /* Smartreflex device init */
                 omap_devinit_smartreflex();
+
+                /* cpufreq dummy device instantiation */
+                omap_init_cpufreq();
         }
 
 #ifdef CONFIG_SUSPEND
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index b59d93908341..ce956b0a7ba4 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -200,22 +200,17 @@ static int omap2_can_sleep(void)
 
 static void omap2_pm_idle(void)
 {
-        local_fiq_disable();
-
         if (!omap2_can_sleep()) {
                 if (omap_irq_pending())
-                        goto out;
+                        return;
                 omap2_enter_mpu_retention();
-                goto out;
+                return;
         }
 
         if (omap_irq_pending())
-                goto out;
+                return;
 
         omap2_enter_full_retention();
-
-out:
-        local_fiq_enable();
 }
 
 static void __init prcm_setup_regs(void)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2d93d8b23835..c01859398b54 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -346,19 +346,14 @@ void omap_sram_idle(void)
 
 static void omap3_pm_idle(void)
 {
-        local_fiq_disable();
-
         if (omap_irq_pending())
-                goto out;
+                return;
 
         trace_cpu_idle(1, smp_processor_id());
 
         omap_sram_idle();
 
         trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
-
-out:
-        local_fiq_enable();
 }
 
 #ifdef CONFIG_SUSPEND
@@ -757,14 +752,12 @@ int __init omap3_pm_init(void)
                         pr_err("Memory allocation failed when allocating for secure sram context\n");
 
                 local_irq_disable();
-                local_fiq_disable();
 
                 omap_dma_global_context_save();
                 omap3_save_secure_ram_context();
                 omap_dma_global_context_restore();
 
                 local_irq_enable();
-                local_fiq_enable();
         }
 
         omap3_save_scratchpad_contents();
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index ea62e75ef21d..a251f87fa2a2 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -126,16 +126,12 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
  * omap_default_idle - OMAP4 default ilde routine.'
  *
  * Implements OMAP4 memory, IO ordering requirements which can't be addressed
- * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
- * by secondary CPU with CONFIG_CPUIDLE.
+ * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPU_IDLE and
+ * by secondary CPU with CONFIG_CPU_IDLE.
  */
 static void omap_default_idle(void)
 {
-        local_fiq_disable();
-
         omap_do_wfi();
-
-        local_fiq_enable();
 }
 
 /**
@@ -147,8 +143,8 @@ static void omap_default_idle(void)
 int __init omap4_pm_init(void)
 {
         int ret;
-        struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup;
-        struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
+        struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
+        struct clockdomain *ducati_clkdm, *l3_2_clkdm;
 
         if (omap_rev() == OMAP4430_REV_ES1_0) {
                 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
@@ -175,27 +171,19 @@ int __init omap4_pm_init(void)
          * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
          * expected. The hardware recommendation is to enable static
          * dependencies for these to avoid system lock ups or random crashes.
-         * The L4 wakeup depedency is added to workaround the OCP sync hardware
-         * BUG with 32K synctimer which lead to incorrect timer value read
-         * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
-         * are part of L4 wakeup clockdomain.
          */
         mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
         emif_clkdm = clkdm_lookup("l3_emif_clkdm");
         l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
         l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
-        l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
-        l4wkup = clkdm_lookup("l4_wkup_clkdm");
         ducati_clkdm = clkdm_lookup("ducati_clkdm");
-        if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || (!l4wkup) ||
-                (!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm))
+        if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
+                (!l3_2_clkdm) || (!ducati_clkdm))
                 goto err2;
 
         ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
         ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
         ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
-        ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
-        ret |= clkdm_add_wkdep(mpuss_clkdm, l4wkup);
         ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
         ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
         if (ret) {
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 8e61d80bf6b3..86babd740d41 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -52,7 +52,6 @@ enum {
 #define ALREADYACTIVE_SWITCH            0
 #define FORCEWAKEUP_SWITCH              1
 #define LOWPOWERSTATE_SWITCH            2
-#define ERROR_SWITCH                    3
 
 /* pwrdm_list contains all registered struct powerdomains */
 static LIST_HEAD(pwrdm_list);
@@ -233,10 +232,7 @@ static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm,
 {
         u8 sleep_switch;
 
-        if (curr_pwrst < 0) {
-                WARN_ON(1);
-                sleep_switch = ERROR_SWITCH;
-        } else if (curr_pwrst < PWRDM_POWER_ON) {
+        if (curr_pwrst < PWRDM_POWER_ON) {
                 if (curr_pwrst > pwrst &&
                     pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE &&
                     arch_pwrdm->pwrdm_set_lowpwrstchange) {
@@ -1091,7 +1087,8 @@ int pwrdm_post_transition(struct powerdomain *pwrdm)
  */
 int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst)
 {
-        u8 curr_pwrst, next_pwrst, sleep_switch;
+        u8 next_pwrst, sleep_switch;
+        int curr_pwrst;
         int ret = 0;
         bool hwsup = false;
 
@@ -1107,16 +1104,17 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst)
         pwrdm_lock(pwrdm);
 
         curr_pwrst = pwrdm_read_pwrst(pwrdm);
+        if (curr_pwrst < 0) {
+                ret = -EINVAL;
+                goto osps_out;
+        }
+
         next_pwrst = pwrdm_read_next_pwrst(pwrdm);
         if (curr_pwrst == pwrst && next_pwrst == pwrst)
                 goto osps_out;
 
         sleep_switch = _pwrdm_save_clkdm_state_and_activate(pwrdm, curr_pwrst,
                                                             pwrst, &hwsup);
-        if (sleep_switch == ERROR_SWITCH) {
-                ret = -EINVAL;
-                goto osps_out;
-        }
 
         ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
         if (ret)
@@ -1182,7 +1180,7 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm)
 {
         int i;
 
-        if (IS_ERR_OR_NULL(pwrdm)) {
+        if (!pwrdm) {
                 pr_debug("powerdomain: %s: invalid powerdomain pointer\n",
                          __func__);
                 return 1;
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index d35f98aabf7a..415c7e0c9393 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -81,13 +81,13 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
 /* Read a register in a CM/PRM instance in the PRM module */
 u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
 {
-        return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg));
+        return __raw_readl(prm_base + inst + reg);
 }
 
 /* Write into a register in a CM/PRM instance in the PRM module */
 void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
 {
-        __raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg));
+        __raw_writel(val, prm_base + inst + reg);
 }
 
 /* Read-modify-write a register in a PRM module. Caller must lock */
@@ -650,7 +650,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
 
 int __init omap44xx_prm_init(void)
 {
-        if (!cpu_is_omap44xx())
+        if (!cpu_is_omap44xx() && !soc_is_omap54xx())
                 return 0;
 
         return prm_register(&omap44xx_prm_ll_data);
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index c62116bbc760..18fdeeb3a44a 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -413,7 +413,9 @@ IS_OMAP_TYPE(3430, 0x3430)
 
 #define OMAP54XX_CLASS          0x54000054
 #define OMAP5430_REV_ES1_0      (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
+#define OMAP5430_REV_ES2_0      (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8))
 #define OMAP5432_REV_ES1_0      (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
+#define OMAP5432_REV_ES2_0      (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8))
 
 void omap2xxx_check_revision(void);
 void omap3xxx_check_revision(void);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index f62b509ed08d..f12aa6c15da4 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -57,15 +57,6 @@
 #include "common.h"
 #include "powerdomain.h"
 
-/* Parent clocks, eventually these will come from the clock framework */
-
-#define OMAP2_MPU_SOURCE        "sys_ck"
-#define OMAP3_MPU_SOURCE        OMAP2_MPU_SOURCE
-#define OMAP4_MPU_SOURCE        "sys_clkin_ck"
-#define OMAP2_32K_SOURCE        "func_32k_ck"
-#define OMAP3_32K_SOURCE        "omap_32k_fck"
-#define OMAP4_32K_SOURCE        "sys_32k_ck"
-
 #define REALTIME_COUNTER_BASE                           0x48243200
 #define INCREMENTER_NUMERATOR_OFFSET                    0x10
 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET           0x14
@@ -129,7 +120,6 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 }
 
 static struct clock_event_device clockevent_gpt = {
-        .name           = "gp_timer",
         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
         .rating         = 300,
         .set_next_event = omap2_gp_timer_set_next_event,
@@ -170,6 +160,12 @@ static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
                 if (property && !of_get_property(np, property, NULL))
                         continue;
 
+                if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
+                                  of_get_property(np, "ti,timer-dsp", NULL) ||
+                                  of_get_property(np, "ti,timer-pwm", NULL) ||
+                                  of_get_property(np, "ti,timer-secure", NULL)))
+                        continue;
+
                 of_add_property(np, &device_disabled);
                 return np;
         }
@@ -214,16 +210,17 @@ static u32 __init omap_dm_timer_get_errata(void)
 }
 
 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
-                                                int gptimer_id,
-                                                const char *fck_source,
-                                                const char *property,
-                                                int posted)
+                                         const char *fck_source,
+                                         const char *property,
+                                         const char **timer_name,
+                                         int posted)
 {
         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
         const char *oh_name;
         struct device_node *np;
         struct omap_hwmod *oh;
         struct resource irq, mem;
+        struct clk *src;
         int r = 0;
 
         if (of_have_populated_dt()) {
@@ -243,10 +240,10 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 
                 of_node_put(np);
         } else {
-                if (omap_dm_timer_reserve_systimer(gptimer_id))
+                if (omap_dm_timer_reserve_systimer(timer->id))
                         return -ENODEV;
 
-                sprintf(name, "timer%d", gptimer_id);
+                sprintf(name, "timer%d", timer->id);
                 oh_name = name;
         }
 
@@ -254,6 +251,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
         if (!oh)
                 return -ENODEV;
 
+        *timer_name = oh->name;
+
         if (!of_have_populated_dt()) {
                 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
                                                    &irq);
@@ -276,24 +275,24 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
         /* After the dmtimer is using hwmod these clocks won't be needed */
         timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
         if (IS_ERR(timer->fclk))
-                return -ENODEV;
+                return PTR_ERR(timer->fclk);
 
-        /* FIXME: Need to remove hard-coded test on timer ID */
-        if (gptimer_id != 12) {
-                struct clk *src;
-
-                src = clk_get(NULL, fck_source);
-                if (IS_ERR(src)) {
-                        r = -EINVAL;
-                } else {
-                        r = clk_set_parent(timer->fclk, src);
-                        if (IS_ERR_VALUE(r))
-                                pr_warn("%s: %s cannot set source\n",
-                                        __func__, oh->name);
+        src = clk_get(NULL, fck_source);
+        if (IS_ERR(src))
+                return PTR_ERR(src);
+
+        if (clk_get_parent(timer->fclk) != src) {
+                r = clk_set_parent(timer->fclk, src);
+                if (r < 0) {
+                        pr_warn("%s: %s cannot set source\n", __func__,
+                                oh->name);
                         clk_put(src);
+                        return r;
                 }
         }
 
+        clk_put(src);
+
         omap_hwmod_setup_one(oh_name);
         omap_hwmod_enable(oh);
         __omap_dm_timer_init_regs(timer);
@@ -317,6 +316,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
 {
         int res;
 
+        clkev.id = gptimer_id;
         clkev.errata = omap_dm_timer_get_errata();
 
         /*
@@ -326,8 +326,8 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
          */
         __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
 
-        res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property,
-                                     OMAP_TIMER_POSTED);
+        res = omap_dm_timer_init_one(&clkev, fck_source, property,
+                                     &clockevent_gpt.name, OMAP_TIMER_POSTED);
         BUG_ON(res);
 
         omap2_gp_timer_irq.dev_id = &clkev;
@@ -341,8 +341,8 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
                                         3, /* Timer internal resynch latency */
                                         0xffffffff);
 
-        pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
-                gptimer_id, clkev.rate);
+        pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
+                clkev.rate);
 }
 
 /* Clocksource code */
@@ -359,7 +359,6 @@ static cycle_t clocksource_read_cycles(struct clocksource *cs)
 }
 
 static struct clocksource clocksource_gpt = {
-        .name           = "gp_timer",
         .rating         = 300,
         .read           = clocksource_read_cycles,
         .mask           = CLOCKSOURCE_MASK(32),
@@ -442,13 +441,16 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
 }
 
 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
-                                                const char *fck_source)
+                                                  const char *fck_source,
+                                                  const char *property)
 {
         int res;
 
+        clksrc.id = gptimer_id;
         clksrc.errata = omap_dm_timer_get_errata();
 
-        res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL,
+        res = omap_dm_timer_init_one(&clksrc, fck_source, property,
+                                     &clocksource_gpt.name,
                                      OMAP_TIMER_NONPOSTED);
         BUG_ON(res);
 
@@ -461,8 +463,8 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
                 pr_err("Could not register clocksource %s\n",
                         clocksource_gpt.name);
         else
-                pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
-                        gptimer_id, clksrc.rate);
+                pr_info("OMAP clocksource: %s at %lu Hz\n",
+                        clocksource_gpt.name, clksrc.rate);
 }
 
 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
@@ -487,7 +489,7 @@ static void __init realtime_counter_init(void)
                 pr_err("%s: ioremap failed\n", __func__);
                 return;
         }
-        sys_clk = clk_get(NULL, "sys_clkin_ck");
+        sys_clk = clk_get(NULL, "sys_clkin");
         if (IS_ERR(sys_clk)) {
                 pr_err("%s: failed to get system clock handle\n", __func__);
                 iounmap(base);
@@ -544,53 +546,52 @@ static inline void __init realtime_counter_init(void)
 #endif
 
 #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,   \
-                               clksrc_nr, clksrc_src)                   \
+                               clksrc_nr, clksrc_src, clksrc_prop)      \
 void __init omap##name##_gptimer_timer_init(void)                       \
 {                                                                       \
-        if (omap_clk_init)                                              \
-                omap_clk_init();                                        \
         omap_dmtimer_init();                                            \
         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
-        omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);        \
+        omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src,         \
+                                        clksrc_prop);                   \
 }
 
 #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop,  \
-                                clksrc_nr, clksrc_src)                  \
+                                clksrc_nr, clksrc_src, clksrc_prop)     \
 void __init omap##name##_sync32k_timer_init(void)               \
 {                                                                       \
-        if (omap_clk_init)                                              \
-                omap_clk_init();                                        \
         omap_dmtimer_init();                                            \
         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
         /* Enable the use of clocksource="gp_timer" kernel parameter */ \
         if (use_gptimer_clksrc)                                         \
-                omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);\
+                omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \
+                                                clksrc_prop);           \
         else                                                            \
                 omap2_sync32k_clocksource_init();                       \
 }
 
 #ifdef CONFIG_ARCH_OMAP2
-OMAP_SYS_32K_TIMER_INIT(2, 1, OMAP2_32K_SOURCE, "ti,timer-alwon",
-                        2, OMAP2_MPU_SOURCE);
+OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon",
+                        2, "timer_sys_ck", NULL);
 #endif /* CONFIG_ARCH_OMAP2 */
 
 #ifdef CONFIG_ARCH_OMAP3
-OMAP_SYS_32K_TIMER_INIT(3, 1, OMAP3_32K_SOURCE, "ti,timer-alwon",
-                        2, OMAP3_MPU_SOURCE);
-OMAP_SYS_32K_TIMER_INIT(3_secure, 12, OMAP3_32K_SOURCE, "ti,timer-secure",
-                        2, OMAP3_MPU_SOURCE);
-OMAP_SYS_GP_TIMER_INIT(3_gp, 1, OMAP3_MPU_SOURCE, "ti,timer-alwon",
-                       2, OMAP3_MPU_SOURCE);
+OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon",
+                        2, "timer_sys_ck", NULL);
+OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure",
+                        2, "timer_sys_ck", NULL);
 #endif /* CONFIG_ARCH_OMAP3 */
 
-#ifdef CONFIG_SOC_AM33XX
-OMAP_SYS_GP_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon",
-                       2, OMAP4_MPU_SOURCE);
-#endif /* CONFIG_SOC_AM33XX */
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
+OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL,
+                       1, "timer_sys_ck", "ti,timer-alwon");
+#endif
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
+static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
+                               2, "sys_clkin_ck", NULL);
+#endif
 
 #ifdef CONFIG_ARCH_OMAP4
-OMAP_SYS_32K_TIMER_INIT(4, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
-                        2, OMAP4_MPU_SOURCE);
 #ifdef CONFIG_LOCAL_TIMERS
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
 void __init omap4_local_timer_init(void)
@@ -601,7 +602,7 @@ void __init omap4_local_timer_init(void)
                 int err;
 
                 if (of_have_populated_dt()) {
-                        twd_local_timer_of_register();
+                        clocksource_of_init();
                         return;
                 }
 
@@ -619,13 +620,11 @@ void __init omap4_local_timer_init(void)
 #endif /* CONFIG_ARCH_OMAP4 */
 
 #ifdef CONFIG_SOC_OMAP5
-OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
-                        2, OMAP4_MPU_SOURCE);
 void __init omap5_realtime_timer_init(void)
 {
         int err;
 
-        omap5_sync32k_timer_init();
+        omap4_sync32k_timer_init();
         realtime_counter_init();
 
         err = arch_timer_of_register();
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index 5706bdccf45e..aa27d7f5cbb7 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -22,8 +22,12 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/dma-mapping.h>
-
-#include <asm/io.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/string.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/usb/phy.h>
 
 #include "soc.h"
 #include "omap_device.h"
@@ -526,3 +530,155 @@ void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
 }
 
 #endif
+
+/* Template for PHY regulators */
+static struct fixed_voltage_config hsusb_reg_config = {
+        /* .supply_name filled later */
+        .microvolts = 3300000,
+        .gpio = -1,             /* updated later */
+        .startup_delay = 70000, /* 70msec */
+        .enable_high = 1,       /* updated later */
+        .enabled_at_boot = 0,   /* keep in RESET */
+        /* .init_data filled later */
+};
+
+static const char *nop_name = "nop_usb_xceiv"; /* NOP PHY driver */
+static const char *reg_name = "reg-fixed-voltage"; /* Regulator driver */
+
+/**
+ * usbhs_add_regulator - Add a gpio based fixed voltage regulator device
+ * @name: name for the regulator
+ * @dev_id: device id of the device this regulator supplies power to
+ * @dev_supply: supply name that the device expects
+ * @gpio: GPIO number
+ * @polarity: 1 - Active high, 0 - Active low
+ */
+static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
+                                                int gpio, int polarity)
+{
+        struct regulator_consumer_supply *supplies;
+        struct regulator_init_data *reg_data;
+        struct fixed_voltage_config *config;
+        struct platform_device *pdev;
+        int ret;
+
+        supplies = kzalloc(sizeof(*supplies), GFP_KERNEL);
+        if (!supplies)
+                return -ENOMEM;
+
+        supplies->supply = dev_supply;
+        supplies->dev_name = dev_id;
+
+        reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
+        if (!reg_data)
+                return -ENOMEM;
+
+        reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
+        reg_data->consumer_supplies = supplies;
+        reg_data->num_consumer_supplies = 1;
+
+        config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
+                        GFP_KERNEL);
+        if (!config)
+                return -ENOMEM;
+
+        config->supply_name = name;
+        config->gpio = gpio;
+        config->enable_high = polarity;
+        config->init_data = reg_data;
+
+        /* create a regulator device */
+        pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
+        if (!pdev)
+                return -ENOMEM;
+
+        pdev->id = PLATFORM_DEVID_AUTO;
+        pdev->name = reg_name;
+        pdev->dev.platform_data = config;
+
+        ret = platform_device_register(pdev);
+        if (ret)
+                pr_err("%s: Failed registering regulator %s for %s\n",
+                                __func__, name, dev_id);
+
+        return ret;
+}
+
+int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
+{
+        char *rail_name;
+        int i, len;
+        struct platform_device *pdev;
+        char *phy_id;
+
+        /* the phy_id will be something like "nop_usb_xceiv.1" */
+        len = strlen(nop_name) + 3; /* 3 -> ".1" and NULL terminator */
+
+        for (i = 0; i < num_phys; i++) {
+
+                if (!phy->port) {
+                        pr_err("%s: Invalid port 0. Must start from 1\n",
+                                                __func__);
+                        continue;
+                }
+
+                /* do we need a NOP PHY device ? */
+                if (!gpio_is_valid(phy->reset_gpio) &&
+                        !gpio_is_valid(phy->vcc_gpio))
+                        continue;
+
+                /* create a NOP PHY device */
+                pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
+                if (!pdev)
+                        return -ENOMEM;
+
+                pdev->id = phy->port;
+                pdev->name = nop_name;
+                pdev->dev.platform_data = phy->platform_data;
+
+                phy_id = kmalloc(len, GFP_KERNEL);
+                if (!phy_id)
+                        return -ENOMEM;
+
+                scnprintf(phy_id, len, "nop_usb_xceiv.%d\n",
+                                        pdev->id);
+
+                if (platform_device_register(pdev)) {
+                        pr_err("%s: Failed to register device %s\n",
+                                __func__,  phy_id);
+                        continue;
+                }
+
+                usb_bind_phy("ehci-omap.0", phy->port - 1, phy_id);
+
+                /* Do we need RESET regulator ? */
+                if (gpio_is_valid(phy->reset_gpio)) {
+
+                        rail_name = kmalloc(13, GFP_KERNEL);
+                        if (!rail_name)
+                                return -ENOMEM;
+
+                        scnprintf(rail_name, 13, "hsusb%d_reset", phy->port);
+
+                        usbhs_add_regulator(rail_name, phy_id, "reset",
+                                                phy->reset_gpio, 1);
+                }
+
+                /* Do we need VCC regulator ? */
+                if (gpio_is_valid(phy->vcc_gpio)) {
+
+                        rail_name = kmalloc(13, GFP_KERNEL);
+                        if (!rail_name)
+                                return -ENOMEM;
+
+                        scnprintf(rail_name, 13, "hsusb%d_vcc", phy->port);
+
+                        usbhs_add_regulator(rail_name, phy_id, "vcc",
+                                        phy->vcc_gpio, phy->vcc_polarity);
+                }
+
+                phy++;
+        }
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index c5a3c6f9504e..e832bc7b8e2d 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/err.h>
 #include <linux/string.h>
 #include <linux/types.h>
 #include <linux/errno.h>
@@ -26,6 +27,24 @@
 static u8               async_cs, sync_cs;
 static unsigned         refclk_psec;
 
+static struct gpmc_settings tusb_async = {
+        .wait_on_read   = true,
+        .wait_on_write  = true,
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+};
+
+static struct gpmc_settings tusb_sync = {
+        .burst_read     = true,
+        .burst_write    = true,
+        .sync_read      = true,
+        .sync_write     = true,
+        .wait_on_read   = true,
+        .wait_on_write  = true,
+        .burst_len      = GPMC_BURST_16,
+        .device_width   = GPMC_DEVWIDTH_16BIT,
+        .mux_add_data   = GPMC_MUX_AD,
+};
 
 /* NOTE:  timings are from tusb 6010 datasheet Rev 1.8, 12-Sept 2006 */
 
@@ -37,8 +56,6 @@ static int tusb_set_async_mode(unsigned sysclk_ps)
 
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
-
         dev_t.t_ceasu = 8 * 1000;
         dev_t.t_avdasu = t_acsnh_advnh - 7000;
         dev_t.t_ce_avd = 1000;
@@ -52,7 +69,7 @@ static int tusb_set_async_mode(unsigned sysclk_ps)
         dev_t.t_wpl = 300;
         dev_t.cyc_aavdh_we = 1;
 
-        gpmc_calc_timings(&t, &dev_t);
+        gpmc_calc_timings(&t, &tusb_async, &dev_t);
 
         return gpmc_cs_set_timings(async_cs, &t);
 }
@@ -65,10 +82,6 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
 
         memset(&dev_t, 0, sizeof(dev_t));
 
-        dev_t.mux = true;
-        dev_t.sync_read = true;
-        dev_t.sync_write = true;
-
         dev_t.clk = 11100;
         dev_t.t_bacc = 1000;
         dev_t.t_ces = 1000;
@@ -84,7 +97,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps)
         dev_t.cyc_wpl = 6;
         dev_t.t_ce_rdyz = 7000;
 
-        gpmc_calc_timings(&t, &dev_t);
+        gpmc_calc_timings(&t, &tusb_sync, &dev_t);
 
         return gpmc_cs_set_timings(sync_cs, &t);
 }
@@ -165,18 +178,12 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
                 return status;
         }
         tusb_resources[0].end = tusb_resources[0].start + 0x9ff;
+        tusb_async.wait_pin = waitpin;
         async_cs = async;
-        gpmc_cs_write_reg(async, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_PAGE_LEN(2)
-                        | GPMC_CONFIG1_WAIT_READ_MON
-                        | GPMC_CONFIG1_WAIT_WRITE_MON
-                        | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin)
-                        | GPMC_CONFIG1_READTYPE_ASYNC
-                        | GPMC_CONFIG1_WRITETYPE_ASYNC
-                        | GPMC_CONFIG1_DEVICESIZE_16
-                        | GPMC_CONFIG1_DEVICETYPE_NOR
-                        | GPMC_CONFIG1_MUXADDDATA);
 
+        status = gpmc_cs_program_settings(async_cs, &tusb_async);
+        if (status < 0)
+                return status;
 
         /* SYNC region, primarily for DMA */
         status = gpmc_cs_request(sync, SZ_16M, (unsigned long *)
@@ -186,21 +193,12 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
                 return status;
         }
         tusb_resources[1].end = tusb_resources[1].start + 0x9ff;
+        tusb_sync.wait_pin = waitpin;
         sync_cs = sync;
-        gpmc_cs_write_reg(sync, GPMC_CS_CONFIG1,
-                          GPMC_CONFIG1_READMULTIPLE_SUPP
-                        | GPMC_CONFIG1_READTYPE_SYNC
-                        | GPMC_CONFIG1_WRITEMULTIPLE_SUPP
-                        | GPMC_CONFIG1_WRITETYPE_SYNC
-                        | GPMC_CONFIG1_PAGE_LEN(2)
-                        | GPMC_CONFIG1_WAIT_READ_MON
-                        | GPMC_CONFIG1_WAIT_WRITE_MON
-                        | GPMC_CONFIG1_WAIT_PIN_SEL(waitpin)
-                        | GPMC_CONFIG1_DEVICESIZE_16
-                        | GPMC_CONFIG1_DEVICETYPE_NOR
-                        | GPMC_CONFIG1_MUXADDDATA
-                        /* fclk divider gets set later */
-                        );
+
+        status = gpmc_cs_program_settings(sync_cs, &tusb_sync);
+        if (status < 0)
+                return status;
 
         /* IRQ */
         status = gpio_request_one(irq, GPIOF_IN, "TUSB6010 irq");
diff --git a/arch/arm/mach-omap2/usb.h b/arch/arm/mach-omap2/usb.h
index 3319f5cf47a3..e7261ebcf7b0 100644
--- a/arch/arm/mach-omap2/usb.h
+++ b/arch/arm/mach-omap2/usb.h
@@ -53,8 +53,17 @@
 #define USBPHY_OTGSESSEND_EN    (1 << 20)
 #define USBPHY_DATA_POLARITY    (1 << 23)
 
+struct usbhs_phy_data {
+        int port;               /* 1 indexed port number */
+        int reset_gpio;
+        int vcc_gpio;
+        bool vcc_polarity;      /* 1 active high, 0 active low */
+        void *platform_data;
+};
+
 extern void usb_musb_init(struct omap_musb_board_data *board_data);
 extern void usbhs_init(struct usbhs_omap_platform_data *pdata);
+extern int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys);
 
 extern void am35x_musb_reset(void);
 extern void am35x_musb_phy_power(u8 on);
diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
index 35a8014529ca..94fbb815680c 100644
--- a/arch/arm/mach-orion5x/board-dt.c
+++ b/arch/arm/mach-orion5x/board-dt.c
@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
+#include <linux/cpu.h>
 #include <asm/system_misc.h>
 #include <asm/mach/arch.h>
 #include <mach/orion5x.h>
@@ -52,7 +53,7 @@ static void __init orion5x_dt_init(void)
          */
         if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
                 printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
-                disable_hlt();
+                cpu_idle_poll_ctrl(true);
         }
 
         if (of_machine_is_compatible("lacie,ethernet-disk-mini-v2"))
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index d068f1431c40..2075bf8e3d90 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -19,6 +19,7 @@
 #include <linux/ata_platform.h>
 #include <linux/delay.h>
 #include <linux/clk-provider.h>
+#include <linux/cpu.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/setup.h>
@@ -293,7 +294,7 @@ void __init orion5x_init(void)
          */
         if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
                 printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
-                disable_hlt();
+                cpu_idle_poll_ctrl(true);
         }
 
         /*
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index d9c7c3bf0d9c..973db98a3c27 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -402,8 +402,9 @@ static void __init orion5x_pci_master_slave_enable(void)
         orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
 }
 
-static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
+static void __init orion5x_setup_pci_wins(void)
 {
+        const struct mbus_dram_target_info *dram = mv_mbus_dram_info();
         u32 win_enable;
         int bus;
         int i;
@@ -420,7 +421,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
         bus = orion5x_pci_local_bus_nr();
 
         for (i = 0; i < dram->num_cs; i++) {
-                struct mbus_dram_window *cs = dram->cs + i;
+                const struct mbus_dram_window *cs = dram->cs + i;
                 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
                 u32 reg;
                 u32 val;
@@ -467,7 +468,7 @@ static int __init pci_setup(struct pci_sys_data *sys)
         /*
          * Point PCI unit MBUS decode windows to DRAM space.
          */
-        orion5x_setup_pci_wins(&orion_mbus_dram_info);
+        orion5x_setup_pci_wins();
 
         /*
          * Master + Slave enable
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
index 4f7379fe01e2..80ca974b2f82 100644
--- a/arch/arm/mach-prima2/Kconfig
+++ b/arch/arm/mach-prima2/Kconfig
@@ -1,6 +1,26 @@
+config ARCH_SIRF
+        bool "CSR SiRF" if ARCH_MULTI_V7
+        select ARCH_REQUIRE_GPIOLIB
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_IRQ_CHIP
+        select MIGHT_HAVE_CACHE_L2X0
+        select NO_IOPORT
+        select PINCTRL
+        select PINCTRL_SIRF
+        help
+          Support for CSR SiRFprimaII/Marco/Polo platforms
+
 if ARCH_SIRF
 
-menu "CSR SiRF primaII/Marco/Polo Specific Features"
+menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features"
+
+config ARCH_ATLAS6
+        bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
+        default y
+        select CPU_V7
+        select SIRF_IRQ
+        help
+          Support for CSR SiRFSoC ARM Cortex A9 Platform
 
 config ARCH_PRIMA2
         bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
@@ -16,6 +36,7 @@ config ARCH_MARCO
         default y
         select ARM_GIC
         select CPU_V7
+        select HAVE_ARM_SCU if SMP
         select HAVE_SMP
         select SMP_ON_UP
         help
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index bfe360cbd177..7a6b4a323125 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -4,8 +4,7 @@ obj-y += rtciobrg.o
 obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_CACHE_L2X0) += l2x0.o
 obj-$(CONFIG_SUSPEND) += pm.o sleep.o
-obj-$(CONFIG_SIRF_IRQ) += irq.o
 obj-$(CONFIG_SMP) += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)  += hotplug.o
-obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o
-obj-$(CONFIG_ARCH_MARCO) += timer-marco.o
+
+CFLAGS_hotplug.o += -march=armv7-a
diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index 2d57aa479a7b..4f94cd87972a 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -6,6 +6,7 @@
  * Licensed under GPLv2 or later.
  */
 
+#include <linux/clocksource.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/irqchip.h>
@@ -31,12 +32,38 @@ void __init sirfsoc_init_late(void)
         sirfsoc_pm_init();
 }
 
+static __init void sirfsoc_init_time(void)
+{
+        /* initialize clocking early, we want to set the OS timer */
+        sirfsoc_of_clk_init();
+        clocksource_of_init();
+}
+
 static __init void sirfsoc_map_io(void)
 {
         sirfsoc_map_lluart();
         sirfsoc_map_scu();
 }
 
+#ifdef CONFIG_ARCH_ATLAS6
+static const char *atlas6_dt_match[] __initdata = {
+        "sirf,atlas6",
+        NULL
+};
+
+DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
+        /* Maintainer: Barry Song <baohua.song@csr.com> */
+        .nr_irqs        = 128,
+        .map_io         = sirfsoc_map_io,
+        .init_irq       = irqchip_init,
+        .init_time      = sirfsoc_init_time,
+        .init_machine   = sirfsoc_mach_init,
+        .init_late      = sirfsoc_init_late,
+        .dt_compat      = atlas6_dt_match,
+        .restart        = sirfsoc_restart,
+MACHINE_END
+#endif
+
 #ifdef CONFIG_ARCH_PRIMA2
 static const char *prima2_dt_match[] __initdata = {
        "sirf,prima2",
@@ -45,12 +72,10 @@ static const char *prima2_dt_match[] __initdata = {
 
 DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
         /* Maintainer: Barry Song <baohua.song@csr.com> */
+        .nr_irqs        = 128,
         .map_io         = sirfsoc_map_io,
-        .init_irq       = sirfsoc_of_irq_init,
-        .init_time      = sirfsoc_prima2_timer_init,
-#ifdef CONFIG_MULTI_IRQ_HANDLER
-        .handle_irq     = sirfsoc_handle_irq,
-#endif
+        .init_irq       = irqchip_init,
+        .init_time      = sirfsoc_init_time,
         .dma_zone_size  = SZ_256M,
         .init_machine   = sirfsoc_mach_init,
         .init_late      = sirfsoc_init_late,
@@ -70,7 +95,7 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
         .smp            = smp_ops(sirfsoc_smp_ops),
         .map_io         = sirfsoc_map_io,
         .init_irq       = irqchip_init,
-        .init_time      = sirfsoc_marco_timer_init,
+        .init_time      = sirfsoc_init_time,
         .init_machine   = sirfsoc_mach_init,
         .init_late      = sirfsoc_init_late,
         .dt_compat      = marco_dt_match,
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index b7c26b62e4a7..81135cd88e54 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -13,8 +13,8 @@
 #include <asm/mach/time.h>
 #include <asm/exception.h>
 
-extern void sirfsoc_prima2_timer_init(void);
-extern void sirfsoc_marco_timer_init(void);
+#define SIRFSOC_VA_BASE         _AC(0xFEC00000, UL)
+#define SIRFSOC_VA(x)           (SIRFSOC_VA_BASE + ((x) & 0x00FFF000))
 
 extern struct smp_operations   sirfsoc_smp_ops;
 extern void sirfsoc_secondary_startup(void);
diff --git a/arch/arm/mach-prima2/hotplug.c b/arch/arm/mach-prima2/hotplug.c
index f4b17cbababd..0ab2f8bae28e 100644
--- a/arch/arm/mach-prima2/hotplug.c
+++ b/arch/arm/mach-prima2/hotplug.c
@@ -10,13 +10,10 @@
 #include <linux/errno.h>
 #include <linux/smp.h>
 
-#include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 
 static inline void platform_do_lowpower(unsigned int cpu)
 {
-        flush_cache_all();
-
         /* we put the platform to just WFI */
         for (;;) {
                 __asm__ __volatile__("dsb\n\t" "wfi\n\t"
diff --git a/arch/arm/mach-prima2/include/mach/clkdev.h b/arch/arm/mach-prima2/include/mach/clkdev.h
deleted file mode 100644
index 66932518b1b7..000000000000
--- a/arch/arm/mach-prima2/include/mach/clkdev.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/clkdev.h
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef __MACH_CLKDEV_H
-#define __MACH_CLKDEV_H
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/mach-prima2/include/mach/debug-macro.S b/arch/arm/mach-prima2/include/mach/debug-macro.S
deleted file mode 100644
index cd97492bb075..000000000000
--- a/arch/arm/mach-prima2/include/mach/debug-macro.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/debug-macro.S
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#include <mach/hardware.h>
-#include <mach/uart.h>
-
-        .macro  addruart, rp, rv, tmp
-        ldr     \rp, =SIRFSOC_UART1_PA_BASE             @ physical
-        ldr     \rv, =SIRFSOC_UART1_VA_BASE             @ virtual
-        .endm
-
-        .macro  senduart,rd,rx
-        str     \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA]
-        .endm
-
-        .macro  busyuart,rd,rx
-        .endm
-
-        .macro  waituart,rd,rx
-1001:   ldr     \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS]
-        tst     \rd, #SIRFSOC_UART1_TXFIFO_EMPTY
-        beq     1001b
-        .endm
-
diff --git a/arch/arm/mach-prima2/include/mach/entry-macro.S b/arch/arm/mach-prima2/include/mach/entry-macro.S
deleted file mode 100644
index 86434e7a5be9..000000000000
--- a/arch/arm/mach-prima2/include/mach/entry-macro.S
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/entry-macro.S
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#include <mach/hardware.h>
-
-#define SIRFSOC_INT_ID 0x38
-
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =sirfsoc_intc_base
-        ldr     \base, [\base]
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr \irqnr, [\base, #SIRFSOC_INT_ID]    @ Get the highest priority irq
-        cmp \irqnr, #0x40                       @ the irq num can't be larger than 0x3f
-        movges \irqnr, #0
-        .endm
diff --git a/arch/arm/mach-prima2/include/mach/hardware.h b/arch/arm/mach-prima2/include/mach/hardware.h
deleted file mode 100644
index 105b96964f25..000000000000
--- a/arch/arm/mach-prima2/include/mach/hardware.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/hardware.h
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef __MACH_HARDWARE_H__
-#define __MACH_HARDWARE_H__
-
-#include <asm/sizes.h>
-#include <mach/map.h>
-
-#endif
diff --git a/arch/arm/mach-prima2/include/mach/irqs.h b/arch/arm/mach-prima2/include/mach/irqs.h
deleted file mode 100644
index b778a0f248ed..000000000000
--- a/arch/arm/mach-prima2/include/mach/irqs.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/irqs.h
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#define SIRFSOC_INTENAL_IRQ_START  0
-#define SIRFSOC_INTENAL_IRQ_END    127
-#define SIRFSOC_GPIO_IRQ_START     (SIRFSOC_INTENAL_IRQ_END + 1)
-#define NR_IRQS 288
-
-#endif
diff --git a/arch/arm/mach-prima2/include/mach/map.h b/arch/arm/mach-prima2/include/mach/map.h
deleted file mode 100644
index 6f243532570c..000000000000
--- a/arch/arm/mach-prima2/include/mach/map.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * memory & I/O static mapping definitions for CSR SiRFprimaII
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef __MACH_PRIMA2_MAP_H__
-#define __MACH_PRIMA2_MAP_H__
-
-#include <linux/const.h>
-
-#define SIRFSOC_VA_BASE         _AC(0xFEC00000, UL)
-
-#define SIRFSOC_VA(x)           (SIRFSOC_VA_BASE + ((x) & 0x00FFF000))
-
-#endif
diff --git a/arch/arm/mach-prima2/include/mach/timex.h b/arch/arm/mach-prima2/include/mach/timex.h
deleted file mode 100644
index d6f98a75e562..000000000000
--- a/arch/arm/mach-prima2/include/mach/timex.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/timex.h
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef __MACH_TIMEX_H__
-#define __MACH_TIMEX_H__
-
-#define CLOCK_TICK_RATE  1000000
-
-#endif
diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h
deleted file mode 100644
index d1513a33709a..000000000000
--- a/arch/arm/mach-prima2/include/mach/uncompress.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * arch/arm/mach-prima2/include/mach/uncompress.h
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/uart.h>
-
-void arch_decomp_setup(void)
-{
-}
-
-static __inline__ void putc(char c)
-{
-        /*
-         * during kernel decompression, all mappings are flat:
-         *  virt_addr == phys_addr
-         */
-        if (!SIRFSOC_UART1_PA_BASE)
-                return;
-
-        while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
-                & SIRFSOC_UART1_TXFIFO_FULL)
-                barrier();
-
-        __raw_writel(c, (void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA);
-}
-
-static inline void flush(void)
-{
-}
-
-#endif
-
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
deleted file mode 100644
index 6c0f3e9c43fb..000000000000
--- a/arch/arm/mach-prima2/irq.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * interrupt controller support for CSR SiRFprimaII
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/irqdomain.h>
-#include <linux/syscore_ops.h>
-#include <asm/mach/irq.h>
-#include <asm/exception.h>
-#include <mach/hardware.h>
-
-#define SIRFSOC_INT_RISC_MASK0          0x0018
-#define SIRFSOC_INT_RISC_MASK1          0x001C
-#define SIRFSOC_INT_RISC_LEVEL0         0x0020
-#define SIRFSOC_INT_RISC_LEVEL1         0x0024
-#define SIRFSOC_INIT_IRQ_ID             0x0038
-
-void __iomem *sirfsoc_intc_base;
-
-static __init void
-sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
-{
-        struct irq_chip_generic *gc;
-        struct irq_chip_type *ct;
-
-        gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
-        ct = gc->chip_types;
-
-        ct->chip.irq_mask = irq_gc_mask_clr_bit;
-        ct->chip.irq_unmask = irq_gc_mask_set_bit;
-        ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
-
-        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
-}
-
-static __init void sirfsoc_irq_init(void)
-{
-        sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
-        sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32,
-                        SIRFSOC_INTENAL_IRQ_END + 1 - 32);
-
-        writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
-        writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
-
-        writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
-        writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
-}
-
-asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
-{
-        u32 irqstat, irqnr;
-
-        irqstat = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INIT_IRQ_ID);
-        irqnr = irqstat & 0xff;
-
-        handle_IRQ(irqnr, regs);
-}
-
-static struct of_device_id intc_ids[]  = {
-        { .compatible = "sirf,prima2-intc" },
-        {},
-};
-
-void __init sirfsoc_of_irq_init(void)
-{
-        struct device_node *np;
-
-        np = of_find_matching_node(NULL, intc_ids);
-        if (!np)
-                return;
-
-        sirfsoc_intc_base = of_iomap(np, 0);
-        if (!sirfsoc_intc_base)
-                panic("unable to map intc cpu registers\n");
-
-        irq_domain_add_legacy(np, SIRFSOC_INTENAL_IRQ_END + 1, 0, 0,
-                &irq_domain_simple_ops, NULL);
-
-        of_node_put(np);
-
-        sirfsoc_irq_init();
-}
-
-struct sirfsoc_irq_status {
-        u32 mask0;
-        u32 mask1;
-        u32 level0;
-        u32 level1;
-};
-
-static struct sirfsoc_irq_status sirfsoc_irq_st;
-
-static int sirfsoc_irq_suspend(void)
-{
-        sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
-        sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
-        sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
-        sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
-
-        return 0;
-}
-
-static void sirfsoc_irq_resume(void)
-{
-        writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
-        writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
-        writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
-        writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
-}
-
-static struct syscore_ops sirfsoc_irq_syscore_ops = {
-        .suspend        = sirfsoc_irq_suspend,
-        .resume         = sirfsoc_irq_resume,
-};
-
-static int __init sirfsoc_irq_pm_init(void)
-{
-        register_syscore_ops(&sirfsoc_irq_syscore_ops);
-        return 0;
-}
-device_initcall(sirfsoc_irq_pm_init);
diff --git a/arch/arm/mach-prima2/lluart.c b/arch/arm/mach-prima2/lluart.c
index a89f9b3c8cc5..99c0c927ca4a 100644
--- a/arch/arm/mach-prima2/lluart.c
+++ b/arch/arm/mach-prima2/lluart.c
@@ -9,8 +9,18 @@
 #include <linux/kernel.h>
 #include <asm/page.h>
 #include <asm/mach/map.h>
-#include <mach/map.h>
-#include <mach/uart.h>
+#include "common.h"
+
+#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
+#define SIRFSOC_UART1_PA_BASE          0xb0060000
+#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1)
+#define SIRFSOC_UART1_PA_BASE          0xcc060000
+#else
+#define SIRFSOC_UART1_PA_BASE          0
+#endif
+
+#define SIRFSOC_UART1_VA_BASE          SIRFSOC_VA(0x060000)
+#define SIRFSOC_UART1_SIZE              SZ_4K
 
 void __init sirfsoc_map_lluart(void)
 {
diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c
index 4b788310f6a6..1c3de7bed841 100644
--- a/arch/arm/mach-prima2/platsmp.c
+++ b/arch/arm/mach-prima2/platsmp.c
@@ -11,14 +11,12 @@
 #include <linux/delay.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/irqchip/arm-gic.h>
 #include <asm/page.h>
 #include <asm/mach/map.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <asm/cacheflush.h>
 #include <asm/cputype.h>
-#include <mach/map.h>
 
 #include "common.h"
 
@@ -49,13 +47,6 @@ void __init sirfsoc_map_scu(void)
 static void __cpuinit sirfsoc_secondary_init(unsigned int cpu)
 {
         /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-
-        /*
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
diff --git a/arch/arm/mach-prima2/timer-marco.c b/arch/arm/mach-prima2/timer-marco.c
deleted file mode 100644
index f4eea2e97eb0..000000000000
--- a/arch/arm/mach-prima2/timer-marco.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
- * System timer for CSR SiRFprimaII
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/clockchips.h>
-#include <linux/clocksource.h>
-#include <linux/bitops.h>
-#include <linux/irq.h>
-#include <linux/clk.h>
-#include <linux/slab.h>
-#include <linux/of.h>
-#include <linux/of_irq.h>
-#include <linux/of_address.h>
-#include <asm/sched_clock.h>
-#include <asm/localtimer.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-
-#define SIRFSOC_TIMER_32COUNTER_0_CTRL                  0x0000
-#define SIRFSOC_TIMER_32COUNTER_1_CTRL                  0x0004
-#define SIRFSOC_TIMER_MATCH_0                           0x0018
-#define SIRFSOC_TIMER_MATCH_1                           0x001c
-#define SIRFSOC_TIMER_COUNTER_0                         0x0048
-#define SIRFSOC_TIMER_COUNTER_1                         0x004c
-#define SIRFSOC_TIMER_INTR_STATUS                       0x0060
-#define SIRFSOC_TIMER_WATCHDOG_EN                       0x0064
-#define SIRFSOC_TIMER_64COUNTER_CTRL                    0x0068
-#define SIRFSOC_TIMER_64COUNTER_LO                      0x006c
-#define SIRFSOC_TIMER_64COUNTER_HI                      0x0070
-#define SIRFSOC_TIMER_64COUNTER_LOAD_LO                 0x0074
-#define SIRFSOC_TIMER_64COUNTER_LOAD_HI                 0x0078
-#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO             0x007c
-#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI             0x0080
-
-#define SIRFSOC_TIMER_REG_CNT 6
-
-static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
-        SIRFSOC_TIMER_WATCHDOG_EN,
-        SIRFSOC_TIMER_32COUNTER_0_CTRL,
-        SIRFSOC_TIMER_32COUNTER_1_CTRL,
-        SIRFSOC_TIMER_64COUNTER_CTRL,
-        SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
-        SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
-};
-
-static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
-
-static void __iomem *sirfsoc_timer_base;
-static void __init sirfsoc_of_timer_map(void);
-
-/* disable count and interrupt */
-static inline void sirfsoc_timer_count_disable(int idx)
-{
-        writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
-                sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
-}
-
-/* enable count and interrupt */
-static inline void sirfsoc_timer_count_enable(int idx)
-{
-        writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7,
-                sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
-}
-
-/* timer interrupt handler */
-static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
-{
-        struct clock_event_device *ce = dev_id;
-        int cpu = smp_processor_id();
-
-        /* clear timer interrupt */
-        writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
-
-        if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
-                sirfsoc_timer_count_disable(cpu);
-
-        ce->event_handler(ce);
-
-        return IRQ_HANDLED;
-}
-
-/* read 64-bit timer counter */
-static cycle_t sirfsoc_timer_read(struct clocksource *cs)
-{
-        u64 cycles;
-
-        writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
-                        BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
-
-        cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
-        cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
-
-        return cycles;
-}
-
-static int sirfsoc_timer_set_next_event(unsigned long delta,
-        struct clock_event_device *ce)
-{
-        int cpu = smp_processor_id();
-
-        writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
-                4 * cpu);
-        writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
-                4 * cpu);
-
-        /* enable the tick */
-        sirfsoc_timer_count_enable(cpu);
-
-        return 0;
-}
-
-static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
-        struct clock_event_device *ce)
-{
-        switch (mode) {
-        case CLOCK_EVT_MODE_ONESHOT:
-                /* enable in set_next_event */
-                break;
-        default:
-                break;
-        }
-
-        sirfsoc_timer_count_disable(smp_processor_id());
-}
-
-static void sirfsoc_clocksource_suspend(struct clocksource *cs)
-{
-        int i;
-
-        for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
-                sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
-}
-
-static void sirfsoc_clocksource_resume(struct clocksource *cs)
-{
-        int i;
-
-        for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
-                writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
-
-        writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
-                sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
-        writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
-                sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
-
-        writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
-                BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
-}
-
-static struct clock_event_device sirfsoc_clockevent = {
-        .name = "sirfsoc_clockevent",
-        .rating = 200,
-        .features = CLOCK_EVT_FEAT_ONESHOT,
-        .set_mode = sirfsoc_timer_set_mode,
-        .set_next_event = sirfsoc_timer_set_next_event,
-};
-
-static struct clocksource sirfsoc_clocksource = {
-        .name = "sirfsoc_clocksource",
-        .rating = 200,
-        .mask = CLOCKSOURCE_MASK(64),
-        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-        .read = sirfsoc_timer_read,
-        .suspend = sirfsoc_clocksource_suspend,
-        .resume = sirfsoc_clocksource_resume,
-};
-
-static struct irqaction sirfsoc_timer_irq = {
-        .name = "sirfsoc_timer0",
-        .flags = IRQF_TIMER | IRQF_NOBALANCING,
-        .handler = sirfsoc_timer_interrupt,
-        .dev_id = &sirfsoc_clockevent,
-};
-
-#ifdef CONFIG_LOCAL_TIMERS
-
-static struct irqaction sirfsoc_timer1_irq = {
-        .name = "sirfsoc_timer1",
-        .flags = IRQF_TIMER | IRQF_NOBALANCING,
-        .handler = sirfsoc_timer_interrupt,
-};
-
-static int __cpuinit sirfsoc_local_timer_setup(struct clock_event_device *ce)
-{
-        /* Use existing clock_event for cpu 0 */
-        if (!smp_processor_id())
-                return 0;
-
-        ce->irq = sirfsoc_timer1_irq.irq;
-        ce->name = "local_timer";
-        ce->features = sirfsoc_clockevent.features;
-        ce->rating = sirfsoc_clockevent.rating;
-        ce->set_mode = sirfsoc_timer_set_mode;
-        ce->set_next_event = sirfsoc_timer_set_next_event;
-        ce->shift = sirfsoc_clockevent.shift;
-        ce->mult = sirfsoc_clockevent.mult;
-        ce->max_delta_ns = sirfsoc_clockevent.max_delta_ns;
-        ce->min_delta_ns = sirfsoc_clockevent.min_delta_ns;
-
-        sirfsoc_timer1_irq.dev_id = ce;
-        BUG_ON(setup_irq(ce->irq, &sirfsoc_timer1_irq));
-        irq_set_affinity(sirfsoc_timer1_irq.irq, cpumask_of(1));
-
-        clockevents_register_device(ce);
-        return 0;
-}
-
-static void sirfsoc_local_timer_stop(struct clock_event_device *ce)
-{
-        sirfsoc_timer_count_disable(1);
-
-        remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
-}
-
-static struct local_timer_ops sirfsoc_local_timer_ops __cpuinitdata = {
-        .setup  = sirfsoc_local_timer_setup,
-        .stop   = sirfsoc_local_timer_stop,
-};
-#endif /* CONFIG_LOCAL_TIMERS */
-
-static void __init sirfsoc_clockevent_init(void)
-{
-        clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60);
-
-        sirfsoc_clockevent.max_delta_ns =
-                clockevent_delta2ns(-2, &sirfsoc_clockevent);
-        sirfsoc_clockevent.min_delta_ns =
-                clockevent_delta2ns(2, &sirfsoc_clockevent);
-
-        sirfsoc_clockevent.cpumask = cpumask_of(0);
-        clockevents_register_device(&sirfsoc_clockevent);
-#ifdef CONFIG_LOCAL_TIMERS
-        local_timer_register(&sirfsoc_local_timer_ops);
-#endif
-}
-
-/* initialize the kernel jiffy timer source */
-void __init sirfsoc_marco_timer_init(void)
-{
-        unsigned long rate;
-        u32 timer_div;
-        struct clk *clk;
-
-        /* initialize clocking early, we want to set the OS timer */
-        sirfsoc_of_clk_init();
-
-        /* timer's input clock is io clock */
-        clk = clk_get_sys("io", NULL);
-
-        BUG_ON(IS_ERR(clk));
-        rate = clk_get_rate(clk);
-
-        BUG_ON(rate < CLOCK_TICK_RATE);
-        BUG_ON(rate % CLOCK_TICK_RATE);
-
-        sirfsoc_of_timer_map();
-
-        /* Initialize the timer dividers */
-        timer_div = rate / CLOCK_TICK_RATE - 1;
-        writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
-        writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
-        writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
-
-        /* Initialize timer counters to 0 */
-        writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
-        writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
-        writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
-                BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
-        writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
-        writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
-
-        /* Clear all interrupts */
-        writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
-
-        BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
-
-        BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
-
-        sirfsoc_clockevent_init();
-}
-
-static struct of_device_id timer_ids[] = {
-        { .compatible = "sirf,marco-tick" },
-        {},
-};
-
-static void __init sirfsoc_of_timer_map(void)
-{
-        struct device_node *np;
-
-        np = of_find_matching_node(NULL, timer_ids);
-        if (!np)
-                return;
-        sirfsoc_timer_base = of_iomap(np, 0);
-        if (!sirfsoc_timer_base)
-                panic("unable to map timer cpu registers\n");
-
-        sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
-        if (!sirfsoc_timer_irq.irq)
-                panic("No irq passed for timer0 via DT\n");
-
-#ifdef CONFIG_LOCAL_TIMERS
-        sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
-        if (!sirfsoc_timer1_irq.irq)
-                panic("No irq passed for timer1 via DT\n");
-#endif
-
-        of_node_put(np);
-}
diff --git a/arch/arm/mach-prima2/timer-prima2.c b/arch/arm/mach-prima2/timer-prima2.c
deleted file mode 100644
index 6da584f8a949..000000000000
--- a/arch/arm/mach-prima2/timer-prima2.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * System timer for CSR SiRFprimaII
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/clockchips.h>
-#include <linux/clocksource.h>
-#include <linux/bitops.h>
-#include <linux/irq.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/slab.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <mach/map.h>
-#include <asm/sched_clock.h>
-#include <asm/mach/time.h>
-
-#include "common.h"
-
-#define SIRFSOC_TIMER_COUNTER_LO        0x0000
-#define SIRFSOC_TIMER_COUNTER_HI        0x0004
-#define SIRFSOC_TIMER_MATCH_0           0x0008
-#define SIRFSOC_TIMER_MATCH_1           0x000C
-#define SIRFSOC_TIMER_MATCH_2           0x0010
-#define SIRFSOC_TIMER_MATCH_3           0x0014
-#define SIRFSOC_TIMER_MATCH_4           0x0018
-#define SIRFSOC_TIMER_MATCH_5           0x001C
-#define SIRFSOC_TIMER_STATUS            0x0020
-#define SIRFSOC_TIMER_INT_EN            0x0024
-#define SIRFSOC_TIMER_WATCHDOG_EN       0x0028
-#define SIRFSOC_TIMER_DIV               0x002C
-#define SIRFSOC_TIMER_LATCH             0x0030
-#define SIRFSOC_TIMER_LATCHED_LO        0x0034
-#define SIRFSOC_TIMER_LATCHED_HI        0x0038
-
-#define SIRFSOC_TIMER_WDT_INDEX         5
-
-#define SIRFSOC_TIMER_LATCH_BIT  BIT(0)
-
-#define SIRFSOC_TIMER_REG_CNT 11
-
-static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
-        SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2,
-        SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5,
-        SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV,
-        SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI,
-};
-
-static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
-
-static void __iomem *sirfsoc_timer_base;
-static void __init sirfsoc_of_timer_map(void);
-
-/* timer0 interrupt handler */
-static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
-{
-        struct clock_event_device *ce = dev_id;
-
-        WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & BIT(0)));
-
-        /* clear timer0 interrupt */
-        writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
-
-        ce->event_handler(ce);
-
-        return IRQ_HANDLED;
-}
-
-/* read 64-bit timer counter */
-static cycle_t sirfsoc_timer_read(struct clocksource *cs)
-{
-        u64 cycles;
-
-        /* latch the 64-bit timer counter */
-        writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
-        cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
-        cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
-
-        return cycles;
-}
-
-static int sirfsoc_timer_set_next_event(unsigned long delta,
-        struct clock_event_device *ce)
-{
-        unsigned long now, next;
-
-        writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
-        now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
-        next = now + delta;
-        writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
-        writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
-        now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
-
-        return next - now > delta ? -ETIME : 0;
-}
-
-static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
-        struct clock_event_device *ce)
-{
-        u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                WARN_ON(1);
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-                writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
-                break;
-        case CLOCK_EVT_MODE_SHUTDOWN:
-                writel_relaxed(val & ~BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
-                break;
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_RESUME:
-                break;
-        }
-}
-
-static void sirfsoc_clocksource_suspend(struct clocksource *cs)
-{
-        int i;
-
-        writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
-
-        for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
-                sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
-}
-
-static void sirfsoc_clocksource_resume(struct clocksource *cs)
-{
-        int i;
-
-        for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
-                writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
-
-        writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
-        writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
-}
-
-static struct clock_event_device sirfsoc_clockevent = {
-        .name = "sirfsoc_clockevent",
-        .rating = 200,
-        .features = CLOCK_EVT_FEAT_ONESHOT,
-        .set_mode = sirfsoc_timer_set_mode,
-        .set_next_event = sirfsoc_timer_set_next_event,
-};
-
-static struct clocksource sirfsoc_clocksource = {
-        .name = "sirfsoc_clocksource",
-        .rating = 200,
-        .mask = CLOCKSOURCE_MASK(64),
-        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-        .read = sirfsoc_timer_read,
-        .suspend = sirfsoc_clocksource_suspend,
-        .resume = sirfsoc_clocksource_resume,
-};
-
-static struct irqaction sirfsoc_timer_irq = {
-        .name = "sirfsoc_timer0",
-        .flags = IRQF_TIMER,
-        .irq = 0,
-        .handler = sirfsoc_timer_interrupt,
-        .dev_id = &sirfsoc_clockevent,
-};
-
-/* Overwrite weak default sched_clock with more precise one */
-static u32 notrace sirfsoc_read_sched_clock(void)
-{
-        return (u32)(sirfsoc_timer_read(NULL) & 0xffffffff);
-}
-
-static void __init sirfsoc_clockevent_init(void)
-{
-        sirfsoc_clockevent.cpumask = cpumask_of(0);
-        clockevents_config_and_register(&sirfsoc_clockevent, CLOCK_TICK_RATE,
-                                        2, -2);
-}
-
-/* initialize the kernel jiffy timer source */
-void __init sirfsoc_prima2_timer_init(void)
-{
-        unsigned long rate;
-        struct clk *clk;
-
-        /* initialize clocking early, we want to set the OS timer */
-        sirfsoc_of_clk_init();
-
-        /* timer's input clock is io clock */
-        clk = clk_get_sys("io", NULL);
-
-        BUG_ON(IS_ERR(clk));
-
-        rate = clk_get_rate(clk);
-
-        BUG_ON(rate < CLOCK_TICK_RATE);
-        BUG_ON(rate % CLOCK_TICK_RATE);
-
-        sirfsoc_of_timer_map();
-
-        writel_relaxed(rate / CLOCK_TICK_RATE / 2 - 1, sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
-        writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
-        writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
-        writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
-
-        BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
-
-        setup_sched_clock(sirfsoc_read_sched_clock, 32, CLOCK_TICK_RATE);
-
-        BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
-
-        sirfsoc_clockevent_init();
-}
-
-static struct of_device_id timer_ids[] = {
-        { .compatible = "sirf,prima2-tick" },
-        {},
-};
-
-static void __init sirfsoc_of_timer_map(void)
-{
-        struct device_node *np;
-        const unsigned int *intspec;
-
-        np = of_find_matching_node(NULL, timer_ids);
-        if (!np)
-                return;
-        sirfsoc_timer_base = of_iomap(np, 0);
-        if (!sirfsoc_timer_base)
-                panic("unable to map timer cpu registers\n");
-
-        /* Get the interrupts property */
-        intspec = of_get_property(np, "interrupts", NULL);
-        BUG_ON(!intspec);
-        sirfsoc_timer_irq.irq = be32_to_cpup(intspec);
-
-        of_node_put(np);
-}
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 86eec4159cbc..9075461999c1 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -51,11 +51,13 @@ config MACH_LITTLETON
 config MACH_TAVOREVB
         bool "PXA930 Evaluation Board (aka TavorEVB)"
         select CPU_PXA930
+        select CPU_PXA935
         select PXA3xx
 
 config MACH_SAAR
         bool "PXA930 Handheld Platform (aka SAAR)"
         select CPU_PXA930
+        select CPU_PXA935
         select PXA3xx
 
 comment "Third Party Dev Platforms (sorted by vendor name)"
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 12c500558387..648867a8caa8 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -7,12 +7,6 @@ obj-y				+= clock.o devices.o generic.o irq.o \
                                    time.o reset.o
 obj-$(CONFIG_PM)                += pm.o sleep.o standby.o
 
-ifeq ($(CONFIG_CPU_FREQ),y)
-obj-$(CONFIG_PXA25x)            += cpufreq-pxa2xx.o
-obj-$(CONFIG_PXA27x)            += cpufreq-pxa2xx.o
-obj-$(CONFIG_PXA3xx)            += cpufreq-pxa3xx.o
-endif
-
 # Generic drivers that other drivers may depend upon
 
 # SoC-specific code
diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
deleted file mode 100644
index 6a7aeab42f6c..000000000000
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ /dev/null
@@ -1,494 +0,0 @@
-/*
- *  linux/arch/arm/mach-pxa/cpufreq-pxa2xx.c
- *
- *  Copyright (C) 2002,2003 Intrinsyc Software
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- * History:
- *   31-Jul-2002 : Initial version [FB]
- *   29-Jan-2003 : added PXA255 support [FB]
- *   20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
- *
- * Note:
- *   This driver may change the memory bus clock rate, but will not do any
- *   platform specific access timing changes... for example if you have flash
- *   memory connected to CS0, you will need to register a platform specific
- *   notifier which will adjust the memory access strobes to maintain a
- *   minimum strobe width.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/cpufreq.h>
-#include <linux/err.h>
-#include <linux/regulator/consumer.h>
-#include <linux/io.h>
-
-#include <mach/pxa2xx-regs.h>
-#include <mach/smemc.h>
-
-#ifdef DEBUG
-static unsigned int freq_debug;
-module_param(freq_debug, uint, 0);
-MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
-#else
-#define freq_debug  0
-#endif
-
-static struct regulator *vcc_core;
-
-static unsigned int pxa27x_maxfreq;
-module_param(pxa27x_maxfreq, uint, 0);
-MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
-                 "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
-
-typedef struct {
-        unsigned int khz;
-        unsigned int membus;
-        unsigned int cccr;
-        unsigned int div2;
-        unsigned int cclkcfg;
-        int vmin;
-        int vmax;
-} pxa_freqs_t;
-
-/* Define the refresh period in mSec for the SDRAM and the number of rows */
-#define SDRAM_TREF      64      /* standard 64ms SDRAM */
-static unsigned int sdram_rows;
-
-#define CCLKCFG_TURBO           0x1
-#define CCLKCFG_FCS             0x2
-#define CCLKCFG_HALFTURBO       0x4
-#define CCLKCFG_FASTBUS         0x8
-#define MDREFR_DB2_MASK         (MDREFR_K2DB2 | MDREFR_K1DB2)
-#define MDREFR_DRI_MASK         0xFFF
-
-#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
-#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
-
-/*
- * PXA255 definitions
- */
-/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
-#define CCLKCFG                 CCLKCFG_TURBO | CCLKCFG_FCS
-
-static pxa_freqs_t pxa255_run_freqs[] =
-{
-        /* CPU   MEMBUS  CCCR  DIV2 CCLKCFG                run  turbo PXbus SDRAM */
-        { 99500,  99500, 0x121, 1,  CCLKCFG, -1, -1},   /*  99,   99,   50,   50  */
-        {132700, 132700, 0x123, 1,  CCLKCFG, -1, -1},   /* 133,  133,   66,   66  */
-        {199100,  99500, 0x141, 0,  CCLKCFG, -1, -1},   /* 199,  199,   99,   99  */
-        {265400, 132700, 0x143, 1,  CCLKCFG, -1, -1},   /* 265,  265,  133,   66  */
-        {331800, 165900, 0x145, 1,  CCLKCFG, -1, -1},   /* 331,  331,  166,   83  */
-        {398100,  99500, 0x161, 0,  CCLKCFG, -1, -1},   /* 398,  398,  196,   99  */
-};
-
-/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
-static pxa_freqs_t pxa255_turbo_freqs[] =
-{
-        /* CPU   MEMBUS  CCCR  DIV2 CCLKCFG        run  turbo PXbus SDRAM */
-        { 99500, 99500,  0x121, 1,  CCLKCFG, -1, -1},   /*  99,   99,   50,   50  */
-        {199100, 99500,  0x221, 0,  CCLKCFG, -1, -1},   /*  99,  199,   50,   99  */
-        {298500, 99500,  0x321, 0,  CCLKCFG, -1, -1},   /*  99,  287,   50,   99  */
-        {298600, 99500,  0x1c1, 0,  CCLKCFG, -1, -1},   /* 199,  287,   99,   99  */
-        {398100, 99500,  0x241, 0,  CCLKCFG, -1, -1},   /* 199,  398,   99,   99  */
-};
-
-#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
-#define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
-
-static struct cpufreq_frequency_table
-        pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
-static struct cpufreq_frequency_table
-        pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
-
-static unsigned int pxa255_turbo_table;
-module_param(pxa255_turbo_table, uint, 0);
-MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");
-
-/*
- * PXA270 definitions
- *
- * For the PXA27x:
- * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
- *
- * A = 0 => memory controller clock from table 3-7,
- * A = 1 => memory controller clock = system bus clock
- * Run mode frequency   = 13 MHz * L
- * Turbo mode frequency = 13 MHz * L * N
- * System bus frequency = 13 MHz * L / (B + 1)
- *
- * In CCCR:
- * A = 1
- * L = 16         oscillator to run mode ratio
- * 2N = 6         2 * (turbo mode to run mode ratio)
- *
- * In CCLKCFG:
- * B = 1          Fast bus mode
- * HT = 0         Half-Turbo mode
- * T = 1          Turbo mode
- *
- * For now, just support some of the combinations in table 3-7 of
- * PXA27x Processor Family Developer's Manual to simplify frequency
- * change sequences.
- */
-#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
-#define CCLKCFG2(B, HT, T) \
-  (CCLKCFG_FCS | \
-   ((B)  ? CCLKCFG_FASTBUS : 0) | \
-   ((HT) ? CCLKCFG_HALFTURBO : 0) | \
-   ((T)  ? CCLKCFG_TURBO : 0))
-
-static pxa_freqs_t pxa27x_freqs[] = {
-        {104000, 104000, PXA27x_CCCR(1,  8, 2), 0, CCLKCFG2(1, 0, 1),  900000, 1705000 },
-        {156000, 104000, PXA27x_CCCR(1,  8, 3), 0, CCLKCFG2(1, 0, 1), 1000000, 1705000 },
-        {208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1), 1180000, 1705000 },
-        {312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1), 1250000, 1705000 },
-        {416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1), 1350000, 1705000 },
-        {520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1), 1450000, 1705000 },
-        {624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1), 1550000, 1705000 }
-};
-
-#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
-static struct cpufreq_frequency_table
-        pxa27x_freq_table[NUM_PXA27x_FREQS+1];
-
-extern unsigned get_clk_frequency_khz(int info);
-
-#ifdef CONFIG_REGULATOR
-
-static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq)
-{
-        int ret = 0;
-        int vmin, vmax;
-
-        if (!cpu_is_pxa27x())
-                return 0;
-
-        vmin = pxa_freq->vmin;
-        vmax = pxa_freq->vmax;
-        if ((vmin == -1) || (vmax == -1))
-                return 0;
-
-        ret = regulator_set_voltage(vcc_core, vmin, vmax);
-        if (ret)
-                pr_err("cpufreq: Failed to set vcc_core in [%dmV..%dmV]\n",
-                       vmin, vmax);
-        return ret;
-}
-
-static __init void pxa_cpufreq_init_voltages(void)
-{
-        vcc_core = regulator_get(NULL, "vcc_core");
-        if (IS_ERR(vcc_core)) {
-                pr_info("cpufreq: Didn't find vcc_core regulator\n");
-                vcc_core = NULL;
-        } else {
-                pr_info("cpufreq: Found vcc_core regulator\n");
-        }
-}
-#else
-static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq)
-{
-        return 0;
-}
-
-static __init void pxa_cpufreq_init_voltages(void) { }
-#endif
-
-static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
-                             pxa_freqs_t **pxa_freqs)
-{
-        if (cpu_is_pxa25x()) {
-                if (!pxa255_turbo_table) {
-                        *pxa_freqs = pxa255_run_freqs;
-                        *freq_table = pxa255_run_freq_table;
-                } else {
-                        *pxa_freqs = pxa255_turbo_freqs;
-                        *freq_table = pxa255_turbo_freq_table;
-                }
-        }
-        if (cpu_is_pxa27x()) {
-                *pxa_freqs = pxa27x_freqs;
-                *freq_table = pxa27x_freq_table;
-        }
-}
-
-static void pxa27x_guess_max_freq(void)
-{
-        if (!pxa27x_maxfreq) {
-                pxa27x_maxfreq = 416000;
-                printk(KERN_INFO "PXA CPU 27x max frequency not defined "
-                       "(pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
-                       pxa27x_maxfreq);
-        } else {
-                pxa27x_maxfreq *= 1000;
-        }
-}
-
-static void init_sdram_rows(void)
-{
-        uint32_t mdcnfg = __raw_readl(MDCNFG);
-        unsigned int drac2 = 0, drac0 = 0;
-
-        if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
-                drac2 = MDCNFG_DRAC2(mdcnfg);
-
-        if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
-                drac0 = MDCNFG_DRAC0(mdcnfg);
-
-        sdram_rows = 1 << (11 + max(drac0, drac2));
-}
-
-static u32 mdrefr_dri(unsigned int freq)
-{
-        u32 interval = freq * SDRAM_TREF / sdram_rows;
-
-        return (interval - (cpu_is_pxa27x() ? 31 : 0)) / 32;
-}
-
-/* find a valid frequency point */
-static int pxa_verify_policy(struct cpufreq_policy *policy)
-{
-        struct cpufreq_frequency_table *pxa_freqs_table;
-        pxa_freqs_t *pxa_freqs;
-        int ret;
-
-        find_freq_tables(&pxa_freqs_table, &pxa_freqs);
-        ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
-
-        if (freq_debug)
-                pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n",
-                         policy->min, policy->max);
-
-        return ret;
-}
-
-static unsigned int pxa_cpufreq_get(unsigned int cpu)
-{
-        return get_clk_frequency_khz(0);
-}
-
-static int pxa_set_target(struct cpufreq_policy *policy,
-                          unsigned int target_freq,
-                          unsigned int relation)
-{
-        struct cpufreq_frequency_table *pxa_freqs_table;
-        pxa_freqs_t *pxa_freq_settings;
-        struct cpufreq_freqs freqs;
-        unsigned int idx;
-        unsigned long flags;
-        unsigned int new_freq_cpu, new_freq_mem;
-        unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
-        int ret = 0;
-
-        /* Get the current policy */
-        find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
-
-        /* Lookup the next frequency */
-        if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
-                                           target_freq, relation, &idx)) {
-                return -EINVAL;
-        }
-
-        new_freq_cpu = pxa_freq_settings[idx].khz;
-        new_freq_mem = pxa_freq_settings[idx].membus;
-        freqs.old = policy->cur;
-        freqs.new = new_freq_cpu;
-        freqs.cpu = policy->cpu;
-
-        if (freq_debug)
-                pr_debug("Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n",
-                         freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
-                         (new_freq_mem / 2000) : (new_freq_mem / 1000));
-
-        if (vcc_core && freqs.new > freqs.old)
-                ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
-        if (ret)
-                return ret;
-        /*
-         * Tell everyone what we're about to do...
-         * you should add a notify client with any platform specific
-         * Vcc changing capability
-         */
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
-        /* Calculate the next MDREFR.  If we're slowing down the SDRAM clock
-         * we need to preset the smaller DRI before the change.  If we're
-         * speeding up we need to set the larger DRI value after the change.
-         */
-        preset_mdrefr = postset_mdrefr = __raw_readl(MDREFR);
-        if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
-                preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
-                preset_mdrefr |= mdrefr_dri(new_freq_mem);
-        }
-        postset_mdrefr =
-                (postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem);
-
-        /* If we're dividing the memory clock by two for the SDRAM clock, this
-         * must be set prior to the change.  Clearing the divide must be done
-         * after the change.
-         */
-        if (pxa_freq_settings[idx].div2) {
-                preset_mdrefr  |= MDREFR_DB2_MASK;
-                postset_mdrefr |= MDREFR_DB2_MASK;
-        } else {
-                postset_mdrefr &= ~MDREFR_DB2_MASK;
-        }
-
-        local_irq_save(flags);
-
-        /* Set new the CCCR and prepare CCLKCFG */
-        CCCR = pxa_freq_settings[idx].cccr;
-        cclkcfg = pxa_freq_settings[idx].cclkcfg;
-
-        asm volatile("                                                  \n\
-                ldr     r4, [%1]                /* load MDREFR */       \n\
-                b       2f                                              \n\
-                .align  5                                               \n\
-1:                                                                      \n\
-                str     %3, [%1]                /* preset the MDREFR */ \n\
-                mcr     p14, 0, %2, c6, c0, 0   /* set CCLKCFG[FCS] */  \n\
-                str     %4, [%1]                /* postset the MDREFR */ \n\
-                                                                        \n\
-                b       3f                                              \n\
-2:              b       1b                                              \n\
-3:              nop                                                     \n\
-          "
-                     : "=&r" (unused)
-                     : "r" (MDREFR), "r" (cclkcfg),
-                       "r" (preset_mdrefr), "r" (postset_mdrefr)
-                     : "r4", "r5");
-        local_irq_restore(flags);
-
-        /*
-         * Tell everyone what we've just done...
-         * you should add a notify client with any platform specific
-         * SDRAM refresh timer adjustments
-         */
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
-        /*
-         * Even if voltage setting fails, we don't report it, as the frequency
-         * change succeeded. The voltage reduction is not a critical failure,
-         * only power savings will suffer from this.
-         *
-         * Note: if the voltage change fails, and a return value is returned, a
-         * bug is triggered (seems a deadlock). Should anybody find out where,
-         * the "return 0" should become a "return ret".
-         */
-        if (vcc_core && freqs.new < freqs.old)
-                ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
-
-        return 0;
-}
-
-static int pxa_cpufreq_init(struct cpufreq_policy *policy)
-{
-        int i;
-        unsigned int freq;
-        struct cpufreq_frequency_table *pxa255_freq_table;
-        pxa_freqs_t *pxa255_freqs;
-
-        /* try to guess pxa27x cpu */
-        if (cpu_is_pxa27x())
-                pxa27x_guess_max_freq();
-
-        pxa_cpufreq_init_voltages();
-
-        init_sdram_rows();
-
-        /* set default policy and cpuinfo */
-        policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
-        policy->cur = get_clk_frequency_khz(0);    /* current freq */
-        policy->min = policy->max = policy->cur;
-
-        /* Generate pxa25x the run cpufreq_frequency_table struct */
-        for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
-                pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
-                pxa255_run_freq_table[i].index = i;
-        }
-        pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
-
-        /* Generate pxa25x the turbo cpufreq_frequency_table struct */
-        for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
-                pxa255_turbo_freq_table[i].frequency =
-                        pxa255_turbo_freqs[i].khz;
-                pxa255_turbo_freq_table[i].index = i;
-        }
-        pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
-
-        pxa255_turbo_table = !!pxa255_turbo_table;
-
-        /* Generate the pxa27x cpufreq_frequency_table struct */
-        for (i = 0; i < NUM_PXA27x_FREQS; i++) {
-                freq = pxa27x_freqs[i].khz;
-                if (freq > pxa27x_maxfreq)
-                        break;
-                pxa27x_freq_table[i].frequency = freq;
-                pxa27x_freq_table[i].index = i;
-        }
-        pxa27x_freq_table[i].index = i;
-        pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;
-
-        /*
-         * Set the policy's minimum and maximum frequencies from the tables
-         * just constructed.  This sets cpuinfo.mxx_freq, min and max.
-         */
-        if (cpu_is_pxa25x()) {
-                find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
-                pr_info("PXA255 cpufreq using %s frequency table\n",
-                        pxa255_turbo_table ? "turbo" : "run");
-                cpufreq_frequency_table_cpuinfo(policy, pxa255_freq_table);
-        }
-        else if (cpu_is_pxa27x())
-                cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table);
-
-        printk(KERN_INFO "PXA CPU frequency change support initialized\n");
-
-        return 0;
-}
-
-static struct cpufreq_driver pxa_cpufreq_driver = {
-        .verify = pxa_verify_policy,
-        .target = pxa_set_target,
-        .init   = pxa_cpufreq_init,
-        .get    = pxa_cpufreq_get,
-        .name   = "PXA2xx",
-};
-
-static int __init pxa_cpu_init(void)
-{
-        int ret = -ENODEV;
-        if (cpu_is_pxa25x() || cpu_is_pxa27x())
-                ret = cpufreq_register_driver(&pxa_cpufreq_driver);
-        return ret;
-}
-
-static void __exit pxa_cpu_exit(void)
-{
-        cpufreq_unregister_driver(&pxa_cpufreq_driver);
-}
-
-
-MODULE_AUTHOR("Intrinsyc Software Inc.");
-MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
-MODULE_LICENSE("GPL");
-module_init(pxa_cpu_init);
-module_exit(pxa_cpu_exit);
diff --git a/arch/arm/mach-pxa/cpufreq-pxa3xx.c b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
deleted file mode 100644
index b85b4ab7aac6..000000000000
--- a/arch/arm/mach-pxa/cpufreq-pxa3xx.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/cpufreq-pxa3xx.c
- *
- * Copyright (C) 2008 Marvell International Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/cpufreq.h>
-#include <linux/slab.h>
-#include <linux/io.h>
-
-#include <mach/pxa3xx-regs.h>
-
-#include "generic.h"
-
-#define HSS_104M        (0)
-#define HSS_156M        (1)
-#define HSS_208M        (2)
-#define HSS_312M        (3)
-
-#define SMCFS_78M       (0)
-#define SMCFS_104M      (2)
-#define SMCFS_208M      (5)
-
-#define SFLFS_104M      (0)
-#define SFLFS_156M      (1)
-#define SFLFS_208M      (2)
-#define SFLFS_312M      (3)
-
-#define XSPCLK_156M     (0)
-#define XSPCLK_NONE     (3)
-
-#define DMCFS_26M       (0)
-#define DMCFS_260M      (3)
-
-struct pxa3xx_freq_info {
-        unsigned int cpufreq_mhz;
-        unsigned int core_xl : 5;
-        unsigned int core_xn : 3;
-        unsigned int hss : 2;
-        unsigned int dmcfs : 2;
-        unsigned int smcfs : 3;
-        unsigned int sflfs : 2;
-        unsigned int df_clkdiv : 3;
-
-        int     vcc_core;       /* in mV */
-        int     vcc_sram;       /* in mV */
-};
-
-#define OP(cpufreq, _xl, _xn, _hss, _dmc, _smc, _sfl, _dfi, vcore, vsram) \
-{                                                                       \
-        .cpufreq_mhz    = cpufreq,                                      \
-        .core_xl        = _xl,                                          \
-        .core_xn        = _xn,                                          \
-        .hss            = HSS_##_hss##M,                                \
-        .dmcfs          = DMCFS_##_dmc##M,                              \
-        .smcfs          = SMCFS_##_smc##M,                              \
-        .sflfs          = SFLFS_##_sfl##M,                              \
-        .df_clkdiv      = _dfi,                                         \
-        .vcc_core       = vcore,                                        \
-        .vcc_sram       = vsram,                                        \
-}
-
-static struct pxa3xx_freq_info pxa300_freqs[] = {
-        /*  CPU XL XN  HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
-        OP(104,  8, 1, 104, 260,  78, 104, 3, 1000, 1100), /* 104MHz */
-        OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
-        OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
-        OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
-};
-
-static struct pxa3xx_freq_info pxa320_freqs[] = {
-        /*  CPU XL XN  HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
-        OP(104,  8, 1, 104, 260,  78, 104, 3, 1000, 1100), /* 104MHz */
-        OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
-        OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
-        OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
-        OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
-};
-
-static unsigned int pxa3xx_freqs_num;
-static struct pxa3xx_freq_info *pxa3xx_freqs;
-static struct cpufreq_frequency_table *pxa3xx_freqs_table;
-
-static int setup_freqs_table(struct cpufreq_policy *policy,
-                             struct pxa3xx_freq_info *freqs, int num)
-{
-        struct cpufreq_frequency_table *table;
-        int i;
-
-        table = kzalloc((num + 1) * sizeof(*table), GFP_KERNEL);
-        if (table == NULL)
-                return -ENOMEM;
-
-        for (i = 0; i < num; i++) {
-                table[i].index = i;
-                table[i].frequency = freqs[i].cpufreq_mhz * 1000;
-        }
-        table[num].index = i;
-        table[num].frequency = CPUFREQ_TABLE_END;
-
-        pxa3xx_freqs = freqs;
-        pxa3xx_freqs_num = num;
-        pxa3xx_freqs_table = table;
-
-        return cpufreq_frequency_table_cpuinfo(policy, table);
-}
-
-static void __update_core_freq(struct pxa3xx_freq_info *info)
-{
-        uint32_t mask = ACCR_XN_MASK | ACCR_XL_MASK;
-        uint32_t accr = ACCR;
-        uint32_t xclkcfg;
-
-        accr &= ~(ACCR_XN_MASK | ACCR_XL_MASK | ACCR_XSPCLK_MASK);
-        accr |= ACCR_XN(info->core_xn) | ACCR_XL(info->core_xl);
-
-        /* No clock until core PLL is re-locked */
-        accr |= ACCR_XSPCLK(XSPCLK_NONE);
-
-        xclkcfg = (info->core_xn == 2) ? 0x3 : 0x2;     /* turbo bit */
-
-        ACCR = accr;
-        __asm__("mcr p14, 0, %0, c6, c0, 0\n" : : "r"(xclkcfg));
-
-        while ((ACSR & mask) != (accr & mask))
-                cpu_relax();
-}
-
-static void __update_bus_freq(struct pxa3xx_freq_info *info)
-{
-        uint32_t mask;
-        uint32_t accr = ACCR;
-
-        mask = ACCR_SMCFS_MASK | ACCR_SFLFS_MASK | ACCR_HSS_MASK |
-                ACCR_DMCFS_MASK;
-
-        accr &= ~mask;
-        accr |= ACCR_SMCFS(info->smcfs) | ACCR_SFLFS(info->sflfs) |
-                ACCR_HSS(info->hss) | ACCR_DMCFS(info->dmcfs);
-
-        ACCR = accr;
-
-        while ((ACSR & mask) != (accr & mask))
-                cpu_relax();
-}
-
-static int pxa3xx_cpufreq_verify(struct cpufreq_policy *policy)
-{
-        return cpufreq_frequency_table_verify(policy, pxa3xx_freqs_table);
-}
-
-static unsigned int pxa3xx_cpufreq_get(unsigned int cpu)
-{
-        return pxa3xx_get_clk_frequency_khz(0);
-}
-
-static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy,
-                              unsigned int target_freq,
-                              unsigned int relation)
-{
-        struct pxa3xx_freq_info *next;
-        struct cpufreq_freqs freqs;
-        unsigned long flags;
-        int idx;
-
-        if (policy->cpu != 0)
-                return -EINVAL;
-
-        /* Lookup the next frequency */
-        if (cpufreq_frequency_table_target(policy, pxa3xx_freqs_table,
-                                target_freq, relation, &idx))
-                return -EINVAL;
-
-        next = &pxa3xx_freqs[idx];
-
-        freqs.old = policy->cur;
-        freqs.new = next->cpufreq_mhz * 1000;
-        freqs.cpu = policy->cpu;
-
-        pr_debug("CPU frequency from %d MHz to %d MHz%s\n",
-                        freqs.old / 1000, freqs.new / 1000,
-                        (freqs.old == freqs.new) ? " (skipped)" : "");
-
-        if (freqs.old == target_freq)
-                return 0;
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
-        local_irq_save(flags);
-        __update_core_freq(next);
-        __update_bus_freq(next);
-        local_irq_restore(flags);
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
-        return 0;
-}
-
-static int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
-{
-        int ret = -EINVAL;
-
-        /* set default policy and cpuinfo */
-        policy->cpuinfo.min_freq = 104000;
-        policy->cpuinfo.max_freq = (cpu_is_pxa320()) ? 806000 : 624000;
-        policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
-        policy->max = pxa3xx_get_clk_frequency_khz(0);
-        policy->cur = policy->min = policy->max;
-
-        if (cpu_is_pxa300() || cpu_is_pxa310())
-                ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa300_freqs));
-
-        if (cpu_is_pxa320())
-                ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa320_freqs));
-
-        if (ret) {
-                pr_err("failed to setup frequency table\n");
-                return ret;
-        }
-
-        pr_info("CPUFREQ support for PXA3xx initialized\n");
-        return 0;
-}
-
-static struct cpufreq_driver pxa3xx_cpufreq_driver = {
-        .verify         = pxa3xx_cpufreq_verify,
-        .target         = pxa3xx_cpufreq_set,
-        .init           = pxa3xx_cpufreq_init,
-        .get            = pxa3xx_cpufreq_get,
-        .name           = "pxa3xx-cpufreq",
-};
-
-static int __init cpufreq_init(void)
-{
-        if (cpu_is_pxa3xx())
-                return cpufreq_register_driver(&pxa3xx_cpufreq_driver);
-
-        return 0;
-}
-module_init(cpufreq_init);
-
-static void __exit cpufreq_exit(void)
-{
-        cpufreq_unregister_driver(&pxa3xx_cpufreq_driver);
-}
-module_exit(cpufreq_exit);
-
-MODULE_DESCRIPTION("CPU frequency scaling driver for PXA3xx");
-MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index daa86d39ed9e..666094315ab1 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -1107,8 +1107,33 @@ struct resource pxa_resource_gpio[] = {
         },
 };
 
-struct platform_device pxa_device_gpio = {
-        .name           = "pxa-gpio",
+struct platform_device pxa25x_device_gpio = {
+#ifdef CONFIG_CPU_PXA26x
+        .name           = "pxa26x-gpio",
+#else
+        .name           = "pxa25x-gpio",
+#endif
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pxa_resource_gpio),
+        .resource       = pxa_resource_gpio,
+};
+
+struct platform_device pxa27x_device_gpio = {
+        .name           = "pxa27x-gpio",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pxa_resource_gpio),
+        .resource       = pxa_resource_gpio,
+};
+
+struct platform_device pxa3xx_device_gpio = {
+        .name           = "pxa3xx-gpio",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pxa_resource_gpio),
+        .resource       = pxa_resource_gpio,
+};
+
+struct platform_device pxa93x_device_gpio = {
+        .name           = "pxa93x-gpio",
         .id             = -1,
         .num_resources  = ARRAY_SIZE(pxa_resource_gpio),
         .resource       = pxa_resource_gpio,
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index 1475db107254..0f3fd0d65b12 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -16,7 +16,6 @@ extern struct platform_device pxa_device_ficp;
 extern struct platform_device sa1100_device_rtc;
 extern struct platform_device pxa_device_rtc;
 extern struct platform_device pxa_device_ac97;
-extern struct platform_device pxa_device_gpio;
 
 extern struct platform_device pxa27x_device_i2c_power;
 extern struct platform_device pxa27x_device_ohci;
@@ -46,4 +45,9 @@ extern struct platform_device pxa_device_asoc_ssp2;
 extern struct platform_device pxa_device_asoc_ssp3;
 extern struct platform_device pxa_device_asoc_ssp4;
 
+extern struct platform_device pxa25x_device_gpio;
+extern struct platform_device pxa27x_device_gpio;
+extern struct platform_device pxa3xx_device_gpio;
+extern struct platform_device pxa93x_device_gpio;
+
 void __init pxa_register_device(struct platform_device *dev, void *data);
diff --git a/arch/arm/mach-pxa/include/mach/debug-macro.S b/arch/arm/mach-pxa/include/mach/debug-macro.S
deleted file mode 100644
index 70b112e8ef68..000000000000
--- a/arch/arm/mach-pxa/include/mach/debug-macro.S
+++ /dev/null
@@ -1,23 +0,0 @@
-/* arch/arm/mach-pxa/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#include "hardware.h"
-
-                .macro  addruart, rp, rv, tmp
-                mov     \rp, #0x00100000
-                orr     \rv, \rp, #io_p2v(0x40000000)   @ virtual
-                orr     \rp, \rp, #0x40000000           @ physical
-                .endm
-
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-pxa/include/mach/generic.h b/arch/arm/mach-pxa/include/mach/generic.h
new file mode 100644
index 000000000000..665542e0c9e2
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/generic.h
@@ -0,0 +1 @@
+#include "../../generic.h"
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 3f5171eaf67b..f2c28972084d 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -208,7 +208,11 @@ static struct clk_lookup pxa25x_clkregs[] = {
         INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
         INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
         INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
-        INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
+#ifdef CONFIG_CPU_PXA26x
+        INIT_CLKREG(&clk_dummy, "pxa26x-gpio", NULL),
+#else
+        INIT_CLKREG(&clk_dummy, "pxa25x-gpio", NULL),
+#endif
         INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 
@@ -340,7 +344,8 @@ void __init pxa25x_map_io(void)
 }
 
 static struct pxa_gpio_platform_data pxa25x_gpio_info __initdata = {
-        .gpio_set_wake = gpio_set_wake,
+        .irq_base       = PXA_GPIO_TO_IRQ(0),
+        .gpio_set_wake  = gpio_set_wake,
 };
 
 static struct platform_device *pxa25x_devices[] __initdata = {
@@ -375,7 +380,7 @@ static int __init pxa25x_init(void)
                 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
                 register_syscore_ops(&pxa2xx_clock_syscore_ops);
 
-                pxa_register_device(&pxa_device_gpio, &pxa25x_gpio_info);
+                pxa_register_device(&pxa25x_device_gpio, &pxa25x_gpio_info);
                 ret = platform_add_devices(pxa25x_devices,
                                            ARRAY_SIZE(pxa25x_devices));
                 if (ret)
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 3203a9f5b4a2..301471a07a10 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -237,7 +237,7 @@ static struct clk_lookup pxa27x_clkregs[] = {
         INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
         INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
         INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
-        INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_dummy, "pxa27x-gpio", NULL),
         INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 
@@ -431,7 +431,8 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 }
 
 static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
-        .gpio_set_wake = gpio_set_wake,
+        .irq_base       = PXA_GPIO_TO_IRQ(0),
+        .gpio_set_wake  = gpio_set_wake,
 };
 
 static struct platform_device *devices[] __initdata = {
@@ -470,7 +471,7 @@ static int __init pxa27x_init(void)
                 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
                 register_syscore_ops(&pxa2xx_clock_syscore_ops);
 
-                pxa_register_device(&pxa_device_gpio, &pxa27x_gpio_info);
+                pxa_register_device(&pxa27x_device_gpio, &pxa27x_gpio_info);
                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
         }
 
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 656a1bb16d14..87011f3de69d 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -15,6 +15,7 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/gpio-pxa.h>
 #include <linux/pm.h>
 #include <linux/platform_device.h>
 #include <linux/irq.h>
@@ -92,7 +93,8 @@ static struct clk_lookup pxa3xx_clkregs[] = {
         INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
         INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
         INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
-        INIT_CLKREG(&clk_pxa3xx_gpio, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_pxa3xx_gpio, "pxa3xx-gpio", NULL),
+        INIT_CLKREG(&clk_pxa3xx_gpio, "pxa93x-gpio", NULL),
         INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 
@@ -435,8 +437,11 @@ void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
         pxa_register_device(&pxa3xx_device_i2c_power, info);
 }
 
+static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = {
+        .irq_base       = PXA_GPIO_TO_IRQ(0),
+};
+
 static struct platform_device *devices[] __initdata = {
-        &pxa_device_gpio,
         &pxa27x_device_udc,
         &pxa_device_pmu,
         &pxa_device_i2s,
@@ -482,8 +487,18 @@ static int __init pxa3xx_init(void)
                 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
                 register_syscore_ops(&pxa3xx_clock_syscore_ops);
 
-                if (!of_have_populated_dt())
-                        ret = platform_add_devices(devices, ARRAY_SIZE(devices));
+                if (of_have_populated_dt())
+                        return 0;
+
+                ret = platform_add_devices(devices, ARRAY_SIZE(devices));
+                if (ret)
+                        return ret;
+                if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) {
+                        platform_device_add_data(&pxa3xx_device_gpio,
+                                                 &pxa3xx_gpio_pdata,
+                                                 sizeof(pxa3xx_gpio_pdata));
+                        ret = platform_device_register(&pxa3xx_device_gpio);
+                }
         }
 
         return ret;
diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c
index 8aeacf908784..ab624487cf39 100644
--- a/arch/arm/mach-pxa/pxa930.c
+++ b/arch/arm/mach-pxa/pxa930.c
@@ -12,12 +12,15 @@
 
 #include <linux/module.h>
 #include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
 #include <linux/dma-mapping.h>
+#include <linux/irq.h>
+#include <linux/gpio-pxa.h>
+#include <linux/platform_device.h>
 
 #include <mach/pxa930.h>
 
+#include "devices.h"
+
 static struct mfp_addr_map pxa930_mfp_addr_map[] __initdata = {
 
         MFP_ADDR(GPIO0, 0x02e0),
@@ -190,11 +193,21 @@ static struct mfp_addr_map pxa935_mfp_addr_map[] __initdata = {
         MFP_ADDR_END,
 };
 
+static struct pxa_gpio_platform_data pxa93x_gpio_pdata = {
+        .irq_base       = PXA_GPIO_TO_IRQ(0),
+};
+
 static int __init pxa930_init(void)
 {
+        int ret = 0;
+
         if (cpu_is_pxa93x()) {
                 mfp_init_base(io_p2v(MFPR_BASE));
                 mfp_init_addr(pxa930_mfp_addr_map);
+                platform_device_add_data(&pxa93x_device_gpio,
+                                         &pxa93x_gpio_pdata,
+                                         sizeof(pxa93x_gpio_pdata));
+                ret = platform_device_register(&pxa93x_device_gpio);
         }
 
         if (cpu_is_pxa935())
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index 14c1d47e1abf..d210c0f9c2c4 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -12,6 +12,8 @@ config REALVIEW_EB_A9MP
         bool "Support Multicore Cortex-A9 Tile"
         depends on MACH_REALVIEW_EB
         select CPU_V7
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
         help
@@ -23,6 +25,8 @@ config REALVIEW_EB_ARM11MP
         depends on MACH_REALVIEW_EB
         select ARCH_HAS_BARRIERS if SMP
         select CPU_V6K
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
         help
@@ -43,6 +47,8 @@ config MACH_REALVIEW_PB11MP
         select ARCH_HAS_BARRIERS if SMP
         select ARM_GIC
         select CPU_V6K
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
         select HAVE_PATA_PLATFORM
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
@@ -85,6 +91,8 @@ config MACH_REALVIEW_PBX
         bool "Support RealView(R) Platform Baseboard Explore"
         select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
         select ARM_GIC
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
         select HAVE_PATA_PLATFORM
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c
index 53818e5cd3ad..ac22dd41b135 100644
--- a/arch/arm/mach-realview/hotplug.c
+++ b/arch/arm/mach-realview/hotplug.c
@@ -12,7 +12,6 @@
 #include <linux/errno.h>
 #include <linux/smp.h>
 
-#include <asm/cacheflush.h>
 #include <asm/cp15.h>
 #include <asm/smp_plat.h>
 
@@ -20,7 +19,6 @@ static inline void cpu_enter_lowpower(void)
 {
         unsigned int v;
 
-        flush_cache_all();
         asm volatile(
         "       mcr     p15, 0, %1, c7, c5, 0\n"
         "       mcr     p15, 0, %1, c7, c10, 4\n"
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 37f513d1588e..f2f7088bfd22 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -30,29 +30,30 @@ config CPU_S3C2410
         select S3C2410_CLOCK
         select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
         select S3C2410_PM if PM
+        select SAMSUNG_HRT
         help
           Support for S3C2410 and S3C2410A family from the S3C24XX line
           of Samsung Mobile CPUs.
 
 config CPU_S3C2412
         bool "SAMSUNG S3C2412"
-        depends on ARCH_S3C24XX
         select CPU_ARM926T
         select CPU_LLSERIAL_S3C2440
         select S3C2412_DMA if S3C24XX_DMA
         select S3C2412_PM if PM
+        select SAMSUNG_HRT
         help
           Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
 
 config CPU_S3C2416
         bool "SAMSUNG S3C2416/S3C2450"
-        depends on ARCH_S3C24XX
         select CPU_ARM926T
         select CPU_LLSERIAL_S3C2440
         select S3C2416_PM if PM
         select S3C2443_COMMON
         select S3C2443_DMA if S3C24XX_DMA
         select SAMSUNG_CLKSRC
+        select SAMSUNG_HRT
         help
           Support for the S3C2416 SoC from the S3C24XX line
 
@@ -63,6 +64,7 @@ config CPU_S3C2440
         select S3C2410_CLOCK
         select S3C2410_PM if PM
         select S3C2440_DMA if S3C24XX_DMA
+        select SAMSUNG_HRT
         help
           Support for S3C2440 Samsung Mobile CPU based systems.
 
@@ -72,6 +74,7 @@ config CPU_S3C2442
         select CPU_LLSERIAL_S3C2440
         select S3C2410_CLOCK
         select S3C2410_PM if PM
+        select SAMSUNG_HRT
         help
           Support for S3C2442 Samsung Mobile CPU based systems.
 
@@ -81,12 +84,12 @@ config CPU_S3C244X
 
 config CPU_S3C2443
         bool "SAMSUNG S3C2443"
-        depends on ARCH_S3C24XX
         select CPU_ARM920T
         select CPU_LLSERIAL_S3C2440
         select S3C2443_COMMON
         select S3C2443_DMA if S3C24XX_DMA
         select SAMSUNG_CLKSRC
+        select SAMSUNG_HRT
         help
           Support for the S3C2443 SoC from the S3C24XX line
 
@@ -133,7 +136,6 @@ config S3C24XX_SETUP_TS
 
 config S3C24XX_DMA
         bool "S3C2410 DMA support"
-        depends on ARCH_S3C24XX
         select S3C_DMA
         help
           S3C2410 DMA support. This is needed for drivers like sound which
@@ -142,7 +144,7 @@ config S3C24XX_DMA
 
 config S3C2410_DMA_DEBUG
         bool "S3C2410 DMA support debug"
-        depends on ARCH_S3C24XX && S3C2410_DMA
+        depends on S3C2410_DMA
         help
           Enable debugging output for the DMA code. This option sends info
           to the kernel log, at priority KERN_DEBUG.
@@ -233,7 +235,7 @@ if CPU_S3C2410
 
 config S3C2410_CPUFREQ
         bool
-        depends on CPU_FREQ_S3C24XX && CPU_S3C2410
+        depends on CPU_FREQ_S3C24XX
         select S3C2410_CPUFREQ_UTILS
         help
           CPU Frequency scaling support for S3C2410
@@ -320,7 +322,6 @@ config PM_H1940
 
 config MACH_N30
         bool "Acer N30 family"
-        select MACH_N35
         select S3C_DEV_NAND
         select S3C_DEV_USB_HOST
         help
@@ -380,14 +381,13 @@ if CPU_S3C2412
 
 config CPU_S3C2412_ONLY
         bool
-        depends on ARCH_S3C24XX && !CPU_S3C2410 && \
-                   !CPU_S3C2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
-                   !CPU_S3C2443 && CPU_S3C2412
+        depends on !CPU_S3C2410 && !CPU_S3C2416 && !CPU_S3C2440 && \
+                   !CPU_S3C2442 && !CPU_S3C2443
         default y
 
 config S3C2412_CPUFREQ
         bool
-        depends on CPU_FREQ_S3C24XX && CPU_S3C2412
+        depends on CPU_FREQ_S3C24XX
         default y
         select S3C2412_IOTIMING
         help
@@ -401,6 +401,7 @@ config S3C2412_DMA
 config S3C2412_PM
         bool
         select S3C2412_PM_SLEEP
+        select SAMSUNG_WAKEMASK
         help
           Internal config node to apply S3C2412 power management
 
@@ -642,7 +643,6 @@ comment "S3C2442 Boards"
 config MACH_NEO1973_GTA02
         bool "Openmoko GTA02 / Freerunner phone"
         select I2C
-        select MACH_NEO1973
         select MFD_PCF50633
         select PCF50633_GPIO
         select POWER_SUPPLY
@@ -663,10 +663,7 @@ config MACH_RX1950
         help
            Say Y here if you're using HP iPAQ rx1950
 
-config SMDK2440_CPU2442
-        bool "SMDM2440 with S3C2442 CPU module"
-
-endif   # CPU_S3C2440
+endif   # CPU_S3C2442
 
 if CPU_S3C2443 || CPU_S3C2416
 
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index af53d27d5c36..6f46ecfc8396 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -14,7 +14,7 @@ obj-				:=
 
 # core
 
-obj-y                           += common.o irq.o
+obj-y                           += common.o
 
 obj-$(CONFIG_CPU_S3C2410)       += s3c2410.o
 obj-$(CONFIG_S3C2410_CPUFREQ)   += cpufreq-s3c2410.o
@@ -22,7 +22,7 @@ obj-$(CONFIG_S3C2410_DMA)	+= dma-s3c2410.o
 obj-$(CONFIG_S3C2410_PLL)       += pll-s3c2410.o
 obj-$(CONFIG_S3C2410_PM)        += pm-s3c2410.o sleep-s3c2410.o
 
-obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o irq-s3c2412.o clock-s3c2412.o
+obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o clock-s3c2412.o
 obj-$(CONFIG_S3C2412_CPUFREQ)   += cpufreq-s3c2412.o
 obj-$(CONFIG_S3C2412_DMA)       += dma-s3c2412.o
 obj-$(CONFIG_S3C2412_PM)        += pm-s3c2412.o
@@ -31,9 +31,9 @@ obj-$(CONFIG_S3C2412_PM_SLEEP)	+= sleep-s3c2412.o
 obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o clock-s3c2416.o
 obj-$(CONFIG_S3C2416_PM)        += pm-s3c2416.o
 
-obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o irq-s3c2440.o clock-s3c2440.o
+obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o clock-s3c2440.o
 obj-$(CONFIG_CPU_S3C2442)       += s3c2442.o
-obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o irq-s3c244x.o clock-s3c244x.o
+obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o clock-s3c244x.o
 obj-$(CONFIG_S3C2440_CPUFREQ)   += cpufreq-s3c2440.o
 obj-$(CONFIG_S3C2440_DMA)       += dma-s3c2440.o
 obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
diff --git a/arch/arm/mach-s3c24xx/bast-irq.c b/arch/arm/mach-s3c24xx/bast-irq.c
index c0daa9590b4c..cb1b791954de 100644
--- a/arch/arm/mach-s3c24xx/bast-irq.c
+++ b/arch/arm/mach-s3c24xx/bast-irq.c
@@ -34,8 +34,6 @@
 #include <mach/hardware.h>
 #include <mach/regs-irq.h>
 
-#include <plat/irq.h>
-
 #include "bast.h"
 
 #define irqdbf(x...)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2410.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c
index 641266f3d152..34fffdf6fc1d 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2410.c
@@ -40,7 +40,6 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
 
-#include <plat/s3c2410.h>
 #include <plat/clock.h>
 #include <plat/cpu.h>
 
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2412.c b/arch/arm/mach-s3c24xx/clock-s3c2412.c
index d10b695a9066..2cc017da88fe 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2412.c
@@ -41,7 +41,6 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
 
-#include <plat/s3c2412.h>
 #include <plat/clock.h>
 #include <plat/cpu.h>
 
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
index 14a81c2317a4..036056cea57c 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c
@@ -14,7 +14,6 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 
-#include <plat/s3c2416.h>
 #include <plat/clock.h>
 #include <plat/clock-clksrc.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c
index 04b87ec92537..1069b5680826 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c
@@ -123,6 +123,11 @@ static struct clk s3c2440_clk_ac97 = {
         .ctrlbit        = S3C2440_CLKCON_AC97,
 };
 
+#define S3C24XX_VA_UART0      (S3C_VA_UART)
+#define S3C24XX_VA_UART1      (S3C_VA_UART + 0x4000 )
+#define S3C24XX_VA_UART2      (S3C_VA_UART + 0x8000 )
+#define S3C24XX_VA_UART3      (S3C_VA_UART + 0xC000 )
+
 static unsigned long  s3c2440_fclk_n_getrate(struct clk *clk)
 {
         unsigned long ucon0, ucon1, ucon2, divisor;
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index bdaba59b42dc..0a53051b0787 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -41,7 +41,6 @@
 
 #include <plat/cpu-freq.h>
 
-#include <plat/s3c2443.h>
 #include <plat/clock.h>
 #include <plat/clock-clksrc.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c
index 3b2cf6db3634..404444dd3840 100644
--- a/arch/arm/mach-s3c24xx/common-smdk.c
+++ b/arch/arm/mach-s3c24xx/common-smdk.c
@@ -41,11 +41,12 @@
 
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 
-#include <plat/common-smdk.h>
 #include <plat/gpio-cfg.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
 
+#include "common-smdk.h"
+
 /* LED devices */
 
 static struct s3c24xx_led_platdata smdk_pdata_led4 = {
diff --git a/arch/arm/plat-samsung/include/plat/common-smdk.h b/arch/arm/mach-s3c24xx/common-smdk.h
index ba028f1ed30b..98f733e1cb42 100644
--- a/arch/arm/plat-samsung/include/plat/common-smdk.h
+++ b/arch/arm/mach-s3c24xx/common-smdk.h
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-samsung/include/plat/common-smdk.h
- *
+/*
  * Copyright (c) 2006 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 6bcf87f65f9e..c157103ed8eb 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -47,14 +47,11 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/clock.h>
-#include <plat/s3c2410.h>
-#include <plat/s3c2412.h>
-#include <plat/s3c2416.h>
-#include <plat/s3c244x.h>
-#include <plat/s3c2443.h>
 #include <plat/cpu-freq.h>
 #include <plat/pll.h>
 
+#include "common.h"
+
 /* table of supported CPUs */
 
 static const char name_s3c2410[]  = "S3C2410";
@@ -239,6 +236,11 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
 
 /* Serial port registrations */
 
+#define S3C2410_PA_UART0      (S3C24XX_PA_UART)
+#define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
+#define S3C2410_PA_UART2      (S3C24XX_PA_UART + 0x8000 )
+#define S3C2443_PA_UART3      (S3C24XX_PA_UART + 0xC000 )
+
 static struct resource s3c2410_uart0_resource[] = {
         [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
         [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index ed6276fcaa3b..307c3714be55 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -12,8 +12,98 @@
 #ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H
 #define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__
 
-void s3c2410_restart(char mode, const char *cmd);
-void s3c244x_restart(char mode, const char *cmd);
+struct s3c2410_uartcfg;
+
+#ifdef CONFIG_CPU_S3C2410
+extern  int s3c2410_init(void);
+extern  int s3c2410a_init(void);
+extern void s3c2410_map_io(void);
+extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c2410_init_clocks(int xtal);
+extern void s3c2410_restart(char mode, const char *cmd);
+extern void s3c2410_init_irq(void);
+#else
+#define s3c2410_init_clocks NULL
+#define s3c2410_init_uarts NULL
+#define s3c2410_map_io NULL
+#define s3c2410_init NULL
+#define s3c2410a_init NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2412
+extern  int s3c2412_init(void);
+extern void s3c2412_map_io(void);
+extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c2412_init_clocks(int xtal);
+extern  int s3c2412_baseclk_add(void);
+extern void s3c2412_restart(char mode, const char *cmd);
+extern void s3c2412_init_irq(void);
+#else
+#define s3c2412_init_clocks NULL
+#define s3c2412_init_uarts NULL
+#define s3c2412_map_io NULL
+#define s3c2412_init NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2416
+extern  int s3c2416_init(void);
+extern void s3c2416_map_io(void);
+extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c2416_init_clocks(int xtal);
+extern  int s3c2416_baseclk_add(void);
+extern void s3c2416_restart(char mode, const char *cmd);
+extern void s3c2416_init_irq(void);
+
+extern struct syscore_ops s3c2416_irq_syscore_ops;
+#else
+#define s3c2416_init_clocks NULL
+#define s3c2416_init_uarts NULL
+#define s3c2416_map_io NULL
+#define s3c2416_init NULL
+#endif
+
+#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
+extern void s3c244x_map_io(void);
+extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c244x_init_clocks(int xtal);
+extern void s3c244x_restart(char mode, const char *cmd);
+#else
+#define s3c244x_init_clocks NULL
+#define s3c244x_init_uarts NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2440
+extern  int s3c2440_init(void);
+extern void s3c2440_map_io(void);
+extern void s3c2440_init_irq(void);
+#else
+#define s3c2440_init NULL
+#define s3c2440_map_io NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2442
+extern  int s3c2442_init(void);
+extern void s3c2442_map_io(void);
+extern void s3c2442_init_irq(void);
+#else
+#define s3c2442_init NULL
+#define s3c2442_map_io NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2443
+extern  int s3c2443_init(void);
+extern void s3c2443_map_io(void);
+extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c2443_init_clocks(int xtal);
+extern  int s3c2443_baseclk_add(void);
+extern void s3c2443_restart(char mode, const char *cmd);
+extern void s3c2443_init_irq(void);
+#else
+#define s3c2443_init_clocks NULL
+#define s3c2443_init_uarts NULL
+#define s3c2443_map_io NULL
+#define s3c2443_init NULL
+#endif
 
 extern struct syscore_ops s3c24xx_irq_syscore_ops;
 
diff --git a/arch/arm/mach-s3c24xx/cpufreq.c b/arch/arm/mach-s3c24xx/cpufreq.c
index 5f181e733eee..3c0e78ede0da 100644
--- a/arch/arm/mach-s3c24xx/cpufreq.c
+++ b/arch/arm/mach-s3c24xx/cpufreq.c
@@ -204,7 +204,6 @@ static int s3c_cpufreq_settarget(struct cpufreq_policy *policy,
         freqs.old = cpu_cur.freq;
         freqs.new = cpu_new.freq;
 
-        freqs.freqs.cpu = 0;
         freqs.freqs.old = cpu_cur.freq.armclk / 1000;
         freqs.freqs.new = cpu_new.freq.armclk / 1000;
 
@@ -218,9 +217,7 @@ static int s3c_cpufreq_settarget(struct cpufreq_policy *policy,
         s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk);
 
         /* start the frequency change */
-
-        if (policy)
-                cpufreq_notify_transition(&freqs.freqs, CPUFREQ_PRECHANGE);
+        cpufreq_notify_transition(policy, &freqs.freqs, CPUFREQ_PRECHANGE);
 
         /* If hclk is staying the same, then we do not need to
          * re-write the IO or the refresh timings whilst we are changing
@@ -264,8 +261,7 @@ static int s3c_cpufreq_settarget(struct cpufreq_policy *policy,
         local_irq_restore(flags);
 
         /* notify everyone we've done this */
-        if (policy)
-                cpufreq_notify_transition(&freqs.freqs, CPUFREQ_POSTCHANGE);
+        cpufreq_notify_transition(policy, &freqs.freqs, CPUFREQ_POSTCHANGE);
 
         s3c_freq_dbg("%s: finished\n", __func__);
         return 0;
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2410.c b/arch/arm/mach-s3c24xx/dma-s3c2410.c
index 25d085adc93c..30aa53ff07a6 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2410.c
@@ -25,11 +25,8 @@
 
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
-#include <mach/regs-sdi.h>
-#include <plat/regs-iis.h>
 #include <plat/regs-spi.h>
 
 static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c
index d2408ba372cb..ab1700ec8e64 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c
@@ -25,11 +25,8 @@
 
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
-#include <mach/regs-sdi.h>
-#include <plat/regs-iis.h>
 #include <plat/regs-spi.h>
 
 #define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2440.c b/arch/arm/mach-s3c24xx/dma-s3c2440.c
index 0b86e74d104f..cd25de28804c 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2440.c
@@ -25,11 +25,8 @@
 
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
-#include <mach/regs-sdi.h>
-#include <plat/regs-iis.h>
 #include <plat/regs-spi.h>
 
 static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index 05536254a3f8..5fe3539dc2b5 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -25,11 +25,8 @@
 
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
-#include <mach/regs-sdi.h>
-#include <plat/regs-iis.h>
 #include <plat/regs-spi.h>
 
 #define MAP(x) { \
diff --git a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
index 13ed33c69113..2558952e3147 100644
--- a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
@@ -98,4 +98,4 @@
 
 /* include the reset of the code which will do the work */
 
-#include <plat/debug-macro.S>
+#include <debug/samsung.S>
diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h
index 6b72d5a4b377..b55da1d8cd8f 100644
--- a/arch/arm/mach-s3c24xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c24xx/include/mach/dma.h
@@ -24,7 +24,6 @@
 */
 
 enum dma_ch {
-        DMACH_DT_PROP = -1,     /* not yet supported, do not use */
         DMACH_XD0 = 0,
         DMACH_XD1,
         DMACH_SDI,
diff --git a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S b/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
deleted file mode 100644
index 6a21beeba1da..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * arch/arm/mach-s3c2410/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for S3C2410-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
-*/
-
-/* We have a problem that the INTOFFSET register does not always
- * show one interrupt. Occasionally we get two interrupts through
- * the prioritiser, and this causes the INTOFFSET register to show
- * what looks like the logical-or of the two interrupt numbers.
- *
- * Thanks to Klaus, Shannon, et al for helping to debug this problem
-*/
-
-#define INTPND          (0x10)
-#define INTOFFSET       (0x14)
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-        .macro  get_irqnr_preamble, base, tmp
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-                mov     \base, #S3C24XX_VA_IRQ
-
-                @@ try the interrupt offset register, since it is there
-
-                ldr     \irqstat, [\base, #INTPND ]
-                teq     \irqstat, #0
-                beq     1002f
-                ldr     \irqnr, [\base, #INTOFFSET ]
-                mov     \tmp, #1
-                tst     \irqstat, \tmp, lsl \irqnr
-                bne     1001f
-
-                @@ the number specified is not a valid irq, so try
-                @@ and work it out for ourselves
-
-                mov     \irqnr, #0              @@ start here
-
-                @@ work out which irq (if any) we got
-
-                movs    \tmp, \irqstat, lsl#16
-                addeq   \irqnr, \irqnr, #16
-                moveq   \irqstat, \irqstat, lsr#16
-                tst     \irqstat, #0xff
-                addeq   \irqnr, \irqnr, #8
-                moveq   \irqstat, \irqstat, lsr#8
-                tst     \irqstat, #0xf
-                addeq   \irqnr, \irqnr, #4
-                moveq   \irqstat, \irqstat, lsr#4
-                tst     \irqstat, #0x3
-                addeq   \irqnr, \irqnr, #2
-                moveq   \irqstat, \irqstat, lsr#2
-                tst     \irqstat, #0x1
-                addeq   \irqnr, \irqnr, #1
-
-                @@ we have the value
-1001:
-                adds    \irqnr, \irqnr, #IRQ_EINT0
-1002:
-                @@ exit here, Z flag unset if IRQ
-
-        .endm
diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h
index 1e73f5fa8659..b6dd4cb5a2ec 100644
--- a/arch/arm/mach-s3c24xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c24xx/include/mach/irqs.h
@@ -59,49 +59,53 @@
 #define IRQ_ADCPARENT  S3C2410_IRQ(31)
 
 /* interrupts generated from the external interrupts sources */
-#define IRQ_EINT4      S3C2410_IRQ(32)     /* 48 */
-#define IRQ_EINT5      S3C2410_IRQ(33)
-#define IRQ_EINT6      S3C2410_IRQ(34)
-#define IRQ_EINT7      S3C2410_IRQ(35)
-#define IRQ_EINT8      S3C2410_IRQ(36)
-#define IRQ_EINT9      S3C2410_IRQ(37)
-#define IRQ_EINT10     S3C2410_IRQ(38)
-#define IRQ_EINT11     S3C2410_IRQ(39)
-#define IRQ_EINT12     S3C2410_IRQ(40)
-#define IRQ_EINT13     S3C2410_IRQ(41)
-#define IRQ_EINT14     S3C2410_IRQ(42)
-#define IRQ_EINT15     S3C2410_IRQ(43)
-#define IRQ_EINT16     S3C2410_IRQ(44)
-#define IRQ_EINT17     S3C2410_IRQ(45)
-#define IRQ_EINT18     S3C2410_IRQ(46)
-#define IRQ_EINT19     S3C2410_IRQ(47)
-#define IRQ_EINT20     S3C2410_IRQ(48)     /* 64 */
-#define IRQ_EINT21     S3C2410_IRQ(49)
-#define IRQ_EINT22     S3C2410_IRQ(50)
-#define IRQ_EINT23     S3C2410_IRQ(51)
+#define IRQ_EINT0_2412 S3C2410_IRQ(32)
+#define IRQ_EINT1_2412 S3C2410_IRQ(33)
+#define IRQ_EINT2_2412 S3C2410_IRQ(34)
+#define IRQ_EINT3_2412 S3C2410_IRQ(35)
+#define IRQ_EINT4      S3C2410_IRQ(36)     /* 52 */
+#define IRQ_EINT5      S3C2410_IRQ(37)
+#define IRQ_EINT6      S3C2410_IRQ(38)
+#define IRQ_EINT7      S3C2410_IRQ(39)
+#define IRQ_EINT8      S3C2410_IRQ(40)
+#define IRQ_EINT9      S3C2410_IRQ(41)
+#define IRQ_EINT10     S3C2410_IRQ(42)
+#define IRQ_EINT11     S3C2410_IRQ(43)
+#define IRQ_EINT12     S3C2410_IRQ(44)
+#define IRQ_EINT13     S3C2410_IRQ(45)
+#define IRQ_EINT14     S3C2410_IRQ(46)
+#define IRQ_EINT15     S3C2410_IRQ(47)
+#define IRQ_EINT16     S3C2410_IRQ(48)
+#define IRQ_EINT17     S3C2410_IRQ(49)
+#define IRQ_EINT18     S3C2410_IRQ(50)
+#define IRQ_EINT19     S3C2410_IRQ(51)
+#define IRQ_EINT20     S3C2410_IRQ(52)     /* 68 */
+#define IRQ_EINT21     S3C2410_IRQ(53)
+#define IRQ_EINT22     S3C2410_IRQ(54)
+#define IRQ_EINT23     S3C2410_IRQ(55)
 
 #define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4)
 #define IRQ_EINT(x)    (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
 
-#define IRQ_LCD_FIFO   S3C2410_IRQ(52)
-#define IRQ_LCD_FRAME  S3C2410_IRQ(53)
+#define IRQ_LCD_FIFO   S3C2410_IRQ(56)
+#define IRQ_LCD_FRAME  S3C2410_IRQ(57)
 
 /* IRQs for the interal UARTs, and ADC
  * these need to be ordered in number of appearance in the
  * SUBSRC mask register
 */
 
-#define S3C2410_IRQSUB(x)       S3C2410_IRQ((x)+54)
+#define S3C2410_IRQSUB(x)       S3C2410_IRQ((x)+58)
 
-#define IRQ_S3CUART_RX0         S3C2410_IRQSUB(0)       /* 70 */
+#define IRQ_S3CUART_RX0         S3C2410_IRQSUB(0)       /* 74 */
 #define IRQ_S3CUART_TX0         S3C2410_IRQSUB(1)
 #define IRQ_S3CUART_ERR0        S3C2410_IRQSUB(2)
 
-#define IRQ_S3CUART_RX1         S3C2410_IRQSUB(3)       /* 73 */
+#define IRQ_S3CUART_RX1         S3C2410_IRQSUB(3)       /* 77 */
 #define IRQ_S3CUART_TX1         S3C2410_IRQSUB(4)
 #define IRQ_S3CUART_ERR1        S3C2410_IRQSUB(5)
 
-#define IRQ_S3CUART_RX2         S3C2410_IRQSUB(6)       /* 76 */
+#define IRQ_S3CUART_RX2         S3C2410_IRQSUB(6)       /* 80 */
 #define IRQ_S3CUART_TX2         S3C2410_IRQSUB(7)
 #define IRQ_S3CUART_ERR2        S3C2410_IRQSUB(8)
 
@@ -136,7 +140,7 @@
 
 /* second interrupt-register of s3c2416/s3c2450 */
 
-#define S3C2416_IRQ(x)          S3C2410_IRQ((x) + 54 + 29)
+#define S3C2416_IRQ(x)          S3C2410_IRQ((x) + 58 + 29)
 #define IRQ_S3C2416_2D          S3C2416_IRQ(0)
 #define IRQ_S3C2416_IIC1        S3C2416_IRQ(1)
 #define IRQ_S3C2416_RESERVED2   S3C2416_IRQ(2)
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h b/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h
deleted file mode 100644
index cbf2d8884e30..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-sdi.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 MMC/SDIO register definitions
-*/
-
-#ifndef __ASM_ARM_REGS_SDI
-#define __ASM_ARM_REGS_SDI "regs-sdi.h"
-
-#define S3C2410_SDICON                (0x00)
-#define S3C2410_SDIPRE                (0x04)
-#define S3C2410_SDICMDARG             (0x08)
-#define S3C2410_SDICMDCON             (0x0C)
-#define S3C2410_SDICMDSTAT            (0x10)
-#define S3C2410_SDIRSP0               (0x14)
-#define S3C2410_SDIRSP1               (0x18)
-#define S3C2410_SDIRSP2               (0x1C)
-#define S3C2410_SDIRSP3               (0x20)
-#define S3C2410_SDITIMER              (0x24)
-#define S3C2410_SDIBSIZE              (0x28)
-#define S3C2410_SDIDCON               (0x2C)
-#define S3C2410_SDIDCNT               (0x30)
-#define S3C2410_SDIDSTA               (0x34)
-#define S3C2410_SDIFSTA               (0x38)
-
-#define S3C2410_SDIDATA               (0x3C)
-#define S3C2410_SDIIMSK               (0x40)
-
-#define S3C2440_SDIDATA               (0x40)
-#define S3C2440_SDIIMSK               (0x3C)
-
-#define S3C2440_SDICON_SDRESET        (1<<8)
-#define S3C2440_SDICON_MMCCLOCK       (1<<5)
-#define S3C2410_SDICON_BYTEORDER      (1<<4)
-#define S3C2410_SDICON_SDIOIRQ        (1<<3)
-#define S3C2410_SDICON_RWAITEN        (1<<2)
-#define S3C2410_SDICON_FIFORESET      (1<<1)
-#define S3C2410_SDICON_CLOCKTYPE      (1<<0)
-
-#define S3C2410_SDICMDCON_ABORT       (1<<12)
-#define S3C2410_SDICMDCON_WITHDATA    (1<<11)
-#define S3C2410_SDICMDCON_LONGRSP     (1<<10)
-#define S3C2410_SDICMDCON_WAITRSP     (1<<9)
-#define S3C2410_SDICMDCON_CMDSTART    (1<<8)
-#define S3C2410_SDICMDCON_SENDERHOST  (1<<6)
-#define S3C2410_SDICMDCON_INDEX       (0x3f)
-
-#define S3C2410_SDICMDSTAT_CRCFAIL    (1<<12)
-#define S3C2410_SDICMDSTAT_CMDSENT    (1<<11)
-#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10)
-#define S3C2410_SDICMDSTAT_RSPFIN     (1<<9)
-#define S3C2410_SDICMDSTAT_XFERING    (1<<8)
-#define S3C2410_SDICMDSTAT_INDEX      (0xff)
-
-#define S3C2440_SDIDCON_DS_BYTE       (0<<22)
-#define S3C2440_SDIDCON_DS_HALFWORD   (1<<22)
-#define S3C2440_SDIDCON_DS_WORD       (2<<22)
-#define S3C2410_SDIDCON_IRQPERIOD     (1<<21)
-#define S3C2410_SDIDCON_TXAFTERRESP   (1<<20)
-#define S3C2410_SDIDCON_RXAFTERCMD    (1<<19)
-#define S3C2410_SDIDCON_BUSYAFTERCMD  (1<<18)
-#define S3C2410_SDIDCON_BLOCKMODE     (1<<17)
-#define S3C2410_SDIDCON_WIDEBUS       (1<<16)
-#define S3C2410_SDIDCON_DMAEN         (1<<15)
-#define S3C2410_SDIDCON_STOP          (1<<14)
-#define S3C2440_SDIDCON_DATSTART      (1<<14)
-#define S3C2410_SDIDCON_DATMODE       (3<<12)
-#define S3C2410_SDIDCON_BLKNUM        (0x7ff)
-
-/* constants for S3C2410_SDIDCON_DATMODE */
-#define S3C2410_SDIDCON_XFER_READY    (0<<12)
-#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12)
-#define S3C2410_SDIDCON_XFER_RXSTART  (2<<12)
-#define S3C2410_SDIDCON_XFER_TXSTART  (3<<12)
-
-#define S3C2410_SDIDCON_BLKNUM_MASK   (0xFFF)
-#define S3C2410_SDIDCNT_BLKNUM_SHIFT  (12)
-
-#define S3C2410_SDIDSTA_RDYWAITREQ    (1<<10)
-#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9)
-#define S3C2410_SDIDSTA_FIFOFAIL      (1<<8)    /* reserved on 2440 */
-#define S3C2410_SDIDSTA_CRCFAIL       (1<<7)
-#define S3C2410_SDIDSTA_RXCRCFAIL     (1<<6)
-#define S3C2410_SDIDSTA_DATATIMEOUT   (1<<5)
-#define S3C2410_SDIDSTA_XFERFINISH    (1<<4)
-#define S3C2410_SDIDSTA_BUSYFINISH    (1<<3)
-#define S3C2410_SDIDSTA_SBITERR       (1<<2)    /* reserved on 2410a/2440 */
-#define S3C2410_SDIDSTA_TXDATAON      (1<<1)
-#define S3C2410_SDIDSTA_RXDATAON      (1<<0)
-
-#define S3C2440_SDIFSTA_FIFORESET      (1<<16)
-#define S3C2440_SDIFSTA_FIFOFAIL       (3<<14)  /* 3 is correct (2 bits) */
-#define S3C2410_SDIFSTA_TFDET          (1<<13)
-#define S3C2410_SDIFSTA_RFDET          (1<<12)
-#define S3C2410_SDIFSTA_TFHALF         (1<<11)
-#define S3C2410_SDIFSTA_TFEMPTY        (1<<10)
-#define S3C2410_SDIFSTA_RFLAST         (1<<9)
-#define S3C2410_SDIFSTA_RFFULL         (1<<8)
-#define S3C2410_SDIFSTA_RFHALF         (1<<7)
-#define S3C2410_SDIFSTA_COUNTMASK      (0x7f)
-
-#define S3C2410_SDIIMSK_RESPONSECRC    (1<<17)
-#define S3C2410_SDIIMSK_CMDSENT        (1<<16)
-#define S3C2410_SDIIMSK_CMDTIMEOUT     (1<<15)
-#define S3C2410_SDIIMSK_RESPONSEND     (1<<14)
-#define S3C2410_SDIIMSK_READWAIT       (1<<13)
-#define S3C2410_SDIIMSK_SDIOIRQ        (1<<12)
-#define S3C2410_SDIIMSK_FIFOFAIL       (1<<11)
-#define S3C2410_SDIIMSK_CRCSTATUS      (1<<10)
-#define S3C2410_SDIIMSK_DATACRC        (1<<9)
-#define S3C2410_SDIIMSK_DATATIMEOUT    (1<<8)
-#define S3C2410_SDIIMSK_DATAFINISH     (1<<7)
-#define S3C2410_SDIIMSK_BUSYFINISH     (1<<6)
-#define S3C2410_SDIIMSK_SBITERR        (1<<5)   /* reserved 2440/2410a */
-#define S3C2410_SDIIMSK_TXFIFOHALF     (1<<4)
-#define S3C2410_SDIIMSK_TXFIFOEMPTY    (1<<3)
-#define S3C2410_SDIIMSK_RXFIFOLAST     (1<<2)
-#define S3C2410_SDIIMSK_RXFIFOFULL     (1<<1)
-#define S3C2410_SDIIMSK_RXFIFOHALF     (1<<0)
-
-#endif /* __ASM_ARM_REGS_SDI */
diff --git a/arch/arm/mach-s3c24xx/irq-pm.c b/arch/arm/mach-s3c24xx/irq-pm.c
index e1199599873e..b91341ef2b2e 100644
--- a/arch/arm/mach-s3c24xx/irq-pm.c
+++ b/arch/arm/mach-s3c24xx/irq-pm.c
@@ -16,10 +16,15 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/syscore_ops.h>
+#include <linux/io.h>
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <plat/irq.h>
+#include <plat/map-base.h>
+#include <plat/map-s3c.h>
+
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
 
 #include <asm/irq.h>
 
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2412.c b/arch/arm/mach-s3c24xx/irq-s3c2412.c
deleted file mode 100644
index 67d763178d3f..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c2412.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/* linux/arch/arm/mach-s3c2412/irq.c
- *
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/irq.h>
-#include <plat/pm.h>
-
-#include "s3c2412-power.h"
-
-#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
-#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))
-
-/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
- * having them turn up in both the INT* and the EINT* registers. Whilst
- * both show the status, they both now need to be acked when the IRQs
- * go off.
-*/
-
-static void
-s3c2412_irq_mask(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-        unsigned long mask;
-
-        mask = __raw_readl(S3C2410_INTMSK);
-        __raw_writel(mask | bitval, S3C2410_INTMSK);
-
-        mask = __raw_readl(S3C2412_EINTMASK);
-        __raw_writel(mask | bitval, S3C2412_EINTMASK);
-}
-
-static inline void
-s3c2412_irq_ack(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-
-        __raw_writel(bitval, S3C2412_EINTPEND);
-        __raw_writel(bitval, S3C2410_SRCPND);
-        __raw_writel(bitval, S3C2410_INTPND);
-}
-
-static inline void
-s3c2412_irq_maskack(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-        unsigned long mask;
-
-        mask = __raw_readl(S3C2410_INTMSK);
-        __raw_writel(mask|bitval, S3C2410_INTMSK);
-
-        mask = __raw_readl(S3C2412_EINTMASK);
-        __raw_writel(mask | bitval, S3C2412_EINTMASK);
-
-        __raw_writel(bitval, S3C2412_EINTPEND);
-        __raw_writel(bitval, S3C2410_SRCPND);
-        __raw_writel(bitval, S3C2410_INTPND);
-}
-
-static void
-s3c2412_irq_unmask(struct irq_data *data)
-{
-        unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
-        unsigned long mask;
-
-        mask = __raw_readl(S3C2412_EINTMASK);
-        __raw_writel(mask & ~bitval, S3C2412_EINTMASK);
-
-        mask = __raw_readl(S3C2410_INTMSK);
-        __raw_writel(mask & ~bitval, S3C2410_INTMSK);
-}
-
-static struct irq_chip s3c2412_irq_eint0t4 = {
-        .irq_ack        = s3c2412_irq_ack,
-        .irq_mask       = s3c2412_irq_mask,
-        .irq_unmask     = s3c2412_irq_unmask,
-        .irq_set_wake   = s3c_irq_wake,
-        .irq_set_type   = s3c_irqext_type,
-};
-
-#define INTBIT(x)       (1 << ((x) - S3C2410_IRQSUB(0)))
-
-/* CF and SDI sub interrupts */
-
-static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)
-{
-        unsigned int subsrc, submsk;
-
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-
-        subsrc  &= ~submsk;
-
-        if (subsrc & INTBIT(IRQ_S3C2412_SDI))
-                generic_handle_irq(IRQ_S3C2412_SDI);
-
-        if (subsrc & INTBIT(IRQ_S3C2412_CF))
-                generic_handle_irq(IRQ_S3C2412_CF);
-}
-
-#define INTMSK_CFSDI    (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))
-#define SUBMSK_CFSDI    INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF)
-
-static void s3c2412_irq_cfsdi_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
-}
-
-static void s3c2412_irq_cfsdi_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_CFSDI);
-}
-
-static void s3c2412_irq_cfsdi_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
-}
-
-static struct irq_chip s3c2412_irq_cfsdi = {
-        .name           = "s3c2412-cfsdi",
-        .irq_ack        = s3c2412_irq_cfsdi_ack,
-        .irq_mask       = s3c2412_irq_cfsdi_mask,
-        .irq_unmask     = s3c2412_irq_cfsdi_unmask,
-};
-
-static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)
-{
-        unsigned long pwrcfg;
-
-        pwrcfg = __raw_readl(S3C2412_PWRCFG);
-        if (state)
-                pwrcfg &= ~S3C2412_PWRCFG_RTC_MASKIRQ;
-        else
-                pwrcfg |= S3C2412_PWRCFG_RTC_MASKIRQ;
-        __raw_writel(pwrcfg, S3C2412_PWRCFG);
-
-        return s3c_irq_chip.irq_set_wake(data, state);
-}
-
-static struct irq_chip s3c2412_irq_rtc_chip;
-
-static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif)
-{
-        unsigned int irqno;
-
-        for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
-                irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,
-                                         handle_edge_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-
-        /* add demux support for CF/SDI */
-
-        irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
-
-        for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
-                irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi,
-                                         handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-
-        /* change RTC IRQ's set wake method */
-
-        s3c2412_irq_rtc_chip = s3c_irq_chip;
-        s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;
-
-        irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
-
-        return 0;
-}
-
-static struct subsys_interface s3c2412_irq_interface = {
-        .name           = "s3c2412_irq",
-        .subsys         = &s3c2412_subsys,
-        .add_dev        = s3c2412_irq_add,
-};
-
-static int s3c2412_irq_init(void)
-{
-        return subsys_interface_register(&s3c2412_irq_interface);
-}
-
-arch_initcall(s3c2412_irq_init);
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2440.c b/arch/arm/mach-s3c24xx/irq-s3c2440.c
deleted file mode 100644
index 4a18cde439cc..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c2440.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* linux/arch/arm/mach-s3c2440/irq.c
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/irq.h>
-
-/* WDT/AC97 */
-
-static void s3c_irq_demux_wdtac97(unsigned int irq,
-                                  struct irq_desc *desc)
-{
-        unsigned int subsrc, submsk;
-
-        /* read the current pending interrupts, and the mask
-         * for what it is available */
-
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-
-        subsrc &= ~submsk;
-        subsrc >>= 13;
-        subsrc &= 3;
-
-        if (subsrc != 0) {
-                if (subsrc & 1) {
-                        generic_handle_irq(IRQ_S3C2440_WDT);
-                }
-                if (subsrc & 2) {
-                        generic_handle_irq(IRQ_S3C2440_AC97);
-                }
-        }
-}
-
-
-#define INTMSK_WDT       (1UL << (IRQ_WDT - IRQ_EINT0))
-
-static void
-s3c_irq_wdtac97_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_WDT, 3 << 13);
-}
-
-static void
-s3c_irq_wdtac97_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_WDT);
-}
-
-static void
-s3c_irq_wdtac97_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_WDT, 3 << 13);
-}
-
-static struct irq_chip s3c_irq_wdtac97 = {
-        .irq_mask       = s3c_irq_wdtac97_mask,
-        .irq_unmask     = s3c_irq_wdtac97_unmask,
-        .irq_ack        = s3c_irq_wdtac97_ack,
-};
-
-static int s3c2440_irq_add(struct device *dev, struct subsys_interface *sif)
-{
-        unsigned int irqno;
-
-        printk("S3C2440: IRQ Support\n");
-
-        /* add new chained handler for wdt, ac7 */
-
-        irq_set_chip_and_handler(IRQ_WDT, &s3c_irq_level_chip,
-                                 handle_level_irq);
-        irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
-
-        for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
-                irq_set_chip_and_handler(irqno, &s3c_irq_wdtac97,
-                                         handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-
-        return 0;
-}
-
-static struct subsys_interface s3c2440_irq_interface = {
-        .name           = "s3c2440_irq",
-        .subsys         = &s3c2440_subsys,
-        .add_dev        = s3c2440_irq_add,
-};
-
-static int s3c2440_irq_init(void)
-{
-        return subsys_interface_register(&s3c2440_irq_interface);
-}
-
-arch_initcall(s3c2440_irq_init);
-
diff --git a/arch/arm/mach-s3c24xx/irq-s3c244x.c b/arch/arm/mach-s3c24xx/irq-s3c244x.c
deleted file mode 100644
index 5fe8e58d3afd..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c244x.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/s3c244x-irq.c
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <plat/irq.h>
-
-/* camera irq */
-
-static void s3c_irq_demux_cam(unsigned int irq,
-                              struct irq_desc *desc)
-{
-        unsigned int subsrc, submsk;
-
-        /* read the current pending interrupts, and the mask
-         * for what it is available */
-
-        subsrc = __raw_readl(S3C2410_SUBSRCPND);
-        submsk = __raw_readl(S3C2410_INTSUBMSK);
-
-        subsrc &= ~submsk;
-        subsrc >>= 11;
-        subsrc &= 3;
-
-        if (subsrc != 0) {
-                if (subsrc & 1) {
-                        generic_handle_irq(IRQ_S3C2440_CAM_C);
-                }
-                if (subsrc & 2) {
-                        generic_handle_irq(IRQ_S3C2440_CAM_P);
-                }
-        }
-}
-
-#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
-
-static void
-s3c_irq_cam_mask(struct irq_data *data)
-{
-        s3c_irqsub_mask(data->irq, INTMSK_CAM, 3 << 11);
-}
-
-static void
-s3c_irq_cam_unmask(struct irq_data *data)
-{
-        s3c_irqsub_unmask(data->irq, INTMSK_CAM);
-}
-
-static void
-s3c_irq_cam_ack(struct irq_data *data)
-{
-        s3c_irqsub_maskack(data->irq, INTMSK_CAM, 3 << 11);
-}
-
-static struct irq_chip s3c_irq_cam = {
-        .irq_mask       = s3c_irq_cam_mask,
-        .irq_unmask     = s3c_irq_cam_unmask,
-        .irq_ack        = s3c_irq_cam_ack,
-};
-
-static int s3c244x_irq_add(struct device *dev, struct subsys_interface *sif)
-{
-        unsigned int irqno;
-
-        irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip,
-                                 handle_level_irq);
-        set_irq_flags(IRQ_NFCON, IRQF_VALID);
-
-        /* add chained handler for camera */
-
-        irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip,
-                                 handle_level_irq);
-        irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
-
-        for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
-                irq_set_chip_and_handler(irqno, &s3c_irq_cam,
-                                         handle_level_irq);
-                set_irq_flags(irqno, IRQF_VALID);
-        }
-
-        return 0;
-}
-
-static struct subsys_interface s3c2440_irq_interface = {
-        .name           = "s3c2440_irq",
-        .subsys         = &s3c2440_subsys,
-        .add_dev        = s3c244x_irq_add,
-};
-
-static int s3c2440_irq_init(void)
-{
-        return subsys_interface_register(&s3c2440_irq_interface);
-}
-
-arch_initcall(s3c2440_irq_init);
-
-static struct subsys_interface s3c2442_irq_interface = {
-        .name           = "s3c2442_irq",
-        .subsys         = &s3c2442_subsys,
-        .add_dev        = s3c244x_irq_add,
-};
-
-
-static int s3c2442_irq_init(void)
-{
-        return subsys_interface_register(&s3c2442_irq_interface);
-}
-
-arch_initcall(s3c2442_irq_init);
diff --git a/arch/arm/mach-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c
deleted file mode 100644
index d8ba9bee4c7e..000000000000
--- a/arch/arm/mach-s3c24xx/irq.c
+++ /dev/null
@@ -1,822 +0,0 @@
-/*
- * S3C24XX IRQ handling
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-*/
-
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/irqdomain.h>
-
-#include <asm/mach/irq.h>
-
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/cpu.h>
-#include <plat/regs-irqtype.h>
-#include <plat/pm.h>
-#include <plat/irq.h>
-
-#define S3C_IRQTYPE_NONE        0
-#define S3C_IRQTYPE_EINT        1
-#define S3C_IRQTYPE_EDGE        2
-#define S3C_IRQTYPE_LEVEL       3
-
-struct s3c_irq_data {
-        unsigned int type;
-        unsigned long parent_irq;
-
-        /* data gets filled during init */
-        struct s3c_irq_intc *intc;
-        unsigned long sub_bits;
-        struct s3c_irq_intc *sub_intc;
-};
-
-/*
- * Sructure holding the controller data
- * @reg_pending         register holding pending irqs
- * @reg_intpnd          special register intpnd in main intc
- * @reg_mask            mask register
- * @domain              irq_domain of the controller
- * @parent              parent controller for ext and sub irqs
- * @irqs                irq-data, always s3c_irq_data[32]
- */
-struct s3c_irq_intc {
-        void __iomem            *reg_pending;
-        void __iomem            *reg_intpnd;
-        void __iomem            *reg_mask;
-        struct irq_domain       *domain;
-        struct s3c_irq_intc     *parent;
-        struct s3c_irq_data     *irqs;
-};
-
-static void s3c_irq_mask(struct irq_data *data)
-{
-        struct s3c_irq_intc *intc = data->domain->host_data;
-        struct s3c_irq_intc *parent_intc = intc->parent;
-        struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
-        struct s3c_irq_data *parent_data;
-        unsigned long mask;
-        unsigned int irqno;
-
-        mask = __raw_readl(intc->reg_mask);
-        mask |= (1UL << data->hwirq);
-        __raw_writel(mask, intc->reg_mask);
-
-        if (parent_intc && irq_data->parent_irq) {
-                parent_data = &parent_intc->irqs[irq_data->parent_irq];
-
-                /* check to see if we need to mask the parent IRQ */
-                if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
-                        irqno = irq_find_mapping(parent_intc->domain,
-                                         irq_data->parent_irq);
-                        s3c_irq_mask(irq_get_irq_data(irqno));
-                }
-        }
-}
-
-static void s3c_irq_unmask(struct irq_data *data)
-{
-        struct s3c_irq_intc *intc = data->domain->host_data;
-        struct s3c_irq_intc *parent_intc = intc->parent;
-        struct s3c_irq_data *irq_data = &intc->irqs[data->hwirq];
-        unsigned long mask;
-        unsigned int irqno;
-
-        mask = __raw_readl(intc->reg_mask);
-        mask &= ~(1UL << data->hwirq);
-        __raw_writel(mask, intc->reg_mask);
-
-        if (parent_intc && irq_data->parent_irq) {
-                irqno = irq_find_mapping(parent_intc->domain,
-                                         irq_data->parent_irq);
-                s3c_irq_unmask(irq_get_irq_data(irqno));
-        }
-}
-
-static inline void s3c_irq_ack(struct irq_data *data)
-{
-        struct s3c_irq_intc *intc = data->domain->host_data;
-        unsigned long bitval = 1UL << data->hwirq;
-
-        __raw_writel(bitval, intc->reg_pending);
-        if (intc->reg_intpnd)
-                __raw_writel(bitval, intc->reg_intpnd);
-}
-
-static int s3c_irqext_type_set(void __iomem *gpcon_reg,
-                               void __iomem *extint_reg,
-                               unsigned long gpcon_offset,
-                               unsigned long extint_offset,
-                               unsigned int type)
-{
-        unsigned long newvalue = 0, value;
-
-        /* Set the GPIO to external interrupt mode */
-        value = __raw_readl(gpcon_reg);
-        value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
-        __raw_writel(value, gpcon_reg);
-
-        /* Set the external interrupt to pointed trigger type */
-        switch (type)
-        {
-                case IRQ_TYPE_NONE:
-                        pr_warn("No edge setting!\n");
-                        break;
-
-                case IRQ_TYPE_EDGE_RISING:
-                        newvalue = S3C2410_EXTINT_RISEEDGE;
-                        break;
-
-                case IRQ_TYPE_EDGE_FALLING:
-                        newvalue = S3C2410_EXTINT_FALLEDGE;
-                        break;
-
-                case IRQ_TYPE_EDGE_BOTH:
-                        newvalue = S3C2410_EXTINT_BOTHEDGE;
-                        break;
-
-                case IRQ_TYPE_LEVEL_LOW:
-                        newvalue = S3C2410_EXTINT_LOWLEV;
-                        break;
-
-                case IRQ_TYPE_LEVEL_HIGH:
-                        newvalue = S3C2410_EXTINT_HILEV;
-                        break;
-
-                default:
-                        pr_err("No such irq type %d", type);
-                        return -EINVAL;
-        }
-
-        value = __raw_readl(extint_reg);
-        value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
-        __raw_writel(value, extint_reg);
-
-        return 0;
-}
-
-/* FIXME: make static when it's out of plat-samsung/irq.h */
-int s3c_irqext_type(struct irq_data *data, unsigned int type)
-{
-        void __iomem *extint_reg;
-        void __iomem *gpcon_reg;
-        unsigned long gpcon_offset, extint_offset;
-
-        if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
-                gpcon_reg = S3C2410_GPFCON;
-                extint_reg = S3C24XX_EXTINT0;
-                gpcon_offset = (data->hwirq) * 2;
-                extint_offset = (data->hwirq) * 4;
-        } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
-                gpcon_reg = S3C2410_GPGCON;
-                extint_reg = S3C24XX_EXTINT1;
-                gpcon_offset = (data->hwirq - 8) * 2;
-                extint_offset = (data->hwirq - 8) * 4;
-        } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
-                gpcon_reg = S3C2410_GPGCON;
-                extint_reg = S3C24XX_EXTINT2;
-                gpcon_offset = (data->hwirq - 8) * 2;
-                extint_offset = (data->hwirq - 16) * 4;
-        } else {
-                return -EINVAL;
-        }
-
-        return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
-                                   extint_offset, type);
-}
-
-static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
-{
-        void __iomem *extint_reg;
-        void __iomem *gpcon_reg;
-        unsigned long gpcon_offset, extint_offset;
-
-        if ((data->hwirq >= 0) && (data->hwirq <= 3)) {
-                gpcon_reg = S3C2410_GPFCON;
-                extint_reg = S3C24XX_EXTINT0;
-                gpcon_offset = (data->hwirq) * 2;
-                extint_offset = (data->hwirq) * 4;
-        } else {
-                return -EINVAL;
-        }
-
-        return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
-                                   extint_offset, type);
-}
-
-struct irq_chip s3c_irq_chip = {
-        .name           = "s3c",
-        .irq_ack        = s3c_irq_ack,
-        .irq_mask       = s3c_irq_mask,
-        .irq_unmask     = s3c_irq_unmask,
-        .irq_set_wake   = s3c_irq_wake
-};
-
-struct irq_chip s3c_irq_level_chip = {
-        .name           = "s3c-level",
-        .irq_mask       = s3c_irq_mask,
-        .irq_unmask     = s3c_irq_unmask,
-        .irq_ack        = s3c_irq_ack,
-};
-
-static struct irq_chip s3c_irqext_chip = {
-        .name           = "s3c-ext",
-        .irq_mask       = s3c_irq_mask,
-        .irq_unmask     = s3c_irq_unmask,
-        .irq_ack        = s3c_irq_ack,
-        .irq_set_type   = s3c_irqext_type,
-        .irq_set_wake   = s3c_irqext_wake
-};
-
-static struct irq_chip s3c_irq_eint0t4 = {
-        .name           = "s3c-ext0",
-        .irq_ack        = s3c_irq_ack,
-        .irq_mask       = s3c_irq_mask,
-        .irq_unmask     = s3c_irq_unmask,
-        .irq_set_wake   = s3c_irq_wake,
-        .irq_set_type   = s3c_irqext0_type,
-};
-
-static void s3c_irq_demux(unsigned int irq, struct irq_desc *desc)
-{
-        struct irq_chip *chip = irq_desc_get_chip(desc);
-        struct s3c_irq_intc *intc = desc->irq_data.domain->host_data;
-        struct s3c_irq_data *irq_data = &intc->irqs[desc->irq_data.hwirq];
-        struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
-        unsigned long src;
-        unsigned long msk;
-        unsigned int n;
-
-        chained_irq_enter(chip, desc);
-
-        src = __raw_readl(sub_intc->reg_pending);
-        msk = __raw_readl(sub_intc->reg_mask);
-
-        src &= ~msk;
-        src &= irq_data->sub_bits;
-
-        while (src) {
-                n = __ffs(src);
-                src &= ~(1 << n);
-                generic_handle_irq(irq_find_mapping(sub_intc->domain, n));
-        }
-
-        chained_irq_exit(chip, desc);
-}
-
-#ifdef CONFIG_FIQ
-/**
- * s3c24xx_set_fiq - set the FIQ routing
- * @irq: IRQ number to route to FIQ on processor.
- * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
- *
- * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
- * @on is true, the @irq is checked to see if it can be routed and the
- * interrupt controller updated to route the IRQ. If @on is false, the FIQ
- * routing is cleared, regardless of which @irq is specified.
- */
-int s3c24xx_set_fiq(unsigned int irq, bool on)
-{
-        u32 intmod;
-        unsigned offs;
-
-        if (on) {
-                offs = irq - FIQ_START;
-                if (offs > 31)
-                        return -EINVAL;
-
-                intmod = 1 << offs;
-        } else {
-                intmod = 0;
-        }
-
-        __raw_writel(intmod, S3C2410_INTMOD);
-        return 0;
-}
-
-EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
-#endif
-
-static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
-                                                        irq_hw_number_t hw)
-{
-        struct s3c_irq_intc *intc = h->host_data;
-        struct s3c_irq_data *irq_data = &intc->irqs[hw];
-        struct s3c_irq_intc *parent_intc;
-        struct s3c_irq_data *parent_irq_data;
-        unsigned int irqno;
-
-        if (!intc) {
-                pr_err("irq-s3c24xx: no controller found for hwirq %lu\n", hw);
-                return -EINVAL;
-        }
-
-        if (!irq_data) {
-                pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n", hw);
-                return -EINVAL;
-        }
-
-        /* attach controller pointer to irq_data */
-        irq_data->intc = intc;
-
-        /* set handler and flags */
-        switch (irq_data->type) {
-        case S3C_IRQTYPE_NONE:
-                return 0;
-        case S3C_IRQTYPE_EINT:
-                if (irq_data->parent_irq)
-                        irq_set_chip_and_handler(virq, &s3c_irqext_chip,
-                                                 handle_edge_irq);
-                else
-                        irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
-                                                 handle_edge_irq);
-                break;
-        case S3C_IRQTYPE_EDGE:
-                if (irq_data->parent_irq ||
-                    intc->reg_pending == S3C2416_SRCPND2)
-                        irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
-                                                 handle_edge_irq);
-                else
-                        irq_set_chip_and_handler(virq, &s3c_irq_chip,
-                                                 handle_edge_irq);
-                break;
-        case S3C_IRQTYPE_LEVEL:
-                if (irq_data->parent_irq)
-                        irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
-                                                 handle_level_irq);
-                else
-                        irq_set_chip_and_handler(virq, &s3c_irq_chip,
-                                                 handle_level_irq);
-                break;
-        default:
-                pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
-                return -EINVAL;
-        }
-        set_irq_flags(virq, IRQF_VALID);
-
-        if (irq_data->parent_irq) {
-                parent_intc = intc->parent;
-                if (!parent_intc) {
-                        pr_err("irq-s3c24xx: no parent controller found for hwirq %lu\n",
-                               hw);
-                        goto err;
-                }
-
-                parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
-                if (!irq_data) {
-                        pr_err("irq-s3c24xx: no irq data found for hwirq %lu\n",
-                               hw);
-                        goto err;
-                }
-
-                parent_irq_data->sub_intc = intc;
-                parent_irq_data->sub_bits |= (1UL << hw);
-
-                /* attach the demuxer to the parent irq */
-                irqno = irq_find_mapping(parent_intc->domain,
-                                         irq_data->parent_irq);
-                if (!irqno) {
-                        pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
-                               irq_data->parent_irq);
-                        goto err;
-                }
-                irq_set_chained_handler(irqno, s3c_irq_demux);
-        }
-
-        return 0;
-
-err:
-        set_irq_flags(virq, 0);
-
-        /* the only error can result from bad mapping data*/
-        return -EINVAL;
-}
-
-static struct irq_domain_ops s3c24xx_irq_ops = {
-        .map = s3c24xx_irq_map,
-        .xlate = irq_domain_xlate_twocell,
-};
-
-static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
-{
-        void __iomem *reg_source;
-        unsigned long pend;
-        unsigned long last;
-        int i;
-
-        /* if intpnd is set, read the next pending irq from there */
-        reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
-
-        last = 0;
-        for (i = 0; i < 4; i++) {
-                pend = __raw_readl(reg_source);
-
-                if (pend == 0 || pend == last)
-                        break;
-
-                __raw_writel(pend, intc->reg_pending);
-                if (intc->reg_intpnd)
-                        __raw_writel(pend, intc->reg_intpnd);
-
-                pr_info("irq: clearing pending status %08x\n", (int)pend);
-                last = pend;
-        }
-}
-
-struct s3c_irq_intc *s3c24xx_init_intc(struct device_node *np,
-                                       struct s3c_irq_data *irq_data,
-                                       struct s3c_irq_intc *parent,
-                                       unsigned long address)
-{
-        struct s3c_irq_intc *intc;
-        void __iomem *base = (void *)0xf6000000; /* static mapping */
-        int irq_num;
-        int irq_start;
-        int irq_offset;
-        int ret;
-
-        intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
-        if (!intc)
-                return ERR_PTR(-ENOMEM);
-
-        intc->irqs = irq_data;
-
-        if (parent)
-                intc->parent = parent;
-
-        /* select the correct data for the controller.
-         * Need to hard code the irq num start and offset
-         * to preserve the static mapping for now
-         */
-        switch (address) {
-        case 0x4a000000:
-                pr_debug("irq: found main intc\n");
-                intc->reg_pending = base;
-                intc->reg_mask = base + 0x08;
-                intc->reg_intpnd = base + 0x10;
-                irq_num = 32;
-                irq_start = S3C2410_IRQ(0);
-                irq_offset = 0;
-                break;
-        case 0x4a000018:
-                pr_debug("irq: found subintc\n");
-                intc->reg_pending = base + 0x18;
-                intc->reg_mask = base + 0x1c;
-                irq_num = 29;
-                irq_start = S3C2410_IRQSUB(0);
-                irq_offset = 0;
-                break;
-        case 0x4a000040:
-                pr_debug("irq: found intc2\n");
-                intc->reg_pending = base + 0x40;
-                intc->reg_mask = base + 0x48;
-                intc->reg_intpnd = base + 0x50;
-                irq_num = 8;
-                irq_start = S3C2416_IRQ(0);
-                irq_offset = 0;
-                break;
-        case 0x560000a4:
-                pr_debug("irq: found eintc\n");
-                base = (void *)0xfd000000;
-
-                intc->reg_mask = base + 0xa4;
-                intc->reg_pending = base + 0xa8;
-                irq_num = 20;
-                irq_start = S3C2410_IRQ(32);
-                irq_offset = 4;
-                break;
-        default:
-                pr_err("irq: unsupported controller address\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        /* now that all the data is complete, init the irq-domain */
-        s3c24xx_clear_intc(intc);
-        intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
-                                             irq_offset, &s3c24xx_irq_ops,
-                                             intc);
-        if (!intc->domain) {
-                pr_err("irq: could not create irq-domain\n");
-                ret = -EINVAL;
-                goto err;
-        }
-
-        return intc;
-
-err:
-        kfree(intc);
-        return ERR_PTR(ret);
-}
-
-/* s3c24xx_init_irq
- *
- * Initialise S3C2410 IRQ system
-*/
-
-static struct s3c_irq_data init_base[32] = {
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
-        { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
-        { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
-        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
-        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
-};
-
-static struct s3c_irq_data init_eint[32] = {
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
-        { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
-};
-
-static struct s3c_irq_data init_subint[32] = {
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
-        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
-        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
-};
-
-void __init s3c24xx_init_irq(void)
-{
-        struct s3c_irq_intc *main_intc;
-
-#ifdef CONFIG_FIQ
-        init_FIQ(FIQ_START);
-#endif
-
-        main_intc = s3c24xx_init_intc(NULL, &init_base[0], NULL, 0x4a000000);
-        if (IS_ERR(main_intc)) {
-                pr_err("irq: could not create main interrupt controller\n");
-                return;
-        }
-
-        s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018);
-        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
-}
-
-#ifdef CONFIG_CPU_S3C2416
-static struct s3c_irq_data init_s3c2416base[32] = {
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
-        { .type = S3C_IRQTYPE_NONE, }, /* reserved */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
-        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
-        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
-        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
-        { .type = S3C_IRQTYPE_NONE, },
-        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
-};
-
-static struct s3c_irq_data init_s3c2416subint[32] = {
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
-        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
-        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
-};
-
-static struct s3c_irq_data init_s3c2416_second[32] = {
-        { .type = S3C_IRQTYPE_EDGE }, /* 2D */
-        { .type = S3C_IRQTYPE_EDGE }, /* IIC1 */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
-        { .type = S3C_IRQTYPE_EDGE }, /* PCM1 */
-        { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
-        { .type = S3C_IRQTYPE_EDGE }, /* I2S1 */
-};
-
-void __init s3c2416_init_irq(void)
-{
-        struct s3c_irq_intc *main_intc;
-
-        pr_info("S3C2416: IRQ Support\n");
-
-#ifdef CONFIG_FIQ
-        init_FIQ(FIQ_START);
-#endif
-
-        main_intc = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000);
-        if (IS_ERR(main_intc)) {
-                pr_err("irq: could not create main interrupt controller\n");
-                return;
-        }
-
-        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
-        s3c24xx_init_intc(NULL, &init_s3c2416subint[0], main_intc, 0x4a000018);
-
-        s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040);
-}
-
-#endif
-
-#ifdef CONFIG_CPU_S3C2443
-static struct s3c_irq_data init_s3c2443base[32] = {
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
-        { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
-        { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
-        { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
-        { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
-        { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
-        { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
-        { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
-};
-
-
-static struct s3c_irq_data init_s3c2443subint[32] = {
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
-        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
-        { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
-        { .type = S3C_IRQTYPE_NONE }, /* reserved */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
-        { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
-};
-
-void __init s3c2443_init_irq(void)
-{
-        struct s3c_irq_intc *main_intc;
-
-        pr_info("S3C2443: IRQ Support\n");
-
-#ifdef CONFIG_FIQ
-        init_FIQ(FIQ_START);
-#endif
-
-        main_intc = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000);
-        if (IS_ERR(main_intc)) {
-                pr_err("irq: could not create main interrupt controller\n");
-                return;
-        }
-
-        s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
-        s3c24xx_init_intc(NULL, &init_s3c2443subint[0], main_intc, 0x4a000018);
-}
-#endif
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 0e0279e79150..e27b5c91b3db 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -63,6 +63,8 @@
 #include <linux/mtd/map.h>
 #include <linux/mtd/physmap.h>
 
+#include <plat/samsung-time.h>
+
 #include "common.h"
 
 static struct resource amlm5900_nor_resource =
@@ -160,6 +162,7 @@ static void __init amlm5900_map_io(void)
         s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 #ifdef CONFIG_FB_S3C2410
@@ -235,8 +238,8 @@ static void __init amlm5900_init(void)
 MACHINE_START(AML_M5900, "AML_M5900")
         .atag_offset    = 0x100,
         .map_io         = amlm5900_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = amlm5900_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index bb595f15ce36..c1fb6c37867f 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/asoc-s3c24xx_simtec.h>
+#include <plat/samsung-time.h>
 
 #include "anubis.h"
 #include "common.h"
@@ -410,6 +411,7 @@ static void __init anubis_map_io(void)
         s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* check for the newer revision boards with large page nand */
 
@@ -443,7 +445,7 @@ MACHINE_START(ANUBIS, "Simtec-Anubis")
         .atag_offset    = 0x100,
         .map_io         = anubis_map_io,
         .init_machine   = anubis_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2440_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index b4bc60c78ebb..6dfeeb7ef469 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -48,6 +48,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/mmc-s3cmci.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -192,6 +193,7 @@ static void __init at2440evb_map_io(void)
         s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
         s3c24xx_init_clocks(16934400);
         s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init at2440evb_init(void)
@@ -209,7 +211,7 @@ MACHINE_START(AT2440EVB, "AT2440EVB")
         .atag_offset    = 0x100,
         .map_io         = at2440evb_map_io,
         .init_machine   = at2440evb_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2440_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index ca6618081041..22d6ae926d91 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -55,6 +55,7 @@
 #include <plat/devs.h>
 #include <plat/gpio-cfg.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "bast.h"
 #include "common.h"
@@ -576,6 +577,7 @@ static void __init bast_map_io(void)
         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init bast_init(void)
@@ -603,8 +605,8 @@ MACHINE_START(BAST, "Simtec-BAST")
         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
         .atag_offset    = 0x100,
         .map_io         = bast_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = bast_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index a25e8c5a7b4c..13d8d073675a 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -81,6 +81,7 @@
 #include <plat/gpio-cfg.h>
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "gta02.h"
@@ -501,6 +502,7 @@ static void __init gta02_map_io(void)
         s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 
@@ -587,8 +589,8 @@ MACHINE_START(NEO1973_GTA02, "GTA02")
         /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */
         .atag_offset    = 0x100,
         .map_io         = gta02_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2442_init_irq,
         .init_machine   = gta02_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index 79bc0830d740..af4334d6b4d5 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -62,7 +62,7 @@
 #include <plat/pll.h>
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
-
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "h1940.h"
@@ -646,6 +646,7 @@ static void __init h1940_map_io(void)
         s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* setup PM */
 
@@ -666,11 +667,6 @@ static void __init h1940_reserve(void)
         memblock_reserve(0x30081000, 0x1000);
 }
 
-static void __init h1940_init_irq(void)
-{
-        s3c24xx_init_irq();
-}
-
 static void __init h1940_init(void)
 {
         u32 tmp;
@@ -739,8 +735,8 @@ MACHINE_START(H1940, "IPAQ-H1940")
         .atag_offset    = 0x100,
         .map_io         = h1940_map_io,
         .reserve        = h1940_reserve,
-        .init_irq       = h1940_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = h1940_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index 54e83c1f780c..a45fcd8ccf79 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -46,14 +46,15 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
 
-#include <plat/s3c2412.h>
 #include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
+#include <plat/samsung-time.h>
 
+#include "common.h"
 #include "s3c2412-power.h"
 
 static struct map_desc jive_iodesc[] __initdata = {
@@ -506,6 +507,7 @@ static void __init jive_map_io(void)
         s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void jive_power_off(void)
@@ -658,9 +660,9 @@ MACHINE_START(JIVE, "JIVE")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
         .atag_offset    = 0x100,
 
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .map_io         = jive_map_io,
         .init_machine   = jive_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 2865e5919f2c..a83db46320bc 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -56,6 +56,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include <sound/s3c24xx_uda134x.h>
 
@@ -525,6 +526,7 @@ static void __init mini2440_map_io(void)
         s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 /*
@@ -686,7 +688,7 @@ MACHINE_START(MINI2440, "MINI2440")
         .atag_offset    = 0x100,
         .map_io         = mini2440_map_io,
         .init_machine   = mini2440_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2440_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index d9d04b240295..2cb46c37c920 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -48,8 +48,8 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <linux/platform_data/mmc-s3cmci.h>
-#include <plat/s3c2410.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -536,6 +536,7 @@ static void __init n30_map_io(void)
         n30_hwinit();
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 /* GPB3 is the line that controls the pull-up for the USB D+ line */
@@ -589,9 +590,9 @@ MACHINE_START(N30, "Acer-N30")
                                 Ben Dooks <ben-linux@fluff.org>
         */
         .atag_offset    = 0x100,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .init_machine   = n30_init,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .map_io         = n30_map_io,
         .restart        = s3c2410_restart,
 MACHINE_END
@@ -600,9 +601,9 @@ MACHINE_START(N35, "Acer-N35")
         /* Maintainer: Christer Weinigel <christer@weinigel.se>
         */
         .atag_offset    = 0x100,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .init_machine   = n30_init,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .map_io         = n30_map_io,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index a454e2461860..01f4354206f9 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -41,11 +41,10 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/s3c2410.h>
-#include <plat/s3c244x.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -137,6 +136,7 @@ static void __init nexcoder_map_io(void)
         s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         nexcoder_sensorboard_init();
 }
@@ -152,7 +152,7 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
         .atag_offset    = 0x100,
         .map_io         = nexcoder_map_io,
         .init_machine   = nexcoder_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2440_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index ae2cbdf3e3ca..58d6fbe5bf1f 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -45,6 +45,7 @@
 #include <plat/devs.h>
 #include <plat/gpio-cfg.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
@@ -384,6 +385,7 @@ static void __init osiris_map_io(void)
         s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* check for the newer revision boards with large page nand */
 
@@ -424,8 +426,8 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS")
         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
         .atag_offset    = 0x100,
         .map_io         = osiris_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2440_init_irq,
         .init_machine   = osiris_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index 40a47d6c6a85..7e16b0740ec1 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -33,7 +33,7 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/regs-serial.h>
-#include <plat/s3c2410.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "otom.h"
@@ -102,6 +102,7 @@ static void __init otom11_map_io(void)
         s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init otom11_init(void)
@@ -115,7 +116,7 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
         .atag_offset    = 0x100,
         .map_io         = otom11_map_io,
         .init_machine   = otom11_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2410_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 56175f0941b1..f8feaeadb55a 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -55,13 +55,14 @@
 #include <linux/platform_data/usb-s3c2410_udc.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <plat/common-smdk.h>
 #include <plat/gpio-cfg.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc qt2410_iodesc[] __initdata = {
         { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
@@ -304,6 +305,7 @@ static void __init qt2410_map_io(void)
         s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
         s3c24xx_init_clocks(12*1000*1000);
         s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init qt2410_machine_init(void)
@@ -341,8 +343,8 @@ static void __init qt2410_machine_init(void)
 MACHINE_START(QT2410, "QT2410")
         .atag_offset    = 0x100,
         .map_io         = qt2410_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = qt2410_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index 1f9ba2ae5288..44ca018e1f96 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -56,8 +56,8 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
-#include <plat/regs-iic.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "h1940.h"
@@ -741,6 +741,7 @@ static void __init rx1950_map_io(void)
         s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc));
         s3c24xx_init_clocks(16934000);
         s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* setup PM */
 
@@ -811,8 +812,8 @@ MACHINE_START(RX1950, "HP iPAQ RX1950")
         .atag_offset = 0x100,
         .map_io = rx1950_map_io,
         .reserve        = rx1950_reserve,
-        .init_irq = s3c24xx_init_irq,
+        .init_irq       = s3c2442_init_irq,
         .init_machine = rx1950_init_machine,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index f20418a2fb1b..3bc6231d0a1f 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "h1940.h"
@@ -179,6 +180,7 @@ static void __init rx3715_map_io(void)
         s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
         s3c24xx_init_clocks(16934000);
         s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 /* H1940 and RX3715 need to reserve this for suspend */
@@ -188,11 +190,6 @@ static void __init rx3715_reserve(void)
         memblock_reserve(0x30081000, 0x1000);
 }
 
-static void __init rx3715_init_irq(void)
-{
-        s3c24xx_init_irq();
-}
-
 static void __init rx3715_init_machine(void)
 {
 #ifdef CONFIG_PM_H1940
@@ -210,8 +207,8 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
         .atag_offset    = 0x100,
         .map_io         = rx3715_map_io,
         .reserve        = rx3715_reserve,
-        .init_irq       = rx3715_init_irq,
+        .init_irq       = s3c2440_init_irq,
         .init_machine   = rx3715_init_machine,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index e184bfa9613a..a773789e4f38 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
@@ -51,10 +51,10 @@
 
 #include <plat/devs.h>
 #include <plat/cpu.h>
-
-#include <plat/common-smdk.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2410_iodesc[] __initdata = {
   /* nothing here yet */
@@ -101,6 +101,7 @@ static void __init smdk2410_map_io(void)
         s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2410_init(void)
@@ -115,8 +116,8 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc
         /* Maintainer: Jonas Dietsche */
         .atag_offset    = 0x100,
         .map_io         = smdk2410_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = smdk2410_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index 86d7847c9d45..8146e920f10d 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -41,13 +41,13 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <mach/fb.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c2412.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
-#include <plat/common-smdk.h>
+#include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2413_iodesc[] __initdata = {
 };
@@ -106,6 +106,7 @@ static void __init smdk2413_map_io(void)
         s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2413_machine_init(void)
@@ -129,10 +130,10 @@ MACHINE_START(S3C2413, "S3C2413")
         .atag_offset    = 0x100,
 
         .fixup          = smdk2413_fixup,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
 
@@ -141,10 +142,10 @@ MACHINE_START(SMDK2412, "SMDK2412")
         .atag_offset    = 0x100,
 
         .fixup          = smdk2413_fixup,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
 
@@ -153,9 +154,9 @@ MACHINE_START(SMDK2413, "SMDK2413")
         .atag_offset    = 0x100,
 
         .fixup          = smdk2413_fixup,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .map_io         = smdk2413_map_io,
         .init_machine   = smdk2413_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index ebb2e61f3d07..cb46847c66b4 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -42,7 +42,6 @@
 #include <linux/platform_data/leds-s3c24xx.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <plat/s3c2416.h>
 #include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
@@ -51,10 +50,12 @@
 #include <plat/sdhci.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
 #include <linux/platform_data/s3c-hsudc.h>
+#include <plat/samsung-time.h>
 
 #include <plat/fb.h>
 
-#include <plat/common-smdk.h>
+#include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2416_iodesc[] __initdata = {
         /* ISA IO Space map (memory space selected by A24) */
@@ -221,6 +222,7 @@ static void __init smdk2416_map_io(void)
         s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2416_machine_init(void)
@@ -253,6 +255,6 @@ MACHINE_START(SMDK2416, "SMDK2416")
         .init_irq       = s3c2416_init_irq,
         .map_io         = smdk2416_map_io,
         .init_machine   = smdk2416_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2416_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index 08cc38c8a4ae..de2e5d39a847 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
@@ -38,15 +38,13 @@
 #include <mach/fb.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c244x.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-
-#include <plat/common-smdk.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2440_iodesc[] __initdata = {
         /* ISA IO Space map (memory space selected by A24) */
@@ -163,6 +161,7 @@ static void __init smdk2440_map_io(void)
         s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc));
         s3c24xx_init_clocks(16934400);
         s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2440_machine_init(void)
@@ -178,9 +177,9 @@ MACHINE_START(S3C2440, "SMDK2440")
         /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
         .atag_offset    = 0x100,
 
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2440_init_irq,
         .map_io         = smdk2440_map_io,
         .init_machine   = smdk2440_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index fc65d74d3c73..9435c3bef18a 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -38,13 +38,13 @@
 #include <mach/fb.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c2443.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
-#include <plat/common-smdk.h>
+#include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2443_iodesc[] __initdata = {
         /* ISA IO Space map (memory space selected by A24) */
@@ -122,6 +122,7 @@ static void __init smdk2443_map_io(void)
         s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdk2443_machine_init(void)
@@ -143,6 +144,6 @@ MACHINE_START(SMDK2443, "SMDK2443")
         .init_irq       = s3c2443_init_irq,
         .map_io         = smdk2443_map_io,
         .init_machine   = smdk2443_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2443_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index 24b3d79e7b2c..7fad8f055cab 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
@@ -53,6 +53,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/physmap.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -136,6 +137,7 @@ static void __init tct_hammer_map_io(void)
         s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init tct_hammer_init(void)
@@ -147,8 +149,8 @@ static void __init tct_hammer_init(void)
 MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
         .atag_offset    = 0x100,
         .map_io         = tct_hammer_map_io,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2410_init_irq,
         .init_machine   = tct_hammer_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index ec42d1e4e465..42e7187fed60 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -45,6 +45,7 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/regs-serial.h>
+#include <plat/samsung-time.h>
 
 #include "bast.h"
 #include "common.h"
@@ -332,6 +333,7 @@ static void __init vr1000_map_io(void)
         s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init vr1000_init(void)
@@ -353,7 +355,7 @@ MACHINE_START(VR1000, "Thorcom-VR1000")
         .atag_offset    = 0x100,
         .map_io         = vr1000_map_io,
         .init_machine   = vr1000_init,
-        .init_irq       = s3c24xx_init_irq,
-        .init_time      = s3c24xx_timer_init,
+        .init_irq       = s3c2410_init_irq,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 3e2bfddc9df1..b66588428ec9 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -41,12 +41,12 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c2412.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
+#include "common.h"
 
 static struct map_desc vstms_iodesc[] __initdata = {
 };
@@ -143,6 +143,7 @@ static void __init vstms_map_io(void)
         s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init vstms_init(void)
@@ -157,9 +158,9 @@ MACHINE_START(VSTMS, "VSTMS")
         .atag_offset    = 0x100,
 
         .fixup          = vstms_fixup,
-        .init_irq       = s3c24xx_init_irq,
+        .init_irq       = s3c2412_init_irq,
         .init_machine   = vstms_init,
         .map_io         = vstms_map_io,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2412.c b/arch/arm/mach-s3c24xx/pm-s3c2412.c
index 668a78a8b195..d75f95e487ee 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2412.c
@@ -29,7 +29,7 @@
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <plat/s3c2412.h>
+#include <plat/wakeup-mask.h>
 
 #include "regs-dsc.h"
 #include "s3c2412-power.h"
@@ -52,8 +52,15 @@ static int s3c2412_cpu_suspend(unsigned long arg)
         return 1; /* Aborting suspend */
 }
 
+/* mapping of interrupts to parts of the wakeup mask */
+static struct samsung_wakeup_mask wake_irqs[] = {
+        { .irq = IRQ_RTC,       .bit = S3C2412_PWRCFG_RTC_MASKIRQ, },
+};
+
 static void s3c2412_pm_prepare(void)
 {
+        samsung_sync_wakemask(S3C2412_PWRCFG,
+                              wake_irqs, ARRAY_SIZE(wake_irqs));
 }
 
 static int s3c2412_pm_add(struct device *dev, struct subsys_interface *sif)
diff --git a/arch/arm/mach-s3c24xx/regs-dsc.h b/arch/arm/mach-s3c24xx/regs-dsc.h
index 98fd4a05587c..61b3d1387d76 100644
--- a/arch/arm/mach-s3c24xx/regs-dsc.h
+++ b/arch/arm/mach-s3c24xx/regs-dsc.h
@@ -1,5 +1,4 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-dsc.h
- *
+/*
  * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
  *                    http://www.simtec.co.uk/products/SWLINUX/
  *
@@ -12,209 +11,15 @@
 
 
 #ifndef __ASM_ARCH_REGS_DSC_H
-#define __ASM_ARCH_REGS_DSC_H "2440-dsc"
+#define __ASM_ARCH_REGS_DSC_H __FILE__
 
-#if defined(CONFIG_CPU_S3C2412)
+/* S3C2412 */
 #define S3C2412_DSC0       S3C2410_GPIOREG(0xdc)
 #define S3C2412_DSC1       S3C2410_GPIOREG(0xe0)
-#endif
-
-#if defined(CONFIG_CPU_S3C2416)
-#define S3C2416_DSC0       S3C2410_GPIOREG(0xc0)
-#define S3C2416_DSC1       S3C2410_GPIOREG(0xc4)
-#define S3C2416_DSC2       S3C2410_GPIOREG(0xc8)
-#define S3C2416_DSC3       S3C2410_GPIOREG(0x110)
-
-#define S3C2416_SELECT_DSC0     (0 << 30)
-#define S3C2416_SELECT_DSC1     (1 << 30)
-#define S3C2416_SELECT_DSC2     (2 << 30)
-#define S3C2416_SELECT_DSC3     (3 << 30)
-
-#define S3C2416_DSC_GETSHIFT(x) (x & 30)
-
-#define S3C2416_DSC0_CF         (S3C2416_SELECT_DSC0 | 28)
-#define S3C2416_DSC0_CF_5mA     (0 << 28)
-#define S3C2416_DSC0_CF_10mA    (1 << 28)
-#define S3C2416_DSC0_CF_15mA    (2 << 28)
-#define S3C2416_DSC0_CF_21mA    (3 << 28)
-#define S3C2416_DSC0_CF_MASK    (3 << 28)
-
-#define S3C2416_DSC0_nRBE       (S3C2416_SELECT_DSC0 | 26)
-#define S3C2416_DSC0_nRBE_5mA   (0 << 26)
-#define S3C2416_DSC0_nRBE_10mA  (1 << 26)
-#define S3C2416_DSC0_nRBE_15mA  (2 << 26)
-#define S3C2416_DSC0_nRBE_21mA  (3 << 26)
-#define S3C2416_DSC0_nRBE_MASK  (3 << 26)
-
-#define S3C2416_DSC0_nROE       (S3C2416_SELECT_DSC0 | 24)
-#define S3C2416_DSC0_nROE_5mA   (0 << 24)
-#define S3C2416_DSC0_nROE_10mA  (1 << 24)
-#define S3C2416_DSC0_nROE_15mA  (2 << 24)
-#define S3C2416_DSC0_nROE_21mA  (3 << 24)
-#define S3C2416_DSC0_nROE_MASK  (3 << 24)
-
-#endif
-
-#if defined(CONFIG_CPU_S3C244X)
 
+/* S3C2440 */
 #define S3C2440_DSC0       S3C2410_GPIOREG(0xc4)
 #define S3C2440_DSC1       S3C2410_GPIOREG(0xc8)
 
-#define S3C2440_SELECT_DSC0 (0)
-#define S3C2440_SELECT_DSC1 (1<<31)
-
-#define S3C2440_DSC_GETSHIFT(x) ((x) & 31)
-
-#define S3C2440_DSC0_DISABLE    (1<<31)
-
-#define S3C2440_DSC0_ADDR       (S3C2440_SELECT_DSC0 | 8)
-#define S3C2440_DSC0_ADDR_12mA  (0<<8)
-#define S3C2440_DSC0_ADDR_10mA  (1<<8)
-#define S3C2440_DSC0_ADDR_8mA   (2<<8)
-#define S3C2440_DSC0_ADDR_6mA   (3<<8)
-#define S3C2440_DSC0_ADDR_MASK  (3<<8)
-
-/* D24..D31 */
-#define S3C2440_DSC0_DATA3      (S3C2440_SELECT_DSC0 | 6)
-#define S3C2440_DSC0_DATA3_12mA (0<<6)
-#define S3C2440_DSC0_DATA3_10mA (1<<6)
-#define S3C2440_DSC0_DATA3_8mA  (2<<6)
-#define S3C2440_DSC0_DATA3_6mA  (3<<6)
-#define S3C2440_DSC0_DATA3_MASK (3<<6)
-
-/* D16..D23 */
-#define S3C2440_DSC0_DATA2      (S3C2440_SELECT_DSC0 | 4)
-#define S3C2440_DSC0_DATA2_12mA (0<<4)
-#define S3C2440_DSC0_DATA2_10mA (1<<4)
-#define S3C2440_DSC0_DATA2_8mA  (2<<4)
-#define S3C2440_DSC0_DATA2_6mA  (3<<4)
-#define S3C2440_DSC0_DATA2_MASK (3<<4)
-
-/* D8..D15 */
-#define S3C2440_DSC0_DATA1      (S3C2440_SELECT_DSC0 | 2)
-#define S3C2440_DSC0_DATA1_12mA (0<<2)
-#define S3C2440_DSC0_DATA1_10mA (1<<2)
-#define S3C2440_DSC0_DATA1_8mA  (2<<2)
-#define S3C2440_DSC0_DATA1_6mA  (3<<2)
-#define S3C2440_DSC0_DATA1_MASK (3<<2)
-
-/* D0..D7 */
-#define S3C2440_DSC0_DATA0      (S3C2440_SELECT_DSC0 | 0)
-#define S3C2440_DSC0_DATA0_12mA (0<<0)
-#define S3C2440_DSC0_DATA0_10mA (1<<0)
-#define S3C2440_DSC0_DATA0_8mA  (2<<0)
-#define S3C2440_DSC0_DATA0_6mA  (3<<0)
-#define S3C2440_DSC0_DATA0_MASK (3<<0)
-
-#define S3C2440_DSC1_SCK1       (S3C2440_SELECT_DSC1 | 28)
-#define S3C2440_DSC1_SCK1_12mA  (0<<28)
-#define S3C2440_DSC1_SCK1_10mA  (1<<28)
-#define S3C2440_DSC1_SCK1_8mA   (2<<28)
-#define S3C2440_DSC1_SCK1_6mA   (3<<28)
-#define S3C2440_DSC1_SCK1_MASK  (3<<28)
-
-#define S3C2440_DSC1_SCK0       (S3C2440_SELECT_DSC1 | 26)
-#define S3C2440_DSC1_SCK0_12mA  (0<<26)
-#define S3C2440_DSC1_SCK0_10mA  (1<<26)
-#define S3C2440_DSC1_SCK0_8mA   (2<<26)
-#define S3C2440_DSC1_SCK0_6mA   (3<<26)
-#define S3C2440_DSC1_SCK0_MASK  (3<<26)
-
-#define S3C2440_DSC1_SCKE       (S3C2440_SELECT_DSC1 | 24)
-#define S3C2440_DSC1_SCKE_10mA  (0<<24)
-#define S3C2440_DSC1_SCKE_8mA   (1<<24)
-#define S3C2440_DSC1_SCKE_6mA   (2<<24)
-#define S3C2440_DSC1_SCKE_4mA   (3<<24)
-#define S3C2440_DSC1_SCKE_MASK  (3<<24)
-
-/* SDRAM nRAS/nCAS */
-#define S3C2440_DSC1_SDR        (S3C2440_SELECT_DSC1 | 22)
-#define S3C2440_DSC1_SDR_10mA   (0<<22)
-#define S3C2440_DSC1_SDR_8mA    (1<<22)
-#define S3C2440_DSC1_SDR_6mA    (2<<22)
-#define S3C2440_DSC1_SDR_4mA    (3<<22)
-#define S3C2440_DSC1_SDR_MASK   (3<<22)
-
-/* NAND Flash Controller */
-#define S3C2440_DSC1_NFC        (S3C2440_SELECT_DSC1 | 20)
-#define S3C2440_DSC1_NFC_10mA   (0<<20)
-#define S3C2440_DSC1_NFC_8mA    (1<<20)
-#define S3C2440_DSC1_NFC_6mA    (2<<20)
-#define S3C2440_DSC1_NFC_4mA    (3<<20)
-#define S3C2440_DSC1_NFC_MASK   (3<<20)
-
-/* nBE[0..3] */
-#define S3C2440_DSC1_nBE        (S3C2440_SELECT_DSC1 | 18)
-#define S3C2440_DSC1_nBE_10mA   (0<<18)
-#define S3C2440_DSC1_nBE_8mA    (1<<18)
-#define S3C2440_DSC1_nBE_6mA    (2<<18)
-#define S3C2440_DSC1_nBE_4mA    (3<<18)
-#define S3C2440_DSC1_nBE_MASK   (3<<18)
-
-#define S3C2440_DSC1_WOE        (S3C2440_SELECT_DSC1 | 16)
-#define S3C2440_DSC1_WOE_10mA   (0<<16)
-#define S3C2440_DSC1_WOE_8mA    (1<<16)
-#define S3C2440_DSC1_WOE_6mA    (2<<16)
-#define S3C2440_DSC1_WOE_4mA    (3<<16)
-#define S3C2440_DSC1_WOE_MASK   (3<<16)
-
-#define S3C2440_DSC1_CS7        (S3C2440_SELECT_DSC1 | 14)
-#define S3C2440_DSC1_CS7_10mA   (0<<14)
-#define S3C2440_DSC1_CS7_8mA    (1<<14)
-#define S3C2440_DSC1_CS7_6mA    (2<<14)
-#define S3C2440_DSC1_CS7_4mA    (3<<14)
-#define S3C2440_DSC1_CS7_MASK   (3<<14)
-
-#define S3C2440_DSC1_CS6        (S3C2440_SELECT_DSC1 | 12)
-#define S3C2440_DSC1_CS6_10mA   (0<<12)
-#define S3C2440_DSC1_CS6_8mA    (1<<12)
-#define S3C2440_DSC1_CS6_6mA    (2<<12)
-#define S3C2440_DSC1_CS6_4mA    (3<<12)
-#define S3C2440_DSC1_CS6_MASK   (3<<12)
-
-#define S3C2440_DSC1_CS5        (S3C2440_SELECT_DSC1 | 10)
-#define S3C2440_DSC1_CS5_10mA   (0<<10)
-#define S3C2440_DSC1_CS5_8mA    (1<<10)
-#define S3C2440_DSC1_CS5_6mA    (2<<10)
-#define S3C2440_DSC1_CS5_4mA    (3<<10)
-#define S3C2440_DSC1_CS5_MASK   (3<<10)
-
-#define S3C2440_DSC1_CS4        (S3C2440_SELECT_DSC1 | 8)
-#define S3C2440_DSC1_CS4_10mA   (0<<8)
-#define S3C2440_DSC1_CS4_8mA    (1<<8)
-#define S3C2440_DSC1_CS4_6mA    (2<<8)
-#define S3C2440_DSC1_CS4_4mA    (3<<8)
-#define S3C2440_DSC1_CS4_MASK   (3<<8)
-
-#define S3C2440_DSC1_CS3        (S3C2440_SELECT_DSC1 | 6)
-#define S3C2440_DSC1_CS3_10mA   (0<<6)
-#define S3C2440_DSC1_CS3_8mA    (1<<6)
-#define S3C2440_DSC1_CS3_6mA    (2<<6)
-#define S3C2440_DSC1_CS3_4mA    (3<<6)
-#define S3C2440_DSC1_CS3_MASK   (3<<6)
-
-#define S3C2440_DSC1_CS2        (S3C2440_SELECT_DSC1 | 4)
-#define S3C2440_DSC1_CS2_10mA   (0<<4)
-#define S3C2440_DSC1_CS2_8mA    (1<<4)
-#define S3C2440_DSC1_CS2_6mA    (2<<4)
-#define S3C2440_DSC1_CS2_4mA    (3<<4)
-#define S3C2440_DSC1_CS2_MASK   (3<<4)
-
-#define S3C2440_DSC1_CS1        (S3C2440_SELECT_DSC1 | 2)
-#define S3C2440_DSC1_CS1_10mA   (0<<2)
-#define S3C2440_DSC1_CS1_8mA    (1<<2)
-#define S3C2440_DSC1_CS1_6mA    (2<<2)
-#define S3C2440_DSC1_CS1_4mA    (3<<2)
-#define S3C2440_DSC1_CS1_MASK   (3<<2)
-
-#define S3C2440_DSC1_CS0        (S3C2440_SELECT_DSC1 | 0)
-#define S3C2440_DSC1_CS0_10mA   (0<<0)
-#define S3C2440_DSC1_CS0_8mA    (1<<0)
-#define S3C2440_DSC1_CS0_6mA    (2<<0)
-#define S3C2440_DSC1_CS0_4mA    (3<<0)
-#define S3C2440_DSC1_CS0_MASK   (3<<0)
-
-#endif /* CONFIG_CPU_S3C2440 */
-
 #endif  /* __ASM_ARCH_REGS_DSC_H */
 
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index 9ebef95da721..d850ea5adac2 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -37,7 +37,6 @@
 #include <mach/regs-clock.h>
 #include <plat/regs-serial.h>
 
-#include <plat/s3c2410.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/clock.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 0d592159a5c3..0f864d4c97de 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -44,7 +44,6 @@
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-spi.h>
-#include <plat/s3c2412.h>
 
 #include "common.h"
 #include "regs-dsc.h"
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index e30476db0295..b9c5d382dafb 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -50,7 +50,6 @@
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
-#include <plat/s3c2416.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/sdhci.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2440.c b/arch/arm/mach-s3c24xx/s3c2440.c
index 559e394e8989..5f9d6569475d 100644
--- a/arch/arm/mach-s3c24xx/s3c2440.c
+++ b/arch/arm/mach-s3c24xx/s3c2440.c
@@ -33,7 +33,6 @@
 
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/s3c244x.h>
 #include <plat/pm.h>
 
 #include <plat/gpio-core.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c
index f732826c2359..6819961f6b19 100644
--- a/arch/arm/mach-s3c24xx/s3c2442.c
+++ b/arch/arm/mach-s3c24xx/s3c2442.c
@@ -44,7 +44,6 @@
 
 #include <plat/clock.h>
 #include <plat/cpu.h>
-#include <plat/s3c244x.h>
 #include <plat/pm.h>
 
 #include <plat/gpio-core.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
index 165b6a6b3daa..8328cd65bf3d 100644
--- a/arch/arm/mach-s3c24xx/s3c2443.c
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -36,7 +36,6 @@
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
-#include <plat/s3c2443.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/fb-core.h>
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index ad2671baa910..2a35edb67354 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -37,8 +37,6 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c244x.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 131c86284711..20578536aec7 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -17,11 +17,13 @@ config PLAT_S3C64XX
 # Configuration options for the S3C6410 CPU
 
 config CPU_S3C6400
+        select SAMSUNG_HRT
         bool
         help
           Enable S3C6400 CPU support
 
 config CPU_S3C6410
+        select SAMSUNG_HRT
         bool
         help
           Enable S3C6410 CPU support
@@ -198,10 +200,7 @@ endchoice
 config SMDK6410_WM1190_EV1
         bool "Support Wolfson Microelectronics 1190-EV1 PMIC card"
         depends on MACH_SMDK6410
-        select MFD_WM8350_CONFIG_MODE_0
-        select MFD_WM8350_CONFIG_MODE_3
         select MFD_WM8350_I2C
-        select MFD_WM8352_CONFIG_MODE_0
         select REGULATOR
         select REGULATOR_WM8350
         select SAMSUNG_GPIO_EXTRA64
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index f9ce1dc28ce4..31d0c9101272 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -32,7 +32,6 @@ obj-$(CONFIG_S3C64XX_DMA)	+= dma.o
 
 obj-y                           += dev-uart.o
 obj-y                           += dev-audio.o
-obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
 
 # Device setup
 
diff --git a/arch/arm/mach-s3c64xx/cpuidle.c b/arch/arm/mach-s3c64xx/cpuidle.c
index ead5fab0dbb5..3c8ab07c2012 100644
--- a/arch/arm/mach-s3c64xx/cpuidle.c
+++ b/arch/arm/mach-s3c64xx/cpuidle.c
@@ -40,12 +40,9 @@ static int s3c64xx_enter_idle(struct cpuidle_device *dev,
         return index;
 }
 
-static DEFINE_PER_CPU(struct cpuidle_device, s3c64xx_cpuidle_device);
-
 static struct cpuidle_driver s3c64xx_cpuidle_driver = {
         .name   = "s3c64xx_cpuidle",
         .owner  = THIS_MODULE,
-        .en_core_tk_irqen = 1,
         .states = {
                 {
                         .enter            = s3c64xx_enter_idle,
@@ -61,16 +58,6 @@ static struct cpuidle_driver s3c64xx_cpuidle_driver = {
 
 static int __init s3c64xx_init_cpuidle(void)
 {
-        int ret;
-
-        cpuidle_register_driver(&s3c64xx_cpuidle_driver);
-
-        ret = cpuidle_register_device(&s3c64xx_cpuidle_device);
-        if (ret) {
-                pr_err("Failed to register cpuidle device: %d\n", ret);
-                return ret;
-        }
-
-        return 0;
+        return cpuidle_register(&s3c64xx_cpuidle_driver, NULL);
 }
 device_initcall(s3c64xx_init_cpuidle);
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index 6af1aa1ef213..759846c28d12 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -509,6 +509,7 @@ int s3c2410_dma_request(enum dma_ch channel,
         chan->client = client;
         chan->in_use = 1;
         chan->peripheral = channel;
+        chan->flags = 0;
 
         local_irq_restore(flags);
 
diff --git a/arch/arm/mach-s3c64xx/include/mach/debug-macro.S b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
index c0c076a90f27..dd9ccca5de1f 100644
--- a/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
@@ -35,4 +35,4 @@
  * will be fine with us.
  */
 
-#include <plat/debug-macro.S>
+#include <debug/samsung.S>
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h
index 57b1ff4b2d7c..fe1a98cf0e4c 100644
--- a/arch/arm/mach-s3c64xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c64xx/include/mach/dma.h
@@ -21,7 +21,6 @@
  */
 enum dma_ch {
         /* DMA0/SDMA0 */
-        DMACH_DT_PROP = -1, /* not yet supported, do not use */
         DMACH_UART0 = 0,
         DMACH_UART0_SRC2,
         DMACH_UART1,
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index 728eef3296b2..35e3f54574ef 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <mach/regs-gpio.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -208,6 +209,7 @@ static void __init anw6410_map_io(void)
         s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         anw6410_lcd_mode_set();
 }
@@ -232,6 +234,6 @@ MACHINE_START(ANW6410, "A&W6410")
         .map_io         = anw6410_map_io,
         .init_machine   = anw6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index bf3d1c09b085..7ccfef227c77 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -208,8 +208,9 @@ static const struct i2c_board_info wm1277_devs[] = {
 static struct arizona_pdata wm5102_reva_pdata = {
         .ldoena = S3C64XX_GPN(7),
         .gpio_base = CODEC_GPIO_BASE,
-        .irq_active_high = true,
+        .irq_flags = IRQF_TRIGGER_HIGH,
         .micd_pol_gpio = CODEC_GPIO_BASE + 4,
+        .micd_rate = 6,
         .gpio_defaults = {
                 [2] = 0x10000, /* AIF3TXLRCLK */
                 [3] = 0x4,     /* OPCLK */
@@ -237,7 +238,7 @@ static struct spi_board_info wm5102_reva_spi_devs[] = {
 static struct arizona_pdata wm5102_pdata = {
         .ldoena = S3C64XX_GPN(7),
         .gpio_base = CODEC_GPIO_BASE,
-        .irq_active_high = true,
+        .irq_flags = IRQF_TRIGGER_HIGH,
         .micd_pol_gpio = CODEC_GPIO_BASE + 2,
         .gpio_defaults = {
                 [2] = 0x10000, /* AIF3TXLRCLK */
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 1acf02bace57..8ad88ace795a 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -64,6 +64,7 @@
 #include <plat/adc.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/pm.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "crag6410.h"
@@ -744,6 +745,7 @@ static void __init crag6410_map_io(void)
         s3c64xx_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* LCD type and Bypass set by bootloader */
 }
@@ -868,6 +870,6 @@ MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
         .map_io         = crag6410_map_io,
         .init_machine   = crag6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 7212eb9cfeb9..5b7f357d8c22 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -41,6 +41,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -248,6 +249,7 @@ static void __init hmt_map_io(void)
         s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init hmt_machine_init(void)
@@ -275,6 +277,6 @@ MACHINE_START(HMT, "Airgoo-HMT")
         .map_io         = hmt_map_io,
         .init_machine   = hmt_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 4b41fcdaa7b6..fc043e3ecdf8 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -41,6 +41,7 @@
 
 #include <video/platform_lcd.h>
 #include <video/samsung_fimd.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -232,6 +233,7 @@ static void __init mini6410_map_io(void)
         s3c64xx_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* set the LCD type */
         tmp = __raw_readl(S3C64XX_SPCON);
@@ -354,6 +356,6 @@ MACHINE_START(MINI6410, "MINI6410")
         .map_io         = mini6410_map_io,
         .init_machine   = mini6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index 8d3cedd995ff..7e2c3908f1f8 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -43,6 +43,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -87,6 +88,7 @@ static void __init ncp_map_io(void)
         s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init ncp_machine_init(void)
@@ -103,6 +105,6 @@ MACHINE_START(NCP, "NCP")
         .map_io         = ncp_map_io,
         .init_machine   = ncp_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index fa12bd21ad82..8bed37b3d5ac 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -42,6 +42,7 @@
 
 #include <video/platform_lcd.h>
 #include <video/samsung_fimd.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -211,6 +212,7 @@ static void __init real6410_map_io(void)
         s3c64xx_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* set the LCD type */
         tmp = __raw_readl(S3C64XX_SPCON);
@@ -333,6 +335,6 @@ MACHINE_START(REAL6410, "REAL6410")
         .map_io         = real6410_map_io,
         .init_machine   = real6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index fc3e9b32e26f..58ac99041274 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -38,6 +38,7 @@
 #include <linux/platform_data/touchscreen-s3c2410.h>
 
 #include <video/platform_lcd.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -378,6 +379,7 @@ void __init smartq_map_io(void)
         s3c64xx_init_io(smartq_iodesc, ARRAY_SIZE(smartq_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         smartq_lcd_mode_set();
 }
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index ca2afcfce573..8aca5daf3d05 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -28,6 +28,7 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "mach-smartq.h"
@@ -155,6 +156,6 @@ MACHINE_START(SMARTQ5, "SmartQ 5")
         .map_io         = smartq_map_io,
         .init_machine   = smartq5_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index 37bb0c632a5e..a052e107c0b4 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -28,6 +28,7 @@
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "mach-smartq.h"
@@ -171,6 +172,6 @@ MACHINE_START(SMARTQ7, "SmartQ 7")
         .map_io         = smartq_map_io,
         .init_machine   = smartq7_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index a392869c8342..d70c0843aea2 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -35,6 +35,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/i2c-s3c2410.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -66,6 +67,7 @@ static void __init smdk6400_map_io(void)
         s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static struct platform_device *smdk6400_devices[] __initdata = {
@@ -92,6 +94,6 @@ MACHINE_START(SMDK6400, "SMDK6400")
         .map_io         = smdk6400_map_io,
         .init_machine   = smdk6400_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index ba7544e2d04d..bd3295a19ad7 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -69,6 +69,7 @@
 #include <linux/platform_data/touchscreen-s3c2410.h>
 #include <plat/keypad.h>
 #include <plat/backlight.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 #include "regs-modem.h"
@@ -634,6 +635,7 @@ static void __init smdk6410_map_io(void)
         s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 
         /* set the LCD type */
 
@@ -702,6 +704,6 @@ MACHINE_START(SMDK6410, "SMDK6410")
         .map_io         = smdk6410_map_io,
         .init_machine   = smdk6410_machine_init,
         .init_late      = s3c64xx_init_late,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
index c8174d95339b..ca960bda02fd 100644
--- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -76,7 +76,7 @@ static int s3c_usb_otgphy_exit(struct platform_device *pdev)
 
 int s5p_usb_phy_init(struct platform_device *pdev, int type)
 {
-        if (type == S5P_USB_PHY_DEVICE)
+        if (type == USB_PHY_TYPE_DEVICE)
                 return s3c_usb_otgphy_init(pdev);
 
         return -EINVAL;
@@ -84,7 +84,7 @@ int s5p_usb_phy_init(struct platform_device *pdev, int type)
 
 int s5p_usb_phy_exit(struct platform_device *pdev, int type)
 {
-        if (type == S5P_USB_PHY_DEVICE)
+        if (type == USB_PHY_TYPE_DEVICE)
                 return s3c_usb_otgphy_exit(pdev);
 
         return -EINVAL;
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index e8742cb7ddd9..5a707bdb9ea0 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -9,16 +9,16 @@ if ARCH_S5P64X0
 
 config CPU_S5P6440
         bool
-        select S5P_HRT
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
+        select SAMSUNG_HRT
         select SAMSUNG_WAKEMASK if PM
         help
           Enable S5P6440 CPU support
 
 config CPU_S5P6450
         bool
-        select S5P_HRT
+        select SAMSUNG_HRT
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
         select SAMSUNG_WAKEMASK if PM
diff --git a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
index e80ba3c69814..5e2916fb19a9 100644
--- a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
@@ -30,4 +30,4 @@
 #endif
         .endm
 
-#include <plat/debug-macro.S>
+#include <debug/samsung.S>
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index e23723a5a214..73f71a698a34 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -48,7 +48,7 @@
 #include <plat/pll.h>
 #include <plat/adc.h>
 #include <linux/platform_data/touchscreen-s3c2410.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/backlight.h>
 #include <plat/fb.h>
 #include <plat/sdhci.h>
@@ -229,7 +229,7 @@ static void __init smdk6440_map_io(void)
         s5p64x0_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void s5p6440_set_lcd_interface(void)
@@ -273,6 +273,6 @@ MACHINE_START(SMDK6440, "SMDK6440")
         .init_irq       = s5p6440_init_irq,
         .map_io         = smdk6440_map_io,
         .init_machine   = smdk6440_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5p64x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index ca10963a959e..18303e12019f 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -48,7 +48,7 @@
 #include <plat/pll.h>
 #include <plat/adc.h>
 #include <linux/platform_data/touchscreen-s3c2410.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/backlight.h>
 #include <plat/fb.h>
 #include <plat/sdhci.h>
@@ -248,7 +248,7 @@ static void __init smdk6450_map_io(void)
         s5p64x0_init_io(NULL, 0);
         s3c24xx_init_clocks(19200000);
         s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void s5p6450_set_lcd_interface(void)
@@ -292,6 +292,6 @@ MACHINE_START(SMDK6450, "SMDK6450")
         .init_irq       = s5p6450_init_irq,
         .map_io         = smdk6450_map_io,
         .init_machine   = smdk6450_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5p64x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 15170be97a74..2f456a4533ba 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -11,6 +11,7 @@ config CPU_S5PC100
         bool
         select S5P_EXT_INT
         select SAMSUNG_DMADEV
+        select SAMSUNG_HRT
         help
           Enable S5PC100 CPU support
 
diff --git a/arch/arm/mach-s5pc100/common.h b/arch/arm/mach-s5pc100/common.h
index 9fbd3ae2b401..c41f912e9e1f 100644
--- a/arch/arm/mach-s5pc100/common.h
+++ b/arch/arm/mach-s5pc100/common.h
@@ -20,18 +20,9 @@ void s5pc100_setup_clocks(void);
 
 void s5pc100_restart(char mode, const char *cmd);
 
-#ifdef CONFIG_CPU_S5PC100
-
 extern  int s5pc100_init(void);
 extern void s5pc100_map_io(void);
 extern void s5pc100_init_clocks(int xtal);
 extern void s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 
-#else
-#define s5pc100_init_clocks NULL
-#define s5pc100_init_uarts NULL
-#define s5pc100_map_io NULL
-#define s5pc100_init NULL
-#endif
-
 #endif /* __ARCH_ARM_MACH_S5PC100_COMMON_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
index 694f75937000..66cb7f16bf2a 100644
--- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
@@ -36,4 +36,4 @@
  * will be fine with us.
  */
 
-#include <plat/debug-macro.S>
+#include <debug/samsung.S>
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 185a19583898..8c880f76f274 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -51,6 +51,7 @@
 #include <linux/platform_data/touchscreen-s3c2410.h>
 #include <linux/platform_data/asoc-s3c.h>
 #include <plat/backlight.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -221,6 +222,7 @@ static void __init smdkc100_map_io(void)
         s5pc100_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs));
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdkc100_machine_init(void)
@@ -255,6 +257,6 @@ MACHINE_START(SMDKC100, "SMDKC100")
         .init_irq       = s5pc100_init_irq,
         .map_io         = smdkc100_map_io,
         .init_machine   = smdkc100_machine_init,
-        .init_time      = s3c24xx_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pc100_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
index 03c02d04c68c..6010c0310cb5 100644
--- a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
@@ -19,7 +19,6 @@
 #include <linux/mmc/card.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/regs-sdhci.h>
 #include <plat/sdhci.h>
 
 void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 92ad72f0ef98..0963283a7c5d 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -12,10 +12,10 @@ if ARCH_S5PV210
 config CPU_S5PV210
         bool
         select S5P_EXT_INT
-        select S5P_HRT
         select S5P_PM if PM
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
+        select SAMSUNG_HRT
         help
           Enable S5PV210 CPU support
 
diff --git a/arch/arm/mach-s5pv210/common.h b/arch/arm/mach-s5pv210/common.h
index 6ed2af5c7518..0a1cc0aef720 100644
--- a/arch/arm/mach-s5pv210/common.h
+++ b/arch/arm/mach-s5pv210/common.h
@@ -20,18 +20,9 @@ void s5pv210_setup_clocks(void);
 
 void s5pv210_restart(char mode, const char *cmd);
 
-#ifdef CONFIG_CPU_S5PV210
-
 extern  int s5pv210_init(void);
 extern void s5pv210_map_io(void);
 extern void s5pv210_init_clocks(int xtal);
 extern void s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 
-#else
-#define s5pv210_init_clocks NULL
-#define s5pv210_init_uarts NULL
-#define s5pv210_map_io NULL
-#define s5pv210_init NULL
-#endif
-
 #endif /* __ARCH_ARM_MACH_S5PV210_COMMON_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/debug-macro.S b/arch/arm/mach-s5pv210/include/mach/debug-macro.S
index 79e55597ab63..80c21996c943 100644
--- a/arch/arm/mach-s5pv210/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pv210/include/mach/debug-macro.S
@@ -38,4 +38,4 @@
  * will be fine with us.
  */
 
-#include <plat/debug-macro.S>
+#include <debug/samsung.S>
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 11900a8e88a3..ed2b85485b9d 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -38,7 +38,7 @@
 #include <plat/fb.h>
 #include <plat/fimc-core.h>
 #include <plat/sdhci.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -651,7 +651,7 @@ static void __init aquila_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init aquila_machine_init(void)
@@ -686,6 +686,6 @@ MACHINE_START(AQUILA, "Aquila")
         .init_irq       = s5pv210_init_irq,
         .map_io         = aquila_map_io,
         .init_machine   = aquila_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index e373de44a8b6..30b24ad84f49 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -47,7 +47,7 @@
 #include <plat/keypad.h>
 #include <plat/sdhci.h>
 #include <plat/clock.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/mfc.h>
 #include <plat/camport.h>
 
@@ -908,7 +908,7 @@ static void __init goni_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(goni_uartcfgs, ARRAY_SIZE(goni_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init goni_reserve(void)
@@ -973,7 +973,7 @@ MACHINE_START(GONI, "GONI")
         .init_irq       = s5pv210_init_irq,
         .map_io         = goni_map_io,
         .init_machine   = goni_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .reserve        = &goni_reserve,
         .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index 28bd0248a3e2..7c0ed07a78a3 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -29,7 +29,7 @@
 #include <linux/platform_data/ata-samsung_cf.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/pm.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/mfc.h>
 
 #include "common.h"
@@ -120,7 +120,7 @@ static void __init smdkc110_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init smdkc110_reserve(void)
@@ -153,7 +153,7 @@ MACHINE_START(SMDKC110, "SMDKC110")
         .init_irq       = s5pv210_init_irq,
         .map_io         = smdkc110_map_io,
         .init_machine   = smdkc110_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
         .reserve        = &smdkc110_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 3c73f36869bb..d50b6f124465 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -44,7 +44,7 @@
 #include <plat/keypad.h>
 #include <plat/pm.h>
 #include <plat/fb.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 #include <plat/backlight.h>
 #include <plat/mfc.h>
 #include <plat/clock.h>
@@ -285,7 +285,7 @@ static void __init smdkv210_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
-        s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
 }
 
 static void __init smdkv210_reserve(void)
@@ -329,7 +329,7 @@ MACHINE_START(SMDKV210, "SMDKV210")
         .init_irq       = s5pv210_init_irq,
         .map_io         = smdkv210_map_io,
         .init_machine   = smdkv210_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
         .reserve        = &smdkv210_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
index 2d4c5531819c..579afe89842a 100644
--- a/arch/arm/mach-s5pv210/mach-torbreck.c
+++ b/arch/arm/mach-s5pv210/mach-torbreck.c
@@ -26,7 +26,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 
 #include "common.h"
 
@@ -106,7 +106,7 @@ static void __init torbreck_map_io(void)
         s5pv210_init_io(NULL, 0);
         s3c24xx_init_clocks(24000000);
         s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs));
-        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
+        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
 
 static void __init torbreck_machine_init(void)
@@ -130,6 +130,6 @@ MACHINE_START(TORBRECK, "TORBRECK")
         .init_irq       = s5pv210_init_irq,
         .map_io         = torbreck_map_io,
         .init_machine   = torbreck_machine_init,
-        .init_time      = s5p_timer_init,
+        .init_time      = samsung_timer_init,
         .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
index 3e3ac05bb7b1..0512ada00522 100644
--- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
@@ -20,7 +20,6 @@
 #include <linux/mmc/card.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/regs-sdhci.h>
 #include <plat/sdhci.h>
 
 void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
diff --git a/arch/arm/mach-s5pv210/setup-usb-phy.c b/arch/arm/mach-s5pv210/setup-usb-phy.c
index 356a0900af03..b2ee5333f89c 100644
--- a/arch/arm/mach-s5pv210/setup-usb-phy.c
+++ b/arch/arm/mach-s5pv210/setup-usb-phy.c
@@ -80,7 +80,7 @@ static int s5pv210_usb_otgphy_exit(struct platform_device *pdev)
 
 int s5p_usb_phy_init(struct platform_device *pdev, int type)
 {
-        if (type == S5P_USB_PHY_DEVICE)
+        if (type == USB_PHY_TYPE_DEVICE)
                 return s5pv210_usb_otgphy_init(pdev);
 
         return -EINVAL;
@@ -88,7 +88,7 @@ int s5p_usb_phy_init(struct platform_device *pdev, int type)
 
 int s5p_usb_phy_exit(struct platform_device *pdev, int type)
 {
-        if (type == S5P_USB_PHY_DEVICE)
+        if (type == USB_PHY_TYPE_DEVICE)
                 return s5pv210_usb_otgphy_exit(pdev);
 
         return -EINVAL;
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index ca14dbdcfb22..04f9784ff0ed 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -4,7 +4,7 @@ menu "SA11x0 Implementations"
 
 config SA1100_ASSABET
         bool "Assabet"
-        select CPU_FREQ_SA1110
+        select ARM_SA1110_CPUFREQ
         help
           Say Y here if you are using the Intel(R) StrongARM(R) SA-1110
           Microprocessor Development Board (also known as the Assabet).
@@ -20,7 +20,7 @@ config ASSABET_NEPONSET
 
 config SA1100_CERF
         bool "CerfBoard"
-        select CPU_FREQ_SA1110
+        select ARM_SA1110_CPUFREQ
         help
           The Intrinsyc CerfBoard is based on the StrongARM 1110 (Discontinued).
           More information is available at:
@@ -47,7 +47,7 @@ endchoice
 
 config SA1100_COLLIE
         bool "Sharp Zaurus SL5500"
-        # FIXME: select CPU_FREQ_SA11x0
+        # FIXME: select ARM_SA11x0_CPUFREQ
         select SHARP_LOCOMO
         select SHARP_PARAM
         select SHARP_SCOOP
@@ -56,7 +56,7 @@ config SA1100_COLLIE
 
 config SA1100_H3100
         bool "Compaq iPAQ H3100"
-        select CPU_FREQ_SA1110
+        select ARM_SA1110_CPUFREQ
         select HTC_EGPIO
         help
           Say Y here if you intend to run this kernel on the Compaq iPAQ
@@ -67,7 +67,7 @@ config SA1100_H3100
 
 config SA1100_H3600
         bool "Compaq iPAQ H3600/H3700"
-        select CPU_FREQ_SA1110
+        select ARM_SA1110_CPUFREQ
         select HTC_EGPIO
         help
           Say Y here if you intend to run this kernel on the Compaq iPAQ
@@ -78,7 +78,7 @@ config SA1100_H3600
 
 config SA1100_BADGE4
         bool "HP Labs BadgePAD 4"
-        select CPU_FREQ_SA1100
+        select ARM_SA1100_CPUFREQ
         select SA1111
         help
           Say Y here if you want to build a kernel for the HP Laboratories
@@ -86,7 +86,7 @@ config SA1100_BADGE4
 
 config SA1100_JORNADA720
         bool "HP Jornada 720"
-        # FIXME: select CPU_FREQ_SA11x0
+        # FIXME: select ARM_SA11x0_CPUFREQ
         select SA1111
         help
           Say Y here if you want to build a kernel for the HP Jornada 720
@@ -105,14 +105,14 @@ config SA1100_JORNADA720_SSP
 
 config SA1100_HACKKIT
         bool "HackKit Core CPU Board"
-        select CPU_FREQ_SA1100
+        select ARM_SA1100_CPUFREQ
         help
           Say Y here to support the HackKit Core CPU Board
           <http://hackkit.eletztrick.de>;
 
 config SA1100_LART
         bool "LART"
-        select CPU_FREQ_SA1100
+        select ARM_SA1100_CPUFREQ
         help
           Say Y here if you are using the Linux Advanced Radio Terminal
           (also known as the LART).  See <http://www.lartmaker.nl/> for
@@ -120,7 +120,7 @@ config SA1100_LART
 
 config SA1100_NANOENGINE
         bool "nanoEngine"
-        select CPU_FREQ_SA1110
+        select ARM_SA1110_CPUFREQ
         select PCI
         select PCI_NANOENGINE
         help
@@ -130,7 +130,7 @@ config SA1100_NANOENGINE
 
 config SA1100_PLEB
         bool "PLEB"
-        select CPU_FREQ_SA1100
+        select ARM_SA1100_CPUFREQ
         help
           Say Y here if you are using version 1 of the Portable Linux
           Embedded Board (also known as PLEB).
@@ -139,7 +139,7 @@ config SA1100_PLEB
 
 config SA1100_SHANNON
         bool "Shannon"
-        select CPU_FREQ_SA1100
+        select ARM_SA1100_CPUFREQ
         help
           The Shannon (also known as a Tuxscreen, and also as a IS2630) was a
           limited edition webphone produced by Philips. The Shannon is a SA1100
@@ -148,7 +148,7 @@ config SA1100_SHANNON
 
 config SA1100_SIMPAD
         bool "Simpad"
-        select CPU_FREQ_SA1110
+        select ARM_SA1110_CPUFREQ
         help
           The SIEMENS webpad SIMpad is based on the StrongARM 1110. There
           are two different versions CL4 and SL4. CL4 has 32MB RAM and 16MB
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
index 1aed9e70465d..2732eef48966 100644
--- a/arch/arm/mach-sa1100/Makefile
+++ b/arch/arm/mach-sa1100/Makefile
@@ -8,9 +8,6 @@ obj-m :=
 obj-n :=
 obj-  :=
 
-obj-$(CONFIG_CPU_FREQ_SA1100)           += cpu-sa1100.o
-obj-$(CONFIG_CPU_FREQ_SA1110)           += cpu-sa1110.o
-
 # Specific board support
 obj-$(CONFIG_SA1100_ASSABET)            += assabet.o
 obj-$(CONFIG_ASSABET_NEPONSET)          += neponset.o
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c
deleted file mode 100644
index e8f4d1e19233..000000000000
--- a/arch/arm/mach-sa1100/cpu-sa1100.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * cpu-sa1100.c: clock scaling for the SA1100
- *
- * Copyright (C) 2000 2001, The Delft University of Technology
- *
- * Authors:
- * - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version
- * - Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
- *   - major rewrite for linux-2.3.99
- *   - rewritten for the more generic power management scheme in
- *     linux-2.4.5-rmk1
- *
- * This software has been developed while working on the LART
- * computing board (http://www.lartmaker.nl/), which is
- * sponsored by the Mobile Multi-media Communications
- * (http://www.mobimedia.org/) and Ubiquitous Communications
- * (http://www.ubicom.tudelft.nl/) projects.
- *
- * The authors can be reached at:
- *
- *  Erik Mouw
- *  Information and Communication Theory Group
- *  Faculty of Information Technology and Systems
- *  Delft University of Technology
- *  P.O. Box 5031
- *  2600 GA Delft
- *  The Netherlands
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- *
- * Theory of operations
- * ====================
- *
- * Clock scaling can be used to lower the power consumption of the CPU
- * core. This will give you a somewhat longer running time.
- *
- * The SA-1100 has a single register to change the core clock speed:
- *
- *   PPCR      0x90020014    PLL config
- *
- * However, the DRAM timings are closely related to the core clock
- * speed, so we need to change these, too. The used registers are:
- *
- *   MDCNFG    0xA0000000    DRAM config
- *   MDCAS0    0xA0000004    Access waveform
- *   MDCAS1    0xA0000008    Access waveform
- *   MDCAS2    0xA000000C    Access waveform
- *
- * Care must be taken to change the DRAM parameters the correct way,
- * because otherwise the DRAM becomes unusable and the kernel will
- * crash.
- *
- * The simple solution to avoid a kernel crash is to put the actual
- * clock change in ROM and jump to that code from the kernel. The main
- * disadvantage is that the ROM has to be modified, which is not
- * possible on all SA-1100 platforms. Another disadvantage is that
- * jumping to ROM makes clock switching unnecessary complicated.
- *
- * The idea behind this driver is that the memory configuration can be
- * changed while running from DRAM (even with interrupts turned on!)
- * as long as all re-configuration steps yield a valid DRAM
- * configuration. The advantages are clear: it will run on all SA-1100
- * platforms, and the code is very simple.
- *
- * If you really want to understand what is going on in
- * sa1100_update_dram_timings(), you'll have to read sections 8.2,
- * 9.5.7.3, and 10.2 from the "Intel StrongARM SA-1100 Microprocessor
- * Developers Manual" (available for free from Intel).
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/cpufreq.h>
-#include <linux/io.h>
-
-#include <asm/cputype.h>
-
-#include <mach/hardware.h>
-
-#include "generic.h"
-
-struct sa1100_dram_regs {
-        int speed;
-        u32 mdcnfg;
-        u32 mdcas0;
-        u32 mdcas1;
-        u32 mdcas2;
-};
-
-
-static struct cpufreq_driver sa1100_driver;
-
-static struct sa1100_dram_regs sa1100_dram_settings[] = {
-        /*speed,     mdcnfg,     mdcas0,     mdcas1,     mdcas2,   clock freq */
-        { 59000, 0x00dc88a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/*  59.0 MHz */
-        { 73700, 0x011490a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/*  73.7 MHz */
-        { 88500, 0x014e90a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/*  88.5 MHz */
-        {103200, 0x01889923, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 103.2 MHz */
-        {118000, 0x01c29923, 0x9999998f, 0xfffffff9, 0xffffffff},/* 118.0 MHz */
-        {132700, 0x01fb2123, 0x9999998f, 0xfffffff9, 0xffffffff},/* 132.7 MHz */
-        {147500, 0x02352123, 0x3333330f, 0xfffffff3, 0xffffffff},/* 147.5 MHz */
-        {162200, 0x026b29a3, 0x38e38e1f, 0xfff8e38e, 0xffffffff},/* 162.2 MHz */
-        {176900, 0x02a329a3, 0x71c71c1f, 0xfff1c71c, 0xffffffff},/* 176.9 MHz */
-        {191700, 0x02dd31a3, 0xe38e383f, 0xffe38e38, 0xffffffff},/* 191.7 MHz */
-        {206400, 0x03153223, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 206.4 MHz */
-        {221200, 0x034fba23, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 221.2 MHz */
-        {235900, 0x03853a23, 0xe1e1e07f, 0xe1e1e1e1, 0xffffffe1},/* 235.9 MHz */
-        {250700, 0x03bf3aa3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 250.7 MHz */
-        {265400, 0x03f7c2a3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 265.4 MHz */
-        {280200, 0x0431c2a3, 0x878780ff, 0x87878787, 0xffffff87},/* 280.2 MHz */
-        { 0, 0, 0, 0, 0 } /* last entry */
-};
-
-static void sa1100_update_dram_timings(int current_speed, int new_speed)
-{
-        struct sa1100_dram_regs *settings = sa1100_dram_settings;
-
-        /* find speed */
-        while (settings->speed != 0) {
-                if (new_speed == settings->speed)
-                        break;
-
-                settings++;
-        }
-
-        if (settings->speed == 0) {
-                panic("%s: couldn't find dram setting for speed %d\n",
-                      __func__, new_speed);
-        }
-
-        /* No risk, no fun: run with interrupts on! */
-        if (new_speed > current_speed) {
-                /* We're going FASTER, so first relax the memory
-                 * timings before changing the core frequency
-                 */
-
-                /* Half the memory access clock */
-                MDCNFG |= MDCNFG_CDB2;
-
-                /* The order of these statements IS important, keep 8
-                 * pulses!!
-                 */
-                MDCAS2 = settings->mdcas2;
-                MDCAS1 = settings->mdcas1;
-                MDCAS0 = settings->mdcas0;
-                MDCNFG = settings->mdcnfg;
-        } else {
-                /* We're going SLOWER: first decrease the core
-                 * frequency and then tighten the memory settings.
-                 */
-
-                /* Half the memory access clock */
-                MDCNFG |= MDCNFG_CDB2;
-
-                /* The order of these statements IS important, keep 8
-                 * pulses!!
-                 */
-                MDCAS0 = settings->mdcas0;
-                MDCAS1 = settings->mdcas1;
-                MDCAS2 = settings->mdcas2;
-                MDCNFG = settings->mdcnfg;
-        }
-}
-
-static int sa1100_target(struct cpufreq_policy *policy,
-                         unsigned int target_freq,
-                         unsigned int relation)
-{
-        unsigned int cur = sa11x0_getspeed(0);
-        unsigned int new_ppcr;
-        struct cpufreq_freqs freqs;
-
-        new_ppcr = sa11x0_freq_to_ppcr(target_freq);
-        switch (relation) {
-        case CPUFREQ_RELATION_L:
-                if (sa11x0_ppcr_to_freq(new_ppcr) > policy->max)
-                        new_ppcr--;
-                break;
-        case CPUFREQ_RELATION_H:
-                if ((sa11x0_ppcr_to_freq(new_ppcr) > target_freq) &&
-                    (sa11x0_ppcr_to_freq(new_ppcr - 1) >= policy->min))
-                        new_ppcr--;
-                break;
-        }
-
-        freqs.old = cur;
-        freqs.new = sa11x0_ppcr_to_freq(new_ppcr);
-        freqs.cpu = 0;
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
-        if (freqs.new > cur)
-                sa1100_update_dram_timings(cur, freqs.new);
-
-        PPCR = new_ppcr;
-
-        if (freqs.new < cur)
-                sa1100_update_dram_timings(cur, freqs.new);
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
-        return 0;
-}
-
-static int __init sa1100_cpu_init(struct cpufreq_policy *policy)
-{
-        if (policy->cpu != 0)
-                return -EINVAL;
-        policy->cur = policy->min = policy->max = sa11x0_getspeed(0);
-        policy->cpuinfo.min_freq = 59000;
-        policy->cpuinfo.max_freq = 287000;
-        policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
-        return 0;
-}
-
-static struct cpufreq_driver sa1100_driver __refdata = {
-        .flags          = CPUFREQ_STICKY,
-        .verify         = sa11x0_verify_speed,
-        .target         = sa1100_target,
-        .get            = sa11x0_getspeed,
-        .init           = sa1100_cpu_init,
-        .name           = "sa1100",
-};
-
-static int __init sa1100_dram_init(void)
-{
-        if (cpu_is_sa1100())
-                return cpufreq_register_driver(&sa1100_driver);
-        else
-                return -ENODEV;
-}
-
-arch_initcall(sa1100_dram_init);
diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c
deleted file mode 100644
index 48c45b0c92bb..000000000000
--- a/arch/arm/mach-sa1100/cpu-sa1110.c
+++ /dev/null
@@ -1,408 +0,0 @@
-/*
- *  linux/arch/arm/mach-sa1100/cpu-sa1110.c
- *
- *  Copyright (C) 2001 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Note: there are two erratas that apply to the SA1110 here:
- *  7 - SDRAM auto-power-up failure (rev A0)
- * 13 - Corruption of internal register reads/writes following
- *      SDRAM reads (rev A0, B0, B1)
- *
- * We ignore rev. A0 and B0 devices; I don't think they're worth supporting.
- *
- * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
- */
-#include <linux/cpufreq.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/moduleparam.h>
-#include <linux/types.h>
-
-#include <asm/cputype.h>
-#include <asm/mach-types.h>
-
-#include <mach/hardware.h>
-
-#include "generic.h"
-
-#undef DEBUG
-
-struct sdram_params {
-        const char name[20];
-        u_char  rows;           /* bits                          */
-        u_char  cas_latency;    /* cycles                        */
-        u_char  tck;            /* clock cycle time (ns)         */
-        u_char  trcd;           /* activate to r/w (ns)          */
-        u_char  trp;            /* precharge to activate (ns)    */
-        u_char  twr;            /* write recovery time (ns)      */
-        u_short refresh;        /* refresh time for array (us)   */
-};
-
-struct sdram_info {
-        u_int   mdcnfg;
-        u_int   mdrefr;
-        u_int   mdcas[3];
-};
-
-static struct sdram_params sdram_tbl[] __initdata = {
-        {       /* Toshiba TC59SM716 CL2 */
-                .name           = "TC59SM716-CL2",
-                .rows           = 12,
-                .tck            = 10,
-                .trcd           = 20,
-                .trp            = 20,
-                .twr            = 10,
-                .refresh        = 64000,
-                .cas_latency    = 2,
-        }, {    /* Toshiba TC59SM716 CL3 */
-                .name           = "TC59SM716-CL3",
-                .rows           = 12,
-                .tck            = 8,
-                .trcd           = 20,
-                .trp            = 20,
-                .twr            = 8,
-                .refresh        = 64000,
-                .cas_latency    = 3,
-        }, {    /* Samsung K4S641632D TC75 */
-                .name           = "K4S641632D",
-                .rows           = 14,
-                .tck            = 9,
-                .trcd           = 27,
-                .trp            = 20,
-                .twr            = 9,
-                .refresh        = 64000,
-                .cas_latency    = 3,
-        }, {    /* Samsung K4S281632B-1H */
-                .name           = "K4S281632B-1H",
-                .rows           = 12,
-                .tck            = 10,
-                .trp            = 20,
-                .twr            = 10,
-                .refresh        = 64000,
-                .cas_latency    = 3,
-        }, {    /* Samsung KM416S4030CT */
-                .name           = "KM416S4030CT",
-                .rows           = 13,
-                .tck            = 8,
-                .trcd           = 24,   /* 3 CLKs */
-                .trp            = 24,   /* 3 CLKs */
-                .twr            = 16,   /* Trdl: 2 CLKs */
-                .refresh        = 64000,
-                .cas_latency    = 3,
-        }, {    /* Winbond W982516AH75L CL3 */
-                .name           = "W982516AH75L",
-                .rows           = 16,
-                .tck            = 8,
-                .trcd           = 20,
-                .trp            = 20,
-                .twr            = 8,
-                .refresh        = 64000,
-                .cas_latency    = 3,
-        }, {    /* Micron MT48LC8M16A2TG-75 */
-                .name           = "MT48LC8M16A2TG-75",
-                .rows           = 12,
-                .tck            = 8,
-                .trcd           = 20,
-                .trp            = 20,
-                .twr            = 8,
-                .refresh        = 64000,
-                .cas_latency    = 3,
-        },
-};
-
-static struct sdram_params sdram_params;
-
-/*
- * Given a period in ns and frequency in khz, calculate the number of
- * cycles of frequency in period.  Note that we round up to the next
- * cycle, even if we are only slightly over.
- */
-static inline u_int ns_to_cycles(u_int ns, u_int khz)
-{
-        return (ns * khz + 999999) / 1000000;
-}
-
-/*
- * Create the MDCAS register bit pattern.
- */
-static inline void set_mdcas(u_int *mdcas, int delayed, u_int rcd)
-{
-        u_int shift;
-
-        rcd = 2 * rcd - 1;
-        shift = delayed + 1 + rcd;
-
-        mdcas[0]  = (1 << rcd) - 1;
-        mdcas[0] |= 0x55555555 << shift;
-        mdcas[1]  = mdcas[2] = 0x55555555 << (shift & 1);
-}
-
-static void
-sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz,
-                       struct sdram_params *sdram)
-{
-        u_int mem_khz, sd_khz, trp, twr;
-
-        mem_khz = cpu_khz / 2;
-        sd_khz = mem_khz;
-
-        /*
-         * If SDCLK would invalidate the SDRAM timings,
-         * run SDCLK at half speed.
-         *
-         * CPU steppings prior to B2 must either run the memory at
-         * half speed or use delayed read latching (errata 13).
-         */
-        if ((ns_to_cycles(sdram->tck, sd_khz) > 1) ||
-            (CPU_REVISION < CPU_SA1110_B2 && sd_khz < 62000))
-                sd_khz /= 2;
-
-        sd->mdcnfg = MDCNFG & 0x007f007f;
-
-        twr = ns_to_cycles(sdram->twr, mem_khz);
-
-        /* trp should always be >1 */
-        trp = ns_to_cycles(sdram->trp, mem_khz) - 1;
-        if (trp < 1)
-                trp = 1;
-
-        sd->mdcnfg |= trp << 8;
-        sd->mdcnfg |= trp << 24;
-        sd->mdcnfg |= sdram->cas_latency << 12;
-        sd->mdcnfg |= sdram->cas_latency << 28;
-        sd->mdcnfg |= twr << 14;
-        sd->mdcnfg |= twr << 30;
-
-        sd->mdrefr = MDREFR & 0xffbffff0;
-        sd->mdrefr |= 7;
-
-        if (sd_khz != mem_khz)
-                sd->mdrefr |= MDREFR_K1DB2;
-
-        /* initial number of '1's in MDCAS + 1 */
-        set_mdcas(sd->mdcas, sd_khz >= 62000,
-                ns_to_cycles(sdram->trcd, mem_khz));
-
-#ifdef DEBUG
-        printk(KERN_DEBUG "MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
-                sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1],
-                sd->mdcas[2]);
-#endif
-}
-
-/*
- * Set the SDRAM refresh rate.
- */
-static inline void sdram_set_refresh(u_int dri)
-{
-        MDREFR = (MDREFR & 0xffff000f) | (dri << 4);
-        (void) MDREFR;
-}
-
-/*
- * Update the refresh period.  We do this such that we always refresh
- * the SDRAMs within their permissible period.  The refresh period is
- * always a multiple of the memory clock (fixed at cpu_clock / 2).
- *
- * FIXME: we don't currently take account of burst accesses here,
- * but neither do Intels DM nor Angel.
- */
-static void
-sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram)
-{
-        u_int ns_row = (sdram->refresh * 1000) >> sdram->rows;
-        u_int dri = ns_to_cycles(ns_row, cpu_khz / 2) / 32;
-
-#ifdef DEBUG
-        mdelay(250);
-        printk(KERN_DEBUG "new dri value = %d\n", dri);
-#endif
-
-        sdram_set_refresh(dri);
-}
-
-/*
- * Ok, set the CPU frequency.
- */
-static int sa1110_target(struct cpufreq_policy *policy,
-                         unsigned int target_freq,
-                         unsigned int relation)
-{
-        struct sdram_params *sdram = &sdram_params;
-        struct cpufreq_freqs freqs;
-        struct sdram_info sd;
-        unsigned long flags;
-        unsigned int ppcr, unused;
-
-        switch (relation) {
-        case CPUFREQ_RELATION_L:
-                ppcr = sa11x0_freq_to_ppcr(target_freq);
-                if (sa11x0_ppcr_to_freq(ppcr) > policy->max)
-                        ppcr--;
-                break;
-        case CPUFREQ_RELATION_H:
-                ppcr = sa11x0_freq_to_ppcr(target_freq);
-                if (ppcr && (sa11x0_ppcr_to_freq(ppcr) > target_freq) &&
-                    (sa11x0_ppcr_to_freq(ppcr-1) >= policy->min))
-                        ppcr--;
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        freqs.old = sa11x0_getspeed(0);
-        freqs.new = sa11x0_ppcr_to_freq(ppcr);
-        freqs.cpu = 0;
-
-        sdram_calculate_timing(&sd, freqs.new, sdram);
-
-#if 0
-        /*
-         * These values are wrong according to the SA1110 documentation
-         * and errata, but they seem to work.  Need to get a storage
-         * scope on to the SDRAM signals to work out why.
-         */
-        if (policy->max < 147500) {
-                sd.mdrefr |= MDREFR_K1DB2;
-                sd.mdcas[0] = 0xaaaaaa7f;
-        } else {
-                sd.mdrefr &= ~MDREFR_K1DB2;
-                sd.mdcas[0] = 0xaaaaaa9f;
-        }
-        sd.mdcas[1] = 0xaaaaaaaa;
-        sd.mdcas[2] = 0xaaaaaaaa;
-#endif
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
-        /*
-         * The clock could be going away for some time.  Set the SDRAMs
-         * to refresh rapidly (every 64 memory clock cycles).  To get
-         * through the whole array, we need to wait 262144 mclk cycles.
-         * We wait 20ms to be safe.
-         */
-        sdram_set_refresh(2);
-        if (!irqs_disabled())
-                msleep(20);
-        else
-                mdelay(20);
-
-        /*
-         * Reprogram the DRAM timings with interrupts disabled, and
-         * ensure that we are doing this within a complete cache line.
-         * This means that we won't access SDRAM for the duration of
-         * the programming.
-         */
-        local_irq_save(flags);
-        asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-        udelay(10);
-        __asm__ __volatile__("\n\
-                b       2f                                      \n\
-                .align  5                                       \n\
-1:              str     %3, [%1, #0]            @ MDCNFG        \n\
-                str     %4, [%1, #28]           @ MDREFR        \n\
-                str     %5, [%1, #4]            @ MDCAS0        \n\
-                str     %6, [%1, #8]            @ MDCAS1        \n\
-                str     %7, [%1, #12]           @ MDCAS2        \n\
-                str     %8, [%2, #0]            @ PPCR          \n\
-                ldr     %0, [%1, #0]                            \n\
-                b       3f                                      \n\
-2:              b       1b                                      \n\
-3:              nop                                             \n\
-                nop"
-                : "=&r" (unused)
-                : "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg),
-                  "r" (sd.mdrefr), "r" (sd.mdcas[0]),
-                  "r" (sd.mdcas[1]), "r" (sd.mdcas[2]), "r" (ppcr));
-        local_irq_restore(flags);
-
-        /*
-         * Now, return the SDRAM refresh back to normal.
-         */
-        sdram_update_refresh(freqs.new, sdram);
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
-        return 0;
-}
-
-static int __init sa1110_cpu_init(struct cpufreq_policy *policy)
-{
-        if (policy->cpu != 0)
-                return -EINVAL;
-        policy->cur = policy->min = policy->max = sa11x0_getspeed(0);
-        policy->cpuinfo.min_freq = 59000;
-        policy->cpuinfo.max_freq = 287000;
-        policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
-        return 0;
-}
-
-/* sa1110_driver needs __refdata because it must remain after init registers
- * it with cpufreq_register_driver() */
-static struct cpufreq_driver sa1110_driver __refdata = {
-        .flags          = CPUFREQ_STICKY,
-        .verify         = sa11x0_verify_speed,
-        .target         = sa1110_target,
-        .get            = sa11x0_getspeed,
-        .init           = sa1110_cpu_init,
-        .name           = "sa1110",
-};
-
-static struct sdram_params *sa1110_find_sdram(const char *name)
-{
-        struct sdram_params *sdram;
-
-        for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl);
-             sdram++)
-                if (strcmp(name, sdram->name) == 0)
-                        return sdram;
-
-        return NULL;
-}
-
-static char sdram_name[16];
-
-static int __init sa1110_clk_init(void)
-{
-        struct sdram_params *sdram;
-        const char *name = sdram_name;
-
-        if (!cpu_is_sa1110())
-                return -ENODEV;
-
-        if (!name[0]) {
-                if (machine_is_assabet())
-                        name = "TC59SM716-CL3";
-                if (machine_is_pt_system3())
-                        name = "K4S641632D";
-                if (machine_is_h3100())
-                        name = "KM416S4030CT";
-                if (machine_is_jornada720())
-                        name = "K4S281632B-1H";
-                if (machine_is_nanoengine())
-                        name = "MT48LC8M16A2TG-75";
-        }
-
-        sdram = sa1110_find_sdram(name);
-        if (sdram) {
-                printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d"
-                        " twr: %d refresh: %d cas_latency: %d\n",
-                        sdram->tck, sdram->trcd, sdram->trp,
-                        sdram->twr, sdram->refresh, sdram->cas_latency);
-
-                memcpy(&sdram_params, sdram, sizeof(sdram_params));
-
-                return cpufreq_register_driver(&sa1110_driver);
-        }
-
-        return 0;
-}
-
-module_param_string(sdram, sdram_name, sizeof(sdram_name), 0);
-arch_initcall(sa1110_clk_init);
diff --git a/arch/arm/mach-sa1100/include/mach/generic.h b/arch/arm/mach-sa1100/include/mach/generic.h
new file mode 100644
index 000000000000..665542e0c9e2
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/generic.h
@@ -0,0 +1 @@
+#include "../../generic.h"
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index b63dec848195..153555724988 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -10,6 +10,7 @@
 #include <linux/sched.h>
 #include <linux/serial_8250.h>
 #include <linux/io.h>
+#include <linux/cpu.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -130,7 +131,7 @@ static void __init shark_timer_init(void)
 
 static void shark_init_early(void)
 {
-        disable_hlt();
+        cpu_idle_poll_ctrl(true);
 }
 
 MACHINE_START(SHARK, "Shark")
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 9255546e7bf6..eb3a7ff19e72 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -16,6 +16,7 @@ config ARCH_SH73A0
         select CPU_V7
         select I2C
         select SH_CLK_CPG
+        select RENESAS_INTC_IRQPIN
 
 config ARCH_R8A7740
         bool "R-Mobile A1 (R8A77400)"
@@ -31,6 +32,7 @@ config ARCH_R8A7779
         select SH_CLK_CPG
         select USB_ARCH_HAS_EHCI
         select USB_ARCH_HAS_OHCI
+        select RENESAS_INTC_IRQPIN
 
 config ARCH_EMEV2
         bool "Emma Mobile EV2"
@@ -102,6 +104,19 @@ config MACH_MARZEN
         select ARCH_REQUIRE_GPIOLIB
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
 
+config MACH_MARZEN_REFERENCE
+        bool "MARZEN board - Reference Device Tree Implementation"
+        depends on ARCH_R8A7779
+        select ARCH_REQUIRE_GPIOLIB
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
+        select USE_OF
+        ---help---
+           Use reference implementation of Marzen board support
+           which makes use of device tree at the expense
+           of not supporting a number of devices.
+
+           This is intended to aid developers
+
 config MACH_KZM9D
         bool "KZM9D board"
         depends on ARCH_EMEV2
@@ -116,6 +131,20 @@ config MACH_KZM9G
         select SND_SOC_AK4642 if SND_SIMPLE_CARD
         select USE_OF
 
+config MACH_KZM9G_REFERENCE
+        bool "KZM-A9-GT board - Reference Device Tree Implementation"
+        depends on ARCH_SH73A0
+        select ARCH_REQUIRE_GPIOLIB
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
+        select SND_SOC_AK4642 if SND_SIMPLE_CARD
+        select USE_OF
+        ---help---
+           Use reference implementation of KZM-A9-GT board support
+           which makes as greater use of device tree at the expense
+           of not supporting a number of devices.
+
+           This is intended to aid developers
+
 comment "SH-Mobile System Configuration"
 
 config CPU_HAS_INTEVT
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index e1fac57514b9..c621edfa6ead 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -14,10 +14,9 @@ obj-$(CONFIG_ARCH_EMEV2)	+= setup-emev2.o clock-emev2.o
 
 # SMP objects
 smp-y                           := platsmp.o headsmp.o
-smp-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
-smp-$(CONFIG_ARCH_SH73A0)       += smp-sh73a0.o headsmp-sh73a0.o
-smp-$(CONFIG_ARCH_R8A7779)      += smp-r8a7779.o
-smp-$(CONFIG_ARCH_EMEV2)        += smp-emev2.o
+smp-$(CONFIG_ARCH_SH73A0)       += smp-sh73a0.o headsmp-scu.o
+smp-$(CONFIG_ARCH_R8A7779)      += smp-r8a7779.o headsmp-scu.o
+smp-$(CONFIG_ARCH_EMEV2)        += smp-emev2.o headsmp-scu.o
 
 # IRQ objects
 obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o
@@ -39,9 +38,11 @@ obj-$(CONFIG_MACH_MACKEREL)	+= board-mackerel.o
 obj-$(CONFIG_MACH_KOTA2)        += board-kota2.o
 obj-$(CONFIG_MACH_BONITO)       += board-bonito.o
 obj-$(CONFIG_MACH_MARZEN)       += board-marzen.o
+obj-$(CONFIG_MACH_MARZEN_REFERENCE)     += board-marzen-reference.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA)      += board-armadillo800eva.o
 obj-$(CONFIG_MACH_KZM9D)        += board-kzm9d.o
 obj-$(CONFIG_MACH_KZM9G)        += board-kzm9g.o
+obj-$(CONFIG_MACH_KZM9G_REFERENCE)      += board-kzm9g-reference.o
 
 # Framework support
 obj-$(CONFIG_SMP)               += $(smp-y)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 8ff53a19c48c..c7540710906f 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -23,6 +23,8 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/io.h>
@@ -304,9 +306,9 @@ static int lcd_backlight_set_brightness(int brightness)
 
         if (brightness == 0) {
                 /* Reset the chip */
-                gpio_set_value(GPIO_PORT235, 0);
+                gpio_set_value(235, 0);
                 mdelay(24);
-                gpio_set_value(GPIO_PORT235, 1);
+                gpio_set_value(235, 1);
                 return 0;
         }
 
@@ -406,7 +408,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
         .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
         .tmio_ocr_mask  = MMC_VDD_27_28 | MMC_VDD_28_29,
-        .cd_gpio        = GPIO_PORT251,
+        .cd_gpio        = 251,
 };
 
 static struct resource sdhi0_resources[] = {
@@ -461,7 +463,7 @@ static struct regulator_init_data cn4_power_init_data = {
 static struct fixed_voltage_config cn4_power_info = {
         .supply_name = "CN4 SD/MMC Vdd",
         .microvolts = 3300000,
-        .gpio = GPIO_PORT114,
+        .gpio = 114,
         .enable_high = 1,
         .init_data = &cn4_power_init_data,
 };
@@ -479,10 +481,10 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
         static int power_gpio = -EINVAL;
 
         if (power_gpio < 0) {
-                int ret = gpio_request_one(GPIO_PORT114, GPIOF_OUT_INIT_LOW,
+                int ret = gpio_request_one(114, GPIOF_OUT_INIT_LOW,
                                            "sdhi1_power");
                 if (!ret)
-                        power_gpio = GPIO_PORT114;
+                        power_gpio = 114;
         }
 
         /*
@@ -493,7 +495,7 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
          * regulator driver. We have to live with the race in case the driver
          * gets unloaded and the GPIO freed between these two steps.
          */
-        gpio_set_value(GPIO_PORT114, state);
+        gpio_set_value(114, state);
 }
 
 static struct sh_mobile_sdhi_info sh_sdhi1_info = {
@@ -550,6 +552,77 @@ static struct platform_device *ag5evm_devices[] __initdata = {
         &sdhi1_device,
 };
 
+static unsigned long pin_pullup_conf[] = {
+        PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
+};
+
+static const struct pinctrl_map ag5evm_pinctrl_map[] = {
+        /* FSIA */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+                                  "fsia_mclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+                                  "fsia_sclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+                                  "fsia_data_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+                                  "fsia_data_out", "fsia"),
+        /* I2C2 & I2C3 */
+        PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.2", "pfc-sh73a0",
+                                  "i2c2_0", "i2c2"),
+        PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
+                                  "i2c3_0", "i2c3"),
+        /* IrDA */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_irda.0", "pfc-sh73a0",
+                                  "irda_0", "irda"),
+        /* KEYSC */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_in8", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out04", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out5", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out6_0", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out7_0", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out8_0", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out9_2", "keysc"),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                      "keysc_in8", pin_pullup_conf),
+        /* MMCIF */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                  "mmc0_data8_0", "mmc0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                  "mmc0_ctrl_0", "mmc0"),
+        PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                    "PORT279", pin_pullup_conf),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                      "mmc0_data8_0", pin_pullup_conf),
+        /* SCIFA2 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
+                                  "scifa2_data_0", "scifa2"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
+                                  "scifa2_ctrl_0", "scifa2"),
+        /* SDHI0 (CN15 [SD I/F]) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_wp", "sdhi0"),
+        /* SDHI1 (CN4 [WLAN I/F]) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+                                  "sdhi1_data4", "sdhi1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+                                  "sdhi1_ctrl", "sdhi1"),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+                                      "sdhi1_data4", pin_pullup_conf),
+        PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+                                    "PORT263", pin_pullup_conf),
+};
+
 static void __init ag5evm_init(void)
 {
         regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
@@ -558,96 +631,27 @@ static void __init ag5evm_init(void)
                                      ARRAY_SIZE(fixed2v8_power_consumers), 3300000);
         regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 
+        pinctrl_register_mappings(ag5evm_pinctrl_map,
+                                  ARRAY_SIZE(ag5evm_pinctrl_map));
         sh73a0_pinmux_init();
 
-        /* enable SCIFA2 */
-        gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
-        gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
-        gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
-        gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
-
-        /* enable KEYSC */
-        gpio_request(GPIO_FN_KEYIN0_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN1_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN2_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN3_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN4_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN5_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN6_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN7_PU, NULL);
-        gpio_request(GPIO_FN_KEYOUT0, NULL);
-        gpio_request(GPIO_FN_KEYOUT1, NULL);
-        gpio_request(GPIO_FN_KEYOUT2, NULL);
-        gpio_request(GPIO_FN_KEYOUT3, NULL);
-        gpio_request(GPIO_FN_KEYOUT4, NULL);
-        gpio_request(GPIO_FN_KEYOUT5, NULL);
-        gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
-        gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
-        gpio_request(GPIO_FN_KEYOUT8, NULL);
-        gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL);
-
-        /* enable I2C channel 2 and 3 */
-        gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
-        gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
-        gpio_request(GPIO_FN_PORT248_I2C_SCL3, NULL);
-        gpio_request(GPIO_FN_PORT249_I2C_SDA3, NULL);
-
         /* enable MMCIF */
-        gpio_request(GPIO_FN_MMCCLK0, NULL);
-        gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
-        gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
-        gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
-        gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
-        gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
-        gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
-        gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
-        gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
-        gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
-        gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
+        gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
 
         /* enable SMSC911X */
-        gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */
-        gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
-
-        /* FSI A */
-        gpio_request(GPIO_FN_FSIACK, NULL);
-        gpio_request(GPIO_FN_FSIAILR, NULL);
-        gpio_request(GPIO_FN_FSIAIBT, NULL);
-        gpio_request(GPIO_FN_FSIAISLD, NULL);
-        gpio_request(GPIO_FN_FSIAOSLD, NULL);
-
-        /* IrDA */
-        gpio_request(GPIO_FN_PORT241_IRDA_OUT, NULL);
-        gpio_request(GPIO_FN_PORT242_IRDA_IN,  NULL);
-        gpio_request(GPIO_FN_PORT243_IRDA_FIRSEL, NULL);
+        gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
+        gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
 
         /* LCD panel */
-        gpio_request_one(GPIO_PORT217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
+        gpio_request_one(217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
         mdelay(1);
-        gpio_set_value(GPIO_PORT217, 1);
+        gpio_set_value(217, 1);
         mdelay(100);
 
         /* LCD backlight controller */
-        gpio_request_one(GPIO_PORT235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
+        gpio_request_one(235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
         lcd_backlight_set_brightness(0);
 
-        /* enable SDHI0 on CN15 [SD I/F] */
-        gpio_request(GPIO_FN_SDHIWP0, NULL);
-        gpio_request(GPIO_FN_SDHICMD0, NULL);
-        gpio_request(GPIO_FN_SDHICLK0, NULL);
-        gpio_request(GPIO_FN_SDHID0_3, NULL);
-        gpio_request(GPIO_FN_SDHID0_2, NULL);
-        gpio_request(GPIO_FN_SDHID0_1, NULL);
-        gpio_request(GPIO_FN_SDHID0_0, NULL);
-
-        /* enable SDHI1 on CN4 [WLAN I/F] */
-        gpio_request(GPIO_FN_SDHICLK1, NULL);
-        gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
-        gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
-        gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
-        gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
-        gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
-
 #ifdef CONFIG_CACHE_L2X0
         /* Shared attribute override enable, 64K*8way */
         l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff);
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 38f1259a0daf..45f78cadec1d 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -34,6 +34,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c/tsc2007.h>
 #include <linux/io.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
@@ -273,11 +274,11 @@ static struct platform_device smc911x_device = {
 
 /*
  * The card detect pin of the top SD/MMC slot (CN7) is active low and is
- * connected to GPIO A22 of SH7372 (GPIO_PORT41).
+ * connected to GPIO A22 of SH7372 (GPIO 41).
  */
 static int slot_cn7_get_cd(struct platform_device *pdev)
 {
-        return !gpio_get_value(GPIO_PORT41);
+        return !gpio_get_value(41);
 }
 /* MERAM */
 static struct sh_mobile_meram_info meram_info = {
@@ -838,22 +839,22 @@ static struct platform_device fsi_hdmi_device = {
 static struct gpio_led ap4evb_leds[] = {
         {
                 .name                   = "led4",
-                .gpio                   = GPIO_PORT185,
+                .gpio                   = 185,
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         },
         {
                 .name                   = "led2",
-                .gpio                   = GPIO_PORT186,
+                .gpio                   = 186,
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         },
         {
                 .name                   = "led3",
-                .gpio                   = GPIO_PORT187,
+                .gpio                   = 187,
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         },
         {
                 .name                   = "led1",
-                .gpio                   = GPIO_PORT188,
+                .gpio                   = 188,
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         }
 };
@@ -1026,10 +1027,10 @@ out:
 /* TouchScreen */
 #ifdef CONFIG_AP4EVB_QHD
 # define GPIO_TSC_IRQ   GPIO_FN_IRQ28_123
-# define GPIO_TSC_PORT  GPIO_PORT123
+# define GPIO_TSC_PORT  123
 #else /* WVGA */
 # define GPIO_TSC_IRQ   GPIO_FN_IRQ7_40
-# define GPIO_TSC_PORT  GPIO_PORT40
+# define GPIO_TSC_PORT  40
 #endif
 
 #define IRQ28   evt2irq(0x3380) /* IRQ28A */
@@ -1084,6 +1085,28 @@ static struct i2c_board_info i2c1_devices[] = {
 };
 
 
+static const struct pinctrl_map ap4evb_pinctrl_map[] = {
+        /* MMCIF */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
+                                  "mmc0_data8_0", "mmc0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
+                                  "mmc0_ctrl_0", "mmc0"),
+        /* SDHI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+                                  "sdhi0_cd", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+                                  "sdhi0_wp", "sdhi0"),
+        /* SDHI1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
+                                  "sdhi1_data4", "sdhi1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
+                                  "sdhi1_ctrl", "sdhi1"),
+};
+
 #define GPIO_PORT9CR    IOMEM(0xE6051009)
 #define GPIO_PORT10CR   IOMEM(0xE605100A)
 #define USCCR1          IOMEM(0xE6058144)
@@ -1110,6 +1133,8 @@ static void __init ap4evb_init(void)
         /* External clock source */
         clk_set_rate(&sh7372_dv_clki_clk, 27000000);
 
+        pinctrl_register_mappings(ap4evb_pinctrl_map,
+                                  ARRAY_SIZE(ap4evb_pinctrl_map));
         sh7372_pinmux_init();
 
         /* enable SCIFA0 */
@@ -1121,40 +1146,10 @@ static void __init ap4evb_init(void)
         gpio_request(GPIO_FN_IRQ6_39,   NULL);
 
         /* enable Debug switch (S6) */
-        gpio_request_one(GPIO_PORT32, GPIOF_IN | GPIOF_EXPORT, NULL);
-        gpio_request_one(GPIO_PORT33, GPIOF_IN | GPIOF_EXPORT, NULL);
-        gpio_request_one(GPIO_PORT34, GPIOF_IN | GPIOF_EXPORT, NULL);
-        gpio_request_one(GPIO_PORT35, GPIOF_IN | GPIOF_EXPORT, NULL);
-
-        /* SDHI0 */
-        gpio_request(GPIO_FN_SDHICD0, NULL);
-        gpio_request(GPIO_FN_SDHIWP0, NULL);
-        gpio_request(GPIO_FN_SDHICMD0, NULL);
-        gpio_request(GPIO_FN_SDHICLK0, NULL);
-        gpio_request(GPIO_FN_SDHID0_3, NULL);
-        gpio_request(GPIO_FN_SDHID0_2, NULL);
-        gpio_request(GPIO_FN_SDHID0_1, NULL);
-        gpio_request(GPIO_FN_SDHID0_0, NULL);
-
-        /* SDHI1 */
-        gpio_request(GPIO_FN_SDHICMD1, NULL);
-        gpio_request(GPIO_FN_SDHICLK1, NULL);
-        gpio_request(GPIO_FN_SDHID1_3, NULL);
-        gpio_request(GPIO_FN_SDHID1_2, NULL);
-        gpio_request(GPIO_FN_SDHID1_1, NULL);
-        gpio_request(GPIO_FN_SDHID1_0, NULL);
-
-        /* MMCIF */
-        gpio_request(GPIO_FN_MMCD0_0, NULL);
-        gpio_request(GPIO_FN_MMCD0_1, NULL);
-        gpio_request(GPIO_FN_MMCD0_2, NULL);
-        gpio_request(GPIO_FN_MMCD0_3, NULL);
-        gpio_request(GPIO_FN_MMCD0_4, NULL);
-        gpio_request(GPIO_FN_MMCD0_5, NULL);
-        gpio_request(GPIO_FN_MMCD0_6, NULL);
-        gpio_request(GPIO_FN_MMCD0_7, NULL);
-        gpio_request(GPIO_FN_MMCCMD0, NULL);
-        gpio_request(GPIO_FN_MMCCLK0, NULL);
+        gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL);
+        gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL);
+        gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL);
+        gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL);
 
         /* USB enable */
         gpio_request(GPIO_FN_VBUS0_1,    NULL);
@@ -1172,15 +1167,15 @@ static void __init ap4evb_init(void)
         gpio_request(GPIO_FN_FSIAILR,   NULL);
         gpio_request(GPIO_FN_FSIAISLD,  NULL);
         gpio_request(GPIO_FN_FSIAOSLD,  NULL);
-        gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
+        gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
 
-        gpio_request(GPIO_PORT9, NULL);
-        gpio_request(GPIO_PORT10, NULL);
+        gpio_request(9, NULL);
+        gpio_request(10, NULL);
         gpio_direction_none(GPIO_PORT9CR);  /* FSIAOBT needs no direction */
         gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
 
         /* card detect pin for MMC slot (CN7) */
-        gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL);
+        gpio_request_one(41, GPIOF_IN, NULL);
 
         /* setup FSI2 port B (HDMI) */
         gpio_request(GPIO_FN_FSIBCK, NULL);
@@ -1268,8 +1263,8 @@ static void __init ap4evb_init(void)
         gpio_request(GPIO_FN_LCDDISP,  NULL);
         gpio_request(GPIO_FN_LCDDCK,   NULL);
 
-        gpio_request_one(GPIO_PORT189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
-        gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
+        gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
+        gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
 
         lcdc_info.clock_source                  = LCDC_CLK_BUS;
         lcdc_info.ch[0].interface_type          = RGB18;
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index f2ec0777cfbe..4dfe32262eb7 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -24,11 +24,15 @@
 #include <linux/err.h>
 #include <linux/kernel.h>
 #include <linux/input.h>
+#include <linux/platform_data/st1232_pdata.h>
 #include <linux/irq.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
+#include <linux/regulator/driver.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/regulator/fixed.h>
+#include <linux/regulator/gpio-regulator.h>
 #include <linux/regulator/machine.h>
 #include <linux/sh_eth.h>
 #include <linux/videodev2.h>
@@ -169,7 +173,7 @@ static int usbhsf_get_id(struct platform_device *pdev)
         return USBHS_GADGET;
 }
 
-static void usbhsf_power_ctrl(struct platform_device *pdev,
+static int usbhsf_power_ctrl(struct platform_device *pdev,
                               void __iomem *base, int enable)
 {
         struct usbhsf_private *priv = usbhsf_get_priv(pdev);
@@ -223,11 +227,13 @@ static void usbhsf_power_ctrl(struct platform_device *pdev,
                 clk_disable(priv->pci);         /* usb work around */
                 clk_disable(priv->usb24);       /* usb work around */
         }
+
+        return 0;
 }
 
 static int usbhsf_get_vbus(struct platform_device *pdev)
 {
-        return gpio_get_value(GPIO_PORT209);
+        return gpio_get_value(209);
 }
 
 static irqreturn_t usbhsf_interrupt(int irq, void *data)
@@ -239,7 +245,7 @@ static irqreturn_t usbhsf_interrupt(int irq, void *data)
         return IRQ_HANDLED;
 }
 
-static void usbhsf_hardware_exit(struct platform_device *pdev)
+static int usbhsf_hardware_exit(struct platform_device *pdev)
 {
         struct usbhsf_private *priv = usbhsf_get_priv(pdev);
 
@@ -264,6 +270,8 @@ static void usbhsf_hardware_exit(struct platform_device *pdev)
         priv->usbh_base = NULL;
 
         free_irq(IRQ7, pdev);
+
+        return 0;
 }
 
 static int usbhsf_hardware_init(struct platform_device *pdev)
@@ -535,10 +543,10 @@ static struct platform_device hdmi_lcdc_device = {
         { .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ }
 
 static struct gpio_keys_button gpio_buttons[] = {
-        GPIO_KEY(KEY_POWER,     GPIO_PORT99,    "SW3", .wakeup = 1),
-        GPIO_KEY(KEY_BACK,      GPIO_PORT100,   "SW4"),
-        GPIO_KEY(KEY_MENU,      GPIO_PORT97,    "SW5"),
-        GPIO_KEY(KEY_HOME,      GPIO_PORT98,    "SW6"),
+        GPIO_KEY(KEY_POWER,     99,     "SW3", .wakeup = 1),
+        GPIO_KEY(KEY_BACK,      100,    "SW4"),
+        GPIO_KEY(KEY_MENU,      97,     "SW5"),
+        GPIO_KEY(KEY_HOME,      98,     "SW6"),
 };
 
 static struct gpio_keys_platform_data gpio_key_info = {
@@ -554,15 +562,119 @@ static struct platform_device gpio_keys_device = {
         },
 };
 
-/* Fixed 3.3V regulator to be used by SDHI0, SDHI1, MMCIF */
-static struct regulator_consumer_supply fixed3v3_power_consumers[] =
-{
+/* Fixed 3.3V regulator to be used by SDHI1, MMCIF */
+static struct regulator_consumer_supply fixed3v3_power_consumers[] = {
+        REGULATOR_SUPPLY("vmmc", "sh_mmcif"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mmcif"),
+};
+
+/* Fixed 3.3V regulator to be used by SDHI0 */
+static struct regulator_consumer_supply vcc_sdhi0_consumers[] = {
         REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+};
+
+static struct regulator_init_data vcc_sdhi0_init_data = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(vcc_sdhi0_consumers),
+        .consumer_supplies      = vcc_sdhi0_consumers,
+};
+
+static struct fixed_voltage_config vcc_sdhi0_info = {
+        .supply_name = "SDHI0 Vcc",
+        .microvolts = 3300000,
+        .gpio = GPIO_PORT75,
+        .enable_high = 1,
+        .init_data = &vcc_sdhi0_init_data,
+};
+
+static struct platform_device vcc_sdhi0 = {
+        .name = "reg-fixed-voltage",
+        .id   = 1,
+        .dev  = {
+                .platform_data = &vcc_sdhi0_info,
+        },
+};
+
+/* 1.8 / 3.3V SDHI0 VccQ regulator */
+static struct regulator_consumer_supply vccq_sdhi0_consumers[] = {
         REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
+
+static struct regulator_init_data vccq_sdhi0_init_data = {
+        .constraints = {
+                .input_uV       = 3300000,
+                .min_uV         = 1800000,
+                .max_uV         = 3300000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                  REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(vccq_sdhi0_consumers),
+        .consumer_supplies      = vccq_sdhi0_consumers,
+};
+
+static struct gpio vccq_sdhi0_gpios[] = {
+        {GPIO_PORT17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" },
+};
+
+static struct gpio_regulator_state vccq_sdhi0_states[] = {
+        { .value = 3300000, .gpios = (0 << 0) },
+        { .value = 1800000, .gpios = (1 << 0) },
+};
+
+static struct gpio_regulator_config vccq_sdhi0_info = {
+        .supply_name = "vqmmc",
+
+        .enable_gpio = GPIO_PORT74,
+        .enable_high = 1,
+        .enabled_at_boot = 0,
+
+        .gpios = vccq_sdhi0_gpios,
+        .nr_gpios = ARRAY_SIZE(vccq_sdhi0_gpios),
+
+        .states = vccq_sdhi0_states,
+        .nr_states = ARRAY_SIZE(vccq_sdhi0_states),
+
+        .type = REGULATOR_VOLTAGE,
+        .init_data = &vccq_sdhi0_init_data,
+};
+
+static struct platform_device vccq_sdhi0 = {
+        .name = "gpio-regulator",
+        .id   = -1,
+        .dev  = {
+                .platform_data = &vccq_sdhi0_info,
+        },
+};
+
+/* Fixed 3.3V regulator to be used by SDHI1 */
+static struct regulator_consumer_supply vcc_sdhi1_consumers[] = {
         REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
-        REGULATOR_SUPPLY("vmmc", "sh_mmcif"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mmcif"),
+};
+
+static struct regulator_init_data vcc_sdhi1_init_data = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(vcc_sdhi1_consumers),
+        .consumer_supplies      = vcc_sdhi1_consumers,
+};
+
+static struct fixed_voltage_config vcc_sdhi1_info = {
+        .supply_name = "SDHI1 Vcc",
+        .microvolts = 3300000,
+        .gpio = GPIO_PORT16,
+        .enable_high = 1,
+        .init_data = &vcc_sdhi1_init_data,
+};
+
+static struct platform_device vcc_sdhi1 = {
+        .name = "reg-fixed-voltage",
+        .id   = 2,
+        .dev  = {
+                .platform_data = &vcc_sdhi1_info,
+        },
 };
 
 /* SDHI0 */
@@ -578,10 +690,10 @@ static struct regulator_consumer_supply fixed3v3_power_consumers[] =
 static struct sh_mobile_sdhi_info sdhi0_info = {
         .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
         .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
-        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |\
-                          MMC_CAP_NEEDS_POLL,
-        .tmio_ocr_mask  = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
-        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+                          MMC_CAP_POWER_OFF_CARD,
+        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
+        .cd_gpio        = GPIO_PORT167,
 };
 
 static struct resource sdhi0_resources[] = {
@@ -620,9 +732,11 @@ static struct platform_device sdhi0_device = {
 static struct sh_mobile_sdhi_info sdhi1_info = {
         .dma_slave_tx   = SHDMA_SLAVE_SDHI1_TX,
         .dma_slave_rx   = SHDMA_SLAVE_SDHI1_RX,
-        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
-        .tmio_ocr_mask  = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
-        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+                          MMC_CAP_POWER_OFF_CARD,
+        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
+        /* Port72 cannot generate IRQs, will be used in polling mode. */
+        .cd_gpio        = GPIO_PORT72,
 };
 
 static struct resource sdhi1_resources[] = {
@@ -656,10 +770,20 @@ static struct platform_device sdhi1_device = {
         .resource       = sdhi1_resources,
 };
 
+static const struct pinctrl_map eva_sdhi1_pinctrl_map[] = {
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
+                                  "sdhi1_data4", "sdhi1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
+                                  "sdhi1_ctrl", "sdhi1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
+                                  "sdhi1_cd", "sdhi1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
+                                  "sdhi1_wp", "sdhi1"),
+};
+
 /* MMCIF */
 static struct sh_mmcif_plat_data sh_mmcif_plat = {
         .sup_pclk       = 0,
-        .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
         .caps           = MMC_CAP_4_BIT_DATA |
                           MMC_CAP_8_BIT_DATA |
                           MMC_CAP_NONREMOVABLE,
@@ -708,9 +832,9 @@ static int mt9t111_power(struct device *dev, int mode)
                 /* video1 (= CON1 camera) expect 24MHz */
                 clk_set_rate(mclk, clk_round_rate(mclk, 24000000));
                 clk_enable(mclk);
-                gpio_set_value(GPIO_PORT158, 1);
+                gpio_set_value(158, 1);
         } else {
-                gpio_set_value(GPIO_PORT158, 0);
+                gpio_set_value(158, 0);
                 clk_disable(mclk);
         }
 
@@ -864,8 +988,8 @@ static struct platform_device fsi_hdmi_device = {
 
 /* RTC: RTC connects i2c-gpio. */
 static struct i2c_gpio_platform_data i2c_gpio_data = {
-        .sda_pin        = GPIO_PORT208,
-        .scl_pin        = GPIO_PORT91,
+        .sda_pin        = 208,
+        .scl_pin        = 91,
         .udelay         = 5, /* 100 kHz */
 };
 
@@ -878,10 +1002,15 @@ static struct platform_device i2c_gpio_device = {
 };
 
 /* I2C */
+static struct st1232_pdata st1232_i2c0_pdata = {
+        .reset_gpio = 166,
+};
+
 static struct i2c_board_info i2c0_devices[] = {
         {
                 I2C_BOARD_INFO("st1232-ts", 0x55),
                 .irq = evt2irq(0x0340),
+                .platform_data = &st1232_i2c0_pdata,
         },
         {
                 I2C_BOARD_INFO("wm8978", 0x1a),
@@ -902,6 +1031,8 @@ static struct platform_device *eva_devices[] __initdata = {
         &lcdc0_device,
         &gpio_keys_device,
         &sh_eth_device,
+        &vcc_sdhi0,
+        &vccq_sdhi0,
         &sdhi0_device,
         &sh_mmcif_device,
         &hdmi_device,
@@ -914,6 +1045,28 @@ static struct platform_device *eva_devices[] __initdata = {
         &i2c_gpio_device,
 };
 
+static const struct pinctrl_map eva_pinctrl_map[] = {
+        /* LCD0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+                                  "lcd0_data24_0", "lcd0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+                                  "lcd0_lclk_1", "lcd0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+                                  "lcd0_sync", "lcd0"),
+        /* MMCIF */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
+                                  "mmc0_data8_1", "mmc0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
+                                  "mmc0_ctrl_1", "mmc0"),
+        /* SDHI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
+                                  "sdhi0_wp", "sdhi0"),
+};
+
 static void __init eva_clock_init(void)
 {
         struct clk *system      = clk_get(NULL, "system_clk");
@@ -961,6 +1114,8 @@ static void __init eva_init(void)
         regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
                                      ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
 
+        pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map));
+
         r8a7740_pinmux_init();
         r8a7740_meram_workaround();
 
@@ -970,42 +1125,12 @@ static void __init eva_init(void)
 
         /* LCDC0 */
         gpio_request(GPIO_FN_LCDC0_SELECT,      NULL);
-        gpio_request(GPIO_FN_LCD0_D0,           NULL);
-        gpio_request(GPIO_FN_LCD0_D1,           NULL);
-        gpio_request(GPIO_FN_LCD0_D2,           NULL);
-        gpio_request(GPIO_FN_LCD0_D3,           NULL);
-        gpio_request(GPIO_FN_LCD0_D4,           NULL);
-        gpio_request(GPIO_FN_LCD0_D5,           NULL);
-        gpio_request(GPIO_FN_LCD0_D6,           NULL);
-        gpio_request(GPIO_FN_LCD0_D7,           NULL);
-        gpio_request(GPIO_FN_LCD0_D8,           NULL);
-        gpio_request(GPIO_FN_LCD0_D9,           NULL);
-        gpio_request(GPIO_FN_LCD0_D10,          NULL);
-        gpio_request(GPIO_FN_LCD0_D11,          NULL);
-        gpio_request(GPIO_FN_LCD0_D12,          NULL);
-        gpio_request(GPIO_FN_LCD0_D13,          NULL);
-        gpio_request(GPIO_FN_LCD0_D14,          NULL);
-        gpio_request(GPIO_FN_LCD0_D15,          NULL);
-        gpio_request(GPIO_FN_LCD0_D16,          NULL);
-        gpio_request(GPIO_FN_LCD0_D17,          NULL);
-        gpio_request(GPIO_FN_LCD0_D18_PORT40,   NULL);
-        gpio_request(GPIO_FN_LCD0_D19_PORT4,    NULL);
-        gpio_request(GPIO_FN_LCD0_D20_PORT3,    NULL);
-        gpio_request(GPIO_FN_LCD0_D21_PORT2,    NULL);
-        gpio_request(GPIO_FN_LCD0_D22_PORT0,    NULL);
-        gpio_request(GPIO_FN_LCD0_D23_PORT1,    NULL);
-        gpio_request(GPIO_FN_LCD0_DCK,          NULL);
-        gpio_request(GPIO_FN_LCD0_VSYN,         NULL);
-        gpio_request(GPIO_FN_LCD0_HSYN,         NULL);
-        gpio_request(GPIO_FN_LCD0_DISP,         NULL);
-        gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
-
-        gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
-        gpio_request_one(GPIO_PORT202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
+
+        gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
+        gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
 
         /* Touchscreen */
         gpio_request(GPIO_FN_IRQ10,     NULL); /* TP_INT */
-        gpio_request_one(GPIO_PORT166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
 
         /* GETHER */
         gpio_request(GPIO_FN_ET_CRS,            NULL);
@@ -1028,12 +1153,12 @@ static void __init eva_init(void)
         gpio_request(GPIO_FN_ET_RX_DV,          NULL);
         gpio_request(GPIO_FN_ET_RX_CLK,         NULL);
 
-        gpio_request_one(GPIO_PORT18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
+        gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
 
         /* USB */
-        gpio_request_one(GPIO_PORT159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */
+        gpio_request_one(159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */
 
-        if (gpio_get_value(GPIO_PORT159)) {
+        if (gpio_get_value(159)) {
                 /* USB Host */
         } else {
                 /* USB Func */
@@ -1042,47 +1167,15 @@ static void __init eva_init(void)
                  * OTOH, usbhs interrupt needs its value (HI/LOW) to decide
                  * USB connection/disconnection (usbhsf_get_vbus()).
                  * This means we needs to select GPIO_FN_IRQ7_PORT209 first,
-                 * and select GPIO_PORT209 here
+                 * and select GPIO 209 here
                  */
                 gpio_request(GPIO_FN_IRQ7_PORT209, NULL);
-                gpio_request_one(GPIO_PORT209, GPIOF_IN, NULL);
+                gpio_request_one(209, GPIOF_IN, NULL);
 
                 platform_device_register(&usbhsf_device);
                 usb = &usbhsf_device;
         }
 
-        /* SDHI0 */
-        gpio_request(GPIO_FN_SDHI0_CMD, NULL);
-        gpio_request(GPIO_FN_SDHI0_CLK, NULL);
-        gpio_request(GPIO_FN_SDHI0_D0, NULL);
-        gpio_request(GPIO_FN_SDHI0_D1, NULL);
-        gpio_request(GPIO_FN_SDHI0_D2, NULL);
-        gpio_request(GPIO_FN_SDHI0_D3, NULL);
-        gpio_request(GPIO_FN_SDHI0_WP, NULL);
-
-        gpio_request_one(GPIO_PORT17, GPIOF_OUT_INIT_LOW, NULL);  /* SDHI0_18/33_B */
-        gpio_request_one(GPIO_PORT74, GPIOF_OUT_INIT_HIGH, NULL); /* SDHI0_PON */
-        gpio_request_one(GPIO_PORT75, GPIOF_OUT_INIT_HIGH, NULL); /* SDSLOT1_PON */
-
-        /* we can use GPIO_FN_IRQ31_PORT167 here for SDHI0 CD irq */
-
-        /*
-         * MMCIF
-         *
-         * Here doesn't care SW1.4 status,
-         * since CON2 is not mounted.
-         */
-        gpio_request(GPIO_FN_MMC1_CLK_PORT103,  NULL);
-        gpio_request(GPIO_FN_MMC1_CMD_PORT104,  NULL);
-        gpio_request(GPIO_FN_MMC1_D0_PORT149,   NULL);
-        gpio_request(GPIO_FN_MMC1_D1_PORT148,   NULL);
-        gpio_request(GPIO_FN_MMC1_D2_PORT147,   NULL);
-        gpio_request(GPIO_FN_MMC1_D3_PORT146,   NULL);
-        gpio_request(GPIO_FN_MMC1_D4_PORT145,   NULL);
-        gpio_request(GPIO_FN_MMC1_D5_PORT144,   NULL);
-        gpio_request(GPIO_FN_MMC1_D6_PORT143,   NULL);
-        gpio_request(GPIO_FN_MMC1_D7_PORT142,   NULL);
-
         /* CEU0 */
         gpio_request(GPIO_FN_VIO0_D7,           NULL);
         gpio_request(GPIO_FN_VIO0_D6,           NULL);
@@ -1099,10 +1192,10 @@ static void __init eva_init(void)
         gpio_request(GPIO_FN_VIO_CKO,           NULL);
 
         /* CON1/CON15 Camera */
-        gpio_request_one(GPIO_PORT173, GPIOF_OUT_INIT_LOW, NULL);  /* STANDBY */
-        gpio_request_one(GPIO_PORT172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
+        gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL);  /* STANDBY */
+        gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
         /* see mt9t111_power() */
-        gpio_request_one(GPIO_PORT158, GPIOF_OUT_INIT_LOW, NULL);  /* CAM_PON */
+        gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL);  /* CAM_PON */
 
         /* FSI-WM8978 */
         gpio_request(GPIO_FN_FSIAIBT,           NULL);
@@ -1111,8 +1204,8 @@ static void __init eva_init(void)
         gpio_request(GPIO_FN_FSIAOSLD,          NULL);
         gpio_request(GPIO_FN_FSIAISLD_PORT5,    NULL);
 
-        gpio_request(GPIO_PORT7, NULL);
-        gpio_request(GPIO_PORT8, NULL);
+        gpio_request(7, NULL);
+        gpio_request(8, NULL);
         gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */
         gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */
 
@@ -1129,29 +1222,21 @@ static void __init eva_init(void)
          * DBGMD/LCDC0/FSIA MUX
          * DBGMD_SELECT_B should be set after setting PFC Function.
          */
-        gpio_request_one(GPIO_PORT176, GPIOF_OUT_INIT_HIGH, NULL);
+        gpio_request_one(176, GPIOF_OUT_INIT_HIGH, NULL);
 
         /*
          * We can switch CON8/CON14 by SW1.5,
          * but it needs after DBGMD_SELECT_B
          */
-        gpio_request_one(GPIO_PORT6, GPIOF_IN, NULL);
-        if (gpio_get_value(GPIO_PORT6)) {
+        gpio_request_one(6, GPIOF_IN, NULL);
+        if (gpio_get_value(6)) {
                 /* CON14 enable */
         } else {
                 /* CON8 (SDHI1) enable */
-                gpio_request(GPIO_FN_SDHI1_CLK, NULL);
-                gpio_request(GPIO_FN_SDHI1_CMD, NULL);
-                gpio_request(GPIO_FN_SDHI1_D0,  NULL);
-                gpio_request(GPIO_FN_SDHI1_D1,  NULL);
-                gpio_request(GPIO_FN_SDHI1_D2,  NULL);
-                gpio_request(GPIO_FN_SDHI1_D3,  NULL);
-                gpio_request(GPIO_FN_SDHI1_CD,  NULL);
-                gpio_request(GPIO_FN_SDHI1_WP,  NULL);
-
-                /* SDSLOT2_PON */
-                gpio_request_one(GPIO_PORT16, GPIOF_OUT_INIT_HIGH, NULL);
+                pinctrl_register_mappings(eva_sdhi1_pinctrl_map,
+                                          ARRAY_SIZE(eva_sdhi1_pinctrl_map));
 
+                platform_device_register(&vcc_sdhi1);
                 platform_device_register(&sdhi1_device);
         }
 
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index e50f86691539..70d992c540ae 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -24,6 +24,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/regulator/fixed.h>
@@ -288,6 +289,16 @@ static struct platform_device lcdc0_device = {
         },
 };
 
+static const struct pinctrl_map lcdc0_pinctrl_map[] = {
+        /* LCD0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+                                  "lcd0_data24_1", "lcd0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+                                  "lcd0_lclk_1", "lcd0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+                                  "lcd0_sync", "lcd0"),
+};
+
 /*
  * SMSC 9221
  */
@@ -392,8 +403,8 @@ static void __init bonito_init(void)
         /*
          * base board settings
          */
-        gpio_request_one(GPIO_PORT176, GPIOF_IN, NULL);
-        if (!gpio_get_value(GPIO_PORT176)) {
+        gpio_request_one(176, GPIOF_IN, NULL);
+        if (!gpio_get_value(176)) {
                 u16 bsw2;
                 u16 bsw3;
                 u16 bsw4;
@@ -430,38 +441,11 @@ static void __init bonito_init(void)
                  */
                 if (BIT_ON(bsw2, 3) &&  /* S38.1 = OFF */
                     BIT_ON(bsw2, 2)) {  /* S38.2 = OFF */
-                        gpio_request(GPIO_FN_LCDC0_SELECT,      NULL);
-                        gpio_request(GPIO_FN_LCD0_D0,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D1,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D2,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D3,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D4,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D5,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D6,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D7,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D8,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D9,           NULL);
-                        gpio_request(GPIO_FN_LCD0_D10,          NULL);
-                        gpio_request(GPIO_FN_LCD0_D11,          NULL);
-                        gpio_request(GPIO_FN_LCD0_D12,          NULL);
-                        gpio_request(GPIO_FN_LCD0_D13,          NULL);
-                        gpio_request(GPIO_FN_LCD0_D14,          NULL);
-                        gpio_request(GPIO_FN_LCD0_D15,          NULL);
-                        gpio_request(GPIO_FN_LCD0_D16,          NULL);
-                        gpio_request(GPIO_FN_LCD0_D17,          NULL);
-                        gpio_request(GPIO_FN_LCD0_D18_PORT163,  NULL);
-                        gpio_request(GPIO_FN_LCD0_D19_PORT162,  NULL);
-                        gpio_request(GPIO_FN_LCD0_D20_PORT161,  NULL);
-                        gpio_request(GPIO_FN_LCD0_D21_PORT158,  NULL);
-                        gpio_request(GPIO_FN_LCD0_D22_PORT160,  NULL);
-                        gpio_request(GPIO_FN_LCD0_D23_PORT159,  NULL);
-                        gpio_request(GPIO_FN_LCD0_DCK,          NULL);
-                        gpio_request(GPIO_FN_LCD0_VSYN,         NULL);
-                        gpio_request(GPIO_FN_LCD0_HSYN,         NULL);
-                        gpio_request(GPIO_FN_LCD0_DISP,         NULL);
-                        gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
-
-                        gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH,
+                        pinctrl_register_mappings(lcdc0_pinctrl_map,
+                                                  ARRAY_SIZE(lcdc0_pinctrl_map));
+                        gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
+
+                        gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
                                          NULL); /* LCDDON */
 
                         /* backlight on */
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index 2ccc860403ef..ef5ca0ef0cb5 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -24,6 +24,8 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/io.h>
@@ -135,17 +137,17 @@ static struct platform_device keysc_device = {
 #define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
 
 static struct gpio_keys_button gpio_buttons[] = {
-        GPIO_KEY(KEY_VOLUMEUP, GPIO_PORT56, "+"), /* S2: VOL+ [IRQ9] */
-        GPIO_KEY(KEY_VOLUMEDOWN, GPIO_PORT54, "-"), /* S3: VOL- [IRQ10] */
-        GPIO_KEY(KEY_MENU, GPIO_PORT27, "Menu"), /* S4: MENU [IRQ30] */
-        GPIO_KEY(KEY_HOMEPAGE, GPIO_PORT26, "Home"), /* S5: HOME [IRQ31] */
-        GPIO_KEY(KEY_BACK, GPIO_PORT11, "Back"), /* S6: BACK [IRQ0] */
-        GPIO_KEY(KEY_PHONE, GPIO_PORT238, "Tel"), /* S7: TEL [IRQ11] */
-        GPIO_KEY(KEY_POWER, GPIO_PORT239, "C1"), /* S8: CAM [IRQ13] */
-        GPIO_KEY(KEY_MAIL, GPIO_PORT224, "Mail"), /* S9: MAIL [IRQ3] */
-        /* Omitted button "C3?": GPIO_PORT223 - S10: CUST [IRQ8] */
-        GPIO_KEY(KEY_CAMERA, GPIO_PORT164, "C2"), /* S11: CAM_HALF [IRQ25] */
-        /* Omitted button "?": GPIO_PORT152 - S12: CAM_FULL [No IRQ] */
+        GPIO_KEY(KEY_VOLUMEUP, 56, "+"), /* S2: VOL+ [IRQ9] */
+        GPIO_KEY(KEY_VOLUMEDOWN, 54, "-"), /* S3: VOL- [IRQ10] */
+        GPIO_KEY(KEY_MENU, 27, "Menu"), /* S4: MENU [IRQ30] */
+        GPIO_KEY(KEY_HOMEPAGE, 26, "Home"), /* S5: HOME [IRQ31] */
+        GPIO_KEY(KEY_BACK, 11, "Back"), /* S6: BACK [IRQ0] */
+        GPIO_KEY(KEY_PHONE, 238, "Tel"), /* S7: TEL [IRQ11] */
+        GPIO_KEY(KEY_POWER, 239, "C1"), /* S8: CAM [IRQ13] */
+        GPIO_KEY(KEY_MAIL, 224, "Mail"), /* S9: MAIL [IRQ3] */
+        /* Omitted button "C3?": 223 - S10: CUST [IRQ8] */
+        GPIO_KEY(KEY_CAMERA, 164, "C2"), /* S11: CAM_HALF [IRQ25] */
+        /* Omitted button "?": 152 - S12: CAM_FULL [No IRQ] */
 };
 
 static struct gpio_keys_platform_data gpio_key_info = {
@@ -165,9 +167,9 @@ static struct platform_device gpio_keys_device = {
 #define GPIO_LED(n, g) { .name = n, .gpio = g }
 
 static struct gpio_led gpio_leds[] = {
-        GPIO_LED("G", GPIO_PORT20), /* PORT20 [GPO0] -> LED7 -> "G" */
-        GPIO_LED("H", GPIO_PORT21), /* PORT21 [GPO1] -> LED8 -> "H" */
-        GPIO_LED("J", GPIO_PORT22), /* PORT22 [GPO2] -> LED9 -> "J" */
+        GPIO_LED("G", 20), /* PORT20 [GPO0] -> LED7 -> "G" */
+        GPIO_LED("H", 21), /* PORT21 [GPO1] -> LED8 -> "H" */
+        GPIO_LED("J", 22), /* PORT22 [GPO2] -> LED9 -> "J" */
 };
 
 static struct gpio_led_platform_data gpio_leds_info = {
@@ -187,7 +189,7 @@ static struct platform_device gpio_leds_device = {
 static struct led_renesas_tpu_config led_renesas_tpu12_pdata = {
         .name           = "V2513",
         .pin_gpio_fn    = GPIO_FN_TPU1TO2,
-        .pin_gpio       = GPIO_PORT153,
+        .pin_gpio       = 153,
         .channel_offset = 0x90,
         .timer_bit = 2,
         .max_brightness = 1000,
@@ -215,7 +217,7 @@ static struct platform_device leds_tpu12_device = {
 static struct led_renesas_tpu_config led_renesas_tpu41_pdata = {
         .name           = "V2514",
         .pin_gpio_fn    = GPIO_FN_TPU4TO1,
-        .pin_gpio       = GPIO_PORT199,
+        .pin_gpio       = 199,
         .channel_offset = 0x50,
         .timer_bit = 1,
         .max_brightness = 1000,
@@ -243,7 +245,7 @@ static struct platform_device leds_tpu41_device = {
 static struct led_renesas_tpu_config led_renesas_tpu21_pdata = {
         .name           = "V2515",
         .pin_gpio_fn    = GPIO_FN_TPU2TO1,
-        .pin_gpio       = GPIO_PORT197,
+        .pin_gpio       = 197,
         .channel_offset = 0x50,
         .timer_bit = 1,
         .max_brightness = 1000,
@@ -271,7 +273,7 @@ static struct platform_device leds_tpu21_device = {
 static struct led_renesas_tpu_config led_renesas_tpu30_pdata = {
         .name           = "KEYLED",
         .pin_gpio_fn    = GPIO_FN_TPU3TO0,
-        .pin_gpio       = GPIO_PORT163,
+        .pin_gpio       = 163,
         .channel_offset = 0x10,
         .timer_bit = 0,
         .max_brightness = 1000,
@@ -433,6 +435,85 @@ static struct platform_device *kota2_devices[] __initdata = {
         &sdhi1_device,
 };
 
+static unsigned long pin_pullup_conf[] = {
+        PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
+};
+
+static const struct pinctrl_map kota2_pinctrl_map[] = {
+        /* KEYSC */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_in8", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out04", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out5", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out6_0", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out7_0", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                  "keysc_out8_0", "keysc"),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+                                      "keysc_in8", pin_pullup_conf),
+        /* MMCIF */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                  "mmc0_data8_0", "mmc0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                  "mmc0_ctrl_0", "mmc0"),
+        PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                    "PORT279", pin_pullup_conf),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                      "mmc0_data8_0", pin_pullup_conf),
+        /* SCIFA2 (UART2) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
+                                  "scifa2_data_0", "scifa2"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
+                                  "scifa2_ctrl_0", "scifa2"),
+        /* SCIFA4 (UART1) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+                                  "scifa4_data", "scifa4"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+                                  "scifa4_ctrl", "scifa4"),
+        /* SCIFB (BT) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
+                                  "scifb_data_0", "scifb"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
+                                  "scifb_clk_0", "scifb"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
+                                  "scifb_ctrl_0", "scifb"),
+        /* SDHI0 (microSD) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_cd", "sdhi0"),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                      "sdhi0_data4", pin_pullup_conf),
+        PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                    "PORT256", pin_pullup_conf),
+        PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                    "PORT251", pin_pullup_conf),
+        /* SDHI1 (BCM4330) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+                                  "sdhi1_data4", "sdhi1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+                                  "sdhi1_ctrl", "sdhi1"),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+                                      "sdhi1_data4", pin_pullup_conf),
+        PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+                                    "PORT263", pin_pullup_conf),
+        /* SMSC911X */
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+                                  "bsc_data_0_7", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+                                  "bsc_data_8_15", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+                                  "bsc_cs5_a", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+                                  "bsc_we0", "bsc"),
+};
+
 static void __init kota2_init(void)
 {
         regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
@@ -441,97 +522,16 @@ static void __init kota2_init(void)
                                      ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
         regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 
+        pinctrl_register_mappings(kota2_pinctrl_map,
+                                  ARRAY_SIZE(kota2_pinctrl_map));
         sh73a0_pinmux_init();
 
-        /* SCIFA2 (UART2) */
-        gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
-        gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
-        gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
-        gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
-
-        /* SCIFA4 (UART1) */
-        gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
-        gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
-        gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
-        gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
-
         /* SMSC911X */
-        gpio_request(GPIO_FN_D0_NAF0, NULL);
-        gpio_request(GPIO_FN_D1_NAF1, NULL);
-        gpio_request(GPIO_FN_D2_NAF2, NULL);
-        gpio_request(GPIO_FN_D3_NAF3, NULL);
-        gpio_request(GPIO_FN_D4_NAF4, NULL);
-        gpio_request(GPIO_FN_D5_NAF5, NULL);
-        gpio_request(GPIO_FN_D6_NAF6, NULL);
-        gpio_request(GPIO_FN_D7_NAF7, NULL);
-        gpio_request(GPIO_FN_D8_NAF8, NULL);
-        gpio_request(GPIO_FN_D9_NAF9, NULL);
-        gpio_request(GPIO_FN_D10_NAF10, NULL);
-        gpio_request(GPIO_FN_D11_NAF11, NULL);
-        gpio_request(GPIO_FN_D12_NAF12, NULL);
-        gpio_request(GPIO_FN_D13_NAF13, NULL);
-        gpio_request(GPIO_FN_D14_NAF14, NULL);
-        gpio_request(GPIO_FN_D15_NAF15, NULL);
-        gpio_request(GPIO_FN_CS5A_, NULL);
-        gpio_request(GPIO_FN_WE0__FWE, NULL);
-        gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */
-        gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
-
-        /* KEYSC */
-        gpio_request(GPIO_FN_KEYIN0_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN1_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN2_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN3_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN4_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN5_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN6_PU, NULL);
-        gpio_request(GPIO_FN_KEYIN7_PU, NULL);
-        gpio_request(GPIO_FN_KEYOUT0, NULL);
-        gpio_request(GPIO_FN_KEYOUT1, NULL);
-        gpio_request(GPIO_FN_KEYOUT2, NULL);
-        gpio_request(GPIO_FN_KEYOUT3, NULL);
-        gpio_request(GPIO_FN_KEYOUT4, NULL);
-        gpio_request(GPIO_FN_KEYOUT5, NULL);
-        gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
-        gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
-        gpio_request(GPIO_FN_KEYOUT8, NULL);
+        gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
+        gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
 
         /* MMCIF */
-        gpio_request(GPIO_FN_MMCCLK0, NULL);
-        gpio_request(GPIO_FN_MMCD0_0, NULL);
-        gpio_request(GPIO_FN_MMCD0_1, NULL);
-        gpio_request(GPIO_FN_MMCD0_2, NULL);
-        gpio_request(GPIO_FN_MMCD0_3, NULL);
-        gpio_request(GPIO_FN_MMCD0_4, NULL);
-        gpio_request(GPIO_FN_MMCD0_5, NULL);
-        gpio_request(GPIO_FN_MMCD0_6, NULL);
-        gpio_request(GPIO_FN_MMCD0_7, NULL);
-        gpio_request(GPIO_FN_MMCCMD0, NULL);
-        gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
-
-        /* SDHI0 (microSD) */
-        gpio_request(GPIO_FN_SDHICD0_PU, NULL);
-        gpio_request(GPIO_FN_SDHICMD0_PU, NULL);
-        gpio_request(GPIO_FN_SDHICLK0, NULL);
-        gpio_request(GPIO_FN_SDHID0_3_PU, NULL);
-        gpio_request(GPIO_FN_SDHID0_2_PU, NULL);
-        gpio_request(GPIO_FN_SDHID0_1_PU, NULL);
-        gpio_request(GPIO_FN_SDHID0_0_PU, NULL);
-
-        /* SCIFB (BT) */
-        gpio_request(GPIO_FN_PORT159_SCIFB_SCK, NULL);
-        gpio_request(GPIO_FN_PORT160_SCIFB_TXD, NULL);
-        gpio_request(GPIO_FN_PORT161_SCIFB_CTS_, NULL);
-        gpio_request(GPIO_FN_PORT162_SCIFB_RXD, NULL);
-        gpio_request(GPIO_FN_PORT163_SCIFB_RTS_, NULL);
-
-        /* SDHI1 (BCM4330) */
-        gpio_request(GPIO_FN_SDHICLK1, NULL);
-        gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
-        gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
-        gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
-        gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
-        gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
+        gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
 
 #ifdef CONFIG_CACHE_L2X0
         /* Early BRESP enable, Shared attribute override enable, 64K*8way */
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
new file mode 100644
index 000000000000..aefa50d385b7
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -0,0 +1,107 @@
+/*
+ * KZM-A9-GT board support - Reference Device Tree Implementation
+ *
+ * Copyright (C) 2012   Horms Solutions Ltd.
+ *
+ * Based on board-kzm9g.c
+ * Copyright (C) 2012   Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/input.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <mach/sh73a0.h>
+#include <mach/common.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+static unsigned long pin_pullup_conf[] = {
+        PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
+};
+
+static const struct pinctrl_map kzm_pinctrl_map[] = {
+        PIN_MAP_MUX_GROUP_DEFAULT("e6826000.i2c", "pfc-sh73a0",
+                                  "i2c3_1", "i2c3"),
+        /* MMCIF */
+        PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+                                  "mmc0_data8_0", "mmc0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+                                  "mmc0_ctrl_0", "mmc0"),
+        PIN_MAP_CONFIGS_PIN_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+                                    "PORT279", pin_pullup_conf),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+                                      "mmc0_data8_0", pin_pullup_conf),
+        /* SCIFA4 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+                                  "scifa4_data", "scifa4"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+                                  "scifa4_ctrl", "scifa4"),
+        /* SDHI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+                                  "sdhi0_cd", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+                                  "sdhi0_wp", "sdhi0"),
+        /* SDHI2 */
+        PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0",
+                                  "sdhi2_data4", "sdhi2"),
+        PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0",
+                                  "sdhi2_ctrl", "sdhi2"),
+};
+
+static void __init kzm_init(void)
+{
+        sh73a0_add_standard_devices_dt();
+        pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
+        sh73a0_pinmux_init();
+
+        /* enable SD */
+        gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
+        gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
+
+        gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
+
+#ifdef CONFIG_CACHE_L2X0
+        /* Early BRESP enable, Shared attribute override enable, 64K*8way */
+        l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
+#endif
+}
+
+static const char *kzm9g_boards_compat_dt[] __initdata = {
+        "renesas,kzm9g-reference",
+        NULL,
+};
+
+DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
+        .smp            = smp_ops(sh73a0_smp_ops),
+        .map_io         = sh73a0_map_io,
+        .init_early     = sh73a0_init_delay,
+        .nr_irqs        = NR_IRQS_LEGACY,
+        .init_irq       = irqchip_init,
+        .init_machine   = kzm_init,
+        .init_time      = shmobile_timer_init,
+        .dt_compat      = kzm9g_boards_compat_dt,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 7f3a6b7e7b7c..e6b775a10aad 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -30,6 +30,8 @@
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_device.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
@@ -61,8 +63,8 @@
 
 /* Dummy supplies, where voltage doesn't matter */
 static struct regulator_consumer_supply dummy_supplies[] = {
-        REGULATOR_SUPPLY("vddvario", "smsc911x"),
-        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+        REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
 };
 
 /*
@@ -81,7 +83,7 @@ static struct resource smsc9221_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = intcs_evt2irq(0x260), /* IRQ3 */
+                .start  = irq_pin(3), /* IRQ3 */
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -115,7 +117,7 @@ static struct resource usb_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = intcs_evt2irq(0x220), /* IRQ1 */
+                .start  = irq_pin(1), /* IRQ1 */
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -138,7 +140,7 @@ struct usbhs_private {
         struct renesas_usbhs_platform_info info;
 };
 
-#define IRQ15                   intcs_evt2irq(0x03e0)
+#define IRQ15                   irq_pin(15)
 #define USB_PHY_MODE            (1 << 4)
 #define USB_PHY_INT_EN          ((1 << 3) | (1 << 2))
 #define USB_PHY_ON              (1 << 1)
@@ -155,12 +157,14 @@ static int usbhs_get_vbus(struct platform_device *pdev)
         return !((1 << 7) & __raw_readw(priv->cr2));
 }
 
-static void usbhs_phy_reset(struct platform_device *pdev)
+static int usbhs_phy_reset(struct platform_device *pdev)
 {
         struct usbhs_private *priv = usbhs_get_priv(pdev);
 
         /* init phy */
         __raw_writew(0x8a0a, priv->cr2);
+
+        return 0;
 }
 
 static int usbhs_get_id(struct platform_device *pdev)
@@ -202,7 +206,7 @@ static int usbhs_hardware_init(struct platform_device *pdev)
         return 0;
 }
 
-static void usbhs_hardware_exit(struct platform_device *pdev)
+static int usbhs_hardware_exit(struct platform_device *pdev)
 {
         struct usbhs_private *priv = usbhs_get_priv(pdev);
 
@@ -210,6 +214,8 @@ static void usbhs_hardware_exit(struct platform_device *pdev)
         __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->phy);
 
         free_irq(IRQ15, pdev);
+
+        return 0;
 }
 
 static u32 usbhs_pipe_cfg[] = {
@@ -373,13 +379,64 @@ static struct platform_device mmc_device = {
         .resource       = sh_mmcif_resources,
 };
 
-/* Fixed 2.8V regulators to be used by SDHI0 and SDHI2 */
-static struct regulator_consumer_supply fixed2v8_power_consumers[] =
+/* Fixed 3.3V regulators to be used by SDHI0 */
+static struct regulator_consumer_supply vcc_sdhi0_consumers[] =
 {
         REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
+
+static struct regulator_init_data vcc_sdhi0_init_data = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(vcc_sdhi0_consumers),
+        .consumer_supplies      = vcc_sdhi0_consumers,
+};
+
+static struct fixed_voltage_config vcc_sdhi0_info = {
+        .supply_name = "SDHI0 Vcc",
+        .microvolts = 3300000,
+        .gpio = 15,
+        .enable_high = 1,
+        .init_data = &vcc_sdhi0_init_data,
+};
+
+static struct platform_device vcc_sdhi0 = {
+        .name = "reg-fixed-voltage",
+        .id   = 0,
+        .dev  = {
+                .platform_data = &vcc_sdhi0_info,
+        },
+};
+
+/* Fixed 3.3V regulators to be used by SDHI2 */
+static struct regulator_consumer_supply vcc_sdhi2_consumers[] =
+{
         REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.2"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.2"),
+};
+
+static struct regulator_init_data vcc_sdhi2_init_data = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(vcc_sdhi2_consumers),
+        .consumer_supplies      = vcc_sdhi2_consumers,
+};
+
+static struct fixed_voltage_config vcc_sdhi2_info = {
+        .supply_name = "SDHI2 Vcc",
+        .microvolts = 3300000,
+        .gpio = 14,
+        .enable_high = 1,
+        .init_data = &vcc_sdhi2_init_data,
+};
+
+static struct platform_device vcc_sdhi2 = {
+        .name = "reg-fixed-voltage",
+        .id   = 1,
+        .dev  = {
+                .platform_data = &vcc_sdhi2_info,
+        },
 };
 
 /* SDHI */
@@ -387,8 +444,8 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
         .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
         .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
-        .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
-        .tmio_ocr_mask  = MMC_VDD_27_28 | MMC_VDD_28_29,
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+                          MMC_CAP_POWER_OFF_CARD,
 };
 
 static struct resource sdhi0_resources[] = {
@@ -431,9 +488,8 @@ static struct sh_mobile_sdhi_info sdhi2_info = {
         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT |
                           TMIO_MMC_USE_GPIO_CD |
                           TMIO_MMC_WRPROTECT_DISABLE,
-        .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
-        .tmio_ocr_mask  = MMC_VDD_27_28 | MMC_VDD_28_29,
-        .cd_gpio        = GPIO_PORT13,
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_POWER_OFF_CARD,
+        .cd_gpio        = 13,
 };
 
 static struct resource sdhi2_resources[] = {
@@ -563,25 +619,25 @@ static struct i2c_board_info i2c0_devices[] = {
         },
         {
                 I2C_BOARD_INFO("ak8975", 0x0c),
-                .irq = intcs_evt2irq(0x3380), /* IRQ28 */
+                .irq = irq_pin(28), /* IRQ28 */
         },
         {
                 I2C_BOARD_INFO("adxl34x", 0x1d),
-                .irq = intcs_evt2irq(0x3340), /* IRQ26 */
+                .irq = irq_pin(26), /* IRQ26 */
         },
 };
 
 static struct i2c_board_info i2c1_devices[] = {
         {
                 I2C_BOARD_INFO("st1232-ts", 0x55),
-                .irq = intcs_evt2irq(0x300), /* IRQ8 */
+                .irq = irq_pin(8), /* IRQ8 */
         },
 };
 
 static struct i2c_board_info i2c3_devices[] = {
         {
                 I2C_BOARD_INFO("pcf8575", 0x20),
-                .irq            = intcs_evt2irq(0x3260), /* IRQ19 */
+                .irq = irq_pin(19), /* IRQ19 */
                 .platform_data = &pcf8575_pdata,
         },
 };
@@ -592,6 +648,8 @@ static struct platform_device *kzm_devices[] __initdata = {
         &usbhs_device,
         &lcdc_device,
         &mmc_device,
+        &vcc_sdhi0,
+        &vcc_sdhi2,
         &sdhi0_device,
         &sdhi2_device,
         &gpio_keys_device,
@@ -599,6 +657,64 @@ static struct platform_device *kzm_devices[] __initdata = {
         &fsi_ak4648_device,
 };
 
+static unsigned long pin_pullup_conf[] = {
+        PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
+};
+
+static const struct pinctrl_map kzm_pinctrl_map[] = {
+        /* FSIA (AK4648) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+                                  "fsia_mclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+                                  "fsia_sclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+                                  "fsia_data_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+                                  "fsia_data_out", "fsia"),
+        /* I2C3 */
+        PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
+                                  "i2c3_1", "i2c3"),
+        /* LCD */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
+                                  "lcd_data24", "lcd"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
+                                  "lcd_sync", "lcd"),
+        /* MMCIF */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                  "mmc0_data8_0", "mmc0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                  "mmc0_ctrl_0", "mmc0"),
+        PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                    "PORT279", pin_pullup_conf),
+        PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+                                      "mmc0_data8_0", pin_pullup_conf),
+        /* SCIFA4 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+                                  "scifa4_data", "scifa4"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+                                  "scifa4_ctrl", "scifa4"),
+        /* SDHI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_cd", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+                                  "sdhi0_wp", "sdhi0"),
+        /* SDHI2 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
+                                  "sdhi2_data4", "sdhi2"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
+                                  "sdhi2_ctrl", "sdhi2"),
+        /* SMSC */
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+                                  "bsc_cs4", "bsc"),
+        /* USB */
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-sh73a0",
+                                  "usb_vbus", "usb"),
+};
+
 /*
  * FIXME
  *
@@ -654,106 +770,26 @@ device_initcall(as3711_enable_lcdc_backlight);
 
 static void __init kzm_init(void)
 {
-        regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
+        regulator_register_always_on(2, "fixed-1.8V", fixed1v8_power_consumers,
                                      ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
-        regulator_register_always_on(1, "fixed-2.8V", fixed2v8_power_consumers,
-                                     ARRAY_SIZE(fixed2v8_power_consumers), 2800000);
-        regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+        regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 
-        sh73a0_pinmux_init();
-
-        /* enable SCIFA4 */
-        gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
-        gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
-        gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
-        gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
+        pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
 
-        /* CS4 for SMSC/USB */
-        gpio_request(GPIO_FN_CS4_, NULL); /* CS4 */
+        sh73a0_pinmux_init();
 
         /* SMSC */
-        gpio_request_one(GPIO_PORT224, GPIOF_IN, NULL); /* IRQ3 */
+        gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */
 
         /* LCDC */
-        gpio_request(GPIO_FN_LCDD23,    NULL);
-        gpio_request(GPIO_FN_LCDD22,    NULL);
-        gpio_request(GPIO_FN_LCDD21,    NULL);
-        gpio_request(GPIO_FN_LCDD20,    NULL);
-        gpio_request(GPIO_FN_LCDD19,    NULL);
-        gpio_request(GPIO_FN_LCDD18,    NULL);
-        gpio_request(GPIO_FN_LCDD17,    NULL);
-        gpio_request(GPIO_FN_LCDD16,    NULL);
-        gpio_request(GPIO_FN_LCDD15,    NULL);
-        gpio_request(GPIO_FN_LCDD14,    NULL);
-        gpio_request(GPIO_FN_LCDD13,    NULL);
-        gpio_request(GPIO_FN_LCDD12,    NULL);
-        gpio_request(GPIO_FN_LCDD11,    NULL);
-        gpio_request(GPIO_FN_LCDD10,    NULL);
-        gpio_request(GPIO_FN_LCDD9,     NULL);
-        gpio_request(GPIO_FN_LCDD8,     NULL);
-        gpio_request(GPIO_FN_LCDD7,     NULL);
-        gpio_request(GPIO_FN_LCDD6,     NULL);
-        gpio_request(GPIO_FN_LCDD5,     NULL);
-        gpio_request(GPIO_FN_LCDD4,     NULL);
-        gpio_request(GPIO_FN_LCDD3,     NULL);
-        gpio_request(GPIO_FN_LCDD2,     NULL);
-        gpio_request(GPIO_FN_LCDD1,     NULL);
-        gpio_request(GPIO_FN_LCDD0,     NULL);
-        gpio_request(GPIO_FN_LCDDISP,   NULL);
-        gpio_request(GPIO_FN_LCDDCK,    NULL);
-
-        gpio_request_one(GPIO_PORT222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
-        gpio_request_one(GPIO_PORT226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
+        gpio_request_one(222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
+        gpio_request_one(226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
 
         /* Touchscreen */
-        gpio_request_one(GPIO_PORT223, GPIOF_IN, NULL); /* IRQ8 */
-
-        /* enable MMCIF */
-        gpio_request(GPIO_FN_MMCCLK0,           NULL);
-        gpio_request(GPIO_FN_MMCCMD0_PU,        NULL);
-        gpio_request(GPIO_FN_MMCD0_0_PU,        NULL);
-        gpio_request(GPIO_FN_MMCD0_1_PU,        NULL);
-        gpio_request(GPIO_FN_MMCD0_2_PU,        NULL);
-        gpio_request(GPIO_FN_MMCD0_3_PU,        NULL);
-        gpio_request(GPIO_FN_MMCD0_4_PU,        NULL);
-        gpio_request(GPIO_FN_MMCD0_5_PU,        NULL);
-        gpio_request(GPIO_FN_MMCD0_6_PU,        NULL);
-        gpio_request(GPIO_FN_MMCD0_7_PU,        NULL);
+        gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
 
         /* enable SD */
-        gpio_request(GPIO_FN_SDHIWP0,           NULL);
-        gpio_request(GPIO_FN_SDHICD0,           NULL);
-        gpio_request(GPIO_FN_SDHICMD0,          NULL);
-        gpio_request(GPIO_FN_SDHICLK0,          NULL);
-        gpio_request(GPIO_FN_SDHID0_3,          NULL);
-        gpio_request(GPIO_FN_SDHID0_2,          NULL);
-        gpio_request(GPIO_FN_SDHID0_1,          NULL);
-        gpio_request(GPIO_FN_SDHID0_0,          NULL);
         gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
-        gpio_request_one(GPIO_PORT15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
-
-        /* enable Micro SD */
-        gpio_request(GPIO_FN_SDHID2_0,          NULL);
-        gpio_request(GPIO_FN_SDHID2_1,          NULL);
-        gpio_request(GPIO_FN_SDHID2_2,          NULL);
-        gpio_request(GPIO_FN_SDHID2_3,          NULL);
-        gpio_request(GPIO_FN_SDHICMD2,          NULL);
-        gpio_request(GPIO_FN_SDHICLK2,          NULL);
-        gpio_request_one(GPIO_PORT14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
-
-        /* I2C 3 */
-        gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
-        gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
-
-        /* enable FSI2 port A (ak4648) */
-        gpio_request(GPIO_FN_FSIACK,    NULL);
-        gpio_request(GPIO_FN_FSIAILR,   NULL);
-        gpio_request(GPIO_FN_FSIAIBT,   NULL);
-        gpio_request(GPIO_FN_FSIAISLD,  NULL);
-        gpio_request(GPIO_FN_FSIAOSLD,  NULL);
-
-        /* enable USB */
-        gpio_request(GPIO_FN_VBUS_0,    NULL);
 
 #ifdef CONFIG_CACHE_L2X0
         /* Early BRESP enable, Shared attribute override enable, 64K*8way */
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index db968a585ff0..2b60f2bf1fbb 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -40,6 +40,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/sh_flctl.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/pm_clock.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
@@ -363,7 +364,7 @@ static struct fb_videomode mackerel_lcdc_modes[] = {
 
 static int mackerel_set_brightness(int brightness)
 {
-        gpio_set_value(GPIO_PORT31, brightness);
+        gpio_set_value(31, brightness);
 
         return 0;
 }
@@ -596,12 +597,14 @@ static int usbhs_get_vbus(struct platform_device *pdev)
         return usbhs_is_connected(usbhs_get_priv(pdev));
 }
 
-static void usbhs_phy_reset(struct platform_device *pdev)
+static int usbhs_phy_reset(struct platform_device *pdev)
 {
         struct usbhs_private *priv = usbhs_get_priv(pdev);
 
         /* init phy */
         __raw_writew(0x8a0a, priv->usbcrcaddr);
+
+        return 0;
 }
 
 static int usbhs0_get_id(struct platform_device *pdev)
@@ -628,11 +631,13 @@ static int usbhs0_hardware_init(struct platform_device *pdev)
         return 0;
 }
 
-static void usbhs0_hardware_exit(struct platform_device *pdev)
+static int usbhs0_hardware_exit(struct platform_device *pdev)
 {
         struct usbhs_private *priv = usbhs_get_priv(pdev);
 
         cancel_delayed_work_sync(&priv->work);
+
+        return 0;
 }
 
 static struct usbhs_private usbhs0_private = {
@@ -735,7 +740,7 @@ static int usbhs1_hardware_init(struct platform_device *pdev)
         return 0;
 }
 
-static void usbhs1_hardware_exit(struct platform_device *pdev)
+static int usbhs1_hardware_exit(struct platform_device *pdev)
 {
         struct usbhs_private *priv = usbhs_get_priv(pdev);
 
@@ -743,6 +748,8 @@ static void usbhs1_hardware_exit(struct platform_device *pdev)
         __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr);
 
         free_irq(IRQ8, pdev);
+
+        return 0;
 }
 
 static int usbhs1_get_id(struct platform_device *pdev)
@@ -819,22 +826,22 @@ static struct platform_device usbhs1_device = {
 static struct gpio_led mackerel_leds[] = {
         {
                 .name           = "led0",
-                .gpio           = GPIO_PORT0,
+                .gpio           = 0,
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         },
         {
                 .name           = "led1",
-                .gpio           = GPIO_PORT1,
+                .gpio           = 1,
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         },
         {
                 .name           = "led2",
-                .gpio           = GPIO_PORT2,
+                .gpio           = 2,
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         },
         {
                 .name           = "led3",
-                .gpio           = GPIO_PORT159,
+                .gpio           = 159,
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         }
 };
@@ -964,11 +971,11 @@ static struct platform_device nand_flash_device = {
 
 /*
  * The card detect pin of the top SD/MMC slot (CN7) is active low and is
- * connected to GPIO A22 of SH7372 (GPIO_PORT41).
+ * connected to GPIO A22 of SH7372 (GPIO 41).
  */
 static int slot_cn7_get_cd(struct platform_device *pdev)
 {
-        return !gpio_get_value(GPIO_PORT41);
+        return !gpio_get_value(41);
 }
 
 /* SDHI0 */
@@ -977,7 +984,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
         .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
         .tmio_flags     = TMIO_MMC_USE_GPIO_CD,
         .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
-        .cd_gpio        = GPIO_PORT172,
+        .cd_gpio        = 172,
 };
 
 static struct resource sdhi0_resources[] = {
@@ -1060,11 +1067,11 @@ static struct platform_device sdhi1_device = {
 
 /*
  * The card detect pin of the top SD/MMC slot (CN23) is active low and is
- * connected to GPIO SCIFB_SCK of SH7372 (GPIO_PORT162).
+ * connected to GPIO SCIFB_SCK of SH7372 (162).
  */
 static int slot_cn23_get_cd(struct platform_device *pdev)
 {
-        return !gpio_get_value(GPIO_PORT162);
+        return !gpio_get_value(162);
 }
 
 /* SDHI2 */
@@ -1142,7 +1149,7 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = {
         .slave_id_rx    = SHDMA_SLAVE_MMCIF_RX,
 };
 
-static struct platform_device sh_mmcif_device = {
+static struct platform_device sh_mmcif_device __maybe_unused = {
         .name           = "sh_mmcif",
         .id             = 0,
         .dev            = {
@@ -1328,6 +1335,33 @@ static struct i2c_board_info i2c1_devices[] = {
         },
 };
 
+static const struct pinctrl_map mackerel_pinctrl_map[] = {
+        /* MMCIF */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
+                                  "mmc0_data8_0", "mmc0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
+                                  "mmc0_ctrl_0", "mmc0"),
+        /* SDHI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+                                  "sdhi0_wp", "sdhi0"),
+        /* SDHI1 */
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
+                                  "sdhi1_data4", "sdhi1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
+                                  "sdhi1_ctrl", "sdhi1"),
+#endif
+        /* SDHI2 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
+                                  "sdhi2_data4", "sdhi2"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
+                                  "sdhi2_ctrl", "sdhi2"),
+};
+
 #define GPIO_PORT9CR    IOMEM(0xE6051009)
 #define GPIO_PORT10CR   IOMEM(0xE605100A)
 #define GPIO_PORT167CR  IOMEM(0xE60520A7)
@@ -1364,6 +1398,8 @@ static void __init mackerel_init(void)
         /* External clock source */
         clk_set_rate(&sh7372_dv_clki_clk, 27000000);
 
+        pinctrl_register_mappings(mackerel_pinctrl_map,
+                                  ARRAY_SIZE(mackerel_pinctrl_map));
         sh7372_pinmux_init();
 
         /* enable SCIFA0 */
@@ -1403,9 +1439,9 @@ static void __init mackerel_init(void)
         gpio_request(GPIO_FN_LCDDCK,   NULL);
 
         /* backlight, off by default */
-        gpio_request_one(GPIO_PORT31, GPIOF_OUT_INIT_LOW, NULL);
+        gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL);
 
-        gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
+        gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
 
         /* USBHS0 */
         gpio_request(GPIO_FN_VBUS0_0, NULL);
@@ -1421,10 +1457,10 @@ static void __init mackerel_init(void)
         gpio_request(GPIO_FN_FSIAILR,   NULL);
         gpio_request(GPIO_FN_FSIAISLD,  NULL);
         gpio_request(GPIO_FN_FSIAOSLD,  NULL);
-        gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
+        gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
 
-        gpio_request(GPIO_PORT9,  NULL);
-        gpio_request(GPIO_PORT10, NULL);
+        gpio_request(9,  NULL);
+        gpio_request(10, NULL);
         gpio_direction_none(GPIO_PORT9CR);  /* FSIAOBT needs no direction */
         gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
 
@@ -1453,52 +1489,14 @@ static void __init mackerel_init(void)
         gpio_request(GPIO_FN_IRQ21,     NULL);
         irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
 
-        /* enable SDHI0 */
-        gpio_request(GPIO_FN_SDHIWP0, NULL);
-        gpio_request(GPIO_FN_SDHICMD0, NULL);
-        gpio_request(GPIO_FN_SDHICLK0, NULL);
-        gpio_request(GPIO_FN_SDHID0_3, NULL);
-        gpio_request(GPIO_FN_SDHID0_2, NULL);
-        gpio_request(GPIO_FN_SDHID0_1, NULL);
-        gpio_request(GPIO_FN_SDHID0_0, NULL);
-
         /* SDHI0 PORT172 card-detect IRQ26 */
         gpio_request(GPIO_FN_IRQ26_172, NULL);
 
-#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
-        /* enable SDHI1 */
-        gpio_request(GPIO_FN_SDHICMD1, NULL);
-        gpio_request(GPIO_FN_SDHICLK1, NULL);
-        gpio_request(GPIO_FN_SDHID1_3, NULL);
-        gpio_request(GPIO_FN_SDHID1_2, NULL);
-        gpio_request(GPIO_FN_SDHID1_1, NULL);
-        gpio_request(GPIO_FN_SDHID1_0, NULL);
-#endif
         /* card detect pin for MMC slot (CN7) */
-        gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL);
-
-        /* enable SDHI2 */
-        gpio_request(GPIO_FN_SDHICMD2, NULL);
-        gpio_request(GPIO_FN_SDHICLK2, NULL);
-        gpio_request(GPIO_FN_SDHID2_3, NULL);
-        gpio_request(GPIO_FN_SDHID2_2, NULL);
-        gpio_request(GPIO_FN_SDHID2_1, NULL);
-        gpio_request(GPIO_FN_SDHID2_0, NULL);
+        gpio_request_one(41, GPIOF_IN, NULL);
 
         /* card detect pin for microSD slot (CN23) */
-        gpio_request_one(GPIO_PORT162, GPIOF_IN, NULL);
-
-        /* MMCIF */
-        gpio_request(GPIO_FN_MMCD0_0, NULL);
-        gpio_request(GPIO_FN_MMCD0_1, NULL);
-        gpio_request(GPIO_FN_MMCD0_2, NULL);
-        gpio_request(GPIO_FN_MMCD0_3, NULL);
-        gpio_request(GPIO_FN_MMCD0_4, NULL);
-        gpio_request(GPIO_FN_MMCD0_5, NULL);
-        gpio_request(GPIO_FN_MMCD0_6, NULL);
-        gpio_request(GPIO_FN_MMCD0_7, NULL);
-        gpio_request(GPIO_FN_MMCCMD0, NULL);
-        gpio_request(GPIO_FN_MMCCLK0, NULL);
+        gpio_request_one(162, GPIOF_IN, NULL);
 
         /* FLCTL */
         gpio_request(GPIO_FN_D0_NAF0, NULL);
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
new file mode 100644
index 000000000000..480d882e42c7
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -0,0 +1,75 @@
+/*
+ * marzen board support - Reference DT implementation
+ *
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Magnus Damm
+ * Copyright (C) 2013  Simon Horman
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/pinctrl/machine.h>
+#include <mach/r8a7779.h>
+#include <mach/common.h>
+#include <mach/irqs.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+
+static const struct pinctrl_map marzen_pinctrl_map[] = {
+        /* SCIF2 (CN18: DEBUG0) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
+                                  "scif2_data_c", "scif2"),
+        /* SCIF4 (CN19: DEBUG1) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
+                                  "scif4_data", "scif4"),
+        /* SDHI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+                                  "sdhi0_cd", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+                                  "sdhi0_wp", "sdhi0"),
+        /* SMSC */
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
+                                  "intc_irq1_b", "intc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
+                                  "lbsc_ex_cs0", "lbsc"),
+};
+
+static void __init marzen_init(void)
+{
+        pinctrl_register_mappings(marzen_pinctrl_map,
+                                  ARRAY_SIZE(marzen_pinctrl_map));
+        r8a7779_pinmux_init();
+
+        r8a7779_add_standard_devices_dt();
+}
+
+static const char *marzen_boards_compat_dt[] __initdata = {
+        "renesas,marzen-reference",
+        NULL,
+};
+
+DT_MACHINE_START(MARZEN, "marzen")
+        .smp            = smp_ops(r8a7779_smp_ops),
+        .map_io         = r8a7779_map_io,
+        .init_early     = r8a7779_init_delay,
+        .nr_irqs        = NR_IRQS_LEGACY,
+        .init_irq       = r8a7779_init_irq_dt,
+        .init_machine   = marzen_init,
+        .init_time      = shmobile_timer_init,
+        .dt_compat      = marzen_boards_compat_dt,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index fec49ebc359a..2333a2d7c937 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -25,8 +25,8 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/io.h>
-#include <linux/gpio.h>
 #include <linux/dma-mapping.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
@@ -67,7 +67,7 @@ static struct resource smsc911x_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         [1] = {
-                .start          = gic_spi(28), /* IRQ 1 */
+                .start          = gic_iid(0x3c), /* IRQ 1 */
                 .flags          = IORESOURCE_IRQ,
         },
 };
@@ -97,7 +97,7 @@ static struct resource sdhi0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gic_spi(104),
+                .start  = gic_iid(0x88),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -215,7 +215,7 @@ static struct resource ehci0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gic_spi(44),
+                .start  = gic_iid(0x4c),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -239,7 +239,7 @@ static struct resource ehci1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gic_spi(45),
+                .start  = gic_iid(0x4d),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -269,7 +269,7 @@ static struct resource ohci0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gic_spi(44),
+                .start  = gic_iid(0x4c),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -293,7 +293,7 @@ static struct resource ohci1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gic_spi(45),
+                .start  = gic_iid(0x4d),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -327,6 +327,41 @@ void __init marzen_init_late(void)
                              ARRAY_SIZE(marzen_late_devices));
 }
 
+static const struct pinctrl_map marzen_pinctrl_map[] = {
+        /* HSPI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779",
+                                  "hspi0", "hspi0"),
+        /* SCIF2 (CN18: DEBUG0) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
+                                  "scif2_data_c", "scif2"),
+        /* SCIF4 (CN19: DEBUG1) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
+                                  "scif4_data", "scif4"),
+        /* SDHI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+                                  "sdhi0_data4", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+                                  "sdhi0_ctrl", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+                                  "sdhi0_cd", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+                                  "sdhi0_wp", "sdhi0"),
+        /* SMSC */
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
+                                  "intc_irq1_b", "intc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
+                                  "lbsc_ex_cs0", "lbsc"),
+        /* USB0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
+                                  "usb0", "usb0"),
+        /* USB1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
+                                  "usb1", "usb1"),
+        /* USB2 */
+        PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.1", "pfc-r8a7779",
+                                  "usb2", "usb2"),
+};
+
 static void __init marzen_init(void)
 {
         regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
@@ -334,44 +369,10 @@ static void __init marzen_init(void)
         regulator_register_fixed(1, dummy_supplies,
                                 ARRAY_SIZE(dummy_supplies));
 
+        pinctrl_register_mappings(marzen_pinctrl_map,
+                                  ARRAY_SIZE(marzen_pinctrl_map));
         r8a7779_pinmux_init();
 
-        /* SCIF2 (CN18: DEBUG0) */
-        gpio_request(GPIO_FN_TX2_C, NULL);
-        gpio_request(GPIO_FN_RX2_C, NULL);
-
-        /* SCIF4 (CN19: DEBUG1) */
-        gpio_request(GPIO_FN_TX4, NULL);
-        gpio_request(GPIO_FN_RX4, NULL);
-
-        /* LAN89218 */
-        gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
-        gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
-
-        /* SD0 (CN20) */
-        gpio_request(GPIO_FN_SD0_CLK, NULL);
-        gpio_request(GPIO_FN_SD0_CMD, NULL);
-        gpio_request(GPIO_FN_SD0_DAT0, NULL);
-        gpio_request(GPIO_FN_SD0_DAT1, NULL);
-        gpio_request(GPIO_FN_SD0_DAT2, NULL);
-        gpio_request(GPIO_FN_SD0_DAT3, NULL);
-        gpio_request(GPIO_FN_SD0_CD, NULL);
-        gpio_request(GPIO_FN_SD0_WP, NULL);
-
-        /* HSPI 0 */
-        gpio_request(GPIO_FN_HSPI_CLK0, NULL);
-        gpio_request(GPIO_FN_HSPI_CS0,  NULL);
-        gpio_request(GPIO_FN_HSPI_TX0,  NULL);
-        gpio_request(GPIO_FN_HSPI_RX0,  NULL);
-
-        /* USB (CN21) */
-        gpio_request(GPIO_FN_USB_OVC0, NULL);
-        gpio_request(GPIO_FN_USB_OVC1, NULL);
-        gpio_request(GPIO_FN_USB_OVC2, NULL);
-
-        /* USB (CN22) */
-        gpio_request(GPIO_FN_USB_PENC2, NULL);
-
         r8a7779_add_standard_devices();
         platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
 }
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 19ce885a3b43..1feb9a2286a8 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -593,29 +593,42 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mobile_ceu.1",        &mstp_clks[MSTP128]),
 
         CLKDEV_DEV_ID("sh-sci.4",               &mstp_clks[MSTP200]),
+        CLKDEV_DEV_ID("e6c80000.sci",           &mstp_clks[MSTP200]),
         CLKDEV_DEV_ID("sh-sci.3",               &mstp_clks[MSTP201]),
+        CLKDEV_DEV_ID("e6c70000.sci",           &mstp_clks[MSTP201]),
         CLKDEV_DEV_ID("sh-sci.2",               &mstp_clks[MSTP202]),
+        CLKDEV_DEV_ID("e6c60000.sci",           &mstp_clks[MSTP202]),
         CLKDEV_DEV_ID("sh-sci.1",               &mstp_clks[MSTP203]),
+        CLKDEV_DEV_ID("e6c50000.sci",           &mstp_clks[MSTP203]),
         CLKDEV_DEV_ID("sh-sci.0",               &mstp_clks[MSTP204]),
+        CLKDEV_DEV_ID("e6c40000.sci",           &mstp_clks[MSTP204]),
         CLKDEV_DEV_ID("sh-sci.8",               &mstp_clks[MSTP206]),
+        CLKDEV_DEV_ID("e6c30000.sci",           &mstp_clks[MSTP206]),
         CLKDEV_DEV_ID("sh-sci.5",               &mstp_clks[MSTP207]),
+        CLKDEV_DEV_ID("e6cb0000.sci",           &mstp_clks[MSTP207]),
         CLKDEV_DEV_ID("sh-dma-engine.3",        &mstp_clks[MSTP214]),
         CLKDEV_DEV_ID("sh-dma-engine.2",        &mstp_clks[MSTP216]),
         CLKDEV_DEV_ID("sh-dma-engine.1",        &mstp_clks[MSTP217]),
         CLKDEV_DEV_ID("sh-dma-engine.0",        &mstp_clks[MSTP218]),
         CLKDEV_DEV_ID("sh-sci.7",               &mstp_clks[MSTP222]),
+        CLKDEV_DEV_ID("e6cd0000.sci",           &mstp_clks[MSTP222]),
         CLKDEV_DEV_ID("sh-sci.6",               &mstp_clks[MSTP230]),
+        CLKDEV_DEV_ID("e6cc0000.sci",           &mstp_clks[MSTP230]),
 
         CLKDEV_DEV_ID("sh_cmt.10",              &mstp_clks[MSTP329]),
         CLKDEV_DEV_ID("sh_fsi2",                &mstp_clks[MSTP328]),
         CLKDEV_DEV_ID("i2c-sh_mobile.1",        &mstp_clks[MSTP323]),
         CLKDEV_DEV_ID("renesas_usbhs",          &mstp_clks[MSTP320]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.0",       &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("e6850000.sdhi",          &mstp_clks[MSTP314]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.1",       &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("e6860000.sdhi",          &mstp_clks[MSTP313]),
         CLKDEV_DEV_ID("sh_mmcif",               &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("e6bd0000.mmcif",         &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("sh-eth",                 &mstp_clks[MSTP309]),
 
         CLKDEV_DEV_ID("sh_mobile_sdhi.2",       &mstp_clks[MSTP415]),
+        CLKDEV_DEV_ID("e6870000.sdhi",          &mstp_clks[MSTP415]),
 
         /* ICK */
         CLKDEV_ICK_ID("host",   "renesas_usbhs",        &mstp_clks[MSTP416]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 1db36537255c..d9edeaf66007 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -87,7 +87,8 @@ static struct clk div4_clks[DIV4_NR] = {
 };
 
 enum { MSTP323, MSTP322, MSTP321, MSTP320,
-        MSTP101, MSTP100,
+        MSTP115,
+        MSTP103, MSTP101, MSTP100,
         MSTP030,
         MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
         MSTP016, MSTP015, MSTP014,
@@ -99,6 +100,8 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
         [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
         [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
+        [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), /* SATA */
+        [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR1,  3, 0), /* DU */
         [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  1, 0), /* USB2 */
         [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1,  0, 0), /* USB0/1 */
         [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */
@@ -156,6 +159,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
 
         /* MSTP32 clocks */
+        CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
+        CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
         CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
         CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
         CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
@@ -180,6 +185,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
+        CLKDEV_DEV_ID("rcar-du.0", &mstp_clks[MSTP103]), /* DU */
 };
 
 void __init r8a7779_clock_init(void)
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index afa5423a0f93..71843dd39e16 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -265,12 +265,12 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
 
 static struct clk div4_clks[DIV4_NR] = {
         [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
-        [DIV4_ZG] = DIV4(FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
+        [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
         [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
         [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
         [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
         [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
-        [DIV4_Z] = DIV4(FRQCRB, 24, 0x97f, 0),
+        [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0),
         [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0),
         [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0),
         [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),
@@ -581,10 +581,13 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */
         CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
+        CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
+        CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
         CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
+        CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */
         CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */
         CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */
         CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */
diff --git a/arch/arm/mach-shmobile/cpuidle.c b/arch/arm/mach-shmobile/cpuidle.c
index 9e050268cde4..0afeb5c7061c 100644
--- a/arch/arm/mach-shmobile/cpuidle.c
+++ b/arch/arm/mach-shmobile/cpuidle.c
@@ -16,39 +16,22 @@
 #include <asm/cpuidle.h>
 #include <asm/io.h>
 
-int shmobile_enter_wfi(struct cpuidle_device *dev, struct cpuidle_driver *drv,
-                       int index)
-{
-        cpu_do_idle();
-        return 0;
-}
-
-static struct cpuidle_device shmobile_cpuidle_dev;
 static struct cpuidle_driver shmobile_cpuidle_default_driver = {
         .name                   = "shmobile_cpuidle",
         .owner                  = THIS_MODULE,
-        .en_core_tk_irqen       = 1,
         .states[0]              = ARM_CPUIDLE_WFI_STATE,
-        .states[0].enter        = shmobile_enter_wfi,
         .safe_state_index       = 0, /* C1 */
         .state_count            = 1,
 };
 
 static struct cpuidle_driver *cpuidle_drv = &shmobile_cpuidle_default_driver;
 
-void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv)
+void __init shmobile_cpuidle_set_driver(struct cpuidle_driver *drv)
 {
         cpuidle_drv = drv;
 }
 
-int shmobile_cpuidle_init(void)
+int __init shmobile_cpuidle_init(void)
 {
-        struct cpuidle_device *dev = &shmobile_cpuidle_dev;
-
-        cpuidle_register_driver(cpuidle_drv);
-
-        dev->state_count = cpuidle_drv->state_count;
-        cpuidle_register_device(dev);
-
-        return 0;
+        return cpuidle_register(cpuidle_drv, NULL);
 }
diff --git a/arch/arm/mach-shmobile/headsmp-sh73a0.S b/arch/arm/mach-shmobile/headsmp-scu.S
index bec4c0d9b713..7d113f898e7f 100644
--- a/arch/arm/mach-shmobile/headsmp-sh73a0.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -1,5 +1,5 @@
 /*
- * SMP support for SoC sh73a0
+ * Shared SCU setup for mach-shmobile
  *
  * Copyright (C) 2012 Bastian Hecht
  *
@@ -35,11 +35,12 @@
  * the physical address as the MMU is still turned off.
  */
         .align  12
-ENTRY(sh73a0_secondary_vector)
+ENTRY(shmobile_secondary_vector_scu)
         mrc     p15, 0, r0, c0, c0, 5   @ read MIPDR
         and     r0, r0, #3              @ mask out cpu ID
         lsl     r0, r0, #3              @ we will shift by cpu_id * 8 bits
-        mov     r1, #0xf0000000         @ SCU base address
+        ldr     r1, 2f
+        ldr     r1, [r1]                @ SCU base address
         ldr     r2, [r1, #8]            @ SCU Power Status Register
         mov     r3, #3
         bic     r2, r2, r3, lsl r0      @ Clear bits of our CPU (Run Mode)
@@ -47,4 +48,10 @@ ENTRY(sh73a0_secondary_vector)
 
         ldr     pc, 1f
 1:      .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
-ENDPROC(sh73a0_secondary_vector)
+2:      .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET
+ENDPROC(shmobile_secondary_vector_scu)
+
+        .text
+        .globl  shmobile_scu_base
+shmobile_scu_base:
+        .space  4
diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c
deleted file mode 100644
index a1524e3367b0..000000000000
--- a/arch/arm/mach-shmobile/hotplug.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * SMP support for R-Mobile / SH-Mobile
- *
- * Copyright (C) 2010  Magnus Damm
- *
- * Based on realview, Copyright (C) 2002 ARM Ltd, All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-#include <linux/cpumask.h>
-#include <linux/delay.h>
-#include <linux/of.h>
-#include <mach/common.h>
-#include <mach/r8a7779.h>
-#include <mach/emev2.h>
-#include <asm/cacheflush.h>
-#include <asm/mach-types.h>
-
-static cpumask_t dead_cpus;
-
-void shmobile_cpu_die(unsigned int cpu)
-{
-        /* hardware shutdown code running on the CPU that is being offlined */
-        flush_cache_all();
-        dsb();
-
-        /* notify platform_cpu_kill() that hardware shutdown is finished */
-        cpumask_set_cpu(cpu, &dead_cpus);
-
-        /* wait for SoC code in platform_cpu_kill() to shut off CPU core
-         * power. CPU bring up starts from the reset vector.
-         */
-        while (1) {
-                /*
-                 * here's the WFI
-                 */
-                asm(".word      0xe320f003\n"
-                    :
-                    :
-                    : "memory", "cc");
-        }
-}
-
-int shmobile_cpu_disable(unsigned int cpu)
-{
-        cpumask_clear_cpu(cpu, &dead_cpus);
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
-
-int shmobile_cpu_disable_any(unsigned int cpu)
-{
-        cpumask_clear_cpu(cpu, &dead_cpus);
-        return 0;
-}
-
-int shmobile_cpu_is_dead(unsigned int cpu)
-{
-        return cpumask_test_cpu(cpu, &dead_cpus);
-}
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index e48606d8a2be..1fef737a4c1a 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -8,14 +8,12 @@ extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
 struct twd_local_timer;
 extern void shmobile_setup_console(void);
 extern void shmobile_secondary_vector(void);
+extern void shmobile_secondary_vector_scu(void);
 struct clk;
 extern int shmobile_clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
 extern struct platform_suspend_ops shmobile_suspend_ops;
 struct cpuidle_driver;
-struct cpuidle_device;
-extern int shmobile_enter_wfi(struct cpuidle_device *dev,
-                              struct cpuidle_driver *drv, int index);
 extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
 
 extern void sh7372_init_irq(void);
@@ -33,23 +31,23 @@ extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
 extern struct clk sh7372_extal1_clk;
 extern struct clk sh7372_extal2_clk;
 
+extern void sh73a0_init_delay(void);
 extern void sh73a0_init_irq(void);
 extern void sh73a0_init_irq_dt(void);
 extern void sh73a0_map_io(void);
 extern void sh73a0_earlytimer_init(void);
 extern void sh73a0_add_early_devices(void);
-extern void sh73a0_add_early_devices_dt(void);
 extern void sh73a0_add_standard_devices(void);
 extern void sh73a0_add_standard_devices_dt(void);
 extern void sh73a0_clock_init(void);
 extern void sh73a0_pinmux_init(void);
 extern void sh73a0_pm_init(void);
-extern void sh73a0_secondary_vector(void);
 extern struct clk sh73a0_extal1_clk;
 extern struct clk sh73a0_extal2_clk;
 extern struct clk sh73a0_extcki_clk;
 extern struct clk sh73a0_extalr_clk;
 
+extern void r8a7740_meram_workaround(void);
 extern void r8a7740_init_irq(void);
 extern void r8a7740_map_io(void);
 extern void r8a7740_add_early_devices(void);
@@ -58,16 +56,18 @@ extern void r8a7740_clock_init(u8 md_ck);
 extern void r8a7740_pinmux_init(void);
 extern void r8a7740_pm_init(void);
 
+extern void r8a7779_init_delay(void);
 extern void r8a7779_init_irq(void);
+extern void r8a7779_init_irq_extpin(int irlm);
+extern void r8a7779_init_irq_dt(void);
 extern void r8a7779_map_io(void);
 extern void r8a7779_earlytimer_init(void);
 extern void r8a7779_add_early_devices(void);
 extern void r8a7779_add_standard_devices(void);
+extern void r8a7779_add_standard_devices_dt(void);
 extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
-extern void r8a7740_meram_workaround(void);
-
 extern void r8a7779_register_twd(void);
 
 #ifdef CONFIG_SUSPEND
@@ -82,16 +82,7 @@ int shmobile_cpuidle_init(void);
 static inline int shmobile_cpuidle_init(void) { return 0; }
 #endif
 
-extern void shmobile_cpu_die(unsigned int cpu);
-extern int shmobile_cpu_disable(unsigned int cpu);
-extern int shmobile_cpu_disable_any(unsigned int cpu);
-
-#ifdef CONFIG_HOTPLUG_CPU
-extern int shmobile_cpu_is_dead(unsigned int cpu);
-#else
-static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; }
-#endif
-
+extern void __iomem *shmobile_scu_base;
 extern void shmobile_smp_init_cpus(unsigned int ncores);
 
 static inline void __init shmobile_init_late(void)
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index 06a5da3c3050..b2074e2acb15 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -5,10 +5,15 @@
 
 /* GIC */
 #define gic_spi(nr)             ((nr) + 32)
+#define gic_iid(nr)             (nr) /* ICCIAR / interrupt ID */
 
 /* INTCS */
 #define INTCS_VECT_BASE         0x3400
 #define INTCS_VECT(n, vect)     INTC_VECT((n), INTCS_VECT_BASE + (vect))
 #define intcs_evt2irq(evt)      evt2irq(INTCS_VECT_BASE + (evt))
 
+/* External IRQ pins */
+#define IRQPIN_BASE             2000
+#define irq_pin(nr)             ((nr) + IRQPIN_BASE)
+
 #endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 59d252f4cf97..c2583610ad36 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -241,48 +241,9 @@ enum {
 
         /* LCD0 */
         GPIO_FN_LCDC0_SELECT,
-        GPIO_FN_LCD0_D0,        GPIO_FN_LCD0_D1,        GPIO_FN_LCD0_D2,
-        GPIO_FN_LCD0_D3,        GPIO_FN_LCD0_D4,        GPIO_FN_LCD0_D5,
-        GPIO_FN_LCD0_D6,        GPIO_FN_LCD0_D7,        GPIO_FN_LCD0_D8,
-        GPIO_FN_LCD0_D9,        GPIO_FN_LCD0_D10,       GPIO_FN_LCD0_D11,
-        GPIO_FN_LCD0_D12,       GPIO_FN_LCD0_D13,       GPIO_FN_LCD0_D14,
-        GPIO_FN_LCD0_D15,       GPIO_FN_LCD0_D16,       GPIO_FN_LCD0_D17,
-        GPIO_FN_LCD0_DON,       GPIO_FN_LCD0_VCPWC,     GPIO_FN_LCD0_VEPWC,
-
-        GPIO_FN_LCD0_DCK,       GPIO_FN_LCD0_VSYN, /* for RGB */
-        GPIO_FN_LCD0_HSYN,      GPIO_FN_LCD0_DISP, /* for RGB */
-
-        GPIO_FN_LCD0_WR,        GPIO_FN_LCD0_RD, /* for SYS */
-        GPIO_FN_LCD0_CS,        GPIO_FN_LCD0_RS, /* for SYS */
-
-        GPIO_FN_LCD0_D18_PORT163,       GPIO_FN_LCD0_D19_PORT162,
-        GPIO_FN_LCD0_D20_PORT161,       GPIO_FN_LCD0_D21_PORT158,
-        GPIO_FN_LCD0_D22_PORT160,       GPIO_FN_LCD0_D23_PORT159,
-        GPIO_FN_LCD0_LCLK_PORT165,       /* MSEL5CR_6_1 */
-
-        GPIO_FN_LCD0_D18_PORT40,        GPIO_FN_LCD0_D19_PORT4,
-        GPIO_FN_LCD0_D20_PORT3,         GPIO_FN_LCD0_D21_PORT2,
-        GPIO_FN_LCD0_D22_PORT0,         GPIO_FN_LCD0_D23_PORT1,
-        GPIO_FN_LCD0_LCLK_PORT102,      /* MSEL5CR_6_0 */
 
         /* LCD1 */
         GPIO_FN_LCDC1_SELECT,
-        GPIO_FN_LCD1_D0,        GPIO_FN_LCD1_D1,        GPIO_FN_LCD1_D2,
-        GPIO_FN_LCD1_D3,        GPIO_FN_LCD1_D4,        GPIO_FN_LCD1_D5,
-        GPIO_FN_LCD1_D6,        GPIO_FN_LCD1_D7,        GPIO_FN_LCD1_D8,
-        GPIO_FN_LCD1_D9,        GPIO_FN_LCD1_D10,       GPIO_FN_LCD1_D11,
-        GPIO_FN_LCD1_D12,       GPIO_FN_LCD1_D13,       GPIO_FN_LCD1_D14,
-        GPIO_FN_LCD1_D15,       GPIO_FN_LCD1_D16,       GPIO_FN_LCD1_D17,
-        GPIO_FN_LCD1_D18,       GPIO_FN_LCD1_D19,       GPIO_FN_LCD1_D20,
-        GPIO_FN_LCD1_D21,       GPIO_FN_LCD1_D22,       GPIO_FN_LCD1_D23,
-        GPIO_FN_LCD1_DON,       GPIO_FN_LCD1_VCPWC,
-        GPIO_FN_LCD1_LCLK,      GPIO_FN_LCD1_VEPWC,
-
-        GPIO_FN_LCD1_DCK,       GPIO_FN_LCD1_VSYN, /* for RGB */
-        GPIO_FN_LCD1_HSYN,      GPIO_FN_LCD1_DISP, /* for RGB */
-
-        GPIO_FN_LCD1_WR,        GPIO_FN_LCD1_RD, /* for SYS */
-        GPIO_FN_LCD1_CS,        GPIO_FN_LCD1_RS, /* for SYS */
 
         /* RSPI */
         GPIO_FN_RSPI_SSL0_A,    GPIO_FN_RSPI_SSL1_A,
@@ -346,26 +307,6 @@ enum {
         GPIO_FN_SIM_D_PORT22, /* SIM_D  Port 22/199 */
         GPIO_FN_SIM_D_PORT199,
 
-        /* SDHI0 */
-        GPIO_FN_SDHI0_D0,       GPIO_FN_SDHI0_D1,       GPIO_FN_SDHI0_D2,
-        GPIO_FN_SDHI0_D3,       GPIO_FN_SDHI0_CD,       GPIO_FN_SDHI0_WP,
-        GPIO_FN_SDHI0_CMD,      GPIO_FN_SDHI0_CLK,
-
-        /* SDHI1 */
-        GPIO_FN_SDHI1_D0,       GPIO_FN_SDHI1_D1,       GPIO_FN_SDHI1_D2,
-        GPIO_FN_SDHI1_D3,       GPIO_FN_SDHI1_CD,       GPIO_FN_SDHI1_WP,
-        GPIO_FN_SDHI1_CMD,      GPIO_FN_SDHI1_CLK,
-
-        /* SDHI2 */
-        GPIO_FN_SDHI2_D0,       GPIO_FN_SDHI2_D1,       GPIO_FN_SDHI2_D2,
-        GPIO_FN_SDHI2_D3,       GPIO_FN_SDHI2_CLK,      GPIO_FN_SDHI2_CMD,
-
-        GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
-        GPIO_FN_SDHI2_WP_PORT25,
-
-        GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
-        GPIO_FN_SDHI2_CD_PORT202,
-
         /* MSIOF2 */
         GPIO_FN_MSIOF2_TXD,     GPIO_FN_MSIOF2_RXD,     GPIO_FN_MSIOF2_TSCK,
         GPIO_FN_MSIOF2_SS2,     GPIO_FN_MSIOF2_TSYNC,   GPIO_FN_MSIOF2_SS1,
@@ -417,21 +358,6 @@ enum {
         GPIO_FN_MEMC_DREQ1,
         GPIO_FN_MEMC_A0,
 
-        /* MMC */
-        GPIO_FN_MMC0_D0_PORT68,         GPIO_FN_MMC0_D1_PORT69,
-        GPIO_FN_MMC0_D2_PORT70,         GPIO_FN_MMC0_D3_PORT71,
-        GPIO_FN_MMC0_D4_PORT72,         GPIO_FN_MMC0_D5_PORT73,
-        GPIO_FN_MMC0_D6_PORT74,         GPIO_FN_MMC0_D7_PORT75,
-        GPIO_FN_MMC0_CLK_PORT66,
-        GPIO_FN_MMC0_CMD_PORT67,        /* MSEL4CR_15_0 */
-
-        GPIO_FN_MMC1_D0_PORT149,        GPIO_FN_MMC1_D1_PORT148,
-        GPIO_FN_MMC1_D2_PORT147,        GPIO_FN_MMC1_D3_PORT146,
-        GPIO_FN_MMC1_D4_PORT145,        GPIO_FN_MMC1_D5_PORT144,
-        GPIO_FN_MMC1_D6_PORT143,        GPIO_FN_MMC1_D7_PORT142,
-        GPIO_FN_MMC1_CLK_PORT103,
-        GPIO_FN_MMC1_CMD_PORT104,       /* MSEL4CR_15_1 */
-
         /* MSIOF0 */
         GPIO_FN_MSIOF0_SS1,     GPIO_FN_MSIOF0_SS2,
         GPIO_FN_MSIOF0_RXD,     GPIO_FN_MSIOF0_TXD,
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 8ab0cd6ad6b0..8ea0ad18cdff 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -71,128 +71,125 @@ enum {
         GPIO_FN_A19,
 
         /* IPSR0 */
-        GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
-        GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
-        GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
-        GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
-        GPIO_FN_MMC0_D3, GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D,
-        GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_SCK5_D, GPIO_FN_HSPI_CLK2_B,
-        GPIO_FN_A22, GPIO_FN_RX5_D, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0,
-        GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1,
-        GPIO_FN_A24, GPIO_FN_SD1_CD, GPIO_FN_MMC0_D4, GPIO_FN_FD4,
-        GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
-        GPIO_FN_SD1_WP, GPIO_FN_MMC0_D5, GPIO_FN_FD5, GPIO_FN_HSPI_RX2,
-        GPIO_FN_VI1_R3, GPIO_FN_TX5_B, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CTS0_B,
-        GPIO_FN_CLKOUT, GPIO_FN_TX3C_IRDA_TX_C, GPIO_FN_PWM0_B, GPIO_FN_CS0,
-        GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2,
+        GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
+        GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS,
+        GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
+        GPIO_FN_HCTS1, GPIO_FN_A0,
+        GPIO_FN_FD3, GPIO_FN_A20,
+        GPIO_FN_A21,
+        GPIO_FN_A22, GPIO_FN_VI1_R0,
+        GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_VI1_R1,
+        GPIO_FN_A24, GPIO_FN_FD4,
+        GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
+        GPIO_FN_FD5,
+        GPIO_FN_VI1_R3, GPIO_FN_SSI_SDATA7_B,
+        GPIO_FN_CLKOUT, GPIO_FN_PWM0_B,
         GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
-        GPIO_FN_VI1_R7, GPIO_FN_HRTS1, GPIO_FN_RX4_C,
+        GPIO_FN_VI1_R7, GPIO_FN_HRTS1,
 
         /* IPSR1 */
-        GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C, GPIO_FN_MMC0_D6,
-        GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_MMC0_D7, GPIO_FN_FD7,
-        GPIO_FN_EX_CS2, GPIO_FN_SD1_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_FALE,
-        GPIO_FN_ATACS00, GPIO_FN_EX_CS3, GPIO_FN_SD1_CMD, GPIO_FN_MMC0_CMD,
-        GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_RX5_B,
-        GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_RTS0_B_TANS_B,
-        GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, GPIO_FN_SD1_DAT0, GPIO_FN_MMC0_D0,
-        GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_SCK5_B,
-        GPIO_FN_HTX1, GPIO_FN_TX2_E, GPIO_FN_TX0_B, GPIO_FN_SSI_SCK9,
-        GPIO_FN_EX_CS5, GPIO_FN_SD1_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FD1,
-        GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_RX2_E,
-        GPIO_FN_RX0_B, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
-        GPIO_FN_SCK4, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, GPIO_FN_TX4,
-        GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_RX4, GPIO_FN_HTX0,
-        GPIO_FN_TX1, GPIO_FN_SDATA, GPIO_FN_CTS0_C, GPIO_FN_SUB_TCK,
+        GPIO_FN_FD6, GPIO_FN_FD7,
+        GPIO_FN_FALE,
+        GPIO_FN_ATACS00,
+        GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4,
+        GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B,
+        GPIO_FN_SSI_SDATA9,
+        GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5,
+        GPIO_FN_HTX1, GPIO_FN_SSI_SCK9,
+        GPIO_FN_FD1,
+        GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1,
+        GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
+        GPIO_FN_MLB_SIG, GPIO_FN_PWM3,
+        GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_HTX0,
+        GPIO_FN_SDATA, GPIO_FN_SUB_TCK,
         GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18,
         GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34,
 
         /* IPSR2 */
-        GPIO_FN_HRX0, GPIO_FN_RX1, GPIO_FN_SCKZ, GPIO_FN_RTS0_C_TANS_C,
+        GPIO_FN_HRX0, GPIO_FN_SCKZ,
         GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11,
         GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35,
-        GPIO_FN_HSCK0, GPIO_FN_SCK1, GPIO_FN_MTS, GPIO_FN_PWM5,
-        GPIO_FN_SCK0_C, GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
+        GPIO_FN_HSCK0, GPIO_FN_MTS, GPIO_FN_PWM5,
+        GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
         GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16,
-        GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0, GPIO_FN_CTS1,
-        GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_RX0_C, GPIO_FN_SCIF_CLK_C,
+        GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0,
+        GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_SCIF_CLK_C,
         GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0,
-        GPIO_FN_RTS1_TANS, GPIO_FN_MDATA, GPIO_FN_TX0_C, GPIO_FN_SUB_TMS,
+        GPIO_FN_MDATA, GPIO_FN_SUB_TMS,
         GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17,
-        GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, GPIO_FN_DU0_DR0,
+        GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33,
         GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0,
-        GPIO_FN_TX5_C, GPIO_FN_DU0_DR1, GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
-        GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_RX5_C,
-        GPIO_FN_DU0_DR2, GPIO_FN_LCDOUT2, GPIO_FN_DU0_DR3, GPIO_FN_LCDOUT3,
-        GPIO_FN_DU0_DR4, GPIO_FN_LCDOUT4, GPIO_FN_DU0_DR5, GPIO_FN_LCDOUT5,
-        GPIO_FN_DU0_DR6, GPIO_FN_LCDOUT6, GPIO_FN_DU0_DR7, GPIO_FN_LCDOUT7,
-        GPIO_FN_DU0_DG0, GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
+        GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
+        GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1,
+        GPIO_FN_LCDOUT2, GPIO_FN_LCDOUT3,
+        GPIO_FN_LCDOUT4, GPIO_FN_LCDOUT5,
+        GPIO_FN_LCDOUT6, GPIO_FN_LCDOUT7,
+        GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
         GPIO_FN_AUDATA2,
 
         /* IPSR3 */
-        GPIO_FN_DU0_DG1, GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
-        GPIO_FN_AUDATA3, GPIO_FN_DU0_DG2, GPIO_FN_LCDOUT10, GPIO_FN_DU0_DG3,
-        GPIO_FN_LCDOUT11, GPIO_FN_DU0_DG4, GPIO_FN_LCDOUT12, GPIO_FN_DU0_DG5,
-        GPIO_FN_LCDOUT13, GPIO_FN_DU0_DG6, GPIO_FN_LCDOUT14, GPIO_FN_DU0_DG7,
-        GPIO_FN_LCDOUT15, GPIO_FN_DU0_DB0, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
-        GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, GPIO_FN_DU0_DB1,
+        GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
+        GPIO_FN_AUDATA3, GPIO_FN_LCDOUT10,
+        GPIO_FN_LCDOUT11, GPIO_FN_LCDOUT12,
+        GPIO_FN_LCDOUT13, GPIO_FN_LCDOUT14,
+        GPIO_FN_LCDOUT15, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
+        GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4,
         GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B,
-        GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_DU0_DB2, GPIO_FN_LCDOUT18,
-        GPIO_FN_DU0_DB3, GPIO_FN_LCDOUT19, GPIO_FN_DU0_DB4, GPIO_FN_LCDOUT20,
-        GPIO_FN_DU0_DB5, GPIO_FN_LCDOUT21, GPIO_FN_DU0_DB6, GPIO_FN_LCDOUT22,
-        GPIO_FN_DU0_DB7, GPIO_FN_LCDOUT23, GPIO_FN_DU0_DOTCLKIN,
-        GPIO_FN_QSTVA_QVS, GPIO_FN_TX3_D_IRDA_TX_D, GPIO_FN_SCL3_B,
-        GPIO_FN_DU0_DOTCLKOUT0, GPIO_FN_QCLK, GPIO_FN_DU0_DOTCLKOUT1,
-        GPIO_FN_QSTVB_QVE, GPIO_FN_RX3_D_IRDA_RX_D, GPIO_FN_SDA3_B,
+        GPIO_FN_AUDATA5, GPIO_FN_LCDOUT18,
+        GPIO_FN_LCDOUT19, GPIO_FN_LCDOUT20,
+        GPIO_FN_LCDOUT21, GPIO_FN_LCDOUT22,
+        GPIO_FN_LCDOUT23,
+        GPIO_FN_QSTVA_QVS, GPIO_FN_SCL3_B,
+        GPIO_FN_QCLK,
+        GPIO_FN_QSTVB_QVE, GPIO_FN_SDA3_B,
         GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B,
-        GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_QSTH_QHS,
-        GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE,
-        GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
-        GPIO_FN_CAN1_TX, GPIO_FN_TX2_C, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
+        GPIO_FN_QSTH_QHS,
+        GPIO_FN_QSTB_QHE,
+        GPIO_FN_QCPV_QDE,
+        GPIO_FN_CAN1_TX, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
 
         /* IPSR4 */
-        GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C,
-        GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C,
-        GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, GPIO_FN_DU1_DR0,
-        GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_SD3_CLK,
-        GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
-        GPIO_FN_DU1_DR1, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
-        GPIO_FN_SD3_CMD, GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC,
-        GPIO_FN_CTS0_D, GPIO_FN_DU1_DR2, GPIO_FN_VI2_G0, GPIO_FN_DU1_DR3,
-        GPIO_FN_VI2_G1, GPIO_FN_DU1_DR4, GPIO_FN_VI2_G2, GPIO_FN_DU1_DR5,
-        GPIO_FN_VI2_G3, GPIO_FN_DU1_DR6, GPIO_FN_VI2_G4, GPIO_FN_DU1_DR7,
-        GPIO_FN_VI2_G5, GPIO_FN_DU1_DG0, GPIO_FN_VI2_DATA2_VI2_B2,
-        GPIO_FN_SCL1_B, GPIO_FN_SD3_DAT2, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6,
-        GPIO_FN_TX0_D, GPIO_FN_DU1_DG1, GPIO_FN_VI2_DATA3_VI2_B3,
-        GPIO_FN_SDA1_B, GPIO_FN_SD3_DAT3, GPIO_FN_SCK5, GPIO_FN_AUDATA7,
-        GPIO_FN_RX0_D, GPIO_FN_DU1_DG2, GPIO_FN_VI2_G6, GPIO_FN_DU1_DG3,
-        GPIO_FN_VI2_G7, GPIO_FN_DU1_DG4, GPIO_FN_VI2_R0, GPIO_FN_DU1_DG5,
-        GPIO_FN_VI2_R1, GPIO_FN_DU1_DG6, GPIO_FN_VI2_R2, GPIO_FN_DU1_DG7,
-        GPIO_FN_VI2_R3, GPIO_FN_DU1_DB0, GPIO_FN_VI2_DATA4_VI2_B4,
-        GPIO_FN_SCL2_B, GPIO_FN_SD3_DAT0, GPIO_FN_TX5, GPIO_FN_SCK0_D,
+        GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C,
+        GPIO_FN_QPOLB, GPIO_FN_CAN1_RX,
+        GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B,
+        GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6,
+        GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
+        GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
+        GPIO_FN_AUDSYNC,
+        GPIO_FN_VI2_G0,
+        GPIO_FN_VI2_G1, GPIO_FN_VI2_G2,
+        GPIO_FN_VI2_G3, GPIO_FN_VI2_G4,
+        GPIO_FN_VI2_G5, GPIO_FN_VI2_DATA2_VI2_B2,
+        GPIO_FN_SCL1_B, GPIO_FN_AUDATA6,
+        GPIO_FN_VI2_DATA3_VI2_B3,
+        GPIO_FN_SDA1_B, GPIO_FN_AUDATA7,
+        GPIO_FN_VI2_G6,
+        GPIO_FN_VI2_G7, GPIO_FN_VI2_R0,
+        GPIO_FN_VI2_R1, GPIO_FN_VI2_R2,
+        GPIO_FN_VI2_R3, GPIO_FN_VI2_DATA4_VI2_B4,
+        GPIO_FN_SCL2_B,
 
         /* IPSR5 */
-        GPIO_FN_DU1_DB1, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
-        GPIO_FN_SD3_DAT1, GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D,
-        GPIO_FN_DU1_DB2, GPIO_FN_VI2_R4, GPIO_FN_DU1_DB3, GPIO_FN_VI2_R5,
-        GPIO_FN_DU1_DB4, GPIO_FN_VI2_R6, GPIO_FN_DU1_DB5, GPIO_FN_VI2_R7,
-        GPIO_FN_DU1_DB6, GPIO_FN_SCL2_D, GPIO_FN_DU1_DB7, GPIO_FN_SDA2_D,
-        GPIO_FN_DU1_DOTCLKIN, GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1,
-        GPIO_FN_SCL1_D, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_VI2_FIELD,
-        GPIO_FN_SDA1_D, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_VI2_HSYNC,
-        GPIO_FN_VI3_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_VI2_VSYNC,
-        GPIO_FN_VI3_VSYNC, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
-        GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_SD3_CD,
-        GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
-        GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN,
-        GPIO_FN_GPS_SIGN_D, GPIO_FN_DU1_DISP, GPIO_FN_VI2_DATA6_VI2_B6,
-        GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1,
-        GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
-        GPIO_FN_DU1_CDE, GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B,
-        GPIO_FN_SD3_WP, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
-        GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C,
+        GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
+        GPIO_FN_VI2_R4, GPIO_FN_VI2_R5,
+        GPIO_FN_VI2_R6, GPIO_FN_VI2_R7,
+        GPIO_FN_SCL2_D, GPIO_FN_SDA2_D,
+        GPIO_FN_VI2_CLKENB,
+        GPIO_FN_SCL1_D, GPIO_FN_VI2_FIELD,
+        GPIO_FN_SDA1_D, GPIO_FN_VI2_HSYNC,
+        GPIO_FN_VI3_HSYNC, GPIO_FN_VI2_VSYNC,
+        GPIO_FN_VI3_VSYNC,
+        GPIO_FN_VI2_CLK,
+        GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
+        GPIO_FN_AUDIO_CLKC, GPIO_FN_SPEEDIN,
+        GPIO_FN_GPS_SIGN_D, GPIO_FN_VI2_DATA6_VI2_B6,
+        GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B,
+        GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
+        GPIO_FN_VI2_DATA7_VI2_B7,
+        GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
+        GPIO_FN_AUDIO_CLKOUT, GPIO_FN_GPS_CLK_C,
         GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
-        GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0,
+        GPIO_FN_AUDIO_CLKB, GPIO_FN_CAN_DEBUGOUT0,
         GPIO_FN_MOUT0,
 
         /* IPSR6 */
@@ -208,85 +205,84 @@ enum {
         GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B,
         GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C,
         GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10,
-        GPIO_FN_SCK3, GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
-        GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_TX3_IRDA_TX, GPIO_FN_SSI_SDATA5,
-        GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_RX3_IRDA_RX,
+        GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
+        GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5,
+        GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12,
         GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B,
 
         /* IPSR7 */
         GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B,
         GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B,
-        GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_IRQ0_B,
-        GPIO_FN_SSI_SCK9_B, GPIO_FN_HSPI_CLK1_C, GPIO_FN_SSI_WS78,
-        GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_IRQ1_B, GPIO_FN_SSI_WS9_B,
-        GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
-        GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C,
-        GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C,
-        GPIO_FN_SD0_CLK, GPIO_FN_ATACS01, GPIO_FN_SCK1_B, GPIO_FN_SD0_CMD,
-        GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO, GPIO_FN_SD0_DAT0,
-        GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST, GPIO_FN_SD0_DAT1,
-        GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS, GPIO_FN_SD0_DAT2,
-        GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK, GPIO_FN_SD0_DAT3,
-        GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI, GPIO_FN_SD0_CD,
-        GPIO_FN_DREQ2,  GPIO_FN_RTS1_B_TANS_B, GPIO_FN_SD0_WP, GPIO_FN_DACK2,
-        GPIO_FN_CTS1_B,
+        GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13,
+        GPIO_FN_SSI_SCK9_B, GPIO_FN_SSI_WS78,
+        GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_WS9_B,
+        GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
+        GPIO_FN_TCLK1_C,
+        GPIO_FN_SSI_SDATA8, GPIO_FN_VSP,
+        GPIO_FN_ATACS01,
+        GPIO_FN_ATACS11, GPIO_FN_CC5_TDO,
+        GPIO_FN_ATADIR1, GPIO_FN_CC5_TRST,
+        GPIO_FN_ATAG1, GPIO_FN_CC5_TMS,
+        GPIO_FN_ATARD1, GPIO_FN_CC5_TCK,
+        GPIO_FN_ATAWR1, GPIO_FN_CC5_TDI,
+        GPIO_FN_DREQ2,  GPIO_FN_DACK2,
 
         /* IPSR8 */
-        GPIO_FN_HSPI_CLK0, GPIO_FN_CTS0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK,
+        GPIO_FN_AD_CLK,
         GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
-        GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_HSPI_CS0,
-        GPIO_FN_RTS0_TANS, GPIO_FN_USB_OVC1, GPIO_FN_AD_DI,
+        GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36,
+        GPIO_FN_AD_DI,
         GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
-        GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_HSPI_TX0,
-        GPIO_FN_TX0, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
+        GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37,
+        GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
         GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22,
-        GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_HSPI_RX0,
-        GPIO_FN_RX0, GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
+        GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38,
+        GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
         GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
         GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
         GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA,
-        GPIO_FN_VI0_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C,
-        GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_RX1_C,
+        GPIO_FN_VI0_CLK, GPIO_FN_VI0_CLKENB,
+        GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD,
         GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B,
-        GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_MMC1_CMD, GPIO_FN_HSCK1_B,
+        GPIO_FN_HSCK1_B,
         GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B,
-        GPIO_FN_RTS1_C_TANS_C, GPIO_FN_RX4_D, GPIO_FN_PWMFSW0_C,
+        GPIO_FN_PWMFSW0_C,
 
         /* IPSR9 */
         GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO,
         GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM,
-        GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_MMC1_D0, GPIO_FN_VI0_DATA3_VI0_B3,
-        GPIO_FN_MMC1_D1, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_MMC1_D2,
-        GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_MMC1_D3, GPIO_FN_VI0_DATA6_VI0_B6,
-        GPIO_FN_MMC1_D4, GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
-        GPIO_FN_MMC1_D5, GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
-        GPIO_FN_SSI_SCK78_C, GPIO_FN_IRQ0, GPIO_FN_ARM_TRACEDATA_2,
-        GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_IRQ1,
+        GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_VI0_DATA3_VI0_B3,
+        GPIO_FN_VI0_DATA4_VI0_B4,
+        GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_VI0_DATA6_VI0_B6,
+        GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
+        GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
+        GPIO_FN_SSI_SCK78_C, GPIO_FN_ARM_TRACEDATA_2,
+        GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C,
         GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1,
-        GPIO_FN_MMC1_D6, GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
-        GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, GPIO_FN_MMC1_D7,
+        GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
+        GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV,
         GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4,
-        GPIO_FN_ETH_TX_EN, GPIO_FN_SD2_DAT0_B, GPIO_FN_ARM_TRACEDATA_6,
-        GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER, GPIO_FN_SD2_DAT1_B,
+        GPIO_FN_ETH_TX_EN, GPIO_FN_ARM_TRACEDATA_6,
+        GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER,
         GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0,
-        GPIO_FN_SD2_DAT2_B, GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
-        GPIO_FN_ETH_RXD1, GPIO_FN_SD2_DAT3_B, GPIO_FN_ARM_TRACEDATA_9,
+        GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
+        GPIO_FN_ETH_RXD1, GPIO_FN_ARM_TRACEDATA_9,
 
         /* IPSR10 */
-        GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_SCK1_C, GPIO_FN_DREQ1_B,
+        GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_DREQ1_B,
         GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
         GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
         GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
-        GPIO_FN_SD2_CLK_B, GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12,
-        GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_SD2_CMD_B, GPIO_FN_IRQ3,
+        GPIO_FN_ARM_TRACEDATA_12,
+        GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC,
         GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
-        GPIO_FN_SD2_CD_B, GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14,
+        GPIO_FN_ARM_TRACEDATA_14,
         GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
-        GPIO_FN_SD2_WP_B, GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15,
+        GPIO_FN_ARM_TRACEDATA_15,
         GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC,
-        GPIO_FN_DREQ2_C, GPIO_FN_HSPI_TX1_B, GPIO_FN_TRACECLK,
+        GPIO_FN_DREQ2_C, GPIO_FN_TRACECLK,
         GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO,
-        GPIO_FN_DACK2_C, GPIO_FN_HSPI_RX1_B, GPIO_FN_SCIF_CLK_D,
+        GPIO_FN_DACK2_C, GPIO_FN_SCIF_CLK_D,
         GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D,
         GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4,
         GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC,
@@ -294,35 +290,35 @@ enum {
         GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3,
 
         /* IPSR11 */
-        GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SD2_DAT0, GPIO_FN_SIM_RST,
+        GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SIM_RST,
         GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1,
-        GPIO_FN_SD2_DAT1, GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
-        GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SD2_DAT2,
+        GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
+        GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2,
         GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B,
-        GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SD2_DAT3, GPIO_FN_MT0_BEN,
+        GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_MT0_BEN,
         GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4,
-        GPIO_FN_SD2_CLK, GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
-        GPIO_FN_HSPI_CLK1_D, GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
-        GPIO_FN_SD2_CMD, GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
-        GPIO_FN_HSPI_CS1_D, GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
-        GPIO_FN_SD2_CD, GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D,
-        GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_SD2_WP, GPIO_FN_MT0_PWM,
-        GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
-        GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2,
+        GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
+        GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
+        GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
+        GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
+        GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS,
+        GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_MT0_PWM,
+        GPIO_FN_SPA_TDI, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
+        GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B,
         GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
-        GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_RX2,
+        GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B,
         GPIO_FN_HRTS0_B,
 
         /* IPSR12 */
         GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1,
-        GPIO_FN_SCK2, GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
+        GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
         GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B,
         GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C,
         GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5,
-        GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_TX4_B, GPIO_FN_SIM_D_B,
+        GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_SIM_D_B,
         GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB,
-        GPIO_FN_RX4_B, GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
-        GPIO_FN_GPS_MAG, GPIO_FN_FCE, GPIO_FN_SCK4_B,
+        GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
+        GPIO_FN_GPS_MAG, GPIO_FN_FCE,
 };
 
 struct platform_device;
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index b582facc1cf6..7ded4ebaf5cc 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -294,21 +294,6 @@ enum {
         GPIO_FN_D12_NAF12,      GPIO_FN_D13_NAF13,      GPIO_FN_D14_NAF14,
         GPIO_FN_D15_NAF15,
 
-        /*
-         * MMCIF(1)             (PORT 84, 85, 86, 87, 88, 89,
-         *                            90, 91, 92, 99)
-         */
-        GPIO_FN_MMCD0_0,        GPIO_FN_MMCD0_1,        GPIO_FN_MMCD0_2,
-        GPIO_FN_MMCD0_3,        GPIO_FN_MMCD0_4,        GPIO_FN_MMCD0_5,
-        GPIO_FN_MMCD0_6,        GPIO_FN_MMCD0_7,
-        GPIO_FN_MMCCMD0,        GPIO_FN_MMCCLK0,
-
-        /* MMCIF(2)             (PORT 54, 55, 56, 57, 58, 59, 60, 61, 66, 67) */
-        GPIO_FN_MMCD1_0,        GPIO_FN_MMCD1_1,        GPIO_FN_MMCD1_2,
-        GPIO_FN_MMCD1_3,        GPIO_FN_MMCD1_4,        GPIO_FN_MMCD1_5,
-        GPIO_FN_MMCD1_6,        GPIO_FN_MMCD1_7,
-        GPIO_FN_MMCCLK1,        GPIO_FN_MMCCMD1,
-
         /* SPU2         (PORT 65) */
         GPIO_FN_VINT_I,
 
@@ -416,20 +401,6 @@ enum {
         /* HDMI         (PORT 169, 170) */
         GPIO_FN_HDMI_HPD,       GPIO_FN_HDMI_CEC,
 
-        /* SDHI0        (PORT 171, 172, 173, 174, 175, 176, 177, 178) */
-        GPIO_FN_SDHICLK0,       GPIO_FN_SDHICD0,
-        GPIO_FN_SDHICMD0,       GPIO_FN_SDHIWP0,
-        GPIO_FN_SDHID0_0,       GPIO_FN_SDHID0_1,
-        GPIO_FN_SDHID0_2,       GPIO_FN_SDHID0_3,
-
-        /* SDHI1        (PORT 179, 180, 181, 182, 183, 184) */
-        GPIO_FN_SDHICLK1,       GPIO_FN_SDHICMD1,       GPIO_FN_SDHID1_0,
-        GPIO_FN_SDHID1_1,       GPIO_FN_SDHID1_2,       GPIO_FN_SDHID1_3,
-
-        /* SDHI2        (PORT 185, 186, 187, 188, 189, 190) */
-        GPIO_FN_SDHICLK2,       GPIO_FN_SDHICMD2,       GPIO_FN_SDHID2_0,
-        GPIO_FN_SDHID2_1,       GPIO_FN_SDHID2_2,       GPIO_FN_SDHID2_3,
-
         /* SDENC        see MSEL4CR 19 */
         GPIO_FN_SDENC_CPG,
         GPIO_FN_SDENC_DV_CLKI,
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index 606d31d02a4e..fbc1584d6712 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -94,8 +94,7 @@ enum {
         GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
 
         /* Table 25-1 (Function 0-7) */
-        GPIO_FN_VBUS_0,
-        GPIO_FN_GPI0,
+        GPIO_FN_GPI0 = 310,
         GPIO_FN_GPI1,
         GPIO_FN_GPI2,
         GPIO_FN_GPI3,
@@ -103,15 +102,11 @@ enum {
         GPIO_FN_GPI5,
         GPIO_FN_GPI6,
         GPIO_FN_GPI7,
-        GPIO_FN_SCIFA7_RXD,
-        GPIO_FN_SCIFA7_CTS_,
         GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
         GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
-        GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \
+        GPIO_FN_GPO5,
         GPIO_FN_PORT16_VIO_CKOR,
-        GPIO_FN_SCIFA0_TXD,
-        GPIO_FN_SCIFA7_TXD,
-        GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2,
+        GPIO_FN_PORT19_VIO_CKO2,
         GPIO_FN_GPO0,
         GPIO_FN_GPO1,
         GPIO_FN_GPO2, GPIO_FN_STATUS0,
@@ -119,83 +114,44 @@ enum {
         GPIO_FN_GPO4, GPIO_FN_STATUS2,
         GPIO_FN_VINT,
         GPIO_FN_TCKON,
-        GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \
+        GPIO_FN_XDVFS1,
         GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
-        GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \
+        GPIO_FN_XDVFS2,
         GPIO_FN_PORT28_TPU1TO1,
         GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
         GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
         GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
-        GPIO_FN_SCIFA4_TXD,
-        GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
-        GPIO_FN_SCIFA4_RTS_,
-        GPIO_FN_SCIFA4_CTS_,
-        GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
-        GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
-        GPIO_FN_FSIBOSLD,
-        GPIO_FN_FSIBISLD,
+        GPIO_FN_XWUP,
         GPIO_FN_VACK,
         GPIO_FN_XTAL1L,
-        GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2,
-        GPIO_FN_SCIFA0_RXD,
-        GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1,
-        GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT,
-        GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR,
-        GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF,
-        GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD,
-        GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \
-        GPIO_FN_FSIAOMC,
-        GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR,
-
-        GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT,
-        GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2,
-        GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \
-        GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF,
-        GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \
-        GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC,
-        GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0,
+        GPIO_FN_PORT49_IROUT,
+        GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2,
+
+        GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3,
+        GPIO_FN_BBIF2_TXD2,
+        GPIO_FN_TPU3TO3,
+        GPIO_FN_TPU3TO2,
+        GPIO_FN_TPU0TO0,
         GPIO_FN_A0, GPIO_FN_BS_,
-        GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2,
-        GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1,
-        GPIO_FN_A14, GPIO_FN_KEYOUT5,
-        GPIO_FN_A15, GPIO_FN_KEYOUT4,
-        GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1,
-        GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
-        GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
-        GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD,
-        GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK,
-        GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
-        GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0,
-        GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1,
-        GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD,
-        GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2,
-        GPIO_FN_A26, GPIO_FN_KEYIN6,
-        GPIO_FN_KEYIN7,
-        GPIO_FN_D0_NAF0,
-        GPIO_FN_D1_NAF1,
-        GPIO_FN_D2_NAF2,
-        GPIO_FN_D3_NAF3,
-        GPIO_FN_D4_NAF4,
-        GPIO_FN_D5_NAF5,
-        GPIO_FN_D6_NAF6,
-        GPIO_FN_D7_NAF7,
-        GPIO_FN_D8_NAF8,
-        GPIO_FN_D9_NAF9,
-        GPIO_FN_D10_NAF10,
-        GPIO_FN_D11_NAF11,
-        GPIO_FN_D12_NAF12,
-        GPIO_FN_D13_NAF13,
-        GPIO_FN_D14_NAF14,
-        GPIO_FN_D15_NAF15,
-        GPIO_FN_CS4_,
-        GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR,
-        GPIO_FN_CS5B_, GPIO_FN_FCE1_,
-        GPIO_FN_CS6B_, GPIO_FN_DACK0,
-        GPIO_FN_FCE0_, GPIO_FN_CS6A_,
+        GPIO_FN_A12, GPIO_FN_TPU4TO2,
+        GPIO_FN_A13, GPIO_FN_TPU0TO1,
+        GPIO_FN_A14,
+        GPIO_FN_A15,
+        GPIO_FN_A16, GPIO_FN_MSIOF0_SS1,
+        GPIO_FN_A17, GPIO_FN_MSIOF0_TSYNC,
+        GPIO_FN_A18, GPIO_FN_MSIOF0_TSCK,
+        GPIO_FN_A19, GPIO_FN_MSIOF0_TXD,
+        GPIO_FN_A20, GPIO_FN_MSIOF0_RSCK,
+        GPIO_FN_A21, GPIO_FN_MSIOF0_RSYNC,
+        GPIO_FN_A22, GPIO_FN_MSIOF0_MCK0,
+        GPIO_FN_A23, GPIO_FN_MSIOF0_MCK1,
+        GPIO_FN_A24, GPIO_FN_MSIOF0_RXD,
+        GPIO_FN_A25, GPIO_FN_MSIOF0_SS2,
+        GPIO_FN_A26,
+        GPIO_FN_FCE1_,
+        GPIO_FN_DACK0,
+        GPIO_FN_FCE0_,
         GPIO_FN_WAIT_, GPIO_FN_DREQ0,
-        GPIO_FN_RD__FSC,
-        GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE,
-        GPIO_FN_WE1_,
         GPIO_FN_FRB,
         GPIO_FN_CKO,
         GPIO_FN_NBRSTOUT_,
@@ -204,145 +160,118 @@ enum {
         GPIO_FN_BBIF2_RXD,
         GPIO_FN_BBIF2_SYNC,
         GPIO_FN_BBIF2_SCK,
-        GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2,
-        GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1,
-        GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1,
-        GPIO_FN_SCIFA3_TXD,
+        GPIO_FN_MFG3_IN2,
+        GPIO_FN_MFG3_IN1,
+        GPIO_FN_BBIF1_SS2, GPIO_FN_MFG3_OUT1,
         GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
         GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
         GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
         GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
-        GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \
-        GPIO_FN_PORT115_I2C_SCL3,
-        GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \
-        GPIO_FN_PORT116_I2C_SDA3,
+        GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK,
+        GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC,
         GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
         GPIO_FN_HSI_TX_FLAG,
-        GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \
-        GPIO_FN_LCD2D0,
-
-        GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \
-        GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1,
-        GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10,
-        GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \
-        GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11,
-        GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \
-        GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12,
-        GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13,
-        GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14,
-        GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15,
-        GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16,
-        GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17,
-        GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \
-        GPIO_FN_LCD2D6,
-        GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \
-        GPIO_FN_LCD2D7,
-        GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8,
-        GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9,
-        GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \
-        GPIO_FN_LCD2D2,
-        GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \
-        GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3,
-        GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
-        GPIO_FN_LCD2D4,
-        GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \
-        GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5,
-        GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \
-        GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18,
-        GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19,
+        GPIO_FN_VIO_VD, GPIO_FN_VIO2_VD,
+
+        GPIO_FN_VIO_HD,
+        GPIO_FN_VIO2_HD,
+        GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD,
+        GPIO_FN_VIO_D1, GPIO_FN_PORT131_MSIOF2_SS1,
+        GPIO_FN_VIO_D2, GPIO_FN_PORT132_MSIOF2_SS2,
+        GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC,
+        GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD,
+        GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK,
+        GPIO_FN_VIO_D6,
+        GPIO_FN_VIO_D7,
+        GPIO_FN_VIO_D8, GPIO_FN_VIO2_D0,
+        GPIO_FN_VIO_D9, GPIO_FN_VIO2_D1,
+        GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2,
+        GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3,
+        GPIO_FN_VIO_D12, GPIO_FN_VIO2_D4,
+        GPIO_FN_VIO_D13,
+        GPIO_FN_VIO2_D5,
+        GPIO_FN_VIO_D14, GPIO_FN_VIO2_D6,
+        GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3,
+        GPIO_FN_VIO2_D7,
+        GPIO_FN_VIO_CLK,
+        GPIO_FN_VIO2_CLK,
+        GPIO_FN_VIO_FIELD, GPIO_FN_VIO2_FIELD,
         GPIO_FN_VIO_CKO,
-        GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \
-        GPIO_FN_PORT149_KEYOUT9,
+        GPIO_FN_A27, GPIO_FN_MFG0_IN1,
         GPIO_FN_MFG0_IN2,
         GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
         GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
         GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
-        GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
-        GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
-        GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2,
-        GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD,
-        GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
-        GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
-        GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD,
-        GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_,
-        GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
-        GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
+        GPIO_FN_MSIOF2_MCK0,
+        GPIO_FN_MSIOF2_MCK1,
+        GPIO_FN_PORT156_MSIOF2_SS2,
+        GPIO_FN_PORT157_MSIOF2_RXD,
+        GPIO_FN_DINT_, GPIO_FN_TS_SCK3,
+        GPIO_FN_NMI,
         GPIO_FN_TPU3TO0,
-        GPIO_FN_LCDD0,
-        GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1,
-        GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1,
-        GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1,
-        GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD,
-        GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \
+        GPIO_FN_BBIF2_TSYNC1,
+        GPIO_FN_BBIF2_TSCK1,
+        GPIO_FN_BBIF2_TXD1,
+        GPIO_FN_MFG2_OUT2,
         GPIO_FN_TPU2TO1,
-        GPIO_FN_LCDD6,
-        GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
-        GPIO_FN_LCDD8, GPIO_FN_D16,
-        GPIO_FN_LCDD9, GPIO_FN_D17,
-        GPIO_FN_LCDD10, GPIO_FN_D18,
-        GPIO_FN_LCDD11, GPIO_FN_D19,
-        GPIO_FN_LCDD12, GPIO_FN_D20,
-        GPIO_FN_LCDD13, GPIO_FN_D21,
-        GPIO_FN_LCDD14, GPIO_FN_D22,
-        GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
-        GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
-        GPIO_FN_LCDD17, GPIO_FN_D25,
-        GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
-        GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
-        GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
-        GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
-        GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
-        GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
-        GPIO_FN_LCDDCK, GPIO_FN_LCDWR_,
-        GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \
-        GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP,
-        GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \
+        GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
+        GPIO_FN_D16,
+        GPIO_FN_D17,
+        GPIO_FN_D18,
+        GPIO_FN_D19,
+        GPIO_FN_D20,
+        GPIO_FN_D21,
+        GPIO_FN_D22,
+        GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
+        GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
+        GPIO_FN_D25,
+        GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
+        GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
+        GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
+        GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
+        GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
+        GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
+        GPIO_FN_DACK2,
+        GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3,
+        GPIO_FN_DACK3,
         GPIO_FN_PORT218_VIO_CKOR,
-        GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \
         GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
-        GPIO_FN_LCD2DCK_2,
-        GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2,
-        GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \
+        GPIO_FN_DREQ1,
         GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
-        GPIO_FN_PORT221_LCD2HSYN,
-        GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \
-        GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN,
-
-        GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
-        GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2,
-        GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN,
-        GPIO_FN_SCIFA1_RXD,
-        GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1,
-        GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2,
-        GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_,
-        GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2,
-        GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
-        GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
-        GPIO_FN_LCD2D20,
+        GPIO_FN_DACK1, GPIO_FN_OVCN,
+        GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3,
+
+        GPIO_FN_OVCN2,
+        GPIO_FN_EXTLP, GPIO_FN_PORT226_VIO_CKO2,
+        GPIO_FN_IDIN,
+        GPIO_FN_MFG1_IN1,
+        GPIO_FN_MSIOF1_TXD,
+        GPIO_FN_MSIOF1_TSYNC,
+        GPIO_FN_MSIOF1_TSCK,
+        GPIO_FN_MSIOF1_RXD,
+        GPIO_FN_MSIOF1_RSCK, GPIO_FN_VIO2_CLK2,
         GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
-        GPIO_FN_LCD2D21,
-        GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2,
-        GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2,
-        GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22,
-        GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23,
-        GPIO_FN_SCIFA6_TXD,
-        GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
+        GPIO_FN_MSIOF1_MCK0,
+        GPIO_FN_MSIOF1_MCK1,
+        GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2,
+        GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2,
+        GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
         GPIO_FN_TPU4TO0,
-        GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
-        GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
-        GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \
-        GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD,
-        GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \
-        GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD,
-        GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \
-        GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
-        GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \
-        GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
-        GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \
-        GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \
-        GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK,
+        GPIO_FN_MFG4_IN2,
+        GPIO_FN_PORT243_VIO_CKO2,
+        GPIO_FN_MFG2_IN1,
+        GPIO_FN_MSIOF2R_RXD,
+        GPIO_FN_MFG2_IN2,
+        GPIO_FN_MSIOF2R_TXD,
+        GPIO_FN_MFG1_OUT1,
+        GPIO_FN_TPU1TO0,
+        GPIO_FN_MFG3_OUT2,
+        GPIO_FN_TPU3TO1,
+        GPIO_FN_MFG2_OUT1,
+        GPIO_FN_TPU2TO0,
+        GPIO_FN_MSIOF2R_TSCK,
         GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
-        GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC,
+        GPIO_FN_MSIOF2R_TSYNC,
         GPIO_FN_SDHICLK0,
         GPIO_FN_SDHICD0,
         GPIO_FN_SDHID0_0,
@@ -435,54 +364,12 @@ enum {
         GPIO_FN_IRQ9_MEM_INT,
         GPIO_FN_IRQ9_MCP_INT,
         GPIO_FN_A11,
-        GPIO_FN_KEYOUT8,
         GPIO_FN_TPU4TO3,
         GPIO_FN_RESETA_N_PU_ON,
         GPIO_FN_RESETA_N_PU_OFF,
         GPIO_FN_EDBGREQ_PD,
         GPIO_FN_EDBGREQ_PU,
 
-        /* Functions with pull-ups */
-        GPIO_FN_KEYIN0_PU,
-        GPIO_FN_KEYIN1_PU,
-        GPIO_FN_KEYIN2_PU,
-        GPIO_FN_KEYIN3_PU,
-        GPIO_FN_KEYIN4_PU,
-        GPIO_FN_KEYIN5_PU,
-        GPIO_FN_KEYIN6_PU,
-        GPIO_FN_KEYIN7_PU,
-        GPIO_FN_SDHICD0_PU,
-        GPIO_FN_SDHID0_0_PU,
-        GPIO_FN_SDHID0_1_PU,
-        GPIO_FN_SDHID0_2_PU,
-        GPIO_FN_SDHID0_3_PU,
-        GPIO_FN_SDHICMD0_PU,
-        GPIO_FN_SDHIWP0_PU,
-        GPIO_FN_SDHID1_0_PU,
-        GPIO_FN_SDHID1_1_PU,
-        GPIO_FN_SDHID1_2_PU,
-        GPIO_FN_SDHID1_3_PU,
-        GPIO_FN_SDHICMD1_PU,
-        GPIO_FN_SDHID2_0_PU,
-        GPIO_FN_SDHID2_1_PU,
-        GPIO_FN_SDHID2_2_PU,
-        GPIO_FN_SDHID2_3_PU,
-        GPIO_FN_SDHICMD2_PU,
-        GPIO_FN_MMCCMD0_PU,
-        GPIO_FN_MMCCMD1_PU,
-        GPIO_FN_MMCD0_0_PU,
-        GPIO_FN_MMCD0_1_PU,
-        GPIO_FN_MMCD0_2_PU,
-        GPIO_FN_MMCD0_3_PU,
-        GPIO_FN_MMCD0_4_PU,
-        GPIO_FN_MMCD0_5_PU,
-        GPIO_FN_MMCD0_6_PU,
-        GPIO_FN_MMCD0_7_PU,
-        GPIO_FN_FSIACK_PU,
-        GPIO_FN_FSIAILR_PU,
-        GPIO_FN_FSIAIBT_PU,
-        GPIO_FN_FSIAISLD_PU,
-
         /* end of GPIO */
         GPIO_NR,
 };
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
index 8807c27f71f9..b86dc8908724 100644
--- a/arch/arm/mach-shmobile/intc-r8a7779.c
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -19,12 +19,16 @@
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/platform_data/irq-renesas-intc-irqpin.h>
+#include <linux/irqchip.h>
 #include <mach/common.h>
 #include <mach/intc.h>
+#include <mach/irqs.h>
 #include <mach/r8a7779.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -38,18 +42,61 @@
 #define INT2NTSR0 IOMEM(0xfe700060)
 #define INT2NTSR1 IOMEM(0xfe700064)
 
+static struct renesas_intc_irqpin_config irqpin0_platform_data = {
+        .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
+        .sense_bitfield_width = 2,
+};
+
+static struct resource irqpin0_resources[] = {
+        DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
+        DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
+        DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
+        DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
+        DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
+        DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
+        DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
+        DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
+        DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
+};
+
+static struct platform_device irqpin0_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 0,
+        .resource       = irqpin0_resources,
+        .num_resources  = ARRAY_SIZE(irqpin0_resources),
+        .dev            = {
+                .platform_data  = &irqpin0_platform_data,
+        },
+};
+
+void __init r8a7779_init_irq_extpin(int irlm)
+{
+        void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
+        unsigned long tmp;
+
+        if (icr0) {
+                tmp = ioread32(icr0);
+                if (irlm)
+                        tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
+                else
+                        tmp &= ~(1 << 23); /* IRL mode - not supported */
+                tmp |= (1 << 21); /* LVLMODE = 1 */
+                iowrite32(tmp, icr0);
+                iounmap(icr0);
+
+                if (irlm)
+                        platform_device_register(&irqpin0_device);
+        } else
+                pr_warn("r8a7779: unable to setup external irq pin mode\n");
+}
+
 static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
 {
         return 0; /* always allow wakeup */
 }
 
-void __init r8a7779_init_irq(void)
+static void __init r8a7779_init_irq_common(void)
 {
-        void __iomem *gic_dist_base = IOMEM(0xf0001000);
-        void __iomem *gic_cpu_base = IOMEM(0xf0000100);
-
-        /* use GIC to handle interrupts */
-        gic_init(0, 29, gic_dist_base, gic_cpu_base);
         gic_arch_extn.irq_set_wake = r8a7779_set_wake;
 
         /* route all interrupts to ARM */
@@ -63,3 +110,22 @@ void __init r8a7779_init_irq(void)
         __raw_writel(0xbffffffc, INT2SMSKCR3);
         __raw_writel(0x003fee3f, INT2SMSKCR4);
 }
+
+void __init r8a7779_init_irq(void)
+{
+        void __iomem *gic_dist_base = IOMEM(0xf0001000);
+        void __iomem *gic_cpu_base = IOMEM(0xf0000100);
+
+        /* use GIC to handle interrupts */
+        gic_init(0, 29, gic_dist_base, gic_cpu_base);
+
+        r8a7779_init_irq_common();
+}
+
+#ifdef CONFIG_OF
+void __init r8a7779_init_irq_dt(void)
+{
+        irqchip_init();
+        r8a7779_init_irq_common();
+}
+#endif
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index 91faba666d46..19a26f4579b3 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -260,108 +260,6 @@ static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
         return 0; /* always allow wakeup */
 }
 
-#define RELOC_BASE 0x1200
-
-/* INTCA IRQ pins at INTCS + RELOC_BASE to make space for GIC+INTC handling */
-#define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE)
-
-INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
-                 INTCS_VECT_RELOC, "sh73a0-intca-irq-pins");
-
-static int to_gic_irq(struct irq_data *data)
-{
-        unsigned int vect = irq2evt(data->irq) - INTCS_VECT_BASE;
-
-        if (vect >= 0x3200)
-                vect -= 0x3000;
-        else
-                vect -= 0x0200;
-
-        return gic_spi((vect >> 5) + 1);
-}
-
-static int to_intca_reloc_irq(struct irq_data *data)
-{
-        return data->irq + (RELOC_BASE >> 5);
-}
-
-#define irq_cb(cb, irq) irq_get_chip(irq)->cb(irq_get_irq_data(irq))
-#define irq_cbp(cb, irq, p...) irq_get_chip(irq)->cb(irq_get_irq_data(irq), p)
-
-static void intca_gic_enable(struct irq_data *data)
-{
-        irq_cb(irq_unmask, to_intca_reloc_irq(data));
-        irq_cb(irq_unmask, to_gic_irq(data));
-}
-
-static void intca_gic_disable(struct irq_data *data)
-{
-        irq_cb(irq_mask, to_gic_irq(data));
-        irq_cb(irq_mask, to_intca_reloc_irq(data));
-}
-
-static void intca_gic_mask_ack(struct irq_data *data)
-{
-        irq_cb(irq_mask, to_gic_irq(data));
-        irq_cb(irq_mask_ack, to_intca_reloc_irq(data));
-}
-
-static void intca_gic_eoi(struct irq_data *data)
-{
-        irq_cb(irq_eoi, to_gic_irq(data));
-}
-
-static int intca_gic_set_type(struct irq_data *data, unsigned int type)
-{
-        return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type);
-}
-
-#ifdef CONFIG_SMP
-static int intca_gic_set_affinity(struct irq_data *data,
-                                  const struct cpumask *cpumask,
-                                  bool force)
-{
-        return irq_cbp(irq_set_affinity, to_gic_irq(data), cpumask, force);
-}
-#endif
-
-struct irq_chip intca_gic_irq_chip = {
-        .name                   = "INTCA-GIC",
-        .irq_mask               = intca_gic_disable,
-        .irq_unmask             = intca_gic_enable,
-        .irq_mask_ack           = intca_gic_mask_ack,
-        .irq_eoi                = intca_gic_eoi,
-        .irq_enable             = intca_gic_enable,
-        .irq_disable            = intca_gic_disable,
-        .irq_shutdown           = intca_gic_disable,
-        .irq_set_type           = intca_gic_set_type,
-        .irq_set_wake           = sh73a0_set_wake,
-#ifdef CONFIG_SMP
-        .irq_set_affinity       = intca_gic_set_affinity,
-#endif
-};
-
-static int to_intc_vect(int irq)
-{
-        unsigned int irq_pin = irq - gic_spi(1);
-        unsigned int offs;
-
-        if (irq_pin < 16)
-                offs = 0x0200;
-        else
-                offs = 0x3000;
-
-        return offs + (irq_pin << 5);
-}
-
-static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id)
-{
-        generic_handle_irq(intcs_evt2irq(to_intc_vect(irq)));
-        return IRQ_HANDLED;
-}
-
-static struct irqaction sh73a0_irq_pin_cascade[32];
-
 #define PINTER0_PHYS 0xe69000a0
 #define PINTER1_PHYS 0xe69000a4
 #define PINTER0_VIRT IOMEM(0xe69000a0)
@@ -422,13 +320,11 @@ void __init sh73a0_init_irq(void)
         void __iomem *gic_dist_base = IOMEM(0xf0001000);
         void __iomem *gic_cpu_base = IOMEM(0xf0000100);
         void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
-        int k, n;
 
         gic_init(0, 29, gic_dist_base, gic_cpu_base);
         gic_arch_extn.irq_set_wake = sh73a0_set_wake;
 
         register_intc_controller(&intcs_desc);
-        register_intc_controller(&intca_irq_pins_desc);
         register_intc_controller(&intc_pint0_desc);
         register_intc_controller(&intc_pint1_desc);
 
@@ -438,19 +334,6 @@ void __init sh73a0_init_irq(void)
         sh73a0_intcs_cascade.dev_id = intevtsa;
         setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
 
-        /* IRQ pins require special handling through INTCA and GIC */
-        for (k = 0; k < 32; k++) {
-                sh73a0_irq_pin_cascade[k].name = "INTCA-GIC cascade";
-                sh73a0_irq_pin_cascade[k].handler = sh73a0_irq_pin_demux;
-                setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]);
-
-                n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k)));
-                WARN_ON(irq_alloc_desc_at(n, numa_node_id()) != n);
-                irq_set_chip_and_handler_name(n, &intca_gic_irq_chip,
-                                              handle_level_irq, "level");
-                set_irq_flags(n, IRQF_VALID); /* yuck */
-        }
-
         /* PINT pins are sanely tied to the GIC as SPI */
         sh73a0_pint0_cascade.name = "PINT0 cascade";
         sh73a0_pint0_cascade.handler = sh73a0_pint0_demux;
@@ -460,11 +343,3 @@ void __init sh73a0_init_irq(void)
         sh73a0_pint1_cascade.handler = sh73a0_pint1_demux;
         setup_irq(gic_spi(34), &sh73a0_pint1_cascade);
 }
-
-#ifdef CONFIG_OF
-void __init sh73a0_init_irq_dt(void)
-{
-        irqchip_init();
-        gic_arch_extn.irq_set_wake = sh73a0_set_wake;
-}
-#endif
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index a0826a48dd08..dec9293bb90d 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -410,11 +410,9 @@ static int sh7372_enter_a4s(struct cpuidle_device *dev,
 static struct cpuidle_driver sh7372_cpuidle_driver = {
         .name                   = "sh7372_cpuidle",
         .owner                  = THIS_MODULE,
-        .en_core_tk_irqen       = 1,
         .state_count            = 5,
         .safe_state_index       = 0, /* C1 */
         .states[0] = ARM_CPUIDLE_WFI_STATE,
-        .states[0].enter = shmobile_enter_wfi,
         .states[1] = {
                 .name = "C2",
                 .desc = "Core Standby Mode",
@@ -450,12 +448,12 @@ static struct cpuidle_driver sh7372_cpuidle_driver = {
         },
 };
 
-static void sh7372_cpuidle_init(void)
+static void __init sh7372_cpuidle_init(void)
 {
         shmobile_cpuidle_set_driver(&sh7372_cpuidle_driver);
 }
 #else
-static void sh7372_cpuidle_init(void) {}
+static void __init sh7372_cpuidle_init(void) {}
 #endif
 
 #ifdef CONFIG_SUSPEND
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index 47662a581c0a..e4545c152722 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -404,7 +404,7 @@ void __init emev2_add_standard_devices(void)
                              ARRAY_SIZE(emev2_late_devices));
 }
 
-void __init emev2_init_delay(void)
+static void __init emev2_init_delay(void)
 {
         shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
 }
@@ -439,7 +439,7 @@ static const struct of_dev_auxdata emev2_auxdata_lookup[] __initconst = {
         { }
 };
 
-void __init emev2_add_standard_devices_dt(void)
+static void __init emev2_add_standard_devices_dt(void)
 {
         of_platform_populate(NULL, of_default_bus_match_table,
                              emev2_auxdata_lookup, NULL);
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index c54ff9b29fe5..042df35e71a0 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -21,6 +21,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/input.h>
@@ -28,6 +29,7 @@
 #include <linux/serial_sci.h>
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
+#include <linux/dma-mapping.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <mach/r8a7779.h>
@@ -91,7 +93,7 @@ static struct plat_sci_port scif0_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(88)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x78)),
 };
 
 static struct platform_device scif0_device = {
@@ -108,7 +110,7 @@ static struct plat_sci_port scif1_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(89)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x79)),
 };
 
 static struct platform_device scif1_device = {
@@ -125,7 +127,7 @@ static struct plat_sci_port scif2_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(90)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7a)),
 };
 
 static struct platform_device scif2_device = {
@@ -142,7 +144,7 @@ static struct plat_sci_port scif3_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(91)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7b)),
 };
 
 static struct platform_device scif3_device = {
@@ -159,7 +161,7 @@ static struct plat_sci_port scif4_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(92)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7c)),
 };
 
 static struct platform_device scif4_device = {
@@ -176,7 +178,7 @@ static struct plat_sci_port scif5_platform_data = {
         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
         .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
-        .irqs           = SCIx_IRQ_MUXED(gic_spi(93)),
+        .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7d)),
 };
 
 static struct platform_device scif5_device = {
@@ -203,7 +205,7 @@ static struct resource tmu00_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gic_spi(32),
+                .start  = gic_iid(0x40),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -233,7 +235,7 @@ static struct resource tmu01_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = gic_spi(33),
+                .start  = gic_iid(0x41),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -255,7 +257,7 @@ static struct resource rcar_i2c0_res[] = {
                 .end    = 0xffc70fff,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = gic_spi(79),
+                .start  = gic_iid(0x6f),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -273,7 +275,7 @@ static struct resource rcar_i2c1_res[] = {
                 .end    = 0xffc71fff,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = gic_spi(82),
+                .start  = gic_iid(0x72),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -291,7 +293,7 @@ static struct resource rcar_i2c2_res[] = {
                 .end    = 0xffc72fff,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = gic_spi(80),
+                .start  = gic_iid(0x70),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -309,7 +311,7 @@ static struct resource rcar_i2c3_res[] = {
                 .end    = 0xffc73fff,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = gic_spi(81),
+                .start  = gic_iid(0x71),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -321,7 +323,31 @@ static struct platform_device i2c3_device = {
         .num_resources  = ARRAY_SIZE(rcar_i2c3_res),
 };
 
-static struct platform_device *r8a7779_early_devices[] __initdata = {
+static struct resource sata_resources[] = {
+        [0] = {
+                .name   = "rcar-sata",
+                .start  = 0xfc600000,
+                .end    = 0xfc601fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_iid(0x84),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sata_device = {
+        .name           = "sata_rcar",
+        .id             = -1,
+        .resource       = sata_resources,
+        .num_resources  = ARRAY_SIZE(sata_resources),
+        .dev            = {
+                .dma_mask               = &sata_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+static struct platform_device *r8a7779_devices_dt[] __initdata = {
         &scif0_device,
         &scif1_device,
         &scif2_device,
@@ -330,13 +356,14 @@ static struct platform_device *r8a7779_early_devices[] __initdata = {
         &scif5_device,
         &tmu00_device,
         &tmu01_device,
+};
+
+static struct platform_device *r8a7779_late_devices[] __initdata = {
         &i2c0_device,
         &i2c1_device,
         &i2c2_device,
         &i2c3_device,
-};
-
-static struct platform_device *r8a7779_late_devices[] __initdata = {
+        &sata_device,
 };
 
 void __init r8a7779_add_standard_devices(void)
@@ -349,8 +376,8 @@ void __init r8a7779_add_standard_devices(void)
 
         r8a7779_init_pm_domains();
 
-        platform_add_devices(r8a7779_early_devices,
-                            ARRAY_SIZE(r8a7779_early_devices));
+        platform_add_devices(r8a7779_devices_dt,
+                            ARRAY_SIZE(r8a7779_devices_dt));
         platform_add_devices(r8a7779_late_devices,
                             ARRAY_SIZE(r8a7779_late_devices));
 }
@@ -367,8 +394,8 @@ void __init r8a7779_earlytimer_init(void)
 
 void __init r8a7779_add_early_devices(void)
 {
-        early_platform_add_devices(r8a7779_early_devices,
-                                   ARRAY_SIZE(r8a7779_early_devices));
+        early_platform_add_devices(r8a7779_devices_dt,
+                                   ARRAY_SIZE(r8a7779_devices_dt));
 
         /* Early serial console setup is not included here due to
          * memory map collisions. The SCIF serial ports in r8a7779
@@ -386,3 +413,40 @@ void __init r8a7779_add_early_devices(void)
          * command line in case of the marzen board.
          */
 }
+
+#ifdef CONFIG_USE_OF
+void __init r8a7779_init_delay(void)
+{
+        shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
+}
+
+static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = {
+        {},
+};
+
+void __init r8a7779_add_standard_devices_dt(void)
+{
+        /* clocks are setup late during boot in the case of DT */
+        r8a7779_clock_init();
+
+        platform_add_devices(r8a7779_devices_dt,
+                             ARRAY_SIZE(r8a7779_devices_dt));
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             r8a7779_auxdata_lookup, NULL);
+}
+
+static const char *r8a7779_compat_dt[] __initdata = {
+        "renesas,r8a7779",
+        NULL,
+};
+
+DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
+        .map_io         = r8a7779_map_io,
+        .init_early     = r8a7779_init_delay,
+        .nr_irqs        = NR_IRQS_LEGACY,
+        .init_irq       = r8a7779_init_irq_dt,
+        .init_machine   = r8a7779_add_standard_devices_dt,
+        .init_time      = shmobile_timer_init,
+        .dt_compat      = r8a7779_compat_dt,
+MACHINE_END
+#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index bdab575f88bc..e8cd93a5c550 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -22,6 +22,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/irqchip.h>
 #include <linux/platform_device.h>
 #include <linux/of_platform.h>
 #include <linux/delay.h>
@@ -32,6 +33,7 @@
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
 #include <linux/platform_data/sh_ipmmu.h>
+#include <linux/platform_data/irq-renesas-intc-irqpin.h>
 #include <mach/dma-register.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
@@ -810,7 +812,128 @@ static struct platform_device ipmmu_device = {
         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 };
 
-static struct platform_device *sh73a0_early_devices_dt[] __initdata = {
+static struct renesas_intc_irqpin_config irqpin0_platform_data = {
+        .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
+};
+
+static struct resource irqpin0_resources[] = {
+        DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
+        DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
+        DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
+        DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
+        DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
+        DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
+        DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
+        DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
+        DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
+        DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
+        DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
+        DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
+        DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
+};
+
+static struct platform_device irqpin0_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 0,
+        .resource       = irqpin0_resources,
+        .num_resources  = ARRAY_SIZE(irqpin0_resources),
+        .dev            = {
+                .platform_data  = &irqpin0_platform_data,
+        },
+};
+
+static struct renesas_intc_irqpin_config irqpin1_platform_data = {
+        .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
+        .control_parent = true, /* Disable spurious IRQ10 */
+};
+
+static struct resource irqpin1_resources[] = {
+        DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
+        DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
+        DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
+        DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
+        DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
+        DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
+        DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
+        DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
+        DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
+        DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
+        DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
+        DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
+        DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
+};
+
+static struct platform_device irqpin1_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 1,
+        .resource       = irqpin1_resources,
+        .num_resources  = ARRAY_SIZE(irqpin1_resources),
+        .dev            = {
+                .platform_data  = &irqpin1_platform_data,
+        },
+};
+
+static struct renesas_intc_irqpin_config irqpin2_platform_data = {
+        .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
+};
+
+static struct resource irqpin2_resources[] = {
+        DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
+        DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
+        DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
+        DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
+        DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
+        DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
+        DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
+        DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
+        DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
+        DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
+        DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
+        DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
+        DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
+};
+
+static struct platform_device irqpin2_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 2,
+        .resource       = irqpin2_resources,
+        .num_resources  = ARRAY_SIZE(irqpin2_resources),
+        .dev            = {
+                .platform_data  = &irqpin2_platform_data,
+        },
+};
+
+static struct renesas_intc_irqpin_config irqpin3_platform_data = {
+        .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
+};
+
+static struct resource irqpin3_resources[] = {
+        DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
+        DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
+        DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
+        DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
+        DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
+        DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
+        DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
+        DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
+        DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
+        DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
+        DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
+        DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
+        DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
+};
+
+static struct platform_device irqpin3_device = {
+        .name           = "renesas_intc_irqpin",
+        .id             = 3,
+        .resource       = irqpin3_resources,
+        .num_resources  = ARRAY_SIZE(irqpin3_resources),
+        .dev            = {
+                .platform_data  = &irqpin3_platform_data,
+        },
+};
+
+static struct platform_device *sh73a0_devices_dt[] __initdata = {
         &scif0_device,
         &scif1_device,
         &scif2_device,
@@ -838,6 +961,10 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
         &dma0_device,
         &mpdma0_device,
         &pmu_device,
+        &irqpin0_device,
+        &irqpin1_device,
+        &irqpin2_device,
+        &irqpin3_device,
 };
 
 #define SRCR2          IOMEM(0xe61580b0)
@@ -847,8 +974,8 @@ void __init sh73a0_add_standard_devices(void)
         /* Clear software reset bit on SY-DMAC module */
         __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
 
-        platform_add_devices(sh73a0_early_devices_dt,
-                            ARRAY_SIZE(sh73a0_early_devices_dt));
+        platform_add_devices(sh73a0_devices_dt,
+                            ARRAY_SIZE(sh73a0_devices_dt));
         platform_add_devices(sh73a0_early_devices,
                             ARRAY_SIZE(sh73a0_early_devices));
         platform_add_devices(sh73a0_late_devices,
@@ -867,8 +994,8 @@ void __init sh73a0_earlytimer_init(void)
 
 void __init sh73a0_add_early_devices(void)
 {
-        early_platform_add_devices(sh73a0_early_devices_dt,
-                                   ARRAY_SIZE(sh73a0_early_devices_dt));
+        early_platform_add_devices(sh73a0_devices_dt,
+                                   ARRAY_SIZE(sh73a0_devices_dt));
         early_platform_add_devices(sh73a0_early_devices,
                                    ARRAY_SIZE(sh73a0_early_devices));
 
@@ -878,23 +1005,9 @@ void __init sh73a0_add_early_devices(void)
 
 #ifdef CONFIG_USE_OF
 
-/* Please note that the clock initialisation shcheme used in
- * sh73a0_add_early_devices_dt() and sh73a0_add_standard_devices_dt()
- * does not work with SMP as there is a yet to be resolved lock-up in
- * workqueue initialisation.
- *
- * CONFIG_SMP should be disabled when using this code.
- */
-
-void __init sh73a0_add_early_devices_dt(void)
+void __init sh73a0_init_delay(void)
 {
         shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
-
-        early_platform_add_devices(sh73a0_early_devices_dt,
-                                   ARRAY_SIZE(sh73a0_early_devices_dt));
-
-        /* setup early console here as well */
-        shmobile_setup_console();
 }
 
 static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
@@ -906,8 +1019,8 @@ void __init sh73a0_add_standard_devices_dt(void)
         /* clocks are setup late during boot in the case of DT */
         sh73a0_clock_init();
 
-        platform_add_devices(sh73a0_early_devices_dt,
-                             ARRAY_SIZE(sh73a0_early_devices_dt));
+        platform_add_devices(sh73a0_devices_dt,
+                             ARRAY_SIZE(sh73a0_devices_dt));
         of_platform_populate(NULL, of_default_bus_match_table,
                              sh73a0_auxdata_lookup, NULL);
 }
@@ -918,10 +1031,11 @@ static const char *sh73a0_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
+        .smp            = smp_ops(sh73a0_smp_ops),
         .map_io         = sh73a0_map_io,
-        .init_early     = sh73a0_add_early_devices_dt,
+        .init_early     = sh73a0_init_delay,
         .nr_irqs        = NR_IRQS_LEGACY,
-        .init_irq       = sh73a0_init_irq_dt,
+        .init_irq       = irqchip_init,
         .init_machine   = sh73a0_add_standard_devices_dt,
         .init_time      = shmobile_timer_init,
         .dt_compat      = sh73a0_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 953eb1f9388d..e38691b4d0dd 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -23,100 +23,39 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/delay.h>
-#include <linux/irqchip/arm-gic.h>
 #include <mach/common.h>
 #include <mach/emev2.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
-#include <asm/cacheflush.h>
 
 #define EMEV2_SCU_BASE 0x1e000000
 
-static DEFINE_SPINLOCK(scu_lock);
-static void __iomem *scu_base;
-
-static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
-{
-        unsigned long tmp;
-
-        /* we assume this code is running on a different cpu
-         * than the one that is changing coherency setting */
-        spin_lock(&scu_lock);
-        tmp = readl(scu_base + 8);
-        tmp &= ~clr;
-        tmp |= set;
-        writel(tmp, scu_base + 8);
-        spin_unlock(&scu_lock);
-
-}
-
-static unsigned int __init emev2_get_core_count(void)
-{
-        if (!scu_base) {
-                scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
-                emev2_clock_init(); /* need ioremapped SMU */
-        }
-
-        WARN_ON_ONCE(!scu_base);
-
-        return scu_base ? scu_get_core_count(scu_base) : 1;
-}
-
-static int emev2_platform_cpu_kill(unsigned int cpu)
-{
-        return 0; /* not supported yet */
-}
-
-static int __maybe_unused emev2_cpu_kill(unsigned int cpu)
-{
-        int k;
-
-        /* this function is running on another CPU than the offline target,
-         * here we need wait for shutdown code in platform_cpu_die() to
-         * finish before asking SoC-specific code to power off the CPU core.
-         */
-        for (k = 0; k < 1000; k++) {
-                if (shmobile_cpu_is_dead(cpu))
-                        return emev2_platform_cpu_kill(cpu);
-                mdelay(1);
-        }
-
-        return 0;
-}
-
-
-static void __cpuinit emev2_secondary_init(unsigned int cpu)
-{
-        gic_secondary_init(0);
-}
-
 static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        cpu = cpu_logical_map(cpu);
-
-        /* enable cache coherency */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
-
-        /* Tell ROM loader about our vector (in headsmp.S) */
-        emev2_set_boot_vector(__pa(shmobile_secondary_vector));
-
-        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu)));
         return 0;
 }
 
 static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
 {
-        int cpu = cpu_logical_map(0);
+        scu_enable(shmobile_scu_base);
 
-        scu_enable(scu_base);
+        /* Tell ROM loader about our vector (in headsmp-scu.S) */
+        emev2_set_boot_vector(__pa(shmobile_secondary_vector_scu));
 
-        /* enable cache coherency on CPU0 */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
+        /* enable cache coherency on booting CPU */
+        scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
 }
 
 static void __init emev2_smp_init_cpus(void)
 {
-        unsigned int ncores = emev2_get_core_count();
+        unsigned int ncores;
+
+        /* setup EMEV2 specific SCU base */
+        shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
+        emev2_clock_init(); /* need ioremapped SMU */
+
+        ncores = shmobile_scu_base ? scu_get_core_count(shmobile_scu_base) : 1;
 
         shmobile_smp_init_cpus(ncores);
 }
@@ -124,11 +63,5 @@ static void __init emev2_smp_init_cpus(void)
 struct smp_operations emev2_smp_ops __initdata = {
         .smp_init_cpus          = emev2_smp_init_cpus,
         .smp_prepare_cpus       = emev2_smp_prepare_cpus,
-        .smp_secondary_init     = emev2_secondary_init,
         .smp_boot_secondary     = emev2_boot_secondary,
-#ifdef CONFIG_HOTPLUG_CPU
-        .cpu_kill               = emev2_cpu_kill,
-        .cpu_die                = shmobile_cpu_die,
-        .cpu_disable            = shmobile_cpu_disable,
-#endif
 };
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 3a4acf23edcf..a853bf182ed5 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -23,14 +23,15 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/delay.h>
-#include <linux/irqchip/arm-gic.h>
 #include <mach/common.h>
 #include <mach/r8a7779.h>
+#include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <asm/smp_twd.h>
 
 #define AVECR IOMEM(0xfe700040)
+#define R8A7779_SCU_BASE 0xf0000000
 
 static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
         .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
@@ -56,44 +57,14 @@ static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = {
         [3] = &r8a7779_ch_cpu3,
 };
 
-static void __iomem *scu_base_addr(void)
-{
-        return (void __iomem *)0xf0000000;
-}
-
-static DEFINE_SPINLOCK(scu_lock);
-static unsigned long tmp;
-
 #ifdef CONFIG_HAVE_ARM_TWD
-static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
-
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29);
 void __init r8a7779_register_twd(void)
 {
         twd_local_timer_register(&twd_local_timer);
 }
 #endif
 
-static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
-{
-        void __iomem *scu_base = scu_base_addr();
-
-        spin_lock(&scu_lock);
-        tmp = __raw_readl(scu_base + 8);
-        tmp &= ~clr;
-        tmp |= set;
-        spin_unlock(&scu_lock);
-
-        /* disable cache coherency after releasing the lock */
-        __raw_writel(tmp, scu_base + 8);
-}
-
-static unsigned int __init r8a7779_get_core_count(void)
-{
-        void __iomem *scu_base = scu_base_addr();
-
-        return scu_get_core_count(scu_base);
-}
-
 static int r8a7779_platform_cpu_kill(unsigned int cpu)
 {
         struct r8a7779_pm_ch *ch = NULL;
@@ -101,9 +72,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
 
         cpu = cpu_logical_map(cpu);
 
-        /* disable cache coherency */
-        modify_scu_cpu_psr(3 << (cpu * 8), 0);
-
         if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
                 ch = r8a7779_ch_cpu[cpu];
 
@@ -113,30 +81,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
         return ret ? ret : 1;
 }
 
-static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu)
-{
-        int k;
-
-        /* this function is running on another CPU than the offline target,
-         * here we need wait for shutdown code in platform_cpu_die() to
-         * finish before asking SoC-specific code to power off the CPU core.
-         */
-        for (k = 0; k < 1000; k++) {
-                if (shmobile_cpu_is_dead(cpu))
-                        return r8a7779_platform_cpu_kill(cpu);
-
-                mdelay(1);
-        }
-
-        return 0;
-}
-
-
-static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
-{
-        gic_secondary_init(0);
-}
-
 static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         struct r8a7779_pm_ch *ch = NULL;
@@ -144,9 +88,6 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
 
         cpu = cpu_logical_map(cpu);
 
-        /* enable cache coherency */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
-
         if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
                 ch = r8a7779_ch_cpu[cpu];
 
@@ -158,15 +99,13 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
 
 static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
 {
-        int cpu = cpu_logical_map(0);
-
-        scu_enable(scu_base_addr());
+        scu_enable(shmobile_scu_base);
 
-        /* Map the reset vector (in headsmp.S) */
-        __raw_writel(__pa(shmobile_secondary_vector), AVECR);
+        /* Map the reset vector (in headsmp-scu.S) */
+        __raw_writel(__pa(shmobile_secondary_vector_scu), AVECR);
 
-        /* enable cache coherency on CPU0 */
-        modify_scu_cpu_psr(0, 3 << (cpu * 8));
+        /* enable cache coherency on booting CPU */
+        scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
 
         r8a7779_pm_init();
 
@@ -178,19 +117,68 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
 
 static void __init r8a7779_smp_init_cpus(void)
 {
-        unsigned int ncores = r8a7779_get_core_count();
+        /* setup r8a7779 specific SCU base */
+        shmobile_scu_base = IOMEM(R8A7779_SCU_BASE);
+
+        shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+static int r8a7779_scu_psr_core_disabled(int cpu)
+{
+        unsigned long mask = 3 << (cpu * 8);
+
+        if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask)
+                return 1;
+
+        return 0;
+}
+
+static int r8a7779_cpu_kill(unsigned int cpu)
+{
+        int k;
 
-        shmobile_smp_init_cpus(ncores);
+        /* this function is running on another CPU than the offline target,
+         * here we need wait for shutdown code in platform_cpu_die() to
+         * finish before asking SoC-specific code to power off the CPU core.
+         */
+        for (k = 0; k < 1000; k++) {
+                if (r8a7779_scu_psr_core_disabled(cpu))
+                        return r8a7779_platform_cpu_kill(cpu);
+
+                mdelay(1);
+        }
+
+        return 0;
+}
+
+static void r8a7779_cpu_die(unsigned int cpu)
+{
+        dsb();
+        flush_cache_all();
+
+        /* disable cache coherency */
+        scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
+
+        /* Endless loop until power off from r8a7779_cpu_kill() */
+        while (1)
+                cpu_do_idle();
+}
+
+static int r8a7779_cpu_disable(unsigned int cpu)
+{
+        /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */
+        return cpu == 0 ? -EPERM : 0;
 }
+#endif /* CONFIG_HOTPLUG_CPU */
 
 struct smp_operations r8a7779_smp_ops  __initdata = {
         .smp_init_cpus          = r8a7779_smp_init_cpus,
         .smp_prepare_cpus       = r8a7779_smp_prepare_cpus,
-        .smp_secondary_init     = r8a7779_secondary_init,
         .smp_boot_secondary     = r8a7779_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_kill               = r8a7779_cpu_kill,
-        .cpu_die                = shmobile_cpu_die,
-        .cpu_disable            = shmobile_cpu_disable,
+        .cpu_die                = r8a7779_cpu_die,
+        .cpu_disable            = r8a7779_cpu_disable,
 #endif
 };
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index acb46a94ccdf..496592b6c763 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -23,7 +23,6 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/delay.h>
-#include <linux/irqchip/arm-gic.h>
 #include <mach/common.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
@@ -39,31 +38,16 @@
 
 #define PSTR_SHUTDOWN_MODE      3
 
-static void __iomem *scu_base_addr(void)
-{
-        return (void __iomem *)0xf0000000;
-}
+#define SH73A0_SCU_BASE 0xf0000000
 
 #ifdef CONFIG_HAVE_ARM_TWD
-static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
+static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29);
 void __init sh73a0_register_twd(void)
 {
         twd_local_timer_register(&twd_local_timer);
 }
 #endif
 
-static unsigned int __init sh73a0_get_core_count(void)
-{
-        void __iomem *scu_base = scu_base_addr();
-
-        return scu_get_core_count(scu_base);
-}
-
-static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
-{
-        gic_secondary_init(0);
-}
-
 static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         cpu = cpu_logical_map(cpu);
@@ -78,21 +62,22 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
 
 static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
 {
-        scu_enable(scu_base_addr());
+        scu_enable(shmobile_scu_base);
 
-        /* Map the reset vector (in headsmp-sh73a0.S) */
+        /* Map the reset vector (in headsmp-scu.S) */
         __raw_writel(0, APARMBAREA);      /* 4k */
-        __raw_writel(__pa(sh73a0_secondary_vector), SBAR);
+        __raw_writel(__pa(shmobile_secondary_vector_scu), SBAR);
 
         /* enable cache coherency on booting CPU */
-        scu_power_mode(scu_base_addr(), SCU_PM_NORMAL);
+        scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
 }
 
 static void __init sh73a0_smp_init_cpus(void)
 {
-        unsigned int ncores = sh73a0_get_core_count();
+        /* setup sh73a0 specific SCU base */
+        shmobile_scu_base = IOMEM(SH73A0_SCU_BASE);
 
-        shmobile_smp_init_cpus(ncores);
+        shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
@@ -119,30 +104,26 @@ static int sh73a0_cpu_kill(unsigned int cpu)
 
 static void sh73a0_cpu_die(unsigned int cpu)
 {
-        /*
-         * The ARM MPcore does not issue a cache coherency request for the L1
-         * cache when powering off single CPUs. We must take care of this and
-         * further caches.
-         */
-        dsb();
-        flush_cache_all();
-
         /* Set power off mode. This takes the CPU out of the MP cluster */
-        scu_power_mode(scu_base_addr(), SCU_PM_POWEROFF);
+        scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
 
         /* Enter shutdown mode */
         cpu_do_idle();
 }
+
+static int sh73a0_cpu_disable(unsigned int cpu)
+{
+        return 0; /* CPU0 and CPU1 supported */
+}
 #endif /* CONFIG_HOTPLUG_CPU */
 
 struct smp_operations sh73a0_smp_ops __initdata = {
         .smp_init_cpus          = sh73a0_smp_init_cpus,
         .smp_prepare_cpus       = sh73a0_smp_prepare_cpus,
-        .smp_secondary_init     = sh73a0_secondary_init,
         .smp_boot_secondary     = sh73a0_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_kill               = sh73a0_cpu_kill,
         .cpu_die                = sh73a0_cpu_die,
-        .cpu_disable            = shmobile_cpu_disable_any,
+        .cpu_disable            = sh73a0_cpu_disable,
 #endif
 };
diff --git a/arch/arm/mach-shmobile/suspend.c b/arch/arm/mach-shmobile/suspend.c
index 47d83f7a70b6..5d92b5dd486b 100644
--- a/arch/arm/mach-shmobile/suspend.c
+++ b/arch/arm/mach-shmobile/suspend.c
@@ -12,6 +12,8 @@
 #include <linux/suspend.h>
 #include <linux/module.h>
 #include <linux/err.h>
+#include <linux/cpu.h>
+
 #include <asm/io.h>
 #include <asm/system_misc.h>
 
@@ -23,13 +25,13 @@ static int shmobile_suspend_default_enter(suspend_state_t suspend_state)
 
 static int shmobile_suspend_begin(suspend_state_t state)
 {
-        disable_hlt();
+        cpu_idle_poll_ctrl(true);
         return 0;
 }
 
 static void shmobile_suspend_end(void)
 {
-        enable_hlt();
+        cpu_idle_poll_ctrl(false);
 }
 
 struct platform_suspend_ops shmobile_suspend_ops = {
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 315edff610f2..572b8f719ffb 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -20,12 +20,23 @@
 #ifndef __MACH_CORE_H
 #define __MACH_CORE_H
 
+#define SOCFPGA_RSTMGR_CTRL     0x04
+#define SOCFPGA_RSTMGR_MODPERRST        0x14
+#define SOCFPGA_RSTMGR_BRGMODRST        0x1c
+
+/* System Manager bits */
+#define RSTMGR_CTRL_SWCOLDRSTREQ        0x1     /* Cold Reset */
+#define RSTMGR_CTRL_SWWARMRSTREQ        0x2     /* Warm Reset */
+
 extern void socfpga_secondary_startup(void);
 extern void __iomem *socfpga_scu_base_addr;
 
 extern void socfpga_init_clocks(void);
 extern void socfpga_sysmgr_init(void);
 
+extern void __iomem *sys_manager_base_addr;
+extern void __iomem *rst_manager_base_addr;
+
 extern struct smp_operations socfpga_smp_ops;
 extern char secondary_trampoline, secondary_trampoline_end;
 
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 84c60fa8daa0..b51ce8c7929d 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -22,7 +22,6 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/irqchip/arm-gic.h>
 
 #include <asm/cacheflush.h>
 #include <asm/smp_scu.h>
@@ -30,19 +29,6 @@
 
 #include "core.h"
 
-extern void __iomem *sys_manager_base_addr;
-extern void __iomem *rst_manager_base_addr;
-
-static void __cpuinit socfpga_secondary_init(unsigned int cpu)
-{
-        /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-}
-
 static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
@@ -109,7 +95,6 @@ static void socfpga_cpu_die(unsigned int cpu)
 struct smp_operations socfpga_smp_ops __initdata = {
         .smp_init_cpus          = socfpga_smp_init_cpus,
         .smp_prepare_cpus       = socfpga_smp_prepare_cpus,
-        .smp_secondary_init     = socfpga_secondary_init,
         .smp_boot_secondary     = socfpga_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_die                = socfpga_cpu_die,
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 1042c023cf24..46a051359f02 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -15,6 +15,7 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 #include <linux/dw_apb_timer.h>
+#include <linux/clk-provider.h>
 #include <linux/irqchip.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
@@ -29,6 +30,7 @@
 void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
 void __iomem *sys_manager_base_addr;
 void __iomem *rst_manager_base_addr;
+void __iomem *clk_mgr_base_addr;
 unsigned long cpu1start_addr;
 
 static struct map_desc scu_io_desc __initdata = {
@@ -77,6 +79,9 @@ void __init socfpga_sysmgr_init(void)
 
         np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
         rst_manager_base_addr = of_iomap(np, 0);
+
+        np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
+        clk_mgr_base_addr = of_iomap(np, 0);
 }
 
 static void __init socfpga_init_irq(void)
@@ -87,13 +92,22 @@ static void __init socfpga_init_irq(void)
 
 static void socfpga_cyclone5_restart(char mode, const char *cmd)
 {
-        /* TODO: */
+        u32 temp;
+
+        temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
+
+        if (mode == 'h')
+                temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
+        else
+                temp |= RSTMGR_CTRL_SWWARMRSTREQ;
+        writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
 }
 
 static void __init socfpga_cyclone5_init(void)
 {
         l2x0_of_init(0, ~0UL);
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        of_clk_init(NULL);
         socfpga_init_clocks();
 }
 
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
new file mode 100644
index 000000000000..442917eedff3
--- /dev/null
+++ b/arch/arm/mach-spear/Kconfig
@@ -0,0 +1,105 @@
+#
+# SPEAr Platform configuration file
+#
+
+menuconfig PLAT_SPEAR
+        bool "ST SPEAr Family" if ARCH_MULTI_V7 || ARCH_MULTI_V5
+        default PLAT_SPEAR_SINGLE
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_AMBA
+        select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
+        select COMMON_CLK
+        select GENERIC_CLOCKEVENTS
+        select HAVE_CLK
+
+if PLAT_SPEAR
+
+config ARCH_SPEAR13XX
+        bool "ST SPEAr13xx"
+        depends on ARCH_MULTI_V7 || PLAT_SPEAR_SINGLE
+        select ARCH_HAS_CPUFREQ
+        select ARM_GIC
+        select CPU_V7
+        select GPIO_SPEAR_SPICS
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_SMP
+        select MIGHT_HAVE_CACHE_L2X0
+        select PINCTRL
+        select USE_OF
+        help
+          Supports for ARM's SPEAR13XX family
+
+if ARCH_SPEAR13XX
+
+config MACH_SPEAR1310
+        bool "SPEAr1310 Machine support with Device Tree"
+        select PINCTRL_SPEAR1310
+        help
+          Supports ST SPEAr1310 machine configured via the device-tree
+
+config MACH_SPEAR1340
+        bool "SPEAr1340 Machine support with Device Tree"
+        select PINCTRL_SPEAR1340
+        help
+          Supports ST SPEAr1340 machine configured via the device-tree
+
+endif #ARCH_SPEAR13XX
+
+config ARCH_SPEAR3XX
+        bool "ST SPEAr3xx"
+        depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
+        depends on !ARCH_SPEAR13XX
+        select ARM_VIC
+        select CPU_ARM926T
+        select PINCTRL
+        select USE_OF
+        help
+          Supports for ARM's SPEAR3XX family
+
+if ARCH_SPEAR3XX
+
+config MACH_SPEAR300
+        bool "SPEAr300 Machine support with Device Tree"
+        select PINCTRL_SPEAR300
+        help
+          Supports ST SPEAr300 machine configured via the device-tree
+
+config MACH_SPEAR310
+        bool "SPEAr310 Machine support with Device Tree"
+        select PINCTRL_SPEAR310
+        help
+          Supports ST SPEAr310 machine configured via the device-tree
+
+config MACH_SPEAR320
+        bool "SPEAr320 Machine support with Device Tree"
+        select PINCTRL_SPEAR320
+        help
+          Supports ST SPEAr320 machine configured via the device-tree
+
+endif
+
+config ARCH_SPEAR6XX
+        bool "ST SPEAr6XX"
+        depends on ARCH_MULTI_V5 || PLAT_SPEAR_SINGLE
+        depends on !ARCH_SPEAR13XX
+        select ARM_VIC
+        select CPU_ARM926T
+        help
+          Supports for ARM's SPEAR6XX family
+
+config MACH_SPEAR600
+        def_bool y
+        depends on ARCH_SPEAR6XX
+        select USE_OF
+        help
+          Supports ST SPEAr600 boards configured via the device-treesource "arch/arm/mach-spear6xx/Kconfig"
+
+config ARCH_SPEAR_AUTO
+        def_bool PLAT_SPEAR_SINGLE
+        depends on !ARCH_SPEAR13XX && !ARCH_SPEAR6XX
+        select ARCH_SPEAR3XX
+
+endif
+
diff --git a/arch/arm/mach-spear/Makefile b/arch/arm/mach-spear/Makefile
new file mode 100644
index 000000000000..af9bffb94f1c
--- /dev/null
+++ b/arch/arm/mach-spear/Makefile
@@ -0,0 +1,26 @@
+#
+# SPEAr Platform specific Makefile
+#
+
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+
+# Common support
+obj-y   := restart.o time.o
+
+obj-$(CONFIG_SMP)               += headsmp.o platsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
+
+obj-$(CONFIG_ARCH_SPEAR13XX)    += spear13xx.o
+obj-$(CONFIG_MACH_SPEAR1310)    += spear1310.o
+obj-$(CONFIG_MACH_SPEAR1340)    += spear1340.o
+
+obj-$(CONFIG_ARCH_SPEAR3XX)     += spear3xx.o
+obj-$(CONFIG_ARCH_SPEAR3XX)     += pl080.o
+obj-$(CONFIG_MACH_SPEAR300)     += spear300.o
+obj-$(CONFIG_MACH_SPEAR310)     += spear310.o
+obj-$(CONFIG_MACH_SPEAR320)     += spear320.o
+
+obj-$(CONFIG_ARCH_SPEAR6XX)     += spear6xx.o
+obj-$(CONFIG_ARCH_SPEAR6XX)     += pl080.o
+
+CFLAGS_hotplug.o                += -march=armv7-a
diff --git a/arch/arm/mach-spear13xx/Makefile.boot b/arch/arm/mach-spear/Makefile.boot
index 4674a4c221db..4674a4c221db 100644
--- a/arch/arm/mach-spear13xx/Makefile.boot
+++ b/arch/arm/mach-spear/Makefile.boot
diff --git a/arch/arm/mach-spear13xx/include/mach/generic.h b/arch/arm/mach-spear/generic.h
index 633e678e01a3..8ba7e75b648d 100644
--- a/arch/arm/mach-spear13xx/include/mach/generic.h
+++ b/arch/arm/mach-spear/generic.h
@@ -1,9 +1,8 @@
 /*
- * arch/arm/mach-spear13xx/include/mach/generic.h
+ * spear machine family generic header file
  *
- * spear13xx machine family generic header file
- *
- * Copyright (C) 2012 ST Microelectronics
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Rajeev Kumar <rajeev-dlh.kumar@st.com>
  * Viresh Kumar <viresh.linux@gmail.com>
  *
  * This file is licensed under the terms of the GNU General Public
@@ -15,37 +14,46 @@
 #define __MACH_GENERIC_H
 
 #include <linux/dmaengine.h>
+#include <linux/amba/pl08x.h>
+#include <linux/init.h>
 #include <asm/mach/time.h>
 
-/* Add spear13xx structure declarations here */
 extern void spear13xx_timer_init(void);
+extern void spear3xx_timer_init(void);
 extern struct pl022_ssp_controller pl022_plat_data;
+extern struct pl08x_platform_data pl080_plat_data;
 extern struct dw_dma_platform_data dmac_plat_data;
 extern struct dw_dma_slave cf_dma_priv;
 extern struct dw_dma_slave nand_read_dma_priv;
 extern struct dw_dma_slave nand_write_dma_priv;
+bool dw_dma_filter(struct dma_chan *chan, void *slave);
 
-/* Add spear13xx family function declarations here */
 void __init spear_setup_of_timer(void);
+void __init spear3xx_clk_init(void __iomem *misc_base,
+                              void __iomem *soc_config_base);
+void __init spear3xx_map_io(void);
+void __init spear3xx_dt_init_irq(void);
+void __init spear6xx_clk_init(void __iomem *misc_base);
 void __init spear13xx_map_io(void);
 void __init spear13xx_l2x0_init(void);
-bool dw_dma_filter(struct dma_chan *chan, void *slave);
+
 void spear_restart(char, const char *);
+
 void spear13xx_secondary_startup(void);
 void __cpuinit spear13xx_cpu_die(unsigned int cpu);
 
 extern struct smp_operations spear13xx_smp_ops;
 
 #ifdef CONFIG_MACH_SPEAR1310
-void __init spear1310_clk_init(void);
+void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base);
 #else
-static inline void spear1310_clk_init(void) {}
+static inline void spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) {}
 #endif
 
 #ifdef CONFIG_MACH_SPEAR1340
-void __init spear1340_clk_init(void);
+void __init spear1340_clk_init(void __iomem *misc_base);
 #else
-static inline void spear1340_clk_init(void) {}
+static inline void spear1340_clk_init(void __iomem *misc_base) {}
 #endif
 
 #endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear13xx/headsmp.S b/arch/arm/mach-spear/headsmp.S
index ed85473a047f..ed85473a047f 100644
--- a/arch/arm/mach-spear13xx/headsmp.S
+++ b/arch/arm/mach-spear/headsmp.S
diff --git a/arch/arm/mach-spear13xx/hotplug.c b/arch/arm/mach-spear/hotplug.c
index a7d2dd11a4f2..d97749c642ce 100644
--- a/arch/arm/mach-spear13xx/hotplug.c
+++ b/arch/arm/mach-spear/hotplug.c
@@ -13,7 +13,6 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/smp.h>
-#include <asm/cacheflush.h>
 #include <asm/cp15.h>
 #include <asm/smp_plat.h>
 
@@ -21,7 +20,6 @@ static inline void cpu_enter_lowpower(void)
 {
         unsigned int v;
 
-        flush_cache_all();
         asm volatile(
         "       mcr     p15, 0, %1, c7, c5, 0\n"
         "       dsb\n"
diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/mach-spear/include/mach/debug-macro.S
index 75b05ad0fbad..75b05ad0fbad 100644
--- a/arch/arm/plat-spear/include/plat/debug-macro.S
+++ b/arch/arm/mach-spear/include/mach/debug-macro.S
diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear/include/mach/irqs.h
index 37a5c411a866..92da0a8c6bce 100644
--- a/arch/arm/mach-spear6xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear/include/mach/irqs.h
@@ -1,10 +1,9 @@
 /*
- * arch/arm/mach-spear6xx/include/mach/irqs.h
+ * IRQ helper macros for spear machine family
  *
- * IRQ helper macros for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ * Copyright (C) 2009-2012 ST Microelectronics
+ * Rajeev Kumar <rajeev-dlh.kumar@st.com>
+ * Viresh Kumar <viresh.linux@gmail.com>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
@@ -14,6 +13,11 @@
 #ifndef __MACH_IRQS_H
 #define __MACH_IRQS_H
 
+#ifdef CONFIG_ARCH_SPEAR3XX
+#define NR_IRQS                 256
+#endif
+
+#ifdef CONFIG_ARCH_SPEAR6XX
 /* IRQ definitions */
 /* VIC 1 */
 #define IRQ_VIC_END                             64
@@ -21,5 +25,11 @@
 /* GPIO pins virtual irqs */
 #define VIRTUAL_IRQS                            24
 #define NR_IRQS                                 (IRQ_VIC_END + VIRTUAL_IRQS)
+#endif
+
+#ifdef CONFIG_ARCH_SPEAR13XX
+#define IRQ_GIC_END                     160
+#define NR_IRQS                         IRQ_GIC_END
+#endif
 
-#endif  /* __MACH_IRQS_H */
+#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear/include/mach/misc_regs.h
index 6309bf68d6f8..935639ce59ba 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear/include/mach/misc_regs.h
@@ -16,7 +16,7 @@
 
 #include <mach/spear.h>
 
-#define MISC_BASE               IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
+#define MISC_BASE               (VA_SPEAR_ICM3_MISC_REG_BASE)
 #define DMA_CHN_CFG             (MISC_BASE + 0x0A0)
 
 #endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
new file mode 100644
index 000000000000..374ddc393df1
--- /dev/null
+++ b/arch/arm/mach-spear/include/mach/spear.h
@@ -0,0 +1,95 @@
+/*
+ * SPEAr3xx/6xx Machine family specific definition
+ *
+ * Copyright (C) 2009,2012 ST Microelectronics
+ * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ * Viresh Kumar <viresh.linux@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SPEAR_H
+#define __MACH_SPEAR_H
+
+#include <asm/memory.h>
+
+#if defined(CONFIG_ARCH_SPEAR3XX) || defined (CONFIG_ARCH_SPEAR6XX)
+
+/* ICM1 - Low speed connection */
+#define SPEAR_ICM1_2_BASE               UL(0xD0000000)
+#define VA_SPEAR_ICM1_2_BASE            IOMEM(0xFD000000)
+#define SPEAR_ICM1_UART_BASE            UL(0xD0000000)
+#define VA_SPEAR_ICM1_UART_BASE         (VA_SPEAR_ICM1_2_BASE - SPEAR_ICM1_2_BASE + SPEAR_ICM1_UART_BASE)
+#define SPEAR3XX_ICM1_SSP_BASE          UL(0xD0100000)
+
+/* ML-1, 2 - Multi Layer CPU Subsystem */
+#define SPEAR_ICM3_ML1_2_BASE           UL(0xF0000000)
+#define VA_SPEAR6XX_ML_CPU_BASE         IOMEM(0xF0000000)
+
+/* ICM3 - Basic Subsystem */
+#define SPEAR_ICM3_SMI_CTRL_BASE        UL(0xFC000000)
+#define VA_SPEAR_ICM3_SMI_CTRL_BASE     IOMEM(0xFC000000)
+#define SPEAR_ICM3_DMA_BASE             UL(0xFC400000)
+#define SPEAR_ICM3_SYS_CTRL_BASE        UL(0xFCA00000)
+#define VA_SPEAR_ICM3_SYS_CTRL_BASE     (VA_SPEAR_ICM3_SMI_CTRL_BASE - SPEAR_ICM3_SMI_CTRL_BASE + SPEAR_ICM3_SYS_CTRL_BASE)
+#define SPEAR_ICM3_MISC_REG_BASE        UL(0xFCA80000)
+#define VA_SPEAR_ICM3_MISC_REG_BASE     (VA_SPEAR_ICM3_SMI_CTRL_BASE - SPEAR_ICM3_SMI_CTRL_BASE + SPEAR_ICM3_MISC_REG_BASE)
+
+/* Debug uart for linux, will be used for debug and uncompress messages */
+#define SPEAR_DBG_UART_BASE             SPEAR_ICM1_UART_BASE
+#define VA_SPEAR_DBG_UART_BASE          VA_SPEAR_ICM1_UART_BASE
+
+/* Sysctl base for spear platform */
+#define SPEAR_SYS_CTRL_BASE             SPEAR_ICM3_SYS_CTRL_BASE
+#define VA_SPEAR_SYS_CTRL_BASE          VA_SPEAR_ICM3_SYS_CTRL_BASE
+#endif /* SPEAR3xx || SPEAR6XX */
+
+/* SPEAr320 Macros */
+#define SPEAR320_SOC_CONFIG_BASE        UL(0xB3000000)
+#define VA_SPEAR320_SOC_CONFIG_BASE     IOMEM(0xFE000000)
+
+#ifdef CONFIG_ARCH_SPEAR13XX
+
+#define PERIP_GRP2_BASE                         UL(0xB3000000)
+#define VA_PERIP_GRP2_BASE                      IOMEM(0xFE000000)
+#define MCIF_SDHCI_BASE                         UL(0xB3000000)
+#define SYSRAM0_BASE                            UL(0xB3800000)
+#define VA_SYSRAM0_BASE                         IOMEM(0xFE800000)
+#define SYS_LOCATION                            (VA_SYSRAM0_BASE + 0x600)
+
+#define PERIP_GRP1_BASE                         UL(0xE0000000)
+#define VA_PERIP_GRP1_BASE                      IOMEM(0xFD000000)
+#define UART_BASE                               UL(0xE0000000)
+#define VA_UART_BASE                            IOMEM(0xFD000000)
+#define SSP_BASE                                UL(0xE0100000)
+#define MISC_BASE                               UL(0xE0700000)
+#define VA_MISC_BASE                            IOMEM(0xFD700000)
+
+#define A9SM_AND_MPMC_BASE                      UL(0xEC000000)
+#define VA_A9SM_AND_MPMC_BASE                   IOMEM(0xFC000000)
+
+#define SPEAR1310_RAS_BASE                      UL(0xD8400000)
+#define VA_SPEAR1310_RAS_BASE                   IOMEM(UL(0xFA400000))
+
+/* A9SM peripheral offsets */
+#define A9SM_PERIP_BASE                         UL(0xEC800000)
+#define VA_A9SM_PERIP_BASE                      IOMEM(0xFC800000)
+#define VA_SCU_BASE                             (VA_A9SM_PERIP_BASE + 0x00)
+
+#define L2CC_BASE                               UL(0xED000000)
+#define VA_L2CC_BASE                            IOMEM(UL(0xFB000000))
+
+/* others */
+#define DMAC0_BASE                              UL(0xEA800000)
+#define DMAC1_BASE                              UL(0xEB000000)
+#define MCIF_CF_BASE                            UL(0xB2800000)
+
+/* Debug uart for linux, will be used for debug and uncompress messages */
+#define SPEAR_DBG_UART_BASE                     UART_BASE
+#define VA_SPEAR_DBG_UART_BASE                  VA_UART_BASE
+
+#endif /* SPEAR13XX */
+
+#endif /* __MACH_SPEAR_H */
diff --git a/arch/arm/plat-spear/include/plat/timex.h b/arch/arm/mach-spear/include/mach/timex.h
index ef95e5b780bd..ef95e5b780bd 100644
--- a/arch/arm/plat-spear/include/plat/timex.h
+++ b/arch/arm/mach-spear/include/mach/timex.h
diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/mach-spear/include/mach/uncompress.h
index 51b2dc93e4da..51b2dc93e4da 100644
--- a/arch/arm/plat-spear/include/plat/uncompress.h
+++ b/arch/arm/mach-spear/include/mach/uncompress.h
diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/mach-spear/pl080.c
index cfa1199d0f4a..cfa1199d0f4a 100644
--- a/arch/arm/plat-spear/pl080.c
+++ b/arch/arm/mach-spear/pl080.c
diff --git a/arch/arm/plat-spear/include/plat/pl080.h b/arch/arm/mach-spear/pl080.h
index eb6590ded40d..eb6590ded40d 100644
--- a/arch/arm/plat-spear/include/plat/pl080.h
+++ b/arch/arm/mach-spear/pl080.h
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear/platsmp.c
index af4ade61cd95..9c4c722c954e 100644
--- a/arch/arm/mach-spear13xx/platsmp.c
+++ b/arch/arm/mach-spear/platsmp.c
@@ -15,11 +15,10 @@
 #include <linux/jiffies.h>
 #include <linux/io.h>
 #include <linux/smp.h>
-#include <linux/irqchip/arm-gic.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_scu.h>
 #include <mach/spear.h>
-#include <mach/generic.h>
+#include "generic.h"
 
 static DEFINE_SPINLOCK(boot_lock);
 
@@ -28,13 +27,6 @@ static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
 static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
 {
         /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-
-        /*
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/mach-spear/restart.c
index 7d4616d5df11..2b44500bb718 100644
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/mach-spear/restart.c
@@ -14,7 +14,7 @@
 #include <linux/amba/sp810.h>
 #include <asm/system_misc.h>
 #include <mach/spear.h>
-#include <mach/generic.h>
+#include "generic.h"
 
 #define SPEAR13XX_SYS_SW_RES                    (VA_MISC_BASE + 0x204)
 void spear_restart(char mode, const char *cmd)
@@ -26,7 +26,8 @@ void spear_restart(char mode, const char *cmd)
                 /* hardware reset, Use on-chip reset capability */
 #ifdef CONFIG_ARCH_SPEAR13XX
                 writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES);
-#else
+#endif
+#if defined(CONFIG_ARCH_SPEAR3XX) || defined(CONFIG_ARCH_SPEAR6XX)
                 sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE);
 #endif
         }
diff --git a/arch/arm/mach-spear13xx/spear1310.c b/arch/arm/mach-spear/spear1310.c
index 56214d1076ef..ed3b5c287a7b 100644
--- a/arch/arm/mach-spear13xx/spear1310.c
+++ b/arch/arm/mach-spear/spear1310.c
@@ -19,7 +19,7 @@
 #include <linux/pata_arasan_cf_data.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/generic.h>
+#include "generic.h"
 #include <mach/spear.h>
 
 /* Base addresses */
@@ -30,8 +30,6 @@
 
 #define SPEAR1310_RAS_GRP1_BASE                 UL(0xD8000000)
 #define VA_SPEAR1310_RAS_GRP1_BASE              UL(0xFA000000)
-#define SPEAR1310_RAS_BASE                      UL(0xD8400000)
-#define VA_SPEAR1310_RAS_BASE                   IOMEM(UL(0xFA400000))
 
 static struct arasan_cf_pdata cf_pdata = {
         .cf_if_clk = CF_IF_CLK_166M,
diff --git a/arch/arm/mach-spear13xx/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 9a28beb2a113..75e38644bbfb 100644
--- a/arch/arm/mach-spear13xx/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -20,10 +20,11 @@
 #include <linux/of_platform.h>
 #include <linux/irqchip.h>
 #include <asm/mach/arch.h>
-#include <mach/dma.h>
-#include <mach/generic.h>
+#include "generic.h"
 #include <mach/spear.h>
 
+#include "spear13xx-dma.h"
+
 /* Base addresses */
 #define SPEAR1340_SATA_BASE                     UL(0xB1000000)
 #define SPEAR1340_UART1_BASE                    UL(0xB4100000)
diff --git a/arch/arm/mach-spear13xx/include/mach/dma.h b/arch/arm/mach-spear/spear13xx-dma.h
index d50bdb605925..d50bdb605925 100644
--- a/arch/arm/mach-spear13xx/include/mach/dma.h
+++ b/arch/arm/mach-spear/spear13xx-dma.h
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index c7d2b4a8d8cc..6dd208997176 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -15,16 +15,17 @@
 
 #include <linux/amba/pl022.h>
 #include <linux/clk.h>
+#include <linux/clocksource.h>
 #include <linux/dw_dmac.h>
 #include <linux/err.h>
 #include <linux/of.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
-#include <asm/smp_twd.h>
-#include <mach/dma.h>
-#include <mach/generic.h>
+#include "generic.h"
 #include <mach/spear.h>
 
+#include "spear13xx-dma.h"
+
 /* common dw_dma filter routine to be used by peripherals */
 bool dw_dma_filter(struct dma_chan *chan, void *slave)
 {
@@ -145,9 +146,9 @@ void __init spear13xx_map_io(void)
 static void __init spear13xx_clk_init(void)
 {
         if (of_machine_is_compatible("st,spear1310"))
-                spear1310_clk_init();
+                spear1310_clk_init(VA_MISC_BASE, VA_SPEAR1310_RAS_BASE);
         else if (of_machine_is_compatible("st,spear1340"))
-                spear1340_clk_init();
+                spear1340_clk_init(VA_MISC_BASE);
         else
                 pr_err("%s: Unknown machine\n", __func__);
 }
@@ -179,5 +180,5 @@ void __init spear13xx_timer_init(void)
         clk_put(pclk);
 
         spear_setup_of_timer();
-        twd_local_timer_of_register();
+        clocksource_of_init();
 }
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear/spear300.c
index bbc9b7e9c62c..bac56e845f7a 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear/spear300.c
@@ -17,7 +17,7 @@
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
-#include <mach/generic.h>
+#include "generic.h"
 #include <mach/spear.h>
 
 /* DMAC platform data's slave info */
@@ -185,7 +185,7 @@ struct pl08x_channel_data spear300_dma_info[] = {
 static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
                         &pl022_plat_data),
-        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+        OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
                         &pl080_plat_data),
         {}
 };
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear/spear310.c
index c13a434a8195..6ffbc63d516d 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear/spear310.c
@@ -18,7 +18,7 @@
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
-#include <mach/generic.h>
+#include "generic.h"
 #include <mach/spear.h>
 
 #define SPEAR310_UART1_BASE             UL(0xB2000000)
@@ -217,7 +217,7 @@ static struct amba_pl011_data spear310_uart_data[] = {
 static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
                         &pl022_plat_data),
-        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+        OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
                         &pl080_plat_data),
         OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
                         &spear310_uart_data[0]),
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear/spear320.c
index e1c77079a3e5..6eb3eec65f96 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear/spear320.c
@@ -19,7 +19,8 @@
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
-#include <mach/generic.h>
+#include <asm/mach/map.h>
+#include "generic.h"
 #include <mach/spear.h>
 
 #define SPEAR320_UART1_BASE             UL(0xA3000000)
@@ -222,7 +223,7 @@ static struct amba_pl011_data spear320_uart_data[] = {
 static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
                         &pl022_plat_data),
-        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+        OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
                         &pl080_plat_data),
         OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
                         &spear320_ssp_data[0]),
@@ -253,7 +254,7 @@ static const char * const spear320_dt_board_compat[] = {
 
 struct map_desc spear320_io_desc[] __initdata = {
         {
-                .virtual        = VA_SPEAR320_SOC_CONFIG_BASE,
+                .virtual        = (unsigned long)VA_SPEAR320_SOC_CONFIG_BASE,
                 .pfn            = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear/spear3xx.c
index d2b3937c4014..0227c97797cd 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear/spear3xx.c
@@ -15,10 +15,13 @@
 
 #include <linux/amba/pl022.h>
 #include <linux/amba/pl080.h>
+#include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/pl080.h>
-#include <mach/generic.h>
+#include <asm/mach/map.h>
+#include "pl080.h"
+#include "generic.h"
 #include <mach/spear.h>
+#include <mach/misc_regs.h>
 
 /* ssp device registration */
 struct pl022_ssp_controller pl022_plat_data = {
@@ -65,13 +68,13 @@ struct pl08x_platform_data pl080_plat_data = {
  */
 struct map_desc spear3xx_io_desc[] __initdata = {
         {
-                .virtual        = VA_SPEAR3XX_ICM1_2_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
+                .virtual        = (unsigned long)VA_SPEAR_ICM1_2_BASE,
+                .pfn            = __phys_to_pfn(SPEAR_ICM1_2_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
+                .virtual        = (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE,
+                .pfn            = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
         },
@@ -88,7 +91,7 @@ void __init spear3xx_timer_init(void)
         char pclk_name[] = "pll3_clk";
         struct clk *gpt_clk, *pclk;
 
-        spear3xx_clk_init();
+        spear3xx_clk_init(MISC_BASE, VA_SPEAR320_SOC_CONFIG_BASE);
 
         /* get the system timer clock */
         gpt_clk = clk_get_sys("gpt0", NULL);
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear/spear6xx.c
index 8904d8a52d84..ec8eefbbdfad 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear/spear6xx.c
@@ -24,9 +24,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <plat/pl080.h>
-#include <mach/generic.h>
+#include "pl080.h"
+#include "generic.h"
 #include <mach/spear.h>
+#include <mach/misc_regs.h>
 
 /* dmac device registration */
 static struct pl08x_channel_data spear600_dma_info[] = {
@@ -321,7 +322,7 @@ static struct pl08x_channel_data spear600_dma_info[] = {
         },
 };
 
-struct pl08x_platform_data pl080_plat_data = {
+static struct pl08x_platform_data spear6xx_pl080_plat_data = {
         .memcpy_channel = {
                 .bus_id = "memcpy",
                 .cctl_memcpy =
@@ -350,18 +351,18 @@ struct pl08x_platform_data pl080_plat_data = {
  */
 struct map_desc spear6xx_io_desc[] __initdata = {
         {
-                .virtual        = VA_SPEAR6XX_ML_CPU_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
+                .virtual        = (unsigned long)VA_SPEAR6XX_ML_CPU_BASE,
+                .pfn            = __phys_to_pfn(SPEAR_ICM3_ML1_2_BASE),
                 .length         = 2 * SZ_16M,
                 .type           = MT_DEVICE
         },      {
-                .virtual        = VA_SPEAR6XX_ICM1_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_ICM1_BASE),
+                .virtual        = (unsigned long)VA_SPEAR_ICM1_2_BASE,
+                .pfn            = __phys_to_pfn(SPEAR_ICM1_2_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
+                .virtual        = (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE,
+                .pfn            = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
         },
@@ -378,7 +379,7 @@ void __init spear6xx_timer_init(void)
         char pclk_name[] = "pll3_clk";
         struct clk *gpt_clk, *pclk;
 
-        spear6xx_clk_init();
+        spear6xx_clk_init(MISC_BASE);
 
         /* get the system timer clock */
         gpt_clk = clk_get_sys("gpt0", NULL);
@@ -404,8 +405,8 @@ void __init spear6xx_timer_init(void)
 
 /* Add auxdata to pass platform data */
 struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
-        OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
-                        &pl080_plat_data),
+        OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
+                        &spear6xx_pl080_plat_data),
         {}
 };
 
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/mach-spear/time.c
index bd5c53cd6962..d449673e40f7 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/mach-spear/time.c
@@ -23,7 +23,7 @@
 #include <linux/time.h>
 #include <linux/irq.h>
 #include <asm/mach/time.h>
-#include <mach/generic.h>
+#include "generic.h"
 
 /*
  * We would use TIMER0 and TIMER1 as clockevent and clocksource.
diff --git a/arch/arm/mach-spear13xx/Kconfig b/arch/arm/mach-spear13xx/Kconfig
deleted file mode 100644
index eaadc66d96b3..000000000000
--- a/arch/arm/mach-spear13xx/Kconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# SPEAr13XX Machine configuration file
-#
-
-if ARCH_SPEAR13XX
-
-menu "SPEAr13xx Implementations"
-config MACH_SPEAR1310
-        bool "SPEAr1310 Machine support with Device Tree"
-        select PINCTRL_SPEAR1310
-        help
-          Supports ST SPEAr1310 machine configured via the device-tree
-
-config MACH_SPEAR1340
-        bool "SPEAr1340 Machine support with Device Tree"
-        select PINCTRL_SPEAR1340
-        help
-          Supports ST SPEAr1340 machine configured via the device-tree
-endmenu
-endif #ARCH_SPEAR13XX
diff --git a/arch/arm/mach-spear13xx/Makefile b/arch/arm/mach-spear13xx/Makefile
deleted file mode 100644
index 3435ea78c15d..000000000000
--- a/arch/arm/mach-spear13xx/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Makefile for SPEAr13XX machine series
-#
-
-obj-$(CONFIG_SMP)               += headsmp.o platsmp.o
-obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
-
-obj-$(CONFIG_ARCH_SPEAR13XX)    += spear13xx.o
-obj-$(CONFIG_MACH_SPEAR1310)    += spear1310.o
-obj-$(CONFIG_MACH_SPEAR1340)    += spear1340.o
diff --git a/arch/arm/mach-spear13xx/include/mach/debug-macro.S b/arch/arm/mach-spear13xx/include/mach/debug-macro.S
deleted file mode 100644
index 9e3ae6bfe50d..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * arch/arm/mach-spear13xx/include/mach/debug-macro.S
- *
- * Debugging macro include header spear13xx machine family
- *
- * Copyright (C) 2012 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear13xx/include/mach/hardware.h b/arch/arm/mach-spear13xx/include/mach/hardware.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/hardware.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-spear13xx/include/mach/irqs.h b/arch/arm/mach-spear13xx/include/mach/irqs.h
deleted file mode 100644
index 271a62b4cd31..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/irqs.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-spear13xx/include/mach/irqs.h
- *
- * IRQ helper macros for spear13xx machine family
- *
- * Copyright (C) 2012 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-
-#define IRQ_GIC_END                     160
-#define NR_IRQS                         IRQ_GIC_END
-
-#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
deleted file mode 100644
index 7cfa6818865a..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/spear.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * arch/arm/mach-spear13xx/include/mach/spear.h
- *
- * spear13xx Machine family specific definition
- *
- * Copyright (C) 2012 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_SPEAR13XX_H
-#define __MACH_SPEAR13XX_H
-
-#include <asm/memory.h>
-
-#define PERIP_GRP2_BASE                         UL(0xB3000000)
-#define VA_PERIP_GRP2_BASE                      IOMEM(0xFE000000)
-#define MCIF_SDHCI_BASE                         UL(0xB3000000)
-#define SYSRAM0_BASE                            UL(0xB3800000)
-#define VA_SYSRAM0_BASE                         IOMEM(0xFE800000)
-#define SYS_LOCATION                            (VA_SYSRAM0_BASE + 0x600)
-
-#define PERIP_GRP1_BASE                         UL(0xE0000000)
-#define VA_PERIP_GRP1_BASE                      IOMEM(0xFD000000)
-#define UART_BASE                               UL(0xE0000000)
-#define VA_UART_BASE                            IOMEM(0xFD000000)
-#define SSP_BASE                                UL(0xE0100000)
-#define MISC_BASE                               UL(0xE0700000)
-#define VA_MISC_BASE                            IOMEM(0xFD700000)
-
-#define A9SM_AND_MPMC_BASE                      UL(0xEC000000)
-#define VA_A9SM_AND_MPMC_BASE                   IOMEM(0xFC000000)
-
-/* A9SM peripheral offsets */
-#define A9SM_PERIP_BASE                         UL(0xEC800000)
-#define VA_A9SM_PERIP_BASE                      IOMEM(0xFC800000)
-#define VA_SCU_BASE                             (VA_A9SM_PERIP_BASE + 0x00)
-
-#define L2CC_BASE                               UL(0xED000000)
-#define VA_L2CC_BASE                            IOMEM(UL(0xFB000000))
-
-/* others */
-#define DMAC0_BASE                              UL(0xEA800000)
-#define DMAC1_BASE                              UL(0xEB000000)
-#define MCIF_CF_BASE                            UL(0xB2800000)
-
-/* Debug uart for linux, will be used for debug and uncompress messages */
-#define SPEAR_DBG_UART_BASE                     UART_BASE
-#define VA_SPEAR_DBG_UART_BASE                  VA_UART_BASE
-
-#endif /* __MACH_SPEAR13XX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/timex.h b/arch/arm/mach-spear13xx/include/mach/timex.h
deleted file mode 100644
index 3a58b8284a6a..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/timex.h
- *
- * SPEAr3XX machine family specific timex definitions
- *
- * Copyright (C) 2012 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_TIMEX_H
-#define __MACH_TIMEX_H
-
-#include <plat/timex.h>
-
-#endif /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear13xx/include/mach/uncompress.h b/arch/arm/mach-spear13xx/include/mach/uncompress.h
deleted file mode 100644
index 70fe72f05dea..000000000000
--- a/arch/arm/mach-spear13xx/include/mach/uncompress.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear13xx/include/mach/uncompress.h
- *
- * Serial port stubs for kernel decompress status messages
- *
- * Copyright (C) 2012 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_UNCOMPRESS_H
-#define __MACH_UNCOMPRESS_H
-
-#include <plat/uncompress.h>
-
-#endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
deleted file mode 100644
index 8bd37291fa4f..000000000000
--- a/arch/arm/mach-spear3xx/Kconfig
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# SPEAr3XX Machine configuration file
-#
-
-if ARCH_SPEAR3XX
-
-menu "SPEAr3xx Implementations"
-config MACH_SPEAR300
-        bool "SPEAr300 Machine support with Device Tree"
-        select PINCTRL_SPEAR300
-        help
-          Supports ST SPEAr300 machine configured via the device-tree
-
-config MACH_SPEAR310
-        bool "SPEAr310 Machine support with Device Tree"
-        select PINCTRL_SPEAR310
-        help
-          Supports ST SPEAr310 machine configured via the device-tree
-
-config MACH_SPEAR320
-        bool "SPEAr320 Machine support with Device Tree"
-        select PINCTRL_SPEAR320
-        help
-          Supports ST SPEAr320 machine configured via the device-tree
-endmenu
-endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
deleted file mode 100644
index 8d12faa178fd..000000000000
--- a/arch/arm/mach-spear3xx/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Makefile for SPEAr3XX machine series
-#
-
-# common files
-obj-$(CONFIG_ARCH_SPEAR3XX)     += spear3xx.o
-
-# spear300 specific files
-obj-$(CONFIG_MACH_SPEAR300) += spear300.o
-
-# spear310 specific files
-obj-$(CONFIG_MACH_SPEAR310) += spear310.o
-
-# spear320 specific files
-obj-$(CONFIG_MACH_SPEAR320) += spear320.o
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
deleted file mode 100644
index 4674a4c221db..000000000000
--- a/arch/arm/mach-spear3xx/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
-zreladdr-y      += 0x00008000
-params_phys-y   := 0x00000100
-initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-spear3xx/include/mach/debug-macro.S b/arch/arm/mach-spear3xx/include/mach/debug-macro.S
deleted file mode 100644
index 0a6381fad5d9..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/debug-macro.S
- *
- * Debugging macro include header spear3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
deleted file mode 100644
index df310799e416..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/generic.h
- *
- * SPEAr3XX machine family generic header file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_GENERIC_H
-#define __MACH_GENERIC_H
-
-#include <linux/amba/pl08x.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/amba/bus.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-/* Add spear3xx family device structure declarations here */
-extern void spear3xx_timer_init(void);
-extern struct pl022_ssp_controller pl022_plat_data;
-extern struct pl08x_platform_data pl080_plat_data;
-
-/* Add spear3xx family function declarations here */
-void __init spear_setup_of_timer(void);
-void __init spear3xx_clk_init(void);
-void __init spear3xx_map_io(void);
-
-void spear_restart(char, const char *);
-
-#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
deleted file mode 100644
index f95e5b2b6686..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/irqs.h
- *
- * IRQ helper macros for SPEAr3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-
-#define NR_IRQS                 256
-
-#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
deleted file mode 100644
index 8cca95193d4d..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear.h
- *
- * SPEAr3xx Machine family specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_SPEAR3XX_H
-#define __MACH_SPEAR3XX_H
-
-#include <asm/memory.h>
-
-/* ICM1 - Low speed connection */
-#define SPEAR3XX_ICM1_2_BASE            UL(0xD0000000)
-#define VA_SPEAR3XX_ICM1_2_BASE         UL(0xFD000000)
-#define SPEAR3XX_ICM1_UART_BASE         UL(0xD0000000)
-#define VA_SPEAR3XX_ICM1_UART_BASE      (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
-#define SPEAR3XX_ICM1_SSP_BASE          UL(0xD0100000)
-
-/* ML1 - Multi Layer CPU Subsystem */
-#define SPEAR3XX_ICM3_ML1_2_BASE        UL(0xF0000000)
-#define VA_SPEAR6XX_ML_CPU_BASE         UL(0xF0000000)
-
-/* ICM3 - Basic Subsystem */
-#define SPEAR3XX_ICM3_SMI_CTRL_BASE     UL(0xFC000000)
-#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE  UL(0xFC000000)
-#define SPEAR3XX_ICM3_DMA_BASE          UL(0xFC400000)
-#define SPEAR3XX_ICM3_SYS_CTRL_BASE     UL(0xFCA00000)
-#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE  (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
-#define SPEAR3XX_ICM3_MISC_REG_BASE     UL(0xFCA80000)
-#define VA_SPEAR3XX_ICM3_MISC_REG_BASE  (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
-
-/* Debug uart for linux, will be used for debug and uncompress messages */
-#define SPEAR_DBG_UART_BASE             SPEAR3XX_ICM1_UART_BASE
-#define VA_SPEAR_DBG_UART_BASE          VA_SPEAR3XX_ICM1_UART_BASE
-
-/* Sysctl base for spear platform */
-#define SPEAR_SYS_CTRL_BASE             SPEAR3XX_ICM3_SYS_CTRL_BASE
-#define VA_SPEAR_SYS_CTRL_BASE          VA_SPEAR3XX_ICM3_SYS_CTRL_BASE
-
-/* SPEAr320 Macros */
-#define SPEAR320_SOC_CONFIG_BASE        UL(0xB3000000)
-#define VA_SPEAR320_SOC_CONFIG_BASE     UL(0xFE000000)
-#define SPEAR320_CONTROL_REG            IOMEM(VA_SPEAR320_SOC_CONFIG_BASE)
-#define SPEAR320_EXT_CTRL_REG           IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018)
-        #define SPEAR320_UARTX_PCLK_MASK                0x1
-        #define SPEAR320_UART2_PCLK_SHIFT               8
-        #define SPEAR320_UART3_PCLK_SHIFT               9
-        #define SPEAR320_UART4_PCLK_SHIFT               10
-        #define SPEAR320_UART5_PCLK_SHIFT               11
-        #define SPEAR320_UART6_PCLK_SHIFT               12
-        #define SPEAR320_RS485_PCLK_SHIFT               13
-
-#endif /* __MACH_SPEAR3XX_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/timex.h b/arch/arm/mach-spear3xx/include/mach/timex.h
deleted file mode 100644
index 9f5d08bd0c44..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/timex.h
- *
- * SPEAr3XX machine family specific timex definitions
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_TIMEX_H
-#define __MACH_TIMEX_H
-
-#include <plat/timex.h>
-
-#endif /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/uncompress.h b/arch/arm/mach-spear3xx/include/mach/uncompress.h
deleted file mode 100644
index b909b011f7c8..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/uncompress.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/uncompress.h
- *
- * Serial port stubs for kernel decompress status messages
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_UNCOMPRESS_H
-#define __MACH_UNCOMPRESS_H
-
-#include <plat/uncompress.h>
-
-#endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig
deleted file mode 100644
index 339f397dea70..000000000000
--- a/arch/arm/mach-spear6xx/Kconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# SPEAr6XX Machine configuration file
-#
-
-config MACH_SPEAR600
-        def_bool y
-        depends on ARCH_SPEAR6XX
-        select USE_OF
-        help
-          Supports ST SPEAr600 boards configured via the device-tree
diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
deleted file mode 100644
index 898831d93f37..000000000000
--- a/arch/arm/mach-spear6xx/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Makefile for SPEAr6XX machine series
-#
-
-# common files
-obj-y   += spear6xx.o
diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
deleted file mode 100644
index 4674a4c221db..000000000000
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
-zreladdr-y      += 0x00008000
-params_phys-y   := 0x00000100
-initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-spear6xx/include/mach/debug-macro.S b/arch/arm/mach-spear6xx/include/mach/debug-macro.S
deleted file mode 100644
index 0f3ea39edd96..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/debug-macro.S
- *
- * Debugging macro include header for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
deleted file mode 100644
index 65514b159370..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/generic.h
- *
- * SPEAr6XX machine family specific generic header file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_GENERIC_H
-#define __MACH_GENERIC_H
-
-#include <linux/init.h>
-
-void __init spear_setup_of_timer(void);
-void spear_restart(char, const char *);
-void __init spear6xx_clk_init(void);
-
-#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/hardware.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
deleted file mode 100644
index c34acc201d34..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/misc_regs.h
- *
- * Miscellaneous registers definitions for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_MISC_REGS_H
-#define __MACH_MISC_REGS_H
-
-#include <mach/spear.h>
-
-#define MISC_BASE               IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
-#define DMA_CHN_CFG             (MISC_BASE + 0x0A0)
-
-#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
deleted file mode 100644
index cb8ed2f4dc85..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/spear.h
- *
- * SPEAr6xx Machine family specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_SPEAR6XX_H
-#define __MACH_SPEAR6XX_H
-
-#include <asm/memory.h>
-
-/* ICM1 - Low speed connection */
-#define SPEAR6XX_ICM1_BASE              UL(0xD0000000)
-#define VA_SPEAR6XX_ICM1_BASE           UL(0xFD000000)
-#define SPEAR6XX_ICM1_UART0_BASE        UL(0xD0000000)
-#define VA_SPEAR6XX_ICM1_UART0_BASE     (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE)
-
-/* ML-1, 2 - Multi Layer CPU Subsystem */
-#define SPEAR6XX_ML_CPU_BASE            UL(0xF0000000)
-#define VA_SPEAR6XX_ML_CPU_BASE         UL(0xF0000000)
-
-/* ICM3 - Basic Subsystem */
-#define SPEAR6XX_ICM3_SMI_CTRL_BASE     UL(0xFC000000)
-#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE  UL(0xFC000000)
-#define SPEAR6XX_ICM3_DMA_BASE          UL(0xFC400000)
-#define SPEAR6XX_ICM3_SYS_CTRL_BASE     UL(0xFCA00000)
-#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE  (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE)
-#define SPEAR6XX_ICM3_MISC_REG_BASE     UL(0xFCA80000)
-#define VA_SPEAR6XX_ICM3_MISC_REG_BASE  (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE)
-
-/* Debug uart for linux, will be used for debug and uncompress messages */
-#define SPEAR_DBG_UART_BASE             SPEAR6XX_ICM1_UART0_BASE
-#define VA_SPEAR_DBG_UART_BASE          VA_SPEAR6XX_ICM1_UART0_BASE
-
-/* Sysctl base for spear platform */
-#define SPEAR_SYS_CTRL_BASE             SPEAR6XX_ICM3_SYS_CTRL_BASE
-#define VA_SPEAR_SYS_CTRL_BASE          VA_SPEAR6XX_ICM3_SYS_CTRL_BASE
-
-#endif /* __MACH_SPEAR6XX_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/timex.h b/arch/arm/mach-spear6xx/include/mach/timex.h
deleted file mode 100644
index ac1c5b005695..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/timex.h
- *
- * SPEAr6XX machine family specific timex definitions
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_TIMEX_H
-#define __MACH_TIMEX_H
-
-#include <plat/timex.h>
-
-#endif  /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/uncompress.h b/arch/arm/mach-spear6xx/include/mach/uncompress.h
deleted file mode 100644
index 77f0765e21e1..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/uncompress.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/uncompress.h
- *
- * Serial port stubs for kernel decompress status messages
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_UNCOMPRESS_H
-#define __MACH_UNCOMPRESS_H
-
-#include <plat/uncompress.h>
-
-#endif  /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 8709a39bd34c..d259c782d742 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -1,10 +1,11 @@
 config ARCH_SUNXI
         bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
         select CLKSRC_MMIO
+        select CLKSRC_OF
         select COMMON_CLK
         select GENERIC_CLOCKEVENTS
         select GENERIC_IRQ_CHIP
         select PINCTRL
         select SPARSE_IRQ
-        select SUNXI_TIMER
-        select PINCTRL_SUNXI
\ No newline at end of file
+        select SUN4I_TIMER
+        select PINCTRL_SUNXI
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 23afb732cb40..706ce35396b8 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -10,63 +10,77 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/clocksource.h>
 #include <linux/delay.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/irqchip.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/io.h>
-#include <linux/sunxi_timer.h>
 
-#include <linux/irqchip/sunxi.h>
+#include <linux/clk/sunxi.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 
 #include "sunxi.h"
 
-#define WATCHDOG_CTRL_REG       0x00
-#define WATCHDOG_CTRL_RESTART           (1 << 0)
-#define WATCHDOG_MODE_REG       0x04
-#define WATCHDOG_MODE_ENABLE            (1 << 0)
-#define WATCHDOG_MODE_RESET_ENABLE      (1 << 1)
+#define SUN4I_WATCHDOG_CTRL_REG         0x00
+#define SUN4I_WATCHDOG_CTRL_RESTART             (1 << 0)
+#define SUN4I_WATCHDOG_MODE_REG         0x04
+#define SUN4I_WATCHDOG_MODE_ENABLE              (1 << 0)
+#define SUN4I_WATCHDOG_MODE_RESET_ENABLE        (1 << 1)
 
 static void __iomem *wdt_base;
 
-static void sunxi_setup_restart(void)
-{
-        struct device_node *np = of_find_compatible_node(NULL, NULL,
-                                                "allwinner,sunxi-wdt");
-        if (WARN(!np, "unable to setup watchdog restart"))
-                return;
-
-        wdt_base = of_iomap(np, 0);
-        WARN(!wdt_base, "failed to map watchdog base address");
-}
-
-static void sunxi_restart(char mode, const char *cmd)
+static void sun4i_restart(char mode, const char *cmd)
 {
         if (!wdt_base)
                 return;
 
         /* Enable timer and set reset bit in the watchdog */
-        writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE,
-                wdt_base + WATCHDOG_MODE_REG);
+        writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
+               wdt_base + SUN4I_WATCHDOG_MODE_REG);
 
         /*
          * Restart the watchdog. The default (and lowest) interval
          * value for the watchdog is 0.5s.
          */
-        writel(WATCHDOG_CTRL_RESTART, wdt_base + WATCHDOG_CTRL_REG);
+        writel(SUN4I_WATCHDOG_CTRL_RESTART, wdt_base + SUN4I_WATCHDOG_CTRL_REG);
 
         while (1) {
                 mdelay(5);
-                writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE,
-                        wdt_base + WATCHDOG_MODE_REG);
+                writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
+                       wdt_base + SUN4I_WATCHDOG_MODE_REG);
         }
 }
 
+static struct of_device_id sunxi_restart_ids[] = {
+        { .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart },
+        { /*sentinel*/ }
+};
+
+static void sunxi_setup_restart(void)
+{
+        const struct of_device_id *of_id;
+        struct device_node *np;
+
+        np = of_find_matching_node(NULL, sunxi_restart_ids);
+        if (WARN(!np, "unable to setup watchdog restart"))
+                return;
+
+        wdt_base = of_iomap(np, 0);
+        WARN(!wdt_base, "failed to map watchdog base address");
+
+        of_id = of_match_node(sunxi_restart_ids, np);
+        WARN(!of_id, "restart function not available");
+
+        arm_pm_restart = of_id->data;
+}
+
 static struct map_desc sunxi_io_desc[] __initdata = {
         {
                 .virtual        = (unsigned long) SUNXI_REGS_VIRT_BASE,
@@ -81,6 +95,12 @@ void __init sunxi_map_io(void)
         iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc));
 }
 
+static void __init sunxi_timer_init(void)
+{
+        sunxi_init_clocks();
+        clocksource_of_init();
+}
+
 static void __init sunxi_dt_init(void)
 {
         sunxi_setup_restart();
@@ -97,9 +117,7 @@ static const char * const sunxi_board_dt_compat[] = {
 DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
         .init_machine   = sunxi_dt_init,
         .map_io         = sunxi_map_io,
-        .init_irq       = sunxi_init_irq,
-        .handle_irq     = sunxi_handle_irq,
-        .restart        = sunxi_restart,
-        .init_time      = &sunxi_timer_init,
+        .init_irq       = irqchip_init,
+        .init_time      = sunxi_timer_init,
         .dt_compat      = sunxi_board_dt_compat,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index d1c4893894ce..20c3b372cdf5 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -1,13 +1,30 @@
-if ARCH_TEGRA
+config ARCH_TEGRA
+        bool "NVIDIA Tegra" if ARCH_MULTI_V7
+        select ARCH_HAS_CPUFREQ
+        select ARCH_REQUIRE_GPIOLIB
+        select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
+        select CLKSRC_OF
+        select COMMON_CLK
+        select GENERIC_CLOCKEVENTS
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_CLK
+        select HAVE_SMP
+        select MIGHT_HAVE_CACHE_L2X0
+        select SOC_BUS
+        select SPARSE_IRQ
+        select USE_OF
+        help
+          This enables support for NVIDIA Tegra based systems.
 
-comment "NVIDIA Tegra options"
+menu "NVIDIA Tegra options"
+        depends on ARCH_TEGRA
 
 config ARCH_TEGRA_2x_SOC
         bool "Enable support for Tegra20 family"
         select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
         select ARM_ERRATA_720789
-        select ARM_ERRATA_742230 if SMP
-        select ARM_ERRATA_751472
         select ARM_ERRATA_754327 if SMP
         select ARM_ERRATA_764369 if SMP
         select ARM_GIC
@@ -18,16 +35,14 @@ config ARCH_TEGRA_2x_SOC
         select PL310_ERRATA_727915 if CACHE_L2X0
         select PL310_ERRATA_769419 if CACHE_L2X0
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
-        select USB_ULPI if USB
-        select USB_ULPI_VIEWPORT if USB_SUPPORT
+        select USB_ULPI if USB_PHY
+        select USB_ULPI_VIEWPORT if USB_PHY
         help
           Support for NVIDIA Tegra AP20 and T20 processors, based on the
           ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
 
 config ARCH_TEGRA_3x_SOC
         bool "Enable support for Tegra30 family"
-        select ARM_ERRATA_743622
-        select ARM_ERRATA_751472
         select ARM_ERRATA_754322
         select ARM_ERRATA_764369 if SMP
         select ARM_GIC
@@ -37,8 +52,8 @@ config ARCH_TEGRA_3x_SOC
         select PINCTRL_TEGRA30
         select PL310_ERRATA_769419 if CACHE_L2X0
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
-        select USB_ULPI if USB
-        select USB_ULPI_VIEWPORT if USB_SUPPORT
+        select USB_ULPI if USB_PHY
+        select USB_ULPI_VIEWPORT if USB_PHY
         help
           Support for NVIDIA Tegra T30 processor family, based on the
           ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
@@ -71,4 +86,4 @@ config TEGRA_AHB
 config TEGRA_EMC_SCALING_ENABLE
         bool "Enable scaling the memory frequency"
 
-endif
+endmenu
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index f6b46ae2b7f8..d011f0ad49c4 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,3 +1,5 @@
+asflags-y                               += -march=armv7-a
+
 obj-y                                   += common.o
 obj-y                                   += io.o
 obj-y                                   += irq.o
@@ -10,6 +12,7 @@ obj-y					+= pm.o
 obj-y                                   += reset.o
 obj-y                                   += reset-handler.o
 obj-y                                   += sleep.o
+obj-y                                   += tegra.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_speedo.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
@@ -24,12 +27,9 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= cpuidle-tegra30.o
 endif
 obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
-obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += board-dt-tegra20.o
-obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += board-dt-tegra30.o
-obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += board-dt-tegra114.o
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += tegra114_speedo.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += cpuidle-tegra114.o
 endif
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
deleted file mode 100644
index 29433816233c..000000000000
--- a/arch/arm/mach-tegra/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
-zreladdr-$(CONFIG_ARCH_TEGRA_2x_SOC)    += 0x00008000
-params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100
-initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000
diff --git a/arch/arm/mach-tegra/board-dt-tegra114.c b/arch/arm/mach-tegra/board-dt-tegra114.c
deleted file mode 100644
index 085d63637b62..000000000000
--- a/arch/arm/mach-tegra/board-dt-tegra114.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * NVIDIA Tegra114 device tree board support
- *
- * Copyright (C) 2013 NVIDIA Corporation
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/of.h>
-#include <linux/of_platform.h>
-#include <linux/clocksource.h>
-
-#include <asm/mach/arch.h>
-
-#include "board.h"
-#include "common.h"
-
-static void __init tegra114_dt_init(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
-static const char * const tegra114_dt_board_compat[] = {
-        "nvidia,tegra114",
-        NULL,
-};
-
-DT_MACHINE_START(TEGRA114_DT, "NVIDIA Tegra114 (Flattened Device Tree)")
-        .smp            = smp_ops(tegra_smp_ops),
-        .map_io         = tegra_map_common_io,
-        .init_early     = tegra114_init_early,
-        .init_irq       = tegra_dt_init_irq,
-        .init_time      = clocksource_of_init,
-        .init_machine   = tegra114_dt_init,
-        .init_late      = tegra_init_late,
-        .restart        = tegra_assert_system_reset,
-        .dt_compat      = tegra114_dt_board_compat,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
deleted file mode 100644
index bf68567e549d..000000000000
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-dt-tegra30.c
- *
- * NVIDIA Tegra30 device tree board support
- *
- * Copyright (C) 2011 NVIDIA Corporation
- *
- * Derived from:
- *
- * arch/arm/mach-tegra/board-dt-tegra20.c
- *
- * Copyright (C) 2010 Secret Lab Technologies, Ltd.
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/clocksource.h>
-#include <linux/kernel.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_fdt.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-
-#include <asm/mach/arch.h>
-
-#include "board.h"
-#include "common.h"
-#include "iomap.h"
-
-static void __init tegra30_dt_init(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
-static const char *tegra30_dt_board_compat[] = {
-        "nvidia,tegra30",
-        NULL
-};
-
-DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
-        .smp            = smp_ops(tegra_smp_ops),
-        .map_io         = tegra_map_common_io,
-        .init_early     = tegra30_init_early,
-        .init_irq       = tegra_dt_init_irq,
-        .init_time      = clocksource_of_init,
-        .init_machine   = tegra30_dt_init,
-        .init_late      = tegra_init_late,
-        .restart        = tegra_assert_system_reset,
-        .dt_compat      = tegra30_dt_board_compat,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
index 3cdc1bb8254c..035b240b9e15 100644
--- a/arch/arm/mach-tegra/board-harmony-pcie.c
+++ b/arch/arm/mach-tegra/board-harmony-pcie.c
@@ -56,13 +56,17 @@ int __init harmony_pcie_init(void)
         gpio_direction_output(en_vdd_1v05, 1);
 
         regulator = regulator_get(NULL, "vdd_ldo0,vddio_pex_clk");
-        if (IS_ERR_OR_NULL(regulator)) {
-                pr_err("%s: regulator_get failed: %d\n", __func__,
-                       (int)PTR_ERR(regulator));
+        if (IS_ERR(regulator)) {
+                err = PTR_ERR(regulator);
+                pr_err("%s: regulator_get failed: %d\n", __func__, err);
                 goto err_reg;
         }
 
-        regulator_enable(regulator);
+        err = regulator_enable(regulator);
+        if (err) {
+                pr_err("%s: regulator_enable failed: %d\n", __func__, err);
+                goto err_en;
+        }
 
         err = tegra_pcie_init(true, true);
         if (err) {
@@ -74,6 +78,7 @@ int __init harmony_pcie_init(void)
 
 err_pcie:
         regulator_disable(regulator);
+err_en:
         regulator_put(regulator);
 err_reg:
         gpio_free(en_vdd_1v05);
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 86851c81a350..1787327fae3a 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -26,9 +26,7 @@
 
 void tegra_assert_system_reset(char mode, const char *cmd);
 
-void __init tegra20_init_early(void);
-void __init tegra30_init_early(void);
-void __init tegra114_init_early(void);
+void __init tegra_init_early(void);
 void __init tegra_map_common_io(void);
 void __init tegra_init_irq(void);
 void __init tegra_dt_init_irq(void);
@@ -42,6 +40,7 @@ int tegra_clk_debugfs_init(void);
 static inline int tegra_clk_debugfs_init(void) { return 0; }
 #endif
 
+int __init tegra_powergate_init(void);
 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) && defined(CONFIG_DEBUG_FS)
 int __init tegra_powergate_debugfs_init(void);
 #else
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 5449a3f2977b..9f852c6fe5b9 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -27,12 +27,11 @@
 
 #include <asm/hardware/cache-l2x0.h>
 
-#include <mach/powergate.h>
-
 #include "board.h"
 #include "common.h"
 #include "fuse.h"
 #include "iomap.h"
+#include "irq.h"
 #include "pmc.h"
 #include "apbio.h"
 #include "sleep.h"
@@ -61,8 +60,10 @@ u32 tegra_uart_config[4] = {
 void __init tegra_dt_init_irq(void)
 {
         tegra_clocks_init();
+        tegra_pmc_init();
         tegra_init_irq();
         irqchip_init();
+        tegra_legacy_irq_syscore_init();
 }
 #endif
 
@@ -94,40 +95,18 @@ static void __init tegra_init_cache(void)
 
 }
 
-static void __init tegra_init_early(void)
+void __init tegra_init_early(void)
 {
         tegra_cpu_reset_handler_init();
         tegra_apb_io_init();
         tegra_init_fuse();
         tegra_init_cache();
-        tegra_pmc_init();
         tegra_powergate_init();
+        tegra_hotplug_init();
 }
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-void __init tegra20_init_early(void)
-{
-        tegra_init_early();
-        tegra20_hotplug_init();
-}
-#endif
-
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-void __init tegra30_init_early(void)
-{
-        tegra_init_early();
-        tegra30_hotplug_init();
-}
-#endif
-
-#ifdef CONFIG_ARCH_TEGRA_114_SOC
-void __init tegra114_init_early(void)
-{
-        tegra_init_early();
-}
-#endif
-
 void __init tegra_init_late(void)
 {
+        tegra_init_suspend();
         tegra_powergate_debugfs_init();
 }
diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h
index 32f8eb3fe344..5900cc44f780 100644
--- a/arch/arm/mach-tegra/common.h
+++ b/arch/arm/mach-tegra/common.h
@@ -2,4 +2,3 @@ extern struct smp_operations tegra_smp_ops;
 
 extern int tegra_cpu_kill(unsigned int cpu);
 extern void tegra_cpu_die(unsigned int cpu);
-extern int tegra_cpu_disable(unsigned int cpu);
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
deleted file mode 100644
index e3d6e15ff188..000000000000
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- * arch/arm/mach-tegra/cpu-tegra.c
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *      Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/sched.h>
-#include <linux/cpufreq.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/suspend.h>
-
-/* Frequency table index must be sequential starting at 0 */
-static struct cpufreq_frequency_table freq_table[] = {
-        { 0, 216000 },
-        { 1, 312000 },
-        { 2, 456000 },
-        { 3, 608000 },
-        { 4, 760000 },
-        { 5, 816000 },
-        { 6, 912000 },
-        { 7, 1000000 },
-        { 8, CPUFREQ_TABLE_END },
-};
-
-#define NUM_CPUS        2
-
-static struct clk *cpu_clk;
-static struct clk *pll_x_clk;
-static struct clk *pll_p_clk;
-static struct clk *emc_clk;
-
-static unsigned long target_cpu_speed[NUM_CPUS];
-static DEFINE_MUTEX(tegra_cpu_lock);
-static bool is_suspended;
-
-static int tegra_verify_speed(struct cpufreq_policy *policy)
-{
-        return cpufreq_frequency_table_verify(policy, freq_table);
-}
-
-static unsigned int tegra_getspeed(unsigned int cpu)
-{
-        unsigned long rate;
-
-        if (cpu >= NUM_CPUS)
-                return 0;
-
-        rate = clk_get_rate(cpu_clk) / 1000;
-        return rate;
-}
-
-static int tegra_cpu_clk_set_rate(unsigned long rate)
-{
-        int ret;
-
-        /*
-         * Take an extra reference to the main pll so it doesn't turn
-         * off when we move the cpu off of it
-         */
-        clk_prepare_enable(pll_x_clk);
-
-        ret = clk_set_parent(cpu_clk, pll_p_clk);
-        if (ret) {
-                pr_err("Failed to switch cpu to clock pll_p\n");
-                goto out;
-        }
-
-        if (rate == clk_get_rate(pll_p_clk))
-                goto out;
-
-        ret = clk_set_rate(pll_x_clk, rate);
-        if (ret) {
-                pr_err("Failed to change pll_x to %lu\n", rate);
-                goto out;
-        }
-
-        ret = clk_set_parent(cpu_clk, pll_x_clk);
-        if (ret) {
-                pr_err("Failed to switch cpu to clock pll_x\n");
-                goto out;
-        }
-
-out:
-        clk_disable_unprepare(pll_x_clk);
-        return ret;
-}
-
-static int tegra_update_cpu_speed(unsigned long rate)
-{
-        int ret = 0;
-        struct cpufreq_freqs freqs;
-
-        freqs.old = tegra_getspeed(0);
-        freqs.new = rate;
-
-        if (freqs.old == freqs.new)
-                return ret;
-
-        /*
-         * Vote on memory bus frequency based on cpu frequency
-         * This sets the minimum frequency, display or avp may request higher
-         */
-        if (rate >= 816000)
-                clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
-        else if (rate >= 456000)
-                clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
-        else
-                clk_set_rate(emc_clk, 100000000);  /* emc 50Mhz */
-
-        for_each_online_cpu(freqs.cpu)
-                cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
-#ifdef CONFIG_CPU_FREQ_DEBUG
-        printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
-               freqs.old, freqs.new);
-#endif
-
-        ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
-        if (ret) {
-                pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
-                        freqs.new);
-                return ret;
-        }
-
-        for_each_online_cpu(freqs.cpu)
-                cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
-        return 0;
-}
-
-static unsigned long tegra_cpu_highest_speed(void)
-{
-        unsigned long rate = 0;
-        int i;
-
-        for_each_online_cpu(i)
-                rate = max(rate, target_cpu_speed[i]);
-        return rate;
-}
-
-static int tegra_target(struct cpufreq_policy *policy,
-                       unsigned int target_freq,
-                       unsigned int relation)
-{
-        unsigned int idx;
-        unsigned int freq;
-        int ret = 0;
-
-        mutex_lock(&tegra_cpu_lock);
-
-        if (is_suspended) {
-                ret = -EBUSY;
-                goto out;
-        }
-
-        cpufreq_frequency_table_target(policy, freq_table, target_freq,
-                relation, &idx);
-
-        freq = freq_table[idx].frequency;
-
-        target_cpu_speed[policy->cpu] = freq;
-
-        ret = tegra_update_cpu_speed(tegra_cpu_highest_speed());
-
-out:
-        mutex_unlock(&tegra_cpu_lock);
-        return ret;
-}
-
-static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
-        void *dummy)
-{
-        mutex_lock(&tegra_cpu_lock);
-        if (event == PM_SUSPEND_PREPARE) {
-                is_suspended = true;
-                pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
-                        freq_table[0].frequency);
-                tegra_update_cpu_speed(freq_table[0].frequency);
-        } else if (event == PM_POST_SUSPEND) {
-                is_suspended = false;
-        }
-        mutex_unlock(&tegra_cpu_lock);
-
-        return NOTIFY_OK;
-}
-
-static struct notifier_block tegra_cpu_pm_notifier = {
-        .notifier_call = tegra_pm_notify,
-};
-
-static int tegra_cpu_init(struct cpufreq_policy *policy)
-{
-        if (policy->cpu >= NUM_CPUS)
-                return -EINVAL;
-
-        clk_prepare_enable(emc_clk);
-        clk_prepare_enable(cpu_clk);
-
-        cpufreq_frequency_table_cpuinfo(policy, freq_table);
-        cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
-        policy->cur = tegra_getspeed(policy->cpu);
-        target_cpu_speed[policy->cpu] = policy->cur;
-
-        /* FIXME: what's the actual transition time? */
-        policy->cpuinfo.transition_latency = 300 * 1000;
-
-        cpumask_copy(policy->cpus, cpu_possible_mask);
-
-        if (policy->cpu == 0)
-                register_pm_notifier(&tegra_cpu_pm_notifier);
-
-        return 0;
-}
-
-static int tegra_cpu_exit(struct cpufreq_policy *policy)
-{
-        cpufreq_frequency_table_cpuinfo(policy, freq_table);
-        clk_disable_unprepare(emc_clk);
-        return 0;
-}
-
-static struct freq_attr *tegra_cpufreq_attr[] = {
-        &cpufreq_freq_attr_scaling_available_freqs,
-        NULL,
-};
-
-static struct cpufreq_driver tegra_cpufreq_driver = {
-        .verify         = tegra_verify_speed,
-        .target         = tegra_target,
-        .get            = tegra_getspeed,
-        .init           = tegra_cpu_init,
-        .exit           = tegra_cpu_exit,
-        .name           = "tegra",
-        .attr           = tegra_cpufreq_attr,
-};
-
-static int __init tegra_cpufreq_init(void)
-{
-        cpu_clk = clk_get_sys(NULL, "cpu");
-        if (IS_ERR(cpu_clk))
-                return PTR_ERR(cpu_clk);
-
-        pll_x_clk = clk_get_sys(NULL, "pll_x");
-        if (IS_ERR(pll_x_clk))
-                return PTR_ERR(pll_x_clk);
-
-        pll_p_clk = clk_get_sys(NULL, "pll_p_cclk");
-        if (IS_ERR(pll_p_clk))
-                return PTR_ERR(pll_p_clk);
-
-        emc_clk = clk_get_sys("cpu", "emc");
-        if (IS_ERR(emc_clk)) {
-                clk_put(cpu_clk);
-                return PTR_ERR(emc_clk);
-        }
-
-        return cpufreq_register_driver(&tegra_cpufreq_driver);
-}
-
-static void __exit tegra_cpufreq_exit(void)
-{
-        cpufreq_unregister_driver(&tegra_cpufreq_driver);
-        clk_put(emc_clk);
-        clk_put(cpu_clk);
-}
-
-
-MODULE_AUTHOR("Colin Cross <ccross@android.com>");
-MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
-MODULE_LICENSE("GPL");
-module_init(tegra_cpufreq_init);
-module_exit(tegra_cpufreq_exit);
diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
index 0f4e8c483b34..1d1c6023f4a2 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra114.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
@@ -23,39 +23,13 @@
 static struct cpuidle_driver tegra_idle_driver = {
         .name = "tegra_idle",
         .owner = THIS_MODULE,
-        .en_core_tk_irqen = 1,
         .state_count = 1,
         .states = {
                 [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
         },
 };
 
-static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
-
 int __init tegra114_cpuidle_init(void)
 {
-        int ret;
-        unsigned int cpu;
-        struct cpuidle_device *dev;
-        struct cpuidle_driver *drv = &tegra_idle_driver;
-
-        ret = cpuidle_register_driver(&tegra_idle_driver);
-        if (ret) {
-                pr_err("CPUidle driver registration failed\n");
-                return ret;
-        }
-
-        for_each_possible_cpu(cpu) {
-                dev = &per_cpu(tegra_idle_device, cpu);
-                dev->cpu = cpu;
-
-                dev->state_count = drv->state_count;
-                ret = cpuidle_register_device(dev);
-                if (ret) {
-                        pr_err("CPU%u: CPUidle device registration failed\n",
-                                cpu);
-                        return ret;
-                }
-        }
-        return 0;
+        return cpuidle_register(&tegra_idle_driver, NULL);
 }
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index 825ced4f7a40..0cdba8de8c77 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -43,32 +43,33 @@ static atomic_t abort_barrier;
 static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
                                     struct cpuidle_driver *drv,
                                     int index);
+#define TEGRA20_MAX_STATES 2
+#else
+#define TEGRA20_MAX_STATES 1
 #endif
 
-static struct cpuidle_state tegra_idle_states[] = {
-        [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
-#ifdef CONFIG_PM_SLEEP
-        [1] = {
-                .enter                  = tegra20_idle_lp2_coupled,
-                .exit_latency           = 5000,
-                .target_residency       = 10000,
-                .power_usage            = 0,
-                .flags                  = CPUIDLE_FLAG_TIME_VALID |
-                                          CPUIDLE_FLAG_COUPLED,
-                .name                   = "powered-down",
-                .desc                   = "CPU power gated",
-        },
-#endif
-};
-
 static struct cpuidle_driver tegra_idle_driver = {
         .name = "tegra_idle",
         .owner = THIS_MODULE,
-        .en_core_tk_irqen = 1,
+        .states = {
+                ARM_CPUIDLE_WFI_STATE_PWR(600),
+#ifdef CONFIG_PM_SLEEP
+                {
+                        .enter            = tegra20_idle_lp2_coupled,
+                        .exit_latency     = 5000,
+                        .target_residency = 10000,
+                        .power_usage      = 0,
+                        .flags            = CPUIDLE_FLAG_TIME_VALID |
+                        CPUIDLE_FLAG_COUPLED,
+                        .name             = "powered-down",
+                        .desc             = "CPU power gated",
+                },
+#endif
+        },
+        .state_count = TEGRA20_MAX_STATES,
+        .safe_state_index = 0,
 };
 
-static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
-
 #ifdef CONFIG_PM_SLEEP
 #ifdef CONFIG_SMP
 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
@@ -130,10 +131,6 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
                                            struct cpuidle_driver *drv,
                                            int index)
 {
-        struct cpuidle_state *state = &drv->states[index];
-        u32 cpu_on_time = state->exit_latency;
-        u32 cpu_off_time = state->target_residency - state->exit_latency;
-
         while (tegra20_cpu_is_resettable_soon())
                 cpu_relax();
 
@@ -142,7 +139,7 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
 
-        tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
+        tegra_idle_lp2_last();
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
 
@@ -217,39 +214,8 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
 
 int __init tegra20_cpuidle_init(void)
 {
-        int ret;
-        unsigned int cpu;
-        struct cpuidle_device *dev;
-        struct cpuidle_driver *drv = &tegra_idle_driver;
-
 #ifdef CONFIG_PM_SLEEP
         tegra_tear_down_cpu = tegra20_tear_down_cpu;
 #endif
-
-        drv->state_count = ARRAY_SIZE(tegra_idle_states);
-        memcpy(drv->states, tegra_idle_states,
-                        drv->state_count * sizeof(drv->states[0]));
-
-        ret = cpuidle_register_driver(&tegra_idle_driver);
-        if (ret) {
-                pr_err("CPUidle driver registration failed\n");
-                return ret;
-        }
-
-        for_each_possible_cpu(cpu) {
-                dev = &per_cpu(tegra_idle_device, cpu);
-                dev->cpu = cpu;
-#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
-                dev->coupled_cpus = *cpu_possible_mask;
-#endif
-
-                dev->state_count = drv->state_count;
-                ret = cpuidle_register_device(dev);
-                if (ret) {
-                        pr_err("CPU%u: CPUidle device registration failed\n",
-                                cpu);
-                        return ret;
-                }
-        }
-        return 0;
+        return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
 }
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 8b50cf4ddd6f..3cf9aca5f3ea 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -43,7 +43,6 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev,
 static struct cpuidle_driver tegra_idle_driver = {
         .name = "tegra_idle",
         .owner = THIS_MODULE,
-        .en_core_tk_irqen = 1,
 #ifdef CONFIG_PM_SLEEP
         .state_count = 2,
 #else
@@ -65,17 +64,11 @@ static struct cpuidle_driver tegra_idle_driver = {
         },
 };
 
-static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
-
 #ifdef CONFIG_PM_SLEEP
 static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
                                            struct cpuidle_driver *drv,
                                            int index)
 {
-        struct cpuidle_state *state = &drv->states[index];
-        u32 cpu_on_time = state->exit_latency;
-        u32 cpu_off_time = state->target_residency - state->exit_latency;
-
         /* All CPUs entering LP2 is not working.
          * Don't let CPU0 enter LP2 when any secondary CPU is online.
          */
@@ -86,7 +79,7 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
 
-        tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
+        tegra_idle_lp2_last();
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
 
@@ -102,12 +95,8 @@ static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
 
         smp_wmb();
 
-        save_cpu_arch_register();
-
         cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
 
-        restore_cpu_arch_register();
-
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
 
         return true;
@@ -157,32 +146,8 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev,
 
 int __init tegra30_cpuidle_init(void)
 {
-        int ret;
-        unsigned int cpu;
-        struct cpuidle_device *dev;
-        struct cpuidle_driver *drv = &tegra_idle_driver;
-
 #ifdef CONFIG_PM_SLEEP
         tegra_tear_down_cpu = tegra30_tear_down_cpu;
 #endif
-
-        ret = cpuidle_register_driver(&tegra_idle_driver);
-        if (ret) {
-                pr_err("CPUidle driver registration failed\n");
-                return ret;
-        }
-
-        for_each_possible_cpu(cpu) {
-                dev = &per_cpu(tegra_idle_device, cpu);
-                dev->cpu = cpu;
-
-                dev->state_count = drv->state_count;
-                ret = cpuidle_register_device(dev);
-                if (ret) {
-                        pr_err("CPU%u: CPUidle device registration failed\n",
-                                cpu);
-                        return ret;
-                }
-        }
-        return 0;
+        return cpuidle_register(&tegra_idle_driver, NULL);
 }
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index f7db0782a6b6..e035cd284a6e 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -2,6 +2,7 @@
  * arch/arm/mach-tegra/fuse.c
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *      Colin Cross <ccross@android.com>
@@ -137,6 +138,9 @@ void tegra_init_fuse(void)
                 tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
                 tegra_init_speedo_data = &tegra30_init_speedo_data;
                 break;
+        case TEGRA114:
+                tegra_init_speedo_data = &tegra114_init_speedo_data;
+                break;
         default:
                 pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
                 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index da78434678c7..aacc00d05980 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *      Colin Cross <ccross@android.com>
@@ -66,4 +67,10 @@ void tegra30_init_speedo_data(void);
 static inline void tegra30_init_speedo_data(void) {}
 #endif
 
+#ifdef CONFIG_ARCH_TEGRA_114_SOC
+void tegra114_init_speedo_data(void);
+#else
+static inline void tegra114_init_speedo_data(void) {}
+#endif
+
 #endif
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index fd473f2b4c3d..045c16f2dd51 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -7,8 +7,5 @@
 
 ENTRY(tegra_secondary_startup)
         bl      v7_invalidate_l1
-        /* Enable coresight */
-        mov32   r0, 0xC5ACCE55
-        mcr     p14, 0, r0, c7, c12, 6
         b       secondary_startup
 ENDPROC(tegra_secondary_startup)
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index a599f6e36dea..184914a68d73 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -1,8 +1,7 @@
 /*
- *
  *  Copyright (C) 2002 ARM Ltd.
  *  All Rights Reserved
- *  Copyright (c) 2010, 2012 NVIDIA Corporation. All rights reserved.
+ *  Copyright (c) 2010, 2012-2013, NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -12,9 +11,9 @@
 #include <linux/smp.h>
 #include <linux/clk/tegra.h>
 
-#include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 
+#include "fuse.h"
 #include "sleep.h"
 
 static void (*tegra_hotplug_shutdown)(void);
@@ -47,27 +46,13 @@ void __ref tegra_cpu_die(unsigned int cpu)
         BUG();
 }
 
-int tegra_cpu_disable(unsigned int cpu)
-{
-        /*
-         * we don't allow CPU 0 to be shutdown (it is still too special
-         * e.g. clock tick interrupts)
-         */
-        return cpu == 0 ? -EPERM : 0;
-}
-
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-extern void tegra20_hotplug_shutdown(void);
-void __init tegra20_hotplug_init(void)
+void __init tegra_hotplug_init(void)
 {
-        tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
-}
-#endif
+        if (!IS_ENABLED(CONFIG_HOTPLUG_CPU))
+                return;
 
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-extern void tegra30_hotplug_shutdown(void);
-void __init tegra30_hotplug_init(void)
-{
-        tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20)
+                tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
+                tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
 }
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h
deleted file mode 100644
index 06763fe7529d..000000000000
--- a/arch/arm/mach-tegra/include/mach/powergate.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * drivers/regulator/tegra-regulator.c
- *
- * Copyright (c) 2010 Google, Inc
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _MACH_TEGRA_POWERGATE_H_
-#define _MACH_TEGRA_POWERGATE_H_
-
-struct clk;
-
-#define TEGRA_POWERGATE_CPU     0
-#define TEGRA_POWERGATE_3D      1
-#define TEGRA_POWERGATE_VENC    2
-#define TEGRA_POWERGATE_PCIE    3
-#define TEGRA_POWERGATE_VDEC    4
-#define TEGRA_POWERGATE_L2      5
-#define TEGRA_POWERGATE_MPE     6
-#define TEGRA_POWERGATE_HEG     7
-#define TEGRA_POWERGATE_SATA    8
-#define TEGRA_POWERGATE_CPU1    9
-#define TEGRA_POWERGATE_CPU2    10
-#define TEGRA_POWERGATE_CPU3    11
-#define TEGRA_POWERGATE_CELP    12
-#define TEGRA_POWERGATE_3D1     13
-
-#define TEGRA_POWERGATE_CPU0    TEGRA_POWERGATE_CPU
-#define TEGRA_POWERGATE_3D0     TEGRA_POWERGATE_3D
-
-int  __init tegra_powergate_init(void);
-
-int tegra_cpu_powergate_id(int cpuid);
-int tegra_powergate_is_powered(int id);
-int tegra_powergate_power_on(int id);
-int tegra_powergate_power_off(int id);
-int tegra_powergate_remove_clamping(int id);
-
-/* Must be called with clk disabled, and returns with clk enabled */
-int tegra_powergate_sequence_power_up(int id, struct clk *clk);
-
-#endif /* _MACH_TEGRA_POWERGATE_H_ */
diff --git a/arch/arm/mach-tegra/include/mach/timex.h b/arch/arm/mach-tegra/include/mach/timex.h
deleted file mode 100644
index a44ccbdb7dbf..000000000000
--- a/arch/arm/mach-tegra/include/mach/timex.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/timex.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *      Erik Gilling <konkers@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_TIMEX_H
-#define __MACH_TEGRA_TIMEX_H
-
-#define CLOCK_TICK_RATE         1000000
-
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h
deleted file mode 100644
index 08386418196f..000000000000
--- a/arch/arm/mach-tegra/include/mach/uncompress.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/uncompress.h
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2011 Google, Inc.
- * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *      Erik Gilling <konkers@google.com>
- *      Doug Anderson <dianders@chromium.org>
- *      Stephen Warren <swarren@nvidia.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_UNCOMPRESS_H
-#define __MACH_TEGRA_UNCOMPRESS_H
-
-#include <linux/types.h>
-#include <linux/serial_reg.h>
-
-#include "../../iomap.h"
-
-#define BIT(x) (1 << (x))
-#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
-
-#define DEBUG_UART_SHIFT 2
-
-volatile u8 *uart;
-
-static void putc(int c)
-{
-        if (uart == NULL)
-                return;
-
-        while (!(uart[UART_LSR << DEBUG_UART_SHIFT] & UART_LSR_THRE))
-                barrier();
-        uart[UART_TX << DEBUG_UART_SHIFT] = c;
-}
-
-static inline void flush(void)
-{
-}
-
-static const struct {
-        u32 base;
-        u32 reset_reg;
-        u32 clock_reg;
-        u32 bit;
-} uarts[] = {
-        {
-                TEGRA_UARTA_BASE,
-                TEGRA_CLK_RESET_BASE + 0x04,
-                TEGRA_CLK_RESET_BASE + 0x10,
-                6,
-        },
-        {
-                TEGRA_UARTB_BASE,
-                TEGRA_CLK_RESET_BASE + 0x04,
-                TEGRA_CLK_RESET_BASE + 0x10,
-                7,
-        },
-        {
-                TEGRA_UARTC_BASE,
-                TEGRA_CLK_RESET_BASE + 0x08,
-                TEGRA_CLK_RESET_BASE + 0x14,
-                23,
-        },
-        {
-                TEGRA_UARTD_BASE,
-                TEGRA_CLK_RESET_BASE + 0x0c,
-                TEGRA_CLK_RESET_BASE + 0x18,
-                1,
-        },
-        {
-                TEGRA_UARTE_BASE,
-                TEGRA_CLK_RESET_BASE + 0x0c,
-                TEGRA_CLK_RESET_BASE + 0x18,
-                2,
-        },
-};
-
-static inline bool uart_clocked(int i)
-{
-        if (*(u8 *)uarts[i].reset_reg & BIT(uarts[i].bit))
-                return false;
-
-        if (!(*(u8 *)uarts[i].clock_reg & BIT(uarts[i].bit)))
-                return false;
-
-        return true;
-}
-
-#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA
-int auto_odmdata(void)
-{
-        volatile u32 *pmc = (volatile u32 *)TEGRA_PMC_BASE;
-        u32 odmdata = pmc[0xa0 / 4];
-
-        /*
-         * Bits 19:18 are the console type: 0=default, 1=none, 2==DCC, 3==UART
-         * Some boards apparently swap the last two values, but we don't have
-         * any way of catering for that here, so we just accept either. If this
-         * doesn't make sense for your board, just don't enable this feature.
-         *
-         * Bits 17:15 indicate the UART to use, 0/1/2/3/4 are UART A/B/C/D/E.
-         */
-
-        switch  ((odmdata >> 18) & 3) {
-        case 2:
-        case 3:
-                break;
-        default:
-                return -1;
-        }
-
-        return (odmdata >> 15) & 7;
-}
-#endif
-
-/*
- * Setup before decompression.  This is where we do UART selection for
- * earlyprintk and init the uart_base register.
- */
-static inline void arch_decomp_setup(void)
-{
-        int uart_id;
-        volatile u32 *apb_misc = (volatile u32 *)TEGRA_APB_MISC_BASE;
-        u32 chip, div;
-
-#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
-        uart_id = auto_odmdata();
-#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
-        uart_id = 0;
-#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
-        uart_id = 1;
-#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
-        uart_id = 2;
-#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
-        uart_id = 3;
-#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
-        uart_id = 4;
-#endif
-
-        if (uart_id < 0 || uart_id >= ARRAY_SIZE(uarts) ||
-            !uart_clocked(uart_id))
-                uart = NULL;
-        else
-                uart = (volatile u8 *)uarts[uart_id].base;
-
-        if (uart == NULL)
-                return;
-
-        chip = (apb_misc[0x804 / 4] >> 8) & 0xff;
-        if (chip == 0x20)
-                div = 0x0075;
-        else
-                div = 0x00dd;
-
-        uart[UART_LCR << DEBUG_UART_SHIFT] |= UART_LCR_DLAB;
-        uart[UART_DLL << DEBUG_UART_SHIFT] = div & 0xff;
-        uart[UART_DLM << DEBUG_UART_SHIFT] = div >> 8;
-        uart[UART_LCR << DEBUG_UART_SHIFT] = 3;
-}
-
-#endif
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 1952e82797cc..0de4eed1493d 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -4,7 +4,7 @@
  * Author:
  *      Colin Cross <ccross@android.com>
  *
- * Copyright (C) 2010, NVIDIA Corporation
+ * Copyright (C) 2010,2013, NVIDIA Corporation
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -23,6 +23,7 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/syscore_ops.h>
 
 #include "board.h"
 #include "iomap.h"
@@ -43,6 +44,7 @@
 #define ICTLR_COP_IEP_CLASS     0x3c
 
 #define FIRST_LEGACY_IRQ 32
+#define TEGRA_MAX_NUM_ICTLRS    5
 
 #define SGI_MASK 0xFFFF
 
@@ -56,6 +58,15 @@ static void __iomem *ictlr_reg_base[] = {
         IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
 };
 
+#ifdef CONFIG_PM_SLEEP
+static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
+static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
+static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
+static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
+
+static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
+#endif
+
 bool tegra_pending_sgi(void)
 {
         u32 pending_set;
@@ -125,6 +136,87 @@ static int tegra_retrigger(struct irq_data *d)
         return 1;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int tegra_set_wake(struct irq_data *d, unsigned int enable)
+{
+        u32 irq = d->irq;
+        u32 index, mask;
+
+        if (irq < FIRST_LEGACY_IRQ ||
+                irq >= FIRST_LEGACY_IRQ + num_ictlrs * 32)
+                return -EINVAL;
+
+        index = ((irq - FIRST_LEGACY_IRQ) / 32);
+        mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
+        if (enable)
+                ictlr_wake_mask[index] |= mask;
+        else
+                ictlr_wake_mask[index] &= ~mask;
+
+        return 0;
+}
+
+static int tegra_legacy_irq_suspend(void)
+{
+        unsigned long flags;
+        int i;
+
+        local_irq_save(flags);
+        for (i = 0; i < num_ictlrs; i++) {
+                void __iomem *ictlr = ictlr_reg_base[i];
+                /* Save interrupt state */
+                cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
+                cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS);
+                cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
+                cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
+
+                /* Disable COP interrupts */
+                writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
+
+                /* Disable CPU interrupts */
+                writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
+
+                /* Enable the wakeup sources of ictlr */
+                writel_relaxed(ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
+        }
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static void tegra_legacy_irq_resume(void)
+{
+        unsigned long flags;
+        int i;
+
+        local_irq_save(flags);
+        for (i = 0; i < num_ictlrs; i++) {
+                void __iomem *ictlr = ictlr_reg_base[i];
+                writel_relaxed(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS);
+                writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
+                writel_relaxed(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET);
+                writel_relaxed(cop_iep[i], ictlr + ICTLR_COP_IEP_CLASS);
+                writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
+                writel_relaxed(cop_ier[i], ictlr + ICTLR_COP_IER_SET);
+        }
+        local_irq_restore(flags);
+}
+
+static struct syscore_ops tegra_legacy_irq_syscore_ops = {
+        .suspend = tegra_legacy_irq_suspend,
+        .resume = tegra_legacy_irq_resume,
+};
+
+int tegra_legacy_irq_syscore_init(void)
+{
+        register_syscore_ops(&tegra_legacy_irq_syscore_ops);
+
+        return 0;
+}
+#else
+#define tegra_set_wake NULL
+#endif
+
 void __init tegra_init_irq(void)
 {
         int i;
@@ -150,6 +242,8 @@ void __init tegra_init_irq(void)
         gic_arch_extn.irq_mask = tegra_mask;
         gic_arch_extn.irq_unmask = tegra_unmask;
         gic_arch_extn.irq_retrigger = tegra_retrigger;
+        gic_arch_extn.irq_set_wake = tegra_set_wake;
+        gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
 
         /*
          * Check if there is a devicetree present, since the GIC will be
diff --git a/arch/arm/mach-tegra/irq.h b/arch/arm/mach-tegra/irq.h
index 5142649bba05..bc05ce5613fb 100644
--- a/arch/arm/mach-tegra/irq.h
+++ b/arch/arm/mach-tegra/irq.h
@@ -19,4 +19,10 @@
 
 bool tegra_pending_sgi(void);
 
+#ifdef CONFIG_PM_SLEEP
+int tegra_legacy_irq_syscore_init(void);
+#else
+static inline int tegra_legacy_irq_syscore_init(void) { return 0; }
+#endif
+
 #endif
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index b60165f1ca02..46144a19a7e7 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -34,12 +34,11 @@
 #include <linux/delay.h>
 #include <linux/export.h>
 #include <linux/clk/tegra.h>
+#include <linux/tegra-powergate.h>
 
 #include <asm/sizes.h>
 #include <asm/mach/pci.h>
 
-#include <mach/powergate.h>
-
 #include "board.h"
 #include "iomap.h"
 
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 2c6b3d55213b..fad4226ef710 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -18,7 +18,6 @@
 #include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
 #include <linux/clk/tegra.h>
 
 #include <asm/cacheflush.h>
@@ -26,53 +25,58 @@
 #include <asm/smp_scu.h>
 #include <asm/smp_plat.h>
 
-#include <mach/powergate.h>
-
 #include "fuse.h"
 #include "flowctrl.h"
 #include "reset.h"
+#include "pmc.h"
 
 #include "common.h"
 #include "iomap.h"
 
-extern void tegra_secondary_startup(void);
-
 static cpumask_t tegra_cpu_init_mask;
 
-#define EVP_CPU_RESET_VECTOR \
-        (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
-
 static void __cpuinit tegra_secondary_init(unsigned int cpu)
 {
-        /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-
         cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
 }
 
-static int tegra20_power_up_cpu(unsigned int cpu)
+
+static int tegra20_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        /* Enable the CPU clock. */
-        tegra_enable_cpu_clock(cpu);
+        cpu = cpu_logical_map(cpu);
+
+        /*
+         * Force the CPU into reset. The CPU must remain in reset when
+         * the flow controller state is cleared (which will cause the
+         * flow controller to stop driving reset if the CPU has been
+         * power-gated via the flow controller). This will have no
+         * effect on first boot of the CPU since it should already be
+         * in reset.
+         */
+        tegra_put_cpu_in_reset(cpu);
 
-        /* Clear flow controller CSR. */
-        flowctrl_write_cpu_csr(cpu, 0);
+        /*
+         * Unhalt the CPU. If the flow controller was used to
+         * power-gate the CPU this will cause the flow controller to
+         * stop driving reset. The CPU will remain in reset because the
+         * clock and reset block is now driving reset.
+         */
+        flowctrl_write_cpu_halt(cpu, 0);
 
+        tegra_enable_cpu_clock(cpu);
+        flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */
+        tegra_cpu_out_of_reset(cpu);
         return 0;
 }
 
-static int tegra30_power_up_cpu(unsigned int cpu)
+static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        int ret, pwrgateid;
+        int ret;
         unsigned long timeout;
 
-        pwrgateid = tegra_cpu_powergate_id(cpu);
-        if (pwrgateid < 0)
-                return pwrgateid;
+        cpu = cpu_logical_map(cpu);
+        tegra_put_cpu_in_reset(cpu);
+        flowctrl_write_cpu_halt(cpu, 0);
 
         /*
          * The power up sequence of cold boot CPU and warm boot CPU
@@ -85,13 +89,13 @@ static int tegra30_power_up_cpu(unsigned int cpu)
          * the IO clamps.
          * For cold boot CPU, do not wait. After the cold boot CPU be
          * booted, it will run to tegra_secondary_init() and set
-         * tegra_cpu_init_mask which influences what tegra30_power_up_cpu()
+         * tegra_cpu_init_mask which influences what tegra30_boot_secondary()
          * next time around.
          */
         if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
                 timeout = jiffies + msecs_to_jiffies(50);
                 do {
-                        if (!tegra_powergate_is_powered(pwrgateid))
+                        if (tegra_pmc_cpu_is_powered(cpu))
                                 goto remove_clamps;
                         udelay(10);
                 } while (time_before(jiffies, timeout));
@@ -103,14 +107,14 @@ static int tegra30_power_up_cpu(unsigned int cpu)
          * be un-gated by un-toggling the power gate register
          * manually.
          */
-        if (!tegra_powergate_is_powered(pwrgateid)) {
-                ret = tegra_powergate_power_on(pwrgateid);
+        if (!tegra_pmc_cpu_is_powered(cpu)) {
+                ret = tegra_pmc_cpu_power_on(cpu);
                 if (ret)
                         return ret;
 
                 /* Wait for the power to come up. */
                 timeout = jiffies + msecs_to_jiffies(100);
-                while (tegra_powergate_is_powered(pwrgateid)) {
+                while (tegra_pmc_cpu_is_powered(cpu)) {
                         if (time_after(jiffies, timeout))
                                 return -ETIMEDOUT;
                         udelay(10);
@@ -123,57 +127,34 @@ remove_clamps:
         udelay(10);
 
         /* Remove I/O clamps. */
-        ret = tegra_powergate_remove_clamping(pwrgateid);
-        udelay(10);
+        ret = tegra_pmc_cpu_remove_clamping(cpu);
+        if (ret)
+                return ret;
 
-        /* Clear flow controller CSR. */
-        flowctrl_write_cpu_csr(cpu, 0);
+        udelay(10);
 
+        flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */
+        tegra_cpu_out_of_reset(cpu);
         return 0;
 }
 
-static int __cpuinit tegra_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        int status;
-
         cpu = cpu_logical_map(cpu);
+        return tegra_pmc_cpu_power_on(cpu);
+}
 
-        /*
-         * Force the CPU into reset. The CPU must remain in reset when the
-         * flow controller state is cleared (which will cause the flow
-         * controller to stop driving reset if the CPU has been power-gated
-         * via the flow controller). This will have no effect on first boot
-         * of the CPU since it should already be in reset.
-         */
-        tegra_put_cpu_in_reset(cpu);
-
-        /*
-         * Unhalt the CPU. If the flow controller was used to power-gate the
-         * CPU this will cause the flow controller to stop driving reset.
-         * The CPU will remain in reset because the clock and reset block
-         * is now driving reset.
-         */
-        flowctrl_write_cpu_halt(cpu, 0);
-
-        switch (tegra_chip_id) {
-        case TEGRA20:
-                status = tegra20_power_up_cpu(cpu);
-                break;
-        case TEGRA30:
-                status = tegra30_power_up_cpu(cpu);
-                break;
-        default:
-                status = -EINVAL;
-                break;
-        }
-
-        if (status)
-                goto done;
-
-        /* Take the CPU out of reset. */
-        tegra_cpu_out_of_reset(cpu);
-done:
-        return status;
+static int __cpuinit tegra_boot_secondary(unsigned int cpu,
+                                          struct task_struct *idle)
+{
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20)
+                return tegra20_boot_secondary(cpu, idle);
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
+                return tegra30_boot_secondary(cpu, idle);
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
+                return tegra114_boot_secondary(cpu, idle);
+
+        return -EINVAL;
 }
 
 static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
@@ -192,6 +173,5 @@ struct smp_operations tegra_smp_ops __initdata = {
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_kill               = tegra_cpu_kill,
         .cpu_die                = tegra_cpu_die,
-        .cpu_disable            = tegra_cpu_disable,
 #endif
 };
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 523604de666f..45cf52c7e528 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -22,7 +22,7 @@
 #include <linux/cpumask.h>
 #include <linux/delay.h>
 #include <linux/cpu_pm.h>
-#include <linux/clk.h>
+#include <linux/suspend.h>
 #include <linux/err.h>
 #include <linux/clk/tegra.h>
 
@@ -37,67 +37,13 @@
 #include "reset.h"
 #include "flowctrl.h"
 #include "fuse.h"
+#include "pmc.h"
 #include "sleep.h"
 
-#define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU pwr req enable */
-
-#define PMC_CTRL                0x0
-#define PMC_CPUPWRGOOD_TIMER    0xc8
-#define PMC_CPUPWROFF_TIMER     0xcc
-
 #ifdef CONFIG_PM_SLEEP
-static unsigned int g_diag_reg;
 static DEFINE_SPINLOCK(tegra_lp2_lock);
-static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
-static struct clk *tegra_pclk;
 void (*tegra_tear_down_cpu)(void);
 
-void save_cpu_arch_register(void)
-{
-        /* read diagnostic register */
-        asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
-        return;
-}
-
-void restore_cpu_arch_register(void)
-{
-        /* write diagnostic register */
-        asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
-        return;
-}
-
-static void set_power_timers(unsigned long us_on, unsigned long us_off)
-{
-        unsigned long long ticks;
-        unsigned long long pclk;
-        unsigned long rate;
-        static unsigned long tegra_last_pclk;
-
-        if (tegra_pclk == NULL) {
-                tegra_pclk = clk_get_sys(NULL, "pclk");
-                WARN_ON(IS_ERR(tegra_pclk));
-        }
-
-        rate = clk_get_rate(tegra_pclk);
-
-        if (WARN_ON_ONCE(rate <= 0))
-                pclk = 100000000;
-        else
-                pclk = rate;
-
-        if ((rate != tegra_last_pclk)) {
-                ticks = (us_on * pclk) + 999999ull;
-                do_div(ticks, 1000000);
-                writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER);
-
-                ticks = (us_off * pclk) + 999999ull;
-                do_div(ticks, 1000000);
-                writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER);
-                wmb();
-        }
-        tegra_last_pclk = pclk;
-}
-
 /*
  * restore_cpu_complex
  *
@@ -119,8 +65,6 @@ static void restore_cpu_complex(void)
         tegra_cpu_clock_resume();
 
         flowctrl_cpu_suspend_exit(cpu);
-
-        restore_cpu_arch_register();
 }
 
 /*
@@ -145,8 +89,6 @@ static void suspend_cpu_complex(void)
         tegra_cpu_clock_suspend();
 
         flowctrl_cpu_suspend_enter(cpu);
-
-        save_cpu_arch_register();
 }
 
 void tegra_clear_cpu_in_lp2(int phy_cpu_id)
@@ -181,14 +123,14 @@ bool tegra_set_cpu_in_lp2(int phy_cpu_id)
         return last_cpu;
 }
 
-static int tegra_sleep_cpu(unsigned long v2p)
+int tegra_cpu_do_idle(void)
 {
-        /* Switch to the identity mapping. */
-        cpu_switch_mm(idmap_pgd, &init_mm);
-
-        /* Flush the TLB. */
-        local_flush_tlb_all();
+        return cpu_do_idle();
+}
 
+static int tegra_sleep_cpu(unsigned long v2p)
+{
+        setup_mm_for_reboot();
         tegra_sleep_cpu_finish(v2p);
 
         /* should never here */
@@ -197,16 +139,9 @@ static int tegra_sleep_cpu(unsigned long v2p)
         return 0;
 }
 
-void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
+void tegra_idle_lp2_last(void)
 {
-        u32 mode;
-
-        /* Only the last cpu down does the final suspend steps */
-        mode = readl(pmc + PMC_CTRL);
-        mode |= TEGRA_POWER_CPU_PWRREQ_OE;
-        writel(mode, pmc + PMC_CTRL);
-
-        set_power_timers(cpu_on_time, cpu_off_time);
+        tegra_pmc_pm_set(TEGRA_SUSPEND_LP2);
 
         cpu_cluster_pm_enter();
         suspend_cpu_complex();
@@ -216,4 +151,81 @@ void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
         restore_cpu_complex();
         cpu_cluster_pm_exit();
 }
+
+enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
+                                enum tegra_suspend_mode mode)
+{
+        /* Tegra114 didn't support any suspending mode yet. */
+        if (tegra_chip_id == TEGRA114)
+                return TEGRA_SUSPEND_NONE;
+
+        /*
+         * The Tegra devices only support suspending to LP2 currently.
+         */
+        if (mode > TEGRA_SUSPEND_LP2)
+                return TEGRA_SUSPEND_LP2;
+
+        return mode;
+}
+
+static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
+        [TEGRA_SUSPEND_NONE] = "none",
+        [TEGRA_SUSPEND_LP2] = "LP2",
+        [TEGRA_SUSPEND_LP1] = "LP1",
+        [TEGRA_SUSPEND_LP0] = "LP0",
+};
+
+static int __cpuinit tegra_suspend_enter(suspend_state_t state)
+{
+        enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
+
+        if (WARN_ON(mode < TEGRA_SUSPEND_NONE ||
+                    mode >= TEGRA_MAX_SUSPEND_MODE))
+                return -EINVAL;
+
+        pr_info("Entering suspend state %s\n", lp_state[mode]);
+
+        tegra_pmc_pm_set(mode);
+
+        local_fiq_disable();
+
+        suspend_cpu_complex();
+        switch (mode) {
+        case TEGRA_SUSPEND_LP2:
+                tegra_set_cpu_in_lp2(0);
+                break;
+        default:
+                break;
+        }
+
+        cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
+
+        switch (mode) {
+        case TEGRA_SUSPEND_LP2:
+                tegra_clear_cpu_in_lp2(0);
+                break;
+        default:
+                break;
+        }
+        restore_cpu_complex();
+
+        local_fiq_enable();
+
+        return 0;
+}
+
+static const struct platform_suspend_ops tegra_suspend_ops = {
+        .valid          = suspend_valid_only_mem,
+        .enter          = tegra_suspend_enter,
+};
+
+void __init tegra_init_suspend(void)
+{
+        if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE)
+                return;
+
+        tegra_pmc_suspend_init();
+
+        suspend_set_ops(&tegra_suspend_ops);
+}
 #endif
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 787335cc964c..778a4aa7c3fa 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -21,6 +21,8 @@
 #ifndef _MACH_TEGRA_PM_H_
 #define _MACH_TEGRA_PM_H_
 
+#include "pmc.h"
+
 extern unsigned long l2x0_saved_regs_addr;
 
 void save_cpu_arch_register(void);
@@ -29,7 +31,20 @@ void restore_cpu_arch_register(void);
 void tegra_clear_cpu_in_lp2(int phy_cpu_id);
 bool tegra_set_cpu_in_lp2(int phy_cpu_id);
 
-void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time);
+void tegra_idle_lp2_last(void);
 extern void (*tegra_tear_down_cpu)(void);
 
+#ifdef CONFIG_PM_SLEEP
+enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
+                                enum tegra_suspend_mode mode);
+void tegra_init_suspend(void);
+#else
+static inline enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
+                                enum tegra_suspend_mode mode)
+{
+        return TEGRA_SUSPEND_NONE;
+}
+static inline void tegra_init_suspend(void) {}
+#endif
+
 #endif /* _MACH_TEGRA_PM_H_ */
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index d4fdb5fcec20..32360e540ce6 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
+ * Copyright (C) 2012,2013 NVIDIA CORPORATION. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -16,59 +16,313 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 
-#include "iomap.h"
+#include "fuse.h"
+#include "pm.h"
+#include "pmc.h"
+#include "sleep.h"
 
-#define PMC_CTRL                0x0
-#define PMC_CTRL_INTR_LOW       (1 << 17)
+#define TEGRA_POWER_EFFECT_LP0          (1 << 14)  /* LP0 when CPU pwr gated */
+#define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15)  /* CPU pwr req polarity */
+#define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU pwr req enable */
+
+#define PMC_CTRL                        0x0
+#define PMC_CTRL_INTR_LOW               (1 << 17)
+#define PMC_PWRGATE_TOGGLE              0x30
+#define PMC_PWRGATE_TOGGLE_START        (1 << 8)
+#define PMC_REMOVE_CLAMPING             0x34
+#define PMC_PWRGATE_STATUS              0x38
+
+#define PMC_CPUPWRGOOD_TIMER    0xc8
+#define PMC_CPUPWROFF_TIMER     0xcc
+
+#define TEGRA_POWERGATE_PCIE    3
+#define TEGRA_POWERGATE_VDEC    4
+#define TEGRA_POWERGATE_CPU1    9
+#define TEGRA_POWERGATE_CPU2    10
+#define TEGRA_POWERGATE_CPU3    11
+
+static u8 tegra_cpu_domains[] = {
+        0xFF,                   /* not available for CPU0 */
+        TEGRA_POWERGATE_CPU1,
+        TEGRA_POWERGATE_CPU2,
+        TEGRA_POWERGATE_CPU3,
+};
+static DEFINE_SPINLOCK(tegra_powergate_lock);
+
+static void __iomem *tegra_pmc_base;
+static bool tegra_pmc_invert_interrupt;
+static struct clk *tegra_pclk;
+
+struct pmc_pm_data {
+        u32 cpu_good_time;      /* CPU power good time in uS */
+        u32 cpu_off_time;       /* CPU power off time in uS */
+        u32 core_osc_time;      /* Core power good osc time in uS */
+        u32 core_pmu_time;      /* Core power good pmu time in uS */
+        u32 core_off_time;      /* Core power off time in uS */
+        bool corereq_high;      /* Core power request active-high */
+        bool sysclkreq_high;    /* System clock request active-high */
+        bool combined_req;      /* Combined pwr req for CPU & Core */
+        bool cpu_pwr_good_en;   /* CPU power good signal is enabled */
+        u32 lp0_vec_phy_addr;   /* The phy addr of LP0 warm boot code */
+        u32 lp0_vec_size;       /* The size of LP0 warm boot code */
+        enum tegra_suspend_mode suspend_mode;
+};
+static struct pmc_pm_data pmc_pm_data;
 
 static inline u32 tegra_pmc_readl(u32 reg)
 {
-        return readl(IO_ADDRESS(TEGRA_PMC_BASE + reg));
+        return readl(tegra_pmc_base + reg);
 }
 
 static inline void tegra_pmc_writel(u32 val, u32 reg)
 {
-        writel(val, IO_ADDRESS(TEGRA_PMC_BASE + reg));
+        writel(val, tegra_pmc_base + reg);
+}
+
+static int tegra_pmc_get_cpu_powerdomain_id(int cpuid)
+{
+        if (cpuid <= 0 || cpuid >= num_possible_cpus())
+                return -EINVAL;
+        return tegra_cpu_domains[cpuid];
+}
+
+static bool tegra_pmc_powergate_is_powered(int id)
+{
+        return (tegra_pmc_readl(PMC_PWRGATE_STATUS) >> id) & 1;
+}
+
+static int tegra_pmc_powergate_set(int id, bool new_state)
+{
+        bool old_state;
+        unsigned long flags;
+
+        spin_lock_irqsave(&tegra_powergate_lock, flags);
+
+        old_state = tegra_pmc_powergate_is_powered(id);
+        WARN_ON(old_state == new_state);
+
+        tegra_pmc_writel(PMC_PWRGATE_TOGGLE_START | id, PMC_PWRGATE_TOGGLE);
+
+        spin_unlock_irqrestore(&tegra_powergate_lock, flags);
+
+        return 0;
+}
+
+static int tegra_pmc_powergate_remove_clamping(int id)
+{
+        u32 mask;
+
+        /*
+         * Tegra has a bug where PCIE and VDE clamping masks are
+         * swapped relatively to the partition ids.
+         */
+        if (id ==  TEGRA_POWERGATE_VDEC)
+                mask = (1 << TEGRA_POWERGATE_PCIE);
+        else if (id == TEGRA_POWERGATE_PCIE)
+                mask = (1 << TEGRA_POWERGATE_VDEC);
+        else
+                mask = (1 << id);
+
+        tegra_pmc_writel(mask, PMC_REMOVE_CLAMPING);
+
+        return 0;
+}
+
+bool tegra_pmc_cpu_is_powered(int cpuid)
+{
+        int id;
+
+        id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
+        if (id < 0)
+                return false;
+        return tegra_pmc_powergate_is_powered(id);
 }
 
-#ifdef CONFIG_OF
+int tegra_pmc_cpu_power_on(int cpuid)
+{
+        int id;
+
+        id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
+        if (id < 0)
+                return id;
+        return tegra_pmc_powergate_set(id, true);
+}
+
+int tegra_pmc_cpu_remove_clamping(int cpuid)
+{
+        int id;
+
+        id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
+        if (id < 0)
+                return id;
+        return tegra_pmc_powergate_remove_clamping(id);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate)
+{
+        unsigned long long ticks;
+        unsigned long long pclk;
+        static unsigned long tegra_last_pclk;
+
+        if (WARN_ON_ONCE(rate <= 0))
+                pclk = 100000000;
+        else
+                pclk = rate;
+
+        if ((rate != tegra_last_pclk)) {
+                ticks = (us_on * pclk) + 999999ull;
+                do_div(ticks, 1000000);
+                tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWRGOOD_TIMER);
+
+                ticks = (us_off * pclk) + 999999ull;
+                do_div(ticks, 1000000);
+                tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWROFF_TIMER);
+                wmb();
+        }
+        tegra_last_pclk = pclk;
+}
+
+enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
+{
+        return pmc_pm_data.suspend_mode;
+}
+
+void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
+{
+        u32 reg;
+        unsigned long rate = 0;
+
+        reg = tegra_pmc_readl(PMC_CTRL);
+        reg |= TEGRA_POWER_CPU_PWRREQ_OE;
+        reg &= ~TEGRA_POWER_EFFECT_LP0;
+
+        switch (mode) {
+        case TEGRA_SUSPEND_LP2:
+                rate = clk_get_rate(tegra_pclk);
+                break;
+        default:
+                break;
+        }
+
+        set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time,
+                         rate);
+
+        tegra_pmc_writel(reg, PMC_CTRL);
+}
+
+void tegra_pmc_suspend_init(void)
+{
+        u32 reg;
+
+        /* Always enable CPU power request */
+        reg = tegra_pmc_readl(PMC_CTRL);
+        reg |= TEGRA_POWER_CPU_PWRREQ_OE;
+        tegra_pmc_writel(reg, PMC_CTRL);
+}
+#endif
+
 static const struct of_device_id matches[] __initconst = {
+        { .compatible = "nvidia,tegra114-pmc" },
+        { .compatible = "nvidia,tegra30-pmc" },
         { .compatible = "nvidia,tegra20-pmc" },
         { }
 };
-#endif
 
-void __init tegra_pmc_init(void)
+static void tegra_pmc_parse_dt(void)
 {
-        /*
-         * For now, Harmony is the only board that uses the PMC, and it wants
-         * the signal inverted. Seaboard would too if it used the PMC.
-         * Hopefully by the time other boards want to use the PMC, everything
-         * will be device-tree, or they also want it inverted.
-         */
-        bool invert_interrupt = true;
-        u32 val;
+        struct device_node *np;
+        u32 prop;
+        enum tegra_suspend_mode suspend_mode;
+        u32 core_good_time[2] = {0, 0};
+        u32 lp0_vec[2] = {0, 0};
 
-#ifdef CONFIG_OF
-        if (of_have_populated_dt()) {
-                struct device_node *np;
+        np = of_find_matching_node(NULL, matches);
+        BUG_ON(!np);
 
-                invert_interrupt = false;
+        tegra_pmc_base = of_iomap(np, 0);
 
-                np = of_find_matching_node(NULL, matches);
-                if (np) {
-                        if (of_find_property(np, "nvidia,invert-interrupt",
-                                                NULL))
-                                invert_interrupt = true;
+        tegra_pmc_invert_interrupt = of_property_read_bool(np,
+                                     "nvidia,invert-interrupt");
+        tegra_pclk = of_clk_get_by_name(np, "pclk");
+        WARN_ON(IS_ERR(tegra_pclk));
+
+        /* Grabbing the power management configurations */
+        if (of_property_read_u32(np, "nvidia,suspend-mode", &prop)) {
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        } else {
+                switch (prop) {
+                case 0:
+                        suspend_mode = TEGRA_SUSPEND_LP0;
+                        break;
+                case 1:
+                        suspend_mode = TEGRA_SUSPEND_LP1;
+                        break;
+                case 2:
+                        suspend_mode = TEGRA_SUSPEND_LP2;
+                        break;
+                default:
+                        suspend_mode = TEGRA_SUSPEND_NONE;
+                        break;
                 }
         }
-#endif
+        suspend_mode = tegra_pm_validate_suspend_mode(suspend_mode);
+
+        if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.cpu_good_time = prop;
+
+        if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &prop))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.cpu_off_time = prop;
+
+        if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
+                        core_good_time, ARRAY_SIZE(core_good_time)))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.core_osc_time = core_good_time[0];
+        pmc_pm_data.core_pmu_time = core_good_time[1];
+
+        if (of_property_read_u32(np, "nvidia,core-pwr-off-time",
+                                 &prop))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.core_off_time = prop;
+
+        pmc_pm_data.corereq_high = of_property_read_bool(np,
+                                "nvidia,core-power-req-active-high");
+
+        pmc_pm_data.sysclkreq_high = of_property_read_bool(np,
+                                "nvidia,sys-clock-req-active-high");
+
+        pmc_pm_data.combined_req = of_property_read_bool(np,
+                                "nvidia,combined-power-req");
+
+        pmc_pm_data.cpu_pwr_good_en = of_property_read_bool(np,
+                                "nvidia,cpu-pwr-good-en");
+
+        if (of_property_read_u32_array(np, "nvidia,lp0-vec", lp0_vec,
+                                       ARRAY_SIZE(lp0_vec)))
+                if (suspend_mode == TEGRA_SUSPEND_LP0)
+                        suspend_mode = TEGRA_SUSPEND_LP1;
+
+        pmc_pm_data.lp0_vec_phy_addr = lp0_vec[0];
+        pmc_pm_data.lp0_vec_size = lp0_vec[1];
+
+        pmc_pm_data.suspend_mode = suspend_mode;
+}
+
+void __init tegra_pmc_init(void)
+{
+        u32 val;
+
+        tegra_pmc_parse_dt();
 
         val = tegra_pmc_readl(PMC_CTRL);
-        if (invert_interrupt)
+        if (tegra_pmc_invert_interrupt)
                 val |= PMC_CTRL_INTR_LOW;
         else
                 val &= ~PMC_CTRL_INTR_LOW;
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h
index 8995ee4a8768..e1c2df272f7d 100644
--- a/arch/arm/mach-tegra/pmc.h
+++ b/arch/arm/mach-tegra/pmc.h
@@ -18,6 +18,24 @@
 #ifndef __MACH_TEGRA_PMC_H
 #define __MACH_TEGRA_PMC_H
 
+enum tegra_suspend_mode {
+        TEGRA_SUSPEND_NONE = 0,
+        TEGRA_SUSPEND_LP2,      /* CPU voltage off */
+        TEGRA_SUSPEND_LP1,      /* CPU voltage off, DRAM self-refresh */
+        TEGRA_SUSPEND_LP0,      /* CPU + core voltage off, DRAM self-refresh */
+        TEGRA_MAX_SUSPEND_MODE,
+};
+
+#ifdef CONFIG_PM_SLEEP
+enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
+void tegra_pmc_pm_set(enum tegra_suspend_mode mode);
+void tegra_pmc_suspend_init(void);
+#endif
+
+bool tegra_pmc_cpu_is_powered(int cpuid);
+int tegra_pmc_cpu_power_on(int cpuid);
+int tegra_pmc_cpu_remove_clamping(int cpuid);
+
 void tegra_pmc_init(void);
 
 #endif
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index c6bc8f85759c..f076f0f80fcd 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -22,13 +22,13 @@
 #include <linux/debugfs.h>
 #include <linux/delay.h>
 #include <linux/err.h>
+#include <linux/export.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/seq_file.h>
 #include <linux/spinlock.h>
 #include <linux/clk/tegra.h>
-
-#include <mach/powergate.h>
+#include <linux/tegra-powergate.h>
 
 #include "fuse.h"
 #include "iomap.h"
@@ -75,7 +75,7 @@ static int tegra_powergate_set(int id, bool new_state)
 
         if (status == new_state) {
                 spin_unlock_irqrestore(&tegra_powergate_lock, flags);
-                return -EINVAL;
+                return 0;
         }
 
         pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
@@ -168,6 +168,7 @@ err_clk:
 err_power:
         return ret;
 }
+EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
 
 int tegra_cpu_powergate_id(int cpuid)
 {
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 54382ceade4a..e6de88a2ea06 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -41,12 +41,10 @@
  */
 ENTRY(tegra_resume)
         bl      v7_invalidate_l1
-        /* Enable coresight */
-        mov32   r0, 0xC5ACCE55
-        mcr     p14, 0, r0, c7, c12, 6
 
         cpu_id  r0
         cmp     r0, #0                          @ CPU0?
+ THUMB( it      ne )
         bne     cpu_resume                      @ no
 
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
@@ -99,6 +97,8 @@ ENTRY(__tegra_cpu_reset_handler_start)
  *
  * Register usage within the reset handler:
  *
+ *      Others: scratch
+ *      R6  = SoC ID << 8
  *      R7  = CPU present (to the OS) mask
  *      R8  = CPU in LP1 state mask
  *      R9  = CPU in LP2 state mask
@@ -114,6 +114,40 @@ ENTRY(__tegra_cpu_reset_handler_start)
 ENTRY(__tegra_cpu_reset_handler)
 
         cpsid   aif, 0x13                       @ SVC mode, interrupts disabled
+
+        mov32   r6, TEGRA_APB_MISC_BASE
+        ldr     r6, [r6, #APB_MISC_GP_HIDREV]
+        and     r6, r6, #0xff00
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+t20_check:
+        cmp     r6, #(0x20 << 8)
+        bne     after_t20_check
+t20_errata:
+        # Tegra20 is a Cortex-A9 r1p1
+        mrc     p15, 0, r0, c1, c0, 0   @ read system control register
+        orr     r0, r0, #1 << 14        @ erratum 716044
+        mcr     p15, 0, r0, c1, c0, 0   @ write system control register
+        mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
+        orr     r0, r0, #1 << 4         @ erratum 742230
+        orr     r0, r0, #1 << 11        @ erratum 751472
+        mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
+        b       after_errata
+after_t20_check:
+#endif
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+t30_check:
+        cmp     r6, #(0x30 << 8)
+        bne     after_t30_check
+t30_errata:
+        # Tegra30 is a Cortex-A9 r2p9
+        mrc     p15, 0, r0, c15, c0, 1  @ read diagnostic register
+        orr     r0, r0, #1 << 6         @ erratum 743622
+        orr     r0, r0, #1 << 11        @ erratum 751472
+        mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
+        b       after_errata
+after_t30_check:
+#endif
+after_errata:
         mrc     p15, 0, r10, c0, c0, 5          @ MPIDR
         and     r10, r10, #0x3                  @ R10 = CPU number
         mov     r11, #1
@@ -129,16 +163,13 @@ ENTRY(__tegra_cpu_reset_handler)
 
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
         /* Are we on Tegra20? */
-        mov32   r6, TEGRA_APB_MISC_BASE
-        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
-        and     r0, r0, #0xff00
-        cmp     r0, #(0x20 << 8)
+        cmp     r6, #(0x20 << 8)
         bne     1f
         /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
-        mov32   r6, TEGRA_PMC_BASE
+        mov32   r5, TEGRA_PMC_BASE
         mov     r0, #0
         cmp     r10, #0
-        strne   r0, [r6, #PMC_SCRATCH41]
+        strne   r0, [r5, #PMC_SCRATCH41]
 1:
 #endif
 
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index 9f6bfafdd512..e3f2417c420e 100644
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -197,7 +197,7 @@ ENTRY(tegra20_sleep_cpu_secondary_finish)
         mov     r3, #CPU_RESETTABLE
         str     r3, [r0]
 
-        bl      cpu_do_idle
+        bl      tegra_cpu_do_idle
 
         /*
          * cpu may be reset while in wfi, which will return through
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 63a15bd9b653..d29dfcce948d 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -66,7 +66,9 @@ ENTRY(tegra30_cpu_shutdown)
                 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
                 FLOW_CTRL_CSR_ENABLE
         mov     r4, #(1 << 4)
-        orr     r12, r12, r4, lsl r3
+ ARM(   orr     r12, r12, r4, lsl r3    )
+ THUMB( lsl     r4, r4, r3              )
+ THUMB( orr     r12, r12, r4            )
         str     r12, [r1]
 
         /* Halt this CPU. */
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 4ffae541726e..2080fb12ce26 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -92,7 +92,7 @@
 
 #ifdef CONFIG_CACHE_L2X0
 .macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
-        adr     \tmp1, \phys_l2x0_saved_regs
+        W(adr)  \tmp1, \phys_l2x0_saved_regs
         ldr     \tmp1, [\tmp1]
         ldr     \tmp2, [\tmp1, #L2X0_R_PHY_BASE]
         ldr     \tmp3, [\tmp2, #L2X0_CTRL]
@@ -124,11 +124,11 @@ int tegra_sleep_cpu_finish(unsigned long);
 void tegra_disable_clean_inv_dcache(void);
 
 #ifdef CONFIG_HOTPLUG_CPU
-void tegra20_hotplug_init(void);
-void tegra30_hotplug_init(void);
+void tegra20_hotplug_shutdown(void);
+void tegra30_hotplug_shutdown(void);
+void tegra_hotplug_init(void);
 #else
-static inline void tegra20_hotplug_init(void) {}
-static inline void tegra30_hotplug_init(void) {}
+static inline void tegra_hotplug_init(void) {}
 #endif
 
 void tegra20_cpu_shutdown(int cpu);
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/tegra.c
index a0edf2510280..0d1e4128d460 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -1,6 +1,7 @@
 /*
- * nVidia Tegra device tree board support
+ * NVIDIA Tegra SoC device tree board support
  *
+ * Copyright (C) 2011, 2013, NVIDIA Corporation
  * Copyright (C) 2010 Secret Lab Technologies, Ltd.
  * Copyright (C) 2010 Google, Inc.
  *
@@ -30,9 +31,10 @@
 #include <linux/pda_power.h>
 #include <linux/platform_data/tegra_usb.h>
 #include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/i2c-tegra.h>
+#include <linux/slab.h>
+#include <linux/sys_soc.h>
 #include <linux/usb/tegra_usb_phy.h>
+#include <linux/clk/tegra.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -41,6 +43,7 @@
 
 #include "board.h"
 #include "common.h"
+#include "fuse.h"
 #include "iomap.h"
 
 static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
@@ -79,12 +82,38 @@ static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 
 static void __init tegra_dt_init(void)
 {
+        struct soc_device_attribute *soc_dev_attr;
+        struct soc_device *soc_dev;
+        struct device *parent = NULL;
+
+        tegra_clocks_apply_init_table();
+
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                goto out;
+
+        soc_dev_attr->family = kasprintf(GFP_KERNEL, "Tegra");
+        soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_revision);
+        soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%d", tegra_chip_id);
+
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR(soc_dev)) {
+                kfree(soc_dev_attr->family);
+                kfree(soc_dev_attr->revision);
+                kfree(soc_dev_attr->soc_id);
+                kfree(soc_dev_attr);
+                goto out;
+        }
+
+        parent = soc_device_to_device(soc_dev);
+
         /*
          * Finished with the static registrations now; fill in the missing
          * devices
          */
+out:
         of_platform_populate(NULL, of_default_bus_match_table,
-                                tegra20_auxdata_lookup, NULL);
+                                tegra20_auxdata_lookup, parent);
 }
 
 static void __init trimslice_init(void)
@@ -111,7 +140,8 @@ static void __init harmony_init(void)
 
 static void __init paz00_init(void)
 {
-        tegra_paz00_wifikill_init();
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
+                tegra_paz00_wifikill_init();
 }
 
 static struct {
@@ -137,19 +167,21 @@ static void __init tegra_dt_init_late(void)
         }
 }
 
-static const char *tegra20_dt_board_compat[] = {
+static const char * const tegra_dt_board_compat[] = {
+        "nvidia,tegra114",
+        "nvidia,tegra30",
         "nvidia,tegra20",
         NULL
 };
 
-DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
+DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
         .map_io         = tegra_map_common_io,
         .smp            = smp_ops(tegra_smp_ops),
-        .init_early     = tegra20_init_early,
+        .init_early     = tegra_init_early,
         .init_irq       = tegra_dt_init_irq,
         .init_time      = clocksource_of_init,
         .init_machine   = tegra_dt_init,
         .init_late      = tegra_dt_init_late,
         .restart        = tegra_assert_system_reset,
-        .dt_compat      = tegra20_dt_board_compat,
+        .dt_compat      = tegra_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/tegra114_speedo.c b/arch/arm/mach-tegra/tegra114_speedo.c
new file mode 100644
index 000000000000..5218d4853cd3
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra114_speedo.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bug.h>
+
+#include "fuse.h"
+
+#define CORE_PROCESS_CORNERS_NUM        2
+#define CPU_PROCESS_CORNERS_NUM         2
+
+enum {
+        THRESHOLD_INDEX_0,
+        THRESHOLD_INDEX_1,
+        THRESHOLD_INDEX_COUNT,
+};
+
+static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
+        {1123,     UINT_MAX},
+        {0,        UINT_MAX},
+};
+
+static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
+        {1695,     UINT_MAX},
+        {0,        UINT_MAX},
+};
+
+static void rev_sku_to_speedo_ids(int rev, int sku, int *threshold)
+{
+        u32 tmp;
+
+        switch (sku) {
+        case 0x00:
+        case 0x10:
+        case 0x05:
+        case 0x06:
+                tegra_cpu_speedo_id = 1;
+                tegra_soc_speedo_id = 0;
+                *threshold = THRESHOLD_INDEX_0;
+                break;
+
+        case 0x03:
+        case 0x04:
+                tegra_cpu_speedo_id = 2;
+                tegra_soc_speedo_id = 1;
+                *threshold = THRESHOLD_INDEX_1;
+                break;
+
+        default:
+                pr_err("Tegra114 Unknown SKU %d\n", sku);
+                tegra_cpu_speedo_id = 0;
+                tegra_soc_speedo_id = 0;
+                *threshold = THRESHOLD_INDEX_0;
+                break;
+        }
+
+        if (rev == TEGRA_REVISION_A01) {
+                tmp = tegra_fuse_readl(0x270) << 1;
+                tmp |= tegra_fuse_readl(0x26c);
+                if (!tmp)
+                        tegra_cpu_speedo_id = 0;
+        }
+}
+
+void tegra114_init_speedo_data(void)
+{
+        u32 cpu_speedo_val;
+        u32 core_speedo_val;
+        int threshold;
+        int i;
+
+        BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
+                        THRESHOLD_INDEX_COUNT);
+        BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
+                        THRESHOLD_INDEX_COUNT);
+
+        rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id, &threshold);
+
+        cpu_speedo_val = tegra_fuse_readl(0x12c) + 1024;
+        core_speedo_val = tegra_fuse_readl(0x134);
+
+        for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++)
+                if (cpu_speedo_val < cpu_process_speedos[threshold][i])
+                        break;
+        tegra_cpu_process_id = i;
+
+        for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++)
+                if (core_speedo_val < core_process_speedos[threshold][i])
+                        break;
+        tegra_core_process_id = i;
+}
diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c
index ce7ce42a1ac9..9e8bdfa2b369 100644
--- a/arch/arm/mach-tegra/tegra2_emc.c
+++ b/arch/arm/mach-tegra/tegra2_emc.c
@@ -276,7 +276,7 @@ static struct tegra_emc_pdata *tegra_emc_fill_pdata(struct platform_device *pdev
         int i;
 
         WARN_ON(pdev->dev.platform_data);
-        BUG_ON(IS_ERR_OR_NULL(c));
+        BUG_ON(IS_ERR(c));
 
         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
         pdata->tables = devm_kzalloc(&pdev->dev, sizeof(*pdata->tables),
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
index 1e49d901f2c9..0320495efc4d 100644
--- a/arch/arm/mach-u300/include/mach/u300-regs.h
+++ b/arch/arm/mach-u300/include/mach/u300-regs.h
@@ -95,7 +95,7 @@
 #define U300_SPI_BASE                   (U300_FAST_PER_PHYS_BASE+0x6000)
 
 /* Fast UART1 on U335 only */
-#define U300_UART1_BASE                 (U300_SLOW_PER_PHYS_BASE+0x7000)
+#define U300_UART1_BASE                 (U300_FAST_PER_PHYS_BASE+0x7000)
 
 /*
  * SLOW peripherals
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 3e5bbd0e5b23..f66d7deae46d 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -1,3 +1,19 @@
+config ARCH_U8500
+        bool "ST-Ericsson U8500 Series" if ARCH_MULTI_V7
+        depends on MMU
+        select ARCH_HAS_CPUFREQ
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_AMBA
+        select CLKDEV_LOOKUP
+        select CPU_V7
+        select GENERIC_CLOCKEVENTS
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_SMP
+        select MIGHT_HAVE_CACHE_L2X0
+        help
+          Support for ST-Ericsson's Ux500 architecture
+
 if ARCH_U8500
 
 config UX500_SOC_COMMON
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index f24710dfc395..bf9b6be5b180 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -3,7 +3,7 @@
 #
 
 obj-y                           := cpu.o devices.o devices-common.o \
-                                   id.o usb.o timer.o
+                                   id.o usb.o timer.o pm.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
 obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o
@@ -15,3 +15,5 @@ obj-$(CONFIG_MACH_MOP500)	+= board-mop500.o board-mop500-sdi.o \
                                 board-mop500-audio.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
+
+CFLAGS_hotplug.o                += -march=armv7-a
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index 7209db7cdc72..aba9e5692958 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -10,10 +10,9 @@
 #include <linux/platform_data/pinctrl-nomadik.h>
 #include <linux/platform_data/dma-ste-dma40.h>
 
-#include <mach/devices.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include <mach/msp.h>
+#include "devices.h"
+#include "irqs.h"
+#include <linux/platform_data/asoc-ux500-msp.h>
 
 #include "ste-dma40-db8500.h"
 #include "board-mop500.h"
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 0a3f30df1eb8..947bd9eca079 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -13,8 +13,6 @@
 
 #include <asm/mach-types.h>
 
-#include <mach/hardware.h>
-
 #include "pins-db8500.h"
 #include "board-mop500.h"
 
@@ -48,8 +46,12 @@ BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE);
 BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_in_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
+        PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
 BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(slpm_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
+        PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
 BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
 BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED|
@@ -78,9 +80,6 @@ BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
 #define DB8500_PIN_HOG(pin,conf) \
         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
-#define DB8500_PIN_SLEEP(pin, conf, dev) \
-        PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
-                            pin, conf)
 
 /* These are default states associated with device and changed runtime */
 #define DB8500_MUX(group,func,dev) \
@@ -309,8 +308,23 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
         DB8500_PIN_SLEEP("GPIO207_AJ23", slpm_in_wkup_pdis, "sdi4"), /* DAT4 */
 
         /* Mux in USB pins, drive STP high */
-        DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
-        DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
+        /* USB default state */
+        DB8500_MUX("usb_a_1", "usb", "ab8500-usb.0"),
+        DB8500_PIN("GPIO257_AE29", out_hi, "ab8500-usb.0"), /* STP */
+        /* USB sleep state */
+        DB8500_PIN_SLEEP("GPIO256_AF28", slpm_wkup_pdis_en, "ab8500-usb.0"), /* NXT */
+        DB8500_PIN_SLEEP("GPIO257_AE29", slpm_out_hi_wkup_pdis, "ab8500-usb.0"), /* STP */
+        DB8500_PIN_SLEEP("GPIO258_AD29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* XCLK */
+        DB8500_PIN_SLEEP("GPIO259_AC29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* DIR */
+        DB8500_PIN_SLEEP("GPIO260_AD28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT7 */
+        DB8500_PIN_SLEEP("GPIO261_AD26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT6 */
+        DB8500_PIN_SLEEP("GPIO262_AE26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT5 */
+        DB8500_PIN_SLEEP("GPIO263_AG29", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT4 */
+        DB8500_PIN_SLEEP("GPIO264_AE27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT3 */
+        DB8500_PIN_SLEEP("GPIO265_AD27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT2 */
+        DB8500_PIN_SLEEP("GPIO266_AC28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT1 */
+        DB8500_PIN_SLEEP("GPIO267_AC27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT0 */
+
         /* Mux in SPI2 pins on the "other C1" altfunction */
         DB8500_MUX("spi2_oc1_2", "spi2", "spi2"),
         DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
@@ -318,9 +332,9 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
         DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
         DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
         /* SPI2 idle state */
-        DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
-        DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
-        DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
+        DB8500_PIN_IDLE("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
+        DB8500_PIN_IDLE("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
+        DB8500_PIN_IDLE("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
         /* SPI2 sleep state */
         DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */
         DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
@@ -747,6 +761,8 @@ static struct pinctrl_map __initdata snowball_pinmap[] = {
         DB8500_PIN_HOG("GPIO21_AB3", out_hi),
         /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
         DB8500_MUX_HOG("sm_b_1", "sm"),
+        /* User LED */
+        DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi),
         /* Drive RSTn_LAN high */
         DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
         /*  Accelerometer/Magnetometer */
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index 2a17bc506cff..33c353bc1c4a 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -5,6 +5,7 @@
  *
  * Authors: Sundar Iyer <sundar.iyer@stericsson.com>
  *          Bengt Jonsson <bengt.g.jonsson@stericsson.com>
+ *          Daniel Willerud <daniel.willerud@stericsson.com>
  *
  * MOP500 board specific initialization for regulators
  */
@@ -12,6 +13,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/ab8500.h>
 #include "board-mop500-regulators.h"
+#include "id.h"
 
 static struct regulator_consumer_supply gpio_en_3v3_consumers[] = {
        REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
@@ -28,6 +30,20 @@ struct regulator_init_data gpio_en_3v3_regulator = {
        .consumer_supplies = gpio_en_3v3_consumers,
 };
 
+static struct regulator_consumer_supply sdi0_reg_consumers[] = {
+        REGULATOR_SUPPLY("vqmmc", "sdi0"),
+};
+
+struct regulator_init_data sdi0_reg_init_data = {
+        .constraints = {
+                .min_uV         = 1800000,
+                .max_uV         = 2900000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(sdi0_reg_consumers),
+        .consumer_supplies      = sdi0_reg_consumers,
+};
+
 /*
  * TPS61052 regulator
  */
@@ -53,21 +69,37 @@ struct regulator_init_data tps61052_regulator = {
 };
 
 static struct regulator_consumer_supply ab8500_vaux1_consumers[] = {
-        /* External displays, connector on board 2v5 power supply */
-        REGULATOR_SUPPLY("vaux12v5", "mcde.0"),
+        /* Main display, u8500 R3 uib */
+        REGULATOR_SUPPLY("vddi", "mcde_disp_sony_acx424akp.0"),
+        /* Main display, u8500 uib and ST uib */
+        REGULATOR_SUPPLY("vdd1", "samsung_s6d16d0.0"),
+        /* Secondary display, ST uib */
+        REGULATOR_SUPPLY("vdd1", "samsung_s6d16d0.1"),
         /* SFH7741 proximity sensor */
         REGULATOR_SUPPLY("vcc", "gpio-keys.0"),
         /* BH1780GLS ambient light sensor */
         REGULATOR_SUPPLY("vcc", "2-0029"),
         /* lsm303dlh accelerometer */
-        REGULATOR_SUPPLY("vdd", "3-0018"),
+        REGULATOR_SUPPLY("vdd", "2-0018"),
+        /* lsm303dlhc accelerometer */
+        REGULATOR_SUPPLY("vdd", "2-0019"),
         /* lsm303dlh magnetometer */
-        REGULATOR_SUPPLY("vdd", "3-001e"),
+        REGULATOR_SUPPLY("vdd", "2-001e"),
         /* Rohm BU21013 Touchscreen devices */
         REGULATOR_SUPPLY("avdd", "3-005c"),
         REGULATOR_SUPPLY("avdd", "3-005d"),
         /* Synaptics RMI4 Touchscreen device */
         REGULATOR_SUPPLY("vdd", "3-004b"),
+        /* L3G4200D Gyroscope device */
+        REGULATOR_SUPPLY("vdd", "2-0068"),
+        /* Ambient light sensor device */
+        REGULATOR_SUPPLY("vdd", "3-0029"),
+        /* Pressure sensor device */
+        REGULATOR_SUPPLY("vdd", "2-005c"),
+        /* Cypress TrueTouch Touchscreen device */
+        REGULATOR_SUPPLY("vcpin", "spi8.0"),
+        /* Camera device */
+        REGULATOR_SUPPLY("vaux12v5", "mmio_camera"),
 };
 
 static struct regulator_consumer_supply ab8500_vaux2_consumers[] = {
@@ -75,18 +107,50 @@ static struct regulator_consumer_supply ab8500_vaux2_consumers[] = {
         REGULATOR_SUPPLY("vmmc", "sdi4"),
         /* AB8500 audio codec */
         REGULATOR_SUPPLY("vcc-N2158", "ab8500-codec.0"),
+        /* AB8500 accessory detect 1 */
+        REGULATOR_SUPPLY("vcc-N2158", "ab8500-acc-det.0"),
+        /* AB8500 Tv-out device */
+        REGULATOR_SUPPLY("vcc-N2158", "mcde_tv_ab8500.4"),
+        /* AV8100 HDMI device */
+        REGULATOR_SUPPLY("vcc-N2158", "av8100_hdmi.3"),
 };
 
 static struct regulator_consumer_supply ab8500_vaux3_consumers[] = {
+        REGULATOR_SUPPLY("v-SD-STM", "stm"),
         /* External MMC slot power */
         REGULATOR_SUPPLY("vmmc", "sdi0"),
 };
 
+static struct regulator_consumer_supply ab8505_vaux4_consumers[] = {
+};
+
+static struct regulator_consumer_supply ab8505_vaux5_consumers[] = {
+};
+
+static struct regulator_consumer_supply ab8505_vaux6_consumers[] = {
+};
+
+static struct regulator_consumer_supply ab8505_vaux8_consumers[] = {
+        /* AB8500 audio codec device */
+        REGULATOR_SUPPLY("v-aux8", NULL),
+};
+
+static struct regulator_consumer_supply ab8505_vadc_consumers[] = {
+        /* Internal general-purpose ADC */
+        REGULATOR_SUPPLY("vddadc", "ab8500-gpadc.0"),
+        /* ADC for charger */
+        REGULATOR_SUPPLY("vddadc", "ab8500-charger.0"),
+};
+
 static struct regulator_consumer_supply ab8500_vtvout_consumers[] = {
         /* TV-out DENC supply */
         REGULATOR_SUPPLY("vtvout", "ab8500-denc.0"),
         /* Internal general-purpose ADC */
         REGULATOR_SUPPLY("vddadc", "ab8500-gpadc.0"),
+        /* ADC for charger */
+        REGULATOR_SUPPLY("vddadc", "ab8500-charger.0"),
+        /* AB8500 Tv-out device */
+        REGULATOR_SUPPLY("vtvout", "mcde_tv_ab8500.4"),
 };
 
 static struct regulator_consumer_supply ab8500_vaud_consumers[] = {
@@ -114,77 +178,90 @@ static struct regulator_consumer_supply ab8500_vintcore_consumers[] = {
         REGULATOR_SUPPLY("v-intcore", NULL),
         /* USB Transceiver */
         REGULATOR_SUPPLY("vddulpivio18", "ab8500-usb.0"),
+        /* Handled by abx500 clk driver */
+        REGULATOR_SUPPLY("v-intcore", "abx500-clk.0"),
+};
+
+static struct regulator_consumer_supply ab8505_usb_consumers[] = {
+        /* HS USB OTG physical interface */
+        REGULATOR_SUPPLY("v-ape", NULL),
 };
 
 static struct regulator_consumer_supply ab8500_vana_consumers[] = {
-        /* External displays, connector on board, 1v8 power supply */
-        REGULATOR_SUPPLY("vsmps2", "mcde.0"),
+        /* DB8500 DSI */
+        REGULATOR_SUPPLY("vdddsi1v2", "mcde"),
+        REGULATOR_SUPPLY("vdddsi1v2", "b2r2_core"),
+        REGULATOR_SUPPLY("vdddsi1v2", "b2r2_1_core"),
+        REGULATOR_SUPPLY("vdddsi1v2", "dsilink.0"),
+        REGULATOR_SUPPLY("vdddsi1v2", "dsilink.1"),
+        REGULATOR_SUPPLY("vdddsi1v2", "dsilink.2"),
+        /* DB8500 CSI */
+        REGULATOR_SUPPLY("vddcsi1v2", "mmio_camera"),
 };
 
 /* ab8500 regulator register initialization */
-struct ab8500_regulator_reg_init
-ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS] = {
+static struct ab8500_regulator_reg_init ab8500_reg_init[] = {
         /*
          * VanaRequestCtrl          = HP/LP depending on VxRequest
          * VextSupply1RequestCtrl   = HP/LP depending on VxRequest
          */
-        INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL2, 0x00),
+        INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL2,       0xf0, 0x00),
         /*
          * VextSupply2RequestCtrl   = HP/LP depending on VxRequest
          * VextSupply3RequestCtrl   = HP/LP depending on VxRequest
          * Vaux1RequestCtrl         = HP/LP depending on VxRequest
          * Vaux2RequestCtrl         = HP/LP depending on VxRequest
          */
-        INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL3, 0x00),
+        INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL3,       0xff, 0x00),
         /*
          * Vaux3RequestCtrl         = HP/LP depending on VxRequest
          * SwHPReq                  = Control through SWValid disabled
          */
-        INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL4, 0x00),
+        INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL4,       0x07, 0x00),
         /*
          * VanaSysClkReq1HPValid    = disabled
          * Vaux1SysClkReq1HPValid   = disabled
          * Vaux2SysClkReq1HPValid   = disabled
          * Vaux3SysClkReq1HPValid   = disabled
          */
-        INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID1, 0x00),
+        INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID1, 0xe8, 0x00),
         /*
          * VextSupply1SysClkReq1HPValid = disabled
          * VextSupply2SysClkReq1HPValid = disabled
          * VextSupply3SysClkReq1HPValid = SysClkReq1 controlled
          */
-        INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID2, 0x40),
+        INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID2, 0x70, 0x40),
         /*
          * VanaHwHPReq1Valid        = disabled
          * Vaux1HwHPreq1Valid       = disabled
          * Vaux2HwHPReq1Valid       = disabled
          * Vaux3HwHPReqValid        = disabled
          */
-        INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID1, 0x00),
+        INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID1,     0xe8, 0x00),
         /*
          * VextSupply1HwHPReq1Valid = disabled
          * VextSupply2HwHPReq1Valid = disabled
          * VextSupply3HwHPReq1Valid = disabled
          */
-        INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID2, 0x00),
+        INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID2,     0x07, 0x00),
         /*
          * VanaHwHPReq2Valid        = disabled
          * Vaux1HwHPReq2Valid       = disabled
          * Vaux2HwHPReq2Valid       = disabled
          * Vaux3HwHPReq2Valid       = disabled
          */
-        INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID1, 0x00),
+        INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID1,     0xe8, 0x00),
         /*
          * VextSupply1HwHPReq2Valid = disabled
          * VextSupply2HwHPReq2Valid = disabled
          * VextSupply3HwHPReq2Valid = HWReq2 controlled
          */
-        INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID2, 0x04),
+        INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID2,     0x07, 0x04),
         /*
          * VanaSwHPReqValid         = disabled
          * Vaux1SwHPReqValid        = disabled
          */
-        INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID1, 0x00),
+        INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID1,      0xa0, 0x00),
         /*
          * Vaux2SwHPReqValid        = disabled
          * Vaux3SwHPReqValid        = disabled
@@ -192,7 +269,7 @@ ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS] = {
          * VextSupply2SwHPReqValid  = disabled
          * VextSupply3SwHPReqValid  = disabled
          */
-        INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID2, 0x00),
+        INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID2,      0x1f, 0x00),
         /*
          * SysClkReq2Valid1         = SysClkReq2 controlled
          * SysClkReq3Valid1         = disabled
@@ -202,7 +279,7 @@ ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS] = {
          * SysClkReq7Valid1         = disabled
          * SysClkReq8Valid1         = disabled
          */
-        INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID1, 0x2a),
+        INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID1,    0xfe, 0x2a),
         /*
          * SysClkReq2Valid2         = disabled
          * SysClkReq3Valid2         = disabled
@@ -212,7 +289,7 @@ ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS] = {
          * SysClkReq7Valid2         = disabled
          * SysClkReq8Valid2         = disabled
          */
-        INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID2, 0x20),
+        INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID2,    0xfe, 0x20),
         /*
          * VTVoutEna                = disabled
          * Vintcore12Ena            = disabled
@@ -220,66 +297,62 @@ ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS] = {
          * Vintcore12LP             = inactive (HP)
          * VTVoutLP                 = inactive (HP)
          */
-        INIT_REGULATOR_REGISTER(AB8500_REGUMISC1, 0x10),
+        INIT_REGULATOR_REGISTER(AB8500_REGUMISC1,              0xfe, 0x10),
         /*
          * VaudioEna                = disabled
          * VdmicEna                 = disabled
          * Vamic1Ena                = disabled
          * Vamic2Ena                = disabled
          */
-        INIT_REGULATOR_REGISTER(AB8500_VAUDIOSUPPLY, 0x00),
+        INIT_REGULATOR_REGISTER(AB8500_VAUDIOSUPPLY,           0x1e, 0x00),
         /*
          * Vamic1_dzout             = high-Z when Vamic1 is disabled
          * Vamic2_dzout             = high-Z when Vamic2 is disabled
          */
-        INIT_REGULATOR_REGISTER(AB8500_REGUCTRL1VAMIC, 0x00),
+        INIT_REGULATOR_REGISTER(AB8500_REGUCTRL1VAMIC,         0x03, 0x00),
         /*
-         * VPll                     = Hw controlled
+         * VPll                     = Hw controlled (NOTE! PRCMU bits)
          * VanaRegu                 = force off
          */
-        INIT_REGULATOR_REGISTER(AB8500_VPLLVANAREGU, 0x02),
+        INIT_REGULATOR_REGISTER(AB8500_VPLLVANAREGU,           0x0f, 0x02),
         /*
          * VrefDDREna               = disabled
          * VrefDDRSleepMode         = inactive (no pulldown)
          */
-        INIT_REGULATOR_REGISTER(AB8500_VREFDDR, 0x00),
+        INIT_REGULATOR_REGISTER(AB8500_VREFDDR,                0x03, 0x00),
         /*
-         * VextSupply1Regu          = HW control
-         * VextSupply2Regu          = HW control
-         * VextSupply3Regu          = HW control
+         * VextSupply1Regu          = force LP
+         * VextSupply2Regu          = force OFF
+         * VextSupply3Regu          = force HP (-> STBB2=LP and TPS=LP)
          * ExtSupply2Bypass         = ExtSupply12LPn ball is 0 when Ena is 0
          * ExtSupply3Bypass         = ExtSupply3LPn ball is 0 when Ena is 0
          */
-        INIT_REGULATOR_REGISTER(AB8500_EXTSUPPLYREGU, 0x2a),
+        INIT_REGULATOR_REGISTER(AB8500_EXTSUPPLYREGU,          0xff, 0x13),
         /*
          * Vaux1Regu                = force HP
          * Vaux2Regu                = force off
          */
-        INIT_REGULATOR_REGISTER(AB8500_VAUX12REGU, 0x01),
-        /*
-         * Vaux3regu                = force off
-         */
-        INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3REGU, 0x00),
+        INIT_REGULATOR_REGISTER(AB8500_VAUX12REGU,             0x0f, 0x01),
         /*
-         * Vsmps1                   = 1.15V
+         * Vaux3Regu                = force off
          */
-        INIT_REGULATOR_REGISTER(AB8500_VSMPS1SEL1, 0x24),
+        INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3REGU,          0x03, 0x00),
         /*
-         * Vaux1Sel                 = 2.5 V
+         * Vaux1Sel                 = 2.8 V
          */
-        INIT_REGULATOR_REGISTER(AB8500_VAUX1SEL, 0x08),
+        INIT_REGULATOR_REGISTER(AB8500_VAUX1SEL,               0x0f, 0x0C),
         /*
          * Vaux2Sel                 = 2.9 V
          */
-        INIT_REGULATOR_REGISTER(AB8500_VAUX2SEL, 0x0d),
+        INIT_REGULATOR_REGISTER(AB8500_VAUX2SEL,               0x0f, 0x0d),
         /*
          * Vaux3Sel                 = 2.91 V
          */
-        INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3SEL, 0x07),
+        INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3SEL,           0x07, 0x07),
         /*
          * VextSupply12LP           = disabled (no LP)
          */
-        INIT_REGULATOR_REGISTER(AB8500_REGUCTRL2SPARE, 0x00),
+        INIT_REGULATOR_REGISTER(AB8500_REGUCTRL2SPARE,         0x01, 0x00),
         /*
          * Vaux1Disch               = short discharge time
          * Vaux2Disch               = short discharge time
@@ -288,33 +361,26 @@ ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS] = {
          * VTVoutDisch              = short discharge time
          * VaudioDisch              = short discharge time
          */
-        INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH, 0x00),
+        INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH,          0xfc, 0x00),
         /*
          * VanaDisch                = short discharge time
          * VdmicPullDownEna         = pulldown disabled when Vdmic is disabled
          * VdmicDisch               = short discharge time
          */
-        INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH2, 0x00),
+        INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH2,         0x16, 0x00),
 };
 
 /* AB8500 regulators */
-struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
+static struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
         /* supplies to the display/camera */
         [AB8500_LDO_AUX1] = {
                 .constraints = {
                         .name = "V-DISPLAY",
-                        .min_uV = 2500000,
-                        .max_uV = 2900000,
+                        .min_uV = 2800000,
+                        .max_uV = 3300000,
                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
                                           REGULATOR_CHANGE_STATUS,
                         .boot_on = 1, /* display is on at boot */
-                        /*
-                         * This voltage cannot be disabled right now because
-                         * it is somehow affecting the external MMC
-                         * functionality, though that typically will use
-                         * AUX3.
-                         */
-                        .always_on = 1,
                 },
                 .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers),
                 .consumer_supplies = ab8500_vaux1_consumers,
@@ -326,7 +392,10 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                         .min_uV = 1100000,
                         .max_uV = 3300000,
                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                          REGULATOR_CHANGE_STATUS,
+                                          REGULATOR_CHANGE_STATUS |
+                                          REGULATOR_CHANGE_MODE,
+                        .valid_modes_mask = REGULATOR_MODE_NORMAL |
+                                            REGULATOR_MODE_IDLE,
                 },
                 .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux2_consumers),
                 .consumer_supplies = ab8500_vaux2_consumers,
@@ -338,7 +407,10 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                         .min_uV = 1100000,
                         .max_uV = 3300000,
                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                          REGULATOR_CHANGE_STATUS,
+                                          REGULATOR_CHANGE_STATUS |
+                                          REGULATOR_CHANGE_MODE,
+                        .valid_modes_mask = REGULATOR_MODE_NORMAL |
+                                            REGULATOR_MODE_IDLE,
                 },
                 .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux3_consumers),
                 .consumer_supplies = ab8500_vaux3_consumers,
@@ -392,18 +464,614 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
         [AB8500_LDO_INTCORE] = {
                 .constraints = {
                         .name = "V-INTCORE",
-                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                        .min_uV = 1250000,
+                        .max_uV = 1350000,
+                        .input_uV = 1800000,
+                        .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                          REGULATOR_CHANGE_STATUS |
+                                          REGULATOR_CHANGE_MODE |
+                                          REGULATOR_CHANGE_DRMS,
+                        .valid_modes_mask = REGULATOR_MODE_NORMAL |
+                                            REGULATOR_MODE_IDLE,
                 },
                 .num_consumer_supplies = ARRAY_SIZE(ab8500_vintcore_consumers),
                 .consumer_supplies = ab8500_vintcore_consumers,
         },
-        /* supply for U8500 CSI/DSI, VANA LDO */
+        /* supply for U8500 CSI-DSI, VANA LDO */
         [AB8500_LDO_ANA] = {
                 .constraints = {
-                        .name = "V-CSI/DSI",
+                        .name = "V-CSI-DSI",
                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
                 },
                 .num_consumer_supplies = ARRAY_SIZE(ab8500_vana_consumers),
                 .consumer_supplies = ab8500_vana_consumers,
         },
 };
+
+/* supply for VextSupply3 */
+static struct regulator_consumer_supply ab8500_ext_supply3_consumers[] = {
+        /* SIM supply for 3 V SIM cards */
+        REGULATOR_SUPPLY("vinvsim", "sim-detect.0"),
+};
+
+/* extended configuration for VextSupply2, only used for HREFP_V20 boards */
+static struct ab8500_ext_regulator_cfg ab8500_ext_supply2 = {
+        .hwreq = true,
+};
+
+/*
+ * AB8500 external regulators
+ */
+static struct regulator_init_data ab8500_ext_regulators[] = {
+        /* fixed Vbat supplies VSMPS1_EXT_1V8 */
+        [AB8500_EXT_SUPPLY1] = {
+                .constraints = {
+                        .name = "ab8500-ext-supply1",
+                        .min_uV = 1800000,
+                        .max_uV = 1800000,
+                        .initial_mode = REGULATOR_MODE_IDLE,
+                        .boot_on = 1,
+                        .always_on = 1,
+                },
+        },
+        /* fixed Vbat supplies VSMPS2_EXT_1V36 and VSMPS5_EXT_1V15 */
+        [AB8500_EXT_SUPPLY2] = {
+                .constraints = {
+                        .name = "ab8500-ext-supply2",
+                        .min_uV = 1360000,
+                        .max_uV = 1360000,
+                },
+        },
+        /* fixed Vbat supplies VSMPS3_EXT_3V4 and VSMPS4_EXT_3V4 */
+        [AB8500_EXT_SUPPLY3] = {
+                .constraints = {
+                        .name = "ab8500-ext-supply3",
+                        .min_uV = 3400000,
+                        .max_uV = 3400000,
+                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                        .boot_on = 1,
+                },
+                .num_consumer_supplies =
+                        ARRAY_SIZE(ab8500_ext_supply3_consumers),
+                .consumer_supplies = ab8500_ext_supply3_consumers,
+        },
+};
+
+/* ab8505 regulator register initialization */
+static struct ab8500_regulator_reg_init ab8505_reg_init[] = {
+        /*
+         * VarmRequestCtrl
+         * VsmpsCRequestCtrl
+         * VsmpsARequestCtrl
+         * VsmpsBRequestCtrl
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUREQUESTCTRL1,       0x00, 0x00),
+        /*
+         * VsafeRequestCtrl
+         * VpllRequestCtrl
+         * VanaRequestCtrl          = HP/LP depending on VxRequest
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUREQUESTCTRL2,       0x30, 0x00),
+        /*
+         * Vaux1RequestCtrl         = HP/LP depending on VxRequest
+         * Vaux2RequestCtrl         = HP/LP depending on VxRequest
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUREQUESTCTRL3,       0xf0, 0x00),
+        /*
+         * Vaux3RequestCtrl         = HP/LP depending on VxRequest
+         * SwHPReq                  = Control through SWValid disabled
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUREQUESTCTRL4,       0x07, 0x00),
+        /*
+         * VsmpsASysClkReq1HPValid
+         * VsmpsBSysClkReq1HPValid
+         * VsafeSysClkReq1HPValid
+         * VanaSysClkReq1HPValid    = disabled
+         * VpllSysClkReq1HPValid
+         * Vaux1SysClkReq1HPValid   = disabled
+         * Vaux2SysClkReq1HPValid   = disabled
+         * Vaux3SysClkReq1HPValid   = disabled
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUSYSCLKREQ1HPVALID1, 0xe8, 0x00),
+        /*
+         * VsmpsCSysClkReq1HPValid
+         * VarmSysClkReq1HPValid
+         * VbbSysClkReq1HPValid
+         * VsmpsMSysClkReq1HPValid
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUSYSCLKREQ1HPVALID2, 0x00, 0x00),
+        /*
+         * VsmpsAHwHPReq1Valid
+         * VsmpsBHwHPReq1Valid
+         * VsafeHwHPReq1Valid
+         * VanaHwHPReq1Valid        = disabled
+         * VpllHwHPReq1Valid
+         * Vaux1HwHPreq1Valid       = disabled
+         * Vaux2HwHPReq1Valid       = disabled
+         * Vaux3HwHPReqValid        = disabled
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUHWHPREQ1VALID1,     0xe8, 0x00),
+        /*
+         * VsmpsMHwHPReq1Valid
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUHWHPREQ1VALID2,     0x00, 0x00),
+        /*
+         * VsmpsAHwHPReq2Valid
+         * VsmpsBHwHPReq2Valid
+         * VsafeHwHPReq2Valid
+         * VanaHwHPReq2Valid        = disabled
+         * VpllHwHPReq2Valid
+         * Vaux1HwHPReq2Valid       = disabled
+         * Vaux2HwHPReq2Valid       = disabled
+         * Vaux3HwHPReq2Valid       = disabled
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUHWHPREQ2VALID1,     0xe8, 0x00),
+        /*
+         * VsmpsMHwHPReq2Valid
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUHWHPREQ2VALID2,     0x00, 0x00),
+        /**
+         * VsmpsCSwHPReqValid
+         * VarmSwHPReqValid
+         * VsmpsASwHPReqValid
+         * VsmpsBSwHPReqValid
+         * VsafeSwHPReqValid
+         * VanaSwHPReqValid
+         * VanaSwHPReqValid         = disabled
+         * VpllSwHPReqValid
+         * Vaux1SwHPReqValid        = disabled
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUSWHPREQVALID1,      0xa0, 0x00),
+        /*
+         * Vaux2SwHPReqValid        = disabled
+         * Vaux3SwHPReqValid        = disabled
+         * VsmpsMSwHPReqValid
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUSWHPREQVALID2,      0x03, 0x00),
+        /*
+         * SysClkReq2Valid1         = SysClkReq2 controlled
+         * SysClkReq3Valid1         = disabled
+         * SysClkReq4Valid1         = SysClkReq4 controlled
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUSYSCLKREQVALID1,    0x0e, 0x0a),
+        /*
+         * SysClkReq2Valid2         = disabled
+         * SysClkReq3Valid2         = disabled
+         * SysClkReq4Valid2         = disabled
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUSYSCLKREQVALID2,    0x0e, 0x00),
+        /*
+         * Vaux4SwHPReqValid
+         * Vaux4HwHPReq2Valid
+         * Vaux4HwHPReq1Valid
+         * Vaux4SysClkReq1HPValid
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUVAUX4REQVALID,    0x00, 0x00),
+        /*
+         * VadcEna                  = disabled
+         * VintCore12Ena            = disabled
+         * VintCore12Sel            = 1.25 V
+         * VintCore12LP             = inactive (HP)
+         * VadcLP                   = inactive (HP)
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUMISC1,              0xfe, 0x10),
+        /*
+         * VaudioEna                = disabled
+         * Vaux8Ena                 = disabled
+         * Vamic1Ena                = disabled
+         * Vamic2Ena                = disabled
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VAUDIOSUPPLY,           0x1e, 0x00),
+        /*
+         * Vamic1_dzout             = high-Z when Vamic1 is disabled
+         * Vamic2_dzout             = high-Z when Vamic2 is disabled
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUCTRL1VAMIC,         0x03, 0x00),
+        /*
+         * VsmpsARegu
+         * VsmpsASelCtrl
+         * VsmpsAAutoMode
+         * VsmpsAPWMMode
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VSMPSAREGU,    0x00, 0x00),
+        /*
+         * VsmpsBRegu
+         * VsmpsBSelCtrl
+         * VsmpsBAutoMode
+         * VsmpsBPWMMode
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VSMPSBREGU,    0x00, 0x00),
+        /*
+         * VsafeRegu
+         * VsafeSelCtrl
+         * VsafeAutoMode
+         * VsafePWMMode
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VSAFEREGU,    0x00, 0x00),
+        /*
+         * VPll                     = Hw controlled (NOTE! PRCMU bits)
+         * VanaRegu                 = force off
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VPLLVANAREGU,           0x0f, 0x02),
+        /*
+         * VextSupply1Regu          = force OFF (OTP_ExtSupply12LPnPolarity 1)
+         * VextSupply2Regu          = force OFF (OTP_ExtSupply12LPnPolarity 1)
+         * VextSupply3Regu          = force OFF (OTP_ExtSupply3LPnPolarity 0)
+         * ExtSupply2Bypass         = ExtSupply12LPn ball is 0 when Ena is 0
+         * ExtSupply3Bypass         = ExtSupply3LPn ball is 0 when Ena is 0
+         */
+        INIT_REGULATOR_REGISTER(AB8505_EXTSUPPLYREGU,          0xff, 0x30),
+        /*
+         * Vaux1Regu                = force HP
+         * Vaux2Regu                = force off
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VAUX12REGU,             0x0f, 0x01),
+        /*
+         * Vaux3Regu                = force off
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VRF1VAUX3REGU,          0x03, 0x00),
+        /*
+         * VsmpsASel1
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VSMPSASEL1,    0x00, 0x00),
+        /*
+         * VsmpsASel2
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VSMPSASEL2,    0x00, 0x00),
+        /*
+         * VsmpsASel3
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VSMPSASEL3,    0x00, 0x00),
+        /*
+         * VsmpsBSel1
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VSMPSBSEL1,    0x00, 0x00),
+        /*
+         * VsmpsBSel2
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VSMPSBSEL2,    0x00, 0x00),
+        /*
+         * VsmpsBSel3
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VSMPSBSEL3,    0x00, 0x00),
+        /*
+         * VsafeSel1
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VSAFESEL1,    0x00, 0x00),
+        /*
+         * VsafeSel2
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VSAFESEL2,    0x00, 0x00),
+        /*
+         * VsafeSel3
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VSAFESEL3,    0x00, 0x00),
+        /*
+         * Vaux1Sel                 = 2.8 V
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VAUX1SEL,               0x0f, 0x0C),
+        /*
+         * Vaux2Sel                 = 2.9 V
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VAUX2SEL,               0x0f, 0x0d),
+        /*
+         * Vaux3Sel                 = 2.91 V
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VRF1VAUX3SEL,           0x07, 0x07),
+        /*
+         * Vaux4RequestCtrl
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VAUX4REQCTRL,    0x00, 0x00),
+        /*
+         * Vaux4Regu
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VAUX4REGU,    0x00, 0x00),
+        /*
+         * Vaux4Sel
+         */
+        INIT_REGULATOR_REGISTER(AB8505_VAUX4SEL,    0x00, 0x00),
+        /*
+         * Vaux1Disch               = short discharge time
+         * Vaux2Disch               = short discharge time
+         * Vaux3Disch               = short discharge time
+         * Vintcore12Disch          = short discharge time
+         * VTVoutDisch              = short discharge time
+         * VaudioDisch              = short discharge time
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUCTRLDISCH,          0xfc, 0x00),
+        /*
+         * VanaDisch                = short discharge time
+         * Vaux8PullDownEna         = pulldown disabled when Vaux8 is disabled
+         * Vaux8Disch               = short discharge time
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUCTRLDISCH2,         0x16, 0x00),
+        /*
+         * Vaux4Disch               = short discharge time
+         */
+        INIT_REGULATOR_REGISTER(AB8505_REGUCTRLDISCH3,         0x01, 0x00),
+        /*
+         * Vaux5Sel
+         * Vaux5LP
+         * Vaux5Ena
+         * Vaux5Disch
+         * Vaux5DisSfst
+         * Vaux5DisPulld
+         */
+        INIT_REGULATOR_REGISTER(AB8505_CTRLVAUX5,              0x00, 0x00),
+        /*
+         * Vaux6Sel
+         * Vaux6LP
+         * Vaux6Ena
+         * Vaux6DisPulld
+         */
+        INIT_REGULATOR_REGISTER(AB8505_CTRLVAUX6,              0x00, 0x00),
+};
+
+struct regulator_init_data ab8505_regulators[AB8505_NUM_REGULATORS] = {
+        /* supplies to the display/camera */
+        [AB8505_LDO_AUX1] = {
+                .constraints = {
+                        .name = "V-DISPLAY",
+                        .min_uV = 2800000,
+                        .max_uV = 3300000,
+                        .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                          REGULATOR_CHANGE_STATUS,
+                        .boot_on = 1, /* display is on at boot */
+                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers),
+                .consumer_supplies = ab8500_vaux1_consumers,
+        },
+        /* supplies to the on-board eMMC */
+        [AB8505_LDO_AUX2] = {
+                .constraints = {
+                        .name = "V-eMMC1",
+                        .min_uV = 1100000,
+                        .max_uV = 3300000,
+                        .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                          REGULATOR_CHANGE_STATUS |
+                                          REGULATOR_CHANGE_MODE,
+                        .valid_modes_mask = REGULATOR_MODE_NORMAL |
+                                            REGULATOR_MODE_IDLE,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux2_consumers),
+                .consumer_supplies = ab8500_vaux2_consumers,
+        },
+        /* supply for VAUX3, supplies to SDcard slots */
+        [AB8505_LDO_AUX3] = {
+                .constraints = {
+                        .name = "V-MMC-SD",
+                        .min_uV = 1100000,
+                        .max_uV = 3300000,
+                        .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                          REGULATOR_CHANGE_STATUS |
+                                          REGULATOR_CHANGE_MODE,
+                        .valid_modes_mask = REGULATOR_MODE_NORMAL |
+                                            REGULATOR_MODE_IDLE,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux3_consumers),
+                .consumer_supplies = ab8500_vaux3_consumers,
+        },
+        /* supply for VAUX4, supplies to NFC and standalone secure element */
+        [AB8505_LDO_AUX4] = {
+                .constraints = {
+                        .name = "V-NFC-SE",
+                        .min_uV = 1100000,
+                        .max_uV = 3300000,
+                        .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                          REGULATOR_CHANGE_STATUS |
+                                          REGULATOR_CHANGE_MODE,
+                        .valid_modes_mask = REGULATOR_MODE_NORMAL |
+                                            REGULATOR_MODE_IDLE,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8505_vaux4_consumers),
+                .consumer_supplies = ab8505_vaux4_consumers,
+        },
+        /* supply for VAUX5, supplies to TBD */
+        [AB8505_LDO_AUX5] = {
+                .constraints = {
+                        .name = "V-AUX5",
+                        .min_uV = 1050000,
+                        .max_uV = 2790000,
+                        .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                          REGULATOR_CHANGE_STATUS |
+                                          REGULATOR_CHANGE_MODE,
+                        .valid_modes_mask = REGULATOR_MODE_NORMAL |
+                                            REGULATOR_MODE_IDLE,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8505_vaux5_consumers),
+                .consumer_supplies = ab8505_vaux5_consumers,
+        },
+        /* supply for VAUX6, supplies to TBD */
+        [AB8505_LDO_AUX6] = {
+                .constraints = {
+                        .name = "V-AUX6",
+                        .min_uV = 1050000,
+                        .max_uV = 2790000,
+                        .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                          REGULATOR_CHANGE_STATUS |
+                                          REGULATOR_CHANGE_MODE,
+                        .valid_modes_mask = REGULATOR_MODE_NORMAL |
+                                            REGULATOR_MODE_IDLE,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8505_vaux6_consumers),
+                .consumer_supplies = ab8505_vaux6_consumers,
+        },
+        /* supply for gpadc, ADC LDO */
+        [AB8505_LDO_ADC] = {
+                .constraints = {
+                        .name = "V-ADC",
+                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8505_vadc_consumers),
+                .consumer_supplies = ab8505_vadc_consumers,
+        },
+        /* supply for ab8500-vaudio, VAUDIO LDO */
+        [AB8505_LDO_AUDIO] = {
+                .constraints = {
+                        .name = "V-AUD",
+                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vaud_consumers),
+                .consumer_supplies = ab8500_vaud_consumers,
+        },
+        /* supply for v-anamic1 VAMic1-LDO */
+        [AB8505_LDO_ANAMIC1] = {
+                .constraints = {
+                        .name = "V-AMIC1",
+                        .valid_ops_mask = REGULATOR_CHANGE_STATUS |
+                                          REGULATOR_CHANGE_MODE,
+                        .valid_modes_mask = REGULATOR_MODE_NORMAL |
+                                            REGULATOR_MODE_IDLE,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vamic1_consumers),
+                .consumer_supplies = ab8500_vamic1_consumers,
+        },
+        /* supply for v-amic2, VAMIC2 LDO, reuse constants for AMIC1 */
+        [AB8505_LDO_ANAMIC2] = {
+                .constraints = {
+                        .name = "V-AMIC2",
+                        .valid_ops_mask = REGULATOR_CHANGE_STATUS |
+                                          REGULATOR_CHANGE_MODE,
+                        .valid_modes_mask = REGULATOR_MODE_NORMAL |
+                                            REGULATOR_MODE_IDLE,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vamic2_consumers),
+                .consumer_supplies = ab8500_vamic2_consumers,
+        },
+        /* supply for v-aux8, VAUX8 LDO */
+        [AB8505_LDO_AUX8] = {
+                .constraints = {
+                        .name = "V-AUX8",
+                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8505_vaux8_consumers),
+                .consumer_supplies = ab8505_vaux8_consumers,
+        },
+        /* supply for v-intcore12, VINTCORE12 LDO */
+        [AB8505_LDO_INTCORE] = {
+                .constraints = {
+                        .name = "V-INTCORE",
+                        .min_uV = 1250000,
+                        .max_uV = 1350000,
+                        .input_uV = 1800000,
+                        .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                          REGULATOR_CHANGE_STATUS |
+                                          REGULATOR_CHANGE_MODE |
+                                          REGULATOR_CHANGE_DRMS,
+                        .valid_modes_mask = REGULATOR_MODE_NORMAL |
+                                            REGULATOR_MODE_IDLE,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vintcore_consumers),
+                .consumer_supplies = ab8500_vintcore_consumers,
+        },
+        /* supply for LDO USB */
+        [AB8505_LDO_USB] = {
+                .constraints = {
+                        .name = "V-USB",
+                        .valid_ops_mask = REGULATOR_CHANGE_STATUS |
+                                          REGULATOR_CHANGE_MODE,
+                        .valid_modes_mask = REGULATOR_MODE_NORMAL |
+                                            REGULATOR_MODE_IDLE,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8505_usb_consumers),
+                .consumer_supplies = ab8505_usb_consumers,
+        },
+        /* supply for U8500 CSI-DSI, VANA LDO */
+        [AB8505_LDO_ANA] = {
+                .constraints = {
+                        .name = "V-CSI-DSI",
+                        .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                },
+                .num_consumer_supplies = ARRAY_SIZE(ab8500_vana_consumers),
+                .consumer_supplies = ab8500_vana_consumers,
+        },
+};
+
+struct ab8500_regulator_platform_data ab8500_regulator_plat_data = {
+        .reg_init               = ab8500_reg_init,
+        .num_reg_init           = ARRAY_SIZE(ab8500_reg_init),
+        .regulator              = ab8500_regulators,
+        .num_regulator          = ARRAY_SIZE(ab8500_regulators),
+        .ext_regulator          = ab8500_ext_regulators,
+        .num_ext_regulator      = ARRAY_SIZE(ab8500_ext_regulators),
+};
+
+/* Use the AB8500 init settings for AB8505 as they are the same right now */
+struct ab8500_regulator_platform_data ab8505_regulator_plat_data = {
+        .reg_init               = ab8505_reg_init,
+        .num_reg_init           = ARRAY_SIZE(ab8505_reg_init),
+        .regulator              = ab8505_regulators,
+        .num_regulator          = ARRAY_SIZE(ab8505_regulators),
+};
+
+static void ab8500_modify_reg_init(int id, u8 mask, u8 value)
+{
+        int i;
+
+        if (cpu_is_u8520()) {
+                for (i = ARRAY_SIZE(ab8505_reg_init) - 1; i >= 0; i--) {
+                        if (ab8505_reg_init[i].id == id) {
+                                u8 initval = ab8505_reg_init[i].value;
+                                initval = (initval & ~mask) | (value & mask);
+                                ab8505_reg_init[i].value = initval;
+
+                                BUG_ON(mask & ~ab8505_reg_init[i].mask);
+                                return;
+                        }
+                }
+        } else {
+                for (i = ARRAY_SIZE(ab8500_reg_init) - 1; i >= 0; i--) {
+                        if (ab8500_reg_init[i].id == id) {
+                                u8 initval = ab8500_reg_init[i].value;
+                                initval = (initval & ~mask) | (value & mask);
+                                ab8500_reg_init[i].value = initval;
+
+                                BUG_ON(mask & ~ab8500_reg_init[i].mask);
+                                return;
+                        }
+                }
+        }
+
+        BUG_ON(1);
+}
+
+void mop500_regulator_init(void)
+{
+        struct regulator_init_data *regulator;
+
+        /*
+         * Temporarily turn on Vaux2 on 8520 machine
+         */
+        if (cpu_is_u8520()) {
+                /* Vaux2 initialized to be on */
+                ab8500_modify_reg_init(AB8505_VAUX12REGU, 0x0f, 0x05);
+        }
+
+        /*
+         * Handle AB8500_EXT_SUPPLY2 on HREFP_V20_V50 boards (do it for
+         * all HREFP_V20 boards)
+         */
+        if (cpu_is_u8500v20()) {
+                /* VextSupply2RequestCtrl =  HP/OFF depending on VxRequest */
+                ab8500_modify_reg_init(AB8500_REGUREQUESTCTRL3, 0x01, 0x01);
+
+                /* VextSupply2SysClkReq1HPValid = SysClkReq1 controlled */
+                ab8500_modify_reg_init(AB8500_REGUSYSCLKREQ1HPVALID2,
+                        0x20, 0x20);
+
+                /* VextSupply2 = force HP at initialization */
+                ab8500_modify_reg_init(AB8500_EXTSUPPLYREGU, 0x0c, 0x04);
+
+                /* enable VextSupply2 during platform active */
+                regulator = &ab8500_ext_regulators[AB8500_EXT_SUPPLY2];
+                regulator->constraints.always_on = 1;
+
+                /* disable VextSupply2 in suspend */
+                regulator = &ab8500_ext_regulators[AB8500_EXT_SUPPLY2];
+                regulator->constraints.state_mem.disabled = 1;
+                regulator->constraints.state_standby.disabled = 1;
+
+                /* enable VextSupply2 HW control (used in suspend) */
+                regulator->driver_data = (void *)&ab8500_ext_supply2;
+        }
+}
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h
index 78a0642a2206..039f5132c370 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.h
+++ b/arch/arm/mach-ux500/board-mop500-regulators.h
@@ -14,10 +14,12 @@
 #include <linux/regulator/machine.h>
 #include <linux/regulator/ab8500.h>
 
-extern struct ab8500_regulator_reg_init
-ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS];
-extern struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS];
+extern struct ab8500_regulator_platform_data ab8500_regulator_plat_data;
+extern struct ab8500_regulator_platform_data ab8505_regulator_plat_data;
 extern struct regulator_init_data tps61052_regulator;
 extern struct regulator_init_data gpio_en_3v3_regulator;
+extern struct regulator_init_data sdi0_reg_init_data;
+
+void mop500_regulator_init(void);
 
 #endif
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 7f2cb6c5e2c1..0ef38775a0c1 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -14,9 +14,9 @@
 #include <linux/platform_data/dma-ste-dma40.h>
 
 #include <asm/mach-types.h>
-#include <mach/devices.h>
-#include <mach/hardware.h>
+#include "devices.h"
 
+#include "db8500-regs.h"
 #include "devices-db8500.h"
 #include "board-mop500.h"
 #include "ste-dma40-db8500.h"
@@ -31,35 +31,6 @@
  * SDI 0 (MicroSD slot)
  */
 
-/* GPIO pins used by the sdi0 level shifter */
-static int sdi0_en = -1;
-static int sdi0_vsel = -1;
-
-static int mop500_sdi0_ios_handler(struct device *dev, struct mmc_ios *ios)
-{
-        switch (ios->power_mode) {
-        case MMC_POWER_UP:
-        case MMC_POWER_ON:
-                /*
-                 * Level shifter voltage should depend on vdd to when deciding
-                 * on either 1.8V or 2.9V. Once the decision has been made the
-                 * level shifter must be disabled and re-enabled with a changed
-                 * select signal in order to switch the voltage. Since there is
-                 * no framework support yet for indicating 1.8V in vdd, use the
-                 * default 2.9V.
-                 */
-                gpio_direction_output(sdi0_vsel, 0);
-                gpio_direction_output(sdi0_en, 1);
-                break;
-        case MMC_POWER_OFF:
-                gpio_direction_output(sdi0_vsel, 0);
-                gpio_direction_output(sdi0_en, 0);
-                break;
-        }
-
-        return 0;
-}
-
 #ifdef CONFIG_STE_DMA40
 struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
         .mode = STEDMA40_MODE_LOGICAL,
@@ -100,22 +71,6 @@ struct mmci_platform_data mop500_sdi0_data = {
 
 static void sdi0_configure(struct device *parent)
 {
-        int ret;
-
-        ret = gpio_request(sdi0_en, "level shifter enable");
-        if (!ret)
-                ret = gpio_request(sdi0_vsel,
-                                   "level shifter 1v8-3v select");
-
-        if (ret) {
-                pr_warning("unable to config sdi0 gpios for level shifter.\n");
-                return;
-        }
-
-        /* Select the default 2.9V and enable level shifter */
-        gpio_direction_output(sdi0_vsel, 0);
-        gpio_direction_output(sdi0_en, 1);
-
         /* Add the device, force v2 to subrevision 1 */
         db8500_add_sdi0(parent, &mop500_sdi0_data, U8500_SDI_V2_PERIPHID);
 }
@@ -123,8 +78,6 @@ static void sdi0_configure(struct device *parent)
 void mop500_sdi_tc35892_init(struct device *parent)
 {
         mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD;
-        sdi0_en = GPIO_SDMMC_EN;
-        sdi0_vsel = GPIO_SDMMC_1V8_3V_SEL;
         sdi0_configure(parent);
 }
 
@@ -263,8 +216,6 @@ void __init snowball_sdi_init(struct device *parent)
         /* External Micro SD slot */
         mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
         mop500_sdi0_data.cd_invert = true;
-        sdi0_en = SNOWBALL_SDMMC_EN_GPIO;
-        sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO;
         sdi0_configure(parent);
 }
 
@@ -276,8 +227,6 @@ void __init hrefv60_sdi_init(struct device *parent)
         db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
         /* External Micro SD slot */
         mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
-        sdi0_en = HREFV60_SDMMC_EN_GPIO;
-        sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
         sdi0_configure(parent);
         /* WLAN SDIO channel */
         db8500_add_sdi1(parent, &mop500_sdi1_data, U8500_SDI_V2_PERIPHID);
diff --git a/arch/arm/mach-ux500/board-mop500-u8500uib.c b/arch/arm/mach-ux500/board-mop500-u8500uib.c
index ead91c968ff4..d397c19570af 100644
--- a/arch/arm/mach-ux500/board-mop500-u8500uib.c
+++ b/arch/arm/mach-ux500/board-mop500-u8500uib.c
@@ -12,12 +12,15 @@
 #include <linux/mfd/tc3589x.h>
 #include <linux/input/matrix_keypad.h>
 
-#include <mach/irqs.h>
+#include "irqs.h"
 
 #include "board-mop500.h"
 
-/* Dummy data that can be overridden by staging driver */
-struct i2c_board_info __initdata __weak mop500_i2c3_devices_u8500[] = {
+static struct i2c_board_info __initdata mop500_i2c3_devices_u8500[] = {
+        {
+                I2C_BOARD_INFO("synaptics_rmi4_i2c", 0x4B),
+                .irq = NOMADIK_GPIO_TO_IRQ(84),
+        },
 };
 
 /*
diff --git a/arch/arm/mach-ux500/board-mop500-uib.c b/arch/arm/mach-ux500/board-mop500-uib.c
index 7037d3687e9f..bdaa422da028 100644
--- a/arch/arm/mach-ux500/board-mop500-uib.c
+++ b/arch/arm/mach-ux500/board-mop500-uib.c
@@ -11,7 +11,6 @@
 #include <linux/init.h>
 #include <linux/i2c.h>
 
-#include <mach/hardware.h>
 #include "board-mop500.h"
 #include "id.h"
 
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 87d2d7b38ce9..a15dd6b63a8f 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -25,6 +25,8 @@
 #include <linux/mfd/abx500/ab8500.h>
 #include <linux/regulator/ab8500.h>
 #include <linux/regulator/fixed.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/gpio-regulator.h>
 #include <linux/mfd/tc3589x.h>
 #include <linux/mfd/tps6105x.h>
 #include <linux/mfd/abx500/ab8500-gpio.h>
@@ -42,13 +44,13 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/hardware.h>
-#include <mach/setup.h>
-#include <mach/devices.h>
-#include <mach/irqs.h>
+#include "setup.h"
+#include "devices.h"
+#include "irqs.h"
 #include <linux/platform_data/crypto-ux500.h>
 
 #include "ste-dma40-db8500.h"
+#include "db8500-regs.h"
 #include "devices-db8500.h"
 #include "board-mop500.h"
 #include "board-mop500-regulators.h"
@@ -90,6 +92,37 @@ static struct platform_device snowball_gpio_en_3v3_regulator_dev = {
        },
 };
 
+/* Dynamically populated. */
+static struct gpio sdi0_reg_gpios[] = {
+        { 0, GPIOF_OUT_INIT_LOW, "mmci_vsel" },
+};
+
+static struct gpio_regulator_state sdi0_reg_states[] = {
+        { .value = 2900000, .gpios = (0 << 0) },
+        { .value = 1800000, .gpios = (1 << 0) },
+};
+
+static struct gpio_regulator_config sdi0_reg_info = {
+        .supply_name            = "ext-mmc-level-shifter",
+        .gpios                  = sdi0_reg_gpios,
+        .nr_gpios               = ARRAY_SIZE(sdi0_reg_gpios),
+        .states                 = sdi0_reg_states,
+        .nr_states              = ARRAY_SIZE(sdi0_reg_states),
+        .type                   = REGULATOR_VOLTAGE,
+        .enable_high            = 1,
+        .enabled_at_boot        = 0,
+        .init_data              = &sdi0_reg_init_data,
+        .startup_delay          = 100,
+};
+
+static struct platform_device sdi0_regulator = {
+        .name = "gpio-regulator",
+        .id   = -1,
+        .dev  = {
+                .platform_data = &sdi0_reg_info,
+        },
+};
+
 static struct abx500_gpio_platform_data ab8500_gpio_pdata = {
         .gpio_base              = MOP500_AB8500_PIN_GPIO(1),
 };
@@ -199,71 +232,11 @@ static struct platform_device snowball_sbnet_dev = {
 
 struct ab8500_platform_data ab8500_platdata = {
         .irq_base       = MOP500_AB8500_IRQ_BASE,
-        .regulator_reg_init = ab8500_regulator_reg_init,
-        .num_regulator_reg_init = ARRAY_SIZE(ab8500_regulator_reg_init),
-        .regulator      = ab8500_regulators,
-        .num_regulator  = ARRAY_SIZE(ab8500_regulators),
+        .regulator      = &ab8500_regulator_plat_data,
         .gpio           = &ab8500_gpio_pdata,
         .codec          = &ab8500_codec_pdata,
 };
 
-/*
- * Thermal Sensor
- */
-
-static struct resource db8500_thsens_resources[] = {
-        {
-                .name = "IRQ_HOTMON_LOW",
-                .start  = IRQ_PRCMU_HOTMON_LOW,
-                .end    = IRQ_PRCMU_HOTMON_LOW,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .name = "IRQ_HOTMON_HIGH",
-                .start  = IRQ_PRCMU_HOTMON_HIGH,
-                .end    = IRQ_PRCMU_HOTMON_HIGH,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct db8500_thsens_platform_data db8500_thsens_data = {
-        .trip_points[0] = {
-                .temp = 70000,
-                .type = THERMAL_TRIP_ACTIVE,
-                .cdev_name = {
-                        [0] = "thermal-cpufreq-0",
-                },
-        },
-        .trip_points[1] = {
-                .temp = 75000,
-                .type = THERMAL_TRIP_ACTIVE,
-                .cdev_name = {
-                        [0] = "thermal-cpufreq-0",
-                },
-        },
-        .trip_points[2] = {
-                .temp = 80000,
-                .type = THERMAL_TRIP_ACTIVE,
-                .cdev_name = {
-                        [0] = "thermal-cpufreq-0",
-                },
-        },
-        .trip_points[3] = {
-                .temp = 85000,
-                .type = THERMAL_TRIP_CRITICAL,
-        },
-        .num_trips = 4,
-};
-
-static struct platform_device u8500_thsens_device = {
-        .name           = "db8500-thermal",
-        .resource       = db8500_thsens_resources,
-        .num_resources  = ARRAY_SIZE(db8500_thsens_resources),
-        .dev    = {
-                .platform_data  = &db8500_thsens_data,
-        },
-};
-
 static struct platform_device u8500_cpufreq_cooling_device = {
         .name           = "db8500-cpufreq-cooling",
 };
@@ -491,6 +464,7 @@ static struct hash_platform_data u8500_hash1_platform_data = {
 /* add any platform devices here - TODO */
 static struct platform_device *mop500_platform_devs[] __initdata = {
         &mop500_gpio_keys_device,
+        &sdi0_regulator,
 };
 
 #ifdef CONFIG_STE_DMA40
@@ -632,8 +606,8 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
         &snowball_key_dev,
         &snowball_sbnet_dev,
         &snowball_gpio_en_3v3_regulator_dev,
-        &u8500_thsens_device,
         &u8500_cpufreq_cooling_device,
+        &sdi0_regulator,
 };
 
 static void __init mop500_init_machine(void)
@@ -645,6 +619,9 @@ static void __init mop500_init_machine(void)
         platform_device_register(&db8500_prcmu_device);
         mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
 
+        sdi0_reg_info.enable_gpio = GPIO_SDMMC_EN;
+        sdi0_reg_info.gpios[0].gpio = GPIO_SDMMC_1V8_3V_SEL;
+
         mop500_pinmaps_init();
         parent = u8500_init_devices(&ab8500_platdata);
 
@@ -678,6 +655,10 @@ static void __init snowball_init_machine(void)
         int i;
 
         platform_device_register(&db8500_prcmu_device);
+
+        sdi0_reg_info.enable_gpio = SNOWBALL_SDMMC_EN_GPIO;
+        sdi0_reg_info.gpios[0].gpio = SNOWBALL_SDMMC_1V8_3V_GPIO;
+
         snowball_pinmaps_init();
         parent = u8500_init_devices(&ab8500_platdata);
 
@@ -713,6 +694,9 @@ static void __init hrefv60_init_machine(void)
          */
         mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
 
+        sdi0_reg_info.enable_gpio = HREFV60_SDMMC_EN_GPIO;
+        sdi0_reg_info.gpios[0].gpio = HREFV60_SDMMC_1V8_3V_GPIO;
+
         hrefv60_pinmaps_init();
         parent = u8500_init_devices(&ab8500_platdata);
 
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index d38951be70df..49514b825034 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -8,8 +8,8 @@
 #define __BOARD_MOP500_H
 
 /* For NOMADIK_NR_GPIO */
-#include <mach/irqs.h>
-#include <mach/msp.h>
+#include "irqs.h"
+#include <linux/platform_data/asoc-ux500-msp.h>
 #include <linux/amba/mmci.h>
 
 /* Snowball specific GPIO assignments, this board has no GPIO expander */
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index 1c1609da76ce..f58615b5c601 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -9,8 +9,8 @@
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <mach/hardware.h>
 
+#include "db8500-regs.h"
 #include "id.h"
 
 static void __iomem *l2x0_base;
@@ -47,8 +47,8 @@ static int __init ux500_l2x0_init(void)
         /* Unlock before init */
         ux500_l2x0_unlock();
 
-        /* DB9540's L2 has 128KB way size */
-        if (cpu_is_u9540())
+        /* DBx540's L2 has 128KB way size */
+        if (cpu_is_ux540_family())
                 /* 128KB way size */
                 aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
         else
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index f1a581844372..995928ba22fd 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -28,15 +28,13 @@
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
 
-#include <mach/hardware.h>
-#include <mach/setup.h>
-#include <mach/devices.h>
-#include <mach/db8500-regs.h>
-#include <mach/irqs.h>
+#include "setup.h"
+#include "devices.h"
+#include "irqs.h"
 
 #include "devices-db8500.h"
 #include "ste-dma40-db8500.h"
-
+#include "db8500-regs.h"
 #include "board-mop500.h"
 #include "id.h"
 
@@ -94,8 +92,6 @@ void __init u8500_map_io(void)
                 iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc));
         else
                 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
-
-        _PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
 }
 
 static struct resource db8500_pmu_resources[] = {
@@ -282,6 +278,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
         OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
                         &db8500_prcmu_pdata),
+        OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x", NULL),
         /* Requires device name bindings. */
         OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
                 "pinctrl-db8500", NULL),
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 537870d3fea8..b6145ea51641 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -8,7 +8,7 @@
 
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <linux/mfd/db8500-prcmu.h>
+#include <linux/mfd/dbx500-prcmu.h>
 #include <linux/clksrc-dbx500-prcmu.h>
 #include <linux/sys_soc.h>
 #include <linux/err.h>
@@ -20,18 +20,17 @@
 #include <linux/irqchip.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-ux500.h>
+#include <linux/platform_data/arm-ux500-pm.h>
 
 #include <asm/mach/map.h>
 
-#include <mach/hardware.h>
-#include <mach/setup.h>
-#include <mach/devices.h>
+#include "setup.h"
+#include "devices.h"
 
 #include "board-mop500.h"
+#include "db8500-regs.h"
 #include "id.h"
 
-void __iomem *_PRCMU_BASE;
-
 /*
  * FIXME: Should we set up the GPIO domain here?
  *
@@ -68,13 +67,23 @@ void __init ux500_init_irq(void)
          * Init clocks here so that they are available for system timer
          * initialization.
          */
-        if (cpu_is_u8500_family() || cpu_is_u9540())
-                db8500_prcmu_early_init();
-
-        if (cpu_is_u8500_family() || cpu_is_u9540())
-                u8500_clk_init();
-        else if (cpu_is_u8540())
+        if (cpu_is_u8500_family()) {
+                prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
+                ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
+                u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
+                               U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
+                               U8500_CLKRST6_BASE);
+        } else if (cpu_is_u9540()) {
+                prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
+                ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
+                u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
+                               U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
+                               U8500_CLKRST6_BASE);
+        } else if (cpu_is_u8540()) {
+                prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
+                ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
                 u8540_clk_init();
+        }
 }
 
 void __init ux500_init_late(void)
@@ -140,14 +149,13 @@ struct device * __init ux500_soc_device_init(const char *soc_id)
         soc_info_populate(soc_dev_attr, soc_id);
 
         soc_dev = soc_device_register(soc_dev_attr);
-        if (IS_ERR_OR_NULL(soc_dev)) {
+        if (IS_ERR(soc_dev)) {
                 kfree(soc_dev_attr);
                 return NULL;
         }
 
         parent = soc_device_to_device(soc_dev);
-        if (!IS_ERR_OR_NULL(parent))
-                device_create_file(parent, &ux500_soc_attr);
+        device_create_file(parent, &ux500_soc_attr);
 
         return parent;
 }
diff --git a/arch/arm/mach-ux500/cpuidle.c b/arch/arm/mach-ux500/cpuidle.c
index ce9149302cc3..317a2be129fb 100644
--- a/arch/arm/mach-ux500/cpuidle.c
+++ b/arch/arm/mach-ux500/cpuidle.c
@@ -11,18 +11,19 @@
 
 #include <linux/module.h>
 #include <linux/cpuidle.h>
-#include <linux/clockchips.h>
 #include <linux/spinlock.h>
 #include <linux/atomic.h>
 #include <linux/smp.h>
 #include <linux/mfd/dbx500-prcmu.h>
+#include <linux/platform_data/arm-ux500-pm.h>
 
 #include <asm/cpuidle.h>
 #include <asm/proc-fns.h>
 
+#include "db8500-regs.h"
+
 static atomic_t master = ATOMIC_INIT(0);
 static DEFINE_SPINLOCK(master_lock);
-static DEFINE_PER_CPU(struct cpuidle_device, ux500_cpuidle_device);
 
 static inline int ux500_enter_idle(struct cpuidle_device *dev,
                                    struct cpuidle_driver *drv, int index)
@@ -30,8 +31,6 @@ static inline int ux500_enter_idle(struct cpuidle_device *dev,
         int this_cpu = smp_processor_id();
         bool recouple = false;
 
-        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &this_cpu);
-
         if (atomic_inc_return(&master) == num_online_cpus()) {
 
                 /* With this lock, we prevent the other cpu to exit and enter
@@ -91,22 +90,20 @@ out:
                 spin_unlock(&master_lock);
         }
 
-        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &this_cpu);
-
         return index;
 }
 
 static struct cpuidle_driver ux500_idle_driver = {
         .name = "ux500_idle",
         .owner = THIS_MODULE,
-        .en_core_tk_irqen = 1,
         .states = {
                 ARM_CPUIDLE_WFI_STATE,
                 {
                         .enter            = ux500_enter_idle,
                         .exit_latency     = 70,
                         .target_residency = 260,
-                        .flags            = CPUIDLE_FLAG_TIME_VALID,
+                        .flags            = CPUIDLE_FLAG_TIME_VALID |
+                                            CPUIDLE_FLAG_TIMER_STOP,
                         .name             = "ApIdle",
                         .desc             = "ARM Retention",
                 },
@@ -115,59 +112,13 @@ static struct cpuidle_driver ux500_idle_driver = {
         .state_count = 2,
 };
 
-/*
- * For each cpu, setup the broadcast timer because we will
- * need to migrate the timers for the states >= ApIdle.
- */
-static void ux500_setup_broadcast_timer(void *arg)
-{
-        int cpu = smp_processor_id();
-        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
-}
-
 int __init ux500_idle_init(void)
 {
-        int ret, cpu;
-        struct cpuidle_device *device;
-
-        /* Configure wake up reasons */
+        /* Configure wake up reasons */
         prcmu_enable_wakeups(PRCMU_WAKEUP(ARM) | PRCMU_WAKEUP(RTC) |
                              PRCMU_WAKEUP(ABB));
 
-        /*
-         * Configure the timer broadcast for each cpu, that must
-         * be done from the cpu context, so we use a smp cross
-         * call with 'on_each_cpu'.
-         */
-        on_each_cpu(ux500_setup_broadcast_timer, NULL, 1);
-
-        ret = cpuidle_register_driver(&ux500_idle_driver);
-        if (ret) {
-                printk(KERN_ERR "failed to register ux500 idle driver\n");
-                return ret;
-        }
-
-        for_each_online_cpu(cpu) {
-                device = &per_cpu(ux500_cpuidle_device, cpu);
-                device->cpu = cpu;
-                ret = cpuidle_register_device(device);
-                if (ret) {
-                        printk(KERN_ERR "Failed to register cpuidle "
-                               "device for cpu%d\n", cpu);
-                        goto out_unregister;
-                }
-        }
-out:
-        return ret;
-
-out_unregister:
-        for_each_online_cpu(cpu) {
-                device = &per_cpu(ux500_cpuidle_device, cpu);
-                cpuidle_unregister_device(device);
-        }
-
-        cpuidle_unregister_driver(&ux500_idle_driver);
-        goto out;
+        return cpuidle_register(&ux500_idle_driver, NULL);
 }
 
 device_initcall(ux500_idle_init);
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/db8500-regs.h
index 1530d493879d..b2d7a0b98629 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/db8500-regs.h
@@ -170,4 +170,32 @@
 /* SoC identification number information */
 #define U8500_BB_UID_BASE      (U8500_BACKUPRAM1_BASE + 0xFC0)
 
+/* Offsets to specific addresses in some IP blocks for DMA */
+#define MSP_TX_RX_REG_OFFSET    0
+#define CRYP1_RX_REG_OFFSET     0x10
+#define CRYP1_TX_REG_OFFSET     0x8
+#define HASH1_TX_REG_OFFSET     0x4
+
+/*
+ * Macros to get at IO space when running virtually
+ * We dont map all the peripherals, let ioremap do
+ * this for us. We map only very basic peripherals here.
+ */
+#define U8500_IO_VIRTUAL        0xf0000000
+#define U8500_IO_PHYSICAL       0xa0000000
+/* This is where we map in the ROM to check ASIC IDs */
+#define UX500_VIRT_ROM          0xf0000000
+
+/* This macro is used in assembly, so no cast */
+#define IO_ADDRESS(x)           \
+        (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
+
+/* typesafe io address */
+#define __io_address(n)         IOMEM(IO_ADDRESS(n))
+
+/* Used by some plat-nomadik code */
+#define io_p2v(n)               __io_address(n)
+
+#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
+
 #endif
diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c
index 16b5f71e6974..f71b3d7bd4fb 100644
--- a/arch/arm/mach-ux500/devices-common.c
+++ b/arch/arm/mach-ux500/devices-common.c
@@ -13,8 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/platform_data/pinctrl-nomadik.h>
 
-#include <mach/hardware.h>
-#include <mach/irqs.h>
+#include "irqs.h"
 
 #include "devices-common.h"
 
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index f3d9419f75d3..1cf94ce0feec 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -15,10 +15,10 @@
 #include <linux/platform_data/dma-ste-dma40.h>
 #include <linux/mfd/dbx500-prcmu.h>
 
-#include <mach/hardware.h>
-#include <mach/setup.h>
-#include <mach/irqs.h>
+#include "setup.h"
+#include "irqs.h"
 
+#include "db8500-regs.h"
 #include "devices-db8500.h"
 #include "ste-dma40-db8500.h"
 
@@ -199,6 +199,8 @@ struct platform_device u8500_ske_keypad_device = {
 
 struct prcmu_pdata db8500_prcmu_pdata = {
         .ab_platdata    = &ab8500_platdata,
+        .ab_irq         = IRQ_DB8500_AB8500,
+        .irq_base       = IRQ_PRCMU_BASE,
         .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET,
         .legacy_offset  = DB8500_PRCMU_LEGACY_OFFSET,
 };
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index dbcb35c48f06..321998320f98 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -9,7 +9,8 @@
 #define __DEVICES_DB8500_H
 
 #include <linux/platform_data/usb-musb-ux500.h>
-#include <mach/irqs.h>
+#include "irqs.h"
+#include "db8500-regs.h"
 #include "devices-common.h"
 
 struct ske_keypad_platform_data;
diff --git a/arch/arm/mach-ux500/devices.c b/arch/arm/mach-ux500/devices.c
index ea0a2f92ca70..0f9e52b95935 100644
--- a/arch/arm/mach-ux500/devices.c
+++ b/arch/arm/mach-ux500/devices.c
@@ -11,8 +11,9 @@
 #include <linux/io.h>
 #include <linux/amba/bus.h>
 
-#include <mach/hardware.h>
-#include <mach/setup.h>
+#include "setup.h"
+
+#include "db8500-regs.h"
 
 void __init amba_add_devices(struct amba_device *devs[], int num)
 {
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/devices.h
index cbc6f1e4104d..cbc6f1e4104d 100644
--- a/arch/arm/mach-ux500/include/mach/devices.h
+++ b/arch/arm/mach-ux500/devices.h
diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c
index 2f6af259015d..2bc00b085e38 100644
--- a/arch/arm/mach-ux500/hotplug.c
+++ b/arch/arm/mach-ux500/hotplug.c
@@ -12,10 +12,9 @@
 #include <linux/errno.h>
 #include <linux/smp.h>
 
-#include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 
-#include <mach/setup.h>
+#include "setup.h"
 
 /*
  * platform-specific code to shutdown a CPU
@@ -24,8 +23,6 @@
  */
 void __ref ux500_cpu_die(unsigned int cpu)
 {
-        flush_cache_all();
-
         /* directly enter low power state, skipping secure registers */
         for (;;) {
                 __asm__ __volatile__("dsb\n\t" "wfi\n\t"
diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c
index 9f951842e1e5..0d33d1a06955 100644
--- a/arch/arm/mach-ux500/id.c
+++ b/arch/arm/mach-ux500/id.c
@@ -14,9 +14,9 @@
 #include <asm/cacheflush.h>
 #include <asm/mach/map.h>
 
-#include <mach/hardware.h>
-#include <mach/setup.h>
+#include "setup.h"
 
+#include "db8500-regs.h"
 #include "id.h"
 
 struct dbx500_asic_id dbx500_id;
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
deleted file mode 100644
index 67035223334a..000000000000
--- a/arch/arm/mach-ux500/include/mach/debug-macro.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Debugging macro include header
- *
- *  Copyright (C) 2009 ST-Ericsson
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#include <mach/hardware.h>
-
-#if CONFIG_UX500_DEBUG_UART > 2
-#error Invalid Ux500 debug UART
-#endif
-
-/*
- * DEBUG_LL only works if only one SOC is built in.  We don't use #else below
- * in order to get "__UX500_UART redefined" warnings if more than one SOC is
- * built, so that there's some hint during the build that something is wrong.
- */
-
-#ifdef CONFIG_UX500_SOC_DB8500
-#define __UX500_UART(n) U8500_UART##n##_BASE
-#endif
-
-#ifndef __UX500_UART
-#error Unknown SOC
-#endif
-
-#define UX500_UART(n)   __UX500_UART(n)
-#define UART_BASE       UX500_UART(CONFIG_UX500_DEBUG_UART)
-
-        .macro  addruart, rp, rv, tmp
-        ldr     \rp, =UART_BASE                         @ no, physical address
-        ldr     \rv, =IO_ADDRESS(UART_BASE)             @ yes, virtual address
-        .endm
-
-#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
deleted file mode 100644
index 5201ddace503..000000000000
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (C) 2009 ST-Ericsson.
- *
- * U8500 hardware definitions
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-
-/*
- * Macros to get at IO space when running virtually
- * We dont map all the peripherals, let ioremap do
- * this for us. We map only very basic peripherals here.
- */
-#define U8500_IO_VIRTUAL        0xf0000000
-#define U8500_IO_PHYSICAL       0xa0000000
-/* This is where we map in the ROM to check ASIC IDs */
-#define UX500_VIRT_ROM          0xf0000000
-
-/* This macro is used in assembly, so no cast */
-#define IO_ADDRESS(x)           \
-        (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
-
-/* typesafe io address */
-#define __io_address(n)         IOMEM(IO_ADDRESS(n))
-
-/* Used by some plat-nomadik code */
-#define io_p2v(n)               __io_address(n)
-
-#include <mach/db8500-regs.h>
-
-#define MSP_TX_RX_REG_OFFSET    0
-#define CRYP1_RX_REG_OFFSET     0x10
-#define CRYP1_TX_REG_OFFSET     0x8
-#define HASH1_TX_REG_OFFSET     0x4
-
-#ifndef __ASSEMBLY__
-
-extern void __iomem *_PRCMU_BASE;
-
-#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
-
-#endif                          /* __ASSEMBLY__ */
-#endif                          /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/arch/arm/mach-ux500/include/mach/msp.h
deleted file mode 100644
index 9991aea3d577..000000000000
--- a/arch/arm/mach-ux500/include/mach/msp.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
- * License terms: GNU General Public License (GPL), version 2.
- */
-
-#ifndef __MSP_H
-#define __MSP_H
-
-#include <linux/platform_data/dma-ste-dma40.h>
-
-enum msp_i2s_id {
-        MSP_I2S_0 = 0,
-        MSP_I2S_1,
-        MSP_I2S_2,
-        MSP_I2S_3,
-};
-
-/* Platform data structure for a MSP I2S-device */
-struct msp_i2s_platform_data {
-        enum msp_i2s_id id;
-        struct stedma40_chan_cfg *msp_i2s_dma_rx;
-        struct stedma40_chan_cfg *msp_i2s_dma_tx;
-};
-
-#endif
diff --git a/arch/arm/mach-ux500/include/mach/timex.h b/arch/arm/mach-ux500/include/mach/timex.h
deleted file mode 100644
index d0942c174018..000000000000
--- a/arch/arm/mach-ux500/include/mach/timex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-
-#define CLOCK_TICK_RATE         110000000
-
-#endif
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
deleted file mode 100644
index 36969d52e53a..000000000000
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- *  Copyright (C) 2009 ST-Ericsson
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <linux/io.h>
-#include <linux/amba/serial.h>
-#include <mach/hardware.h>
-
-void __iomem *ux500_uart_base;
-
-static void putc(const char c)
-{
-        /* Do nothing if the UART is not enabled. */
-        if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1))
-                return;
-
-        if (c == '\n')
-                putc('\r');
-
-        while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 5))
-                barrier();
-        __raw_writeb(c, ux500_uart_base + UART01x_DR);
-}
-
-static void flush(void)
-{
-        if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1))
-                return;
-        while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 3))
-                barrier();
-}
-
-static inline void arch_decomp_setup(void)
-{
-        /* Use machine_is_foo() macro if you need to switch base someday */
-        ux500_uart_base = (void __iomem *)U8500_UART2_BASE;
-}
-
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/irqs-board-mop500.h
index d526dd8e87d3..d526dd8e87d3 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
+++ b/arch/arm/mach-ux500/irqs-board-mop500.h
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db8500.h b/arch/arm/mach-ux500/irqs-db8500.h
index 68bc14974608..f3a9d5947ef3 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-db8500.h
+++ b/arch/arm/mach-ux500/irqs-db8500.h
@@ -109,31 +109,6 @@
 
 /* Virtual interrupts corresponding to the PRCMU wakeups.  */
 #define IRQ_PRCMU_BASE IRQ_SOC_START
-#define NUM_PRCMU_WAKEUPS (IRQ_PRCMU_END - IRQ_PRCMU_BASE)
-
-#define IRQ_PRCMU_RTC (IRQ_PRCMU_BASE)
-#define IRQ_PRCMU_RTT0 (IRQ_PRCMU_BASE + 1)
-#define IRQ_PRCMU_RTT1 (IRQ_PRCMU_BASE + 2)
-#define IRQ_PRCMU_HSI0 (IRQ_PRCMU_BASE + 3)
-#define IRQ_PRCMU_HSI1 (IRQ_PRCMU_BASE + 4)
-#define IRQ_PRCMU_CA_WAKE (IRQ_PRCMU_BASE + 5)
-#define IRQ_PRCMU_USB (IRQ_PRCMU_BASE + 6)
-#define IRQ_PRCMU_ABB (IRQ_PRCMU_BASE + 7)
-#define IRQ_PRCMU_ABB_FIFO (IRQ_PRCMU_BASE + 8)
-#define IRQ_PRCMU_ARM (IRQ_PRCMU_BASE + 9)
-#define IRQ_PRCMU_MODEM_SW_RESET_REQ (IRQ_PRCMU_BASE + 10)
-#define IRQ_PRCMU_GPIO0 (IRQ_PRCMU_BASE + 11)
-#define IRQ_PRCMU_GPIO1 (IRQ_PRCMU_BASE + 12)
-#define IRQ_PRCMU_GPIO2 (IRQ_PRCMU_BASE + 13)
-#define IRQ_PRCMU_GPIO3 (IRQ_PRCMU_BASE + 14)
-#define IRQ_PRCMU_GPIO4 (IRQ_PRCMU_BASE + 15)
-#define IRQ_PRCMU_GPIO5 (IRQ_PRCMU_BASE + 16)
-#define IRQ_PRCMU_GPIO6 (IRQ_PRCMU_BASE + 17)
-#define IRQ_PRCMU_GPIO7 (IRQ_PRCMU_BASE + 18)
-#define IRQ_PRCMU_GPIO8 (IRQ_PRCMU_BASE + 19)
-#define IRQ_PRCMU_CA_SLEEP (IRQ_PRCMU_BASE + 20)
-#define IRQ_PRCMU_HOTMON_LOW (IRQ_PRCMU_BASE + 21)
-#define IRQ_PRCMU_HOTMON_HIGH (IRQ_PRCMU_BASE + 22)
 #define IRQ_PRCMU_END (IRQ_PRCMU_BASE + 23)
 
 /*
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/irqs.h
index fc77b4274c8d..15b2af698ed7 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/irqs.h
@@ -10,8 +10,6 @@
 #ifndef ASM_ARCH_IRQS_H
 #define ASM_ARCH_IRQS_H
 
-#include <mach/hardware.h>
-
 #define IRQ_LOCALTIMER                  29
 #define IRQ_LOCALWDOG                   30
 
@@ -36,14 +34,14 @@
 /* This will be overridden by SoC-specific irq headers */
 #define IRQ_SOC_END             IRQ_SOC_START
 
-#include <mach/irqs-db8500.h>
+#include "irqs-db8500.h"
 
 #define IRQ_BOARD_START         IRQ_SOC_END
 /* This will be overridden by board-specific irq headers */
 #define IRQ_BOARD_END           IRQ_BOARD_START
 
 #ifdef CONFIG_MACH_MOP500
-#include <mach/irqs-board-mop500.h>
+#include "irqs-board-mop500.h"
 #endif
 
 #define UX500_NR_IRQS           IRQ_BOARD_END
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 18f7af339dc9..14d90469392f 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -16,15 +16,14 @@
 #include <linux/device.h>
 #include <linux/smp.h>
 #include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
 
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 
-#include <mach/hardware.h>
-#include <mach/setup.h>
+#include "setup.h"
 
+#include "db8500-regs.h"
 #include "id.h"
 
 /* This is called from headsmp.S to wakeup the secondary core */
@@ -58,13 +57,6 @@ static DEFINE_SPINLOCK(boot_lock);
 static void __cpuinit ux500_secondary_init(unsigned int cpu)
 {
         /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-
-        /*
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
diff --git a/arch/arm/mach-ux500/pm.c b/arch/arm/mach-ux500/pm.c
new file mode 100644
index 000000000000..1a468f0fd22e
--- /dev/null
+++ b/arch/arm/mach-ux500/pm.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010-2013
+ * Author: Rickard Andersson <rickard.andersson@stericsson.com> for
+ *         ST-Ericsson.
+ * Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro.
+ * License terms: GNU General Public License (GPL) version 2
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/irqchip/arm-gic.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/platform_data/arm-ux500-pm.h>
+
+#include "db8500-regs.h"
+
+/* ARM WFI Standby signal register */
+#define PRCM_ARM_WFI_STANDBY    (prcmu_base + 0x130)
+#define PRCM_ARM_WFI_STANDBY_WFI0               0x08
+#define PRCM_ARM_WFI_STANDBY_WFI1               0x10
+#define PRCM_IOCR               (prcmu_base + 0x310)
+#define PRCM_IOCR_IOFORCE                       0x1
+
+/* Dual A9 core interrupt management unit registers */
+#define PRCM_A9_MASK_REQ        (prcmu_base + 0x328)
+#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ       0x1
+
+#define PRCM_A9_MASK_ACK        (prcmu_base + 0x32c)
+#define PRCM_ARMITMSK31TO0      (prcmu_base + 0x11c)
+#define PRCM_ARMITMSK63TO32     (prcmu_base + 0x120)
+#define PRCM_ARMITMSK95TO64     (prcmu_base + 0x124)
+#define PRCM_ARMITMSK127TO96    (prcmu_base + 0x128)
+#define PRCM_POWER_STATE_VAL    (prcmu_base + 0x25C)
+#define PRCM_ARMITVAL31TO0      (prcmu_base + 0x260)
+#define PRCM_ARMITVAL63TO32     (prcmu_base + 0x264)
+#define PRCM_ARMITVAL95TO64     (prcmu_base + 0x268)
+#define PRCM_ARMITVAL127TO96    (prcmu_base + 0x26C)
+
+static void __iomem *prcmu_base;
+
+/* This function decouple the gic from the prcmu */
+int prcmu_gic_decouple(void)
+{
+        u32 val = readl(PRCM_A9_MASK_REQ);
+
+        /* Set bit 0 register value to 1 */
+        writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
+               PRCM_A9_MASK_REQ);
+
+        /* Make sure the register is updated */
+        readl(PRCM_A9_MASK_REQ);
+
+        /* Wait a few cycles for the gic mask completion */
+        udelay(1);
+
+        return 0;
+}
+
+/* This function recouple the gic with the prcmu */
+int prcmu_gic_recouple(void)
+{
+        u32 val = readl(PRCM_A9_MASK_REQ);
+
+        /* Set bit 0 register value to 0 */
+        writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
+
+        return 0;
+}
+
+#define PRCMU_GIC_NUMBER_REGS 5
+
+/*
+ * This function checks if there are pending irq on the gic. It only
+ * makes sense if the gic has been decoupled before with the
+ * db8500_prcmu_gic_decouple function. Disabling an interrupt only
+ * disables the forwarding of the interrupt to any CPU interface. It
+ * does not prevent the interrupt from changing state, for example
+ * becoming pending, or active and pending if it is already
+ * active. Hence, we have to check the interrupt is pending *and* is
+ * active.
+ */
+bool prcmu_gic_pending_irq(void)
+{
+        u32 pr; /* Pending register */
+        u32 er; /* Enable register */
+        void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
+        int i;
+
+        /* 5 registers. STI & PPI not skipped */
+        for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {
+
+                pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
+                er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
+
+                if (pr & er)
+                        return true; /* There is a pending interrupt */
+        }
+
+        return false;
+}
+
+/*
+ * This function checks if there are pending interrupt on the
+ * prcmu which has been delegated to monitor the irqs with the
+ * db8500_prcmu_copy_gic_settings function.
+ */
+bool prcmu_pending_irq(void)
+{
+        u32 it, im;
+        int i;
+
+        for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
+                it = readl(PRCM_ARMITVAL31TO0 + i * 4);
+                im = readl(PRCM_ARMITMSK31TO0 + i * 4);
+                if (it & im)
+                        return true; /* There is a pending interrupt */
+        }
+
+        return false;
+}
+
+/*
+ * This function checks if the specified cpu is in in WFI. It's usage
+ * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
+ * function. Of course passing smp_processor_id() to this function will
+ * always return false...
+ */
+bool prcmu_is_cpu_in_wfi(int cpu)
+{
+        return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 :
+                     PRCM_ARM_WFI_STANDBY_WFI0;
+}
+
+/*
+ * This function copies the gic SPI settings to the prcmu in order to
+ * monitor them and abort/finish the retention/off sequence or state.
+ */
+int prcmu_copy_gic_settings(void)
+{
+        u32 er; /* Enable register */
+        void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
+        int i;
+
+        /* We skip the STI and PPI */
+        for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
+                er = readl_relaxed(dist_base +
+                                   GIC_DIST_ENABLE_SET + (i + 1) * 4);
+                writel(er, PRCM_ARMITMSK31TO0 + i * 4);
+        }
+
+        return 0;
+}
+
+void __init ux500_pm_init(u32 phy_base, u32 size)
+{
+        prcmu_base = ioremap(phy_base, size);
+        if (!prcmu_base) {
+                pr_err("could not remap PRCMU for PM functions\n");
+                return;
+        }
+        /*
+         * On watchdog reboot the GIC is in some cases decoupled.
+         * This will make sure that the GIC is correctly configured.
+         */
+        prcmu_gic_recouple();
+}
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/setup.h
index bddce2b49372..bddce2b49372 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/setup.h
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index a6af0b8732ba..b6bd0efcbe64 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -7,16 +7,17 @@
 #include <linux/io.h>
 #include <linux/errno.h>
 #include <linux/clksrc-dbx500-prcmu.h>
+#include <linux/clocksource.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/platform_data/clocksource-nomadik-mtu.h>
 
 #include <asm/smp_twd.h>
 
-#include <mach/setup.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
+#include "setup.h"
+#include "irqs.h"
 
+#include "db8500-regs.h"
 #include "id.h"
 
 #ifdef CONFIG_HAVE_ARM_TWD
@@ -32,7 +33,7 @@ static void __init ux500_twd_init(void)
         twd_local_timer = &u8500_twd_local_timer;
 
         if (of_have_populated_dt())
-                twd_local_timer_of_register();
+                clocksource_of_init();
         else {
                 err = twd_local_timer_register(twd_local_timer);
                 if (err)
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 78ac65f62e87..2dfc72f7cd8a 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -10,7 +10,7 @@
 #include <linux/platform_data/usb-musb-ux500.h>
 #include <linux/platform_data/dma-ste-dma40.h>
 
-#include <mach/hardware.h>
+#include "db8500-regs.h"
 
 #define MUSB_DMA40_RX_CH { \
                 .mode = STEDMA40_MODE_LOGICAL, \
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 52d315b792c8..5907e10c37fd 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -9,6 +9,8 @@ config ARCH_VEXPRESS
         select COMMON_CLK_VERSATILE
         select CPU_V7
         select GENERIC_CLOCKEVENTS
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
         select HAVE_CLK
         select HAVE_PATA_PLATFORM
         select HAVE_SMP
@@ -17,6 +19,9 @@ config ARCH_VEXPRESS
         select NO_IOPORT
         select PLAT_VERSATILE
         select PLAT_VERSATILE_CLCD
+        select POWER_RESET
+        select POWER_RESET_VEXPRESS
+        select POWER_SUPPLY
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
         select VEXPRESS_CONFIG
         help
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 80b64971fbdd..42703e8b4d3b 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -4,7 +4,7 @@
 ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
         -I$(srctree)/arch/arm/plat-versatile/include
 
-obj-y                                   := v2m.o reset.o
+obj-y                                   := v2m.o
 obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)       += ct-ca9x4.o
 obj-$(CONFIG_SMP)                       += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-vexpress/hotplug.c b/arch/arm/mach-vexpress/hotplug.c
index a141b98d84fe..f0ce6b8f5e71 100644
--- a/arch/arm/mach-vexpress/hotplug.c
+++ b/arch/arm/mach-vexpress/hotplug.c
@@ -12,7 +12,6 @@
 #include <linux/errno.h>
 #include <linux/smp.h>
 
-#include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <asm/cp15.h>
 
@@ -20,7 +19,6 @@ static inline void cpu_enter_lowpower(void)
 {
         unsigned int v;
 
-        flush_cache_all();
         asm volatile(
                 "mcr    p15, 0, %1, c7, c5, 0\n"
         "       mcr     p15, 0, %1, c7, c10, 4\n"
diff --git a/arch/arm/mach-vexpress/reset.c b/arch/arm/mach-vexpress/reset.c
deleted file mode 100644
index 465923aa3819..000000000000
--- a/arch/arm/mach-vexpress/reset.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * Copyright (C) 2012 ARM Limited
- */
-
-#include <linux/jiffies.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/stat.h>
-#include <linux/vexpress.h>
-
-static void vexpress_reset_do(struct device *dev, const char *what)
-{
-        int err = -ENOENT;
-        struct vexpress_config_func *func =
-                        vexpress_config_func_get_by_dev(dev);
-
-        if (func) {
-                unsigned long timeout;
-
-                err = vexpress_config_write(func, 0, 0);
-
-                timeout = jiffies + HZ;
-                while (time_before(jiffies, timeout))
-                        cpu_relax();
-        }
-
-        dev_emerg(dev, "Unable to %s (%d)\n", what, err);
-}
-
-static struct device *vexpress_power_off_device;
-
-void vexpress_power_off(void)
-{
-        vexpress_reset_do(vexpress_power_off_device, "power off");
-}
-
-static struct device *vexpress_restart_device;
-
-void vexpress_restart(char str, const char *cmd)
-{
-        vexpress_reset_do(vexpress_restart_device, "restart");
-}
-
-static ssize_t vexpress_reset_active_show(struct device *dev,
-                struct device_attribute *attr, char *buf)
-{
-        return sprintf(buf, "%d\n", vexpress_restart_device == dev);
-}
-
-static ssize_t vexpress_reset_active_store(struct device *dev,
-                struct device_attribute *attr, const char *buf, size_t count)
-{
-        long value;
-        int err = kstrtol(buf, 0, &value);
-
-        if (!err && value)
-                vexpress_restart_device = dev;
-
-        return err ? err : count;
-}
-
-DEVICE_ATTR(active, S_IRUGO | S_IWUSR, vexpress_reset_active_show,
-                vexpress_reset_active_store);
-
-
-enum vexpress_reset_func { FUNC_RESET, FUNC_SHUTDOWN, FUNC_REBOOT };
-
-static struct of_device_id vexpress_reset_of_match[] = {
-        {
-                .compatible = "arm,vexpress-reset",
-                .data = (void *)FUNC_RESET,
-        }, {
-                .compatible = "arm,vexpress-shutdown",
-                .data = (void *)FUNC_SHUTDOWN
-        }, {
-                .compatible = "arm,vexpress-reboot",
-                .data = (void *)FUNC_REBOOT
-        },
-        {}
-};
-
-static int vexpress_reset_probe(struct platform_device *pdev)
-{
-        enum vexpress_reset_func func;
-        const struct of_device_id *match =
-                        of_match_device(vexpress_reset_of_match, &pdev->dev);
-
-        if (match)
-                func = (enum vexpress_reset_func)match->data;
-        else
-                func = pdev->id_entry->driver_data;
-
-        switch (func) {
-        case FUNC_SHUTDOWN:
-                vexpress_power_off_device = &pdev->dev;
-                break;
-        case FUNC_RESET:
-                if (!vexpress_restart_device)
-                        vexpress_restart_device = &pdev->dev;
-                device_create_file(&pdev->dev, &dev_attr_active);
-                break;
-        case FUNC_REBOOT:
-                vexpress_restart_device = &pdev->dev;
-                device_create_file(&pdev->dev, &dev_attr_active);
-                break;
-        };
-
-        return 0;
-}
-
-static const struct platform_device_id vexpress_reset_id_table[] = {
-        { .name = "vexpress-reset", .driver_data = FUNC_RESET, },
-        { .name = "vexpress-shutdown", .driver_data = FUNC_SHUTDOWN, },
-        { .name = "vexpress-reboot", .driver_data = FUNC_REBOOT, },
-        {}
-};
-
-static struct platform_driver vexpress_reset_driver = {
-        .probe = vexpress_reset_probe,
-        .driver = {
-                .name = "vexpress-reset",
-                .of_match_table = vexpress_reset_of_match,
-        },
-        .id_table = vexpress_reset_id_table,
-};
-
-static int __init vexpress_reset_init(void)
-{
-        return platform_driver_register(&vexpress_reset_driver);
-}
-device_initcall(vexpress_reset_init);
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 915683cb67d6..9366f37902d9 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -5,6 +5,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
+#include <linux/clocksource.h>
 #include <linux/smp.h>
 #include <linux/init.h>
 #include <linux/irqchip.h>
@@ -21,11 +22,12 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/vexpress.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
 
 #include <asm/arch_timer.h>
 #include <asm/mach-types.h>
 #include <asm/sizes.h>
-#include <asm/smp_twd.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -361,8 +363,6 @@ static void __init v2m_init(void)
         for (i = 0; i < ARRAY_SIZE(v2m_amba_devs); i++)
                 amba_device_register(v2m_amba_devs[i], &iomem_resource);
 
-        pm_power_off = vexpress_power_off;
-
         ct_desc->init_tile();
 }
 
@@ -374,7 +374,6 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
         .init_irq       = v2m_init_irq,
         .init_time      = v2m_timer_init,
         .init_machine   = v2m_init,
-        .restart        = vexpress_restart,
 MACHINE_END
 
 static struct map_desc v2m_rs1_io_desc __initdata = {
@@ -433,20 +432,24 @@ static void __init v2m_dt_timer_init(void)
 {
         struct device_node *node = NULL;
 
-        vexpress_clk_of_init();
+        of_clk_init(NULL);
 
+        clocksource_of_init();
         do {
                 node = of_find_compatible_node(node, NULL, "arm,sp804");
         } while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB);
         if (node) {
                 pr_info("Using SP804 '%s' as a clock & events source\n",
                                 node->full_name);
+                WARN_ON(clk_register_clkdev(of_clk_get_by_name(node,
+                                "timclken1"), "v2m-timer0", "sp804"));
+                WARN_ON(clk_register_clkdev(of_clk_get_by_name(node,
+                                "timclken2"), "v2m-timer1", "sp804"));
                 v2m_sp804_init(of_iomap(node, 0),
                                 irq_of_parse_and_map(node, 0));
         }
 
-        if (arch_timer_of_register() != 0)
-                twd_local_timer_of_register();
+        arch_timer_of_register();
 
         if (arch_timer_sched_clock_init() != 0)
                 versatile_sched_clock_init(vexpress_get_24mhz_clock_base(),
@@ -464,7 +467,6 @@ static void __init v2m_dt_init(void)
 {
         l2x0_of_init(0x00400000, 0xfe0fffff);
         of_platform_populate(NULL, v2m_dt_bus_match, NULL, NULL);
-        pm_power_off = vexpress_power_off;
 }
 
 static const char * const v2m_dt_match[] __initconst = {
@@ -481,5 +483,4 @@ DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
         .init_irq       = irqchip_init,
         .init_time      = v2m_dt_timer_init,
         .init_machine   = v2m_dt_init,
-        .restart        = vexpress_restart,
 MACHINE_END
diff --git a/arch/arm/mach-virt/platsmp.c b/arch/arm/mach-virt/platsmp.c
index 8badaabe70a1..f4143f5bfa5b 100644
--- a/arch/arm/mach-virt/platsmp.c
+++ b/arch/arm/mach-virt/platsmp.c
@@ -21,8 +21,6 @@
 #include <linux/smp.h>
 #include <linux/of.h>
 
-#include <linux/irqchip/arm-gic.h>
-
 #include <asm/psci.h>
 #include <asm/smp_plat.h>
 
@@ -45,14 +43,8 @@ static int __cpuinit virt_boot_secondary(unsigned int cpu,
         return -ENODEV;
 }
 
-static void __cpuinit virt_secondary_init(unsigned int cpu)
-{
-        gic_secondary_init(0);
-}
-
 struct smp_operations __initdata virt_smp_ops = {
         .smp_init_cpus          = virt_smp_init_cpus,
         .smp_prepare_cpus       = virt_smp_prepare_cpus,
-        .smp_secondary_init     = virt_secondary_init,
         .smp_boot_secondary     = virt_boot_secondary,
 };
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
index e3e94b2fa145..9b252934b206 100644
--- a/arch/arm/mach-vt8500/Kconfig
+++ b/arch/arm/mach-vt8500/Kconfig
@@ -7,6 +7,7 @@ config ARCH_VT8500
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK
         select VT8500_TIMER
+        select PINCTRL
         help
           Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 
diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile
index 92ceb2436b60..4c8a84637594 100644
--- a/arch/arm/mach-vt8500/Makefile
+++ b/arch/arm/mach-vt8500/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_ARCH_VT8500) += irq.o vt8500.o
+obj-$(CONFIG_ARCH_VT8500) += vt8500.o
diff --git a/arch/arm/mach-vt8500/common.h b/arch/arm/mach-vt8500/common.h
index 77611a6968d6..087787af62f1 100644
--- a/arch/arm/mach-vt8500/common.h
+++ b/arch/arm/mach-vt8500/common.h
@@ -18,13 +18,7 @@
 
 #include <linux/of.h>
 
-int __init vt8500_irq_init(struct device_node *node,
-                                struct device_node *parent);
-
 /* defined in drivers/clk/clk-vt8500.c */
 void __init vtwm_clk_init(void __iomem *pmc_base);
 
-/* defined in irq.c */
-asmlinkage void vt8500_handle_irq(struct pt_regs *regs);
-
 #endif
diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c
deleted file mode 100644
index b9cf5ce9efbb..000000000000
--- a/arch/arm/mach-vt8500/irq.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/irq.c
- *
- *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/*
- * This file is copied and modified from the original irq.c provided by
- * Alexey Charkov. Minor changes have been made for Device Tree Support.
- */
-
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/interrupt.h>
-#include <linux/bitops.h>
-
-#include <linux/of.h>
-#include <linux/of_irq.h>
-#include <linux/of_address.h>
-
-#include <asm/irq.h>
-#include <asm/exception.h>
-
-#define VT8500_ICPC_IRQ         0x20
-#define VT8500_ICPC_FIQ         0x24
-#define VT8500_ICDC             0x40            /* Destination Control 64*u32 */
-#define VT8500_ICIS             0x80            /* Interrupt status, 16*u32 */
-
-/* ICPC */
-#define ICPC_MASK               0x3F
-#define ICPC_ROTATE             BIT(6)
-
-/* IC_DCTR */
-#define ICDC_IRQ                0x00
-#define ICDC_FIQ                0x01
-#define ICDC_DSS0               0x02
-#define ICDC_DSS1               0x03
-#define ICDC_DSS2               0x04
-#define ICDC_DSS3               0x05
-#define ICDC_DSS4               0x06
-#define ICDC_DSS5               0x07
-
-#define VT8500_INT_DISABLE      0
-#define VT8500_INT_ENABLE       BIT(3)
-
-#define VT8500_TRIGGER_HIGH     0
-#define VT8500_TRIGGER_RISING   BIT(5)
-#define VT8500_TRIGGER_FALLING  BIT(6)
-#define VT8500_EDGE             ( VT8500_TRIGGER_RISING \
-                                | VT8500_TRIGGER_FALLING)
-
-/* vt8500 has 1 intc, wm8505 and wm8650 have 2 */
-#define VT8500_INTC_MAX         2
-
-struct vt8500_irq_data {
-        void __iomem            *base;          /* IO Memory base address */
-        struct irq_domain       *domain;        /* Domain for this controller */
-};
-
-/* Global variable for accessing io-mem addresses */
-static struct vt8500_irq_data intc[VT8500_INTC_MAX];
-static u32 active_cnt = 0;
-
-static void vt8500_irq_mask(struct irq_data *d)
-{
-        struct vt8500_irq_data *priv = d->domain->host_data;
-        void __iomem *base = priv->base;
-        void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4);
-        u8 edge, dctr;
-        u32 status;
-
-        edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
-        if (edge) {
-                status = readl(stat_reg);
-
-                status |= (1 << (d->hwirq & 0x1f));
-                writel(status, stat_reg);
-        } else {
-                dctr = readb(base + VT8500_ICDC + d->hwirq);
-                dctr &= ~VT8500_INT_ENABLE;
-                writeb(dctr, base + VT8500_ICDC + d->hwirq);
-        }
-}
-
-static void vt8500_irq_unmask(struct irq_data *d)
-{
-        struct vt8500_irq_data *priv = d->domain->host_data;
-        void __iomem *base = priv->base;
-        u8 dctr;
-
-        dctr = readb(base + VT8500_ICDC + d->hwirq);
-        dctr |= VT8500_INT_ENABLE;
-        writeb(dctr, base + VT8500_ICDC + d->hwirq);
-}
-
-static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
-{
-        struct vt8500_irq_data *priv = d->domain->host_data;
-        void __iomem *base = priv->base;
-        u8 dctr;
-
-        dctr = readb(base + VT8500_ICDC + d->hwirq);
-        dctr &= ~VT8500_EDGE;
-
-        switch (flow_type) {
-        case IRQF_TRIGGER_LOW:
-                return -EINVAL;
-        case IRQF_TRIGGER_HIGH:
-                dctr |= VT8500_TRIGGER_HIGH;
-                __irq_set_handler_locked(d->irq, handle_level_irq);
-                break;
-        case IRQF_TRIGGER_FALLING:
-                dctr |= VT8500_TRIGGER_FALLING;
-                __irq_set_handler_locked(d->irq, handle_edge_irq);
-                break;
-        case IRQF_TRIGGER_RISING:
-                dctr |= VT8500_TRIGGER_RISING;
-                __irq_set_handler_locked(d->irq, handle_edge_irq);
-                break;
-        }
-        writeb(dctr, base + VT8500_ICDC + d->hwirq);
-
-        return 0;
-}
-
-static struct irq_chip vt8500_irq_chip = {
-        .name = "vt8500",
-        .irq_ack = vt8500_irq_mask,
-        .irq_mask = vt8500_irq_mask,
-        .irq_unmask = vt8500_irq_unmask,
-        .irq_set_type = vt8500_irq_set_type,
-};
-
-static void __init vt8500_init_irq_hw(void __iomem *base)
-{
-        u32 i;
-
-        /* Enable rotating priority for IRQ */
-        writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
-        writel(0x00, base + VT8500_ICPC_FIQ);
-
-        /* Disable all interrupts and route them to IRQ */
-        for (i = 0; i < 64; i++)
-                writeb(VT8500_INT_DISABLE | ICDC_IRQ, base + VT8500_ICDC + i);
-}
-
-static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
-                                                        irq_hw_number_t hw)
-{
-        irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
-        set_irq_flags(virq, IRQF_VALID);
-
-        return 0;
-}
-
-static struct irq_domain_ops vt8500_irq_domain_ops = {
-        .map = vt8500_irq_map,
-        .xlate = irq_domain_xlate_onecell,
-};
-
-asmlinkage void __exception_irq_entry vt8500_handle_irq(struct pt_regs *regs)
-{
-        u32 stat, i;
-        int irqnr, virq;
-        void __iomem *base;
-
-        /* Loop through each active controller */
-        for (i=0; i<active_cnt; i++) {
-                base = intc[i].base;
-                irqnr = readl_relaxed(base) & 0x3F;
-                /*
-                  Highest Priority register default = 63, so check that this
-                  is a real interrupt by checking the status register
-                */
-                if (irqnr == 63) {
-                        stat = readl_relaxed(base + VT8500_ICIS + 4);
-                        if (!(stat & BIT(31)))
-                                continue;
-                }
-
-                virq = irq_find_mapping(intc[i].domain, irqnr);
-                handle_IRQ(virq, regs);
-        }
-}
-
-int __init vt8500_irq_init(struct device_node *node, struct device_node *parent)
-{
-        int irq, i;
-        struct device_node *np = node;
-
-        if (active_cnt == VT8500_INTC_MAX) {
-                pr_err("%s: Interrupt controllers > VT8500_INTC_MAX\n",
-                                                                __func__);
-                goto out;
-        }
-
-        intc[active_cnt].base = of_iomap(np, 0);
-        intc[active_cnt].domain = irq_domain_add_linear(node, 64,
-                        &vt8500_irq_domain_ops, &intc[active_cnt]);
-
-        if (!intc[active_cnt].base) {
-                pr_err("%s: Unable to map IO memory\n", __func__);
-                goto out;
-        }
-
-        if (!intc[active_cnt].domain) {
-                pr_err("%s: Unable to add irq domain!\n", __func__);
-                goto out;
-        }
-
-        vt8500_init_irq_hw(intc[active_cnt].base);
-
-        pr_info("vt8500-irq: Added interrupt controller\n");
-
-        active_cnt++;
-
-        /* check if this is a slaved controller */
-        if (of_irq_count(np) != 0) {
-                /* check that we have the correct number of interrupts */
-                if (of_irq_count(np) != 8) {
-                        pr_err("%s: Incorrect IRQ map for slaved controller\n",
-                                        __func__);
-                        return -EINVAL;
-                }
-
-                for (i = 0; i < 8; i++) {
-                        irq = irq_of_parse_and_map(np, i);
-                        enable_irq(irq);
-                }
-
-                pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
-        }
-out:
-        return 0;
-}
-
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index 49e80053d828..1dd281efc020 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -20,6 +20,7 @@
 
 #include <linux/clocksource.h>
 #include <linux/io.h>
+#include <linux/irqchip.h>
 #include <linux/pm.h>
 
 #include <asm/mach-types.h>
@@ -166,16 +167,6 @@ void __init vt8500_init(void)
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static const struct of_device_id vt8500_irq_match[] __initconst = {
-        { .compatible = "via,vt8500-intc", .data = vt8500_irq_init, },
-        { /* sentinel */ },
-};
-
-static void __init vt8500_init_irq(void)
-{
-        of_irq_init(vt8500_irq_match);
-};
-
 static const char * const vt8500_dt_compat[] = {
         "via,vt8500",
         "wm,wm8650",
@@ -187,10 +178,9 @@ static const char * const vt8500_dt_compat[] = {
 DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
         .dt_compat      = vt8500_dt_compat,
         .map_io         = vt8500_map_io,
-        .init_irq       = vt8500_init_irq,
+        .init_irq       = irqchip_init,
         .init_machine   = vt8500_init,
         .init_time      = clocksource_of_init,
         .restart        = vt8500_restart,
-        .handle_irq     = vt8500_handle_irq,
 MACHINE_END
 
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c
index 7abdb9645c5b..e65a80a1ac75 100644
--- a/arch/arm/mach-w90x900/dev.c
+++ b/arch/arm/mach-w90x900/dev.c
@@ -19,6 +19,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
+#include <linux/cpu.h>
 
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/mtd.h>
@@ -531,7 +532,7 @@ static struct platform_device *nuc900_public_dev[] __initdata = {
 
 void __init nuc900_board_init(struct platform_device **device, int size)
 {
-        disable_hlt();
+        cpu_idle_poll_ctrl(true);
         platform_add_devices(device, size);
         platform_add_devices(nuc900_public_dev, ARRAY_SIZE(nuc900_public_dev));
         spi_register_board_info(nuc900_spi_board_info,
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index adb6c0ea0e53..cf3226b041f5 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -5,9 +5,12 @@ config ARCH_ZYNQ
         select COMMON_CLK
         select CPU_V7
         select GENERIC_CLOCKEVENTS
+        select HAVE_ARM_SCU if SMP
+        select HAVE_ARM_TWD if LOCAL_TIMERS
         select ICST
         select MIGHT_HAVE_CACHE_L2X0
         select USE_OF
         select SPARSE_IRQ
+        select CADENCE_TTC_TIMER
         help
           Support for Xilinx Zynq ARM Cortex A9 Platform
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
index 397268c1b250..320faedeb484 100644
--- a/arch/arm/mach-zynq/Makefile
+++ b/arch/arm/mach-zynq/Makefile
@@ -3,4 +3,4 @@
 #
 
 # Common support
-obj-y                           := common.o timer.o
+obj-y                           := common.o
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 5c8983218183..68e0907de5d0 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -20,6 +20,7 @@
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 #include <linux/clk/zynq.h>
+#include <linux/clocksource.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
@@ -77,7 +78,7 @@ static void __init xilinx_zynq_timer_init(void)
 
         xilinx_zynq_clocks_init(slcr);
 
-        xttcps_timer_init();
+        clocksource_of_init();
 }
 
 /**
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index 8b4dbbaa01cf..5050bb10bb12 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -17,6 +17,4 @@
 #ifndef __MACH_ZYNQ_COMMON_H__
 #define __MACH_ZYNQ_COMMON_H__
 
-void __init xttcps_timer_init(void);
-
 #endif
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
deleted file mode 100644
index f9fbc9c1e7a6..000000000000
--- a/arch/arm/mach-zynq/timer.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * This file contains driver for the Xilinx PS Timer Counter IP.
- *
- *  Copyright (C) 2011 Xilinx
- *
- * based on arch/mips/kernel/time.c timer driver
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/interrupt.h>
-#include <linux/clockchips.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/slab.h>
-#include <linux/clk-provider.h>
-#include "common.h"
-
-/*
- * Timer Register Offset Definitions of Timer 1, Increment base address by 4
- * and use same offsets for Timer 2
- */
-#define XTTCPS_CLK_CNTRL_OFFSET         0x00 /* Clock Control Reg, RW */
-#define XTTCPS_CNT_CNTRL_OFFSET         0x0C /* Counter Control Reg, RW */
-#define XTTCPS_COUNT_VAL_OFFSET         0x18 /* Counter Value Reg, RO */
-#define XTTCPS_INTR_VAL_OFFSET          0x24 /* Interval Count Reg, RW */
-#define XTTCPS_ISR_OFFSET               0x54 /* Interrupt Status Reg, RO */
-#define XTTCPS_IER_OFFSET               0x60 /* Interrupt Enable Reg, RW */
-
-#define XTTCPS_CNT_CNTRL_DISABLE_MASK   0x1
-
-/*
- * Setup the timers to use pre-scaling, using a fixed value for now that will
- * work across most input frequency, but it may need to be more dynamic
- */
-#define PRESCALE_EXPONENT       11      /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
-#define PRESCALE                2048    /* The exponent must match this */
-#define CLK_CNTRL_PRESCALE      ((PRESCALE_EXPONENT - 1) << 1)
-#define CLK_CNTRL_PRESCALE_EN   1
-#define CNT_CNTRL_RESET         (1<<4)
-
-/**
- * struct xttcps_timer - This definition defines local timer structure
- *
- * @base_addr:  Base address of timer
- **/
-struct xttcps_timer {
-        void __iomem    *base_addr;
-};
-
-struct xttcps_timer_clocksource {
-        struct xttcps_timer     xttc;
-        struct clocksource      cs;
-};
-
-#define to_xttcps_timer_clksrc(x) \
-                container_of(x, struct xttcps_timer_clocksource, cs)
-
-struct xttcps_timer_clockevent {
-        struct xttcps_timer             xttc;
-        struct clock_event_device       ce;
-        struct clk                      *clk;
-};
-
-#define to_xttcps_timer_clkevent(x) \
-                container_of(x, struct xttcps_timer_clockevent, ce)
-
-/**
- * xttcps_set_interval - Set the timer interval value
- *
- * @timer:      Pointer to the timer instance
- * @cycles:     Timer interval ticks
- **/
-static void xttcps_set_interval(struct xttcps_timer *timer,
-                                        unsigned long cycles)
-{
-        u32 ctrl_reg;
-
-        /* Disable the counter, set the counter value  and re-enable counter */
-        ctrl_reg = __raw_readl(timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-        ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
-        __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-
-        __raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET);
-
-        /*
-         * Reset the counter (0x10) so that it starts from 0, one-shot
-         * mode makes this needed for timing to be right.
-         */
-        ctrl_reg |= CNT_CNTRL_RESET;
-        ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
-        __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-}
-
-/**
- * xttcps_clock_event_interrupt - Clock event timer interrupt handler
- *
- * @irq:        IRQ number of the Timer
- * @dev_id:     void pointer to the xttcps_timer instance
- *
- * returns: Always IRQ_HANDLED - success
- **/
-static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id)
-{
-        struct xttcps_timer_clockevent *xttce = dev_id;
-        struct xttcps_timer *timer = &xttce->xttc;
-
-        /* Acknowledge the interrupt and call event handler */
-        __raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);
-
-        xttce->ce.event_handler(&xttce->ce);
-
-        return IRQ_HANDLED;
-}
-
-/**
- * __xttc_clocksource_read - Reads the timer counter register
- *
- * returns: Current timer counter register value
- **/
-static cycle_t __xttc_clocksource_read(struct clocksource *cs)
-{
-        struct xttcps_timer *timer = &to_xttcps_timer_clksrc(cs)->xttc;
-
-        return (cycle_t)__raw_readl(timer->base_addr +
-                                XTTCPS_COUNT_VAL_OFFSET);
-}
-
-/**
- * xttcps_set_next_event - Sets the time interval for next event
- *
- * @cycles:     Timer interval ticks
- * @evt:        Address of clock event instance
- *
- * returns: Always 0 - success
- **/
-static int xttcps_set_next_event(unsigned long cycles,
-                                        struct clock_event_device *evt)
-{
-        struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
-        struct xttcps_timer *timer = &xttce->xttc;
-
-        xttcps_set_interval(timer, cycles);
-        return 0;
-}
-
-/**
- * xttcps_set_mode - Sets the mode of timer
- *
- * @mode:       Mode to be set
- * @evt:        Address of clock event instance
- **/
-static void xttcps_set_mode(enum clock_event_mode mode,
-                                        struct clock_event_device *evt)
-{
-        struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
-        struct xttcps_timer *timer = &xttce->xttc;
-        u32 ctrl_reg;
-
-        switch (mode) {
-        case CLOCK_EVT_MODE_PERIODIC:
-                xttcps_set_interval(timer,
-                                     DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
-                                                       PRESCALE * HZ));
-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-                ctrl_reg = __raw_readl(timer->base_addr +
-                                        XTTCPS_CNT_CNTRL_OFFSET);
-                ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
-                __raw_writel(ctrl_reg,
-                                timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-                break;
-        case CLOCK_EVT_MODE_RESUME:
-                ctrl_reg = __raw_readl(timer->base_addr +
-                                        XTTCPS_CNT_CNTRL_OFFSET);
-                ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
-                __raw_writel(ctrl_reg,
-                                timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-                break;
-        }
-}
-
-static void __init zynq_ttc_setup_clocksource(struct device_node *np,
-                                             void __iomem *base)
-{
-        struct xttcps_timer_clocksource *ttccs;
-        struct clk *clk;
-        int err;
-        u32 reg;
-
-        ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
-        if (WARN_ON(!ttccs))
-                return;
-
-        err = of_property_read_u32(np, "reg", &reg);
-        if (WARN_ON(err))
-                return;
-
-        clk = of_clk_get_by_name(np, "cpu_1x");
-        if (WARN_ON(IS_ERR(clk)))
-                return;
-
-        err = clk_prepare_enable(clk);
-        if (WARN_ON(err))
-                return;
-
-        ttccs->xttc.base_addr = base + reg * 4;
-
-        ttccs->cs.name = np->name;
-        ttccs->cs.rating = 200;
-        ttccs->cs.read = __xttc_clocksource_read;
-        ttccs->cs.mask = CLOCKSOURCE_MASK(16);
-        ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
-
-        __raw_writel(0x0,  ttccs->xttc.base_addr + XTTCPS_IER_OFFSET);
-        __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
-                     ttccs->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
-        __raw_writel(CNT_CNTRL_RESET,
-                     ttccs->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-
-        err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
-        if (WARN_ON(err))
-                return;
-}
-
-static void __init zynq_ttc_setup_clockevent(struct device_node *np,
-                                            void __iomem *base)
-{
-        struct xttcps_timer_clockevent *ttcce;
-        int err, irq;
-        u32 reg;
-
-        ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
-        if (WARN_ON(!ttcce))
-                return;
-
-        err = of_property_read_u32(np, "reg", &reg);
-        if (WARN_ON(err))
-                return;
-
-        ttcce->xttc.base_addr = base + reg * 4;
-
-        ttcce->clk = of_clk_get_by_name(np, "cpu_1x");
-        if (WARN_ON(IS_ERR(ttcce->clk)))
-                return;
-
-        err = clk_prepare_enable(ttcce->clk);
-        if (WARN_ON(err))
-                return;
-
-        irq = irq_of_parse_and_map(np, 0);
-        if (WARN_ON(!irq))
-                return;
-
-        ttcce->ce.name = np->name;
-        ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
-        ttcce->ce.set_next_event = xttcps_set_next_event;
-        ttcce->ce.set_mode = xttcps_set_mode;
-        ttcce->ce.rating = 200;
-        ttcce->ce.irq = irq;
-        ttcce->ce.cpumask = cpu_possible_mask;
-
-        __raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-        __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
-                     ttcce->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
-        __raw_writel(0x1,  ttcce->xttc.base_addr + XTTCPS_IER_OFFSET);
-
-        err = request_irq(irq, xttcps_clock_event_interrupt, IRQF_TIMER,
-                          np->name, ttcce);
-        if (WARN_ON(err))
-                return;
-
-        clockevents_config_and_register(&ttcce->ce,
-                                        clk_get_rate(ttcce->clk) / PRESCALE,
-                                        1, 0xfffe);
-}
-
-static const __initconst struct of_device_id zynq_ttc_match[] = {
-        { .compatible = "xlnx,ttc-counter-clocksource",
-                .data = zynq_ttc_setup_clocksource, },
-        { .compatible = "xlnx,ttc-counter-clockevent",
-                .data = zynq_ttc_setup_clockevent, },
-        {}
-};
-
-/**
- * xttcps_timer_init - Initialize the timer
- *
- * Initializes the timer hardware and register the clock source and clock event
- * timers with Linux kernal timer framework
- **/
-void __init xttcps_timer_init(void)
-{
-        struct device_node *np;
-
-        for_each_compatible_node(np, NULL, "xlnx,ttc") {
-                struct device_node *np_chld;
-                void __iomem *base;
-
-                base = of_iomap(np, 0);
-                if (WARN_ON(!base))
-                        return;
-
-                for_each_available_child_of_node(np, np_chld) {
-                        int (*cb)(struct device_node *np, void __iomem *base);
-                        const struct of_device_id *match;
-
-                        match = of_match_node(zynq_ttc_match, np_chld);
-                        if (match) {
-                                cb = match->data;
-                                cb(np_chld, base);
-                        }
-                }
-        }
-}
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 4045c4931a30..35955b54944c 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -397,6 +397,13 @@ config CPU_V7
         select CPU_PABRT_V7
         select CPU_TLB_V7 if MMU
 
+config CPU_THUMBONLY
+        bool
+        # There are no CPUs available with MMU that don't implement an ARM ISA:
+        depends on !MMU
+        help
+          Select this if your CPU doesn't support the 32 bit ARM instructions.
+
 # Figure out what processor architecture version we should be using.
 # This defines the compiler instruction set which depends on the machine type.
 config CPU_32v3
@@ -605,7 +612,7 @@ config ARCH_DMA_ADDR_T_64BIT
         bool
 
 config ARM_THUMB
-        bool "Support Thumb user binaries"
+        bool "Support Thumb user binaries" if !CPU_THUMBONLY
         depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
         default y
         help
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index db26e2e543f4..6f4585b89078 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -961,12 +961,14 @@ static int __init alignment_init(void)
                 return -ENOMEM;
 #endif
 
+#ifdef CONFIG_CPU_CP15
         if (cpu_is_v6_unaligned()) {
                 cr_alignment &= ~CR_A;
                 cr_no_alignment &= ~CR_A;
                 set_cr(cr_alignment);
                 ai_usermode = safe_usermode(ai_usermode, false);
         }
+#endif
 
         hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
                         "alignment exception");
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index e9db6b4bf65a..ef3e0f3aac96 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -823,16 +823,17 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset,
                 if (PageHighMem(page)) {
                         if (len + offset > PAGE_SIZE)
                                 len = PAGE_SIZE - offset;
-                        vaddr = kmap_high_get(page);
-                        if (vaddr) {
-                                vaddr += offset;
-                                op(vaddr, len, dir);
-                                kunmap_high(page);
-                        } else if (cache_is_vipt()) {
-                                /* unmapped pages might still be cached */
+
+                        if (cache_is_vipt_nonaliasing()) {
                                 vaddr = kmap_atomic(page);
                                 op(vaddr + offset, len, dir);
                                 kunmap_atomic(vaddr);
+                        } else {
+                                vaddr = kmap_high_get(page);
+                                if (vaddr) {
+                                        op(vaddr + offset, len, dir);
+                                        kunmap_high(page);
+                                }
                         }
                 } else {
                         vaddr = page_address(page) + offset;
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 1c8f7f564175..0d473cce501c 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -170,15 +170,18 @@ void __flush_dcache_page(struct address_space *mapping, struct page *page)
         if (!PageHighMem(page)) {
                 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
         } else {
-                void *addr = kmap_high_get(page);
-                if (addr) {
-                        __cpuc_flush_dcache_area(addr, PAGE_SIZE);
-                        kunmap_high(page);
-                } else if (cache_is_vipt()) {
-                        /* unmapped pages might still be cached */
+                void *addr;
+
+                if (cache_is_vipt_nonaliasing()) {
                         addr = kmap_atomic(page);
                         __cpuc_flush_dcache_area(addr, PAGE_SIZE);
                         kunmap_atomic(addr);
+                } else {
+                        addr = kmap_high_get(page);
+                        if (addr) {
+                                __cpuc_flush_dcache_area(addr, PAGE_SIZE);
+                                kunmap_high(page);
+                        }
                 }
         }
 
diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c
index 5ee505c937d1..83cb3ac27095 100644
--- a/arch/arm/mm/idmap.c
+++ b/arch/arm/mm/idmap.c
@@ -8,7 +8,6 @@
 #include <asm/pgtable.h>
 #include <asm/sections.h>
 #include <asm/system_info.h>
-#include <asm/virt.h>
 
 pgd_t *idmap_pgd;
 
@@ -83,37 +82,10 @@ static void identity_mapping_add(pgd_t *pgd, const char *text_start,
         } while (pgd++, addr = next, addr != end);
 }
 
-#if defined(CONFIG_ARM_VIRT_EXT) && defined(CONFIG_ARM_LPAE)
-pgd_t *hyp_pgd;
-
-extern char  __hyp_idmap_text_start[], __hyp_idmap_text_end[];
-
-static int __init init_static_idmap_hyp(void)
-{
-        hyp_pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
-        if (!hyp_pgd)
-                return -ENOMEM;
-
-        pr_info("Setting up static HYP identity map for 0x%p - 0x%p\n",
-                __hyp_idmap_text_start, __hyp_idmap_text_end);
-        identity_mapping_add(hyp_pgd, __hyp_idmap_text_start,
-                             __hyp_idmap_text_end, PMD_SECT_AP1);
-
-        return 0;
-}
-#else
-static int __init init_static_idmap_hyp(void)
-{
-        return 0;
-}
-#endif
-
 extern char  __idmap_text_start[], __idmap_text_end[];
 
 static int __init init_static_idmap(void)
 {
-        int ret;
-
         idmap_pgd = pgd_alloc(&init_mm);
         if (!idmap_pgd)
                 return -ENOMEM;
@@ -123,12 +95,10 @@ static int __init init_static_idmap(void)
         identity_mapping_add(idmap_pgd, __idmap_text_start,
                              __idmap_text_end, 0);
 
-        ret = init_static_idmap_hyp();
-
         /* Flush L1 for the hardware to see this page table content */
         flush_cache_louis();
 
-        return ret;
+        return 0;
 }
 early_initcall(init_static_idmap);
 
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index ad722f1208a5..9a5cdc01fcdf 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -99,6 +99,9 @@ void show_mem(unsigned int filter)
         printk("Mem-info:\n");
         show_free_areas(filter);
 
+        if (filter & SHOW_MEM_FILTER_PAGE_COUNT)
+                return;
+
         for_each_bank (i, mi) {
                 struct membank *bank = &mi->bank[i];
                 unsigned int pfn1, pfn2;
@@ -424,24 +427,6 @@ void __init bootmem_init(void)
         max_pfn = max_high - PHYS_PFN_OFFSET;
 }
 
-static inline int free_area(unsigned long pfn, unsigned long end, char *s)
-{
-        unsigned int pages = 0, size = (end - pfn) << (PAGE_SHIFT - 10);
-
-        for (; pfn < end; pfn++) {
-                struct page *page = pfn_to_page(pfn);
-                ClearPageReserved(page);
-                init_page_count(page);
-                __free_page(page);
-                pages++;
-        }
-
-        if (size && s)
-                printk(KERN_INFO "Freeing %s memory: %dK\n", s, size);
-
-        return pages;
-}
-
 /*
  * Poison init memory with an undefined instruction (ARM) or a branch to an
  * undefined instruction (Thumb).
@@ -534,6 +519,14 @@ static void __init free_unused_memmap(struct meminfo *mi)
 #endif
 }
 
+#ifdef CONFIG_HIGHMEM
+static inline void free_area_high(unsigned long pfn, unsigned long end)
+{
+        for (; pfn < end; pfn++)
+                free_highmem_page(pfn_to_page(pfn));
+}
+#endif
+
 static void __init free_highpages(void)
 {
 #ifdef CONFIG_HIGHMEM
@@ -569,8 +562,7 @@ static void __init free_highpages(void)
                         if (res_end > end)
                                 res_end = end;
                         if (res_start != start)
-                                totalhigh_pages += free_area(start, res_start,
-                                                             NULL);
+                                free_area_high(start, res_start);
                         start = res_end;
                         if (start == end)
                                 break;
@@ -578,9 +570,8 @@ static void __init free_highpages(void)
 
                 /* And now free anything which remains */
                 if (start < end)
-                        totalhigh_pages += free_area(start, end, NULL);
+                        free_area_high(start, end);
         }
-        totalram_pages += totalhigh_pages;
 #endif
 }
 
@@ -609,8 +600,7 @@ void __init mem_init(void)
 
 #ifdef CONFIG_SA1111
         /* now that our DMA memory is actually so designated, we can free it */
-        totalram_pages += free_area(PHYS_PFN_OFFSET,
-                                    __phys_to_pfn(__pa(swapper_pg_dir)), NULL);
+        free_reserved_area(__va(PHYS_PFN_OFFSET), swapper_pg_dir, 0, NULL);
 #endif
 
         free_highpages();
@@ -738,16 +728,12 @@ void free_initmem(void)
         extern char __tcm_start, __tcm_end;
 
         poison_init_mem(&__tcm_start, &__tcm_end - &__tcm_start);
-        totalram_pages += free_area(__phys_to_pfn(__pa(&__tcm_start)),
-                                    __phys_to_pfn(__pa(&__tcm_end)),
-                                    "TCM link");
+        free_reserved_area(&__tcm_start, &__tcm_end, 0, "TCM link");
 #endif
 
         poison_init_mem(__init_begin, __init_end - __init_begin);
         if (!machine_is_integrator() && !machine_is_cintegrator())
-                totalram_pages += free_area(__phys_to_pfn(__pa(__init_begin)),
-                                            __phys_to_pfn(__pa(__init_end)),
-                                            "init");
+                free_initmem_default(0);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
@@ -758,9 +744,7 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 {
         if (!keep_initrd) {
                 poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
-                totalram_pages += free_area(__phys_to_pfn(__pa(start)),
-                                            __phys_to_pfn(__pa(end)),
-                                            "initrd");
+                free_reserved_area(start, end, 0, "initrd");
         }
 }
 
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index a84ff763ac39..e0d8565671a6 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -113,6 +113,7 @@ static struct cachepolicy cache_policies[] __initdata = {
         }
 };
 
+#ifdef CONFIG_CPU_CP15
 /*
  * These are useful for identifying cache coherency
  * problems by allowing the cache or the cache and
@@ -211,6 +212,22 @@ void adjust_cr(unsigned long mask, unsigned long set)
 }
 #endif
 
+#else /* ifdef CONFIG_CPU_CP15 */
+
+static int __init early_cachepolicy(char *p)
+{
+        pr_warning("cachepolicy kernel parameter not supported without cp15\n");
+}
+early_param("cachepolicy", early_cachepolicy);
+
+static int __init noalign_setup(char *__unused)
+{
+        pr_warning("noalign kernel parameter not supported without cp15\n");
+}
+__setup("noalign", noalign_setup);
+
+#endif /* ifdef CONFIG_CPU_CP15 / else */
+
 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 5c07ee4fe3eb..919405e20b80 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -80,12 +80,10 @@ ENTRY(cpu_v6_do_idle)
         mov     pc, lr
 
 ENTRY(cpu_v6_dcache_clean_area)
-#ifndef TLB_CAN_READ_FROM_L1_CACHE
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         add     r0, r0, #D_CACHE_LINE_SIZE
         subs    r1, r1, #D_CACHE_LINE_SIZE
         bhi     1b
-#endif
         mov     pc, lr
 
 /*
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index 78f520bc0e99..9704097c450e 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -110,7 +110,8 @@ ENTRY(cpu_v7_set_pte_ext)
  ARM(   str     r3, [r0, #2048]! )
  THUMB( add     r0, r0, #2048 )
  THUMB( str     r3, [r0] )
-        mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
+        ALT_SMP(mov     pc,lr)
+        ALT_UP (mcr     p15, 0, r0, c7, c10, 1)         @ flush_pte
 #endif
         mov     pc, lr
 ENDPROC(cpu_v7_set_pte_ext)
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 6ffd78c0f9ab..363027e811d6 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -73,7 +73,8 @@ ENTRY(cpu_v7_set_pte_ext)
         tst     r3, #1 << (55 - 32)             @ L_PTE_DIRTY
         orreq   r2, #L_PTE_RDONLY
 1:      strd    r2, r3, [r0]
-        mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
+        ALT_SMP(mov     pc, lr)
+        ALT_UP (mcr     p15, 0, r0, c7, c10, 1)         @ flush_pte
 #endif
         mov     pc, lr
 ENDPROC(cpu_v7_set_pte_ext)
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index f584d3f5b37c..2c73a7301ff7 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -75,14 +75,14 @@ ENTRY(cpu_v7_do_idle)
 ENDPROC(cpu_v7_do_idle)
 
 ENTRY(cpu_v7_dcache_clean_area)
-#ifndef TLB_CAN_READ_FROM_L1_CACHE
+        ALT_SMP(mov     pc, lr)                 @ MP extensions imply L1 PTW
+        ALT_UP(W(nop))
         dcache_line_size r2, r3
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         add     r0, r0, r2
         subs    r1, r1, r2
         bhi     1b
         dsb
-#endif
         mov     pc, lr
 ENDPROC(cpu_v7_dcache_clean_area)
 
@@ -402,6 +402,8 @@ __v7_ca9mp_proc_info:
         __v7_proc __v7_ca9mp_setup
         .size   __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
 
+#endif  /* CONFIG_ARM_LPAE */
+
         /*
          * Marvell PJ4B processor.
          */
@@ -411,7 +413,6 @@ __v7_pj4b_proc_info:
         .long   0xfffffff0
         __v7_proc __v7_pj4b_setup
         .size   __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
-#endif  /* CONFIG_ARM_LPAE */
 
         /*
          * ARM Ltd. Cortex A7 processor.
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index a0daa2fb5de6..e6dbc8dbe6a6 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -140,8 +140,7 @@ static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
          */
         if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
                 timer->fclk = clk_get(&timer->pdev->dev, "fck");
-                if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) {
-                        timer->fclk = NULL;
+                if (WARN_ON_ONCE(IS_ERR(timer->fclk))) {
                         dev_err(&timer->pdev->dev, ": No fclk handle.\n");
                         return -EINVAL;
                 }
@@ -373,7 +372,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
 
 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 {
-        if (timer)
+        if (timer && !IS_ERR(timer->fclk))
                 return timer->fclk;
         return NULL;
 }
@@ -482,7 +481,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
         if (pdata && pdata->set_timer_src)
                 return pdata->set_timer_src(timer->pdev, source);
 
-        if (!timer->fclk)
+        if (IS_ERR(timer->fclk))
                 return -EINVAL;
 
         switch (source) {
@@ -500,13 +499,13 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
         }
 
         parent = clk_get(&timer->pdev->dev, parent_name);
-        if (IS_ERR_OR_NULL(parent)) {
+        if (IS_ERR(parent)) {
                 pr_err("%s: %s not found\n", __func__, parent_name);
                 return -EINVAL;
         }
 
         ret = clk_set_parent(timer->fclk, parent);
-        if (IS_ERR_VALUE(ret))
+        if (ret < 0)
                 pr_err("%s: failed to set %s as parent\n", __func__,
                         parent_name);
 
@@ -808,6 +807,7 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
                 return  -ENOMEM;
         }
 
+        timer->fclk = ERR_PTR(-ENODEV);
         timer->io_base = devm_ioremap_resource(dev, mem);
         if (IS_ERR(timer->io_base))
                 return PTR_ERR(timer->io_base);
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index a82cecb84948..ad97400ba3ad 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -3,7 +3,11 @@
 #
 ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
 
-obj-y                             += addr-map.o
+obj-$(CONFIG_ARCH_MVEBU)          += addr-map.o
+obj-$(CONFIG_ARCH_KIRKWOOD)       += addr-map.o
+obj-$(CONFIG_ARCH_DOVE)           += addr-map.o
+obj-$(CONFIG_ARCH_ORION5X)        += addr-map.o
+obj-$(CONFIG_ARCH_MV78XX0)        += addr-map.o
 
 orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
 obj-$(CONFIG_PLAT_ORION_LEGACY)   += irq.o pcie.o time.o common.o mpp.o
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index f20a321088a2..8b8c06d2e9c4 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -120,12 +120,14 @@ void __init orion_pcie_reset(void __iomem *base)
  * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
  * WIN[0-3] -> DRAM bank[0-3]
  */
-static void __init orion_pcie_setup_wins(void __iomem *base,
-                                         struct mbus_dram_target_info *dram)
+static void __init orion_pcie_setup_wins(void __iomem *base)
 {
+        const struct mbus_dram_target_info *dram;
         u32 size;
         int i;
 
+        dram = mv_mbus_dram_info();
+
         /*
          * First, disable and clear BARs and windows.
          */
@@ -150,7 +152,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base,
          */
         size = 0;
         for (i = 0; i < dram->num_cs; i++) {
-                struct mbus_dram_window *cs = dram->cs + i;
+                const struct mbus_dram_window *cs = dram->cs + i;
 
                 writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));
                 writel(0, base + PCIE_WIN04_REMAP_OFF(i));
@@ -184,7 +186,7 @@ void __init orion_pcie_setup(void __iomem *base)
         /*
          * Point PCIe unit MBUS decode windows to DRAM space.
          */
-        orion_pcie_setup_wins(base, &orion_mbus_dram_info);
+        orion_pcie_setup_wins(base);
 
         /*
          * Master + slave enable.
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index a9d52167e16e..54d186106f9f 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -25,7 +25,7 @@ config PLAT_S5P
         select PLAT_SAMSUNG
         select S3C_GPIO_TRACK
         select S5P_GPIO_DRVSTR
-        select SAMSUNG_CLKSRC
+        select SAMSUNG_CLKSRC if !COMMON_CLK
         select SAMSUNG_GPIOLIB_4BIT
         select SAMSUNG_IRQ_VIC_TIMER
         help
@@ -37,14 +37,6 @@ if PLAT_SAMSUNG
 
 comment "Boot options"
 
-config S3C_BOOT_WATCHDOG
-        bool "S3C Initialisation watchdog"
-        depends on S3C2410_WATCHDOG
-        help
-          Say y to enable the watchdog during the kernel decompression
-          stage. If the kernel fails to uncompress, then the watchdog
-          will trigger a reset and the system should restart.
-
 config S3C_BOOT_ERROR_RESET
         bool "S3C Reboot on decompression error"
         help
@@ -70,7 +62,7 @@ config S3C_LOWLEVEL_UART_PORT
 
 # timer options
 
-config S5P_HRT
+config SAMSUNG_HRT
         bool
         select SAMSUNG_DEV_PWM
         help
@@ -89,7 +81,7 @@ config SAMSUNG_CLKSRC
           used by newer systems such as the S3C64XX.
 
 config S5P_CLOCK
-        def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
+        def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
         help
           Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
 
@@ -125,12 +117,6 @@ config SAMSUNG_GPIOLIB_4BIT
           configuration. GPIOlib shall be compiled only for S3C64XX and S5P
           series of processors.
 
-config S3C_GPIO_CFG_S3C64XX
-        bool
-        help
-          Internal configuration to enable S3C64XX style GPIO configuration
-          functions.
-
 config S5P_GPIO_DRVSTR
         bool
         help
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 3a7c64d1814a..a23c460299a1 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -12,8 +12,7 @@ obj-				:=
 # Objects we always build independent of SoC choice
 
 obj-y                           += init.o cpu.o
-obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET)   += time.o
-obj-$(CONFIG_S5P_HRT)           += s5p-time.o
+obj-$(CONFIG_SAMSUNG_HRT)       += samsung-time.o
 
 obj-$(CONFIG_SAMSUNG_CLOCK)     += clock.o
 obj-$(CONFIG_SAMSUNG_CLOCK)     += pwm-clock.o
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 51afedda9ab6..30c2fe243f76 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -10,6 +10,7 @@
  * published by the Free Software Foundation.
 */
 
+#include <linux/amba/pl330.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/interrupt.h>
@@ -62,7 +63,6 @@
 #include <linux/platform_data/usb-s3c2410_udc.h>
 #include <linux/platform_data/usb-ohci-s3c2410.h>
 #include <plat/usb-phy.h>
-#include <plat/regs-iic.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-spi.h>
 #include <linux/platform_data/spi-s3c64xx.h>
@@ -146,14 +146,20 @@ struct platform_device s3c_device_camif = {
 
 /* ASOC DMA */
 
+#ifdef CONFIG_PLAT_S5P 
+static struct resource samsung_asoc_idma_resource = DEFINE_RES_IRQ(IRQ_I2S0);
+
 struct platform_device samsung_asoc_idma = {
         .name           = "samsung-idma",
         .id             = -1,
+        .num_resources  = 1,
+        .resource       = &samsung_asoc_idma_resource,
         .dev            = {
                 .dma_mask               = &samsung_device_dma_mask,
                 .coherent_dma_mask      = DMA_BIT_MASK(32),
         }
 };
+#endif
 
 /* FB */
 
@@ -878,51 +884,6 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
 }
 #endif /* CONFIG_PLAT_S3C24XX */
 
-/* MFC */
-
-#ifdef CONFIG_S5P_DEV_MFC
-static struct resource s5p_mfc_resource[] = {
-        [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
-        [1] = DEFINE_RES_IRQ(IRQ_MFC),
-};
-
-struct platform_device s5p_device_mfc = {
-        .name           = "s5p-mfc",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(s5p_mfc_resource),
-        .resource       = s5p_mfc_resource,
-};
-
-/*
- * MFC hardware has 2 memory interfaces which are modelled as two separate
- * platform devices to let dma-mapping distinguish between them.
- *
- * MFC parent device (s5p_device_mfc) must be registered before memory
- * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
- */
-
-struct platform_device s5p_device_mfc_l = {
-        .name           = "s5p-mfc-l",
-        .id             = -1,
-        .dev            = {
-                .parent                 = &s5p_device_mfc.dev,
-                .dma_mask               = &samsung_device_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-
-struct platform_device s5p_device_mfc_r = {
-        .name           = "s5p-mfc-r",
-        .id             = -1,
-        .dev            = {
-                .parent                 = &s5p_device_mfc.dev,
-                .dma_mask               = &samsung_device_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-
-#endif /* CONFIG_S5P_DEV_MFC */
-
 /* MIPI CSIS */
 
 #ifdef CONFIG_S5P_DEV_CSIS0
@@ -1113,7 +1074,7 @@ struct platform_device s5p_device_onenand = {
 
 /* PMU */
 
-#ifdef CONFIG_PLAT_S5P
+#if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS)
 static struct resource s5p_pmu_resource[] = {
         DEFINE_RES_IRQ(IRQ_PMU)
 };
@@ -1552,6 +1513,9 @@ void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
         pd.num_cs = num_cs;
         pd.src_clk_nr = src_clk_nr;
         pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
+#ifdef CONFIG_PL330_DMA
+        pd.filter = pl330_filter;
+#endif
 
         s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0);
 }
@@ -1590,6 +1554,9 @@ void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
         pd.num_cs = num_cs;
         pd.src_clk_nr = src_clk_nr;
         pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio;
+#ifdef CONFIG_PL330_DMA
+        pd.filter = pl330_filter;
+#endif
 
         s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1);
 }
@@ -1628,6 +1595,9 @@ void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
         pd.num_cs = num_cs;
         pd.src_clk_nr = src_clk_nr;
         pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio;
+#ifdef CONFIG_PL330_DMA
+        pd.filter = pl330_filter;
+#endif
 
         s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2);
 }
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
index 71d58ddea9c1..ec0d731b0e7b 100644
--- a/arch/arm/plat-samsung/dma-ops.c
+++ b/arch/arm/plat-samsung/dma-ops.c
@@ -23,23 +23,15 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
                                 struct device *dev, char *ch_name)
 {
         dma_cap_mask_t mask;
-        void *filter_param;
 
         dma_cap_zero(mask);
         dma_cap_set(param->cap, mask);
 
-        /*
-         * If a dma channel property of a device node from device tree is
-         * specified, use that as the fliter parameter.
-         */
-        filter_param = (dma_ch == DMACH_DT_PROP) ?
-                (void *)param->dt_dmach_prop : (void *)dma_ch;
-
         if (dev->of_node)
                 return (unsigned)dma_request_slave_channel(dev, ch_name);
         else
                 return (unsigned)dma_request_channel(mask, pl330_filter,
-                                                        filter_param);
+                                                        (void *)dma_ch);
 }
 
 static int samsung_dmadev_release(unsigned ch, void *param)
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 37703ef6dfc7..989fefe18be6 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -23,6 +23,9 @@ extern unsigned long samsung_cpu_id;
 #define S3C24XX_CPU_ID          0x32400000
 #define S3C24XX_CPU_MASK        0xFFF00000
 
+#define S3C2412_CPU_ID          0x32412000
+#define S3C2412_CPU_MASK        0xFFFFF000
+
 #define S3C6400_CPU_ID          0x36400000
 #define S3C6410_CPU_ID          0x36410000
 #define S3C64XX_CPU_MASK        0xFFFFF000
@@ -53,6 +56,7 @@ static inline int is_samsung_##name(void)	\
 }
 
 IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
+IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK)
 IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
@@ -74,6 +78,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_s3c24xx()       0
 #endif
 
+#if defined(CONFIG_CPU_S3C2412)
+# define soc_is_s3c2412()       is_samsung_s3c2412()
+#else
+# define soc_is_s3c2412()       0
+#endif
+
 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
 # define soc_is_s3c64xx()       (is_samsung_s3c6400() || is_samsung_s3c6410())
 #else
@@ -173,7 +183,6 @@ extern void s3c_init_cpu(unsigned long idcode,
 
 /* core initialisation functions */
 
-extern void s3c24xx_init_irq(void);
 extern void s5p_init_irq(u32 *vic, u32 num_vic);
 
 extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
@@ -192,10 +201,6 @@ extern void s3c24xx_init_uartdevs(char *name,
                                   struct s3c24xx_uart_resources *res,
                                   struct s3c2410_uartcfg *cfg, int no);
 
-/* timer for 2410/2440 */
-
-extern void s3c24xx_timer_init(void);
-
 extern struct syscore_ops s3c2410_pm_syscore_ops;
 extern struct syscore_ops s3c2412_pm_syscore_ops;
 extern struct syscore_ops s3c2416_pm_syscore_ops;
diff --git a/arch/arm/plat-samsung/include/plat/dma-ops.h b/arch/arm/plat-samsung/include/plat/dma-ops.h
index 114178268b75..ce6d7634b6cb 100644
--- a/arch/arm/plat-samsung/include/plat/dma-ops.h
+++ b/arch/arm/plat-samsung/include/plat/dma-ops.h
@@ -18,7 +18,6 @@
 
 struct samsung_dma_req {
         enum dma_transaction_type cap;
-        struct property *dt_dmach_prop;
         struct s3c2410_dma_client *client;
 };
 
diff --git a/arch/arm/plat-samsung/include/plat/dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h
index d384a8016b47..abe07fae71db 100644
--- a/arch/arm/plat-samsung/include/plat/dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/dma-pl330.h
@@ -21,7 +21,6 @@
  * use these just as IDs.
  */
 enum dma_ch {
-        DMACH_DT_PROP = -1,
         DMACH_UART0_RX = 0,
         DMACH_UART0_TX,
         DMACH_UART1_RX,
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index b885322717a1..9ae507270785 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -15,55 +15,7 @@
 #ifndef __PLAT_S3C_FB_H
 #define __PLAT_S3C_FB_H __FILE__
 
-/* S3C_FB_MAX_WIN
- * Set to the maximum number of windows that any of the supported hardware
- * can use. Since the platform data uses this for an array size, having it
- * set to the maximum of any version of the hardware can do is safe.
- */
-#define S3C_FB_MAX_WIN  (5)
-
-/**
- * struct s3c_fb_pd_win - per window setup data
- * @xres     : The window X size.
- * @yres     : The window Y size.
- * @virtual_x: The virtual X size.
- * @virtual_y: The virtual Y size.
- */
-struct s3c_fb_pd_win {
-        unsigned short          default_bpp;
-        unsigned short          max_bpp;
-        unsigned short          xres;
-        unsigned short          yres;
-        unsigned short          virtual_x;
-        unsigned short          virtual_y;
-};
-
-/**
- * struct s3c_fb_platdata -  S3C driver platform specific information
- * @setup_gpio: Setup the external GPIO pins to the right state to transfer
- *              the data from the display system to the connected display
- *              device.
- * @vidcon0: The base vidcon0 values to control the panel data format.
- * @vidcon1: The base vidcon1 values to control the panel data output.
- * @vtiming: Video timing when connected to a RGB type panel.
- * @win: The setup data for each hardware window, or NULL for unused.
- * @display_mode: The LCD output display mode.
- *
- * The platform data supplies the video driver with all the information
- * it requires to work with the display(s) attached to the machine. It
- * controls the initial mode, the number of display windows (0 is always
- * the base framebuffer) that are initialised etc.
- *
- */
-struct s3c_fb_platdata {
-        void    (*setup_gpio)(void);
-
-        struct s3c_fb_pd_win    *win[S3C_FB_MAX_WIN];
-        struct fb_videomode     *vtiming;
-
-        u32                      vidcon0;
-        u32                      vidcon1;
-};
+#include <linux/platform_data/video_s3c.h>
 
 /**
  * s3c_fb_set_platdata() - Setup the FB device with platform data.
diff --git a/arch/arm/plat-samsung/include/plat/irq.h b/arch/arm/plat-samsung/include/plat/irq.h
deleted file mode 100644
index e21a89bc26c9..000000000000
--- a/arch/arm/plat-samsung/include/plat/irq.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/irq.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C24XX CPU IRQ support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#define irqdbf(x...)
-#define irqdbf2(x...)
-
-#define EXTINT_OFF (IRQ_EINT4 - 4)
-
-/* these are exported for arch/arm/mach-* usage */
-extern struct irq_chip s3c_irq_level_chip;
-extern struct irq_chip s3c_irq_chip;
-
-static inline void s3c_irqsub_mask(unsigned int irqno,
-                                   unsigned int parentbit,
-                                   int subcheck)
-{
-        unsigned long mask;
-        unsigned long submask;
-
-        submask = __raw_readl(S3C2410_INTSUBMSK);
-        mask = __raw_readl(S3C2410_INTMSK);
-
-        submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
-
-        /* check to see if we need to mask the parent IRQ */
-
-        if ((submask  & subcheck) == subcheck)
-                __raw_writel(mask | parentbit, S3C2410_INTMSK);
-
-        /* write back masks */
-        __raw_writel(submask, S3C2410_INTSUBMSK);
-
-}
-
-static inline void s3c_irqsub_unmask(unsigned int irqno,
-                                     unsigned int parentbit)
-{
-        unsigned long mask;
-        unsigned long submask;
-
-        submask = __raw_readl(S3C2410_INTSUBMSK);
-        mask = __raw_readl(S3C2410_INTMSK);
-
-        submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
-        mask &= ~parentbit;
-
-        /* write back masks */
-        __raw_writel(submask, S3C2410_INTSUBMSK);
-        __raw_writel(mask, S3C2410_INTMSK);
-}
-
-
-static inline void s3c_irqsub_maskack(unsigned int irqno,
-                                      unsigned int parentmask,
-                                      unsigned int group)
-{
-        unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
-
-        s3c_irqsub_mask(irqno, parentmask, group);
-
-        __raw_writel(bit, S3C2410_SUBSRCPND);
-
-        /* only ack parent if we've got all the irqs (seems we must
-         * ack, all and hope that the irq system retriggers ok when
-         * the interrupt goes off again)
-         */
-
-        if (1) {
-                __raw_writel(parentmask, S3C2410_SRCPND);
-                __raw_writel(parentmask, S3C2410_INTPND);
-        }
-}
-
-static inline void s3c_irqsub_ack(unsigned int irqno,
-                                  unsigned int parentmask,
-                                  unsigned int group)
-{
-        unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
-
-        __raw_writel(bit, S3C2410_SUBSRCPND);
-
-        /* only ack parent if we've got all the irqs (seems we must
-         * ack, all and hope that the irq system retriggers ok when
-         * the interrupt goes off again)
-         */
-
-        if (1) {
-                __raw_writel(parentmask, S3C2410_SRCPND);
-                __raw_writel(parentmask, S3C2410_INTPND);
-        }
-}
-
-/* exported for use in arch/arm/mach-s3c2410 */
-
-#ifdef CONFIG_PM
-extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
-#else
-#define s3c_irq_wake NULL
-#endif
-
-extern int s3c_irqext_type(struct irq_data *d, unsigned int type);
diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/plat-samsung/include/plat/map-s5p.h
index c2d7bdae5891..c18678610bc0 100644
--- a/arch/arm/plat-samsung/include/plat/map-s5p.h
+++ b/arch/arm/plat-samsung/include/plat/map-s5p.h
@@ -22,6 +22,7 @@
 #define S5P_VA_GPIO3            S3C_ADDR(0x02280000)
 
 #define S5P_VA_SYSRAM           S3C_ADDR(0x02400000)
+#define S5P_VA_SYSRAM_NS        S3C_ADDR(0x02410000)
 #define S5P_VA_DMC0             S3C_ADDR(0x02440000)
 #define S5P_VA_DMC1             S3C_ADDR(0x02480000)
 #define S5P_VA_SROMC            S3C_ADDR(0x024C0000)
diff --git a/arch/arm/plat-samsung/include/plat/regs-ac97.h b/arch/arm/plat-samsung/include/plat/regs-ac97.h
deleted file mode 100644
index c3878f7acb83..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-ac97.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-ac97.h
- *
- * Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
- *              http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2440 AC97 Controller
-*/
-
-#ifndef __ASM_ARCH_REGS_AC97_H
-#define __ASM_ARCH_REGS_AC97_H __FILE__
-
-#define S3C_AC97_GLBCTRL                                (0x00)
-
-#define S3C_AC97_GLBCTRL_CODECREADYIE                   (1<<22)
-#define S3C_AC97_GLBCTRL_PCMOUTURIE                     (1<<21)
-#define S3C_AC97_GLBCTRL_PCMINORIE                      (1<<20)
-#define S3C_AC97_GLBCTRL_MICINORIE                      (1<<19)
-#define S3C_AC97_GLBCTRL_PCMOUTTIE                      (1<<18)
-#define S3C_AC97_GLBCTRL_PCMINTIE                       (1<<17)
-#define S3C_AC97_GLBCTRL_MICINTIE                       (1<<16)
-#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF                   (0<<12)
-#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO                   (1<<12)
-#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA                   (2<<12)
-#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK                  (3<<12)
-#define S3C_AC97_GLBCTRL_PCMINTM_OFF                    (0<<10)
-#define S3C_AC97_GLBCTRL_PCMINTM_PIO                    (1<<10)
-#define S3C_AC97_GLBCTRL_PCMINTM_DMA                    (2<<10)
-#define S3C_AC97_GLBCTRL_PCMINTM_MASK                   (3<<10)
-#define S3C_AC97_GLBCTRL_MICINTM_OFF                    (0<<8)
-#define S3C_AC97_GLBCTRL_MICINTM_PIO                    (1<<8)
-#define S3C_AC97_GLBCTRL_MICINTM_DMA                    (2<<8)
-#define S3C_AC97_GLBCTRL_MICINTM_MASK                   (3<<8)
-#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE             (1<<3)
-#define S3C_AC97_GLBCTRL_ACLINKON                       (1<<2)
-#define S3C_AC97_GLBCTRL_WARMRESET                      (1<<1)
-#define S3C_AC97_GLBCTRL_COLDRESET                      (1<<0)
-
-#define S3C_AC97_GLBSTAT                                (0x04)
-
-#define S3C_AC97_GLBSTAT_CODECREADY                     (1<<22)
-#define S3C_AC97_GLBSTAT_PCMOUTUR                       (1<<21)
-#define S3C_AC97_GLBSTAT_PCMINORI                       (1<<20)
-#define S3C_AC97_GLBSTAT_MICINORI                       (1<<19)
-#define S3C_AC97_GLBSTAT_PCMOUTTI                       (1<<18)
-#define S3C_AC97_GLBSTAT_PCMINTI                        (1<<17)
-#define S3C_AC97_GLBSTAT_MICINTI                        (1<<16)
-#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE                 (0<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_INIT                 (1<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_READY                (2<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE               (3<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_LP                   (4<<0)
-#define S3C_AC97_GLBSTAT_MAINSTATE_WARM                 (5<<0)
-
-#define S3C_AC97_CODEC_CMD                              (0x08)
-
-#define S3C_AC97_CODEC_CMD_READ                         (1<<23)
-
-#define S3C_AC97_STAT                                   (0x0c)
-#define S3C_AC97_PCM_ADDR                               (0x10)
-#define S3C_AC97_PCM_DATA                               (0x18)
-#define S3C_AC97_MIC_DATA                               (0x1C)
-
-#endif /* __ASM_ARCH_REGS_AC97_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-iic.h b/arch/arm/plat-samsung/include/plat/regs-iic.h
deleted file mode 100644
index 2f7c17de8ac8..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-iic.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-iic.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *              http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 I2C Controller
-*/
-
-#ifndef __ASM_ARCH_REGS_IIC_H
-#define __ASM_ARCH_REGS_IIC_H __FILE__
-
-/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
-
-#define S3C2410_IICREG(x) (x)
-
-#define S3C2410_IICCON    S3C2410_IICREG(0x00)
-#define S3C2410_IICSTAT   S3C2410_IICREG(0x04)
-#define S3C2410_IICADD    S3C2410_IICREG(0x08)
-#define S3C2410_IICDS     S3C2410_IICREG(0x0C)
-#define S3C2440_IICLC     S3C2410_IICREG(0x10)
-
-#define S3C2410_IICCON_ACKEN            (1<<7)
-#define S3C2410_IICCON_TXDIV_16         (0<<6)
-#define S3C2410_IICCON_TXDIV_512        (1<<6)
-#define S3C2410_IICCON_IRQEN            (1<<5)
-#define S3C2410_IICCON_IRQPEND          (1<<4)
-#define S3C2410_IICCON_SCALE(x)         ((x)&15)
-#define S3C2410_IICCON_SCALEMASK        (0xf)
-
-#define S3C2410_IICSTAT_MASTER_RX       (2<<6)
-#define S3C2410_IICSTAT_MASTER_TX       (3<<6)
-#define S3C2410_IICSTAT_SLAVE_RX        (0<<6)
-#define S3C2410_IICSTAT_SLAVE_TX        (1<<6)
-#define S3C2410_IICSTAT_MODEMASK        (3<<6)
-
-#define S3C2410_IICSTAT_START           (1<<5)
-#define S3C2410_IICSTAT_BUSBUSY         (1<<5)
-#define S3C2410_IICSTAT_TXRXEN          (1<<4)
-#define S3C2410_IICSTAT_ARBITR          (1<<3)
-#define S3C2410_IICSTAT_ASSLAVE         (1<<2)
-#define S3C2410_IICSTAT_ADDR0           (1<<1)
-#define S3C2410_IICSTAT_LASTBIT         (1<<0)
-
-#define S3C2410_IICLC_SDA_DELAY0        (0 << 0)
-#define S3C2410_IICLC_SDA_DELAY5        (1 << 0)
-#define S3C2410_IICLC_SDA_DELAY10       (2 << 0)
-#define S3C2410_IICLC_SDA_DELAY15       (3 << 0)
-#define S3C2410_IICLC_SDA_DELAY_MASK    (3 << 0)
-
-#define S3C2410_IICLC_FILTER_ON         (1<<2)
-
-#endif /* __ASM_ARCH_REGS_IIC_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-iis.h b/arch/arm/plat-samsung/include/plat/regs-iis.h
deleted file mode 100644
index a18d35e7a735..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-iis.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* arch/arm/plat-samsung/include/plat/regs-iis.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 IIS register definition
-*/
-
-#ifndef __ASM_ARCH_REGS_IIS_H
-#define __ASM_ARCH_REGS_IIS_H
-
-#define S3C2410_IISCON                  (0x00)
-
-#define S3C2410_IISCON_LRINDEX          (1 << 8)
-#define S3C2410_IISCON_TXFIFORDY        (1 << 7)
-#define S3C2410_IISCON_RXFIFORDY        (1 << 6)
-#define S3C2410_IISCON_TXDMAEN          (1 << 5)
-#define S3C2410_IISCON_RXDMAEN          (1 << 4)
-#define S3C2410_IISCON_TXIDLE           (1 << 3)
-#define S3C2410_IISCON_RXIDLE           (1 << 2)
-#define S3C2410_IISCON_PSCEN            (1 << 1)
-#define S3C2410_IISCON_IISEN            (1 << 0)
-
-#define S3C2410_IISMOD                  (0x04)
-
-#define S3C2440_IISMOD_MPLL             (1 << 9)
-#define S3C2410_IISMOD_SLAVE            (1 << 8)
-#define S3C2410_IISMOD_NOXFER           (0 << 6)
-#define S3C2410_IISMOD_RXMODE           (1 << 6)
-#define S3C2410_IISMOD_TXMODE           (2 << 6)
-#define S3C2410_IISMOD_TXRXMODE         (3 << 6)
-#define S3C2410_IISMOD_LR_LLOW          (0 << 5)
-#define S3C2410_IISMOD_LR_RLOW          (1 << 5)
-#define S3C2410_IISMOD_IIS              (0 << 4)
-#define S3C2410_IISMOD_MSB              (1 << 4)
-#define S3C2410_IISMOD_8BIT             (0 << 3)
-#define S3C2410_IISMOD_16BIT            (1 << 3)
-#define S3C2410_IISMOD_BITMASK          (1 << 3)
-#define S3C2410_IISMOD_256FS            (0 << 2)
-#define S3C2410_IISMOD_384FS            (1 << 2)
-#define S3C2410_IISMOD_16FS             (0 << 0)
-#define S3C2410_IISMOD_32FS             (1 << 0)
-#define S3C2410_IISMOD_48FS             (2 << 0)
-#define S3C2410_IISMOD_FS_MASK          (3 << 0)
-
-#define S3C2410_IISPSR                  (0x08)
-
-#define S3C2410_IISPSR_INTMASK          (31 << 5)
-#define S3C2410_IISPSR_INTSHIFT         (5)
-#define S3C2410_IISPSR_EXTMASK          (31 << 0)
-#define S3C2410_IISPSR_EXTSHFIT         (0)
-
-#define S3C2410_IISFCON                 (0x0c)
-
-#define S3C2410_IISFCON_TXDMA           (1 << 15)
-#define S3C2410_IISFCON_RXDMA           (1 << 14)
-#define S3C2410_IISFCON_TXENABLE        (1 << 13)
-#define S3C2410_IISFCON_RXENABLE        (1 << 12)
-#define S3C2410_IISFCON_TXMASK          (0x3f << 6)
-#define S3C2410_IISFCON_TXSHIFT         (6)
-#define S3C2410_IISFCON_RXMASK          (0x3f)
-#define S3C2410_IISFCON_RXSHIFT         (0)
-
-#define S3C2410_IISFIFO                 (0x10)
-
-#endif /* __ASM_ARCH_REGS_IIS_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-onenand.h b/arch/arm/plat-samsung/include/plat/regs-onenand.h
deleted file mode 100644
index 930ea8b88ed3..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-onenand.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * linux/arch/arm/plat-s3c/include/plat/regs-onenand.h
- *
- *  Copyright (C) 2008-2010 Samsung Electronics
- *  Kyungmin Park <kyungmin.park@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __SAMSUNG_ONENAND_H__
-#define __SAMSUNG_ONENAND_H__
-
-#include <mach/hardware.h>
-
-/*
- * OneNAND Controller
- */
-#define MEM_CFG_OFFSET          0x0000
-#define BURST_LEN_OFFSET        0x0010
-#define MEM_RESET_OFFSET        0x0020
-#define INT_ERR_STAT_OFFSET     0x0030
-#define INT_ERR_MASK_OFFSET     0x0040
-#define INT_ERR_ACK_OFFSET      0x0050
-#define ECC_ERR_STAT_OFFSET     0x0060
-#define MANUFACT_ID_OFFSET      0x0070
-#define DEVICE_ID_OFFSET        0x0080
-#define DATA_BUF_SIZE_OFFSET    0x0090
-#define BOOT_BUF_SIZE_OFFSET    0x00A0
-#define BUF_AMOUNT_OFFSET       0x00B0
-#define TECH_OFFSET             0x00C0
-#define FBA_WIDTH_OFFSET        0x00D0
-#define FPA_WIDTH_OFFSET        0x00E0
-#define FSA_WIDTH_OFFSET        0x00F0
-#define TRANS_SPARE_OFFSET      0x0140
-#define DBS_DFS_WIDTH_OFFSET    0x0160
-#define INT_PIN_ENABLE_OFFSET   0x01A0
-#define ACC_CLOCK_OFFSET        0x01C0
-#define FLASH_VER_ID_OFFSET     0x01F0
-#define FLASH_AUX_CNTRL_OFFSET  0x0300          /* s3c64xx only */
-
-#define ONENAND_MEM_RESET_HOT   0x3
-#define ONENAND_MEM_RESET_COLD  0x2
-#define ONENAND_MEM_RESET_WARM  0x1
-
-#define CACHE_OP_ERR            (1 << 13)
-#define RST_CMP                 (1 << 12)
-#define RDY_ACT                 (1 << 11)
-#define INT_ACT                 (1 << 10)
-#define UNSUP_CMD               (1 << 9)
-#define LOCKED_BLK              (1 << 8)
-#define BLK_RW_CMP              (1 << 7)
-#define ERS_CMP                 (1 << 6)
-#define PGM_CMP                 (1 << 5)
-#define LOAD_CMP                (1 << 4)
-#define ERS_FAIL                (1 << 3)
-#define PGM_FAIL                (1 << 2)
-#define INT_TO                  (1 << 1)
-#define LD_FAIL_ECC_ERR         (1 << 0)
-
-#define TSRF                    (1 << 0)
-
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/regs-rtc.h b/arch/arm/plat-samsung/include/plat/regs-rtc.h
deleted file mode 100644
index 0f8263e93eea..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-rtc.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-rtc.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Internal RTC register definition
-*/
-
-#ifndef __ASM_ARCH_REGS_RTC_H
-#define __ASM_ARCH_REGS_RTC_H __FILE__
-
-#define S3C2410_RTCREG(x) (x)
-#define S3C2410_INTP            S3C2410_RTCREG(0x30)
-#define S3C2410_INTP_ALM        (1 << 1)
-#define S3C2410_INTP_TIC        (1 << 0)
-
-#define S3C2410_RTCCON          S3C2410_RTCREG(0x40)
-#define S3C2410_RTCCON_RTCEN    (1 << 0)
-#define S3C2410_RTCCON_CNTSEL   (1 << 2)
-#define S3C2410_RTCCON_CLKRST   (1 << 3)
-#define S3C2443_RTCCON_TICSEL   (1 << 4)
-#define S3C64XX_RTCCON_TICEN    (1 << 8)
-
-#define S3C2410_TICNT           S3C2410_RTCREG(0x44)
-#define S3C2410_TICNT_ENABLE    (1 << 7)
-
-/* S3C2443: tick count is 15 bit wide
- * TICNT[6:0] contains upper 7 bits
- * TICNT1[7:0] contains lower 8 bits
- */
-#define S3C2443_TICNT_PART(x)   ((x & 0x7f00) >> 8)
-#define S3C2443_TICNT1          S3C2410_RTCREG(0x4C)
-#define S3C2443_TICNT1_PART(x)  (x & 0xff)
-
-/* S3C2416: tick count is 32 bit wide
- * TICNT[6:0] contains bits [14:8]
- * TICNT1[7:0] contains lower 8 bits
- * TICNT2[16:0] contains upper 17 bits
- */
-#define S3C2416_TICNT2          S3C2410_RTCREG(0x48)
-#define S3C2416_TICNT2_PART(x)  ((x & 0xffff8000) >> 15)
-
-#define S3C2410_RTCALM          S3C2410_RTCREG(0x50)
-#define S3C2410_RTCALM_ALMEN    (1 << 6)
-#define S3C2410_RTCALM_YEAREN   (1 << 5)
-#define S3C2410_RTCALM_MONEN    (1 << 4)
-#define S3C2410_RTCALM_DAYEN    (1 << 3)
-#define S3C2410_RTCALM_HOUREN   (1 << 2)
-#define S3C2410_RTCALM_MINEN    (1 << 1)
-#define S3C2410_RTCALM_SECEN    (1 << 0)
-
-#define S3C2410_ALMSEC          S3C2410_RTCREG(0x54)
-#define S3C2410_ALMMIN          S3C2410_RTCREG(0x58)
-#define S3C2410_ALMHOUR         S3C2410_RTCREG(0x5c)
-
-#define S3C2410_ALMDATE         S3C2410_RTCREG(0x60)
-#define S3C2410_ALMMON          S3C2410_RTCREG(0x64)
-#define S3C2410_ALMYEAR         S3C2410_RTCREG(0x68)
-
-#define S3C2410_RTCSEC          S3C2410_RTCREG(0x70)
-#define S3C2410_RTCMIN          S3C2410_RTCREG(0x74)
-#define S3C2410_RTCHOUR         S3C2410_RTCREG(0x78)
-#define S3C2410_RTCDATE         S3C2410_RTCREG(0x7c)
-#define S3C2410_RTCMON          S3C2410_RTCREG(0x84)
-#define S3C2410_RTCYEAR         S3C2410_RTCREG(0x88)
-
-#endif /* __ASM_ARCH_REGS_RTC_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-sdhci.h b/arch/arm/plat-samsung/include/plat/regs-sdhci.h
deleted file mode 100644
index e34049ad44cc..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-sdhci.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* linux/arch/arm/plat-s3c/include/plat/regs-sdhci.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C Platform - SDHCI (HSMMC) register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __PLAT_S3C_SDHCI_REGS_H
-#define __PLAT_S3C_SDHCI_REGS_H __FILE__
-
-#define S3C_SDHCI_CONTROL2                      (0x80)
-#define S3C_SDHCI_CONTROL3                      (0x84)
-#define S3C64XX_SDHCI_CONTROL4                  (0x8C)
-
-#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR       (1 << 31)
-#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK         (1 << 30)
-#define S3C_SDHCI_CTRL2_CDINVRXD3               (1 << 29)
-#define S3C_SDHCI_CTRL2_SLCARDOUT               (1 << 28)
-
-#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK          (0xf << 24)
-#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT         (24)
-#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x)           ((_x) << 24)
-
-#define S3C_SDHCI_CTRL2_LVLDAT_MASK             (0xff << 16)
-#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT            (16)
-#define S3C_SDHCI_CTRL2_LVLDAT(_x)              ((_x) << 16)
-
-#define S3C_SDHCI_CTRL2_ENFBCLKTX               (1 << 15)
-#define S3C_SDHCI_CTRL2_ENFBCLKRX               (1 << 14)
-#define S3C_SDHCI_CTRL2_SDCDSEL                 (1 << 13)
-#define S3C_SDHCI_CTRL2_SDSIGPC                 (1 << 12)
-#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART        (1 << 11)
-
-#define S3C_SDHCI_CTRL2_DFCNT_MASK              (0x3 << 9)
-#define S3C_SDHCI_CTRL2_DFCNT_SHIFT             (9)
-#define S3C_SDHCI_CTRL2_DFCNT_NONE              (0x0 << 9)
-#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK            (0x1 << 9)
-#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK           (0x2 << 9)
-#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK           (0x3 << 9)
-
-#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD            (1 << 8)
-#define S3C_SDHCI_CTRL2_RWAITMODE               (1 << 7)
-#define S3C_SDHCI_CTRL2_DISBUFRD                (1 << 6)
-#define S3C_SDHCI_CTRL2_SELBASECLK_MASK         (0x3 << 4)
-#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT        (4)
-#define S3C_SDHCI_CTRL2_PWRSYNC                 (1 << 3)
-#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON          (1 << 1)
-#define S3C_SDHCI_CTRL2_HWINITFIN               (1 << 0)
-
-#define S3C_SDHCI_CTRL3_FCSEL3                  (1 << 31)
-#define S3C_SDHCI_CTRL3_FCSEL2                  (1 << 23)
-#define S3C_SDHCI_CTRL3_FCSEL1                  (1 << 15)
-#define S3C_SDHCI_CTRL3_FCSEL0                  (1 << 7)
-
-#define S3C_SDHCI_CTRL3_FIA3_MASK               (0x7f << 24)
-#define S3C_SDHCI_CTRL3_FIA3_SHIFT              (24)
-#define S3C_SDHCI_CTRL3_FIA3(_x)                ((_x) << 24)
-
-#define S3C_SDHCI_CTRL3_FIA2_MASK               (0x7f << 16)
-#define S3C_SDHCI_CTRL3_FIA2_SHIFT              (16)
-#define S3C_SDHCI_CTRL3_FIA2(_x)                ((_x) << 16)
-
-#define S3C_SDHCI_CTRL3_FIA1_MASK               (0x7f << 8)
-#define S3C_SDHCI_CTRL3_FIA1_SHIFT              (8)
-#define S3C_SDHCI_CTRL3_FIA1(_x)                ((_x) << 8)
-
-#define S3C_SDHCI_CTRL3_FIA0_MASK               (0x7f << 0)
-#define S3C_SDHCI_CTRL3_FIA0_SHIFT              (0)
-#define S3C_SDHCI_CTRL3_FIA0(_x)                ((_x) << 0)
-
-#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK       (0x3 << 16)
-#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT      (16)
-#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA        (0x0 << 16)
-#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA        (0x1 << 16)
-#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA        (0x2 << 16)
-#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA        (0x3 << 16)
-
-#define S3C64XX_SDHCI_CONTROL4_BUSY             (1)
-
-#endif /* __PLAT_S3C_SDHCI_REGS_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h
index 29c26a818842..f05f2afa440d 100644
--- a/arch/arm/plat-samsung/include/plat/regs-serial.h
+++ b/arch/arm/plat-samsung/include/plat/regs-serial.h
@@ -1,281 +1 @@
-/* arch/arm/plat-samsung/include/plat/regs-serial.h
- *
- *  From linux/include/asm-arm/hardware/serial_s3c2410.h
- *
- *  Internal header file for Samsung S3C2410 serial ports (UART0-2)
- *
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *
- *  Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk)
- *
- *  Adapted from:
- *
- *  Internal header file for MX1ADS serial ports (UART1 & 2)
- *
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#ifndef __ASM_ARM_REGS_SERIAL_H
-#define __ASM_ARM_REGS_SERIAL_H
-
-#define S3C24XX_VA_UART0      (S3C_VA_UART)
-#define S3C24XX_VA_UART1      (S3C_VA_UART + 0x4000 )
-#define S3C24XX_VA_UART2      (S3C_VA_UART + 0x8000 )
-#define S3C24XX_VA_UART3      (S3C_VA_UART + 0xC000 )
-
-#define S3C2410_PA_UART0      (S3C24XX_PA_UART)
-#define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
-#define S3C2410_PA_UART2      (S3C24XX_PA_UART + 0x8000 )
-#define S3C2443_PA_UART3      (S3C24XX_PA_UART + 0xC000 )
-
-#define S3C2410_URXH      (0x24)
-#define S3C2410_UTXH      (0x20)
-#define S3C2410_ULCON     (0x00)
-#define S3C2410_UCON      (0x04)
-#define S3C2410_UFCON     (0x08)
-#define S3C2410_UMCON     (0x0C)
-#define S3C2410_UBRDIV    (0x28)
-#define S3C2410_UTRSTAT   (0x10)
-#define S3C2410_UERSTAT   (0x14)
-#define S3C2410_UFSTAT    (0x18)
-#define S3C2410_UMSTAT    (0x1C)
-
-#define S3C2410_LCON_CFGMASK      ((0xF<<3)|(0x3))
-
-#define S3C2410_LCON_CS5          (0x0)
-#define S3C2410_LCON_CS6          (0x1)
-#define S3C2410_LCON_CS7          (0x2)
-#define S3C2410_LCON_CS8          (0x3)
-#define S3C2410_LCON_CSMASK       (0x3)
-
-#define S3C2410_LCON_PNONE        (0x0)
-#define S3C2410_LCON_PEVEN        (0x5 << 3)
-#define S3C2410_LCON_PODD         (0x4 << 3)
-#define S3C2410_LCON_PMASK        (0x7 << 3)
-
-#define S3C2410_LCON_STOPB        (1<<2)
-#define S3C2410_LCON_IRM          (1<<6)
-
-#define S3C2440_UCON_CLKMASK      (3<<10)
-#define S3C2440_UCON_CLKSHIFT     (10)
-#define S3C2440_UCON_PCLK         (0<<10)
-#define S3C2440_UCON_UCLK         (1<<10)
-#define S3C2440_UCON_PCLK2        (2<<10)
-#define S3C2440_UCON_FCLK         (3<<10)
-#define S3C2443_UCON_EPLL         (3<<10)
-
-#define S3C6400_UCON_CLKMASK    (3<<10)
-#define S3C6400_UCON_CLKSHIFT   (10)
-#define S3C6400_UCON_PCLK       (0<<10)
-#define S3C6400_UCON_PCLK2      (2<<10)
-#define S3C6400_UCON_UCLK0      (1<<10)
-#define S3C6400_UCON_UCLK1      (3<<10)
-
-#define S3C2440_UCON2_FCLK_EN     (1<<15)
-#define S3C2440_UCON0_DIVMASK     (15 << 12)
-#define S3C2440_UCON1_DIVMASK     (15 << 12)
-#define S3C2440_UCON2_DIVMASK     (7 << 12)
-#define S3C2440_UCON_DIVSHIFT     (12)
-
-#define S3C2412_UCON_CLKMASK    (3<<10)
-#define S3C2412_UCON_CLKSHIFT   (10)
-#define S3C2412_UCON_UCLK       (1<<10)
-#define S3C2412_UCON_USYSCLK    (3<<10)
-#define S3C2412_UCON_PCLK       (0<<10)
-#define S3C2412_UCON_PCLK2      (2<<10)
-
-#define S3C2410_UCON_CLKMASK    (1 << 10)
-#define S3C2410_UCON_CLKSHIFT   (10)
-#define S3C2410_UCON_UCLK         (1<<10)
-#define S3C2410_UCON_SBREAK       (1<<4)
-
-#define S3C2410_UCON_TXILEVEL     (1<<9)
-#define S3C2410_UCON_RXILEVEL     (1<<8)
-#define S3C2410_UCON_TXIRQMODE    (1<<2)
-#define S3C2410_UCON_RXIRQMODE    (1<<0)
-#define S3C2410_UCON_RXFIFO_TOI   (1<<7)
-#define S3C2443_UCON_RXERR_IRQEN  (1<<6)
-#define S3C2443_UCON_LOOPBACK     (1<<5)
-
-#define S3C2410_UCON_DEFAULT      (S3C2410_UCON_TXILEVEL  | \
-                                   S3C2410_UCON_RXILEVEL  | \
-                                   S3C2410_UCON_TXIRQMODE | \
-                                   S3C2410_UCON_RXIRQMODE | \
-                                   S3C2410_UCON_RXFIFO_TOI)
-
-#define S3C2410_UFCON_FIFOMODE    (1<<0)
-#define S3C2410_UFCON_TXTRIG0     (0<<6)
-#define S3C2410_UFCON_RXTRIG8     (1<<4)
-#define S3C2410_UFCON_RXTRIG12    (2<<4)
-
-/* S3C2440 FIFO trigger levels */
-#define S3C2440_UFCON_RXTRIG1     (0<<4)
-#define S3C2440_UFCON_RXTRIG8     (1<<4)
-#define S3C2440_UFCON_RXTRIG16    (2<<4)
-#define S3C2440_UFCON_RXTRIG32    (3<<4)
-
-#define S3C2440_UFCON_TXTRIG0     (0<<6)
-#define S3C2440_UFCON_TXTRIG16    (1<<6)
-#define S3C2440_UFCON_TXTRIG32    (2<<6)
-#define S3C2440_UFCON_TXTRIG48    (3<<6)
-
-#define S3C2410_UFCON_RESETBOTH   (3<<1)
-#define S3C2410_UFCON_RESETTX     (1<<2)
-#define S3C2410_UFCON_RESETRX     (1<<1)
-
-#define S3C2410_UFCON_DEFAULT     (S3C2410_UFCON_FIFOMODE | \
-                                   S3C2410_UFCON_TXTRIG0  | \
-                                   S3C2410_UFCON_RXTRIG8 )
-
-#define S3C2410_UMCOM_AFC         (1<<4)
-#define S3C2410_UMCOM_RTS_LOW     (1<<0)
-
-#define S3C2412_UMCON_AFC_63    (0<<5)          /* same as s3c2443 */
-#define S3C2412_UMCON_AFC_56    (1<<5)
-#define S3C2412_UMCON_AFC_48    (2<<5)
-#define S3C2412_UMCON_AFC_40    (3<<5)
-#define S3C2412_UMCON_AFC_32    (4<<5)
-#define S3C2412_UMCON_AFC_24    (5<<5)
-#define S3C2412_UMCON_AFC_16    (6<<5)
-#define S3C2412_UMCON_AFC_8     (7<<5)
-
-#define S3C2410_UFSTAT_TXFULL     (1<<9)
-#define S3C2410_UFSTAT_RXFULL     (1<<8)
-#define S3C2410_UFSTAT_TXMASK     (15<<4)
-#define S3C2410_UFSTAT_TXSHIFT    (4)
-#define S3C2410_UFSTAT_RXMASK     (15<<0)
-#define S3C2410_UFSTAT_RXSHIFT    (0)
-
-/* UFSTAT S3C2443 same as S3C2440 */
-#define S3C2440_UFSTAT_TXFULL     (1<<14)
-#define S3C2440_UFSTAT_RXFULL     (1<<6)
-#define S3C2440_UFSTAT_TXSHIFT    (8)
-#define S3C2440_UFSTAT_RXSHIFT    (0)
-#define S3C2440_UFSTAT_TXMASK     (63<<8)
-#define S3C2440_UFSTAT_RXMASK     (63)
-
-#define S3C2410_UTRSTAT_TXE       (1<<2)
-#define S3C2410_UTRSTAT_TXFE      (1<<1)
-#define S3C2410_UTRSTAT_RXDR      (1<<0)
-
-#define S3C2410_UERSTAT_OVERRUN   (1<<0)
-#define S3C2410_UERSTAT_FRAME     (1<<2)
-#define S3C2410_UERSTAT_BREAK     (1<<3)
-#define S3C2443_UERSTAT_PARITY    (1<<1)
-
-#define S3C2410_UERSTAT_ANY       (S3C2410_UERSTAT_OVERRUN | \
-                                   S3C2410_UERSTAT_FRAME | \
-                                   S3C2410_UERSTAT_BREAK)
-
-#define S3C2410_UMSTAT_CTS        (1<<0)
-#define S3C2410_UMSTAT_DeltaCTS   (1<<2)
-
-#define S3C2443_DIVSLOT           (0x2C)
-
-/* S3C64XX interrupt registers. */
-#define S3C64XX_UINTP           0x30
-#define S3C64XX_UINTSP          0x34
-#define S3C64XX_UINTM           0x38
-
-#define S3C64XX_UINTM_RXD       (0)
-#define S3C64XX_UINTM_TXD       (2)
-#define S3C64XX_UINTM_RXD_MSK   (1 << S3C64XX_UINTM_RXD)
-#define S3C64XX_UINTM_TXD_MSK   (1 << S3C64XX_UINTM_TXD)
-
-/* Following are specific to S5PV210 */
-#define S5PV210_UCON_CLKMASK    (1<<10)
-#define S5PV210_UCON_CLKSHIFT   (10)
-#define S5PV210_UCON_PCLK       (0<<10)
-#define S5PV210_UCON_UCLK       (1<<10)
-
-#define S5PV210_UFCON_TXTRIG0   (0<<8)
-#define S5PV210_UFCON_TXTRIG4   (1<<8)
-#define S5PV210_UFCON_TXTRIG8   (2<<8)
-#define S5PV210_UFCON_TXTRIG16  (3<<8)
-#define S5PV210_UFCON_TXTRIG32  (4<<8)
-#define S5PV210_UFCON_TXTRIG64  (5<<8)
-#define S5PV210_UFCON_TXTRIG128 (6<<8)
-#define S5PV210_UFCON_TXTRIG256 (7<<8)
-
-#define S5PV210_UFCON_RXTRIG1   (0<<4)
-#define S5PV210_UFCON_RXTRIG4   (1<<4)
-#define S5PV210_UFCON_RXTRIG8   (2<<4)
-#define S5PV210_UFCON_RXTRIG16  (3<<4)
-#define S5PV210_UFCON_RXTRIG32  (4<<4)
-#define S5PV210_UFCON_RXTRIG64  (5<<4)
-#define S5PV210_UFCON_RXTRIG128 (6<<4)
-#define S5PV210_UFCON_RXTRIG256 (7<<4)
-
-#define S5PV210_UFSTAT_TXFULL   (1<<24)
-#define S5PV210_UFSTAT_RXFULL   (1<<8)
-#define S5PV210_UFSTAT_TXMASK   (255<<16)
-#define S5PV210_UFSTAT_TXSHIFT  (16)
-#define S5PV210_UFSTAT_RXMASK   (255<<0)
-#define S5PV210_UFSTAT_RXSHIFT  (0)
-
-#define S3C2410_UCON_CLKSEL0    (1 << 0)
-#define S3C2410_UCON_CLKSEL1    (1 << 1)
-#define S3C2410_UCON_CLKSEL2    (1 << 2)
-#define S3C2410_UCON_CLKSEL3    (1 << 3)
-
-/* Default values for s5pv210 UCON and UFCON uart registers */
-#define S5PV210_UCON_DEFAULT    (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define S5PV210_UFCON_DEFAULT   (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-
-#ifndef __ASSEMBLY__
-
-/* configuration structure for per-machine configurations for the
- * serial port
- *
- * the pointer is setup by the machine specific initialisation from the
- * arch/arm/mach-s3c2410/ directory.
-*/
-
-struct s3c2410_uartcfg {
-        unsigned char      hwport;       /* hardware port number */
-        unsigned char      unused;
-        unsigned short     flags;
-        upf_t              uart_flags;   /* default uart flags */
-        unsigned int       clk_sel;
-
-        unsigned int       has_fracval;
-
-        unsigned long      ucon;         /* value of ucon for port */
-        unsigned long      ulcon;        /* value of ulcon for port */
-        unsigned long      ufcon;        /* value of ufcon for port */
-};
-
-/* s3c24xx_uart_devs
- *
- * this is exported from the core as we cannot use driver_register(),
- * or platform_add_device() before the console_initcall()
-*/
-
-extern struct platform_device *s3c24xx_uart_devs[4];
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ASM_ARM_REGS_SERIAL_H */
-
+#include <linux/serial_s3c.h>
diff --git a/arch/arm/plat-samsung/include/plat/rtc-core.h b/arch/arm/plat-samsung/include/plat/rtc-core.h
index 21d8594d37ca..7b542f7b7938 100644
--- a/arch/arm/plat-samsung/include/plat/rtc-core.h
+++ b/arch/arm/plat-samsung/include/plat/rtc-core.h
@@ -19,7 +19,7 @@
 /* re-define device name depending on support. */
 static inline void s3c_rtc_setname(char *name)
 {
-#if defined(CONFIG_SAMSUNG_DEV_RTC) || defined(CONFIG_PLAT_S3C24XX)
+#if defined(CONFIG_S3C_DEV_RTC) || defined(CONFIG_PLAT_S3C24XX)
         s3c_device_rtc.name = name;
 #endif
 }
diff --git a/arch/arm/plat-samsung/include/plat/s3c2410.h b/arch/arm/plat-samsung/include/plat/s3c2410.h
deleted file mode 100644
index 55b0e5f51e97..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c2410.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c2410.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2410 machine directory
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#ifdef CONFIG_CPU_S3C2410
-
-extern  int s3c2410_init(void);
-extern  int s3c2410a_init(void);
-
-extern void s3c2410_map_io(void);
-
-extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2410_init_clocks(int xtal);
-
-#else
-#define s3c2410_init_clocks NULL
-#define s3c2410_init_uarts NULL
-#define s3c2410_map_io NULL
-#define s3c2410_init NULL
-#define s3c2410a_init NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c2412.h b/arch/arm/plat-samsung/include/plat/s3c2412.h
deleted file mode 100644
index cbae50ddacc8..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c2412.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c2412.h
- *
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2412 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2412
-
-extern  int s3c2412_init(void);
-
-extern void s3c2412_map_io(void);
-
-extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2412_init_clocks(int xtal);
-
-extern  int s3c2412_baseclk_add(void);
-
-extern void s3c2412_restart(char mode, const char *cmd);
-#else
-#define s3c2412_init_clocks NULL
-#define s3c2412_init_uarts NULL
-#define s3c2412_map_io NULL
-#define s3c2412_init NULL
-#define s3c2412_restart NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c2416.h b/arch/arm/plat-samsung/include/plat/s3c2416.h
deleted file mode 100644
index f27399a3c68d..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c2416.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c2416.h
- *
- * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>
- *
- * Header file for s3c2416 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2416
-
-struct s3c2410_uartcfg;
-
-extern  int s3c2416_init(void);
-
-extern void s3c2416_map_io(void);
-
-extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2416_init_clocks(int xtal);
-
-extern  int s3c2416_baseclk_add(void);
-
-extern void s3c2416_restart(char mode, const char *cmd);
-
-extern void s3c2416_init_irq(void);
-extern struct syscore_ops s3c2416_irq_syscore_ops;
-
-#else
-#define s3c2416_init_clocks NULL
-#define s3c2416_init_uarts NULL
-#define s3c2416_map_io NULL
-#define s3c2416_init NULL
-#define s3c2416_restart NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c2443.h b/arch/arm/plat-samsung/include/plat/s3c2443.h
deleted file mode 100644
index 71b88ec48956..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c2443.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c2443.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2443 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2443
-
-struct s3c2410_uartcfg;
-
-extern  int s3c2443_init(void);
-
-extern void s3c2443_map_io(void);
-
-extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2443_init_clocks(int xtal);
-
-extern  int s3c2443_baseclk_add(void);
-
-extern void s3c2443_restart(char mode, const char *cmd);
-
-extern void s3c2443_init_irq(void);
-#else
-#define s3c2443_init_clocks NULL
-#define s3c2443_init_uarts NULL
-#define s3c2443_map_io NULL
-#define s3c2443_init NULL
-#define s3c2443_restart NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c244x.h b/arch/arm/plat-samsung/include/plat/s3c244x.h
deleted file mode 100644
index ea0c961b7603..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c244x.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c244x.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C2440 and S3C2442 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
-
-extern void s3c244x_map_io(void);
-
-extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c244x_init_clocks(int xtal);
-
-#else
-#define s3c244x_init_clocks NULL
-#define s3c244x_init_uarts NULL
-#endif
-
-#ifdef CONFIG_CPU_S3C2440
-extern  int s3c2440_init(void);
-
-extern void s3c2440_map_io(void);
-#else
-#define s3c2440_init NULL
-#define s3c2440_map_io NULL
-#endif
-
-#ifdef CONFIG_CPU_S3C2442
-extern  int s3c2442_init(void);
-
-extern void s3c2442_map_io(void);
-#else
-#define s3c2442_init NULL
-#define s3c2442_map_io NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/s5p-time.h b/arch/arm/plat-samsung/include/plat/s5p-time.h
deleted file mode 100644
index 9c96f3586ce0..000000000000
--- a/arch/arm/plat-samsung/include/plat/s5p-time.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s5p-time.h
- *
- * Copyright 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Header file for s5p time support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_S5P_TIME_H
-#define __ASM_PLAT_S5P_TIME_H __FILE__
-
-/* S5P HR-Timer Clock mode */
-enum s5p_timer_mode {
-        S5P_PWM0,
-        S5P_PWM1,
-        S5P_PWM2,
-        S5P_PWM3,
-        S5P_PWM4,
-};
-
-struct s5p_timer_source {
-        unsigned int event_id;
-        unsigned int source_id;
-};
-
-/* Be able to sleep for atleast 4 seconds (usually more) */
-#define S5PTIMER_MIN_RANGE      4
-
-#define TCNT_MAX                0xffffffff
-#define NON_PERIODIC            0
-#define PERIODIC                1
-
-extern void __init s5p_set_timer_source(enum s5p_timer_mode event,
-                                        enum s5p_timer_mode source);
-extern  void s5p_timer_init(void);
-#endif /* __ASM_PLAT_S5P_TIME_H */
diff --git a/arch/arm/plat-samsung/include/plat/samsung-time.h b/arch/arm/plat-samsung/include/plat/samsung-time.h
new file mode 100644
index 000000000000..4cc99bb1f176
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/samsung-time.h
@@ -0,0 +1,53 @@
+/* linux/arch/arm/plat-samsung/include/plat/samsung-time.h
+ *
+ * Copyright 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Header file for samsung s3c and s5p time support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_SAMSUNG_TIME_H
+#define __ASM_PLAT_SAMSUNG_TIME_H __FILE__
+
+/* SAMSUNG HR-Timer Clock mode */
+enum samsung_timer_mode {
+        SAMSUNG_PWM0,
+        SAMSUNG_PWM1,
+        SAMSUNG_PWM2,
+        SAMSUNG_PWM3,
+        SAMSUNG_PWM4,
+};
+
+struct samsung_timer_source {
+        unsigned int event_id;
+        unsigned int source_id;
+};
+
+/* Be able to sleep for atleast 4 seconds (usually more) */
+#define SAMSUNG_TIMER_MIN_RANGE 4
+
+#if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S5PC100)
+#define TCNT_MAX                0xffff
+#define TSCALER_DIV             25
+#define TDIV                    50
+#define TSIZE                   16
+#else
+#define TCNT_MAX                0xffffffff
+#define TSCALER_DIV             2
+#define TDIV                    2
+#define TSIZE                   32
+#endif
+
+#define NON_PERIODIC            0
+#define PERIODIC                1
+
+extern void __init samsung_set_timer_source(enum samsung_timer_mode event,
+                                        enum samsung_timer_mode source);
+
+extern void __init samsung_timer_init(void);
+
+#endif /* __ASM_PLAT_SAMSUNG_TIME_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 9b87f38fc4f4..ce1d0f785efd 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -18,62 +18,9 @@
 #ifndef __PLAT_S3C_SDHCI_H
 #define __PLAT_S3C_SDHCI_H __FILE__
 
+#include <linux/platform_data/mmc-sdhci-s3c.h>
 #include <plat/devs.h>
 
-struct platform_device;
-struct mmc_host;
-struct mmc_card;
-struct mmc_ios;
-
-enum cd_types {
-        S3C_SDHCI_CD_INTERNAL,  /* use mmc internal CD line */
-        S3C_SDHCI_CD_EXTERNAL,  /* use external callback */
-        S3C_SDHCI_CD_GPIO,      /* use external gpio pin for CD line */
-        S3C_SDHCI_CD_NONE,      /* no CD line, use polling to detect card */
-        S3C_SDHCI_CD_PERMANENT, /* no CD line, card permanently wired to host */
-};
-
-/**
- * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
- * @max_width: The maximum number of data bits supported.
- * @host_caps: Standard MMC host capabilities bit field.
- * @host_caps2: The second standard MMC host capabilities bit field.
- * @cd_type: Type of Card Detection method (see cd_types enum above)
- * @ext_cd_init: Initialize external card detect subsystem. Called on
- *               sdhci-s3c driver probe when cd_type == S3C_SDHCI_CD_EXTERNAL.
- *               notify_func argument is a callback to the sdhci-s3c driver
- *               that triggers the card detection event. Callback arguments:
- *               dev is pointer to platform device of the host controller,
- *               state is new state of the card (0 - removed, 1 - inserted).
- * @ext_cd_cleanup: Cleanup external card detect subsystem. Called on
- *               sdhci-s3c driver remove when cd_type == S3C_SDHCI_CD_EXTERNAL.
- *               notify_func argument is the same callback as for ext_cd_init.
- * @ext_cd_gpio: gpio pin used for external CD line, valid only if
- *               cd_type == S3C_SDHCI_CD_GPIO
- * @ext_cd_gpio_invert: invert values for external CD gpio line
- * @cfg_gpio: Configure the GPIO for a specific card bit-width
- *
- * Initialisation data specific to either the machine or the platform
- * for the device driver to use or call-back when configuring gpio or
- * card speed information.
-*/
-struct s3c_sdhci_platdata {
-        unsigned int    max_width;
-        unsigned int    host_caps;
-        unsigned int    host_caps2;
-        unsigned int    pm_caps;
-        enum cd_types   cd_type;
-
-        int             ext_cd_gpio;
-        bool            ext_cd_gpio_invert;
-        int     (*ext_cd_init)(void (*notify_func)(struct platform_device *,
-                                                   int state));
-        int     (*ext_cd_cleanup)(void (*notify_func)(struct platform_device *,
-                                                      int state));
-
-        void    (*cfg_gpio)(struct platform_device *dev, int width);
-};
-
 /* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data
  * @pd: The default platform data for this device.
  * @set: Pointer to the platform data to fill in.
@@ -206,7 +153,7 @@ static inline void s3c6400_default_sdhci2(void) { }
 
 /* S5P64X0 SDHCI setup */
 
-#ifdef CONFIG_S5P64X0_SETUP_SDHCI
+#ifdef CONFIG_S5P64X0_SETUP_SDHCI_GPIO
 static inline void s5p64x0_default_sdhci0(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC
@@ -241,7 +188,7 @@ static inline void s5p64x0_default_sdhci1(void) { }
 static inline void s5p6440_default_sdhci2(void) { }
 static inline void s5p6450_default_sdhci2(void) { }
 
-#endif /* CONFIG_S5P64X0_SETUP_SDHCI */
+#endif /* CONFIG_S5P64X0_SETUP_SDHCI_GPIO */
 
 /* S5PC100 SDHCI setup */
 
@@ -378,5 +325,4 @@ static inline void s3c_sdhci_setname(int id, char *name)
                 break;
         }
 }
-
 #endif /* __PLAT_S3C_SDHCI_H */
diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h
index 959bcdb03a25..ab34dfadb7f9 100644
--- a/arch/arm/plat-samsung/include/plat/usb-phy.h
+++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
@@ -11,10 +11,7 @@
 #ifndef __PLAT_SAMSUNG_USB_PHY_H
 #define __PLAT_SAMSUNG_USB_PHY_H __FILE__
 
-enum s5p_usb_phy_type {
-        S5P_USB_PHY_DEVICE,
-        S5P_USB_PHY_HOST,
-};
+#include <linux/usb/samsung_usb_phy.h>
 
 extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
 extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index f980cf3d2baa..0fceb4273824 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -16,15 +16,15 @@
 #include <linux/kernel.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/io.h>
 
 #include <mach/map.h>
+#include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/irq-vic-timer.h>
 #include <plat/regs-timer.h>
 
-#include <asm/mach/irq.h>
-
 static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
 {
         struct irq_chip *chip = irq_get_chip(irq);
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 002b1472293b..53210ec4e8ec 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -27,6 +27,7 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-irq.h>
+#include <mach/irqs.h>
 #include <asm/irq.h>
 
 #include <plat/pm.h>
diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c
index 5ec104b5408b..a93fb6fb6606 100644
--- a/arch/arm/plat-samsung/s5p-dev-mfc.c
+++ b/arch/arm/plat-samsung/s5p-dev-mfc.c
@@ -18,10 +18,50 @@
 #include <linux/of.h>
 
 #include <mach/map.h>
+#include <mach/irqs.h>
 #include <plat/devs.h>
-#include <plat/irqs.h>
 #include <plat/mfc.h>
 
+static struct resource s5p_mfc_resource[] = {
+        [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
+        [1] = DEFINE_RES_IRQ(IRQ_MFC),
+};
+
+struct platform_device s5p_device_mfc = {
+        .name           = "s5p-mfc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s5p_mfc_resource),
+        .resource       = s5p_mfc_resource,
+};
+
+/*
+ * MFC hardware has 2 memory interfaces which are modelled as two separate
+ * platform devices to let dma-mapping distinguish between them.
+ *
+ * MFC parent device (s5p_device_mfc) must be registered before memory
+ * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
+ */
+
+struct platform_device s5p_device_mfc_l = {
+        .name           = "s5p-mfc-l",
+        .id             = -1,
+        .dev            = {
+                .parent                 = &s5p_device_mfc.dev,
+                .dma_mask               = &s5p_device_mfc_l.dev.coherent_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+struct platform_device s5p_device_mfc_r = {
+        .name           = "s5p-mfc-r",
+        .id             = -1,
+        .dev            = {
+                .parent                 = &s5p_device_mfc.dev,
+                .dma_mask               = &s5p_device_mfc_r.dev.coherent_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
 struct s5p_mfc_reserved_mem {
         phys_addr_t     base;
         unsigned long   size;
diff --git a/arch/arm/plat-samsung/s5p-irq-gpioint.c b/arch/arm/plat-samsung/s5p-irq-gpioint.c
index bae56131a50a..fafdb059043a 100644
--- a/arch/arm/plat-samsung/s5p-irq-gpioint.c
+++ b/arch/arm/plat-samsung/s5p-irq-gpioint.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/slab.h>
@@ -22,8 +23,6 @@
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
 
-#include <asm/mach/irq.h>
-
 #define GPIO_BASE(chip)         ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))
 
 #define CON_OFFSET              0x700
diff --git a/arch/arm/plat-samsung/s5p-irq.c b/arch/arm/plat-samsung/s5p-irq.c
index 103e371f5e35..ff1a76011b1e 100644
--- a/arch/arm/plat-samsung/s5p-irq.c
+++ b/arch/arm/plat-samsung/s5p-irq.c
@@ -15,6 +15,7 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-vic.h>
 
+#include <mach/irqs.h>
 #include <mach/map.h>
 #include <plat/regs-timer.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S
index bdf6dadf8790..a030e7301da8 100644
--- a/arch/arm/plat-samsung/s5p-sleep.S
+++ b/arch/arm/plat-samsung/s5p-sleep.S
@@ -25,6 +25,9 @@
 #include <asm/asm-offsets.h>
 #include <asm/hardware/cache-l2x0.h>
 
+#define CPU_MASK        0xff0ffff0
+#define CPU_CORTEX_A9   0x410fc090
+
 /*
  *       The following code is located into the .data section. This is to
  *       allow l2x0_regs_phys to be accessed with a relative load while we
@@ -51,6 +54,12 @@
 
 ENTRY(s3c_cpu_resume)
 #ifdef CONFIG_CACHE_L2X0
+        mrc     p15, 0, r0, c0, c0, 0
+        ldr     r1, =CPU_MASK
+        and     r0, r0, r1
+        ldr     r1, =CPU_CORTEX_A9
+        cmp     r0, r1
+        bne     resume_l2on
         adr     r0, l2x0_regs_phys
         ldr     r0, [r0]
         ldr     r1, [r0, #L2X0_R_PHY_BASE]
diff --git a/arch/arm/plat-samsung/s5p-time.c b/arch/arm/plat-samsung/samsung-time.c
index e92510cf82ee..f899cbc9b288 100644
--- a/arch/arm/plat-samsung/s5p-time.c
+++ b/arch/arm/plat-samsung/samsung-time.c
@@ -2,7 +2,7 @@
  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
  *
- * S5P - Common hr-timer support
+ * samsung - Common hr-timer support (s3c and s5p)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -25,41 +25,41 @@
 #include <mach/map.h>
 #include <plat/devs.h>
 #include <plat/regs-timer.h>
-#include <plat/s5p-time.h>
+#include <plat/samsung-time.h>
 
 static struct clk *tin_event;
 static struct clk *tin_source;
 static struct clk *tdiv_event;
 static struct clk *tdiv_source;
 static struct clk *timerclk;
-static struct s5p_timer_source timer_source;
+static struct samsung_timer_source timer_source;
 static unsigned long clock_count_per_tick;
-static void s5p_timer_resume(void);
+static void samsung_timer_resume(void);
 
-static void s5p_time_stop(enum s5p_timer_mode mode)
+static void samsung_time_stop(enum samsung_timer_mode mode)
 {
         unsigned long tcon;
 
         tcon = __raw_readl(S3C2410_TCON);
 
         switch (mode) {
-        case S5P_PWM0:
+        case SAMSUNG_PWM0:
                 tcon &= ~S3C2410_TCON_T0START;
                 break;
 
-        case S5P_PWM1:
+        case SAMSUNG_PWM1:
                 tcon &= ~S3C2410_TCON_T1START;
                 break;
 
-        case S5P_PWM2:
+        case SAMSUNG_PWM2:
                 tcon &= ~S3C2410_TCON_T2START;
                 break;
 
-        case S5P_PWM3:
+        case SAMSUNG_PWM3:
                 tcon &= ~S3C2410_TCON_T3START;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 tcon &= ~S3C2410_TCON_T4START;
                 break;
 
@@ -70,7 +70,7 @@ static void s5p_time_stop(enum s5p_timer_mode mode)
         __raw_writel(tcon, S3C2410_TCON);
 }
 
-static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt)
+static void samsung_time_setup(enum samsung_timer_mode mode, unsigned long tcnt)
 {
         unsigned long tcon;
 
@@ -79,27 +79,27 @@ static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt)
         tcnt--;
 
         switch (mode) {
-        case S5P_PWM0:
+        case SAMSUNG_PWM0:
                 tcon &= ~(0x0f << 0);
                 tcon |= S3C2410_TCON_T0MANUALUPD;
                 break;
 
-        case S5P_PWM1:
+        case SAMSUNG_PWM1:
                 tcon &= ~(0x0f << 8);
                 tcon |= S3C2410_TCON_T1MANUALUPD;
                 break;
 
-        case S5P_PWM2:
+        case SAMSUNG_PWM2:
                 tcon &= ~(0x0f << 12);
                 tcon |= S3C2410_TCON_T2MANUALUPD;
                 break;
 
-        case S5P_PWM3:
+        case SAMSUNG_PWM3:
                 tcon &= ~(0x0f << 16);
                 tcon |= S3C2410_TCON_T3MANUALUPD;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 tcon &= ~(0x07 << 20);
                 tcon |= S3C2410_TCON_T4MANUALUPD;
                 break;
@@ -114,14 +114,14 @@ static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt)
         __raw_writel(tcon, S3C2410_TCON);
 }
 
-static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
+static void samsung_time_start(enum samsung_timer_mode mode, bool periodic)
 {
         unsigned long tcon;
 
         tcon  = __raw_readl(S3C2410_TCON);
 
         switch (mode) {
-        case S5P_PWM0:
+        case SAMSUNG_PWM0:
                 tcon |= S3C2410_TCON_T0START;
                 tcon &= ~S3C2410_TCON_T0MANUALUPD;
 
@@ -131,7 +131,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T0RELOAD;
                 break;
 
-        case S5P_PWM1:
+        case SAMSUNG_PWM1:
                 tcon |= S3C2410_TCON_T1START;
                 tcon &= ~S3C2410_TCON_T1MANUALUPD;
 
@@ -141,7 +141,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T1RELOAD;
                 break;
 
-        case S5P_PWM2:
+        case SAMSUNG_PWM2:
                 tcon |= S3C2410_TCON_T2START;
                 tcon &= ~S3C2410_TCON_T2MANUALUPD;
 
@@ -151,7 +151,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T2RELOAD;
                 break;
 
-        case S5P_PWM3:
+        case SAMSUNG_PWM3:
                 tcon |= S3C2410_TCON_T3START;
                 tcon &= ~S3C2410_TCON_T3MANUALUPD;
 
@@ -161,7 +161,7 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
                         tcon &= ~S3C2410_TCON_T3RELOAD;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 tcon |= S3C2410_TCON_T4START;
                 tcon &= ~S3C2410_TCON_T4MANUALUPD;
 
@@ -178,24 +178,24 @@ static void s5p_time_start(enum s5p_timer_mode mode, bool periodic)
         __raw_writel(tcon, S3C2410_TCON);
 }
 
-static int s5p_set_next_event(unsigned long cycles,
+static int samsung_set_next_event(unsigned long cycles,
                                 struct clock_event_device *evt)
 {
-        s5p_time_setup(timer_source.event_id, cycles);
-        s5p_time_start(timer_source.event_id, NON_PERIODIC);
+        samsung_time_setup(timer_source.event_id, cycles);
+        samsung_time_start(timer_source.event_id, NON_PERIODIC);
 
         return 0;
 }
 
-static void s5p_set_mode(enum clock_event_mode mode,
+static void samsung_set_mode(enum clock_event_mode mode,
                                 struct clock_event_device *evt)
 {
-        s5p_time_stop(timer_source.event_id);
+        samsung_time_stop(timer_source.event_id);
 
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
-                s5p_time_setup(timer_source.event_id, clock_count_per_tick);
-                s5p_time_start(timer_source.event_id, PERIODIC);
+                samsung_time_setup(timer_source.event_id, clock_count_per_tick);
+                samsung_time_start(timer_source.event_id, PERIODIC);
                 break;
 
         case CLOCK_EVT_MODE_ONESHOT:
@@ -206,24 +206,24 @@ static void s5p_set_mode(enum clock_event_mode mode,
                 break;
 
         case CLOCK_EVT_MODE_RESUME:
-                s5p_timer_resume();
+                samsung_timer_resume();
                 break;
         }
 }
 
-static void s5p_timer_resume(void)
+static void samsung_timer_resume(void)
 {
         /* event timer restart */
-        s5p_time_setup(timer_source.event_id, clock_count_per_tick);
-        s5p_time_start(timer_source.event_id, PERIODIC);
+        samsung_time_setup(timer_source.event_id, clock_count_per_tick);
+        samsung_time_start(timer_source.event_id, PERIODIC);
 
         /* source timer restart */
-        s5p_time_setup(timer_source.source_id, TCNT_MAX);
-        s5p_time_start(timer_source.source_id, PERIODIC);
+        samsung_time_setup(timer_source.source_id, TCNT_MAX);
+        samsung_time_start(timer_source.source_id, PERIODIC);
 }
 
-void __init s5p_set_timer_source(enum s5p_timer_mode event,
-                                 enum s5p_timer_mode source)
+void __init samsung_set_timer_source(enum samsung_timer_mode event,
+                                 enum samsung_timer_mode source)
 {
         s3c_device_timer[event].dev.bus = &platform_bus_type;
         s3c_device_timer[source].dev.bus = &platform_bus_type;
@@ -233,14 +233,14 @@ void __init s5p_set_timer_source(enum s5p_timer_mode event,
 }
 
 static struct clock_event_device time_event_device = {
-        .name           = "s5p_event_timer",
+        .name           = "samsung_event_timer",
         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
         .rating         = 200,
-        .set_next_event = s5p_set_next_event,
-        .set_mode       = s5p_set_mode,
+        .set_next_event = samsung_set_next_event,
+        .set_mode       = samsung_set_mode,
 };
 
-static irqreturn_t s5p_clock_event_isr(int irq, void *dev_id)
+static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
 {
         struct clock_event_device *evt = dev_id;
 
@@ -249,14 +249,14 @@ static irqreturn_t s5p_clock_event_isr(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-static struct irqaction s5p_clock_event_irq = {
-        .name           = "s5p_time_irq",
+static struct irqaction samsung_clock_event_irq = {
+        .name           = "samsung_time_irq",
         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = s5p_clock_event_isr,
+        .handler        = samsung_clock_event_isr,
         .dev_id         = &time_event_device,
 };
 
-static void __init s5p_clockevent_init(void)
+static void __init samsung_clockevent_init(void)
 {
         unsigned long pclk;
         unsigned long clock_rate;
@@ -267,8 +267,8 @@ static void __init s5p_clockevent_init(void)
 
         tscaler = clk_get_parent(tdiv_event);
 
-        clk_set_rate(tscaler, pclk / 2);
-        clk_set_rate(tdiv_event, pclk / 2);
+        clk_set_rate(tscaler, pclk / TSCALER_DIV);
+        clk_set_rate(tdiv_event, pclk / TDIV);
         clk_set_parent(tin_event, tdiv_event);
 
         clock_rate = clk_get_rate(tin_event);
@@ -278,22 +278,22 @@ static void __init s5p_clockevent_init(void)
         clockevents_config_and_register(&time_event_device, clock_rate, 1, -1);
 
         irq_number = timer_source.event_id + IRQ_TIMER0;
-        setup_irq(irq_number, &s5p_clock_event_irq);
+        setup_irq(irq_number, &samsung_clock_event_irq);
 }
 
-static void __iomem *s5p_timer_reg(void)
+static void __iomem *samsung_timer_reg(void)
 {
         unsigned long offset = 0;
 
         switch (timer_source.source_id) {
-        case S5P_PWM0:
-        case S5P_PWM1:
-        case S5P_PWM2:
-        case S5P_PWM3:
+        case SAMSUNG_PWM0:
+        case SAMSUNG_PWM1:
+        case SAMSUNG_PWM2:
+        case SAMSUNG_PWM3:
                 offset = (timer_source.source_id * 0x0c) + 0x14;
                 break;
 
-        case S5P_PWM4:
+        case SAMSUNG_PWM4:
                 offset = 0x40;
                 break;
 
@@ -312,9 +312,9 @@ static void __iomem *s5p_timer_reg(void)
  * this wraps around for now, since it is just a relative time
  * stamp. (Inspired by U300 implementation.)
  */
-static u32 notrace s5p_read_sched_clock(void)
+static u32 notrace samsung_read_sched_clock(void)
 {
-        void __iomem *reg = s5p_timer_reg();
+        void __iomem *reg = samsung_timer_reg();
 
         if (!reg)
                 return 0;
@@ -322,29 +322,29 @@ static u32 notrace s5p_read_sched_clock(void)
         return ~__raw_readl(reg);
 }
 
-static void __init s5p_clocksource_init(void)
+static void __init samsung_clocksource_init(void)
 {
         unsigned long pclk;
         unsigned long clock_rate;
 
         pclk = clk_get_rate(timerclk);
 
-        clk_set_rate(tdiv_source, pclk / 2);
+        clk_set_rate(tdiv_source, pclk / TDIV);
         clk_set_parent(tin_source, tdiv_source);
 
         clock_rate = clk_get_rate(tin_source);
 
-        s5p_time_setup(timer_source.source_id, TCNT_MAX);
-        s5p_time_start(timer_source.source_id, PERIODIC);
+        samsung_time_setup(timer_source.source_id, TCNT_MAX);
+        samsung_time_start(timer_source.source_id, PERIODIC);
 
-        setup_sched_clock(s5p_read_sched_clock, 32, clock_rate);
+        setup_sched_clock(samsung_read_sched_clock, TSIZE, clock_rate);
 
-        if (clocksource_mmio_init(s5p_timer_reg(), "s5p_clocksource_timer",
-                        clock_rate, 250, 32, clocksource_mmio_readl_down))
-                panic("s5p_clocksource_timer: can't register clocksource\n");
+        if (clocksource_mmio_init(samsung_timer_reg(), "samsung_clocksource_timer",
+                        clock_rate, 250, TSIZE, clocksource_mmio_readl_down))
+                panic("samsung_clocksource_timer: can't register clocksource\n");
 }
 
-static void __init s5p_timer_resources(void)
+static void __init samsung_timer_resources(void)
 {
 
         unsigned long event_id = timer_source.event_id;
@@ -386,9 +386,9 @@ static void __init s5p_timer_resources(void)
         clk_enable(tin_source);
 }
 
-void __init s5p_timer_init(void)
+void __init samsung_timer_init(void)
 {
-        s5p_timer_resources();
-        s5p_clockevent_init();
-        s5p_clocksource_init();
+        samsung_timer_resources();
+        samsung_clockevent_init();
+        samsung_clocksource_init();
 }
diff --git a/arch/arm/plat-samsung/setup-mipiphy.c b/arch/arm/plat-samsung/setup-mipiphy.c
index 147459327601..66df315990a7 100644
--- a/arch/arm/plat-samsung/setup-mipiphy.c
+++ b/arch/arm/plat-samsung/setup-mipiphy.c
@@ -8,6 +8,7 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/export.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
@@ -50,8 +51,10 @@ int s5p_csis_phy_enable(int id, bool on)
 {
         return __s5p_mipi_phy_control(id, on, S5P_MIPI_DPHY_SRESETN);
 }
+EXPORT_SYMBOL(s5p_csis_phy_enable);
 
 int s5p_dsim_phy_enable(struct platform_device *pdev, bool on)
 {
         return __s5p_mipi_phy_control(pdev->id, on, S5P_MIPI_DPHY_MRESETN);
 }
+EXPORT_SYMBOL(s5p_dsim_phy_enable);
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
deleted file mode 100644
index 73defd00c3e4..000000000000
--- a/arch/arm/plat-samsung/time.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/* linux/arch/arm/plat-samsung/time.c
- *
- * Copyright (C) 2003-2005 Simtec Electronics
- *      Ben Dooks, <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/syscore_ops.h>
-
-#include <asm/mach-types.h>
-
-#include <asm/irq.h>
-#include <mach/map.h>
-#include <plat/regs-timer.h>
-#include <mach/regs-irq.h>
-#include <asm/mach/time.h>
-#include <mach/tick.h>
-
-#include <plat/clock.h>
-#include <plat/cpu.h>
-
-static unsigned long timer_startval;
-static unsigned long timer_usec_ticks;
-
-#ifndef TICK_MAX
-#define TICK_MAX (0xffff)
-#endif
-
-#define TIMER_USEC_SHIFT 16
-
-/* we use the shifted arithmetic to work out the ratio of timer ticks
- * to usecs, as often the peripheral clock is not a nice even multiple
- * of 1MHz.
- *
- * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
- * for the current HZ value of 200 without producing overflows.
- *
- * Original patch by Dimitry Andric, updated by Ben Dooks
-*/
-
-
-/* timer_mask_usec_ticks
- *
- * given a clock and divisor, make the value to pass into timer_ticks_to_usec
- * to scale the ticks into usecs
-*/
-
-static inline unsigned long
-timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
-{
-        unsigned long den = pclk / 1000;
-
-        return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
-}
-
-/* timer_ticks_to_usec
- *
- * convert timer ticks to usec.
-*/
-
-static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
-{
-        unsigned long res;
-
-        res = ticks * timer_usec_ticks;
-        res += 1 << (TIMER_USEC_SHIFT - 4);     /* round up slightly */
-
-        return res >> TIMER_USEC_SHIFT;
-}
-
-/***
- * Returns microsecond  since last clock interrupt.  Note that interrupts
- * will have been disabled by do_gettimeoffset()
- * IRQs are disabled before entering here from do_gettimeofday()
- */
-
-static u32 s3c2410_gettimeoffset(void)
-{
-        unsigned long tdone;
-        unsigned long tval;
-
-        /* work out how many ticks have gone since last timer interrupt */
-
-        tval =  __raw_readl(S3C2410_TCNTO(4));
-        tdone = timer_startval - tval;
-
-        /* check to see if there is an interrupt pending */
-
-        if (s3c24xx_ostimer_pending()) {
-                /* re-read the timer, and try and fix up for the missed
-                 * interrupt. Note, the interrupt may go off before the
-                 * timer has re-loaded from wrapping.
-                 */
-
-                tval =  __raw_readl(S3C2410_TCNTO(4));
-                tdone = timer_startval - tval;
-
-                if (tval != 0)
-                        tdone += timer_startval;
-        }
-
-        return timer_ticks_to_usec(tdone) * 1000;
-}
-
-
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t
-s3c2410_timer_interrupt(int irq, void *dev_id)
-{
-        timer_tick();
-        return IRQ_HANDLED;
-}
-
-static struct irqaction s3c2410_timer_irq = {
-        .name           = "S3C2410 Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = s3c2410_timer_interrupt,
-};
-
-#define use_tclk1_12() ( \
-        machine_is_bast()       || \
-        machine_is_vr1000()     || \
-        machine_is_anubis()     || \
-        machine_is_osiris())
-
-static struct clk *tin;
-static struct clk *tdiv;
-static struct clk *timerclk;
-
-/*
- * Set up timer interrupt, and return the current time in seconds.
- *
- * Currently we only use timer4, as it is the only timer which has no
- * other function that can be exploited externally
- */
-static void s3c2410_timer_setup (void)
-{
-        unsigned long tcon;
-        unsigned long tcnt;
-        unsigned long tcfg1;
-        unsigned long tcfg0;
-
-        tcnt = TICK_MAX;  /* default value for tcnt */
-
-        /* configure the system for whichever machine is in use */
-
-        if (use_tclk1_12()) {
-                /* timer is at 12MHz, scaler is 1 */
-                timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
-                tcnt = 12000000 / HZ;
-
-                tcfg1 = __raw_readl(S3C2410_TCFG1);
-                tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
-                tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
-                __raw_writel(tcfg1, S3C2410_TCFG1);
-        } else {
-                unsigned long pclk;
-                struct clk *tscaler;
-
-                /* for the h1940 (and others), we use the pclk from the core
-                 * to generate the timer values. since values around 50 to
-                 * 70MHz are not values we can directly generate the timer
-                 * value from, we need to pre-scale and divide before using it.
-                 *
-                 * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz
-                 * (8.45 ticks per usec)
-                 */
-
-                pclk = clk_get_rate(timerclk);
-
-                /* configure clock tick */
-
-                timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
-
-                tscaler = clk_get_parent(tdiv);
-
-                clk_set_rate(tscaler, pclk / 3);
-                clk_set_rate(tdiv, pclk / 6);
-                clk_set_parent(tin, tdiv);
-
-                tcnt = clk_get_rate(tin) / HZ;
-        }
-
-        tcon = __raw_readl(S3C2410_TCON);
-        tcfg0 = __raw_readl(S3C2410_TCFG0);
-        tcfg1 = __raw_readl(S3C2410_TCFG1);
-
-        /* timers reload after counting zero, so reduce the count by 1 */
-
-        tcnt--;
-
-        printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
-               tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
-
-        /* check to see if timer is within 16bit range... */
-        if (tcnt > TICK_MAX) {
-                panic("setup_timer: HZ is too small, cannot configure timer!");
-                return;
-        }
-
-        __raw_writel(tcfg1, S3C2410_TCFG1);
-        __raw_writel(tcfg0, S3C2410_TCFG0);
-
-        timer_startval = tcnt;
-        __raw_writel(tcnt, S3C2410_TCNTB(4));
-
-        /* ensure timer is stopped... */
-
-        tcon &= ~(7<<20);
-        tcon |= S3C2410_TCON_T4RELOAD;
-        tcon |= S3C2410_TCON_T4MANUALUPD;
-
-        __raw_writel(tcon, S3C2410_TCON);
-        __raw_writel(tcnt, S3C2410_TCNTB(4));
-        __raw_writel(tcnt, S3C2410_TCMPB(4));
-
-        /* start the timer running */
-        tcon |= S3C2410_TCON_T4START;
-        tcon &= ~S3C2410_TCON_T4MANUALUPD;
-        __raw_writel(tcon, S3C2410_TCON);
-}
-
-static void __init s3c2410_timer_resources(void)
-{
-        struct platform_device tmpdev;
-
-        tmpdev.dev.bus = &platform_bus_type;
-        tmpdev.id = 4;
-
-        timerclk = clk_get(NULL, "timers");
-        if (IS_ERR(timerclk))
-                panic("failed to get clock for system timer");
-
-        clk_enable(timerclk);
-
-        if (!use_tclk1_12()) {
-                tmpdev.id = 4;
-                tmpdev.dev.init_name = "s3c24xx-pwm.4";
-                tin = clk_get(&tmpdev.dev, "pwm-tin");
-                if (IS_ERR(tin))
-                        panic("failed to get pwm-tin clock for system timer");
-
-                tdiv = clk_get(&tmpdev.dev, "pwm-tdiv");
-                if (IS_ERR(tdiv))
-                        panic("failed to get pwm-tdiv clock for system timer");
-        }
-
-        clk_enable(tin);
-}
-
-static struct syscore_ops s3c24xx_syscore_ops = {
-        .resume         = s3c2410_timer_setup,
-};
-
-void __init s3c24xx_timer_init(void)
-{
-        arch_gettimeoffset = s3c2410_gettimeoffset;
-
-        s3c2410_timer_resources();
-        s3c2410_timer_setup();
-        setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
-        register_syscore_ops(&s3c24xx_syscore_ops);
-}
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
deleted file mode 100644
index 8a08c31b5e20..000000000000
--- a/arch/arm/plat-spear/Kconfig
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# SPEAr Platform configuration file
-#
-
-if PLAT_SPEAR
-
-choice
-        prompt "ST SPEAr Family"
-        default ARCH_SPEAR3XX
-
-config ARCH_SPEAR13XX
-        bool "ST SPEAr13xx with Device Tree"
-        select ARCH_HAS_CPUFREQ
-        select ARM_GIC
-        select CPU_V7
-        select GPIO_SPEAR_SPICS
-        select HAVE_SMP
-        select MIGHT_HAVE_CACHE_L2X0
-        select PINCTRL
-        select USE_OF
-        help
-          Supports for ARM's SPEAR13XX family
-
-config ARCH_SPEAR3XX
-        bool "ST SPEAr3xx with Device Tree"
-        select ARM_VIC
-        select CPU_ARM926T
-        select PINCTRL
-        select USE_OF
-        help
-          Supports for ARM's SPEAR3XX family
-
-config ARCH_SPEAR6XX
-        bool "SPEAr6XX"
-        select ARM_VIC
-        select CPU_ARM926T
-        help
-          Supports for ARM's SPEAR6XX family
-
-endchoice
-
-# Adding SPEAr machine specific configuration files
-source "arch/arm/mach-spear13xx/Kconfig"
-source "arch/arm/mach-spear3xx/Kconfig"
-source "arch/arm/mach-spear6xx/Kconfig"
-
-endif
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
deleted file mode 100644
index 01e88532a5db..000000000000
--- a/arch/arm/plat-spear/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# SPEAr Platform specific Makefile
-#
-
-# Common support
-obj-y   := restart.o time.o
-
-obj-$(CONFIG_ARCH_SPEAR3XX)     += pl080.o
-obj-$(CONFIG_ARCH_SPEAR6XX)     += pl080.o
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
index f2ac15561778..1e1b2d769748 100644
--- a/arch/arm/plat-versatile/platsmp.c
+++ b/arch/arm/plat-versatile/platsmp.c
@@ -14,7 +14,6 @@
 #include <linux/device.h>
 #include <linux/jiffies.h>
 #include <linux/smp.h>
-#include <linux/irqchip/arm-gic.h>
 
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
@@ -37,13 +36,6 @@ static DEFINE_SPINLOCK(boot_lock);
 void __cpuinit versatile_secondary_init(unsigned int cpu)
 {
         /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-
-        /*
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 831e1fdfdb2f..a10297da122b 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -16,7 +16,7 @@
 # are merged into mainline or have been edited in the machine database
 # within the last 12 months.  References to machine_is_NAME() do not count!
 #
-# Last update: Thu Apr 26 08:44:23 2012
+# Last update: Fri Mar 22 17:24:50 2013
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -64,8 +64,8 @@ h7201			ARCH_H7201		H7201			161
 h7202                   ARCH_H7202              H7202                   162
 iq80321                 ARCH_IQ80321            IQ80321                 169
 ks8695                  ARCH_KS8695             KS8695                  180
-karo                    ARCH_KARO               KARO                    190
 smdk2410                ARCH_SMDK2410           SMDK2410                193
+ceiva                   ARCH_CEIVA              CEIVA                   200
 voiceblue               MACH_VOICEBLUE          VOICEBLUE               218
 h5400                   ARCH_H5400              H5400                   220
 omap_innovator          MACH_OMAP_INNOVATOR     OMAP_INNOVATOR          234
@@ -95,6 +95,7 @@ lpd7a400		MACH_LPD7A400		LPD7A400		389
 lpd7a404                MACH_LPD7A404           LPD7A404                390
 csb337                  MACH_CSB337             CSB337                  399
 mainstone               MACH_MAINSTONE          MAINSTONE               406
+lite300                 MACH_LITE300            LITE300                 408
 xcep                    MACH_XCEP               XCEP                    413
 arcom_vulcan            MACH_ARCOM_VULCAN       ARCOM_VULCAN            414
 nomadik                 MACH_NOMADIK            NOMADIK                 420
@@ -131,12 +132,14 @@ kb9200			MACH_KB9200		KB9200			612
 sx1                     MACH_SX1                SX1                     613
 ixdp465                 MACH_IXDP465            IXDP465                 618
 ixdp2351                MACH_IXDP2351           IXDP2351                619
+cm4008                  MACH_CM4008             CM4008                  624
 iq80332                 MACH_IQ80332            IQ80332                 629
 gtwx5715                MACH_GTWX5715           GTWX5715                641
 csb637                  MACH_CSB637             CSB637                  648
 n30                     MACH_N30                N30                     656
 nec_mp900               MACH_NEC_MP900          NEC_MP900               659
 kafa                    MACH_KAFA               KAFA                    662
+cm41xx                  MACH_CM41XX             CM41XX                  672
 ts72xx                  MACH_TS72XX             TS72XX                  673
 otom                    MACH_OTOM               OTOM                    680
 nexcoder_2440           MACH_NEXCODER_2440      NEXCODER_2440           681
@@ -149,6 +152,7 @@ colibri			MACH_COLIBRI		COLIBRI			729
 gateway7001             MACH_GATEWAY7001        GATEWAY7001             731
 pcm027                  MACH_PCM027             PCM027                  732
 anubis                  MACH_ANUBIS             ANUBIS                  734
+xboardgp8               MACH_XBOARDGP8          XBOARDGP8               742
 akita                   MACH_AKITA              AKITA                   744
 e330                    MACH_E330               E330                    753
 nokia770                MACH_NOKIA770           NOKIA770                755
@@ -157,9 +161,11 @@ edb9315a		MACH_EDB9315A		EDB9315A		772
 stargate2               MACH_STARGATE2          STARGATE2               774
 intelmote2              MACH_INTELMOTE2         INTELMOTE2              775
 trizeps4                MACH_TRIZEPS4           TRIZEPS4                776
+pnx4008                 MACH_PNX4008            PNX4008                 782
 cpuat91                 MACH_CPUAT91            CPUAT91                 787
 iq81340sc               MACH_IQ81340SC          IQ81340SC               799
 iq81340mc               MACH_IQ81340MC          IQ81340MC               801
+se4200                  MACH_SE4200             SE4200                  809
 micro9                  MACH_MICRO9             MICRO9                  811
 micro9l                 MACH_MICRO9L            MICRO9L                 812
 omap_palmte             MACH_OMAP_PALMTE        OMAP_PALMTE             817
@@ -178,6 +184,7 @@ mx21ads			MACH_MX21ADS		MX21ADS			851
 ams_delta               MACH_AMS_DELTA          AMS_DELTA               862
 nas100d                 MACH_NAS100D            NAS100D                 865
 magician                MACH_MAGICIAN           MAGICIAN                875
+cm4002                  MACH_CM4002             CM4002                  876
 nxdkn                   MACH_NXDKN              NXDKN                   880
 palmtx                  MACH_PALMTX             PALMTX                  885
 s3c2413                 MACH_S3C2413            S3C2413                 887
@@ -203,7 +210,6 @@ omap_fsample		MACH_OMAP_FSAMPLE	OMAP_FSAMPLE		970
 snapper_cl15            MACH_SNAPPER_CL15       SNAPPER_CL15            986
 omap_palmz71            MACH_OMAP_PALMZ71       OMAP_PALMZ71            993
 smdk2412                MACH_SMDK2412           SMDK2412                1009
-bkde303                 MACH_BKDE303            BKDE303                 1021
 smdk2413                MACH_SMDK2413           SMDK2413                1022
 aml_m5900               MACH_AML_M5900          AML_M5900               1024
 balloon3                MACH_BALLOON3           BALLOON3                1029
@@ -214,6 +220,7 @@ fsg			MACH_FSG		FSG			1091
 at91sam9260ek           MACH_AT91SAM9260EK      AT91SAM9260EK           1099
 glantank                MACH_GLANTANK           GLANTANK                1100
 n2100                   MACH_N2100              N2100                   1101
+im42xx                  MACH_IM42XX             IM42XX                  1105
 qt2410                  MACH_QT2410             QT2410                  1108
 kixrp435                MACH_KIXRP435           KIXRP435                1109
 cc9p9360dev             MACH_CC9P9360DEV        CC9P9360DEV             1114
@@ -247,6 +254,7 @@ csb726			MACH_CSB726		CSB726			1359
 davinci_dm6467_evm      MACH_DAVINCI_DM6467_EVM DAVINCI_DM6467_EVM      1380
 davinci_dm355_evm       MACH_DAVINCI_DM355_EVM  DAVINCI_DM355_EVM       1381
 littleton               MACH_LITTLETON          LITTLETON               1388
+im4004                  MACH_IM4004             IM4004                  1400
 realview_pb11mp         MACH_REALVIEW_PB11MP    REALVIEW_PB11MP         1407
 mx27_3ds                MACH_MX27_3DS           MX27_3DS                1430
 halibut                 MACH_HALIBUT            HALIBUT                 1439
@@ -268,6 +276,7 @@ dns323			MACH_DNS323		DNS323			1542
 omap3_beagle            MACH_OMAP3_BEAGLE       OMAP3_BEAGLE            1546
 nokia_n810              MACH_NOKIA_N810         NOKIA_N810              1548
 pcm038                  MACH_PCM038             PCM038                  1551
+sg310                   MACH_SG310              SG310                   1564
 ts209                   MACH_TS209              TS209                   1565
 at91cap9adk             MACH_AT91CAP9ADK        AT91CAP9ADK             1566
 mx31moboard             MACH_MX31MOBOARD        MX31MOBOARD             1574
@@ -371,7 +380,6 @@ pcm043			MACH_PCM043		PCM043			2072
 sheevaplug              MACH_SHEEVAPLUG         SHEEVAPLUG              2097
 avengers_lite           MACH_AVENGERS_LITE      AVENGERS_LITE           2104
 mx51_babbage            MACH_MX51_BABBAGE       MX51_BABBAGE            2125
-tx37                    MACH_TX37               TX37                    2127
 rd78x00_masa            MACH_RD78X00_MASA       RD78X00_MASA            2135
 dm355_leopard           MACH_DM355_LEOPARD      DM355_LEOPARD           2138
 ts219                   MACH_TS219              TS219                   2139
@@ -380,12 +388,12 @@ davinci_da850_evm	MACH_DAVINCI_DA850_EVM	DAVINCI_DA850_EVM	2157
 at91sam9g10ek           MACH_AT91SAM9G10EK      AT91SAM9G10EK           2159
 omap_4430sdp            MACH_OMAP_4430SDP       OMAP_4430SDP            2160
 magx_zn5                MACH_MAGX_ZN5           MAGX_ZN5                2162
-tx25                    MACH_TX25               TX25                    2177
 omap3_torpedo           MACH_OMAP3_TORPEDO      OMAP3_TORPEDO           2178
 anw6410                 MACH_ANW6410            ANW6410                 2183
 imx27_visstrim_m10      MACH_IMX27_VISSTRIM_M10 IMX27_VISSTRIM_M10      2187
 portuxg20               MACH_PORTUXG20          PORTUXG20               2191
 smdkc110                MACH_SMDKC110           SMDKC110                2193
+cabespresso             MACH_CABESPRESSO        CABESPRESSO             2194
 omap3517evm             MACH_OMAP3517EVM        OMAP3517EVM             2200
 netspace_v2             MACH_NETSPACE_V2        NETSPACE_V2             2201
 netspace_max_v2         MACH_NETSPACE_MAX_V2    NETSPACE_MAX_V2         2202
@@ -404,6 +412,7 @@ bigdisk			MACH_BIGDISK		BIGDISK			2283
 at91sam9g20ek_2mmc      MACH_AT91SAM9G20EK_2MMC AT91SAM9G20EK_2MMC      2288
 bcmring                 MACH_BCMRING            BCMRING                 2289
 mahimahi                MACH_MAHIMAHI           MAHIMAHI                2304
+cerebric                MACH_CEREBRIC           CEREBRIC                2311
 smdk6442                MACH_SMDK6442           SMDK6442                2324
 openrd_base             MACH_OPENRD_BASE        OPENRD_BASE             2325
 devkit8000              MACH_DEVKIT8000         DEVKIT8000              2330
@@ -423,10 +432,10 @@ raumfeld_rc		MACH_RAUMFELD_RC	RAUMFELD_RC		2413
 raumfeld_connector      MACH_RAUMFELD_CONNECTOR RAUMFELD_CONNECTOR      2414
 raumfeld_speaker        MACH_RAUMFELD_SPEAKER   RAUMFELD_SPEAKER        2415
 tnetv107x               MACH_TNETV107X          TNETV107X               2418
-mx51_m2id               MACH_MX51_M2ID          MX51_M2ID               2428
 smdkv210                MACH_SMDKV210           SMDKV210                2456
 omap_zoom3              MACH_OMAP_ZOOM3         OMAP_ZOOM3              2464
 omap_3630sdp            MACH_OMAP_3630SDP       OMAP_3630SDP            2465
+cybook2440              MACH_CYBOOK2440         CYBOOK2440              2466
 smartq7                 MACH_SMARTQ7            SMARTQ7                 2479
 watson_efm_plugin       MACH_WATSON_EFM_PLUGIN  WATSON_EFM_PLUGIN       2491
 g4evm                   MACH_G4EVM              G4EVM                   2493
@@ -434,12 +443,10 @@ omapl138_hawkboard	MACH_OMAPL138_HAWKBOARD	OMAPL138_HAWKBOARD	2495
 ts41x                   MACH_TS41X              TS41X                   2502
 phy3250                 MACH_PHY3250            PHY3250                 2511
 mini6410                MACH_MINI6410           MINI6410                2520
-tx51                    MACH_TX51               TX51                    2529
 mx28evk                 MACH_MX28EVK            MX28EVK                 2531
 smartq5                 MACH_SMARTQ5            SMARTQ5                 2534
 davinci_dm6467tevm      MACH_DAVINCI_DM6467TEVM DAVINCI_DM6467TEVM      2548
 mxt_td60                MACH_MXT_TD60           MXT_TD60                2550
-pca101                  MACH_PCA101             PCA101                  2595
 capc7117                MACH_CAPC7117           CAPC7117                2612
 icontrol                MACH_ICONTROL           ICONTROL                2624
 gplugd                  MACH_GPLUGD             GPLUGD                  2625
@@ -465,6 +472,7 @@ igep0030		MACH_IGEP0030		IGEP0030		2717
 sbc3530                 MACH_SBC3530            SBC3530                 2722
 saarb                   MACH_SAARB              SAARB                   2727
 harmony                 MACH_HARMONY            HARMONY                 2731
+cybook_orizon           MACH_CYBOOK_ORIZON      CYBOOK_ORIZON           2733
 msm7x30_fluid           MACH_MSM7X30_FLUID      MSM7X30_FLUID           2741
 cm_t3517                MACH_CM_T3517           CM_T3517                2750
 wbd222                  MACH_WBD222             WBD222                  2753
@@ -480,10 +488,8 @@ eukrea_cpuimx35sd	MACH_EUKREA_CPUIMX35SD	EUKREA_CPUIMX35SD	2821
 eukrea_cpuimx51sd       MACH_EUKREA_CPUIMX51SD  EUKREA_CPUIMX51SD       2822
 eukrea_cpuimx51         MACH_EUKREA_CPUIMX51    EUKREA_CPUIMX51         2823
 smdkc210                MACH_SMDKC210           SMDKC210                2838
-pcaal1                  MACH_PCAAL1             PCAAL1                  2843
 t5325                   MACH_T5325              T5325                   2846
 income                  MACH_INCOME             INCOME                  2849
-mx257sx                 MACH_MX257SX            MX257SX                 2861
 goni                    MACH_GONI               GONI                    2862
 bv07                    MACH_BV07               BV07                    2882
 openrd_ultimate         MACH_OPENRD_ULTIMATE    OPENRD_ULTIMATE         2884
@@ -491,7 +497,6 @@ devixp			MACH_DEVIXP		DEVIXP			2885
 miccpt                  MACH_MICCPT             MICCPT                  2886
 mic256                  MACH_MIC256             MIC256                  2887
 u5500                   MACH_U5500              U5500                   2890
-pov15hd                 MACH_POV15HD            POV15HD                 2910
 linkstation_lschl       MACH_LINKSTATION_LSCHL  LINKSTATION_LSCHL       2913
 smdkv310                MACH_SMDKV310           SMDKV310                2925
 wm8505_7in_netbook      MACH_WM8505_7IN_NETBOOK WM8505_7IN_NETBOOK      2928
@@ -518,7 +523,6 @@ prima2_evb		MACH_PRIMA2_EVB		PRIMA2_EVB		3103
 paz00                   MACH_PAZ00              PAZ00                   3128
 acmenetusfoxg20         MACH_ACMENETUSFOXG20    ACMENETUSFOXG20         3129
 ag5evm                  MACH_AG5EVM             AG5EVM                  3189
-tsunagi                 MACH_TSUNAGI            TSUNAGI                 3197
 ics_if_voip             MACH_ICS_IF_VOIP        ICS_IF_VOIP             3206
 wlf_cragg_6410          MACH_WLF_CRAGG_6410     WLF_CRAGG_6410          3207
 trimslice               MACH_TRIMSLICE          TRIMSLICE               3209
@@ -529,8 +533,6 @@ msm8960_sim		MACH_MSM8960_SIM	MSM8960_SIM		3230
 msm8960_rumi3           MACH_MSM8960_RUMI3      MSM8960_RUMI3           3231
 gsia18s                 MACH_GSIA18S            GSIA18S                 3234
 mx53_loco               MACH_MX53_LOCO          MX53_LOCO               3273
-tx53                    MACH_TX53               TX53                    3279
-encore                  MACH_ENCORE             ENCORE                  3284
 wario                   MACH_WARIO              WARIO                   3288
 cm_t3730                MACH_CM_T3730           CM_T3730                3290
 hrefv60                 MACH_HREFV60            HREFV60                 3293
@@ -538,603 +540,24 @@ armlex4210		MACH_ARMLEX4210		ARMLEX4210		3361
 snowball                MACH_SNOWBALL           SNOWBALL                3363
 xilinx_ep107            MACH_XILINX_EP107       XILINX_EP107            3378
 nuri                    MACH_NURI               NURI                    3379
-wtplug                  MACH_WTPLUG             WTPLUG                  3412
-veridis_a300            MACH_VERIDIS_A300       VERIDIS_A300            3448
 origen                  MACH_ORIGEN             ORIGEN                  3455
-wm8650refboard          MACH_WM8650REFBOARD     WM8650REFBOARD          3472
-xarina                  MACH_XARINA             XARINA                  3476
-sdvr                    MACH_SDVR               SDVR                    3478
-acer_maya               MACH_ACER_MAYA          ACER_MAYA               3479
-pico                    MACH_PICO               PICO                    3480
-cwmx233                 MACH_CWMX233            CWMX233                 3481
-cwam1808                MACH_CWAM1808           CWAM1808                3482
-cwdm365                 MACH_CWDM365            CWDM365                 3483
-mx51_moray              MACH_MX51_MORAY         MX51_MORAY              3484
-thales_cbc              MACH_THALES_CBC         THALES_CBC              3485
-bluepoint               MACH_BLUEPOINT          BLUEPOINT               3486
-dir665                  MACH_DIR665             DIR665                  3487
-acmerover1              MACH_ACMEROVER1         ACMEROVER1              3488
-shooter_ct              MACH_SHOOTER_CT         SHOOTER_CT              3489
-bliss                   MACH_BLISS              BLISS                   3490
-blissc                  MACH_BLISSC             BLISSC                  3491
-thales_adc              MACH_THALES_ADC         THALES_ADC              3492
-ubisys_p9d_evp          MACH_UBISYS_P9D_EVP     UBISYS_P9D_EVP          3493
-atdgp318                MACH_ATDGP318           ATDGP318                3494
-dma210u                 MACH_DMA210U            DMA210U                 3495
-em_t3                   MACH_EM_T3              EM_T3                   3496
-htx3250                 MACH_HTX3250            HTX3250                 3497
-g50                     MACH_G50                G50                     3498
-eco5                    MACH_ECO5               ECO5                    3499
-wintergrasp             MACH_WINTERGRASP        WINTERGRASP             3500
-puro                    MACH_PURO               PURO                    3501
-shooter_k               MACH_SHOOTER_K          SHOOTER_K               3502
 nspire                  MACH_NSPIRE             NSPIRE                  3503
-mickxx                  MACH_MICKXX             MICKXX                  3504
-lxmb                    MACH_LXMB               LXMB                    3505
-adam                    MACH_ADAM               ADAM                    3507
-b1004                   MACH_B1004              B1004                   3508
-oboea                   MACH_OBOEA              OBOEA                   3509
-a1015                   MACH_A1015              A1015                   3510
-robin_vbdt30            MACH_ROBIN_VBDT30       ROBIN_VBDT30            3511
-tegra_enterprise        MACH_TEGRA_ENTERPRISE   TEGRA_ENTERPRISE        3512
-rfl108200_mk10          MACH_RFL108200_MK10     RFL108200_MK10          3513
-rfl108300_mk16          MACH_RFL108300_MK16     RFL108300_MK16          3514
-rover_v7                MACH_ROVER_V7           ROVER_V7                3515
-miphone                 MACH_MIPHONE            MIPHONE                 3516
-femtobts                MACH_FEMTOBTS           FEMTOBTS                3517
-monopoli                MACH_MONOPOLI           MONOPOLI                3518
-boss                    MACH_BOSS               BOSS                    3519
-davinci_dm368_vtam      MACH_DAVINCI_DM368_VTAM DAVINCI_DM368_VTAM      3520
-clcon                   MACH_CLCON              CLCON                   3521
 nokia_rm696             MACH_NOKIA_RM696        NOKIA_RM696             3522
-tahiti                  MACH_TAHITI             TAHITI                  3523
-fighter                 MACH_FIGHTER            FIGHTER                 3524
-sgh_i710                MACH_SGH_I710           SGH_I710                3525
-integreproscb           MACH_INTEGREPROSCB      INTEGREPROSCB           3526
-monza                   MACH_MONZA              MONZA                   3527
-calimain                MACH_CALIMAIN           CALIMAIN                3528
-mx6q_sabreauto          MACH_MX6Q_SABREAUTO     MX6Q_SABREAUTO          3529
-gma01x                  MACH_GMA01X             GMA01X                  3530
-sbc51                   MACH_SBC51              SBC51                   3531
-fit                     MACH_FIT                FIT                     3532
-steelhead               MACH_STEELHEAD          STEELHEAD               3533
-panther                 MACH_PANTHER            PANTHER                 3534
-msm8960_liquid          MACH_MSM8960_LIQUID     MSM8960_LIQUID          3535
-lexikonct               MACH_LEXIKONCT          LEXIKONCT               3536
-ns2816_stb              MACH_NS2816_STB         NS2816_STB              3537
-sei_mm2_lpc3250         MACH_SEI_MM2_LPC3250    SEI_MM2_LPC3250         3538
-cmimx53                 MACH_CMIMX53            CMIMX53                 3539
-sandwich                MACH_SANDWICH           SANDWICH                3540
-chief                   MACH_CHIEF              CHIEF                   3541
-pogo_e02                MACH_POGO_E02           POGO_E02                3542
 mikrap_x168             MACH_MIKRAP_X168        MIKRAP_X168             3543
-htcmozart               MACH_HTCMOZART          HTCMOZART               3544
-htcgold                 MACH_HTCGOLD            HTCGOLD                 3545
-mt72xx                  MACH_MT72XX             MT72XX                  3546
-mx51_ivy                MACH_MX51_IVY           MX51_IVY                3547
-mx51_lvd                MACH_MX51_LVD           MX51_LVD                3548
-omap3_wiser2            MACH_OMAP3_WISER2       OMAP3_WISER2            3549
-dreamplug               MACH_DREAMPLUG          DREAMPLUG               3550
-cobas_c_111             MACH_COBAS_C_111        COBAS_C_111             3551
-cobas_u_411             MACH_COBAS_U_411        COBAS_U_411             3552
-hssd                    MACH_HSSD               HSSD                    3553
-iom35x                  MACH_IOM35X             IOM35X                  3554
-psom_omap               MACH_PSOM_OMAP          PSOM_OMAP               3555
-iphone_2g               MACH_IPHONE_2G          IPHONE_2G               3556
-iphone_3g               MACH_IPHONE_3G          IPHONE_3G               3557
-ipod_touch_1g           MACH_IPOD_TOUCH_1G      IPOD_TOUCH_1G           3558
-pharos_tpc              MACH_PHAROS_TPC         PHAROS_TPC              3559
-mx53_hydra              MACH_MX53_HYDRA         MX53_HYDRA              3560
-ns2816_dev_board        MACH_NS2816_DEV_BOARD   NS2816_DEV_BOARD        3561
-iphone_3gs              MACH_IPHONE_3GS         IPHONE_3GS              3562
-iphone_4                MACH_IPHONE_4           IPHONE_4                3563
-ipod_touch_4g           MACH_IPOD_TOUCH_4G      IPOD_TOUCH_4G           3564
-dragon_e1100            MACH_DRAGON_E1100       DRAGON_E1100            3565
-topside                 MACH_TOPSIDE            TOPSIDE                 3566
-irisiii                 MACH_IRISIII            IRISIII                 3567
 deto_macarm9            MACH_DETO_MACARM9       DETO_MACARM9            3568
-eti_d1                  MACH_ETI_D1             ETI_D1                  3569
-som3530sdk              MACH_SOM3530SDK         SOM3530SDK              3570
-oc_engine               MACH_OC_ENGINE          OC_ENGINE               3571
-apq8064_sim             MACH_APQ8064_SIM        APQ8064_SIM             3572
-alps                    MACH_ALPS               ALPS                    3575
-tny_t3730               MACH_TNY_T3730          TNY_T3730               3576
-geryon_nfe              MACH_GERYON_NFE         GERYON_NFE              3577
-ns2816_ref_board        MACH_NS2816_REF_BOARD   NS2816_REF_BOARD        3578
-silverstone             MACH_SILVERSTONE        SILVERSTONE             3579
-mtt2440                 MACH_MTT2440            MTT2440                 3580
-ynicdb                  MACH_YNICDB             YNICDB                  3581
-bct                     MACH_BCT                BCT                     3582
-tuscan                  MACH_TUSCAN             TUSCAN                  3583
-xbt_sam9g45             MACH_XBT_SAM9G45        XBT_SAM9G45             3584
-enbw_cmc                MACH_ENBW_CMC           ENBW_CMC                3585
-ch104mx257              MACH_CH104MX257         CH104MX257              3587
-openpri                 MACH_OPENPRI            OPENPRI                 3588
-am335xevm               MACH_AM335XEVM          AM335XEVM               3589
-picodmb                 MACH_PICODMB            PICODMB                 3590
-waluigi                 MACH_WALUIGI            WALUIGI                 3591
-punicag7                MACH_PUNICAG7           PUNICAG7                3592
-ipad_1g                 MACH_IPAD_1G            IPAD_1G                 3593
-appletv_2g              MACH_APPLETV_2G         APPLETV_2G              3594
-mach_ecog45             MACH_MACH_ECOG45        MACH_ECOG45             3595
-ait_cam_enc_4xx         MACH_AIT_CAM_ENC_4XX    AIT_CAM_ENC_4XX         3596
-runnymede               MACH_RUNNYMEDE          RUNNYMEDE               3597
-play                    MACH_PLAY               PLAY                    3598
-hw90260                 MACH_HW90260            HW90260                 3599
-tagh                    MACH_TAGH               TAGH                    3600
-filbert                 MACH_FILBERT            FILBERT                 3601
-getinge_netcomv3        MACH_GETINGE_NETCOMV3   GETINGE_NETCOMV3        3602
-cw20                    MACH_CW20               CW20                    3603
-cinema                  MACH_CINEMA             CINEMA                  3604
-cinema_tea              MACH_CINEMA_TEA         CINEMA_TEA              3605
-cinema_coffee           MACH_CINEMA_COFFEE      CINEMA_COFFEE           3606
-cinema_juice            MACH_CINEMA_JUICE       CINEMA_JUICE            3607
-mx53_mirage2            MACH_MX53_MIRAGE2       MX53_MIRAGE2            3609
-mx53_efikasb            MACH_MX53_EFIKASB       MX53_EFIKASB            3610
-stm_b2000               MACH_STM_B2000          STM_B2000               3612
 m28evk                  MACH_M28EVK             M28EVK                  3613
-pda                     MACH_PDA                PDA                     3614
-meraki_mr58             MACH_MERAKI_MR58        MERAKI_MR58             3615
 kota2                   MACH_KOTA2              KOTA2                   3616
-letcool                 MACH_LETCOOL            LETCOOL                 3617
-mx27iat                 MACH_MX27IAT            MX27IAT                 3618
-apollo_td               MACH_APOLLO_TD          APOLLO_TD               3619
-arena                   MACH_ARENA              ARENA                   3620
-gsngateway              MACH_GSNGATEWAY         GSNGATEWAY              3621
-lf2000                  MACH_LF2000             LF2000                  3622
 bonito                  MACH_BONITO             BONITO                  3623
-asymptote               MACH_ASYMPTOTE          ASYMPTOTE               3624
-bst2brd                 MACH_BST2BRD            BST2BRD                 3625
-tx335s                  MACH_TX335S             TX335S                  3626
-pelco_tesla             MACH_PELCO_TESLA        PELCO_TESLA             3627
-rrhtestplat             MACH_RRHTESTPLAT        RRHTESTPLAT             3628
-vidtonic_pro            MACH_VIDTONIC_PRO       VIDTONIC_PRO            3629
-pl_apollo               MACH_PL_APOLLO          PL_APOLLO               3630
-pl_phoenix              MACH_PL_PHOENIX         PL_PHOENIX              3631
-m28cu3                  MACH_M28CU3             M28CU3                  3632
-vvbox_hd                MACH_VVBOX_HD           VVBOX_HD                3633
-coreware_sam9260_       MACH_COREWARE_SAM9260_  COREWARE_SAM9260_       3634
-marmaduke               MACH_MARMADUKE          MARMADUKE               3635
-amg_xlcore_camera       MACH_AMG_XLCORE_CAMERA  AMG_XLCORE_CAMERA       3636
 omap3_egf               MACH_OMAP3_EGF          OMAP3_EGF               3637
 smdk4212                MACH_SMDK4212           SMDK4212                3638
-dnp9200                 MACH_DNP9200            DNP9200                 3639
-tf101                   MACH_TF101              TF101                   3640
-omap3silvio             MACH_OMAP3SILVIO        OMAP3SILVIO             3641
-picasso2                MACH_PICASSO2           PICASSO2                3642
-vangogh2                MACH_VANGOGH2           VANGOGH2                3643
-olpc_xo_1_75            MACH_OLPC_XO_1_75       OLPC_XO_1_75            3644
-gx400                   MACH_GX400              GX400                   3645
-gs300                   MACH_GS300              GS300                   3646
-acer_a9                 MACH_ACER_A9            ACER_A9                 3647
-vivow_evm               MACH_VIVOW_EVM          VIVOW_EVM               3648
-veloce_cxq              MACH_VELOCE_CXQ         VELOCE_CXQ              3649
-veloce_cxm              MACH_VELOCE_CXM         VELOCE_CXM              3650
-p1852                   MACH_P1852              P1852                   3651
-naxy100                 MACH_NAXY100            NAXY100                 3652
-taishan                 MACH_TAISHAN            TAISHAN                 3653
-touchlink               MACH_TOUCHLINK          TOUCHLINK               3654
-stm32f103ze             MACH_STM32F103ZE        STM32F103ZE             3655
-mcx                     MACH_MCX                MCX                     3656
-stm_nmhdk_fli7610       MACH_STM_NMHDK_FLI7610  STM_NMHDK_FLI7610       3657
-top28x                  MACH_TOP28X             TOP28X                  3658
-okl4vp_microvisor       MACH_OKL4VP_MICROVISOR  OKL4VP_MICROVISOR       3659
-pop                     MACH_POP                POP                     3660
-layer                   MACH_LAYER              LAYER                   3661
-trondheim               MACH_TRONDHEIM          TRONDHEIM               3662
-eva                     MACH_EVA                EVA                     3663
-trust_taurus            MACH_TRUST_TAURUS       TRUST_TAURUS            3664
-ns2816_huashan          MACH_NS2816_HUASHAN     NS2816_HUASHAN          3665
-ns2816_yangcheng        MACH_NS2816_YANGCHENG   NS2816_YANGCHENG        3666
-p852                    MACH_P852               P852                    3667
-flea3                   MACH_FLEA3              FLEA3                   3668
-bowfin                  MACH_BOWFIN             BOWFIN                  3669
-mv88de3100              MACH_MV88DE3100         MV88DE3100              3670
-pia_am35x               MACH_PIA_AM35X          PIA_AM35X               3671
-cedar                   MACH_CEDAR              CEDAR                   3672
-picasso_e               MACH_PICASSO_E          PICASSO_E               3673
-samsung_e60             MACH_SAMSUNG_E60        SAMSUNG_E60             3674
-sdvr_mini               MACH_SDVR_MINI          SDVR_MINI               3676
-omap3_ij3k              MACH_OMAP3_IJ3K         OMAP3_IJ3K              3677
-modasmc1                MACH_MODASMC1           MODASMC1                3678
-apq8064_rumi3           MACH_APQ8064_RUMI3      APQ8064_RUMI3           3679
-matrix506               MACH_MATRIX506          MATRIX506               3680
-msm9615_mtp             MACH_MSM9615_MTP        MSM9615_MTP             3681
-dm36x_spawndc           MACH_DM36X_SPAWNDC      DM36X_SPAWNDC           3682
-sff792                  MACH_SFF792             SFF792                  3683
-am335xiaevm             MACH_AM335XIAEVM        AM335XIAEVM             3684
-g3c2440                 MACH_G3C2440            G3C2440                 3685
-tion270                 MACH_TION270            TION270                 3686
-w22q7arm02              MACH_W22Q7ARM02         W22Q7ARM02              3687
-omap_cat                MACH_OMAP_CAT           OMAP_CAT                3688
-at91sam9n12ek           MACH_AT91SAM9N12EK      AT91SAM9N12EK           3689
-morrison                MACH_MORRISON           MORRISON                3690
-svdu                    MACH_SVDU               SVDU                    3691
-lpp01                   MACH_LPP01              LPP01                   3692
-ubc283                  MACH_UBC283             UBC283                  3693
-zeppelin                MACH_ZEPPELIN           ZEPPELIN                3694
-motus                   MACH_MOTUS              MOTUS                   3695
-neomainboard            MACH_NEOMAINBOARD       NEOMAINBOARD            3696
-devkit3250              MACH_DEVKIT3250         DEVKIT3250              3697
-devkit7000              MACH_DEVKIT7000         DEVKIT7000              3698
-fmc_uic                 MACH_FMC_UIC            FMC_UIC                 3699
-fmc_dcm                 MACH_FMC_DCM            FMC_DCM                 3700
-batwm                   MACH_BATWM              BATWM                   3701
-atlas6cb                MACH_ATLAS6CB           ATLAS6CB                3702
-blue                    MACH_BLUE               BLUE                    3705
-colorado                MACH_COLORADO           COLORADO                3706
-popc                    MACH_POPC               POPC                    3707
-promwad_jade            MACH_PROMWAD_JADE       PROMWAD_JADE            3708
-amp                     MACH_AMP                AMP                     3709
-gnet_amp                MACH_GNET_AMP           GNET_AMP                3710
-toques                  MACH_TOQUES             TOQUES                  3711
 apx4devkit              MACH_APX4DEVKIT         APX4DEVKIT              3712
-dct_storm               MACH_DCT_STORM          DCT_STORM               3713
-owl                     MACH_OWL                OWL                     3715
-cogent_csb1741          MACH_COGENT_CSB1741     COGENT_CSB1741          3716
-adillustra610           MACH_ADILLUSTRA610      ADILLUSTRA610           3718
-ecafe_na04              MACH_ECAFE_NA04         ECAFE_NA04              3719
-popct                   MACH_POPCT              POPCT                   3720
-omap3_helena            MACH_OMAP3_HELENA       OMAP3_HELENA            3721
-ach                     MACH_ACH                ACH                     3722
-module_dtb              MACH_MODULE_DTB         MODULE_DTB              3723
-oslo_elisabeth          MACH_OSLO_ELISABETH     OSLO_ELISABETH          3725
-tt01                    MACH_TT01               TT01                    3726
-msm8930_cdp             MACH_MSM8930_CDP        MSM8930_CDP             3727
-msm8930_mtp             MACH_MSM8930_MTP        MSM8930_MTP             3728
-msm8930_fluid           MACH_MSM8930_FLUID      MSM8930_FLUID           3729
-ltu11                   MACH_LTU11              LTU11                   3730
-am1808_spawnco          MACH_AM1808_SPAWNCO     AM1808_SPAWNCO          3731
-flx6410                 MACH_FLX6410            FLX6410                 3732
-mx6q_qsb                MACH_MX6Q_QSB           MX6Q_QSB                3733
-mx53_plt424             MACH_MX53_PLT424        MX53_PLT424             3734
-jasmine                 MACH_JASMINE            JASMINE                 3735
-l138_owlboard_plus      MACH_L138_OWLBOARD_PLUS L138_OWLBOARD_PLUS      3736
-wr21                    MACH_WR21               WR21                    3737
-peaboy                  MACH_PEABOY             PEABOY                  3739
-mx28_plato              MACH_MX28_PLATO         MX28_PLATO              3740
-kacom2                  MACH_KACOM2             KACOM2                  3741
-slco                    MACH_SLCO               SLCO                    3742
-imx51pico               MACH_IMX51PICO          IMX51PICO               3743
-glink1                  MACH_GLINK1             GLINK1                  3744
-diamond                 MACH_DIAMOND            DIAMOND                 3745
-d9000                   MACH_D9000              D9000                   3746
-w5300e01                MACH_W5300E01           W5300E01                3747
-im6000                  MACH_IM6000             IM6000                  3748
-mx51_fred51             MACH_MX51_FRED51        MX51_FRED51             3749
-stm32f2                 MACH_STM32F2            STM32F2                 3750
-ville                   MACH_VILLE              VILLE                   3751
-ptip_murnau             MACH_PTIP_MURNAU        PTIP_MURNAU             3752
-ptip_classic            MACH_PTIP_CLASSIC       PTIP_CLASSIC            3753
-mx53grb                 MACH_MX53GRB            MX53GRB                 3754
-gagarin                 MACH_GAGARIN            GAGARIN                 3755
-nas2big                 MACH_NAS2BIG            NAS2BIG                 3757
-superfemto              MACH_SUPERFEMTO         SUPERFEMTO              3758
-teufel                  MACH_TEUFEL             TEUFEL                  3759
-dinara                  MACH_DINARA             DINARA                  3760
-vanquish                MACH_VANQUISH           VANQUISH                3761
-zipabox1                MACH_ZIPABOX1           ZIPABOX1                3762
-u9540                   MACH_U9540              U9540                   3763
-jet                     MACH_JET                JET                     3764
 smdk4412                MACH_SMDK4412           SMDK4412                3765
-elite                   MACH_ELITE              ELITE                   3766
-spear320_hmi            MACH_SPEAR320_HMI       SPEAR320_HMI            3767
-ontario                 MACH_ONTARIO            ONTARIO                 3768
-mx6q_sabrelite          MACH_MX6Q_SABRELITE     MX6Q_SABRELITE          3769
-vc200                   MACH_VC200              VC200                   3770
-msm7625a_ffa            MACH_MSM7625A_FFA       MSM7625A_FFA            3771
-msm7625a_surf           MACH_MSM7625A_SURF      MSM7625A_SURF           3772
-benthossbp              MACH_BENTHOSSBP         BENTHOSSBP              3773
-smdk5210                MACH_SMDK5210           SMDK5210                3774
-empq2300                MACH_EMPQ2300           EMPQ2300                3775
-minipos                 MACH_MINIPOS            MINIPOS                 3776
-omap5_sevm              MACH_OMAP5_SEVM         OMAP5_SEVM              3777
-shelter                 MACH_SHELTER            SHELTER                 3778
-omap3_devkit8500        MACH_OMAP3_DEVKIT8500   OMAP3_DEVKIT8500        3779
-edgetd                  MACH_EDGETD             EDGETD                  3780
-copperyard              MACH_COPPERYARD         COPPERYARD              3781
-edge_u                  MACH_EDGE_U             EDGE_U                  3783
-edge_td                 MACH_EDGE_TD            EDGE_TD                 3784
-wdss                    MACH_WDSS               WDSS                    3785
-dl_pb25                 MACH_DL_PB25            DL_PB25                 3786
-dss11                   MACH_DSS11              DSS11                   3787
-cpa                     MACH_CPA                CPA                     3788
-aptp2000                MACH_APTP2000           APTP2000                3789
 marzen                  MACH_MARZEN             MARZEN                  3790
-st_turbine              MACH_ST_TURBINE         ST_TURBINE              3791
-gtl_it3300              MACH_GTL_IT3300         GTL_IT3300              3792
-mx6_mule                MACH_MX6_MULE           MX6_MULE                3793
-v7pxa_dt                MACH_V7PXA_DT           V7PXA_DT                3794
-v7mmp_dt                MACH_V7MMP_DT           V7MMP_DT                3795
-dragon7                 MACH_DRAGON7            DRAGON7                 3796
 krome                   MACH_KROME              KROME                   3797
-oratisdante             MACH_ORATISDANTE        ORATISDANTE             3798
-fathom                  MACH_FATHOM             FATHOM                  3799
-dns325                  MACH_DNS325             DNS325                  3800
-sarnen                  MACH_SARNEN             SARNEN                  3801
-ubisys_g1               MACH_UBISYS_G1          UBISYS_G1               3802
-mx53_pf1                MACH_MX53_PF1           MX53_PF1                3803
-asanti                  MACH_ASANTI             ASANTI                  3804
-volta                   MACH_VOLTA              VOLTA                   3805
-knight                  MACH_KNIGHT             KNIGHT                  3807
-beaglebone              MACH_BEAGLEBONE         BEAGLEBONE              3808
-becker                  MACH_BECKER             BECKER                  3809
-fc360                   MACH_FC360              FC360                   3810
-pmi2_xls                MACH_PMI2_XLS           PMI2_XLS                3811
-taranto                 MACH_TARANTO            TARANTO                 3812
-plutux                  MACH_PLUTUX             PLUTUX                  3813
-ipmp_medcom             MACH_IPMP_MEDCOM        IPMP_MEDCOM             3814
-absolut                 MACH_ABSOLUT            ABSOLUT                 3815
-awpb3                   MACH_AWPB3              AWPB3                   3816
-nfp32xx_dt              MACH_NFP32XX_DT         NFP32XX_DT              3817
-dl_pb53                 MACH_DL_PB53            DL_PB53                 3818
-acu_ii                  MACH_ACU_II             ACU_II                  3819
-avalon                  MACH_AVALON             AVALON                  3820
-sphinx                  MACH_SPHINX             SPHINX                  3821
-titan_t                 MACH_TITAN_T            TITAN_T                 3822
-harvest_boris           MACH_HARVEST_BORIS      HARVEST_BORIS           3823
-mach_msm7x30_m3s        MACH_MACH_MSM7X30_M3S   MACH_MSM7X30_M3S        3824
-smdk5250                MACH_SMDK5250           SMDK5250                3825
-imxt_lite               MACH_IMXT_LITE          IMXT_LITE               3826
-imxt_std                MACH_IMXT_STD           IMXT_STD                3827
-imxt_log                MACH_IMXT_LOG           IMXT_LOG                3828
-imxt_nav                MACH_IMXT_NAV           IMXT_NAV                3829
-imxt_full               MACH_IMXT_FULL          IMXT_FULL               3830
-ag09015                 MACH_AG09015            AG09015                 3831
-am3517_mt_ventoux       MACH_AM3517_MT_VENTOUX  AM3517_MT_VENTOUX       3832
-dp1arm9                 MACH_DP1ARM9            DP1ARM9                 3833
-picasso_m               MACH_PICASSO_M          PICASSO_M               3834
-video_gadget            MACH_VIDEO_GADGET       VIDEO_GADGET            3835
-mtt_om3x                MACH_MTT_OM3X           MTT_OM3X                3836
-mx6q_arm2               MACH_MX6Q_ARM2          MX6Q_ARM2               3837
-picosam9g45             MACH_PICOSAM9G45        PICOSAM9G45             3838
-vpm_dm365               MACH_VPM_DM365          VPM_DM365               3839
-bonfire                 MACH_BONFIRE            BONFIRE                 3840
-mt2p2d                  MACH_MT2P2D             MT2P2D                  3841
-sigpda01                MACH_SIGPDA01           SIGPDA01                3842
-cn27                    MACH_CN27               CN27                    3843
-mx25_cwtap              MACH_MX25_CWTAP         MX25_CWTAP              3844
-apf28                   MACH_APF28              APF28                   3845
-pelco_maxwell           MACH_PELCO_MAXWELL      PELCO_MAXWELL           3846
-ge_phoenix              MACH_GE_PHOENIX         GE_PHOENIX              3847
-empc_a500               MACH_EMPC_A500          EMPC_A500               3848
-ims_arm9                MACH_IMS_ARM9           IMS_ARM9                3849
-mini2416                MACH_MINI2416           MINI2416                3850
-mini2450                MACH_MINI2450           MINI2450                3851
-mini310                 MACH_MINI310            MINI310                 3852
-spear_hurricane         MACH_SPEAR_HURRICANE    SPEAR_HURRICANE         3853
-mt7208                  MACH_MT7208             MT7208                  3854
-lpc178x                 MACH_LPC178X            LPC178X                 3855
-farleys                 MACH_FARLEYS            FARLEYS                 3856
-efm32gg_dk3750          MACH_EFM32GG_DK3750     EFM32GG_DK3750          3857
-zeus_board              MACH_ZEUS_BOARD         ZEUS_BOARD              3858
-cc51                    MACH_CC51               CC51                    3859
-fxi_c210                MACH_FXI_C210           FXI_C210                3860
-msm8627_cdp             MACH_MSM8627_CDP        MSM8627_CDP             3861
-msm8627_mtp             MACH_MSM8627_MTP        MSM8627_MTP             3862
 armadillo800eva         MACH_ARMADILLO800EVA    ARMADILLO800EVA         3863
-primou                  MACH_PRIMOU             PRIMOU                  3864
-primoc                  MACH_PRIMOC             PRIMOC                  3865
-primoct                 MACH_PRIMOCT            PRIMOCT                 3866
-a9500                   MACH_A9500              A9500                   3867
-pluto                   MACH_PLUTO              PLUTO                   3869
-acfx100                 MACH_ACFX100            ACFX100                 3870
-msm8625_rumi3           MACH_MSM8625_RUMI3      MSM8625_RUMI3           3871
-valente                 MACH_VALENTE            VALENTE                 3872
-crfs_rfeye              MACH_CRFS_RFEYE         CRFS_RFEYE              3873
-rfeye                   MACH_RFEYE              RFEYE                   3874
-phidget_sbc3            MACH_PHIDGET_SBC3       PHIDGET_SBC3            3875
-tcw_mika                MACH_TCW_MIKA           TCW_MIKA                3876
-imx28_egf               MACH_IMX28_EGF          IMX28_EGF               3877
-valente_wx              MACH_VALENTE_WX         VALENTE_WX              3878
-huangshans              MACH_HUANGSHANS         HUANGSHANS              3879
-bosphorus1              MACH_BOSPHORUS1         BOSPHORUS1              3880
-prima                   MACH_PRIMA              PRIMA                   3881
-evita_ulk               MACH_EVITA_ULK          EVITA_ULK               3884
-merisc600               MACH_MERISC600          MERISC600               3885
-dolak                   MACH_DOLAK              DOLAK                   3886
-sbc53                   MACH_SBC53              SBC53                   3887
-elite_ulk               MACH_ELITE_ULK          ELITE_ULK               3888
-pov2                    MACH_POV2               POV2                    3889
-ipod_touch_2g           MACH_IPOD_TOUCH_2G      IPOD_TOUCH_2G           3890
-da850_pqab              MACH_DA850_PQAB         DA850_PQAB              3891
-fermi                   MACH_FERMI              FERMI                   3892
-ccardwmx28              MACH_CCARDWMX28         CCARDWMX28              3893
-ccardmx28               MACH_CCARDMX28          CCARDMX28               3894
-fs20_fcm2050            MACH_FS20_FCM2050       FS20_FCM2050            3895
-kinetis                 MACH_KINETIS            KINETIS                 3896
-kai                     MACH_KAI                KAI                     3897
-bcthb2                  MACH_BCTHB2             BCTHB2                  3898
-inels3_cu               MACH_INELS3_CU          INELS3_CU               3899
-da850_apollo            MACH_DA850_APOLLO       DA850_APOLLO            3901
-tracnas                 MACH_TRACNAS            TRACNAS                 3902
-mityarm335x             MACH_MITYARM335X        MITYARM335X             3903
-xcgz7x                  MACH_XCGZ7X             XCGZ7X                  3904
-cubox                   MACH_CUBOX              CUBOX                   3905
-terminator              MACH_TERMINATOR         TERMINATOR              3906
-eye03                   MACH_EYE03              EYE03                   3907
-kota3                   MACH_KOTA3              KOTA3                   3908
-pscpe                   MACH_PSCPE              PSCPE                   3910
-akt1100                 MACH_AKT1100            AKT1100                 3911
-pcaaxl2                 MACH_PCAAXL2            PCAAXL2                 3912
-primodd_ct              MACH_PRIMODD_CT         PRIMODD_CT              3913
-nsbc                    MACH_NSBC               NSBC                    3914
-meson2_skt              MACH_MESON2_SKT         MESON2_SKT              3915
-meson2_ref              MACH_MESON2_REF         MESON2_REF              3916
-ccardwmx28js            MACH_CCARDWMX28JS       CCARDWMX28JS            3917
-ccardmx28js             MACH_CCARDMX28JS        CCARDMX28JS             3918
-indico                  MACH_INDICO             INDICO                  3919
-msm8960dt               MACH_MSM8960DT          MSM8960DT               3920
-primods                 MACH_PRIMODS            PRIMODS                 3921
-beluga_m1388            MACH_BELUGA_M1388       BELUGA_M1388            3922
-primotd                 MACH_PRIMOTD            PRIMOTD                 3923
-varan_master            MACH_VARAN_MASTER       VARAN_MASTER            3924
-primodd                 MACH_PRIMODD            PRIMODD                 3925
-jetduo                  MACH_JETDUO             JETDUO                  3926
 mx53_umobo              MACH_MX53_UMOBO         MX53_UMOBO              3927
-trats                   MACH_TRATS              TRATS                   3928
-starcraft               MACH_STARCRAFT          STARCRAFT               3929
-qseven_tegra2           MACH_QSEVEN_TEGRA2      QSEVEN_TEGRA2           3930
-lichee_sun4i_devbd      MACH_LICHEE_SUN4I_DEVBD LICHEE_SUN4I_DEVBD      3931
-movenow                 MACH_MOVENOW            MOVENOW                 3932
-golf_u                  MACH_GOLF_U             GOLF_U                  3933
-msm7627a_evb            MACH_MSM7627A_EVB       MSM7627A_EVB            3934
-rambo                   MACH_RAMBO              RAMBO                   3935
-golfu                   MACH_GOLFU              GOLFU                   3936
-mango310                MACH_MANGO310           MANGO310                3937
-dns343                  MACH_DNS343             DNS343                  3938
-var_som_om44            MACH_VAR_SOM_OM44       VAR_SOM_OM44            3939
-naon                    MACH_NAON               NAON                    3940
-vp4000                  MACH_VP4000             VP4000                  3941
-impcard                 MACH_IMPCARD            IMPCARD                 3942
-smoovcam                MACH_SMOOVCAM           SMOOVCAM                3943
-cobham3725              MACH_COBHAM3725         COBHAM3725              3944
-cobham3730              MACH_COBHAM3730         COBHAM3730              3945
-cobham3703              MACH_COBHAM3703         COBHAM3703              3946
-quetzal                 MACH_QUETZAL            QUETZAL                 3947
-apq8064_cdp             MACH_APQ8064_CDP        APQ8064_CDP             3948
-apq8064_mtp             MACH_APQ8064_MTP        APQ8064_MTP             3949
-apq8064_fluid           MACH_APQ8064_FLUID      APQ8064_FLUID           3950
-apq8064_liquid          MACH_APQ8064_LIQUID     APQ8064_LIQUID          3951
-mango210                MACH_MANGO210           MANGO210                3952
-mango100                MACH_MANGO100           MANGO100                3953
-mango24                 MACH_MANGO24            MANGO24                 3954
-mango64                 MACH_MANGO64            MANGO64                 3955
-nsa320                  MACH_NSA320             NSA320                  3956
-elv_ccu2                MACH_ELV_CCU2           ELV_CCU2                3957
-triton_x00              MACH_TRITON_X00         TRITON_X00              3958
-triton_1500_2000        MACH_TRITON_1500_2000   TRITON_1500_2000        3959
-pogoplugv4              MACH_POGOPLUGV4         POGOPLUGV4              3960
-venus_cl                MACH_VENUS_CL           VENUS_CL                3961
-vulcano_g20             MACH_VULCANO_G20        VULCANO_G20             3962
-sgs_i9100               MACH_SGS_I9100          SGS_I9100               3963
-stsv2                   MACH_STSV2              STSV2                   3964
-csb1724                 MACH_CSB1724            CSB1724                 3965
-omapl138_lcdk           MACH_OMAPL138_LCDK      OMAPL138_LCDK           3966
-pvd_mx25                MACH_PVD_MX25           PVD_MX25                3968
-meson6_skt              MACH_MESON6_SKT         MESON6_SKT              3969
-meson6_ref              MACH_MESON6_REF         MESON6_REF              3970
-pxm                     MACH_PXM                PXM                     3971
-pogoplugv3              MACH_POGOPLUGV3         POGOPLUGV3              3973
-mlp89626                MACH_MLP89626           MLP89626                3974
-iomegahmndce            MACH_IOMEGAHMNDCE       IOMEGAHMNDCE            3975
-pogoplugv3pci           MACH_POGOPLUGV3PCI      POGOPLUGV3PCI           3976
-bntv250                 MACH_BNTV250            BNTV250                 3977
-mx53_qseven             MACH_MX53_QSEVEN        MX53_QSEVEN             3978
-gtl_it1100              MACH_GTL_IT1100         GTL_IT1100              3979
-mx6q_sabresd            MACH_MX6Q_SABRESD       MX6Q_SABRESD            3980
 mt4                     MACH_MT4                MT4                     3981
-jumbo_d                 MACH_JUMBO_D            JUMBO_D                 3982
-jumbo_i                 MACH_JUMBO_I            JUMBO_I                 3983
-fs20_dmp                MACH_FS20_DMP           FS20_DMP                3984
-dns320                  MACH_DNS320             DNS320                  3985
-mx28bacos               MACH_MX28BACOS          MX28BACOS               3986
-tl80                    MACH_TL80               TL80                    3987
-polatis_nic_1001        MACH_POLATIS_NIC_1001   POLATIS_NIC_1001        3988
-tely                    MACH_TELY               TELY                    3989
 u8520                   MACH_U8520              U8520                   3990
-manta                   MACH_MANTA              MANTA                   3991
-mpq8064_cdp             MACH_MPQ8064_CDP        MPQ8064_CDP             3993
-mpq8064_dtv             MACH_MPQ8064_DTV        MPQ8064_DTV             3995
-dm368som                MACH_DM368SOM           DM368SOM                3996
-gprisb2                 MACH_GPRISB2            GPRISB2                 3997
-chammid                 MACH_CHAMMID            CHAMMID                 3998
-seoul2                  MACH_SEOUL2             SEOUL2                  3999
-omap4_nooktablet        MACH_OMAP4_NOOKTABLET   OMAP4_NOOKTABLET        4000
-aalto                   MACH_AALTO              AALTO                   4001
-metro                   MACH_METRO              METRO                   4002
-cydm3730                MACH_CYDM3730           CYDM3730                4003
-tqma53                  MACH_TQMA53             TQMA53                  4004
-msm7627a_qrd3           MACH_MSM7627A_QRD3      MSM7627A_QRD3           4005
-mx28_canby              MACH_MX28_CANBY         MX28_CANBY              4006
-tiger                   MACH_TIGER              TIGER                   4007
-pcats_9307_type_a       MACH_PCATS_9307_TYPE_A  PCATS_9307_TYPE_A       4008
-pcats_9307_type_o       MACH_PCATS_9307_TYPE_O  PCATS_9307_TYPE_O       4009
-pcats_9307_type_r       MACH_PCATS_9307_TYPE_R  PCATS_9307_TYPE_R       4010
-streamplug              MACH_STREAMPLUG         STREAMPLUG              4011
-icechicken_dev          MACH_ICECHICKEN_DEV     ICECHICKEN_DEV          4012
-hedgehog                MACH_HEDGEHOG           HEDGEHOG                4013
-yusend_obc              MACH_YUSEND_OBC         YUSEND_OBC              4014
-imxninja                MACH_IMXNINJA           IMXNINJA                4015
-omap4_jarod             MACH_OMAP4_JAROD        OMAP4_JAROD             4016
-eco5_pk                 MACH_ECO5_PK            ECO5_PK                 4017
-qj2440                  MACH_QJ2440             QJ2440                  4018
-mx6q_mercury            MACH_MX6Q_MERCURY       MX6Q_MERCURY            4019
-cm6810                  MACH_CM6810             CM6810                  4020
-omap4_torpedo           MACH_OMAP4_TORPEDO      OMAP4_TORPEDO           4021
-nsa310                  MACH_NSA310             NSA310                  4022
-tmx536                  MACH_TMX536             TMX536                  4023
-ktt20                   MACH_KTT20              KTT20                   4024
-dragonix                MACH_DRAGONIX           DRAGONIX                4025
-lungching               MACH_LUNGCHING          LUNGCHING               4026
-bulogics                MACH_BULOGICS           BULOGICS                4027
-mx535_sx                MACH_MX535_SX           MX535_SX                4028
-ngui3250                MACH_NGUI3250           NGUI3250                4029
-salutec_dac             MACH_SALUTEC_DAC        SALUTEC_DAC             4030
-loco                    MACH_LOCO               LOCO                    4031
-ctera_plug_usi          MACH_CTERA_PLUG_USI     CTERA_PLUG_USI          4032
-scepter                 MACH_SCEPTER            SCEPTER                 4033
-sga                     MACH_SGA                SGA                     4034
-p_81_j5                 MACH_P_81_J5            P_81_J5                 4035
-p_81_o4                 MACH_P_81_O4            P_81_O4                 4036
-msm8625_surf            MACH_MSM8625_SURF       MSM8625_SURF            4037
-carallon_shark          MACH_CARALLON_SHARK     CARALLON_SHARK          4038
-ordog                   MACH_ORDOG              ORDOG                   4040
-puente_io               MACH_PUENTE_IO          PUENTE_IO               4041
-msm8625_evb             MACH_MSM8625_EVB        MSM8625_EVB             4042
-ev_am1707               MACH_EV_AM1707          EV_AM1707               4043
-ev_am1707e2             MACH_EV_AM1707E2        EV_AM1707E2             4044
-ev_am3517e2             MACH_EV_AM3517E2        EV_AM3517E2             4045
-calabria                MACH_CALABRIA           CALABRIA                4046
-ev_imx287               MACH_EV_IMX287          EV_IMX287               4047
-erau                    MACH_ERAU               ERAU                    4048
-sichuan                 MACH_SICHUAN            SICHUAN                 4049
-davinci_da850           MACH_DAVINCI_DA850      DAVINCI_DA850           4051
-omap138_trunarc         MACH_OMAP138_TRUNARC    OMAP138_TRUNARC         4052
-bcm4761                 MACH_BCM4761            BCM4761                 4053
-picasso_e2              MACH_PICASSO_E2         PICASSO_E2              4054
-picasso_mf              MACH_PICASSO_MF         PICASSO_MF              4055
-miro                    MACH_MIRO               MIRO                    4056
-at91sam9g20ewon3        MACH_AT91SAM9G20EWON3   AT91SAM9G20EWON3        4057
-yoyo                    MACH_YOYO               YOYO                    4058
-windjkl                 MACH_WINDJKL            WINDJKL                 4059
-monarudo                MACH_MONARUDO           MONARUDO                4060
-batan                   MACH_BATAN              BATAN                   4061
-tadao                   MACH_TADAO              TADAO                   4062
-baso                    MACH_BASO               BASO                    4063
-mahon                   MACH_MAHON              MAHON                   4064
-villec2                 MACH_VILLEC2            VILLEC2                 4065
-asi1230                 MACH_ASI1230            ASI1230                 4066
-alaska                  MACH_ALASKA             ALASKA                  4067
-swarco_shdsl2           MACH_SWARCO_SHDSL2      SWARCO_SHDSL2           4068
-oxrtu                   MACH_OXRTU              OXRTU                   4069
-omap5_panda             MACH_OMAP5_PANDA        OMAP5_PANDA             4070
-c8000                   MACH_C8000              C8000                   4072
-bje_display3_5          MACH_BJE_DISPLAY3_5     BJE_DISPLAY3_5          4073
-picomod7                MACH_PICOMOD7           PICOMOD7                4074
-picocom5                MACH_PICOCOM5           PICOCOM5                4075
-qblissa8                MACH_QBLISSA8           QBLISSA8                4076
-armstonea8              MACH_ARMSTONEA8         ARMSTONEA8              4077
-netdcu14                MACH_NETDCU14           NETDCU14                4078
-at91sam9x5_epiphan      MACH_AT91SAM9X5_EPIPHAN AT91SAM9X5_EPIPHAN      4079
-p2u                     MACH_P2U                P2U                     4080
-doris                   MACH_DORIS              DORIS                   4081
-j49                     MACH_J49                J49                     4082
-vdss2e                  MACH_VDSS2E             VDSS2E                  4083
-vc300                   MACH_VC300              VC300                   4084
-ns115_pad_test          MACH_NS115_PAD_TEST     NS115_PAD_TEST          4085
-ns115_pad_ref           MACH_NS115_PAD_REF      NS115_PAD_REF           4086
-ns115_phone_test        MACH_NS115_PHONE_TEST   NS115_PHONE_TEST        4087
-ns115_phone_ref         MACH_NS115_PHONE_REF    NS115_PHONE_REF         4088
-golfc                   MACH_GOLFC              GOLFC                   4089
-xerox_olympus           MACH_XEROX_OLYMPUS      XEROX_OLYMPUS           4090
-mx6sl_arm2              MACH_MX6SL_ARM2         MX6SL_ARM2              4091
-csb1701_csb1726         MACH_CSB1701_CSB1726    CSB1701_CSB1726         4092
-at91sam9xeek            MACH_AT91SAM9XEEK       AT91SAM9XEEK            4093
-ebv210                  MACH_EBV210             EBV210                  4094
-msm7627a_qrd7           MACH_MSM7627A_QRD7      MSM7627A_QRD7           4095
-svthin                  MACH_SVTHIN             SVTHIN                  4096
-duovero                 MACH_DUOVERO            DUOVERO                 4097
 chupacabra              MACH_CHUPACABRA         CHUPACABRA              4098
 scorpion                MACH_SCORPION           SCORPION                4099
 davinci_he_hmi10        MACH_DAVINCI_HE_HMI10   DAVINCI_HE_HMI10        4100
@@ -1157,7 +580,6 @@ tam335x			MACH_TAM335X		TAM335X			4116
 grouper                 MACH_GROUPER            GROUPER                 4117
 mpcsa21_9g20            MACH_MPCSA21_9G20       MPCSA21_9G20            4118
 m6u_cpu                 MACH_M6U_CPU            M6U_CPU                 4119
-davinci_dp10            MACH_DAVINCI_DP10       DAVINCI_DP10            4120
 ginkgo                  MACH_GINKGO             GINKGO                  4121
 cgt_qmx6                MACH_CGT_QMX6           CGT_QMX6                4122
 profpga                 MACH_PROFPGA            PROFPGA                 4123
@@ -1204,3 +626,384 @@ baileys			MACH_BAILEYS		BAILEYS			4169
 familybox               MACH_FAMILYBOX          FAMILYBOX               4170
 ensemble_mx35           MACH_ENSEMBLE_MX35      ENSEMBLE_MX35           4171
 sc_sps_1                MACH_SC_SPS_1           SC_SPS_1                4172
+ucsimply_sam9260        MACH_UCSIMPLY_SAM9260   UCSIMPLY_SAM9260        4173
+unicorn                 MACH_UNICORN            UNICORN                 4174
+m9g45a                  MACH_M9G45A             M9G45A                  4175
+mtwebif                 MACH_MTWEBIF            MTWEBIF                 4176
+playstone               MACH_PLAYSTONE          PLAYSTONE               4177
+chelsea                 MACH_CHELSEA            CHELSEA                 4178
+bayern                  MACH_BAYERN             BAYERN                  4179
+mitwo                   MACH_MITWO              MITWO                   4180
+mx25_noah               MACH_MX25_NOAH          MX25_NOAH               4181
+stm_b2020               MACH_STM_B2020          STM_B2020               4182
+annax_src               MACH_ANNAX_SRC          ANNAX_SRC               4183
+ionics_stratus          MACH_IONICS_STRATUS     IONICS_STRATUS          4184
+hugo                    MACH_HUGO               HUGO                    4185
+em300                   MACH_EM300              EM300                   4186
+mmp3_qseven             MACH_MMP3_QSEVEN        MMP3_QSEVEN             4187
+bosphorus2              MACH_BOSPHORUS2         BOSPHORUS2              4188
+tt2200                  MACH_TT2200             TT2200                  4189
+ocelot3                 MACH_OCELOT3            OCELOT3                 4190
+tek_cobra               MACH_TEK_COBRA          TEK_COBRA               4191
+protou                  MACH_PROTOU             PROTOU                  4192
+msm8625_evt             MACH_MSM8625_EVT        MSM8625_EVT             4193
+mx53_sellwood           MACH_MX53_SELLWOOD      MX53_SELLWOOD           4194
+somiq_am35              MACH_SOMIQ_AM35         SOMIQ_AM35              4195
+somiq_am37              MACH_SOMIQ_AM37         SOMIQ_AM37              4196
+k2_plc_cl               MACH_K2_PLC_CL          K2_PLC_CL               4197
+tc2                     MACH_TC2                TC2                     4198
+dulex_j                 MACH_DULEX_J            DULEX_J                 4199
+stm_b2044               MACH_STM_B2044          STM_B2044               4200
+deluxe_j                MACH_DELUXE_J           DELUXE_J                4201
+mango2443               MACH_MANGO2443          MANGO2443               4202
+cp2dcg                  MACH_CP2DCG             CP2DCG                  4203
+cp2dtg                  MACH_CP2DTG             CP2DTG                  4204
+cp2dug                  MACH_CP2DUG             CP2DUG                  4205
+var_som_am33            MACH_VAR_SOM_AM33       VAR_SOM_AM33            4206
+pepper                  MACH_PEPPER             PEPPER                  4207
+mango2450               MACH_MANGO2450          MANGO2450               4208
+valente_wx_c9           MACH_VALENTE_WX_C9      VALENTE_WX_C9           4209
+minitv                  MACH_MINITV             MINITV                  4210
+u8540                   MACH_U8540              U8540                   4211
+iv_atlas_i_z7e          MACH_IV_ATLAS_I_Z7E     IV_ATLAS_I_Z7E          4212
+mach_type_sky           MACH_MACH_TYPE_SKY      MACH_TYPE_SKY           4214
+bluesky                 MACH_BLUESKY            BLUESKY                 4215
+ngrouter                MACH_NGROUTER           NGROUTER                4216
+mx53_denetim            MACH_MX53_DENETIM       MX53_DENETIM            4217
+opal                    MACH_OPAL               OPAL                    4218
+gnet_us3gref            MACH_GNET_US3GREF       GNET_US3GREF            4219
+gnet_nc3g               MACH_GNET_NC3G          GNET_NC3G               4220
+gnet_ge3g               MACH_GNET_GE3G          GNET_GE3G               4221
+adp2                    MACH_ADP2               ADP2                    4222
+tqma28                  MACH_TQMA28             TQMA28                  4223
+kacom3                  MACH_KACOM3             KACOM3                  4224
+rrhdemo                 MACH_RRHDEMO            RRHDEMO                 4225
+protodug                MACH_PROTODUG           PROTODUG                4226
+lago                    MACH_LAGO               LAGO                    4227
+ktt30                   MACH_KTT30              KTT30                   4228
+ts43xx                  MACH_TS43XX             TS43XX                  4229
+mx6q_denso              MACH_MX6Q_DENSO         MX6Q_DENSO              4230
+comsat_gsmumts8         MACH_COMSAT_GSMUMTS8    COMSAT_GSMUMTS8         4231
+dreamx                  MACH_DREAMX             DREAMX                  4232
+thunderstonem           MACH_THUNDERSTONEM      THUNDERSTONEM           4233
+yoyopad                 MACH_YOYOPAD            YOYOPAD                 4234
+yoyopatient             MACH_YOYOPATIENT        YOYOPATIENT             4235
+a10l                    MACH_A10L               A10L                    4236
+mq60                    MACH_MQ60               MQ60                    4237
+linkstation_lsql        MACH_LINKSTATION_LSQL   LINKSTATION_LSQL        4238
+am3703gateway           MACH_AM3703GATEWAY      AM3703GATEWAY           4239
+accipiter               MACH_ACCIPITER          ACCIPITER               4240
+magnidug                MACH_MAGNIDUG           MAGNIDUG                4242
+hydra                   MACH_HYDRA              HYDRA                   4243
+sun3i                   MACH_SUN3I              SUN3I                   4244
+stm_b2078               MACH_STM_B2078          STM_B2078               4245
+at91sam9263deskv2       MACH_AT91SAM9263DESKV2  AT91SAM9263DESKV2       4246
+deluxe_r                MACH_DELUXE_R           DELUXE_R                4247
+p_98_v                  MACH_P_98_V             P_98_V                  4248
+p_98_c                  MACH_P_98_C             P_98_C                  4249
+davinci_am18xx_omn      MACH_DAVINCI_AM18XX_OMN DAVINCI_AM18XX_OMN      4250
+socfpga_cyclone5        MACH_SOCFPGA_CYCLONE5   SOCFPGA_CYCLONE5        4251
+cabatuin                MACH_CABATUIN           CABATUIN                4252
+yoyopad_ft              MACH_YOYOPAD_FT         YOYOPAD_FT              4253
+dan2400evb              MACH_DAN2400EVB         DAN2400EVB              4254
+dan3400evb              MACH_DAN3400EVB         DAN3400EVB              4255
+edm_sf_imx6             MACH_EDM_SF_IMX6        EDM_SF_IMX6             4256
+edm_cf_imx6             MACH_EDM_CF_IMX6        EDM_CF_IMX6             4257
+vpos3xx                 MACH_VPOS3XX            VPOS3XX                 4258
+vulcano_9x5             MACH_VULCANO_9X5        VULCANO_9X5             4259
+spmp8000                MACH_SPMP8000           SPMP8000                4260
+catalina                MACH_CATALINA           CATALINA                4261
+rd88f5181l_fe           MACH_RD88F5181L_FE      RD88F5181L_FE           4262
+mx535_mx                MACH_MX535_MX           MX535_MX                4263
+armadillo840            MACH_ARMADILLO840       ARMADILLO840            4264
+spc9000baseboard        MACH_SPC9000BASEBOARD   SPC9000BASEBOARD        4265
+iris                    MACH_IRIS               IRIS                    4266
+protodcg                MACH_PROTODCG           PROTODCG                4267
+palmtree                MACH_PALMTREE           PALMTREE                4268
+novena                  MACH_NOVENA             NOVENA                  4269
+ma_um                   MACH_MA_UM              MA_UM                   4270
+ma_am                   MACH_MA_AM              MA_AM                   4271
+ems348                  MACH_EMS348             EMS348                  4272
+cm_fx6                  MACH_CM_FX6             CM_FX6                  4273
+arndale                 MACH_ARNDALE            ARNDALE                 4274
+q5xr5                   MACH_Q5XR5              Q5XR5                   4275
+willow                  MACH_WILLOW             WILLOW                  4276
+omap3621_odyv3          MACH_OMAP3621_ODYV3     OMAP3621_ODYV3          4277
+omapl138_presonus       MACH_OMAPL138_PRESONUS  OMAPL138_PRESONUS       4278
+dvf99                   MACH_DVF99              DVF99                   4279
+impression_j            MACH_IMPRESSION_J       IMPRESSION_J            4280
+qblissa9                MACH_QBLISSA9           QBLISSA9                4281
+robin_heliview10        MACH_ROBIN_HELIVIEW10   ROBIN_HELIVIEW10        4282
+sun7i                   MACH_SUN7I              SUN7I                   4283
+mx6q_hdmidongle         MACH_MX6Q_HDMIDONGLE    MX6Q_HDMIDONGLE         4284
+mx6_sid2                MACH_MX6_SID2           MX6_SID2                4285
+helios_v3               MACH_HELIOS_V3          HELIOS_V3               4286
+helios_v4               MACH_HELIOS_V4          HELIOS_V4               4287
+q7_imx6                 MACH_Q7_IMX6            Q7_IMX6                 4288
+odroidx                 MACH_ODROIDX            ODROIDX                 4289
+robpro                  MACH_ROBPRO             ROBPRO                  4290
+research59if_mk1        MACH_RESEARCH59IF_MK1   RESEARCH59IF_MK1        4291
+bobsleigh               MACH_BOBSLEIGH          BOBSLEIGH               4292
+dcshgwt3                MACH_DCSHGWT3           DCSHGWT3                4293
+gld1018                 MACH_GLD1018            GLD1018                 4294
+ev10                    MACH_EV10               EV10                    4295
+nitrogen6x              MACH_NITROGEN6X         NITROGEN6X              4296
+p_107_bb                MACH_P_107_BB           P_107_BB                4297
+evita_utl               MACH_EVITA_UTL          EVITA_UTL               4298
+falconwing              MACH_FALCONWING         FALCONWING              4299
+dct3                    MACH_DCT3               DCT3                    4300
+cpx2e_cell              MACH_CPX2E_CELL         CPX2E_CELL              4301
+amiro                   MACH_AMIRO              AMIRO                   4302
+mx6q_brassboard         MACH_MX6Q_BRASSBOARD    MX6Q_BRASSBOARD         4303
+dalmore                 MACH_DALMORE            DALMORE                 4304
+omap3_portal7cp         MACH_OMAP3_PORTAL7CP    OMAP3_PORTAL7CP         4305
+tegra_pluto             MACH_TEGRA_PLUTO        TEGRA_PLUTO             4306
+mx6sl_evk               MACH_MX6SL_EVK          MX6SL_EVK               4307
+m7                      MACH_M7                 M7                      4308
+pxm2                    MACH_PXM2               PXM2                    4309
+haba_knx_lite           MACH_HABA_KNX_LITE      HABA_KNX_LITE           4310
+tai                     MACH_TAI                TAI                     4311
+prototd                 MACH_PROTOTD            PROTOTD                 4312
+dst_tonto               MACH_DST_TONTO          DST_TONTO               4313
+draco                   MACH_DRACO              DRACO                   4314
+dxr2                    MACH_DXR2               DXR2                    4315
+rut                     MACH_RUT                RUT                     4316
+am180x_wsc              MACH_AM180X_WSC         AM180X_WSC              4317
+deluxe_u                MACH_DELUXE_U           DELUXE_U                4318
+deluxe_ul               MACH_DELUXE_UL          DELUXE_UL               4319
+at91sam9260medths       MACH_AT91SAM9260MEDTHS  AT91SAM9260MEDTHS       4320
+matrix516               MACH_MATRIX516          MATRIX516               4321
+vid401x                 MACH_VID401X            VID401X                 4322
+helios_v5               MACH_HELIOS_V5          HELIOS_V5               4323
+playpaq2                MACH_PLAYPAQ2           PLAYPAQ2                4324
+igam                    MACH_IGAM               IGAM                    4325
+amico_i                 MACH_AMICO_I            AMICO_I                 4326
+amico_e                 MACH_AMICO_E            AMICO_E                 4327
+sentient_mm3_ck         MACH_SENTIENT_MM3_CK    SENTIENT_MM3_CK         4328
+smx6                    MACH_SMX6               SMX6                    4329
+pango                   MACH_PANGO              PANGO                   4330
+ns115_stick             MACH_NS115_STICK        NS115_STICK             4331
+bctrm3                  MACH_BCTRM3             BCTRM3                  4332
+doctorws                MACH_DOCTORWS           DOCTORWS                4333
+m2601                   MACH_M2601              M2601                   4334
+vgg1111                 MACH_VGG1111            VGG1111                 4337
+countach                MACH_COUNTACH           COUNTACH                4338
+visstrim_sm20           MACH_VISSTRIM_SM20      VISSTRIM_SM20           4339
+a639                    MACH_A639               A639                    4340
+spacemonkey             MACH_SPACEMONKEY        SPACEMONKEY             4341
+zpdu_stamp              MACH_ZPDU_STAMP         ZPDU_STAMP              4342
+htc_g7_clone            MACH_HTC_G7_CLONE       HTC_G7_CLONE            4343
+ft2080_corvus           MACH_FT2080_CORVUS      FT2080_CORVUS           4344
+fisland                 MACH_FISLAND            FISLAND                 4345
+zpdu                    MACH_ZPDU               ZPDU                    4346
+urt                     MACH_URT                URT                     4347
+conti_ovip              MACH_CONTI_OVIP         CONTI_OVIP              4348
+omapl138_nagra          MACH_OMAPL138_NAGRA     OMAPL138_NAGRA          4349
+da850_at3kp1            MACH_DA850_AT3KP1       DA850_AT3KP1            4350
+da850_at3kp2            MACH_DA850_AT3KP2       DA850_AT3KP2            4351
+surma                   MACH_SURMA              SURMA                   4352
+stm_b2092               MACH_STM_B2092          STM_B2092               4353
+mx535_ycr               MACH_MX535_YCR          MX535_YCR               4354
+m7_wl                   MACH_M7_WL              M7_WL                   4355
+m7_u                    MACH_M7_U               M7_U                    4356
+omap3_stndt_evm         MACH_OMAP3_STNDT_EVM    OMAP3_STNDT_EVM         4357
+m7_wlv                  MACH_M7_WLV             M7_WLV                  4358
+xam3517                 MACH_XAM3517            XAM3517                 4359
+a220                    MACH_A220               A220                    4360
+aclima_odie             MACH_ACLIMA_ODIE        ACLIMA_ODIE             4361
+vibble                  MACH_VIBBLE             VIBBLE                  4362
+k2_u                    MACH_K2_U               K2_U                    4363
+mx53_egf                MACH_MX53_EGF           MX53_EGF                4364
+novpek_imx53            MACH_NOVPEK_IMX53       NOVPEK_IMX53            4365
+novpek_imx6x            MACH_NOVPEK_IMX6X       NOVPEK_IMX6X            4366
+mx25_smartbox           MACH_MX25_SMARTBOX      MX25_SMARTBOX           4367
+eicg6410                MACH_EICG6410           EICG6410                4368
+picasso_e3              MACH_PICASSO_E3         PICASSO_E3              4369
+motonavigator           MACH_MOTONAVIGATOR      MOTONAVIGATOR           4370
+varioconnect2           MACH_VARIOCONNECT2      VARIOCONNECT2           4371
+deluxe_tw               MACH_DELUXE_TW          DELUXE_TW               4372
+kore3                   MACH_KORE3              KORE3                   4374
+mx6s_drs                MACH_MX6S_DRS           MX6S_DRS                4375
+cmimx6                  MACH_CMIMX6             CMIMX6                  4376
+roth                    MACH_ROTH               ROTH                    4377
+eq4ux                   MACH_EQ4UX              EQ4UX                   4378
+x1plus                  MACH_X1PLUS             X1PLUS                  4379
+modimx27                MACH_MODIMX27           MODIMX27                4380
+videon_hduac            MACH_VIDEON_HDUAC       VIDEON_HDUAC            4381
+blackbird               MACH_BLACKBIRD          BLACKBIRD               4382
+runmaster               MACH_RUNMASTER          RUNMASTER               4383
+ceres                   MACH_CERES              CERES                   4384
+nad435                  MACH_NAD435             NAD435                  4385
+ns115_proto_type        MACH_NS115_PROTO_TYPE   NS115_PROTO_TYPE        4386
+fs20_vcc                MACH_FS20_VCC           FS20_VCC                4387
+meson6tv_skt            MACH_MESON6TV_SKT       MESON6TV_SKT            4389
+keystone                MACH_KEYSTONE           KEYSTONE                4390
+pcm052                  MACH_PCM052             PCM052                  4391
+qrd_skud_prime          MACH_QRD_SKUD_PRIME     QRD_SKUD_PRIME          4393
+guf_santaro             MACH_GUF_SANTARO        GUF_SANTARO             4395
+sheepshead              MACH_SHEEPSHEAD         SHEEPSHEAD              4396
+mx6_iwg15m_mxm          MACH_MX6_IWG15M_MXM     MX6_IWG15M_MXM          4397
+mx6_iwg15m_q7           MACH_MX6_IWG15M_Q7      MX6_IWG15M_Q7           4398
+at91sam9263if8mic       MACH_AT91SAM9263IF8MIC  AT91SAM9263IF8MIC       4399
+marcopolo               MACH_MARCOPOLO          MARCOPOLO               4401
+mx535_sdcr              MACH_MX535_SDCR         MX535_SDCR              4402
+mx53_csb2733            MACH_MX53_CSB2733       MX53_CSB2733            4403
+diva                    MACH_DIVA               DIVA                    4404
+ncr_7744                MACH_NCR_7744           NCR_7744                4405
+macallan                MACH_MACALLAN           MACALLAN                4406
+wnr3500                 MACH_WNR3500            WNR3500                 4407
+pgavrf                  MACH_PGAVRF             PGAVRF                  4408
+helios_v6               MACH_HELIOS_V6          HELIOS_V6               4409
+lcct                    MACH_LCCT               LCCT                    4410
+csndug                  MACH_CSNDUG             CSNDUG                  4411
+wandboard_imx6          MACH_WANDBOARD_IMX6     WANDBOARD_IMX6          4412
+omap4_jet               MACH_OMAP4_JET          OMAP4_JET               4413
+tegra_roth              MACH_TEGRA_ROTH         TEGRA_ROTH              4414
+m7dcg                   MACH_M7DCG              M7DCG                   4415
+m7dug                   MACH_M7DUG              M7DUG                   4416
+m7dtg                   MACH_M7DTG              M7DTG                   4417
+ap42x                   MACH_AP42X              AP42X                   4418
+var_som_mx6             MACH_VAR_SOM_MX6        VAR_SOM_MX6             4419
+pdlu                    MACH_PDLU               PDLU                    4420
+hydrogen                MACH_HYDROGEN           HYDROGEN                4421
+npa211e                 MACH_NPA211E            NPA211E                 4422
+arcadia                 MACH_ARCADIA            ARCADIA                 4423
+arcadia_l               MACH_ARCADIA_L          ARCADIA_L               4424
+msm8930dt               MACH_MSM8930DT          MSM8930DT               4425
+ktam3874                MACH_KTAM3874           KTAM3874                4426
+cec4                    MACH_CEC4               CEC4                    4427
+ape6evm                 MACH_APE6EVM            APE6EVM                 4428
+tx6                     MACH_TX6                TX6                     4429
+cfa10037                MACH_CFA10037           CFA10037                4431
+ezp1000                 MACH_EZP1000            EZP1000                 4433
+wgr826v                 MACH_WGR826V            WGR826V                 4434
+exuma                   MACH_EXUMA              EXUMA                   4435
+fregate                 MACH_FREGATE            FREGATE                 4436
+osirisimx508            MACH_OSIRISIMX508       OSIRISIMX508            4437
+st_exigo                MACH_ST_EXIGO           ST_EXIGO                4438
+pismo                   MACH_PISMO              PISMO                   4439
+atc7                    MACH_ATC7               ATC7                    4440
+nspireclp               MACH_NSPIRECLP          NSPIRECLP               4441
+nspiretp                MACH_NSPIRETP           NSPIRETP                4442
+nspirecx                MACH_NSPIRECX           NSPIRECX                4443
+maya                    MACH_MAYA               MAYA                    4444
+wecct                   MACH_WECCT              WECCT                   4445
+m2s                     MACH_M2S                M2S                     4446
+msm8625q_evbd           MACH_MSM8625Q_EVBD      MSM8625Q_EVBD           4447
+tiny210                 MACH_TINY210            TINY210                 4448
+g3                      MACH_G3                 G3                      4449
+hurricane               MACH_HURRICANE          HURRICANE               4450
+mx6_pod                 MACH_MX6_POD            MX6_POD                 4451
+elondcn                 MACH_ELONDCN            ELONDCN                 4452
+cwmx535                 MACH_CWMX535            CWMX535                 4453
+m7_wlj                  MACH_M7_WLJ             M7_WLJ                  4454
+qsp_arm                 MACH_QSP_ARM            QSP_ARM                 4455
+msm8625q_skud           MACH_MSM8625Q_SKUD      MSM8625Q_SKUD           4456
+htcmondrian             MACH_HTCMONDRIAN        HTCMONDRIAN             4457
+watson_ead              MACH_WATSON_EAD         WATSON_EAD              4458
+mitwoa                  MACH_MITWOA             MITWOA                  4459
+omap3_wolverine         MACH_OMAP3_WOLVERINE    OMAP3_WOLVERINE         4460
+mapletree               MACH_MAPLETREE          MAPLETREE               4461
+msm8625_fih_sae         MACH_MSM8625_FIH_SAE    MSM8625_FIH_SAE         4462
+epc35                   MACH_EPC35              EPC35                   4463
+smartrtu                MACH_SMARTRTU           SMARTRTU                4464
+rcm101                  MACH_RCM101             RCM101                  4465
+amx_imx53_mxx           MACH_AMX_IMX53_MXX      AMX_IMX53_MXX           4466
+acer_a12                MACH_ACER_A12           ACER_A12                4470
+sbc6x                   MACH_SBC6X              SBC6X                   4471
+u2                      MACH_U2                 U2                      4472
+smdk4270                MACH_SMDK4270           SMDK4270                4473
+priscillag              MACH_PRISCILLAG         PRISCILLAG              4474
+priscillac              MACH_PRISCILLAC         PRISCILLAC              4475
+priscilla               MACH_PRISCILLA          PRISCILLA               4476
+innova_shpu_v2          MACH_INNOVA_SHPU_V2     INNOVA_SHPU_V2          4477
+mach_type_dep2410       MACH_MACH_TYPE_DEP2410  MACH_TYPE_DEP2410       4479
+bctre3                  MACH_BCTRE3             BCTRE3                  4480
+omap_m100               MACH_OMAP_M100          OMAP_M100               4481
+flo                     MACH_FLO                FLO                     4482
+nanobone                MACH_NANOBONE           NANOBONE                4483
+stm_b2105               MACH_STM_B2105          STM_B2105               4484
+omap4_bsc_bap_v3        MACH_OMAP4_BSC_BAP_V3   OMAP4_BSC_BAP_V3        4485
+ss1pam                  MACH_SS1PAM             SS1PAM                  4486
+primominiu              MACH_PRIMOMINIU         PRIMOMINIU              4488
+mrt_35hd_dualnas_e      MACH_MRT_35HD_DUALNAS_E MRT_35HD_DUALNAS_E      4489
+kiwi                    MACH_KIWI               KIWI                    4490
+hw90496                 MACH_HW90496            HW90496                 4491
+mep2440                 MACH_MEP2440            MEP2440                 4492
+colibri_t30             MACH_COLIBRI_T30        COLIBRI_T30             4493
+cwv1                    MACH_CWV1               CWV1                    4494
+nsa325                  MACH_NSA325             NSA325                  4495
+dpxmtc                  MACH_DPXMTC             DPXMTC                  4497
+tt_stuttgart            MACH_TT_STUTTGART       TT_STUTTGART            4498
+miranda_apcii           MACH_MIRANDA_APCII      MIRANDA_APCII           4499
+mx6q_moderox            MACH_MX6Q_MODEROX       MX6Q_MODEROX            4500
+mudskipper              MACH_MUDSKIPPER         MUDSKIPPER              4501
+urania                  MACH_URANIA             URANIA                  4502
+stm_b2112               MACH_STM_B2112          STM_B2112               4503
+mx6q_ats_phoenix        MACH_MX6Q_ATS_PHOENIX   MX6Q_ATS_PHOENIX        4505
+stm_b2116               MACH_STM_B2116          STM_B2116               4506
+mythology               MACH_MYTHOLOGY          MYTHOLOGY               4507
+fc360v1                 MACH_FC360V1            FC360V1                 4508
+gps_sensor              MACH_GPS_SENSOR         GPS_SENSOR              4509
+gazelle                 MACH_GAZELLE            GAZELLE                 4510
+mpq8064_dma             MACH_MPQ8064_DMA        MPQ8064_DMA             4511
+wems_asd01              MACH_WEMS_ASD01         WEMS_ASD01              4512
+apalis_t30              MACH_APALIS_T30         APALIS_T30              4513
+armstonea9              MACH_ARMSTONEA9         ARMSTONEA9              4515
+omap_blazetablet        MACH_OMAP_BLAZETABLET   OMAP_BLAZETABLET        4516
+ar6mxq                  MACH_AR6MXQ             AR6MXQ                  4517
+ar6mxs                  MACH_AR6MXS             AR6MXS                  4518
+gwventana               MACH_GWVENTANA          GWVENTANA               4520
+igep0033                MACH_IGEP0033           IGEP0033                4521
+h52c1_concerto          MACH_H52C1_CONCERTO     H52C1_CONCERTO          4524
+fcmbrd                  MACH_FCMBRD             FCMBRD                  4525
+pcaaxs1                 MACH_PCAAXS1            PCAAXS1                 4526
+ls_orca                 MACH_LS_ORCA            LS_ORCA                 4527
+pcm051lb                MACH_PCM051LB           PCM051LB                4528
+mx6s_lp507_gvci         MACH_MX6S_LP507_GVCI    MX6S_LP507_GVCI         4529
+dido                    MACH_DIDO               DIDO                    4530
+swarco_itc3_9g20        MACH_SWARCO_ITC3_9G20   SWARCO_ITC3_9G20        4531
+robo_roady              MACH_ROBO_ROADY         ROBO_ROADY              4532
+rskrza1                 MACH_RSKRZA1            RSKRZA1                 4533
+swarco_sid              MACH_SWARCO_SID         SWARCO_SID              4534
+mx6_iwg15s_sbc          MACH_MX6_IWG15S_SBC     MX6_IWG15S_SBC          4535
+mx6q_camaro             MACH_MX6Q_CAMARO        MX6Q_CAMARO             4536
+hb6mxs                  MACH_HB6MXS             HB6MXS                  4537
+lager                   MACH_LAGER              LAGER                   4538
+lp8x4x                  MACH_LP8X4X             LP8X4X                  4539
+tegratab7               MACH_TEGRATAB7          TEGRATAB7               4540
+andromeda               MACH_ANDROMEDA          ANDROMEDA               4541
+bootes                  MACH_BOOTES             BOOTES                  4542
+nethmi                  MACH_NETHMI             NETHMI                  4543
+tegratab                MACH_TEGRATAB           TEGRATAB                4544
+som5_evb                MACH_SOM5_EVB           SOM5_EVB                4545
+venaticorum             MACH_VENATICORUM        VENATICORUM             4546
+stm_b2110               MACH_STM_B2110          STM_B2110               4547
+elux_hathor             MACH_ELUX_HATHOR        ELUX_HATHOR             4548
+helios_v7               MACH_HELIOS_V7          HELIOS_V7               4549
+xc10v1                  MACH_XC10V1             XC10V1                  4550
+cp2u                    MACH_CP2U               CP2U                    4551
+iap_f                   MACH_IAP_F              IAP_F                   4552
+iap_g                   MACH_IAP_G              IAP_G                   4553
+aae                     MACH_AAE                AAE                     4554
+pegasus                 MACH_PEGASUS            PEGASUS                 4555
+cygnus                  MACH_CYGNUS             CYGNUS                  4556
+centaurus               MACH_CENTAURUS          CENTAURUS               4557
+msm8930_qrd8930         MACH_MSM8930_QRD8930    MSM8930_QRD8930         4558
+quby_tim                MACH_QUBY_TIM           QUBY_TIM                4559
+zedi3250a               MACH_ZEDI3250A          ZEDI3250A               4560
+grus                    MACH_GRUS               GRUS                    4561
+apollo3                 MACH_APOLLO3            APOLLO3                 4562
+cowon_r7                MACH_COWON_R7           COWON_R7                4563
+tonga3                  MACH_TONGA3             TONGA3                  4564
+p535                    MACH_P535               P535                    4565
+sa3874i                 MACH_SA3874I            SA3874I                 4566
+mx6_navico_com          MACH_MX6_NAVICO_COM     MX6_NAVICO_COM          4567
+proxmobil2              MACH_PROXMOBIL2         PROXMOBIL2              4568
+ubinux1                 MACH_UBINUX1            UBINUX1                 4569
+istos                   MACH_ISTOS              ISTOS                   4570
+benvolio4               MACH_BENVOLIO4          BENVOLIO4               4571
+eco5_bx2                MACH_ECO5_BX2           ECO5_BX2                4572
+eukrea_cpuimx28sd       MACH_EUKREA_CPUIMX28SD  EUKREA_CPUIMX28SD       4573
+domotab                 MACH_DOMOTAB            DOMOTAB                 4574
+pfla03                  MACH_PFLA03             PFLA03                  4575
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 9b6d19f74078..73b6e764034c 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -99,7 +99,16 @@ source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
 
-menu "System Type"
+menu "Platform selection"
+
+config ARCH_VEXPRESS
+        bool "ARMv8 software model (Versatile Express)"
+        select ARCH_REQUIRE_GPIOLIB
+        select COMMON_CLK_VERSATILE
+        select VEXPRESS_CONFIG
+        help
+          This enables support for the ARMv8 software model (Versatile
+          Express).
 
 endmenu
 
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 32ac0aef0068..68457e9e0975 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,5 @@
+dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
+
 targets += dtbs
 targets += $(dtb-y)
 
diff --git a/arch/arm64/boot/dts/foundation-v8.dts b/arch/arm64/boot/dts/foundation-v8.dts
new file mode 100644
index 000000000000..198682b6de31
--- /dev/null
+++ b/arch/arm64/boot/dts/foundation-v8.dts
@@ -0,0 +1,230 @@
+/*
+ * ARM Ltd.
+ *
+ * ARMv8 Foundation model DTS
+ */
+
+/dts-v1/;
+
+/ {
+        model = "Foundation-v8A";
+        compatible = "arm,foundation-aarch64", "arm,vexpress";
+        interrupt-parent = <&gic>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        chosen { };
+
+        aliases {
+                serial0 = &v2m_serial0;
+                serial1 = &v2m_serial1;
+                serial2 = &v2m_serial2;
+                serial3 = &v2m_serial3;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x0>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x0 0x8000fff8>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x1>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x0 0x8000fff8>;
+                };
+                cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x2>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x0 0x8000fff8>;
+                };
+                cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x3>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x0 0x8000fff8>;
+                };
+        };
+
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0x00000000 0x80000000 0 0x80000000>,
+                      <0x00000008 0x80000000 0 0x80000000>;
+        };
+
+        gic: interrupt-controller@2c001000 {
+                compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0x0 0x2c001000 0 0x1000>,
+                      <0x0 0x2c002000 0 0x1000>,
+                      <0x0 0x2c004000 0 0x2000>,
+                      <0x0 0x2c006000 0 0x2000>;
+                interrupts = <1 9 0xf04>;
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts = <1 13 0xff01>,
+                             <1 14 0xff01>,
+                             <1 11 0xff01>,
+                             <1 10 0xff01>;
+                clock-frequency = <100000000>;
+        };
+
+        pmu {
+                compatible = "arm,armv8-pmuv3";
+                interrupts = <0 60 4>,
+                             <0 61 4>,
+                             <0 62 4>,
+                             <0 63 4>;
+        };
+
+        smb {
+                compatible = "arm,vexpress,v2m-p1", "simple-bus";
+                arm,v2m-memory-map = "rs1";
+                #address-cells = <2>; /* SMB chipselect number and offset */
+                #size-cells = <1>;
+
+                ranges = <0 0 0 0x08000000 0x04000000>,
+                         <1 0 0 0x14000000 0x04000000>,
+                         <2 0 0 0x18000000 0x04000000>,
+                         <3 0 0 0x1c000000 0x04000000>,
+                         <4 0 0 0x0c000000 0x04000000>,
+                         <5 0 0 0x10000000 0x04000000>;
+
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 63>;
+                interrupt-map = <0 0  0 &gic 0  0 4>,
+                                <0 0  1 &gic 0  1 4>,
+                                <0 0  2 &gic 0  2 4>,
+                                <0 0  3 &gic 0  3 4>,
+                                <0 0  4 &gic 0  4 4>,
+                                <0 0  5 &gic 0  5 4>,
+                                <0 0  6 &gic 0  6 4>,
+                                <0 0  7 &gic 0  7 4>,
+                                <0 0  8 &gic 0  8 4>,
+                                <0 0  9 &gic 0  9 4>,
+                                <0 0 10 &gic 0 10 4>,
+                                <0 0 11 &gic 0 11 4>,
+                                <0 0 12 &gic 0 12 4>,
+                                <0 0 13 &gic 0 13 4>,
+                                <0 0 14 &gic 0 14 4>,
+                                <0 0 15 &gic 0 15 4>,
+                                <0 0 16 &gic 0 16 4>,
+                                <0 0 17 &gic 0 17 4>,
+                                <0 0 18 &gic 0 18 4>,
+                                <0 0 19 &gic 0 19 4>,
+                                <0 0 20 &gic 0 20 4>,
+                                <0 0 21 &gic 0 21 4>,
+                                <0 0 22 &gic 0 22 4>,
+                                <0 0 23 &gic 0 23 4>,
+                                <0 0 24 &gic 0 24 4>,
+                                <0 0 25 &gic 0 25 4>,
+                                <0 0 26 &gic 0 26 4>,
+                                <0 0 27 &gic 0 27 4>,
+                                <0 0 28 &gic 0 28 4>,
+                                <0 0 29 &gic 0 29 4>,
+                                <0 0 30 &gic 0 30 4>,
+                                <0 0 31 &gic 0 31 4>,
+                                <0 0 32 &gic 0 32 4>,
+                                <0 0 33 &gic 0 33 4>,
+                                <0 0 34 &gic 0 34 4>,
+                                <0 0 35 &gic 0 35 4>,
+                                <0 0 36 &gic 0 36 4>,
+                                <0 0 37 &gic 0 37 4>,
+                                <0 0 38 &gic 0 38 4>,
+                                <0 0 39 &gic 0 39 4>,
+                                <0 0 40 &gic 0 40 4>,
+                                <0 0 41 &gic 0 41 4>,
+                                <0 0 42 &gic 0 42 4>;
+
+                ethernet@2,02000000 {
+                        compatible = "smsc,lan91c111";
+                        reg = <2 0x02000000 0x10000>;
+                        interrupts = <15>;
+                };
+
+                v2m_clk24mhz: clk24mhz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <24000000>;
+                        clock-output-names = "v2m:clk24mhz";
+                };
+
+                v2m_refclk1mhz: refclk1mhz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <1000000>;
+                        clock-output-names = "v2m:refclk1mhz";
+                };
+
+                v2m_refclk32khz: refclk32khz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                        clock-output-names = "v2m:refclk32khz";
+                };
+
+                iofpga@3,00000000 {
+                        compatible = "arm,amba-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 3 0 0x200000>;
+
+                        v2m_sysreg: sysreg@010000 {
+                                compatible = "arm,vexpress-sysreg";
+                                reg = <0x010000 0x1000>;
+                        };
+
+                        v2m_serial0: uart@090000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x090000 0x1000>;
+                                interrupts = <5>;
+                                clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+                                clock-names = "uartclk", "apb_pclk";
+                        };
+
+                        v2m_serial1: uart@0a0000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x0a0000 0x1000>;
+                                interrupts = <6>;
+                                clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+                                clock-names = "uartclk", "apb_pclk";
+                        };
+
+                        v2m_serial2: uart@0b0000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x0b0000 0x1000>;
+                                interrupts = <7>;
+                                clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+                                clock-names = "uartclk", "apb_pclk";
+                        };
+
+                        v2m_serial3: uart@0c0000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x0c0000 0x1000>;
+                                interrupts = <8>;
+                                clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+                                clock-names = "uartclk", "apb_pclk";
+                        };
+
+                        virtio_block@0130000 {
+                                compatible = "virtio,mmio";
+                                reg = <0x130000 0x1000>;
+                                interrupts = <42>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm64/boot/dts/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/rtsm_ve-aemv8a.dts
new file mode 100644
index 000000000000..572005ea2217
--- /dev/null
+++ b/arch/arm64/boot/dts/rtsm_ve-aemv8a.dts
@@ -0,0 +1,159 @@
+/*
+ * ARM Ltd. Fast Models
+ *
+ * Architecture Envelope Model (AEM) ARMv8-A
+ * ARMAEMv8AMPCT
+ *
+ * RTSM_VE_AEMv8A.lisa
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x80000000 0x00010000;
+
+/ {
+        model = "RTSM_VE_AEMv8A";
+        compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress";
+        interrupt-parent = <&gic>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        chosen { };
+
+        aliases {
+                serial0 = &v2m_serial0;
+                serial1 = &v2m_serial1;
+                serial2 = &v2m_serial2;
+                serial3 = &v2m_serial3;
+        };
+
+        cpus {
+                #address-cells = <2>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x0>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x0 0x8000fff8>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x1>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x0 0x8000fff8>;
+                };
+                cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x2>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x0 0x8000fff8>;
+                };
+                cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x3>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x0 0x8000fff8>;
+                };
+        };
+
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0x00000000 0x80000000 0 0x80000000>,
+                      <0x00000008 0x80000000 0 0x80000000>;
+        };
+
+        gic: interrupt-controller@2c001000 {
+                compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0x0 0x2c001000 0 0x1000>,
+                      <0x0 0x2c002000 0 0x1000>,
+                      <0x0 0x2c004000 0 0x2000>,
+                      <0x0 0x2c006000 0 0x2000>;
+                interrupts = <1 9 0xf04>;
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts = <1 13 0xff01>,
+                             <1 14 0xff01>,
+                             <1 11 0xff01>,
+                             <1 10 0xff01>;
+                clock-frequency = <100000000>;
+        };
+
+        pmu {
+                compatible = "arm,armv8-pmuv3";
+                interrupts = <0 60 4>,
+                             <0 61 4>,
+                             <0 62 4>,
+                             <0 63 4>;
+        };
+
+        smb {
+                compatible = "simple-bus";
+
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <0 0 0 0x08000000 0x04000000>,
+                         <1 0 0 0x14000000 0x04000000>,
+                         <2 0 0 0x18000000 0x04000000>,
+                         <3 0 0 0x1c000000 0x04000000>,
+                         <4 0 0 0x0c000000 0x04000000>,
+                         <5 0 0 0x10000000 0x04000000>;
+
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 63>;
+                interrupt-map = <0 0  0 &gic 0  0 4>,
+                                <0 0  1 &gic 0  1 4>,
+                                <0 0  2 &gic 0  2 4>,
+                                <0 0  3 &gic 0  3 4>,
+                                <0 0  4 &gic 0  4 4>,
+                                <0 0  5 &gic 0  5 4>,
+                                <0 0  6 &gic 0  6 4>,
+                                <0 0  7 &gic 0  7 4>,
+                                <0 0  8 &gic 0  8 4>,
+                                <0 0  9 &gic 0  9 4>,
+                                <0 0 10 &gic 0 10 4>,
+                                <0 0 11 &gic 0 11 4>,
+                                <0 0 12 &gic 0 12 4>,
+                                <0 0 13 &gic 0 13 4>,
+                                <0 0 14 &gic 0 14 4>,
+                                <0 0 15 &gic 0 15 4>,
+                                <0 0 16 &gic 0 16 4>,
+                                <0 0 17 &gic 0 17 4>,
+                                <0 0 18 &gic 0 18 4>,
+                                <0 0 19 &gic 0 19 4>,
+                                <0 0 20 &gic 0 20 4>,
+                                <0 0 21 &gic 0 21 4>,
+                                <0 0 22 &gic 0 22 4>,
+                                <0 0 23 &gic 0 23 4>,
+                                <0 0 24 &gic 0 24 4>,
+                                <0 0 25 &gic 0 25 4>,
+                                <0 0 26 &gic 0 26 4>,
+                                <0 0 27 &gic 0 27 4>,
+                                <0 0 28 &gic 0 28 4>,
+                                <0 0 29 &gic 0 29 4>,
+                                <0 0 30 &gic 0 30 4>,
+                                <0 0 31 &gic 0 31 4>,
+                                <0 0 32 &gic 0 32 4>,
+                                <0 0 33 &gic 0 33 4>,
+                                <0 0 34 &gic 0 34 4>,
+                                <0 0 35 &gic 0 35 4>,
+                                <0 0 36 &gic 0 36 4>,
+                                <0 0 37 &gic 0 37 4>,
+                                <0 0 38 &gic 0 38 4>,
+                                <0 0 39 &gic 0 39 4>,
+                                <0 0 40 &gic 0 40 4>,
+                                <0 0 41 &gic 0 41 4>,
+                                <0 0 42 &gic 0 42 4>;
+
+                /include/ "rtsm_ve-motherboard.dtsi"
+        };
+};
diff --git a/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi
new file mode 100644
index 000000000000..b45e5f39f577
--- /dev/null
+++ b/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi
@@ -0,0 +1,234 @@
+/*
+ * ARM Ltd. Fast Models
+ *
+ * Versatile Express (VE) system model
+ * Motherboard component
+ *
+ * VEMotherBoard.lisa
+ */
+
+        motherboard {
+                arm,v2m-memory-map = "rs1";
+                compatible = "arm,vexpress,v2m-p1", "simple-bus";
+                #address-cells = <2>; /* SMB chipselect number and offset */
+                #size-cells = <1>;
+                #interrupt-cells = <1>;
+                ranges;
+
+                flash@0,00000000 {
+                        compatible = "arm,vexpress-flash", "cfi-flash";
+                        reg = <0 0x00000000 0x04000000>,
+                              <4 0x00000000 0x04000000>;
+                        bank-width = <4>;
+                };
+
+                vram@2,00000000 {
+                        compatible = "arm,vexpress-vram";
+                        reg = <2 0x00000000 0x00800000>;
+                };
+
+                ethernet@2,02000000 {
+                        compatible = "smsc,lan91c111";
+                        reg = <2 0x02000000 0x10000>;
+                        interrupts = <15>;
+                };
+
+                v2m_clk24mhz: clk24mhz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <24000000>;
+                        clock-output-names = "v2m:clk24mhz";
+                };
+
+                v2m_refclk1mhz: refclk1mhz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <1000000>;
+                        clock-output-names = "v2m:refclk1mhz";
+                };
+
+                v2m_refclk32khz: refclk32khz {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                        clock-output-names = "v2m:refclk32khz";
+                };
+
+                iofpga@3,00000000 {
+                        compatible = "arm,amba-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 3 0 0x200000>;
+
+                        v2m_sysreg: sysreg@010000 {
+                                compatible = "arm,vexpress-sysreg";
+                                reg = <0x010000 0x1000>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                        };
+
+                        v2m_sysctl: sysctl@020000 {
+                                compatible = "arm,sp810", "arm,primecell";
+                                reg = <0x020000 0x1000>;
+                                clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
+                                clock-names = "refclk", "timclk", "apb_pclk";
+                                #clock-cells = <1>;
+                                clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
+                        };
+
+                        aaci@040000 {
+                                compatible = "arm,pl041", "arm,primecell";
+                                reg = <0x040000 0x1000>;
+                                interrupts = <11>;
+                                clocks = <&v2m_clk24mhz>;
+                                clock-names = "apb_pclk";
+                        };
+
+                        mmci@050000 {
+                                compatible = "arm,pl180", "arm,primecell";
+                                reg = <0x050000 0x1000>;
+                                interrupts = <9 10>;
+                                cd-gpios = <&v2m_sysreg 0 0>;
+                                wp-gpios = <&v2m_sysreg 1 0>;
+                                max-frequency = <12000000>;
+                                vmmc-supply = <&v2m_fixed_3v3>;
+                                clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+                                clock-names = "mclk", "apb_pclk";
+                        };
+
+                        kmi@060000 {
+                                compatible = "arm,pl050", "arm,primecell";
+                                reg = <0x060000 0x1000>;
+                                interrupts = <12>;
+                                clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+                                clock-names = "KMIREFCLK", "apb_pclk";
+                        };
+
+                        kmi@070000 {
+                                compatible = "arm,pl050", "arm,primecell";
+                                reg = <0x070000 0x1000>;
+                                interrupts = <13>;
+                                clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+                                clock-names = "KMIREFCLK", "apb_pclk";
+                        };
+
+                        v2m_serial0: uart@090000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x090000 0x1000>;
+                                interrupts = <5>;
+                                clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+                                clock-names = "uartclk", "apb_pclk";
+                        };
+
+                        v2m_serial1: uart@0a0000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x0a0000 0x1000>;
+                                interrupts = <6>;
+                                clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+                                clock-names = "uartclk", "apb_pclk";
+                        };
+
+                        v2m_serial2: uart@0b0000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x0b0000 0x1000>;
+                                interrupts = <7>;
+                                clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+                                clock-names = "uartclk", "apb_pclk";
+                        };
+
+                        v2m_serial3: uart@0c0000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x0c0000 0x1000>;
+                                interrupts = <8>;
+                                clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
+                                clock-names = "uartclk", "apb_pclk";
+                        };
+
+                        wdt@0f0000 {
+                                compatible = "arm,sp805", "arm,primecell";
+                                reg = <0x0f0000 0x1000>;
+                                interrupts = <0>;
+                                clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
+                                clock-names = "wdogclk", "apb_pclk";
+                        };
+
+                        v2m_timer01: timer@110000 {
+                                compatible = "arm,sp804", "arm,primecell";
+                                reg = <0x110000 0x1000>;
+                                interrupts = <2>;
+                                clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
+                                clock-names = "timclken1", "timclken2", "apb_pclk";
+                        };
+
+                        v2m_timer23: timer@120000 {
+                                compatible = "arm,sp804", "arm,primecell";
+                                reg = <0x120000 0x1000>;
+                                interrupts = <3>;
+                                clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
+                                clock-names = "timclken1", "timclken2", "apb_pclk";
+                        };
+
+                        rtc@170000 {
+                                compatible = "arm,pl031", "arm,primecell";
+                                reg = <0x170000 0x1000>;
+                                interrupts = <4>;
+                                clocks = <&v2m_clk24mhz>;
+                                clock-names = "apb_pclk";
+                        };
+
+                        clcd@1f0000 {
+                                compatible = "arm,pl111", "arm,primecell";
+                                reg = <0x1f0000 0x1000>;
+                                interrupts = <14>;
+                                clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
+                                clock-names = "clcdclk", "apb_pclk";
+                        };
+                };
+
+                v2m_fixed_3v3: fixedregulator@0 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3V3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+
+                mcc {
+                        compatible = "arm,vexpress,config-bus", "simple-bus";
+                        arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+                        v2m_oscclk1: osc@1 {
+                                /* CLCD clock */
+                                compatible = "arm,vexpress-osc";
+                                arm,vexpress-sysreg,func = <1 1>;
+                                freq-range = <23750000 63500000>;
+                                #clock-cells = <0>;
+                                clock-output-names = "v2m:oscclk1";
+                        };
+
+                        reset@0 {
+                                compatible = "arm,vexpress-reset";
+                                arm,vexpress-sysreg,func = <5 0>;
+                        };
+
+                        muxfpga@0 {
+                                compatible = "arm,vexpress-muxfpga";
+                                arm,vexpress-sysreg,func = <7 0>;
+                        };
+
+                        shutdown@0 {
+                                compatible = "arm,vexpress-shutdown";
+                                arm,vexpress-sysreg,func = <8 0>;
+                        };
+
+                        reboot@0 {
+                                compatible = "arm,vexpress-reboot";
+                                arm,vexpress-sysreg,func = <9 0>;
+                        };
+
+                        dvimode@0 {
+                                compatible = "arm,vexpress-dvimode";
+                                arm,vexpress-sysreg,func = <11 0>;
+                        };
+                };
+        };
diff --git a/arch/arm64/boot/dts/skeleton.dtsi b/arch/arm64/boot/dts/skeleton.dtsi
new file mode 100644
index 000000000000..38ead821bb42
--- /dev/null
+++ b/arch/arm64/boot/dts/skeleton.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Skeleton device tree; the bare minimum needed to boot; just include and
+ * add a compatible value.  The bootloader will typically populate the memory
+ * node.
+ */
+
+/ {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        chosen { };
+        aliases { };
+        memory { device_type = "memory"; reg = <0 0 0>; };
+};
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 09bef29f3a09..8d9696adb440 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -23,6 +23,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_ARCH_VEXPRESS=y
 CONFIG_SMP=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_CMDLINE="console=ttyAMA0"
@@ -47,11 +48,14 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
 CONFIG_MII=y
+CONFIG_SMC91X=y
 # CONFIG_WLAN is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_SERIO_I8042 is not set
 # CONFIG_SERIO_SERPORT is not set
 CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 # CONFIG_HWMON is not set
 CONFIG_FB=y
diff --git a/arch/arm64/include/asm/Kbuild b/arch/arm64/include/asm/Kbuild
index e5fe4f99fe10..79a642d199f2 100644
--- a/arch/arm64/include/asm/Kbuild
+++ b/arch/arm64/include/asm/Kbuild
@@ -39,7 +39,6 @@ generic-y += shmbuf.h
 generic-y += sizes.h
 generic-y += socket.h
 generic-y += sockios.h
-generic-y += string.h
 generic-y += switch_to.h
 generic-y += swab.h
 generic-y += termbits.h
@@ -49,4 +48,5 @@ generic-y += trace_clock.h
 generic-y += types.h
 generic-y += unaligned.h
 generic-y += user.h
+generic-y += vga.h
 generic-y += xor.h
diff --git a/arch/arm64/include/asm/bitops.h b/arch/arm64/include/asm/bitops.h
index 5e693073b030..aa5b59d6ba43 100644
--- a/arch/arm64/include/asm/bitops.h
+++ b/arch/arm64/include/asm/bitops.h
@@ -32,6 +32,16 @@
 #error only <linux/bitops.h> can be included directly
 #endif
 
+/*
+ * Little endian assembly atomic bitops.
+ */
+extern void set_bit(int nr, volatile unsigned long *p);
+extern void clear_bit(int nr, volatile unsigned long *p);
+extern void change_bit(int nr, volatile unsigned long *p);
+extern int test_and_set_bit(int nr, volatile unsigned long *p);
+extern int test_and_clear_bit(int nr, volatile unsigned long *p);
+extern int test_and_change_bit(int nr, volatile unsigned long *p);
+
 #include <asm-generic/bitops/builtin-__ffs.h>
 #include <asm-generic/bitops/builtin-ffs.h>
 #include <asm-generic/bitops/builtin-__fls.h>
@@ -45,9 +55,13 @@
 #include <asm-generic/bitops/hweight.h>
 #include <asm-generic/bitops/lock.h>
 
-#include <asm-generic/bitops/atomic.h>
 #include <asm-generic/bitops/non-atomic.h>
 #include <asm-generic/bitops/le.h>
-#include <asm-generic/bitops/ext2-atomic.h>
+
+/*
+ * Ext2 is defined to use little-endian byte ordering.
+ */
+#define ext2_set_bit_atomic(lock, nr, p)        test_and_set_bit_le(nr, p)
+#define ext2_clear_bit_atomic(lock, nr, p)      test_and_clear_bit_le(nr, p)
 
 #endif /* __ASM_BITOPS_H */
diff --git a/arch/arm64/include/asm/cmpxchg.h b/arch/arm64/include/asm/cmpxchg.h
index 968b5cbfc260..8a8ce0e73a38 100644
--- a/arch/arm64/include/asm/cmpxchg.h
+++ b/arch/arm64/include/asm/cmpxchg.h
@@ -170,4 +170,7 @@ static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
                                        (unsigned long)(n),              \
                                        sizeof(*(ptr))))
 
+#define cmpxchg64(ptr,o,n)              cmpxchg((ptr),(o),(n))
+#define cmpxchg64_local(ptr,o,n)        cmpxchg_local((ptr),(o),(n))
+
 #endif  /* __ASM_CMPXCHG_H */
diff --git a/arch/arm64/include/asm/compat.h b/arch/arm64/include/asm/compat.h
index 618b450e5a1d..899af807ef0f 100644
--- a/arch/arm64/include/asm/compat.h
+++ b/arch/arm64/include/asm/compat.h
@@ -35,14 +35,16 @@ typedef s32		compat_clock_t;
 typedef s32             compat_pid_t;
 typedef u32             __compat_uid_t;
 typedef u32             __compat_gid_t;
+typedef u16             __compat_uid16_t;
+typedef u16             __compat_gid16_t;
 typedef u32             __compat_uid32_t;
 typedef u32             __compat_gid32_t;
-typedef u32             compat_mode_t;
+typedef u16             compat_mode_t;
 typedef u32             compat_ino_t;
 typedef u32             compat_dev_t;
 typedef s32             compat_off_t;
 typedef s64             compat_loff_t;
-typedef s16             compat_nlink_t;
+typedef s32             compat_nlink_t;
 typedef u16             compat_ipc_pid_t;
 typedef s32             compat_daddr_t;
 typedef u32             compat_caddr_t;
@@ -50,9 +52,11 @@ typedef __kernel_fsid_t	compat_fsid_t;
 typedef s32             compat_key_t;
 typedef s32             compat_timer_t;
 
+typedef s16             compat_short_t;
 typedef s32             compat_int_t;
 typedef s32             compat_long_t;
 typedef s64             compat_s64;
+typedef u16             compat_ushort_t;
 typedef u32             compat_uint_t;
 typedef u32             compat_ulong_t;
 typedef u64             compat_u64;
@@ -72,20 +76,20 @@ struct compat_stat {
         compat_dev_t    st_dev;
         compat_ino_t    st_ino;
         compat_mode_t   st_mode;
-        compat_nlink_t  st_nlink;
-        __compat_uid32_t        st_uid;
-        __compat_gid32_t        st_gid;
+        compat_ushort_t st_nlink;
+        __compat_uid16_t        st_uid;
+        __compat_gid16_t        st_gid;
         compat_dev_t    st_rdev;
         compat_off_t    st_size;
         compat_off_t    st_blksize;
         compat_off_t    st_blocks;
         compat_time_t   st_atime;
-        u32             st_atime_nsec;
+        compat_ulong_t  st_atime_nsec;
         compat_time_t   st_mtime;
-        u32             st_mtime_nsec;
+        compat_ulong_t  st_mtime_nsec;
         compat_time_t   st_ctime;
-        u32             st_ctime_nsec;
-        u32             __unused4[2];
+        compat_ulong_t  st_ctime_nsec;
+        compat_ulong_t  __unused4[2];
 };
 
 struct compat_flock {
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index ef54125e6c1e..cf2749488cd4 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -17,6 +17,7 @@
 #define __ASM_CPUTYPE_H
 
 #define ID_MIDR_EL1             "midr_el1"
+#define ID_MPIDR_EL1            "mpidr_el1"
 #define ID_CTR_EL0              "ctr_el0"
 
 #define ID_AA64PFR0_EL1         "id_aa64pfr0_el1"
@@ -25,12 +26,24 @@
 #define ID_AA64ISAR0_EL1        "id_aa64isar0_el1"
 #define ID_AA64MMFR0_EL1        "id_aa64mmfr0_el1"
 
+#define INVALID_HWID            ULONG_MAX
+
+#define MPIDR_HWID_BITMASK      0xff00ffffff
+
 #define read_cpuid(reg) ({                                              \
         u64 __val;                                                      \
         asm("mrs        %0, " reg : "=r" (__val));                      \
         __val;                                                          \
 })
 
+#define ARM_CPU_IMP_ARM         0x41
+
+#define ARM_CPU_PART_AEM_V8     0xD0F0
+#define ARM_CPU_PART_FOUNDATION 0xD000
+#define ARM_CPU_PART_CORTEX_A57 0xD070
+
+#ifndef __ASSEMBLY__
+
 /*
  * The CPU ID never changes at run time, so we might as well tell the
  * compiler that it's constant.  Use this function to read the CPU ID
@@ -41,9 +54,26 @@ static inline u32 __attribute_const__ read_cpuid_id(void)
         return read_cpuid(ID_MIDR_EL1);
 }
 
+static inline u64 __attribute_const__ read_cpuid_mpidr(void)
+{
+        return read_cpuid(ID_MPIDR_EL1);
+}
+
+static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
+{
+        return (read_cpuid_id() & 0xFF000000) >> 24;
+}
+
+static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
+{
+        return (read_cpuid_id() & 0xFFF0);
+}
+
 static inline u32 __attribute_const__ read_cpuid_cachetype(void)
 {
         return read_cpuid(ID_CTR_EL0);
 }
 
+#endif /* __ASSEMBLY__ */
+
 #endif
diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
new file mode 100644
index 000000000000..78834123a32e
--- /dev/null
+++ b/arch/arm64/include/asm/esr.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ASM_ESR_H
+#define __ASM_ESR_H
+
+#define ESR_EL1_EC_SHIFT        (26)
+#define ESR_EL1_IL              (1U << 25)
+
+#define ESR_EL1_EC_UNKNOWN      (0x00)
+#define ESR_EL1_EC_WFI          (0x01)
+#define ESR_EL1_EC_CP15_32      (0x03)
+#define ESR_EL1_EC_CP15_64      (0x04)
+#define ESR_EL1_EC_CP14_MR      (0x05)
+#define ESR_EL1_EC_CP14_LS      (0x06)
+#define ESR_EL1_EC_FP_ASIMD     (0x07)
+#define ESR_EL1_EC_CP10_ID      (0x08)
+#define ESR_EL1_EC_CP14_64      (0x0C)
+#define ESR_EL1_EC_ILL_ISS      (0x0E)
+#define ESR_EL1_EC_SVC32        (0x11)
+#define ESR_EL1_EC_SVC64        (0x15)
+#define ESR_EL1_EC_SYS64        (0x18)
+#define ESR_EL1_EC_IABT_EL0     (0x20)
+#define ESR_EL1_EC_IABT_EL1     (0x21)
+#define ESR_EL1_EC_PC_ALIGN     (0x22)
+#define ESR_EL1_EC_DABT_EL0     (0x24)
+#define ESR_EL1_EC_DABT_EL1     (0x25)
+#define ESR_EL1_EC_SP_ALIGN     (0x26)
+#define ESR_EL1_EC_FP_EXC32     (0x28)
+#define ESR_EL1_EC_FP_EXC64     (0x2C)
+#define ESR_EL1_EC_SERRROR      (0x2F)
+#define ESR_EL1_EC_BREAKPT_EL0  (0x30)
+#define ESR_EL1_EC_BREAKPT_EL1  (0x31)
+#define ESR_EL1_EC_SOFTSTP_EL0  (0x32)
+#define ESR_EL1_EC_SOFTSTP_EL1  (0x33)
+#define ESR_EL1_EC_WATCHPT_EL0  (0x34)
+#define ESR_EL1_EC_WATCHPT_EL1  (0x35)
+#define ESR_EL1_EC_BKPT32       (0x38)
+#define ESR_EL1_EC_BRK64        (0x3C)
+
+#endif /* __ASM_ESR_H */
diff --git a/arch/arm64/include/asm/exception.h b/arch/arm64/include/asm/exception.h
index ac63519b7b90..0303705fcad6 100644
--- a/arch/arm64/include/asm/exception.h
+++ b/arch/arm64/include/asm/exception.h
@@ -19,5 +19,6 @@
 #define __ASM_EXCEPTION_H
 
 #define __exception     __attribute__((section(".exception.text")))
+#define __exception_irq_entry   __exception
 
 #endif  /* __ASM_EXCEPTION_H */
diff --git a/arch/arm64/include/asm/hardirq.h b/arch/arm64/include/asm/hardirq.h
index 507546353d62..990c051e7829 100644
--- a/arch/arm64/include/asm/hardirq.h
+++ b/arch/arm64/include/asm/hardirq.h
@@ -49,4 +49,9 @@ static inline void ack_bad_irq(unsigned int irq)
 
 extern void handle_IRQ(unsigned int, struct pt_regs *);
 
+/*
+ * No arch-specific IRQ flags.
+ */
+#define set_irq_flags(irq, flags)
+
 #endif /* __ASM_HARDIRQ_H */
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index 57f12c991de2..2e12258aa7e4 100644
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -92,10 +92,12 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
 #define readb_relaxed(c)        ({ u8  __v = __raw_readb(c); __v; })
 #define readw_relaxed(c)        ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; })
 #define readl_relaxed(c)        ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; })
+#define readq_relaxed(c)        ({ u64 __v = le64_to_cpu((__force __le64)__raw_readq(c)); __v; })
 
 #define writeb_relaxed(v,c)     ((void)__raw_writeb((v),(c)))
 #define writew_relaxed(v,c)     ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
 #define writel_relaxed(v,c)     ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
+#define writeq_relaxed(v,c)     ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
 
 /*
  * I/O memory access primitives. Reads are ordered relative to any
@@ -105,10 +107,12 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
 #define readb(c)                ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
 #define readw(c)                ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
 #define readl(c)                ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
+#define readq(c)                ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
 
 #define writeb(v,c)             ({ __iowmb(); writeb_relaxed((v),(c)); })
 #define writew(v,c)             ({ __iowmb(); writew_relaxed((v),(c)); })
 #define writel(v,c)             ({ __iowmb(); writel_relaxed((v),(c)); })
+#define writeq(v,c)             ({ __iowmb(); writeq_relaxed((v),(c)); })
 
 /*
  *  I/O port access primitives.
diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h
index a4e1cad3202a..0332fc077f6e 100644
--- a/arch/arm64/include/asm/irq.h
+++ b/arch/arm64/include/asm/irq.h
@@ -4,5 +4,6 @@
 #include <asm-generic/irq.h>
 
 extern void (*handle_arch_irq)(struct pt_regs *);
+extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
 
 #endif
diff --git a/arch/arm64/lib/bitops.c b/arch/arm64/include/asm/smp_plat.h
index aa4965e60acc..ed43a0d2b1b2 100644
--- a/arch/arm64/lib/bitops.c
+++ b/arch/arm64/include/asm/smp_plat.h
@@ -1,7 +1,9 @@
 /*
- * Copyright (C) 2012 ARM Limited
+ * Definitions specific to SMP platforms.
  *
- * This program is free software; you can redistribute it and/or modify
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
@@ -14,12 +16,15 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <linux/kernel.h>
-#include <linux/spinlock.h>
-#include <linux/atomic.h>
+#ifndef __ASM_SMP_PLAT_H
+#define __ASM_SMP_PLAT_H
+
+#include <asm/types.h>
+
+/*
+ * Logical CPU mapping.
+ */
+extern u64 __cpu_logical_map[NR_CPUS];
+#define cpu_logical_map(cpu)    __cpu_logical_map[cpu]
 
-#ifdef CONFIG_SMP
-arch_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned = {
-       [0 ... (ATOMIC_HASH_SIZE-1)]  = __ARCH_SPIN_LOCK_UNLOCKED
-};
-#endif
+#endif /* __ASM_SMP_PLAT_H */
diff --git a/arch/arm64/include/asm/string.h b/arch/arm64/include/asm/string.h
new file mode 100644
index 000000000000..3ee8b303d9a9
--- /dev/null
+++ b/arch/arm64/include/asm/string.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ASM_STRING_H
+#define __ASM_STRING_H
+
+#define __HAVE_ARCH_STRRCHR
+extern char *strrchr(const char *, int c);
+
+#define __HAVE_ARCH_STRCHR
+extern char *strchr(const char *, int c);
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *, int, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+#endif
diff --git a/arch/arm64/kernel/arm64ksyms.c b/arch/arm64/kernel/arm64ksyms.c
index aa3e948f7885..7df1aad29b67 100644
--- a/arch/arm64/kernel/arm64ksyms.c
+++ b/arch/arm64/kernel/arm64ksyms.c
@@ -39,10 +39,21 @@ EXPORT_SYMBOL(__copy_from_user);
 EXPORT_SYMBOL(__copy_to_user);
 EXPORT_SYMBOL(__clear_user);
 
-        /* bitops */
-#ifdef CONFIG_SMP
-EXPORT_SYMBOL(__atomic_hash);
-#endif
-
         /* physical memory */
 EXPORT_SYMBOL(memstart_addr);
+
+        /* string / mem functions */
+EXPORT_SYMBOL(strchr);
+EXPORT_SYMBOL(strrchr);
+EXPORT_SYMBOL(memset);
+EXPORT_SYMBOL(memcpy);
+EXPORT_SYMBOL(memmove);
+EXPORT_SYMBOL(memchr);
+
+        /* atomic bitops */
+EXPORT_SYMBOL(set_bit);
+EXPORT_SYMBOL(test_and_set_bit);
+EXPORT_SYMBOL(clear_bit);
+EXPORT_SYMBOL(test_and_clear_bit);
+EXPORT_SYMBOL(change_bit);
+EXPORT_SYMBOL(test_and_change_bit);
diff --git a/arch/arm64/kernel/early_printk.c b/arch/arm64/kernel/early_printk.c
index 7e320a2edb9b..ac974f48a7a2 100644
--- a/arch/arm64/kernel/early_printk.c
+++ b/arch/arm64/kernel/early_printk.c
@@ -24,6 +24,7 @@
 #include <linux/io.h>
 
 #include <linux/amba/serial.h>
+#include <linux/serial_reg.h>
 
 static void __iomem *early_base;
 static void (*printch)(char ch);
@@ -40,6 +41,37 @@ static void pl011_printch(char ch)
                 ;
 }
 
+/*
+ * Semihosting-based debug console
+ */
+static void smh_printch(char ch)
+{
+        asm volatile("mov  x1, %0\n"
+                     "mov  x0, #3\n"
+                     "hlt  0xf000\n"
+                     : : "r" (&ch) : "x0", "x1", "memory");
+}
+
+/*
+ * 8250/16550 (8-bit aligned registers) single character TX.
+ */
+static void uart8250_8bit_printch(char ch)
+{
+        while (!(readb_relaxed(early_base + UART_LSR) & UART_LSR_THRE))
+                ;
+        writeb_relaxed(ch, early_base + UART_TX);
+}
+
+/*
+ * 8250/16550 (32-bit aligned registers) single character TX.
+ */
+static void uart8250_32bit_printch(char ch)
+{
+        while (!(readl_relaxed(early_base + (UART_LSR << 2)) & UART_LSR_THRE))
+                ;
+        writel_relaxed(ch, early_base + (UART_TX << 2));
+}
+
 struct earlycon_match {
         const char *name;
         void (*printch)(char ch);
@@ -47,6 +79,9 @@ struct earlycon_match {
 
 static const struct earlycon_match earlycon_match[] __initconst = {
         { .name = "pl011", .printch = pl011_printch, },
+        { .name = "smh", .printch = smh_printch, },
+        { .name = "uart8250-8bit", .printch = uart8250_8bit_printch, },
+        { .name = "uart8250-32bit", .printch = uart8250_32bit_printch, },
         {}
 };
 
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index 514d6098dbee..c7e047049f2c 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -24,6 +24,7 @@
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 #include <asm/errno.h>
+#include <asm/esr.h>
 #include <asm/thread_info.h>
 #include <asm/unistd.h>
 #include <asm/unistd32.h>
@@ -239,18 +240,18 @@ ENDPROC(el1_error_invalid)
 el1_sync:
         kernel_entry 1
         mrs     x1, esr_el1                     // read the syndrome register
-        lsr     x24, x1, #26                    // exception class
-        cmp     x24, #0x25                      // data abort in EL1
+        lsr     x24, x1, #ESR_EL1_EC_SHIFT      // exception class
+        cmp     x24, #ESR_EL1_EC_DABT_EL1       // data abort in EL1
         b.eq    el1_da
-        cmp     x24, #0x18                      // configurable trap
+        cmp     x24, #ESR_EL1_EC_SYS64          // configurable trap
         b.eq    el1_undef
-        cmp     x24, #0x26                      // stack alignment exception
+        cmp     x24, #ESR_EL1_EC_SP_ALIGN       // stack alignment exception
         b.eq    el1_sp_pc
-        cmp     x24, #0x22                      // pc alignment exception
+        cmp     x24, #ESR_EL1_EC_PC_ALIGN       // pc alignment exception
         b.eq    el1_sp_pc
-        cmp     x24, #0x00                      // unknown exception in EL1
+        cmp     x24, #ESR_EL1_EC_UNKNOWN        // unknown exception in EL1
         b.eq    el1_undef
-        cmp     x24, #0x30                      // debug exception in EL1
+        cmp     x24, #ESR_EL1_EC_BREAKPT_EL1    // debug exception in EL1
         b.ge    el1_dbg
         b       el1_inv
 el1_da:
@@ -346,27 +347,27 @@ el1_preempt:
 el0_sync:
         kernel_entry 0
         mrs     x25, esr_el1                    // read the syndrome register
-        lsr     x24, x25, #26                   // exception class
-        cmp     x24, #0x15                      // SVC in 64-bit state
+        lsr     x24, x25, #ESR_EL1_EC_SHIFT     // exception class
+        cmp     x24, #ESR_EL1_EC_SVC64          // SVC in 64-bit state
         b.eq    el0_svc
         adr     lr, ret_from_exception
-        cmp     x24, #0x24                      // data abort in EL0
+        cmp     x24, #ESR_EL1_EC_DABT_EL0       // data abort in EL0
         b.eq    el0_da
-        cmp     x24, #0x20                      // instruction abort in EL0
+        cmp     x24, #ESR_EL1_EC_IABT_EL0       // instruction abort in EL0
         b.eq    el0_ia
-        cmp     x24, #0x07                      // FP/ASIMD access
+        cmp     x24, #ESR_EL1_EC_FP_ASIMD       // FP/ASIMD access
         b.eq    el0_fpsimd_acc
-        cmp     x24, #0x2c                      // FP/ASIMD exception
+        cmp     x24, #ESR_EL1_EC_FP_EXC64       // FP/ASIMD exception
         b.eq    el0_fpsimd_exc
-        cmp     x24, #0x18                      // configurable trap
+        cmp     x24, #ESR_EL1_EC_SYS64          // configurable trap
         b.eq    el0_undef
-        cmp     x24, #0x26                      // stack alignment exception
+        cmp     x24, #ESR_EL1_EC_SP_ALIGN       // stack alignment exception
         b.eq    el0_sp_pc
-        cmp     x24, #0x22                      // pc alignment exception
+        cmp     x24, #ESR_EL1_EC_PC_ALIGN       // pc alignment exception
         b.eq    el0_sp_pc
-        cmp     x24, #0x00                      // unknown exception in EL0
+        cmp     x24, #ESR_EL1_EC_UNKNOWN        // unknown exception in EL0
         b.eq    el0_undef
-        cmp     x24, #0x30                      // debug exception in EL0
+        cmp     x24, #ESR_EL1_EC_BREAKPT_EL0    // debug exception in EL0
         b.ge    el0_dbg
         b       el0_inv
 
@@ -375,21 +376,21 @@ el0_sync:
 el0_sync_compat:
         kernel_entry 0, 32
         mrs     x25, esr_el1                    // read the syndrome register
-        lsr     x24, x25, #26                   // exception class
-        cmp     x24, #0x11                      // SVC in 32-bit state
+        lsr     x24, x25, #ESR_EL1_EC_SHIFT     // exception class
+        cmp     x24, #ESR_EL1_EC_SVC32          // SVC in 32-bit state
         b.eq    el0_svc_compat
         adr     lr, ret_from_exception
-        cmp     x24, #0x24                      // data abort in EL0
+        cmp     x24, #ESR_EL1_EC_DABT_EL0       // data abort in EL0
         b.eq    el0_da
-        cmp     x24, #0x20                      // instruction abort in EL0
+        cmp     x24, #ESR_EL1_EC_IABT_EL0       // instruction abort in EL0
         b.eq    el0_ia
-        cmp     x24, #0x07                      // FP/ASIMD access
+        cmp     x24, #ESR_EL1_EC_FP_ASIMD       // FP/ASIMD access
         b.eq    el0_fpsimd_acc
-        cmp     x24, #0x28                      // FP/ASIMD exception
+        cmp     x24, #ESR_EL1_EC_FP_EXC32       // FP/ASIMD exception
         b.eq    el0_fpsimd_exc
-        cmp     x24, #0x00                      // unknown exception in EL0
+        cmp     x24, #ESR_EL1_EC_UNKNOWN        // unknown exception in EL0
         b.eq    el0_undef
-        cmp     x24, #0x30                      // debug exception in EL0
+        cmp     x24, #ESR_EL1_EC_BREAKPT_EL0    // debug exception in EL0
         b.ge    el0_dbg
         b       el0_inv
 el0_svc_compat:
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 0a0a49756826..53dcae49e729 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -26,6 +26,7 @@
 #include <asm/assembler.h>
 #include <asm/ptrace.h>
 #include <asm/asm-offsets.h>
+#include <asm/cputype.h>
 #include <asm/memory.h>
 #include <asm/thread_info.h>
 #include <asm/pgtable-hwdef.h>
@@ -229,7 +230,8 @@ ENTRY(secondary_holding_pen)
         bl      __calc_phys_offset              // x24=phys offset
         bl      el2_setup                       // Drop to EL1
         mrs     x0, mpidr_el1
-        and     x0, x0, #15                     // CPU number
+        ldr     x1, =MPIDR_HWID_BITMASK
+        and     x0, x0, x1
         adr     x1, 1b
         ldp     x2, x3, [x1]
         sub     x1, x1, x2
diff --git a/arch/arm64/kernel/irq.c b/arch/arm64/kernel/irq.c
index 0373c6609eaf..ecb3354292ed 100644
--- a/arch/arm64/kernel/irq.c
+++ b/arch/arm64/kernel/irq.c
@@ -25,7 +25,7 @@
 #include <linux/irq.h>
 #include <linux/smp.h>
 #include <linux/init.h>
-#include <linux/of_irq.h>
+#include <linux/irqchip.h>
 #include <linux/seq_file.h>
 #include <linux/ratelimit.h>
 
@@ -67,18 +67,17 @@ void handle_IRQ(unsigned int irq, struct pt_regs *regs)
         set_irq_regs(old_regs);
 }
 
-/*
- * Interrupt controllers supported by the kernel.
- */
-static const struct of_device_id intctrl_of_match[] __initconst = {
-        /* IRQ controllers { .compatible, .data } info to go here */
-        {}
-};
+void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
+{
+        if (handle_arch_irq)
+                return;
+
+        handle_arch_irq = handle_irq;
+}
 
 void __init init_IRQ(void)
 {
-        of_irq_init(intctrl_of_match);
-
+        irqchip_init();
         if (!handle_arch_irq)
                 panic("No interrupt controller found.");
 }
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 0337cdb0667b..f4919721f7dd 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -84,11 +84,15 @@ EXPORT_SYMBOL_GPL(pm_power_off);
 void (*pm_restart)(const char *cmd);
 EXPORT_SYMBOL_GPL(pm_restart);
 
+void arch_cpu_idle_prepare(void)
+{
+        local_fiq_enable();
+}
 
 /*
  * This is our default idle handler.
  */
-static void default_idle(void)
+void arch_cpu_idle(void)
 {
         /*
          * This should do all the clock switching and wait for interrupt
@@ -98,43 +102,6 @@ static void default_idle(void)
         local_irq_enable();
 }
 
-/*
- * The idle thread.
- * We always respect 'hlt_counter' to prevent low power idle.
- */
-void cpu_idle(void)
-{
-        local_fiq_enable();
-
-        /* endless idle loop with no priority at all */
-        while (1) {
-                tick_nohz_idle_enter();
-                rcu_idle_enter();
-                while (!need_resched()) {
-                        /*
-                         * We need to disable interrupts here to ensure
-                         * we don't miss a wakeup call.
-                         */
-                        local_irq_disable();
-                        if (!need_resched()) {
-                                stop_critical_timings();
-                                default_idle();
-                                start_critical_timings();
-                                /*
-                                 * default_idle functions should always return
-                                 * with IRQs enabled.
-                                 */
-                                WARN_ON(irqs_disabled());
-                        } else {
-                                local_irq_enable();
-                        }
-                }
-                rcu_idle_exit();
-                tick_nohz_idle_exit();
-                schedule_preempt_disabled();
-        }
-}
-
 void machine_shutdown(void)
 {
 #ifdef CONFIG_SMP
@@ -178,11 +145,7 @@ void __show_regs(struct pt_regs *regs)
 {
         int i;
 
-        printk("CPU: %d    %s  (%s %.*s)\n",
-                raw_smp_processor_id(), print_tainted(),
-                init_utsname()->release,
-                (int)strcspn(init_utsname()->version, " "),
-                init_utsname()->version);
+        show_regs_print_info(KERN_DEFAULT);
         print_symbol("PC is at %s\n", instruction_pointer(regs));
         print_symbol("LR is at %s\n", regs->regs[30]);
         printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
@@ -199,7 +162,6 @@ void __show_regs(struct pt_regs *regs)
 void show_regs(struct pt_regs * regs)
 {
         printk("\n");
-        printk("Pid: %d, comm: %20s\n", task_pid_nr(current), current->comm);
         __show_regs(regs);
 }
 
@@ -311,11 +273,17 @@ struct task_struct *__switch_to(struct task_struct *prev,
         fpsimd_thread_switch(next);
         tls_thread_switch(next);
         hw_breakpoint_thread_switch(next);
+        contextidr_thread_switch(next);
+
+        /*
+         * Complete any pending TLB or cache maintenance on this CPU in case
+         * the thread migrates to a different CPU.
+         */
+        dsb();
 
         /* the actual thread switch */
         last = cpu_switch_to(prev, next);
 
-        contextidr_thread_switch(next);
         return last;
 }
 
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index 113db863f832..6a9a53292590 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -32,6 +32,7 @@
 #include <linux/kexec.h>
 #include <linux/crash_dump.h>
 #include <linux/root_dev.h>
+#include <linux/clk-provider.h>
 #include <linux/cpu.h>
 #include <linux/interrupt.h>
 #include <linux/smp.h>
@@ -46,6 +47,7 @@
 #include <asm/cputable.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
+#include <asm/smp_plat.h>
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
 #include <asm/traps.h>
@@ -240,6 +242,8 @@ static void __init request_standard_resources(void)
         }
 }
 
+u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
+
 void __init setup_arch(char **cmdline_p)
 {
         setup_processor();
@@ -264,6 +268,7 @@ void __init setup_arch(char **cmdline_p)
 
         psci_init();
 
+        cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
 #ifdef CONFIG_SMP
         smp_init_cpus();
 #endif
@@ -277,6 +282,13 @@ void __init setup_arch(char **cmdline_p)
 #endif
 }
 
+static int __init arm64_of_clk_init(void)
+{
+        of_clk_init(NULL);
+        return 0;
+}
+arch_initcall(arm64_of_clk_init);
+
 static DEFINE_PER_CPU(struct cpu, cpu_data);
 
 static int __init topology_init(void)
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index bdd34597254b..5d54e3717bf8 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -43,6 +43,7 @@
 #include <asm/pgtable.h>
 #include <asm/pgalloc.h>
 #include <asm/processor.h>
+#include <asm/smp_plat.h>
 #include <asm/sections.h>
 #include <asm/tlbflush.h>
 #include <asm/ptrace.h>
@@ -53,7 +54,7 @@
  * where to place its SVC stack
  */
 struct secondary_data secondary_data;
-volatile unsigned long secondary_holding_pen_release = -1;
+volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
 
 enum ipi_msg_type {
         IPI_RESCHEDULE,
@@ -70,7 +71,7 @@ static DEFINE_RAW_SPINLOCK(boot_lock);
  * in coherency or not.  This is necessary for the hotplug code to work
  * reliably.
  */
-static void __cpuinit write_pen_release(int val)
+static void __cpuinit write_pen_release(u64 val)
 {
         void *start = (void *)&secondary_holding_pen_release;
         unsigned long size = sizeof(secondary_holding_pen_release);
@@ -96,7 +97,7 @@ static int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
         /*
          * Update the pen release flag.
          */
-        write_pen_release(cpu);
+        write_pen_release(cpu_logical_map(cpu));
 
         /*
          * Send an event, causing the secondaries to read pen_release.
@@ -105,7 +106,7 @@ static int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 
         timeout = jiffies + (1 * HZ);
         while (time_before(jiffies, timeout)) {
-                if (secondary_holding_pen_release == -1UL)
+                if (secondary_holding_pen_release == INVALID_HWID)
                         break;
                 udelay(10);
         }
@@ -116,7 +117,7 @@ static int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
          */
         raw_spin_unlock(&boot_lock);
 
-        return secondary_holding_pen_release != -1 ? -ENOSYS : 0;
+        return secondary_holding_pen_release != INVALID_HWID ? -ENOSYS : 0;
 }
 
 static DECLARE_COMPLETION(cpu_running);
@@ -190,7 +191,7 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
          * Let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
-        write_pen_release(-1);
+        write_pen_release(INVALID_HWID);
 
         /*
          * Synchronise with the boot thread.
@@ -216,7 +217,7 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
         /*
          * OK, it's off to the idle thread for us
          */
-        cpu_idle();
+        cpu_startup_entry(CPUHP_ONLINE);
 }
 
 void __init smp_cpus_done(unsigned int max_cpus)
@@ -244,11 +245,11 @@ static const struct smp_enable_ops *smp_enable_ops[NR_CPUS];
 
 static const struct smp_enable_ops * __init smp_get_enable_ops(const char *name)
 {
-        const struct smp_enable_ops *ops = enable_ops[0];
+        const struct smp_enable_ops **ops = enable_ops;
 
-        while (ops) {
-                if (!strcmp(name, ops->name))
-                        return ops;
+        while (*ops) {
+                if (!strcmp(name, (*ops)->name))
+                        return *ops;
 
                 ops++;
         }
@@ -257,15 +258,80 @@ static const struct smp_enable_ops * __init smp_get_enable_ops(const char *name)
 }
 
 /*
- * Enumerate the possible CPU set from the device tree.
+ * Enumerate the possible CPU set from the device tree and build the
+ * cpu logical map array containing MPIDR values related to logical
+ * cpus. Assumes that cpu_logical_map(0) has already been initialized.
  */
 void __init smp_init_cpus(void)
 {
         const char *enable_method;
         struct device_node *dn = NULL;
-        int cpu = 0;
+        int i, cpu = 1;
+        bool bootcpu_valid = false;
 
         while ((dn = of_find_node_by_type(dn, "cpu"))) {
+                const u32 *cell;
+                u64 hwid;
+
+                /*
+                 * A cpu node with missing "reg" property is
+                 * considered invalid to build a cpu_logical_map
+                 * entry.
+                 */
+                cell = of_get_property(dn, "reg", NULL);
+                if (!cell) {
+                        pr_err("%s: missing reg property\n", dn->full_name);
+                        goto next;
+                }
+                hwid = of_read_number(cell, of_n_addr_cells(dn));
+
+                /*
+                 * Non affinity bits must be set to 0 in the DT
+                 */
+                if (hwid & ~MPIDR_HWID_BITMASK) {
+                        pr_err("%s: invalid reg property\n", dn->full_name);
+                        goto next;
+                }
+
+                /*
+                 * Duplicate MPIDRs are a recipe for disaster. Scan
+                 * all initialized entries and check for
+                 * duplicates. If any is found just ignore the cpu.
+                 * cpu_logical_map was initialized to INVALID_HWID to
+                 * avoid matching valid MPIDR values.
+                 */
+                for (i = 1; (i < cpu) && (i < NR_CPUS); i++) {
+                        if (cpu_logical_map(i) == hwid) {
+                                pr_err("%s: duplicate cpu reg properties in the DT\n",
+                                        dn->full_name);
+                                goto next;
+                        }
+                }
+
+                /*
+                 * The numbering scheme requires that the boot CPU
+                 * must be assigned logical id 0. Record it so that
+                 * the logical map built from DT is validated and can
+                 * be used.
+                 */
+                if (hwid == cpu_logical_map(0)) {
+                        if (bootcpu_valid) {
+                                pr_err("%s: duplicate boot cpu reg property in DT\n",
+                                        dn->full_name);
+                                goto next;
+                        }
+
+                        bootcpu_valid = true;
+
+                        /*
+                         * cpu_logical_map has already been
+                         * initialized and the boot cpu doesn't need
+                         * the enable-method so continue without
+                         * incrementing cpu.
+                         */
+                        continue;
+                }
+
                 if (cpu >= NR_CPUS)
                         goto next;
 
@@ -274,22 +340,24 @@ void __init smp_init_cpus(void)
                  */
                 enable_method = of_get_property(dn, "enable-method", NULL);
                 if (!enable_method) {
-                        pr_err("CPU %d: missing enable-method property\n", cpu);
+                        pr_err("%s: missing enable-method property\n",
+                                dn->full_name);
                         goto next;
                 }
 
                 smp_enable_ops[cpu] = smp_get_enable_ops(enable_method);
 
                 if (!smp_enable_ops[cpu]) {
-                        pr_err("CPU %d: invalid enable-method property: %s\n",
-                               cpu, enable_method);
+                        pr_err("%s: invalid enable-method property: %s\n",
+                               dn->full_name, enable_method);
                         goto next;
                 }
 
                 if (smp_enable_ops[cpu]->init_cpu(dn, cpu))
                         goto next;
 
-                set_cpu_possible(cpu, true);
+                pr_debug("cpu logical map 0x%llx\n", hwid);
+                cpu_logical_map(cpu) = hwid;
 next:
                 cpu++;
         }
@@ -298,6 +366,19 @@ next:
         if (cpu > NR_CPUS)
                 pr_warning("no. of cores (%d) greater than configured maximum of %d - clipping\n",
                            cpu, NR_CPUS);
+
+        if (!bootcpu_valid) {
+                pr_err("DT missing boot CPU MPIDR, not enabling secondaries\n");
+                return;
+        }
+
+        /*
+         * All the cpus that made it to the cpu_logical_map have been
+         * validated so set them as possible cpus.
+         */
+        for (i = 0; i < NR_CPUS; i++)
+                if (cpu_logical_map(i) != INVALID_HWID)
+                        set_cpu_possible(i, true);
 }
 
 void __init smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm64/kernel/smp_psci.c b/arch/arm64/kernel/smp_psci.c
index 112091684c22..0c533301be77 100644
--- a/arch/arm64/kernel/smp_psci.c
+++ b/arch/arm64/kernel/smp_psci.c
@@ -21,6 +21,7 @@
 #include <linux/smp.h>
 
 #include <asm/psci.h>
+#include <asm/smp_plat.h>
 
 static int __init smp_psci_init_cpu(struct device_node *dn, int cpu)
 {
@@ -36,7 +37,7 @@ static int __init smp_psci_prepare_cpu(int cpu)
                 return -ENODEV;
         }
 
-        err = psci_ops.cpu_on(cpu, __pa(secondary_holding_pen));
+        err = psci_ops.cpu_on(cpu_logical_map(cpu), __pa(secondary_holding_pen));
         if (err) {
                 pr_err("psci: failed to boot CPU%d (%d)\n", cpu, err);
                 return err;
@@ -47,6 +48,6 @@ static int __init smp_psci_prepare_cpu(int cpu)
 
 const struct smp_enable_ops smp_psci_ops __initconst = {
         .name           = "psci",
-        .init_cpu       = smp_psci_init_cpu,
+        .init_cpu       = smp_psci_init_cpu,
         .prepare_cpu    = smp_psci_prepare_cpu,
 };
diff --git a/arch/arm64/kernel/sys32.S b/arch/arm64/kernel/sys32.S
index 9416d045a687..db01aa978c41 100644
--- a/arch/arm64/kernel/sys32.S
+++ b/arch/arm64/kernel/sys32.S
@@ -84,13 +84,6 @@ compat_sys_readahead_wrapper:
         b       sys_readahead
 ENDPROC(compat_sys_readahead_wrapper)
 
-compat_sys_lookup_dcookie:
-        orr     x0, x0, x1, lsl #32
-        mov     w1, w2
-        mov     w2, w3
-        b       sys_lookup_dcookie
-ENDPROC(compat_sys_lookup_dcookie)
-
 compat_sys_fadvise64_64_wrapper:
         mov     w6, w1
         orr     x1, x2, x3, lsl #32
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index b3c5f628bdb4..61d7dd29f756 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -167,13 +167,6 @@ static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
         }
 }
 
-void dump_stack(void)
-{
-        dump_backtrace(NULL, NULL);
-}
-
-EXPORT_SYMBOL(dump_stack);
-
 void show_stack(struct task_struct *tsk, unsigned long *sp)
 {
         dump_backtrace(NULL, tsk);
diff --git a/arch/arm64/lib/Makefile b/arch/arm64/lib/Makefile
index 2fb7f6092aae..59acc0ef0462 100644
--- a/arch/arm64/lib/Makefile
+++ b/arch/arm64/lib/Makefile
@@ -1,4 +1,6 @@
 lib-y           := bitops.o delay.o                                     \
                    strncpy_from_user.o strnlen_user.o clear_user.o      \
                    copy_from_user.o copy_to_user.o copy_in_user.o       \
-                   copy_page.o clear_page.o
+                   copy_page.o clear_page.o                             \
+                   memchr.o memcpy.o memmove.o memset.o                 \
+                   strchr.o strrchr.o
diff --git a/arch/arm64/lib/bitops.S b/arch/arm64/lib/bitops.S
new file mode 100644
index 000000000000..36216d30cb9a
--- /dev/null
+++ b/arch/arm64/lib/bitops.S
@@ -0,0 +1,68 @@
+/*
+ * Based on arch/arm/lib/bitops.h
+ *
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * x0: bits 5:0  bit offset
+ *     bits 63:6 word offset
+ * x1: address
+ */
+        .macro  bitop, name, instr
+ENTRY(  \name   )
+        and     x3, x0, #63             // Get bit offset
+        eor     x0, x0, x3              // Clear low bits
+        mov     x2, #1
+        add     x1, x1, x0, lsr #3      // Get word offset
+        lsl     x3, x2, x3              // Create mask
+1:      ldxr    x2, [x1]
+        \instr  x2, x2, x3
+        stxr    w0, x2, [x1]
+        cbnz    w0, 1b
+        ret
+ENDPROC(\name   )
+        .endm
+
+        .macro  testop, name, instr
+ENTRY(  \name   )
+        and     x3, x0, #63             // Get bit offset
+        eor     x0, x0, x3              // Clear low bits
+        mov     x2, #1
+        add     x1, x1, x0, lsr #3      // Get word offset
+        lsl     x4, x2, x3              // Create mask
+1:      ldaxr   x2, [x1]
+        lsr     x0, x2, x3              // Save old value of bit
+        \instr  x2, x2, x4              // toggle bit
+        stlxr   w5, x2, [x1]
+        cbnz    w5, 1b
+        and     x0, x0, #1
+3:      ret
+ENDPROC(\name   )
+        .endm
+
+/*
+ * Atomic bit operations.
+ */
+        bitop   change_bit, eor
+        bitop   clear_bit, bic
+        bitop   set_bit, orr
+
+        testop  test_and_change_bit, eor
+        testop  test_and_clear_bit, bic
+        testop  test_and_set_bit, orr
diff --git a/arch/arm64/lib/memchr.S b/arch/arm64/lib/memchr.S
new file mode 100644
index 000000000000..8636b7549163
--- /dev/null
+++ b/arch/arm64/lib/memchr.S
@@ -0,0 +1,44 @@
+/*
+ * Based on arch/arm/lib/memchr.S
+ *
+ * Copyright (C) 1995-2000 Russell King
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * Find a character in an area of memory.
+ *
+ * Parameters:
+ *      x0 - buf
+ *      x1 - c
+ *      x2 - n
+ * Returns:
+ *      x0 - address of first occurrence of 'c' or 0
+ */
+ENTRY(memchr)
+        and     w1, w1, #0xff
+1:      subs    x2, x2, #1
+        b.mi    2f
+        ldrb    w3, [x0], #1
+        cmp     w3, w1
+        b.ne    1b
+        sub     x0, x0, #1
+        ret
+2:      mov     x0, #0
+        ret
+ENDPROC(memchr)
diff --git a/arch/arm64/lib/memcpy.S b/arch/arm64/lib/memcpy.S
new file mode 100644
index 000000000000..27b5003609b6
--- /dev/null
+++ b/arch/arm64/lib/memcpy.S
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * Copy a buffer from src to dest (alignment handled by the hardware)
+ *
+ * Parameters:
+ *      x0 - dest
+ *      x1 - src
+ *      x2 - n
+ * Returns:
+ *      x0 - dest
+ */
+ENTRY(memcpy)
+        mov     x4, x0
+        subs    x2, x2, #8
+        b.mi    2f
+1:      ldr     x3, [x1], #8
+        subs    x2, x2, #8
+        str     x3, [x4], #8
+        b.pl    1b
+2:      adds    x2, x2, #4
+        b.mi    3f
+        ldr     w3, [x1], #4
+        sub     x2, x2, #4
+        str     w3, [x4], #4
+3:      adds    x2, x2, #2
+        b.mi    4f
+        ldrh    w3, [x1], #2
+        sub     x2, x2, #2
+        strh    w3, [x4], #2
+4:      adds    x2, x2, #1
+        b.mi    5f
+        ldrb    w3, [x1]
+        strb    w3, [x4]
+5:      ret
+ENDPROC(memcpy)
diff --git a/arch/arm64/lib/memmove.S b/arch/arm64/lib/memmove.S
new file mode 100644
index 000000000000..b79fdfa42d39
--- /dev/null
+++ b/arch/arm64/lib/memmove.S
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * Move a buffer from src to test (alignment handled by the hardware).
+ * If dest <= src, call memcpy, otherwise copy in reverse order.
+ *
+ * Parameters:
+ *      x0 - dest
+ *      x1 - src
+ *      x2 - n
+ * Returns:
+ *      x0 - dest
+ */
+ENTRY(memmove)
+        cmp     x0, x1
+        b.ls    memcpy
+        add     x4, x0, x2
+        add     x1, x1, x2
+        subs    x2, x2, #8
+        b.mi    2f
+1:      ldr     x3, [x1, #-8]!
+        subs    x2, x2, #8
+        str     x3, [x4, #-8]!
+        b.pl    1b
+2:      adds    x2, x2, #4
+        b.mi    3f
+        ldr     w3, [x1, #-4]!
+        sub     x2, x2, #4
+        str     w3, [x4, #-4]!
+3:      adds    x2, x2, #2
+        b.mi    4f
+        ldrh    w3, [x1, #-2]!
+        sub     x2, x2, #2
+        strh    w3, [x4, #-2]!
+4:      adds    x2, x2, #1
+        b.mi    5f
+        ldrb    w3, [x1, #-1]
+        strb    w3, [x4, #-1]
+5:      ret
+ENDPROC(memmove)
diff --git a/arch/arm64/lib/memset.S b/arch/arm64/lib/memset.S
new file mode 100644
index 000000000000..87e4a68fbbbc
--- /dev/null
+++ b/arch/arm64/lib/memset.S
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * Fill in the buffer with character c (alignment handled by the hardware)
+ *
+ * Parameters:
+ *      x0 - buf
+ *      x1 - c
+ *      x2 - n
+ * Returns:
+ *      x0 - buf
+ */
+ENTRY(memset)
+        mov     x4, x0
+        and     w1, w1, #0xff
+        orr     w1, w1, w1, lsl #8
+        orr     w1, w1, w1, lsl #16
+        orr     x1, x1, x1, lsl #32
+        subs    x2, x2, #8
+        b.mi    2f
+1:      str     x1, [x4], #8
+        subs    x2, x2, #8
+        b.pl    1b
+2:      adds    x2, x2, #4
+        b.mi    3f
+        sub     x2, x2, #4
+        str     w1, [x4], #4
+3:      adds    x2, x2, #2
+        b.mi    4f
+        sub     x2, x2, #2
+        strh    w1, [x4], #2
+4:      adds    x2, x2, #1
+        b.mi    5f
+        strb    w1, [x4]
+5:      ret
+ENDPROC(memset)
diff --git a/arch/arm64/lib/strchr.S b/arch/arm64/lib/strchr.S
new file mode 100644
index 000000000000..dae0cf5591f9
--- /dev/null
+++ b/arch/arm64/lib/strchr.S
@@ -0,0 +1,42 @@
+/*
+ * Based on arch/arm/lib/strchr.S
+ *
+ * Copyright (C) 1995-2000 Russell King
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * Find the first occurrence of a character in a string.
+ *
+ * Parameters:
+ *      x0 - str
+ *      x1 - c
+ * Returns:
+ *      x0 - address of first occurrence of 'c' or 0
+ */
+ENTRY(strchr)
+        and     w1, w1, #0xff
+1:      ldrb    w2, [x0], #1
+        cmp     w2, w1
+        ccmp    w2, wzr, #4, ne
+        b.ne    1b
+        sub     x0, x0, #1
+        cmp     w2, w1
+        csel    x0, x0, xzr, eq
+        ret
+ENDPROC(strchr)
diff --git a/arch/arm64/lib/strrchr.S b/arch/arm64/lib/strrchr.S
new file mode 100644
index 000000000000..61eabd9a289a
--- /dev/null
+++ b/arch/arm64/lib/strrchr.S
@@ -0,0 +1,43 @@
+/*
+ * Based on arch/arm/lib/strrchr.S
+ *
+ * Copyright (C) 1995-2000 Russell King
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * Find the last occurrence of a character in a string.
+ *
+ * Parameters:
+ *      x0 - str
+ *      x1 - c
+ * Returns:
+ *      x0 - address of last occurrence of 'c' or 0
+ */
+ENTRY(strrchr)
+        mov     x3, #0
+        and     w1, w1, #0xff
+1:      ldrb    w2, [x0], #1
+        cbz     w2, 2f
+        cmp     w2, w1
+        b.ne    1b
+        sub     x3, x0, #1
+        b       1b
+2:      mov     x0, x3
+        ret
+ENDPROC(strrchr)
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index afadae6682ed..52638171d6fd 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -57,16 +57,16 @@ void show_pte(struct mm_struct *mm, unsigned long addr)
                 pmd_t *pmd;
                 pte_t *pte;
 
-                if (pgd_none_or_clear_bad(pgd))
+                if (pgd_none(*pgd) || pgd_bad(*pgd))
                         break;
 
                 pud = pud_offset(pgd, addr);
-                if (pud_none_or_clear_bad(pud))
+                if (pud_none(*pud) || pud_bad(*pud))
                         break;
 
                 pmd = pmd_offset(pud, addr);
                 printk(", *pmd=%016llx", pmd_val(*pmd));
-                if (pmd_none_or_clear_bad(pmd))
+                if (pmd_none(*pmd) || pmd_bad(*pmd))
                         break;
 
                 pte = pte_offset_map(pmd, addr);
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 800aac306a08..f497ca77925a 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -197,24 +197,6 @@ void __init bootmem_init(void)
         max_pfn = max_low_pfn = max;
 }
 
-static inline int free_area(unsigned long pfn, unsigned long end, char *s)
-{
-        unsigned int pages = 0, size = (end - pfn) << (PAGE_SHIFT - 10);
-
-        for (; pfn < end; pfn++) {
-                struct page *page = pfn_to_page(pfn);
-                ClearPageReserved(page);
-                init_page_count(page);
-                __free_page(page);
-                pages++;
-        }
-
-        if (size && s)
-                pr_info("Freeing %s memory: %dK\n", s, size);
-
-        return pages;
-}
-
 /*
  * Poison init memory with an undefined instruction (0x0).
  */
@@ -405,9 +387,7 @@ void __init mem_init(void)
 void free_initmem(void)
 {
         poison_init_mem(__init_begin, __init_end - __init_begin);
-        totalram_pages += free_area(__phys_to_pfn(__pa(__init_begin)),
-                                    __phys_to_pfn(__pa(__init_end)),
-                                    "init");
+        free_initmem_default(0);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
@@ -418,9 +398,7 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 {
         if (!keep_initrd) {
                 poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
-                totalram_pages += free_area(__phys_to_pfn(__pa(start)),
-                                            __phys_to_pfn(__pa(end)),
-                                            "initrd");
+                free_reserved_area(start, end, 0, "initrd");
         }
 }
 
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index 70b8cd4021c4..eeecc9c8ed68 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -391,17 +391,14 @@ int kern_addr_valid(unsigned long addr)
 }
 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 #ifdef CONFIG_ARM64_64K_PAGES
-int __meminit vmemmap_populate(struct page *start_page,
-                               unsigned long size, int node)
+int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node)
 {
-        return vmemmap_populate_basepages(start_page, size, node);
+        return vmemmap_populate_basepages(start, end, node);
 }
 #else   /* !CONFIG_ARM64_64K_PAGES */
-int __meminit vmemmap_populate(struct page *start_page,
-                               unsigned long size, int node)
+int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node)
 {
-        unsigned long addr = (unsigned long)start_page;
-        unsigned long end = (unsigned long)(start_page + size);
+        unsigned long addr = start;
         unsigned long next;
         pgd_t *pgd;
         pud_t *pud;
@@ -434,7 +431,7 @@ int __meminit vmemmap_populate(struct page *start_page,
         return 0;
 }
 #endif  /* CONFIG_ARM64_64K_PAGES */
-void vmemmap_free(struct page *memmap, unsigned long nr_pages)
+void vmemmap_free(unsigned long start, unsigned long end)
 {
 }
 #endif  /* CONFIG_SPARSEMEM_VMEMMAP */
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index c1a868d398bd..22c40308360b 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -250,20 +250,7 @@ config ARCH_SUSPEND_POSSIBLE
         def_bool y
 
 menu "CPU Frequency scaling"
-
 source "drivers/cpufreq/Kconfig"
-
-config CPU_FREQ_AT32AP
-        bool "CPU frequency driver for AT32AP"
-        depends on CPU_FREQ && PLATFORM_AT32AP
-        default n
-        help
-          This enables the CPU frequency driver for AT32AP processors.
-
-          For details, take a look in <file:Documentation/cpu-freq>.
-
-          If in doubt, say N.
-
 endmenu
 
 endmenu
diff --git a/arch/avr32/configs/atngw100_defconfig b/arch/avr32/configs/atngw100_defconfig
index f4025db184ff..d5aff36ade92 100644
--- a/arch/avr32/configs/atngw100_defconfig
+++ b/arch/avr32/configs/atngw100_defconfig
@@ -26,7 +26,7 @@ CONFIG_CPU_FREQ=y
 # CONFIG_CPU_FREQ_STAT is not set
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_AT32AP=y
+CONFIG_AVR32_AT32AP_CPUFREQ=y
 CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
 CONFIG_NET=y
 CONFIG_PACKET=y
diff --git a/arch/avr32/configs/atngw100_evklcd100_defconfig b/arch/avr32/configs/atngw100_evklcd100_defconfig
index c76a49b9e9d0..4abcf435d599 100644
--- a/arch/avr32/configs/atngw100_evklcd100_defconfig
+++ b/arch/avr32/configs/atngw100_evklcd100_defconfig
@@ -28,7 +28,7 @@ CONFIG_CPU_FREQ=y
 # CONFIG_CPU_FREQ_STAT is not set
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_AT32AP=y
+CONFIG_AVR32_AT32AP_CPUFREQ=y
 CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
 CONFIG_NET=y
 CONFIG_PACKET=y
diff --git a/arch/avr32/configs/atngw100_evklcd101_defconfig b/arch/avr32/configs/atngw100_evklcd101_defconfig
index 2d8ab089a64e..18f3fa0470ff 100644
--- a/arch/avr32/configs/atngw100_evklcd101_defconfig
+++ b/arch/avr32/configs/atngw100_evklcd101_defconfig
@@ -27,7 +27,7 @@ CONFIG_CPU_FREQ=y
 # CONFIG_CPU_FREQ_STAT is not set
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_AT32AP=y
+CONFIG_AVR32_AT32AP_CPUFREQ=y
 CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
 CONFIG_NET=y
 CONFIG_PACKET=y
diff --git a/arch/avr32/configs/atngw100_mrmt_defconfig b/arch/avr32/configs/atngw100_mrmt_defconfig
index b189e0cab04b..06e389cfcd12 100644
--- a/arch/avr32/configs/atngw100_mrmt_defconfig
+++ b/arch/avr32/configs/atngw100_mrmt_defconfig
@@ -23,7 +23,7 @@ CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_GOV_POWERSAVE=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
 CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_AT32AP=y
+CONFIG_AVR32_AT32AP_CPUFREQ=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/avr32/configs/atngw100mkii_defconfig b/arch/avr32/configs/atngw100mkii_defconfig
index 2e4de42a53c4..2518a1368d7c 100644
--- a/arch/avr32/configs/atngw100mkii_defconfig
+++ b/arch/avr32/configs/atngw100mkii_defconfig
@@ -26,7 +26,7 @@ CONFIG_CPU_FREQ=y
 # CONFIG_CPU_FREQ_STAT is not set
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_AT32AP=y
+CONFIG_AVR32_AT32AP_CPUFREQ=y
 CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
 CONFIG_NET=y
 CONFIG_PACKET=y
diff --git a/arch/avr32/configs/atngw100mkii_evklcd100_defconfig b/arch/avr32/configs/atngw100mkii_evklcd100_defconfig
index fad3cd22dfd3..245ef6bd0fa6 100644
--- a/arch/avr32/configs/atngw100mkii_evklcd100_defconfig
+++ b/arch/avr32/configs/atngw100mkii_evklcd100_defconfig
@@ -29,7 +29,7 @@ CONFIG_CPU_FREQ=y
 # CONFIG_CPU_FREQ_STAT is not set
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_AT32AP=y
+CONFIG_AVR32_AT32AP_CPUFREQ=y
 CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
 CONFIG_NET=y
 CONFIG_PACKET=y
diff --git a/arch/avr32/configs/atngw100mkii_evklcd101_defconfig b/arch/avr32/configs/atngw100mkii_evklcd101_defconfig
index 29986230aaa5..fa6cbac6e418 100644
--- a/arch/avr32/configs/atngw100mkii_evklcd101_defconfig
+++ b/arch/avr32/configs/atngw100mkii_evklcd101_defconfig
@@ -28,7 +28,7 @@ CONFIG_CPU_FREQ=y
 # CONFIG_CPU_FREQ_STAT is not set
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_AT32AP=y
+CONFIG_AVR32_AT32AP_CPUFREQ=y
 CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
 CONFIG_NET=y
 CONFIG_PACKET=y
diff --git a/arch/avr32/configs/atstk1002_defconfig b/arch/avr32/configs/atstk1002_defconfig
index a582465e1cef..bbd5131021a5 100644
--- a/arch/avr32/configs/atstk1002_defconfig
+++ b/arch/avr32/configs/atstk1002_defconfig
@@ -25,7 +25,7 @@ CONFIG_CPU_FREQ=y
 # CONFIG_CPU_FREQ_STAT is not set
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_AT32AP=y
+CONFIG_AVR32_AT32AP_CPUFREQ=y
 CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
 CONFIG_NET=y
 CONFIG_PACKET=y
diff --git a/arch/avr32/configs/atstk1003_defconfig b/arch/avr32/configs/atstk1003_defconfig
index 57a79df2ce5d..c1cd726f9012 100644
--- a/arch/avr32/configs/atstk1003_defconfig
+++ b/arch/avr32/configs/atstk1003_defconfig
@@ -26,7 +26,7 @@ CONFIG_CPU_FREQ=y
 # CONFIG_CPU_FREQ_STAT is not set
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_AT32AP=y
+CONFIG_AVR32_AT32AP_CPUFREQ=y
 CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
 CONFIG_NET=y
 CONFIG_PACKET=y
diff --git a/arch/avr32/configs/atstk1004_defconfig b/arch/avr32/configs/atstk1004_defconfig
index 1a49bd8c6340..754ae56b2767 100644
--- a/arch/avr32/configs/atstk1004_defconfig
+++ b/arch/avr32/configs/atstk1004_defconfig
@@ -26,7 +26,7 @@ CONFIG_CPU_FREQ=y
 # CONFIG_CPU_FREQ_STAT is not set
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_AT32AP=y
+CONFIG_AVR32_AT32AP_CPUFREQ=y
 CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
 CONFIG_NET=y
 CONFIG_PACKET=y
diff --git a/arch/avr32/configs/atstk1006_defconfig b/arch/avr32/configs/atstk1006_defconfig
index 206a1b67f763..58589d8cc0ac 100644
--- a/arch/avr32/configs/atstk1006_defconfig
+++ b/arch/avr32/configs/atstk1006_defconfig
@@ -26,7 +26,7 @@ CONFIG_CPU_FREQ=y
 # CONFIG_CPU_FREQ_STAT is not set
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_AT32AP=y
+CONFIG_AVR32_AT32AP_CPUFREQ=y
 CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
 CONFIG_NET=y
 CONFIG_PACKET=y
diff --git a/arch/avr32/configs/favr-32_defconfig b/arch/avr32/configs/favr-32_defconfig
index 0421498d666b..c90fbf6d35bc 100644
--- a/arch/avr32/configs/favr-32_defconfig
+++ b/arch/avr32/configs/favr-32_defconfig
@@ -27,7 +27,7 @@ CONFIG_CPU_FREQ=y
 # CONFIG_CPU_FREQ_STAT is not set
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_AT32AP=y
+CONFIG_AVR32_AT32AP_CPUFREQ=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -122,7 +122,6 @@ CONFIG_USB_G_SERIAL=m
 CONFIG_USB_CDC_COMPOSITE=m
 CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=y
-CONFIG_MMC_ATMELMCI_DMA=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_ATMEL_PWM=m
diff --git a/arch/avr32/configs/hammerhead_defconfig b/arch/avr32/configs/hammerhead_defconfig
index 82f24eb251bd..ba7c31e269cb 100644
--- a/arch/avr32/configs/hammerhead_defconfig
+++ b/arch/avr32/configs/hammerhead_defconfig
@@ -31,7 +31,7 @@ CONFIG_CPU_FREQ=y
 # CONFIG_CPU_FREQ_STAT is not set
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_AT32AP=y
+CONFIG_AVR32_AT32AP_CPUFREQ=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/avr32/configs/merisc_defconfig b/arch/avr32/configs/merisc_defconfig
index 3befab966827..65de4431108c 100644
--- a/arch/avr32/configs/merisc_defconfig
+++ b/arch/avr32/configs/merisc_defconfig
@@ -102,7 +102,6 @@ CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
 CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=y
-CONFIG_MMC_ATMELMCI_DMA=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_ATMEL_PWM=y
diff --git a/arch/avr32/configs/mimc200_defconfig b/arch/avr32/configs/mimc200_defconfig
index 1bee51f22154..0a8bfdc420e0 100644
--- a/arch/avr32/configs/mimc200_defconfig
+++ b/arch/avr32/configs/mimc200_defconfig
@@ -24,7 +24,7 @@ CONFIG_CPU_FREQ=y
 # CONFIG_CPU_FREQ_STAT is not set
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_AT32AP=y
+CONFIG_AVR32_AT32AP_CPUFREQ=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
diff --git a/arch/avr32/include/asm/unistd.h b/arch/avr32/include/asm/unistd.h
index dc4d5a931112..c1eb080e45fe 100644
--- a/arch/avr32/include/asm/unistd.h
+++ b/arch/avr32/include/asm/unistd.h
@@ -41,12 +41,4 @@
 #define __ARCH_WANT_SYS_VFORK
 #define __ARCH_WANT_SYS_CLONE
 
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall");
-
 #endif /* __ASM_AVR32_UNISTD_H */
diff --git a/arch/avr32/kernel/process.c b/arch/avr32/kernel/process.c
index fd78f58ea79a..e7b61494c312 100644
--- a/arch/avr32/kernel/process.c
+++ b/arch/avr32/kernel/process.c
@@ -30,18 +30,9 @@ EXPORT_SYMBOL(pm_power_off);
  * This file handles the architecture-dependent parts of process handling..
  */
 
-void cpu_idle(void)
+void arch_cpu_idle(void)
 {
-        /* endless idle loop with no priority at all */
-        while (1) {
-                tick_nohz_idle_enter();
-                rcu_idle_enter();
-                while (!need_resched())
-                        cpu_idle_sleep();
-                rcu_idle_exit();
-                tick_nohz_idle_exit();
-                schedule_preempt_disabled();
-        }
+        cpu_enter_idle();
 }
 
 void machine_halt(void)
@@ -213,14 +204,6 @@ void show_stack(struct task_struct *tsk, unsigned long *stack)
         show_stack_log_lvl(tsk, (unsigned long)stack, NULL, "");
 }
 
-void dump_stack(void)
-{
-        unsigned long stack;
-
-        show_trace_log_lvl(current, &stack, NULL, "");
-}
-EXPORT_SYMBOL(dump_stack);
-
 static const char *cpu_modes[] = {
         "Application", "Supervisor", "Interrupt level 0", "Interrupt level 1",
         "Interrupt level 2", "Interrupt level 3", "Exception", "NMI"
@@ -232,6 +215,8 @@ void show_regs_log_lvl(struct pt_regs *regs, const char *log_lvl)
         unsigned long lr = regs->lr;
         unsigned long mode = (regs->sr & MODE_MASK) >> MODE_SHIFT;
 
+        show_regs_print_info(log_lvl);
+
         if (!user_mode(regs)) {
                 sp = (unsigned long)regs + FRAME_SIZE_FULL;
 
@@ -269,9 +254,6 @@ void show_regs_log_lvl(struct pt_regs *regs, const char *log_lvl)
                regs->sr & SR_I0M ? '0' : '.',
                regs->sr & SR_GM ? 'G' : 'g');
         printk("%sCPU Mode: %s\n", log_lvl, cpu_modes[mode]);
-        printk("%sProcess: %s [%d] (task: %p thread: %p)\n",
-               log_lvl, current->comm, current->pid, current,
-               task_thread_info(current));
 }
 
 void show_regs(struct pt_regs *regs)
diff --git a/arch/avr32/kernel/time.c b/arch/avr32/kernel/time.c
index 05ad29112ff4..869a1c6ffeee 100644
--- a/arch/avr32/kernel/time.c
+++ b/arch/avr32/kernel/time.c
@@ -12,6 +12,7 @@
 #include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/time.h>
+#include <linux/cpu.h>
 
 #include <asm/sysreg.h>
 
@@ -87,13 +88,17 @@ static void comparator_mode(enum clock_event_mode mode,
                 pr_debug("%s: start\n", evdev->name);
                 /* FALLTHROUGH */
         case CLOCK_EVT_MODE_RESUME:
-                cpu_disable_idle_sleep();
+                /*
+                 * If we're using the COUNT and COMPARE registers we
+                 * need to force idle poll.
+                 */
+                cpu_idle_poll_ctrl(true);
                 break;
         case CLOCK_EVT_MODE_UNUSED:
         case CLOCK_EVT_MODE_SHUTDOWN:
                 sysreg_write(COMPARE, 0);
                 pr_debug("%s: stop\n", evdev->name);
-                cpu_enable_idle_sleep();
+                cpu_idle_poll_ctrl(false);
                 break;
         default:
                 BUG();
diff --git a/arch/avr32/mach-at32ap/Makefile b/arch/avr32/mach-at32ap/Makefile
index 514c9a9b009a..fc09ec4bc725 100644
--- a/arch/avr32/mach-at32ap/Makefile
+++ b/arch/avr32/mach-at32ap/Makefile
@@ -1,7 +1,6 @@
 obj-y                           += pdc.o clock.o intc.o extint.o pio.o hsmc.o
 obj-y                           += hmatrix.o
 obj-$(CONFIG_CPU_AT32AP700X)    += at32ap700x.o pm-at32ap700x.o
-obj-$(CONFIG_CPU_FREQ_AT32AP)   += cpufreq.o
 obj-$(CONFIG_PM)                += pm.o
 
 ifeq ($(CONFIG_PM_DEBUG),y)
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index b323d8d3185b..7c2f6685bf43 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -1453,7 +1453,7 @@ static struct resource atmel_lcdfb0_resource[] = {
         },
 };
 DEFINE_DEV_DATA(atmel_lcdfb, 0);
-DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
+DEV_CLK(hclk, atmel_lcdfb0, hsb, 7);
 static struct clk atmel_lcdfb0_pixclk = {
         .name           = "lcdc_clk",
         .dev            = &atmel_lcdfb0_device.dev,
@@ -1530,6 +1530,8 @@ at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
         info->default_monspecs = monspecs;
 
+        pdev->name = "at32ap-lcdfb";
+
         platform_device_register(pdev);
         return pdev;
 
@@ -2246,7 +2248,7 @@ static __initdata struct clk *init_clocks[] = {
         &atmel_twi0_pclk,
         &atmel_mci0_pclk,
 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
-        &atmel_lcdfb0_hck1,
+        &atmel_lcdfb0_hclk,
         &atmel_lcdfb0_pixclk,
 #endif
         &ssc0_pclk,
diff --git a/arch/avr32/mach-at32ap/cpufreq.c b/arch/avr32/mach-at32ap/cpufreq.c
deleted file mode 100644
index 18b765629a0c..000000000000
--- a/arch/avr32/mach-at32ap/cpufreq.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Copyright (C) 2004-2007 Atmel Corporation
- *
- * Based on MIPS implementation arch/mips/kernel/time.c
- *   Copyright 2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/*#define DEBUG*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/cpufreq.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/export.h>
-
-static struct clk *cpuclk;
-
-static int at32_verify_speed(struct cpufreq_policy *policy)
-{
-        if (policy->cpu != 0)
-                return -EINVAL;
-
-        cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
-                        policy->cpuinfo.max_freq);
-        return 0;
-}
-
-static unsigned int at32_get_speed(unsigned int cpu)
-{
-        /* No SMP support */
-        if (cpu)
-                return 0;
-        return (unsigned int)((clk_get_rate(cpuclk) + 500) / 1000);
-}
-
-static unsigned int     ref_freq;
-static unsigned long    loops_per_jiffy_ref;
-
-static int at32_set_target(struct cpufreq_policy *policy,
-                          unsigned int target_freq,
-                          unsigned int relation)
-{
-        struct cpufreq_freqs freqs;
-        long freq;
-
-        /* Convert target_freq from kHz to Hz */
-        freq = clk_round_rate(cpuclk, target_freq * 1000);
-
-        /* Check if policy->min <= new_freq <= policy->max */
-        if(freq < (policy->min * 1000) || freq > (policy->max * 1000))
-                return -EINVAL;
-
-        pr_debug("cpufreq: requested frequency %u Hz\n", target_freq * 1000);
-
-        freqs.old = at32_get_speed(0);
-        freqs.new = (freq + 500) / 1000;
-        freqs.cpu = 0;
-        freqs.flags = 0;
-
-        if (!ref_freq) {
-                ref_freq = freqs.old;
-                loops_per_jiffy_ref = boot_cpu_data.loops_per_jiffy;
-        }
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-        if (freqs.old < freqs.new)
-                boot_cpu_data.loops_per_jiffy = cpufreq_scale(
-                                loops_per_jiffy_ref, ref_freq, freqs.new);
-        clk_set_rate(cpuclk, freq);
-        if (freqs.new < freqs.old)
-                boot_cpu_data.loops_per_jiffy = cpufreq_scale(
-                                loops_per_jiffy_ref, ref_freq, freqs.new);
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
-        pr_debug("cpufreq: set frequency %lu Hz\n", freq);
-
-        return 0;
-}
-
-static int __init at32_cpufreq_driver_init(struct cpufreq_policy *policy)
-{
-        if (policy->cpu != 0)
-                return -EINVAL;
-
-        cpuclk = clk_get(NULL, "cpu");
-        if (IS_ERR(cpuclk)) {
-                pr_debug("cpufreq: could not get CPU clk\n");
-                return PTR_ERR(cpuclk);
-        }
-
-        policy->cpuinfo.min_freq = (clk_round_rate(cpuclk, 1) + 500) / 1000;
-        policy->cpuinfo.max_freq = (clk_round_rate(cpuclk, ~0UL) + 500) / 1000;
-        policy->cpuinfo.transition_latency = 0;
-        policy->cur = at32_get_speed(0);
-        policy->min = policy->cpuinfo.min_freq;
-        policy->max = policy->cpuinfo.max_freq;
-
-        printk("cpufreq: AT32AP CPU frequency driver\n");
-
-        return 0;
-}
-
-static struct cpufreq_driver at32_driver = {
-        .name           = "at32ap",
-        .owner          = THIS_MODULE,
-        .init           = at32_cpufreq_driver_init,
-        .verify         = at32_verify_speed,
-        .target         = at32_set_target,
-        .get            = at32_get_speed,
-        .flags          = CPUFREQ_STICKY,
-};
-
-static int __init at32_cpufreq_init(void)
-{
-        return cpufreq_register_driver(&at32_driver);
-}
-late_initcall(at32_cpufreq_init);
diff --git a/arch/avr32/mach-at32ap/include/mach/pm.h b/arch/avr32/mach-at32ap/include/mach/pm.h
index 979b355b77b6..f29ff2cd23d3 100644
--- a/arch/avr32/mach-at32ap/include/mach/pm.h
+++ b/arch/avr32/mach-at32ap/include/mach/pm.h
@@ -21,30 +21,6 @@
 extern void cpu_enter_idle(void);
 extern void cpu_enter_standby(unsigned long sdramc_base);
 
-extern bool disable_idle_sleep;
-
-static inline void cpu_disable_idle_sleep(void)
-{
-        disable_idle_sleep = true;
-}
-
-static inline void cpu_enable_idle_sleep(void)
-{
-        disable_idle_sleep = false;
-}
-
-static inline void cpu_idle_sleep(void)
-{
-        /*
-         * If we're using the COUNT and COMPARE registers for
-         * timekeeping, we can't use the IDLE state.
-         */
-        if (disable_idle_sleep)
-                cpu_relax();
-        else
-                cpu_enter_idle();
-}
-
 void intc_set_suspend_handler(unsigned long offset);
 #endif
 
diff --git a/arch/avr32/mach-at32ap/pm-at32ap700x.S b/arch/avr32/mach-at32ap/pm-at32ap700x.S
index f868f4ce761b..1c8e4e6bff03 100644
--- a/arch/avr32/mach-at32ap/pm-at32ap700x.S
+++ b/arch/avr32/mach-at32ap/pm-at32ap700x.S
@@ -18,13 +18,6 @@
 /* Same as 0xfff00000 but fits in a 21 bit signed immediate */
 #define PM_BASE -0x100000
 
-        .section .bss, "wa", @nobits
-        .global disable_idle_sleep
-        .type   disable_idle_sleep, @object
-disable_idle_sleep:
-        .int    4
-        .size   disable_idle_sleep, . - disable_idle_sleep
-
         /* Keep this close to the irq handlers */
         .section .irq.text, "ax", @progbits
 
diff --git a/arch/avr32/mm/init.c b/arch/avr32/mm/init.c
index 2798c2d4a1cf..e66e8406f992 100644
--- a/arch/avr32/mm/init.c
+++ b/arch/avr32/mm/init.c
@@ -146,34 +146,14 @@ void __init mem_init(void)
                 initsize >> 10);
 }
 
-static inline void free_area(unsigned long addr, unsigned long end, char *s)
-{
-        unsigned int size = (end - addr) >> 10;
-
-        for (; addr < end; addr += PAGE_SIZE) {
-                struct page *page = virt_to_page(addr);
-                ClearPageReserved(page);
-                init_page_count(page);
-                free_page(addr);
-                totalram_pages++;
-        }
-
-        if (size && s)
-                printk(KERN_INFO "Freeing %s memory: %dK (%lx - %lx)\n",
-                       s, size, end - (size << 10), end);
-}
-
 void free_initmem(void)
 {
-        free_area((unsigned long)__init_begin, (unsigned long)__init_end,
-                  "init");
+        free_initmem_default(0);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
-
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_area(start, end, "initrd");
+        free_reserved_area(start, end, 0, "initrd");
 }
-
 #endif
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index c3f2e0bc644a..453ebe46b065 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -1,7 +1,3 @@
-config SYMBOL_PREFIX
-        string
-        default "_"
-
 config MMU
         def_bool n
 
@@ -33,6 +29,7 @@ config BLACKFIN
         select ARCH_HAVE_CUSTOM_GPIO_H
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select HAVE_UID16
+        select HAVE_UNDERSCORE_SYMBOL_PREFIX
         select VIRT_TO_BUS
         select ARCH_WANT_IPC_PARSE_VERSION
         select HAVE_GENERIC_HARDIRQS
diff --git a/arch/blackfin/include/asm/bfin_sport3.h b/arch/blackfin/include/asm/bfin_sport3.h
index 03c00220d69b..d82f5fa0ad9f 100644
--- a/arch/blackfin/include/asm/bfin_sport3.h
+++ b/arch/blackfin/include/asm/bfin_sport3.h
@@ -41,7 +41,7 @@
 #define SPORT_CTL_LAFS                0x00020000    /* Late Transmit frame select */
 #define SPORT_CTL_RJUST               0x00040000    /* Right Justified mode select */
 #define SPORT_CTL_FSED                0x00080000    /* External frame sync edge select */
-#define SPORT_CTL_TFIEN               0x00100000    /* Transmit finish interrrupt enable select */
+#define SPORT_CTL_TFIEN               0x00100000    /* Transmit finish interrupt enable select */
 #define SPORT_CTL_GCLKEN              0x00200000    /* Gated clock mode select */
 #define SPORT_CTL_SPENSEC             0x01000000    /* Enable secondary channel */
 #define SPORT_CTL_SPTRAN              0x02000000    /* Data direction control */
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
index 04e83ea8d5cc..c35414bdf7bd 100644
--- a/arch/blackfin/include/asm/unistd.h
+++ b/arch/blackfin/include/asm/unistd.h
@@ -20,12 +20,4 @@
 #define __ARCH_WANT_SYS_NICE
 #define __ARCH_WANT_SYS_VFORK
 
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t_" #x "\n\t.set\t_" #x ",_sys_ni_syscall");
-
 #endif                          /* __ASM_BFIN_UNISTD_H */
diff --git a/arch/blackfin/kernel/cplbinfo.c b/arch/blackfin/kernel/cplbinfo.c
index e1d0b24c6070..404045dcc5e4 100644
--- a/arch/blackfin/kernel/cplbinfo.c
+++ b/arch/blackfin/kernel/cplbinfo.c
@@ -116,14 +116,12 @@ static const struct seq_operations cplbinfo_sops = {
 
 static int cplbinfo_open(struct inode *inode, struct file *file)
 {
-        struct proc_dir_entry *pde = PDE(file_inode(file));
         char cplb_type;
-        unsigned int cpu;
+        unsigned int cpu = (unsigned long)PDE_DATA(file_inode(file));
         int ret;
         struct seq_file *m;
         struct cplbinfo_data *cdata;
 
-        cpu = (unsigned int)pde->data;
         cplb_type = cpu & CPLBINFO_DCPLB_FLAG ? 'D' : 'I';
         cpu &= ~CPLBINFO_DCPLB_FLAG;
 
diff --git a/arch/blackfin/kernel/dumpstack.c b/arch/blackfin/kernel/dumpstack.c
index 5cfbaa298211..95ba6d9e9a3d 100644
--- a/arch/blackfin/kernel/dumpstack.c
+++ b/arch/blackfin/kernel/dumpstack.c
@@ -168,6 +168,7 @@ void dump_stack(void)
 #endif
         trace_buffer_save(tflags);
         dump_bfin_trace_buffer();
+        dump_stack_print_info(KERN_DEFAULT);
         show_stack(current, &stack);
         trace_buffer_restore(tflags);
 }
diff --git a/arch/blackfin/kernel/early_printk.c b/arch/blackfin/kernel/early_printk.c
index 84ed8375113c..61fbd2de993d 100644
--- a/arch/blackfin/kernel/early_printk.c
+++ b/arch/blackfin/kernel/early_printk.c
@@ -25,8 +25,6 @@ extern struct console *bfin_earlyserial_init(unsigned int port,
 extern struct console *bfin_jc_early_init(void);
 #endif
 
-static struct console *early_console;
-
 /* Default console */
 #define DEFAULT_PORT 0
 #define DEFAULT_CFLAG CS8|B57600
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index 9782c0329c14..4aa5545c4fde 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -46,15 +46,14 @@ EXPORT_SYMBOL(pm_power_off);
  * The idle loop on BFIN
  */
 #ifdef CONFIG_IDLE_L1
-static void default_idle(void)__attribute__((l1_text));
-void cpu_idle(void)__attribute__((l1_text));
+void arch_cpu_idle(void)__attribute__((l1_text));
 #endif
 
 /*
  * This is our default idle handler.  We need to disable
  * interrupts here to ensure we don't miss a wakeup call.
  */
-static void default_idle(void)
+void arch_cpu_idle(void)
 {
 #ifdef CONFIG_IPIPE
         ipipe_suspend_domain();
@@ -66,31 +65,12 @@ static void default_idle(void)
         hard_local_irq_enable();
 }
 
-/*
- * The idle thread.  We try to conserve power, while trying to keep
- * overall latency low.  The architecture specific idle is passed
- * a value to indicate the level of "idleness" of the system.
- */
-void cpu_idle(void)
-{
-        /* endless idle loop with no priority at all */
-        while (1) {
-
 #ifdef CONFIG_HOTPLUG_CPU
-                if (cpu_is_offline(smp_processor_id()))
-                        cpu_die();
-#endif
-                tick_nohz_idle_enter();
-                rcu_idle_enter();
-                while (!need_resched())
-                        default_idle();
-                rcu_idle_exit();
-                tick_nohz_idle_exit();
-                preempt_enable_no_resched();
-                schedule();
-                preempt_disable();
-        }
+void arch_cpu_idle_dead(void)
+{
+        cpu_die();
 }
+#endif
 
 /*
  * Do necessary setup to start up a newly executed thread.
diff --git a/arch/blackfin/kernel/trace.c b/arch/blackfin/kernel/trace.c
index f7f7a18abca9..c36efa0c7163 100644
--- a/arch/blackfin/kernel/trace.c
+++ b/arch/blackfin/kernel/trace.c
@@ -853,6 +853,8 @@ void show_regs(struct pt_regs *fp)
         unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
 
         pr_notice("\n");
+        show_regs_print_info(KERN_NOTICE);
+
         if (CPUID != bfin_cpuid())
                 pr_notice("Compiled for cpu family 0x%04x (Rev %d), "
                         "but running on:0x%04x (Rev %d)\n",
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c
index 61c1f47a4bf2..97d701639585 100644
--- a/arch/blackfin/mach-bf609/boards/ezkit.c
+++ b/arch/blackfin/mach-bf609/boards/ezkit.c
@@ -936,19 +936,19 @@ static struct v4l2_input adv7842_inputs[] = {
                 .index = 2,
                 .name = "Component",
                 .type = V4L2_INPUT_TYPE_CAMERA,
-                .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
+                .capabilities = V4L2_IN_CAP_DV_TIMINGS,
         },
         {
                 .index = 3,
                 .name = "VGA",
                 .type = V4L2_INPUT_TYPE_CAMERA,
-                .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
+                .capabilities = V4L2_IN_CAP_DV_TIMINGS,
         },
         {
                 .index = 4,
                 .name = "HDMI",
                 .type = V4L2_INPUT_TYPE_CAMERA,
-                .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
+                .capabilities = V4L2_IN_CAP_DV_TIMINGS,
         },
 };
 
@@ -1074,7 +1074,7 @@ static struct v4l2_output adv7511_outputs[] = {
                 .index = 0,
                 .name = "HDMI",
                 .type = V4L2_INPUT_TYPE_CAMERA,
-                .capabilities = V4L2_OUT_CAP_CUSTOM_TIMINGS,
+                .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
         },
 };
 
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
index 75f0ba29ebb9..675466d490d4 100644
--- a/arch/blackfin/mach-common/Makefile
+++ b/arch/blackfin/mach-common/Makefile
@@ -10,7 +10,6 @@ obj-$(CONFIG_PM)          += pm.o
 ifneq ($(CONFIG_BF60x),y)
 obj-$(CONFIG_PM)          += dpmc_modes.o
 endif
-obj-$(CONFIG_CPU_FREQ)    += cpufreq.o
 obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
 obj-$(CONFIG_SMP)         += smp.o
 obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c
deleted file mode 100644
index d88bd31319e6..000000000000
--- a/arch/blackfin/mach-common/cpufreq.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * Blackfin core clock scaling
- *
- * Copyright 2008-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/cpufreq.h>
-#include <linux/fs.h>
-#include <linux/delay.h>
-#include <asm/blackfin.h>
-#include <asm/time.h>
-#include <asm/dpmc.h>
-
-
-/* this is the table of CCLK frequencies, in Hz */
-/* .index is the entry in the auxiliary dpm_state_table[] */
-static struct cpufreq_frequency_table bfin_freq_table[] = {
-        {
-                .frequency = CPUFREQ_TABLE_END,
-                .index = 0,
-        },
-        {
-                .frequency = CPUFREQ_TABLE_END,
-                .index = 1,
-        },
-        {
-                .frequency = CPUFREQ_TABLE_END,
-                .index = 2,
-        },
-        {
-                .frequency = CPUFREQ_TABLE_END,
-                .index = 0,
-        },
-};
-
-static struct bfin_dpm_state {
-        unsigned int csel; /* system clock divider */
-        unsigned int tscale; /* change the divider on the core timer interrupt */
-} dpm_state_table[3];
-
-#if defined(CONFIG_CYCLES_CLOCKSOURCE)
-/*
- * normalized to maximum frequency offset for CYCLES,
- * used in time-ts cycles clock source, but could be used
- * somewhere also.
- */
-unsigned long long __bfin_cycles_off;
-unsigned int __bfin_cycles_mod;
-#endif
-
-/**************************************************************************/
-static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
-{
-
-        unsigned long csel, min_cclk;
-        int index;
-
-        /* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */
-#if ANOMALY_05000273 || ANOMALY_05000274 || \
-        (!(defined(CONFIG_BF54x) || defined(CONFIG_BF60x)) \
-        && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
-        min_cclk = sclk * 2;
-#else
-        min_cclk = sclk;
-#endif
-
-#ifndef CONFIG_BF60x
-        csel = ((bfin_read_PLL_DIV() & CSEL) >> 4);
-#else
-        csel = bfin_read32(CGU0_DIV) & 0x1F;
-#endif
-
-        for (index = 0;  (cclk >> index) >= min_cclk && csel <= 3 && index < 3; index++, csel++) {
-                bfin_freq_table[index].frequency = cclk >> index;
-#ifndef CONFIG_BF60x
-                dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
-#else
-                dpm_state_table[index].csel = csel;
-#endif
-                dpm_state_table[index].tscale =  (TIME_SCALE >> index) - 1;
-
-                pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n",
-                                                 bfin_freq_table[index].frequency,
-                                                 dpm_state_table[index].csel,
-                                                 dpm_state_table[index].tscale);
-        }
-        return;
-}
-
-static void bfin_adjust_core_timer(void *info)
-{
-        unsigned int tscale;
-        unsigned int index = *(unsigned int *)info;
-
-        /* we have to adjust the core timer, because it is using cclk */
-        tscale = dpm_state_table[index].tscale;
-        bfin_write_TSCALE(tscale);
-        return;
-}
-
-static unsigned int bfin_getfreq_khz(unsigned int cpu)
-{
-        /* Both CoreA/B have the same core clock */
-        return get_cclk() / 1000;
-}
-
-#ifdef CONFIG_BF60x
-unsigned long cpu_set_cclk(int cpu, unsigned long new)
-{
-        struct clk *clk;
-        int ret;
-
-        clk = clk_get(NULL, "CCLK");
-        if (IS_ERR(clk))
-                return -ENODEV;
-
-        ret = clk_set_rate(clk, new);
-        clk_put(clk);
-        return ret;
-}
-#endif
-
-static int bfin_target(struct cpufreq_policy *poli,
-                        unsigned int target_freq, unsigned int relation)
-{
-#ifndef CONFIG_BF60x
-        unsigned int plldiv;
-#endif
-        unsigned int index, cpu;
-        unsigned long cclk_hz;
-        struct cpufreq_freqs freqs;
-        static unsigned long lpj_ref;
-        static unsigned int  lpj_ref_freq;
-        int ret = 0;
-
-#if defined(CONFIG_CYCLES_CLOCKSOURCE)
-        cycles_t cycles;
-#endif
-
-        for_each_online_cpu(cpu) {
-                struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
-
-                if (!policy)
-                        continue;
-
-                if (cpufreq_frequency_table_target(policy, bfin_freq_table,
-                                 target_freq, relation, &index))
-                        return -EINVAL;
-
-                cclk_hz = bfin_freq_table[index].frequency;
-
-                freqs.old = bfin_getfreq_khz(0);
-                freqs.new = cclk_hz;
-                freqs.cpu = cpu;
-
-                pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n",
-                         cclk_hz, target_freq, freqs.old);
-
-                cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-                if (cpu == CPUFREQ_CPU) {
-#ifndef CONFIG_BF60x
-                        plldiv = (bfin_read_PLL_DIV() & SSEL) |
-                                                dpm_state_table[index].csel;
-                        bfin_write_PLL_DIV(plldiv);
-#else
-                        ret = cpu_set_cclk(cpu, freqs.new * 1000);
-                        if (ret != 0) {
-                                WARN_ONCE(ret, "cpufreq set freq failed %d\n", ret);
-                                break;
-                        }
-#endif
-                        on_each_cpu(bfin_adjust_core_timer, &index, 1);
-#if defined(CONFIG_CYCLES_CLOCKSOURCE)
-                        cycles = get_cycles();
-                        SSYNC();
-                        cycles += 10; /* ~10 cycles we lose after get_cycles() */
-                        __bfin_cycles_off +=
-                            (cycles << __bfin_cycles_mod) - (cycles << index);
-                        __bfin_cycles_mod = index;
-#endif
-                        if (!lpj_ref_freq) {
-                                lpj_ref = loops_per_jiffy;
-                                lpj_ref_freq = freqs.old;
-                        }
-                        if (freqs.new != freqs.old) {
-                                loops_per_jiffy = cpufreq_scale(lpj_ref,
-                                                lpj_ref_freq, freqs.new);
-                        }
-                }
-                /* TODO: just test case for cycles clock source, remove later */
-                cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-        }
-
-        pr_debug("cpufreq: done\n");
-        return ret;
-}
-
-static int bfin_verify_speed(struct cpufreq_policy *policy)
-{
-        return cpufreq_frequency_table_verify(policy, bfin_freq_table);
-}
-
-static int __bfin_cpu_init(struct cpufreq_policy *policy)
-{
-
-        unsigned long cclk, sclk;
-
-        cclk = get_cclk() / 1000;
-        sclk = get_sclk() / 1000;
-
-        if (policy->cpu == CPUFREQ_CPU)
-                bfin_init_tables(cclk, sclk);
-
-        policy->cpuinfo.transition_latency = 50000; /* 50us assumed */
-
-        policy->cur = cclk;
-        cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);
-        return cpufreq_frequency_table_cpuinfo(policy, bfin_freq_table);
-}
-
-static struct freq_attr *bfin_freq_attr[] = {
-        &cpufreq_freq_attr_scaling_available_freqs,
-        NULL,
-};
-
-static struct cpufreq_driver bfin_driver = {
-        .verify = bfin_verify_speed,
-        .target = bfin_target,
-        .get = bfin_getfreq_khz,
-        .init = __bfin_cpu_init,
-        .name = "bfin cpufreq",
-        .owner = THIS_MODULE,
-        .attr = bfin_freq_attr,
-};
-
-static int __init bfin_cpu_init(void)
-{
-        return cpufreq_register_driver(&bfin_driver);
-}
-
-static void __exit bfin_cpu_exit(void)
-{
-        cpufreq_unregister_driver(&bfin_driver);
-}
-
-MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
-MODULE_DESCRIPTION("cpufreq driver for Blackfin");
-MODULE_LICENSE("GPL");
-
-module_init(bfin_cpu_init);
-module_exit(bfin_cpu_exit);
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index bb61ae4986e4..1bc2ce6f3c94 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -335,7 +335,7 @@ void __cpuinit secondary_start_kernel(void)
          */
         calibrate_delay();
 
-        cpu_idle();
+        cpu_startup_entry(CPUHP_ONLINE);
 }
 
 void __init smp_prepare_boot_cpu(void)
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index 9cb85537bd2b..82d01a71207f 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -103,7 +103,7 @@ void __init mem_init(void)
         max_mapnr = num_physpages = MAP_NR(high_memory);
         printk(KERN_DEBUG "Kernel managed physical pages: %lu\n", num_physpages);
 
-        /* This will put all memory onto the freelists. */
+        /* This will put all low memory onto the freelists. */
         totalram_pages = free_all_bootmem();
 
         reservedpages = 0;
@@ -129,24 +129,11 @@ void __init mem_init(void)
                 initk, codek, datak, DMA_UNCACHED_REGION >> 10, (reservedpages << (PAGE_SHIFT-10)));
 }
 
-static void __init free_init_pages(const char *what, unsigned long begin, unsigned long end)
-{
-        unsigned long addr;
-        /* next to check that the page we free is not a partial page */
-        for (addr = begin; addr + PAGE_SIZE <= end; addr += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(addr));
-                init_page_count(virt_to_page(addr));
-                free_page(addr);
-                totalram_pages++;
-        }
-        printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
-}
-
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
 #ifndef CONFIG_MPU
-        free_init_pages("initrd memory", start, end);
+        free_reserved_area(start, end, 0, "initrd");
 #endif
 }
 #endif
@@ -154,10 +141,7 @@ void __init free_initrd_mem(unsigned long start, unsigned long end)
 void __init_refok free_initmem(void)
 {
 #if defined CONFIG_RAMKERNEL && !defined CONFIG_MPU
-        free_init_pages("unused kernel memory",
-                        (unsigned long)(&__init_begin),
-                        (unsigned long)(&__init_end));
-
+        free_initmem_default(0);
         if (memory_start == (unsigned long)(&__init_end))
                 memory_start = (unsigned long)(&__init_begin);
 #endif
diff --git a/arch/c6x/kernel/process.c b/arch/c6x/kernel/process.c
index 6434df476f77..57d2ea8d1977 100644
--- a/arch/c6x/kernel/process.c
+++ b/arch/c6x/kernel/process.c
@@ -33,7 +33,7 @@ extern asmlinkage void ret_from_kernel_thread(void);
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
-static void c6x_idle(void)
+void arch_cpu_idle(void)
 {
         unsigned long tmp;
 
@@ -49,32 +49,6 @@ static void c6x_idle(void)
                       : "=b"(tmp));
 }
 
-/*
- * The idle loop for C64x
- */
-void cpu_idle(void)
-{
-        /* endless idle loop with no priority at all */
-        while (1) {
-                tick_nohz_idle_enter();
-                rcu_idle_enter();
-                while (1) {
-                        local_irq_disable();
-                        if (need_resched()) {
-                                local_irq_enable();
-                                break;
-                        }
-                        c6x_idle(); /* enables local irqs */
-                }
-                rcu_idle_exit();
-                tick_nohz_idle_exit();
-
-                preempt_enable_no_resched();
-                schedule();
-                preempt_disable();
-        }
-}
-
 static void halt_loop(void)
 {
         printk(KERN_EMERG "System Halted, OK to turn off power\n");
diff --git a/arch/c6x/kernel/traps.c b/arch/c6x/kernel/traps.c
index 1be74e5b4788..dcc2c2f6d67c 100644
--- a/arch/c6x/kernel/traps.c
+++ b/arch/c6x/kernel/traps.c
@@ -31,6 +31,7 @@ void __init trap_init(void)
 void show_regs(struct pt_regs *regs)
 {
         pr_err("\n");
+        show_regs_print_info(KERN_ERR);
         pr_err("PC: %08lx SP: %08lx\n", regs->pc, regs->sp);
         pr_err("Status: %08lx ORIG_A4: %08lx\n", regs->csr, regs->orig_a4);
         pr_err("A0: %08lx  B0: %08lx\n", regs->a0, regs->b0);
@@ -67,15 +68,6 @@ void show_regs(struct pt_regs *regs)
         pr_err("A31: %08lx  B31: %08lx\n", regs->a31, regs->b31);
 }
 
-void dump_stack(void)
-{
-        unsigned long stack;
-
-        show_stack(current, &stack);
-}
-EXPORT_SYMBOL(dump_stack);
-
-
 void die(char *str, struct pt_regs *fp, int nr)
 {
         console_verbose();
diff --git a/arch/c6x/mm/init.c b/arch/c6x/mm/init.c
index 89395f09648a..a9fcd89b251b 100644
--- a/arch/c6x/mm/init.c
+++ b/arch/c6x/mm/init.c
@@ -77,37 +77,11 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-        int pages = 0;
-        for (; start < end; start += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(start));
-                init_page_count(virt_to_page(start));
-                free_page(start);
-                totalram_pages++;
-                pages++;
-        }
-        printk(KERN_INFO "Freeing initrd memory: %luk freed\n",
-               (pages * PAGE_SIZE) >> 10);
+        free_reserved_area(start, end, 0, "initrd");
 }
 #endif
 
 void __init free_initmem(void)
 {
-        unsigned long addr;
-
-        /*
-         * The following code should be cool even if these sections
-         * are not page aligned.
-         */
-        addr = PAGE_ALIGN((unsigned long)(__init_begin));
-
-        /* next to check that the page we free is not a partial page */
-        for (; addr + PAGE_SIZE < (unsigned long)(__init_end);
-             addr += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(addr));
-                init_page_count(virt_to_page(addr));
-                free_page(addr);
-                totalram_pages++;
-        }
-        printk(KERN_INFO "Freeing unused kernel memory: %dK freed\n",
-               (int) ((addr - PAGE_ALIGN((long) &__init_begin)) >> 10));
+        free_initmem_default(0);
 }
diff --git a/arch/cris/arch-v10/kernel/fasttimer.c b/arch/cris/arch-v10/kernel/fasttimer.c
index 082f1890bacb..48a59afbeeb1 100644
--- a/arch/cris/arch-v10/kernel/fasttimer.c
+++ b/arch/cris/arch-v10/kernel/fasttimer.c
@@ -25,6 +25,7 @@
 #include <arch/svinto.h>
 #include <asm/fasttimer.h>
 #include <linux/proc_fs.h>
+#include <linux/seq_file.h>
 
 
 #define DEBUG_LOG_INCLUDED
@@ -489,197 +490,162 @@ void schedule_usleep(unsigned long us)
 }
 
 #ifdef CONFIG_PROC_FS
-static int proc_fasttimer_read(char *buf, char **start, off_t offset, int len
-                       ,int *eof, void *data_unused);
-static struct proc_dir_entry *fasttimer_proc_entry;
-#endif /* CONFIG_PROC_FS */
-
-#ifdef CONFIG_PROC_FS
-
 /* This value is very much based on testing */
 #define BIG_BUF_SIZE (500 + NUM_TIMER_STATS * 300)
 
-static int proc_fasttimer_read(char *buf, char **start, off_t offset, int len
-                       ,int *eof, void *data_unused)
+static int proc_fasttimer_show(struct seq_file *m, void *v)
 {
-  unsigned long flags;
-  int i = 0;
-  int num_to_show;
+        unsigned long flags;
+        int i = 0;
+        int num_to_show;
         struct fasttime_t tv;
-  struct fast_timer *t, *nextt;
-  static char *bigbuf = NULL;
-  static unsigned long used;
-
-  if (!bigbuf && !(bigbuf = vmalloc(BIG_BUF_SIZE)))
-  {
-    used = 0;
-        if (buf)
-                buf[0] = '\0';
-    return 0;
-  }
-
-  if (!offset || !used)
-  {
-    do_gettimeofday_fast(&tv);
-
-    used = 0;
-    used += sprintf(bigbuf + used, "Fast timers added:     %i\n",
-                    fast_timers_added);
-    used += sprintf(bigbuf + used, "Fast timers started:   %i\n",
-                    fast_timers_started);
-    used += sprintf(bigbuf + used, "Fast timer interrupts: %i\n",
-                    fast_timer_ints);
-    used += sprintf(bigbuf + used, "Fast timers expired:   %i\n",
-                    fast_timers_expired);
-    used += sprintf(bigbuf + used, "Fast timers deleted:   %i\n",
-                    fast_timers_deleted);
-    used += sprintf(bigbuf + used, "Fast timer running:    %s\n",
-                    fast_timer_running ? "yes" : "no");
-    used += sprintf(bigbuf + used, "Current time:          %lu.%06lu\n",
-                        (unsigned long)tv.tv_jiff,
-                    (unsigned long)tv.tv_usec);
+        struct fast_timer *t, *nextt;
+
+        do_gettimeofday_fast(&tv);
+
+        seq_printf(m, "Fast timers added:     %i\n", fast_timers_added);
+        seq_printf(m, "Fast timers started:   %i\n", fast_timers_started);
+        seq_printf(m, "Fast timer interrupts: %i\n", fast_timer_ints);
+        seq_printf(m, "Fast timers expired:   %i\n", fast_timers_expired);
+        seq_printf(m, "Fast timers deleted:   %i\n", fast_timers_deleted);
+        seq_printf(m, "Fast timer running:    %s\n",
+                   fast_timer_running ? "yes" : "no");
+        seq_printf(m, "Current time:          %lu.%06lu\n",
+                   (unsigned long)tv.tv_jiff,
+                   (unsigned long)tv.tv_usec);
 #ifdef FAST_TIMER_SANITY_CHECKS
-    used += sprintf(bigbuf + used, "Sanity failed:         %i\n",
-                    sanity_failed);
+        seq_printf(m, "Sanity failed:         %i\n", sanity_failed);
 #endif
-    used += sprintf(bigbuf + used, "\n");
+        seq_putc(m, '\n');
 
 #ifdef DEBUG_LOG_INCLUDED
-    {
-      int end_i = debug_log_cnt;
-      i = 0;
-
-      if (debug_log_cnt_wrapped)
-      {
-        i = debug_log_cnt;
-      }
-
-      while ((i != end_i || (debug_log_cnt_wrapped && !used)) &&
-             used+100 < BIG_BUF_SIZE)
-      {
-        used += sprintf(bigbuf + used, debug_log_string[i],
-                        debug_log_value[i]);
-        i = (i+1) % DEBUG_LOG_MAX;
-      }
-    }
-    used += sprintf(bigbuf + used, "\n");
+        {
+                int end_i = debug_log_cnt;
+                i = 0;
+
+                if (debug_log_cnt_wrapped)
+                        i = debug_log_cnt;
+
+                while (i != end_i || debug_log_cnt_wrapped) {
+                        if (seq_printf(m, debug_log_string[i], debug_log_value[i]) < 0)
+                                return 0;
+                        i = (i+1) % DEBUG_LOG_MAX;
+                }
+        }
+        seq_putc(m, '\n');
 #endif
 
-    num_to_show = (fast_timers_started < NUM_TIMER_STATS ? fast_timers_started:
-                   NUM_TIMER_STATS);
-    used += sprintf(bigbuf + used, "Timers started: %i\n", fast_timers_started);
-    for (i = 0; i < num_to_show && (used+100 < BIG_BUF_SIZE) ; i++)
-    {
-      int cur = (fast_timers_started - i - 1) % NUM_TIMER_STATS;
+        num_to_show = (fast_timers_started < NUM_TIMER_STATS ? fast_timers_started:
+                       NUM_TIMER_STATS);
+        seq_printf(m, "Timers started: %i\n", fast_timers_started);
+        for (i = 0; i < num_to_show; i++) {
+                int cur = (fast_timers_started - i - 1) % NUM_TIMER_STATS;
 
 #if 1 //ndef FAST_TIMER_LOG
-      used += sprintf(bigbuf + used, "div: %i freq: %i delay: %i"
-                      "\n",
-                      timer_div_settings[cur],
-                      timer_freq_settings[cur],
-                      timer_delay_settings[cur]
-                      );
+                seq_printf(m, "div: %i freq: %i delay: %i"
+                           "\n",
+                           timer_div_settings[cur],
+                           timer_freq_settings[cur],
+                           timer_delay_settings[cur]);
 #endif
 #ifdef FAST_TIMER_LOG
-      t = &timer_started_log[cur];
-      used += sprintf(bigbuf + used, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
-                      "d: %6li us data: 0x%08lX"
-                      "\n",
-                      t->name,
-                        (unsigned long)t->tv_set.tv_jiff,
-                      (unsigned long)t->tv_set.tv_usec,
-                        (unsigned long)t->tv_expires.tv_jiff,
-                      (unsigned long)t->tv_expires.tv_usec,
-                      t->delay_us,
-                      t->data
-                      );
+                t = &timer_started_log[cur];
+                if (seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
+                               "d: %6li us data: 0x%08lX"
+                               "\n",
+                               t->name,
+                               (unsigned long)t->tv_set.tv_jiff,
+                               (unsigned long)t->tv_set.tv_usec,
+                               (unsigned long)t->tv_expires.tv_jiff,
+                               (unsigned long)t->tv_expires.tv_usec,
+                               t->delay_us,
+                               t->data) < 0)
+                        return 0;
 #endif
-    }
-    used += sprintf(bigbuf + used, "\n");
+        }
+        seq_putc(m, '\n');
 
 #ifdef FAST_TIMER_LOG
-    num_to_show = (fast_timers_added < NUM_TIMER_STATS ? fast_timers_added:
-                   NUM_TIMER_STATS);
-    used += sprintf(bigbuf + used, "Timers added: %i\n", fast_timers_added);
-    for (i = 0; i < num_to_show && (used+100 < BIG_BUF_SIZE); i++)
-    {
-      t = &timer_added_log[(fast_timers_added - i - 1) % NUM_TIMER_STATS];
-      used += sprintf(bigbuf + used, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
-                      "d: %6li us data: 0x%08lX"
-                      "\n",
-                      t->name,
-                        (unsigned long)t->tv_set.tv_jiff,
-                      (unsigned long)t->tv_set.tv_usec,
-                        (unsigned long)t->tv_expires.tv_jiff,
-                      (unsigned long)t->tv_expires.tv_usec,
-                      t->delay_us,
-                      t->data
-                      );
-    }
-    used += sprintf(bigbuf + used, "\n");
-
-    num_to_show = (fast_timers_expired < NUM_TIMER_STATS ? fast_timers_expired:
-                   NUM_TIMER_STATS);
-    used += sprintf(bigbuf + used, "Timers expired: %i\n", fast_timers_expired);
-    for (i = 0; i < num_to_show && (used+100 < BIG_BUF_SIZE); i++)
-    {
-      t = &timer_expired_log[(fast_timers_expired - i - 1) % NUM_TIMER_STATS];
-      used += sprintf(bigbuf + used, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
-                      "d: %6li us data: 0x%08lX"
-                      "\n",
-                      t->name,
-                        (unsigned long)t->tv_set.tv_jiff,
-                      (unsigned long)t->tv_set.tv_usec,
-                        (unsigned long)t->tv_expires.tv_jiff,
-                      (unsigned long)t->tv_expires.tv_usec,
-                      t->delay_us,
-                      t->data
-                      );
-    }
-    used += sprintf(bigbuf + used, "\n");
+        num_to_show = (fast_timers_added < NUM_TIMER_STATS ? fast_timers_added:
+                       NUM_TIMER_STATS);
+        seq_printf(m, "Timers added: %i\n", fast_timers_added);
+        for (i = 0; i < num_to_show; i++) {
+                t = &timer_added_log[(fast_timers_added - i - 1) % NUM_TIMER_STATS];
+                if (seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
+                               "d: %6li us data: 0x%08lX"
+                               "\n",
+                               t->name,
+                               (unsigned long)t->tv_set.tv_jiff,
+                               (unsigned long)t->tv_set.tv_usec,
+                               (unsigned long)t->tv_expires.tv_jiff,
+                               (unsigned long)t->tv_expires.tv_usec,
+                               t->delay_us,
+                               t->data) < 0)
+                        return 0;
+        }
+        seq_putc(m, '\n');
+
+        num_to_show = (fast_timers_expired < NUM_TIMER_STATS ? fast_timers_expired:
+                       NUM_TIMER_STATS);
+        seq_printf(m, "Timers expired: %i\n", fast_timers_expired);
+        for (i = 0; i < num_to_show; i++) {
+                t = &timer_expired_log[(fast_timers_expired - i - 1) % NUM_TIMER_STATS];
+                if (seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
+                               "d: %6li us data: 0x%08lX"
+                               "\n",
+                               t->name,
+                               (unsigned long)t->tv_set.tv_jiff,
+                               (unsigned long)t->tv_set.tv_usec,
+                               (unsigned long)t->tv_expires.tv_jiff,
+                               (unsigned long)t->tv_expires.tv_usec,
+                               t->delay_us,
+                               t->data) < 0)
+                        return 0;
+        }
+        seq_putc(m, '\n');
 #endif
 
-    used += sprintf(bigbuf + used, "Active timers:\n");
-    local_irq_save(flags);
-    t = fast_timer_list;
-    while (t != NULL && (used+100 < BIG_BUF_SIZE))
-    {
-      nextt = t->next;
-      local_irq_restore(flags);
-      used += sprintf(bigbuf + used, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
-                      "d: %6li us data: 0x%08lX"
+        seq_puts(m, "Active timers:\n");
+        local_irq_save(flags);
+        t = fast_timer_list;
+        while (t) {
+                nextt = t->next;
+                local_irq_restore(flags);
+                if (seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
+                               "d: %6li us data: 0x%08lX"
 /*                      " func: 0x%08lX" */
-                      "\n",
-                      t->name,
-                        (unsigned long)t->tv_set.tv_jiff,
-                      (unsigned long)t->tv_set.tv_usec,
-                        (unsigned long)t->tv_expires.tv_jiff,
-                      (unsigned long)t->tv_expires.tv_usec,
-                      t->delay_us,
-                      t->data
+                               "\n",
+                               t->name,
+                               (unsigned long)t->tv_set.tv_jiff,
+                               (unsigned long)t->tv_set.tv_usec,
+                               (unsigned long)t->tv_expires.tv_jiff,
+                               (unsigned long)t->tv_expires.tv_usec,
+                               t->delay_us,
+                               t->data
 /*                      , t->function */
-                      );
-        local_irq_save(flags);
-      if (t->next != nextt)
-      {
-        printk(KERN_WARNING "timer removed!\n");
-      }
-      t = nextt;
-    }
-    local_irq_restore(flags);
-  }
-
-  if (used - offset < len)
-  {
-    len = used - offset;
-  }
+                               ) < 0)
+                        return 0;
+                local_irq_save(flags);
+                if (t->next != nextt)
+                        printk(KERN_WARNING "timer removed!\n");
+                t = nextt;
+        }
+        local_irq_restore(flags);
 
-  memcpy(buf, bigbuf + offset, len);
-  *start = buf;
-  *eof = 1;
+        return 0;
+}
 
-  return len;
+static int proc_fasttimer_open(struct inode *inode, struct file *file)
+{
+        return single_open_size(file, proc_fasttimer_show, PDE_DATA(inode), BIG_BUF_SIZE);
 }
+
+static const struct file_operations proc_fasttimer_fops = {
+        .open           = proc_fasttimer_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
 #endif /* PROC_FS */
 
 #ifdef FAST_TIMER_TEST
@@ -857,8 +823,7 @@ int fast_timer_init(void)
     }
 #endif
 #ifdef CONFIG_PROC_FS
-   if ((fasttimer_proc_entry = create_proc_entry( "fasttimer", 0, 0 )))
-     fasttimer_proc_entry->read_proc = proc_fasttimer_read;
+   proc_create("fasttimer", 0, NULL, &proc_fasttimer_fops);
 #endif /* PROC_FS */
     if(request_irq(TIMER1_IRQ_NBR, timer1_handler, 0,
                    "fast timer int", NULL))
diff --git a/arch/cris/arch-v10/kernel/process.c b/arch/cris/arch-v10/kernel/process.c
index b1018750cffb..753e9a03cf87 100644
--- a/arch/cris/arch-v10/kernel/process.c
+++ b/arch/cris/arch-v10/kernel/process.c
@@ -30,8 +30,9 @@ void etrax_gpio_wake_up_check(void); /* drivers/gpio.c */
 void default_idle(void)
 {
 #ifdef CONFIG_ETRAX_GPIO
-  etrax_gpio_wake_up_check();
+        etrax_gpio_wake_up_check();
 #endif
+        local_irq_enable();
 }
 
 /*
@@ -175,6 +176,9 @@ unsigned long get_wchan(struct task_struct *p)
 void show_regs(struct pt_regs * regs)
 {
         unsigned long usp = rdusp();
+
+        show_regs_print_info(KERN_DEFAULT);
+
         printk("IRP: %08lx SRP: %08lx DCCR: %08lx USP: %08lx MOF: %08lx\n",
                regs->irp, regs->srp, regs->dccr, usp, regs->mof );
         printk(" r0: %08lx  r1: %08lx   r2: %08lx  r3: %08lx\n",
diff --git a/arch/cris/arch-v32/kernel/fasttimer.c b/arch/cris/arch-v32/kernel/fasttimer.c
index ab1551ee43c5..f6644535b17e 100644
--- a/arch/cris/arch-v32/kernel/fasttimer.c
+++ b/arch/cris/arch-v32/kernel/fasttimer.c
@@ -23,6 +23,7 @@
 #include <hwregs/timer_defs.h>
 #include <asm/fasttimer.h>
 #include <linux/proc_fs.h>
+#include <linux/seq_file.h>
 
 /*
  * timer0 is running at 100MHz and generating jiffies timer ticks
@@ -463,195 +464,161 @@ void schedule_usleep(unsigned long us)
 }
 
 #ifdef CONFIG_PROC_FS
-static int proc_fasttimer_read(char *buf, char **start, off_t offset, int len
-                       ,int *eof, void *data_unused);
-static struct proc_dir_entry *fasttimer_proc_entry;
-#endif /* CONFIG_PROC_FS */
-
-#ifdef CONFIG_PROC_FS
-
 /* This value is very much based on testing */
 #define BIG_BUF_SIZE (500 + NUM_TIMER_STATS * 300)
 
-static int proc_fasttimer_read(char *buf, char **start, off_t offset, int len
-                       ,int *eof, void *data_unused)
+static int proc_fasttimer_show(struct seq_file *m, void *v)
 {
-  unsigned long flags;
-  int i = 0;
-  int num_to_show;
+        unsigned long flags;
+        int i = 0;
+        int num_to_show;
         struct fasttime_t tv;
-  struct fast_timer *t, *nextt;
-  static char *bigbuf = NULL;
-  static unsigned long used;
-
-        if (!bigbuf) {
-                bigbuf = vmalloc(BIG_BUF_SIZE);
-                if (!bigbuf) {
-                        used = 0;
-                        if (buf)
-                                buf[0] = '\0';
-                        return 0;
-                }
-        }
-
-        if (!offset || !used) {
-    do_gettimeofday_fast(&tv);
-
-    used = 0;
-    used += sprintf(bigbuf + used, "Fast timers added:     %i\n",
-                    fast_timers_added);
-    used += sprintf(bigbuf + used, "Fast timers started:   %i\n",
-                    fast_timers_started);
-    used += sprintf(bigbuf + used, "Fast timer interrupts: %i\n",
-                    fast_timer_ints);
-    used += sprintf(bigbuf + used, "Fast timers expired:   %i\n",
-                    fast_timers_expired);
-    used += sprintf(bigbuf + used, "Fast timers deleted:   %i\n",
-                    fast_timers_deleted);
-    used += sprintf(bigbuf + used, "Fast timer running:    %s\n",
-                    fast_timer_running ? "yes" : "no");
-    used += sprintf(bigbuf + used, "Current time:          %lu.%06lu\n",
-                        (unsigned long)tv.tv_jiff,
-                    (unsigned long)tv.tv_usec);
+        struct fast_timer *t, *nextt;
+
+        do_gettimeofday_fast(&tv);
+
+        seq_printf(m, "Fast timers added:     %i\n", fast_timers_added);
+        seq_printf(m, "Fast timers started:   %i\n", fast_timers_started);
+        seq_printf(m, "Fast timer interrupts: %i\n", fast_timer_ints);
+        seq_printf(m, "Fast timers expired:   %i\n", fast_timers_expired);
+        seq_printf(m, "Fast timers deleted:   %i\n", fast_timers_deleted);
+        seq_printf(m, "Fast timer running:    %s\n",
+                   fast_timer_running ? "yes" : "no");
+        seq_printf(m, "Current time:          %lu.%06lu\n",
+                   (unsigned long)tv.tv_jiff,
+                   (unsigned long)tv.tv_usec);
 #ifdef FAST_TIMER_SANITY_CHECKS
-    used += sprintf(bigbuf + used, "Sanity failed:         %i\n",
-                    sanity_failed);
+        seq_printf(m, "Sanity failed:         %i\n", sanity_failed);
 #endif
-    used += sprintf(bigbuf + used, "\n");
+        seq_putc(m, '\n');
 
 #ifdef DEBUG_LOG_INCLUDED
-    {
-      int end_i = debug_log_cnt;
-      i = 0;
-
-                        if (debug_log_cnt_wrapped)
-        i = debug_log_cnt;
-
-      while ((i != end_i || (debug_log_cnt_wrapped && !used)) &&
-             used+100 < BIG_BUF_SIZE)
-      {
-        used += sprintf(bigbuf + used, debug_log_string[i],
-                        debug_log_value[i]);
-        i = (i+1) % DEBUG_LOG_MAX;
-      }
-    }
-    used += sprintf(bigbuf + used, "\n");
+        {
+                int end_i = debug_log_cnt;
+                i = 0;
+
+                if (debug_log_cnt_wrapped)
+                        i = debug_log_cnt;
+
+                while ((i != end_i || debug_log_cnt_wrapped)) {
+                        if (seq_printf(m, debug_log_string[i], debug_log_value[i]) < 0)
+                                return 0;
+                        i = (i+1) % DEBUG_LOG_MAX;
+                }
+        }
+        seq_putc(m, '\n');
 #endif
 
-    num_to_show = (fast_timers_started < NUM_TIMER_STATS ? fast_timers_started:
-                   NUM_TIMER_STATS);
-    used += sprintf(bigbuf + used, "Timers started: %i\n", fast_timers_started);
-    for (i = 0; i < num_to_show && (used+100 < BIG_BUF_SIZE) ; i++)
-    {
-      int cur = (fast_timers_started - i - 1) % NUM_TIMER_STATS;
+        num_to_show = (fast_timers_started < NUM_TIMER_STATS ? fast_timers_started:
+                       NUM_TIMER_STATS);
+        seq_printf(m, "Timers started: %i\n", fast_timers_started);
+        for (i = 0; i < num_to_show; i++) {
+                int cur = (fast_timers_started - i - 1) % NUM_TIMER_STATS;
 
 #if 1 //ndef FAST_TIMER_LOG
-      used += sprintf(bigbuf + used, "div: %i delay: %i"
-                      "\n",
-                      timer_div_settings[cur],
-                      timer_delay_settings[cur]
-                      );
+                seq_printf(m, "div: %i delay: %i"
+                           "\n",
+                           timer_div_settings[cur],
+                           timer_delay_settings[cur]);
 #endif
 #ifdef FAST_TIMER_LOG
-      t = &timer_started_log[cur];
-      used += sprintf(bigbuf + used, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
-                      "d: %6li us data: 0x%08lX"
-                      "\n",
-                      t->name,
-                                (unsigned long)t->tv_set.tv_jiff,
-                      (unsigned long)t->tv_set.tv_usec,
-                                (unsigned long)t->tv_expires.tv_jiff,
-                      (unsigned long)t->tv_expires.tv_usec,
-                      t->delay_us,
-                      t->data
-                      );
+                t = &timer_started_log[cur];
+                if (seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
+                               "d: %6li us data: 0x%08lX"
+                               "\n",
+                               t->name,
+                               (unsigned long)t->tv_set.tv_jiff,
+                               (unsigned long)t->tv_set.tv_usec,
+                               (unsigned long)t->tv_expires.tv_jiff,
+                               (unsigned long)t->tv_expires.tv_usec,
+                               t->delay_us,
+                               t->data) < 0)
+                        return 0;
 #endif
-    }
-    used += sprintf(bigbuf + used, "\n");
+        }
+        seq_putc(m, '\n');
 
 #ifdef FAST_TIMER_LOG
-    num_to_show = (fast_timers_added < NUM_TIMER_STATS ? fast_timers_added:
-                   NUM_TIMER_STATS);
-    used += sprintf(bigbuf + used, "Timers added: %i\n", fast_timers_added);
-    for (i = 0; i < num_to_show && (used+100 < BIG_BUF_SIZE); i++)
-    {
-      t = &timer_added_log[(fast_timers_added - i - 1) % NUM_TIMER_STATS];
-      used += sprintf(bigbuf + used, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
-                      "d: %6li us data: 0x%08lX"
-                      "\n",
-                      t->name,
-                                (unsigned long)t->tv_set.tv_jiff,
-                      (unsigned long)t->tv_set.tv_usec,
-                                (unsigned long)t->tv_expires.tv_jiff,
-                      (unsigned long)t->tv_expires.tv_usec,
-                      t->delay_us,
-                      t->data
-                      );
-    }
-    used += sprintf(bigbuf + used, "\n");
-
-    num_to_show = (fast_timers_expired < NUM_TIMER_STATS ? fast_timers_expired:
-                   NUM_TIMER_STATS);
-    used += sprintf(bigbuf + used, "Timers expired: %i\n", fast_timers_expired);
-    for (i = 0; i < num_to_show && (used+100 < BIG_BUF_SIZE); i++)
-    {
-      t = &timer_expired_log[(fast_timers_expired - i - 1) % NUM_TIMER_STATS];
-      used += sprintf(bigbuf + used, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
-                      "d: %6li us data: 0x%08lX"
-                      "\n",
-                      t->name,
-                                (unsigned long)t->tv_set.tv_jiff,
-                      (unsigned long)t->tv_set.tv_usec,
-                                (unsigned long)t->tv_expires.tv_jiff,
-                      (unsigned long)t->tv_expires.tv_usec,
-                      t->delay_us,
-                      t->data
-                      );
-    }
-    used += sprintf(bigbuf + used, "\n");
+        num_to_show = (fast_timers_added < NUM_TIMER_STATS ? fast_timers_added:
+                       NUM_TIMER_STATS);
+        seq_printf(m, "Timers added: %i\n", fast_timers_added);
+        for (i = 0; i < num_to_show; i++) {
+                t = &timer_added_log[(fast_timers_added - i - 1) % NUM_TIMER_STATS];
+                if (seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
+                               "d: %6li us data: 0x%08lX"
+                               "\n",
+                               t->name,
+                               (unsigned long)t->tv_set.tv_jiff,
+                               (unsigned long)t->tv_set.tv_usec,
+                               (unsigned long)t->tv_expires.tv_jiff,
+                               (unsigned long)t->tv_expires.tv_usec,
+                               t->delay_us,
+                               t->data) < 0)
+                        return 0;
+        }
+        seq_putc(m, '\n');
+
+        num_to_show = (fast_timers_expired < NUM_TIMER_STATS ? fast_timers_expired:
+                       NUM_TIMER_STATS);
+        seq_printf(m, "Timers expired: %i\n", fast_timers_expired);
+        for (i = 0; i < num_to_show; i++){
+                t = &timer_expired_log[(fast_timers_expired - i - 1) % NUM_TIMER_STATS];
+                if (seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
+                               "d: %6li us data: 0x%08lX"
+                               "\n",
+                               t->name,
+                               (unsigned long)t->tv_set.tv_jiff,
+                               (unsigned long)t->tv_set.tv_usec,
+                               (unsigned long)t->tv_expires.tv_jiff,
+                               (unsigned long)t->tv_expires.tv_usec,
+                               t->delay_us,
+                               t->data) < 0)
+                        return 0;
+        }
+        seq_putc(m, '\n');
 #endif
 
-    used += sprintf(bigbuf + used, "Active timers:\n");
-    local_irq_save(flags);
-    t = fast_timer_list;
-    while (t != NULL && (used+100 < BIG_BUF_SIZE))
-    {
-      nextt = t->next;
-      local_irq_restore(flags);
-      used += sprintf(bigbuf + used, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
-                        "d: %6li us data: 0x%08lX"
+        seq_puts(m, "Active timers:\n");
+        local_irq_save(flags);
+        t = fast_timer_list;
+        while (t != NULL){
+                nextt = t->next;
+                local_irq_restore(flags);
+                if (seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
+                               "d: %6li us data: 0x%08lX"
 /*                      " func: 0x%08lX" */
-                        "\n",
-                        t->name,
-                        (unsigned long)t->tv_set.tv_jiff,
-                        (unsigned long)t->tv_set.tv_usec,
-                        (unsigned long)t->tv_expires.tv_jiff,
-                        (unsigned long)t->tv_expires.tv_usec,
-                      t->delay_us,
-                      t->data
+                               "\n",
+                               t->name,
+                               (unsigned long)t->tv_set.tv_jiff,
+                               (unsigned long)t->tv_set.tv_usec,
+                               (unsigned long)t->tv_expires.tv_jiff,
+                               (unsigned long)t->tv_expires.tv_usec,
+                               t->delay_us,
+                               t->data
 /*                      , t->function */
-                      );
-                        local_irq_save(flags);
-      if (t->next != nextt)
-      {
-        printk("timer removed!\n");
-      }
-      t = nextt;
-    }
-    local_irq_restore(flags);
-  }
+                               ) < 0)
+                        return 0;
+                local_irq_save(flags);
+                if (t->next != nextt)
+                        printk("timer removed!\n");
+                t = nextt;
+        }
+        local_irq_restore(flags);
+        return 0;
+}
 
-  if (used - offset < len)
-  {
-    len = used - offset;
-  }
+static int proc_fasttimer_open(struct inode *inode, struct file *file)
+{
+        return single_open_size(file, proc_fasttimer_show, PDE_DATA(inode), BIG_BUF_SIZE);
+}
 
-  memcpy(buf, bigbuf + offset, len);
-  *start = buf;
-  *eof = 1;
+static const struct file_operations proc_fasttimer_fops = {
+        .open           = proc_fasttimer_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
 
-  return len;
-}
 #endif /* PROC_FS */
 
 #ifdef FAST_TIMER_TEST
@@ -816,9 +783,7 @@ int fast_timer_init(void)
     printk("fast_timer_init()\n");
 
 #ifdef CONFIG_PROC_FS
-    fasttimer_proc_entry = create_proc_entry("fasttimer", 0, 0);
-    if (fasttimer_proc_entry)
-      fasttimer_proc_entry->read_proc = proc_fasttimer_read;
+    proc_create("fasttimer", 0, NULL, &proc_fasttimer_fops);
 #endif /* PROC_FS */
                 if (request_irq(TIMER0_INTR_VECT, timer_trig_interrupt,
                                 IRQF_SHARED | IRQF_DISABLED,
diff --git a/arch/cris/arch-v32/kernel/process.c b/arch/cris/arch-v32/kernel/process.c
index 2b23ef0e4452..cebd32e2a8fb 100644
--- a/arch/cris/arch-v32/kernel/process.c
+++ b/arch/cris/arch-v32/kernel/process.c
@@ -20,18 +20,12 @@
 
 extern void stop_watchdog(void);
 
-extern int cris_hlt_counter;
-
 /* We use this if we don't have any better idle routine. */
 void default_idle(void)
 {
-        local_irq_disable();
-        if (!need_resched() && !cris_hlt_counter) {
-                /* Halt until exception. */
-                __asm__ volatile("ei    \n\t"
-                                 "halt      ");
-        }
-        local_irq_enable();
+        /* Halt until exception. */
+        __asm__ volatile("ei    \n\t"
+                         "halt      ");
 }
 
 /*
@@ -170,6 +164,9 @@ get_wchan(struct task_struct *p)
 void show_regs(struct pt_regs * regs)
 {
         unsigned long usp = rdusp();
+
+        show_regs_print_info(KERN_DEFAULT);
+
         printk("ERP: %08lx SRP: %08lx  CCS: %08lx USP: %08lx MOF: %08lx\n",
                 regs->erp, regs->srp, regs->ccs, usp, regs->mof);
 
diff --git a/arch/cris/arch-v32/kernel/smp.c b/arch/cris/arch-v32/kernel/smp.c
index 04a16edd5401..cdd12028de0c 100644
--- a/arch/cris/arch-v32/kernel/smp.c
+++ b/arch/cris/arch-v32/kernel/smp.c
@@ -145,8 +145,6 @@ smp_boot_one_cpu(int cpuid, struct task_struct idle)
  * specific stuff such as the local timer and the MMU. */
 void __init smp_callin(void)
 {
-        extern void cpu_idle(void);
-
         int cpu = cpu_now_booting;
         reg_intr_vect_rw_mask vect_mask = {0};
 
@@ -170,7 +168,7 @@ void __init smp_callin(void)
         local_irq_enable();
 
         set_cpu_online(cpu, true);
-        cpu_idle();
+        cpu_startup_entry(CPUHP_ONLINE);
 }
 
 /* Stop execution on this CPU.*/
diff --git a/arch/cris/arch-v32/mach-a3/Makefile b/arch/cris/arch-v32/mach-a3/Makefile
index d366e0891988..18a227196a41 100644
--- a/arch/cris/arch-v32/mach-a3/Makefile
+++ b/arch/cris/arch-v32/mach-a3/Makefile
@@ -3,7 +3,6 @@
 #
 
 obj-y   := dma.o pinmux.o io.o arbiter.o
-obj-$(CONFIG_CPU_FREQ)   += cpufreq.o
 
 clean:
 
diff --git a/arch/cris/arch-v32/mach-a3/cpufreq.c b/arch/cris/arch-v32/mach-a3/cpufreq.c
deleted file mode 100644
index ee391ecb5bc9..000000000000
--- a/arch/cris/arch-v32/mach-a3/cpufreq.c
+++ /dev/null
@@ -1,152 +0,0 @@
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/cpufreq.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/clkgen_defs.h>
-#include <hwregs/ddr2_defs.h>
-
-static int
-cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
-        void *data);
-
-static struct notifier_block cris_sdram_freq_notifier_block = {
-        .notifier_call = cris_sdram_freq_notifier
-};
-
-static struct cpufreq_frequency_table cris_freq_table[] = {
-        {0x01,  6000},
-        {0x02,  200000},
-        {0,     CPUFREQ_TABLE_END},
-};
-
-static unsigned int cris_freq_get_cpu_frequency(unsigned int cpu)
-{
-        reg_clkgen_rw_clk_ctrl clk_ctrl;
-        clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
-        return clk_ctrl.pll ? 200000 : 6000;
-}
-
-static void cris_freq_set_cpu_state(unsigned int state)
-{
-        int i = 0;
-        struct cpufreq_freqs freqs;
-        reg_clkgen_rw_clk_ctrl clk_ctrl;
-        clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
-
-#ifdef CONFIG_SMP
-        for_each_present_cpu(i)
-#endif
-        {
-                freqs.old = cris_freq_get_cpu_frequency(i);
-                freqs.new = cris_freq_table[state].frequency;
-                freqs.cpu = i;
-        }
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
-        local_irq_disable();
-
-        /* Even though we may be SMP they will share the same clock
-         * so all settings are made on CPU0. */
-        if (cris_freq_table[state].frequency == 200000)
-                clk_ctrl.pll = 1;
-        else
-                clk_ctrl.pll = 0;
-        REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
-
-        local_irq_enable();
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-};
-
-static int cris_freq_verify(struct cpufreq_policy *policy)
-{
-        return cpufreq_frequency_table_verify(policy, &cris_freq_table[0]);
-}
-
-static int cris_freq_target(struct cpufreq_policy *policy,
-                            unsigned int target_freq,
-                            unsigned int relation)
-{
-        unsigned int newstate = 0;
-
-        if (cpufreq_frequency_table_target(policy, cris_freq_table,
-                        target_freq, relation, &newstate))
-                return -EINVAL;
-
-        cris_freq_set_cpu_state(newstate);
-
-        return 0;
-}
-
-static int cris_freq_cpu_init(struct cpufreq_policy *policy)
-{
-        int result;
-
-        /* cpuinfo and default policy values */
-        policy->cpuinfo.transition_latency = 1000000; /* 1ms */
-        policy->cur = cris_freq_get_cpu_frequency(0);
-
-        result = cpufreq_frequency_table_cpuinfo(policy, cris_freq_table);
-        if (result)
-                return (result);
-
-        cpufreq_frequency_table_get_attr(cris_freq_table, policy->cpu);
-
-        return 0;
-}
-
-
-static int cris_freq_cpu_exit(struct cpufreq_policy *policy)
-{
-        cpufreq_frequency_table_put_attr(policy->cpu);
-        return 0;
-}
-
-
-static struct freq_attr *cris_freq_attr[] = {
-        &cpufreq_freq_attr_scaling_available_freqs,
-        NULL,
-};
-
-static struct cpufreq_driver cris_freq_driver = {
-        .get    = cris_freq_get_cpu_frequency,
-        .verify = cris_freq_verify,
-        .target = cris_freq_target,
-        .init   = cris_freq_cpu_init,
-        .exit   = cris_freq_cpu_exit,
-        .name   = "cris_freq",
-        .owner  = THIS_MODULE,
-        .attr   = cris_freq_attr,
-};
-
-static int __init cris_freq_init(void)
-{
-        int ret;
-        ret = cpufreq_register_driver(&cris_freq_driver);
-        cpufreq_register_notifier(&cris_sdram_freq_notifier_block,
-                CPUFREQ_TRANSITION_NOTIFIER);
-        return ret;
-}
-
-static int
-cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
-        void *data)
-{
-        int i;
-        struct cpufreq_freqs *freqs = data;
-        if (val == CPUFREQ_PRECHANGE) {
-                reg_ddr2_rw_cfg cfg =
-                  REG_RD(ddr2, regi_ddr2_ctrl, rw_cfg);
-                cfg.ref_interval = (freqs->new == 200000 ? 1560 : 46);
-
-                if (freqs->new == 200000)
-                        for (i = 0; i < 50000; i++);
-                REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing);
-        }
-        return 0;
-}
-
-
-module_init(cris_freq_init);
diff --git a/arch/cris/arch-v32/mach-fs/Makefile b/arch/cris/arch-v32/mach-fs/Makefile
index d366e0891988..18a227196a41 100644
--- a/arch/cris/arch-v32/mach-fs/Makefile
+++ b/arch/cris/arch-v32/mach-fs/Makefile
@@ -3,7 +3,6 @@
 #
 
 obj-y   := dma.o pinmux.o io.o arbiter.o
-obj-$(CONFIG_CPU_FREQ)   += cpufreq.o
 
 clean:
 
diff --git a/arch/cris/arch-v32/mach-fs/cpufreq.c b/arch/cris/arch-v32/mach-fs/cpufreq.c
deleted file mode 100644
index d92cf70d1cbe..000000000000
--- a/arch/cris/arch-v32/mach-fs/cpufreq.c
+++ /dev/null
@@ -1,145 +0,0 @@
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/cpufreq.h>
-#include <hwregs/reg_map.h>
-#include <arch/hwregs/reg_rdwr.h>
-#include <arch/hwregs/config_defs.h>
-#include <arch/hwregs/bif_core_defs.h>
-
-static int
-cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
-                         void *data);
-
-static struct notifier_block cris_sdram_freq_notifier_block = {
-        .notifier_call = cris_sdram_freq_notifier
-};
-
-static struct cpufreq_frequency_table cris_freq_table[] = {
-        {0x01, 6000},
-        {0x02, 200000},
-        {0, CPUFREQ_TABLE_END},
-};
-
-static unsigned int cris_freq_get_cpu_frequency(unsigned int cpu)
-{
-        reg_config_rw_clk_ctrl clk_ctrl;
-        clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
-        return clk_ctrl.pll ? 200000 : 6000;
-}
-
-static void cris_freq_set_cpu_state(unsigned int state)
-{
-        int i;
-        struct cpufreq_freqs freqs;
-        reg_config_rw_clk_ctrl clk_ctrl;
-        clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
-
-        for_each_possible_cpu(i) {
-                freqs.old = cris_freq_get_cpu_frequency(i);
-                freqs.new = cris_freq_table[state].frequency;
-                freqs.cpu = i;
-        }
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
-        local_irq_disable();
-
-        /* Even though we may be SMP they will share the same clock
-         * so all settings are made on CPU0. */
-        if (cris_freq_table[state].frequency == 200000)
-                clk_ctrl.pll = 1;
-        else
-                clk_ctrl.pll = 0;
-        REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl);
-
-        local_irq_enable();
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-};
-
-static int cris_freq_verify(struct cpufreq_policy *policy)
-{
-        return cpufreq_frequency_table_verify(policy, &cris_freq_table[0]);
-}
-
-static int cris_freq_target(struct cpufreq_policy *policy,
-                            unsigned int target_freq, unsigned int relation)
-{
-        unsigned int newstate = 0;
-
-        if (cpufreq_frequency_table_target
-            (policy, cris_freq_table, target_freq, relation, &newstate))
-                return -EINVAL;
-
-        cris_freq_set_cpu_state(newstate);
-
-        return 0;
-}
-
-static int cris_freq_cpu_init(struct cpufreq_policy *policy)
-{
-        int result;
-
-        /* cpuinfo and default policy values */
-        policy->cpuinfo.transition_latency = 1000000;   /* 1ms */
-        policy->cur = cris_freq_get_cpu_frequency(0);
-
-        result = cpufreq_frequency_table_cpuinfo(policy, cris_freq_table);
-        if (result)
-                return (result);
-
-        cpufreq_frequency_table_get_attr(cris_freq_table, policy->cpu);
-
-        return 0;
-}
-
-static int cris_freq_cpu_exit(struct cpufreq_policy *policy)
-{
-        cpufreq_frequency_table_put_attr(policy->cpu);
-        return 0;
-}
-
-static struct freq_attr *cris_freq_attr[] = {
-        &cpufreq_freq_attr_scaling_available_freqs,
-        NULL,
-};
-
-static struct cpufreq_driver cris_freq_driver = {
-        .get = cris_freq_get_cpu_frequency,
-        .verify = cris_freq_verify,
-        .target = cris_freq_target,
-        .init = cris_freq_cpu_init,
-        .exit = cris_freq_cpu_exit,
-        .name = "cris_freq",
-        .owner = THIS_MODULE,
-        .attr = cris_freq_attr,
-};
-
-static int __init cris_freq_init(void)
-{
-        int ret;
-        ret = cpufreq_register_driver(&cris_freq_driver);
-        cpufreq_register_notifier(&cris_sdram_freq_notifier_block,
-                                  CPUFREQ_TRANSITION_NOTIFIER);
-        return ret;
-}
-
-static int
-cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
-                         void *data)
-{
-        int i;
-        struct cpufreq_freqs *freqs = data;
-        if (val == CPUFREQ_PRECHANGE) {
-                reg_bif_core_rw_sdram_timing timing =
-                    REG_RD(bif_core, regi_bif_core, rw_sdram_timing);
-                timing.cpd = (freqs->new == 200000 ? 0 : 1);
-
-                if (freqs->new == 200000)
-                        for (i = 0; i < 50000; i++) ;
-                REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing);
-        }
-        return 0;
-}
-
-module_init(cris_freq_init);
diff --git a/arch/cris/include/asm/processor.h b/arch/cris/include/asm/processor.h
index 675823f70c0f..c0a29b96b92b 100644
--- a/arch/cris/include/asm/processor.h
+++ b/arch/cris/include/asm/processor.h
@@ -65,13 +65,6 @@ static inline void release_thread(struct task_struct *dead_task)
 
 #define cpu_relax()     barrier()
 
-/*
- * disable hlt during certain critical i/o operations
- */
-#define HAVE_DISABLE_HLT
-void disable_hlt(void);
-void enable_hlt(void);
-
 void default_idle(void);
 
 #endif /* __ASM_CRIS_PROCESSOR_H */
diff --git a/arch/cris/include/asm/unistd.h b/arch/cris/include/asm/unistd.h
index be57a988bfb9..0ff3f6889842 100644
--- a/arch/cris/include/asm/unistd.h
+++ b/arch/cris/include/asm/unistd.h
@@ -34,12 +34,4 @@
 #define __ARCH_WANT_SYS_VFORK
 #define __ARCH_WANT_SYS_CLONE
 
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
-
 #endif /* _ASM_CRIS_UNISTD_H_ */
diff --git a/arch/cris/kernel/process.c b/arch/cris/kernel/process.c
index 104ff4dd9b98..b78498eb079b 100644
--- a/arch/cris/kernel/process.c
+++ b/arch/cris/kernel/process.c
@@ -29,59 +29,14 @@
 
 //#define DEBUG
 
-/*
- * The hlt_counter, disable_hlt and enable_hlt is just here as a hook if
- * there would ever be a halt sequence (for power save when idle) with
- * some largish delay when halting or resuming *and* a driver that can't
- * afford that delay.  The hlt_counter would then be checked before
- * executing the halt sequence, and the driver marks the unhaltable
- * region by enable_hlt/disable_hlt.
- */
-
-int cris_hlt_counter=0;
-
-void disable_hlt(void)
-{
-        cris_hlt_counter++;
-}
-
-EXPORT_SYMBOL(disable_hlt);
-
-void enable_hlt(void)
-{
-        cris_hlt_counter--;
-}
-
-EXPORT_SYMBOL(enable_hlt);
- 
 extern void default_idle(void);
 
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
-/*
- * The idle thread. There's no useful work to be
- * done, so just try to conserve power and have a
- * low exit latency (ie sit in a loop waiting for
- * somebody to say that they'd like to reschedule)
- */
-
-void cpu_idle (void)
+void arch_cpu_idle(void)
 {
-        /* endless idle loop with no priority at all */
-        while (1) {
-                rcu_idle_enter();
-                while (!need_resched()) {
-                        /*
-                         * Mark this as an RCU critical section so that
-                         * synchronize_kernel() in the unload path waits
-                         * for our completion.
-                         */
-                        default_idle();
-                }
-                rcu_idle_exit();
-                schedule_preempt_disabled();
-        }
+        default_idle();
 }
 
 void hard_reset_now (void);
diff --git a/arch/cris/kernel/traps.c b/arch/cris/kernel/traps.c
index a11ad3229f8c..0ffda73734f5 100644
--- a/arch/cris/kernel/traps.c
+++ b/arch/cris/kernel/traps.c
@@ -147,13 +147,6 @@ show_stack(void)
 #endif
 
 void
-dump_stack(void)
-{
-        show_stack(NULL, NULL);
-}
-EXPORT_SYMBOL(dump_stack);
-
-void
 set_nmi_handler(void (*handler)(struct pt_regs *))
 {
         nmi_handler = handler;
diff --git a/arch/cris/mm/init.c b/arch/cris/mm/init.c
index d72ab58fd83e..9ac80946dada 100644
--- a/arch/cris/mm/init.c
+++ b/arch/cris/mm/init.c
@@ -12,12 +12,10 @@
 #include <linux/init.h>
 #include <linux/bootmem.h>
 #include <asm/tlb.h>
+#include <asm/sections.h>
 
 unsigned long empty_zero_page;
 
-extern char _stext, _edata, _etext; /* From linkerscript */
-extern char __init_begin, __init_end;
-
 void __init
 mem_init(void)
 {
@@ -67,15 +65,5 @@ mem_init(void)
 void 
 free_initmem(void)
 {
-        unsigned long addr;
-
-        addr = (unsigned long)(&__init_begin);
-        for (; addr < (unsigned long)(&__init_end); addr += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(addr));
-                init_page_count(virt_to_page(addr));
-                free_page(addr);
-                totalram_pages++;
-        }
-        printk (KERN_INFO "Freeing unused kernel memory: %luk freed\n",
-                (unsigned long)((&__init_end - &__init_begin) >> 10));
+        free_initmem_default(0);
 }
diff --git a/arch/frv/include/asm/unistd.h b/arch/frv/include/asm/unistd.h
index 4cfcc7bba25a..70ec7293dce7 100644
--- a/arch/frv/include/asm/unistd.h
+++ b/arch/frv/include/asm/unistd.h
@@ -31,14 +31,4 @@
 #define __ARCH_WANT_SYS_VFORK
 #define __ARCH_WANT_SYS_CLONE
 
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#ifndef cond_syscall
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
-#endif
-
 #endif /* _ASM_UNISTD_H_ */
diff --git a/arch/frv/kernel/process.c b/arch/frv/kernel/process.c
index 23916b2a12a2..5d40aeb7712e 100644
--- a/arch/frv/kernel/process.c
+++ b/arch/frv/kernel/process.c
@@ -59,29 +59,12 @@ static void core_sleep_idle(void)
         mb();
 }
 
-void (*idle)(void) = core_sleep_idle;
-
-/*
- * The idle thread. There's no useful work to be
- * done, so just try to conserve power and have a
- * low exit latency (ie sit in a loop waiting for
- * somebody to say that they'd like to reschedule)
- */
-void cpu_idle(void)
+void arch_cpu_idle(void)
 {
-        /* endless idle loop with no priority at all */
-        while (1) {
-                rcu_idle_enter();
-                while (!need_resched()) {
-                        check_pgt_cache();
-
-                        if (!frv_dma_inprogress && idle)
-                                idle();
-                }
-                rcu_idle_exit();
-
-                schedule_preempt_disabled();
-        }
+        if (!frv_dma_inprogress)
+                core_sleep_idle();
+        else
+                local_irq_enable();
 }
 
 void machine_restart(char * __unused)
diff --git a/arch/frv/kernel/traps.c b/arch/frv/kernel/traps.c
index 5cfd1420b091..4bff48c19d29 100644
--- a/arch/frv/kernel/traps.c
+++ b/arch/frv/kernel/traps.c
@@ -466,17 +466,6 @@ asmlinkage void compound_exception(unsigned long esfr1,
         BUG();
 } /* end compound_exception() */
 
-/*****************************************************************************/
-/*
- * The architecture-independent backtrace generator
- */
-void dump_stack(void)
-{
-        show_stack(NULL, NULL);
-}
-
-EXPORT_SYMBOL(dump_stack);
-
 void show_stack(struct task_struct *task, unsigned long *sp)
 {
 }
@@ -508,6 +497,7 @@ void show_regs(struct pt_regs *regs)
         int loop;
 
         printk("\n");
+        show_regs_print_info(KERN_DEFAULT);
 
         printk("Frame: @%08lx [%s]\n",
                (unsigned long) regs,
@@ -522,8 +512,6 @@ void show_regs(struct pt_regs *regs)
                 else
                         printk(" | ");
         }
-
-        printk("Process %s (pid: %d)\n", current->comm, current->pid);
 }
 
 void die_if_kernel(const char *str, ...)
diff --git a/arch/frv/mm/init.c b/arch/frv/mm/init.c
index 92e97b0894a6..dee354fa6b64 100644
--- a/arch/frv/mm/init.c
+++ b/arch/frv/mm/init.c
@@ -122,7 +122,7 @@ void __init mem_init(void)
 #endif
         int codek = 0, datak = 0;
 
-        /* this will put all memory onto the freelists */
+        /* this will put all low memory onto the freelists */
         totalram_pages = free_all_bootmem();
 
 #ifdef CONFIG_MMU
@@ -131,14 +131,8 @@ void __init mem_init(void)
                         datapages++;
 
 #ifdef CONFIG_HIGHMEM
-        for (pfn = num_physpages - 1; pfn >= num_mappedpages; pfn--) {
-                struct page *page = &mem_map[pfn];
-
-                ClearPageReserved(page);
-                init_page_count(page);
-                __free_page(page);
-                totalram_pages++;
-        }
+        for (pfn = num_physpages - 1; pfn >= num_mappedpages; pfn--)
+                free_highmem_page(&mem_map[pfn]);
 #endif
 
         codek = ((unsigned long) &_etext - (unsigned long) &_stext) >> 10;
@@ -168,21 +162,7 @@ void __init mem_init(void)
 void free_initmem(void)
 {
 #if defined(CONFIG_RAMKERNEL) && !defined(CONFIG_PROTECT_KERNEL)
-        unsigned long start, end, addr;
-
-        start = PAGE_ALIGN((unsigned long) &__init_begin);      /* round up */
-        end   = ((unsigned long) &__init_end) & PAGE_MASK;      /* round down */
-
-        /* next to check that the page we free is not a partial page */
-        for (addr = start; addr < end; addr += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(addr));
-                init_page_count(virt_to_page(addr));
-                free_page(addr);
-                totalram_pages++;
-        }
-
-        printk("Freeing unused kernel memory: %ldKiB freed (0x%lx - 0x%lx)\n",
-               (end - start) >> 10, start, end);
+        free_initmem_default(0);
 #endif
 } /* end free_initmem() */
 
@@ -193,14 +173,6 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-        int pages = 0;
-        for (; start < end; start += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(start));
-                init_page_count(virt_to_page(start));
-                free_page(start);
-                totalram_pages++;
-                pages++;
-        }
-        printk("Freeing initrd memory: %dKiB freed\n", (pages * PAGE_SIZE) >> 10);
+        free_reserved_area(start, end, 0, "initrd");
 } /* end free_initrd_mem() */
 #endif
diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig
index 79250de1b12a..303e4f9a79d1 100644
--- a/arch/h8300/Kconfig
+++ b/arch/h8300/Kconfig
@@ -12,10 +12,7 @@ config H8300
         select MODULES_USE_ELF_RELA
         select OLD_SIGSUSPEND3
         select OLD_SIGACTION
-
-config SYMBOL_PREFIX
-        string
-        default "_"
+        select HAVE_UNDERSCORE_SYMBOL_PREFIX
 
 config MMU
         bool
diff --git a/arch/h8300/include/asm/linkage.h b/arch/h8300/include/asm/linkage.h
index 6f4df7d46180..1d81604fb0ad 100644
--- a/arch/h8300/include/asm/linkage.h
+++ b/arch/h8300/include/asm/linkage.h
@@ -2,7 +2,5 @@
 #define _H8300_LINKAGE_H
 
 #undef SYMBOL_NAME_LABEL
-#undef SYMBOL_NAME
 #define SYMBOL_NAME_LABEL(_name_) _##_name_##:
-#define SYMBOL_NAME(_name_) _##_name_
 #endif
diff --git a/arch/h8300/include/asm/unistd.h b/arch/h8300/include/asm/unistd.h
index 6721856d841b..ab671ecf5196 100644
--- a/arch/h8300/include/asm/unistd.h
+++ b/arch/h8300/include/asm/unistd.h
@@ -33,11 +33,4 @@
 #define __ARCH_WANT_SYS_VFORK
 #define __ARCH_WANT_SYS_CLONE
 
-/*
- * "Conditional" syscalls
- */
-#define cond_syscall(name)                                              \
-  asm (".weak\t_" #name "\n"                            \
-       ".set\t_" #name ",_sys_ni_syscall");
-
 #endif /* _ASM_H8300_UNISTD_H_ */
diff --git a/arch/h8300/kernel/gpio.c b/arch/h8300/kernel/gpio.c
index 6a25dd5530e7..084bfd0c107e 100644
--- a/arch/h8300/kernel/gpio.c
+++ b/arch/h8300/kernel/gpio.c
@@ -11,6 +11,7 @@
 
 #include <linux/stddef.h>
 #include <linux/proc_fs.h>
+#include <linux/seq_file.h>
 #include <linux/kernel.h>
 #include <linux/string.h>
 #include <linux/fs.h>
@@ -138,30 +139,34 @@ static char *port_status(int portno)
         return result;
 }
 
-static int gpio_proc_read(char *buf, char **start, off_t offset, 
-                          int len, int *unused_i, void *unused_v)
+static int gpio_proc_show(struct seq_file *m, void *v)
 {
-        int c,outlen;
         static const char port_name[]="123456789ABCDEFGH";
-        outlen = 0;
+        int c;
+
         for (c = 0; c < MAX_PORT; c++) {
                 if (ddrs[c] == NULL)
-                        continue ;
-                len = sprintf(buf,"P%c: %s\n",port_name[c],port_status(c));
-                buf += len;
-                outlen += len;
+                        continue;
+                seq_printf(m, "P%c: %s\n", port_name[c], port_status(c));
         }
-        return outlen;
+        return 0;
 }
 
-static __init int register_proc(void)
+static int gpio_proc_open(struct inode *inode, struct file *file)
 {
-        struct proc_dir_entry *proc_gpio;
+        return single_open(file, gpio_proc_show, PDE_DATA(inode));
+}
 
-        proc_gpio = create_proc_entry("gpio", S_IRUGO, NULL);
-        if (proc_gpio) 
-                proc_gpio->read_proc = gpio_proc_read;
-        return proc_gpio != NULL;
+static const struct file_operations gpio_proc_fops = {
+        .open           = gpio_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static __init int register_proc(void)
+{
+        return proc_create("gpio", S_IRUGO, NULL, &gpio_proc_fops) != NULL;
 }
 
 __initcall(register_proc);
diff --git a/arch/h8300/kernel/process.c b/arch/h8300/kernel/process.c
index b609f63f1590..1a744ab7e7e5 100644
--- a/arch/h8300/kernel/process.c
+++ b/arch/h8300/kernel/process.c
@@ -53,40 +53,13 @@ asmlinkage void ret_from_kernel_thread(void);
  * The idle loop on an H8/300..
  */
 #if !defined(CONFIG_H8300H_SIM) && !defined(CONFIG_H8S_SIM)
-static void default_idle(void)
+void arch_cpu_idle(void)
 {
-        local_irq_disable();
-        if (!need_resched()) {
-                local_irq_enable();
-                /* XXX: race here! What if need_resched() gets set now? */
-                __asm__("sleep");
-        } else
-                local_irq_enable();
-}
-#else
-static void default_idle(void)
-{
-        cpu_relax();
+        local_irq_enable();
+        /* XXX: race here! What if need_resched() gets set now? */
+        __asm__("sleep");
 }
 #endif
-void (*idle)(void) = default_idle;
-
-/*
- * The idle thread. There's no useful work to be
- * done, so just try to conserve power and have a
- * low exit latency (ie sit in a loop waiting for
- * somebody to say that they'd like to reschedule)
- */
-void cpu_idle(void)
-{
-        while (1) {
-                rcu_idle_enter();
-                while (!need_resched())
-                        idle();
-                rcu_idle_exit();
-                schedule_preempt_disabled();
-        }
-}
 
 void machine_restart(char * __unused)
 {
@@ -110,6 +83,8 @@ void machine_power_off(void)
 
 void show_regs(struct pt_regs * regs)
 {
+        show_regs_print_info(KERN_DEFAULT);
+
         printk("\nPC: %08lx  Status: %02x",
                regs->pc, regs->ccr);
         printk("\nORIG_ER0: %08lx ER0: %08lx ER1: %08lx",
diff --git a/arch/h8300/kernel/traps.c b/arch/h8300/kernel/traps.c
index 7833aa3e7c7d..cfe494dbe3da 100644
--- a/arch/h8300/kernel/traps.c
+++ b/arch/h8300/kernel/traps.c
@@ -164,10 +164,3 @@ void show_trace_task(struct task_struct *tsk)
 {
         show_stack(tsk,(unsigned long *)tsk->thread.esp0);
 }
-
-void dump_stack(void)
-{
-        show_stack(NULL,NULL);
-}
-
-EXPORT_SYMBOL(dump_stack);
diff --git a/arch/h8300/mm/init.c b/arch/h8300/mm/init.c
index 981e25094b1a..ff349d70a29b 100644
--- a/arch/h8300/mm/init.c
+++ b/arch/h8300/mm/init.c
@@ -139,7 +139,7 @@ void __init mem_init(void)
         start_mem = PAGE_ALIGN(start_mem);
         max_mapnr = num_physpages = MAP_NR(high_memory);
 
-        /* this will put all memory onto the freelists */
+        /* this will put all low memory onto the freelists */
         totalram_pages = free_all_bootmem();
 
         codek = (_etext - _stext) >> 10;
@@ -161,15 +161,7 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        int pages = 0;
-        for (; start < end; start += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(start));
-                init_page_count(virt_to_page(start));
-                free_page(start);
-                totalram_pages++;
-                pages++;
-        }
-        printk ("Freeing initrd memory: %dk freed\n", pages);
+        free_reserved_area(start, end, 0, "initrd");
 }
 #endif
 
@@ -177,23 +169,7 @@ void
 free_initmem(void)
 {
 #ifdef CONFIG_RAMKERNEL
-        unsigned long addr;
-/*
- *      the following code should be cool even if these sections
- *      are not page aligned.
- */
-        addr = PAGE_ALIGN((unsigned long)(__init_begin));
-        /* next to check that the page we free is not a partial page */
-        for (; addr + PAGE_SIZE < (unsigned long)__init_end; addr +=PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(addr));
-                init_page_count(virt_to_page(addr));
-                free_page(addr);
-                totalram_pages++;
-        }
-        printk(KERN_INFO "Freeing unused kernel memory: %ldk freed (0x%x - 0x%x)\n",
-                        (addr - PAGE_ALIGN((long) __init_begin)) >> 10,
-                        (int)(PAGE_ALIGN((unsigned long)__init_begin)),
-                        (int)(addr - PAGE_SIZE));
+        free_initmem_default(0);
 #endif
 }
 
diff --git a/arch/hexagon/Kconfig b/arch/hexagon/Kconfig
index e4decc6b8947..04dff5bdcbf7 100644
--- a/arch/hexagon/Kconfig
+++ b/arch/hexagon/Kconfig
@@ -29,21 +29,17 @@ config HEXAGON
         select GENERIC_CLOCKEVENTS
         select GENERIC_CLOCKEVENTS_BROADCAST
         select MODULES_USE_ELF_RELA
+        select GENERIC_CPU_DEVICES
+        select GENERIC_KERNEL_THREAD
+        select GENERIC_KERNEL_EXECVE
         ---help---
           Qualcomm Hexagon is a processor architecture designed for high
           performance and low power across a wide variety of applications.
 
-config HEXAGON_ARCH_V1
-        bool
-
-config HEXAGON_ARCH_V2
-        bool
-
-config HEXAGON_ARCH_V3
-        bool
-
-config HEXAGON_ARCH_V4
-        bool
+config HEXAGON_PHYS_OFFSET
+        def_bool y
+        ---help---
+          Platforms that don't load the kernel at zero set this.
 
 config FRAME_POINTER
         def_bool y
@@ -81,9 +77,6 @@ config RWSEM_GENERIC_SPINLOCK
 config RWSEM_XCHGADD_ALGORITHM
         def_bool y
 
-config GENERIC_FIND_NEXT_BIT
-        def_bool y
-
 config GENERIC_HWEIGHT
         def_bool y
 
@@ -103,14 +96,14 @@ choice
 
 config HEXAGON_COMET
         bool "Comet Board"
-        select HEXAGON_ARCH_V2
         ---help---
           Support for the Comet platform.
 
 endchoice
 
-config HEXAGON_VM
-        def_bool y
+config HEXAGON_ARCH_VERSION
+        int "Architecture version"
+        default 2
 
 config CMDLINE
         string "Default kernel command string"
@@ -122,12 +115,6 @@ config CMDLINE
           minimum, you should specify the memory size and the root device
           (e.g., mem=64M root=/dev/nfs).
 
-config HEXAGON_ANGEL_TRAPS
-        bool "Use Angel Traps"
-        default n
-        ---help---
-          Enable angel debug traps (for printk's).
-
 config SMP
         bool "Multi-Processing support"
         ---help---
diff --git a/arch/hexagon/Makefile b/arch/hexagon/Makefile
index d00d900b2566..207711a0fd0c 100644
--- a/arch/hexagon/Makefile
+++ b/arch/hexagon/Makefile
@@ -15,20 +15,9 @@ KBUILD_CFLAGS += -fno-short-enums
 # LDFLAGS_MODULE += -shared
 CFLAGS_MODULE += -mlong-calls
 
-cflags-$(CONFIG_HEXAGON_ARCH_V1) += $(call cc-option,-mv1)
-cflags-$(CONFIG_HEXAGON_ARCH_V2) += $(call cc-option,-mv2)
-cflags-$(CONFIG_HEXAGON_ARCH_V3) += $(call cc-option,-mv3)
-cflags-$(CONFIG_HEXAGON_ARCH_V4) += $(call cc-option,-mv4)
-
-aflags-$(CONFIG_HEXAGON_ARCH_V1) += $(call cc-option,-mv1)
-aflags-$(CONFIG_HEXAGON_ARCH_V2) += $(call cc-option,-mv2)
-aflags-$(CONFIG_HEXAGON_ARCH_V3) += $(call cc-option,-mv3)
-aflags-$(CONFIG_HEXAGON_ARCH_V4) += $(call cc-option,-mv4)
-
-ldflags-$(CONFIG_HEXAGON_ARCH_V1) += $(call cc-option,-mv1)
-ldflags-$(CONFIG_HEXAGON_ARCH_V2) += $(call cc-option,-mv2)
-ldflags-$(CONFIG_HEXAGON_ARCH_V3) += $(call cc-option,-mv3)
-ldflags-$(CONFIG_HEXAGON_ARCH_V4) += $(call cc-option,-mv4)
+cflags-y += $(call cc-option,-mv${CONFIG_HEXAGON_ARCH_VERSION})
+aflags-y += $(call cc-option,-mv${CONFIG_HEXAGON_ARCH_VERSION})
+ldflags-y += $(call cc-option,-mv${CONFIG_HEXAGON_ARCH_VERSION})
 
 KBUILD_CFLAGS += $(cflags-y)
 KBUILD_AFLAGS += $(aflags-y)
diff --git a/arch/hexagon/include/asm/Kbuild b/arch/hexagon/include/asm/Kbuild
index bdb54ceb53bc..1da17caac23c 100644
--- a/arch/hexagon/include/asm/Kbuild
+++ b/arch/hexagon/include/asm/Kbuild
@@ -25,7 +25,6 @@ generic-y += kdebug.h
 generic-y += kmap_types.h
 generic-y += local64.h
 generic-y += local.h
-generic-y += local.h
 generic-y += mman.h
 generic-y += msgbuf.h
 generic-y += pci.h
@@ -41,6 +40,7 @@ generic-y += sembuf.h
 generic-y += shmbuf.h
 generic-y += shmparam.h
 generic-y += siginfo.h
+generic-y += sizes.h
 generic-y += socket.h
 generic-y += sockios.h
 generic-y += statfs.h
diff --git a/arch/hexagon/include/asm/atomic.h b/arch/hexagon/include/asm/atomic.h
index 468fbb0781cd..8a64ff2337f6 100644
--- a/arch/hexagon/include/asm/atomic.h
+++ b/arch/hexagon/include/asm/atomic.h
@@ -1,7 +1,7 @@
 /*
  * Atomic operations for the Hexagon architecture
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
  *
  *
  * This program is free software; you can redistribute it and/or modify
@@ -117,35 +117,37 @@ static inline int atomic_sub_return(int i, atomic_t *v)
 #define atomic_sub(i, v) atomic_sub_return(i, (v))
 
 /**
- * atomic_add_unless - add unless the number is a given value
+ * __atomic_add_unless - add unless the number is a given value
  * @v: pointer to value
  * @a: amount to add
  * @u: unless value is equal to u
  *
- * Returns 1 if the add happened, 0 if it didn't.
+ * Returns old value.
+ *
  */
+
 static inline int __atomic_add_unless(atomic_t *v, int a, int u)
 {
-        int output, __oldval;
+        int __oldval;
+        register int tmp;
+
         asm volatile(
                 "1:     %0 = memw_locked(%2);"
                 "       {"
                 "               p3 = cmp.eq(%0, %4);"
                 "               if (p3.new) jump:nt 2f;"
-                "               %0 = add(%0, %3);"
-                "               %1 = #0;"
+                "               %1 = add(%0, %3);"
                 "       }"
-                "       memw_locked(%2, p3) = %0;"
+                "       memw_locked(%2, p3) = %1;"
                 "       {"
                 "               if !p3 jump 1b;"
-                "               %1 = #1;"
                 "       }"
                 "2:"
-                : "=&r" (__oldval), "=&r" (output)
+                : "=&r" (__oldval), "=&r" (tmp)
                 : "r" (v), "r" (a), "r" (u)
                 : "memory", "p3"
         );
-        return output;
+        return __oldval;
 }
 
 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
diff --git a/arch/hexagon/include/asm/elf.h b/arch/hexagon/include/asm/elf.h
index 1f14e082588e..e1b933a0e121 100644
--- a/arch/hexagon/include/asm/elf.h
+++ b/arch/hexagon/include/asm/elf.h
@@ -1,7 +1,7 @@
 /*
  * ELF definitions for the Hexagon architecture
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -104,6 +104,16 @@ typedef unsigned long elf_fpregset_t;
  * Bypass the whole "regsets" thing for now and use the define.
  */
 
+#if CONFIG_HEXAGON_ARCH_VERSION >= 4
+#define CS_COPYREGS(DEST,REGS) \
+do {\
+        DEST.cs0 = REGS->cs0;\
+        DEST.cs1 = REGS->cs1;\
+} while (0)
+#else
+#define CS_COPYREGS(DEST,REGS)
+#endif
+
 #define ELF_CORE_COPY_REGS(DEST, REGS)  \
 do {                                    \
         DEST.r0 = REGS->r00;            \
@@ -148,13 +158,12 @@ do {					\
         DEST.p3_0 = REGS->preds;        \
         DEST.gp = REGS->gp;             \
         DEST.ugp = REGS->ugp;           \
-        DEST.pc = pt_elr(REGS); \
+        CS_COPYREGS(DEST,REGS);         \
+        DEST.pc = pt_elr(REGS);         \
         DEST.cause = pt_cause(REGS);    \
         DEST.badva = pt_badva(REGS);    \
 } while (0);
 
-
-
 /*
  * This is used to ensure we don't load something for the wrong architecture.
  * Checks the machine and ABI type.
@@ -168,15 +177,15 @@ do {					\
 #define ELF_DATA        ELFDATA2LSB
 #define ELF_ARCH        EM_HEXAGON
 
-#ifdef CONFIG_HEXAGON_ARCH_V2
+#if CONFIG_HEXAGON_ARCH_VERSION == 2
 #define ELF_CORE_EFLAGS 0x1
 #endif
 
-#ifdef CONFIG_HEXAGON_ARCH_V3
+#if CONFIG_HEXAGON_ARCH_VERSION == 3
 #define ELF_CORE_EFLAGS 0x2
 #endif
 
-#ifdef CONFIG_HEXAGON_ARCH_V4
+#if CONFIG_HEXAGON_ARCH_VERSION == 4
 #define ELF_CORE_EFLAGS 0x3
 #endif
 
diff --git a/arch/hexagon/include/asm/hexagon_vm.h b/arch/hexagon/include/asm/hexagon_vm.h
index c144bee6cabe..67bb6d6f3337 100644
--- a/arch/hexagon/include/asm/hexagon_vm.h
+++ b/arch/hexagon/include/asm/hexagon_vm.h
@@ -1,7 +1,7 @@
 /*
  * Declarations for to Hexagon Virtal Machine.
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -31,10 +31,26 @@
  * for tracing/debugging.
  */
 
-/*
- * Lets make this stuff visible only if configured,
- * so we can unconditionally include the file.
- */
+#define HVM_TRAP1_VMVERSION             0
+#define HVM_TRAP1_VMRTE                 1
+#define HVM_TRAP1_VMSETVEC              2
+#define HVM_TRAP1_VMSETIE               3
+#define HVM_TRAP1_VMGETIE               4
+#define HVM_TRAP1_VMINTOP               5
+#define HVM_TRAP1_VMCLRMAP              10
+#define HVM_TRAP1_VMNEWMAP              11
+#define HVM_TRAP1_FORMERLY_VMWIRE       12
+#define HVM_TRAP1_VMCACHE               13
+#define HVM_TRAP1_VMGETTIME             14
+#define HVM_TRAP1_VMSETTIME             15
+#define HVM_TRAP1_VMWAIT                16
+#define HVM_TRAP1_VMYIELD               17
+#define HVM_TRAP1_VMSTART               18
+#define HVM_TRAP1_VMSTOP                19
+#define HVM_TRAP1_VMVPID                20
+#define HVM_TRAP1_VMSETREGS             21
+#define HVM_TRAP1_VMGETREGS             22
+#define HVM_TRAP1_VMTIMEROP             24
 
 #ifndef __ASSEMBLY__
 
@@ -175,31 +191,19 @@ static inline long __vmintop_clear(long i)
 
 #else /* Only assembly code should reference these */
 
-#define HVM_TRAP1_VMRTE                 1
-#define HVM_TRAP1_VMSETVEC              2
-#define HVM_TRAP1_VMSETIE               3
-#define HVM_TRAP1_VMGETIE               4
-#define HVM_TRAP1_VMINTOP               5
-#define HVM_TRAP1_VMCLRMAP              10
-#define HVM_TRAP1_VMNEWMAP              11
-#define HVM_TRAP1_FORMERLY_VMWIRE       12
-#define HVM_TRAP1_VMCACHE               13
-#define HVM_TRAP1_VMGETTIME             14
-#define HVM_TRAP1_VMSETTIME             15
-#define HVM_TRAP1_VMWAIT                16
-#define HVM_TRAP1_VMYIELD               17
-#define HVM_TRAP1_VMSTART               18
-#define HVM_TRAP1_VMSTOP                19
-#define HVM_TRAP1_VMVPID                20
-#define HVM_TRAP1_VMSETREGS             21
-#define HVM_TRAP1_VMGETREGS             22
-
 #endif /* __ASSEMBLY__ */
 
 /*
  * Constants for virtual instruction parameters and return values
  */
 
+/* vmnewmap arguments */
+
+#define VM_TRANS_TYPE_LINEAR 0
+#define VM_TRANS_TYPE_TABLE 1
+#define VM_TLB_INVALIDATE_FALSE 0
+#define VM_TLB_INVALIDATE_TRUE 1
+
 /* vmsetie arguments */
 
 #define VM_INT_DISABLE  0
@@ -224,6 +228,8 @@ static inline long __vmintop_clear(long i)
 #define HVM_VMEST_UM_MSK        1
 #define HVM_VMEST_IE_SFT        30
 #define HVM_VMEST_IE_MSK        1
+#define HVM_VMEST_SS_SFT        29
+#define HVM_VMEST_SS_MSK        1
 #define HVM_VMEST_EVENTNUM_SFT  16
 #define HVM_VMEST_EVENTNUM_MSK  0xff
 #define HVM_VMEST_CAUSE_SFT     0
@@ -260,6 +266,8 @@ static inline long __vmintop_clear(long i)
 #define HVM_GE_C_INVI   0x15
 #define HVM_GE_C_PRIVI  0x1B
 #define HVM_GE_C_XMAL   0x1C
+#define HVM_GE_C_WREG   0x1D
+#define HVM_GE_C_PCAL   0x1E
 #define HVM_GE_C_RMAL   0x20
 #define HVM_GE_C_WMAL   0x21
 #define HVM_GE_C_RPROT  0x22
diff --git a/arch/hexagon/include/asm/io.h b/arch/hexagon/include/asm/io.h
index e527cfeff5ba..1b7698e19139 100644
--- a/arch/hexagon/include/asm/io.h
+++ b/arch/hexagon/include/asm/io.h
@@ -1,7 +1,7 @@
 /*
  * IO definitions for the Hexagon architecture
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -40,6 +40,8 @@
 #define IO_SPACE_LIMIT 0xffff
 #define _IO_BASE ((void __iomem *)0xfe000000)
 
+#define IOMEM(x)        ((void __force __iomem *)(x))
+
 extern int remap_area_pages(unsigned long start, unsigned long phys_addr,
                                 unsigned long end, unsigned long flags);
 
@@ -176,6 +178,18 @@ static inline void writel(u32 data, volatile void __iomem *addr)
 #define __raw_readl readl
 
 /*
+ * http://comments.gmane.org/gmane.linux.ports.arm.kernel/117626
+ */
+
+#define readb_relaxed __raw_readb
+#define readw_relaxed __raw_readw
+#define readl_relaxed __raw_readl
+
+#define writeb_relaxed __raw_writeb
+#define writew_relaxed __raw_writew
+#define writel_relaxed __raw_writel
+
+/*
  * Need an mtype somewhere in here, for cache type deals?
  * This is probably too long for an inline.
  */
diff --git a/arch/hexagon/include/asm/mem-layout.h b/arch/hexagon/include/asm/mem-layout.h
index af16e977c55e..60556f8c45d8 100644
--- a/arch/hexagon/include/asm/mem-layout.h
+++ b/arch/hexagon/include/asm/mem-layout.h
@@ -1,7 +1,7 @@
 /*
  * Memory layout definitions for the Hexagon architecture
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -32,16 +32,25 @@
 #define PAGE_OFFSET                     _AC(0xc0000000, UL)
 
 /*
- * LOAD_ADDRESS is the physical/linear address of where in memory
- * the kernel gets loaded. The 12 least significant bits must be zero (0)
- * due to limitations on setting the EVB
- *
+ * Compiling for a platform that needs a crazy physical offset
+ * (like if the memory starts at 1GB and up) means we need
+ * an actual PHYS_OFFSET.  Should be set up in head.S.
  */
 
-#ifndef LOAD_ADDRESS
-#define LOAD_ADDRESS                    0x00000000
+#ifdef CONFIG_HEXAGON_PHYS_OFFSET
+#ifndef __ASSEMBLY__
+extern unsigned long    __phys_offset;
+#endif
+#define PHYS_OFFSET     __phys_offset
+#endif
+
+#ifndef PHYS_OFFSET
+#define PHYS_OFFSET     0
 #endif
 
+#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT)
+#define ARCH_PFN_OFFSET PHYS_PFN_OFFSET
+
 #define TASK_SIZE                       (PAGE_OFFSET)
 
 /*  not sure how these are used yet  */
@@ -55,7 +64,7 @@ enum fixed_addresses {
         __end_of_fixed_addresses
 };
 
-#define MIN_KERNEL_SEG 0x300   /* From 0xc0000000 */
+#define MIN_KERNEL_SEG (PAGE_OFFSET >> PGDIR_SHIFT)   /* L1 shift is 22 bits */
 extern int max_kernel_seg;
 
 /*
@@ -63,8 +72,7 @@ extern int max_kernel_seg;
  * supposed to be based on the amount of physical memory available
  */
 
-#define VMALLOC_START (PAGE_OFFSET + VMALLOC_OFFSET + \
-        (unsigned long)high_memory)
+#define VMALLOC_START ((unsigned long) __va(high_memory + VMALLOC_OFFSET))
 
 /* Gap between physical ram and vmalloc space for guard purposes. */
 #define VMALLOC_OFFSET PAGE_SIZE
diff --git a/arch/hexagon/include/asm/page.h b/arch/hexagon/include/asm/page.h
index 692adc213429..93f5669b4aa1 100644
--- a/arch/hexagon/include/asm/page.h
+++ b/arch/hexagon/include/asm/page.h
@@ -1,7 +1,7 @@
 /*
  * Page management definitions for the Hexagon architecture
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -96,8 +96,8 @@ typedef struct page *pgtable_t;
  * MIPS says they're only used during mem_init.
  * also, check if we need a PHYS_OFFSET.
  */
-#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET)
-#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET))
+#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET)
+#define __va(x) ((void *)((unsigned long)(x) - PHYS_OFFSET + PAGE_OFFSET))
 
 /* The "page frame" descriptor is defined in linux/mm.h */
 struct page;
@@ -140,6 +140,11 @@ static inline void clear_page(void *page)
  */
 #define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
 
+#define virt_to_pfn(kaddr)      (__pa(kaddr) >> PAGE_SHIFT)
+#define pfn_to_virt(pfn)        __va((pfn) << PAGE_SHIFT)
+
+#define page_to_virt(page)      __va(page_to_phys(page))
+
 /*
  * For port to Hexagon Virtual Machine, MAYBE we check for attempts
  * to reference reserved HVM space, but in any case, the VM will be
@@ -147,6 +152,7 @@ static inline void clear_page(void *page)
  */
 #define kern_addr_valid(addr)   (1)
 
+#include <asm/mem-layout.h>
 #include <asm-generic/memory_model.h>
 /* XXX Todo: implement assembly-optimized version of getorder. */
 #include <asm-generic/getorder.h>
diff --git a/arch/hexagon/include/asm/processor.h b/arch/hexagon/include/asm/processor.h
index 6dd5d3706869..45a825402f63 100644
--- a/arch/hexagon/include/asm/processor.h
+++ b/arch/hexagon/include/asm/processor.h
@@ -1,7 +1,7 @@
 /*
  * Process/processor support for the Hexagon architecture
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -100,12 +100,49 @@ extern unsigned long get_wchan(struct task_struct *p);
  */
 
 struct hexagon_switch_stack {
-        unsigned long long      r1716;
-        unsigned long long      r1918;
-        unsigned long long      r2120;
-        unsigned long long      r2322;
-        unsigned long long      r2524;
-        unsigned long long      r2726;
+        union {
+                struct {
+                        unsigned long r16;
+                        unsigned long r17;
+                };
+                unsigned long long      r1716;
+        };
+        union {
+                struct {
+                        unsigned long r18;
+                        unsigned long r19;
+                };
+                unsigned long long      r1918;
+        };
+        union {
+                struct {
+                        unsigned long r20;
+                        unsigned long r21;
+                };
+                unsigned long long      r2120;
+        };
+        union {
+                struct {
+                        unsigned long r22;
+                        unsigned long r23;
+                };
+                unsigned long long      r2322;
+        };
+        union {
+                struct {
+                        unsigned long r24;
+                        unsigned long r25;
+                };
+                unsigned long long      r2524;
+        };
+        union {
+                struct {
+                        unsigned long r26;
+                        unsigned long r27;
+                };
+                unsigned long long      r2726;
+        };
+
         unsigned long           fp;
         unsigned long           lr;
 };
diff --git a/arch/hexagon/include/asm/vm_mmu.h b/arch/hexagon/include/asm/vm_mmu.h
index 9a94de7969bb..096537d8f4c5 100644
--- a/arch/hexagon/include/asm/vm_mmu.h
+++ b/arch/hexagon/include/asm/vm_mmu.h
@@ -1,7 +1,7 @@
 /*
  * Hexagon VM page table entry definitions
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2011,2013 The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -68,14 +68,13 @@
 
 #define __HEXAGON_C_WB          0x0     /* Write-back, no L2 */
 #define __HEXAGON_C_WT          0x1     /* Write-through, no L2 */
+#define __HEXAGON_C_UNC         0x6     /* Uncached memory */
+#if CONFIG_HEXAGON_ARCH_VERSION >= 2
 #define __HEXAGON_C_DEV         0x4     /* Device register space */
-#define __HEXAGON_C_WT_L2       0x5     /* Write-through, with L2 */
-/* this really should be #if CONFIG_HEXAGON_ARCH = 2 but that's not defined */
-#if defined(CONFIG_HEXAGON_COMET) || defined(CONFIG_QDSP6_ST1)
-#define __HEXAGON_C_UNC         __HEXAGON_C_DEV
 #else
-#define __HEXAGON_C_UNC         0x6     /* Uncached memory */
+#define __HEXAGON_C_DEV         __HEXAGON_C_UNC
 #endif
+#define __HEXAGON_C_WT_L2       0x5     /* Write-through, with L2 */
 #define __HEXAGON_C_WB_L2       0x7     /* Write-back, with L2 */
 
 /*
diff --git a/arch/hexagon/include/uapi/asm/ptrace.h b/arch/hexagon/include/uapi/asm/ptrace.h
index 1ffce0c6ee07..065e5b32313f 100644
--- a/arch/hexagon/include/uapi/asm/ptrace.h
+++ b/arch/hexagon/include/uapi/asm/ptrace.h
@@ -36,4 +36,9 @@ extern const char *regs_query_register_name(unsigned int offset);
         ((struct pt_regs *) \
          ((unsigned long)current_thread_info() + THREAD_SIZE) - 1)
 
+#if CONFIG_HEXAGON_ARCH_VERSION >= 4
+#define arch_has_single_step()  (1)
+#endif
+
+
 #endif
diff --git a/arch/hexagon/include/uapi/asm/registers.h b/arch/hexagon/include/uapi/asm/registers.h
index c20406f63b5c..487d6ceca5e7 100644
--- a/arch/hexagon/include/uapi/asm/registers.h
+++ b/arch/hexagon/include/uapi/asm/registers.h
@@ -57,10 +57,17 @@ struct pt_regs {
         };
         union {
                 struct {
-                        unsigned long gp;
                         unsigned long ugp;
+                        unsigned long gp;
                 };
-                long long int ugpgp;
+                long long int gpugp;
+        };
+        union {
+                struct {
+                        unsigned long cs0;
+                        unsigned long cs1;
+                };
+                long long int cs1cs0;
         };
         /*
         * Be extremely careful with rearranging these, if at all.  Some code
@@ -204,9 +211,11 @@ struct pt_regs {
 #define pt_psp(regs) ((regs)->hvmer.vmpsp)
 #define pt_badva(regs) ((regs)->hvmer.vmbadva)
 
+#define pt_set_singlestep(regs) ((regs)->hvmer.vmest |= (1<<HVM_VMEST_SS_SFT))
+#define pt_clr_singlestep(regs) ((regs)->hvmer.vmest &= ~(1<<HVM_VMEST_SS_SFT))
+
 #define pt_set_rte_sp(regs, sp) do {\
-        pt_psp(regs) = (sp);\
-        (regs)->SP = (unsigned long) &((regs)->hvmer);\
+        pt_psp(regs) = (regs)->SP = (sp);\
         } while (0)
 
 #define pt_set_kmode(regs) \
diff --git a/arch/hexagon/include/uapi/asm/signal.h b/arch/hexagon/include/uapi/asm/signal.h
index 939556817d34..98106e55ad4f 100644
--- a/arch/hexagon/include/uapi/asm/signal.h
+++ b/arch/hexagon/include/uapi/asm/signal.h
@@ -19,8 +19,12 @@
 #ifndef _ASM_SIGNAL_H
 #define _ASM_SIGNAL_H
 
+#include <uapi/asm/registers.h>
+
 extern unsigned long __rt_sigtramp_template[2];
 
+void do_signal(struct pt_regs *regs);
+
 #include <asm-generic/signal.h>
 
 #endif
diff --git a/arch/hexagon/include/uapi/asm/unistd.h b/arch/hexagon/include/uapi/asm/unistd.h
index 4a87cc47075c..ffee405d6803 100644
--- a/arch/hexagon/include/uapi/asm/unistd.h
+++ b/arch/hexagon/include/uapi/asm/unistd.h
@@ -27,6 +27,9 @@
  */
 
 #define sys_mmap2 sys_mmap_pgoff
+#define __ARCH_WANT_SYS_EXECVE
 #define __ARCH_WANT_SYS_CLONE
+#define __ARCH_WANT_SYS_VFORK
+#define __ARCH_WANT_SYS_FORK
 
 #include <asm-generic/unistd.h>
diff --git a/arch/hexagon/include/uapi/asm/user.h b/arch/hexagon/include/uapi/asm/user.h
index cef13ee1413f..3dae94d9ced7 100644
--- a/arch/hexagon/include/uapi/asm/user.h
+++ b/arch/hexagon/include/uapi/asm/user.h
@@ -55,9 +55,15 @@ struct user_regs_struct {
         unsigned long pc;
         unsigned long cause;
         unsigned long badva;
+#if CONFIG_HEXAGON_ARCH_VERSION < 4
         unsigned long pad1;  /* pad out to 48 words total */
         unsigned long pad2;  /* pad out to 48 words total */
         unsigned long pad3;  /* pad out to 48 words total */
+#else
+        unsigned long cs0;
+        unsigned long cs1;
+        unsigned long pad1;  /* pad out to 48 words total */
+#endif
 };
 
 #endif
diff --git a/arch/hexagon/kernel/Makefile b/arch/hexagon/kernel/Makefile
index 6c19501b487c..29fc933a7722 100644
--- a/arch/hexagon/kernel/Makefile
+++ b/arch/hexagon/kernel/Makefile
@@ -1,6 +1,6 @@
 extra-y := head.o vmlinux.lds
 
-obj-$(CONFIG_SMP) += smp.o topology.o
+obj-$(CONFIG_SMP) += smp.o
 
 obj-y += setup.o irq_cpu.o traps.o syscalltab.o signal.o time.o
 obj-y += process.o trampoline.o reset.o ptrace.o vdso.o
diff --git a/arch/hexagon/kernel/asm-offsets.c b/arch/hexagon/kernel/asm-offsets.c
index 2d5e84d3b00d..308be68d4fb3 100644
--- a/arch/hexagon/kernel/asm-offsets.c
+++ b/arch/hexagon/kernel/asm-offsets.c
@@ -5,7 +5,7 @@
  * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2000 MIPS Technologies, Inc.
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -44,7 +44,8 @@ int main(void)
 
         COMMENT("Hexagon pt_regs definitions");
         OFFSET(_PT_SYSCALL_NR, pt_regs, syscall_nr);
-        OFFSET(_PT_UGPGP, pt_regs, ugpgp);
+        OFFSET(_PT_GPUGP, pt_regs, gpugp);
+        OFFSET(_PT_CS1CS0, pt_regs, cs1cs0);
         OFFSET(_PT_R3130, pt_regs, r3130);
         OFFSET(_PT_R2928, pt_regs, r2928);
         OFFSET(_PT_R2726, pt_regs, r2726);
diff --git a/arch/hexagon/kernel/dma.c b/arch/hexagon/kernel/dma.c
index 65c7bdcf565e..b74f9bae31a3 100644
--- a/arch/hexagon/kernel/dma.c
+++ b/arch/hexagon/kernel/dma.c
@@ -1,7 +1,7 @@
 /*
  * DMA implementation for Hexagon
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -23,12 +23,18 @@
 #include <linux/genalloc.h>
 #include <asm/dma-mapping.h>
 #include <linux/module.h>
+#include <asm/page.h>
 
 struct dma_map_ops *dma_ops;
 EXPORT_SYMBOL(dma_ops);
 
 int bad_dma_address;  /*  globals are automatically initialized to zero  */
 
+static inline void *dma_addr_to_virt(dma_addr_t dma_addr)
+{
+        return phys_to_virt((unsigned long) dma_addr);
+}
+
 int dma_supported(struct device *dev, u64 mask)
 {
         if (mask == DMA_BIT_MASK(32))
@@ -60,6 +66,12 @@ static void *hexagon_dma_alloc_coherent(struct device *dev, size_t size,
 {
         void *ret;
 
+        /*
+         * Our max_low_pfn should have been backed off by 16MB in
+         * mm/init.c to create DMA coherent space.  Use that as the VA
+         * for the pool.
+         */
+
         if (coherent_pool == NULL) {
                 coherent_pool = gen_pool_create(PAGE_SHIFT, -1);
 
@@ -67,7 +79,7 @@ static void *hexagon_dma_alloc_coherent(struct device *dev, size_t size,
                         panic("Can't create %s() memory pool!", __func__);
                 else
                         gen_pool_add(coherent_pool,
-                                (PAGE_OFFSET + (max_low_pfn << PAGE_SHIFT)),
+                                pfn_to_virt(max_low_pfn),
                                 hexagon_coherent_pool_size, -1);
         }
 
@@ -75,7 +87,7 @@ static void *hexagon_dma_alloc_coherent(struct device *dev, size_t size,
 
         if (ret) {
                 memset(ret, 0, size);
-                *dma_addr = (dma_addr_t) (ret - PAGE_OFFSET);
+                *dma_addr = (dma_addr_t) virt_to_phys(ret);
         } else
                 *dma_addr = ~0;
 
@@ -118,8 +130,8 @@ static int hexagon_map_sg(struct device *hwdev, struct scatterlist *sg,
 
                 s->dma_length = s->length;
 
-                flush_dcache_range(PAGE_OFFSET + s->dma_address,
-                                   PAGE_OFFSET + s->dma_address + s->length);
+                flush_dcache_range(dma_addr_to_virt(s->dma_address),
+                                   dma_addr_to_virt(s->dma_address + s->length));
         }
 
         return nents;
@@ -149,11 +161,6 @@ static inline void dma_sync(void *addr, size_t size,
         }
 }
 
-static inline void *dma_addr_to_virt(dma_addr_t dma_addr)
-{
-        return phys_to_virt((unsigned long) dma_addr);
-}
-
 /**
  * hexagon_map_page() - maps an address for device DMA
  * @dev:        pointer to DMA device
diff --git a/arch/hexagon/kernel/head.S b/arch/hexagon/kernel/head.S
index d859402c73ba..b9b63d085db2 100644
--- a/arch/hexagon/kernel/head.S
+++ b/arch/hexagon/kernel/head.S
@@ -1,7 +1,7 @@
 /*
  * Early kernel startup code for Hexagon
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
  *
  *
  * This program is free software; you can redistribute it and/or modify
@@ -25,6 +25,9 @@
 #include <asm/mem-layout.h>
 #include <asm/vm_mmu.h>
 #include <asm/page.h>
+#include <asm/hexagon_vm.h>
+
+#define SEGTABLE_ENTRIES #0x0e0
 
         __INIT
 ENTRY(stext)
@@ -43,40 +46,93 @@ ENTRY(stext)
          * Symbol is kernel segment address, but we need
          * the logical/physical address.
          */
-        r24 = asl(r24, #2)
-        r24 = lsr(r24, #2)
+        r25 = pc;
+        r2.h = #0xffc0;
+        r2.l = #0x0000;
+        r25 = and(r2,r25);      /*  R25 holds PHYS_OFFSET now  */
+        r1.h = #HI(PAGE_OFFSET);
+        r1.l = #LO(PAGE_OFFSET);
+        r24 = sub(r24,r1);      /* swapper_pg_dir - PAGE_OFFSET */
+        r24 = add(r24,r25);     /* + PHYS_OFFSET */
 
-        r0 = r24
+        r0 = r24;  /* aka __pa(swapper_pg_dir)  */
 
         /*
-         * Initialize a 16MB PTE to make the virtual and physical
+         * Initialize page dir to make the virtual and physical
          * addresses where the kernel was loaded be identical.
+         * Done in 4MB chunks.
          */
 #define PTE_BITS ( __HVM_PTE_R | __HVM_PTE_W | __HVM_PTE_X      \
                   | __HEXAGON_C_WB_L2 << 6                      \
                   | __HVM_PDE_S_4MB)
 
-        r1 = pc
-        r2.H = #0xffc0
-        r2.L = #0x0000
-        r1 = and(r1,r2)         /* round PC to 4MB boundary     */
+        /*
+         * Get number of VA=PA entries; only really needed for jump
+         * to hyperspace; gets blown away immediately after
+         */
+
+        {
+                r1.l = #LO(_end);
+                r2.l = #LO(stext);
+                r3 = #1;
+        }
+        {
+                r1.h = #HI(_end);
+                r2.h = #HI(stext);
+                r3 = asl(r3, #22);
+        }
+        {
+                r1 = sub(r1, r2);
+                r3 = add(r3, #-1);
+        }  /* r1 =  _end - stext  */
+        r1 = add(r1, r3);  /*  + (4M-1) */
+        r26 = lsr(r1, #22); /*  / 4M = # of entries */
+
+        r1 = r25;
+        r2.h = #0xffc0;
+        r2.l = #0x0000;         /* round back down to 4MB boundary  */
+        r1 = and(r1,r2);
         r2 = lsr(r1, #22)       /* 4MB page number              */
         r2 = asl(r2, #2)        /* times sizeof(PTE) (4bytes)   */
         r0 = add(r0,r2)         /* r0 = address of correct PTE  */
         r2 = #PTE_BITS
         r1 = add(r1,r2)         /* r1 = 4MB PTE for the first entry     */
         r2.h = #0x0040
-        r2.l = #0x0000          /* 4MB  */
-        memw(r0 ++ #4) = r1
-        r1 = add(r1, r2)
+        r2.l = #0x0000          /* 4MB increments */
+        loop0(1f,r26);
+1:
         memw(r0 ++ #4) = r1
+        { r1 = add(r1, r2); } :endloop0
+
+        /*  Also need to overwrite the initial 0xc0000000 entries  */
+        /*  PAGE_OFFSET >> (4MB shift - 4 bytes per entry shift)  */
+        R1.H = #HI(PAGE_OFFSET >> (22 - 2))
+        R1.L = #LO(PAGE_OFFSET >> (22 - 2))
+
+        r0 = add(r1, r24);      /* advance to 0xc0000000 entry */
+        r1 = r25;
+        r2.h = #0xffc0;
+        r2.l = #0x0000;         /* round back down to 4MB boundary  */
+        r1 = and(r1,r2);        /* for huge page */
+        r2 = #PTE_BITS
+        r1 = add(r1,r2);
+        r2.h = #0x0040
+        r2.l = #0x0000          /* 4MB increments */
 
-        r0 = r24
+        loop0(1f,SEGTABLE_ENTRIES);
+1:
+        memw(r0 ++ #4) = r1;
+        { r1 = add(r1,r2); } :endloop0
+
+        r0 = r24;
 
         /*
          * The subroutine wrapper around the virtual instruction touches
          * no memory, so we should be able to use it even here.
+         * Note that in this version, R1 and R2 get "clobbered"; see
+         * vm_ops.S
          */
+        r1 = #VM_TRANS_TYPE_TABLE
         call    __vmnewmap;
 
         /*  Jump into virtual address range.  */
@@ -90,17 +146,29 @@ ENTRY(stext)
 __head_s_vaddr_target:
         /*
          * Tear down VA=PA translation now that we are running
-         * in the desgnated kernel segments.
+         * in kernel virtual space.
          */
         r0 = #__HVM_PDE_S_INVALID
-        r1 = r24
-        loop0(1f,#0x100)
+
+        r1.h = #0xffc0;
+        r1.l = #0x0000;
+        r2 = r25;               /* phys_offset */
+        r2 = and(r1,r2);
+
+        r1.l = #lo(swapper_pg_dir)
+        r1.h = #hi(swapper_pg_dir)
+        r2 = lsr(r2, #22)       /* 4MB page number              */
+        r2 = asl(r2, #2)        /* times sizeof(PTE) (4bytes)   */
+        r1 = add(r1,r2);
+        loop0(1f,r26)
+
 1:
         {
                 memw(R1 ++ #4) = R0
         }:endloop0
 
         r0 = r24
+        r1 = #VM_TRANS_TYPE_TABLE
         call __vmnewmap
 
         /*  Go ahead and install the trap0 return so angel calls work  */
@@ -143,6 +211,13 @@ __head_s_vaddr_target:
         r2 = sub(r2,r0);
         call memset;
 
+        /*  Set PHYS_OFFSET; should be in R25 */
+#ifdef CONFIG_HEXAGON_PHYS_OFFSET
+        r0.l = #LO(__phys_offset);
+        r0.h = #HI(__phys_offset);
+        memw(r0) = r25;
+#endif
+
         /* Time to make the doughnuts.   */
         call start_kernel
 
diff --git a/arch/hexagon/kernel/kgdb.c b/arch/hexagon/kernel/kgdb.c
index 344645370646..82d5c2593323 100644
--- a/arch/hexagon/kernel/kgdb.c
+++ b/arch/hexagon/kernel/kgdb.c
@@ -1,7 +1,7 @@
 /*
  * arch/hexagon/kernel/kgdb.c - Hexagon KGDB Support
  *
- * Copyright (c) 2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -70,6 +70,8 @@ struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = {
         { "lc1", GDB_SIZEOF_REG, offsetof(struct pt_regs, lc1)},
         { " gp", GDB_SIZEOF_REG, offsetof(struct pt_regs, gp)},
         { "ugp", GDB_SIZEOF_REG, offsetof(struct pt_regs, ugp)},
+        { "cs0", GDB_SIZEOF_REG, offsetof(struct pt_regs, cs0)},
+        { "cs1", GDB_SIZEOF_REG, offsetof(struct pt_regs, cs1)},
         { "psp", GDB_SIZEOF_REG, offsetof(struct pt_regs, hvmer.vmpsp)},
         { "elr", GDB_SIZEOF_REG, offsetof(struct pt_regs, hvmer.vmel)},
         { "est", GDB_SIZEOF_REG, offsetof(struct pt_regs, hvmer.vmest)},
diff --git a/arch/hexagon/kernel/process.c b/arch/hexagon/kernel/process.c
index 06ae9ffcabd5..0a0dd5c05b46 100644
--- a/arch/hexagon/kernel/process.c
+++ b/arch/hexagon/kernel/process.c
@@ -24,6 +24,7 @@
 #include <linux/tick.h>
 #include <linux/uaccess.h>
 #include <linux/slab.h>
+#include <linux/tracehook.h>
 
 /*
  * Program thread launch.  Often defined as a macro in processor.h,
@@ -51,28 +52,11 @@ void start_thread(struct pt_regs *regs, unsigned long pc, unsigned long sp)
  *  If hardware or VM offer wait termination even though interrupts
  *  are disabled.
  */
-static void default_idle(void)
+void arch_cpu_idle(void)
 {
         __vmwait();
-}
-
-void (*idle_sleep)(void) = default_idle;
-
-void cpu_idle(void)
-{
-        while (1) {
-                tick_nohz_idle_enter();
-                local_irq_disable();
-                while (!need_resched()) {
-                        idle_sleep();
-                        /*  interrupts wake us up, but aren't serviced  */
-                        local_irq_enable();     /* service interrupt   */
-                        local_irq_disable();
-                }
-                local_irq_enable();
-                tick_nohz_idle_exit();
-                schedule();
-        }
+        /*  interrupts wake us up, but irqs are still disabled */
+        local_irq_enable();
 }
 
 /*
@@ -112,7 +96,8 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
         if (unlikely(p->flags & PF_KTHREAD)) {
                 memset(childregs, 0, sizeof(struct pt_regs));
                 /* r24 <- fn, r25 <- arg */
-                ss->r2524 = usp | ((u64)arg << 32);
+                ss->r24 = usp;
+                ss->r25 = arg;
                 pt_set_kmode(childregs);
                 return 0;
         }
@@ -202,3 +187,41 @@ int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpu)
 {
         return 0;
 }
+
+
+/*
+ * Called on the exit path of event entry; see vm_entry.S
+ *
+ * Interrupts will already be disabled.
+ *
+ * Returns 0 if there's no need to re-check for more work.
+ */
+
+int do_work_pending(struct pt_regs *regs, u32 thread_info_flags)
+{
+        if (!(thread_info_flags & _TIF_WORK_MASK)) {
+                return 0;
+        }  /* shortcut -- no work to be done */
+
+        local_irq_enable();
+
+        if (thread_info_flags & _TIF_NEED_RESCHED) {
+                schedule();
+                return 1;
+        }
+
+        if (thread_info_flags & _TIF_SIGPENDING) {
+                do_signal(regs);
+                return 1;
+        }
+
+        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
+                return 1;
+        }
+
+        /* Should not even reach here */
+        panic("%s: bad thread_info flags 0x%08x\n", __func__,
+                thread_info_flags);
+}
diff --git a/arch/hexagon/kernel/ptrace.c b/arch/hexagon/kernel/ptrace.c
index 670b1b0bee63..de829eb7f185 100644
--- a/arch/hexagon/kernel/ptrace.c
+++ b/arch/hexagon/kernel/ptrace.c
@@ -1,7 +1,7 @@
 /*
  * Ptrace support for Hexagon
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -32,6 +32,21 @@
 
 #include <asm/user.h>
 
+#if arch_has_single_step()
+/*  Both called from ptrace_resume  */
+void user_enable_single_step(struct task_struct *child)
+{
+        pt_set_singlestep(task_pt_regs(child));
+        set_tsk_thread_flag(child, TIF_SINGLESTEP);
+}
+
+void user_disable_single_step(struct task_struct *child)
+{
+        pt_clr_singlestep(task_pt_regs(child));
+        clear_tsk_thread_flag(child, TIF_SINGLESTEP);
+}
+#endif
+
 static int genregs_get(struct task_struct *target,
                    const struct user_regset *regset,
                    unsigned int pos, unsigned int count,
@@ -76,6 +91,10 @@ static int genregs_get(struct task_struct *target,
         dummy = pt_cause(regs);
         ONEXT(&dummy, cause);
         ONEXT(&pt_badva(regs), badva);
+#if CONFIG_HEXAGON_ARCH_VERSION >=4
+        ONEXT(&regs->cs0, cs0);
+        ONEXT(&regs->cs1, cs1);
+#endif
 
         /* Pad the rest with zeros, if needed */
         if (!ret)
@@ -123,6 +142,11 @@ static int genregs_set(struct task_struct *target,
         INEXT(&bucket, cause);
         INEXT(&bucket, badva);
 
+#if CONFIG_HEXAGON_ARCH_VERSION >=4
+        INEXT(&regs->cs0, cs0);
+        INEXT(&regs->cs1, cs1);
+#endif
+
         /* Ignore the rest, if needed */
         if (!ret)
                 ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
diff --git a/arch/hexagon/kernel/setup.c b/arch/hexagon/kernel/setup.c
index 94a387835008..bfe13311d70d 100644
--- a/arch/hexagon/kernel/setup.c
+++ b/arch/hexagon/kernel/setup.c
@@ -1,7 +1,7 @@
 /*
  * Arch related setup for Hexagon
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -68,6 +68,8 @@ void __init setup_arch(char **cmdline_p)
          */
         __vmsetvec(_K_VM_event_vector);
 
+        printk(KERN_INFO "PHYS_OFFSET=0x%08x\n", PHYS_OFFSET);
+
         /*
          * Simulator has a few differences from the hardware.
          * For now, check uninitialized-but-mapped memory
@@ -128,6 +130,11 @@ static int show_cpuinfo(struct seq_file *m, void *v)
 {
         int cpu = (unsigned long) v - 1;
 
+#ifdef CONFIG_SMP
+        if (!cpu_online(cpu))
+                return 0;
+#endif
+
         seq_printf(m, "processor\t: %d\n", cpu);
         seq_printf(m, "model name\t: Hexagon Virtual Machine\n");
         seq_printf(m, "BogoMips\t: %lu.%02lu\n",
diff --git a/arch/hexagon/kernel/signal.c b/arch/hexagon/kernel/signal.c
index 60fa2ca3202b..d7c73874b515 100644
--- a/arch/hexagon/kernel/signal.c
+++ b/arch/hexagon/kernel/signal.c
@@ -1,7 +1,7 @@
 /*
  * Signal support for Hexagon processor
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -41,6 +41,10 @@ static void __user *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs,
 {
         unsigned long sp = regs->r29;
 
+        /* check if we would overflow the alt stack */
+        if (on_sig_stack(sp) && !likely(on_sig_stack(sp - frame_size)))
+                return (void __user __force *)-1UL;
+
         /* Switch to signal stack if appropriate */
         if ((ka->sa.sa_flags & SA_ONSTACK) && (sas_ss_flags(sp) == 0))
                 sp = current->sas_ss_sp + current->sas_ss_size;
@@ -66,7 +70,10 @@ static int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
         err |= __put_user(regs->preds, &sc->sc_regs.p3_0);
         err |= __put_user(regs->gp, &sc->sc_regs.gp);
         err |= __put_user(regs->ugp, &sc->sc_regs.ugp);
-
+#if CONFIG_HEXAGON_ARCH_VERSION >= 4
+        err |= __put_user(regs->cs0, &sc->sc_regs.cs0);
+        err |= __put_user(regs->cs1, &sc->sc_regs.cs1);
+#endif
         tmp = pt_elr(regs); err |= __put_user(tmp, &sc->sc_regs.pc);
         tmp = pt_cause(regs); err |= __put_user(tmp, &sc->sc_regs.cause);
         tmp = pt_badva(regs); err |= __put_user(tmp, &sc->sc_regs.badva);
@@ -93,7 +100,10 @@ static int restore_sigcontext(struct pt_regs *regs,
         err |= __get_user(regs->preds, &sc->sc_regs.p3_0);
         err |= __get_user(regs->gp, &sc->sc_regs.gp);
         err |= __get_user(regs->ugp, &sc->sc_regs.ugp);
-
+#if CONFIG_HEXAGON_ARCH_VERSION >= 4
+        err |= __get_user(regs->cs0, &sc->sc_regs.cs0);
+        err |= __get_user(regs->cs1, &sc->sc_regs.cs1);
+#endif
         err |= __get_user(tmp, &sc->sc_regs.pc); pt_set_elr(regs, tmp);
 
         return err;
@@ -193,7 +203,7 @@ static void handle_signal(int sig, siginfo_t *info, struct k_sigaction *ka,
 /*
  * Called from return-from-event code.
  */
-static void do_signal(struct pt_regs *regs)
+void do_signal(struct pt_regs *regs)
 {
         struct k_sigaction sigact;
         siginfo_t info;
@@ -210,8 +220,9 @@ static void do_signal(struct pt_regs *regs)
         }
 
         /*
-         * If we came from a system call, handle the restart.
+         * No (more) signals; if we came from a system call, handle the restart.
          */
+
         if (regs->syscall_nr >= 0) {
                 switch (regs->r00) {
                 case -ERESTARTNOHAND:
@@ -234,17 +245,6 @@ no_restart:
         restore_saved_sigmask();
 }
 
-void do_notify_resume(struct pt_regs *regs, unsigned long thread_info_flags)
-{
-        if (thread_info_flags & _TIF_SIGPENDING)
-                do_signal(regs);
-
-        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
-                clear_thread_flag(TIF_NOTIFY_RESUME);
-                tracehook_notify_resume(regs);
-        }
-}
-
 /*
  * Architecture-specific wrappers for signal-related system calls
  */
@@ -272,21 +272,12 @@ asmlinkage int sys_rt_sigreturn(void)
         /* Restore the user's stack as well */
         pt_psp(regs) = regs->r29;
 
-        /*
-         * Leave a trace in the stack frame that this was a sigreturn.
-         * If the system call is to replay, we've already restored the
-         * number in the GPR slot and it will be regenerated on the
-         * new system call trap entry. Note that if restore_sigcontext()
-         * did something other than a bulk copy of the pt_regs struct,
-         * we could avoid this assignment by simply not overwriting
-         * regs->syscall_nr.
-         */
-        regs->syscall_nr = __NR_rt_sigreturn;
+        regs->syscall_nr = -1;
 
         if (restore_altstack(&frame->uc.uc_stack))
                 goto badframe;
 
-        return 0;
+        return regs->r00;
 
 badframe:
         force_sig(SIGSEGV, current);
diff --git a/arch/hexagon/kernel/smp.c b/arch/hexagon/kernel/smp.c
index 8e095dffd070..0e364ca43198 100644
--- a/arch/hexagon/kernel/smp.c
+++ b/arch/hexagon/kernel/smp.c
@@ -184,7 +184,7 @@ void __cpuinit start_secondary(void)
 
         local_irq_enable();
 
-        cpu_idle();
+        cpu_startup_entry(CPUHP_ONLINE);
 }
 
 
diff --git a/arch/hexagon/kernel/topology.c b/arch/hexagon/kernel/topology.c
deleted file mode 100644
index 352f27e809fd..000000000000
--- a/arch/hexagon/kernel/topology.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * CPU topology for Hexagon
- *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-
-#include <linux/cpu.h>
-#include <linux/cpumask.h>
-#include <linux/init.h>
-#include <linux/node.h>
-#include <linux/nodemask.h>
-#include <linux/percpu.h>
-
-/*  Swiped from MIPS.  */
-
-static DEFINE_PER_CPU(struct cpu, cpu_devices);
-
-static int __init topology_init(void)
-{
-        int i, ret;
-
-        for_each_present_cpu(i) {
-
-                /*
-                 * register_cpu takes a per_cpu pointer and
-                 * just points it at another per_cpu struct...
-                 */
-
-                ret = register_cpu(&per_cpu(cpu_devices, i), i);
-                if (ret)
-                        printk(KERN_WARNING "topology_init: register_cpu %d "
-                               "failed (%d)\n", i, ret);
-        }
-
-        return 0;
-}
-
-subsys_initcall(topology_init);
diff --git a/arch/hexagon/kernel/traps.c b/arch/hexagon/kernel/traps.c
index be5e2dd9c9d3..7858663352b9 100644
--- a/arch/hexagon/kernel/traps.c
+++ b/arch/hexagon/kernel/traps.c
@@ -1,7 +1,7 @@
 /*
  * Kernel traps/events for Hexagon processor
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -65,6 +65,10 @@ static const char *ex_name(int ex)
                 return "Write protection fault";
         case HVM_GE_C_XMAL:
                 return "Misaligned instruction";
+        case HVM_GE_C_WREG:
+                return "Multiple writes to same register in packet";
+        case HVM_GE_C_PCAL:
+                return "Program counter values that are not properly aligned";
         case HVM_GE_C_RMAL:
                 return "Misaligned data load";
         case HVM_GE_C_WMAL:
@@ -191,14 +195,6 @@ void show_stack(struct task_struct *task, unsigned long *fp)
         do_show_stack(task, fp, 0);
 }
 
-void dump_stack(void)
-{
-        unsigned long *fp;
-        asm("%0 = r30" : "=r" (fp));
-        show_stack(current, fp);
-}
-EXPORT_SYMBOL(dump_stack);
-
 int die(const char *str, struct pt_regs *regs, long err)
 {
         static struct {
@@ -324,6 +320,12 @@ void do_genex(struct pt_regs *regs)
         case HVM_GE_C_XMAL:
                 misaligned_instruction(regs);
                 break;
+        case HVM_GE_C_WREG:
+                illegal_instruction(regs);
+                break;
+        case HVM_GE_C_PCAL:
+                misaligned_instruction(regs);
+                break;
         case HVM_GE_C_RMAL:
                 misaligned_data_load(regs);
                 break;
@@ -356,7 +358,6 @@ long sys_syscall(void)
 
 void do_trap0(struct pt_regs *regs)
 {
-        unsigned long syscallret = 0;
         syscall_fn syscall;
 
         switch (pt_cause(regs)) {
@@ -396,21 +397,11 @@ void do_trap0(struct pt_regs *regs)
                 } else {
                         syscall = (syscall_fn)
                                   (sys_call_table[regs->syscall_nr]);
-                        syscallret = syscall(regs->r00, regs->r01,
+                        regs->r00 = syscall(regs->r00, regs->r01,
                                    regs->r02, regs->r03,
                                    regs->r04, regs->r05);
                 }
 
-                /*
-                 * If it was a sigreturn system call, don't overwrite
-                 * r0 value in stack frame with return value.
-                 *
-                 * __NR_sigreturn doesn't seem to exist in new unistd.h
-                 */
-
-                if (regs->syscall_nr != __NR_rt_sigreturn)
-                        regs->r00 = syscallret;
-
                 /* allow strace to get the syscall return state  */
                 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACE)))
                         tracehook_report_syscall_exit(regs, 0);
@@ -452,3 +443,14 @@ void do_machcheck(struct pt_regs *regs)
         /* Halt and catch fire */
         __vmstop();
 }
+
+/*
+ * Treat this like the old 0xdb trap.
+ */
+
+void do_debug_exception(struct pt_regs *regs)
+{
+        regs->hvmer.vmest &= ~HVM_VMEST_CAUSE_MSK;
+        regs->hvmer.vmest |= (TRAP_DEBUG << HVM_VMEST_CAUSE_SFT);
+        do_trap0(regs);
+}
diff --git a/arch/hexagon/kernel/vm_entry.S b/arch/hexagon/kernel/vm_entry.S
index 425e50c694f7..e3086185fc9f 100644
--- a/arch/hexagon/kernel/vm_entry.S
+++ b/arch/hexagon/kernel/vm_entry.S
@@ -1,7 +1,7 @@
 /*
  * Event entry/exit for Hexagon
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -45,48 +45,88 @@
  * number in the case where we decode a system call (trap0(#1)).
  */
 
+#if CONFIG_HEXAGON_ARCH_VERSION < 4
 #define save_pt_regs()\
-        memd(R0 + #_PT_R3130) = R31:30; \
+ memd(R0 + #_PT_R3130) = R31:30; \
+ { memw(R0 + #_PT_R2928) = R28; \
+   R31 = memw(R0 + #_PT_ER_VMPSP); }\
+ { memw(R0 + #(_PT_R2928 + 4)) = R31; \
+   R31 = ugp; } \
+ { memd(R0 + #_PT_R2726) = R27:26; \
+   R30 = gp ; } \
+ memd(R0 + #_PT_R2524) = R25:24; \
+ memd(R0 + #_PT_R2322) = R23:22; \
+ memd(R0 + #_PT_R2120) = R21:20; \
+ memd(R0 + #_PT_R1918) = R19:18; \
+ memd(R0 + #_PT_R1716) = R17:16; \
+ memd(R0 + #_PT_R1514) = R15:14; \
+ memd(R0 + #_PT_R1312) = R13:12; \
+ { memd(R0 + #_PT_R1110) = R11:10; \
+   R15 = lc0; } \
+ { memd(R0 + #_PT_R0908) = R9:8; \
+   R14 = sa0; } \
+ { memd(R0 + #_PT_R0706) = R7:6; \
+   R13 = lc1; } \
+ { memd(R0 + #_PT_R0504) = R5:4; \
+   R12 = sa1; } \
+ { memd(R0 + #_PT_GPUGP) = R31:30; \
+   R11 = m1; \
+   R2.H = #HI(_THREAD_SIZE); } \
+ { memd(R0 + #_PT_LC0SA0) = R15:14; \
+   R10 = m0; \
+   R2.L = #LO(_THREAD_SIZE); } \
+ { memd(R0 + #_PT_LC1SA1) = R13:12; \
+   R15 = p3:0; \
+   R2 = neg(R2); } \
+ { memd(R0 + #_PT_M1M0) = R11:10; \
+   R14  = usr; \
+   R2 = and(R0,R2); } \
+ { memd(R0 + #_PT_PREDSUSR) =  R15:14; \
+   THREADINFO_REG = R2; } \
+ { r24 = memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS); \
+   memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS) = R0; \
+   R2 = #-1; } \
+ { memw(R0 + #_PT_SYSCALL_NR) = R2; \
+   R30 = #0; }
+#else
+/* V4+ */
+/* the # ## # syntax inserts a literal ## */
+#define save_pt_regs()\
+        { memd(R0 + #_PT_R3130) = R31:30; \
+                R30 = memw(R0 + #_PT_ER_VMPSP); }\
         { memw(R0 + #_PT_R2928) = R28; \
-          R31 = memw(R0 + #_PT_ER_VMPSP); }\
-        { memw(R0 + #(_PT_R2928 + 4)) = R31; \
-          R31 = ugp; } \
-        { memd(R0 + #_PT_R2726) = R27:26; \
-          R30 = gp ; } \
-        memd(R0 + #_PT_R2524) = R25:24; \
-        memd(R0 + #_PT_R2322) = R23:22; \
-        memd(R0 + #_PT_R2120) = R21:20; \
-        memd(R0 + #_PT_R1918) = R19:18; \
-        memd(R0 + #_PT_R1716) = R17:16; \
-        memd(R0 + #_PT_R1514) = R15:14; \
-        memd(R0 + #_PT_R1312) = R13:12; \
+                memw(R0 + #(_PT_R2928 + 4)) = R30; }\
+        { R31:30 = C11:10; \
+                memd(R0 + #_PT_R2726) = R27:26; \
+                memd(R0 + #_PT_R2524) = R25:24; }\
+        { memd(R0 + #_PT_R2322) = R23:22; \
+                memd(R0 + #_PT_R2120) = R21:20; }\
+        { memd(R0 + #_PT_R1918) = R19:18; \
+                memd(R0 + #_PT_R1716) = R17:16; }\
+        { memd(R0 + #_PT_R1514) = R15:14; \
+                memd(R0 + #_PT_R1312) = R13:12; \
+                R17:16 = C13:12; }\
         { memd(R0 + #_PT_R1110) = R11:10; \
-          R15 = lc0; } \
-        { memd(R0 + #_PT_R0908) = R9:8; \
-          R14 = sa0; } \
+                memd(R0 + #_PT_R0908) = R9:8; \
+          R15:14 = C1:0; } \
         { memd(R0 + #_PT_R0706) = R7:6; \
-          R13 = lc1; } \
-        { memd(R0 + #_PT_R0504) = R5:4; \
-          R12 = sa1; } \
-        { memd(R0 + #_PT_UGPGP) = R31:30; \
-          R11 = m1; \
-          R2.H = #HI(_THREAD_SIZE); } \
-        { memd(R0 + #_PT_LC0SA0) = R15:14; \
-          R10 = m0; \
-          R2.L = #LO(_THREAD_SIZE); } \
-        { memd(R0 + #_PT_LC1SA1) = R13:12; \
-          R15 = p3:0; \
-          R2 = neg(R2); } \
+                memd(R0 + #_PT_R0504) = R5:4; \
+    R13:12 = C3:2; } \
+        { memd(R0 + #_PT_GPUGP) = R31:30; \
+                memd(R0 + #_PT_LC0SA0) = R15:14; \
+          R11:10 = C7:6; }\
+        {       THREADINFO_REG = and(R0, # ## #-_THREAD_SIZE); \
+                memd(R0 + #_PT_LC1SA1) = R13:12; \
+          R15 = p3:0; }\
         { memd(R0 + #_PT_M1M0) = R11:10; \
-          R14  = usr; \
-          R2 = and(R0,R2); } \
-        { memd(R0 + #_PT_PREDSUSR) =  R15:14; \
-          THREADINFO_REG = R2; } \
+                memw(R0 + #_PT_PREDSUSR + 4) =  R15; }\
         { r24 = memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS); \
           memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS) = R0; \
           R2 = #-1; } \
         { memw(R0 + #_PT_SYSCALL_NR) = R2; \
+                memd(R0 + #_PT_CS1CS0) = R17:16; \
           R30 = #0; }
+#endif
 
 /*
  * Restore registers and thread_info.regs state. THREADINFO_REG
@@ -94,6 +134,7 @@
  * preserved. Don't restore R29 (SP) until later.
  */
 
+#if CONFIG_HEXAGON_ARCH_VERSION < 4
 #define restore_pt_regs() \
         { memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS) = R24; \
           R15:14 = memd(R0 + #_PT_PREDSUSR); } \
@@ -121,11 +162,44 @@
           R23:22 = memd(R0 + #_PT_R2322); } \
         { R25:24 = memd(R0 + #_PT_R2524); \
           R27:26 = memd(R0 + #_PT_R2726); } \
-        R31:30 = memd(R0 + #_PT_UGPGP); \
+        R31:30 = memd(R0 + #_PT_GPUGP); \
         { R28 = memw(R0 + #_PT_R2928); \
           ugp = R31; } \
         { R31:30 = memd(R0 + #_PT_R3130); \
           gp = R30; }
+#else
+/* V4+ */
+#define restore_pt_regs() \
+        { memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS) = R24; \
+          R15:14 = memd(R0 + #_PT_PREDSUSR); } \
+        { R11:10 = memd(R0 + #_PT_M1M0); \
+                R13:12 = memd(R0 + #_PT_LC1SA1); \
+                p3:0 = R15; } \
+        { R15:14 = memd(R0 + #_PT_LC0SA0); \
+                R3:2 = memd(R0 + #_PT_R0302); \
+                usr = R14; } \
+        { R5:4 = memd(R0 + #_PT_R0504); \
+                R7:6 = memd(R0 + #_PT_R0706); \
+                C7:6 = R11:10; }\
+        { R9:8 = memd(R0 + #_PT_R0908); \
+                R11:10 = memd(R0 + #_PT_R1110); \
+    C3:2 = R13:12; }\
+        { R13:12 = memd(R0 + #_PT_R1312); \
+          R15:14 = memd(R0 + #_PT_R1514); \
+                C1:0 = R15:14; }\
+        { R17:16 = memd(R0 + #_PT_R1716); \
+          R19:18 = memd(R0 + #_PT_R1918); } \
+        { R21:20 = memd(R0 + #_PT_R2120); \
+          R23:22 = memd(R0 + #_PT_R2322); } \
+        { R25:24 = memd(R0 + #_PT_R2524); \
+          R27:26 = memd(R0 + #_PT_R2726); } \
+        R31:30 = memd(R0 + #_PT_CS1CS0); \
+        { C13:12 = R31:30; \
+                R31:30 = memd(R0 + #_PT_GPUGP) ; \
+                R28 = memw(R0 + #_PT_R2928); }\
+        { C11:10 = R31:30; \
+                R31:30 = memd(R0 + #_PT_R3130); }
+#endif
 
         /*
          * Clears off enough space for the rest of pt_regs; evrec is a part
@@ -139,6 +213,7 @@
  * Need to save off R0, R1, R2, R3 immediately.
  */
 
+#if CONFIG_HEXAGON_ARCH_VERSION < 4
 #define vm_event_entry(CHandler) \
         { \
                 R29 = add(R29, #-(_PT_REGS_SIZE)); \
@@ -158,6 +233,34 @@
                 R1.H = #HI(CHandler); \
                 jump event_dispatch; \
         }
+#else
+/* V4+ */
+/* turn on I$ prefetch early */
+/* the # ## # syntax inserts a literal ## */
+#define vm_event_entry(CHandler) \
+        { \
+                R29 = add(R29, #-(_PT_REGS_SIZE)); \
+                memd(R29 + #(_PT_R0100 + -_PT_REGS_SIZE)) = R1:0; \
+                memd(R29 + #(_PT_R0302 + -_PT_REGS_SIZE)) = R3:2; \
+                R0 = usr; \
+        } \
+        { \
+                memw(R29 + #_PT_PREDSUSR) = R0; \
+                R0 = setbit(R0, #16); \
+        } \
+        usr = R0; \
+        R1:0 = G1:0; \
+        { \
+                memd(R29 + #_PT_ER_VMEL) = R1:0; \
+                R1 = # ## #(CHandler); \
+                R3:2 = G3:2; \
+        } \
+        { \
+                R0 = R29; \
+                memd(R29 + #_PT_ER_VMPSP) = R3:2; \
+                jump event_dispatch; \
+        }
+#endif
 
 .text
         /*
@@ -171,6 +274,9 @@ event_dispatch:
         callr   r1
 
         /*
+         * Coming back from the C-world, our thread info pointer
+         * should be in the designated register (usually R19)
+         *
          * If we were in kernel mode, we don't need to check scheduler
          * or signals if CONFIG_PREEMPT is not set.  If set, then it has
          * to jump to a need_resched kind of block.
@@ -183,69 +289,68 @@ event_dispatch:
 #endif
 
         /*  "Nested control path" -- if the previous mode was kernel  */
-        R0 = memw(R29 + #_PT_ER_VMEST);
-        P0 = tstbit(R0, #HVM_VMEST_UM_SFT);
-        if !P0 jump restore_all;
-        /*
-         * Returning from system call, normally coming back from user mode
-         */
-return_from_syscall:
-        /*  Disable interrupts while checking TIF  */
-        R0 = #VM_INT_DISABLE
-        trap1(#HVM_TRAP1_VMSETIE)
-
-        /*
-         * Coming back from the C-world, our thread info pointer
-         * should be in the designated register (usually R19)
-         */
-        R1.L = #LO(_TIF_ALLWORK_MASK)
         {
-                R1.H = #HI(_TIF_ALLWORK_MASK);
-                R0 = memw(THREADINFO_REG + #_THREAD_INFO_FLAGS);
+                R0 = memw(R29 + #_PT_ER_VMEST);
+                R16.L = #LO(do_work_pending);
+        }
+        {
+                P0 = tstbit(R0, #HVM_VMEST_UM_SFT);
+                if (!P0.new) jump:nt restore_all;
+                R16.H = #HI(do_work_pending);
+                R0 = #VM_INT_DISABLE;
         }
 
         /*
-         * Compare against the "return to userspace" _TIF_WORK_MASK
+         * Check also the return from fork/system call, normally coming back from
+         * user mode
+         *
+         * R16 needs to have do_work_pending, and R0 should have VM_INT_DISABLE
          */
-        R1 = and(R1,R0);
-        { P0 = cmp.eq(R1,#0); if (!P0.new) jump:t work_pending;}
-        jump restore_all;  /*  we're outta here!  */
 
-work_pending:
+check_work_pending:
+        /*  Disable interrupts while checking TIF  */
+        trap1(#HVM_TRAP1_VMSETIE)
         {
-                P0 = tstbit(R1, #TIF_NEED_RESCHED);
-                if (!P0.new) jump:nt work_notifysig;
+                R0 = R29;  /*  regs should still be at top of stack  */
+                R1 = memw(THREADINFO_REG + #_THREAD_INFO_FLAGS);
+                callr R16;
         }
-        call schedule
-        jump return_from_syscall;  /*  check for more work  */
 
-work_notifysig:
-        /*  this is the part that's kind of fuzzy.  */
-        R1 = and(R0, #(_TIF_SIGPENDING | _TIF_NOTIFY_RESUME));
-        P0 = cmp.eq(R1, #0);
-        if P0 jump restore_all
-        R1 = R0;        /* unsigned long thread_info_flags */
-        R0 = R29;       /* regs should still be at top of stack  */
-        call do_notify_resume
+        {
+                P0 = cmp.eq(R0, #0); if (!P0.new) jump:nt check_work_pending;
+                R0 = #VM_INT_DISABLE;
+        }
 
 restore_all:
-        /* Disable interrupts, if they weren't already, before reg restore.  */
-        R0 = #VM_INT_DISABLE
+        /*
+         * Disable interrupts, if they weren't already, before reg restore.
+         * R0 gets preloaded with #VM_INT_DISABLE before we get here.
+         */
         trap1(#HVM_TRAP1_VMSETIE)
 
         /*  do the setregs here for VM 0.5  */
         /*  R29 here should already be pointing at pt_regs  */
-        R1:0 = memd(R29 + #_PT_ER_VMEL);
-        R3:2 = memd(R29 + #_PT_ER_VMPSP);
+        {
+                R1:0 = memd(R29 + #_PT_ER_VMEL);
+                R3:2 = memd(R29 + #_PT_ER_VMPSP);
+        }
+#if CONFIG_HEXAGON_ARCH_VERSION < 4
         trap1(#HVM_TRAP1_VMSETREGS);
+#else
+        G1:0 = R1:0;
+        G3:2 = R3:2;
+#endif
 
         R0 = R29
         restore_pt_regs()
-        R1:0 = memd(R29 + #_PT_R0100);
-        R29 = add(R29, #_PT_REGS_SIZE);
+        {
+                R1:0 = memd(R29 + #_PT_R0100);
+                R29 = add(R29, #_PT_REGS_SIZE);
+        }
         trap1(#HVM_TRAP1_VMRTE)
         /* Notreached */
 
+
         .globl _K_enter_genex
 _K_enter_genex:
         vm_event_entry(do_genex)
@@ -262,12 +367,27 @@ _K_enter_trap0:
 _K_enter_machcheck:
         vm_event_entry(do_machcheck)
 
+        .globl _K_enter_debug
+_K_enter_debug:
+        vm_event_entry(do_debug_exception)
 
         .globl ret_from_fork
 ret_from_fork:
-        call schedule_tail
-        P0 = cmp.eq(R24, #0);
-        if P0 jump return_from_syscall
-        R0 = R25;
-        callr R24
-        jump return_from_syscall
+        {
+                call schedule_tail
+                R16.H = #HI(do_work_pending);
+        }
+        {
+                P0 = cmp.eq(R24, #0);
+                R16.L = #LO(do_work_pending);
+                R0 = #VM_INT_DISABLE;
+        }
+        if P0 jump check_work_pending
+        {
+                R0 = R25;
+                callr R24
+        }
+        {
+                jump check_work_pending
+                R0 = #VM_INT_DISABLE;
+        }
diff --git a/arch/hexagon/kernel/vm_events.c b/arch/hexagon/kernel/vm_events.c
index 9b5a4a295a68..741aaa917cda 100644
--- a/arch/hexagon/kernel/vm_events.c
+++ b/arch/hexagon/kernel/vm_events.c
@@ -1,7 +1,7 @@
 /*
  * Mostly IRQ support for Hexagon
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -33,6 +33,8 @@
  */
 void show_regs(struct pt_regs *regs)
 {
+        show_regs_print_info(KERN_EMERG);
+
         printk(KERN_EMERG "restart_r0: \t0x%08lx   syscall_nr: %ld\n",
                regs->restart_r0, regs->syscall_nr);
         printk(KERN_EMERG "preds: \t\t0x%08lx\n", regs->preds);
@@ -42,6 +44,8 @@ void show_regs(struct pt_regs *regs)
                regs->lc1, regs->sa1, regs->m1);
         printk(KERN_EMERG "gp: \t0x%08lx   ugp: 0x%08lx   usr: 0x%08lx\n",
                regs->gp, regs->ugp, regs->usr);
+        printk(KERN_EMERG "cs0: \t0x%08lx   cs1: 0x%08lx\n",
+               regs->cs0, regs->cs1);
         printk(KERN_EMERG "r0: \t0x%08lx %08lx %08lx %08lx\n", regs->r00,
                 regs->r01,
                 regs->r02,
diff --git a/arch/hexagon/kernel/vm_vectors.S b/arch/hexagon/kernel/vm_vectors.S
index 620f42cc582a..791a7422dde4 100644
--- a/arch/hexagon/kernel/vm_vectors.S
+++ b/arch/hexagon/kernel/vm_vectors.S
@@ -1,7 +1,7 @@
 /*
  * Event jump tables
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2012,2013, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -41,7 +41,7 @@ _K_VM_event_vector:
         jump 1b;  /*  Reset  */
         jump _K_enter_machcheck;
         jump _K_enter_genex;
-        jump 1b;  /*  3 Rsvd  */
+        jump _K_enter_debug;
         jump 1b;  /*  4 Rsvd  */
         jump _K_enter_trap0;
         jump 1b;  /*  6 Rsvd  */
diff --git a/arch/hexagon/kernel/vmlinux.lds.S b/arch/hexagon/kernel/vmlinux.lds.S
index 14e793f6abbf..44d8c47bae2f 100644
--- a/arch/hexagon/kernel/vmlinux.lds.S
+++ b/arch/hexagon/kernel/vmlinux.lds.S
@@ -1,7 +1,7 @@
 /*
  * Linker script for Hexagon kernel
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -18,8 +18,6 @@
  * 02110-1301, USA.
  */
 
-#define LOAD_OFFSET PAGE_OFFSET
-
 #include <asm-generic/vmlinux.lds.h>
 #include <asm/asm-offsets.h>    /*  Most of the kernel defines are here  */
 #include <asm/mem-layout.h>     /*  except for page_offset  */
@@ -36,13 +34,9 @@ See asm-generic/sections.h for seemingly required labels.
 
 #define PAGE_SIZE _PAGE_SIZE
 
-/*  This LOAD_OFFSET is temporary for debugging on the simulator; it may change
-    for hypervisor pseudo-physical memory.  */
-
-
 SECTIONS
 {
-        . = PAGE_OFFSET + LOAD_ADDRESS;
+        . = PAGE_OFFSET;
 
         __init_begin = .;
         HEAD_TEXT_SECTION
@@ -52,7 +46,7 @@ SECTIONS
 
         . = ALIGN(_PAGE_SIZE);
         _stext = .;
-        .text : AT(ADDR(.text) - LOAD_OFFSET) {
+        .text : AT(ADDR(.text)) {
                 _text = .;
                 TEXT_TEXT
                 SCHED_TEXT
diff --git a/arch/hexagon/mm/init.c b/arch/hexagon/mm/init.c
index 69ffcfd28794..2561d259a296 100644
--- a/arch/hexagon/mm/init.c
+++ b/arch/hexagon/mm/init.c
@@ -1,7 +1,7 @@
 /*
  * Memory subsystem initialization for Hexagon
  *
- * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -31,9 +31,10 @@
  * Define a startpg just past the end of the kernel image and a lastpg
  * that corresponds to the end of real or simulated platform memory.
  */
-#define bootmem_startpg (PFN_UP(((unsigned long) _end) - PAGE_OFFSET))
+#define bootmem_startpg (PFN_UP(((unsigned long) _end) - PAGE_OFFSET + PHYS_OFFSET))
 
-unsigned long bootmem_lastpg;  /*  Should be set by platform code  */
+unsigned long bootmem_lastpg;   /*  Should be set by platform code  */
+unsigned long __phys_offset;    /*  physical kernel offset >> 12  */
 
 /*  Set as variable to limit PMD copies  */
 int max_kernel_seg = 0x303;
@@ -44,7 +45,6 @@ unsigned long zero_page_mask;
 /*  indicate pfn's of high memory  */
 unsigned long highstart_pfn, highend_pfn;
 
-/* struct mmu_gather defined in asm-generic.h;  */
 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
 
 /* Default cache attribute for newly created page tables */
@@ -71,7 +71,7 @@ void __init mem_init(void)
 {
         /*  No idea where this is actually declared.  Seems to evade LXR.  */
         totalram_pages += free_all_bootmem();
-        num_physpages = bootmem_lastpg; /*  seriously, what?  */
+        num_physpages = bootmem_lastpg-ARCH_PFN_OFFSET;
 
         printk(KERN_INFO "totalram_pages = %ld\n", totalram_pages);
 
@@ -193,6 +193,9 @@ void __init setup_arch_memory(void)
          * This needs to change for highmem setups.
          */
 
+        /*  Prior to this, bootmem_lastpg is actually mem size  */
+        bootmem_lastpg += ARCH_PFN_OFFSET;
+
         /* Memory size needs to be a multiple of 16M */
         bootmem_lastpg = PFN_DOWN((bootmem_lastpg << PAGE_SHIFT) &
                 ~((BIG_KERNEL_PAGE_SIZE) - 1));
@@ -201,12 +204,15 @@ void __init setup_arch_memory(void)
          * Reserve the top DMA_RESERVE bytes of RAM for DMA (uncached)
          * memory allocation
          */
-        bootmap_size = init_bootmem(bootmem_startpg, bootmem_lastpg -
-                                    PFN_DOWN(DMA_RESERVED_BYTES));
+
+        max_low_pfn = bootmem_lastpg - PFN_DOWN(DMA_RESERVED_BYTES);
+        min_low_pfn = ARCH_PFN_OFFSET;
+        bootmap_size =  init_bootmem_node(NODE_DATA(0), bootmem_startpg, min_low_pfn, max_low_pfn);
 
         printk(KERN_INFO "bootmem_startpg:  0x%08lx\n", bootmem_startpg);
         printk(KERN_INFO "bootmem_lastpg:  0x%08lx\n", bootmem_lastpg);
         printk(KERN_INFO "bootmap_size:  %d\n", bootmap_size);
+        printk(KERN_INFO "min_low_pfn:  0x%08lx\n", min_low_pfn);
         printk(KERN_INFO "max_low_pfn:  0x%08lx\n", max_low_pfn);
 
         /*
@@ -221,14 +227,17 @@ void __init setup_arch_memory(void)
         /*  this actually only goes to the end of the first gig  */
         segtable_end = segtable + (1<<(30-22));
 
-        /*  Move forward to the start of empty pages  */
-        segtable += bootmem_lastpg >> (22-PAGE_SHIFT);
+        /*
+         * Move forward to the start of empty pages; take into account
+         * phys_offset shift.
+         */
 
+        segtable += (bootmem_lastpg-ARCH_PFN_OFFSET)>>(22-PAGE_SHIFT);
         {
-            int i;
+                int i;
 
-            for (i = 1 ; i <= DMA_RESERVE ; i++)
-                segtable[-i] = ((segtable[-i] & __HVM_PTE_PGMASK_4MB)
+                for (i = 1 ; i <= DMA_RESERVE ; i++)
+                        segtable[-i] = ((segtable[-i] & __HVM_PTE_PGMASK_4MB)
                                 | __HVM_PTE_R | __HVM_PTE_W | __HVM_PTE_X
                                 | __HEXAGON_C_UNC << 6
                                 | __HVM_PDE_S_4MB);
@@ -256,7 +265,7 @@ void __init setup_arch_memory(void)
          * Free all the memory that wasn't taken up by the bootmap, the DMA
          * reserve, or kernel itself.
          */
-        free_bootmem(PFN_PHYS(bootmem_startpg)+bootmap_size,
+        free_bootmem(PFN_PHYS(bootmem_startpg) + bootmap_size,
                      PFN_PHYS(bootmem_lastpg - bootmem_startpg) - bootmap_size -
                      DMA_RESERVED_BYTES);
 
diff --git a/arch/hexagon/mm/vm_fault.c b/arch/hexagon/mm/vm_fault.c
index 308ef0ce648b..1bd276dbec7d 100644
--- a/arch/hexagon/mm/vm_fault.c
+++ b/arch/hexagon/mm/vm_fault.c
@@ -147,7 +147,7 @@ good_area:
         }
         info.si_errno = 0;
         info.si_addr = (void __user *)address;
-        force_sig_info(info.si_code, &info, current);
+        force_sig_info(info.si_signo, &info, current);
         return;
 
 bad_area:
@@ -158,7 +158,7 @@ bad_area:
                 info.si_errno = 0;
                 info.si_code = si_code;
                 info.si_addr = (void *)address;
-                force_sig_info(SIGSEGV, &info, current);
+                force_sig_info(info.si_signo, &info, current);
                 return;
         }
         /* Kernel-mode fault falls through */
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 9a02f71c6b1f..d393f841ff5a 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -110,6 +110,7 @@ config DMI
 
 config EFI
         bool
+        select UCS2_STRING
         default y
 
 config SCHED_OMIT_FRAME_POINTER
@@ -187,7 +188,7 @@ config IA64_DIG
 
 config IA64_DIG_VTD
         bool "DIG+Intel+IOMMU"
-        select DMAR
+        select INTEL_IOMMU
         select PCI_MSI
 
 config IA64_HP_ZX1
@@ -591,9 +592,9 @@ source "kernel/power/Kconfig"
 source "drivers/acpi/Kconfig"
 
 if PM
-
-source "arch/ia64/kernel/cpufreq/Kconfig"
-
+menu "CPU Frequency scaling"
+source "drivers/cpufreq/Kconfig"
+endmenu
 endif
 
 endmenu
diff --git a/arch/ia64/hp/sim/simserial.c b/arch/ia64/hp/sim/simserial.c
index da2f319fb71d..e70cadec7ce6 100644
--- a/arch/ia64/hp/sim/simserial.c
+++ b/arch/ia64/hp/sim/simserial.c
@@ -142,8 +142,7 @@ static void transmit_chars(struct tty_struct *tty, struct serial_state *info,
                 goto out;
         }
 
-        if (info->xmit.head == info->xmit.tail || tty->stopped ||
-                        tty->hw_stopped) {
+        if (info->xmit.head == info->xmit.tail || tty->stopped) {
 #ifdef SIMSERIAL_DEBUG
                 printk("transmit_chars: head=%d, tail=%d, stopped=%d\n",
                        info->xmit.head, info->xmit.tail, tty->stopped);
@@ -181,7 +180,7 @@ static void rs_flush_chars(struct tty_struct *tty)
         struct serial_state *info = tty->driver_data;
 
         if (info->xmit.head == info->xmit.tail || tty->stopped ||
-                        tty->hw_stopped || !info->xmit.buf)
+                        !info->xmit.buf)
                 return;
 
         transmit_chars(tty, info, NULL);
@@ -217,7 +216,7 @@ static int rs_write(struct tty_struct * tty,
          * Hey, we transmit directly from here in our case
          */
         if (CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE) &&
-                        !tty->stopped && !tty->hw_stopped)
+                        !tty->stopped)
                 transmit_chars(tty, info, NULL);
 
         return ret;
@@ -325,14 +324,6 @@ static int rs_ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg)
 
 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
 
-static void rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
-{
-        /* Handle turning off CRTSCTS */
-        if ((old_termios->c_cflag & CRTSCTS) &&
-            !(tty->termios.c_cflag & CRTSCTS)) {
-                tty->hw_stopped = 0;
-        }
-}
 /*
  * This routine will shutdown a serial port; interrupts are disabled, and
  * DTR is dropped if the hangup on close termio flag is on.
@@ -481,7 +472,6 @@ static const struct tty_operations hp_ops = {
         .throttle = rs_throttle,
         .unthrottle = rs_unthrottle,
         .send_xchar = rs_send_xchar,
-        .set_termios = rs_set_termios,
         .hangup = rs_hangup,
         .proc_fops = &rs_proc_fops,
 };
diff --git a/arch/ia64/include/asm/futex.h b/arch/ia64/include/asm/futex.h
index d2bf1fd5e44f..76acbcd5c060 100644
--- a/arch/ia64/include/asm/futex.h
+++ b/arch/ia64/include/asm/futex.h
@@ -106,16 +106,15 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
                 return -EFAULT;
 
         {
-                register unsigned long r8 __asm ("r8");
+                register unsigned long r8 __asm ("r8") = 0;
                 unsigned long prev;
                 __asm__ __volatile__(
                         "       mf;;                                    \n"
-                        "       mov %0=r0                               \n"
                         "       mov ar.ccv=%4;;                         \n"
                         "[1:]   cmpxchg4.acq %1=[%2],%3,ar.ccv          \n"
                         "       .xdata4 \"__ex_table\", 1b-., 2f-.      \n"
                         "[2:]"
-                        : "=r" (r8), "=r" (prev)
+                        : "+r" (r8), "=&r" (prev)
                         : "r" (uaddr), "r" (newval),
                           "rO" ((long) (unsigned) oldval)
                         : "memory");
diff --git a/arch/ia64/include/asm/hugetlb.h b/arch/ia64/include/asm/hugetlb.h
index 94eaa5bd5d0c..aa910054b8e7 100644
--- a/arch/ia64/include/asm/hugetlb.h
+++ b/arch/ia64/include/asm/hugetlb.h
@@ -2,6 +2,7 @@
 #define _ASM_IA64_HUGETLB_H
 
 #include <asm/page.h>
+#include <asm-generic/hugetlb.h>
 
 
 void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,
diff --git a/arch/ia64/include/asm/irqflags.h b/arch/ia64/include/asm/irqflags.h
index 2b68d856dc78..1bf2cf2f4ab4 100644
--- a/arch/ia64/include/asm/irqflags.h
+++ b/arch/ia64/include/asm/irqflags.h
@@ -89,6 +89,7 @@ static inline bool arch_irqs_disabled(void)
 
 static inline void arch_safe_halt(void)
 {
+        arch_local_irq_enable();
         ia64_pal_halt_light();  /* PAL_HALT_LIGHT */
 }
 
diff --git a/arch/ia64/include/asm/kvm_host.h b/arch/ia64/include/asm/kvm_host.h
index cfa74983c675..989dd3fe8de1 100644
--- a/arch/ia64/include/asm/kvm_host.h
+++ b/arch/ia64/include/asm/kvm_host.h
@@ -26,6 +26,7 @@
 #define KVM_USER_MEM_SLOTS 32
 
 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
+#define KVM_IRQCHIP_NUM_PINS  KVM_IOAPIC_NUM_PINS
 
 /* define exit reasons from vmm to kvm*/
 #define EXIT_REASON_VM_PANIC            0
diff --git a/arch/ia64/include/asm/linkage.h b/arch/ia64/include/asm/linkage.h
index ef22a45c1890..787575701f1c 100644
--- a/arch/ia64/include/asm/linkage.h
+++ b/arch/ia64/include/asm/linkage.h
@@ -11,4 +11,8 @@
 
 #endif
 
+#define cond_syscall(x) asm(".weak\t" #x "#\n" #x "#\t=\tsys_ni_syscall#")
+#define SYSCALL_ALIAS(alias, name)                                      \
+        asm ( #alias "# = " #name "#\n\t.globl " #alias "#")
+
 #endif
diff --git a/arch/ia64/include/asm/mca.h b/arch/ia64/include/asm/mca.h
index 43f96ab18fa0..8c7096168716 100644
--- a/arch/ia64/include/asm/mca.h
+++ b/arch/ia64/include/asm/mca.h
@@ -143,6 +143,7 @@ extern unsigned long __per_cpu_mca[NR_CPUS];
 extern int cpe_vector;
 extern int ia64_cpe_irq;
 extern void ia64_mca_init(void);
+extern void ia64_mca_irq_init(void);
 extern void ia64_mca_cpu_init(void *);
 extern void ia64_os_mca_dispatch(void);
 extern void ia64_os_mca_dispatch_end(void);
diff --git a/arch/ia64/include/asm/numa.h b/arch/ia64/include/asm/numa.h
index 2e27ef175652..2db0a6c6daa5 100644
--- a/arch/ia64/include/asm/numa.h
+++ b/arch/ia64/include/asm/numa.h
@@ -67,14 +67,13 @@ extern int paddr_to_nid(unsigned long paddr);
 
 extern void map_cpu_to_node(int cpu, int nid);
 extern void unmap_cpu_from_node(int cpu, int nid);
-
+extern void numa_clear_node(int cpu);
 
 #else /* !CONFIG_NUMA */
 #define map_cpu_to_node(cpu, nid)       do{}while(0)
 #define unmap_cpu_from_node(cpu, nid)   do{}while(0)
-
 #define paddr_to_nid(addr)      0
-
+#define numa_clear_node(cpu)    do { } while (0)
 #endif /* CONFIG_NUMA */
 
 #endif /* _ASM_IA64_NUMA_H */
diff --git a/arch/ia64/include/asm/thread_info.h b/arch/ia64/include/asm/thread_info.h
index 020d655ed082..cade13dd0299 100644
--- a/arch/ia64/include/asm/thread_info.h
+++ b/arch/ia64/include/asm/thread_info.h
@@ -131,8 +131,6 @@ struct thread_info {
 #define TS_POLLING              1       /* true if in idle loop and not sleeping */
 #define TS_RESTORE_SIGMASK      2       /* restore signal mask in do_signal() */
 
-#define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING)
-
 #ifndef __ASSEMBLY__
 #define HAVE_SET_RESTORE_SIGMASK        1
 static inline void set_restore_sigmask(void)
diff --git a/arch/ia64/include/asm/unistd.h b/arch/ia64/include/asm/unistd.h
index 096373800f73..afd45e0d552e 100644
--- a/arch/ia64/include/asm/unistd.h
+++ b/arch/ia64/include/asm/unistd.h
@@ -46,15 +46,5 @@ asmlinkage unsigned long sys_mmap2(
 struct pt_regs;
 asmlinkage long sys_ia64_pipe(void);
 
-/*
- * "Conditional" syscalls
- *
- * Note, this macro can only be used in the file which defines sys_ni_syscall, i.e., in
- * kernel/sys_ni.c.  This version causes warnings because the declaration isn't a
- * proper prototype, but we can't use __typeof__ either, because not all cond_syscall()
- * declarations have prototypes at the moment.
- */
-#define cond_syscall(x) asmlinkage long x (void) __attribute__((weak,alias("sys_ni_syscall")))
-
 #endif /* !__ASSEMBLY__ */
 #endif /* _ASM_IA64_UNISTD_H */
diff --git a/arch/ia64/include/uapi/asm/kvm.h b/arch/ia64/include/uapi/asm/kvm.h
index ec6c6b301238..99503c284400 100644
--- a/arch/ia64/include/uapi/asm/kvm.h
+++ b/arch/ia64/include/uapi/asm/kvm.h
@@ -27,7 +27,6 @@
 /* Select x86 specific features in <linux/kvm.h> */
 #define __KVM_HAVE_IOAPIC
 #define __KVM_HAVE_IRQ_LINE
-#define __KVM_HAVE_DEVICE_ASSIGNMENT
 
 /* Architectural interrupt line count. */
 #define KVM_NR_INTERRUPTS 256
diff --git a/arch/ia64/kernel/Makefile b/arch/ia64/kernel/Makefile
index d959c84904be..20678a9ed11a 100644
--- a/arch/ia64/kernel/Makefile
+++ b/arch/ia64/kernel/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_SMP)		+= smp.o smpboot.o
 obj-$(CONFIG_NUMA)              += numa.o
 obj-$(CONFIG_PERFMON)           += perfmon_default_smpl.o
 obj-$(CONFIG_IA64_CYCLONE)      += cyclone.o
-obj-$(CONFIG_CPU_FREQ)          += cpufreq/
 obj-$(CONFIG_IA64_MCA_RECOVERY) += mca_recovery.o
 obj-$(CONFIG_KPROBES)           += kprobes.o jprobes.o
 obj-$(CONFIG_DYNAMIC_FTRACE)    += ftrace.o
diff --git a/arch/ia64/kernel/cpufreq/Kconfig b/arch/ia64/kernel/cpufreq/Kconfig
deleted file mode 100644
index 2d9d5279b981..000000000000
--- a/arch/ia64/kernel/cpufreq/Kconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-
-#
-# CPU Frequency scaling
-#
-
-menu "CPU Frequency scaling"
-
-source "drivers/cpufreq/Kconfig"
-
-if CPU_FREQ
-
-comment "CPUFreq processor drivers"
-
-config IA64_ACPI_CPUFREQ
-        tristate "ACPI Processor P-States driver"
-        select CPU_FREQ_TABLE
-        depends on ACPI_PROCESSOR
-        help
-        This driver adds a CPUFreq driver which utilizes the ACPI
-        Processor Performance States.
-
-        For details, take a look at <file:Documentation/cpu-freq/>.
-
-        If in doubt, say N.
-
-endif   # CPU_FREQ
-
-endmenu
-
diff --git a/arch/ia64/kernel/cpufreq/Makefile b/arch/ia64/kernel/cpufreq/Makefile
deleted file mode 100644
index 4838f2a57c7a..000000000000
--- a/arch/ia64/kernel/cpufreq/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-obj-$(CONFIG_IA64_ACPI_CPUFREQ)         += acpi-cpufreq.o
-
diff --git a/arch/ia64/kernel/cpufreq/acpi-cpufreq.c b/arch/ia64/kernel/cpufreq/acpi-cpufreq.c
deleted file mode 100644
index f09b174244d5..000000000000
--- a/arch/ia64/kernel/cpufreq/acpi-cpufreq.c
+++ /dev/null
@@ -1,437 +0,0 @@
-/*
- * arch/ia64/kernel/cpufreq/acpi-cpufreq.c
- * This file provides the ACPI based P-state support. This
- * module works with generic cpufreq infrastructure. Most of
- * the code is based on i386 version
- * (arch/i386/kernel/cpu/cpufreq/acpi-cpufreq.c)
- *
- * Copyright (C) 2005 Intel Corp
- *      Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/cpufreq.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <asm/io.h>
-#include <asm/uaccess.h>
-#include <asm/pal.h>
-
-#include <linux/acpi.h>
-#include <acpi/processor.h>
-
-MODULE_AUTHOR("Venkatesh Pallipadi");
-MODULE_DESCRIPTION("ACPI Processor P-States Driver");
-MODULE_LICENSE("GPL");
-
-
-struct cpufreq_acpi_io {
-        struct acpi_processor_performance       acpi_data;
-        struct cpufreq_frequency_table          *freq_table;
-        unsigned int                            resume;
-};
-
-static struct cpufreq_acpi_io   *acpi_io_data[NR_CPUS];
-
-static struct cpufreq_driver acpi_cpufreq_driver;
-
-
-static int
-processor_set_pstate (
-        u32     value)
-{
-        s64 retval;
-
-        pr_debug("processor_set_pstate\n");
-
-        retval = ia64_pal_set_pstate((u64)value);
-
-        if (retval) {
-                pr_debug("Failed to set freq to 0x%x, with error 0x%lx\n",
-                        value, retval);
-                return -ENODEV;
-        }
-        return (int)retval;
-}
-
-
-static int
-processor_get_pstate (
-        u32     *value)
-{
-        u64     pstate_index = 0;
-        s64     retval;
-
-        pr_debug("processor_get_pstate\n");
-
-        retval = ia64_pal_get_pstate(&pstate_index,
-                                     PAL_GET_PSTATE_TYPE_INSTANT);
-        *value = (u32) pstate_index;
-
-        if (retval)
-                pr_debug("Failed to get current freq with "
-                        "error 0x%lx, idx 0x%x\n", retval, *value);
-
-        return (int)retval;
-}
-
-
-/* To be used only after data->acpi_data is initialized */
-static unsigned
-extract_clock (
-        struct cpufreq_acpi_io *data,
-        unsigned value,
-        unsigned int cpu)
-{
-        unsigned long i;
-
-        pr_debug("extract_clock\n");
-
-        for (i = 0; i < data->acpi_data.state_count; i++) {
-                if (value == data->acpi_data.states[i].status)
-                        return data->acpi_data.states[i].core_frequency;
-        }
-        return data->acpi_data.states[i-1].core_frequency;
-}
-
-
-static unsigned int
-processor_get_freq (
-        struct cpufreq_acpi_io  *data,
-        unsigned int            cpu)
-{
-        int                     ret = 0;
-        u32                     value = 0;
-        cpumask_t               saved_mask;
-        unsigned long           clock_freq;
-
-        pr_debug("processor_get_freq\n");
-
-        saved_mask = current->cpus_allowed;
-        set_cpus_allowed_ptr(current, cpumask_of(cpu));
-        if (smp_processor_id() != cpu)
-                goto migrate_end;
-
-        /* processor_get_pstate gets the instantaneous frequency */
-        ret = processor_get_pstate(&value);
-
-        if (ret) {
-                set_cpus_allowed_ptr(current, &saved_mask);
-                printk(KERN_WARNING "get performance failed with error %d\n",
-                       ret);
-                ret = 0;
-                goto migrate_end;
-        }
-        clock_freq = extract_clock(data, value, cpu);
-        ret = (clock_freq*1000);
-
-migrate_end:
-        set_cpus_allowed_ptr(current, &saved_mask);
-        return ret;
-}
-
-
-static int
-processor_set_freq (
-        struct cpufreq_acpi_io  *data,
-        unsigned int            cpu,
-        int                     state)
-{
-        int                     ret = 0;
-        u32                     value = 0;
-        struct cpufreq_freqs    cpufreq_freqs;
-        cpumask_t               saved_mask;
-        int                     retval;
-
-        pr_debug("processor_set_freq\n");
-
-        saved_mask = current->cpus_allowed;
-        set_cpus_allowed_ptr(current, cpumask_of(cpu));
-        if (smp_processor_id() != cpu) {
-                retval = -EAGAIN;
-                goto migrate_end;
-        }
-
-        if (state == data->acpi_data.state) {
-                if (unlikely(data->resume)) {
-                        pr_debug("Called after resume, resetting to P%d\n", state);
-                        data->resume = 0;
-                } else {
-                        pr_debug("Already at target state (P%d)\n", state);
-                        retval = 0;
-                        goto migrate_end;
-                }
-        }
-
-        pr_debug("Transitioning from P%d to P%d\n",
-                data->acpi_data.state, state);
-
-        /* cpufreq frequency struct */
-        cpufreq_freqs.cpu = cpu;
-        cpufreq_freqs.old = data->freq_table[data->acpi_data.state].frequency;
-        cpufreq_freqs.new = data->freq_table[state].frequency;
-
-        /* notify cpufreq */
-        cpufreq_notify_transition(&cpufreq_freqs, CPUFREQ_PRECHANGE);
-
-        /*
-         * First we write the target state's 'control' value to the
-         * control_register.
-         */
-
-        value = (u32) data->acpi_data.states[state].control;
-
-        pr_debug("Transitioning to state: 0x%08x\n", value);
-
-        ret = processor_set_pstate(value);
-        if (ret) {
-                unsigned int tmp = cpufreq_freqs.new;
-                cpufreq_notify_transition(&cpufreq_freqs, CPUFREQ_POSTCHANGE);
-                cpufreq_freqs.new = cpufreq_freqs.old;
-                cpufreq_freqs.old = tmp;
-                cpufreq_notify_transition(&cpufreq_freqs, CPUFREQ_PRECHANGE);
-                cpufreq_notify_transition(&cpufreq_freqs, CPUFREQ_POSTCHANGE);
-                printk(KERN_WARNING "Transition failed with error %d\n", ret);
-                retval = -ENODEV;
-                goto migrate_end;
-        }
-
-        cpufreq_notify_transition(&cpufreq_freqs, CPUFREQ_POSTCHANGE);
-
-        data->acpi_data.state = state;
-
-        retval = 0;
-
-migrate_end:
-        set_cpus_allowed_ptr(current, &saved_mask);
-        return (retval);
-}
-
-
-static unsigned int
-acpi_cpufreq_get (
-        unsigned int            cpu)
-{
-        struct cpufreq_acpi_io *data = acpi_io_data[cpu];
-
-        pr_debug("acpi_cpufreq_get\n");
-
-        return processor_get_freq(data, cpu);
-}
-
-
-static int
-acpi_cpufreq_target (
-        struct cpufreq_policy   *policy,
-        unsigned int target_freq,
-        unsigned int relation)
-{
-        struct cpufreq_acpi_io *data = acpi_io_data[policy->cpu];
-        unsigned int next_state = 0;
-        unsigned int result = 0;
-
-        pr_debug("acpi_cpufreq_setpolicy\n");
-
-        result = cpufreq_frequency_table_target(policy,
-                        data->freq_table, target_freq, relation, &next_state);
-        if (result)
-                return (result);
-
-        result = processor_set_freq(data, policy->cpu, next_state);
-
-        return (result);
-}
-
-
-static int
-acpi_cpufreq_verify (
-        struct cpufreq_policy   *policy)
-{
-        unsigned int result = 0;
-        struct cpufreq_acpi_io *data = acpi_io_data[policy->cpu];
-
-        pr_debug("acpi_cpufreq_verify\n");
-
-        result = cpufreq_frequency_table_verify(policy,
-                        data->freq_table);
-
-        return (result);
-}
-
-
-static int
-acpi_cpufreq_cpu_init (
-        struct cpufreq_policy   *policy)
-{
-        unsigned int            i;
-        unsigned int            cpu = policy->cpu;
-        struct cpufreq_acpi_io  *data;
-        unsigned int            result = 0;
-
-        pr_debug("acpi_cpufreq_cpu_init\n");
-
-        data = kzalloc(sizeof(struct cpufreq_acpi_io), GFP_KERNEL);
-        if (!data)
-                return (-ENOMEM);
-
-        acpi_io_data[cpu] = data;
-
-        result = acpi_processor_register_performance(&data->acpi_data, cpu);
-
-        if (result)
-                goto err_free;
-
-        /* capability check */
-        if (data->acpi_data.state_count <= 1) {
-                pr_debug("No P-States\n");
-                result = -ENODEV;
-                goto err_unreg;
-        }
-
-        if ((data->acpi_data.control_register.space_id !=
-                                        ACPI_ADR_SPACE_FIXED_HARDWARE) ||
-            (data->acpi_data.status_register.space_id !=
-                                        ACPI_ADR_SPACE_FIXED_HARDWARE)) {
-                pr_debug("Unsupported address space [%d, %d]\n",
-                        (u32) (data->acpi_data.control_register.space_id),
-                        (u32) (data->acpi_data.status_register.space_id));
-                result = -ENODEV;
-                goto err_unreg;
-        }
-
-        /* alloc freq_table */
-        data->freq_table = kmalloc(sizeof(struct cpufreq_frequency_table) *
-                                   (data->acpi_data.state_count + 1),
-                                   GFP_KERNEL);
-        if (!data->freq_table) {
-                result = -ENOMEM;
-                goto err_unreg;
-        }
-
-        /* detect transition latency */
-        policy->cpuinfo.transition_latency = 0;
-        for (i=0; i<data->acpi_data.state_count; i++) {
-                if ((data->acpi_data.states[i].transition_latency * 1000) >
-                    policy->cpuinfo.transition_latency) {
-                        policy->cpuinfo.transition_latency =
-                            data->acpi_data.states[i].transition_latency * 1000;
-                }
-        }
-        policy->cur = processor_get_freq(data, policy->cpu);
-
-        /* table init */
-        for (i = 0; i <= data->acpi_data.state_count; i++)
-        {
-                data->freq_table[i].index = i;
-                if (i < data->acpi_data.state_count) {
-                        data->freq_table[i].frequency =
-                              data->acpi_data.states[i].core_frequency * 1000;
-                } else {
-                        data->freq_table[i].frequency = CPUFREQ_TABLE_END;
-                }
-        }
-
-        result = cpufreq_frequency_table_cpuinfo(policy, data->freq_table);
-        if (result) {
-                goto err_freqfree;
-        }
-
-        /* notify BIOS that we exist */
-        acpi_processor_notify_smm(THIS_MODULE);
-
-        printk(KERN_INFO "acpi-cpufreq: CPU%u - ACPI performance management "
-               "activated.\n", cpu);
-
-        for (i = 0; i < data->acpi_data.state_count; i++)
-                pr_debug("     %cP%d: %d MHz, %d mW, %d uS, %d uS, 0x%x 0x%x\n",
-                        (i == data->acpi_data.state?'*':' '), i,
-                        (u32) data->acpi_data.states[i].core_frequency,
-                        (u32) data->acpi_data.states[i].power,
-                        (u32) data->acpi_data.states[i].transition_latency,
-                        (u32) data->acpi_data.states[i].bus_master_latency,
-                        (u32) data->acpi_data.states[i].status,
-                        (u32) data->acpi_data.states[i].control);
-
-        cpufreq_frequency_table_get_attr(data->freq_table, policy->cpu);
-
-        /* the first call to ->target() should result in us actually
-         * writing something to the appropriate registers. */
-        data->resume = 1;
-
-        return (result);
-
- err_freqfree:
-        kfree(data->freq_table);
- err_unreg:
-        acpi_processor_unregister_performance(&data->acpi_data, cpu);
- err_free:
-        kfree(data);
-        acpi_io_data[cpu] = NULL;
-
-        return (result);
-}
-
-
-static int
-acpi_cpufreq_cpu_exit (
-        struct cpufreq_policy   *policy)
-{
-        struct cpufreq_acpi_io *data = acpi_io_data[policy->cpu];
-
-        pr_debug("acpi_cpufreq_cpu_exit\n");
-
-        if (data) {
-                cpufreq_frequency_table_put_attr(policy->cpu);
-                acpi_io_data[policy->cpu] = NULL;
-                acpi_processor_unregister_performance(&data->acpi_data,
-                                                      policy->cpu);
-                kfree(data);
-        }
-
-        return (0);
-}
-
-
-static struct freq_attr* acpi_cpufreq_attr[] = {
-        &cpufreq_freq_attr_scaling_available_freqs,
-        NULL,
-};
-
-
-static struct cpufreq_driver acpi_cpufreq_driver = {
-        .verify         = acpi_cpufreq_verify,
-        .target         = acpi_cpufreq_target,
-        .get            = acpi_cpufreq_get,
-        .init           = acpi_cpufreq_cpu_init,
-        .exit           = acpi_cpufreq_cpu_exit,
-        .name           = "acpi-cpufreq",
-        .owner          = THIS_MODULE,
-        .attr           = acpi_cpufreq_attr,
-};
-
-
-static int __init
-acpi_cpufreq_init (void)
-{
-        pr_debug("acpi_cpufreq_init\n");
-
-        return cpufreq_register_driver(&acpi_cpufreq_driver);
-}
-
-
-static void __exit
-acpi_cpufreq_exit (void)
-{
-        pr_debug("acpi_cpufreq_exit\n");
-
-        cpufreq_unregister_driver(&acpi_cpufreq_driver);
-        return;
-}
-
-
-late_initcall(acpi_cpufreq_init);
-module_exit(acpi_cpufreq_exit);
-
diff --git a/arch/ia64/kernel/fsys.S b/arch/ia64/kernel/fsys.S
index c4cd45d97749..abc6dee3799c 100644
--- a/arch/ia64/kernel/fsys.S
+++ b/arch/ia64/kernel/fsys.S
@@ -90,53 +90,6 @@ ENTRY(fsys_getpid)
         FSYS_RETURN
 END(fsys_getpid)
 
-ENTRY(fsys_getppid)
-        .prologue
-        .altrp b6
-        .body
-        add r17=IA64_TASK_GROUP_LEADER_OFFSET,r16
-        ;;
-        ld8 r17=[r17]                           // r17 = current->group_leader
-        add r9=TI_FLAGS+IA64_TASK_SIZE,r16
-        ;;
-
-        ld4 r9=[r9]
-        add r17=IA64_TASK_REAL_PARENT_OFFSET,r17 // r17 = &current->group_leader->real_parent
-        ;;
-        and r9=TIF_ALLWORK_MASK,r9
-
-1:      ld8 r18=[r17]                           // r18 = current->group_leader->real_parent
-        ;;
-        cmp.ne p8,p0=0,r9
-        add r8=IA64_TASK_TGID_OFFSET,r18        // r8 = &current->group_leader->real_parent->tgid
-        ;;
-
-        /*
-         * The .acq is needed to ensure that the read of tgid has returned its data before
-         * we re-check "real_parent".
-         */
-        ld4.acq r8=[r8]                         // r8 = current->group_leader->real_parent->tgid
-#ifdef CONFIG_SMP
-        /*
-         * Re-read current->group_leader->real_parent.
-         */
-        ld8 r19=[r17]                           // r19 = current->group_leader->real_parent
-(p8)    br.spnt.many fsys_fallback_syscall
-        ;;
-        cmp.ne p6,p0=r18,r19                    // did real_parent change?
-        mov r19=0                       // i must not leak kernel bits...
-(p6)    br.cond.spnt.few 1b                     // yes -> redo the read of tgid and the check
-        ;;
-        mov r17=0                       // i must not leak kernel bits...
-        mov r18=0                       // i must not leak kernel bits...
-#else
-        mov r17=0                       // i must not leak kernel bits...
-        mov r18=0                       // i must not leak kernel bits...
-        mov r19=0                       // i must not leak kernel bits...
-#endif
-        FSYS_RETURN
-END(fsys_getppid)
-
 ENTRY(fsys_set_tid_address)
         .prologue
         .altrp b6
@@ -614,7 +567,7 @@ paravirt_fsyscall_table:
         data8 0                         // chown
         data8 0                         // lseek                // 1040
         data8 fsys_getpid               // getpid
-        data8 fsys_getppid              // getppid
+        data8 0                         // getppid
         data8 0                         // mount
         data8 0                         // umount
         data8 0                         // setuid               // 1045
diff --git a/arch/ia64/kernel/iosapic.c b/arch/ia64/kernel/iosapic.c
index ee33c3aaa2fc..19f107be734e 100644
--- a/arch/ia64/kernel/iosapic.c
+++ b/arch/ia64/kernel/iosapic.c
@@ -76,7 +76,7 @@
  *      PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
  *
  * Note: The term "IRQ" is loosely used everywhere in Linux kernel to
- * describeinterrupts.  Now we use "IRQ" only for Linux IRQ's.  ISA IRQ
+ * describe interrupts.  Now we use "IRQ" only for Linux IRQ's.  ISA IRQ
  * (isa_irq) is the only exception in this source code.
  */
 
@@ -1010,6 +1010,26 @@ iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver)
         return 0;
 }
 
+static int
+iosapic_delete_rte(unsigned int irq, unsigned int gsi)
+{
+        struct iosapic_rte_info *rte, *temp;
+
+        list_for_each_entry_safe(rte, temp, &iosapic_intr_info[irq].rtes,
+                                                                rte_list) {
+                if (rte->iosapic->gsi_base + rte->rte_index == gsi) {
+                        if (rte->refcnt)
+                                return -EBUSY;
+
+                        list_del(&rte->rte_list);
+                        kfree(rte);
+                        return 0;
+                }
+        }
+
+        return -EINVAL;
+}
+
 int iosapic_init(unsigned long phys_addr, unsigned int gsi_base)
 {
         int num_rte, err, index;
@@ -1069,7 +1089,7 @@ int iosapic_init(unsigned long phys_addr, unsigned int gsi_base)
 
 int iosapic_remove(unsigned int gsi_base)
 {
-        int index, err = 0;
+        int i, irq, index, err = 0;
         unsigned long flags;
 
         spin_lock_irqsave(&iosapic_lock, flags);
@@ -1087,6 +1107,16 @@ int iosapic_remove(unsigned int gsi_base)
                 goto out;
         }
 
+        for (i = gsi_base; i < gsi_base + iosapic_lists[index].num_rte; i++) {
+                irq = __gsi_to_irq(i);
+                if (irq < 0)
+                        continue;
+
+                err = iosapic_delete_rte(irq, i);
+                if (err)
+                        goto out;
+        }
+
         iounmap(iosapic_lists[index].addr);
         iosapic_free(index);
  out:
diff --git a/arch/ia64/kernel/irq.c b/arch/ia64/kernel/irq.c
index ad69606613eb..f2c418281130 100644
--- a/arch/ia64/kernel/irq.c
+++ b/arch/ia64/kernel/irq.c
@@ -23,6 +23,8 @@
 #include <linux/interrupt.h>
 #include <linux/kernel_stat.h>
 
+#include <asm/mca.h>
+
 /*
  * 'what should we do if we get a hw irq event on an illegal vector'.
  * each architecture has to answer this themselves.
@@ -83,6 +85,12 @@ bool is_affinity_mask_valid(const struct cpumask *cpumask)
 
 #endif /* CONFIG_SMP */
 
+int __init arch_early_irq_init(void)
+{
+        ia64_mca_irq_init();
+        return 0;
+}
+
 #ifdef CONFIG_HOTPLUG_CPU
 unsigned int vectors_in_migration[NR_IRQS];
 
diff --git a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c
index 65bf9cd39044..d7396dbb07bb 100644
--- a/arch/ia64/kernel/mca.c
+++ b/arch/ia64/kernel/mca.c
@@ -2074,22 +2074,16 @@ ia64_mca_init(void)
         printk(KERN_INFO "MCA related initialization done\n");
 }
 
+
 /*
- * ia64_mca_late_init
- *
- *      Opportunity to setup things that require initialization later
- *      than ia64_mca_init.  Setup a timer to poll for CPEs if the
- *      platform doesn't support an interrupt driven mechanism.
- *
- *  Inputs  :   None
- *  Outputs :   Status
+ * These pieces cannot be done in ia64_mca_init() because it is called before
+ * early_irq_init() which would wipe out our percpu irq registrations. But we
+ * cannot leave them until ia64_mca_late_init() because by then all the other
+ * processors have been brought online and have set their own CMC vectors to
+ * point at a non-existant action. Called from arch_early_irq_init().
  */
-static int __init
-ia64_mca_late_init(void)
+void __init ia64_mca_irq_init(void)
 {
-        if (!mca_init)
-                return 0;
-
         /*
          *  Configure the CMCI/P vector and handler. Interrupts for CMC are
          *  per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
@@ -2108,6 +2102,23 @@ ia64_mca_late_init(void)
         /* Setup the CPEI/P handler */
         register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
 #endif
+}
+
+/*
+ * ia64_mca_late_init
+ *
+ *      Opportunity to setup things that require initialization later
+ *      than ia64_mca_init.  Setup a timer to poll for CPEs if the
+ *      platform doesn't support an interrupt driven mechanism.
+ *
+ *  Inputs  :   None
+ *  Outputs :   Status
+ */
+static int __init
+ia64_mca_late_init(void)
+{
+        if (!mca_init)
+                return 0;
 
         register_hotcpu_notifier(&mca_cpu_notifier);
 
diff --git a/arch/ia64/kernel/mca_drv.c b/arch/ia64/kernel/mca_drv.c
index 9392e021c93b..94f8bf777afa 100644
--- a/arch/ia64/kernel/mca_drv.c
+++ b/arch/ia64/kernel/mca_drv.c
@@ -349,7 +349,7 @@ init_record_index_pools(void)
 
         /* - 3 - */
         slidx_pool.max_idx = (rec_max_size/sect_min_size) * 2 + 1;
-        slidx_pool.buffer = (slidx_list_t *)
+        slidx_pool.buffer =
                 kmalloc(slidx_pool.max_idx * sizeof(slidx_list_t), GFP_KERNEL);
 
         return slidx_pool.buffer ? 0 : -ENOMEM;
diff --git a/arch/ia64/kernel/palinfo.c b/arch/ia64/kernel/palinfo.c
index 79521d5499f9..2b3c2d79256f 100644
--- a/arch/ia64/kernel/palinfo.c
+++ b/arch/ia64/kernel/palinfo.c
@@ -22,6 +22,7 @@
 #include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/proc_fs.h>
+#include <linux/seq_file.h>
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/efi.h>
@@ -41,7 +42,7 @@ MODULE_LICENSE("GPL");
 
 #define PALINFO_VERSION "0.5"
 
-typedef int (*palinfo_func_t)(char*);
+typedef int (*palinfo_func_t)(struct seq_file *);
 
 typedef struct {
         const char              *name;          /* name of the proc entry */
@@ -54,7 +55,7 @@ typedef struct {
  *  A bunch of string array to get pretty printing
  */
 
-static char *cache_types[] = {
+static const char *cache_types[] = {
         "",                     /* not used */
         "Instruction",
         "Data",
@@ -122,19 +123,16 @@ static const char *mem_attrib[]={
  *      - a pointer to the end of the buffer
  *
  */
-static char *
-bitvector_process(char *p, u64 vector)
+static void bitvector_process(struct seq_file *m, u64 vector)
 {
         int i,j;
-        const char *units[]={ "", "K", "M", "G", "T" };
+        static const char *units[]={ "", "K", "M", "G", "T" };
 
         for (i=0, j=0; i < 64; i++ , j=i/10) {
-                if (vector & 0x1) {
-                        p += sprintf(p, "%d%s ", 1 << (i-j*10), units[j]);
-                }
+                if (vector & 0x1)
+                        seq_printf(m, "%d%s ", 1 << (i-j*10), units[j]);
                 vector >>= 1;
         }
-        return p;
 }
 
 /*
@@ -149,8 +147,7 @@ bitvector_process(char *p, u64 vector)
  *      - a pointer to the end of the buffer
  *
  */
-static char *
-bitregister_process(char *p, u64 *reg_info, int max)
+static void bitregister_process(struct seq_file *m, u64 *reg_info, int max)
 {
         int i, begin, skip = 0;
         u64 value = reg_info[0];
@@ -163,9 +160,9 @@ bitregister_process(char *p, u64 *reg_info, int max)
 
                 if ((value & 0x1) == 0 && skip == 0) {
                         if (begin  <= i - 2)
-                                p += sprintf(p, "%d-%d ", begin, i-1);
+                                seq_printf(m, "%d-%d ", begin, i-1);
                         else
-                                p += sprintf(p, "%d ", i-1);
+                                seq_printf(m, "%d ", i-1);
                         skip  = 1;
                         begin = -1;
                 } else if ((value & 0x1) && skip == 1) {
@@ -176,19 +173,15 @@ bitregister_process(char *p, u64 *reg_info, int max)
         }
         if (begin > -1) {
                 if (begin < 127)
-                        p += sprintf(p, "%d-127", begin);
+                        seq_printf(m, "%d-127", begin);
                 else
-                        p += sprintf(p, "127");
+                        seq_puts(m, "127");
         }
-
-        return p;
 }
 
-static int
-power_info(char *page)
+static int power_info(struct seq_file *m)
 {
         s64 status;
-        char *p = page;
         u64 halt_info_buffer[8];
         pal_power_mgmt_info_u_t *halt_info =(pal_power_mgmt_info_u_t *)halt_info_buffer;
         int i;
@@ -198,26 +191,25 @@ power_info(char *page)
 
         for (i=0; i < 8 ; i++ ) {
                 if (halt_info[i].pal_power_mgmt_info_s.im == 1) {
-                        p += sprintf(p, "Power level %d:\n"
-                                     "\tentry_latency       : %d cycles\n"
-                                     "\texit_latency        : %d cycles\n"
-                                     "\tpower consumption   : %d mW\n"
-                                     "\tCache+TLB coherency : %s\n", i,
-                                     halt_info[i].pal_power_mgmt_info_s.entry_latency,
-                                     halt_info[i].pal_power_mgmt_info_s.exit_latency,
-                                     halt_info[i].pal_power_mgmt_info_s.power_consumption,
-                                     halt_info[i].pal_power_mgmt_info_s.co ? "Yes" : "No");
+                        seq_printf(m,
+                                   "Power level %d:\n"
+                                   "\tentry_latency       : %d cycles\n"
+                                   "\texit_latency        : %d cycles\n"
+                                   "\tpower consumption   : %d mW\n"
+                                   "\tCache+TLB coherency : %s\n", i,
+                                   halt_info[i].pal_power_mgmt_info_s.entry_latency,
+                                   halt_info[i].pal_power_mgmt_info_s.exit_latency,
+                                   halt_info[i].pal_power_mgmt_info_s.power_consumption,
+                                   halt_info[i].pal_power_mgmt_info_s.co ? "Yes" : "No");
                 } else {
-                        p += sprintf(p,"Power level %d: not implemented\n",i);
+                        seq_printf(m,"Power level %d: not implemented\n", i);
                 }
         }
-        return p - page;
+        return 0;
 }
 
-static int
-cache_info(char *page)
+static int cache_info(struct seq_file *m)
 {
-        char *p = page;
         unsigned long i, levels, unique_caches;
         pal_cache_config_info_t cci;
         int j, k;
@@ -228,73 +220,74 @@ cache_info(char *page)
                 return 0;
         }
 
-        p += sprintf(p, "Cache levels  : %ld\nUnique caches : %ld\n\n", levels, unique_caches);
+        seq_printf(m, "Cache levels  : %ld\nUnique caches : %ld\n\n",
+                   levels, unique_caches);
 
         for (i=0; i < levels; i++) {
-
                 for (j=2; j >0 ; j--) {
-
                         /* even without unification some level may not be present */
-                        if ((status=ia64_pal_cache_config_info(i,j, &cci)) != 0) {
+                        if ((status=ia64_pal_cache_config_info(i,j, &cci)) != 0)
                                 continue;
-                        }
-                        p += sprintf(p,
-                                     "%s Cache level %lu:\n"
-                                     "\tSize           : %u bytes\n"
-                                     "\tAttributes     : ",
-                                     cache_types[j+cci.pcci_unified], i+1,
-                                     cci.pcci_cache_size);
-
-                        if (cci.pcci_unified) p += sprintf(p, "Unified ");
-
-                        p += sprintf(p, "%s\n", cache_mattrib[cci.pcci_cache_attr]);
-
-                        p += sprintf(p,
-                                     "\tAssociativity  : %d\n"
-                                     "\tLine size      : %d bytes\n"
-                                     "\tStride         : %d bytes\n",
-                                     cci.pcci_assoc, 1<<cci.pcci_line_size, 1<<cci.pcci_stride);
+
+                        seq_printf(m,
+                                   "%s Cache level %lu:\n"
+                                   "\tSize           : %u bytes\n"
+                                   "\tAttributes     : ",
+                                   cache_types[j+cci.pcci_unified], i+1,
+                                   cci.pcci_cache_size);
+
+                        if (cci.pcci_unified)
+                                seq_puts(m, "Unified ");
+
+                        seq_printf(m, "%s\n", cache_mattrib[cci.pcci_cache_attr]);
+
+                        seq_printf(m,
+                                   "\tAssociativity  : %d\n"
+                                   "\tLine size      : %d bytes\n"
+                                   "\tStride         : %d bytes\n",
+                                   cci.pcci_assoc,
+                                   1<<cci.pcci_line_size,
+                                   1<<cci.pcci_stride);
                         if (j == 1)
-                                p += sprintf(p, "\tStore latency  : N/A\n");
+                                seq_puts(m, "\tStore latency  : N/A\n");
                         else
-                                p += sprintf(p, "\tStore latency  : %d cycle(s)\n",
-                                                cci.pcci_st_latency);
+                                seq_printf(m, "\tStore latency  : %d cycle(s)\n",
+                                           cci.pcci_st_latency);
 
-                        p += sprintf(p,
-                                     "\tLoad latency   : %d cycle(s)\n"
-                                     "\tStore hints    : ", cci.pcci_ld_latency);
+                        seq_printf(m,
+                                   "\tLoad latency   : %d cycle(s)\n"
+                                   "\tStore hints    : ", cci.pcci_ld_latency);
 
                         for(k=0; k < 8; k++ ) {
                                 if ( cci.pcci_st_hints & 0x1)
-                                        p += sprintf(p, "[%s]", cache_st_hints[k]);
+                                        seq_printf(m, "[%s]", cache_st_hints[k]);
                                 cci.pcci_st_hints >>=1;
                         }
-                        p += sprintf(p, "\n\tLoad hints     : ");
+                        seq_puts(m, "\n\tLoad hints     : ");
 
                         for(k=0; k < 8; k++ ) {
                                 if (cci.pcci_ld_hints & 0x1)
-                                        p += sprintf(p, "[%s]", cache_ld_hints[k]);
+                                        seq_printf(m, "[%s]", cache_ld_hints[k]);
                                 cci.pcci_ld_hints >>=1;
                         }
-                        p += sprintf(p,
-                                     "\n\tAlias boundary : %d byte(s)\n"
-                                     "\tTag LSB        : %d\n"
-                                     "\tTag MSB        : %d\n",
-                                     1<<cci.pcci_alias_boundary, cci.pcci_tag_lsb,
-                                     cci.pcci_tag_msb);
+                        seq_printf(m,
+                                   "\n\tAlias boundary : %d byte(s)\n"
+                                   "\tTag LSB        : %d\n"
+                                   "\tTag MSB        : %d\n",
+                                   1<<cci.pcci_alias_boundary, cci.pcci_tag_lsb,
+                                   cci.pcci_tag_msb);
 
                         /* when unified, data(j=2) is enough */
-                        if (cci.pcci_unified) break;
+                        if (cci.pcci_unified)
+                                break;
                 }
         }
-        return p - page;
+        return 0;
 }
 
 
-static int
-vm_info(char *page)
+static int vm_info(struct seq_file *m)
 {
-        char *p = page;
         u64 tr_pages =0, vw_pages=0, tc_pages;
         u64 attrib;
         pal_vm_info_1_u_t vm_info_1;
@@ -309,7 +302,7 @@ vm_info(char *page)
                 printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);
         } else {
 
-                p += sprintf(p,
+                seq_printf(m,
                      "Physical Address Space         : %d bits\n"
                      "Virtual Address Space          : %d bits\n"
                      "Protection Key Registers(PKR)  : %d\n"
@@ -324,49 +317,49 @@ vm_info(char *page)
                      vm_info_1.pal_vm_info_1_s.hash_tag_id,
                      vm_info_2.pal_vm_info_2_s.rid_size);
                 if (vm_info_2.pal_vm_info_2_s.max_purges == PAL_MAX_PURGES)
-                        p += sprintf(p, "unlimited\n");
+                        seq_puts(m, "unlimited\n");
                 else
-                        p += sprintf(p, "%d\n",
+                        seq_printf(m, "%d\n",
                                 vm_info_2.pal_vm_info_2_s.max_purges ?
                                 vm_info_2.pal_vm_info_2_s.max_purges : 1);
         }
 
         if (ia64_pal_mem_attrib(&attrib) == 0) {
-                p += sprintf(p, "Supported memory attributes    : ");
+                seq_puts(m, "Supported memory attributes    : ");
                 sep = "";
                 for (i = 0; i < 8; i++) {
                         if (attrib & (1 << i)) {
-                                p += sprintf(p, "%s%s", sep, mem_attrib[i]);
+                                seq_printf(m, "%s%s", sep, mem_attrib[i]);
                                 sep = ", ";
                         }
                 }
-                p += sprintf(p, "\n");
+                seq_putc(m, '\n');
         }
 
         if ((status = ia64_pal_vm_page_size(&tr_pages, &vw_pages)) !=0) {
                 printk(KERN_ERR "ia64_pal_vm_page_size=%ld\n", status);
         } else {
 
-                p += sprintf(p,
-                             "\nTLB walker                     : %simplemented\n"
-                             "Number of DTR                  : %d\n"
-                             "Number of ITR                  : %d\n"
-                             "TLB insertable page sizes      : ",
-                             vm_info_1.pal_vm_info_1_s.vw ? "" : "not ",
-                             vm_info_1.pal_vm_info_1_s.max_dtr_entry+1,
-                             vm_info_1.pal_vm_info_1_s.max_itr_entry+1);
-
+                seq_printf(m,
+                           "\nTLB walker                     : %simplemented\n"
+                           "Number of DTR                  : %d\n"
+                           "Number of ITR                  : %d\n"
+                           "TLB insertable page sizes      : ",
+                           vm_info_1.pal_vm_info_1_s.vw ? "" : "not ",
+                           vm_info_1.pal_vm_info_1_s.max_dtr_entry+1,
+                           vm_info_1.pal_vm_info_1_s.max_itr_entry+1);
 
-                p = bitvector_process(p, tr_pages);
+                bitvector_process(m, tr_pages);
 
-                p += sprintf(p, "\nTLB purgeable page sizes       : ");
+                seq_puts(m, "\nTLB purgeable page sizes       : ");
 
-                p = bitvector_process(p, vw_pages);
+                bitvector_process(m, vw_pages);
         }
-        if ((status=ia64_get_ptce(&ptce)) != 0) {
+
+        if ((status = ia64_get_ptce(&ptce)) != 0) {
                 printk(KERN_ERR "ia64_get_ptce=%ld\n", status);
         } else {
-                p += sprintf(p,
+                seq_printf(m,
                      "\nPurge base address             : 0x%016lx\n"
                      "Purge outer loop count         : %d\n"
                      "Purge inner loop count         : %d\n"
@@ -375,7 +368,7 @@ vm_info(char *page)
                      ptce.base, ptce.count[0], ptce.count[1],
                      ptce.stride[0], ptce.stride[1]);
 
-                p += sprintf(p,
+                seq_printf(m,
                      "TC Levels                      : %d\n"
                      "Unique TC(s)                   : %d\n",
                      vm_info_1.pal_vm_info_1_s.num_tc_levels,
@@ -385,13 +378,11 @@ vm_info(char *page)
                         for (j=2; j>0 ; j--) {
                                 tc_pages = 0; /* just in case */
 
-
                                 /* even without unification, some levels may not be present */
-                                if ((status=ia64_pal_vm_info(i,j, &tc_info, &tc_pages)) != 0) {
+                                if ((status=ia64_pal_vm_info(i,j, &tc_info, &tc_pages)) != 0)
                                         continue;
-                                }
 
-                                p += sprintf(p,
+                                seq_printf(m,
                                      "\n%s Translation Cache Level %d:\n"
                                      "\tHash sets           : %d\n"
                                      "\tAssociativity       : %d\n"
@@ -403,15 +394,15 @@ vm_info(char *page)
                                      tc_info.tc_num_entries);
 
                                 if (tc_info.tc_pf)
-                                        p += sprintf(p, "PreferredPageSizeOptimized ");
+                                        seq_puts(m, "PreferredPageSizeOptimized ");
                                 if (tc_info.tc_unified)
-                                        p += sprintf(p, "Unified ");
+                                        seq_puts(m, "Unified ");
                                 if (tc_info.tc_reduce_tr)
-                                        p += sprintf(p, "TCReduction");
+                                        seq_puts(m, "TCReduction");
 
-                                p += sprintf(p, "\n\tSupported page sizes: ");
+                                seq_puts(m, "\n\tSupported page sizes: ");
 
-                                p = bitvector_process(p, tc_pages);
+                                bitvector_process(m, tc_pages);
 
                                 /* when unified date (j=2) is enough */
                                 if (tc_info.tc_unified)
@@ -419,16 +410,14 @@ vm_info(char *page)
                         }
                 }
         }
-        p += sprintf(p, "\n");
 
-        return p - page;
+        seq_putc(m, '\n');
+        return 0;
 }
 
 
-static int
-register_info(char *page)
+static int register_info(struct seq_file *m)
 {
-        char *p = page;
         u64 reg_info[2];
         u64 info;
         unsigned long phys_stacked;
@@ -442,35 +431,31 @@ register_info(char *page)
         };
 
         for(info=0; info < 4; info++) {
-
-                if (ia64_pal_register_info(info, &reg_info[0], &reg_info[1]) != 0) return 0;
-
-                p += sprintf(p, "%-32s : ", info_type[info]);
-
-                p = bitregister_process(p, reg_info, 128);
-
-                p += sprintf(p, "\n");
+                if (ia64_pal_register_info(info, &reg_info[0], &reg_info[1]) != 0)
+                        return 0;
+                seq_printf(m, "%-32s : ", info_type[info]);
+                bitregister_process(m, reg_info, 128);
+                seq_putc(m, '\n');
         }
 
-        if (ia64_pal_rse_info(&phys_stacked, &hints) == 0) {
+        if (ia64_pal_rse_info(&phys_stacked, &hints) == 0)
+                seq_printf(m,
+                           "RSE stacked physical registers   : %ld\n"
+                           "RSE load/store hints             : %ld (%s)\n",
+                           phys_stacked, hints.ph_data,
+                           hints.ph_data < RSE_HINTS_COUNT ? rse_hints[hints.ph_data]: "(??)");
 
-        p += sprintf(p,
-                     "RSE stacked physical registers   : %ld\n"
-                     "RSE load/store hints             : %ld (%s)\n",
-                     phys_stacked, hints.ph_data,
-                     hints.ph_data < RSE_HINTS_COUNT ? rse_hints[hints.ph_data]: "(??)");
-        }
         if (ia64_pal_debug_info(&iregs, &dregs))
                 return 0;
 
-        p += sprintf(p,
-                     "Instruction debug register pairs : %ld\n"
-                     "Data debug register pairs        : %ld\n", iregs, dregs);
+        seq_printf(m,
+                   "Instruction debug register pairs : %ld\n"
+                   "Data debug register pairs        : %ld\n", iregs, dregs);
 
-        return p - page;
+        return 0;
 }
 
-static char *proc_features_0[]={                /* Feature set 0 */
+static const char *const proc_features_0[]={            /* Feature set 0 */
         NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
         NULL,NULL,NULL,NULL,NULL,NULL,NULL, NULL,NULL,
         NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
@@ -502,7 +487,7 @@ static char *proc_features_0[]={		/* Feature set 0 */
         "Enable BERR promotion"
 };
 
-static char *proc_features_16[]={               /* Feature set 16 */
+static const char *const proc_features_16[]={           /* Feature set 16 */
         "Disable ETM",
         "Enable ETM",
         "Enable MCA on half-way timer",
@@ -522,7 +507,7 @@ static char *proc_features_16[]={		/* Feature set 16 */
         NULL, NULL, NULL, NULL, NULL
 };
 
-static char **proc_features[]={
+static const char *const *const proc_features[]={
         proc_features_0,
         NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
         NULL, NULL, NULL, NULL,
@@ -530,11 +515,10 @@ static char **proc_features[]={
         NULL, NULL, NULL, NULL,
 };
 
-static char * feature_set_info(char *page, u64 avail, u64 status, u64 control,
-                                                        unsigned long set)
+static void feature_set_info(struct seq_file *m, u64 avail, u64 status, u64 control,
+                             unsigned long set)
 {
-        char *p = page;
-        char **vf, **v;
+        const char *const *vf, *const *v;
         int i;
 
         vf = v = proc_features[set];
@@ -547,13 +531,13 @@ static char * feature_set_info(char *page, u64 avail, u64 status, u64 control,
                 if (vf)
                         v = vf + i;
                 if ( v && *v ) {
-                        p += sprintf(p, "%-40s : %s %s\n", *v,
+                        seq_printf(m, "%-40s : %s %s\n", *v,
                                 avail & 0x1 ? (status & 0x1 ?
-                                                "On " : "Off"): "",
+                                              "On " : "Off"): "",
                                 avail & 0x1 ? (control & 0x1 ?
                                                 "Ctrl" : "NoCtrl"): "");
                 } else {
-                        p += sprintf(p, "Feature set %2ld bit %2d\t\t\t"
+                        seq_printf(m, "Feature set %2ld bit %2d\t\t\t"
                                         " : %s %s\n",
                                 set, i,
                                 avail & 0x1 ? (status & 0x1 ?
@@ -562,36 +546,32 @@ static char * feature_set_info(char *page, u64 avail, u64 status, u64 control,
                                                 "Ctrl" : "NoCtrl"): "");
                 }
         }
-        return p;
 }
 
-static int
-processor_info(char *page)
+static int processor_info(struct seq_file *m)
 {
-        char *p = page;
         u64 avail=1, status=1, control=1, feature_set=0;
         s64 ret;
 
         do {
                 ret = ia64_pal_proc_get_features(&avail, &status, &control,
                                                 feature_set);
-                if (ret < 0) {
-                        return p - page;
-                }
+                if (ret < 0)
+                        return 0;
+
                 if (ret == 1) {
                         feature_set++;
                         continue;
                 }
 
-                p = feature_set_info(p, avail, status, control, feature_set);
-
+                feature_set_info(m, avail, status, control, feature_set);
                 feature_set++;
         } while(1);
 
-        return p - page;
+        return 0;
 }
 
-static const char *bus_features[]={
+static const char *const bus_features[]={
         NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
         NULL,NULL,NULL,NULL,NULL,NULL,NULL, NULL,NULL,
         NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
@@ -617,125 +597,118 @@ static const char *bus_features[]={
 };
 
 
-static int
-bus_info(char *page)
+static int bus_info(struct seq_file *m)
 {
-        char *p = page;
-        const char **v = bus_features;
+        const char *const *v = bus_features;
         pal_bus_features_u_t av, st, ct;
         u64 avail, status, control;
         int i;
         s64 ret;
 
-        if ((ret=ia64_pal_bus_get_features(&av, &st, &ct)) != 0) return 0;
+        if ((ret=ia64_pal_bus_get_features(&av, &st, &ct)) != 0)
+                return 0;
 
         avail   = av.pal_bus_features_val;
         status  = st.pal_bus_features_val;
         control = ct.pal_bus_features_val;
 
         for(i=0; i < 64; i++, v++, avail >>=1, status >>=1, control >>=1) {
-                if ( ! *v ) continue;
-                p += sprintf(p, "%-48s : %s%s %s\n", *v,
-                                avail & 0x1 ? "" : "NotImpl",
-                                avail & 0x1 ? (status  & 0x1 ? "On" : "Off"): "",
-                                avail & 0x1 ? (control & 0x1 ? "Ctrl" : "NoCtrl"): "");
+                if ( ! *v )
+                        continue;
+                seq_printf(m, "%-48s : %s%s %s\n", *v,
+                           avail & 0x1 ? "" : "NotImpl",
+                           avail & 0x1 ? (status  & 0x1 ? "On" : "Off"): "",
+                           avail & 0x1 ? (control & 0x1 ? "Ctrl" : "NoCtrl"): "");
         }
-        return p - page;
+        return 0;
 }
 
-static int
-version_info(char *page)
+static int version_info(struct seq_file *m)
 {
         pal_version_u_t min_ver, cur_ver;
-        char *p = page;
 
         if (ia64_pal_version(&min_ver, &cur_ver) != 0)
                 return 0;
 
-        p += sprintf(p,
-                     "PAL_vendor : 0x%02x (min=0x%02x)\n"
-                     "PAL_A      : %02x.%02x (min=%02x.%02x)\n"
-                     "PAL_B      : %02x.%02x (min=%02x.%02x)\n",
-                     cur_ver.pal_version_s.pv_pal_vendor,
-                     min_ver.pal_version_s.pv_pal_vendor,
-                     cur_ver.pal_version_s.pv_pal_a_model,
-                     cur_ver.pal_version_s.pv_pal_a_rev,
-                     min_ver.pal_version_s.pv_pal_a_model,
-                     min_ver.pal_version_s.pv_pal_a_rev,
-                     cur_ver.pal_version_s.pv_pal_b_model,
-                     cur_ver.pal_version_s.pv_pal_b_rev,
-                     min_ver.pal_version_s.pv_pal_b_model,
-                     min_ver.pal_version_s.pv_pal_b_rev);
-        return p - page;
+        seq_printf(m,
+                   "PAL_vendor : 0x%02x (min=0x%02x)\n"
+                   "PAL_A      : %02x.%02x (min=%02x.%02x)\n"
+                   "PAL_B      : %02x.%02x (min=%02x.%02x)\n",
+                   cur_ver.pal_version_s.pv_pal_vendor,
+                   min_ver.pal_version_s.pv_pal_vendor,
+                   cur_ver.pal_version_s.pv_pal_a_model,
+                   cur_ver.pal_version_s.pv_pal_a_rev,
+                   min_ver.pal_version_s.pv_pal_a_model,
+                   min_ver.pal_version_s.pv_pal_a_rev,
+                   cur_ver.pal_version_s.pv_pal_b_model,
+                   cur_ver.pal_version_s.pv_pal_b_rev,
+                   min_ver.pal_version_s.pv_pal_b_model,
+                   min_ver.pal_version_s.pv_pal_b_rev);
+        return 0;
 }
 
-static int
-perfmon_info(char *page)
+static int perfmon_info(struct seq_file *m)
 {
-        char *p = page;
         u64 pm_buffer[16];
         pal_perf_mon_info_u_t pm_info;
 
-        if (ia64_pal_perf_mon_info(pm_buffer, &pm_info) != 0) return 0;
-
-        p += sprintf(p,
-                     "PMC/PMD pairs                 : %d\n"
-                     "Counter width                 : %d bits\n"
-                     "Cycle event number            : %d\n"
-                     "Retired event number          : %d\n"
-                     "Implemented PMC               : ",
-                     pm_info.pal_perf_mon_info_s.generic, pm_info.pal_perf_mon_info_s.width,
-                     pm_info.pal_perf_mon_info_s.cycles, pm_info.pal_perf_mon_info_s.retired);
+        if (ia64_pal_perf_mon_info(pm_buffer, &pm_info) != 0)
+                return 0;
 
-        p = bitregister_process(p, pm_buffer, 256);
-        p += sprintf(p, "\nImplemented PMD               : ");
-        p = bitregister_process(p, pm_buffer+4, 256);
-        p += sprintf(p, "\nCycles count capable          : ");
-        p = bitregister_process(p, pm_buffer+8, 256);
-        p += sprintf(p, "\nRetired bundles count capable : ");
+        seq_printf(m,
+                   "PMC/PMD pairs                 : %d\n"
+                   "Counter width                 : %d bits\n"
+                   "Cycle event number            : %d\n"
+                   "Retired event number          : %d\n"
+                   "Implemented PMC               : ",
+                   pm_info.pal_perf_mon_info_s.generic,
+                   pm_info.pal_perf_mon_info_s.width,
+                   pm_info.pal_perf_mon_info_s.cycles,
+                   pm_info.pal_perf_mon_info_s.retired);
+
+        bitregister_process(m, pm_buffer, 256);
+        seq_puts(m, "\nImplemented PMD               : ");
+        bitregister_process(m, pm_buffer+4, 256);
+        seq_puts(m, "\nCycles count capable          : ");
+        bitregister_process(m, pm_buffer+8, 256);
+        seq_puts(m, "\nRetired bundles count capable : ");
 
 #ifdef CONFIG_ITANIUM
         /*
          * PAL_PERF_MON_INFO reports that only PMC4 can be used to count CPU_CYCLES
          * which is wrong, both PMC4 and PMD5 support it.
          */
-        if (pm_buffer[12] == 0x10) pm_buffer[12]=0x30;
+        if (pm_buffer[12] == 0x10)
+                pm_buffer[12]=0x30;
 #endif
 
-        p = bitregister_process(p, pm_buffer+12, 256);
-
-        p += sprintf(p, "\n");
-
-        return p - page;
+        bitregister_process(m, pm_buffer+12, 256);
+        seq_putc(m, '\n');
+        return 0;
 }
 
-static int
-frequency_info(char *page)
+static int frequency_info(struct seq_file *m)
 {
-        char *p = page;
         struct pal_freq_ratio proc, itc, bus;
         unsigned long base;
 
         if (ia64_pal_freq_base(&base) == -1)
-                p += sprintf(p, "Output clock            : not implemented\n");
+                seq_puts(m, "Output clock            : not implemented\n");
         else
-                p += sprintf(p, "Output clock            : %ld ticks/s\n", base);
+                seq_printf(m, "Output clock            : %ld ticks/s\n", base);
 
         if (ia64_pal_freq_ratios(&proc, &bus, &itc) != 0) return 0;
 
-        p += sprintf(p,
+        seq_printf(m,
                      "Processor/Clock ratio   : %d/%d\n"
                      "Bus/Clock ratio         : %d/%d\n"
                      "ITC/Clock ratio         : %d/%d\n",
                      proc.num, proc.den, bus.num, bus.den, itc.num, itc.den);
-
-        return p - page;
+        return 0;
 }
 
-static int
-tr_info(char *page)
+static int tr_info(struct seq_file *m)
 {
-        char *p = page;
         long status;
         pal_tr_valid_u_t tr_valid;
         u64 tr_buffer[4];
@@ -794,39 +767,40 @@ tr_info(char *page)
 
                 ifa_reg  = (struct ifa_reg *)&tr_buffer[2];
 
-                if (ifa_reg->valid == 0) continue;
+                if (ifa_reg->valid == 0)
+                        continue;
 
                 gr_reg   = (struct gr_reg *)tr_buffer;
                 itir_reg = (struct itir_reg *)&tr_buffer[1];
                 rid_reg  = (struct rid_reg *)&tr_buffer[3];
 
                 pgm      = -1 << (itir_reg->ps - 12);
-                p += sprintf(p,
-                             "%cTR%lu: av=%d pv=%d dv=%d mv=%d\n"
-                             "\tppn  : 0x%lx\n"
-                             "\tvpn  : 0x%lx\n"
-                             "\tps   : ",
-                             "ID"[i], j,
-                             tr_valid.pal_tr_valid_s.access_rights_valid,
-                             tr_valid.pal_tr_valid_s.priv_level_valid,
-                             tr_valid.pal_tr_valid_s.dirty_bit_valid,
-                             tr_valid.pal_tr_valid_s.mem_attr_valid,
-                             (gr_reg->ppn & pgm)<< 12, (ifa_reg->vpn & pgm)<< 12);
-
-                p = bitvector_process(p, 1<< itir_reg->ps);
-
-                p += sprintf(p,
-                             "\n\tpl   : %d\n"
-                             "\tar   : %d\n"
-                             "\trid  : %x\n"
-                             "\tp    : %d\n"
-                             "\tma   : %d\n"
-                             "\td    : %d\n",
-                             gr_reg->pl, gr_reg->ar, rid_reg->rid, gr_reg->p, gr_reg->ma,
-                             gr_reg->d);
+                seq_printf(m,
+                           "%cTR%lu: av=%d pv=%d dv=%d mv=%d\n"
+                           "\tppn  : 0x%lx\n"
+                           "\tvpn  : 0x%lx\n"
+                           "\tps   : ",
+                           "ID"[i], j,
+                           tr_valid.pal_tr_valid_s.access_rights_valid,
+                           tr_valid.pal_tr_valid_s.priv_level_valid,
+                           tr_valid.pal_tr_valid_s.dirty_bit_valid,
+                           tr_valid.pal_tr_valid_s.mem_attr_valid,
+                           (gr_reg->ppn & pgm)<< 12, (ifa_reg->vpn & pgm)<< 12);
+
+                bitvector_process(m, 1<< itir_reg->ps);
+
+                seq_printf(m,
+                           "\n\tpl   : %d\n"
+                           "\tar   : %d\n"
+                           "\trid  : %x\n"
+                           "\tp    : %d\n"
+                           "\tma   : %d\n"
+                           "\td    : %d\n",
+                           gr_reg->pl, gr_reg->ar, rid_reg->rid, gr_reg->p, gr_reg->ma,
+                           gr_reg->d);
                 }
         }
-        return p - page;
+        return 0;
 }
 
 
@@ -834,7 +808,7 @@ tr_info(char *page)
 /*
  * List {name,function} pairs for every entry in /proc/palinfo/cpu*
  */
-static palinfo_entry_t palinfo_entries[]={
+static const palinfo_entry_t palinfo_entries[]={
         { "version_info",       version_info, },
         { "vm_info",            vm_info, },
         { "cache_info",         cache_info, },
@@ -876,7 +850,7 @@ typedef union {
  */
 typedef struct {
         palinfo_func_t  func;   /* pointer to function to call */
-        char            *page;  /* buffer to store results */
+        struct seq_file *m;     /* buffer to store results */
         int             ret;    /* return value from call */
 } palinfo_smp_data_t;
 
@@ -889,7 +863,7 @@ static void
 palinfo_smp_call(void *info)
 {
         palinfo_smp_data_t *data = (palinfo_smp_data_t *)info;
-        data->ret = (*data->func)(data->page);
+        data->ret = (*data->func)(data->m);
 }
 
 /*
@@ -899,13 +873,13 @@ palinfo_smp_call(void *info)
  *      otherwise how many bytes in the "page" buffer were written
  */
 static
-int palinfo_handle_smp(pal_func_cpu_u_t *f, char *page)
+int palinfo_handle_smp(struct seq_file *m, pal_func_cpu_u_t *f)
 {
         palinfo_smp_data_t ptr;
         int ret;
 
         ptr.func = palinfo_entries[f->func_id].proc_read;
-        ptr.page = page;
+        ptr.m = m;
         ptr.ret  = 0; /* just in case */
 
 
@@ -919,7 +893,7 @@ int palinfo_handle_smp(pal_func_cpu_u_t *f, char *page)
 }
 #else /* ! CONFIG_SMP */
 static
-int palinfo_handle_smp(pal_func_cpu_u_t *f, char *page)
+int palinfo_handle_smp(struct seq_file *m, pal_func_cpu_u_t *f)
 {
         printk(KERN_ERR "palinfo: should not be called with non SMP kernel\n");
         return 0;
@@ -929,34 +903,35 @@ int palinfo_handle_smp(pal_func_cpu_u_t *f, char *page)
 /*
  * Entry point routine: all calls go through this function
  */
-static int
-palinfo_read_entry(char *page, char **start, off_t off, int count, int *eof, void *data)
+static int proc_palinfo_show(struct seq_file *m, void *v)
 {
-        int len=0;
-        pal_func_cpu_u_t *f = (pal_func_cpu_u_t *)&data;
+        pal_func_cpu_u_t *f = (pal_func_cpu_u_t *)&m->private;
 
         /*
          * in SMP mode, we may need to call another CPU to get correct
          * information. PAL, by definition, is processor specific
          */
         if (f->req_cpu == get_cpu())
-                len = (*palinfo_entries[f->func_id].proc_read)(page);
+                (*palinfo_entries[f->func_id].proc_read)(m);
         else
-                len = palinfo_handle_smp(f, page);
+                palinfo_handle_smp(m, f);
 
         put_cpu();
+        return 0;
+}
 
-        if (len <= off+count) *eof = 1;
-
-        *start = page + off;
-        len   -= off;
-
-        if (len>count) len = count;
-        if (len<0) len = 0;
-
-        return len;
+static int proc_palinfo_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, proc_palinfo_show, PDE_DATA(inode));
 }
 
+static const struct file_operations proc_palinfo_fops = {
+        .open           = proc_palinfo_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
 static void __cpuinit
 create_palinfo_proc_entries(unsigned int cpu)
 {
@@ -974,9 +949,8 @@ create_palinfo_proc_entries(unsigned int cpu)
 
         for (j=0; j < NR_PALINFO_ENTRIES; j++) {
                 f.func_id = j;
-                create_proc_read_entry(
-                        palinfo_entries[j].name, 0, cpu_dir,
-                        palinfo_read_entry, (void *)f.value);
+                proc_create_data(palinfo_entries[j].name, 0, cpu_dir,
+                                 &proc_palinfo_fops, (void *)f.value);
         }
 }
 
diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c
index 2eda28414abb..9ea25fce06d5 100644
--- a/arch/ia64/kernel/perfmon.c
+++ b/arch/ia64/kernel/perfmon.c
@@ -42,6 +42,7 @@
 #include <linux/completion.h>
 #include <linux/tracehook.h>
 #include <linux/slab.h>
+#include <linux/cpu.h>
 
 #include <asm/errno.h>
 #include <asm/intrinsics.h>
@@ -1322,8 +1323,6 @@ out:
 }
 EXPORT_SYMBOL(pfm_unregister_buffer_fmt);
 
-extern void update_pal_halt_status(int);
-
 static int
 pfm_reserve_session(struct task_struct *task, int is_syswide, unsigned int cpu)
 {
@@ -1371,9 +1370,9 @@ pfm_reserve_session(struct task_struct *task, int is_syswide, unsigned int cpu)
                 cpu));
 
         /*
-         * disable default_idle() to go to PAL_HALT
+         * Force idle() into poll mode
          */
-        update_pal_halt_status(0);
+        cpu_idle_poll_ctrl(true);
 
         UNLOCK_PFS(flags);
 
@@ -1430,11 +1429,8 @@ pfm_unreserve_session(pfm_context_t *ctx, int is_syswide, unsigned int cpu)
                 is_syswide,
                 cpu));
 
-        /*
-         * if possible, enable default_idle() to go into PAL_HALT
-         */
-        if (pfm_sessions.pfs_task_sessions == 0 && pfm_sessions.pfs_sys_sessions == 0)
-                update_pal_halt_status(1);
+        /* Undo forced polling. Last session reenables pal_halt */
+        cpu_idle_poll_ctrl(false);
 
         UNLOCK_PFS(flags);
 
diff --git a/arch/ia64/kernel/process.c b/arch/ia64/kernel/process.c
index 6f7dc8b7b35c..55d4ba47a907 100644
--- a/arch/ia64/kernel/process.c
+++ b/arch/ia64/kernel/process.c
@@ -96,21 +96,13 @@ show_stack (struct task_struct *task, unsigned long *sp)
 }
 
 void
-dump_stack (void)
-{
-        show_stack(NULL, NULL);
-}
-
-EXPORT_SYMBOL(dump_stack);
-
-void
 show_regs (struct pt_regs *regs)
 {
         unsigned long ip = regs->cr_iip + ia64_psr(regs)->ri;
 
         print_modules();
-        printk("\nPid: %d, CPU %d, comm: %20s\n", task_pid_nr(current),
-                        smp_processor_id(), current->comm);
+        printk("\n");
+        show_regs_print_info(KERN_DEFAULT);
         printk("psr : %016lx ifs : %016lx ip  : [<%016lx>]    %s (%s)\n",
                regs->cr_ipsr, regs->cr_ifs, ip, print_tainted(),
                init_utsname()->release);
@@ -209,41 +201,13 @@ do_notify_resume_user(sigset_t *unused, struct sigscratch *scr, long in_syscall)
         local_irq_disable();    /* force interrupt disable */
 }
 
-static int pal_halt        = 1;
-static int can_do_pal_halt = 1;
-
 static int __init nohalt_setup(char * str)
 {
-        pal_halt = can_do_pal_halt = 0;
+        cpu_idle_poll_ctrl(true);
         return 1;
 }
 __setup("nohalt", nohalt_setup);
 
-void
-update_pal_halt_status(int status)
-{
-        can_do_pal_halt = pal_halt && status;
-}
-
-/*
- * We use this if we don't have any better idle routine..
- */
-void
-default_idle (void)
-{
-        local_irq_enable();
-        while (!need_resched()) {
-                if (can_do_pal_halt) {
-                        local_irq_disable();
-                        if (!need_resched()) {
-                                safe_halt();
-                        }
-                        local_irq_enable();
-                } else
-                        cpu_relax();
-        }
-}
-
 #ifdef CONFIG_HOTPLUG_CPU
 /* We don't actually take CPU down, just spin without interrupts. */
 static inline void play_dead(void)
@@ -270,47 +234,29 @@ static inline void play_dead(void)
 }
 #endif /* CONFIG_HOTPLUG_CPU */
 
-void __attribute__((noreturn))
-cpu_idle (void)
+void arch_cpu_idle_dead(void)
+{
+        play_dead();
+}
+
+void arch_cpu_idle(void)
 {
         void (*mark_idle)(int) = ia64_mark_idle;
-        int cpu = smp_processor_id();
-
-        /* endless idle loop with no priority at all */
-        while (1) {
-                rcu_idle_enter();
-                if (can_do_pal_halt) {
-                        current_thread_info()->status &= ~TS_POLLING;
-                        /*
-                         * TS_POLLING-cleared state must be visible before we
-                         * test NEED_RESCHED:
-                         */
-                        smp_mb();
-                } else {
-                        current_thread_info()->status |= TS_POLLING;
-                }
 
-                if (!need_resched()) {
 #ifdef CONFIG_SMP
-                        min_xtp();
+        min_xtp();
 #endif
-                        rmb();
-                        if (mark_idle)
-                                (*mark_idle)(1);
+        rmb();
+        if (mark_idle)
+                (*mark_idle)(1);
 
-                        default_idle();
-                        if (mark_idle)
-                                (*mark_idle)(0);
+        safe_halt();
+
+        if (mark_idle)
+                (*mark_idle)(0);
 #ifdef CONFIG_SMP
-                        normal_xtp();
+        normal_xtp();
 #endif
-                }
-                rcu_idle_exit();
-                schedule_preempt_disabled();
-                check_pgt_cache();
-                if (cpu_is_offline(cpu))
-                        play_dead();
-        }
 }
 
 void
diff --git a/arch/ia64/kernel/salinfo.c b/arch/ia64/kernel/salinfo.c
index aa527d7e91f2..4bc580af67b3 100644
--- a/arch/ia64/kernel/salinfo.c
+++ b/arch/ia64/kernel/salinfo.c
@@ -40,6 +40,7 @@
 #include <linux/cpu.h>
 #include <linux/types.h>
 #include <linux/proc_fs.h>
+#include <linux/seq_file.h>
 #include <linux/module.h>
 #include <linux/smp.h>
 #include <linux/timer.h>
@@ -53,7 +54,7 @@ MODULE_AUTHOR("Jesse Barnes <jbarnes@sgi.com>");
 MODULE_DESCRIPTION("/proc interface to IA-64 SAL features");
 MODULE_LICENSE("GPL");
 
-static int salinfo_read(char *page, char **start, off_t off, int count, int *eof, void *data);
+static const struct file_operations proc_salinfo_fops;
 
 typedef struct {
         const char              *name;          /* name of the proc entry */
@@ -65,7 +66,7 @@ typedef struct {
  * List {name,feature} pairs for every entry in /proc/sal/<feature>
  * that this module exports
  */
-static salinfo_entry_t salinfo_entries[]={
+static const salinfo_entry_t salinfo_entries[]={
         { "bus_lock",           IA64_SAL_PLATFORM_FEATURE_BUS_LOCK, },
         { "irq_redirection",    IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT, },
         { "ipi_redirection",    IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT, },
@@ -301,9 +302,7 @@ salinfo_event_open(struct inode *inode, struct file *file)
 static ssize_t
 salinfo_event_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
 {
-        struct inode *inode = file_inode(file);
-        struct proc_dir_entry *entry = PDE(inode);
-        struct salinfo_data *data = entry->data;
+        struct salinfo_data *data = PDE_DATA(file_inode(file));
         char cmd[32];
         size_t size;
         int i, n, cpu = -1;
@@ -360,8 +359,7 @@ static const struct file_operations salinfo_event_fops = {
 static int
 salinfo_log_open(struct inode *inode, struct file *file)
 {
-        struct proc_dir_entry *entry = PDE(inode);
-        struct salinfo_data *data = entry->data;
+        struct salinfo_data *data = PDE_DATA(inode);
 
         if (!capable(CAP_SYS_ADMIN))
                 return -EPERM;
@@ -386,8 +384,7 @@ salinfo_log_open(struct inode *inode, struct file *file)
 static int
 salinfo_log_release(struct inode *inode, struct file *file)
 {
-        struct proc_dir_entry *entry = PDE(inode);
-        struct salinfo_data *data = entry->data;
+        struct salinfo_data *data = PDE_DATA(inode);
 
         if (data->state == STATE_NO_DATA) {
                 vfree(data->log_buffer);
@@ -463,9 +460,7 @@ retry:
 static ssize_t
 salinfo_log_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
 {
-        struct inode *inode = file_inode(file);
-        struct proc_dir_entry *entry = PDE(inode);
-        struct salinfo_data *data = entry->data;
+        struct salinfo_data *data = PDE_DATA(file_inode(file));
         u8 *buf;
         u64 bufsize;
 
@@ -524,9 +519,7 @@ salinfo_log_clear(struct salinfo_data *data, int cpu)
 static ssize_t
 salinfo_log_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
 {
-        struct inode *inode = file_inode(file);
-        struct proc_dir_entry *entry = PDE(inode);
-        struct salinfo_data *data = entry->data;
+        struct salinfo_data *data = PDE_DATA(file_inode(file));
         char cmd[32];
         size_t size;
         u32 offset;
@@ -637,8 +630,9 @@ salinfo_init(void)
 
         for (i=0; i < NR_SALINFO_ENTRIES; i++) {
                 /* pass the feature bit in question as misc data */
-                *sdir++ = create_proc_read_entry (salinfo_entries[i].name, 0, salinfo_dir,
-                                                  salinfo_read, (void *)salinfo_entries[i].feature);
+                *sdir++ = proc_create_data(salinfo_entries[i].name, 0, salinfo_dir,
+                                           &proc_salinfo_fops,
+                                           (void *)salinfo_entries[i].feature);
         }
 
         for (i = 0; i < ARRAY_SIZE(salinfo_log_name); i++) {
@@ -684,22 +678,23 @@ salinfo_init(void)
  * 'data' contains an integer that corresponds to the feature we're
  * testing
  */
-static int
-salinfo_read(char *page, char **start, off_t off, int count, int *eof, void *data)
+static int proc_salinfo_show(struct seq_file *m, void *v)
 {
-        int len = 0;
-
-        len = sprintf(page, (sal_platform_features & (unsigned long)data) ? "1\n" : "0\n");
-
-        if (len <= off+count) *eof = 1;
-
-        *start = page + off;
-        len   -= off;
-
-        if (len>count) len = count;
-        if (len<0) len = 0;
+        unsigned long data = (unsigned long)v;
+        seq_puts(m, (sal_platform_features & data) ? "1\n" : "0\n");
+        return 0;
+}
 
-        return len;
+static int proc_salinfo_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, proc_salinfo_show, PDE_DATA(inode));
 }
 
+static const struct file_operations proc_salinfo_fops = {
+        .open           = proc_salinfo_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
 module_init(salinfo_init);
diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c
index 2029cc0d2fc6..13bfdd22afc8 100644
--- a/arch/ia64/kernel/setup.c
+++ b/arch/ia64/kernel/setup.c
@@ -1063,6 +1063,7 @@ check_bugs (void)
 static int __init run_dmi_scan(void)
 {
         dmi_scan_machine();
+        dmi_set_dump_stack_arch_desc();
         return 0;
 }
 core_initcall(run_dmi_scan);
diff --git a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c
index 500f1e4d9f9d..8d87168d218d 100644
--- a/arch/ia64/kernel/smpboot.c
+++ b/arch/ia64/kernel/smpboot.c
@@ -455,7 +455,7 @@ start_secondary (void *unused)
         preempt_disable();
         smp_callin();
 
-        cpu_idle();
+        cpu_startup_entry(CPUHP_ONLINE);
         return 0;
 }
 
diff --git a/arch/ia64/kvm/Kconfig b/arch/ia64/kvm/Kconfig
index 2cd225f8c68d..990b86420cc6 100644
--- a/arch/ia64/kvm/Kconfig
+++ b/arch/ia64/kvm/Kconfig
@@ -21,12 +21,11 @@ config KVM
         tristate "Kernel-based Virtual Machine (KVM) support"
         depends on BROKEN
         depends on HAVE_KVM && MODULES
-        # for device assignment:
-        depends on PCI
         depends on BROKEN
         select PREEMPT_NOTIFIERS
         select ANON_INODES
         select HAVE_KVM_IRQCHIP
+        select HAVE_KVM_IRQ_ROUTING
         select KVM_APIC_ARCHITECTURE
         select KVM_MMIO
         ---help---
@@ -50,6 +49,17 @@ config KVM_INTEL
           Provides support for KVM on Itanium 2 processors equipped with the VT
           extensions.
 
+config KVM_DEVICE_ASSIGNMENT
+        bool "KVM legacy PCI device assignment support"
+        depends on KVM && PCI && IOMMU_API
+        default y
+        ---help---
+          Provide support for legacy PCI device assignment through KVM.  The
+          kernel now also supports a full featured userspace device driver
+          framework through VFIO, which supersedes much of this support.
+
+          If unsure, say Y.
+
 source drivers/vhost/Kconfig
 
 endif # VIRTUALIZATION
diff --git a/arch/ia64/kvm/Makefile b/arch/ia64/kvm/Makefile
index db3d7c5d1071..1a4053789d01 100644
--- a/arch/ia64/kvm/Makefile
+++ b/arch/ia64/kvm/Makefile
@@ -49,10 +49,10 @@ ccflags-y := -Ivirt/kvm -Iarch/ia64/kvm/
 asflags-y := -Ivirt/kvm -Iarch/ia64/kvm/
 
 common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o ioapic.o \
-                coalesced_mmio.o irq_comm.o assigned-dev.o)
+                coalesced_mmio.o irq_comm.o)
 
-ifeq ($(CONFIG_IOMMU_API),y)
-common-objs += $(addprefix ../../../virt/kvm/, iommu.o)
+ifeq ($(CONFIG_KVM_DEVICE_ASSIGNMENT),y)
+common-objs += $(addprefix ../../../virt/kvm/, assigned-dev.o iommu.o)
 endif
 
 kvm-objs := $(common-objs) kvm-ia64.o kvm_fw.o
diff --git a/arch/ia64/kvm/kvm-ia64.c b/arch/ia64/kvm/kvm-ia64.c
index ad3126a58644..5b2dc0d10c8f 100644
--- a/arch/ia64/kvm/kvm-ia64.c
+++ b/arch/ia64/kvm/kvm-ia64.c
@@ -204,9 +204,11 @@ int kvm_dev_ioctl_check_extension(long ext)
         case KVM_CAP_COALESCED_MMIO:
                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
                 break;
+#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
         case KVM_CAP_IOMMU:
                 r = iommu_present(&pci_bus_type);
                 break;
+#endif
         default:
                 r = 0;
         }
@@ -924,13 +926,15 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
         return 0;
 }
 
-int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
+int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
+                bool line_status)
 {
         if (!irqchip_in_kernel(kvm))
                 return -ENXIO;
 
         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
-                                        irq_event->irq, irq_event->level);
+                                        irq_event->irq, irq_event->level,
+                                        line_status);
         return 0;
 }
 
@@ -942,24 +946,6 @@ long kvm_arch_vm_ioctl(struct file *filp,
         int r = -ENOTTY;
 
         switch (ioctl) {
-        case KVM_SET_MEMORY_REGION: {
-                struct kvm_memory_region kvm_mem;
-                struct kvm_userspace_memory_region kvm_userspace_mem;
-
-                r = -EFAULT;
-                if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
-                        goto out;
-                kvm_userspace_mem.slot = kvm_mem.slot;
-                kvm_userspace_mem.flags = kvm_mem.flags;
-                kvm_userspace_mem.guest_phys_addr =
-                                        kvm_mem.guest_phys_addr;
-                kvm_userspace_mem.memory_size = kvm_mem.memory_size;
-                r = kvm_vm_ioctl_set_memory_region(kvm,
-                                        &kvm_userspace_mem, false);
-                if (r)
-                        goto out;
-                break;
-                }
         case KVM_CREATE_IRQCHIP:
                 r = -EFAULT;
                 r = kvm_ioapic_init(kvm);
@@ -1384,9 +1370,7 @@ void kvm_arch_sync_events(struct kvm *kvm)
 void kvm_arch_destroy_vm(struct kvm *kvm)
 {
         kvm_iommu_unmap_guest(kvm);
-#ifdef  KVM_CAP_DEVICE_ASSIGNMENT
         kvm_free_all_assigned_devices(kvm);
-#endif
         kfree(kvm->arch.vioapic);
         kvm_release_vm_pages(kvm);
 }
@@ -1578,9 +1562,8 @@ int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
 
 int kvm_arch_prepare_memory_region(struct kvm *kvm,
                 struct kvm_memory_slot *memslot,
-                struct kvm_memory_slot old,
                 struct kvm_userspace_memory_region *mem,
-                bool user_alloc)
+                enum kvm_mr_change change)
 {
         unsigned long i;
         unsigned long pfn;
@@ -1610,8 +1593,8 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
 
 void kvm_arch_commit_memory_region(struct kvm *kvm,
                 struct kvm_userspace_memory_region *mem,
-                struct kvm_memory_slot old,
-                bool user_alloc)
+                const struct kvm_memory_slot *old,
+                enum kvm_mr_change change)
 {
         return;
 }
diff --git a/arch/ia64/kvm/lapic.h b/arch/ia64/kvm/lapic.h
index c3e2935b6db4..c5f92a926a9a 100644
--- a/arch/ia64/kvm/lapic.h
+++ b/arch/ia64/kvm/lapic.h
@@ -27,10 +27,4 @@ int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq);
 #define kvm_apic_present(x) (true)
 #define kvm_lapic_enabled(x) (true)
 
-static inline bool kvm_apic_vid_enabled(void)
-{
-        /* IA64 has no apicv supporting, do nothing here */
-        return false;
-}
-
 #endif
diff --git a/arch/ia64/kvm/vtlb.c b/arch/ia64/kvm/vtlb.c
index 4332f7ee5203..a7869f8f49a6 100644
--- a/arch/ia64/kvm/vtlb.c
+++ b/arch/ia64/kvm/vtlb.c
@@ -256,7 +256,7 @@ u64 guest_vhpt_lookup(u64 iha, u64 *pte)
                         "srlz.d;;"
                         "ssm psr.i;;"
                         "srlz.d;;"
-                        : "=r"(ret) : "r"(iha), "r"(pte):"memory");
+                        : "=&r"(ret) : "r"(iha), "r"(pte) : "memory");
 
         return ret;
 }
diff --git a/arch/ia64/mm/contig.c b/arch/ia64/mm/contig.c
index 80dab509dfb0..67c59ebec899 100644
--- a/arch/ia64/mm/contig.c
+++ b/arch/ia64/mm/contig.c
@@ -47,6 +47,8 @@ void show_mem(unsigned int filter)
         printk(KERN_INFO "Mem-info:\n");
         show_free_areas(filter);
         printk(KERN_INFO "Node memory in pages:\n");
+        if (filter & SHOW_MEM_FILTER_PAGE_COUNT)
+                return;
         for_each_online_pgdat(pgdat) {
                 unsigned long present;
                 unsigned long flags;
diff --git a/arch/ia64/mm/discontig.c b/arch/ia64/mm/discontig.c
index c2e955ee79a8..ae4db4bd6d97 100644
--- a/arch/ia64/mm/discontig.c
+++ b/arch/ia64/mm/discontig.c
@@ -623,6 +623,8 @@ void show_mem(unsigned int filter)
 
         printk(KERN_INFO "Mem-info:\n");
         show_free_areas(filter);
+        if (filter & SHOW_MEM_FILTER_PAGE_COUNT)
+                return;
         printk(KERN_INFO "Node memory in pages:\n");
         for_each_online_pgdat(pgdat) {
                 unsigned long present;
@@ -817,13 +819,12 @@ void arch_refresh_nodedata(int update_node, pg_data_t *update_pgdat)
 #endif
 
 #ifdef CONFIG_SPARSEMEM_VMEMMAP
-int __meminit vmemmap_populate(struct page *start_page,
-                                                unsigned long size, int node)
+int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node)
 {
-        return vmemmap_populate_basepages(start_page, size, node);
+        return vmemmap_populate_basepages(start, end, node);
 }
 
-void vmemmap_free(struct page *memmap, unsigned long nr_pages)
+void vmemmap_free(unsigned long start, unsigned long end)
 {
 }
 #endif
diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c
index 20bc967c7209..d1fe4b402601 100644
--- a/arch/ia64/mm/init.c
+++ b/arch/ia64/mm/init.c
@@ -154,25 +154,14 @@ ia64_init_addr_space (void)
 void
 free_initmem (void)
 {
-        unsigned long addr, eaddr;
-
-        addr = (unsigned long) ia64_imva(__init_begin);
-        eaddr = (unsigned long) ia64_imva(__init_end);
-        while (addr < eaddr) {
-                ClearPageReserved(virt_to_page(addr));
-                init_page_count(virt_to_page(addr));
-                free_page(addr);
-                ++totalram_pages;
-                addr += PAGE_SIZE;
-        }
-        printk(KERN_INFO "Freeing unused kernel memory: %ldkB freed\n",
-               (__init_end - __init_begin) >> 10);
+        free_reserved_area((unsigned long)ia64_imva(__init_begin),
+                           (unsigned long)ia64_imva(__init_end),
+                           0, "unused kernel");
 }
 
 void __init
 free_initrd_mem (unsigned long start, unsigned long end)
 {
-        struct page *page;
         /*
          * EFI uses 4KB pages while the kernel can use 4KB or bigger.
          * Thus EFI and the kernel may have different page sizes. It is
@@ -213,11 +202,7 @@ free_initrd_mem (unsigned long start, unsigned long end)
         for (; start < end; start += PAGE_SIZE) {
                 if (!virt_addr_valid(start))
                         continue;
-                page = virt_to_page(start);
-                ClearPageReserved(page);
-                init_page_count(page);
-                free_page(start);
-                ++totalram_pages;
+                free_reserved_page(virt_to_page(start));
         }
 }
 
diff --git a/arch/ia64/mm/ioremap.c b/arch/ia64/mm/ioremap.c
index 3dccdd8eb275..43964cde6214 100644
--- a/arch/ia64/mm/ioremap.c
+++ b/arch/ia64/mm/ioremap.c
@@ -16,7 +16,7 @@
 #include <asm/meminit.h>
 
 static inline void __iomem *
-__ioremap (unsigned long phys_addr)
+__ioremap_uc(unsigned long phys_addr)
 {
         return (void __iomem *) (__IA64_UNCACHED_OFFSET | phys_addr);
 }
@@ -24,7 +24,11 @@ __ioremap (unsigned long phys_addr)
 void __iomem *
 early_ioremap (unsigned long phys_addr, unsigned long size)
 {
-        return __ioremap(phys_addr);
+        u64 attr;
+        attr = kern_mem_attribute(phys_addr, size);
+        if (attr & EFI_MEMORY_WB)
+                return (void __iomem *) phys_to_virt(phys_addr);
+        return __ioremap_uc(phys_addr);
 }
 
 void __iomem *
@@ -47,7 +51,7 @@ ioremap (unsigned long phys_addr, unsigned long size)
         if (attr & EFI_MEMORY_WB)
                 return (void __iomem *) phys_to_virt(phys_addr);
         else if (attr & EFI_MEMORY_UC)
-                return __ioremap(phys_addr);
+                return __ioremap_uc(phys_addr);
 
         /*
          * Some chipsets don't support UC access to memory.  If
@@ -93,7 +97,7 @@ ioremap (unsigned long phys_addr, unsigned long size)
                 return (void __iomem *) (offset + (char __iomem *)addr);
         }
 
-        return __ioremap(phys_addr);
+        return __ioremap_uc(phys_addr);
 }
 EXPORT_SYMBOL(ioremap);
 
@@ -103,7 +107,7 @@ ioremap_nocache (unsigned long phys_addr, unsigned long size)
         if (kern_mem_attribute(phys_addr, size) & EFI_MEMORY_WB)
                 return NULL;
 
-        return __ioremap(phys_addr);
+        return __ioremap_uc(phys_addr);
 }
 EXPORT_SYMBOL(ioremap_nocache);
 
diff --git a/arch/ia64/mm/numa.c b/arch/ia64/mm/numa.c
index 3efea7d0a351..4248492b9321 100644
--- a/arch/ia64/mm/numa.c
+++ b/arch/ia64/mm/numa.c
@@ -61,18 +61,36 @@ paddr_to_nid(unsigned long paddr)
 int __meminit __early_pfn_to_nid(unsigned long pfn)
 {
         int i, section = pfn >> PFN_SECTION_SHIFT, ssec, esec;
+        /*
+         * NOTE: The following SMP-unsafe globals are only used early in boot
+         * when the kernel is running single-threaded.
+         */
+        static int __meminitdata last_ssec, last_esec;
+        static int __meminitdata last_nid;
+
+        if (section >= last_ssec && section < last_esec)
+                return last_nid;
 
         for (i = 0; i < num_node_memblks; i++) {
                 ssec = node_memblk[i].start_paddr >> PA_SECTION_SHIFT;
                 esec = (node_memblk[i].start_paddr + node_memblk[i].size +
                         ((1L << PA_SECTION_SHIFT) - 1)) >> PA_SECTION_SHIFT;
-                if (section >= ssec && section < esec)
+                if (section >= ssec && section < esec) {
+                        last_ssec = ssec;
+                        last_esec = esec;
+                        last_nid = node_memblk[i].nid;
                         return node_memblk[i].nid;
+                }
         }
 
         return -1;
 }
 
+void __cpuinit numa_clear_node(int cpu)
+{
+        unmap_cpu_from_node(cpu, NUMA_NO_NODE);
+}
+
 #ifdef CONFIG_MEMORY_HOTPLUG
 /*
  *  SRAT information is stored in node_memblk[], then we can use SRAT
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index 60532ab27346..de1474ff0bc5 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -15,6 +15,7 @@
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/pci.h>
+#include <linux/pci-acpi.h>
 #include <linux/init.h>
 #include <linux/ioport.h>
 #include <linux/slab.h>
@@ -458,6 +459,16 @@ void pcibios_fixup_bus(struct pci_bus *b)
         platform_pci_fixup_bus(b);
 }
 
+void pcibios_add_bus(struct pci_bus *bus)
+{
+        acpi_pci_add_bus(bus);
+}
+
+void pcibios_remove_bus(struct pci_bus *bus)
+{
+        acpi_pci_remove_bus(bus);
+}
+
 void pcibios_set_master (struct pci_dev *dev)
 {
         /* No special bus mastering setup handling */
diff --git a/arch/ia64/sn/kernel/sn2/prominfo_proc.c b/arch/ia64/sn/kernel/sn2/prominfo_proc.c
index 20b88cb1881a..ec4de2b09653 100644
--- a/arch/ia64/sn/kernel/sn2/prominfo_proc.c
+++ b/arch/ia64/sn/kernel/sn2/prominfo_proc.c
@@ -11,6 +11,7 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <linux/proc_fs.h>
+#include <linux/seq_file.h>
 #include <linux/nodemask.h>
 #include <asm/io.h>
 #include <asm/sn/sn_sal.h>
@@ -101,18 +102,18 @@ get_fit_entry(unsigned long nasid, int index, unsigned long *fentry,
 /*
  * These two routines display the FIT table for each node.
  */
-static int dump_fit_entry(char *page, unsigned long *fentry)
+static void dump_fit_entry(struct seq_file *m, unsigned long *fentry)
 {
         unsigned type;
 
         type = FIT_TYPE(fentry[1]);
-        return sprintf(page, "%02x %-25s %x.%02x %016lx %u\n",
-                       type,
-                       fit_type_name(type),
-                       FIT_MAJOR(fentry[1]), FIT_MINOR(fentry[1]),
-                       fentry[0],
-                       /* mult by sixteen to get size in bytes */
-                       (unsigned)(fentry[1] & 0xffffff) * 16);
+        seq_printf(m, "%02x %-25s %x.%02x %016lx %u\n",
+                   type,
+                   fit_type_name(type),
+                   FIT_MAJOR(fentry[1]), FIT_MINOR(fentry[1]),
+                   fentry[0],
+                   /* mult by sixteen to get size in bytes */
+                   (unsigned)(fentry[1] & 0xffffff) * 16);
 }
 
 
@@ -124,31 +125,39 @@ static int dump_fit_entry(char *page, unsigned long *fentry)
  * OK except for 4kB pages (and no one is going to do that on SN
  * anyway).
  */
-static int
-dump_fit(char *page, unsigned long nasid)
+static int proc_fit_show(struct seq_file *m, void *v)
 {
+        unsigned long nasid = (unsigned long)m->private;
         unsigned long fentry[2];
         int index;
-        char *p;
 
-        p = page;
         for (index=0;;index++) {
                 BUG_ON(index * 60 > PAGE_SIZE);
                 if (get_fit_entry(nasid, index, fentry, NULL, 0))
                         break;
-                p += dump_fit_entry(p, fentry);
+                dump_fit_entry(m, fentry);
         }
+        return 0;
+}
 
-        return p - page;
+static int proc_fit_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, proc_fit_show, PDE_DATA(inode));
 }
 
-static int
-dump_version(char *page, unsigned long nasid)
+static const struct file_operations proc_fit_fops = {
+        .open           = proc_fit_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static int proc_version_show(struct seq_file *m, void *v)
 {
+        unsigned long nasid = (unsigned long)m->private;
         unsigned long fentry[2];
         char banner[128];
         int index;
-        int len;
 
         for (index = 0; ; index++) {
                 if (get_fit_entry(nasid, index, fentry, banner,
@@ -158,56 +167,24 @@ dump_version(char *page, unsigned long nasid)
                         break;
         }
 
-        len = sprintf(page, "%x.%02x\n", FIT_MAJOR(fentry[1]),
-                      FIT_MINOR(fentry[1]));
-        page += len;
+        seq_printf(m, "%x.%02x\n", FIT_MAJOR(fentry[1]), FIT_MINOR(fentry[1]));
 
         if (banner[0])
-                len += snprintf(page, PAGE_SIZE-len, "%s\n", banner);
-
-        return len;
-}
-
-/* same as in proc_misc.c */
-static int
-proc_calc_metrics(char *page, char **start, off_t off, int count, int *eof,
-                  int len)
-{
-        if (len <= off + count)
-                *eof = 1;
-        *start = page + off;
-        len -= off;
-        if (len > count)
-                len = count;
-        if (len < 0)
-                len = 0;
-        return len;
+                seq_printf(m, "%s\n", banner);
+        return 0;
 }
 
-static int
-read_version_entry(char *page, char **start, off_t off, int count, int *eof,
-                   void *data)
+static int proc_version_open(struct inode *inode, struct file *file)
 {
-        int len;
-
-        /* data holds the NASID of the node */
-        len = dump_version(page, (unsigned long)data);
-        len = proc_calc_metrics(page, start, off, count, eof, len);
-        return len;
+        return single_open(file, proc_version_show, PDE_DATA(inode));
 }
 
-static int
-read_fit_entry(char *page, char **start, off_t off, int count, int *eof,
-               void *data)
-{
-        int len;
-
-        /* data holds the NASID of the node */
-        len = dump_fit(page, (unsigned long)data);
-        len = proc_calc_metrics(page, start, off, count, eof, len);
-
-        return len;
-}
+static const struct file_operations proc_version_fops = {
+        .open           = proc_version_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
 
 /* module entry points */
 int __init prominfo_init(void);
@@ -216,58 +193,39 @@ void __exit prominfo_exit(void);
 module_init(prominfo_init);
 module_exit(prominfo_exit);
 
-static struct proc_dir_entry **proc_entries;
-static struct proc_dir_entry *sgi_prominfo_entry;
-
 #define NODE_NAME_LEN 11
 
 int __init prominfo_init(void)
 {
-        struct proc_dir_entry **entp;
+        struct proc_dir_entry *sgi_prominfo_entry;
         cnodeid_t cnodeid;
-        unsigned long nasid;
-        int size;
-        char name[NODE_NAME_LEN];
 
         if (!ia64_platform_is("sn2"))
                 return 0;
 
-        size = num_online_nodes() * sizeof(struct proc_dir_entry *);
-        proc_entries = kzalloc(size, GFP_KERNEL);
-        if (!proc_entries)
-                return -ENOMEM;
-
         sgi_prominfo_entry = proc_mkdir("sgi_prominfo", NULL);
+        if (!sgi_prominfo_entry)
+                return -ENOMEM;
 
-        entp = proc_entries;
         for_each_online_node(cnodeid) {
+                struct proc_dir_entry *dir;
+                unsigned long nasid;
+                char name[NODE_NAME_LEN];
+
                 sprintf(name, "node%d", cnodeid);
-                *entp = proc_mkdir(name, sgi_prominfo_entry);
+                dir = proc_mkdir(name, sgi_prominfo_entry);
+                if (!dir)
+                        continue;
                 nasid = cnodeid_to_nasid(cnodeid);
-                create_proc_read_entry("fit", 0, *entp, read_fit_entry,
-                                           (void *)nasid);
-                create_proc_read_entry("version", 0, *entp,
-                                           read_version_entry, (void *)nasid);
-                entp++;
+                proc_create_data("fit", 0, dir,
+                                 &proc_fit_fops, (void *)nasid);
+                proc_create_data("version", 0, dir,
+                                 &proc_version_fops, (void *)nasid);
         }
-
         return 0;
 }
 
 void __exit prominfo_exit(void)
 {
-        struct proc_dir_entry **entp;
-        unsigned int cnodeid;
-        char name[NODE_NAME_LEN];
-
-        entp = proc_entries;
-        for_each_online_node(cnodeid) {
-                remove_proc_entry("fit", *entp);
-                remove_proc_entry("version", *entp);
-                sprintf(name, "node%d", cnodeid);
-                remove_proc_entry(name, sgi_prominfo_entry);
-                entp++;
-        }
-        remove_proc_entry("sgi_prominfo", NULL);
-        kfree(proc_entries);
+        remove_proc_subtree("sgi_prominfo", NULL);
 }
diff --git a/arch/ia64/sn/kernel/tiocx.c b/arch/ia64/sn/kernel/tiocx.c
index 14c1711238c0..e35f6485c1fd 100644
--- a/arch/ia64/sn/kernel/tiocx.c
+++ b/arch/ia64/sn/kernel/tiocx.c
@@ -490,11 +490,14 @@ static int __init tiocx_init(void)
 {
         cnodeid_t cnodeid;
         int found_tiocx_device = 0;
+        int err;
 
         if (!ia64_platform_is("sn2"))
                 return 0;
 
-        bus_register(&tiocx_bus_type);
+        err = bus_register(&tiocx_bus_type);
+        if (err)
+                return err;
 
         for (cnodeid = 0; cnodeid < num_cnodes; cnodeid++) {
                 nasid_t nasid;
diff --git a/arch/m32r/include/asm/unistd.h b/arch/m32r/include/asm/unistd.h
index 555629b05267..59db80193454 100644
--- a/arch/m32r/include/asm/unistd.h
+++ b/arch/m32r/include/asm/unistd.h
@@ -48,14 +48,4 @@
 #define __IGNORE_getresgid
 #define __IGNORE_chown
 
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#ifndef cond_syscall
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
-#endif
-
 #endif /* _ASM_M32R_UNISTD_H */
diff --git a/arch/m32r/kernel/process.c b/arch/m32r/kernel/process.c
index bde899e155d3..e69221d581d5 100644
--- a/arch/m32r/kernel/process.c
+++ b/arch/m32r/kernel/process.c
@@ -47,24 +47,6 @@ unsigned long thread_saved_pc(struct task_struct *tsk)
 void (*pm_power_off)(void) = NULL;
 EXPORT_SYMBOL(pm_power_off);
 
-/*
- * The idle thread. There's no useful work to be
- * done, so just try to conserve power and have a
- * low exit latency (ie sit in a loop waiting for
- * somebody to say that they'd like to reschedule)
- */
-void cpu_idle (void)
-{
-        /* endless idle loop with no priority at all */
-        while (1) {
-                rcu_idle_enter();
-                while (!need_resched())
-                        cpu_relax();
-                rcu_idle_exit();
-                schedule_preempt_disabled();
-        }
-}
-
 void machine_restart(char *__unused)
 {
 #if defined(CONFIG_PLAT_MAPPI3)
@@ -91,6 +73,8 @@ void machine_power_off(void)
 void show_regs(struct pt_regs * regs)
 {
         printk("\n");
+        show_regs_print_info(KERN_DEFAULT);
+
         printk("BPC[%08lx]:PSW[%08lx]:LR [%08lx]:FP [%08lx]\n", \
           regs->bpc, regs->psw, regs->lr, regs->fp);
         printk("BBPC[%08lx]:BBPSW[%08lx]:SPU[%08lx]:SPI[%08lx]\n", \
diff --git a/arch/m32r/kernel/smpboot.c b/arch/m32r/kernel/smpboot.c
index 13168a769f8f..0ac558adc605 100644
--- a/arch/m32r/kernel/smpboot.c
+++ b/arch/m32r/kernel/smpboot.c
@@ -432,7 +432,7 @@ int __init start_secondary(void *unused)
          */
         local_flush_tlb_all();
 
-        cpu_idle();
+        cpu_startup_entry(CPUHP_ONLINE);
         return 0;
 }
 
diff --git a/arch/m32r/kernel/traps.c b/arch/m32r/kernel/traps.c
index 3bcb207e5b6d..a7a424f852e4 100644
--- a/arch/m32r/kernel/traps.c
+++ b/arch/m32r/kernel/traps.c
@@ -132,10 +132,8 @@ static void show_trace(struct task_struct *task, unsigned long *stack)
         printk("Call Trace: ");
         while (!kstack_end(stack)) {
                 addr = *stack++;
-                if (__kernel_text_address(addr)) {
-                        printk("[<%08lx>] ", addr);
-                        print_symbol("%s\n", addr);
-                }
+                if (__kernel_text_address(addr))
+                        printk("[<%08lx>] %pSR\n", addr, (void *)addr);
         }
         printk("\n");
 }
@@ -169,15 +167,6 @@ void show_stack(struct task_struct *task, unsigned long *sp)
         show_trace(task, sp);
 }
 
-void dump_stack(void)
-{
-        unsigned long stack;
-
-        show_trace(current, &stack);
-}
-
-EXPORT_SYMBOL(dump_stack);
-
 static void show_registers(struct pt_regs *regs)
 {
         int i = 0;
diff --git a/arch/m32r/mm/init.c b/arch/m32r/mm/init.c
index 78b660e903da..ab4cbce91a9b 100644
--- a/arch/m32r/mm/init.c
+++ b/arch/m32r/mm/init.c
@@ -28,10 +28,7 @@
 #include <asm/mmu_context.h>
 #include <asm/setup.h>
 #include <asm/tlb.h>
-
-/* References to section boundaries */
-extern char _text, _etext, _edata;
-extern char __init_begin, __init_end;
+#include <asm/sections.h>
 
 pgd_t swapper_pg_dir[1024];
 
@@ -184,17 +181,7 @@ void __init mem_init(void)
  *======================================================================*/
 void free_initmem(void)
 {
-        unsigned long addr;
-
-        addr = (unsigned long)(&__init_begin);
-        for (; addr < (unsigned long)(&__init_end); addr += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(addr));
-                init_page_count(virt_to_page(addr));
-                free_page(addr);
-                totalram_pages++;
-        }
-        printk (KERN_INFO "Freeing unused kernel memory: %dk freed\n", \
-          (int)(&__init_end - &__init_begin) >> 10);
+        free_initmem_default(0);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
@@ -204,13 +191,6 @@ void free_initmem(void)
  *======================================================================*/
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        unsigned long p;
-        for (p = start; p < end; p += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(p));
-                init_page_count(virt_to_page(p));
-                free_page(p);
-                totalram_pages++;
-        }
-        printk (KERN_INFO "Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
+        free_reserved_area(start, end, 0, "initrd");
 }
 #endif
diff --git a/arch/m68k/Kconfig.bus b/arch/m68k/Kconfig.bus
index 93ef0346b209..675b087198f6 100644
--- a/arch/m68k/Kconfig.bus
+++ b/arch/m68k/Kconfig.bus
@@ -45,6 +45,16 @@ config ISA
           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
           newer boards don't support it.  If you have ISA, say Y, otherwise N.
 
+config ATARI_ROM_ISA
+        bool "Atari ROM port ISA adapter support"
+        depends on ATARI
+        help
+          This option enables support for the ROM port ISA adapter used to
+          operate ISA cards on Atari. Only 8  bit cards are supported, and
+          no interrupt lines are connected.
+          The only driver currently using this adapter is the EtherNEC
+          driver for RTL8019AS based NE2000 compatible network cards.
+
 config GENERIC_ISA_DMA
         def_bool ISA
 
diff --git a/arch/m68k/Kconfig.devices b/arch/m68k/Kconfig.devices
index 4bc945dfe467..d163991c5717 100644
--- a/arch/m68k/Kconfig.devices
+++ b/arch/m68k/Kconfig.devices
@@ -55,6 +55,30 @@ config NFETH
           which will emulate a regular ethernet device while presenting an
           ethertap device to the host system.
 
+config ATARI_ETHERNAT
+        bool "Atari EtherNAT Ethernet support"
+        depends on ATARI
+        ---help---
+          Say Y to include support for the EtherNAT network adapter for the
+          CT/60 extension port.
+
+          To compile the actual ethernet driver, choose Y or M for the SMC91X
+          option in the network device section; the module will be called smc91x.
+
+config ATARI_ETHERNEC
+        bool "Atari EtherNEC Ethernet support"
+        depends on ATARI_ROM_ISA
+        ---help---
+          Say Y to include support for the EtherNEC network adapter for the
+          ROM port. The driver works by polling instead of interrupts, so it
+          is quite slow.
+
+          This driver also suppports the ethernet part of the NetUSBee ROM
+          port combined Ethernet/USB adapter.
+
+          To compile the actual ethernet driver, choose Y or M in for the NE2000
+          option in the network device section; the module will be called ne.
+
 endmenu
 
 menu "Character devices"
diff --git a/arch/m68k/atari/ataints.c b/arch/m68k/atari/ataints.c
index 3f41092d1b70..20cde4e9fc77 100644
--- a/arch/m68k/atari/ataints.c
+++ b/arch/m68k/atari/ataints.c
@@ -49,6 +49,7 @@
 #include <asm/atari_stdma.h>
 #include <asm/irq.h>
 #include <asm/entry.h>
+#include <asm/io.h>
 
 
 /*
@@ -122,6 +123,136 @@ static struct irq_chip atari_irq_chip = {
 };
 
 /*
+ * ST-MFP timer D chained interrupts - each driver gets its own timer
+ * interrupt instance.
+ */
+
+struct mfptimerbase {
+        volatile struct MFP *mfp;
+        unsigned char mfp_mask, mfp_data;
+        unsigned short int_mask;
+        int handler_irq, mfptimer_irq, server_irq;
+        char *name;
+} stmfp_base = {
+        .mfp            = &st_mfp,
+        .int_mask       = 0x0,
+        .handler_irq    = IRQ_MFP_TIMD,
+        .mfptimer_irq   = IRQ_MFP_TIMER1,
+        .name           = "MFP Timer D"
+};
+
+static irqreturn_t mfptimer_handler(int irq, void *dev_id)
+{
+        struct mfptimerbase *base = dev_id;
+        int mach_irq;
+        unsigned char ints;
+
+        mach_irq = base->mfptimer_irq;
+        ints = base->int_mask;
+        for (; ints; mach_irq++, ints >>= 1) {
+                if (ints & 1)
+                        generic_handle_irq(mach_irq);
+        }
+        return IRQ_HANDLED;
+}
+
+
+static void atari_mfptimer_enable(struct irq_data *data)
+{
+        int mfp_num = data->irq - IRQ_MFP_TIMER1;
+        stmfp_base.int_mask |= 1 << mfp_num;
+        atari_enable_irq(IRQ_MFP_TIMD);
+}
+
+static void atari_mfptimer_disable(struct irq_data *data)
+{
+        int mfp_num = data->irq - IRQ_MFP_TIMER1;
+        stmfp_base.int_mask &= ~(1 << mfp_num);
+        if (!stmfp_base.int_mask)
+                atari_disable_irq(IRQ_MFP_TIMD);
+}
+
+static struct irq_chip atari_mfptimer_chip = {
+        .name           = "timer_d",
+        .irq_enable     = atari_mfptimer_enable,
+        .irq_disable    = atari_mfptimer_disable,
+};
+
+
+/*
+ * EtherNAT CPLD interrupt handling
+ * CPLD interrupt register is at phys. 0x80000023
+ * Need this mapped in at interrupt startup time
+ * Possibly need this mapped on demand anyway -
+ * EtherNAT USB driver needs to disable IRQ before
+ * startup!
+ */
+
+static unsigned char *enat_cpld;
+
+static unsigned int atari_ethernat_startup(struct irq_data *data)
+{
+        int enat_num = 140 - data->irq + 1;
+
+        m68k_irq_startup(data);
+        /*
+        * map CPLD interrupt register
+        */
+        if (!enat_cpld)
+                enat_cpld = (unsigned char *)ioremap((ATARI_ETHERNAT_PHYS_ADDR+0x23), 0x2);
+        /*
+         * do _not_ enable the USB chip interrupt here - causes interrupt storm
+         * and triggers dead interrupt watchdog
+         * Need to reset the USB chip to a sane state in early startup before
+         * removing this hack
+         */
+        if (enat_num == 1)
+                *enat_cpld |= 1 << enat_num;
+
+        return 0;
+}
+
+static void atari_ethernat_enable(struct irq_data *data)
+{
+        int enat_num = 140 - data->irq + 1;
+        /*
+        * map CPLD interrupt register
+        */
+        if (!enat_cpld)
+                enat_cpld = (unsigned char *)ioremap((ATARI_ETHERNAT_PHYS_ADDR+0x23), 0x2);
+        *enat_cpld |= 1 << enat_num;
+}
+
+static void atari_ethernat_disable(struct irq_data *data)
+{
+        int enat_num = 140 - data->irq + 1;
+        /*
+        * map CPLD interrupt register
+        */
+        if (!enat_cpld)
+                enat_cpld = (unsigned char *)ioremap((ATARI_ETHERNAT_PHYS_ADDR+0x23), 0x2);
+        *enat_cpld &= ~(1 << enat_num);
+}
+
+static void atari_ethernat_shutdown(struct irq_data *data)
+{
+        int enat_num = 140 - data->irq + 1;
+        if (enat_cpld) {
+                *enat_cpld &= ~(1 << enat_num);
+                iounmap(enat_cpld);
+                enat_cpld = NULL;
+        }
+}
+
+static struct irq_chip atari_ethernat_chip = {
+        .name           = "ethernat",
+        .irq_startup    = atari_ethernat_startup,
+        .irq_shutdown   = atari_ethernat_shutdown,
+        .irq_enable     = atari_ethernat_enable,
+        .irq_disable    = atari_ethernat_disable,
+};
+
+/*
  * void atari_init_IRQ (void)
  *
  * Parameters:  None
@@ -198,6 +329,27 @@ void __init atari_init_IRQ(void)
         /* Initialize the PSG: all sounds off, both ports output */
         sound_ym.rd_data_reg_sel = 7;
         sound_ym.wd_data = 0xff;
+
+        m68k_setup_irq_controller(&atari_mfptimer_chip, handle_simple_irq,
+                                  IRQ_MFP_TIMER1, 8);
+
+        /* prepare timer D data for use as poll interrupt */
+        /* set Timer D data Register - needs to be > 0 */
+        st_mfp.tim_dt_d = 254;  /* < 100 Hz */
+        /* start timer D, div = 1:100 */
+        st_mfp.tim_ct_cd = (st_mfp.tim_ct_cd & 0xf0) | 0x6;
+
+        /* request timer D dispatch handler */
+        if (request_irq(IRQ_MFP_TIMD, mfptimer_handler, IRQF_SHARED,
+                        stmfp_base.name, &stmfp_base))
+                pr_err("Couldn't register %s interrupt\n", stmfp_base.name);
+
+        /*
+         * EtherNAT ethernet / USB interrupt handlers
+         */
+
+        m68k_setup_irq_controller(&atari_ethernat_chip, handle_simple_irq,
+                                  139, 2);
 }
 
 
diff --git a/arch/m68k/atari/config.c b/arch/m68k/atari/config.c
index 037c11c99331..fb2d0bd9b3ad 100644
--- a/arch/m68k/atari/config.c
+++ b/arch/m68k/atari/config.c
@@ -31,6 +31,8 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/usb/isp116x.h>
 #include <linux/vt_kern.h>
 #include <linux/module.h>
 
@@ -655,3 +657,240 @@ static void atari_get_hardware_list(struct seq_file *m)
         ATARIHW_ANNOUNCE(VME, "VME Bus");
         ATARIHW_ANNOUNCE(DSP56K, "DSP56001 processor");
 }
+
+/*
+ * MSch: initial platform device support for Atari,
+ * required for EtherNAT/EtherNEC/NetUSBee drivers
+ */
+
+#if defined(CONFIG_ATARI_ETHERNAT) || defined(CONFIG_ATARI_ETHERNEC)
+static void isp1160_delay(struct device *dev, int delay)
+{
+        ndelay(delay);
+}
+#endif
+
+#ifdef CONFIG_ATARI_ETHERNAT
+/*
+ * EtherNAT: SMC91C111 Ethernet chipset, handled by smc91x driver
+ */
+
+#define ATARI_ETHERNAT_IRQ              140
+
+static struct resource smc91x_resources[] = {
+        [0] = {
+                .name   = "smc91x-regs",
+                .start  = ATARI_ETHERNAT_PHYS_ADDR,
+                .end    = ATARI_ETHERNAT_PHYS_ADDR + 0xfffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .name   = "smc91x-irq",
+                .start  = ATARI_ETHERNAT_IRQ,
+                .end    = ATARI_ETHERNAT_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device smc91x_device = {
+        .name           = "smc91x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smc91x_resources),
+        .resource       = smc91x_resources,
+};
+
+/*
+ * ISP 1160 - using the isp116x-hcd module
+ */
+
+#define ATARI_USB_PHYS_ADDR     0x80000012
+#define ATARI_USB_IRQ           139
+
+static struct resource isp1160_resources[] = {
+        [0] = {
+                .name   = "isp1160-data",
+                .start  = ATARI_USB_PHYS_ADDR,
+                .end    = ATARI_USB_PHYS_ADDR + 0x1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .name   = "isp1160-regs",
+                .start  = ATARI_USB_PHYS_ADDR + 0x4,
+                .end    = ATARI_USB_PHYS_ADDR + 0x5,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .name   = "isp1160-irq",
+                .start  = ATARI_USB_IRQ,
+                .end    = ATARI_USB_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+/* (DataBusWidth16|AnalogOCEnable|DREQOutputPolarity|DownstreamPort15KRSel ) */
+static struct isp116x_platform_data isp1160_platform_data = {
+        /* Enable internal resistors on downstream ports */
+        .sel15Kres              = 1,
+        /* On-chip overcurrent protection */
+        .oc_enable              = 1,
+        /* INT output polarity */
+        .int_act_high           = 1,
+        /* INT edge or level triggered */
+        .int_edge_triggered     = 0,
+
+        /* WAKEUP pin connected - NOT SUPPORTED  */
+        /* .remote_wakeup_connected = 0, */
+        /* Wakeup by devices on usb bus enabled */
+        .remote_wakeup_enable   = 0,
+        .delay                  = isp1160_delay,
+};
+
+static struct platform_device isp1160_device = {
+        .name           = "isp116x-hcd",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(isp1160_resources),
+        .resource       = isp1160_resources,
+        .dev                    = {
+                .platform_data  = &isp1160_platform_data,
+        },
+};
+
+static struct platform_device *atari_ethernat_devices[] __initdata = {
+        &smc91x_device,
+        &isp1160_device
+};
+#endif /* CONFIG_ATARI_ETHERNAT */
+
+#ifdef CONFIG_ATARI_ETHERNEC
+/*
+ * EtherNEC: RTL8019 (NE2000 compatible) Ethernet chipset,
+ * handled by ne.c driver
+ */
+
+#define ATARI_ETHERNEC_PHYS_ADDR        0xfffa0000
+#define ATARI_ETHERNEC_BASE             0x300
+#define ATARI_ETHERNEC_IRQ              IRQ_MFP_TIMER1
+
+static struct resource rtl8019_resources[] = {
+        [0] = {
+                .name   = "rtl8019-regs",
+                .start  = ATARI_ETHERNEC_BASE,
+                .end    = ATARI_ETHERNEC_BASE + 0x20 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        [1] = {
+                .name   = "rtl8019-irq",
+                .start  = ATARI_ETHERNEC_IRQ,
+                .end    = ATARI_ETHERNEC_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device rtl8019_device = {
+        .name           = "ne",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(rtl8019_resources),
+        .resource       = rtl8019_resources,
+};
+
+/*
+ * NetUSBee: ISP1160 USB host adapter via ROM-port adapter
+ */
+
+#define ATARI_NETUSBEE_PHYS_ADDR        0xfffa8000
+#define ATARI_NETUSBEE_BASE             0x340
+#define ATARI_NETUSBEE_IRQ              IRQ_MFP_TIMER2
+
+static struct resource netusbee_resources[] = {
+        [0] = {
+                .name   = "isp1160-data",
+                .start  = ATARI_NETUSBEE_BASE,
+                .end    = ATARI_NETUSBEE_BASE + 0x1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .name   = "isp1160-regs",
+                .start  = ATARI_NETUSBEE_BASE + 0x20,
+                .end    = ATARI_NETUSBEE_BASE + 0x21,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .name   = "isp1160-irq",
+                .start  = ATARI_NETUSBEE_IRQ,
+                .end    = ATARI_NETUSBEE_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+/* (DataBusWidth16|AnalogOCEnable|DREQOutputPolarity|DownstreamPort15KRSel ) */
+static struct isp116x_platform_data netusbee_platform_data = {
+        /* Enable internal resistors on downstream ports */
+        .sel15Kres              = 1,
+        /* On-chip overcurrent protection */
+        .oc_enable              = 1,
+        /* INT output polarity */
+        .int_act_high           = 1,
+        /* INT edge or level triggered */
+        .int_edge_triggered     = 0,
+
+        /* WAKEUP pin connected - NOT SUPPORTED  */
+        /* .remote_wakeup_connected = 0, */
+        /* Wakeup by devices on usb bus enabled */
+        .remote_wakeup_enable   = 0,
+        .delay                  = isp1160_delay,
+};
+
+static struct platform_device netusbee_device = {
+        .name           = "isp116x-hcd",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(netusbee_resources),
+        .resource       = netusbee_resources,
+        .dev                    = {
+                .platform_data  = &netusbee_platform_data,
+        },
+};
+
+static struct platform_device *atari_netusbee_devices[] __initdata = {
+        &rtl8019_device,
+        &netusbee_device
+};
+#endif /* CONFIG_ATARI_ETHERNEC */
+
+int __init atari_platform_init(void)
+{
+        int rv = 0;
+
+        if (!MACH_IS_ATARI)
+                return -ENODEV;
+
+#ifdef CONFIG_ATARI_ETHERNAT
+        {
+                unsigned char *enatc_virt;
+                enatc_virt = (unsigned char *)ioremap((ATARI_ETHERNAT_PHYS_ADDR+0x23), 0xf);
+                if (hwreg_present(enatc_virt)) {
+                        rv = platform_add_devices(atari_ethernat_devices,
+                                                ARRAY_SIZE(atari_ethernat_devices));
+                }
+                iounmap(enatc_virt);
+        }
+#endif
+
+#ifdef CONFIG_ATARI_ETHERNEC
+        {
+                int error;
+                unsigned char *enec_virt;
+                enec_virt = (unsigned char *)ioremap((ATARI_ETHERNEC_PHYS_ADDR), 0xf);
+                if (hwreg_present(enec_virt)) {
+                        error = platform_add_devices(atari_netusbee_devices,
+                                                ARRAY_SIZE(atari_netusbee_devices));
+                        if (error && !rv)
+                                rv = error;
+                }
+                iounmap(enec_virt);
+        }
+#endif
+
+        return rv;
+}
+
+arch_initcall(atari_platform_init);
diff --git a/arch/m68k/include/asm/atarihw.h b/arch/m68k/include/asm/atarihw.h
index c0cb36350775..d887050e6da6 100644
--- a/arch/m68k/include/asm/atarihw.h
+++ b/arch/m68k/include/asm/atarihw.h
@@ -805,5 +805,11 @@ struct MSTE_RTC {
 
 #define mste_rtc ((*(volatile struct MSTE_RTC *)MSTE_RTC_BAS))
 
+/*
+** EtherNAT add-on card for Falcon - combined ethernet and USB adapter
+*/
+
+#define ATARI_ETHERNAT_PHYS_ADDR        0x80000000
+
 #endif /* linux/atarihw.h */
 
diff --git a/arch/m68k/include/asm/atariints.h b/arch/m68k/include/asm/atariints.h
index 5fc13bdf9044..953e0ac6855e 100644
--- a/arch/m68k/include/asm/atariints.h
+++ b/arch/m68k/include/asm/atariints.h
@@ -32,7 +32,7 @@
 #define VME_SOURCE_BASE    56
 #define VME_MAX_SOURCES    16
 
-#define NUM_ATARI_SOURCES   (VME_SOURCE_BASE+VME_MAX_SOURCES-STMFP_SOURCE_BASE)
+#define NUM_ATARI_SOURCES  141
 
 /* convert vector number to int source number */
 #define IRQ_VECTOR_TO_SOURCE(v) ((v) - ((v) < 0x20 ? 0x18 : (0x40-8)))
@@ -94,6 +94,15 @@
 #define IRQ_SCCA_RX          (52)
 #define IRQ_SCCA_SPCOND      (54)
 
+/* shared MFP timer D interrupts - hires timer for EtherNEC et al. */
+#define IRQ_MFP_TIMER1       (64)
+#define IRQ_MFP_TIMER2       (65)
+#define IRQ_MFP_TIMER3       (66)
+#define IRQ_MFP_TIMER4       (67)
+#define IRQ_MFP_TIMER5       (68)
+#define IRQ_MFP_TIMER6       (69)
+#define IRQ_MFP_TIMER7       (70)
+#define IRQ_MFP_TIMER8       (71)
 
 #define INT_CLK   24576     /* CLK while int_clk =2.456MHz and divide = 100 */
 #define INT_TICKS 246       /* to make sched_time = 99.902... HZ */
diff --git a/arch/m68k/include/asm/cmpxchg.h b/arch/m68k/include/asm/cmpxchg.h
index 5c81d0eae5cf..bc755bc620ad 100644
--- a/arch/m68k/include/asm/cmpxchg.h
+++ b/arch/m68k/include/asm/cmpxchg.h
@@ -124,6 +124,9 @@ static inline unsigned long __cmpxchg(volatile void *p, unsigned long old,
 #define cmpxchg_local(ptr, o, n)                                            \
         ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o),           \
                         (unsigned long)(n), sizeof(*(ptr))))
+
+#define cmpxchg64(ptr, o, n)    cmpxchg64_local((ptr), (o), (n))
+
 #else
 
 /*
diff --git a/arch/m68k/include/asm/delay.h b/arch/m68k/include/asm/delay.h
index 12d8fe4f1d30..d28fa8fe26fe 100644
--- a/arch/m68k/include/asm/delay.h
+++ b/arch/m68k/include/asm/delay.h
@@ -92,5 +92,28 @@ static inline void __udelay(unsigned long usecs)
 #define udelay(n) (__builtin_constant_p(n) ? \
         ((n) > 20000 ? __bad_udelay() : __const_udelay(n)) : __udelay(n))
 
+/*
+ * nanosecond delay:
+ *
+ * ((((HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6) is the number of loops
+ * per microsecond
+ *
+ * 1000 / ((((HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6) is the number of
+ * nanoseconds per loop
+ *
+ * So n / ( 1000 / ((((HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6) ) would
+ * be the number of loops for n nanoseconds
+ */
+
+/*
+ * The simpler m68k and ColdFire processors do not have a 32*32->64
+ * multiply instruction. So we need to handle them a little differently.
+ * We use a bit of shifting and a single 32*32->32 multiply to get close.
+ * This is a macro so that the const version can factor out the first
+ * multiply and shift.
+ */
+#define HZSCALE         (268435456 / (1000000 / HZ))
+
+#define ndelay(n) __delay(DIV_ROUND_UP((n) * ((((HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6), 1000));
 
 #endif /* defined(_M68K_DELAY_H) */
diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h
index a6686d26fe17..ffdf54f44bc6 100644
--- a/arch/m68k/include/asm/io_mm.h
+++ b/arch/m68k/include/asm/io_mm.h
@@ -63,6 +63,23 @@
 #endif
 #endif /* AMIGA_PCMCIA */
 
+#ifdef CONFIG_ATARI_ROM_ISA
+
+#define enec_isa_read_base  0xfffa0000
+#define enec_isa_write_base 0xfffb0000
+
+#define ENEC_ISA_IO_B(ioaddr)   (enec_isa_read_base+((((unsigned long)(ioaddr))&0x7F)<<9))
+#define ENEC_ISA_IO_W(ioaddr)   (enec_isa_read_base+((((unsigned long)(ioaddr))&0x7F)<<9))
+#define ENEC_ISA_MEM_B(madr)    (enec_isa_read_base+((((unsigned long)(madr))&0x7F)<<9))
+#define ENEC_ISA_MEM_W(madr)    (enec_isa_read_base+((((unsigned long)(madr))&0x7F)<<9))
+
+#ifndef MULTI_ISA
+#define MULTI_ISA 0
+#else
+#undef MULTI_ISA
+#define MULTI_ISA 1
+#endif
+#endif /* ATARI_ROM_ISA */
 
 
 #if defined(CONFIG_PCI) && defined(CONFIG_COLDFIRE)
@@ -111,14 +128,15 @@ void mcf_pci_outsl(u32 addr, const u32 *buf, u32 len);
 #define readw(addr)     in_le16(addr)
 #define writew(v, addr) out_le16((addr), (v))
 
-#elif defined(CONFIG_ISA)
+#elif defined(CONFIG_ISA) || defined(CONFIG_ATARI_ROM_ISA)
 
 #if MULTI_ISA == 0
 #undef MULTI_ISA
 #endif
 
-#define ISA_TYPE_Q40 (1)
-#define ISA_TYPE_AG  (2)
+#define ISA_TYPE_Q40  (1)
+#define ISA_TYPE_AG   (2)
+#define ISA_TYPE_ENEC (3)
 
 #if defined(CONFIG_Q40) && !defined(MULTI_ISA)
 #define ISA_TYPE ISA_TYPE_Q40
@@ -128,6 +146,10 @@ void mcf_pci_outsl(u32 addr, const u32 *buf, u32 len);
 #define ISA_TYPE ISA_TYPE_AG
 #define ISA_SEX  1
 #endif
+#if defined(CONFIG_ATARI_ROM_ISA) && !defined(MULTI_ISA)
+#define ISA_TYPE ISA_TYPE_ENEC
+#define ISA_SEX  0
+#endif
 
 #ifdef MULTI_ISA
 extern int isa_type;
@@ -152,6 +174,9 @@ static inline u8 __iomem *isa_itb(unsigned long addr)
 #ifdef CONFIG_AMIGA_PCMCIA
     case ISA_TYPE_AG: return (u8 __iomem *)AG_ISA_IO_B(addr);
 #endif
+#ifdef CONFIG_ATARI_ROM_ISA
+    case ISA_TYPE_ENEC: return (u8 __iomem *)ENEC_ISA_IO_B(addr);
+#endif
     default: return NULL; /* avoid warnings, just in case */
     }
 }
@@ -165,6 +190,9 @@ static inline u16 __iomem *isa_itw(unsigned long addr)
 #ifdef CONFIG_AMIGA_PCMCIA
     case ISA_TYPE_AG: return (u16 __iomem *)AG_ISA_IO_W(addr);
 #endif
+#ifdef CONFIG_ATARI_ROM_ISA
+    case ISA_TYPE_ENEC: return (u16 __iomem *)ENEC_ISA_IO_W(addr);
+#endif
     default: return NULL; /* avoid warnings, just in case */
     }
 }
@@ -188,6 +216,9 @@ static inline u8 __iomem *isa_mtb(unsigned long addr)
 #ifdef CONFIG_AMIGA_PCMCIA
     case ISA_TYPE_AG: return (u8 __iomem *)addr;
 #endif
+#ifdef CONFIG_ATARI_ROM_ISA
+    case ISA_TYPE_ENEC: return (u8 __iomem *)ENEC_ISA_MEM_B(addr);
+#endif
     default: return NULL; /* avoid warnings, just in case */
     }
 }
@@ -201,6 +232,9 @@ static inline u16 __iomem *isa_mtw(unsigned long addr)
 #ifdef CONFIG_AMIGA_PCMCIA
     case ISA_TYPE_AG: return (u16 __iomem *)addr;
 #endif
+#ifdef CONFIG_ATARI_ROM_ISA
+    case ISA_TYPE_ENEC: return (u16 __iomem *)ENEC_ISA_MEM_W(addr);
+#endif
     default: return NULL; /* avoid warnings, just in case */
     }
 }
@@ -222,6 +256,36 @@ static inline u16 __iomem *isa_mtw(unsigned long addr)
         (ISA_SEX ? out_be16(isa_mtw((unsigned long)(p)),(val))  \
                  : out_le16(isa_mtw((unsigned long)(p)),(val)))
 
+#ifdef CONFIG_ATARI_ROM_ISA
+#define isa_rom_inb(port)      rom_in_8(isa_itb(port))
+#define isa_rom_inw(port)       \
+        (ISA_SEX ? rom_in_be16(isa_itw(port))   \
+                 : rom_in_le16(isa_itw(port)))
+
+#define isa_rom_outb(val, port) rom_out_8(isa_itb(port), (val))
+#define isa_rom_outw(val, port) \
+        (ISA_SEX ? rom_out_be16(isa_itw(port), (val))   \
+                 : rom_out_le16(isa_itw(port), (val)))
+
+#define isa_rom_readb(p)       rom_in_8(isa_mtb((unsigned long)(p)))
+#define isa_rom_readw(p)       \
+        (ISA_SEX ? rom_in_be16(isa_mtw((unsigned long)(p)))     \
+                 : rom_in_le16(isa_mtw((unsigned long)(p))))
+#define isa_rom_readw_swap(p)       \
+        (ISA_SEX ? rom_in_le16(isa_mtw((unsigned long)(p)))     \
+                 : rom_in_be16(isa_mtw((unsigned long)(p))))
+#define isa_rom_readw_raw(p)   rom_in_be16(isa_mtw((unsigned long)(p)))
+
+#define isa_rom_writeb(val, p)  rom_out_8(isa_mtb((unsigned long)(p)), (val))
+#define isa_rom_writew(val, p)  \
+        (ISA_SEX ? rom_out_be16(isa_mtw((unsigned long)(p)), (val))     \
+                 : rom_out_le16(isa_mtw((unsigned long)(p)), (val)))
+#define isa_rom_writew_swap(val, p)  \
+        (ISA_SEX ? rom_out_le16(isa_mtw((unsigned long)(p)), (val))     \
+                 : rom_out_be16(isa_mtw((unsigned long)(p)), (val)))
+#define isa_rom_writew_raw(val, p)  rom_out_be16(isa_mtw((unsigned long)(p)), (val))
+#endif /* CONFIG_ATARI_ROM_ISA */
+
 static inline void isa_delay(void)
 {
   switch(ISA_TYPE)
@@ -232,6 +296,9 @@ static inline void isa_delay(void)
 #ifdef CONFIG_AMIGA_PCMCIA
     case ISA_TYPE_AG: break;
 #endif
+#ifdef CONFIG_ATARI_ROM_ISA
+    case ISA_TYPE_ENEC: break;
+#endif
     default: break; /* avoid warnings */
     }
 }
@@ -263,6 +330,29 @@ static inline void isa_delay(void)
                   raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1))
 
 
+#ifdef CONFIG_ATARI_ROM_ISA
+#define isa_rom_inb_p(p)        ({ u8 _v = isa_rom_inb(p); isa_delay(); _v; })
+#define isa_rom_inw_p(p)        ({ u16 _v = isa_rom_inw(p); isa_delay(); _v; })
+#define isa_rom_outb_p(v, p)    ({ isa_rom_outb((v), (p)); isa_delay(); })
+#define isa_rom_outw_p(v, p)    ({ isa_rom_outw((v), (p)); isa_delay(); })
+
+#define isa_rom_insb(port, buf, nr) raw_rom_insb(isa_itb(port), (u8 *)(buf), (nr))
+
+#define isa_rom_insw(port, buf, nr)     \
+       (ISA_SEX ? raw_rom_insw(isa_itw(port), (u16 *)(buf), (nr)) :    \
+                  raw_rom_insw_swapw(isa_itw(port), (u16 *)(buf), (nr)))
+
+#define isa_rom_outsb(port, buf, nr) raw_rom_outsb(isa_itb(port), (u8 *)(buf), (nr))
+
+#define isa_rom_outsw(port, buf, nr)    \
+       (ISA_SEX ? raw_rom_outsw(isa_itw(port), (u16 *)(buf), (nr)) :  \
+                  raw_rom_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)))
+#endif /* CONFIG_ATARI_ROM_ISA */
+
+#endif  /* CONFIG_ISA || CONFIG_ATARI_ROM_ISA */
+
+
+#if defined(CONFIG_ISA) && !defined(CONFIG_ATARI_ROM_ISA)
 #define inb     isa_inb
 #define inb_p   isa_inb_p
 #define outb    isa_outb
@@ -285,9 +375,43 @@ static inline void isa_delay(void)
 #define readw   isa_readw
 #define writeb  isa_writeb
 #define writew  isa_writew
+#endif  /* CONFIG_ISA && !CONFIG_ATARI_ROM_ISA */
 
-#else  /* CONFIG_ISA */
-
+#ifdef CONFIG_ATARI_ROM_ISA
+/*
+ * kernel with both ROM port ISA and IDE compiled in, those have
+ * conflicting defs for in/out. Simply consider port < 1024
+ * ROM port ISA and everything else regular ISA for IDE. read,write defined
+ * below.
+ */
+#define inb(port)       ((port) < 1024 ? isa_rom_inb(port) : in_8(port))
+#define inb_p(port)     ((port) < 1024 ? isa_rom_inb_p(port) : in_8(port))
+#define inw(port)       ((port) < 1024 ? isa_rom_inw(port) : in_le16(port))
+#define inw_p(port)     ((port) < 1024 ? isa_rom_inw_p(port) : in_le16(port))
+#define inl             isa_inl
+#define inl_p           isa_inl_p
+
+#define outb(val, port) ((port) < 1024 ? isa_rom_outb((val), (port)) : out_8((port), (val)))
+#define outb_p(val, port) ((port) < 1024 ? isa_rom_outb_p((val), (port)) : out_8((port), (val)))
+#define outw(val, port) ((port) < 1024 ? isa_rom_outw((val), (port)) : out_le16((port), (val)))
+#define outw_p(val, port) ((port) < 1024 ? isa_rom_outw_p((val), (port)) : out_le16((port), (val)))
+#define outl            isa_outl
+#define outl_p          isa_outl_p
+
+#define insb(port, buf, nr)     ((port) < 1024 ? isa_rom_insb((port), (buf), (nr)) : isa_insb((port), (buf), (nr)))
+#define insw(port, buf, nr)     ((port) < 1024 ? isa_rom_insw((port), (buf), (nr)) : isa_insw((port), (buf), (nr)))
+#define insl                    isa_insl
+#define outsb(port, buf, nr)    ((port) < 1024 ? isa_rom_outsb((port), (buf), (nr)) : isa_outsb((port), (buf), (nr)))
+#define outsw(port, buf, nr)    ((port) < 1024 ? isa_rom_outsw((port), (buf), (nr)) : isa_outsw((port), (buf), (nr)))
+#define outsl                   isa_outsl
+
+#define readb(addr)             in_8(addr)
+#define writeb(val, addr)       out_8((addr), (val))
+#define readw(addr)             in_le16(addr)
+#define writew(val, addr)       out_le16((addr), (val))
+#endif /* CONFIG_ATARI_ROM_ISA */
+
+#if !defined(CONFIG_ISA) && !defined(CONFIG_ATARI_ROM_ISA)
 /*
  * We need to define dummy functions for GENERIC_IOMAP support.
  */
@@ -319,7 +443,7 @@ static inline void isa_delay(void)
 #define readw(addr)      in_le16(addr)
 #define writew(val,addr) out_le16((addr),(val))
 
-#endif /* CONFIG_ISA */
+#endif /* !CONFIG_ISA && !CONFIG_ATARI_ROM_ISA */
 
 #define readl(addr)      in_le32(addr)
 #define writel(val,addr) out_le32((addr),(val))
diff --git a/arch/m68k/include/asm/irq.h b/arch/m68k/include/asm/irq.h
index c1155f0e22cc..81ca118d58af 100644
--- a/arch/m68k/include/asm/irq.h
+++ b/arch/m68k/include/asm/irq.h
@@ -6,12 +6,16 @@
  * different m68k hosts compiled into the kernel.
  * Currently the Atari has 72 and the Amiga 24, but if both are
  * supported in the kernel it is better to make room for 72.
+ * With EtherNAT add-on card on Atari, the highest interrupt
+ * number is 140 so NR_IRQS needs to be 141.
  */
 #if defined(CONFIG_COLDFIRE)
 #define NR_IRQS 256
 #elif defined(CONFIG_VME) || defined(CONFIG_SUN3) || defined(CONFIG_SUN3X)
 #define NR_IRQS 200
-#elif defined(CONFIG_ATARI) || defined(CONFIG_MAC)
+#elif defined(CONFIG_ATARI)
+#define NR_IRQS 141
+#elif defined(CONFIG_MAC)
 #define NR_IRQS 72
 #elif defined(CONFIG_Q40)
 #define NR_IRQS 43
diff --git a/arch/m68k/include/asm/raw_io.h b/arch/m68k/include/asm/raw_io.h
index d9eb9834ccc8..932faa35655b 100644
--- a/arch/m68k/include/asm/raw_io.h
+++ b/arch/m68k/include/asm/raw_io.h
@@ -10,7 +10,7 @@
 
 #ifdef __KERNEL__
 
-#include <asm/types.h>
+#include <asm/byteorder.h>
 
 
 /* Values for nocacheflag and cmode */
@@ -60,6 +60,57 @@ extern void __iounmap(void *addr, unsigned long size);
 #define __raw_writew(val,addr) out_be16((addr),(val))
 #define __raw_writel(val,addr) out_be32((addr),(val))
 
+/*
+ * Atari ROM port (cartridge port) ISA adapter, used for the EtherNEC NE2000
+ * network card driver.
+ * The ISA adapter connects address lines A9-A13 to ISA address lines A0-A4,
+ * and hardwires the rest of the ISA addresses for a base address of 0x300.
+ *
+ * Data lines D8-D15 are connected to ISA data lines D0-D7 for reading.
+ * For writes, address lines A1-A8 are latched to ISA data lines D0-D7
+ * (meaning the bit pattern on A1-A8 can be read back as byte).
+ *
+ * Read and write operations are distinguished by the base address used:
+ * reads are from the ROM A side range, writes are through the B side range
+ * addresses (A side base + 0x10000).
+ *
+ * Reads and writes are byte only.
+ *
+ * 16 bit reads and writes are necessary for the NetUSBee adapter's USB
+ * chipset - 16 bit words are read straight off the ROM port while 16 bit
+ * reads are split into two byte writes. The low byte is latched to the
+ * NetUSBee buffer by a read from the _read_ window (with the data pattern
+ * asserted as A1-A8 address pattern). The high byte is then written to the
+ * write range as usual, completing the write cycle.
+ */
+
+#if defined(CONFIG_ATARI_ROM_ISA)
+#define rom_in_8(addr) \
+        ({ u16 __v = (*(__force volatile u16 *) (addr)); __v >>= 8; __v; })
+#define rom_in_be16(addr) \
+        ({ u16 __v = (*(__force volatile u16 *) (addr)); __v; })
+#define rom_in_le16(addr) \
+        ({ u16 __v = le16_to_cpu(*(__force volatile u16 *) (addr)); __v; })
+
+#define rom_out_8(addr, b)      \
+        ({u8 __w, __v = (b);  u32 _addr = ((u32) (addr)); \
+        __w = ((*(__force volatile u8 *)  ((_addr | 0x10000) + (__v<<1)))); })
+#define rom_out_be16(addr, w)   \
+        ({u16 __w, __v = (w); u32 _addr = ((u32) (addr)); \
+        __w = ((*(__force volatile u16 *) ((_addr & 0xFFFF0000UL) + ((__v & 0xFF)<<1)))); \
+        __w = ((*(__force volatile u16 *) ((_addr | 0x10000) + ((__v >> 8)<<1)))); })
+#define rom_out_le16(addr, w)   \
+        ({u16 __w, __v = (w); u32 _addr = ((u32) (addr)); \
+        __w = ((*(__force volatile u16 *) ((_addr & 0xFFFF0000UL) + ((__v >> 8)<<1)))); \
+        __w = ((*(__force volatile u16 *) ((_addr | 0x10000) + ((__v & 0xFF)<<1)))); })
+
+#define raw_rom_inb rom_in_8
+#define raw_rom_inw rom_in_be16
+
+#define raw_rom_outb(val, port) rom_out_8((port), (val))
+#define raw_rom_outw(val, port) rom_out_be16((port), (val))
+#endif /* CONFIG_ATARI_ROM_ISA */
+
 static inline void raw_insb(volatile u8 __iomem *port, u8 *buf, unsigned int len)
 {
         unsigned int i;
@@ -342,6 +393,62 @@ static inline void raw_outsw_swapw(volatile u16 __iomem *port, const u16 *buf,
                 : "d0", "a0", "a1", "d6");
 }
 
+
+#if defined(CONFIG_ATARI_ROM_ISA)
+static inline void raw_rom_insb(volatile u8 __iomem *port, u8 *buf, unsigned int len)
+{
+        unsigned int i;
+
+        for (i = 0; i < len; i++)
+                *buf++ = rom_in_8(port);
+}
+
+static inline void raw_rom_outsb(volatile u8 __iomem *port, const u8 *buf,
+                             unsigned int len)
+{
+        unsigned int i;
+
+        for (i = 0; i < len; i++)
+                rom_out_8(port, *buf++);
+}
+
+static inline void raw_rom_insw(volatile u16 __iomem *port, u16 *buf,
+                                   unsigned int nr)
+{
+        unsigned int i;
+
+        for (i = 0; i < nr; i++)
+                *buf++ = rom_in_be16(port);
+}
+
+static inline void raw_rom_outsw(volatile u16 __iomem *port, const u16 *buf,
+                                   unsigned int nr)
+{
+        unsigned int i;
+
+        for (i = 0; i < nr; i++)
+                rom_out_be16(port, *buf++);
+}
+
+static inline void raw_rom_insw_swapw(volatile u16 __iomem *port, u16 *buf,
+                                   unsigned int nr)
+{
+        unsigned int i;
+
+        for (i = 0; i < nr; i++)
+                *buf++ = rom_in_le16(port);
+}
+
+static inline void raw_rom_outsw_swapw(volatile u16 __iomem *port, const u16 *buf,
+                                   unsigned int nr)
+{
+        unsigned int i;
+
+        for (i = 0; i < nr; i++)
+                rom_out_le16(port, *buf++);
+}
+#endif /* CONFIG_ATARI_ROM_ISA */
+
 #endif /* __KERNEL__ */
 
 #endif /* _RAW_IO_H */
diff --git a/arch/m68k/include/asm/string.h b/arch/m68k/include/asm/string.h
index 32198454da70..9aea9f11fa25 100644
--- a/arch/m68k/include/asm/string.h
+++ b/arch/m68k/include/asm/string.h
@@ -4,15 +4,6 @@
 #include <linux/types.h>
 #include <linux/compiler.h>
 
-static inline size_t __kernel_strlen(const char *s)
-{
-        const char *sc;
-
-        for (sc = s; *sc++; )
-                ;
-        return sc - s - 1;
-}
-
 static inline char *__kernel_strcpy(char *dest, const char *src)
 {
         char *xdest = dest;
@@ -27,11 +18,6 @@ static inline char *__kernel_strcpy(char *dest, const char *src)
 
 #ifndef __IN_STRING_C
 
-#define __HAVE_ARCH_STRLEN
-#define strlen(s)       (__builtin_constant_p(s) ?      \
-                         __builtin_strlen(s) :          \
-                         __kernel_strlen(s))
-
 #define __HAVE_ARCH_STRNLEN
 static inline size_t strnlen(const char *s, size_t count)
 {
diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h
index 6cd92671ca5e..014f288fc813 100644
--- a/arch/m68k/include/asm/unistd.h
+++ b/arch/m68k/include/asm/unistd.h
@@ -32,12 +32,4 @@
 #define __ARCH_WANT_SYS_FORK
 #define __ARCH_WANT_SYS_VFORK
 
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
-
 #endif /* _ASM_M68K_UNISTD_H_ */
diff --git a/arch/m68k/kernel/process.c b/arch/m68k/kernel/process.c
index d538694ad208..c55ff719fa72 100644
--- a/arch/m68k/kernel/process.c
+++ b/arch/m68k/kernel/process.c
@@ -51,40 +51,16 @@ unsigned long thread_saved_pc(struct task_struct *tsk)
                 return sw->retpc;
 }
 
-/*
- * The idle loop on an m68k..
- */
-static void default_idle(void)
+void arch_cpu_idle(void)
 {
-        if (!need_resched())
 #if defined(MACH_ATARI_ONLY)
-                /* block out HSYNC on the atari (falcon) */
-                __asm__("stop #0x2200" : : : "cc");
+        /* block out HSYNC on the atari (falcon) */
+        __asm__("stop #0x2200" : : : "cc");
 #else
-                __asm__("stop #0x2000" : : : "cc");
+        __asm__("stop #0x2000" : : : "cc");
 #endif
 }
 
-void (*idle)(void) = default_idle;
-
-/*
- * The idle thread. There's no useful work to be
- * done, so just try to conserve power and have a
- * low exit latency (ie sit in a loop waiting for
- * somebody to say that they'd like to reschedule)
- */
-void cpu_idle(void)
-{
-        /* endless idle loop with no priority at all */
-        while (1) {
-                rcu_idle_enter();
-                while (!need_resched())
-                        idle();
-                rcu_idle_exit();
-                schedule_preempt_disabled();
-        }
-}
-
 void machine_restart(char * __unused)
 {
         if (mach_reset)
diff --git a/arch/m68k/kernel/setup_mm.c b/arch/m68k/kernel/setup_mm.c
index 80cfbe56ea32..e67e53159573 100644
--- a/arch/m68k/kernel/setup_mm.c
+++ b/arch/m68k/kernel/setup_mm.c
@@ -381,6 +381,12 @@ void __init setup_arch(char **cmdline_p)
                 isa_sex = 1;
         }
 #endif
+#ifdef CONFIG_ATARI_ROM_ISA
+        if (MACH_IS_ATARI) {
+                isa_type = ISA_TYPE_ENEC;
+                isa_sex = 0;
+        }
+#endif
 #endif
 }
 
diff --git a/arch/m68k/kernel/traps.c b/arch/m68k/kernel/traps.c
index f32ab22e7ed3..88fcd8c70e7b 100644
--- a/arch/m68k/kernel/traps.c
+++ b/arch/m68k/kernel/traps.c
@@ -992,18 +992,6 @@ void show_stack(struct task_struct *task, unsigned long *stack)
 }
 
 /*
- * The architecture-independent backtrace generator
- */
-void dump_stack(void)
-{
-        unsigned long stack;
-
-        show_trace(&stack);
-}
-
-EXPORT_SYMBOL(dump_stack);
-
-/*
  * The vector number returned in the frame pointer may also contain
  * the "fs" (Fault Status) bits on ColdFire. These are in the bottom
  * 2 bits, and upper 2 bits. So we need to mask out the real vector
diff --git a/arch/m68k/lib/string.c b/arch/m68k/lib/string.c
index b9a57abfad08..4d61fa8a112c 100644
--- a/arch/m68k/lib/string.c
+++ b/arch/m68k/lib/string.c
@@ -17,6 +17,6 @@ EXPORT_SYMBOL(strcpy);
 
 char *strcat(char *dest, const char *src)
 {
-        return __kernel_strcpy(dest + __kernel_strlen(dest), src);
+        return __kernel_strcpy(dest + strlen(dest), src);
 }
 EXPORT_SYMBOL(strcat);
diff --git a/arch/m68k/mm/init.c b/arch/m68k/mm/init.c
index 519aad8fa812..1af2ca3411f6 100644
--- a/arch/m68k/mm/init.c
+++ b/arch/m68k/mm/init.c
@@ -110,18 +110,7 @@ void __init paging_init(void)
 void free_initmem(void)
 {
 #ifndef CONFIG_MMU_SUN3
-        unsigned long addr;
-
-        addr = (unsigned long) __init_begin;
-        for (; addr < ((unsigned long) __init_end); addr += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(addr));
-                init_page_count(virt_to_page(addr));
-                free_page(addr);
-                totalram_pages++;
-        }
-        pr_notice("Freeing unused kernel memory: %luk freed (0x%x - 0x%x)\n",
-                (addr - (unsigned long) __init_begin) >> 10,
-                (unsigned int) __init_begin, (unsigned int) __init_end);
+        free_initmem_default(0);
 #endif /* CONFIG_MMU_SUN3 */
 }
 
@@ -213,15 +202,6 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        int pages = 0;
-        for (; start < end; start += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(start));
-                init_page_count(virt_to_page(start));
-                free_page(start);
-                totalram_pages++;
-                pages++;
-        }
-        pr_notice("Freeing initrd memory: %dk freed\n",
-                pages << (PAGE_SHIFT - 10));
+        free_reserved_area(start, end, 0, "initrd");
 }
 #endif
diff --git a/arch/metag/Kconfig b/arch/metag/Kconfig
index afc8973d1488..6f16c1469327 100644
--- a/arch/metag/Kconfig
+++ b/arch/metag/Kconfig
@@ -1,7 +1,3 @@
-config SYMBOL_PREFIX
-        string
-        default "_"
-
 config METAG
         def_bool y
         select EMBEDDED
@@ -25,8 +21,10 @@ config METAG
         select HAVE_MEMBLOCK
         select HAVE_MEMBLOCK_NODE_MAP
         select HAVE_MOD_ARCH_SPECIFIC
+        select HAVE_OPROFILE
         select HAVE_PERF_EVENTS
         select HAVE_SYSCALL_TRACEPOINTS
+        select HAVE_UNDERSCORE_SYMBOL_PREFIX
         select IRQ_DOMAIN
         select MODULES_USE_ELF_RELA
         select OF
@@ -209,6 +207,9 @@ config METAG_PERFCOUNTER_IRQS
           When disabled, Performance Counters information will be collected
           based on Timer Interrupt.
 
+config HW_PERF_EVENTS
+        def_bool METAG_PERFCOUNTER_IRQS && PERF_EVENTS
+
 config METAG_DA
         bool "DA support"
         help
diff --git a/arch/metag/Makefile b/arch/metag/Makefile
index 81bd6a1c7483..b566116b171b 100644
--- a/arch/metag/Makefile
+++ b/arch/metag/Makefile
@@ -49,6 +49,8 @@ core-y					+= arch/metag/mm/
 libs-y                                  += arch/metag/lib/
 libs-y                                  += arch/metag/tbx/
 
+drivers-$(CONFIG_OPROFILE)              += arch/metag/oprofile/
+
 boot                                    := arch/metag/boot
 
 boot_targets                            += uImage
diff --git a/arch/metag/boot/dts/Makefile b/arch/metag/boot/dts/Makefile
index e0b5afd8bde8..dbd95217733a 100644
--- a/arch/metag/boot/dts/Makefile
+++ b/arch/metag/boot/dts/Makefile
@@ -4,13 +4,17 @@ dtb-y	+= skeleton.dtb
 builtindtb-y                            := skeleton
 
 ifneq ($(CONFIG_METAG_BUILTIN_DTB_NAME),"")
-        builtindtb-y                    := $(CONFIG_METAG_BUILTIN_DTB_NAME)
+        builtindtb-y                    := $(patsubst "%",%,$(CONFIG_METAG_BUILTIN_DTB_NAME))
 endif
-obj-$(CONFIG_METAG_BUILTIN_DTB) += $(patsubst "%",%,$(builtindtb-y)).dtb.o
+
+dtb-$(CONFIG_METAG_BUILTIN_DTB) += $(builtindtb-y).dtb
+obj-$(CONFIG_METAG_BUILTIN_DTB) += $(builtindtb-y).dtb.o
 
 targets += dtbs
 targets += $(dtb-y)
 
+.SECONDARY: $(obj)/$(builtindtb-y).dtb.S
+
 dtbs: $(addprefix $(obj)/, $(dtb-y))
 
-clean-files += *.dtb
+clean-files += *.dtb *.dtb.S
diff --git a/arch/metag/configs/meta1_defconfig b/arch/metag/configs/meta1_defconfig
index c35a75e8ecfe..01cd67e4403d 100644
--- a/arch/metag/configs/meta1_defconfig
+++ b/arch/metag/configs/meta1_defconfig
@@ -1,6 +1,5 @@
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
-CONFIG_LOG_BUF_SHIFT=13
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_KALLSYMS_ALL=y
diff --git a/arch/metag/configs/meta2_defconfig b/arch/metag/configs/meta2_defconfig
index fb3148410183..643392ba7ed5 100644
--- a/arch/metag/configs/meta2_defconfig
+++ b/arch/metag/configs/meta2_defconfig
@@ -1,7 +1,6 @@
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=13
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_KALLSYMS_ALL=y
diff --git a/arch/metag/configs/meta2_smp_defconfig b/arch/metag/configs/meta2_smp_defconfig
index 6c7b777ac276..f3306737da20 100644
--- a/arch/metag/configs/meta2_smp_defconfig
+++ b/arch/metag/configs/meta2_smp_defconfig
@@ -1,7 +1,6 @@
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=13
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_KALLSYMS_ALL=y
diff --git a/arch/metag/include/asm/metag_mem.h b/arch/metag/include/asm/metag_mem.h
index 3f7b54d8ccac..aa5a076df439 100644
--- a/arch/metag/include/asm/metag_mem.h
+++ b/arch/metag/include/asm/metag_mem.h
@@ -700,6 +700,9 @@
 #define     SYSC_xCPARTG_AND_S    8
 #define     SYSC_xCPARTL_OR_BITS  0x000F0000 /* Ors into top 4 bits */
 #define     SYSC_xCPARTL_OR_S     16
+#ifdef METAC_2_1
+#define     SYSC_DCPART_GCON_BIT  0x00100000 /* Coherent shared local */
+#endif /* METAC_2_1 */
 #define     SYSC_xCPARTG_OR_BITS  0x0F000000 /* Ors into top 4 bits */
 #define     SYSC_xCPARTG_OR_S     24
 #define     SYSC_CWRMODE_BIT      0x80000000 /* Write cache mode bit */
diff --git a/arch/metag/include/asm/thread_info.h b/arch/metag/include/asm/thread_info.h
index 0ecd34d8b5f6..7c4a33006142 100644
--- a/arch/metag/include/asm/thread_info.h
+++ b/arch/metag/include/asm/thread_info.h
@@ -150,6 +150,4 @@ static inline int kstack_end(void *addr)
 #define _TIF_WORK_MASK          (_TIF_ALLWORK_MASK & ~(_TIF_SYSCALL_TRACE | \
                                  _TIF_SYSCALL_AUDIT | _TIF_SINGLESTEP))
 
-#define tsk_is_polling(t) test_tsk_thread_flag(t, TIF_POLLING_NRFLAG)
-
 #endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/metag/include/uapi/asm/Kbuild b/arch/metag/include/uapi/asm/Kbuild
index 876c71f866de..84e09feb4d54 100644
--- a/arch/metag/include/uapi/asm/Kbuild
+++ b/arch/metag/include/uapi/asm/Kbuild
@@ -2,6 +2,7 @@
 include include/uapi/asm-generic/Kbuild.asm
 
 header-y += byteorder.h
+header-y += ech.h
 header-y += ptrace.h
 header-y += resource.h
 header-y += sigcontext.h
diff --git a/arch/metag/include/uapi/asm/ech.h b/arch/metag/include/uapi/asm/ech.h
new file mode 100644
index 000000000000..ac94d1cf9be4
--- /dev/null
+++ b/arch/metag/include/uapi/asm/ech.h
@@ -0,0 +1,15 @@
+#ifndef _UAPI_METAG_ECH_H
+#define _UAPI_METAG_ECH_H
+
+/*
+ * These bits can be set in the top half of the D0.8 register when DSP context
+ * switching is enabled, in order to support partial DSP context save/restore.
+ */
+
+#define TBICTX_XEXT_BIT 0x1000  /* Enable extended context save */
+#define TBICTX_XTDP_BIT 0x0800  /* DSP accumulators/RAM/templates */
+#define TBICTX_XHL2_BIT 0x0400  /* Hardware loops */
+#define TBICTX_XAXX_BIT 0x0200  /* Extended AX registers (A*.4-7) */
+#define TBICTX_XDX8_BIT 0x0100  /* Extended DX registers (D*.8-15) */
+
+#endif /* _UAPI_METAG_ECH_H */
diff --git a/arch/metag/kernel/cachepart.c b/arch/metag/kernel/cachepart.c
index 3a589dfb966b..954548b1bea8 100644
--- a/arch/metag/kernel/cachepart.c
+++ b/arch/metag/kernel/cachepart.c
@@ -24,15 +24,21 @@
 unsigned int get_dcache_size(void)
 {
         unsigned int config2 = metag_in32(METAC_CORE_CONFIG2);
-        return 0x1000 << ((config2 & METAC_CORECFG2_DCSZ_BITS)
-                                >> METAC_CORECFG2_DCSZ_S);
+        unsigned int sz = 0x1000 << ((config2 & METAC_CORECFG2_DCSZ_BITS)
+                                     >> METAC_CORECFG2_DCSZ_S);
+        if (config2 & METAC_CORECFG2_DCSMALL_BIT)
+                sz >>= 6;
+        return sz;
 }
 
 unsigned int get_icache_size(void)
 {
         unsigned int config2 = metag_in32(METAC_CORE_CONFIG2);
-        return 0x1000 << ((config2 & METAC_CORE_C2ICSZ_BITS)
-                                >> METAC_CORE_C2ICSZ_S);
+        unsigned int sz = 0x1000 << ((config2 & METAC_CORE_C2ICSZ_BITS)
+                                     >> METAC_CORE_C2ICSZ_S);
+        if (config2 & METAC_CORECFG2_ICSMALL_BIT)
+                sz >>= 6;
+        return sz;
 }
 
 unsigned int get_global_dcache_size(void)
@@ -61,7 +67,7 @@ static unsigned int get_thread_cache_size(unsigned int cache, int thread_id)
                 return 0;
 #if PAGE_OFFSET >= LINGLOBAL_BASE
         /* Checking for global cache */
-        cache_size = (cache == DCACHE ? get_global_dache_size() :
+        cache_size = (cache == DCACHE ? get_global_dcache_size() :
                 get_global_icache_size());
         offset = 8;
 #else
diff --git a/arch/metag/kernel/da.c b/arch/metag/kernel/da.c
index 52aabb658fde..a35dbed6fffa 100644
--- a/arch/metag/kernel/da.c
+++ b/arch/metag/kernel/da.c
@@ -5,12 +5,14 @@
  */
 
 
+#include <linux/export.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <asm/da.h>
 #include <asm/metag_mem.h>
 
 bool _metag_da_present;
+EXPORT_SYMBOL_GPL(_metag_da_present);
 
 int __init metag_da_probe(void)
 {
diff --git a/arch/metag/kernel/head.S b/arch/metag/kernel/head.S
index 969dffabc03a..713f71d1bdfe 100644
--- a/arch/metag/kernel/head.S
+++ b/arch/metag/kernel/head.S
@@ -1,6 +1,7 @@
         ! Copyright 2005,2006,2007,2009 Imagination Technologies
 
 #include <linux/init.h>
+#include <asm/metag_mem.h>
 #include <generated/asm-offsets.h>
 #undef __exit
 
@@ -48,6 +49,13 @@ __exit:
         .global _secondary_startup
         .type _secondary_startup,function
 _secondary_startup:
+#if CONFIG_PAGE_OFFSET < LINGLOBAL_BASE
+        ! In case GCOn has just been turned on we need to fence any writes that
+        ! the boot thread might have performed prior to coherency taking effect.
+        MOVT    D0Re0,#HI(LINSYSEVENT_WR_ATOMIC_UNLOCK)
+        MOV     D1Re0,#0
+        SETD    [D0Re0], D1Re0
+#endif
         MOVT    A0StP,#HI(_secondary_data_stack)
         ADD     A0StP,A0StP,#LO(_secondary_data_stack)
         GETD    A0StP,[A0StP]
diff --git a/arch/metag/kernel/perf/perf_event.c b/arch/metag/kernel/perf/perf_event.c
index a876d5ff3897..366569425c52 100644
--- a/arch/metag/kernel/perf/perf_event.c
+++ b/arch/metag/kernel/perf/perf_event.c
@@ -22,9 +22,9 @@
 #include <linux/slab.h>
 
 #include <asm/core_reg.h>
-#include <asm/hwthread.h>
 #include <asm/io.h>
 #include <asm/irq.h>
+#include <asm/processor.h>
 
 #include "perf_event.h"
 
@@ -40,10 +40,10 @@ static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
 /* PMU admin */
 const char *perf_pmu_name(void)
 {
-        if (metag_pmu)
-                return metag_pmu->pmu.name;
+        if (!metag_pmu)
+                return NULL;
 
-        return NULL;
+        return metag_pmu->name;
 }
 EXPORT_SYMBOL_GPL(perf_pmu_name);
 
@@ -171,6 +171,7 @@ static int metag_pmu_event_init(struct perf_event *event)
         switch (event->attr.type) {
         case PERF_TYPE_HARDWARE:
         case PERF_TYPE_HW_CACHE:
+        case PERF_TYPE_RAW:
                 err = _hw_perf_event_init(event);
                 break;
 
@@ -211,9 +212,10 @@ again:
         /*
          * Calculate the delta and add it to the counter.
          */
-        delta = new_raw_count - prev_raw_count;
+        delta = (new_raw_count - prev_raw_count) & MAX_PERIOD;
 
         local64_add(delta, &event->count);
+        local64_sub(delta, &hwc->period_left);
 }
 
 int metag_pmu_event_set_period(struct perf_event *event,
@@ -223,6 +225,10 @@ int metag_pmu_event_set_period(struct perf_event *event,
         s64 period = hwc->sample_period;
         int ret = 0;
 
+        /* The period may have been changed */
+        if (unlikely(period != hwc->last_period))
+                left += period - hwc->last_period;
+
         if (unlikely(left <= -period)) {
                 left = period;
                 local64_set(&hwc->period_left, left);
@@ -240,8 +246,10 @@ int metag_pmu_event_set_period(struct perf_event *event,
         if (left > (s64)metag_pmu->max_period)
                 left = metag_pmu->max_period;
 
-        if (metag_pmu->write)
-                metag_pmu->write(idx, (u64)(-left) & MAX_PERIOD);
+        if (metag_pmu->write) {
+                local64_set(&hwc->prev_count, -(s32)left);
+                metag_pmu->write(idx, -left & MAX_PERIOD);
+        }
 
         perf_event_update_userpage(event);
 
@@ -549,6 +557,10 @@ static int _hw_perf_event_init(struct perf_event *event)
                 if (err)
                         return err;
                 break;
+
+        case PERF_TYPE_RAW:
+                mapping = attr->config;
+                break;
         }
 
         /* Return early if the event is unsupported */
@@ -610,15 +622,13 @@ static void metag_pmu_enable_counter(struct hw_perf_event *event, int idx)
                 WARN_ONCE((config != 0x100),
                         "invalid configuration (%d) for counter (%d)\n",
                         config, idx);
-
-                /* Reset the cycle count */
-                __core_reg_set(TXTACTCYC, 0);
+                local64_set(&event->prev_count, __core_reg_get(TXTACTCYC));
                 goto unlock;
         }
 
         /* Check for a core internal or performance channel event. */
         if (tmp) {
-                void *perf_addr = (void *)PERF_COUNT(idx);
+                void *perf_addr;
 
                 /*
                  * Anything other than a cycle count will write the low-
@@ -632,9 +642,14 @@ static void metag_pmu_enable_counter(struct hw_perf_event *event, int idx)
                 case 0xf0:
                         perf_addr = (void *)PERF_CHAN(idx);
                         break;
+
+                default:
+                        perf_addr = NULL;
+                        break;
                 }
 
-                metag_out32((tmp & 0x0f), perf_addr);
+                if (perf_addr)
+                        metag_out32((config & 0x0f), perf_addr);
 
                 /*
                  * Now we use the high nibble as the performance event to
@@ -643,13 +658,21 @@ static void metag_pmu_enable_counter(struct hw_perf_event *event, int idx)
                 config = tmp >> 4;
         }
 
-        /*
-         * Enabled counters start from 0. Early cores clear the count on
-         * write but newer cores don't, so we make sure that the count is
-         * set to 0.
-         */
         tmp = ((config & 0xf) << 28) |
-                        ((1 << 24) << cpu_2_hwthread_id[get_cpu()]);
+                        ((1 << 24) << hard_processor_id());
+        if (metag_pmu->max_period)
+                /*
+                 * Cores supporting overflow interrupts may have had the counter
+                 * set to a specific value that needs preserving.
+                 */
+                tmp |= metag_in32(PERF_COUNT(idx)) & 0x00ffffff;
+        else
+                /*
+                 * Older cores reset the counter on write, so prev_count needs
+                 * resetting too so we can calculate a correct delta.
+                 */
+                local64_set(&event->prev_count, 0);
+
         metag_out32(tmp, PERF_COUNT(idx));
 unlock:
         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
@@ -693,9 +716,8 @@ static u64 metag_pmu_read_counter(int idx)
 {
         u32 tmp = 0;
 
-        /* The act of reading the cycle counter also clears it */
         if (METAG_INST_COUNTER == idx) {
-                __core_reg_swap(TXTACTCYC, tmp);
+                tmp = __core_reg_get(TXTACTCYC);
                 goto out;
         }
 
@@ -764,10 +786,16 @@ static irqreturn_t metag_pmu_counter_overflow(int irq, void *dev)
 
         /*
          * Enable the counter again once core overflow processing has
-         * completed.
+         * completed. Note the counter value may have been modified while it was
+         * inactive to set it up ready for the next interrupt.
          */
-        if (!perf_event_overflow(event, &sampledata, regs))
+        if (!perf_event_overflow(event, &sampledata, regs)) {
+                __global_lock2(flags);
+                counter = (counter & 0xff000000) |
+                          (metag_in32(PERF_COUNT(idx)) & 0x00ffffff);
                 metag_out32(counter, PERF_COUNT(idx));
+                __global_unlock2(flags);
+        }
 
         return IRQ_HANDLED;
 }
@@ -830,7 +858,7 @@ static int __init init_hw_perf_events(void)
                         metag_pmu->max_period = 0;
                 }
 
-                metag_pmu->name = "Meta 2";
+                metag_pmu->name = "meta2";
                 metag_pmu->version = version;
                 metag_pmu->pmu = pmu;
         }
diff --git a/arch/metag/kernel/process.c b/arch/metag/kernel/process.c
index c6efe62e5b76..483dff986a23 100644
--- a/arch/metag/kernel/process.c
+++ b/arch/metag/kernel/process.c
@@ -22,6 +22,7 @@
 #include <linux/pm.h>
 #include <linux/syscalls.h>
 #include <linux/uaccess.h>
+#include <linux/smp.h>
 #include <asm/core_reg.h>
 #include <asm/user_gateway.h>
 #include <asm/tcm.h>
@@ -31,7 +32,7 @@
 /*
  * Wait for the next interrupt and enable local interrupts
  */
-static inline void arch_idle(void)
+void arch_cpu_idle(void)
 {
         int tmp;
 
@@ -59,36 +60,12 @@ static inline void arch_idle(void)
                       : "r" (get_trigger_mask()));
 }
 
-void cpu_idle(void)
-{
-        set_thread_flag(TIF_POLLING_NRFLAG);
-
-        while (1) {
-                tick_nohz_idle_enter();
-                rcu_idle_enter();
-
-                while (!need_resched()) {
-                        /*
-                         * We need to disable interrupts here to ensure we don't
-                         * miss a wakeup call.
-                         */
-                        local_irq_disable();
-                        if (!need_resched()) {
 #ifdef CONFIG_HOTPLUG_CPU
-                                if (cpu_is_offline(smp_processor_id()))
-                                        cpu_die();
-#endif
-                                arch_idle();
-                        } else {
-                                local_irq_enable();
-                        }
-                }
-
-                rcu_idle_exit();
-                tick_nohz_idle_exit();
-                schedule_preempt_disabled();
-         }
+void arch_cpu_idle_dead(void)
+{
+        cpu_die();
 }
+#endif
 
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
@@ -152,6 +129,8 @@ void show_regs(struct pt_regs *regs)
                 "D1.7 "
         };
 
+        show_regs_print_info(KERN_INFO);
+
         pr_info(" pt_regs @ %p\n", regs);
         pr_info(" SaveMask = 0x%04hx\n", regs->ctx.SaveMask);
         pr_info(" Flags = 0x%04hx (%c%c%c%c)\n", regs->ctx.Flags,
diff --git a/arch/metag/kernel/ptrace.c b/arch/metag/kernel/ptrace.c
index 47a8828615a5..7563628822bd 100644
--- a/arch/metag/kernel/ptrace.c
+++ b/arch/metag/kernel/ptrace.c
@@ -288,10 +288,36 @@ static int metag_rp_state_set(struct task_struct *target,
         return metag_rp_state_copyin(regs, pos, count, kbuf, ubuf);
 }
 
+static int metag_tls_get(struct task_struct *target,
+                        const struct user_regset *regset,
+                        unsigned int pos, unsigned int count,
+                        void *kbuf, void __user *ubuf)
+{
+        void __user *tls = target->thread.tls_ptr;
+        return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &tls, 0, -1);
+}
+
+static int metag_tls_set(struct task_struct *target,
+                        const struct user_regset *regset,
+                        unsigned int pos, unsigned int count,
+                        const void *kbuf, const void __user *ubuf)
+{
+        int ret;
+        void __user *tls;
+
+        ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &tls, 0, -1);
+        if (ret)
+                return ret;
+
+        target->thread.tls_ptr = tls;
+        return ret;
+}
+
 enum metag_regset {
         REGSET_GENERAL,
         REGSET_CBUF,
         REGSET_READPIPE,
+        REGSET_TLS,
 };
 
 static const struct user_regset metag_regsets[] = {
@@ -319,6 +345,14 @@ static const struct user_regset metag_regsets[] = {
                 .get = metag_rp_state_get,
                 .set = metag_rp_state_set,
         },
+        [REGSET_TLS] = {
+                .core_note_type = NT_METAG_TLS,
+                .n = 1,
+                .size = sizeof(void *),
+                .align = sizeof(void *),
+                .get = metag_tls_get,
+                .set = metag_tls_set,
+        },
 };
 
 static const struct user_regset_view user_metag_view = {
diff --git a/arch/metag/kernel/setup.c b/arch/metag/kernel/setup.c
index 879246170aec..4f5726f1a55b 100644
--- a/arch/metag/kernel/setup.c
+++ b/arch/metag/kernel/setup.c
@@ -124,6 +124,7 @@ struct machine_desc *machine_desc __initdata;
 u8 cpu_2_hwthread_id[NR_CPUS] __read_mostly = {
         [0 ... NR_CPUS-1] = BAD_HWTHREAD_ID
 };
+EXPORT_SYMBOL_GPL(cpu_2_hwthread_id);
 
 /*
  * Map a hardware thread ID to a Linux CPU number
diff --git a/arch/metag/kernel/smp.c b/arch/metag/kernel/smp.c
index 4b6d1f14df32..f443ec9a7cbe 100644
--- a/arch/metag/kernel/smp.c
+++ b/arch/metag/kernel/smp.c
@@ -28,6 +28,8 @@
 #include <asm/cachepart.h>
 #include <asm/core_reg.h>
 #include <asm/cpu.h>
+#include <asm/global_lock.h>
+#include <asm/metag_mem.h>
 #include <asm/mmu_context.h>
 #include <asm/pgtable.h>
 #include <asm/pgalloc.h>
@@ -37,6 +39,9 @@
 #include <asm/hwthread.h>
 #include <asm/traps.h>
 
+#define SYSC_DCPART(n)  (SYSC_DCPART0 + SYSC_xCPARTn_STRIDE * (n))
+#define SYSC_ICPART(n)  (SYSC_ICPART0 + SYSC_xCPARTn_STRIDE * (n))
+
 DECLARE_PER_CPU(PTBI, pTBI);
 
 void *secondary_data_stack;
@@ -99,6 +104,114 @@ int __cpuinit boot_secondary(unsigned int thread, struct task_struct *idle)
         return 0;
 }
 
+/**
+ * describe_cachepart_change: describe a change to cache partitions.
+ * @thread:     Hardware thread number.
+ * @label:      Label of cache type, e.g. "dcache" or "icache".
+ * @sz:         Total size of the cache.
+ * @old:        Old cache partition configuration (*CPART* register).
+ * @new:        New cache partition configuration (*CPART* register).
+ *
+ * If the cache partition has changed, prints a message to the log describing
+ * those changes.
+ */
+static __cpuinit void describe_cachepart_change(unsigned int thread,
+                                                const char *label,
+                                                unsigned int sz,
+                                                unsigned int old,
+                                                unsigned int new)
+{
+        unsigned int lor1, land1, gor1, gand1;
+        unsigned int lor2, land2, gor2, gand2;
+        unsigned int diff = old ^ new;
+
+        if (!diff)
+                return;
+
+        pr_info("Thread %d: %s partition changed:", thread, label);
+        if (diff & (SYSC_xCPARTL_OR_BITS | SYSC_xCPARTL_AND_BITS)) {
+                lor1   = (old & SYSC_xCPARTL_OR_BITS)  >> SYSC_xCPARTL_OR_S;
+                lor2   = (new & SYSC_xCPARTL_OR_BITS)  >> SYSC_xCPARTL_OR_S;
+                land1  = (old & SYSC_xCPARTL_AND_BITS) >> SYSC_xCPARTL_AND_S;
+                land2  = (new & SYSC_xCPARTL_AND_BITS) >> SYSC_xCPARTL_AND_S;
+                pr_cont(" L:%#x+%#x->%#x+%#x",
+                        (lor1 * sz) >> 4,
+                        ((land1 + 1) * sz) >> 4,
+                        (lor2 * sz) >> 4,
+                        ((land2 + 1) * sz) >> 4);
+        }
+        if (diff & (SYSC_xCPARTG_OR_BITS | SYSC_xCPARTG_AND_BITS)) {
+                gor1   = (old & SYSC_xCPARTG_OR_BITS)  >> SYSC_xCPARTG_OR_S;
+                gor2   = (new & SYSC_xCPARTG_OR_BITS)  >> SYSC_xCPARTG_OR_S;
+                gand1  = (old & SYSC_xCPARTG_AND_BITS) >> SYSC_xCPARTG_AND_S;
+                gand2  = (new & SYSC_xCPARTG_AND_BITS) >> SYSC_xCPARTG_AND_S;
+                pr_cont(" G:%#x+%#x->%#x+%#x",
+                        (gor1 * sz) >> 4,
+                        ((gand1 + 1) * sz) >> 4,
+                        (gor2 * sz) >> 4,
+                        ((gand2 + 1) * sz) >> 4);
+        }
+        if (diff & SYSC_CWRMODE_BIT)
+                pr_cont(" %sWR",
+                        (new & SYSC_CWRMODE_BIT) ? "+" : "-");
+        if (diff & SYSC_DCPART_GCON_BIT)
+                pr_cont(" %sGCOn",
+                        (new & SYSC_DCPART_GCON_BIT) ? "+" : "-");
+        pr_cont("\n");
+}
+
+/**
+ * setup_smp_cache: ensure cache coherency for new SMP thread.
+ * @thread:     New hardware thread number.
+ *
+ * Ensures that coherency is enabled and that the threads share the same cache
+ * partitions.
+ */
+static __cpuinit void setup_smp_cache(unsigned int thread)
+{
+        unsigned int this_thread, lflags;
+        unsigned int dcsz, dcpart_this, dcpart_old, dcpart_new;
+        unsigned int icsz, icpart_old, icpart_new;
+
+        /*
+         * Copy over the current thread's cache partition configuration to the
+         * new thread so that they share cache partitions.
+         */
+        __global_lock2(lflags);
+        this_thread = hard_processor_id();
+        /* Share dcache partition */
+        dcpart_this = metag_in32(SYSC_DCPART(this_thread));
+        dcpart_old = metag_in32(SYSC_DCPART(thread));
+        dcpart_new = dcpart_this;
+#if PAGE_OFFSET < LINGLOBAL_BASE
+        /*
+         * For the local data cache to be coherent the threads must also have
+         * GCOn enabled.
+         */
+        dcpart_new |= SYSC_DCPART_GCON_BIT;
+        metag_out32(dcpart_new, SYSC_DCPART(this_thread));
+#endif
+        metag_out32(dcpart_new, SYSC_DCPART(thread));
+        /* Share icache partition too */
+        icpart_new = metag_in32(SYSC_ICPART(this_thread));
+        icpart_old = metag_in32(SYSC_ICPART(thread));
+        metag_out32(icpart_new, SYSC_ICPART(thread));
+        __global_unlock2(lflags);
+
+        /*
+         * Log if the cache partitions were altered so the user is aware of any
+         * potential unintentional cache wastage.
+         */
+        dcsz = get_dcache_size();
+        icsz = get_dcache_size();
+        describe_cachepart_change(this_thread, "dcache", dcsz,
+                                  dcpart_this, dcpart_new);
+        describe_cachepart_change(thread, "dcache", dcsz,
+                                  dcpart_old, dcpart_new);
+        describe_cachepart_change(thread, "icache", icsz,
+                                  icpart_old, icpart_new);
+}
+
 int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
 {
         unsigned int thread = cpu_2_hwthread_id[cpu];
@@ -108,6 +221,8 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
 
         flush_tlb_all();
 
+        setup_smp_cache(thread);
+
         /*
          * Tell the secondary CPU where to find its idle thread's stack.
          */
@@ -297,7 +412,7 @@ asmlinkage void secondary_start_kernel(void)
         /*
          * OK, it's off to the idle thread for us
          */
-        cpu_idle();
+        cpu_startup_entry(CPUHP_ONLINE);
 }
 
 void __init smp_cpus_done(unsigned int max_cpus)
diff --git a/arch/metag/kernel/traps.c b/arch/metag/kernel/traps.c
index 8961f247b500..2ceeaae5b199 100644
--- a/arch/metag/kernel/traps.c
+++ b/arch/metag/kernel/traps.c
@@ -987,9 +987,3 @@ void show_stack(struct task_struct *tsk, unsigned long *sp)
 
         show_trace(tsk, sp, NULL);
 }
-
-void dump_stack(void)
-{
-        show_stack(NULL, NULL);
-}
-EXPORT_SYMBOL(dump_stack);
diff --git a/arch/metag/mm/Kconfig b/arch/metag/mm/Kconfig
index 975f2f4e3ecf..03fb8f1555a1 100644
--- a/arch/metag/mm/Kconfig
+++ b/arch/metag/mm/Kconfig
@@ -93,14 +93,6 @@ config ARCH_SPARSEMEM_ENABLE
 config ARCH_SPARSEMEM_DEFAULT
         def_bool y
 
-config MAX_ACTIVE_REGIONS
-        int
-        default "2" if SPARSEMEM
-        default "1"
-
-config ARCH_POPULATES_NODE_MAP
-        def_bool y
-
 config ARCH_SELECT_MEMORY_MODEL
         def_bool y
 
diff --git a/arch/metag/mm/init.c b/arch/metag/mm/init.c
index 504a398d5f8b..d05b8455c44c 100644
--- a/arch/metag/mm/init.c
+++ b/arch/metag/mm/init.c
@@ -380,14 +380,8 @@ void __init mem_init(void)
 
 #ifdef CONFIG_HIGHMEM
         unsigned long tmp;
-        for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) {
-                struct page *page = pfn_to_page(tmp);
-                ClearPageReserved(page);
-                init_page_count(page);
-                __free_page(page);
-                totalhigh_pages++;
-        }
-        totalram_pages += totalhigh_pages;
+        for (tmp = highstart_pfn; tmp < highend_pfn; tmp++)
+                free_highmem_page(pfn_to_page(tmp));
         num_physpages += totalhigh_pages;
 #endif /* CONFIG_HIGHMEM */
 
@@ -412,32 +406,15 @@ void __init mem_init(void)
         return;
 }
 
-static void free_init_pages(char *what, unsigned long begin, unsigned long end)
-{
-        unsigned long addr;
-
-        for (addr = begin; addr < end; addr += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(addr));
-                init_page_count(virt_to_page(addr));
-                memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
-                free_page(addr);
-                totalram_pages++;
-        }
-        pr_info("Freeing %s: %luk freed\n", what, (end - begin) >> 10);
-}
-
 void free_initmem(void)
 {
-        free_init_pages("unused kernel memory",
-                        (unsigned long)(&__init_begin),
-                        (unsigned long)(&__init_end));
+        free_initmem_default(POISON_FREE_INITMEM);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        end = end & PAGE_MASK;
-        free_init_pages("initrd memory", start, end);
+        free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
 }
 #endif
 
diff --git a/arch/metag/oprofile/Makefile b/arch/metag/oprofile/Makefile
new file mode 100644
index 000000000000..c9639d4734d6
--- /dev/null
+++ b/arch/metag/oprofile/Makefile
@@ -0,0 +1,17 @@
+obj-$(CONFIG_OPROFILE)  += oprofile.o
+
+oprofile-core-y += buffer_sync.o
+oprofile-core-y += cpu_buffer.o
+oprofile-core-y += event_buffer.o
+oprofile-core-y += oprof.o
+oprofile-core-y += oprofile_files.o
+oprofile-core-y += oprofile_stats.o
+oprofile-core-y += oprofilefs.o
+oprofile-core-y += timer_int.o
+oprofile-core-$(CONFIG_HW_PERF_EVENTS)  += oprofile_perf.o
+
+oprofile-y      += backtrace.o
+oprofile-y      += common.o
+oprofile-y      += $(addprefix ../../../drivers/oprofile/,$(oprofile-core-y))
+
+ccflags-y       += -Werror
diff --git a/arch/metag/oprofile/backtrace.c b/arch/metag/oprofile/backtrace.c
new file mode 100644
index 000000000000..7cc3f37cb40e
--- /dev/null
+++ b/arch/metag/oprofile/backtrace.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2010-2013 Imagination Technologies Ltd.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/oprofile.h>
+#include <linux/uaccess.h>
+#include <asm/processor.h>
+#include <asm/stacktrace.h>
+
+#include "backtrace.h"
+
+static void user_backtrace_fp(unsigned long __user *fp, unsigned int depth)
+{
+        while (depth-- && access_ok(VERIFY_READ, fp, 8)) {
+                unsigned long addr;
+                unsigned long __user *fpnew;
+                if (__copy_from_user_inatomic(&addr, fp + 1, sizeof(addr)))
+                        break;
+                addr -= 4;
+
+                oprofile_add_trace(addr);
+
+                /* stack grows up, so frame pointers must decrease */
+                if (__copy_from_user_inatomic(&fpnew, fp + 0, sizeof(fpnew)))
+                        break;
+                if (fpnew >= fp)
+                        break;
+                fp = fpnew;
+        }
+}
+
+static int kernel_backtrace_frame(struct stackframe *frame, void *data)
+{
+        unsigned int *depth = data;
+
+        oprofile_add_trace(frame->pc);
+
+        /* decrement depth and stop if we reach 0 */
+        if ((*depth)-- == 0)
+                return 1;
+
+        /* otherwise onto the next frame */
+        return 0;
+}
+
+void metag_backtrace(struct pt_regs * const regs, unsigned int depth)
+{
+        if (user_mode(regs)) {
+                unsigned long *fp = (unsigned long *)regs->ctx.AX[1].U0;
+                user_backtrace_fp((unsigned long __user __force *)fp, depth);
+        } else {
+                struct stackframe frame;
+                frame.fp = regs->ctx.AX[1].U0;          /* A0FrP */
+                frame.sp = user_stack_pointer(regs);    /* A0StP */
+                frame.lr = 0;                           /* from stack */
+                frame.pc = regs->ctx.CurrPC;            /* PC */
+                walk_stackframe(&frame, &kernel_backtrace_frame, &depth);
+        }
+}
diff --git a/arch/metag/oprofile/backtrace.h b/arch/metag/oprofile/backtrace.h
new file mode 100644
index 000000000000..c0fcc4265abb
--- /dev/null
+++ b/arch/metag/oprofile/backtrace.h
@@ -0,0 +1,6 @@
+#ifndef _METAG_OPROFILE_BACKTRACE_H
+#define _METAG_OPROFILE_BACKTRACE_H
+
+void metag_backtrace(struct pt_regs * const regs, unsigned int depth);
+
+#endif
diff --git a/arch/metag/oprofile/common.c b/arch/metag/oprofile/common.c
new file mode 100644
index 000000000000..ba26152b3c00
--- /dev/null
+++ b/arch/metag/oprofile/common.c
@@ -0,0 +1,66 @@
+/*
+ * arch/metag/oprofile/common.c
+ *
+ * Copyright (C) 2013 Imagination Technologies Ltd.
+ *
+ * Based on arch/sh/oprofile/common.c:
+ *
+ * Copyright (C) 2003 - 2010  Paul Mundt
+ *
+ * Based on arch/mips/oprofile/common.c:
+ *
+ *      Copyright (C) 2004, 2005 Ralf Baechle
+ *      Copyright (C) 2005 MIPS Technologies, Inc.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/oprofile.h>
+#include <linux/perf_event.h>
+#include <linux/slab.h>
+
+#include "backtrace.h"
+
+#ifdef CONFIG_HW_PERF_EVENTS
+/*
+ * This will need to be reworked when multiple PMUs are supported.
+ */
+static char *metag_pmu_op_name;
+
+char *op_name_from_perf_id(void)
+{
+        return metag_pmu_op_name;
+}
+
+int __init oprofile_arch_init(struct oprofile_operations *ops)
+{
+        ops->backtrace = metag_backtrace;
+
+        if (perf_num_counters() == 0)
+                return -ENODEV;
+
+        metag_pmu_op_name = kasprintf(GFP_KERNEL, "metag/%s",
+                                      perf_pmu_name());
+        if (unlikely(!metag_pmu_op_name))
+                return -ENOMEM;
+
+        return oprofile_perf_init(ops);
+}
+
+void oprofile_arch_exit(void)
+{
+        oprofile_perf_exit();
+        kfree(metag_pmu_op_name);
+}
+#else
+int __init oprofile_arch_init(struct oprofile_operations *ops)
+{
+        ops->backtrace = metag_backtrace;
+        /* fall back to timer interrupt PC sampling */
+        return -ENODEV;
+}
+void oprofile_arch_exit(void) {}
+#endif /* CONFIG_HW_PERF_EVENTS */
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 1323fa2530eb..54237af0b07c 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -26,6 +26,7 @@ config MICROBLAZE
         select GENERIC_CPU_DEVICES
         select GENERIC_ATOMIC64
         select GENERIC_CLOCKEVENTS
+        select GENERIC_IDLE_POLL_SETUP
         select MODULES_USE_ELF_RELA
         select CLONE_BACKWARDS
 
@@ -38,9 +39,6 @@ config RWSEM_GENERIC_SPINLOCK
 config ZONE_DMA
         def_bool y
 
-config ARCH_POPULATES_NODE_MAP
-        def_bool y
-
 config RWSEM_XCHGADD_ALGORITHM
         bool
 
diff --git a/arch/microblaze/include/asm/processor.h b/arch/microblaze/include/asm/processor.h
index 0759153e8117..d6e0ffea28b6 100644
--- a/arch/microblaze/include/asm/processor.h
+++ b/arch/microblaze/include/asm/processor.h
@@ -22,7 +22,6 @@
 extern const struct seq_operations cpuinfo_op;
 
 # define cpu_relax()            barrier()
-# define cpu_sleep()            do {} while (0)
 
 #define task_pt_regs(tsk) \
                 (((struct pt_regs *)(THREAD_SIZE + task_stack_page(tsk))) - 1)
@@ -160,10 +159,6 @@ unsigned long get_wchan(struct task_struct *p);
 #  define STACK_TOP     TASK_SIZE
 #  define STACK_TOP_MAX STACK_TOP
 
-void disable_hlt(void);
-void enable_hlt(void);
-void default_idle(void);
-
 #ifdef CONFIG_DEBUG_FS
 extern struct dentry *of_debugfs_root;
 #endif
diff --git a/arch/microblaze/include/asm/setup.h b/arch/microblaze/include/asm/setup.h
index 0e0b0a5ec756..f05df5630c84 100644
--- a/arch/microblaze/include/asm/setup.h
+++ b/arch/microblaze/include/asm/setup.h
@@ -46,7 +46,6 @@ void machine_shutdown(void);
 void machine_halt(void);
 void machine_power_off(void);
 
-void free_init_pages(char *what, unsigned long begin, unsigned long end);
 extern void *alloc_maybe_bootmem(size_t size, gfp_t mask);
 extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
 
diff --git a/arch/microblaze/include/asm/thread_info.h b/arch/microblaze/include/asm/thread_info.h
index 008f30433d22..de26ea6373de 100644
--- a/arch/microblaze/include/asm/thread_info.h
+++ b/arch/microblaze/include/asm/thread_info.h
@@ -182,7 +182,6 @@ static inline bool test_and_clear_restore_sigmask(void)
         ti->status &= ~TS_RESTORE_SIGMASK;
         return true;
 }
-#define tsk_is_polling(t) test_tsk_thread_flag(t, TIF_POLLING_NRFLAG)
 #endif
 
 #endif /* __KERNEL__ */
diff --git a/arch/microblaze/include/asm/unistd.h b/arch/microblaze/include/asm/unistd.h
index b3778391d9cc..6dece2d002dc 100644
--- a/arch/microblaze/include/asm/unistd.h
+++ b/arch/microblaze/include/asm/unistd.h
@@ -37,13 +37,5 @@
 #define __ARCH_WANT_SYS_VFORK
 #define __ARCH_WANT_SYS_FORK
 
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall");
-
 #endif /* __ASSEMBLY__ */
 #endif /* _ASM_MICROBLAZE_UNISTD_H */
diff --git a/arch/microblaze/kernel/early_printk.c b/arch/microblaze/kernel/early_printk.c
index 60dcacc68038..365f2d53f1b2 100644
--- a/arch/microblaze/kernel/early_printk.c
+++ b/arch/microblaze/kernel/early_printk.c
@@ -21,7 +21,6 @@
 #include <asm/setup.h>
 #include <asm/prom.h>
 
-static u32 early_console_initialized;
 static u32 base_addr;
 
 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
@@ -109,27 +108,11 @@ static struct console early_serial_uart16550_console = {
 };
 #endif /* CONFIG_SERIAL_8250_CONSOLE */
 
-static struct console *early_console;
-
-void early_printk(const char *fmt, ...)
-{
-        char buf[512];
-        int n;
-        va_list ap;
-
-        if (early_console_initialized) {
-                va_start(ap, fmt);
-                n = vscnprintf(buf, 512, fmt, ap);
-                early_console->write(early_console, buf, n);
-                va_end(ap);
-        }
-}
-
 int __init setup_early_printk(char *opt)
 {
         int version = 0;
 
-        if (early_console_initialized)
+        if (early_console)
                 return 1;
 
         base_addr = of_early_console(&version);
@@ -159,7 +142,6 @@ int __init setup_early_printk(char *opt)
                 }
 
                 register_console(early_console);
-                early_console_initialized = 1;
                 return 0;
         }
         return 1;
@@ -169,7 +151,7 @@ int __init setup_early_printk(char *opt)
  * only for early console because of performance degression */
 void __init remap_early_printk(void)
 {
-        if (!early_console_initialized || !early_console)
+        if (!early_console)
                 return;
         pr_info("early_printk_console remapping from 0x%x to ", base_addr);
         base_addr = (u32) ioremap(base_addr, PAGE_SIZE);
@@ -194,9 +176,9 @@ void __init remap_early_printk(void)
 
 void __init disable_early_printk(void)
 {
-        if (!early_console_initialized || !early_console)
+        if (!early_console)
                 return;
         pr_warn("disabling early console\n");
         unregister_console(early_console);
-        early_console_initialized = 0;
+        early_console = NULL;
 }
diff --git a/arch/microblaze/kernel/process.c b/arch/microblaze/kernel/process.c
index fa0ea609137c..a55893807274 100644
--- a/arch/microblaze/kernel/process.c
+++ b/arch/microblaze/kernel/process.c
@@ -20,6 +20,8 @@
 
 void show_regs(struct pt_regs *regs)
 {
+        show_regs_print_info(KERN_INFO);
+
         pr_info(" Registers dump: mode=%X\r\n", regs->pt_mode);
         pr_info(" r1=%08lX, r2=%08lX, r3=%08lX, r4=%08lX\n",
                                 regs->r1, regs->r2, regs->r3, regs->r4);
@@ -44,71 +46,6 @@ void show_regs(struct pt_regs *regs)
 void (*pm_power_off)(void) = NULL;
 EXPORT_SYMBOL(pm_power_off);
 
-static int hlt_counter = 1;
-
-void disable_hlt(void)
-{
-        hlt_counter++;
-}
-EXPORT_SYMBOL(disable_hlt);
-
-void enable_hlt(void)
-{
-        hlt_counter--;
-}
-EXPORT_SYMBOL(enable_hlt);
-
-static int __init nohlt_setup(char *__unused)
-{
-        hlt_counter = 1;
-        return 1;
-}
-__setup("nohlt", nohlt_setup);
-
-static int __init hlt_setup(char *__unused)
-{
-        hlt_counter = 0;
-        return 1;
-}
-__setup("hlt", hlt_setup);
-
-void default_idle(void)
-{
-        if (likely(hlt_counter)) {
-                local_irq_disable();
-                stop_critical_timings();
-                cpu_relax();
-                start_critical_timings();
-                local_irq_enable();
-        } else {
-                clear_thread_flag(TIF_POLLING_NRFLAG);
-                smp_mb__after_clear_bit();
-                local_irq_disable();
-                while (!need_resched())
-                        cpu_sleep();
-                local_irq_enable();
-                set_thread_flag(TIF_POLLING_NRFLAG);
-        }
-}
-
-void cpu_idle(void)
-{
-        set_thread_flag(TIF_POLLING_NRFLAG);
-
-        /* endless idle loop with no priority at all */
-        while (1) {
-                tick_nohz_idle_enter();
-                rcu_idle_enter();
-                while (!need_resched())
-                        default_idle();
-                rcu_idle_exit();
-                tick_nohz_idle_exit();
-
-                schedule_preempt_disabled();
-                check_pgt_cache();
-        }
-}
-
 void flush_thread(void)
 {
 }
diff --git a/arch/microblaze/kernel/traps.c b/arch/microblaze/kernel/traps.c
index 30e6b5004a6a..cb619533a192 100644
--- a/arch/microblaze/kernel/traps.c
+++ b/arch/microblaze/kernel/traps.c
@@ -75,9 +75,3 @@ void show_stack(struct task_struct *task, unsigned long *sp)
 
         debug_show_held_locks(task);
 }
-
-void dump_stack(void)
-{
-        show_stack(NULL, NULL);
-}
-EXPORT_SYMBOL(dump_stack);
diff --git a/arch/microblaze/mm/init.c b/arch/microblaze/mm/init.c
index 8f8b367c079e..4ec137d13ad7 100644
--- a/arch/microblaze/mm/init.c
+++ b/arch/microblaze/mm/init.c
@@ -82,13 +82,9 @@ static unsigned long highmem_setup(void)
                 /* FIXME not sure about */
                 if (memblock_is_reserved(pfn << PAGE_SHIFT))
                         continue;
-                ClearPageReserved(page);
-                init_page_count(page);
-                __free_page(page);
-                totalhigh_pages++;
+                free_highmem_page(page);
                 reservedpages++;
         }
-        totalram_pages += totalhigh_pages;
         pr_info("High memory: %luk\n",
                                         totalhigh_pages << (PAGE_SHIFT-10));
 
@@ -236,40 +232,16 @@ void __init setup_memory(void)
         paging_init();
 }
 
-void free_init_pages(char *what, unsigned long begin, unsigned long end)
-{
-        unsigned long addr;
-
-        for (addr = begin; addr < end; addr += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(addr));
-                init_page_count(virt_to_page(addr));
-                free_page(addr);
-                totalram_pages++;
-        }
-        pr_info("Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
-}
-
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        int pages = 0;
-        for (; start < end; start += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(start));
-                init_page_count(virt_to_page(start));
-                free_page(start);
-                totalram_pages++;
-                pages++;
-        }
-        pr_notice("Freeing initrd memory: %dk freed\n",
-                                        (int)(pages * (PAGE_SIZE / 1024)));
+        free_reserved_area(start, end, 0, "initrd");
 }
 #endif
 
 void free_initmem(void)
 {
-        free_init_pages("unused kernel memory",
-                        (unsigned long)(&__init_begin),
-                        (unsigned long)(&__init_end));
+        free_initmem_default(0);
 }
 
 void __init mem_init(void)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 51244bf97271..e5f3794744f1 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -404,6 +404,8 @@ config PMC_MSP
         select IRQ_CPU
         select SERIAL_8250
         select SERIAL_8250_CONSOLE
+        select USB_EHCI_BIG_ENDIAN_MMIO
+        select USB_EHCI_BIG_ENDIAN_DESC
         help
           This adds support for the PMC-Sierra family of Multi-Service
           Processor System-On-A-Chips.  These parts include a number
@@ -1433,6 +1435,7 @@ config CPU_CAVIUM_OCTEON
         select CPU_SUPPORTS_HUGEPAGES
         select LIBFDT
         select USE_OF
+        select USB_EHCI_BIG_ENDIAN_MMIO
         help
           The Cavium Octeon processor is a highly integrated chip containing
           many ethernet hardware widgets for networking tasks. The processor
@@ -1736,7 +1739,6 @@ config 32BIT
 config 64BIT
         bool "64-bit kernel"
         depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
-        select HAVE_SYSCALL_WRAPPERS
         help
           Select this option if you want to build a 64-bit kernel.
 
@@ -2538,7 +2540,14 @@ source "kernel/power/Kconfig"
 
 endmenu
 
-source "arch/mips/kernel/cpufreq/Kconfig"
+config MIPS_EXTERNAL_TIMER
+        bool
+
+if CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
+menu "CPU Power Management"
+source "drivers/cpufreq/Kconfig"
+endmenu
+endif
 
 source "net/Kconfig"
 
diff --git a/arch/mips/bcm63xx/dev-spi.c b/arch/mips/bcm63xx/dev-spi.c
index f1c9c3e2f678..e97fd60e92ef 100644
--- a/arch/mips/bcm63xx/dev-spi.c
+++ b/arch/mips/bcm63xx/dev-spi.c
@@ -85,20 +85,9 @@ static struct platform_device bcm63xx_spi_device = {
 
 int __init bcm63xx_spi_register(void)
 {
-        struct clk *periph_clk;
-
         if (BCMCPU_IS_6328() || BCMCPU_IS_6345())
                 return -ENODEV;
 
-        periph_clk = clk_get(NULL, "periph");
-        if (IS_ERR(periph_clk)) {
-                pr_err("unable to get periph clock\n");
-                return -ENODEV;
-        }
-
-        /* Set bus frequency */
-        spi_pdata.speed_hz = clk_get_rate(periph_clk);
-
         spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
         spi_resources[0].end = spi_resources[0].start;
         spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h
index ef99db994c2f..fe0d15d32660 100644
--- a/arch/mips/include/asm/hugetlb.h
+++ b/arch/mips/include/asm/hugetlb.h
@@ -10,6 +10,7 @@
 #define __ASM_HUGETLB_H
 
 #include <asm/page.h>
+#include <asm-generic/hugetlb.h>
 
 
 static inline int is_hugepage_only_range(struct mm_struct *mm,
diff --git a/arch/mips/include/asm/linkage.h b/arch/mips/include/asm/linkage.h
index e9a940d1b0c6..2767dda9e309 100644
--- a/arch/mips/include/asm/linkage.h
+++ b/arch/mips/include/asm/linkage.h
@@ -6,5 +6,8 @@
 #endif
 
 #define __weak __attribute__((weak))
+#define cond_syscall(x) asm(".weak\t" #x "\n" #x "\t=\tsys_ni_syscall")
+#define SYSCALL_ALIAS(alias, name)                                      \
+        asm ( #alias " = " #name "\n\t.globl " #alias)
 
 #endif
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
index c9bae1362606..b0184cf02575 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
@@ -13,7 +13,6 @@ struct bcm63xx_spi_pdata {
         unsigned int    msg_ctl_width;
         int             bus_num;
         int             num_chipselect;
-        u32             speed_hz;
 };
 
 enum bcm63xx_regs_spi {
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index 99fc547af9d3..eab99e536b5c 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -31,7 +31,7 @@
 #define PAGE_SHIFT      16
 #endif
 #define PAGE_SIZE       (_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_MASK       (~(PAGE_SIZE - 1))
+#define PAGE_MASK       (~((1 << PAGE_SHIFT) - 1))
 
 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
 #define HPAGE_SHIFT     (PAGE_SHIFT + PAGE_SHIFT - 3)
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index 64f661e32879..63c9c886173a 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -63,12 +63,4 @@
 
 #endif /* !__ASSEMBLY__ */
 
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t" #x "\n" #x "\t=\tsys_ni_syscall")
-
 #endif /* _ASM_UNISTD_H */
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index de75fb50562b..520a908d45d6 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -92,8 +92,6 @@ CFLAGS_cpu-bugs64.o	= $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/n
 
 obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT)   += 8250-platform.o
 
-obj-$(CONFIG_MIPS_CPUFREQ)      += cpufreq/
-
 obj-$(CONFIG_PERF_EVENTS)       += perf_event.o
 obj-$(CONFIG_HW_PERF_EVENTS)    += perf_event_mipsxx.o
 
diff --git a/arch/mips/kernel/cpufreq/Kconfig b/arch/mips/kernel/cpufreq/Kconfig
deleted file mode 100644
index 58c601eee6fd..000000000000
--- a/arch/mips/kernel/cpufreq/Kconfig
+++ /dev/null
@@ -1,41 +0,0 @@
-#
-# CPU Frequency scaling
-#
-
-config MIPS_EXTERNAL_TIMER
-        bool
-
-config MIPS_CPUFREQ
-        bool
-        default y
-        depends on CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
-
-if MIPS_CPUFREQ
-
-menu "CPU Frequency scaling"
-
-source "drivers/cpufreq/Kconfig"
-
-if CPU_FREQ
-
-comment "CPUFreq processor drivers"
-
-config LOONGSON2_CPUFREQ
-        tristate "Loongson2 CPUFreq Driver"
-        select CPU_FREQ_TABLE
-        depends on MIPS_CPUFREQ
-        help
-          This option adds a CPUFreq driver for loongson processors which
-          support software configurable cpu frequency.
-
-          Loongson2F and it's successors support this feature.
-
-          For details, take a look at <file:Documentation/cpu-freq/>.
-
-          If in doubt, say N.
-
-endif   # CPU_FREQ
-
-endmenu
-
-endif   # MIPS_CPUFREQ
diff --git a/arch/mips/kernel/cpufreq/Makefile b/arch/mips/kernel/cpufreq/Makefile
deleted file mode 100644
index 05a5715ee38c..000000000000
--- a/arch/mips/kernel/cpufreq/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the Linux/MIPS cpufreq.
-#
-
-obj-$(CONFIG_LOONGSON2_CPUFREQ) += loongson2_cpufreq.o
diff --git a/arch/mips/kernel/cpufreq/loongson2_cpufreq.c b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
deleted file mode 100644
index 3237c5235f9c..000000000000
--- a/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * Cpufreq driver for the loongson-2 processors
- *
- * The 2E revision of loongson processor not support this feature.
- *
- * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology
- * Author: Yanhua, yanh@lemote.com
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/cpufreq.h>
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/sched.h>        /* set_cpus_allowed() */
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-
-#include <asm/clock.h>
-
-#include <asm/mach-loongson/loongson.h>
-
-static uint nowait;
-
-static struct clk *cpuclk;
-
-static void (*saved_cpu_wait) (void);
-
-static int loongson2_cpu_freq_notifier(struct notifier_block *nb,
-                                        unsigned long val, void *data);
-
-static struct notifier_block loongson2_cpufreq_notifier_block = {
-        .notifier_call = loongson2_cpu_freq_notifier
-};
-
-static int loongson2_cpu_freq_notifier(struct notifier_block *nb,
-                                        unsigned long val, void *data)
-{
-        if (val == CPUFREQ_POSTCHANGE)
-                current_cpu_data.udelay_val = loops_per_jiffy;
-
-        return 0;
-}
-
-static unsigned int loongson2_cpufreq_get(unsigned int cpu)
-{
-        return clk_get_rate(cpuclk);
-}
-
-/*
- * Here we notify other drivers of the proposed change and the final change.
- */
-static int loongson2_cpufreq_target(struct cpufreq_policy *policy,
-                                     unsigned int target_freq,
-                                     unsigned int relation)
-{
-        unsigned int cpu = policy->cpu;
-        unsigned int newstate = 0;
-        cpumask_t cpus_allowed;
-        struct cpufreq_freqs freqs;
-        unsigned int freq;
-
-        if (!cpu_online(cpu))
-                return -ENODEV;
-
-        cpus_allowed = current->cpus_allowed;
-        set_cpus_allowed_ptr(current, cpumask_of(cpu));
-
-        if (cpufreq_frequency_table_target
-            (policy, &loongson2_clockmod_table[0], target_freq, relation,
-             &newstate))
-                return -EINVAL;
-
-        freq =
-            ((cpu_clock_freq / 1000) *
-             loongson2_clockmod_table[newstate].index) / 8;
-        if (freq < policy->min || freq > policy->max)
-                return -EINVAL;
-
-        pr_debug("cpufreq: requested frequency %u Hz\n", target_freq * 1000);
-
-        freqs.cpu = cpu;
-        freqs.old = loongson2_cpufreq_get(cpu);
-        freqs.new = freq;
-        freqs.flags = 0;
-
-        if (freqs.new == freqs.old)
-                return 0;
-
-        /* notifiers */
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
-        set_cpus_allowed_ptr(current, &cpus_allowed);
-
-        /* setting the cpu frequency */
-        clk_set_rate(cpuclk, freq);
-
-        /* notifiers */
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
-        pr_debug("cpufreq: set frequency %u kHz\n", freq);
-
-        return 0;
-}
-
-static int loongson2_cpufreq_cpu_init(struct cpufreq_policy *policy)
-{
-        int i;
-        unsigned long rate;
-        int ret;
-
-        if (!cpu_online(policy->cpu))
-                return -ENODEV;
-
-        cpuclk = clk_get(NULL, "cpu_clk");
-        if (IS_ERR(cpuclk)) {
-                printk(KERN_ERR "cpufreq: couldn't get CPU clk\n");
-                return PTR_ERR(cpuclk);
-        }
-
-        rate = cpu_clock_freq / 1000;
-        if (!rate) {
-                clk_put(cpuclk);
-                return -EINVAL;
-        }
-        ret = clk_set_rate(cpuclk, rate);
-        if (ret) {
-                clk_put(cpuclk);
-                return ret;
-        }
-
-        /* clock table init */
-        for (i = 2;
-             (loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END);
-             i++)
-                loongson2_clockmod_table[i].frequency = (rate * i) / 8;
-
-        policy->cur = loongson2_cpufreq_get(policy->cpu);
-
-        cpufreq_frequency_table_get_attr(&loongson2_clockmod_table[0],
-                                         policy->cpu);
-
-        return cpufreq_frequency_table_cpuinfo(policy,
-                                            &loongson2_clockmod_table[0]);
-}
-
-static int loongson2_cpufreq_verify(struct cpufreq_policy *policy)
-{
-        return cpufreq_frequency_table_verify(policy,
-                                              &loongson2_clockmod_table[0]);
-}
-
-static int loongson2_cpufreq_exit(struct cpufreq_policy *policy)
-{
-        clk_put(cpuclk);
-        return 0;
-}
-
-static struct freq_attr *loongson2_table_attr[] = {
-        &cpufreq_freq_attr_scaling_available_freqs,
-        NULL,
-};
-
-static struct cpufreq_driver loongson2_cpufreq_driver = {
-        .owner = THIS_MODULE,
-        .name = "loongson2",
-        .init = loongson2_cpufreq_cpu_init,
-        .verify = loongson2_cpufreq_verify,
-        .target = loongson2_cpufreq_target,
-        .get = loongson2_cpufreq_get,
-        .exit = loongson2_cpufreq_exit,
-        .attr = loongson2_table_attr,
-};
-
-static struct platform_device_id platform_device_ids[] = {
-        {
-                .name = "loongson2_cpufreq",
-        },
-        {}
-};
-
-MODULE_DEVICE_TABLE(platform, platform_device_ids);
-
-static struct platform_driver platform_driver = {
-        .driver = {
-                .name = "loongson2_cpufreq",
-                .owner = THIS_MODULE,
-        },
-        .id_table = platform_device_ids,
-};
-
-/*
- * This is the simple version of Loongson-2 wait, Maybe we need do this in
- * interrupt disabled context.
- */
-
-static DEFINE_SPINLOCK(loongson2_wait_lock);
-
-static void loongson2_cpu_wait(void)
-{
-        unsigned long flags;
-        u32 cpu_freq;
-
-        spin_lock_irqsave(&loongson2_wait_lock, flags);
-        cpu_freq = LOONGSON_CHIPCFG0;
-        LOONGSON_CHIPCFG0 &= ~0x7;      /* Put CPU into wait mode */
-        LOONGSON_CHIPCFG0 = cpu_freq;   /* Restore CPU state */
-        spin_unlock_irqrestore(&loongson2_wait_lock, flags);
-}
-
-static int __init cpufreq_init(void)
-{
-        int ret;
-
-        /* Register platform stuff */
-        ret = platform_driver_register(&platform_driver);
-        if (ret)
-                return ret;
-
-        pr_info("cpufreq: Loongson-2F CPU frequency driver.\n");
-
-        cpufreq_register_notifier(&loongson2_cpufreq_notifier_block,
-                                  CPUFREQ_TRANSITION_NOTIFIER);
-
-        ret = cpufreq_register_driver(&loongson2_cpufreq_driver);
-
-        if (!ret && !nowait) {
-                saved_cpu_wait = cpu_wait;
-                cpu_wait = loongson2_cpu_wait;
-        }
-
-        return ret;
-}
-
-static void __exit cpufreq_exit(void)
-{
-        if (!nowait && saved_cpu_wait)
-                cpu_wait = saved_cpu_wait;
-        cpufreq_unregister_driver(&loongson2_cpufreq_driver);
-        cpufreq_unregister_notifier(&loongson2_cpufreq_notifier_block,
-                                    CPUFREQ_TRANSITION_NOTIFIER);
-
-        platform_driver_unregister(&platform_driver);
-}
-
-module_init(cpufreq_init);
-module_exit(cpufreq_exit);
-
-module_param(nowait, uint, 0644);
-MODULE_PARM_DESC(nowait, "Disable Loongson-2F specific wait");
-
-MODULE_AUTHOR("Yanhua <yanh@lemote.com>");
-MODULE_DESCRIPTION("cpufreq driver for Loongson2F");
-MODULE_LICENSE("GPL");
diff --git a/arch/mips/kernel/early_printk.c b/arch/mips/kernel/early_printk.c
index 9e6440eaa455..505cb77d1280 100644
--- a/arch/mips/kernel/early_printk.c
+++ b/arch/mips/kernel/early_printk.c
@@ -7,7 +7,9 @@
  * Copyright (C) 2007 MIPS Technologies, Inc.
  *   written by Ralf Baechle (ralf@linux-mips.org)
  */
+#include <linux/kernel.h>
 #include <linux/console.h>
+#include <linux/printk.h>
 #include <linux/init.h>
 
 #include <asm/setup.h>
@@ -24,20 +26,18 @@ static void early_console_write(struct console *con, const char *s, unsigned n)
         }
 }
 
-static struct console early_console = {
+static struct console early_console_prom = {
         .name   = "early",
         .write  = early_console_write,
         .flags  = CON_PRINTBUFFER | CON_BOOT,
         .index  = -1
 };
 
-static int early_console_initialized __initdata;
-
 void __init setup_early_printk(void)
 {
-        if (early_console_initialized)
+        if (early_console)
                 return;
-        early_console_initialized = 1;
+        early_console = &early_console_prom;
 
-        register_console(&early_console);
+        register_console(&early_console_prom);
 }
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index db9655f08892..d1d576b765f5 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -119,99 +119,6 @@ SYSCALL_DEFINE6(32_pwrite, unsigned int, fd, const char __user *, buf,
         return sys_pwrite64(fd, buf, count, merge_64(a4, a5));
 }
 
-#ifdef CONFIG_SYSVIPC
-
-SYSCALL_DEFINE6(32_ipc, u32, call, long, first, long, second, long, third,
-        unsigned long, ptr, unsigned long, fifth)
-{
-        int version, err;
-
-        version = call >> 16; /* hack for backward compatibility */
-        call &= 0xffff;
-
-        switch (call) {
-        case SEMOP:
-                /* struct sembuf is the same on 32 and 64bit :)) */
-                err = sys_semtimedop(first, compat_ptr(ptr), second, NULL);
-                break;
-        case SEMTIMEDOP:
-                err = compat_sys_semtimedop(first, compat_ptr(ptr), second,
-                                            compat_ptr(fifth));
-                break;
-        case SEMGET:
-                err = sys_semget(first, second, third);
-                break;
-        case SEMCTL:
-                err = compat_sys_semctl(first, second, third, compat_ptr(ptr));
-                break;
-        case MSGSND:
-                err = compat_sys_msgsnd(first, second, third, compat_ptr(ptr));
-                break;
-        case MSGRCV:
-                err = compat_sys_msgrcv(first, second, fifth, third,
-                                        version, compat_ptr(ptr));
-                break;
-        case MSGGET:
-                err = sys_msgget((key_t) first, second);
-                break;
-        case MSGCTL:
-                err = compat_sys_msgctl(first, second, compat_ptr(ptr));
-                break;
-        case SHMAT:
-                err = compat_sys_shmat(first, second, third, version,
-                                       compat_ptr(ptr));
-                break;
-        case SHMDT:
-                err = sys_shmdt(compat_ptr(ptr));
-                break;
-        case SHMGET:
-                err = sys_shmget(first, (unsigned)second, third);
-                break;
-        case SHMCTL:
-                err = compat_sys_shmctl(first, second, compat_ptr(ptr));
-                break;
-        default:
-                err = -ENOSYS;
-                break;
-        }
-
-        return err;
-}
-
-#else
-
-SYSCALL_DEFINE6(32_ipc, u32, call, int, first, int, second, int, third,
-        u32, ptr, u32, fifth)
-{
-        return -ENOSYS;
-}
-
-#endif /* CONFIG_SYSVIPC */
-
-#ifdef CONFIG_MIPS32_N32
-SYSCALL_DEFINE4(n32_semctl, int, semid, int, semnum, int, cmd, u32, arg)
-{
-        /* compat_sys_semctl expects a pointer to union semun */
-        u32 __user *uptr = compat_alloc_user_space(sizeof(u32));
-        if (put_user(arg, uptr))
-                return -EFAULT;
-        return compat_sys_semctl(semid, semnum, cmd, uptr);
-}
-
-SYSCALL_DEFINE4(n32_msgsnd, int, msqid, u32, msgp, unsigned int, msgsz,
-        int, msgflg)
-{
-        return compat_sys_msgsnd(msqid, msgsz, msgflg, compat_ptr(msgp));
-}
-
-SYSCALL_DEFINE5(n32_msgrcv, int, msqid, u32, msgp, size_t, msgsz,
-        int, msgtyp, int, msgflg)
-{
-        return compat_sys_msgrcv(msqid, msgsz, msgtyp, msgflg, IPC_64,
-                                 compat_ptr(msgp));
-}
-#endif
-
 SYSCALL_DEFINE1(32_personality, unsigned long, personality)
 {
         unsigned int p = personality & 0xffffffff;
@@ -226,26 +133,6 @@ SYSCALL_DEFINE1(32_personality, unsigned long, personality)
         return ret;
 }
 
-SYSCALL_DEFINE4(32_sendfile, long, out_fd, long, in_fd,
-        compat_off_t __user *, offset, s32, count)
-{
-        mm_segment_t old_fs = get_fs();
-        int ret;
-        off_t of;
-
-        if (offset && get_user(of, offset))
-                return -EFAULT;
-
-        set_fs(KERNEL_DS);
-        ret = sys_sendfile(out_fd, in_fd, offset ? (off_t __user *)&of : NULL, count);
-        set_fs(old_fs);
-
-        if (offset && put_user(of, offset))
-                return -EFAULT;
-
-        return ret;
-}
-
 asmlinkage ssize_t sys32_readahead(int fd, u32 pad0, u64 a2, u64 a3,
                                    size_t count)
 {
@@ -279,12 +166,6 @@ asmlinkage long sys32_fallocate(int fd, int mode, unsigned offset_a2,
                              merge_64(len_a4, len_a5));
 }
 
-asmlinkage long sys32_lookup_dcookie(u32 a0, u32 a1, char __user *buf,
-        size_t len)
-{
-        return sys_lookup_dcookie(merge_64(a0, a1), buf, len);
-}
-
 SYSCALL_DEFINE6(32_fanotify_mark, int, fanotify_fd, unsigned int, flags,
                 u64, a3, u64, a4, int, dfd, const char  __user *, pathname)
 {
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 3be4405c2d14..cfc742d75b7f 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -41,44 +41,26 @@
 #include <asm/inst.h>
 #include <asm/stacktrace.h>
 
-/*
- * The idle thread. There's no useful work to be done, so just try to conserve
- * power and have a low exit latency (ie sit in a loop waiting for somebody to
- * say that they'd like to reschedule)
- */
-void __noreturn cpu_idle(void)
+#ifdef CONFIG_HOTPLUG_CPU
+void arch_cpu_idle_dead(void)
 {
-        int cpu;
-
-        /* CPU is going idle. */
-        cpu = smp_processor_id();
+        /* What the heck is this check doing ? */
+        if (!cpu_isset(smp_processor_id(), cpu_callin_map))
+                play_dead();
+}
+#endif
 
-        /* endless idle loop with no priority at all */
-        while (1) {
-                tick_nohz_idle_enter();
-                rcu_idle_enter();
-                while (!need_resched() && cpu_online(cpu)) {
+void arch_cpu_idle(void)
+{
 #ifdef CONFIG_MIPS_MT_SMTC
-                        extern void smtc_idle_loop_hook(void);
+        extern void smtc_idle_loop_hook(void);
 
-                        smtc_idle_loop_hook();
+        smtc_idle_loop_hook();
 #endif
-
-                        if (cpu_wait) {
-                                /* Don't trace irqs off for idle */
-                                stop_critical_timings();
-                                (*cpu_wait)();
-                                start_critical_timings();
-                        }
-                }
-#ifdef CONFIG_HOTPLUG_CPU
-                if (!cpu_online(cpu) && !cpu_isset(cpu, cpu_callin_map))
-                        play_dead();
-#endif
-                rcu_idle_exit();
-                tick_nohz_idle_exit();
-                schedule_preempt_disabled();
-        }
+        if (cpu_wait)
+                (*cpu_wait)();
+        else
+                local_irq_enable();
 }
 
 asmlinkage void ret_from_fork(void);
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 693d60b0855f..edcb6594e7b5 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -143,7 +143,7 @@ EXPORT(sysn32_call_table)
         PTR     compat_sys_setitimer
         PTR     sys_alarm
         PTR     sys_getpid
-        PTR     sys_32_sendfile
+        PTR     compat_sys_sendfile
         PTR     sys_socket                      /* 6040 */
         PTR     sys_connect
         PTR     sys_accept
@@ -168,11 +168,11 @@ EXPORT(sysn32_call_table)
         PTR     sys_newuname
         PTR     sys_semget
         PTR     sys_semop
-        PTR     sys_n32_semctl
+        PTR     compat_sys_semctl
         PTR     sys_shmdt                       /* 6065 */
         PTR     sys_msgget
-        PTR     sys_n32_msgsnd
-        PTR     sys_n32_msgrcv
+        PTR     compat_sys_msgsnd
+        PTR     compat_sys_msgrcv
         PTR     compat_sys_msgctl
         PTR     compat_sys_fcntl                /* 6070 */
         PTR     sys_flock
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index af8887f779f1..103bfe570fe8 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -309,7 +309,7 @@ sys_call_table:
         PTR     compat_sys_wait4
         PTR     sys_swapoff                     /* 4115 */
         PTR     compat_sys_sysinfo
-        PTR     sys_32_ipc
+        PTR     compat_sys_ipc
         PTR     sys_fsync
         PTR     sys32_sigreturn
         PTR     __sys_clone                     /* 4120 */
@@ -399,7 +399,7 @@ sys_call_table:
         PTR     sys_capget
         PTR     sys_capset                      /* 4205 */
         PTR     compat_sys_sigaltstack
-        PTR     sys_32_sendfile
+        PTR     compat_sys_sendfile
         PTR     sys_ni_syscall
         PTR     sys_ni_syscall
         PTR     sys_mips_mmap2                  /* 4210 */
@@ -439,7 +439,7 @@ sys_call_table:
         PTR     compat_sys_io_submit
         PTR     sys_io_cancel                   /* 4245 */
         PTR     sys_exit_group
-        PTR     sys32_lookup_dcookie
+        PTR     compat_sys_lookup_dcookie
         PTR     sys_epoll_create
         PTR     sys_epoll_ctl
         PTR     sys_epoll_wait                  /* 4250 */
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 66bf4e22d9b9..aee04af213c5 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -139,7 +139,7 @@ asmlinkage __cpuinit void start_secondary(void)
         WARN_ON_ONCE(!irqs_disabled());
         mp_ops->smp_finish();
 
-        cpu_idle();
+        cpu_startup_entry(CPUHP_ONLINE);
 }
 
 /*
diff --git a/arch/mips/kernel/smtc-proc.c b/arch/mips/kernel/smtc-proc.c
index aee7c8177b5d..c10aa84c9fa9 100644
--- a/arch/mips/kernel/smtc-proc.c
+++ b/arch/mips/kernel/smtc-proc.c
@@ -16,6 +16,7 @@
 #include <asm/mipsregs.h>
 #include <asm/cacheflush.h>
 #include <linux/proc_fs.h>
+#include <linux/seq_file.h>
 
 #include <asm/smtc_proc.h>
 
@@ -30,51 +31,39 @@ unsigned long selfipis[NR_CPUS];
 
 struct smtc_cpu_proc smtc_cpu_stats[NR_CPUS];
 
-static struct proc_dir_entry *smtc_stats;
-
 atomic_t smtc_fpu_recoveries;
 
-static int proc_read_smtc(char *page, char **start, off_t off,
-                          int count, int *eof, void *data)
+static int smtc_proc_show(struct seq_file *m, void *v)
 {
-        int totalen = 0;
-        int len;
         int i;
         extern unsigned long ebase;
 
-        len = sprintf(page, "SMTC Status Word: 0x%08x\n", smtc_status);
-        totalen += len;
-        page += len;
-        len = sprintf(page, "Config7: 0x%08x\n", read_c0_config7());
-        totalen += len;
-        page += len;
-        len = sprintf(page, "EBASE: 0x%08lx\n", ebase);
-        totalen += len;
-        page += len;
-        len = sprintf(page, "Counter Interrupts taken per CPU (TC)\n");
-        totalen += len;
-        page += len;
-        for (i=0; i < NR_CPUS; i++) {
-                len = sprintf(page, "%d: %ld\n", i, smtc_cpu_stats[i].timerints);
-                totalen += len;
-                page += len;
-        }
-        len = sprintf(page, "Self-IPIs by CPU:\n");
-        totalen += len;
-        page += len;
-        for(i = 0; i < NR_CPUS; i++) {
-                len = sprintf(page, "%d: %ld\n", i, smtc_cpu_stats[i].selfipis);
-                totalen += len;
-                page += len;
-        }
-        len = sprintf(page, "%d Recoveries of \"stolen\" FPU\n",
-                      atomic_read(&smtc_fpu_recoveries));
-        totalen += len;
-        page += len;
+        seq_printf(m, "SMTC Status Word: 0x%08x\n", smtc_status);
+        seq_printf(m, "Config7: 0x%08x\n", read_c0_config7());
+        seq_printf(m, "EBASE: 0x%08lx\n", ebase);
+        seq_printf(m, "Counter Interrupts taken per CPU (TC)\n");
+        for (i=0; i < NR_CPUS; i++)
+                seq_printf(m, "%d: %ld\n", i, smtc_cpu_stats[i].timerints);
+        seq_printf(m, "Self-IPIs by CPU:\n");
+        for(i = 0; i < NR_CPUS; i++)
+                seq_printf(m, "%d: %ld\n", i, smtc_cpu_stats[i].selfipis);
+        seq_printf(m, "%d Recoveries of \"stolen\" FPU\n",
+                   atomic_read(&smtc_fpu_recoveries));
+        return 0;
+}
 
-        return totalen;
+static int smtc_proc_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, smtc_proc_show, NULL);
 }
 
+static const struct file_operations smtc_proc_fops = {
+        .open           = smtc_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
 void init_smtc_stats(void)
 {
         int i;
@@ -86,6 +75,5 @@ void init_smtc_stats(void)
 
         atomic_set(&smtc_fpu_recoveries, 0);
 
-        smtc_stats = create_proc_read_entry("smtc", 0444, NULL,
-                                            proc_read_smtc, NULL);
+        proc_create("smtc", 0444, NULL, &smtc_proc_fops);
 }
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index c3abb88170fc..25225515451f 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -206,19 +206,6 @@ void show_stack(struct task_struct *task, unsigned long *sp)
         show_stacktrace(task, &regs);
 }
 
-/*
- * The architecture-independent dump_stack generator
- */
-void dump_stack(void)
-{
-        struct pt_regs regs;
-
-        prepare_frametrace(&regs);
-        show_backtrace(current, &regs);
-}
-
-EXPORT_SYMBOL(dump_stack);
-
 static void show_code(unsigned int __user *pc)
 {
         long i;
@@ -244,7 +231,7 @@ static void __show_regs(const struct pt_regs *regs)
         unsigned int cause = regs->cp0_cause;
         int i;
 
-        printk("Cpu %d\n", smp_processor_id());
+        show_regs_print_info(KERN_DEFAULT);
 
         /*
          * Saved main processor registers
diff --git a/arch/mips/lasat/picvue_proc.c b/arch/mips/lasat/picvue_proc.c
index c592bc8b8c99..638c5db122c9 100644
--- a/arch/mips/lasat/picvue_proc.c
+++ b/arch/mips/lasat/picvue_proc.c
@@ -58,13 +58,13 @@ static int pvc_line_proc_show(struct seq_file *m, void *v)
 
 static int pvc_line_proc_open(struct inode *inode, struct file *file)
 {
-        return single_open(file, pvc_line_proc_show, PDE(inode)->data);
+        return single_open(file, pvc_line_proc_show, PDE_DATA(inode));
 }
 
 static ssize_t pvc_line_proc_write(struct file *file, const char __user *buf,
                                    size_t count, loff_t *pos)
 {
-        int lineno = *(int *)PDE(file_inode(file))->data;
+        int lineno = *(int *)PDE_DATA(file_inode(file));
         char kbuf[PVC_LINELEN];
         size_t len;
 
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 67929251286c..9b973e0af9cb 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -29,6 +29,7 @@
 #include <linux/pfn.h>
 #include <linux/hardirq.h>
 #include <linux/gfp.h>
+#include <linux/kcore.h>
 
 #include <asm/asm-offsets.h>
 #include <asm/bootinfo.h>
@@ -77,10 +78,9 @@ EXPORT_SYMBOL_GPL(empty_zero_page);
 /*
  * Not static inline because used by IP27 special magic initialization code
  */
-unsigned long setup_zero_pages(void)
+void setup_zero_pages(void)
 {
-        unsigned int order;
-        unsigned long size;
+        unsigned int order, i;
         struct page *page;
 
         if (cpu_has_vce)
@@ -94,15 +94,10 @@ unsigned long setup_zero_pages(void)
 
         page = virt_to_page((void *)empty_zero_page);
         split_page(page, order);
-        while (page < virt_to_page((void *)(empty_zero_page + (PAGE_SIZE << order)))) {
-                SetPageReserved(page);
-                page++;
-        }
-
-        size = PAGE_SIZE << order;
-        zero_page_mask = (size - 1) & PAGE_MASK;
+        for (i = 0; i < (1 << order); i++, page++)
+                mark_page_reserved(page);
 
-        return 1UL << order;
+        zero_page_mask = ((PAGE_SIZE << order) - 1) & PAGE_MASK;
 }
 
 #ifdef CONFIG_MIPS_MT_SMTC
@@ -380,7 +375,7 @@ void __init mem_init(void)
         high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
 
         totalram_pages += free_all_bootmem();
-        totalram_pages -= setup_zero_pages();   /* Setup zeroed pages.  */
+        setup_zero_pages();     /* Setup zeroed pages.  */
 
         reservedpages = ram = 0;
         for (tmp = 0; tmp < max_low_pfn; tmp++)
@@ -399,12 +394,8 @@ void __init mem_init(void)
                         SetPageReserved(page);
                         continue;
                 }
-                ClearPageReserved(page);
-                init_page_count(page);
-                __free_page(page);
-                totalhigh_pages++;
+                free_highmem_page(page);
         }
-        totalram_pages += totalhigh_pages;
         num_physpages += totalhigh_pages;
 #endif
 
@@ -440,11 +431,8 @@ void free_init_pages(const char *what, unsigned long begin, unsigned long end)
                 struct page *page = pfn_to_page(pfn);
                 void *addr = phys_to_virt(PFN_PHYS(pfn));
 
-                ClearPageReserved(page);
-                init_page_count(page);
                 memset(addr, POISON_FREE_INITMEM, PAGE_SIZE);
-                __free_page(page);
-                totalram_pages++;
+                free_reserved_page(page);
         }
         printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
 }
@@ -452,18 +440,14 @@ void free_init_pages(const char *what, unsigned long begin, unsigned long end)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_init_pages("initrd memory",
-                        virt_to_phys((void *)start),
-                        virt_to_phys((void *)end));
+        free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
 }
 #endif
 
 void __init_refok free_initmem(void)
 {
         prom_free_prom_memory();
-        free_init_pages("unused kernel memory",
-                        __pa_symbol(&__init_begin),
-                        __pa_symbol(&__init_end));
+        free_initmem_default(POISON_FREE_INITMEM);
 }
 
 #ifndef CONFIG_MIPS_PGD_C0_CONTEXT
diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c
index d0b6f8399b07..3d27800edba2 100644
--- a/arch/mips/pci/ops-pmcmsp.c
+++ b/arch/mips/pci/ops-pmcmsp.c
@@ -53,56 +53,51 @@ static void pci_proc_init(void);
 
 /*****************************************************************************
  *
- *  FUNCTION: read_msp_pci_counts
+ *  FUNCTION: show_msp_pci_counts
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Prints the count of how many times each PCI
  *               interrupt has asserted. Can be invoked by the
  *               /proc filesystem.
  *
- *  INPUTS:      page    - part of STDOUT calculation
- *               off     - part of STDOUT calculation
- *               count   - part of STDOUT calculation
- *               data    - unused
+ *  INPUTS:      m       - synthetic file construction data
+ *               v       - iterator
  *
- *  OUTPUTS:     start   - new start location
- *               eof     - end of file pointer
- *
- *  RETURNS:     len     - STDOUT length
+ *  RETURNS:     0 or error
  *
  ****************************************************************************/
-static int read_msp_pci_counts(char *page, char **start, off_t off,
-                                int count, int *eof, void *data)
+static int show_msp_pci_counts(struct seq_file *m, void *v)
 {
         int i;
-        int len = 0;
         unsigned int intcount, total = 0;
 
         for (i = 0; i < 32; ++i) {
                 intcount = pci_int_count[i];
                 if (intcount != 0) {
-                        len += sprintf(page + len, "[%d] = %u\n", i, intcount);
+                        seq_printf(m, "[%d] = %u\n", i, intcount);
                         total += intcount;
                 }
         }
 
-        len += sprintf(page + len, "total = %u\n", total);
-        if (len <= off+count)
-                *eof = 1;
-
-        *start = page + off;
-        len -= off;
-        if (len > count)
-                len = count;
-        if (len < 0)
-                len = 0;
+        seq_printf(m, "total = %u\n", total);
+        return 0;
+}
 
-        return len;
+static int msp_pci_rd_cnt_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, show_msp_pci_counts, NULL);
 }
 
+static const struct file_operations msp_pci_rd_cnt_fops = {
+        .open           = msp_pci_rd_cnt_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
 /*****************************************************************************
  *
- *  FUNCTION: gen_pci_cfg_wr
+ *  FUNCTION: gen_pci_cfg_wr_show
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Generates a configuration write cycle for debug purposes.
@@ -112,37 +107,30 @@ static int read_msp_pci_counts(char *page, char **start, off_t off,
  *               PCI bus.  Intent is that this function by invocable from
  *               the /proc filesystem.
  *
- *  INPUTS:      page    - part of STDOUT calculation
- *               off     - part of STDOUT calculation
- *               count   - part of STDOUT calculation
- *               data    - unused
+ *  INPUTS:      m       - synthetic file construction data
+ *               v       - iterator
  *
- *  OUTPUTS:     start   - new start location
- *               eof     - end of file pointer
- *
- *  RETURNS:     len     - STDOUT length
+ *  RETURNS:     0 or error
  *
  ****************************************************************************/
-static int gen_pci_cfg_wr(char *page, char **start, off_t off,
-                                int count, int *eof, void *data)
+static int gen_pci_cfg_wr_show(struct seq_file *m, void *v)
 {
         unsigned char where = 0; /* Write to static Device/Vendor ID */
         unsigned char bus_num = 0; /* Bus 0 */
         unsigned char dev_fn = 0xF; /* Arbitrary device number */
         u32 wr_data = 0xFF00AA00; /* Arbitrary data */
         struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
-        int len = 0;
         unsigned long value;
         int intr;
 
-        len += sprintf(page + len, "PMC MSP PCI: Beginning\n");
+        seq_puts(m, "PMC MSP PCI: Beginning\n");
 
         if (proc_init == 0) {
                 pci_proc_init();
                 proc_init = ~0;
         }
 
-        len += sprintf(page + len, "PMC MSP PCI: Before Cfg Wr\n");
+        seq_puts(m, "PMC MSP PCI: Before Cfg Wr\n");
 
         /*
          * Generate PCI Configuration Write Cycle
@@ -168,21 +156,22 @@ static int gen_pci_cfg_wr(char *page, char **start, off_t off,
          */
         intr = preg->if_status;
 
-        len += sprintf(page + len, "PMC MSP PCI: After Cfg Wr\n");
-
-        /* Handle STDOUT calculations */
-        if (len <= off+count)
-                *eof = 1;
-        *start = page + off;
-        len -= off;
-        if (len > count)
-                len = count;
-        if (len < 0)
-                len = 0;
+        seq_puts(m, "PMC MSP PCI: After Cfg Wr\n");
+        return 0;
+}
 
-        return len;
+static int gen_pci_cfg_wr_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, gen_pci_cfg_wr_show, NULL);
 }
 
+static const struct file_operations gen_pci_cfg_wr_fops = {
+        .open           = gen_pci_cfg_wr_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
 /*****************************************************************************
  *
  *  FUNCTION: pci_proc_init
@@ -199,10 +188,8 @@ static int gen_pci_cfg_wr(char *page, char **start, off_t off,
  ****************************************************************************/
 static void pci_proc_init(void)
 {
-        create_proc_read_entry("pmc_msp_pci_rd_cnt", 0, NULL,
-                                read_msp_pci_counts, NULL);
-        create_proc_read_entry("pmc_msp_pci_cfg_wr", 0, NULL,
-                                gen_pci_cfg_wr, NULL);
+        proc_create("pmc_msp_pci_rd_cnt", 0, NULL, &msp_pci_rd_cnt_fops);
+        proc_create("pmc_msp_pci_cfg_wr", 0, NULL, &gen_pci_cfg_wr_fops);
 }
 #endif /* CONFIG_PROC_FS && PCI_COUNTERS */
 
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 0872f12f268d..594e60d6a43b 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -115,7 +115,6 @@ static void pcibios_scanbus(struct pci_controller *hose)
                         pci_bus_assign_resources(bus);
                         pci_enable_bridges(bus);
                 }
-                bus->dev.of_node = hose->of_node;
         }
 }
 
@@ -169,6 +168,13 @@ void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
                 }
         }
 }
+
+struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
+{
+        struct pci_controller *hose = bus->sysdata;
+
+        return of_node_get(hose->of_node);
+}
 #endif
 
 static DEFINE_MUTEX(pci_scan_mutex);
diff --git a/arch/mips/sgi-ip27/ip27-memory.c b/arch/mips/sgi-ip27/ip27-memory.c
index 3505d08ff2fd..5f2bddb1860e 100644
--- a/arch/mips/sgi-ip27/ip27-memory.c
+++ b/arch/mips/sgi-ip27/ip27-memory.c
@@ -457,7 +457,7 @@ void __init prom_free_prom_memory(void)
         /* We got nothing to free here ...  */
 }
 
-extern unsigned long setup_zero_pages(void);
+extern void setup_zero_pages(void);
 
 void __init paging_init(void)
 {
@@ -492,7 +492,7 @@ void __init mem_init(void)
                 totalram_pages += free_all_bootmem_node(NODE_DATA(node));
         }
 
-        totalram_pages -= setup_zero_pages();   /* This comes from node 0 */
+        setup_zero_pages();     /* This comes from node 0 */
 
         codesize =  (unsigned long) &_etext - (unsigned long) &_text;
         datasize =  (unsigned long) &_edata - (unsigned long) &_etext;
diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c
index e651105b3f0b..8871e3345bff 100644
--- a/arch/mips/sibyte/sb1250/bus_watcher.c
+++ b/arch/mips/sibyte/sb1250/bus_watcher.c
@@ -30,6 +30,7 @@
 #include <linux/interrupt.h>
 #include <linux/sched.h>
 #include <linux/proc_fs.h>
+#include <linux/seq_file.h>
 #include <asm/io.h>
 
 #include <asm/sibyte/sb1250.h>
@@ -99,63 +100,60 @@ void check_bus_watcher(void)
                 printk("Bus watcher indicates no error\n");
 }
 
-static int bw_print_buffer(char *page, struct bw_stats_struct *stats)
+#ifdef CONFIG_PROC_FS
+
+/* For simplicity, I want to assume a single read is required each
+   time */
+static int bw_proc_show(struct seq_file *m, void *v)
 {
-        int len;
-
-        len = sprintf(page, "SiByte Bus Watcher statistics\n");
-        len += sprintf(page+len, "-----------------------------\n");
-        len += sprintf(page+len, "L2-d-cor %8ld\nL2-d-bad %8ld\n",
-                       stats->l2_cor_d, stats->l2_bad_d);
-        len += sprintf(page+len, "L2-t-cor %8ld\nL2-t-bad %8ld\n",
-                       stats->l2_cor_t, stats->l2_bad_t);
-        len += sprintf(page+len, "MC-d-cor %8ld\nMC-d-bad %8ld\n",
-                       stats->mem_cor_d, stats->mem_bad_d);
-        len += sprintf(page+len, "IO-err   %8ld\n", stats->bus_error);
-        len += sprintf(page+len, "\nLast recorded signature:\n");
-        len += sprintf(page+len, "Request %02x from %d, answered by %d with Dcode %d\n",
-                       (unsigned int)(G_SCD_BERR_TID(stats->status) & 0x3f),
-                       (int)(G_SCD_BERR_TID(stats->status) >> 6),
-                       (int)G_SCD_BERR_RID(stats->status),
-                       (int)G_SCD_BERR_DCODE(stats->status));
+        struct bw_stats_struct *stats = m->private;
+
+        seq_puts(m, "SiByte Bus Watcher statistics\n");
+        seq_puts(m, "-----------------------------\n");
+        seq_printf(m, "L2-d-cor %8ld\nL2-d-bad %8ld\n",
+                   stats->l2_cor_d, stats->l2_bad_d);
+        seq_printf(m, "L2-t-cor %8ld\nL2-t-bad %8ld\n",
+                   stats->l2_cor_t, stats->l2_bad_t);
+        seq_printf(m, "MC-d-cor %8ld\nMC-d-bad %8ld\n",
+                   stats->mem_cor_d, stats->mem_bad_d);
+        seq_printf(m, "IO-err   %8ld\n", stats->bus_error);
+        seq_puts(m, "\nLast recorded signature:\n");
+        seq_printf(m, "Request %02x from %d, answered by %d with Dcode %d\n",
+                   (unsigned int)(G_SCD_BERR_TID(stats->status) & 0x3f),
+                   (int)(G_SCD_BERR_TID(stats->status) >> 6),
+                   (int)G_SCD_BERR_RID(stats->status),
+                   (int)G_SCD_BERR_DCODE(stats->status));
         /* XXXKW indicate multiple errors between printings, or stats
            collection (or both)? */
         if (stats->status & M_SCD_BERR_MULTERRS)
-                len += sprintf(page+len, "Multiple errors observed since last check.\n");
+                seq_puts(m, "Multiple errors observed since last check.\n");
         if (stats->status_printed) {
-                len += sprintf(page+len, "(no change since last printing)\n");
+                seq_puts(m, "(no change since last printing)\n");
         } else {
                 stats->status_printed = 1;
         }
 
-        return len;
+        return 0;
 }
 
-#ifdef CONFIG_PROC_FS
-
-/* For simplicity, I want to assume a single read is required each
-   time */
-static int bw_read_proc(char *page, char **start, off_t off,
-                        int count, int *eof, void *data)
+static int bw_proc_open(struct inode *inode, struct file *file)
 {
-        int len;
-
-        if (off == 0) {
-                len = bw_print_buffer(page, data);
-                *start = page;
-        } else {
-                len = 0;
-                *eof = 1;
-        }
-        return len;
+        return single_open(file, bw_proc_show, PDE_DATA(inode));
 }
 
+static const struct file_operations bw_proc_fops = {
+        .open           = bw_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
 static void create_proc_decoder(struct bw_stats_struct *stats)
 {
         struct proc_dir_entry *ent;
 
-        ent = create_proc_read_entry("bus_watcher", S_IWUSR | S_IRUGO, NULL,
-                                     bw_read_proc, stats);
+        ent = proc_create_data("bus_watcher", S_IWUSR | S_IRUGO, NULL,
+                               &bw_proc_fops, stats);
         if (!ent) {
                 printk(KERN_INFO "Unable to initialize bus_watcher /proc entry\n");
                 return;
@@ -210,11 +208,6 @@ static irqreturn_t sibyte_bw_int(int irq, void *data)
         stats->bus_error += G_SCD_MEM_BUSERR(cntr);
         csr_out32(0, IOADDR(A_BUS_MEM_IO_ERRORS));
 
-#ifndef CONFIG_PROC_FS
-        bw_print_buffer(bw_buf, stats);
-        printk(bw_buf);
-#endif
-
         return IRQ_HANDLED;
 }
 
diff --git a/arch/mn10300/include/asm/thread_info.h b/arch/mn10300/include/asm/thread_info.h
index f90062b0622d..224b4262486d 100644
--- a/arch/mn10300/include/asm/thread_info.h
+++ b/arch/mn10300/include/asm/thread_info.h
@@ -165,8 +165,6 @@ void arch_release_thread_info(struct thread_info *ti);
 #define _TIF_WORK_MASK          0x0000FFFE      /* work to do on interrupt/exception return */
 #define _TIF_ALLWORK_MASK       0x0000FFFF      /* work to do on any return to u-space */
 
-#define tsk_is_polling(t) test_tsk_thread_flag(t, TIF_POLLING_NRFLAG)
-
 #endif /* __KERNEL__ */
 
 #endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/mn10300/include/asm/unistd.h b/arch/mn10300/include/asm/unistd.h
index 7f9d9adfa51e..9d4e2d1ef90e 100644
--- a/arch/mn10300/include/asm/unistd.h
+++ b/arch/mn10300/include/asm/unistd.h
@@ -45,14 +45,4 @@
 #define __ARCH_WANT_SYS_VFORK
 #define __ARCH_WANT_SYS_CLONE
 
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#ifndef cond_syscall
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall");
-#endif
-
 #endif /* _ASM_UNISTD_H */
diff --git a/arch/mn10300/kernel/process.c b/arch/mn10300/kernel/process.c
index 84f4e97e3074..3707da583d05 100644
--- a/arch/mn10300/kernel/process.c
+++ b/arch/mn10300/kernel/process.c
@@ -50,77 +50,19 @@ unsigned long thread_saved_pc(struct task_struct *tsk)
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
 
-#if !defined(CONFIG_SMP) || defined(CONFIG_HOTPLUG_CPU)
-/*
- * we use this if we don't have any better idle routine
- */
-static void default_idle(void)
-{
-        local_irq_disable();
-        if (!need_resched())
-                safe_halt();
-        else
-                local_irq_enable();
-}
-
-#else /* !CONFIG_SMP || CONFIG_HOTPLUG_CPU  */
 /*
  * On SMP it's slightly faster (but much more power-consuming!)
  * to poll the ->work.need_resched flag instead of waiting for the
  * cross-CPU IPI to arrive. Use this option with caution.
+ *
+ * tglx: No idea why this depends on HOTPLUG_CPU !?!
  */
-static inline void poll_idle(void)
-{
-        int oldval;
-
-        local_irq_enable();
-
-        /*
-         * Deal with another CPU just having chosen a thread to
-         * run here:
-         */
-        oldval = test_and_clear_thread_flag(TIF_NEED_RESCHED);
-
-        if (!oldval) {
-                set_thread_flag(TIF_POLLING_NRFLAG);
-                while (!need_resched())
-                        cpu_relax();
-                clear_thread_flag(TIF_POLLING_NRFLAG);
-        } else {
-                set_need_resched();
-        }
-}
-#endif /* !CONFIG_SMP || CONFIG_HOTPLUG_CPU */
-
-/*
- * the idle thread
- * - there's no useful work to be done, so just try to conserve power and have
- *   a low exit latency (ie sit in a loop waiting for somebody to say that
- *   they'd like to reschedule)
- */
-void cpu_idle(void)
+#if !defined(CONFIG_SMP) || defined(CONFIG_HOTPLUG_CPU)
+void arch_cpu_idle(void)
 {
-        /* endless idle loop with no priority at all */
-        for (;;) {
-                rcu_idle_enter();
-                while (!need_resched()) {
-                        void (*idle)(void);
-
-                        smp_rmb();
-                        if (!idle) {
-#if defined(CONFIG_SMP) && !defined(CONFIG_HOTPLUG_CPU)
-                                idle = poll_idle;
-#else  /* CONFIG_SMP && !CONFIG_HOTPLUG_CPU */
-                                idle = default_idle;
-#endif /* CONFIG_SMP && !CONFIG_HOTPLUG_CPU */
-                        }
-                        idle();
-                }
-                rcu_idle_exit();
-
-                schedule_preempt_disabled();
-        }
+        safe_halt();
 }
+#endif
 
 void release_segments(struct mm_struct *mm)
 {
@@ -155,6 +97,7 @@ void machine_power_off(void)
 
 void show_regs(struct pt_regs *regs)
 {
+        show_regs_print_info(KERN_DEFAULT);
 }
 
 /*
diff --git a/arch/mn10300/kernel/smp.c b/arch/mn10300/kernel/smp.c
index 5d7e152a23b7..a17f9c9c14c9 100644
--- a/arch/mn10300/kernel/smp.c
+++ b/arch/mn10300/kernel/smp.c
@@ -675,7 +675,7 @@ int __init start_secondary(void *unused)
 #ifdef CONFIG_GENERIC_CLOCKEVENTS
         init_clockevents();
 #endif
-        cpu_idle();
+        cpu_startup_entry(CPUHP_ONLINE);
         return 0;
 }
 
@@ -935,8 +935,6 @@ int __cpu_up(unsigned int cpu, struct task_struct *tidle)
         int timeout;
 
 #ifdef CONFIG_HOTPLUG_CPU
-        if (num_online_cpus() == 1)
-                disable_hlt();
         if (sleep_mode[cpu])
                 run_wakeup_cpu(cpu);
 #endif /* CONFIG_HOTPLUG_CPU */
@@ -1003,9 +1001,6 @@ int __cpu_disable(void)
 void __cpu_die(unsigned int cpu)
 {
         run_sleep_cpu(cpu);
-
-        if (num_online_cpus() == 1)
-                enable_hlt();
 }
 
 #ifdef CONFIG_MN10300_CACHE_ENABLED
diff --git a/arch/mn10300/kernel/traps.c b/arch/mn10300/kernel/traps.c
index b900e5afa0ae..a7a987c7954f 100644
--- a/arch/mn10300/kernel/traps.c
+++ b/arch/mn10300/kernel/traps.c
@@ -294,17 +294,6 @@ void show_stack(struct task_struct *task, unsigned long *sp)
 }
 
 /*
- * the architecture-independent dump_stack generator
- */
-void dump_stack(void)
-{
-        unsigned long stack;
-
-        show_stack(current, &stack);
-}
-EXPORT_SYMBOL(dump_stack);
-
-/*
  * dump the register file in the specified exception frame
  */
 void show_registers_only(struct pt_regs *regs)
diff --git a/arch/mn10300/mm/init.c b/arch/mn10300/mm/init.c
index e57e5bc23562..5a8ace63a6b4 100644
--- a/arch/mn10300/mm/init.c
+++ b/arch/mn10300/mm/init.c
@@ -139,30 +139,11 @@ void __init mem_init(void)
 }
 
 /*
- *
- */
-void free_init_pages(char *what, unsigned long begin, unsigned long end)
-{
-        unsigned long addr;
-
-        for (addr = begin; addr < end; addr += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(addr));
-                init_page_count(virt_to_page(addr));
-                memset((void *) addr, 0xcc, PAGE_SIZE);
-                free_page(addr);
-                totalram_pages++;
-        }
-        printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
-}
-
-/*
  * recycle memory containing stuff only required for initialisation
  */
 void free_initmem(void)
 {
-        free_init_pages("unused kernel memory",
-                        (unsigned long) &__init_begin,
-                        (unsigned long) &__init_end);
+        free_initmem_default(POISON_FREE_INITMEM);
 }
 
 /*
@@ -171,6 +152,6 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_init_pages("initrd memory", start, end);
+        free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
 }
 #endif
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 9ab3bf2eca8d..81b9ddbc9166 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -55,9 +55,6 @@ config TRACE_IRQFLAGS_SUPPORT
 config GENERIC_CSUM
         def_bool y
 
-config GENERIC_FIND_NEXT_BIT
-        def_bool y
-
 source "init/Kconfig"
 
 
diff --git a/arch/openrisc/include/asm/thread_info.h b/arch/openrisc/include/asm/thread_info.h
index 07f3212422ad..d797acc901e4 100644
--- a/arch/openrisc/include/asm/thread_info.h
+++ b/arch/openrisc/include/asm/thread_info.h
@@ -128,8 +128,6 @@ register struct thread_info *current_thread_info_reg asm("r10");
 /* For OpenRISC, this is anything in the LSW other than syscall trace */
 #define _TIF_WORK_MASK (0xff & ~(_TIF_SYSCALL_TRACE|_TIF_SINGLESTEP))
 
-#define tsk_is_polling(t) test_tsk_thread_flag(t, TIF_POLLING_NRFLAG)
-
 #endif /* __KERNEL__ */
 
 #endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile
index 35f92ce51c24..ec6d9d37cefd 100644
--- a/arch/openrisc/kernel/Makefile
+++ b/arch/openrisc/kernel/Makefile
@@ -4,7 +4,7 @@
 
 extra-y := head.o vmlinux.lds
 
-obj-y   := setup.o idle.o or32_ksyms.o process.o dma.o \
+obj-y   := setup.o or32_ksyms.o process.o dma.o \
            traps.o time.o irq.o entry.o ptrace.o signal.o \
            sys_call_table.o
 
diff --git a/arch/openrisc/kernel/idle.c b/arch/openrisc/kernel/idle.c
deleted file mode 100644
index 5e8a3b6d6bc6..000000000000
--- a/arch/openrisc/kernel/idle.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * OpenRISC idle.c
- *
- * Linux architectural port borrowing liberally from similar works of
- * others.  All original copyrights apply as per the original source
- * declaration.
- *
- * Modifications for the OpenRISC architecture:
- * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
- * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- *
- * Idle daemon for or32.  Idle daemon will handle any action
- * that needs to be taken when the system becomes idle.
- */
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/stddef.h>
-#include <linux/unistd.h>
-#include <linux/ptrace.h>
-#include <linux/slab.h>
-#include <linux/tick.h>
-
-#include <asm/pgtable.h>
-#include <asm/uaccess.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/pgalloc.h>
-
-void (*powersave) (void) = NULL;
-
-void cpu_idle(void)
-{
-        set_thread_flag(TIF_POLLING_NRFLAG);
-
-        /* endless idle loop with no priority at all */
-        while (1) {
-                tick_nohz_idle_enter();
-                rcu_idle_enter();
-
-                while (!need_resched()) {
-                        check_pgt_cache();
-                        rmb();
-
-                        clear_thread_flag(TIF_POLLING_NRFLAG);
-
-                        local_irq_disable();
-                        /* Don't trace irqs off for idle */
-                        stop_critical_timings();
-                        if (!need_resched() && powersave != NULL)
-                                powersave();
-                        start_critical_timings();
-                        local_irq_enable();
-                        set_thread_flag(TIF_POLLING_NRFLAG);
-                }
-
-                rcu_idle_exit();
-                tick_nohz_idle_exit();
-                preempt_enable_no_resched();
-                schedule();
-                preempt_disable();
-        }
-}
diff --git a/arch/openrisc/kernel/process.c b/arch/openrisc/kernel/process.c
index 00c233bf0d06..386af258591d 100644
--- a/arch/openrisc/kernel/process.c
+++ b/arch/openrisc/kernel/process.c
@@ -90,6 +90,7 @@ void show_regs(struct pt_regs *regs)
 {
         extern void show_registers(struct pt_regs *regs);
 
+        show_regs_print_info(KERN_DEFAULT);
         /* __PHX__ cleanup this mess */
         show_registers(regs);
 }
diff --git a/arch/openrisc/kernel/traps.c b/arch/openrisc/kernel/traps.c
index 5cce396016d0..3d3f6062f49c 100644
--- a/arch/openrisc/kernel/traps.c
+++ b/arch/openrisc/kernel/traps.c
@@ -105,17 +105,6 @@ void show_trace_task(struct task_struct *tsk)
          */
 }
 
-/*
- * The architecture-independent backtrace generator
- */
-void dump_stack(void)
-{
-        unsigned long stack;
-
-        show_stack(current, &stack);
-}
-EXPORT_SYMBOL(dump_stack);
-
 void show_registers(struct pt_regs *regs)
 {
         int i;
diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c
index e7fdc50c4bf0..b3cbc6703837 100644
--- a/arch/openrisc/mm/init.c
+++ b/arch/openrisc/mm/init.c
@@ -43,6 +43,7 @@
 #include <asm/kmap_types.h>
 #include <asm/fixmap.h>
 #include <asm/tlbflush.h>
+#include <asm/sections.h>
 
 int mem_init_done;
 
@@ -201,9 +202,6 @@ void __init paging_init(void)
 
 /* References to section boundaries */
 
-extern char _stext, _etext, _edata, __bss_start, _end;
-extern char __init_begin, __init_end;
-
 static int __init free_pages_init(void)
 {
         int reservedpages, pfn;
@@ -263,30 +261,11 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        printk(KERN_INFO "Freeing initrd memory: %ldk freed\n",
-               (end - start) >> 10);
-
-        for (; start < end; start += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(start));
-                init_page_count(virt_to_page(start));
-                free_page(start);
-                totalram_pages++;
-        }
+        free_reserved_area(start, end, 0, "initrd");
 }
 #endif
 
 void free_initmem(void)
 {
-        unsigned long addr;
-
-        addr = (unsigned long)(&__init_begin);
-        for (; addr < (unsigned long)(&__init_end); addr += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(addr));
-                init_page_count(virt_to_page(addr));
-                free_page(addr);
-                totalram_pages++;
-        }
-        printk(KERN_INFO "Freeing unused kernel memory: %luk freed\n",
-               ((unsigned long)&__init_end -
-                (unsigned long)&__init_begin) >> 10);
+        free_initmem_default(0);
 }
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index 0339181bf3ac..433e75a2ee9a 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -1,5 +1,6 @@
 config PARISC
         def_bool y
+        select ARCH_HAS_DEBUG_STRICT_USER_COPY_CHECKS
         select HAVE_IDE
         select HAVE_OPROFILE
         select HAVE_FUNCTION_TRACER if 64BIT
diff --git a/arch/parisc/Kconfig.debug b/arch/parisc/Kconfig.debug
index 7305ac8f7f5b..bc989e522a04 100644
--- a/arch/parisc/Kconfig.debug
+++ b/arch/parisc/Kconfig.debug
@@ -12,18 +12,4 @@ config DEBUG_RODATA
          portion of the kernel code won't be covered by a TLB anymore.
          If in doubt, say "N".
 
-config DEBUG_STRICT_USER_COPY_CHECKS
-        bool "Strict copy size checks"
-        depends on DEBUG_KERNEL && !TRACE_BRANCH_PROFILING
-        ---help---
-          Enabling this option turns a certain set of sanity checks for user
-          copy operations into compile time failures.
-
-          The copy_from_user() etc checks are there to help test if there
-          are sufficient security checks on the length argument of
-          the copy operation, by having gcc prove that the argument is
-          within bounds.
-
-          If unsure, or if you run an older (pre 4.4) gcc, say N.
-
 endmenu
diff --git a/arch/parisc/Makefile b/arch/parisc/Makefile
index 01d95e2f0581..113e28206503 100644
--- a/arch/parisc/Makefile
+++ b/arch/parisc/Makefile
@@ -65,8 +65,10 @@ ifndef CONFIG_FUNCTION_TRACER
 endif
 
 # Use long jumps instead of long branches (needed if your linker fails to
-# link a too big vmlinux executable)
-cflags-$(CONFIG_MLONGCALLS)     += -mlong-calls
+# link a too big vmlinux executable). Not enabled for building modules.
+ifdef CONFIG_MLONGCALLS
+KBUILD_CFLAGS_KERNEL += -mlong-calls
+endif
 
 # select which processor to optimise for
 cflags-$(CONFIG_PA7100)         += -march=1.1 -mschedule=7100
diff --git a/arch/parisc/include/asm/cacheflush.h b/arch/parisc/include/asm/cacheflush.h
index 79f694f3ad9b..f0e2784e7cca 100644
--- a/arch/parisc/include/asm/cacheflush.h
+++ b/arch/parisc/include/asm/cacheflush.h
@@ -140,7 +140,10 @@ static inline void *kmap(struct page *page)
         return page_address(page);
 }
 
-#define kunmap(page)                    kunmap_parisc(page_address(page))
+static inline void kunmap(struct page *page)
+{
+        kunmap_parisc(page_address(page));
+}
 
 static inline void *kmap_atomic(struct page *page)
 {
diff --git a/arch/parisc/include/asm/pgtable.h b/arch/parisc/include/asm/pgtable.h
index 7df49fad29f9..1e40d7f86be3 100644
--- a/arch/parisc/include/asm/pgtable.h
+++ b/arch/parisc/include/asm/pgtable.h
@@ -16,6 +16,8 @@
 #include <asm/processor.h>
 #include <asm/cache.h>
 
+extern spinlock_t pa_dbit_lock;
+
 /*
  * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
  * memory.  For the return value to be meaningful, ADDR must be >=
@@ -44,8 +46,11 @@ extern void purge_tlb_entries(struct mm_struct *, unsigned long);
 
 #define set_pte_at(mm, addr, ptep, pteval)                      \
         do {                                                    \
+                unsigned long flags;                            \
+                spin_lock_irqsave(&pa_dbit_lock, flags);        \
                 set_pte(ptep, pteval);                          \
                 purge_tlb_entries(mm, addr);                    \
+                spin_unlock_irqrestore(&pa_dbit_lock, flags);   \
         } while (0)
 
 #endif /* !__ASSEMBLY__ */
@@ -435,48 +440,46 @@ extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
 
 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
 {
-#ifdef CONFIG_SMP
+        pte_t pte;
+        unsigned long flags;
+
         if (!pte_young(*ptep))
                 return 0;
-        return test_and_clear_bit(xlate_pabit(_PAGE_ACCESSED_BIT), &pte_val(*ptep));
-#else
-        pte_t pte = *ptep;
-        if (!pte_young(pte))
+
+        spin_lock_irqsave(&pa_dbit_lock, flags);
+        pte = *ptep;
+        if (!pte_young(pte)) {
+                spin_unlock_irqrestore(&pa_dbit_lock, flags);
                 return 0;
-        set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
+        }
+        set_pte(ptep, pte_mkold(pte));
+        purge_tlb_entries(vma->vm_mm, addr);
+        spin_unlock_irqrestore(&pa_dbit_lock, flags);
         return 1;
-#endif
 }
 
-extern spinlock_t pa_dbit_lock;
-
 struct mm_struct;
 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
         pte_t old_pte;
+        unsigned long flags;
 
-        spin_lock(&pa_dbit_lock);
+        spin_lock_irqsave(&pa_dbit_lock, flags);
         old_pte = *ptep;
         pte_clear(mm,addr,ptep);
-        spin_unlock(&pa_dbit_lock);
+        purge_tlb_entries(mm, addr);
+        spin_unlock_irqrestore(&pa_dbit_lock, flags);
 
         return old_pte;
 }
 
 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
-#ifdef CONFIG_SMP
-        unsigned long new, old;
-
-        do {
-                old = pte_val(*ptep);
-                new = pte_val(pte_wrprotect(__pte (old)));
-        } while (cmpxchg((unsigned long *) ptep, old, new) != old);
+        unsigned long flags;
+        spin_lock_irqsave(&pa_dbit_lock, flags);
+        set_pte(ptep, pte_wrprotect(*ptep));
         purge_tlb_entries(mm, addr);
-#else
-        pte_t old_pte = *ptep;
-        set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
-#endif
+        spin_unlock_irqrestore(&pa_dbit_lock, flags);
 }
 
 #define pte_same(A,B)   (pte_val(A) == pte_val(B))
diff --git a/arch/parisc/include/asm/thread_info.h b/arch/parisc/include/asm/thread_info.h
index d1fb79a36f3d..6182832e5b6c 100644
--- a/arch/parisc/include/asm/thread_info.h
+++ b/arch/parisc/include/asm/thread_info.h
@@ -77,8 +77,6 @@ struct thread_info {
 #define _TIF_SYSCALL_TRACE_MASK (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | \
                                  _TIF_BLOCKSTEP)
 
-#define tsk_is_polling(t) test_tsk_thread_flag(t, TIF_POLLING_NRFLAG)
-
 #endif /* __KERNEL__ */
 
 #endif /* _ASM_PARISC_THREAD_INFO_H */
diff --git a/arch/parisc/include/asm/uaccess.h b/arch/parisc/include/asm/uaccess.h
index 4ba2c93770f1..e0a82358517e 100644
--- a/arch/parisc/include/asm/uaccess.h
+++ b/arch/parisc/include/asm/uaccess.h
@@ -181,30 +181,24 @@ struct exception_data {
 #if !defined(CONFIG_64BIT)
 
 #define __put_kernel_asm64(__val,ptr) do {                  \
-        u64 __val64 = (u64)(__val);                         \
-        u32 hi = (__val64) >> 32;                           \
-        u32 lo = (__val64) & 0xffffffff;                    \
         __asm__ __volatile__ (                              \
                 "\n1:\tstw %2,0(%1)"                        \
-                "\n2:\tstw %3,4(%1)\n\t"                    \
+                "\n2:\tstw %R2,4(%1)\n\t"                   \
                 ASM_EXCEPTIONTABLE_ENTRY(1b,fixup_put_user_skip_2)\
                 ASM_EXCEPTIONTABLE_ENTRY(2b,fixup_put_user_skip_1)\
                 : "=r"(__pu_err)                            \
-                : "r"(ptr), "r"(hi), "r"(lo), "0"(__pu_err) \
+                : "r"(ptr), "r"(__val), "0"(__pu_err) \
                 : "r1");                                    \
 } while (0)
 
 #define __put_user_asm64(__val,ptr) do {                    \
-        u64 __val64 = (u64)(__val);                         \
-        u32 hi = (__val64) >> 32;                           \
-        u32 lo = (__val64) & 0xffffffff;                    \
         __asm__ __volatile__ (                              \
                 "\n1:\tstw %2,0(%%sr3,%1)"                  \
-                "\n2:\tstw %3,4(%%sr3,%1)\n\t"              \
+                "\n2:\tstw %R2,4(%%sr3,%1)\n\t"             \
                 ASM_EXCEPTIONTABLE_ENTRY(1b,fixup_put_user_skip_2)\
                 ASM_EXCEPTIONTABLE_ENTRY(2b,fixup_put_user_skip_1)\
                 : "=r"(__pu_err)                            \
-                : "r"(ptr), "r"(hi), "r"(lo), "0"(__pu_err) \
+                : "r"(ptr), "r"(__val), "0"(__pu_err) \
                 : "r1");                                    \
 } while (0)
 
diff --git a/arch/parisc/include/asm/unistd.h b/arch/parisc/include/asm/unistd.h
index ae9a46cbfd92..74d835820ee7 100644
--- a/arch/parisc/include/asm/unistd.h
+++ b/arch/parisc/include/asm/unistd.h
@@ -170,12 +170,4 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5)	\
 
 #undef STR
 
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
-
 #endif /* _ASM_PARISC_UNISTD_H_ */
diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index 4b12890642eb..83ded26cad06 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -421,14 +421,11 @@ void purge_tlb_entries(struct mm_struct *mm, unsigned long addr)
         /* Note: purge_tlb_entries can be called at startup with
            no context.  */
 
-        /* Disable preemption while we play with %sr1.  */
-        preempt_disable();
-        mtsp(mm->context, 1);
         purge_tlb_start(flags);
+        mtsp(mm->context, 1);
         pdtlb(addr);
         pitlb(addr);
         purge_tlb_end(flags);
-        preempt_enable();
 }
 EXPORT_SYMBOL(purge_tlb_entries);
 
diff --git a/arch/parisc/kernel/parisc_ksyms.c b/arch/parisc/kernel/parisc_ksyms.c
index 6795dc6c995f..568b2c61ea02 100644
--- a/arch/parisc/kernel/parisc_ksyms.c
+++ b/arch/parisc/kernel/parisc_ksyms.c
@@ -120,11 +120,13 @@ extern void __ashrdi3(void);
 extern void __ashldi3(void);
 extern void __lshrdi3(void);
 extern void __muldi3(void);
+extern void __ucmpdi2(void);
 
 EXPORT_SYMBOL(__ashrdi3);
 EXPORT_SYMBOL(__ashldi3);
 EXPORT_SYMBOL(__lshrdi3);
 EXPORT_SYMBOL(__muldi3);
+EXPORT_SYMBOL(__ucmpdi2);
 
 asmlinkage void * __canonicalize_funcptr_for_compare(void *);
 EXPORT_SYMBOL(__canonicalize_funcptr_for_compare);
diff --git a/arch/parisc/kernel/pdc_chassis.c b/arch/parisc/kernel/pdc_chassis.c
index d47ba1aa8253..3e04242de5a7 100644
--- a/arch/parisc/kernel/pdc_chassis.c
+++ b/arch/parisc/kernel/pdc_chassis.c
@@ -30,11 +30,13 @@
 #endif
 
 #include <linux/init.h>
+#include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/reboot.h>
 #include <linux/notifier.h>
 #include <linux/cache.h>
 #include <linux/proc_fs.h>
+#include <linux/seq_file.h>
 
 #include <asm/pdc_chassis.h>
 #include <asm/processor.h>
@@ -244,38 +246,38 @@ int pdc_chassis_send_status(int message)
 
 #ifdef CONFIG_PDC_CHASSIS_WARN
 #ifdef CONFIG_PROC_FS
-static int pdc_chassis_warn_pread(char *page, char **start, off_t off,
-                int count, int *eof, void *data)
+static int pdc_chassis_warn_show(struct seq_file *m, void *v)
 {
-        char *out = page;
-        int len, ret;
         unsigned long warn;
         u32 warnreg;
 
-        ret = pdc_chassis_warn(&warn);
-        if (ret != PDC_OK)
+        if (pdc_chassis_warn(&warn) != PDC_OK)
                 return -EIO;
 
         warnreg = (warn & 0xFFFFFFFF);
 
         if ((warnreg >> 24) & 0xFF)
-                out += sprintf(out, "Chassis component failure! (eg fan or PSU): 0x%.2x\n", ((warnreg >> 24) & 0xFF));
-
-        out += sprintf(out, "Battery: %s\n", (warnreg & 0x04) ? "Low!" : "OK");
-        out += sprintf(out, "Temp low: %s\n", (warnreg & 0x02) ? "Exceeded!" : "OK");
-        out += sprintf(out, "Temp mid: %s\n", (warnreg & 0x01) ? "Exceeded!" : "OK");
-
-        len = out - page - off;
-        if (len < count) {
-                *eof = 1;
-                if (len <= 0) return 0;
-        } else {
-                len = count;
-        }
-        *start = page + off;
-        return len;
+                seq_printf(m, "Chassis component failure! (eg fan or PSU): 0x%.2x\n",
+                           (warnreg >> 24) & 0xFF);
+
+        seq_printf(m, "Battery: %s\n", (warnreg & 0x04) ? "Low!" : "OK");
+        seq_printf(m, "Temp low: %s\n", (warnreg & 0x02) ? "Exceeded!" : "OK");
+        seq_printf(m, "Temp mid: %s\n", (warnreg & 0x01) ? "Exceeded!" : "OK");
+        return 0;
+}
+
+static int pdc_chassis_warn_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, pdc_chassis_warn_show, NULL);
 }
 
+static const struct file_operations pdc_chassis_warn_fops = {
+        .open           = pdc_chassis_warn_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
 static int __init pdc_chassis_create_procfs(void)
 {
         unsigned long test;
@@ -290,8 +292,7 @@ static int __init pdc_chassis_create_procfs(void)
 
         printk(KERN_INFO "Enabling PDC chassis warnings support v%s\n",
                         PDC_CHASSIS_VER);
-        create_proc_read_entry("chassis", 0400, NULL, pdc_chassis_warn_pread,
-                                NULL);
+        proc_create("chassis", 0400, NULL, &pdc_chassis_warn_fops);
         return 0;
 }
 
diff --git a/arch/parisc/kernel/process.c b/arch/parisc/kernel/process.c
index d13507246c5d..55f92b614182 100644
--- a/arch/parisc/kernel/process.c
+++ b/arch/parisc/kernel/process.c
@@ -59,28 +59,6 @@
 #include <asm/unwind.h>
 #include <asm/sections.h>
 
-/*
- * The idle thread. There's no useful work to be
- * done, so just try to conserve power and have a
- * low exit latency (ie sit in a loop waiting for
- * somebody to say that they'd like to reschedule)
- */
-void cpu_idle(void)
-{
-        set_thread_flag(TIF_POLLING_NRFLAG);
-
-        /* endless idle loop with no priority at all */
-        while (1) {
-                rcu_idle_enter();
-                while (!need_resched())
-                        barrier();
-                rcu_idle_exit();
-                schedule_preempt_disabled();
-                check_pgt_cache();
-        }
-}
-
-
 #define COMMAND_GLOBAL  F_EXTEND(0xfffe0030)
 #define CMD_RESET       5       /* reset any module */
 
diff --git a/arch/parisc/kernel/smp.c b/arch/parisc/kernel/smp.c
index 6266730efd61..fd1bb1519c2b 100644
--- a/arch/parisc/kernel/smp.c
+++ b/arch/parisc/kernel/smp.c
@@ -329,7 +329,7 @@ void __init smp_callin(void)
 
         local_irq_enable();  /* Interrupts have been off until now */
 
-        cpu_idle();      /* Wait for timer to schedule some work */
+        cpu_startup_entry(CPUHP_ONLINE);
 
         /* NOTREACHED */
         panic("smp_callin() AAAAaaaaahhhh....\n");
diff --git a/arch/parisc/kernel/sys_parisc32.c b/arch/parisc/kernel/sys_parisc32.c
index 051c8b90231f..f517e08e7f0d 100644
--- a/arch/parisc/kernel/sys_parisc32.c
+++ b/arch/parisc/kernel/sys_parisc32.c
@@ -60,47 +60,6 @@ asmlinkage long sys32_unimplemented(int r26, int r25, int r24, int r23,
     return -ENOSYS;
 }
 
-/* Note: it is necessary to treat out_fd and in_fd as unsigned ints, with the
- * corresponding cast to a signed int to insure that the proper conversion
- * (sign extension) between the register representation of a signed int (msr in
- * 32-bit mode) and the register representation of a signed int (msr in 64-bit
- * mode) is performed.
- */
-asmlinkage long sys32_sendfile(u32 out_fd, u32 in_fd,
-                               compat_off_t __user *offset, compat_size_t count)
-{
-        return compat_sys_sendfile((int)out_fd, (int)in_fd, offset, count);
-}
-
-asmlinkage long sys32_sendfile64(u32 out_fd, u32 in_fd,
-                                 compat_loff_t __user *offset, compat_size_t count)
-{
-        return sys_sendfile64((int)out_fd, (int)in_fd,
-                                (loff_t __user *)offset, count);
-}
-
-asmlinkage long sys32_semctl(int semid, int semnum, int cmd, union semun arg)
-{
-        union semun u;
-        
-        if (cmd == SETVAL) {
-                /* Ugh.  arg is a union of int,ptr,ptr,ptr, so is 8 bytes.
-                 * The int should be in the first 4, but our argument
-                 * frobbing has left it in the last 4.
-                 */
-                u.val = *((int *)&arg + 1);
-                return sys_semctl (semid, semnum, cmd, u);
-        }
-        return sys_semctl (semid, semnum, cmd, arg);
-}
-
-long sys32_lookup_dcookie(u32 cookie_high, u32 cookie_low, char __user *buf,
-                          size_t len)
-{
-        return sys_lookup_dcookie((u64)cookie_high << 32 | cookie_low,
-                                  buf, len);
-}
-
 asmlinkage long compat_sys_fanotify_mark(int fan_fd, int flags, u32 mask_hi,
                                          u32 mask_lo, int fd,
                                          const char __user *pathname)
diff --git a/arch/parisc/kernel/syscall_table.S b/arch/parisc/kernel/syscall_table.S
index f57dc137b8dd..0c9107285e66 100644
--- a/arch/parisc/kernel/syscall_table.S
+++ b/arch/parisc/kernel/syscall_table.S
@@ -198,7 +198,7 @@
         ENTRY_SAME(madvise)
         ENTRY_SAME(clone_wrapper)       /* 120 */
         ENTRY_SAME(setdomainname)
-        ENTRY_DIFF(sendfile)
+        ENTRY_COMP(sendfile)
         /* struct sockaddr... */
         ENTRY_SAME(recvfrom)
         /* struct timex contains longs */
@@ -282,7 +282,7 @@
         ENTRY_COMP(recvmsg)
         ENTRY_SAME(semop)               /* 185 */
         ENTRY_SAME(semget)
-        ENTRY_DIFF(semctl)
+        ENTRY_COMP(semctl)
         ENTRY_COMP(msgsnd)
         ENTRY_COMP(msgrcv)
         ENTRY_SAME(msgget)              /* 190 */
@@ -304,7 +304,7 @@
         ENTRY_SAME(gettid)
         ENTRY_OURS(readahead)
         ENTRY_SAME(tkill)
-        ENTRY_DIFF(sendfile64)
+        ENTRY_COMP(sendfile64)
         ENTRY_COMP(futex)               /* 210 */
         ENTRY_COMP(sched_setaffinity)
         ENTRY_COMP(sched_getaffinity)
@@ -318,7 +318,7 @@
         ENTRY_SAME(alloc_hugepages)     /* 220 */
         ENTRY_SAME(free_hugepages)
         ENTRY_SAME(exit_group)
-        ENTRY_DIFF(lookup_dcookie)
+        ENTRY_COMP(lookup_dcookie)
         ENTRY_SAME(epoll_create)
         ENTRY_SAME(epoll_ctl)           /* 225 */
         ENTRY_SAME(epoll_wait)
diff --git a/arch/parisc/kernel/traps.c b/arch/parisc/kernel/traps.c
index aeb8f8f2c07a..f702bff0bed9 100644
--- a/arch/parisc/kernel/traps.c
+++ b/arch/parisc/kernel/traps.c
@@ -126,6 +126,8 @@ void show_regs(struct pt_regs *regs)
         user = user_mode(regs);
         level = user ? KERN_DEBUG : KERN_CRIT;
 
+        show_regs_print_info(level);
+
         print_gr(level, regs);
 
         for (i = 0; i < 8; i += 4)
@@ -158,14 +160,6 @@ void show_regs(struct pt_regs *regs)
         }
 }
 
-
-void dump_stack(void)
-{
-        show_stack(NULL, NULL);
-}
-
-EXPORT_SYMBOL(dump_stack);
-
 static void do_show_stack(struct unwind_frame_info *info)
 {
         int i = 1;
diff --git a/arch/parisc/lib/Makefile b/arch/parisc/lib/Makefile
index 5f2e6904d14a..5651536ac733 100644
--- a/arch/parisc/lib/Makefile
+++ b/arch/parisc/lib/Makefile
@@ -2,6 +2,7 @@
 # Makefile for parisc-specific library files
 #
 
-lib-y   := lusercopy.o bitops.o checksum.o io.o memset.o fixup.o memcpy.o
+lib-y   := lusercopy.o bitops.o checksum.o io.o memset.o fixup.o memcpy.o \
+           ucmpdi2.o
 
 obj-y   := iomap.o
diff --git a/arch/parisc/lib/ucmpdi2.c b/arch/parisc/lib/ucmpdi2.c
new file mode 100644
index 000000000000..149c016f32c5
--- /dev/null
+++ b/arch/parisc/lib/ucmpdi2.c
@@ -0,0 +1,25 @@
+#include <linux/module.h>
+
+union ull_union {
+        unsigned long long ull;
+        struct {
+                unsigned int high;
+                unsigned int low;
+        } ui;
+};
+
+int __ucmpdi2(unsigned long long a, unsigned long long b)
+{
+        union ull_union au = {.ull = a};
+        union ull_union bu = {.ull = b};
+
+        if (au.ui.high < bu.ui.high)
+                return 0;
+        else if (au.ui.high > bu.ui.high)
+                return 2;
+        if (au.ui.low < bu.ui.low)
+                return 0;
+        else if (au.ui.low > bu.ui.low)
+                return 2;
+        return 1;
+}
diff --git a/arch/parisc/mm/init.c b/arch/parisc/mm/init.c
index 3ac462de53a4..157b931e7b09 100644
--- a/arch/parisc/mm/init.c
+++ b/arch/parisc/mm/init.c
@@ -505,7 +505,6 @@ static void __init map_pages(unsigned long start_vaddr,
 
 void free_initmem(void)
 {
-        unsigned long addr;
         unsigned long init_begin = (unsigned long)__init_begin;
         unsigned long init_end = (unsigned long)__init_end;
 
@@ -533,19 +532,10 @@ void free_initmem(void)
          * pages are no-longer executable */
         flush_icache_range(init_begin, init_end);
         
-        for (addr = init_begin; addr < init_end; addr += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(addr));
-                init_page_count(virt_to_page(addr));
-                free_page(addr);
-                num_physpages++;
-                totalram_pages++;
-        }
+        num_physpages += free_initmem_default(0);
 
         /* set up a new led state on systems shipped LED State panel */
         pdc_chassis_send_status(PDC_CHASSIS_DIRECT_BCOMPLETE);
-        
-        printk(KERN_INFO "Freeing unused kernel memory: %luk freed\n",
-                (init_end - init_begin) >> 10);
 }
 
 
@@ -697,6 +687,8 @@ void show_mem(unsigned int filter)
 
         printk(KERN_INFO "Mem-info:\n");
         show_free_areas(filter);
+        if (filter & SHOW_MEM_FILTER_PAGE_COUNT)
+                return;
 #ifndef CONFIG_DISCONTIGMEM
         i = max_mapnr;
         while (i-- > 0) {
@@ -1107,15 +1099,6 @@ void flush_tlb_all(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        if (start >= end)
-                return;
-        printk(KERN_INFO "Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
-        for (; start < end; start += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(start));
-                init_page_count(virt_to_page(start));
-                free_page(start);
-                num_physpages++;
-                totalram_pages++;
-        }
+        num_physpages += free_reserved_area(start, end, 0, "initrd");
 }
 #endif
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index ea5bb045983a..bbbe02197afb 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -114,7 +114,6 @@ config PPC
         select USE_GENERIC_SMP_HELPERS if SMP
         select HAVE_OPROFILE
         select HAVE_DEBUG_KMEMLEAK
-        select HAVE_SYSCALL_WRAPPERS if PPC64
         select GENERIC_ATOMIC64 if PPC32
         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
         select HAVE_PERF_EVENTS
@@ -428,11 +427,6 @@ config NODES_SHIFT
         default "4"
         depends on NEED_MULTIPLE_NODES
 
-config MAX_ACTIVE_REGIONS
-        int
-        default "256" if PPC64
-        default "32"
-
 config ARCH_SELECT_MEMORY_MODEL
         def_bool y
         depends on PPC64
@@ -647,14 +641,14 @@ menu "Bus options"
 
 config ISA
         bool "Support for ISA-bus hardware"
-        depends on PPC_PREP || PPC_CHRP
+        depends on PPC_CHRP
         select PPC_I8259
         help
           Find out whether you have ISA slots on your motherboard.  ISA is the
           name of a bus system, i.e. the way the CPU talks to the other stuff
           inside your box.  If you have an Apple machine, say N here; if you
-          have an IBM RS/6000 or pSeries machine or a PReP machine, say Y.  If
-          you have an embedded board, consult your board documentation.
+          have an IBM RS/6000 or pSeries machine, say Y.  If you have an
+          embedded board, consult your board documentation.
 
 config ZONE_DMA
         bool
@@ -686,7 +680,6 @@ config SBUS
 config FSL_SOC
         bool
         select HAVE_CAN_FLEXCAN if NET && CAN
-        select PPC_CLOCK
 
 config FSL_PCI
         bool
@@ -745,7 +738,6 @@ config PCI
         bool "PCI support" if PPC_PCI_CHOICE
         default y if !40x && !CPM2 && !8xx && !PPC_83xx \
                 && !PPC_85xx && !PPC_86xx && !GAMECUBE_COMMON
-        default PCI_PERMEDIA if !4xx && !CPM2 && !8xx
         default PCI_QSPAN if !4xx && !CPM2 && 8xx
         select ARCH_SUPPORTS_MSI
         select GENERIC_PCI_IOMAP
@@ -775,11 +767,6 @@ config PCI_8260
         select PPC_INDIRECT_PCI
         default y
 
-config 8260_PCI9
-        bool "Enable workaround for MPC826x erratum PCI 9"
-        depends on PCI_8260 && !8272
-        default y
-
 source "drivers/pci/pcie/Kconfig"
 
 source "drivers/pci/Kconfig"
@@ -969,7 +956,7 @@ config TASK_SIZE_BOOL
 
 config TASK_SIZE
         hex "Size of user task space" if TASK_SIZE_BOOL
-        default "0x80000000" if PPC_PREP || PPC_8xx
+        default "0x80000000" if PPC_8xx
         default "0xc0000000"
 
 config CONSISTENT_SIZE_BOOL
diff --git a/arch/powerpc/boot/dts/ac14xx.dts b/arch/powerpc/boot/dts/ac14xx.dts
new file mode 100644
index 000000000000..a27a4609bb42
--- /dev/null
+++ b/arch/powerpc/boot/dts/ac14xx.dts
@@ -0,0 +1,392 @@
+/*
+ * Device Tree Source for the MPC5121e based ac14xx board
+ *
+ * Copyright 2012 Anatolij Gustschin <agust@denx.de>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+
+/include/ "mpc5121.dtsi"
+
+/ {
+        model = "ac14xx";
+        compatible = "ifm,ac14xx", "fsl,mpc5121";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        aliases {
+                serial0 = &serial0;
+                serial1 = &serial7;
+                spi4 = &spi4;
+                spi5 = &spi5;
+        };
+
+        cpus {
+                PowerPC,5121@0 {
+                        timebase-frequency = <40000000>;        /*  40 MHz (csb/4) */
+                        bus-frequency = <160000000>;            /* 160 MHz csb bus */
+                        clock-frequency = <400000000>;          /* 400 MHz ppc core */
+                };
+        };
+
+        memory {
+                reg = <0x00000000 0x10000000>;                  /* 256MB at 0 */
+        };
+
+        nfc@40000000 {
+                status = "disabled";
+        };
+
+        localbus@80000020 {
+                ranges = <0x0 0x0 0xfc000000 0x04000000 /* CS0: NOR flash */
+                          0x1 0x0 0xe0000000 0x00010000 /* CS1: FRAM */
+                          0x2 0x0 0xe0100000 0x00080000 /* CS2: asi1 */
+                          0x3 0x0 0xe0300000 0x00020000 /* CS3: comm */
+                          0x5 0x0 0xe0400000 0x00010000 /* CS5: safety */
+                          0x6 0x0 0xe0200000 0x00080000>; /* CS6: asi2 */
+
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0x00000000 0x04000000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        bank-width = <2>;
+                        device-width = <2>;
+
+                        partition@0 {
+                                label = "dtb-kernel-production";
+                                reg = <0x00000000 0x00400000>;
+                        };
+                        partition@1 {
+                                label = "filesystem-production";
+                                reg = <0x00400000 0x03400000>;
+                        };
+
+                        partition@2 {
+                                label = "recovery";
+                                reg = <0x03800000 0x00700000>;
+                        };
+
+                        partition@3 {
+                                label = "uboot-code";
+                                reg = <0x03f00000 0x00040000>;
+                        };
+                        partition@4 {
+                                label = "uboot-env1";
+                                reg = <0x03f40000 0x00020000>;
+                        };
+                        partition@5 {
+                                label = "uboot-env2";
+                                reg = <0x03f60000 0x00020000>;
+                        };
+                };
+
+                fram@1,0 {
+                        compatible = "ifm,ac14xx-fram", "linux,uio-pdrv-genirq";
+                        reg = <1 0x00000000 0x00010000>;
+                };
+
+                asi@2,0 {
+                        /* masters mapping: CS, CS offset, size */
+                        reg = <2 0x00000000 0x00080000
+                               6 0x00000000 0x00080000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "ifm,ac14xx-asi-fpga";
+                        gpios = <
+                                &gpio_pic 26 0  /* prog */
+                                &gpio_pic 27 0  /* done */
+                                &gpio_pic 10 0  /* reset */
+                                >;
+
+                        master@1 {
+                                interrupts = <20 0x2>;
+                                interrupt-parent = <&gpio_pic>;
+                                chipselect = <2 0x00009000 0x00009100>;
+                                label = "AS-i master 1";
+                        };
+
+                        master@2 {
+                                interrupts = <21 0x2>;
+                                interrupt-parent = <&gpio_pic>;
+                                chipselect = <6 0x00009000 0x00009100>;
+                                label = "AS-i master 2";
+                        };
+                };
+
+                netx@3,0 {
+                        compatible = "ifm,netx";
+                        reg = <0x3 0x00000000 0x00020000>;
+                        chipselect = <3 0x00101140 0x00203100>;
+                        interrupts = <17 0x8>;
+                        gpios = <&gpio_pic 15 0>;
+                };
+
+                safety@5,0 {
+                        compatible = "ifm,safety";
+                        reg = <0x5 0x00000000 0x00010000>;
+                        chipselect = <5 0x00009000 0x00009100>;
+                        interrupts = <22 0x2>;
+                        interrupt-parent = <&gpio_pic>;
+                        gpios = <
+                                &gpio_pic 12 0  /* prog */
+                                &gpio_pic 11 0  /* done */
+                                >;
+                };
+        };
+
+        soc@80000000 {
+
+                clock@f00 {
+                        compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
+                };
+
+                /*
+                 * GPIO PIC:
+                 * interrupts cell = <pin nr, sense>
+                 * sense == 8: Level, low assertion
+                 * sense == 2: Edge, high-to-low change
+                 */
+                gpio_pic: gpio@1100 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                sdhc@1500 {
+                        cd-gpios = <&gpio_pic 23 0>;    /* card detect */
+                        wp-gpios = <&gpio_pic 24 0>;    /* write protect */
+                        wp-inverted;                    /* WP active high */
+                };
+
+                i2c@1700 {
+                        /* use Fast-mode */
+                        clock-frequency = <400000>;
+
+                        at24@30 {
+                                compatible = "at24,24c01";
+                                reg = <0x30>;
+                        };
+
+                        at24@31 {
+                                compatible = "at24,24c01";
+                                reg = <0x31>;
+                        };
+
+                        temp@48 {
+                                compatible = "ad,ad7414";
+                                reg = <0x48>;
+                        };
+
+                        at24@50 {
+                                compatible = "at24,24c01";
+                                reg = <0x50>;
+                        };
+
+                        at24@51 {
+                                compatible = "at24,24c01";
+                                reg = <0x51>;
+                        };
+
+                        at24@52 {
+                                compatible = "at24,24c01";
+                                reg = <0x52>;
+                        };
+
+                        at24@53 {
+                                compatible = "at24,24c01";
+                                reg = <0x53>;
+                        };
+
+                        at24@54 {
+                                compatible = "at24,24c01";
+                                reg = <0x54>;
+                        };
+
+                        at24@55 {
+                                compatible = "at24,24c01";
+                                reg = <0x55>;
+                        };
+
+                        at24@56 {
+                                compatible = "at24,24c01";
+                                reg = <0x56>;
+                        };
+
+                        at24@57 {
+                                compatible = "at24,24c01";
+                                reg = <0x57>;
+                        };
+
+                        rtc@68 {
+                                compatible = "stm,m41t00";
+                                reg = <0x68>;
+                        };
+                };
+
+                axe_pic: axe-base@2000 {
+                        compatible = "fsl,mpc5121-axe-base";
+                        reg = <0x2000 0x100>;
+                        interrupts = <42 0x8>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                axe-app {
+                        compatible = "fsl,mpc5121-axe-app";
+                        interrupt-parent = <&axe_pic>;
+                        interrupts = <
+                                        /* soft interrupts */
+                                        0 0x0   1 0x0   2 0x0   3 0x0
+                                        4 0x0   5 0x0   6 0x0   7 0x0
+                                        /* fifo interrupts */
+                                        8 0x0   9 0x0   10 0x0  11 0x0
+                                >;
+                };
+
+                display@2100 {
+                        edid = [00 FF FF FF FF FF FF 00 14 94 00 00 00 00 00 00
+                                0A 12 01 03 80 1C 23 78 CA 88 FF 94 52 54 8E 27
+                                1E 4C 50 00 00 00 01 01 01 01 01 01 01 01 01 01
+                                01 01 01 01 01 01 FB 00 B0 14 00 DC 05 00 08 04
+                                21 00 1C 23 00 00 00 18 00 00 00 FD 00 38 3C 1F
+                                3C 01 0A 20 20 20 20 20 20 20 00 00 00 FC 00 45
+                                54 30 31 38 30 30 33 44 4D 55 0A 0A 00 00 00 10
+                                00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D5];
+                };
+
+                can@2300 {
+                        status = "disabled";
+                };
+
+                can@2380 {
+                        status = "disabled";
+                };
+
+                viu@2400 {
+                        status = "disabled";
+                };
+
+                mdio@2800 {
+                        phy0: ethernet-phy@1f {
+                                compatible = "smsc,lan8700";
+                                reg = <0x1f>;
+                        };
+                };
+
+                enet: ethernet@2800 {
+                        phy-handle = <&phy0>;
+                };
+
+                usb@3000 {
+                        status = "disabled";
+                };
+
+                usb@4000 {
+                        status = "disabled";
+                };
+
+                /* PSC3 serial port A, aka ttyPSC0 */
+                serial0: psc@11300 {
+                        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+                        fsl,rx-fifo-size = <512>;
+                        fsl,tx-fifo-size = <512>;
+                };
+
+                /* PSC4 in SPI mode */
+                spi4: psc@11400 {
+                        compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
+                        fsl,rx-fifo-size = <768>;
+                        fsl,tx-fifo-size = <768>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        num-cs = <1>;
+                        cs-gpios = <&gpio_pic 25 0>;
+
+                        flash: m25p128@0 {
+                                compatible = "st,m25p128";
+                                spi-max-frequency = <20000000>;
+                                reg = <0>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+
+                                partition@0 {
+                                        label = "spi-flash0";
+                                        reg = <0x00000000 0x01000000>;
+                                };
+                        };
+                };
+
+                /* PSC5 in SPI mode */
+                spi5: psc@11500 {
+                        compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
+                        fsl,mode = "spi-master";
+                        fsl,rx-fifo-size = <128>;
+                        fsl,tx-fifo-size = <128>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        lcd@0 {
+                                compatible = "ilitek,ili922x";
+                                reg = <0>;
+                                spi-max-frequency = <100000>;
+                                spi-cpol;
+                                spi-cpha;
+                        };
+                };
+
+                /* PSC7 serial port C, aka ttyPSC2 */
+                serial7: psc@11700 {
+                        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+                        fsl,rx-fifo-size = <512>;
+                        fsl,tx-fifo-size = <512>;
+                };
+
+                matrix_keypad@0 {
+                        compatible = "gpio-matrix-keypad";
+                        debounce-delay-ms = <5>;
+                        col-scan-delay-us = <1>;
+                        gpio-activelow;
+                        col-gpios-binary;
+                        col-switch-delay-ms = <200>;
+
+                        col-gpios = <&gpio_pic 1 0>;    /* pin1 */
+
+                        row-gpios = <&gpio_pic 2 0      /* pin2 */
+                                     &gpio_pic 3 0      /* pin3 */
+                                     &gpio_pic 4 0>;    /* pin4 */
+
+                        linux,keymap = <0x0000006e      /* FN LEFT */
+                                        0x01000067      /* UP */
+                                        0x02000066      /* FN RIGHT */
+                                        0x00010069      /* LEFT */
+                                        0x0101006a      /* DOWN */
+                                        0x0201006c>;    /* RIGHT */
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                backlight {
+                        label = "backlight";
+                        gpios = <&gpio_pic 0 0>;
+                        default-state = "keep";
+                };
+                green {
+                        label = "green";
+                        gpios = <&gpio_pic 18 0>;
+                        default-state = "keep";
+                };
+                red {
+                        label = "red";
+                        gpios = <&gpio_pic 19 0>;
+                        default-state = "keep";
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/b4420qds.dts b/arch/powerpc/boot/dts/b4420qds.dts
new file mode 100644
index 000000000000..923156d03b30
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4420qds.dts
@@ -0,0 +1,50 @@
+/*
+ * B4420DS Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+/include/ "fsl/b4420si-pre.dtsi"
+/include/ "b4qds.dts"
+
+/ {
+        model = "fsl,B4420QDS";
+        compatible = "fsl,B4420QDS";
+
+        ifc: localbus@ffe124000 {
+                board-control@3,0 {
+                        compatible = "fsl,b4420qds-fpga", "fsl,fpga-qixis";
+                };
+        };
+
+};
+
+/include/ "fsl/b4420si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/b4860qds.dts b/arch/powerpc/boot/dts/b4860qds.dts
new file mode 100644
index 000000000000..78907f38bb77
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4860qds.dts
@@ -0,0 +1,61 @@
+/*
+ * B4860DS Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/b4860si-pre.dtsi"
+/include/ "b4qds.dts"
+
+/ {
+        model = "fsl,B4860QDS";
+        compatible = "fsl,B4860QDS";
+
+        ifc: localbus@ffe124000 {
+                board-control@3,0 {
+                        compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
+                };
+        };
+
+        rio: rapidio@ffe0c0000 {
+                reg = <0xf 0xfe0c0000 0 0x11000>;
+
+                port1 {
+                        ranges = <0 0 0xc 0x20000000 0 0x10000000>;
+                };
+                port2 {
+                        ranges = <0 0 0xc 0x30000000 0 0x10000000>;
+                };
+        };
+
+};
+
+/include/ "fsl/b4860si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/b4qds.dts b/arch/powerpc/boot/dts/b4qds.dts
new file mode 100644
index 000000000000..e6d2f8f90544
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4qds.dts
@@ -0,0 +1,169 @@
+/*
+ * B4420DS Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+/ {
+        model = "fsl,B4QDS";
+        compatible = "fsl,B4QDS";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+
+        ifc: localbus@ffe124000 {
+                reg = <0xf 0xfe124000 0 0x2000>;
+                ranges = <0 0 0xf 0xe8000000 0x08000000
+                          2 0 0xf 0xff800000 0x00010000
+                          3 0 0xf 0xffdf0000 0x00008000>;
+
+                nor@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x0 0x0 0x8000000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+                };
+
+                nand@2,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,ifc-nand";
+                        reg = <0x2 0x0 0x10000>;
+
+                        partition@0 {
+                                /* This location must not be altered  */
+                                /* 1MB for u-boot Bootloader Image */
+                                reg = <0x0 0x00100000>;
+                                label = "NAND U-Boot Image";
+                                read-only;
+                        };
+
+                        partition@100000 {
+                                /* 1MB for DTB Image */
+                                reg = <0x00100000 0x00100000>;
+                                label = "NAND DTB Image";
+                        };
+
+                        partition@200000 {
+                                /* 10MB for Linux Kernel Image */
+                                reg = <0x00200000 0x00A00000>;
+                                label = "NAND Linux Kernel Image";
+                        };
+
+                        partition@c00000 {
+                                /* 500MB for Root file System Image */
+                                reg = <0x00c00000 0x1F400000>;
+                                label = "NAND RFS Image";
+                        };
+                };
+
+                board-control@3,0 {
+                        compatible = "fsl,b4qds-fpga", "fsl,fpga-qixis";
+                        reg = <3 0 0x300>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+        };
+
+        dcsr: dcsr@f00000000 {
+                ranges = <0x00000000 0xf 0x00000000 0x01052000>;
+        };
+
+        soc: soc@ffe000000 {
+                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+                reg = <0xf 0xfe000000 0 0x00001000>;
+                spi@110000 {
+                        flash@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "sst,sst25wf040";
+                                reg = <0>;
+                                spi-max-frequency = <40000000>; /* input clock */
+                        };
+                };
+
+                sdhc@114000 {
+                        /*Disabled as there is no sdhc connector on B4420QDS board*/
+                        status = "disabled";
+                };
+
+                i2c@118000 {
+                        eeprom@50 {
+                                compatible = "at24,24c64";
+                                reg = <0x50>;
+                        };
+                        eeprom@51 {
+                                compatible = "at24,24c256";
+                                reg = <0x51>;
+                        };
+                        eeprom@53 {
+                                compatible = "at24,24c256";
+                                reg = <0x53>;
+                        };
+                        eeprom@57 {
+                                compatible = "at24,24c256";
+                                reg = <0x57>;
+                        };
+                        rtc@68 {
+                                compatible = "dallas,ds3232";
+                                reg = <0x68>;
+                        };
+                };
+
+                usb@210000 {
+                        dr_mode = "host";
+                        phy_type = "ulpi";
+                };
+
+        };
+
+        pci0: pcie@ffe200000 {
+                reg = <0xf 0xfe200000 0 0x10000>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+                          0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x20000000
+
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+
+};
+
+/include/ "fsl/b4si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
new file mode 100644
index 000000000000..5a6615d0ade2
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -0,0 +1,98 @@
+/*
+ * B4420 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+/include/ "b4si-post.dtsi"
+
+/* controller at 0x200000 */
+&pci0 {
+        compatible = "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
+};
+
+&dcsr {
+        dcsr-epu@0 {
+                compatible = "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
+        };
+        dcsr-npc {
+                compatible = "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
+        };
+        dcsr-dpaa@9000 {
+                compatible = "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
+        };
+        dcsr-ocn@11000 {
+                compatible = "fsl,b4420-dcsr-ocn", "fsl,dcsr-ocn";
+        };
+        dcsr-nal@18000 {
+                compatible = "fsl,b4420-dcsr-nal", "fsl,dcsr-nal";
+        };
+        dcsr-rcpm@22000 {
+                compatible = "fsl,b4420-dcsr-rcpm", "fsl,dcsr-rcpm";
+        };
+        dcsr-snpc@30000 {
+                compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
+        };
+        dcsr-snpc@31000 {
+                compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
+        };
+        dcsr-cpu-sb-proxy@108000 {
+                compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu1>;
+                reg = <0x108000 0x1000 0x109000 0x1000>;
+        };
+};
+
+&soc {
+        cpc: l3-cache-controller@10000 {
+                compatible = "fsl,b4420-l3-cache-controller", "cache";
+        };
+
+        corenet-cf@18000 {
+                compatible = "fsl,b4420-corenet-cf";
+        };
+
+        guts: global-utilities@e0000 {
+                compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
+        };
+
+        clockgen: global-utilities@e1000 {
+                compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
+        };
+
+        rcpm: global-utilities@e2000 {
+                compatible = "fsl,b4420-rcpm", "fsl,qoriq-rcpm-2.0";
+        };
+
+        L2: l2-cache-controller@c20000 {
+                compatible = "fsl,b4420-l2-cache-controller";
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
new file mode 100644
index 000000000000..7b4426e0a5a5
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -0,0 +1,73 @@
+/*
+ * B4420 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+/dts-v1/;
+
+/ {
+        compatible = "fsl,B4420";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+
+        aliases {
+                ccsr = &soc;
+                dcsr = &dcsr;
+
+                serial0 = &serial0;
+                serial1 = &serial1;
+                serial2 = &serial2;
+                serial3 = &serial3;
+                pci0 = &pci0;
+                dma0 = &dma0;
+                dma1 = &dma1;
+                sdhc = &sdhc;
+        };
+
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: PowerPC,e6500@0 {
+                        device_type = "cpu";
+                        reg = <0 1>;
+                        next-level-cache = <&L2>;
+                };
+                cpu1: PowerPC,e6500@2 {
+                        device_type = "cpu";
+                        reg = <2 3>;
+                        next-level-cache = <&L2>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
new file mode 100644
index 000000000000..e5cf6c81dd66
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -0,0 +1,142 @@
+/*
+ * B4860 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "b4si-post.dtsi"
+
+/* controller at 0x200000 */
+&pci0 {
+        compatible = "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
+};
+
+&rio {
+        compatible = "fsl,srio";
+        interrupts = <16 2 1 11>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        fsl,iommu-parent = <&pamu0>;
+        ranges;
+
+        port1 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                cell-index = <1>;
+                fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
+        };
+
+        port2 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                cell-index = <2>;
+                fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
+        };
+};
+
+&dcsr {
+        dcsr-epu@0 {
+                compatible = "fsl,b4860-dcsr-epu", "fsl,dcsr-epu";
+        };
+        dcsr-npc {
+                compatible = "fsl,b4860-dcsr-cnpc", "fsl,dcsr-cnpc";
+        };
+        dcsr-dpaa@9000 {
+                compatible = "fsl,b4860-dcsr-dpaa", "fsl,dcsr-dpaa";
+        };
+        dcsr-ocn@11000 {
+                compatible = "fsl,b4860-dcsr-ocn", "fsl,dcsr-ocn";
+        };
+        dcsr-ddr@13000 {
+                compatible = "fsl,dcsr-ddr";
+                dev-handle = <&ddr2>;
+                reg = <0x13000 0x1000>;
+        };
+        dcsr-nal@18000 {
+                compatible = "fsl,b4860-dcsr-nal", "fsl,dcsr-nal";
+        };
+        dcsr-rcpm@22000 {
+                compatible = "fsl,b4860-dcsr-rcpm", "fsl,dcsr-rcpm";
+        };
+        dcsr-snpc@30000 {
+                compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
+        };
+        dcsr-snpc@31000 {
+                compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
+        };
+        dcsr-cpu-sb-proxy@108000 {
+                compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu1>;
+                reg = <0x108000 0x1000 0x109000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@110000 {
+                compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu2>;
+                reg = <0x110000 0x1000 0x111000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@118000 {
+                compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu3>;
+                reg = <0x118000 0x1000 0x119000 0x1000>;
+        };
+};
+
+&soc {
+        ddr2: memory-controller@9000 {
+                compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+                reg = <0x9000 0x1000>;
+                interrupts = <16 2 1 9>;
+        };
+
+        cpc: l3-cache-controller@10000 {
+                compatible = "fsl,b4860-l3-cache-controller", "cache";
+        };
+
+        corenet-cf@18000 {
+                compatible = "fsl,b4860-corenet-cf";
+        };
+
+        guts: global-utilities@e0000 {
+                compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";
+        };
+
+        clockgen: global-utilities@e1000 {
+                compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";
+        };
+
+        rcpm: global-utilities@e2000 {
+                compatible = "fsl,b4860-rcpm", "fsl,qoriq-rcpm-2.0";
+        };
+
+        L2: l2-cache-controller@c20000 {
+                compatible = "fsl,b4860-l2-cache-controller";
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
new file mode 100644
index 000000000000..5263fa46a3fb
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -0,0 +1,83 @@
+/*
+ * B4860 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/ {
+        compatible = "fsl,B4860";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+
+        aliases {
+                ccsr = &soc;
+                dcsr = &dcsr;
+
+                serial0 = &serial0;
+                serial1 = &serial1;
+                serial2 = &serial2;
+                serial3 = &serial3;
+                pci0 = &pci0;
+                dma0 = &dma0;
+                dma1 = &dma1;
+                sdhc = &sdhc;
+        };
+
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: PowerPC,e6500@0 {
+                        device_type = "cpu";
+                        reg = <0 1>;
+                        next-level-cache = <&L2>;
+                };
+                cpu1: PowerPC,e6500@2 {
+                        device_type = "cpu";
+                        reg = <2 3>;
+                        next-level-cache = <&L2>;
+                };
+                cpu2: PowerPC,e6500@4 {
+                        device_type = "cpu";
+                        reg = <4 5>;
+                        next-level-cache = <&L2>;
+                };
+                cpu3: PowerPC,e6500@6 {
+                        device_type = "cpu";
+                        reg = <6 7>;
+                        next-level-cache = <&L2>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
new file mode 100644
index 000000000000..73991547c69b
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -0,0 +1,268 @@
+/*
+ * B4420 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+&ifc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        compatible = "fsl,ifc", "simple-bus";
+        interrupts = <25 2 0 0>;
+};
+
+/* controller at 0x200000 */
+&pci0 {
+        compatible = "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        interrupts = <20 2 0 0>;
+        fsl,iommu-parent = <&pamu0>;
+        pcie@0 {
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                reg = <0 0 0 0 0>;
+                interrupts = <20 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 40 1 0 0
+                        0000 0 0 2 &mpic 1 1 0 0
+                        0000 0 0 3 &mpic 2 1 0 0
+                        0000 0 0 4 &mpic 3 1 0 0
+                        >;
+        };
+};
+
+&dcsr {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "fsl,dcsr", "simple-bus";
+
+        dcsr-epu@0 {
+                compatible = "fsl,b4-dcsr-epu", "fsl,dcsr-epu";
+                interrupts = <52 2 0 0
+                              84 2 0 0
+                              85 2 0 0
+                              94 2 0 0
+                              95 2 0 0>;
+                reg = <0x0 0x1000>;
+        };
+        dcsr-npc {
+                compatible = "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc";
+                reg = <0x1000 0x1000 0x1002000 0x10000>;
+        };
+        dcsr-nxc@2000 {
+                compatible = "fsl,dcsr-nxc";
+                reg = <0x2000 0x1000>;
+        };
+        dcsr-corenet {
+                compatible = "fsl,dcsr-corenet";
+                reg = <0x8000 0x1000 0x1A000 0x1000>;
+        };
+        dcsr-dpaa@9000 {
+                compatible = "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa";
+                reg = <0x9000 0x1000>;
+        };
+        dcsr-ocn@11000 {
+                compatible = "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn";
+                reg = <0x11000 0x1000>;
+        };
+        dcsr-ddr@12000 {
+                compatible = "fsl,dcsr-ddr";
+                dev-handle = <&ddr1>;
+                reg = <0x12000 0x1000>;
+        };
+        dcsr-nal@18000 {
+                compatible = "fsl,b4-dcsr-nal", "fsl,dcsr-nal";
+                reg = <0x18000 0x1000>;
+        };
+        dcsr-rcpm@22000 {
+                compatible = "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm";
+                reg = <0x22000 0x1000>;
+        };
+        dcsr-snpc@30000 {
+                compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
+                reg = <0x30000 0x1000 0x1022000 0x10000>;
+        };
+        dcsr-snpc@31000 {
+                compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
+                reg = <0x31000 0x1000 0x1042000 0x10000>;
+        };
+        dcsr-cpu-sb-proxy@100000 {
+                compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu0>;
+                reg = <0x100000 0x1000 0x101000 0x1000>;
+        };
+};
+
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "simple-bus";
+
+        soc-sram-error {
+                compatible = "fsl,soc-sram-error";
+                interrupts = <16 2 1 2>;
+        };
+
+        corenet-law@0 {
+                compatible = "fsl,corenet-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <32>;
+        };
+
+        ddr1: memory-controller@8000 {
+                compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+                reg = <0x8000 0x1000>;
+                interrupts = <16 2 1 8>;
+        };
+
+        cpc: l3-cache-controller@10000 {
+                compatible = "fsl,b4-l3-cache-controller", "cache";
+                reg = <0x10000 0x1000>;
+                interrupts = <16 2 1 4>;
+        };
+
+        corenet-cf@18000 {
+                compatible = "fsl,b4-corenet-cf";
+                reg = <0x18000 0x1000>;
+                interrupts = <16 2 1 0>;
+                fsl,ccf-num-csdids = <32>;
+                fsl,ccf-num-snoopids = <32>;
+        };
+
+        iommu@20000 {
+                compatible =  "fsl,pamu-v1.0", "fsl,pamu";
+                reg = <0x20000 0x4000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                interrupts = <
+                        24 2 0 0
+                        16 2 1 1>;
+
+
+                /* PCIe, DMA, SRIO */
+                pamu0: pamu@0 {
+                        reg = <0 0x1000>;
+                        fsl,primary-cache-geometry = <8 1>;
+                        fsl,secondary-cache-geometry = <32 2>;
+                };
+
+                /* AXI2, Maple */
+                pamu1: pamu@1000 {
+                        reg = <0x1000 0x1000>;
+                        fsl,primary-cache-geometry = <32 1>;
+                        fsl,secondary-cache-geometry = <32 2>;
+                };
+
+                /* Q/BMan */
+                pamu2: pamu@2000 {
+                        reg = <0x2000 0x1000>;
+                        fsl,primary-cache-geometry = <32 1>;
+                        fsl,secondary-cache-geometry = <32 2>;
+                };
+
+                /* AXI1, FMAN */
+                pamu3: pamu@3000 {
+                        reg = <0x3000 0x1000>;
+                        fsl,primary-cache-geometry = <32 1>;
+                        fsl,secondary-cache-geometry = <32 2>;
+                };
+        };
+
+/include/ "qoriq-mpic.dtsi"
+
+        guts: global-utilities@e0000 {
+                compatible = "fsl,b4-device-config";
+                reg = <0xe0000 0xe00>;
+                fsl,has-rstcr;
+                fsl,liodn-bits = <12>;
+        };
+
+        clockgen: global-utilities@e1000 {
+                compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
+                reg = <0xe1000 0x1000>;
+        };
+
+        rcpm: global-utilities@e2000 {
+                compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0";
+                reg = <0xe2000 0x1000>;
+        };
+
+/include/ "qoriq-dma-0.dtsi"
+        dma@100300 {
+                fsl,iommu-parent = <&pamu0>;
+                fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
+        };
+
+/include/ "qoriq-dma-1.dtsi"
+        dma@101300 {
+                fsl,iommu-parent = <&pamu0>;
+                fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
+        };
+
+/include/ "qonverge-usb2-dr-0.dtsi"
+        usb0: usb@210000 {
+                compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
+                fsl,iommu-parent = <&pamu1>;
+                fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
+        };
+
+/include/ "qoriq-espi-0.dtsi"
+        spi@110000 {
+                fsl,espi-num-chipselects = <4>;
+        };
+
+/include/ "qoriq-esdhc-0.dtsi"
+        sdhc@114000 {
+                sdhci,auto-cmd12;
+                fsl,iommu-parent = <&pamu1>;
+                fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
+        };
+
+/include/ "qoriq-i2c-0.dtsi"
+/include/ "qoriq-i2c-1.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
+/include/ "qoriq-sec5.3-0.dtsi"
+
+        L2: l2-cache-controller@c20000 {
+                compatible = "fsl,b4-l2-cache-controller";
+                reg = <0xc20000 0x1000>;
+                next-level-cache = <&cpc>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi b/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi
index 870c6535a053..ea145c91cfbd 100644
--- a/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi
+++ b/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi
@@ -53,6 +53,7 @@
                 power-isa-mmc;          // Memory Coherence
                 power-isa-scpm;         // Store Conditional Page Mobility
                 power-isa-wt;           // Wait
+                fsl,eref-deo;           // Data Cache Extended Operations
                 mmu-type = "power-embedded";
         };
 };
diff --git a/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi b/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi
index 3230212f7ad5..c254c981ae87 100644
--- a/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi
+++ b/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi
@@ -54,6 +54,7 @@
                 power-isa-scpm;         // Store Conditional Page Mobility
                 power-isa-wt;           // Wait
                 power-isa-64;           // 64-bit
+                fsl,eref-deo;           // Data Cache Extended Operations
                 mmu-type = "power-embedded";
         };
 };
diff --git a/arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi b/arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
new file mode 100644
index 000000000000..a912dbeff359
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
@@ -0,0 +1,65 @@
+/*
+ * e6500 Power ISA Device Tree Source (include)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/ {
+        cpus {
+                power-isa-version = "2.06";
+                power-isa-b;            // Base
+                power-isa-e;            // Embedded
+                power-isa-atb;          // Alternate Time Base
+                power-isa-cs;           // Cache Specification
+                power-isa-ds;           // Decorated Storage
+                power-isa-e.ed;         // Embedded.Enhanced Debug
+                power-isa-e.pd;         // Embedded.External PID
+                power-isa-e.hv;         // Embedded.Hypervisor
+                power-isa-e.le;         // Embedded.Little-Endian
+                power-isa-e.pm;         // Embedded.Performance Monitor
+                power-isa-e.pc;         // Embedded.Processor Control
+                power-isa-ecl;          // Embedded Cache Locking
+                power-isa-exp;          // External Proxy
+                power-isa-fp;           // Floating Point
+                power-isa-fp.r;         // Floating Point.Record
+                power-isa-mmc;          // Memory Coherence
+                power-isa-scpm;         // Store Conditional Page Mobility
+                power-isa-wt;           // Wait
+                power-isa-64;           // 64-bit
+                power-isa-e.pt;         // Embedded.Page Table
+                power-isa-e.hv.lrat;    // Embedded.Hypervisor.LRAT
+                power-isa-e.em;         // Embedded Multi-Threading
+                power-isa-v;            // Vector (AltiVec)
+                fsl,eref-er;            // Enhanced Reservations (Load and Reserve and Store Cond.)
+                fsl,eref-deo;           // Data Cache Extended Operations
+                mmu-type = "power-embedded";
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
index 941fa159cefb..f1105bffa915 100644
--- a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
@@ -148,6 +148,7 @@
 
         crypto: crypto@300000 {
                 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
+                fsl,sec-era = <3>;
                 #address-cells = <1>;
                 #size-cells = <1>;
                 reg = <0x30000 0x10000>;
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index 69ac1acd4349..dc6cc5afd189 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -155,7 +155,7 @@
         compatible = "fsl,dcsr", "simple-bus";
 
         dcsr-epu@0 {
-                compatible = "fsl,dcsr-epu";
+                compatible = "fsl,p2041-dcsr-epu", "fsl,dcsr-epu";
                 interrupts = <52 2 0 0
                               84 2 0 0
                               85 2 0 0>;
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index 9b5a81a4529c..3fa1e22d544a 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -182,7 +182,7 @@
         compatible = "fsl,dcsr", "simple-bus";
 
         dcsr-epu@0 {
-                compatible = "fsl,dcsr-epu";
+                compatible = "fsl,p3041-dcsr-epu", "fsl,dcsr-epu";
                 interrupts = <52 2 0 0
                               84 2 0 0
                               85 2 0 0>;
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 19859ad851eb..34769a7eafea 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -156,7 +156,7 @@
         compatible = "fsl,dcsr", "simple-bus";
 
         dcsr-epu@0 {
-                compatible = "fsl,dcsr-epu";
+                compatible = "fsl,p4080-dcsr-epu", "fsl,dcsr-epu";
                 interrupts = <52 2 0 0
                               84 2 0 0
                               85 2 0 0>;
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index 9ea77c3513f6..bc3ae5a2252f 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -184,7 +184,7 @@
         compatible = "fsl,dcsr", "simple-bus";
 
         dcsr-epu@0 {
-                compatible = "fsl,dcsr-epu";
+                compatible = "fsl,p5020-dcsr-epu", "fsl,dcsr-epu";
                 interrupts = <52 2 0 0
                               84 2 0 0
                               85 2 0 0>;
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index 97f8c26f9709..a91897f6af09 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -129,7 +129,7 @@
         compatible = "fsl,dcsr", "simple-bus";
 
         dcsr-epu@0 {
-                compatible = "fsl,dcsr-epu";
+                compatible = "fsl,p5040-dcsr-epu", "fsl,dcsr-epu";
                 interrupts = <52 2 0 0
                               84 2 0 0
                               85 2 0 0>;
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
index ffadcb563ada..bb3d8266b5ce 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
@@ -34,6 +34,7 @@
 
 crypto@30000 {
         compatible = "fsl,sec-v4.4", "fsl,sec-v4.0";
+        fsl,sec-era = <3>;
         #address-cells = <1>;
         #size-cells = <1>;
         ranges           = <0x0 0x30000 0x10000>;
diff --git a/arch/powerpc/boot/dts/fsl/qonverge-usb2-dr-0.dtsi b/arch/powerpc/boot/dts/fsl/qonverge-usb2-dr-0.dtsi
new file mode 100644
index 000000000000..29dad723091e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qonverge-usb2-dr-0.dtsi
@@ -0,0 +1,41 @@
+/*
+ * QorIQ Qonverge USB Host device tree stub [ controller @ offset 0x210000 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+usb@210000 {
+        compatible = "fsl-usb2-dr";
+        reg = <0x210000 0x1000>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        interrupts = <44 0x2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi
new file mode 100644
index 000000000000..c2f9cdadb604
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi
@@ -0,0 +1,41 @@
+/*
+ * QorIQ GPIO device tree stub [ controller @ offset 0x131000 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+gpio1: gpio@131000 {
+        compatible = "fsl,qoriq-gpio";
+        reg = <0x131000 0x1000>;
+        interrupts = <54 2 0 0>;
+        #gpio-cells = <2>;
+        gpio-controller;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi
new file mode 100644
index 000000000000..33f3ccbac83f
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi
@@ -0,0 +1,41 @@
+/*
+ * QorIQ GPIO device tree stub [ controller @ offset 0x132000 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+gpio2: gpio@132000 {
+        compatible = "fsl,qoriq-gpio";
+        reg = <0x132000 0x1000>;
+        interrupts = <86 2 0 0>;
+        #gpio-cells = <2>;
+        gpio-controller;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi
new file mode 100644
index 000000000000..86954e95ea02
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi
@@ -0,0 +1,41 @@
+/*
+ * QorIQ GPIO device tree stub [ controller @ offset 0x133000 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+gpio3: gpio@133000 {
+        compatible = "fsl,qoriq-gpio";
+        reg = <0x133000 0x1000>;
+        interrupts = <87 2 0 0>;
+        #gpio-cells = <2>;
+        gpio-controller;
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi
index 0cbbac329539..02bee5fcbb9a 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi
@@ -34,6 +34,7 @@
 
 crypto: crypto@300000 {
         compatible = "fsl,sec-v4.0";
+        fsl,sec-era = <1>;
         #address-cells = <1>;
         #size-cells = <1>;
         reg = <0x300000 0x10000>;
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi
index 7990e0d3d6f2..7f7574e53323 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi
@@ -34,6 +34,7 @@
 
 crypto: crypto@300000 {
         compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
+        fsl,sec-era = <3>;
         #address-cells = <1>;
         #size-cells = <1>;
         reg              = <0x300000 0x10000>;
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec4.1-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec5.0-0.dtsi
index 3308986bba0d..e298efbb0f3e 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-sec4.1-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec5.0-0.dtsi
@@ -1,7 +1,7 @@
 /*
- * QorIQ Sec/Crypto 4.1 device tree stub [ controller @ offset 0x300000 ]
+ * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ]
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2012 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -33,7 +33,8 @@
  */
 
 crypto: crypto@300000 {
-        compatible = "fsl,sec-v4.1", "fsl,sec-v4.0";
+        compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+        fsl,sec-era = <5>;
         #address-cells = <1>;
         #size-cells = <1>;
         reg              = <0x300000 0x10000>;
@@ -41,35 +42,35 @@ crypto: crypto@300000 {
         interrupts       = <92 2 0 0>;
 
         sec_jr0: jr@1000 {
-                compatible = "fsl,sec-v4.1-job-ring",
+                compatible = "fsl,sec-v5.0-job-ring",
                              "fsl,sec-v4.0-job-ring";
                 reg = <0x1000 0x1000>;
                 interrupts = <88 2 0 0>;
         };
 
         sec_jr1: jr@2000 {
-                compatible = "fsl,sec-v4.1-job-ring",
+                compatible = "fsl,sec-v5.0-job-ring",
                              "fsl,sec-v4.0-job-ring";
                 reg = <0x2000 0x1000>;
                 interrupts = <89 2 0 0>;
         };
 
         sec_jr2: jr@3000 {
-                compatible = "fsl,sec-v4.1-job-ring",
+                compatible = "fsl,sec-v5.0-job-ring",
                              "fsl,sec-v4.0-job-ring";
                 reg = <0x3000 0x1000>;
                 interrupts = <90 2 0 0>;
         };
 
         sec_jr3: jr@4000 {
-                compatible = "fsl,sec-v4.1-job-ring",
+                compatible = "fsl,sec-v5.0-job-ring",
                              "fsl,sec-v4.0-job-ring";
                 reg = <0x4000 0x1000>;
                 interrupts = <91 2 0 0>;
         };
 
         rtic@6000 {
-                compatible = "fsl,sec-v4.1-rtic",
+                compatible = "fsl,sec-v5.0-rtic",
                              "fsl,sec-v4.0-rtic";
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -77,25 +78,25 @@ crypto: crypto@300000 {
                 ranges = <0x0 0x6100 0xe00>;
 
                 rtic_a: rtic-a@0 {
-                        compatible = "fsl,sec-v4.1-rtic-memory",
+                        compatible = "fsl,sec-v5.0-rtic-memory",
                                      "fsl,sec-v4.0-rtic-memory";
                         reg = <0x00 0x20 0x100 0x80>;
                 };
 
                 rtic_b: rtic-b@20 {
-                        compatible = "fsl,sec-v4.1-rtic-memory",
+                        compatible = "fsl,sec-v5.0-rtic-memory",
                                      "fsl,sec-v4.0-rtic-memory";
                         reg = <0x20 0x20 0x200 0x80>;
                 };
 
                 rtic_c: rtic-c@40 {
-                        compatible = "fsl,sec-v4.1-rtic-memory",
+                        compatible = "fsl,sec-v5.0-rtic-memory",
                                      "fsl,sec-v4.0-rtic-memory";
                         reg = <0x40 0x20 0x300 0x80>;
                 };
 
                 rtic_d: rtic-d@60 {
-                        compatible = "fsl,sec-v4.1-rtic-memory",
+                        compatible = "fsl,sec-v5.0-rtic-memory",
                                      "fsl,sec-v4.0-rtic-memory";
                         reg = <0x60 0x20 0x500 0x80>;
                 };
@@ -103,7 +104,7 @@ crypto: crypto@300000 {
 };
 
 sec_mon: sec_mon@314000 {
-        compatible = "fsl,sec-v4.1-mon", "fsl,sec-v4.0-mon";
+        compatible = "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
         reg = <0x314000 0x1000>;
         interrupts = <93 2 0 0>;
 };
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi
index 7b2ab8a8c1f4..33ff09d52e05 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi
@@ -34,6 +34,7 @@
 
 crypto: crypto@300000 {
         compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
+        fsl,sec-era = <5>;
         #address-cells = <1>;
         #size-cells = <1>;
         reg              = <0x300000 0x10000>;
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec5.3-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec5.3-0.dtsi
new file mode 100644
index 000000000000..08778221c194
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec5.3-0.dtsi
@@ -0,0 +1,119 @@
+/*
+ * QorIQ Sec/Crypto 5.3 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+crypto: crypto@300000 {
+        compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
+        fsl,sec-era = <4>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        reg              = <0x300000 0x10000>;
+        ranges           = <0 0x300000 0x10000>;
+        interrupts       = <92 2 0 0>;
+
+        sec_jr0: jr@1000 {
+                compatible = "fsl,sec-v5.3-job-ring",
+                             "fsl,sec-v5.0-job-ring",
+                             "fsl,sec-v4.0-job-ring";
+                reg = <0x1000 0x1000>;
+                interrupts = <88 2 0 0>;
+        };
+
+        sec_jr1: jr@2000 {
+                compatible = "fsl,sec-v5.3-job-ring",
+                             "fsl,sec-v5.0-job-ring",
+                             "fsl,sec-v4.0-job-ring";
+                reg = <0x2000 0x1000>;
+                interrupts = <89 2 0 0>;
+        };
+
+        sec_jr2: jr@3000 {
+                compatible = "fsl,sec-v5.3-job-ring",
+                             "fsl,sec-v5.0-job-ring",
+                             "fsl,sec-v4.0-job-ring";
+                reg = <0x3000 0x1000>;
+                interrupts = <90 2 0 0>;
+        };
+
+        sec_jr3: jr@4000 {
+                compatible = "fsl,sec-v5.3-job-ring",
+                             "fsl,sec-v5.0-job-ring",
+                             "fsl,sec-v4.0-job-ring";
+                reg = <0x4000 0x1000>;
+                interrupts = <91 2 0 0>;
+        };
+
+        rtic@6000 {
+                compatible = "fsl,sec-v5.3-rtic",
+                             "fsl,sec-v5.0-rtic",
+                             "fsl,sec-v4.0-rtic";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x6000 0x100>;
+                ranges = <0x0 0x6100 0xe00>;
+
+                rtic_a: rtic-a@0 {
+                        compatible = "fsl,sec-v5.3-rtic-memory",
+                                     "fsl,sec-v5.0-rtic-memory",
+                                     "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x00 0x20 0x100 0x80>;
+                };
+
+                rtic_b: rtic-b@20 {
+                        compatible = "fsl,sec-v5.3-rtic-memory",
+                                     "fsl,sec-v5.0-rtic-memory",
+                                     "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x20 0x20 0x200 0x80>;
+                };
+
+                rtic_c: rtic-c@40 {
+                        compatible = "fsl,sec-v5.3-rtic-memory",
+                                     "fsl,sec-v5.0-rtic-memory",
+                                     "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x40 0x20 0x300 0x80>;
+                };
+
+                rtic_d: rtic-d@60 {
+                        compatible = "fsl,sec-v5.3-rtic-memory",
+                                     "fsl,sec-v5.0-rtic-memory",
+                                     "fsl,sec-v4.0-rtic-memory";
+                        reg = <0x60 0x20 0x500 0x80>;
+                };
+        };
+};
+
+sec_mon: sec_mon@314000 {
+        compatible = "fsl,sec-v5.3-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
+        reg = <0x314000 0x1000>;
+        interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
new file mode 100644
index 000000000000..bd611a9cad32
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -0,0 +1,442 @@
+/*
+ * T4240 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&ifc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        compatible = "fsl,ifc", "simple-bus";
+        interrupts = <25 2 0 0>;
+};
+
+/* controller at 0x240000 */
+&pci0 {
+        compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        interrupts = <20 2 0 0>;
+        pcie@0 {
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                reg = <0 0 0 0 0>;
+                interrupts = <20 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 40 1 0 0
+                        0000 0 0 2 &mpic 1 1 0 0
+                        0000 0 0 3 &mpic 2 1 0 0
+                        0000 0 0 4 &mpic 3 1 0 0
+                        >;
+        };
+};
+
+/* controller at 0x250000 */
+&pci1 {
+        compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0 0xff>;
+        interrupts = <21 2 0 0>;
+        pcie@0 {
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                reg = <0 0 0 0 0>;
+                interrupts = <21 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 41 1 0 0
+                        0000 0 0 2 &mpic 5 1 0 0
+                        0000 0 0 3 &mpic 6 1 0 0
+                        0000 0 0 4 &mpic 7 1 0 0
+                        >;
+        };
+};
+
+/* controller at 0x260000 */
+&pci2 {
+        compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        interrupts = <22 2 0 0>;
+        pcie@0 {
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                reg = <0 0 0 0 0>;
+                interrupts = <22 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 42 1 0 0
+                        0000 0 0 2 &mpic 9 1 0 0
+                        0000 0 0 3 &mpic 10 1 0 0
+                        0000 0 0 4 &mpic 11 1 0 0
+                        >;
+        };
+};
+
+/* controller at 0x270000 */
+&pci3 {
+        compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
+        device_type = "pci";
+        #size-cells = <2>;
+        #address-cells = <3>;
+        bus-range = <0x0 0xff>;
+        interrupts = <23 2 0 0>;
+        pcie@0 {
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                reg = <0 0 0 0 0>;
+                interrupts = <23 2 0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 43 1 0 0
+                        0000 0 0 2 &mpic 0 1 0 0
+                        0000 0 0 3 &mpic 4 1 0 0
+                        0000 0 0 4 &mpic 8 1 0 0
+                        >;
+        };
+};
+
+&rio {
+        compatible = "fsl,srio";
+        interrupts = <16 2 1 11>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges;
+
+        port1 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                cell-index = <1>;
+        };
+
+        port2 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                cell-index = <2>;
+        };
+};
+
+&dcsr {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "fsl,dcsr", "simple-bus";
+
+        dcsr-epu@0 {
+                compatible = "fsl,t4240-dcsr-epu", "fsl,dcsr-epu";
+                interrupts = <52 2 0 0
+                              84 2 0 0
+                              85 2 0 0
+                              94 2 0 0
+                              95 2 0 0>;
+                reg = <0x0 0x1000>;
+        };
+        dcsr-npc {
+                compatible = "fsl,t4240-dcsr-cnpc", "fsl,dcsr-cnpc";
+                reg = <0x1000 0x1000 0x1002000 0x10000>;
+        };
+        dcsr-nxc@2000 {
+                compatible = "fsl,dcsr-nxc";
+                reg = <0x2000 0x1000>;
+        };
+        dcsr-corenet {
+                compatible = "fsl,dcsr-corenet";
+                reg = <0x8000 0x1000 0x1A000 0x1000>;
+        };
+        dcsr-dpaa@9000 {
+                compatible = "fsl,t4240-dcsr-dpaa", "fsl,dcsr-dpaa";
+                reg = <0x9000 0x1000>;
+        };
+        dcsr-ocn@11000 {
+                compatible = "fsl,t4240-dcsr-ocn", "fsl,dcsr-ocn";
+                reg = <0x11000 0x1000>;
+        };
+        dcsr-ddr@12000 {
+                compatible = "fsl,dcsr-ddr";
+                dev-handle = <&ddr1>;
+                reg = <0x12000 0x1000>;
+        };
+        dcsr-ddr@13000 {
+                compatible = "fsl,dcsr-ddr";
+                dev-handle = <&ddr2>;
+                reg = <0x13000 0x1000>;
+        };
+        dcsr-ddr@14000 {
+                compatible = "fsl,dcsr-ddr";
+                dev-handle = <&ddr3>;
+                reg = <0x14000 0x1000>;
+        };
+        dcsr-nal@18000 {
+                compatible = "fsl,t4240-dcsr-nal", "fsl,dcsr-nal";
+                reg = <0x18000 0x1000>;
+        };
+        dcsr-rcpm@22000 {
+                compatible = "fsl,t4240-dcsr-rcpm", "fsl,dcsr-rcpm";
+                reg = <0x22000 0x1000>;
+        };
+        dcsr-snpc@30000 {
+                compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc";
+                reg = <0x30000 0x1000 0x1022000 0x10000>;
+        };
+        dcsr-snpc@31000 {
+                compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc";
+                reg = <0x31000 0x1000 0x1042000 0x10000>;
+        };
+        dcsr-snpc@32000 {
+                compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc";
+                reg = <0x32000 0x1000 0x1062000 0x10000>;
+        };
+        dcsr-cpu-sb-proxy@100000 {
+                compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu0>;
+                reg = <0x100000 0x1000 0x101000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@108000 {
+                compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu1>;
+                reg = <0x108000 0x1000 0x109000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@110000 {
+                compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu2>;
+                reg = <0x110000 0x1000 0x111000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@118000 {
+                compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu3>;
+                reg = <0x118000 0x1000 0x119000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@120000 {
+                compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu4>;
+                reg = <0x120000 0x1000 0x121000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@128000 {
+                compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu5>;
+                reg = <0x128000 0x1000 0x129000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@130000 {
+                compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu6>;
+                reg = <0x130000 0x1000 0x131000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@138000 {
+                compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu7>;
+                reg = <0x138000 0x1000 0x139000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@140000 {
+                compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu8>;
+                reg = <0x140000 0x1000 0x141000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@148000 {
+                compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu9>;
+                reg = <0x148000 0x1000 0x149000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@150000 {
+                compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu10>;
+                reg = <0x150000 0x1000 0x151000 0x1000>;
+        };
+        dcsr-cpu-sb-proxy@158000 {
+                compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+                cpu-handle = <&cpu11>;
+                reg = <0x158000 0x1000 0x159000 0x1000>;
+        };
+};
+
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "simple-bus";
+
+        soc-sram-error {
+                compatible = "fsl,soc-sram-error";
+                interrupts = <16 2 1 29>;
+        };
+
+        corenet-law@0 {
+                compatible = "fsl,corenet-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <32>;
+        };
+
+        ddr1: memory-controller@8000 {
+                compatible = "fsl,qoriq-memory-controller-v4.7",
+                                "fsl,qoriq-memory-controller";
+                reg = <0x8000 0x1000>;
+                interrupts = <16 2 1 23>;
+        };
+
+        ddr2: memory-controller@9000 {
+                compatible = "fsl,qoriq-memory-controller-v4.7",
+                                "fsl,qoriq-memory-controller";
+                reg = <0x9000 0x1000>;
+                interrupts = <16 2 1 22>;
+        };
+
+        ddr3: memory-controller@a000 {
+                compatible = "fsl,qoriq-memory-controller-v4.7",
+                                "fsl,qoriq-memory-controller";
+                reg = <0xa000 0x1000>;
+                interrupts = <16 2 1 21>;
+        };
+
+        cpc: l3-cache-controller@10000 {
+                compatible = "fsl,t4240-l3-cache-controller", "cache";
+                reg = <0x10000 0x1000
+                       0x11000 0x1000
+                       0x12000 0x1000>;
+                interrupts = <16 2 1 27
+                              16 2 1 26
+                              16 2 1 25>;
+        };
+
+        corenet-cf@18000 {
+                compatible = "fsl,corenet-cf";
+                reg = <0x18000 0x1000>;
+                interrupts = <16 2 1 31>;
+                fsl,ccf-num-csdids = <32>;
+                fsl,ccf-num-snoopids = <32>;
+        };
+
+        iommu@20000 {
+                compatible = "fsl,pamu-v1.0", "fsl,pamu";
+                reg = <0x20000 0x6000>;
+                interrupts = <
+                        24 2 0 0
+                        16 2 1 30>;
+        };
+
+/include/ "qoriq-mpic.dtsi"
+
+        guts: global-utilities@e0000 {
+                compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0";
+                reg = <0xe0000 0xe00>;
+                fsl,has-rstcr;
+                fsl,liodn-bits = <12>;
+        };
+
+        clockgen: global-utilities@e1000 {
+                compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
+                reg = <0xe1000 0x1000>;
+        };
+
+        rcpm: global-utilities@e2000 {
+                compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
+                reg = <0xe2000 0x1000>;
+        };
+
+        sfp: sfp@e8000 {
+                compatible = "fsl,t4240-sfp";
+                reg        = <0xe8000 0x1000>;
+        };
+
+        serdes: serdes@ea000 {
+                compatible = "fsl,t4240-serdes";
+                reg        = <0xea000 0x4000>;
+        };
+
+/include/ "qoriq-dma-0.dtsi"
+/include/ "qoriq-dma-1.dtsi"
+
+/include/ "qoriq-espi-0.dtsi"
+        spi@110000 {
+                fsl,espi-num-chipselects = <4>;
+        };
+
+/include/ "qoriq-esdhc-0.dtsi"
+        sdhc@114000 {
+                compatible = "fsl,t4240-esdhc", "fsl,esdhc";
+                sdhci,auto-cmd12;
+        };
+/include/ "qoriq-i2c-0.dtsi"
+/include/ "qoriq-i2c-1.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-gpio-1.dtsi"
+/include/ "qoriq-gpio-2.dtsi"
+/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-usb2-mph-0.dtsi"
+                usb0: usb@210000 {
+                        compatible = "fsl-usb2-mph-v2.4", "fsl-usb2-mph";
+                        phy_type = "utmi";
+                        port0;
+                };
+/include/ "qoriq-usb2-dr-0.dtsi"
+                usb1: usb@211000 {
+                        compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
+                        dr_mode = "host";
+                        phy_type = "utmi";
+                };
+/include/ "qoriq-sata2-0.dtsi"
+/include/ "qoriq-sata2-1.dtsi"
+/include/ "qoriq-sec5.0-0.dtsi"
+
+        L2_1: l2-cache-controller@c20000 {
+                compatible = "fsl,t4240-l2-cache-controller";
+                reg = <0xc20000 0x40000>;
+                next-level-cache = <&cpc>;
+        };
+        L2_2: l2-cache-controller@c60000 {
+                compatible = "fsl,t4240-l2-cache-controller";
+                reg = <0xc60000 0x40000>;
+                next-level-cache = <&cpc>;
+        };
+        L2_3: l2-cache-controller@ca0000 {
+                compatible = "fsl,t4240-l2-cache-controller";
+                reg = <0xca0000 0x40000>;
+                next-level-cache = <&cpc>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
new file mode 100644
index 000000000000..a93c55a88560
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
@@ -0,0 +1,128 @@
+/*
+ * T4240 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/include/ "e6500_power_isa.dtsi"
+
+/ {
+        compatible = "fsl,T4240";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+
+        aliases {
+                ccsr = &soc;
+                dcsr = &dcsr;
+
+                serial0 = &serial0;
+                serial1 = &serial1;
+                serial2 = &serial2;
+                serial3 = &serial3;
+                crypto = &crypto;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+                pci3 = &pci3;
+                dma0 = &dma0;
+                dma1 = &dma1;
+                sdhc = &sdhc;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: PowerPC,e6500@0 {
+                        device_type = "cpu";
+                        reg = <0 1>;
+                        next-level-cache = <&L2_1>;
+                };
+                cpu1: PowerPC,e6500@2 {
+                        device_type = "cpu";
+                        reg = <2 3>;
+                        next-level-cache = <&L2_1>;
+                };
+                cpu2: PowerPC,e6500@4 {
+                        device_type = "cpu";
+                        reg = <4 5>;
+                        next-level-cache = <&L2_1>;
+                };
+                cpu3: PowerPC,e6500@6 {
+                        device_type = "cpu";
+                        reg = <6 7>;
+                        next-level-cache = <&L2_1>;
+                };
+                cpu4: PowerPC,e6500@8 {
+                        device_type = "cpu";
+                        reg = <8 9>;
+                        next-level-cache = <&L2_2>;
+                };
+                cpu5: PowerPC,e6500@10 {
+                        device_type = "cpu";
+                        reg = <10 11>;
+                        next-level-cache = <&L2_2>;
+                };
+                cpu6: PowerPC,e6500@12 {
+                        device_type = "cpu";
+                        reg = <12 13>;
+                        next-level-cache = <&L2_2>;
+                };
+                cpu7: PowerPC,e6500@14 {
+                        device_type = "cpu";
+                        reg = <14 15>;
+                        next-level-cache = <&L2_2>;
+                };
+                cpu8: PowerPC,e6500@16 {
+                        device_type = "cpu";
+                        reg = <16 17>;
+                        next-level-cache = <&L2_3>;
+                };
+                cpu9: PowerPC,e6500@18 {
+                        device_type = "cpu";
+                        reg = <18 19>;
+                        next-level-cache = <&L2_3>;
+                };
+                cpu10: PowerPC,e6500@20 {
+                        device_type = "cpu";
+                        reg = <20 21>;
+                        next-level-cache = <&L2_3>;
+                };
+                cpu11: PowerPC,e6500@22 {
+                        device_type = "cpu";
+                        reg = <22 23>;
+                        next-level-cache = <&L2_3>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
index 723e292b6b4e..bd14c00e5146 100644
--- a/arch/powerpc/boot/dts/mpc5121.dtsi
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -152,6 +152,8 @@
                         compatible = "fsl,mpc5121-sdhc";
                         reg = <0x1500 0x100>;
                         interrupts = <8 0x8>;
+                        dmas = <&dma0 30>;
+                        dma-names = "rx-tx";
                 };
 
                 i2c@1700 {
@@ -384,7 +386,7 @@
                         interrupts = <40 0x8>;
                 };
 
-                dma@14000 {
+                dma0: dma@14000 {
                         compatible = "fsl,mpc5121-dma";
                         reg = <0x14000 0x1800>;
                         interrupts = <65 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
index f269b1382ef7..7d3cb79185cb 100644
--- a/arch/powerpc/boot/dts/mpc5121ads.dts
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -13,7 +13,7 @@
 
 / {
         model = "mpc5121ads";
-        compatible = "fsl,mpc5121ads";
+        compatible = "fsl,mpc5121ads", "fsl,mpc5121";
 
         nfc@40000000 {
                 /*
diff --git a/arch/powerpc/boot/dts/mpc5125twr.dts b/arch/powerpc/boot/dts/mpc5125twr.dts
new file mode 100644
index 000000000000..4177b62240c2
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc5125twr.dts
@@ -0,0 +1,233 @@
+/*
+ * STx/Freescale ADS5125 MPC5125 silicon
+ *
+ * Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved.
+ *
+ * Reworked by Matteo Facchinetti (engineering@sirius-es.it)
+ * Copyright (C) 2013 Sirius Electronic Systems
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+        model = "mpc5125twr"; // In BSP "mpc5125ads"
+        compatible = "fsl,mpc5125ads", "fsl,mpc5125";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        interrupt-parent = <&ipic>;
+
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+                ethernet0 = &eth0;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,5125@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        d-cache-line-size = <0x20>;     // 32 bytes
+                        i-cache-line-size = <0x20>;     // 32 bytes
+                        d-cache-size = <0x8000>;        // L1, 32K
+                        i-cache-size = <0x8000>;        // L1, 32K
+                        timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
+                        bus-frequency = <198000000>;    // 198 MHz csb bus
+                        clock-frequency = <396000000>;  // 396 MHz ppc core
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;  // 256MB at 0
+        };
+
+        sram@30000000 {
+                compatible = "fsl,mpc5121-sram";
+                reg = <0x30000000 0x08000>;             // 32K at 0x30000000
+        };
+
+        soc@80000000 {
+                compatible = "fsl,mpc5121-immr";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                #interrupt-cells = <2>;
+                ranges = <0x0 0x80000000 0x400000>;
+                reg = <0x80000000 0x400000>;
+                bus-frequency = <66000000>;     // 66 MHz ips bus
+
+                // IPIC
+                // interrupts cell = <intr #, sense>
+                // sense values match linux IORESOURCE_IRQ_* defines:
+                // sense == 8: Level, low assertion
+                // sense == 2: Edge, high-to-low change
+                //
+                ipic: interrupt-controller@c00 {
+                        compatible = "fsl,mpc5121-ipic", "fsl,ipic";
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0xc00 0x100>;
+                };
+
+                rtc@a00 {       // Real time clock
+                        compatible = "fsl,mpc5121-rtc";
+                        reg = <0xa00 0x100>;
+                        interrupts = <79 0x8 80 0x8>;
+                };
+
+                reset@e00 {     // Reset module
+                        compatible = "fsl,mpc5125-reset";
+                        reg = <0xe00 0x100>;
+                };
+
+                clock@f00 {     // Clock control
+                        compatible = "fsl,mpc5121-clock";
+                        reg = <0xf00 0x100>;
+                };
+
+                pmc@1000{  // Power Management Controller
+                        compatible = "fsl,mpc5121-pmc";
+                        reg = <0x1000 0x100>;
+                        interrupts = <83 0x2>;
+                };
+
+                gpio0: gpio@1100 {
+                        compatible = "fsl,mpc5125-gpio";
+                        reg = <0x1100 0x080>;
+                        interrupts = <78 0x8>;
+                };
+
+                gpio1: gpio@1180 {
+                        compatible = "fsl,mpc5125-gpio";
+                        reg = <0x1180 0x080>;
+                        interrupts = <86 0x8>;
+                };
+
+                can@1300 { // CAN rev.2
+                        compatible = "fsl,mpc5121-mscan";
+                        interrupts = <12 0x8>;
+                        reg = <0x1300 0x80>;
+                };
+
+                can@1380 {
+                        compatible = "fsl,mpc5121-mscan";
+                        interrupts = <13 0x8>;
+                        reg = <0x1380 0x80>;
+                };
+
+                sdhc@1500 {
+                        compatible = "fsl,mpc5121-sdhc";
+                        interrupts = <8 0x8>;
+                        reg = <0x1500 0x100>;
+                };
+
+                i2c@1700 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,mpc5121-i2c", "fsl-i2c";
+                        reg = <0x1700 0x20>;
+                        interrupts = <0x9 0x8>;
+                };
+
+                i2c@1720 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,mpc5121-i2c", "fsl-i2c";
+                        reg = <0x1720 0x20>;
+                        interrupts = <0xa 0x8>;
+                };
+
+                i2c@1740 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,mpc5121-i2c", "fsl-i2c";
+                        reg = <0x1740 0x20>;
+                        interrupts = <0xb 0x8>;
+                };
+
+                i2ccontrol@1760 {
+                        compatible = "fsl,mpc5121-i2c-ctrl";
+                        reg = <0x1760 0x8>;
+                };
+
+                diu@2100 {
+                        compatible = "fsl,mpc5121-diu";
+                        reg = <0x2100 0x100>;
+                        interrupts = <64 0x8>;
+                };
+
+                mdio@2800 {
+                        compatible = "fsl,mpc5121-fec-mdio";
+                        reg = <0x2800 0x800>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        phy0: ethernet-phy@0 {
+                                reg = <1>;
+                        };
+                };
+
+                eth0: ethernet@2800 {
+                        compatible = "fsl,mpc5125-fec";
+                        reg = <0x2800 0x800>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <4 0x8>;
+                        phy-handle = < &phy0 >;
+                        phy-connection-type = "rmii";
+                };
+
+                // IO control
+                ioctl@a000 {
+                        compatible = "fsl,mpc5125-ioctl";
+                        reg = <0xA000 0x1000>;
+                };
+
+                usb@3000 {
+                        compatible = "fsl,mpc5121-usb2-dr";
+                        reg = <0x3000 0x400>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <43 0x8>;
+                        dr_mode = "host";
+                        phy_type = "ulpi";
+                };
+
+                // 5125 PSCs are not 52xx or 5121 PSC compatible
+                // PSC1 uart0 aka ttyPSC0
+                serial@11100 {
+                        compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
+                        reg = <0x11100 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+                };
+
+                // PSC9 uart1 aka ttyPSC1
+                serial@11900 {
+                        compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
+                        reg = <0x11900 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+                };
+
+                pscfifo@11f00 {
+                        compatible = "fsl,mpc5121-psc-fifo";
+                        reg = <0x11f00 0x100>;
+                        interrupts = <40 0x8>;
+                };
+
+                dma@14000 {
+                        compatible = "fsl,mpc5121-dma"; // BSP name: "mpc512x-dma2"
+                        reg = <0x14000 0x1800>;
+                        interrupts = <65 0x8>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/mpc8536ds_36b.dts b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
index f8a3b3413176..6c723ee108cd 100644
--- a/arch/powerpc/boot/dts/mpc8536ds_36b.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
@@ -32,7 +32,7 @@
                 reg = <0 0 0 0>;        // Filled by U-Boot
         };
 
-        lbc: localbus@ffe05000 {
+        lbc: localbus@fffe05000 {
                 reg = <0xf 0xffe05000 0 0x1000>;
 
                 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
@@ -44,7 +44,7 @@
                 ranges = <0x0 0xf 0xffe00000 0x100000>;
         };
 
-        pci0: pci@ffe08000 {
+        pci0: pci@fffe08000 {
                 reg = <0xf 0xffe08000 0 0x1000>;
                 ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000
                           0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>;
@@ -59,7 +59,7 @@
                         0x8800 0 0 4 &mpic 4 1 0 0>;
         };
 
-        pci1: pcie@ffe09000 {
+        pci1: pcie@fffe09000 {
                 reg = <0xf 0xffe09000 0 0x1000>;
                 ranges = <0x02000000 0 0xf8000000 0xc 0x18000000 0 0x08000000
                           0x01000000 0 0x00000000 0xf 0xffc20000 0 0x00010000>;
diff --git a/arch/powerpc/boot/dts/p1021rdb-pc.dtsi b/arch/powerpc/boot/dts/p1021rdb-pc.dtsi
index c13abfbbe2e2..d6274c58f496 100644
--- a/arch/powerpc/boot/dts/p1021rdb-pc.dtsi
+++ b/arch/powerpc/boot/dts/p1021rdb-pc.dtsi
@@ -62,11 +62,19 @@
                 };
 
                 partition@400000 {
-                        /* 11MB for JFFS2 based Root file System */
-                        reg = <0x00400000 0x00b00000>;
+                        /* 10.75MB for JFFS2 based Root file System */
+                        reg = <0x00400000 0x00ac0000>;
                         label = "NOR JFFS2 Root File System";
                 };
 
+                partition@ec0000 {
+                        /* This location must not be altered  */
+                        /* 256KB for QE ucode firmware*/
+                        reg = <0x00ec0000 0x00040000>;
+                        label = "NOR QE microcode firmware";
+                        read-only;
+                };
+
                 partition@f00000 {
                         /* This location must not be altered  */
                         /* 512KB for u-boot Bootloader Image */
diff --git a/arch/powerpc/boot/dts/p1025rdb_36b.dts b/arch/powerpc/boot/dts/p1025rdb_36b.dts
index 4ce4bfa0eda4..06deb6f341ba 100644
--- a/arch/powerpc/boot/dts/p1025rdb_36b.dts
+++ b/arch/powerpc/boot/dts/p1025rdb_36b.dts
@@ -82,6 +82,11 @@
                                   0x0 0x100000>;
                 };
         };
+
+        qe: qe@fffe80000 {
+                status = "disabled"; /* no firmware loaded */
+        };
+
 };
 
 /include/ "p1025rdb.dtsi"
diff --git a/arch/powerpc/boot/dts/pdm360ng.dts b/arch/powerpc/boot/dts/pdm360ng.dts
index 0b069477838a..74337403faee 100644
--- a/arch/powerpc/boot/dts/pdm360ng.dts
+++ b/arch/powerpc/boot/dts/pdm360ng.dts
@@ -17,7 +17,7 @@
 
 / {
         model = "pdm360ng";
-        compatible = "ifm,pdm360ng";
+        compatible = "ifm,pdm360ng", "fsl,mpc5121";
         #address-cells = <1>;
         #size-cells = <1>;
         interrupt-parent = <&ipic>;
diff --git a/arch/powerpc/boot/dts/t4240qds.dts b/arch/powerpc/boot/dts/t4240qds.dts
new file mode 100644
index 000000000000..0555976dd0f3
--- /dev/null
+++ b/arch/powerpc/boot/dts/t4240qds.dts
@@ -0,0 +1,224 @@
+/*
+ * T4240QDS Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/t4240si-pre.dtsi"
+
+/ {
+        model = "fsl,T4240QDS";
+        compatible = "fsl,T4240QDS";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+
+        ifc: localbus@ffe124000 {
+                reg = <0xf 0xfe124000 0 0x2000>;
+                ranges = <0 0 0xf 0xe8000000 0x08000000
+                          2 0 0xf 0xff800000 0x00010000
+                          3 0 0xf 0xffdf0000 0x00008000>;
+
+                nor@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x0 0x0 0x8000000>;
+
+                        bank-width = <2>;
+                        device-width = <1>;
+                };
+
+                nand@2,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,ifc-nand";
+                        reg = <0x2 0x0 0x10000>;
+
+                        partition@0 {
+                                /* This location must not be altered  */
+                                /* 1MB for u-boot Bootloader Image */
+                                reg = <0x0 0x00100000>;
+                                label = "NAND U-Boot Image";
+                                read-only;
+                        };
+
+                        partition@100000 {
+                                /* 1MB for DTB Image */
+                                reg = <0x00100000 0x00100000>;
+                                label = "NAND DTB Image";
+                        };
+
+                        partition@200000 {
+                                /* 10MB for Linux Kernel Image */
+                                reg = <0x00200000 0x00A00000>;
+                                label = "NAND Linux Kernel Image";
+                        };
+
+                        partition@C00000 {
+                                /* 500MB for Root file System Image */
+                                reg = <0x00c00000 0x1F400000>;
+                                label = "NAND RFS Image";
+                        };
+                };
+
+                board-control@3,0 {
+                        compatible = "fsl,t4240qds-fpga", "fsl,fpga-qixis";
+                        reg = <3 0 0x300>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+        };
+
+        dcsr: dcsr@f00000000 {
+                ranges = <0x00000000 0xf 0x00000000 0x01072000>;
+        };
+
+        soc: soc@ffe000000 {
+                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+                reg = <0xf 0xfe000000 0 0x00001000>;
+                spi@110000 {
+                        flash@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "sst,sst25wf040";
+                                reg = <0>;
+                                spi-max-frequency = <40000000>; /* input clock */
+                        };
+                };
+
+                i2c@118000 {
+                        eeprom@51 {
+                                compatible = "at24,24c256";
+                                reg = <0x51>;
+                        };
+                        eeprom@52 {
+                                compatible = "at24,24c256";
+                                reg = <0x52>;
+                        };
+                        eeprom@53 {
+                                compatible = "at24,24c256";
+                                reg = <0x53>;
+                        };
+                        eeprom@54 {
+                                compatible = "at24,24c256";
+                                reg = <0x54>;
+                        };
+                        eeprom@55 {
+                                compatible = "at24,24c256";
+                                reg = <0x55>;
+                        };
+                        eeprom@56 {
+                                compatible = "at24,24c256";
+                                reg = <0x56>;
+                        };
+                        rtc@68 {
+                                compatible = "dallas,ds3232";
+                                reg = <0x68>;
+                                interrupts = <0x1 0x1 0 0>;
+                        };
+                };
+        };
+
+        pci0: pcie@ffe240000 {
+                reg = <0xf 0xfe240000 0 0x10000>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+                          0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x20000000
+
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+
+        pci1: pcie@ffe250000 {
+                reg = <0xf 0xfe250000 0 0x10000>;
+                ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+                          0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x20000000
+
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+
+        pci2: pcie@ffe260000 {
+                reg = <0xf 0xfe260000 0 0x1000>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
+                          0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x20000000
+
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+
+        pci3: pcie@ffe270000 {
+                reg = <0xf 0xfe270000 0 0x10000>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
+                          0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x20000000
+
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+        rio: rapidio@ffe0c0000 {
+                reg = <0xf 0xfe0c0000 0 0x11000>;
+
+                port1 {
+                        ranges = <0 0 0xc 0x20000000 0 0x10000000>;
+                };
+                port2 {
+                        ranges = <0 0 0xc 0x30000000 0 0x10000000>;
+                };
+        };
+};
+
+/include/ "fsl/t4240si-post.dtsi"
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 3d139fa04050..6c8b020806ff 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -1,14 +1,13 @@
 CONFIG_PPC64=y
 CONFIG_PPC_BOOK3E_64=y
-# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set
+CONFIG_ALTIVEC=y
 CONFIG_SMP=y
-CONFIG_NR_CPUS=2
-CONFIG_EXPERIMENTAL=y
+CONFIG_NR_CPUS=24
 CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_IRQ_DOMAIN_DEBUG=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -22,10 +21,13 @@ CONFIG_MODVERSIONS=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_MAC_PARTITION=y
+CONFIG_B4_QDS=y
 CONFIG_P5020_DS=y
 CONFIG_P5040_DS=y
+CONFIG_T4240_QDS=y
 # CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
 CONFIG_BINFMT_MISC=m
+CONFIG_FSL_IFC=y
 CONFIG_PCIEPORTBUS=y
 CONFIG_PCI_MSI=y
 CONFIG_RAPIDIO=y
@@ -58,16 +60,33 @@ CONFIG_IP_SCTP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
+CONFIG_FTL=y
 CONFIG_MTD_CFI=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_NAND_ECC=y
 CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_IDS=y
 CONFIG_MTD_NAND_FSL_ELBC=y
 CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
@@ -78,6 +97,7 @@ CONFIG_SATA_FSL=y
 CONFIG_SATA_SIL24=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
+CONFIG_E1000E=y
 CONFIG_INPUT_FF_MEMLESS=m
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_KEYBOARD is not set
@@ -121,7 +141,16 @@ CONFIG_NTFS_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_HUGETLBFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_MISC_FILESYSTEMS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=1
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
@@ -129,6 +158,12 @@ CONFIG_NFSD=m
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_UTF8=m
 CONFIG_CRC_T10DIF=y
+CONFIG_CRC16=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
 CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
@@ -140,6 +175,5 @@ CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_MD4=y
 CONFIG_CRYPTO_SHA256=y
 CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_AES=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_DEV_FSL_CAAM=y
diff --git a/arch/powerpc/configs/mpc512x_defconfig b/arch/powerpc/configs/mpc512x_defconfig
index 211fcc9ed700..0d0d981442fd 100644
--- a/arch/powerpc/configs/mpc512x_defconfig
+++ b/arch/powerpc/configs/mpc512x_defconfig
@@ -13,7 +13,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_PPC_CHRP is not set
 CONFIG_PPC_MPC512x=y
 CONFIG_MPC5121_ADS=y
-CONFIG_MPC5121_GENERIC=y
+CONFIG_MPC512x_GENERIC=y
 CONFIG_PDM360NG=y
 # CONFIG_PPC_PMAC is not set
 CONFIG_NO_HZ=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index cf815e847cdc..5a58882e351e 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -1,13 +1,12 @@
 CONFIG_PPC_85xx=y
 CONFIG_PHYS_64BIT=y
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_AUDIT=y
 CONFIG_IRQ_DOMAIN_DEBUG=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -48,6 +47,7 @@ CONFIG_HIGHMEM=y
 CONFIG_BINFMT_MISC=m
 CONFIG_MATH_EMULATION=y
 CONFIG_FORCE_MAX_ZONEORDER=12
+CONFIG_FSL_IFC=y
 CONFIG_PCI=y
 CONFIG_PCI_MSI=y
 CONFIG_RAPIDIO=y
@@ -79,18 +79,33 @@ CONFIG_IP_SCTP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 CONFIG_FTL=y
 CONFIG_MTD_CFI=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_NAND_ECC=y
 CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_IDS=y
 CONFIG_MTD_NAND_FSL_ELBC=y
 CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_NBD=y
@@ -106,6 +121,7 @@ CONFIG_SCSI_LOGGING=y
 CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
 CONFIG_SATA_FSL=y
+CONFIG_SATA_SIL24=y
 CONFIG_PATA_ALI=y
 CONFIG_PATA_VIA=y
 CONFIG_NETDEVICES=y
@@ -113,6 +129,9 @@ CONFIG_DUMMY=y
 CONFIG_FS_ENET=y
 CONFIG_UCC_GETH=y
 CONFIG_GIANFAR=y
+CONFIG_E1000=y
+CONFIG_E1000E=y
+CONFIG_IGB=y
 CONFIG_MARVELL_PHY=y
 CONFIG_DAVICOM_PHY=y
 CONFIG_CICADA_PHY=y
@@ -132,7 +151,6 @@ CONFIG_SERIAL_8250_DETECT_IRQ=y
 CONFIG_SERIAL_8250_RSA=y
 CONFIG_SERIAL_QE=m
 CONFIG_NVRAM=y
-CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_CPM=m
 CONFIG_I2C_MPC=y
@@ -206,6 +224,15 @@ CONFIG_NTFS_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_HUGETLBFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=1
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
 CONFIG_ADFS_FS=m
 CONFIG_AFFS_FS=m
 CONFIG_HFS_FS=m
@@ -224,13 +251,18 @@ CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=y
 CONFIG_CRC_T10DIF=y
+CONFIG_CRC16=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
 CONFIG_DEBUG_FS=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_SHA256=y
 CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_AES=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_DEV_FSL_CAAM=y
 CONFIG_CRYPTO_DEV_TALITOS=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 8d00ea5b8a9f..165e6b32baef 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -50,6 +50,7 @@ CONFIG_HIGHMEM=y
 CONFIG_BINFMT_MISC=m
 CONFIG_MATH_EMULATION=y
 CONFIG_FORCE_MAX_ZONEORDER=12
+CONFIG_FSL_IFC=y
 CONFIG_PCI=y
 CONFIG_PCI_MSI=y
 CONFIG_RAPIDIO=y
@@ -81,18 +82,33 @@ CONFIG_IP_SCTP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 CONFIG_FTL=y
 CONFIG_MTD_CFI=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_NAND_ECC=y
 CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_IDS=y
 CONFIG_MTD_NAND_FSL_ELBC=y
 CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_NBD=y
@@ -108,6 +124,7 @@ CONFIG_SCSI_LOGGING=y
 CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
 CONFIG_SATA_FSL=y
+CONFIG_SATA_SIL24=y
 CONFIG_PATA_ALI=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
@@ -207,6 +224,15 @@ CONFIG_NTFS_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_HUGETLBFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=1
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
 CONFIG_ADFS_FS=m
 CONFIG_AFFS_FS=m
 CONFIG_HFS_FS=m
@@ -225,6 +251,12 @@ CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=y
 CONFIG_CRC_T10DIF=y
+CONFIG_CRC16=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
 CONFIG_DEBUG_FS=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
diff --git a/arch/powerpc/configs/ps3_defconfig b/arch/powerpc/configs/ps3_defconfig
index 7a5c15fcc7cf..f79196232917 100644
--- a/arch/powerpc/configs/ps3_defconfig
+++ b/arch/powerpc/configs/ps3_defconfig
@@ -3,11 +3,11 @@ CONFIG_TUNE_CELL=y
 CONFIG_ALTIVEC=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_LZMA=y
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_EMBEDDED=y
 # CONFIG_PERF_EVENTS is not set
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
index 08bd299c75b1..910194e9a1e2 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -53,7 +53,7 @@
 #define smp_mb__after_clear_bit()       smp_mb()
 
 /* Macro for generating the ***_bits() functions */
-#define DEFINE_BITOP(fn, op, prefix, postfix)   \
+#define DEFINE_BITOP(fn, op, prefix)            \
 static __inline__ void fn(unsigned long mask,   \
                 volatile unsigned long *_p)     \
 {                                               \
@@ -66,16 +66,15 @@ static __inline__ void fn(unsigned long mask,	\
         PPC405_ERR77(0,%3)                      \
         PPC_STLCX "%0,0,%3\n"                   \
         "bne- 1b\n"                             \
-        postfix                                 \
         : "=&r" (old), "+m" (*p)                \
         : "r" (mask), "r" (p)                   \
         : "cc", "memory");                      \
 }
 
-DEFINE_BITOP(set_bits, or, "", "")
-DEFINE_BITOP(clear_bits, andc, "", "")
-DEFINE_BITOP(clear_bits_unlock, andc, PPC_RELEASE_BARRIER, "")
-DEFINE_BITOP(change_bits, xor, "", "")
+DEFINE_BITOP(set_bits, or, "")
+DEFINE_BITOP(clear_bits, andc, "")
+DEFINE_BITOP(clear_bits_unlock, andc, PPC_RELEASE_BARRIER)
+DEFINE_BITOP(change_bits, xor, "")
 
 static __inline__ void set_bit(int nr, volatile unsigned long *addr)
 {
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index fb3245e928ea..26807e5aff51 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -52,6 +52,7 @@ struct cpu_spec {
         char            *cpu_name;
         unsigned long   cpu_features;           /* Kernel features */
         unsigned int    cpu_user_features;      /* Userland features */
+        unsigned int    cpu_user_features2;     /* Userland features v2 */
         unsigned int    mmu_features;           /* MMU features */
 
         /* cache line sizes */
@@ -151,7 +152,7 @@ extern const char *powerpc_base_platform;
 #define CPU_FTR_HVMODE                  LONG_ASM_CONST(0x0000000100000000)
 #define CPU_FTR_ARCH_201                LONG_ASM_CONST(0x0000000200000000)
 #define CPU_FTR_ARCH_206                LONG_ASM_CONST(0x0000000400000000)
-#define CPU_FTR_CFAR                    LONG_ASM_CONST(0x0000000800000000)
+#define CPU_FTR_ARCH_207S               LONG_ASM_CONST(0x0000000800000000)
 #define CPU_FTR_IABR                    LONG_ASM_CONST(0x0000001000000000)
 #define CPU_FTR_MMCRA                   LONG_ASM_CONST(0x0000002000000000)
 #define CPU_FTR_CTRL                    LONG_ASM_CONST(0x0000004000000000)
@@ -172,7 +173,7 @@ extern const char *powerpc_base_platform;
 #define CPU_FTR_ICSWX                   LONG_ASM_CONST(0x0020000000000000)
 #define CPU_FTR_VMX_COPY                LONG_ASM_CONST(0x0040000000000000)
 #define CPU_FTR_TM                      LONG_ASM_CONST(0x0080000000000000)
-#define CPU_FTR_BCTAR                   LONG_ASM_CONST(0x0100000000000000)
+#define CPU_FTR_CFAR                    LONG_ASM_CONST(0x0100000000000000)
 #define CPU_FTR_HAS_PPR                 LONG_ASM_CONST(0x0200000000000000)
 #define CPU_FTR_DAWR                    LONG_ASM_CONST(0x0400000000000000)
 
@@ -223,8 +224,10 @@ extern const char *powerpc_base_platform;
 /* We only set the TM feature if the kernel was compiled with TM supprt */
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 #define CPU_FTR_TM_COMP         CPU_FTR_TM
+#define PPC_FEATURE2_HTM_COMP   PPC_FEATURE2_HTM
 #else
 #define CPU_FTR_TM_COMP         0
+#define PPC_FEATURE2_HTM_COMP   0
 #endif
 
 /* We need to mark all pages as being coherent if we're SMP or we have a
@@ -374,7 +377,7 @@ extern const char *powerpc_base_platform;
 #define CPU_FTRS_E6500  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
             CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
             CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
-            CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
+            CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP)
 #define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 
 /* 64-bit CPUs */
@@ -421,8 +424,8 @@ extern const char *powerpc_base_platform;
             CPU_FTR_DSCR | CPU_FTR_SAO  | \
             CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
             CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
-            CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | CPU_FTR_BCTAR | \
-            CPU_FTR_TM_COMP)
+            CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
+            CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP)
 #define CPU_FTRS_CELL   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
diff --git a/arch/powerpc/include/asm/dma.h b/arch/powerpc/include/asm/dma.h
index f6813e919bb2..a5c6d83b5f60 100644
--- a/arch/powerpc/include/asm/dma.h
+++ b/arch/powerpc/include/asm/dma.h
@@ -16,10 +16,6 @@
  *
  * None of this really applies for Power Macintoshes.  There is
  * basically just enough here to get kernel/dma.c to compile.
- *
- * There may be some comments or restrictions made here which are
- * not valid for the PReP platform.  Take what you read
- * with a grain of salt.
  */
 
 #include <asm/io.h>
@@ -57,7 +53,6 @@
  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
  *  - page registers for 0-3 use bit 0, represent 64K pages
  *
- * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.
  * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
  * Note that addresses loaded into registers must be _physical_ addresses,
  * not logical addresses (which may differ if paging is active).
diff --git a/arch/powerpc/include/asm/elf.h b/arch/powerpc/include/asm/elf.h
index ac9790fc3836..cc0655a702a7 100644
--- a/arch/powerpc/include/asm/elf.h
+++ b/arch/powerpc/include/asm/elf.h
@@ -61,6 +61,7 @@ typedef elf_vrregset_t elf_fpxregset_t;
    instruction set this cpu supports.  This could be done in userspace,
    but it's not easy, and we've already done it here.  */
 # define ELF_HWCAP      (cur_cpu_spec->cpu_user_features)
+# define ELF_HWCAP2     (cur_cpu_spec->cpu_user_features2)
 
 /* This yields a string that ld.so will use to load implementation
    specific libraries for optimization.  This is more specific in
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 05e6d2ee1db9..8e5fae8beaf6 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -414,7 +414,6 @@ label##_relon_hv:						\
 #define SOFTEN_NOTEST_HV(vec)           _SOFTEN_TEST(EXC_HV, vec)
 
 #define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra)              \
-        HMT_MEDIUM_PPR_DISCARD;                                         \
         SET_SCRATCH0(r13);    /* save r13 */                            \
         EXCEPTION_PROLOG_0(PACA_EXGEN);                                 \
         __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec);                   \
@@ -427,6 +426,7 @@ label##_relon_hv:						\
         . = loc;                                                        \
         .globl label##_pSeries;                                         \
 label##_pSeries:                                                        \
+        HMT_MEDIUM_PPR_DISCARD;                                         \
         _MASKABLE_EXCEPTION_PSERIES(vec, label,                         \
                                     EXC_STD, SOFTEN_TEST_PR)
 
diff --git a/arch/powerpc/include/asm/firmware.h b/arch/powerpc/include/asm/firmware.h
index 097dee57a7a9..0df54646f968 100644
--- a/arch/powerpc/include/asm/firmware.h
+++ b/arch/powerpc/include/asm/firmware.h
@@ -18,7 +18,6 @@
 #include <asm/feature-fixups.h>
 
 /* firmware feature bitmask values */
-#define FIRMWARE_MAX_FEATURES 63
 
 #define FW_FEATURE_PFT          ASM_CONST(0x0000000000000001)
 #define FW_FEATURE_TCE          ASM_CONST(0x0000000000000002)
@@ -51,6 +50,8 @@
 #define FW_FEATURE_OPALv2       ASM_CONST(0x0000000020000000)
 #define FW_FEATURE_SET_MODE     ASM_CONST(0x0000000040000000)
 #define FW_FEATURE_BEST_ENERGY  ASM_CONST(0x0000000080000000)
+#define FW_FEATURE_TYPE1_AFFINITY ASM_CONST(0x0000000100000000)
+#define FW_FEATURE_PRRN         ASM_CONST(0x0000000200000000)
 
 #ifndef __ASSEMBLY__
 
@@ -65,7 +66,8 @@ enum {
                 FW_FEATURE_BULK_REMOVE | FW_FEATURE_XDABR |
                 FW_FEATURE_MULTITCE | FW_FEATURE_SPLPAR | FW_FEATURE_LPAR |
                 FW_FEATURE_CMO | FW_FEATURE_VPHN | FW_FEATURE_XCMO |
-                FW_FEATURE_SET_MODE | FW_FEATURE_BEST_ENERGY,
+                FW_FEATURE_SET_MODE | FW_FEATURE_BEST_ENERGY |
+                FW_FEATURE_TYPE1_AFFINITY | FW_FEATURE_PRRN,
         FW_FEATURE_PSERIES_ALWAYS = 0,
         FW_FEATURE_POWERNV_POSSIBLE = FW_FEATURE_OPAL | FW_FEATURE_OPALv2,
         FW_FEATURE_POWERNV_ALWAYS = 0,
diff --git a/arch/powerpc/include/asm/hardirq.h b/arch/powerpc/include/asm/hardirq.h
index 3147a2970125..3bdcfce2c42a 100644
--- a/arch/powerpc/include/asm/hardirq.h
+++ b/arch/powerpc/include/asm/hardirq.h
@@ -10,6 +10,9 @@ typedef struct {
         unsigned int pmu_irqs;
         unsigned int mce_exceptions;
         unsigned int spurious_irqs;
+#ifdef CONFIG_PPC_DOORBELL
+        unsigned int doorbell_irqs;
+#endif
 } ____cacheline_aligned irq_cpustat_t;
 
 DECLARE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index 62e11a32c4c2..f2498c8e595d 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -3,9 +3,37 @@
 
 #ifdef CONFIG_HUGETLB_PAGE
 #include <asm/page.h>
+#include <asm-generic/hugetlb.h>
 
 extern struct kmem_cache *hugepte_cache;
 
+#ifdef CONFIG_PPC_BOOK3S_64
+/*
+ * This should work for other subarchs too. But right now we use the
+ * new format only for 64bit book3s
+ */
+static inline pte_t *hugepd_page(hugepd_t hpd)
+{
+        BUG_ON(!hugepd_ok(hpd));
+        /*
+         * We have only four bits to encode, MMU page size
+         */
+        BUILD_BUG_ON((MMU_PAGE_COUNT - 1) > 0xf);
+        return (pte_t *)(hpd.pd & ~HUGEPD_SHIFT_MASK);
+}
+
+static inline unsigned int hugepd_mmu_psize(hugepd_t hpd)
+{
+        return (hpd.pd & HUGEPD_SHIFT_MASK) >> 2;
+}
+
+static inline unsigned int hugepd_shift(hugepd_t hpd)
+{
+        return mmu_psize_to_shift(hugepd_mmu_psize(hpd));
+}
+
+#else
+
 static inline pte_t *hugepd_page(hugepd_t hpd)
 {
         BUG_ON(!hugepd_ok(hpd));
@@ -17,6 +45,9 @@ static inline unsigned int hugepd_shift(hugepd_t hpd)
         return hpd.pd & HUGEPD_SHIFT_MASK;
 }
 
+#endif /* CONFIG_PPC_BOOK3S_64 */
+
+
 static inline pte_t *hugepte_offset(hugepd_t *hpdp, unsigned long addr,
                                     unsigned pdshift)
 {
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
index 4bc2c3dad6ad..cf4df8e2139a 100644
--- a/arch/powerpc/include/asm/hvcall.h
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -270,6 +270,9 @@
 #define H_SET_MODE              0x31C
 #define MAX_HCALL_OPCODE        H_SET_MODE
 
+/* Platform specific hcalls, used by KVM */
+#define H_RTAS                  0xf000
+
 #ifndef __ASSEMBLY__
 
 /**
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index e45c4947a772..d615b28dda82 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -95,15 +95,13 @@ static inline bool arch_irqs_disabled(void)
 #define __hard_irq_disable()    __mtmsrd(local_paca->kernel_msr, 1)
 #endif
 
-static inline void hard_irq_disable(void)
-{
-        __hard_irq_disable();
-        get_paca()->soft_enabled = 0;
-        get_paca()->irq_happened |= PACA_IRQ_HARD_DIS;
-}
-
-/* include/linux/interrupt.h needs hard_irq_disable to be a macro */
-#define hard_irq_disable        hard_irq_disable
+#define hard_irq_disable()      do {                    \
+        __hard_irq_disable();                           \
+        if (local_paca->soft_enabled)                   \
+                trace_hardirqs_off();                   \
+        get_paca()->soft_enabled = 0;                   \
+        get_paca()->irq_happened |= PACA_IRQ_HARD_DIS;  \
+} while(0)
 
 static inline bool lazy_irq_pending(void)
 {
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index f94ef4213e9d..dd15e5e37d6d 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -15,10 +15,6 @@
 extern int check_legacy_ioport(unsigned long base_port);
 #define I8042_DATA_REG  0x60
 #define FDC_BASE        0x3f0
-/* only relevant for PReP */
-#define _PIDXR          0x279
-#define _PNPWRP         0xa79
-#define PNPBIOS_BASE    0xf000
 
 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
 extern struct pci_dev *isa_bridge_pcidev;
diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h
index aabcdba8f6b0..b9dd382cb349 100644
--- a/arch/powerpc/include/asm/kvm_asm.h
+++ b/arch/powerpc/include/asm/kvm_asm.h
@@ -67,6 +67,10 @@
 #define BOOKE_INTERRUPT_HV_SYSCALL 40
 #define BOOKE_INTERRUPT_HV_PRIV 41
 
+/* altivec */
+#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL 42
+#define BOOKE_INTERRUPT_ALTIVEC_ASSIST 43
+
 /* book3s */
 
 #define BOOK3S_INTERRUPT_SYSTEM_RESET   0x100
diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
index 5a56e1c5f851..349ed85c7d61 100644
--- a/arch/powerpc/include/asm/kvm_book3s.h
+++ b/arch/powerpc/include/asm/kvm_book3s.h
@@ -142,6 +142,8 @@ extern int kvmppc_mmu_hv_init(void);
 extern int kvmppc_ld(struct kvm_vcpu *vcpu, ulong *eaddr, int size, void *ptr, bool data);
 extern int kvmppc_st(struct kvm_vcpu *vcpu, ulong *eaddr, int size, void *ptr, bool data);
 extern void kvmppc_book3s_queue_irqprio(struct kvm_vcpu *vcpu, unsigned int vec);
+extern void kvmppc_book3s_dequeue_irqprio(struct kvm_vcpu *vcpu,
+                                          unsigned int vec);
 extern void kvmppc_inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 flags);
 extern void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat,
                            bool upper, u32 val);
@@ -156,7 +158,8 @@ void kvmppc_clear_ref_hpte(struct kvm *kvm, unsigned long *hptep,
                         unsigned long pte_index);
 extern void *kvmppc_pin_guest_page(struct kvm *kvm, unsigned long addr,
                         unsigned long *nb_ret);
-extern void kvmppc_unpin_guest_page(struct kvm *kvm, void *addr);
+extern void kvmppc_unpin_guest_page(struct kvm *kvm, void *addr,
+                        unsigned long gpa, bool dirty);
 extern long kvmppc_virtmode_h_enter(struct kvm_vcpu *vcpu, unsigned long flags,
                         long pte_index, unsigned long pteh, unsigned long ptel);
 extern long kvmppc_do_h_enter(struct kvm *kvm, unsigned long flags,
@@ -458,6 +461,8 @@ static inline bool kvmppc_critical_section(struct kvm_vcpu *vcpu)
 #define OSI_SC_MAGIC_R4                 0x77810F9B
 
 #define INS_DCBZ                        0x7c0007ec
+/* TO = 31 for unconditional trap */
+#define INS_TW                          0x7fe00008
 
 /* LPIDs we support with this build -- runtime limit may be lower */
 #define KVMPPC_NR_LPIDS                 (LPID_RSVD + 1)
diff --git a/arch/powerpc/include/asm/kvm_book3s_64.h b/arch/powerpc/include/asm/kvm_book3s_64.h
index 38bec1dc9928..9c1ff330c805 100644
--- a/arch/powerpc/include/asm/kvm_book3s_64.h
+++ b/arch/powerpc/include/asm/kvm_book3s_64.h
@@ -268,4 +268,17 @@ static inline int is_vrma_hpte(unsigned long hpte_v)
                 (HPTE_V_1TB_SEG | (VRMA_VSID << (40 - 16)));
 }
 
+#ifdef CONFIG_KVM_BOOK3S_64_HV
+/*
+ * Note modification of an HPTE; set the HPTE modified bit
+ * if anyone is interested.
+ */
+static inline void note_hpte_modification(struct kvm *kvm,
+                                          struct revmap_entry *rev)
+{
+        if (atomic_read(&kvm->arch.hpte_mod_interest))
+                rev->guest_rpte |= HPTE_GR_MODIFIED;
+}
+#endif /* CONFIG_KVM_BOOK3S_64_HV */
+
 #endif /* __ASM_KVM_BOOK3S_64_H__ */
diff --git a/arch/powerpc/include/asm/kvm_book3s_asm.h b/arch/powerpc/include/asm/kvm_book3s_asm.h
index cdc3d2717cc6..9039d3c97eec 100644
--- a/arch/powerpc/include/asm/kvm_book3s_asm.h
+++ b/arch/powerpc/include/asm/kvm_book3s_asm.h
@@ -20,6 +20,11 @@
 #ifndef __ASM_KVM_BOOK3S_ASM_H__
 #define __ASM_KVM_BOOK3S_ASM_H__
 
+/* XICS ICP register offsets */
+#define XICS_XIRR               4
+#define XICS_MFRR               0xc
+#define XICS_IPI                2       /* interrupt source # for IPIs */
+
 #ifdef __ASSEMBLY__
 
 #ifdef CONFIG_KVM_BOOK3S_HANDLER
@@ -81,10 +86,11 @@ struct kvmppc_host_state {
 #ifdef CONFIG_KVM_BOOK3S_64_HV
         u8 hwthread_req;
         u8 hwthread_state;
-
+        u8 host_ipi;
         struct kvm_vcpu *kvm_vcpu;
         struct kvmppc_vcore *kvm_vcore;
         unsigned long xics_phys;
+        u32 saved_xirr;
         u64 dabr;
         u64 host_mmcr[3];
         u32 host_pmc[8];
diff --git a/arch/powerpc/include/asm/kvm_booke.h b/arch/powerpc/include/asm/kvm_booke.h
index b7cd3356a532..d3c1eb34c986 100644
--- a/arch/powerpc/include/asm/kvm_booke.h
+++ b/arch/powerpc/include/asm/kvm_booke.h
@@ -26,6 +26,8 @@
 /* LPIDs we support with this build -- runtime limit may be lower */
 #define KVMPPC_NR_LPIDS                        64
 
+#define KVMPPC_INST_EHPRIV      0x7c00021c
+
 static inline void kvmppc_set_gpr(struct kvm_vcpu *vcpu, int num, ulong val)
 {
         vcpu->arch.gpr[num] = val;
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index d1bb86074721..af326cde7cb6 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -44,6 +44,10 @@
 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
 #endif
 
+/* These values are internal and can be increased later */
+#define KVM_NR_IRQCHIPS          1
+#define KVM_IRQCHIP_NUM_PINS     256
+
 #if !defined(CONFIG_KVM_440)
 #include <linux/mmu_notifier.h>
 
@@ -188,6 +192,10 @@ struct kvmppc_linear_info {
         int              type;
 };
 
+/* XICS components, defined in book3s_xics.c */
+struct kvmppc_xics;
+struct kvmppc_icp;
+
 /*
  * The reverse mapping array has one entry for each HPTE,
  * which stores the guest's view of the second word of the HPTE
@@ -255,6 +263,13 @@ struct kvm_arch {
 #endif /* CONFIG_KVM_BOOK3S_64_HV */
 #ifdef CONFIG_PPC_BOOK3S_64
         struct list_head spapr_tce_tables;
+        struct list_head rtas_tokens;
+#endif
+#ifdef CONFIG_KVM_MPIC
+        struct openpic *mpic;
+#endif
+#ifdef CONFIG_KVM_XICS
+        struct kvmppc_xics *xics;
 #endif
 };
 
@@ -301,11 +316,13 @@ struct kvmppc_vcore {
  * that a guest can register.
  */
 struct kvmppc_vpa {
+        unsigned long gpa;      /* Current guest phys addr */
         void *pinned_addr;      /* Address in kernel linear mapping */
         void *pinned_end;       /* End of region */
         unsigned long next_gpa; /* Guest phys addr for update */
         unsigned long len;      /* Number of bytes required */
         u8 update_pending;      /* 1 => update pinned_addr from next_gpa */
+        bool dirty;             /* true => area has been modified by kernel */
 };
 
 struct kvmppc_pte {
@@ -359,6 +376,11 @@ struct kvmppc_slb {
 #define KVMPPC_BOOKE_MAX_IAC    4
 #define KVMPPC_BOOKE_MAX_DAC    2
 
+/* KVMPPC_EPR_USER takes precedence over KVMPPC_EPR_KERNEL */
+#define KVMPPC_EPR_NONE         0 /* EPR not supported */
+#define KVMPPC_EPR_USER         1 /* exit to userspace to fill EPR */
+#define KVMPPC_EPR_KERNEL       2 /* in-kernel irqchip */
+
 struct kvmppc_booke_debug_reg {
         u32 dbcr0;
         u32 dbcr1;
@@ -370,6 +392,12 @@ struct kvmppc_booke_debug_reg {
         u64 dac[KVMPPC_BOOKE_MAX_DAC];
 };
 
+#define KVMPPC_IRQ_DEFAULT      0
+#define KVMPPC_IRQ_MPIC         1
+#define KVMPPC_IRQ_XICS         2
+
+struct openpic;
+
 struct kvm_vcpu_arch {
         ulong host_stack;
         u32 host_pid;
@@ -502,8 +530,11 @@ struct kvm_vcpu_arch {
         spinlock_t wdt_lock;
         struct timer_list wdt_timer;
         u32 tlbcfg[4];
+        u32 tlbps[4];
         u32 mmucfg;
+        u32 eptcfg;
         u32 epr;
+        u32 crit_save;
         struct kvmppc_booke_debug_reg dbg_reg;
 #endif
         gpa_t paddr_accessed;
@@ -521,7 +552,7 @@ struct kvm_vcpu_arch {
         u8 sane;
         u8 cpu_type;
         u8 hcall_needed;
-        u8 epr_enabled;
+        u8 epr_flags; /* KVMPPC_EPR_xxx */
         u8 epr_needed;
 
         u32 cpr0_cfgaddr; /* holds the last set cpr0_cfgaddr */
@@ -548,6 +579,13 @@ struct kvm_vcpu_arch {
         unsigned long magic_page_pa; /* phys addr to map the magic page to */
         unsigned long magic_page_ea; /* effect. addr to map the magic page to */
 
+        int irq_type;           /* one of KVM_IRQ_* */
+        int irq_cpu_id;
+        struct openpic *mpic;   /* KVM_IRQ_MPIC */
+#ifdef CONFIG_KVM_XICS
+        struct kvmppc_icp *icp; /* XICS presentation controller */
+#endif
+
 #ifdef CONFIG_KVM_BOOK3S_64_HV
         struct kvm_vcpu_arch_shared shregs;
 
@@ -588,5 +626,6 @@ struct kvm_vcpu_arch {
 #define KVM_MMIO_REG_FQPR       0x0060
 
 #define __KVM_HAVE_ARCH_WQP
+#define __KVM_HAVE_CREATE_DEVICE
 
 #endif /* __POWERPC_KVM_HOST_H__ */
diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h
index 44a657adf416..a5287fe03d77 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -44,7 +44,7 @@ enum emulation_result {
         EMULATE_DO_DCR,       /* kvm_run filled with DCR request */
         EMULATE_FAIL,         /* can't emulate this instruction */
         EMULATE_AGAIN,        /* something went wrong. go again */
-        EMULATE_DO_PAPR,      /* kvm_run filled with PAPR request */
+        EMULATE_EXIT_USER,    /* emulation requires exit to user-space */
 };
 
 extern int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu);
@@ -104,8 +104,7 @@ extern void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu);
 extern void kvmppc_core_dequeue_dec(struct kvm_vcpu *vcpu);
 extern void kvmppc_core_queue_external(struct kvm_vcpu *vcpu,
                                        struct kvm_interrupt *irq);
-extern void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu,
-                                         struct kvm_interrupt *irq);
+extern void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu);
 extern void kvmppc_core_flush_tlb(struct kvm_vcpu *vcpu);
 
 extern int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
@@ -131,6 +130,7 @@ extern long kvmppc_prepare_vrma(struct kvm *kvm,
 extern void kvmppc_map_vrma(struct kvm_vcpu *vcpu,
                         struct kvm_memory_slot *memslot, unsigned long porder);
 extern int kvmppc_pseries_do_hcall(struct kvm_vcpu *vcpu);
+
 extern long kvm_vm_ioctl_create_spapr_tce(struct kvm *kvm,
                                 struct kvm_create_spapr_tce *args);
 extern long kvmppc_h_put_tce(struct kvm_vcpu *vcpu, unsigned long liobn,
@@ -152,7 +152,7 @@ extern int kvmppc_core_prepare_memory_region(struct kvm *kvm,
                                 struct kvm_userspace_memory_region *mem);
 extern void kvmppc_core_commit_memory_region(struct kvm *kvm,
                                 struct kvm_userspace_memory_region *mem,
-                                struct kvm_memory_slot old);
+                                const struct kvm_memory_slot *old);
 extern int kvm_vm_ioctl_get_smmu_info(struct kvm *kvm,
                                       struct kvm_ppc_smmu_info *info);
 extern void kvmppc_core_flush_memslot(struct kvm *kvm,
@@ -165,6 +165,18 @@ extern int kvmppc_prepare_to_enter(struct kvm_vcpu *vcpu);
 
 extern int kvm_vm_ioctl_get_htab_fd(struct kvm *kvm, struct kvm_get_htab_fd *);
 
+int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, struct kvm_interrupt *irq);
+
+extern int kvm_vm_ioctl_rtas_define_token(struct kvm *kvm, void __user *argp);
+extern int kvmppc_rtas_hcall(struct kvm_vcpu *vcpu);
+extern void kvmppc_rtas_tokens_free(struct kvm *kvm);
+extern int kvmppc_xics_set_xive(struct kvm *kvm, u32 irq, u32 server,
+                                u32 priority);
+extern int kvmppc_xics_get_xive(struct kvm *kvm, u32 irq, u32 *server,
+                                u32 *priority);
+extern int kvmppc_xics_int_on(struct kvm *kvm, u32 irq);
+extern int kvmppc_xics_int_off(struct kvm *kvm, u32 irq);
+
 /*
  * Cuts out inst bits with ordering according to spec.
  * That means the leftmost bit is zero. All given bits are included.
@@ -246,12 +258,29 @@ int kvmppc_set_one_reg(struct kvm_vcpu *vcpu, u64 id, union kvmppc_one_reg *);
 
 void kvmppc_set_pid(struct kvm_vcpu *vcpu, u32 pid);
 
+struct openpic;
+
 #ifdef CONFIG_KVM_BOOK3S_64_HV
 static inline void kvmppc_set_xics_phys(int cpu, unsigned long addr)
 {
         paca[cpu].kvm_hstate.xics_phys = addr;
 }
 
+static inline u32 kvmppc_get_xics_latch(void)
+{
+        u32 xirr = get_paca()->kvm_hstate.saved_xirr;
+
+        get_paca()->kvm_hstate.saved_xirr = 0;
+
+        return xirr;
+}
+
+static inline void kvmppc_set_host_ipi(int cpu, u8 host_ipi)
+{
+        paca[cpu].kvm_hstate.host_ipi = host_ipi;
+}
+
+extern void kvmppc_fast_vcpu_kick(struct kvm_vcpu *vcpu);
 extern void kvm_linear_init(void);
 
 #else
@@ -260,6 +289,46 @@ static inline void kvmppc_set_xics_phys(int cpu, unsigned long addr)
 
 static inline void kvm_linear_init(void)
 {}
+
+static inline u32 kvmppc_get_xics_latch(void)
+{
+        return 0;
+}
+
+static inline void kvmppc_set_host_ipi(int cpu, u8 host_ipi)
+{}
+
+static inline void kvmppc_fast_vcpu_kick(struct kvm_vcpu *vcpu)
+{
+        kvm_vcpu_kick(vcpu);
+}
+#endif
+
+#ifdef CONFIG_KVM_XICS
+static inline int kvmppc_xics_enabled(struct kvm_vcpu *vcpu)
+{
+        return vcpu->arch.irq_type == KVMPPC_IRQ_XICS;
+}
+extern void kvmppc_xics_free_icp(struct kvm_vcpu *vcpu);
+extern int kvmppc_xics_create_icp(struct kvm_vcpu *vcpu, unsigned long server);
+extern int kvm_vm_ioctl_xics_irq(struct kvm *kvm, struct kvm_irq_level *args);
+extern int kvmppc_xics_hcall(struct kvm_vcpu *vcpu, u32 cmd);
+extern u64 kvmppc_xics_get_icp(struct kvm_vcpu *vcpu);
+extern int kvmppc_xics_set_icp(struct kvm_vcpu *vcpu, u64 icpval);
+extern int kvmppc_xics_connect_vcpu(struct kvm_device *dev,
+                        struct kvm_vcpu *vcpu, u32 cpu);
+#else
+static inline int kvmppc_xics_enabled(struct kvm_vcpu *vcpu)
+        { return 0; }
+static inline void kvmppc_xics_free_icp(struct kvm_vcpu *vcpu) { }
+static inline int kvmppc_xics_create_icp(struct kvm_vcpu *vcpu,
+                                         unsigned long server)
+        { return -EINVAL; }
+static inline int kvm_vm_ioctl_xics_irq(struct kvm *kvm,
+                                        struct kvm_irq_level *args)
+        { return -ENOTTY; }
+static inline int kvmppc_xics_hcall(struct kvm_vcpu *vcpu, u32 cmd)
+        { return 0; }
 #endif
 
 static inline void kvmppc_set_epr(struct kvm_vcpu *vcpu, u32 epr)
@@ -271,6 +340,32 @@ static inline void kvmppc_set_epr(struct kvm_vcpu *vcpu, u32 epr)
 #endif
 }
 
+#ifdef CONFIG_KVM_MPIC
+
+void kvmppc_mpic_set_epr(struct kvm_vcpu *vcpu);
+int kvmppc_mpic_connect_vcpu(struct kvm_device *dev, struct kvm_vcpu *vcpu,
+                             u32 cpu);
+void kvmppc_mpic_disconnect_vcpu(struct openpic *opp, struct kvm_vcpu *vcpu);
+
+#else
+
+static inline void kvmppc_mpic_set_epr(struct kvm_vcpu *vcpu)
+{
+}
+
+static inline int kvmppc_mpic_connect_vcpu(struct kvm_device *dev,
+                struct kvm_vcpu *vcpu, u32 cpu)
+{
+        return -EINVAL;
+}
+
+static inline void kvmppc_mpic_disconnect_vcpu(struct openpic *opp,
+                struct kvm_vcpu *vcpu)
+{
+}
+
+#endif /* CONFIG_KVM_MPIC */
+
 int kvm_vcpu_ioctl_config_tlb(struct kvm_vcpu *vcpu,
                               struct kvm_config_tlb *cfg);
 int kvm_vcpu_ioctl_dirty_tlb(struct kvm_vcpu *vcpu,
@@ -283,8 +378,15 @@ void kvmppc_init_lpid(unsigned long nr_lpids);
 
 static inline void kvmppc_mmu_flush_icache(pfn_t pfn)
 {
-        /* Clear i-cache for new pages */
         struct page *page;
+        /*
+         * We can only access pages that the kernel maps
+         * as memory. Bail out for unmapped ones.
+         */
+        if (!pfn_valid(pfn))
+                return;
+
+        /* Clear i-cache for new pages */
         page = pfn_to_page(pfn);
         if (!test_bit(PG_arch_1, &page->flags)) {
                 flush_dcache_icache_page(page);
@@ -324,4 +426,6 @@ static inline ulong kvmppc_get_ea_indexed(struct kvm_vcpu *vcpu, int ra, int rb)
         return ea;
 }
 
+extern void xics_wake_cpu(int cpu);
+
 #endif /* __POWERPC_KVM_PPC_H__ */
diff --git a/arch/powerpc/include/asm/linkage.h b/arch/powerpc/include/asm/linkage.h
new file mode 100644
index 000000000000..b36f650a13ff
--- /dev/null
+++ b/arch/powerpc/include/asm/linkage.h
@@ -0,0 +1,13 @@
+#ifndef _ASM_POWERPC_LINKAGE_H
+#define _ASM_POWERPC_LINKAGE_H
+
+#ifdef CONFIG_PPC64
+#define cond_syscall(x) \
+        asm ("\t.weak " #x "\n\t.set " #x ", sys_ni_syscall\n"          \
+             "\t.weak ." #x "\n\t.set ." #x ", .sys_ni_syscall\n")
+#define SYSCALL_ALIAS(alias, name)                                      \
+        asm ("\t.globl " #alias "\n\t.set " #alias ", " #name "\n"      \
+             "\t.globl ." #alias "\n\t.set ." #alias ", ." #name)
+#endif
+
+#endif  /* _ASM_POWERPC_LINKAGE_H */
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index 3d6b4100dac1..92386fc4e82a 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -29,6 +29,7 @@ struct rtc_time;
 struct file;
 struct pci_controller;
 struct kimage;
+struct pci_host_bridge;
 
 struct machdep_calls {
         char            *name;
@@ -50,7 +51,8 @@ struct machdep_calls {
                                        unsigned long prpn,
                                        unsigned long rflags,
                                        unsigned long vflags,
-                                       int psize, int ssize);
+                                       int psize, int apsize,
+                                       int ssize);
         long            (*hpte_remove)(unsigned long hpte_group);
         void            (*hpte_removebolted)(unsigned long ea,
                                              int psize, int ssize);
@@ -107,6 +109,8 @@ struct machdep_calls {
         void            (*pcibios_fixup)(void);
         int             (*pci_probe_mode)(struct pci_bus *);
         void            (*pci_irq_fixup)(struct pci_dev *dev);
+        int             (*pcibios_root_bridge_prepare)(struct pci_host_bridge
+                                *bridge);
 
         /* To setup PHBs when using automatic OF platform driver for PCI */
         int             (*pci_setup_phb)(struct pci_controller *host);
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 99d43e0c1e4a..936db360790a 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -215,6 +215,7 @@
 #define TLBILX_T_CLASS3                 7
 
 #ifndef __ASSEMBLY__
+#include <asm/bug.h>
 
 extern unsigned int tlbcam_index;
 
@@ -231,6 +232,10 @@ typedef struct {
         u64 high_slices_psize;  /* 4 bits per slice for now */
         u16 user_psize;         /* page size index */
 #endif
+#ifdef CONFIG_PPC_64K_PAGES
+        /* for 4K PTE fragment support */
+        void *pte_frag;
+#endif
 } mm_context_t;
 
 /* Page size definitions, common between 32 and 64-bit
@@ -250,6 +255,23 @@ struct mmu_psize_def
 };
 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
 
+static inline int shift_to_mmu_psize(unsigned int shift)
+{
+        int psize;
+
+        for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
+                if (mmu_psize_defs[psize].shift == shift)
+                        return psize;
+        return -1;
+}
+
+static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
+{
+        if (mmu_psize_defs[mmu_psize].shift)
+                return mmu_psize_defs[mmu_psize].shift;
+        BUG();
+}
+
 /* The page sizes use the same names as 64-bit hash but are
  * constants
  */
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index b59e06f507ea..2accc9611248 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -21,6 +21,7 @@
  * complete pgtable.h but only a portion of it.
  */
 #include <asm/pgtable-ppc64.h>
+#include <asm/bug.h>
 
 /*
  * Segment table
@@ -154,11 +155,29 @@ extern unsigned long htab_hash_mask;
 struct mmu_psize_def
 {
         unsigned int    shift;  /* number of bits */
-        unsigned int    penc;   /* HPTE encoding */
+        int             penc[MMU_PAGE_COUNT];   /* HPTE encoding */
         unsigned int    tlbiel; /* tlbiel supported for that page size */
         unsigned long   avpnm;  /* bits to mask out in AVPN in the HPTE */
         unsigned long   sllp;   /* SLB L||LP (exact mask to use in slbmte) */
 };
+extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
+
+static inline int shift_to_mmu_psize(unsigned int shift)
+{
+        int psize;
+
+        for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
+                if (mmu_psize_defs[psize].shift == shift)
+                        return psize;
+        return -1;
+}
+
+static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
+{
+        if (mmu_psize_defs[mmu_psize].shift)
+                return mmu_psize_defs[mmu_psize].shift;
+        BUG();
+}
 
 #endif /* __ASSEMBLY__ */
 
@@ -181,6 +200,13 @@ struct mmu_psize_def
  */
 #define VPN_SHIFT       12
 
+/*
+ * HPTE Large Page (LP) details
+ */
+#define LP_SHIFT        12
+#define LP_BITS         8
+#define LP_MASK(i)      ((0xFF >> (i)) << LP_SHIFT)
+
 #ifndef __ASSEMBLY__
 
 static inline int segment_shift(int ssize)
@@ -193,7 +219,6 @@ static inline int segment_shift(int ssize)
 /*
  * The current system page and segment sizes
  */
-extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
 extern int mmu_linear_psize;
 extern int mmu_virtual_psize;
 extern int mmu_vmalloc_psize;
@@ -237,14 +262,14 @@ static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
 
 /*
  * This function sets the AVPN and L fields of the HPTE  appropriately
- * for the page size
+ * using the base page size and actual page size.
  */
-static inline unsigned long hpte_encode_v(unsigned long vpn,
-                                          int psize, int ssize)
+static inline unsigned long hpte_encode_v(unsigned long vpn, int base_psize,
+                                          int actual_psize, int ssize)
 {
         unsigned long v;
-        v = hpte_encode_avpn(vpn, psize, ssize);
-        if (psize != MMU_PAGE_4K)
+        v = hpte_encode_avpn(vpn, base_psize, ssize);
+        if (actual_psize != MMU_PAGE_4K)
                 v |= HPTE_V_LARGE;
         return v;
 }
@@ -254,19 +279,17 @@ static inline unsigned long hpte_encode_v(unsigned long vpn,
  * for the page size. We assume the pa is already "clean" that is properly
  * aligned for the requested page size
  */
-static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
+static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize,
+                                          int actual_psize)
 {
-        unsigned long r;
-
         /* A 4K page needs no special encoding */
-        if (psize == MMU_PAGE_4K)
+        if (actual_psize == MMU_PAGE_4K)
                 return pa & HPTE_R_RPN;
         else {
-                unsigned int penc = mmu_psize_defs[psize].penc;
-                unsigned int shift = mmu_psize_defs[psize].shift;
-                return (pa & ~((1ul << shift) - 1)) | (penc << 12);
+                unsigned int penc = mmu_psize_defs[base_psize].penc[actual_psize];
+                unsigned int shift = mmu_psize_defs[actual_psize].shift;
+                return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT);
         }
-        return r;
 }
 
 /*
@@ -319,7 +342,8 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
                      unsigned int shift, unsigned int mmu_psize);
 extern void hash_failure_debug(unsigned long ea, unsigned long access,
                                unsigned long vsid, unsigned long trap,
-                               int ssize, int psize, unsigned long pte);
+                               int ssize, int psize, int lpsize,
+                               unsigned long pte);
 extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
                              unsigned long pstart, unsigned long prot,
                              int psize, int ssize);
@@ -498,6 +522,10 @@ typedef struct {
         unsigned long acop;     /* mask of enabled coprocessor types */
         unsigned int cop_pid;   /* pid value used with coprocessors */
 #endif /* CONFIG_PPC_ICSWX */
+#ifdef CONFIG_PPC_64K_PAGES
+        /* for 4K PTE fragment support */
+        void *pte_frag;
+#endif
 } mm_context_t;
 
 
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index a4b28f165b6c..b6c8b58b1d76 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -117,6 +117,7 @@ extern int opal_enter_rtas(struct rtas_args *args,
 #define OPAL_SET_SLOT_LED_STATUS                55
 #define OPAL_GET_EPOW_STATUS                    56
 #define OPAL_SET_SYSTEM_ATTENTION_LED           57
+#define OPAL_PCI_MSI_EOI                        63
 
 #ifndef __ASSEMBLY__
 
@@ -506,6 +507,7 @@ int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
                                   uint8_t *p_bit, uint8_t *q_bit);
 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
                                   uint8_t p_bit, uint8_t q_bit);
+int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
                              uint32_t xive_num);
 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
index f072e974f8a2..988c812aab5b 100644
--- a/arch/powerpc/include/asm/page.h
+++ b/arch/powerpc/include/asm/page.h
@@ -249,6 +249,7 @@ extern long long virt_phys_offset;
 #define is_kernel_addr(x)       ((x) >= PAGE_OFFSET)
 #endif
 
+#ifndef CONFIG_PPC_BOOK3S_64
 /*
  * Use the top bit of the higher-level page table entries to indicate whether
  * the entries we point to contain hugepages.  This works because we know that
@@ -260,6 +261,7 @@ extern long long virt_phys_offset;
 #else
 #define PD_HUGE 0x80000000
 #endif
+#endif /* CONFIG_PPC_BOOK3S_64 */
 
 /*
  * Some number of bits at the level of the page table that points to
@@ -354,14 +356,27 @@ typedef unsigned long pgprot_t;
 typedef struct { signed long pd; } hugepd_t;
 
 #ifdef CONFIG_HUGETLB_PAGE
+#ifdef CONFIG_PPC_BOOK3S_64
+static inline int hugepd_ok(hugepd_t hpd)
+{
+        /*
+         * hugepd pointer, bottom two bits == 00 and next 4 bits
+         * indicate size of table
+         */
+        return (((hpd.pd & 0x3) == 0x0) && ((hpd.pd & HUGEPD_SHIFT_MASK) != 0));
+}
+#else
 static inline int hugepd_ok(hugepd_t hpd)
 {
         return (hpd.pd > 0);
 }
+#endif
 
 #define is_hugepd(pdep)               (hugepd_ok(*((hugepd_t *)(pdep))))
+int pgd_huge(pgd_t pgd);
 #else /* CONFIG_HUGETLB_PAGE */
 #define is_hugepd(pdep)                 0
+#define pgd_huge(pgd)                   0
 #endif /* CONFIG_HUGETLB_PAGE */
 
 struct page;
@@ -378,7 +393,11 @@ void arch_free_page(struct page *page, int order);
 
 struct vm_area_struct;
 
+#ifdef CONFIG_PPC_64K_PAGES
+typedef pte_t *pgtable_t;
+#else
 typedef struct page *pgtable_t;
+#endif
 
 #include <asm-generic/memory_model.h>
 #endif /* __ASSEMBLY__ */
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index cd915d6b093d..88693cef4f3d 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -99,8 +99,7 @@ extern unsigned long slice_get_unmapped_area(unsigned long addr,
                                              unsigned long len,
                                              unsigned long flags,
                                              unsigned int psize,
-                                             int topdown,
-                                             int use_cache);
+                                             int topdown);
 
 extern unsigned int get_slice_psize(struct mm_struct *mm,
                                     unsigned long addr);
diff --git a/arch/powerpc/include/asm/parport.h b/arch/powerpc/include/asm/parport.h
index 6dc2577932b1..a452968b29ea 100644
--- a/arch/powerpc/include/asm/parport.h
+++ b/arch/powerpc/include/asm/parport.h
@@ -21,9 +21,7 @@ static int parport_pc_find_nonpci_ports (int autoirq, int autodma)
         int count = 0;
         int virq;
 
-        for (np = NULL; (np = of_find_compatible_node(np,
-                                                      "parallel",
-                                                      "pnpPNP,400")) != NULL;) {
+        for_each_compatible_node(np, "parallel", "pnpPNP,400") {
                 prop = of_get_property(np, "reg", &propsize);
                 if (!prop || propsize > 6*sizeof(u32))
                         continue;
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index 025a130729bc..8b11b5bd9938 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -39,11 +39,6 @@ struct pci_controller {
         resource_size_t io_base_phys;
         resource_size_t pci_io_size;
 
-        /* Some machines (PReP) have a non 1:1 mapping of
-         * the PCI memory space in the CPU bus space
-         */
-        resource_size_t pci_mem_offset;
-
         /* Some machines have a special region to forward the ISA
          * "memory" cycles such as VGA memory regions. Left to 0
          * if unsupported
@@ -70,6 +65,8 @@ struct pci_controller {
          *  BIG_ENDIAN - cfg_addr is a big endian register
          *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
          *   the PLB4.  Effectively disable MRM commands by setting this.
+         *  FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
+         *   link status is in a RC PCIe cfg register (vs being a SoC register)
          */
 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE          0x00000001
 #define PPC_INDIRECT_TYPE_EXT_REG               0x00000002
@@ -77,12 +74,14 @@ struct pci_controller {
 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK          0x00000008
 #define PPC_INDIRECT_TYPE_BIG_ENDIAN            0x00000010
 #define PPC_INDIRECT_TYPE_BROKEN_MRM            0x00000020
+#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK      0x00000040
         u32 indirect_type;
         /* Currently, we limit ourselves to 1 IO range and 3 mem
          * ranges since the common pci_bus structure can't handle more
          */
         struct resource io_resource;
         struct resource mem_resources[3];
+        resource_size_t mem_offset[3];
         int global_number;              /* PCI domain number */
 
         resource_size_t dma_window_base_cur;
@@ -90,9 +89,9 @@ struct pci_controller {
 
 #ifdef CONFIG_PPC64
         unsigned long buid;
+#endif  /* CONFIG_PPC64 */
 
         void *private_data;
-#endif  /* CONFIG_PPC64 */
 };
 
 /* These are used for config access before all the PCI probing
@@ -117,6 +116,12 @@ extern void setup_indirect_pci(struct pci_controller* hose,
                                resource_size_t cfg_addr,
                                resource_size_t cfg_data, u32 flags);
 
+extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
+                                int offset, int len, u32 *val);
+
+extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
+                                 int offset, int len, u32 val);
+
 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
 {
         return bus->sysdata;
@@ -154,6 +159,8 @@ struct pci_dn {
 
         int     pci_ext_config_space;   /* for pci devices */
 
+        int     force_32bit_msi:1;
+
         struct  pci_dev *pcidev;        /* back-pointer to the pci device */
 #ifdef CONFIG_EEH
         struct eeh_dev *edev;           /* eeh device */
diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h
index d0aec72722e9..f265049dd7d6 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -33,6 +33,8 @@ struct power_pmu {
                                 unsigned long *valp);
         int             (*get_alternatives)(u64 event_id, unsigned int flags,
                                 u64 alt[]);
+        u64             (*bhrb_filter_map)(u64 branch_sample_type);
+        void            (*config_bhrb)(u64 pmu_bhrb_filter);
         void            (*disable_pmc)(unsigned int pmc, unsigned long mmcr[]);
         int             (*limited_pmc_event)(u64 event_id);
         u32             flags;
@@ -42,6 +44,9 @@ struct power_pmu {
         int             (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
                                [PERF_COUNT_HW_CACHE_OP_MAX]
                                [PERF_COUNT_HW_CACHE_RESULT_MAX];
+
+        /* BHRB entries in the PMU */
+        int             bhrb_nr;
 };
 
 /*
@@ -52,6 +57,9 @@ struct power_pmu {
 #define PPMU_NO_SIPR            0x00000004 /* no SIPR/HV in MMCRA at all */
 #define PPMU_NO_CONT_SAMPLING   0x00000008 /* no continuous sampling */
 #define PPMU_SIAR_VALID         0x00000010 /* Processor has SIAR Valid bit */
+#define PPMU_HAS_SSLOT          0x00000020 /* Has sampled slot in MMCRA */
+#define PPMU_HAS_SIER           0x00000040 /* Has SIER */
+#define PPMU_BHRB               0x00000080 /* has BHRB feature enabled */
 
 /*
  * Values for flags to get_alternatives()
@@ -65,6 +73,7 @@ extern int register_power_pmu(struct power_pmu *);
 struct pt_regs;
 extern unsigned long perf_misc_flags(struct pt_regs *regs);
 extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
+extern unsigned long int read_bhrb(int n);
 
 /*
  * Only override the default definitions in include/linux/perf_event.h
diff --git a/arch/powerpc/include/asm/pgalloc-32.h b/arch/powerpc/include/asm/pgalloc-32.h
index 580cf73b96e8..27b2386f738a 100644
--- a/arch/powerpc/include/asm/pgalloc-32.h
+++ b/arch/powerpc/include/asm/pgalloc-32.h
@@ -37,6 +37,17 @@ extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
 extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr);
 extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr);
 
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+{
+        free_page((unsigned long)pte);
+}
+
+static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
+{
+        pgtable_page_dtor(ptepage);
+        __free_page(ptepage);
+}
+
 static inline void pgtable_free(void *table, unsigned index_size)
 {
         BUG_ON(index_size); /* 32-bit doesn't use this */
@@ -45,4 +56,38 @@ static inline void pgtable_free(void *table, unsigned index_size)
 
 #define check_pgt_cache()       do { } while (0)
 
+#ifdef CONFIG_SMP
+static inline void pgtable_free_tlb(struct mmu_gather *tlb,
+                                    void *table, int shift)
+{
+        unsigned long pgf = (unsigned long)table;
+        BUG_ON(shift > MAX_PGTABLE_INDEX_SIZE);
+        pgf |= shift;
+        tlb_remove_table(tlb, (void *)pgf);
+}
+
+static inline void __tlb_remove_table(void *_table)
+{
+        void *table = (void *)((unsigned long)_table & ~MAX_PGTABLE_INDEX_SIZE);
+        unsigned shift = (unsigned long)_table & MAX_PGTABLE_INDEX_SIZE;
+
+        pgtable_free(table, shift);
+}
+#else
+static inline void pgtable_free_tlb(struct mmu_gather *tlb,
+                                    void *table, int shift)
+{
+        pgtable_free(table, shift);
+}
+#endif
+
+static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t table,
+                                  unsigned long address)
+{
+        struct page *page = page_address(table);
+
+        tlb_flush_pgtable(tlb, address);
+        pgtable_page_dtor(page);
+        pgtable_free_tlb(tlb, page, 0);
+}
 #endif /* _ASM_POWERPC_PGALLOC_32_H */
diff --git a/arch/powerpc/include/asm/pgalloc-64.h b/arch/powerpc/include/asm/pgalloc-64.h
index 292725cec2e3..91acb12bac92 100644
--- a/arch/powerpc/include/asm/pgalloc-64.h
+++ b/arch/powerpc/include/asm/pgalloc-64.h
@@ -35,7 +35,10 @@ struct vmemmap_backing {
 #define MAX_PGTABLE_INDEX_SIZE  0xf
 
 extern struct kmem_cache *pgtable_cache[];
-#define PGT_CACHE(shift) (pgtable_cache[(shift)-1])
+#define PGT_CACHE(shift) ({                             \
+                        BUG_ON(!(shift));               \
+                        pgtable_cache[(shift) - 1];     \
+                })
 
 static inline pgd_t *pgd_alloc(struct mm_struct *mm)
 {
@@ -72,8 +75,100 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
 #define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, (unsigned long)(pte))
 #define pmd_pgtable(pmd) pmd_page(pmd)
 
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+                                          unsigned long address)
+{
+        return (pte_t *)__get_free_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO);
+}
+
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
+                                      unsigned long address)
+{
+        struct page *page;
+        pte_t *pte;
+
+        pte = pte_alloc_one_kernel(mm, address);
+        if (!pte)
+                return NULL;
+        page = virt_to_page(pte);
+        pgtable_page_ctor(page);
+        return page;
+}
+
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+{
+        free_page((unsigned long)pte);
+}
+
+static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
+{
+        pgtable_page_dtor(ptepage);
+        __free_page(ptepage);
+}
+
+static inline void pgtable_free(void *table, unsigned index_size)
+{
+        if (!index_size)
+                free_page((unsigned long)table);
+        else {
+                BUG_ON(index_size > MAX_PGTABLE_INDEX_SIZE);
+                kmem_cache_free(PGT_CACHE(index_size), table);
+        }
+}
+
+#ifdef CONFIG_SMP
+static inline void pgtable_free_tlb(struct mmu_gather *tlb,
+                                    void *table, int shift)
+{
+        unsigned long pgf = (unsigned long)table;
+        BUG_ON(shift > MAX_PGTABLE_INDEX_SIZE);
+        pgf |= shift;
+        tlb_remove_table(tlb, (void *)pgf);
+}
+
+static inline void __tlb_remove_table(void *_table)
+{
+        void *table = (void *)((unsigned long)_table & ~MAX_PGTABLE_INDEX_SIZE);
+        unsigned shift = (unsigned long)_table & MAX_PGTABLE_INDEX_SIZE;
+
+        pgtable_free(table, shift);
+}
+#else /* !CONFIG_SMP */
+static inline void pgtable_free_tlb(struct mmu_gather *tlb,
+                                    void *table, int shift)
+{
+        pgtable_free(table, shift);
+}
+#endif /* CONFIG_SMP */
+
+static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t table,
+                                  unsigned long address)
+{
+        struct page *page = page_address(table);
+
+        tlb_flush_pgtable(tlb, address);
+        pgtable_page_dtor(page);
+        pgtable_free_tlb(tlb, page, 0);
+}
+
+#else /* if CONFIG_PPC_64K_PAGES */
+/*
+ * we support 16 fragments per PTE page.
+ */
+#define PTE_FRAG_NR     16
+/*
+ * We use a 2K PTE page fragment and another 2K for storing
+ * real_pte_t hash index
+ */
+#define PTE_FRAG_SIZE_SHIFT  12
+#define PTE_FRAG_SIZE (2 * PTRS_PER_PTE * sizeof(pte_t))
 
-#else /* CONFIG_PPC_64K_PAGES */
+extern pte_t *page_table_alloc(struct mm_struct *, unsigned long, int);
+extern void page_table_free(struct mm_struct *, unsigned long *, int);
+extern void pgtable_free_tlb(struct mmu_gather *tlb, void *table, int shift);
+#ifdef CONFIG_SMP
+extern void __tlb_remove_table(void *_table);
+#endif
 
 #define pud_populate(mm, pud, pmd)      pud_set(pud, (unsigned long)pmd)
 
@@ -83,51 +178,56 @@ static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
         pmd_set(pmd, (unsigned long)pte);
 }
 
-#define pmd_populate(mm, pmd, pte_page) \
-        pmd_populate_kernel(mm, pmd, page_address(pte_page))
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-#endif /* CONFIG_PPC_64K_PAGES */
-
-static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
+static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
+                                pgtable_t pte_page)
 {
-        return kmem_cache_alloc(PGT_CACHE(PMD_INDEX_SIZE),
-                                GFP_KERNEL|__GFP_REPEAT);
+        pmd_set(pmd, (unsigned long)pte_page);
 }
 
-static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
+static inline pgtable_t pmd_pgtable(pmd_t pmd)
 {
-        kmem_cache_free(PGT_CACHE(PMD_INDEX_SIZE), pmd);
+        return (pgtable_t)(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE);
 }
 
 static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
                                           unsigned long address)
 {
-        return (pte_t *)__get_free_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO);
+        return (pte_t *)page_table_alloc(mm, address, 1);
 }
 
 static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
                                         unsigned long address)
 {
-        struct page *page;
-        pte_t *pte;
+        return (pgtable_t)page_table_alloc(mm, address, 0);
+}
 
-        pte = pte_alloc_one_kernel(mm, address);
-        if (!pte)
-                return NULL;
-        page = virt_to_page(pte);
-        pgtable_page_ctor(page);
-        return page;
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+{
+        page_table_free(mm, (unsigned long *)pte, 1);
 }
 
-static inline void pgtable_free(void *table, unsigned index_size)
+static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
 {
-        if (!index_size)
-                free_page((unsigned long)table);
-        else {
-                BUG_ON(index_size > MAX_PGTABLE_INDEX_SIZE);
-                kmem_cache_free(PGT_CACHE(index_size), table);
-        }
+        page_table_free(mm, (unsigned long *)ptepage, 0);
+}
+
+static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t table,
+                                  unsigned long address)
+{
+        tlb_flush_pgtable(tlb, address);
+        pgtable_free_tlb(tlb, table, 0);
+}
+#endif /* CONFIG_PPC_64K_PAGES */
+
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+        return kmem_cache_alloc(PGT_CACHE(PMD_INDEX_SIZE),
+                                GFP_KERNEL|__GFP_REPEAT);
+}
+
+static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
+{
+        kmem_cache_free(PGT_CACHE(PMD_INDEX_SIZE), pmd);
 }
 
 #define __pmd_free_tlb(tlb, pmd, addr)                \
diff --git a/arch/powerpc/include/asm/pgalloc.h b/arch/powerpc/include/asm/pgalloc.h
index bf301ac62f35..e9a9f60e596d 100644
--- a/arch/powerpc/include/asm/pgalloc.h
+++ b/arch/powerpc/include/asm/pgalloc.h
@@ -3,6 +3,7 @@
 #ifdef __KERNEL__
 
 #include <linux/mm.h>
+#include <asm-generic/tlb.h>
 
 #ifdef CONFIG_PPC_BOOK3E
 extern void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address);
@@ -13,56 +14,11 @@ static inline void tlb_flush_pgtable(struct mmu_gather *tlb,
 }
 #endif /* !CONFIG_PPC_BOOK3E */
 
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
-        free_page((unsigned long)pte);
-}
-
-static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
-{
-        pgtable_page_dtor(ptepage);
-        __free_page(ptepage);
-}
-
 #ifdef CONFIG_PPC64
 #include <asm/pgalloc-64.h>
 #else
 #include <asm/pgalloc-32.h>
 #endif
 
-#ifdef CONFIG_SMP
-struct mmu_gather;
-extern void tlb_remove_table(struct mmu_gather *, void *);
-
-static inline void pgtable_free_tlb(struct mmu_gather *tlb, void *table, int shift)
-{
-        unsigned long pgf = (unsigned long)table;
-        BUG_ON(shift > MAX_PGTABLE_INDEX_SIZE);
-        pgf |= shift;
-        tlb_remove_table(tlb, (void *)pgf);
-}
-
-static inline void __tlb_remove_table(void *_table)
-{
-        void *table = (void *)((unsigned long)_table & ~MAX_PGTABLE_INDEX_SIZE);
-        unsigned shift = (unsigned long)_table & MAX_PGTABLE_INDEX_SIZE;
-
-        pgtable_free(table, shift);
-}
-#else /* CONFIG_SMP */
-static inline void pgtable_free_tlb(struct mmu_gather *tlb, void *table, unsigned shift)
-{
-        pgtable_free(table, shift);
-}
-#endif /* !CONFIG_SMP */
-
-static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *ptepage,
-                                  unsigned long address)
-{
-        tlb_flush_pgtable(tlb, address);
-        pgtable_page_dtor(ptepage);
-        pgtable_free_tlb(tlb, page_address(ptepage), 0);
-}
-
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_PGALLOC_H */
diff --git a/arch/powerpc/include/asm/pgtable-ppc64-64k.h b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
index be4e2878fbc0..45142d640720 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64-64k.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
@@ -4,10 +4,10 @@
 #include <asm-generic/pgtable-nopud.h>
 
 
-#define PTE_INDEX_SIZE  12
-#define PMD_INDEX_SIZE  12
+#define PTE_INDEX_SIZE  8
+#define PMD_INDEX_SIZE  10
 #define PUD_INDEX_SIZE  0
-#define PGD_INDEX_SIZE  6
+#define PGD_INDEX_SIZE  12
 
 #ifndef __ASSEMBLY__
 #define PTE_TABLE_SIZE  (sizeof(real_pte_t) << PTE_INDEX_SIZE)
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index 0182c203e411..e3d55f6f24fe 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -167,8 +167,7 @@
  * Find an entry in a page-table-directory.  We combine the address region
  * (the high order N bits) and the pgd portion of the address.
  */
-/* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
-#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff)
+#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
 
 #define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
 
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index a9cbd3ba5c33..7aeb9555f6ea 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -17,6 +17,12 @@ struct mm_struct;
 #  include <asm/pgtable-ppc32.h>
 #endif
 
+/*
+ * We save the slot number & secondary bit in the second half of the
+ * PTE page. We use the 8 bytes per each pte entry.
+ */
+#define PTE_PAGE_HIDX_OFFSET (PTRS_PER_PTE * 8)
+
 #ifndef __ASSEMBLY__
 
 #include <asm/tlbflush.h>
@@ -212,6 +218,8 @@ extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
 extern int gup_hugepd(hugepd_t *hugepd, unsigned pdshift, unsigned long addr,
                       unsigned long end, int write, struct page **pages, int *nr);
 
+extern int gup_hugepte(pte_t *ptep, unsigned long sz, unsigned long addr,
+                       unsigned long end, int write, struct page **pages, int *nr);
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 8752bc8e34a3..eccfc161e58e 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -82,6 +82,8 @@
 #define __REGA0_R31     31
 
 /* sorted alphabetically */
+#define PPC_INST_BHRBE                  0x7c00025c
+#define PPC_INST_CLRBHRB                0x7c00035c
 #define PPC_INST_DCBA                   0x7c0005ec
 #define PPC_INST_DCBA_MASK              0xfc0007fe
 #define PPC_INST_DCBAL                  0x7c2005ec
@@ -113,6 +115,10 @@
 #define PPC_INST_MFSPR_DSCR_MASK        0xfc1fffff
 #define PPC_INST_MTSPR_DSCR             0x7c1103a6
 #define PPC_INST_MTSPR_DSCR_MASK        0xfc1fffff
+#define PPC_INST_MFSPR_DSCR_USER        0x7c0302a6
+#define PPC_INST_MFSPR_DSCR_USER_MASK   0xfc1fffff
+#define PPC_INST_MTSPR_DSCR_USER        0x7c0303a6
+#define PPC_INST_MTSPR_DSCR_USER_MASK   0xfc1fffff
 #define PPC_INST_SLBFEE                 0x7c0007a7
 
 #define PPC_INST_STRING                 0x7c00042a
@@ -297,6 +303,12 @@
 #define PPC_NAP                 stringify_in_c(.long PPC_INST_NAP)
 #define PPC_SLEEP               stringify_in_c(.long PPC_INST_SLEEP)
 
+/* BHRB instructions */
+#define PPC_CLRBHRB             stringify_in_c(.long PPC_INST_CLRBHRB)
+#define PPC_MFBHRBE(r, n)       stringify_in_c(.long PPC_INST_BHRBE | \
+                                                __PPC_RT(r) | \
+                                                        (((n) & 0x3ff) << 11))
+
 /* Transactional memory instructions */
 #define TRECHKPT                stringify_in_c(.long PPC_INST_TRECHKPT)
 #define TRECLAIM(r)             stringify_in_c(.long PPC_INST_TRECLAIM \
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 7ff9eaa3ea6c..d7e67ca8b4a6 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -40,7 +40,7 @@
  * -- BenH.
  */
 
-/* PREP sub-platform types see residual.h for these */
+/* PREP sub-platform types. Unused */
 #define _PREP_Motorola  0x01    /* motorola prep */
 #define _PREP_Firm      0x02    /* firmworks prep */
 #define _PREP_IBM       0x00    /* ibm prep */
@@ -56,13 +56,6 @@
 
 extern int _chrp_type;
 
-#ifdef CONFIG_PPC_PREP
-
-/* what kind of prep workstation we are */
-extern int _prep_type;
-
-#endif /* CONFIG_PPC_PREP */
-
 #endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
 
 /*
@@ -288,6 +281,9 @@ struct thread_struct {
 #endif
 #ifdef CONFIG_PPC_BOOK3S_64
         unsigned long   tar;
+        unsigned long   ebbrr;
+        unsigned long   ebbhr;
+        unsigned long   bescr;
 #endif
 };
 
diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
index 99c92d5363e4..bc2da154f68b 100644
--- a/arch/powerpc/include/asm/prom.h
+++ b/arch/powerpc/include/asm/prom.h
@@ -74,6 +74,75 @@ struct of_drconf_cell {
 #define DRCONF_MEM_AI_INVALID   0x00000040
 #define DRCONF_MEM_RESERVED     0x00000080
 
+/*
+ * There are two methods for telling firmware what our capabilities are.
+ * Newer machines have an "ibm,client-architecture-support" method on the
+ * root node.  For older machines, we have to call the "process-elf-header"
+ * method in the /packages/elf-loader node, passing it a fake 32-bit
+ * ELF header containing a couple of PT_NOTE sections that contain
+ * structures that contain various information.
+ */
+
+/* New method - extensible architecture description vector. */
+
+/* Option vector bits - generic bits in byte 1 */
+#define OV_IGNORE               0x80    /* ignore this vector */
+#define OV_CESSATION_POLICY     0x40    /* halt if unsupported option present*/
+
+/* Option vector 1: processor architectures supported */
+#define OV1_PPC_2_00            0x80    /* set if we support PowerPC 2.00 */
+#define OV1_PPC_2_01            0x40    /* set if we support PowerPC 2.01 */
+#define OV1_PPC_2_02            0x20    /* set if we support PowerPC 2.02 */
+#define OV1_PPC_2_03            0x10    /* set if we support PowerPC 2.03 */
+#define OV1_PPC_2_04            0x08    /* set if we support PowerPC 2.04 */
+#define OV1_PPC_2_05            0x04    /* set if we support PowerPC 2.05 */
+#define OV1_PPC_2_06            0x02    /* set if we support PowerPC 2.06 */
+#define OV1_PPC_2_07            0x01    /* set if we support PowerPC 2.07 */
+
+/* Option vector 2: Open Firmware options supported */
+#define OV2_REAL_MODE           0x20    /* set if we want OF in real mode */
+
+/* Option vector 3: processor options supported */
+#define OV3_FP                  0x80    /* floating point */
+#define OV3_VMX                 0x40    /* VMX/Altivec */
+#define OV3_DFP                 0x20    /* decimal FP */
+
+/* Option vector 4: IBM PAPR implementation */
+#define OV4_MIN_ENT_CAP         0x01    /* minimum VP entitled capacity */
+
+/* Option vector 5: PAPR/OF options supported
+ * These bits are also used in firmware_has_feature() to validate
+ * the capabilities reported for vector 5 in the device tree so we
+ * encode the vector index in the define and use the OV5_FEAT()
+ * and OV5_INDX() macros to extract the desired information.
+ */
+#define OV5_FEAT(x)     ((x) & 0xff)
+#define OV5_INDX(x)     ((x) >> 8)
+#define OV5_LPAR                0x0280  /* logical partitioning supported */
+#define OV5_SPLPAR              0x0240  /* shared-processor LPAR supported */
+/* ibm,dynamic-reconfiguration-memory property supported */
+#define OV5_DRCONF_MEMORY       0x0220
+#define OV5_LARGE_PAGES         0x0210  /* large pages supported */
+#define OV5_DONATE_DEDICATE_CPU 0x0202  /* donate dedicated CPU support */
+#define OV5_MSI                 0x0201  /* PCIe/MSI support */
+#define OV5_CMO                 0x0480  /* Cooperative Memory Overcommitment */
+#define OV5_XCMO                0x0440  /* Page Coalescing */
+#define OV5_TYPE1_AFFINITY      0x0580  /* Type 1 NUMA affinity */
+#define OV5_PRRN                0x0540  /* Platform Resource Reassignment */
+#define OV5_PFO_HW_RNG          0x0E80  /* PFO Random Number Generator */
+#define OV5_PFO_HW_842          0x0E40  /* PFO Compression Accelerator */
+#define OV5_PFO_HW_ENCR         0x0E20  /* PFO Encryption Accelerator */
+#define OV5_SUB_PROCESSORS      0x0F01  /* 1,2,or 4 Sub-Processors supported */
+
+/* Option Vector 6: IBM PAPR hints */
+#define OV6_LINUX               0x02    /* Linux is our OS */
+
+/*
+ * The architecture vector has an array of PVR mask/value pairs,
+ * followed by # option vectors - 1, followed by the option vectors.
+ */
+extern unsigned char ibm_architecture_vec[];
+
 /* These includes are put at the bottom because they may contain things
  * that are overridden by this file.  Ideally they shouldn't be included
  * by this file, but there are a bunch of .c files that currently depend
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
index 5f995681bc1d..becc08e6a65c 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -92,7 +92,8 @@ static inline long regs_return_value(struct pt_regs *regs)
         } while(0)
 
 struct task_struct;
-extern unsigned long ptrace_get_reg(struct task_struct *task, int regno);
+extern int ptrace_get_reg(struct task_struct *task, int regno,
+                          unsigned long *data);
 extern int ptrace_put_reg(struct task_struct *task, int regno,
                           unsigned long data);
 
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index c9c67fc888c9..a6136515c7f2 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -267,7 +267,17 @@
 #define SPRN_HSRR1      0x13B   /* Hypervisor Save/Restore 1 */
 #define SPRN_FSCR       0x099   /* Facility Status & Control Register */
 #define   FSCR_TAR      (1 << (63-55)) /* Enable Target Address Register */
+#define   FSCR_EBB      (1 << (63-56)) /* Enable Event Based Branching */
 #define   FSCR_DSCR     (1 << (63-61)) /* Enable Data Stream Control Register */
+#define SPRN_HFSCR      0xbe    /* HV=1 Facility Status & Control Register */
+#define   HFSCR_TAR     (1 << (63-55)) /* Enable Target Address Register */
+#define   HFSCR_EBB     (1 << (63-56)) /* Enable Event Based Branching */
+#define   HFSCR_TM      (1 << (63-58)) /* Enable Transactional Memory */
+#define   HFSCR_PM      (1 << (63-60)) /* Enable prob/priv access to PMU SPRs */
+#define   HFSCR_BHRB    (1 << (63-59)) /* Enable Branch History Rolling Buffer*/
+#define   HFSCR_DSCR    (1 << (63-61)) /* Enable Data Stream Control Register */
+#define   HFSCR_VECVSX  (1 << (63-62)) /* Enable VMX/VSX  */
+#define   HFSCR_FP      (1 << (63-63)) /* Enable Floating Point */
 #define SPRN_TAR        0x32f   /* Target Address Register */
 #define SPRN_LPCR       0x13E   /* LPAR Control Register */
 #define   LPCR_VPM0     (1ul << (63-0))
@@ -290,6 +300,7 @@
 #define     LPCR_PECE1  0x00002000      /* decrementer can cause exit */
 #define     LPCR_PECE2  0x00001000      /* machine check etc can cause exit */
 #define   LPCR_MER      0x00000800      /* Mediated External Exception */
+#define   LPCR_MER_SH   11
 #define   LPCR_LPES    0x0000000c
 #define   LPCR_LPES0   0x00000008      /* LPAR Env selector 0 */
 #define   LPCR_LPES1   0x00000004      /* LPAR Env selector 1 */
@@ -631,6 +642,7 @@
 #define   MMCR0_FCWAIT  0x00000002UL /* freeze counter in WAIT state */
 #define   MMCR0_FCHV    0x00000001UL /* freeze conditions in hypervisor mode */
 #define SPRN_MMCR1      798
+#define SPRN_MMCR2      769
 #define SPRN_MMCRA      0x312
 #define   MMCRA_SDSYNC  0x80000000UL /* SDAR synced with SIAR */
 #define   MMCRA_SDAR_DCACHE_MISS 0x40000000UL
@@ -649,6 +661,13 @@
 #define   POWER7P_MMCRA_SIAR_VALID 0x10000000   /* P7+ SIAR contents valid */
 #define   POWER7P_MMCRA_SDAR_VALID 0x08000000   /* P7+ SDAR contents valid */
 
+#define SPRN_MMCRH      316     /* Hypervisor monitor mode control register */
+#define SPRN_MMCRS      894     /* Supervisor monitor mode control register */
+#define SPRN_MMCRC      851     /* Core monitor mode control register */
+#define SPRN_EBBHR      804     /* Event based branch handler register */
+#define SPRN_EBBRR      805     /* Event based branch return register */
+#define SPRN_BESCR      806     /* Branch event status and control register */
+
 #define SPRN_PMC1       787
 #define SPRN_PMC2       788
 #define SPRN_PMC3       789
@@ -659,6 +678,11 @@
 #define SPRN_PMC8       794
 #define SPRN_SIAR       780
 #define SPRN_SDAR       781
+#define SPRN_SIER       784
+#define   SIER_SIPR             0x2000000       /* Sampled MSR_PR */
+#define   SIER_SIHV             0x1000000       /* Sampled MSR_HV */
+#define   SIER_SIAR_VALID       0x0400000       /* SIAR contents valid */
+#define   SIER_SDAR_VALID       0x0200000       /* SDAR contents valid */
 
 #define SPRN_PA6T_MMCR0 795
 #define   PA6T_MMCR0_EN0        0x0000000000000001UL
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index aef00c675905..a8bc2bb4adc9 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -143,6 +143,8 @@ struct rtas_suspend_me_data {
 #define RTAS_TYPE_PMGM_TIME_ALARM       0x6f
 #define RTAS_TYPE_PMGM_CONFIG_CHANGE    0x70
 #define RTAS_TYPE_PMGM_SERVICE_PROC     0x71
+/* Platform Resource Reassignment Notification */
+#define RTAS_TYPE_PRRN                  0xA0
 
 /* RTAS check-exception vector offset */
 #define RTAS_VECTOR_EXTERNAL_INTERRUPT  0x500
@@ -277,6 +279,10 @@ extern int early_init_dt_scan_rtas(unsigned long node,
 
 extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
 
+#ifdef CONFIG_PPC_PSERIES
+extern int pseries_devicetree_update(s32 scope);
+#endif
+
 #ifdef CONFIG_PPC_RTAS_DAEMON
 extern void rtas_cancel_event_scan(void);
 #else
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index 195ce2ac5691..ffbaabebcdca 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -143,6 +143,8 @@ extern void __cpu_die(unsigned int cpu);
 /* for UP */
 #define hard_smp_processor_id()         get_hard_smp_processor_id(0)
 #define smp_setup_cpu_maps()
+static inline void inhibit_secondary_onlining(void) {}
+static inline void uninhibit_secondary_onlining(void) {}
 
 #endif /* CONFIG_SMP */
 
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index ebbec52d21bd..43523fe0d8b4 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -190,7 +190,7 @@ SYSCALL_SPU(getcwd)
 SYSCALL_SPU(capget)
 SYSCALL_SPU(capset)
 COMPAT_SYS(sigaltstack)
-SYSX_SPU(sys_sendfile,compat_sys_sendfile_wrapper,sys_sendfile)
+COMPAT_SYS_SPU(sendfile)
 SYSCALL(ni_syscall)
 SYSCALL(ni_syscall)
 PPC_SYS(vfork)
@@ -230,7 +230,7 @@ COMPAT_SYS_SPU(sched_setaffinity)
 COMPAT_SYS_SPU(sched_getaffinity)
 SYSCALL(ni_syscall)
 SYSCALL(ni_syscall)
-SYSX(sys_ni_syscall,compat_sys_sendfile64_wrapper,sys_sendfile64)
+SYS32ONLY(sendfile64)
 COMPAT_SYS_SPU(io_setup)
 SYSCALL_SPU(io_destroy)
 COMPAT_SYS_SPU(io_getevents)
@@ -239,7 +239,7 @@ SYSCALL_SPU(io_cancel)
 SYSCALL(set_tid_address)
 SYSX_SPU(sys_fadvise64,ppc32_fadvise64,sys_fadvise64)
 SYSCALL(exit_group)
-SYSX(sys_lookup_dcookie,ppc32_lookup_dcookie,sys_lookup_dcookie)
+COMPAT_SYS(lookup_dcookie)
 SYSCALL_SPU(epoll_create)
 SYSCALL_SPU(epoll_ctl)
 SYSCALL_SPU(epoll_wait)
@@ -273,8 +273,8 @@ COMPAT_SYS(mq_timedreceive)
 COMPAT_SYS(mq_notify)
 COMPAT_SYS(mq_getsetattr)
 COMPAT_SYS(kexec_load)
-COMPAT_SYS(add_key)
-COMPAT_SYS(request_key)
+SYSCALL(add_key)
+SYSCALL(request_key)
 COMPAT_SYS(keyctl)
 COMPAT_SYS(waitid)
 SYSCALL(ioprio_set)
diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h
index 406b7b9a1341..8ceea14d6fe4 100644
--- a/arch/powerpc/include/asm/thread_info.h
+++ b/arch/powerpc/include/asm/thread_info.h
@@ -182,8 +182,6 @@ static inline bool test_thread_local_flags(unsigned int flags)
 #define is_32bit_task() (1)
 #endif
 
-#define tsk_is_polling(t) test_tsk_thread_flag(t, TIF_POLLING_NRFLAG)
-
 #endif  /* !__ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h
index 852ed1b384f6..161ab662843b 100644
--- a/arch/powerpc/include/asm/topology.h
+++ b/arch/powerpc/include/asm/topology.h
@@ -71,6 +71,7 @@ static inline void sysfs_remove_device_from_node(struct device *dev,
 #if defined(CONFIG_NUMA) && defined(CONFIG_PPC_SPLPAR)
 extern int start_topology_update(void);
 extern int stop_topology_update(void);
+extern int prrn_is_enabled(void);
 #else
 static inline int start_topology_update(void)
 {
@@ -80,6 +81,10 @@ static inline int stop_topology_update(void)
 {
         return 0;
 }
+static inline int prrn_is_enabled(void)
+{
+        return 0;
+}
 #endif /* CONFIG_NUMA && CONFIG_PPC_SPLPAR */
 
 #include <asm-generic/topology.h>
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
index 1487f0f12293..3ca819f541bf 100644
--- a/arch/powerpc/include/asm/unistd.h
+++ b/arch/powerpc/include/asm/unistd.h
@@ -56,11 +56,5 @@
 #define __ARCH_WANT_SYS_VFORK
 #define __ARCH_WANT_SYS_CLONE
 
-/*
- * "Conditional" syscalls
- */
-#define cond_syscall(x) \
-        asmlinkage long x (void) __attribute__((weak,alias("sys_ni_syscall")))
-
 #endif          /* __ASSEMBLY__ */
 #endif /* _ASM_POWERPC_UNISTD_H_ */
diff --git a/arch/powerpc/include/asm/uprobes.h b/arch/powerpc/include/asm/uprobes.h
index b532060d0916..23016020915e 100644
--- a/arch/powerpc/include/asm/uprobes.h
+++ b/arch/powerpc/include/asm/uprobes.h
@@ -51,4 +51,5 @@ extern int  arch_uprobe_post_xol(struct arch_uprobe *aup, struct pt_regs *regs);
 extern bool arch_uprobe_xol_was_trapped(struct task_struct *tsk);
 extern int  arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data);
 extern void arch_uprobe_abort_xol(struct arch_uprobe *aup, struct pt_regs *regs);
+extern unsigned long arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs);
 #endif  /* _ASM_UPROBES_H */
diff --git a/arch/powerpc/include/asm/xics.h b/arch/powerpc/include/asm/xics.h
index 4ae9a09c3b89..282d43a0c855 100644
--- a/arch/powerpc/include/asm/xics.h
+++ b/arch/powerpc/include/asm/xics.h
@@ -150,6 +150,7 @@ extern void xics_register_ics(struct ics *ics);
 extern void xics_teardown_cpu(void);
 extern void xics_kexec_teardown_cpu(int secondary);
 extern void xics_migrate_irqs_away(void);
+extern void icp_native_eoi(struct irq_data *d);
 #ifdef CONFIG_SMP
 extern int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask,
                                unsigned int strict_check);
diff --git a/arch/powerpc/include/uapi/asm/cputable.h b/arch/powerpc/include/uapi/asm/cputable.h
index ed9dd8156962..5b7657959faa 100644
--- a/arch/powerpc/include/uapi/asm/cputable.h
+++ b/arch/powerpc/include/uapi/asm/cputable.h
@@ -1,6 +1,7 @@
 #ifndef _UAPI__ASM_POWERPC_CPUTABLE_H
 #define _UAPI__ASM_POWERPC_CPUTABLE_H
 
+/* in AT_HWCAP */
 #define PPC_FEATURE_32                  0x80000000
 #define PPC_FEATURE_64                  0x40000000
 #define PPC_FEATURE_601_INSTR           0x20000000
@@ -33,4 +34,12 @@
 #define PPC_FEATURE_TRUE_LE             0x00000002
 #define PPC_FEATURE_PPC_LE              0x00000001
 
+/* in AT_HWCAP2 */
+#define PPC_FEATURE2_ARCH_2_07          0x80000000
+#define PPC_FEATURE2_HTM                0x40000000
+#define PPC_FEATURE2_DSCR               0x20000000
+#define PPC_FEATURE2_EBB                0x10000000
+#define PPC_FEATURE2_ISEL               0x08000000
+#define PPC_FEATURE2_TAR                0x04000000
+
 #endif /* _UAPI__ASM_POWERPC_CPUTABLE_H */
diff --git a/arch/powerpc/include/uapi/asm/kvm.h b/arch/powerpc/include/uapi/asm/kvm.h
index 16064d00adb9..0fb1a6e9ff90 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -25,6 +25,8 @@
 /* Select powerpc specific features in <linux/kvm.h> */
 #define __KVM_HAVE_SPAPR_TCE
 #define __KVM_HAVE_PPC_SMT
+#define __KVM_HAVE_IRQCHIP
+#define __KVM_HAVE_IRQ_LINE
 
 struct kvm_regs {
         __u64 pc;
@@ -272,8 +274,31 @@ struct kvm_debug_exit_arch {
 
 /* for KVM_SET_GUEST_DEBUG */
 struct kvm_guest_debug_arch {
+        struct {
+                /* H/W breakpoint/watchpoint address */
+                __u64 addr;
+                /*
+                 * Type denotes h/w breakpoint, read watchpoint, write
+                 * watchpoint or watchpoint (both read and write).
+                 */
+#define KVMPPC_DEBUG_NONE               0x0
+#define KVMPPC_DEBUG_BREAKPOINT         (1UL << 1)
+#define KVMPPC_DEBUG_WATCH_WRITE        (1UL << 2)
+#define KVMPPC_DEBUG_WATCH_READ         (1UL << 3)
+                __u32 type;
+                __u32 reserved;
+        } bp[16];
 };
 
+/* Debug related defines */
+/*
+ * kvm_guest_debug->control is a 32 bit field. The lower 16 bits are generic
+ * and upper 16 bits are architecture specific. Architecture specific defines
+ * that ioctl is for setting hardware breakpoint or software breakpoint.
+ */
+#define KVM_GUESTDBG_USE_SW_BP          0x00010000
+#define KVM_GUESTDBG_USE_HW_BP          0x00020000
+
 /* definition of registers in kvm_run */
 struct kvm_sync_regs {
 };
@@ -299,6 +324,12 @@ struct kvm_allocate_rma {
         __u64 rma_size;
 };
 
+/* for KVM_CAP_PPC_RTAS */
+struct kvm_rtas_token_args {
+        char name[120];
+        __u64 token;    /* Use a token of 0 to undefine a mapping */
+};
+
 struct kvm_book3e_206_tlb_entry {
         __u32 mas8;
         __u32 mas1;
@@ -359,6 +390,26 @@ struct kvm_get_htab_header {
         __u16   n_invalid;
 };
 
+/* Per-vcpu XICS interrupt controller state */
+#define KVM_REG_PPC_ICP_STATE   (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c)
+
+#define  KVM_REG_PPC_ICP_CPPR_SHIFT     56      /* current proc priority */
+#define  KVM_REG_PPC_ICP_CPPR_MASK      0xff
+#define  KVM_REG_PPC_ICP_XISR_SHIFT     32      /* interrupt status field */
+#define  KVM_REG_PPC_ICP_XISR_MASK      0xffffff
+#define  KVM_REG_PPC_ICP_MFRR_SHIFT     24      /* pending IPI priority */
+#define  KVM_REG_PPC_ICP_MFRR_MASK      0xff
+#define  KVM_REG_PPC_ICP_PPRI_SHIFT     16      /* pending irq priority */
+#define  KVM_REG_PPC_ICP_PPRI_MASK      0xff
+
+/* Device control API: PPC-specific devices */
+#define KVM_DEV_MPIC_GRP_MISC           1
+#define   KVM_DEV_MPIC_BASE_ADDR        0       /* 64-bit */
+
+#define KVM_DEV_MPIC_GRP_REGISTER       2       /* 32-bit */
+#define KVM_DEV_MPIC_GRP_IRQ_ACTIVE     3       /* 32-bit */
+
+/* One-Reg API: PPC-specific registers */
 #define KVM_REG_PPC_HIOR        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x1)
 #define KVM_REG_PPC_IAC1        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x2)
 #define KVM_REG_PPC_IAC2        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3)
@@ -417,4 +468,47 @@ struct kvm_get_htab_header {
 #define KVM_REG_PPC_EPCR        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x85)
 #define KVM_REG_PPC_EPR         (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x86)
 
+/* Timer Status Register OR/CLEAR interface */
+#define KVM_REG_PPC_OR_TSR      (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x87)
+#define KVM_REG_PPC_CLEAR_TSR   (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x88)
+#define KVM_REG_PPC_TCR         (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x89)
+#define KVM_REG_PPC_TSR         (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8a)
+
+/* Debugging: Special instruction for software breakpoint */
+#define KVM_REG_PPC_DEBUG_INST  (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8b)
+
+/* MMU registers */
+#define KVM_REG_PPC_MAS0        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8c)
+#define KVM_REG_PPC_MAS1        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8d)
+#define KVM_REG_PPC_MAS2        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8e)
+#define KVM_REG_PPC_MAS7_3      (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8f)
+#define KVM_REG_PPC_MAS4        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x90)
+#define KVM_REG_PPC_MAS6        (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x91)
+#define KVM_REG_PPC_MMUCFG      (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x92)
+/*
+ * TLBnCFG fields TLBnCFG_N_ENTRY and TLBnCFG_ASSOC can be changed only using
+ * KVM_CAP_SW_TLB ioctl
+ */
+#define KVM_REG_PPC_TLB0CFG     (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x93)
+#define KVM_REG_PPC_TLB1CFG     (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x94)
+#define KVM_REG_PPC_TLB2CFG     (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x95)
+#define KVM_REG_PPC_TLB3CFG     (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x96)
+#define KVM_REG_PPC_TLB0PS      (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x97)
+#define KVM_REG_PPC_TLB1PS      (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x98)
+#define KVM_REG_PPC_TLB2PS      (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x99)
+#define KVM_REG_PPC_TLB3PS      (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9a)
+#define KVM_REG_PPC_EPTCFG      (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9b)
+
+/* PPC64 eXternal Interrupt Controller Specification */
+#define KVM_DEV_XICS_GRP_SOURCES        1       /* 64-bit source attributes */
+
+/* Layout of 64-bit source attribute values */
+#define  KVM_XICS_DESTINATION_SHIFT     0
+#define  KVM_XICS_DESTINATION_MASK      0xffffffffULL
+#define  KVM_XICS_PRIORITY_SHIFT        32
+#define  KVM_XICS_PRIORITY_MASK         0xff
+#define  KVM_XICS_LEVEL_SENSITIVE       (1ULL << 40)
+#define  KVM_XICS_MASKED                (1ULL << 41)
+#define  KVM_XICS_PENDING               (1ULL << 42)
+
 #endif /* __LINUX_KVM_POWERPC_H */
diff --git a/arch/powerpc/include/uapi/asm/linkage.h b/arch/powerpc/include/uapi/asm/linkage.h
deleted file mode 100644
index e1c4ac1cc4ba..000000000000
--- a/arch/powerpc/include/uapi/asm/linkage.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_POWERPC_LINKAGE_H
-#define _ASM_POWERPC_LINKAGE_H
-
-/* Nothing to see here... */
-
-#endif  /* _ASM_POWERPC_LINKAGE_H */
diff --git a/arch/powerpc/include/uapi/asm/ptrace.h b/arch/powerpc/include/uapi/asm/ptrace.h
index 66b9ca4ee94a..77d2ed35b111 100644
--- a/arch/powerpc/include/uapi/asm/ptrace.h
+++ b/arch/powerpc/include/uapi/asm/ptrace.h
@@ -211,6 +211,7 @@ struct ppc_debug_info {
 #define PPC_DEBUG_FEATURE_INSN_BP_MASK          0x0000000000000002
 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE         0x0000000000000004
 #define PPC_DEBUG_FEATURE_DATA_BP_MASK          0x0000000000000008
+#define PPC_DEBUG_FEATURE_DATA_BP_DAWR          0x0000000000000010
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index b6c17ec9b169..b51a97cfedf8 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -124,6 +124,9 @@ int main(void)
 
 #ifdef CONFIG_PPC_BOOK3S_64
         DEFINE(THREAD_TAR, offsetof(struct thread_struct, tar));
+        DEFINE(THREAD_BESCR, offsetof(struct thread_struct, bescr));
+        DEFINE(THREAD_EBBHR, offsetof(struct thread_struct, ebbhr));
+        DEFINE(THREAD_EBBRR, offsetof(struct thread_struct, ebbrr));
 #endif
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
         DEFINE(PACATMSCRATCH, offsetof(struct paca_struct, tm_scratch));
@@ -477,6 +480,7 @@ int main(void)
         DEFINE(VCPU_DSISR, offsetof(struct kvm_vcpu, arch.shregs.dsisr));
         DEFINE(VCPU_DAR, offsetof(struct kvm_vcpu, arch.shregs.dar));
         DEFINE(VCPU_VPA, offsetof(struct kvm_vcpu, arch.vpa.pinned_addr));
+        DEFINE(VCPU_VPA_DIRTY, offsetof(struct kvm_vcpu, arch.vpa.dirty));
 #endif
 #ifdef CONFIG_PPC_BOOK3S
         DEFINE(VCPU_VCPUID, offsetof(struct kvm_vcpu, vcpu_id));
@@ -573,6 +577,8 @@ int main(void)
         HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu);
         HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore);
         HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys);
+        HSTATE_FIELD(HSTATE_SAVED_XIRR, saved_xirr);
+        HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi);
         HSTATE_FIELD(HSTATE_MMCR, host_mmcr);
         HSTATE_FIELD(HSTATE_PMC, host_pmc);
         HSTATE_FIELD(HSTATE_PURR, host_purr);
@@ -596,6 +602,7 @@ int main(void)
         DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst));
         DEFINE(VCPU_FAULT_DEAR, offsetof(struct kvm_vcpu, arch.fault_dear));
         DEFINE(VCPU_FAULT_ESR, offsetof(struct kvm_vcpu, arch.fault_esr));
+        DEFINE(VCPU_CRIT_SAVE, offsetof(struct kvm_vcpu, arch.crit_save));
 #endif /* CONFIG_PPC_BOOK3S */
 #endif /* CONFIG_KVM */
 
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index dcd881937f7a..0b9af015bedc 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -53,6 +53,15 @@ _GLOBAL(__e500_dcache_setup)
         isync
         blr
 
+_GLOBAL(__setup_cpu_e6500)
+        mflr    r6
+#ifdef CONFIG_PPC64
+        bl      .setup_altivec_ivors
+#endif
+        bl      __setup_cpu_e5500
+        mtlr    r6
+        blr
+
 #ifdef CONFIG_PPC32
 _GLOBAL(__setup_cpu_e200)
         /* enable dedicated debug exception handling resources (Debug APU) */
@@ -107,6 +116,13 @@ _GLOBAL(__setup_cpu_e5500)
 #endif
 
 #ifdef CONFIG_PPC_BOOK3E_64
+_GLOBAL(__restore_cpu_e6500)
+        mflr    r5
+        bl      .setup_altivec_ivors
+        bl      __restore_cpu_e5500
+        mtlr    r5
+        blr
+
 _GLOBAL(__restore_cpu_e5500)
         mflr    r4
         bl      __e500_icache_setup
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
index ea847abb0d0a..a283b6442b26 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -49,6 +49,7 @@ _GLOBAL(__restore_cpu_power7)
 _GLOBAL(__setup_cpu_power8)
         mflr    r11
         bl      __init_FSCR
+        bl      __init_PMU
         bl      __init_hvmode_206
         mtlr    r11
         beqlr
@@ -57,22 +58,28 @@ _GLOBAL(__setup_cpu_power8)
         mfspr   r3,SPRN_LPCR
         oris    r3, r3, LPCR_AIL_3@h
         bl      __init_LPCR
+        bl      __init_HFSCR
         bl      __init_TLB
+        bl      __init_PMU_HV
         mtlr    r11
         blr
 
 _GLOBAL(__restore_cpu_power8)
         mflr    r11
         bl      __init_FSCR
+        bl      __init_PMU
         mfmsr   r3
         rldicl. r0,r3,4,63
+        mtlr    r11
         beqlr
         li      r0,0
         mtspr   SPRN_LPID,r0
         mfspr   r3,SPRN_LPCR
         oris    r3, r3, LPCR_AIL_3@h
         bl      __init_LPCR
+        bl      __init_HFSCR
         bl      __init_TLB
+        bl      __init_PMU_HV
         mtlr    r11
         blr
 
@@ -116,10 +123,17 @@ __init_LPCR:
 
 __init_FSCR:
         mfspr   r3,SPRN_FSCR
-        ori     r3,r3,FSCR_TAR|FSCR_DSCR
+        ori     r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
         mtspr   SPRN_FSCR,r3
         blr
 
+__init_HFSCR:
+        mfspr   r3,SPRN_HFSCR
+        ori     r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
+                      HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB
+        mtspr   SPRN_HFSCR,r3
+        blr
+
 __init_TLB:
         /* Clear the TLB */
         li      r6,128
@@ -131,3 +145,18 @@ __init_TLB:
         bdnz    2b
         ptesync
 1:      blr
+
+__init_PMU_HV:
+        li      r5,0
+        mtspr   SPRN_MMCRC,r5
+        mtspr   SPRN_MMCRH,r5
+        blr
+
+__init_PMU:
+        li      r5,0
+        mtspr   SPRN_MMCRS,r5
+        mtspr   SPRN_MMCRA,r5
+        mtspr   SPRN_MMCR0,r5
+        mtspr   SPRN_MMCR1,r5
+        mtspr   SPRN_MMCR2,r5
+        blr
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 19599ef352bc..c60bbec25c1f 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -74,7 +74,9 @@ extern void __restore_cpu_a2(void);
 #endif /* CONFIG_PPC64 */
 #if defined(CONFIG_E500)
 extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
+extern void __setup_cpu_e6500(unsigned long offset, struct cpu_spec* spec);
 extern void __restore_cpu_e5500(void);
+extern void __restore_cpu_e6500(void);
 #endif /* CONFIG_E500 */
 
 /* This table only contains "desktop" CPUs, it need to be filled with embedded
@@ -96,10 +98,14 @@ extern void __restore_cpu_e5500(void);
                                  PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
                                  PPC_FEATURE_TRUE_LE | \
                                  PPC_FEATURE_PSERIES_PERFMON_COMPAT)
+#define COMMON_USER2_POWER7     (PPC_FEATURE2_DSCR)
 #define COMMON_USER_POWER8      (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
                                  PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
                                  PPC_FEATURE_TRUE_LE | \
                                  PPC_FEATURE_PSERIES_PERFMON_COMPAT)
+#define COMMON_USER2_POWER8     (PPC_FEATURE2_ARCH_2_07 | \
+                                 PPC_FEATURE2_HTM_COMP | PPC_FEATURE2_DSCR | \
+                                 PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR)
 #define COMMON_USER_PA6T        (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
                                  PPC_FEATURE_TRUE_LE | \
                                  PPC_FEATURE_HAS_ALTIVEC_COMP)
@@ -426,6 +432,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .cpu_name               = "POWER7 (architected)",
                 .cpu_features           = CPU_FTRS_POWER7,
                 .cpu_user_features      = COMMON_USER_POWER7,
+                .cpu_user_features2     = COMMON_USER2_POWER7,
                 .mmu_features           = MMU_FTRS_POWER7,
                 .icache_bsize           = 128,
                 .dcache_bsize           = 128,
@@ -441,6 +448,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .cpu_name               = "POWER8 (architected)",
                 .cpu_features           = CPU_FTRS_POWER8,
                 .cpu_user_features      = COMMON_USER_POWER8,
+                .cpu_user_features2     = COMMON_USER2_POWER8,
                 .mmu_features           = MMU_FTRS_POWER8,
                 .icache_bsize           = 128,
                 .dcache_bsize           = 128,
@@ -456,6 +464,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .cpu_name               = "POWER7 (raw)",
                 .cpu_features           = CPU_FTRS_POWER7,
                 .cpu_user_features      = COMMON_USER_POWER7,
+                .cpu_user_features2     = COMMON_USER2_POWER7,
                 .mmu_features           = MMU_FTRS_POWER7,
                 .icache_bsize           = 128,
                 .dcache_bsize           = 128,
@@ -473,6 +482,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .cpu_name               = "POWER7+ (raw)",
                 .cpu_features           = CPU_FTRS_POWER7,
                 .cpu_user_features      = COMMON_USER_POWER7,
+                .cpu_user_features      = COMMON_USER2_POWER7,
                 .mmu_features           = MMU_FTRS_POWER7,
                 .icache_bsize           = 128,
                 .dcache_bsize           = 128,
@@ -490,6 +500,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .cpu_name               = "POWER8 (raw)",
                 .cpu_features           = CPU_FTRS_POWER8,
                 .cpu_user_features      = COMMON_USER_POWER8,
+                .cpu_user_features2     = COMMON_USER2_POWER8,
                 .mmu_features           = MMU_FTRS_POWER8,
                 .icache_bsize           = 128,
                 .dcache_bsize           = 128,
@@ -1993,6 +2004,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .cpu_user_features      = COMMON_USER_BOOKE |
                         PPC_FEATURE_HAS_SPE_COMP |
                         PPC_FEATURE_HAS_EFP_SINGLE_COMP,
+                .cpu_user_features2     = PPC_FEATURE2_ISEL,
                 .mmu_features           = MMU_FTR_TYPE_FSL_E,
                 .icache_bsize           = 32,
                 .dcache_bsize           = 32,
@@ -2012,6 +2024,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                         PPC_FEATURE_HAS_SPE_COMP |
                         PPC_FEATURE_HAS_EFP_SINGLE_COMP |
                         PPC_FEATURE_HAS_EFP_DOUBLE_COMP,
+                .cpu_user_features2     = PPC_FEATURE2_ISEL,
                 .mmu_features           = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS,
                 .icache_bsize           = 32,
                 .dcache_bsize           = 32,
@@ -2028,6 +2041,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .cpu_name               = "e500mc",
                 .cpu_features           = CPU_FTRS_E500MC,
                 .cpu_user_features      = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
+                .cpu_user_features2     = PPC_FEATURE2_ISEL,
                 .mmu_features           = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
                         MMU_FTR_USE_TLBILX,
                 .icache_bsize           = 64,
@@ -2046,6 +2060,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .cpu_name               = "e5500",
                 .cpu_features           = CPU_FTRS_E5500,
                 .cpu_user_features      = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
+                .cpu_user_features2     = PPC_FEATURE2_ISEL,
                 .mmu_features           = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
                         MMU_FTR_USE_TLBILX,
                 .icache_bsize           = 64,
@@ -2065,7 +2080,9 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .pvr_value              = 0x80400000,
                 .cpu_name               = "e6500",
                 .cpu_features           = CPU_FTRS_E6500,
-                .cpu_user_features      = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
+                .cpu_user_features      = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU |
+                        PPC_FEATURE_HAS_ALTIVEC_COMP,
+                .cpu_user_features2     = PPC_FEATURE2_ISEL,
                 .mmu_features           = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
                         MMU_FTR_USE_TLBILX,
                 .icache_bsize           = 64,
@@ -2073,9 +2090,9 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .num_pmcs               = 4,
                 .oprofile_cpu_type      = "ppc/e6500",
                 .oprofile_type          = PPC_OPROFILE_FSL_EMB,
-                .cpu_setup              = __setup_cpu_e5500,
+                .cpu_setup              = __setup_cpu_e6500,
 #ifndef CONFIG_PPC32
-                .cpu_restore            = __restore_cpu_e5500,
+                .cpu_restore            = __restore_cpu_e6500,
 #endif
                 .machine_check          = machine_check_e500mc,
                 .platform               = "ppce6500",
diff --git a/arch/powerpc/kernel/crash_dump.c b/arch/powerpc/kernel/crash_dump.c
index b3ba5163eae2..9ec3fe174cba 100644
--- a/arch/powerpc/kernel/crash_dump.c
+++ b/arch/powerpc/kernel/crash_dump.c
@@ -150,10 +150,7 @@ void crash_free_reserved_phys_range(unsigned long begin, unsigned long end)
                 if (addr <= rtas_end && ((addr + PAGE_SIZE) > rtas_start))
                         continue;
 
-                ClearPageReserved(pfn_to_page(addr >> PAGE_SHIFT));
-                init_page_count(pfn_to_page(addr >> PAGE_SHIFT));
-                free_page((unsigned long)__va(addr));
-                totalram_pages++;
+                free_reserved_page(pfn_to_page(addr >> PAGE_SHIFT));
         }
 }
 #endif
diff --git a/arch/powerpc/kernel/dbell.c b/arch/powerpc/kernel/dbell.c
index 9ebbc24bb23c..d55c76c571f3 100644
--- a/arch/powerpc/kernel/dbell.c
+++ b/arch/powerpc/kernel/dbell.c
@@ -41,6 +41,8 @@ void doorbell_exception(struct pt_regs *regs)
 
         may_hard_irq_enable();
 
+        __get_cpu_var(irq_stat).doorbell_irqs++;
+
         smp_ipi_demux();
 
         irq_exit();
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 04d69c4a5ac2..3fe5259e2fea 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -458,7 +458,15 @@ BEGIN_FTR_SECTION
          */
         mfspr   r0,SPRN_TAR
         std     r0,THREAD_TAR(r3)
-END_FTR_SECTION_IFSET(CPU_FTR_BCTAR)
+
+        /* Event based branch registers */
+        mfspr   r0, SPRN_BESCR
+        std     r0, THREAD_BESCR(r3)
+        mfspr   r0, SPRN_EBBHR
+        std     r0, THREAD_EBBHR(r3)
+        mfspr   r0, SPRN_EBBRR
+        std     r0, THREAD_EBBRR(r3)
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 #endif
 
 #ifdef CONFIG_SMP
@@ -545,9 +553,17 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
 
 #ifdef CONFIG_PPC_BOOK3S_64
 BEGIN_FTR_SECTION
+        /* Event based branch registers */
+        ld      r0, THREAD_BESCR(r4)
+        mtspr   SPRN_BESCR, r0
+        ld      r0, THREAD_EBBHR(r4)
+        mtspr   SPRN_EBBHR, r0
+        ld      r0, THREAD_EBBRR(r4)
+        mtspr   SPRN_EBBRR, r0
+
         ld      r0,THREAD_TAR(r4)
         mtspr   SPRN_TAR,r0
-END_FTR_SECTION_IFSET(CPU_FTR_BCTAR)
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 #endif
 
 #ifdef CONFIG_ALTIVEC
diff --git a/arch/powerpc/kernel/epapr_hcalls.S b/arch/powerpc/kernel/epapr_hcalls.S
index 62c0dc237826..9f1ebf7338f1 100644
--- a/arch/powerpc/kernel/epapr_hcalls.S
+++ b/arch/powerpc/kernel/epapr_hcalls.S
@@ -17,6 +17,7 @@
 #include <asm/asm-compat.h>
 #include <asm/asm-offsets.h>
 
+#ifndef CONFIG_PPC64
 /* epapr_ev_idle() was derived from e500_idle() */
 _GLOBAL(epapr_ev_idle)
         CURRENT_THREAD_INFO(r3, r1)
@@ -42,6 +43,7 @@ epapr_ev_idle_start:
          * _TLF_NAPPING.
          */
         b       idle_loop
+#endif
 
 /* Hypercall entry point. Will be patched with device tree instructions. */
 .global epapr_hypercall_start
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index ae54553eacd9..42a756eec9ff 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -299,6 +299,8 @@ interrupt_base_book3e:					/* fake trap */
         EXCEPTION_STUB(0x1a0, watchdog)                 /* 0x09f0 */
         EXCEPTION_STUB(0x1c0, data_tlb_miss)
         EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
+        EXCEPTION_STUB(0x200, altivec_unavailable)      /* 0x0f20 */
+        EXCEPTION_STUB(0x220, altivec_assist)           /* 0x1700 */
         EXCEPTION_STUB(0x260, perfmon)
         EXCEPTION_STUB(0x280, doorbell)
         EXCEPTION_STUB(0x2a0, doorbell_crit)
@@ -395,6 +397,45 @@ interrupt_end_book3e:
         bl      .kernel_fp_unavailable_exception
         b       .ret_from_except
 
+/* Altivec Unavailable Interrupt */
+        START_EXCEPTION(altivec_unavailable);
+        NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL,
+                                PROLOG_ADDITION_NONE)
+        /* we can probably do a shorter exception entry for that one... */
+        EXCEPTION_COMMON(0x200, PACA_EXGEN, INTS_KEEP)
+#ifdef CONFIG_ALTIVEC
+BEGIN_FTR_SECTION
+        ld      r12,_MSR(r1)
+        andi.   r0,r12,MSR_PR;
+        beq-    1f
+        bl      .load_up_altivec
+        b       fast_exception_return
+1:
+END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
+#endif
+        INTS_DISABLE
+        bl      .save_nvgprs
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .altivec_unavailable_exception
+        b       .ret_from_except
+
+/* AltiVec Assist */
+        START_EXCEPTION(altivec_assist);
+        NORMAL_EXCEPTION_PROLOG(0x220, BOOKE_INTERRUPT_ALTIVEC_ASSIST,
+                                PROLOG_ADDITION_NONE)
+        EXCEPTION_COMMON(0x220, PACA_EXGEN, INTS_DISABLE)
+        bl      .save_nvgprs
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+#ifdef CONFIG_ALTIVEC
+BEGIN_FTR_SECTION
+        bl      .altivec_assist_exception
+END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
+#else
+        bl      .unknown_exception
+#endif
+        b       .ret_from_except
+
+
 /* Decrementer Interrupt */
         MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
                            decrementer, .timer_interrupt, ACK_DEC)
@@ -807,6 +848,7 @@ fast_exception_return:
 BAD_STACK_TRAMPOLINE(0x000)
 BAD_STACK_TRAMPOLINE(0x100)
 BAD_STACK_TRAMPOLINE(0x200)
+BAD_STACK_TRAMPOLINE(0x220)
 BAD_STACK_TRAMPOLINE(0x260)
 BAD_STACK_TRAMPOLINE(0x280)
 BAD_STACK_TRAMPOLINE(0x2a0)
@@ -1350,6 +1392,11 @@ _GLOBAL(__setup_base_ivors)
 
         blr
 
+_GLOBAL(setup_altivec_ivors)
+        SET_IVOR(32, 0x200) /* AltiVec Unavailable */
+        SET_IVOR(33, 0x220) /* AltiVec Assist */
+        blr
+
 _GLOBAL(setup_perfmon_ivor)
         SET_IVOR(35, 0x260) /* Performance Monitor */
         blr
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 56bd92362ce1..e6eba1bf61ad 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -235,6 +235,7 @@ instruction_access_slb_pSeries:
         .globl hardware_interrupt_hv;
 hardware_interrupt_pSeries:
 hardware_interrupt_hv:
+        HMT_MEDIUM_PPR_DISCARD
         BEGIN_FTR_SECTION
                 _MASKABLE_EXCEPTION_PSERIES(0x502, hardware_interrupt,
                                             EXC_HV, SOFTEN_TEST_HV)
@@ -254,7 +255,11 @@ hardware_interrupt_hv:
         STD_EXCEPTION_PSERIES(0x800, 0x800, fp_unavailable)
         KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x800)
 
-        MASKABLE_EXCEPTION_PSERIES(0x900, 0x900, decrementer)
+        . = 0x900
+        .globl decrementer_pSeries
+decrementer_pSeries:
+        _MASKABLE_EXCEPTION_PSERIES(0x900, decrementer, EXC_STD, SOFTEN_TEST_PR)
+
         STD_EXCEPTION_HV(0x980, 0x982, hdecrementer)
 
         MASKABLE_EXCEPTION_PSERIES(0xa00, 0xa00, doorbell_super)
@@ -688,9 +693,18 @@ slb_miss_user_pseries:
         .align  7
         .globl machine_check_common
 machine_check_common:
+
+        mfspr   r10,SPRN_DAR
+        std     r10,PACA_EXGEN+EX_DAR(r13)
+        mfspr   r10,SPRN_DSISR
+        stw     r10,PACA_EXGEN+EX_DSISR(r13)
         EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
         FINISH_NAP
         DISABLE_INTS
+        ld      r3,PACA_EXGEN+EX_DAR(r13)
+        lwz     r4,PACA_EXGEN+EX_DSISR(r13)
+        std     r3,_DAR(r1)
+        std     r4,_DSISR(r1)
         bl      .save_nvgprs
         addi    r3,r1,STACK_FRAME_OVERHEAD
         bl      .machine_check_exception
@@ -797,7 +811,7 @@ hardware_interrupt_relon_hv:
                 _MASKABLE_RELON_EXCEPTION_PSERIES(0x502, hardware_interrupt, EXC_HV, SOFTEN_TEST_HV)
         FTR_SECTION_ELSE
                 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt, EXC_STD, SOFTEN_TEST_PR)
-        ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_206)
+        ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
         STD_RELON_EXCEPTION_PSERIES(0x4600, 0x600, alignment)
         STD_RELON_EXCEPTION_PSERIES(0x4700, 0x700, program_check)
         STD_RELON_EXCEPTION_PSERIES(0x4800, 0x800, fp_unavailable)
@@ -870,10 +884,6 @@ tm_unavailable_relon_pSeries_1:
         . = 0x5500
         b       denorm_exception_hv
 #endif
-#ifdef CONFIG_HVC_SCOM
-        STD_RELON_EXCEPTION_HV(0x5600, 0x1600, maintence_interrupt)
-        KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1600)
-#endif /* CONFIG_HVC_SCOM */
         STD_RELON_EXCEPTION_PSERIES(0x5700, 0x1700, altivec_assist)
 
         /* Other future vectors */
diff --git a/arch/powerpc/kernel/fadump.c b/arch/powerpc/kernel/fadump.c
index 06c8202a69cf..2230fd0ca3e4 100644
--- a/arch/powerpc/kernel/fadump.c
+++ b/arch/powerpc/kernel/fadump.c
@@ -1045,10 +1045,7 @@ static void fadump_release_memory(unsigned long begin, unsigned long end)
                 if (addr <= ra_end && ((addr + PAGE_SIZE) > ra_start))
                         continue;
 
-                ClearPageReserved(pfn_to_page(addr >> PAGE_SHIFT));
-                init_page_count(pfn_to_page(addr >> PAGE_SHIFT));
-                free_page((unsigned long)__va(addr));
-                totalram_pages++;
+                free_reserved_page(pfn_to_page(addr >> PAGE_SHIFT));
         }
 }
 
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index 7a2e5e421abf..97e2671cde7f 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -769,6 +769,8 @@ finish_tlb_load_47x:
          */
         DEBUG_CRIT_EXCEPTION
 
+interrupt_end:
+
 /*
  * Global functions
  */
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 0886ae6dd5be..b61363d557b5 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -509,6 +509,7 @@ _GLOBAL(copy_and_flush)
         sync
         addi    r5,r5,8
         addi    r6,r6,8
+        isync
         blr
 
 .align 8
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index 5f051eeb93a2..a620203f7de3 100644
--- a/arch/powerpc/kernel/head_booke.h
+++ b/arch/powerpc/kernel/head_booke.h
@@ -199,11 +199,6 @@
         .align 5;                                                            \
 label:
 
-#define FINISH_EXCEPTION(func)                                  \
-        bl      transfer_to_handler_full;                       \
-        .long   func;                                           \
-        .long   ret_from_except_full
-
 #define EXCEPTION(n, intno, label, hdlr, xfer)                  \
         START_EXCEPTION(label);                                 \
         NORMAL_EXCEPTION_PROLOG(intno);                         \
@@ -286,13 +281,13 @@ label:
         andis.  r10,r10,(DBSR_IC|DBSR_BT)@h;                                  \
         beq+    2f;                                                           \
                                                                               \
-        lis     r10,KERNELBASE@h;       /* check if exception in vectors */   \
-        ori     r10,r10,KERNELBASE@l;                                         \
+        lis     r10,interrupt_base@h;   /* check if exception in vectors */   \
+        ori     r10,r10,interrupt_base@l;                                     \
         cmplw   r12,r10;                                                      \
         blt+    2f;                     /* addr below exception vectors */    \
                                                                               \
-        lis     r10,DebugDebug@h;                                             \
-        ori     r10,r10,DebugDebug@l;                                         \
+        lis     r10,interrupt_end@h;                                          \
+        ori     r10,r10,interrupt_end@l;                                      \
         cmplw   r12,r10;                                                      \
         bgt+    2f;                     /* addr above exception vectors */    \
                                                                               \
@@ -339,13 +334,13 @@ label:
         andis.  r10,r10,(DBSR_IC|DBSR_BT)@h;                                  \
         beq+    2f;                                                           \
                                                                               \
-        lis     r10,KERNELBASE@h;       /* check if exception in vectors */   \
-        ori     r10,r10,KERNELBASE@l;                                         \
+        lis     r10,interrupt_base@h;   /* check if exception in vectors */   \
+        ori     r10,r10,interrupt_base@l;                                     \
         cmplw   r12,r10;                                                      \
         blt+    2f;                     /* addr below exception vectors */    \
                                                                               \
-        lis     r10,DebugCrit@h;                                              \
-        ori     r10,r10,DebugCrit@l;                                          \
+        lis     r10,interrupt_end@h;                                          \
+        ori     r10,r10,interrupt_end@l;                                      \
         cmplw   r12,r10;                                                      \
         bgt+    2f;                     /* addr above exception vectors */    \
                                                                               \
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 6f62a737f607..d10a7cacccd2 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -605,6 +605,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
         /* Embedded Hypervisor Privilege */
         EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_EE)
 
+interrupt_end:
+
 /*
  * Local functions
  */
diff --git a/arch/powerpc/kernel/idle.c b/arch/powerpc/kernel/idle.c
index ea78761aa169..939ea7ef0dc8 100644
--- a/arch/powerpc/kernel/idle.c
+++ b/arch/powerpc/kernel/idle.c
@@ -33,11 +33,6 @@
 #include <asm/runlatch.h>
 #include <asm/smp.h>
 
-#ifdef CONFIG_HOTPLUG_CPU
-#define cpu_should_die()        cpu_is_offline(smp_processor_id())
-#else
-#define cpu_should_die()        0
-#endif
 
 unsigned long cpuidle_disable = IDLE_NO_OVERRIDE;
 EXPORT_SYMBOL(cpuidle_disable);
@@ -50,64 +45,38 @@ static int __init powersave_off(char *arg)
 }
 __setup("powersave=off", powersave_off);
 
-/*
- * The body of the idle task.
- */
-void cpu_idle(void)
+#ifdef CONFIG_HOTPLUG_CPU
+void arch_cpu_idle_dead(void)
 {
-        set_thread_flag(TIF_POLLING_NRFLAG);
-        while (1) {
-                tick_nohz_idle_enter();
-                rcu_idle_enter();
-
-                while (!need_resched() && !cpu_should_die()) {
-                        ppc64_runlatch_off();
-
-                        if (ppc_md.power_save) {
-                                clear_thread_flag(TIF_POLLING_NRFLAG);
-                                /*
-                                 * smp_mb is so clearing of TIF_POLLING_NRFLAG
-                                 * is ordered w.r.t. need_resched() test.
-                                 */
-                                smp_mb();
-                                local_irq_disable();
-
-                                /* Don't trace irqs off for idle */
-                                stop_critical_timings();
-
-                                /* check again after disabling irqs */
-                                if (!need_resched() && !cpu_should_die())
-                                        ppc_md.power_save();
-
-                                start_critical_timings();
-
-                                /* Some power_save functions return with
-                                 * interrupts enabled, some don't.
-                                 */
-                                if (irqs_disabled())
-                                        local_irq_enable();
-                                set_thread_flag(TIF_POLLING_NRFLAG);
-
-                        } else {
-                                /*
-                                 * Go into low thread priority and possibly
-                                 * low power mode.
-                                 */
-                                HMT_low();
-                                HMT_very_low();
-                        }
-                }
+        sched_preempt_enable_no_resched();
+        cpu_die();
+}
+#endif
 
-                HMT_medium();
-                ppc64_runlatch_on();
-                rcu_idle_exit();
-                tick_nohz_idle_exit();
-                if (cpu_should_die()) {
-                        sched_preempt_enable_no_resched();
-                        cpu_die();
-                }
-                schedule_preempt_disabled();
+void arch_cpu_idle(void)
+{
+        ppc64_runlatch_off();
+
+        if (ppc_md.power_save) {
+                ppc_md.power_save();
+                /*
+                 * Some power_save functions return with
+                 * interrupts enabled, some don't.
+                 */
+                if (irqs_disabled())
+                        local_irq_enable();
+        } else {
+                local_irq_enable();
+                /*
+                 * Go into low thread priority and possibly
+                 * low power mode.
+                 */
+                HMT_low();
+                HMT_very_low();
         }
+
+        HMT_medium();
+        ppc64_runlatch_on();
 }
 
 int powersave_nap;
diff --git a/arch/powerpc/kernel/idle_book3e.S b/arch/powerpc/kernel/idle_book3e.S
index 4c7cb4008585..bfb73cc209ce 100644
--- a/arch/powerpc/kernel/idle_book3e.S
+++ b/arch/powerpc/kernel/idle_book3e.S
@@ -16,11 +16,13 @@
 #include <asm/ppc-opcode.h>
 #include <asm/processor.h>
 #include <asm/thread_info.h>
+#include <asm/epapr_hcalls.h>
 
 /* 64-bit version only for now */
 #ifdef CONFIG_PPC64
 
-_GLOBAL(book3e_idle)
+.macro BOOK3E_IDLE name loop
+_GLOBAL(\name)
         /* Save LR for later */
         mflr    r0
         std     r0,16(r1)
@@ -67,7 +69,33 @@ _GLOBAL(book3e_idle)
 
         /* We can now re-enable hard interrupts and go to sleep */
         wrteei  1
-1:      PPC_WAIT(0)
+        \loop
+
+.endm
+
+.macro BOOK3E_IDLE_LOOP
+1:
+        PPC_WAIT(0)
         b       1b
+.endm
+
+/* epapr_ev_idle_start below is patched with the proper hcall
+   opcodes during kernel initialization */
+.macro EPAPR_EV_IDLE_LOOP
+idle_loop:
+        LOAD_REG_IMMEDIATE(r11, EV_HCALL_TOKEN(EV_IDLE))
+
+.global epapr_ev_idle_start
+epapr_ev_idle_start:
+        li      r3, -1
+        nop
+        nop
+        nop
+        b       idle_loop
+.endm
+
+BOOK3E_IDLE epapr_ev_idle EPAPR_EV_IDLE_LOOP
+
+BOOK3E_IDLE book3e_idle BOOK3E_IDLE_LOOP
 
 #endif /* CONFIG_PPC64 */
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index 31c4fdc6859c..c0d0dbddfba1 100644
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -102,7 +102,7 @@ static int __init fail_iommu_debugfs(void)
         struct dentry *dir = fault_create_debugfs_attr("fail_iommu",
                                                        NULL, &fail_iommu);
 
-        return IS_ERR(dir) ? PTR_ERR(dir) : 0;
+        return PTR_RET(dir);
 }
 late_initcall(fail_iommu_debugfs);
 
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 4f97fe345526..5cbcf4d5a808 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -374,6 +374,15 @@ int arch_show_interrupts(struct seq_file *p, int prec)
                 seq_printf(p, "%10u ", per_cpu(irq_stat, j).mce_exceptions);
         seq_printf(p, "  Machine check exceptions\n");
 
+#ifdef CONFIG_PPC_DOORBELL
+        if (cpu_has_feature(CPU_FTR_DBELL)) {
+                seq_printf(p, "%*s: ", prec, "DBL");
+                for_each_online_cpu(j)
+                        seq_printf(p, "%10u ", per_cpu(irq_stat, j).doorbell_irqs);
+                seq_printf(p, "  Doorbell interrupts\n");
+        }
+#endif
+
         return 0;
 }
 
@@ -387,6 +396,9 @@ u64 arch_irq_stat_cpu(unsigned int cpu)
         sum += per_cpu(irq_stat, cpu).pmu_irqs;
         sum += per_cpu(irq_stat, cpu).mce_exceptions;
         sum += per_cpu(irq_stat, cpu).spurious_irqs;
+#ifdef CONFIG_PPC_DOORBELL
+        sum += per_cpu(irq_stat, cpu).doorbell_irqs;
+#endif
 
         return sum;
 }
diff --git a/arch/powerpc/kernel/kgdb.c b/arch/powerpc/kernel/kgdb.c
index 5ca82cd4a374..c1eef241017a 100644
--- a/arch/powerpc/kernel/kgdb.c
+++ b/arch/powerpc/kernel/kgdb.c
@@ -159,7 +159,7 @@ static int kgdb_singlestep(struct pt_regs *regs)
         if (user_mode(regs))
                 return 0;
 
-        backup_current_thread_info = (struct thread_info *)kmalloc(sizeof(struct thread_info), GFP_KERNEL);
+        backup_current_thread_info = kmalloc(sizeof(struct thread_info), GFP_KERNEL);
         /*
          * On Book E and perhaps other processors, singlestep is handled on
          * the critical exception stack.  This causes current_thread_info()
diff --git a/arch/powerpc/kernel/kvm.c b/arch/powerpc/kernel/kvm.c
index a61b133c4f99..6782221d49bd 100644
--- a/arch/powerpc/kernel/kvm.c
+++ b/arch/powerpc/kernel/kvm.c
@@ -756,12 +756,7 @@ static __init void kvm_free_tmp(void)
         end = (ulong)&kvm_tmp[ARRAY_SIZE(kvm_tmp)] & PAGE_MASK;
 
         /* Free the tmp space we don't need */
-        for (; start < end; start += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(start));
-                init_page_count(virt_to_page(start));
-                free_page(start);
-                totalram_pages++;
-        }
+        free_reserved_area(start, end, 0, NULL);
 }
 
 static int __init kvm_guest_init(void)
diff --git a/arch/powerpc/kernel/lparcfg.c b/arch/powerpc/kernel/lparcfg.c
index f5725bce9ed2..d92f3871e9cf 100644
--- a/arch/powerpc/kernel/lparcfg.c
+++ b/arch/powerpc/kernel/lparcfg.c
@@ -41,8 +41,6 @@
 
 /* #define LPARCFG_DEBUG */
 
-static struct proc_dir_entry *proc_ppc64_lparcfg;
-
 /*
  * Track sum of all purrs across all processors. This is used to further
  * calculate usage values by different applications
@@ -301,6 +299,7 @@ static void parse_system_parameter_string(struct seq_file *m)
                                 __pa(rtas_data_buf),
                                 RTAS_DATA_BUF_SIZE);
         memcpy(local_buffer, rtas_data_buf, SPLPAR_MAXLENGTH);
+        local_buffer[SPLPAR_MAXLENGTH - 1] = '\0';
         spin_unlock(&rtas_data_buf_lock);
 
         if (call_status != 0) {
@@ -688,27 +687,22 @@ static const struct file_operations lparcfg_fops = {
 
 static int __init lparcfg_init(void)
 {
-        struct proc_dir_entry *ent;
         umode_t mode = S_IRUSR | S_IRGRP | S_IROTH;
 
         /* Allow writing if we have FW_FEATURE_SPLPAR */
         if (firmware_has_feature(FW_FEATURE_SPLPAR))
                 mode |= S_IWUSR;
 
-        ent = proc_create("powerpc/lparcfg", mode, NULL, &lparcfg_fops);
-        if (!ent) {
+        if (!proc_create("powerpc/lparcfg", mode, NULL, &lparcfg_fops)) {
                 printk(KERN_ERR "Failed to create powerpc/lparcfg\n");
                 return -EIO;
         }
-
-        proc_ppc64_lparcfg = ent;
         return 0;
 }
 
 static void __exit lparcfg_cleanup(void)
 {
-        if (proc_ppc64_lparcfg)
-                remove_proc_entry("lparcfg", proc_ppc64_lparcfg->parent);
+        remove_proc_subtree("powerpc/lparcfg", NULL);
 }
 
 module_init(lparcfg_init);
diff --git a/arch/powerpc/kernel/nvram_64.c b/arch/powerpc/kernel/nvram_64.c
index bec1e930ed73..48fbc2b97e95 100644
--- a/arch/powerpc/kernel/nvram_64.c
+++ b/arch/powerpc/kernel/nvram_64.c
@@ -511,8 +511,7 @@ int __init nvram_scan_partitions(void)
                                "detected: 0-length partition\n");
                         goto out;
                 }
-                tmp_part = (struct nvram_partition *)
-                        kmalloc(sizeof(struct nvram_partition), GFP_KERNEL);
+                tmp_part = kmalloc(sizeof(struct nvram_partition), GFP_KERNEL);
                 err = -ENOMEM;
                 if (!tmp_part) {
                         printk(KERN_ERR "nvram_scan_partitions: kmalloc failed\n");
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index fa12ae42d98c..f5c5c90799a7 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -30,6 +30,7 @@
 #include <linux/irq.h>
 #include <linux/vmalloc.h>
 #include <linux/slab.h>
+#include <linux/vgaarb.h>
 
 #include <asm/processor.h>
 #include <asm/io.h>
@@ -785,22 +786,8 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose,
                                 hose->isa_mem_size = size;
                         }
 
-                        /* We get the PCI/Mem offset from the first range or
-                         * the, current one if the offset came from an ISA
-                         * hole. If they don't match, bugger.
-                         */
-                        if (memno == 0 ||
-                            (isa_hole >= 0 && pci_addr != 0 &&
-                             hose->pci_mem_offset == isa_mb))
-                                hose->pci_mem_offset = cpu_addr - pci_addr;
-                        else if (pci_addr != 0 &&
-                                 hose->pci_mem_offset != cpu_addr - pci_addr) {
-                                printk(KERN_INFO
-                                       " \\--> Skipped (offset mismatch) !\n");
-                                continue;
-                        }
-
                         /* Build resource */
+                        hose->mem_offset[memno] = cpu_addr - pci_addr;
                         res = &hose->mem_resources[memno++];
                         res->flags = IORESOURCE_MEM;
                         if (pci_space & 0x40000000)
@@ -816,20 +803,6 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose,
                         res->child = NULL;
                 }
         }
-
-        /* If there's an ISA hole and the pci_mem_offset is -not- matching
-         * the ISA hole offset, then we need to remove the ISA hole from
-         * the resource list for that brige
-         */
-        if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
-                unsigned int next = isa_hole + 1;
-                printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb);
-                if (next < memno)
-                        memmove(&hose->mem_resources[isa_hole],
-                                &hose->mem_resources[next],
-                                sizeof(struct resource) * (memno - next));
-                hose->mem_resources[--memno].flags = 0;
-        }
 }
 
 /* Decide whether to display the domain number in /proc */
@@ -844,6 +817,14 @@ int pci_proc_domain(struct pci_bus *bus)
         return 1;
 }
 
+int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
+{
+        if (ppc_md.pcibios_root_bridge_prepare)
+                return ppc_md.pcibios_root_bridge_prepare(bridge);
+
+        return 0;
+}
+
 /* This header fixup will do the resource fixup for all devices as they are
  * probed, but not for bridge ranges
  */
@@ -907,6 +888,7 @@ static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
         struct pci_controller *hose = pci_bus_to_host(bus);
         struct pci_dev *dev = bus->self;
         resource_size_t offset;
+        struct pci_bus_region region;
         u16 command;
         int i;
 
@@ -916,10 +898,10 @@ static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
 
         /* Job is a bit different between memory and IO */
         if (res->flags & IORESOURCE_MEM) {
-                /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been
-                 * initialized by somebody
-                 */
-                if (res->start != hose->pci_mem_offset)
+                pcibios_resource_to_bus(dev, &region, res);
+
+                /* If the BAR is non-0 then it's probably been initialized */
+                if (region.start != 0)
                         return 0;
 
                 /* The BAR is 0, let's check if memory decoding is enabled on
@@ -931,11 +913,11 @@ static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
 
                 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
                  * resources covers that starting address (0 then it's good enough for
-                 * us for memory
+                 * us for memory space)
                  */
                 for (i = 0; i < 3; i++) {
                         if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
-                            hose->mem_resources[i].start == hose->pci_mem_offset)
+                            hose->mem_resources[i].start == hose->mem_offset[i])
                                 return 0;
                 }
 
@@ -1023,6 +1005,27 @@ void pcibios_setup_bus_self(struct pci_bus *bus)
                 ppc_md.pci_dma_bus_setup(bus);
 }
 
+void pcibios_setup_device(struct pci_dev *dev)
+{
+        /* Fixup NUMA node as it may not be setup yet by the generic
+         * code and is needed by the DMA init
+         */
+        set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
+
+        /* Hook up default DMA ops */
+        set_dma_ops(&dev->dev, pci_dma_ops);
+        set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
+
+        /* Additional platform DMA/iommu setup */
+        if (ppc_md.pci_dma_dev_setup)
+                ppc_md.pci_dma_dev_setup(dev);
+
+        /* Read default IRQs and fixup if necessary */
+        pci_read_irq_line(dev);
+        if (ppc_md.pci_irq_fixup)
+                ppc_md.pci_irq_fixup(dev);
+}
+
 void pcibios_setup_bus_devices(struct pci_bus *bus)
 {
         struct pci_dev *dev;
@@ -1037,23 +1040,7 @@ void pcibios_setup_bus_devices(struct pci_bus *bus)
                 if (dev->is_added)
                         continue;
 
-                /* Fixup NUMA node as it may not be setup yet by the generic
-                 * code and is needed by the DMA init
-                 */
-                set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
-
-                /* Hook up default DMA ops */
-                set_dma_ops(&dev->dev, pci_dma_ops);
-                set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
-
-                /* Additional platform DMA/iommu setup */
-                if (ppc_md.pci_dma_dev_setup)
-                        ppc_md.pci_dma_dev_setup(dev);
-
-                /* Read default IRQs and fixup if necessary */
-                pci_read_irq_line(dev);
-                if (ppc_md.pci_irq_fixup)
-                        ppc_md.pci_irq_fixup(dev);
+                pcibios_setup_device(dev);
         }
 }
 
@@ -1367,10 +1354,9 @@ static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
 
  no_io:
         /* Check for memory */
-        offset = hose->pci_mem_offset;
-        pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
         for (i = 0; i < 3; i++) {
                 pres = &hose->mem_resources[i];
+                offset = hose->mem_offset[i];
                 if (!(pres->flags & IORESOURCE_MEM))
                         continue;
                 pr_debug("hose mem res: %pR\n", pres);
@@ -1494,6 +1480,10 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
                 if (ppc_md.pcibios_enable_device_hook(dev))
                         return -EINVAL;
 
+        /* avoid pcie irq fix up impact on cardbus */
+        if (dev->hdr_type != PCI_HEADER_TYPE_CARDBUS)
+                pcibios_setup_device(dev);
+
         return pci_enable_resources(dev, mask);
 }
 
@@ -1506,6 +1496,7 @@ static void pcibios_setup_phb_resources(struct pci_controller *hose,
                                         struct list_head *resources)
 {
         struct resource *res;
+        resource_size_t offset;
         int i;
 
         /* Hookup PHB IO resource */
@@ -1515,49 +1506,37 @@ static void pcibios_setup_phb_resources(struct pci_controller *hose,
                 printk(KERN_WARNING "PCI: I/O resource not set for host"
                        " bridge %s (domain %d)\n",
                        hose->dn->full_name, hose->global_number);
-#ifdef CONFIG_PPC32
-                /* Workaround for lack of IO resource only on 32-bit */
-                res->start = (unsigned long)hose->io_base_virt - isa_io_base;
-                res->end = res->start + IO_SPACE_LIMIT;
-                res->flags = IORESOURCE_IO;
-#endif /* CONFIG_PPC32 */
-        }
+        } else {
+                offset = pcibios_io_space_offset(hose);
 
-        pr_debug("PCI: PHB IO resource    = %016llx-%016llx [%lx]\n",
-                 (unsigned long long)res->start,
-                 (unsigned long long)res->end,
-                 (unsigned long)res->flags);
-        pci_add_resource_offset(resources, res, pcibios_io_space_offset(hose));
+                pr_debug("PCI: PHB IO resource    = %08llx-%08llx [%lx] off 0x%08llx\n",
+                         (unsigned long long)res->start,
+                         (unsigned long long)res->end,
+                         (unsigned long)res->flags,
+                         (unsigned long long)offset);
+                pci_add_resource_offset(resources, res, offset);
+        }
 
         /* Hookup PHB Memory resources */
         for (i = 0; i < 3; ++i) {
                 res = &hose->mem_resources[i];
                 if (!res->flags) {
-                        if (i > 0)
-                                continue;
                         printk(KERN_ERR "PCI: Memory resource 0 not set for "
                                "host bridge %s (domain %d)\n",
                                hose->dn->full_name, hose->global_number);
-#ifdef CONFIG_PPC32
-                        /* Workaround for lack of MEM resource only on 32-bit */
-                        res->start = hose->pci_mem_offset;
-                        res->end = (resource_size_t)-1LL;
-                        res->flags = IORESOURCE_MEM;
-#endif /* CONFIG_PPC32 */
+                        continue;
                 }
+                offset = hose->mem_offset[i];
 
-                pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i,
+
+                pr_debug("PCI: PHB MEM resource %d = %08llx-%08llx [%lx] off 0x%08llx\n", i,
                          (unsigned long long)res->start,
                          (unsigned long long)res->end,
-                         (unsigned long)res->flags);
-                pci_add_resource_offset(resources, res, hose->pci_mem_offset);
-        }
-
-        pr_debug("PCI: PHB MEM offset     = %016llx\n",
-                 (unsigned long long)hose->pci_mem_offset);
-        pr_debug("PCI: PHB IO  offset     = %08lx\n",
-                 (unsigned long)hose->io_base_virt - _IO_BASE);
+                         (unsigned long)res->flags,
+                         (unsigned long long)offset);
 
+                pci_add_resource_offset(resources, res, offset);
+        }
 }
 
 /*
@@ -1725,3 +1704,15 @@ static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
+
+static void fixup_vga(struct pci_dev *pdev)
+{
+        u16 cmd;
+
+        pci_read_config_word(pdev, PCI_COMMAND, &cmd);
+        if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device())
+                vga_set_default_device(pdev);
+
+}
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
+                              PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);
diff --git a/arch/powerpc/kernel/pci_32.c b/arch/powerpc/kernel/pci_32.c
index e37c2152acf4..432459c817fa 100644
--- a/arch/powerpc/kernel/pci_32.c
+++ b/arch/powerpc/kernel/pci_32.c
@@ -295,7 +295,7 @@ long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
         case IOBASE_BRIDGE_NUMBER:
                 return (long)hose->first_busno;
         case IOBASE_MEMORY:
-                return (long)hose->pci_mem_offset;
+                return (long)hose->mem_offset[0];
         case IOBASE_IO:
                 return (long)hose->io_base_phys;
         case IOBASE_ISA_IO:
diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c
index 51a133a78a09..873050d26840 100644
--- a/arch/powerpc/kernel/pci_64.c
+++ b/arch/powerpc/kernel/pci_64.c
@@ -246,7 +246,7 @@ long sys_pciconfig_iobase(long which, unsigned long in_bus,
         case IOBASE_BRIDGE_NUMBER:
                 return (long)hose->first_busno;
         case IOBASE_MEMORY:
-                return (long)hose->pci_mem_offset;
+                return (long)hose->mem_offset[0];
         case IOBASE_IO:
                 return (long)hose->io_base_phys;
         case IOBASE_ISA_IO:
diff --git a/arch/powerpc/kernel/proc_powerpc.c b/arch/powerpc/kernel/proc_powerpc.c
index f19d0bdc3241..feb8580fdc84 100644
--- a/arch/powerpc/kernel/proc_powerpc.c
+++ b/arch/powerpc/kernel/proc_powerpc.c
@@ -32,8 +32,6 @@
 static loff_t page_map_seek( struct file *file, loff_t off, int whence)
 {
         loff_t new;
-        struct proc_dir_entry *dp = PDE(file_inode(file));
-
         switch(whence) {
         case 0:
                 new = off;
@@ -42,12 +40,12 @@ static loff_t page_map_seek( struct file *file, loff_t off, int whence)
                 new = file->f_pos + off;
                 break;
         case 2:
-                new = dp->size + off;
+                new = PAGE_SIZE + off;
                 break;
         default:
                 return -EINVAL;
         }
-        if ( new < 0 || new > dp->size )
+        if ( new < 0 || new > PAGE_SIZE )
                 return -EINVAL;
         return (file->f_pos = new);
 }
@@ -55,19 +53,18 @@ static loff_t page_map_seek( struct file *file, loff_t off, int whence)
 static ssize_t page_map_read( struct file *file, char __user *buf, size_t nbytes,
                               loff_t *ppos)
 {
-        struct proc_dir_entry *dp = PDE(file_inode(file));
-        return simple_read_from_buffer(buf, nbytes, ppos, dp->data, dp->size);
+        return simple_read_from_buffer(buf, nbytes, ppos,
+                        PDE_DATA(file_inode(file)), PAGE_SIZE);
 }
 
 static int page_map_mmap( struct file *file, struct vm_area_struct *vma )
 {
-        struct proc_dir_entry *dp = PDE(file_inode(file));
-
-        if ((vma->vm_end - vma->vm_start) > dp->size)
+        if ((vma->vm_end - vma->vm_start) > PAGE_SIZE)
                 return -EINVAL;
 
-        remap_pfn_range(vma, vma->vm_start, __pa(dp->data) >> PAGE_SHIFT,
-                                                dp->size, vma->vm_page_prot);
+        remap_pfn_range(vma, vma->vm_start,
+                        __pa(PDE_DATA(file_inode(file))) >> PAGE_SHIFT,
+                        PAGE_SIZE, vma->vm_page_prot);
         return 0;
 }
 
@@ -86,7 +83,7 @@ static int __init proc_ppc64_init(void)
                                &page_map_fops, vdso_data);
         if (!pde)
                 return 1;
-        pde->size = PAGE_SIZE;
+        proc_set_size(pde, PAGE_SIZE);
 
         return 0;
 }
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 16e77a81ab4f..ceb4e7b62cf4 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -831,6 +831,8 @@ void show_regs(struct pt_regs * regs)
 {
         int i, trap;
 
+        show_regs_print_info(KERN_DEFAULT);
+
         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
                regs->nip, regs->link, regs->ctr);
         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
@@ -850,12 +852,6 @@ void show_regs(struct pt_regs * regs)
 #else
                 printk("DAR: "REG", DSISR: %08lx\n", regs->dar, regs->dsisr);
 #endif
-        printk("TASK = %p[%d] '%s' THREAD: %p",
-               current, task_pid_nr(current), current->comm, task_thread_info(current));
-
-#ifdef CONFIG_SMP
-        printk(" CPU: %d", raw_smp_processor_id());
-#endif /* CONFIG_SMP */
 
         for (i = 0;  i < 32;  i++) {
                 if ((i % REGS_PER_LINE) == 0)
@@ -912,10 +908,6 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
         flush_altivec_to_thread(src);
         flush_vsx_to_thread(src);
         flush_spe_to_thread(src);
-#ifdef CONFIG_HAVE_HW_BREAKPOINT
-        flush_ptrace_hw_breakpoint(src);
-#endif /* CONFIG_HAVE_HW_BREAKPOINT */
-
         *dst = *src;
         return 0;
 }
@@ -986,6 +978,10 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
                                 _ALIGN_UP(sizeof(struct thread_info), 16);
 
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+        p->thread.ptrace_bps[0] = NULL;
+#endif
+
 #ifdef CONFIG_PPC_STD_MMU_64
         if (mmu_has_feature(MMU_FTR_SLB)) {
                 unsigned long sp_vsid;
@@ -1362,12 +1358,6 @@ void show_stack(struct task_struct *tsk, unsigned long *stack)
         } while (count++ < kstack_depth_to_print);
 }
 
-void dump_stack(void)
-{
-        show_stack(current, NULL);
-}
-EXPORT_SYMBOL(dump_stack);
-
 #ifdef CONFIG_PPC64
 /* Called with hard IRQs off */
 void __ppc64_runlatch_on(void)
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 13f8d168b3f1..5eccda9fd33f 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -627,16 +627,11 @@ static void __init early_cmdline_parse(void)
 
 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
 /*
- * There are two methods for telling firmware what our capabilities are.
- * Newer machines have an "ibm,client-architecture-support" method on the
- * root node.  For older machines, we have to call the "process-elf-header"
- * method in the /packages/elf-loader node, passing it a fake 32-bit
- * ELF header containing a couple of PT_NOTE sections that contain
- * structures that contain various information.
- */
-
-/*
- * New method - extensible architecture description vector.
+ * The architecture vector has an array of PVR mask/value pairs,
+ * followed by # option vectors - 1, followed by the option vectors.
+ *
+ * See prom.h for the definition of the bits specified in the
+ * architecture vector.
  *
  * Because the description vector contains a mix of byte and word
  * values, we declare it as an unsigned char array, and use this
@@ -645,65 +640,7 @@ static void __init early_cmdline_parse(void)
 #define W(x)    ((x) >> 24) & 0xff, ((x) >> 16) & 0xff, \
                 ((x) >> 8) & 0xff, (x) & 0xff
 
-/* Option vector bits - generic bits in byte 1 */
-#define OV_IGNORE               0x80    /* ignore this vector */
-#define OV_CESSATION_POLICY     0x40    /* halt if unsupported option present*/
-
-/* Option vector 1: processor architectures supported */
-#define OV1_PPC_2_00            0x80    /* set if we support PowerPC 2.00 */
-#define OV1_PPC_2_01            0x40    /* set if we support PowerPC 2.01 */
-#define OV1_PPC_2_02            0x20    /* set if we support PowerPC 2.02 */
-#define OV1_PPC_2_03            0x10    /* set if we support PowerPC 2.03 */
-#define OV1_PPC_2_04            0x08    /* set if we support PowerPC 2.04 */
-#define OV1_PPC_2_05            0x04    /* set if we support PowerPC 2.05 */
-#define OV1_PPC_2_06            0x02    /* set if we support PowerPC 2.06 */
-#define OV1_PPC_2_07            0x01    /* set if we support PowerPC 2.07 */
-
-/* Option vector 2: Open Firmware options supported */
-#define OV2_REAL_MODE           0x20    /* set if we want OF in real mode */
-
-/* Option vector 3: processor options supported */
-#define OV3_FP                  0x80    /* floating point */
-#define OV3_VMX                 0x40    /* VMX/Altivec */
-#define OV3_DFP                 0x20    /* decimal FP */
-
-/* Option vector 4: IBM PAPR implementation */
-#define OV4_MIN_ENT_CAP         0x01    /* minimum VP entitled capacity */
-
-/* Option vector 5: PAPR/OF options supported */
-#define OV5_LPAR                0x80    /* logical partitioning supported */
-#define OV5_SPLPAR              0x40    /* shared-processor LPAR supported */
-/* ibm,dynamic-reconfiguration-memory property supported */
-#define OV5_DRCONF_MEMORY       0x20
-#define OV5_LARGE_PAGES         0x10    /* large pages supported */
-#define OV5_DONATE_DEDICATE_CPU 0x02    /* donate dedicated CPU support */
-/* PCIe/MSI support.  Without MSI full PCIe is not supported */
-#ifdef CONFIG_PCI_MSI
-#define OV5_MSI                 0x01    /* PCIe/MSI support */
-#else
-#define OV5_MSI                 0x00
-#endif /* CONFIG_PCI_MSI */
-#ifdef CONFIG_PPC_SMLPAR
-#define OV5_CMO                 0x80    /* Cooperative Memory Overcommitment */
-#define OV5_XCMO                        0x40    /* Page Coalescing */
-#else
-#define OV5_CMO                 0x00
-#define OV5_XCMO                        0x00
-#endif
-#define OV5_TYPE1_AFFINITY      0x80    /* Type 1 NUMA affinity */
-#define OV5_PFO_HW_RNG          0x80    /* PFO Random Number Generator */
-#define OV5_PFO_HW_842          0x40    /* PFO Compression Accelerator */
-#define OV5_PFO_HW_ENCR         0x20    /* PFO Encryption Accelerator */
-#define OV5_SUB_PROCESSORS      0x01    /* 1,2,or 4 Sub-Processors supported */
-
-/* Option Vector 6: IBM PAPR hints */
-#define OV6_LINUX               0x02    /* Linux is our OS */
-
-/*
- * The architecture vector has an array of PVR mask/value pairs,
- * followed by # option vectors - 1, followed by the option vectors.
- */
-static unsigned char ibm_architecture_vec[] = {
+unsigned char ibm_architecture_vec[] = {
         W(0xfffe0000), W(0x003a0000),   /* POWER5/POWER5+ */
         W(0xffff0000), W(0x003e0000),   /* POWER6 */
         W(0xffff0000), W(0x003f0000),   /* POWER7 */
@@ -747,11 +684,21 @@ static unsigned char ibm_architecture_vec[] = {
         /* option vector 5: PAPR/OF options */
         19 - 2,                         /* length */
         0,                              /* don't ignore, don't halt */
-        OV5_LPAR | OV5_SPLPAR | OV5_LARGE_PAGES | OV5_DRCONF_MEMORY |
-        OV5_DONATE_DEDICATE_CPU | OV5_MSI,
+        OV5_FEAT(OV5_LPAR) | OV5_FEAT(OV5_SPLPAR) | OV5_FEAT(OV5_LARGE_PAGES) |
+        OV5_FEAT(OV5_DRCONF_MEMORY) | OV5_FEAT(OV5_DONATE_DEDICATE_CPU) |
+#ifdef CONFIG_PCI_MSI
+        /* PCIe/MSI support.  Without MSI full PCIe is not supported */
+        OV5_FEAT(OV5_MSI),
+#else
         0,
-        OV5_CMO | OV5_XCMO,
-        OV5_TYPE1_AFFINITY,
+#endif
+        0,
+#ifdef CONFIG_PPC_SMLPAR
+        OV5_FEAT(OV5_CMO) | OV5_FEAT(OV5_XCMO),
+#else
+        0,
+#endif
+        OV5_FEAT(OV5_TYPE1_AFFINITY) | OV5_FEAT(OV5_PRRN),
         0,
         0,
         0,
@@ -765,8 +712,9 @@ static unsigned char ibm_architecture_vec[] = {
         0,
         0,
         0,
-        OV5_PFO_HW_RNG | OV5_PFO_HW_ENCR | OV5_PFO_HW_842,
-        OV5_SUB_PROCESSORS,
+        OV5_FEAT(OV5_PFO_HW_RNG) | OV5_FEAT(OV5_PFO_HW_ENCR) |
+        OV5_FEAT(OV5_PFO_HW_842),
+        OV5_FEAT(OV5_SUB_PROCESSORS),
         /* option vector 6: IBM PAPR hints */
         4 - 2,                          /* length */
         0,
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index f9b30c68ba47..3b14d320e69f 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -180,9 +180,10 @@ static int set_user_msr(struct task_struct *task, unsigned long msr)
 }
 
 #ifdef CONFIG_PPC64
-static unsigned long get_user_dscr(struct task_struct *task)
+static int get_user_dscr(struct task_struct *task, unsigned long *data)
 {
-        return task->thread.dscr;
+        *data = task->thread.dscr;
+        return 0;
 }
 
 static int set_user_dscr(struct task_struct *task, unsigned long dscr)
@@ -192,7 +193,7 @@ static int set_user_dscr(struct task_struct *task, unsigned long dscr)
         return 0;
 }
 #else
-static unsigned long get_user_dscr(struct task_struct *task)
+static int get_user_dscr(struct task_struct *task, unsigned long *data)
 {
         return -EIO;
 }
@@ -216,19 +217,23 @@ static int set_user_trap(struct task_struct *task, unsigned long trap)
 /*
  * Get contents of register REGNO in task TASK.
  */
-unsigned long ptrace_get_reg(struct task_struct *task, int regno)
+int ptrace_get_reg(struct task_struct *task, int regno, unsigned long *data)
 {
-        if (task->thread.regs == NULL)
+        if ((task->thread.regs == NULL) || !data)
                 return -EIO;
 
-        if (regno == PT_MSR)
-                return get_user_msr(task);
+        if (regno == PT_MSR) {
+                *data = get_user_msr(task);
+                return 0;
+        }
 
         if (regno == PT_DSCR)
-                return get_user_dscr(task);
+                return get_user_dscr(task, data);
 
-        if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long)))
-                return ((unsigned long *)task->thread.regs)[regno];
+        if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) {
+                *data = ((unsigned long *)task->thread.regs)[regno];
+                return 0;
+        }
 
         return -EIO;
 }
@@ -1560,7 +1565,9 @@ long arch_ptrace(struct task_struct *child, long request,
 
                 CHECK_FULL_REGS(child->thread.regs);
                 if (index < PT_FPR0) {
-                        tmp = ptrace_get_reg(child, (int) index);
+                        ret = ptrace_get_reg(child, (int) index, &tmp);
+                        if (ret)
+                                break;
                 } else {
                         unsigned int fpidx = index - PT_FPR0;
 
@@ -1637,6 +1644,8 @@ long arch_ptrace(struct task_struct *child, long request,
                 dbginfo.sizeof_condition = 0;
 #ifdef CONFIG_HAVE_HW_BREAKPOINT
                 dbginfo.features = PPC_DEBUG_FEATURE_DATA_BP_RANGE;
+                if (cpu_has_feature(CPU_FTR_DAWR))
+                        dbginfo.features |= PPC_DEBUG_FEATURE_DATA_BP_DAWR;
 #else
                 dbginfo.features = 0;
 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
diff --git a/arch/powerpc/kernel/ptrace32.c b/arch/powerpc/kernel/ptrace32.c
index c0244e766834..f51599e941c7 100644
--- a/arch/powerpc/kernel/ptrace32.c
+++ b/arch/powerpc/kernel/ptrace32.c
@@ -95,7 +95,9 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
 
                 CHECK_FULL_REGS(child->thread.regs);
                 if (index < PT_FPR0) {
-                        tmp = ptrace_get_reg(child, index);
+                        ret = ptrace_get_reg(child, index, &tmp);
+                        if (ret)
+                                break;
                 } else {
                         flush_fp_to_thread(child);
                         /*
@@ -148,7 +150,11 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                         tmp = ((u64 *)child->thread.fpr)
                                 [FPRINDEX_3264(numReg)];
                 } else { /* register within PT_REGS struct */
-                        tmp = ptrace_get_reg(child, numReg);
+                        unsigned long tmp2;
+                        ret = ptrace_get_reg(child, numReg, &tmp2);
+                        if (ret)
+                                break;
+                        tmp = tmp2;
                 } 
                 reg32bits = ((u32*)&tmp)[part];
                 ret = put_user(reg32bits, (u32 __user *)data);
@@ -232,7 +238,10 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                         break;
                 CHECK_FULL_REGS(child->thread.regs);
                 if (numReg < PT_FPR0) {
-                        unsigned long freg = ptrace_get_reg(child, numReg);
+                        unsigned long freg;
+                        ret = ptrace_get_reg(child, numReg, &freg);
+                        if (ret)
+                                break;
                         if (index % 2)
                                 freg = (freg & ~0xfffffffful) | (data & 0xfffffffful);
                         else
diff --git a/arch/powerpc/kernel/rtas_flash.c b/arch/powerpc/kernel/rtas_flash.c
index c642f0132988..5b3022470126 100644
--- a/arch/powerpc/kernel/rtas_flash.c
+++ b/arch/powerpc/kernel/rtas_flash.c
@@ -57,13 +57,31 @@
 #define VALIDATE_READY         -1001 /* Firmware image ready for validation */
 #define VALIDATE_PARAM_ERR     -3    /* RTAS Parameter Error */
 #define VALIDATE_HW_ERR        -1    /* RTAS Hardware Error */
-#define VALIDATE_TMP_UPDATE    0     /* Validate Return Status */
-#define VALIDATE_FLASH_AUTH    1     /* Validate Return Status */
-#define VALIDATE_INVALID_IMG   2     /* Validate Return Status */
-#define VALIDATE_CUR_UNKNOWN   3     /* Validate Return Status */
-#define VALIDATE_TMP_COMMIT_DL 4     /* Validate Return Status */
-#define VALIDATE_TMP_COMMIT    5     /* Validate Return Status */
-#define VALIDATE_TMP_UPDATE_DL 6     /* Validate Return Status */
+
+/* ibm,validate-flash-image update result tokens */
+#define VALIDATE_TMP_UPDATE    0     /* T side will be updated */
+#define VALIDATE_FLASH_AUTH    1     /* Partition does not have authority */
+#define VALIDATE_INVALID_IMG   2     /* Candidate image is not valid */
+#define VALIDATE_CUR_UNKNOWN   3     /* Current fixpack level is unknown */
+/*
+ * Current T side will be committed to P side before being replace with new
+ * image, and the new image is downlevel from current image
+ */
+#define VALIDATE_TMP_COMMIT_DL 4
+/*
+ * Current T side will be committed to P side before being replaced with new
+ * image
+ */
+#define VALIDATE_TMP_COMMIT    5
+/*
+ * T side will be updated with a downlevel image
+ */
+#define VALIDATE_TMP_UPDATE_DL 6
+/*
+ * The candidate image's release date is later than the system's firmware
+ * service entitlement date - service warranty period has expired
+ */
+#define VALIDATE_OUT_OF_WRNTY  7
 
 /* ibm,manage-flash-image operation tokens */
 #define RTAS_REJECT_TMP_IMG   0
@@ -102,9 +120,10 @@ static struct kmem_cache *flash_block_cache = NULL;
 
 #define FLASH_BLOCK_LIST_VERSION (1UL)
 
-/* Local copy of the flash block list.
- * We only allow one open of the flash proc file and create this
- * list as we go.  The rtas_firmware_flash_list varable will be
+/*
+ * Local copy of the flash block list.
+ *
+ * The rtas_firmware_flash_list varable will be
  * set once the data is fully read.
  *
  * For convenience as we build the list we use virtual addrs,
@@ -125,23 +144,23 @@ struct rtas_update_flash_t
 struct rtas_manage_flash_t
 {
         int status;                     /* Returned status */
-        unsigned int op;                /* Reject or commit image */
 };
 
 /* Status int must be first member of struct */
 struct rtas_validate_flash_t
 {
         int status;                     /* Returned status */   
-        char buf[VALIDATE_BUF_SIZE];    /* Candidate image buffer */
+        char *buf;                      /* Candidate image buffer */
         unsigned int buf_size;          /* Size of image buf */
         unsigned int update_results;    /* Update results token */
 };
 
-static DEFINE_SPINLOCK(flash_file_open_lock);
-static struct proc_dir_entry *firmware_flash_pde;
-static struct proc_dir_entry *firmware_update_pde;
-static struct proc_dir_entry *validate_pde;
-static struct proc_dir_entry *manage_pde;
+static struct rtas_update_flash_t rtas_update_flash_data;
+static struct rtas_manage_flash_t rtas_manage_flash_data;
+static struct rtas_validate_flash_t rtas_validate_flash_data;
+static DEFINE_MUTEX(rtas_update_flash_mutex);
+static DEFINE_MUTEX(rtas_manage_flash_mutex);
+static DEFINE_MUTEX(rtas_validate_flash_mutex);
 
 /* Do simple sanity checks on the flash image. */
 static int flash_list_valid(struct flash_block_list *flist)
@@ -191,10 +210,10 @@ static void free_flash_list(struct flash_block_list *f)
 
 static int rtas_flash_release(struct inode *inode, struct file *file)
 {
-        struct proc_dir_entry *dp = PDE(file_inode(file));
-        struct rtas_update_flash_t *uf;
-        
-        uf = (struct rtas_update_flash_t *) dp->data;
+        struct rtas_update_flash_t *const uf = &rtas_update_flash_data;
+
+        mutex_lock(&rtas_update_flash_mutex);
+
         if (uf->flist) {    
                 /* File was opened in write mode for a new flash attempt */
                 /* Clear saved list */
@@ -214,13 +233,14 @@ static int rtas_flash_release(struct inode *inode, struct file *file)
                 uf->flist = NULL;
         }
 
-        atomic_dec(&dp->count);
+        mutex_unlock(&rtas_update_flash_mutex);
         return 0;
 }
 
-static void get_flash_status_msg(int status, char *buf)
+static size_t get_flash_status_msg(int status, char *buf)
 {
-        char *msg;
+        const char *msg;
+        size_t len;
 
         switch (status) {
         case FLASH_AUTH:
@@ -242,36 +262,47 @@ static void get_flash_status_msg(int status, char *buf)
                 msg = "ready: firmware image ready for flash on reboot\n";
                 break;
         default:
-                sprintf(buf, "error: unexpected status value %d\n", status);
-                return;
+                return sprintf(buf, "error: unexpected status value %d\n",
+                               status);
         }
 
-        strcpy(buf, msg);       
+        len = strlen(msg);
+        memcpy(buf, msg, len + 1);
+        return len;
 }
 
 /* Reading the proc file will show status (not the firmware contents) */
-static ssize_t rtas_flash_read(struct file *file, char __user *buf,
-                               size_t count, loff_t *ppos)
+static ssize_t rtas_flash_read_msg(struct file *file, char __user *buf,
+                                   size_t count, loff_t *ppos)
 {
-        struct proc_dir_entry *dp = PDE(file_inode(file));
-        struct rtas_update_flash_t *uf;
+        struct rtas_update_flash_t *const uf = &rtas_update_flash_data;
         char msg[RTAS_MSG_MAXLEN];
+        size_t len;
+        int status;
 
-        uf = dp->data;
-
-        if (!strcmp(dp->name, FIRMWARE_FLASH_NAME)) {
-                get_flash_status_msg(uf->status, msg);
-        } else {           /* FIRMWARE_UPDATE_NAME */
-                sprintf(msg, "%d\n", uf->status);
-        }
+        mutex_lock(&rtas_update_flash_mutex);
+        status = uf->status;
+        mutex_unlock(&rtas_update_flash_mutex);
 
-        return simple_read_from_buffer(buf, count, ppos, msg, strlen(msg));
+        /* Read as text message */
+        len = get_flash_status_msg(status, msg);
+        return simple_read_from_buffer(buf, count, ppos, msg, len);
 }
 
-/* constructor for flash_block_cache */
-void rtas_block_ctor(void *ptr)
+static ssize_t rtas_flash_read_num(struct file *file, char __user *buf,
+                                   size_t count, loff_t *ppos)
 {
-        memset(ptr, 0, RTAS_BLK_SIZE);
+        struct rtas_update_flash_t *const uf = &rtas_update_flash_data;
+        char msg[RTAS_MSG_MAXLEN];
+        int status;
+
+        mutex_lock(&rtas_update_flash_mutex);
+        status = uf->status;
+        mutex_unlock(&rtas_update_flash_mutex);
+
+        /* Read as number */
+        sprintf(msg, "%d\n", status);
+        return simple_read_from_buffer(buf, count, ppos, msg, strlen(msg));
 }
 
 /* We could be much more efficient here.  But to keep this function
@@ -282,25 +313,24 @@ void rtas_block_ctor(void *ptr)
 static ssize_t rtas_flash_write(struct file *file, const char __user *buffer,
                                 size_t count, loff_t *off)
 {
-        struct proc_dir_entry *dp = PDE(file_inode(file));
-        struct rtas_update_flash_t *uf;
+        struct rtas_update_flash_t *const uf = &rtas_update_flash_data;
         char *p;
-        int next_free;
+        int next_free, rc;
         struct flash_block_list *fl;
 
-        uf = (struct rtas_update_flash_t *) dp->data;
+        mutex_lock(&rtas_update_flash_mutex);
 
         if (uf->status == FLASH_AUTH || count == 0)
-                return count;   /* discard data */
+                goto out;       /* discard data */
 
         /* In the case that the image is not ready for flashing, the memory
          * allocated for the block list will be freed upon the release of the 
          * proc file
          */
         if (uf->flist == NULL) {
-                uf->flist = kmem_cache_alloc(flash_block_cache, GFP_KERNEL);
+                uf->flist = kmem_cache_zalloc(flash_block_cache, GFP_KERNEL);
                 if (!uf->flist)
-                        return -ENOMEM;
+                        goto nomem;
         }
 
         fl = uf->flist;
@@ -309,63 +339,48 @@ static ssize_t rtas_flash_write(struct file *file, const char __user *buffer,
         next_free = fl->num_blocks;
         if (next_free == FLASH_BLOCKS_PER_NODE) {
                 /* Need to allocate another block_list */
-                fl->next = kmem_cache_alloc(flash_block_cache, GFP_KERNEL);
+                fl->next = kmem_cache_zalloc(flash_block_cache, GFP_KERNEL);
                 if (!fl->next)
-                        return -ENOMEM;
+                        goto nomem;
                 fl = fl->next;
                 next_free = 0;
         }
 
         if (count > RTAS_BLK_SIZE)
                 count = RTAS_BLK_SIZE;
-        p = kmem_cache_alloc(flash_block_cache, GFP_KERNEL);
+        p = kmem_cache_zalloc(flash_block_cache, GFP_KERNEL);
         if (!p)
-                return -ENOMEM;
+                goto nomem;
         
         if(copy_from_user(p, buffer, count)) {
                 kmem_cache_free(flash_block_cache, p);
-                return -EFAULT;
+                rc = -EFAULT;
+                goto error;
         }
         fl->blocks[next_free].data = p;
         fl->blocks[next_free].length = count;
         fl->num_blocks++;
-
+out:
+        mutex_unlock(&rtas_update_flash_mutex);
         return count;
-}
 
-static int rtas_excl_open(struct inode *inode, struct file *file)
-{
-        struct proc_dir_entry *dp = PDE(inode);
-
-        /* Enforce exclusive open with use count of PDE */
-        spin_lock(&flash_file_open_lock);
-        if (atomic_read(&dp->count) > 2) {
-                spin_unlock(&flash_file_open_lock);
-                return -EBUSY;
-        }
-
-        atomic_inc(&dp->count);
-        spin_unlock(&flash_file_open_lock);
-        
-        return 0;
-}
-
-static int rtas_excl_release(struct inode *inode, struct file *file)
-{
-        struct proc_dir_entry *dp = PDE(inode);
-
-        atomic_dec(&dp->count);
-
-        return 0;
+nomem:
+        rc = -ENOMEM;
+error:
+        mutex_unlock(&rtas_update_flash_mutex);
+        return rc;
 }
 
-static void manage_flash(struct rtas_manage_flash_t *args_buf)
+/*
+ * Flash management routines.
+ */
+static void manage_flash(struct rtas_manage_flash_t *args_buf, unsigned int op)
 {
         s32 rc;
 
         do {
-                rc = rtas_call(rtas_token("ibm,manage-flash-image"), 1, 
-                               1, NULL, args_buf->op);
+                rc = rtas_call(rtas_token("ibm,manage-flash-image"), 1, 1,
+                               NULL, op);
         } while (rtas_busy_delay(rc));
 
         args_buf->status = rc;
@@ -374,55 +389,62 @@ static void manage_flash(struct rtas_manage_flash_t *args_buf)
 static ssize_t manage_flash_read(struct file *file, char __user *buf,
                                size_t count, loff_t *ppos)
 {
-        struct proc_dir_entry *dp = PDE(file_inode(file));
-        struct rtas_manage_flash_t *args_buf;
+        struct rtas_manage_flash_t *const args_buf = &rtas_manage_flash_data;
         char msg[RTAS_MSG_MAXLEN];
-        int msglen;
+        int msglen, status;
 
-        args_buf = dp->data;
-        if (args_buf == NULL)
-                return 0;
-
-        msglen = sprintf(msg, "%d\n", args_buf->status);
+        mutex_lock(&rtas_manage_flash_mutex);
+        status = args_buf->status;
+        mutex_unlock(&rtas_manage_flash_mutex);
 
+        msglen = sprintf(msg, "%d\n", status);
         return simple_read_from_buffer(buf, count, ppos, msg, msglen);
 }
 
 static ssize_t manage_flash_write(struct file *file, const char __user *buf,
                                 size_t count, loff_t *off)
 {
-        struct proc_dir_entry *dp = PDE(file_inode(file));
-        struct rtas_manage_flash_t *args_buf;
-        const char reject_str[] = "0";
-        const char commit_str[] = "1";
+        struct rtas_manage_flash_t *const args_buf = &rtas_manage_flash_data;
+        static const char reject_str[] = "0";
+        static const char commit_str[] = "1";
         char stkbuf[10];
-        int op;
+        int op, rc;
+
+        mutex_lock(&rtas_manage_flash_mutex);
 
-        args_buf = (struct rtas_manage_flash_t *) dp->data;
         if ((args_buf->status == MANAGE_AUTH) || (count == 0))
-                return count;
+                goto out;
                 
         op = -1;
         if (buf) {
                 if (count > 9) count = 9;
-                if (copy_from_user (stkbuf, buf, count)) {
-                        return -EFAULT;
-                }
+                rc = -EFAULT;
+                if (copy_from_user (stkbuf, buf, count))
+                        goto error;
                 if (strncmp(stkbuf, reject_str, strlen(reject_str)) == 0) 
                         op = RTAS_REJECT_TMP_IMG;
                 else if (strncmp(stkbuf, commit_str, strlen(commit_str)) == 0) 
                         op = RTAS_COMMIT_TMP_IMG;
         }
         
-        if (op == -1)   /* buf is empty, or contains invalid string */
-                return -EINVAL;
-
-        args_buf->op = op;
-        manage_flash(args_buf);
+        if (op == -1) {   /* buf is empty, or contains invalid string */
+                rc = -EINVAL;
+                goto error;
+        }
 
+        manage_flash(args_buf, op);
+out:
+        mutex_unlock(&rtas_manage_flash_mutex);
         return count;
+
+error:
+        mutex_unlock(&rtas_manage_flash_mutex);
+        return rc;
 }
 
+/*
+ * Validation routines.
+ */
 static void validate_flash(struct rtas_validate_flash_t *args_buf)
 {
         int token = rtas_token("ibm,validate-flash-image");
@@ -462,14 +484,14 @@ static int get_validate_flash_msg(struct rtas_validate_flash_t *args_buf,
 static ssize_t validate_flash_read(struct file *file, char __user *buf,
                                size_t count, loff_t *ppos)
 {
-        struct proc_dir_entry *dp = PDE(file_inode(file));
-        struct rtas_validate_flash_t *args_buf;
+        struct rtas_validate_flash_t *const args_buf =
+                &rtas_validate_flash_data;
         char msg[RTAS_MSG_MAXLEN];
         int msglen;
 
-        args_buf = dp->data;
-
+        mutex_lock(&rtas_validate_flash_mutex);
         msglen = get_validate_flash_msg(args_buf, msg);
+        mutex_unlock(&rtas_validate_flash_mutex);
 
         return simple_read_from_buffer(buf, count, ppos, msg, msglen);
 }
@@ -477,24 +499,18 @@ static ssize_t validate_flash_read(struct file *file, char __user *buf,
 static ssize_t validate_flash_write(struct file *file, const char __user *buf,
                                     size_t count, loff_t *off)
 {
-        struct proc_dir_entry *dp = PDE(file_inode(file));
-        struct rtas_validate_flash_t *args_buf;
+        struct rtas_validate_flash_t *const args_buf =
+                &rtas_validate_flash_data;
         int rc;
 
-        args_buf = (struct rtas_validate_flash_t *) dp->data;
-
-        if (dp->data == NULL) {
-                dp->data = kmalloc(sizeof(struct rtas_validate_flash_t), 
-                                GFP_KERNEL);
-                if (dp->data == NULL) 
-                        return -ENOMEM;
-        }
+        mutex_lock(&rtas_validate_flash_mutex);
 
         /* We are only interested in the first 4K of the
          * candidate image */
         if ((*off >= VALIDATE_BUF_SIZE) || 
                 (args_buf->status == VALIDATE_AUTH)) {
                 *off += count;
+                mutex_unlock(&rtas_validate_flash_mutex);
                 return count;
         }
 
@@ -517,31 +533,29 @@ static ssize_t validate_flash_write(struct file *file, const char __user *buf,
         *off += count;
         rc = count;
 done:
-        if (rc < 0) {
-                kfree(dp->data);
-                dp->data = NULL;
-        }
+        mutex_unlock(&rtas_validate_flash_mutex);
         return rc;
 }
 
 static int validate_flash_release(struct inode *inode, struct file *file)
 {
-        struct proc_dir_entry *dp = PDE(file_inode(file));
-        struct rtas_validate_flash_t *args_buf;
+        struct rtas_validate_flash_t *const args_buf =
+                &rtas_validate_flash_data;
 
-        args_buf = (struct rtas_validate_flash_t *) dp->data;
+        mutex_lock(&rtas_validate_flash_mutex);
 
         if (args_buf->status == VALIDATE_READY) {
                 args_buf->buf_size = VALIDATE_BUF_SIZE;
                 validate_flash(args_buf);
         }
 
-        /* The matching atomic_inc was in rtas_excl_open() */
-        atomic_dec(&dp->count);
-
+        mutex_unlock(&rtas_validate_flash_mutex);
         return 0;
 }
 
+/*
+ * On-reboot flash update applicator.
+ */
 static void rtas_flash_firmware(int reboot_type)
 {
         unsigned long image_size;
@@ -634,75 +648,57 @@ static void rtas_flash_firmware(int reboot_type)
         spin_unlock(&rtas_data_buf_lock);
 }
 
-static void remove_flash_pde(struct proc_dir_entry *dp)
-{
-        if (dp) {
-                kfree(dp->data);
-                remove_proc_entry(dp->name, dp->parent);
-        }
-}
-
-static int initialize_flash_pde_data(const char *rtas_call_name,
-                                     size_t buf_size,
-                                     struct proc_dir_entry *dp)
-{
+/*
+ * Manifest of proc files to create
+ */
+struct rtas_flash_file {
+        const char *filename;
+        const char *rtas_call_name;
         int *status;
-        int token;
-
-        dp->data = kzalloc(buf_size, GFP_KERNEL);
-        if (dp->data == NULL)
-                return -ENOMEM;
-
-        /*
-         * This code assumes that the status int is the first member of the
-         * struct 
-         */
-        status = (int *) dp->data;
-        token = rtas_token(rtas_call_name);
-        if (token == RTAS_UNKNOWN_SERVICE)
-                *status = FLASH_AUTH;
-        else
-                *status = FLASH_NO_OP;
-
-        return 0;
-}
-
-static struct proc_dir_entry *create_flash_pde(const char *filename,
-                                               const struct file_operations *fops)
-{
-        return proc_create(filename, S_IRUSR | S_IWUSR, NULL, fops);
-}
-
-static const struct file_operations rtas_flash_operations = {
-        .owner          = THIS_MODULE,
-        .read           = rtas_flash_read,
-        .write          = rtas_flash_write,
-        .open           = rtas_excl_open,
-        .release        = rtas_flash_release,
-        .llseek         = default_llseek,
-};
-
-static const struct file_operations manage_flash_operations = {
-        .owner          = THIS_MODULE,
-        .read           = manage_flash_read,
-        .write          = manage_flash_write,
-        .open           = rtas_excl_open,
-        .release        = rtas_excl_release,
-        .llseek         = default_llseek,
+        const struct file_operations fops;
 };
 
-static const struct file_operations validate_flash_operations = {
-        .owner          = THIS_MODULE,
-        .read           = validate_flash_read,
-        .write          = validate_flash_write,
-        .open           = rtas_excl_open,
-        .release        = validate_flash_release,
-        .llseek         = default_llseek,
+static const struct rtas_flash_file rtas_flash_files[] = {
+        {
+                .filename       = "powerpc/rtas/" FIRMWARE_FLASH_NAME,
+                .rtas_call_name = "ibm,update-flash-64-and-reboot",
+                .status         = &rtas_update_flash_data.status,
+                .fops.read      = rtas_flash_read_msg,
+                .fops.write     = rtas_flash_write,
+                .fops.release   = rtas_flash_release,
+                .fops.llseek    = default_llseek,
+        },
+        {
+                .filename       = "powerpc/rtas/" FIRMWARE_UPDATE_NAME,
+                .rtas_call_name = "ibm,update-flash-64-and-reboot",
+                .status         = &rtas_update_flash_data.status,
+                .fops.read      = rtas_flash_read_num,
+                .fops.write     = rtas_flash_write,
+                .fops.release   = rtas_flash_release,
+                .fops.llseek    = default_llseek,
+        },
+        {
+                .filename       = "powerpc/rtas/" VALIDATE_FLASH_NAME,
+                .rtas_call_name = "ibm,validate-flash-image",
+                .status         = &rtas_validate_flash_data.status,
+                .fops.read      = validate_flash_read,
+                .fops.write     = validate_flash_write,
+                .fops.release   = validate_flash_release,
+                .fops.llseek    = default_llseek,
+        },
+        {
+                .filename       = "powerpc/rtas/" MANAGE_FLASH_NAME,
+                .rtas_call_name = "ibm,manage-flash-image",
+                .status         = &rtas_manage_flash_data.status,
+                .fops.read      = manage_flash_read,
+                .fops.write     = manage_flash_write,
+                .fops.llseek    = default_llseek,
+        }
 };
 
 static int __init rtas_flash_init(void)
 {
-        int rc;
+        int i;
 
         if (rtas_token("ibm,update-flash-64-and-reboot") ==
                        RTAS_UNKNOWN_SERVICE) {
@@ -710,93 +706,70 @@ static int __init rtas_flash_init(void)
                 return 1;
         }
 
-        firmware_flash_pde = create_flash_pde("powerpc/rtas/"
-                                              FIRMWARE_FLASH_NAME,
-                                              &rtas_flash_operations);
-        if (firmware_flash_pde == NULL) {
-                rc = -ENOMEM;
-                goto cleanup;
-        }
+        rtas_validate_flash_data.buf = kzalloc(VALIDATE_BUF_SIZE, GFP_KERNEL);
+        if (!rtas_validate_flash_data.buf)
+                return -ENOMEM;
 
-        rc = initialize_flash_pde_data("ibm,update-flash-64-and-reboot",
-                                       sizeof(struct rtas_update_flash_t), 
-                                       firmware_flash_pde);
-        if (rc != 0)
-                goto cleanup;
-
-        firmware_update_pde = create_flash_pde("powerpc/rtas/"
-                                               FIRMWARE_UPDATE_NAME,
-                                               &rtas_flash_operations);
-        if (firmware_update_pde == NULL) {
-                rc = -ENOMEM;
-                goto cleanup;
+        flash_block_cache = kmem_cache_create("rtas_flash_cache",
+                                              RTAS_BLK_SIZE, RTAS_BLK_SIZE, 0,
+                                              NULL);
+        if (!flash_block_cache) {
+                printk(KERN_ERR "%s: failed to create block cache\n",
+                                __func__);
+                goto enomem_buf;
         }
 
-        rc = initialize_flash_pde_data("ibm,update-flash-64-and-reboot",
-                                       sizeof(struct rtas_update_flash_t), 
-                                       firmware_update_pde);
-        if (rc != 0)
-                goto cleanup;
-
-        validate_pde = create_flash_pde("powerpc/rtas/" VALIDATE_FLASH_NAME,
-                                        &validate_flash_operations);
-        if (validate_pde == NULL) {
-                rc = -ENOMEM;
-                goto cleanup;
-        }
+        for (i = 0; i < ARRAY_SIZE(rtas_flash_files); i++) {
+                const struct rtas_flash_file *f = &rtas_flash_files[i];
+                int token;
 
-        rc = initialize_flash_pde_data("ibm,validate-flash-image",
-                                       sizeof(struct rtas_validate_flash_t), 
-                                       validate_pde);
-        if (rc != 0)
-                goto cleanup;
-
-        manage_pde = create_flash_pde("powerpc/rtas/" MANAGE_FLASH_NAME,
-                                      &manage_flash_operations);
-        if (manage_pde == NULL) {
-                rc = -ENOMEM;
-                goto cleanup;
-        }
+                if (!proc_create(f->filename, S_IRUSR | S_IWUSR, NULL, &f->fops))
+                        goto enomem;
 
-        rc = initialize_flash_pde_data("ibm,manage-flash-image",
-                                       sizeof(struct rtas_manage_flash_t),
-                                       manage_pde);
-        if (rc != 0)
-                goto cleanup;
+                /*
+                 * This code assumes that the status int is the first member of the
+                 * struct
+                 */
+                token = rtas_token(f->rtas_call_name);
+                if (token == RTAS_UNKNOWN_SERVICE)
+                        *f->status = FLASH_AUTH;
+                else
+                        *f->status = FLASH_NO_OP;
+        }
 
         rtas_flash_term_hook = rtas_flash_firmware;
-
-        flash_block_cache = kmem_cache_create("rtas_flash_cache",
-                                RTAS_BLK_SIZE, RTAS_BLK_SIZE, 0,
-                                rtas_block_ctor);
-        if (!flash_block_cache) {
-                printk(KERN_ERR "%s: failed to create block cache\n",
-                                __func__);
-                rc = -ENOMEM;
-                goto cleanup;
-        }
         return 0;
 
-cleanup:
-        remove_flash_pde(firmware_flash_pde);
-        remove_flash_pde(firmware_update_pde);
-        remove_flash_pde(validate_pde);
-        remove_flash_pde(manage_pde);
+enomem:
+        while (--i >= 0) {
+                const struct rtas_flash_file *f = &rtas_flash_files[i];
+                remove_proc_entry(f->filename, NULL);
+        }
 
-        return rc;
+        kmem_cache_destroy(flash_block_cache);
+enomem_buf:
+        kfree(rtas_validate_flash_data.buf);
+        return -ENOMEM;
 }
 
 static void __exit rtas_flash_cleanup(void)
 {
+        int i;
+
         rtas_flash_term_hook = NULL;
 
-        if (flash_block_cache)
-                kmem_cache_destroy(flash_block_cache);
+        if (rtas_firmware_flash_list) {
+                free_flash_list(rtas_firmware_flash_list);
+                rtas_firmware_flash_list = NULL;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(rtas_flash_files); i++) {
+                const struct rtas_flash_file *f = &rtas_flash_files[i];
+                remove_proc_entry(f->filename, NULL);
+        }
 
-        remove_flash_pde(firmware_flash_pde);
-        remove_flash_pde(firmware_update_pde);
-        remove_flash_pde(validate_pde);
-        remove_flash_pde(manage_pde);
+        kmem_cache_destroy(flash_block_cache);
+        kfree(rtas_validate_flash_data.buf);
 }
 
 module_init(rtas_flash_init);
diff --git a/arch/powerpc/kernel/rtas_pci.c b/arch/powerpc/kernel/rtas_pci.c
index 71cb20d6ec61..6e7b7cdeec65 100644
--- a/arch/powerpc/kernel/rtas_pci.c
+++ b/arch/powerpc/kernel/rtas_pci.c
@@ -201,7 +201,7 @@ static void python_countermeasures(struct device_node *dev)
         iounmap(chip_regs);
 }
 
-void __init init_pci_config_tokens (void)
+void __init init_pci_config_tokens(void)
 {
         read_pci_config = rtas_token("read-pci-config");
         write_pci_config = rtas_token("write-pci-config");
@@ -209,7 +209,7 @@ void __init init_pci_config_tokens (void)
         ibm_write_pci_config = rtas_token("ibm,write-pci-config");
 }
 
-unsigned long get_phb_buid (struct device_node *phb)
+unsigned long get_phb_buid(struct device_node *phb)
 {
         struct resource r;
 
diff --git a/arch/powerpc/kernel/rtasd.c b/arch/powerpc/kernel/rtasd.c
index 1045ff49cc6d..1130c53ad652 100644
--- a/arch/powerpc/kernel/rtasd.c
+++ b/arch/powerpc/kernel/rtasd.c
@@ -29,6 +29,7 @@
 #include <asm/nvram.h>
 #include <linux/atomic.h>
 #include <asm/machdep.h>
+#include <asm/topology.h>
 
 
 static DEFINE_SPINLOCK(rtasd_log_lock);
@@ -87,6 +88,8 @@ static char *rtas_event_type(int type)
                         return "Resource Deallocation Event";
                 case RTAS_TYPE_DUMP:
                         return "Dump Notification Event";
+                case RTAS_TYPE_PRRN:
+                        return "Platform Resource Reassignment Event";
         }
 
         return rtas_type[0];
@@ -265,9 +268,51 @@ void pSeries_log_error(char *buf, unsigned int err_type, int fatal)
                 spin_unlock_irqrestore(&rtasd_log_lock, s);
                 return;
         }
+}
+
+#ifdef CONFIG_PPC_PSERIES
+static s32 prrn_update_scope;
 
+static void prrn_work_fn(struct work_struct *work)
+{
+        /*
+         * For PRRN, we must pass the negative of the scope value in
+         * the RTAS event.
+         */
+        pseries_devicetree_update(-prrn_update_scope);
 }
 
+static DECLARE_WORK(prrn_work, prrn_work_fn);
+
+void prrn_schedule_update(u32 scope)
+{
+        flush_work(&prrn_work);
+        prrn_update_scope = scope;
+        schedule_work(&prrn_work);
+}
+
+static void handle_rtas_event(const struct rtas_error_log *log)
+{
+        if (log->type == RTAS_TYPE_PRRN) {
+                /* For PRRN Events the extended log length is used to denote
+                 * the scope for calling rtas update-nodes.
+                 */
+                if (prrn_is_enabled())
+                        prrn_schedule_update(log->extended_log_length);
+        }
+
+        return;
+}
+
+#else
+
+static void handle_rtas_event(const struct rtas_error_log *log)
+{
+        return;
+}
+
+#endif
+
 static int rtas_log_open(struct inode * inode, struct file * file)
 {
         return 0;
@@ -388,8 +433,10 @@ static void do_event_scan(void)
                         break;
                 }
 
-                if (error == 0)
+                if (error == 0) {
                         pSeries_log_error(logdata, ERR_TYPE_RTAS_LOG, 0);
+                        handle_rtas_event((struct rtas_error_log *)logdata);
+                }
 
         } while(error == 0);
 }
diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index bdc499c17872..63d051f5b7a5 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -621,12 +621,6 @@ int check_legacy_ioport(unsigned long base_port)
         case FDC_BASE: /* FDC1 */
                 np = of_find_node_by_type(NULL, "fdc");
                 break;
-#ifdef CONFIG_PPC_PREP
-        case _PIDXR:
-        case _PNPWRP:
-        case PNPBIOS_BASE:
-                /* implement me */
-#endif
         default:
                 /* ipmi is supposed to fail here */
                 break;
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 75fbaceb5c87..e379d3fd1694 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -583,7 +583,9 @@ void __init setup_arch(char **cmdline_p)
         init_mm.end_code = (unsigned long) _etext;
         init_mm.end_data = (unsigned long) _edata;
         init_mm.brk = klimit;
-        
+#ifdef CONFIG_PPC_64K_PAGES
+        init_mm.context.pte_frag = NULL;
+#endif
         irqstack_early_init();
         exc_lvl_early_init();
         emergency_stack_init();
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 76bd9da8cb71..ee7ac5e6e28a 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -669,7 +669,7 @@ __cpuinit void start_secondary(void *unused)
 
         local_irq_enable();
 
-        cpu_idle();
+        cpu_startup_entry(CPUHP_ONLINE);
 
         BUG();
 }
diff --git a/arch/powerpc/kernel/sys_ppc32.c b/arch/powerpc/kernel/sys_ppc32.c
index d0bafc0cdf06..cd6e19d263b3 100644
--- a/arch/powerpc/kernel/sys_ppc32.c
+++ b/arch/powerpc/kernel/sys_ppc32.c
@@ -61,91 +61,6 @@ asmlinkage long ppc32_select(u32 n, compat_ulong_t __user *inp,
         return compat_sys_select((int)n, inp, outp, exp, compat_ptr(tvp_x));
 }
 
-#ifdef CONFIG_SYSVIPC
-long compat_sys_ipc(u32 call, u32 first, u32 second, u32 third, compat_uptr_t ptr,
-               u32 fifth)
-{
-        int version;
-
-        version = call >> 16; /* hack for backward compatibility */
-        call &= 0xffff;
-
-        switch (call) {
-
-        case SEMTIMEDOP:
-                if (fifth)
-                        /* sign extend semid */
-                        return compat_sys_semtimedop((int)first,
-                                                     compat_ptr(ptr), second,
-                                                     compat_ptr(fifth));
-                /* else fall through for normal semop() */
-        case SEMOP:
-                /* struct sembuf is the same on 32 and 64bit :)) */
-                /* sign extend semid */
-                return sys_semtimedop((int)first, compat_ptr(ptr), second,
-                                      NULL);
-        case SEMGET:
-                /* sign extend key, nsems */
-                return sys_semget((int)first, (int)second, third);
-        case SEMCTL:
-                /* sign extend semid, semnum */
-                return compat_sys_semctl((int)first, (int)second, third,
-                                         compat_ptr(ptr));
-
-        case MSGSND:
-                /* sign extend msqid */
-                return compat_sys_msgsnd((int)first, (int)second, third,
-                                         compat_ptr(ptr));
-        case MSGRCV:
-                /* sign extend msqid, msgtyp */
-                return compat_sys_msgrcv((int)first, second, (int)fifth,
-                                         third, version, compat_ptr(ptr));
-        case MSGGET:
-                /* sign extend key */
-                return sys_msgget((int)first, second);
-        case MSGCTL:
-                /* sign extend msqid */
-                return compat_sys_msgctl((int)first, second, compat_ptr(ptr));
-
-        case SHMAT:
-                /* sign extend shmid */
-                return compat_sys_shmat((int)first, second, third, version,
-                                        compat_ptr(ptr));
-        case SHMDT:
-                return sys_shmdt(compat_ptr(ptr));
-        case SHMGET:
-                /* sign extend key_t */
-                return sys_shmget((int)first, second, third);
-        case SHMCTL:
-                /* sign extend shmid */
-                return compat_sys_shmctl((int)first, second, compat_ptr(ptr));
-
-        default:
-                return -ENOSYS;
-        }
-
-        return -ENOSYS;
-}
-#endif
-
-/* Note: it is necessary to treat out_fd and in_fd as unsigned ints, 
- * with the corresponding cast to a signed int to insure that the 
- * proper conversion (sign extension) between the register representation of a signed int (msr in 32-bit mode)
- * and the register representation of a signed int (msr in 64-bit mode) is performed.
- */
-asmlinkage long compat_sys_sendfile_wrapper(u32 out_fd, u32 in_fd,
-                                            compat_off_t __user *offset, u32 count)
-{
-        return compat_sys_sendfile((int)out_fd, (int)in_fd, offset, count);
-}
-
-asmlinkage long compat_sys_sendfile64_wrapper(u32 out_fd, u32 in_fd,
-                                              compat_loff_t __user *offset, u32 count)
-{
-        return sys_sendfile((int)out_fd, (int)in_fd,
-                            (off_t __user *)offset, count);
-}
-
 unsigned long compat_sys_mmap2(unsigned long addr, size_t len,
                           unsigned long prot, unsigned long flags,
                           unsigned long fd, unsigned long pgoff)
@@ -195,13 +110,6 @@ asmlinkage int compat_sys_ftruncate64(unsigned int fd, u32 reg4, unsigned long h
         return sys_ftruncate(fd, (high << 32) | low);
 }
 
-long ppc32_lookup_dcookie(u32 cookie_high, u32 cookie_low, char __user *buf,
-                          size_t len)
-{
-        return sys_lookup_dcookie((u64)cookie_high << 32 | cookie_low,
-                                  buf, len);
-}
-
 long ppc32_fadvise64(int fd, u32 unused, u32 offset_high, u32 offset_low,
                      size_t len, int advice)
 {
@@ -209,23 +117,6 @@ long ppc32_fadvise64(int fd, u32 unused, u32 offset_high, u32 offset_low,
                              advice);
 }
 
-asmlinkage long compat_sys_add_key(const char __user *_type,
-                              const char __user *_description,
-                              const void __user *_payload,
-                              u32 plen,
-                              u32 ringid)
-{
-        return sys_add_key(_type, _description, _payload, plen, ringid);
-}
-
-asmlinkage long compat_sys_request_key(const char __user *_type,
-                                  const char __user *_description,
-                                  const char __user *_callout_info,
-                                  u32 destringid)
-{
-        return sys_request_key(_type, _description, _callout_info, destringid);
-}
-
 asmlinkage long compat_sys_sync_file_range2(int fd, unsigned int flags,
                                    unsigned offset_hi, unsigned offset_lo,
                                    unsigned nbytes_hi, unsigned nbytes_lo)
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index 3ce1f864c2d3..e68a84568b8b 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -180,7 +180,7 @@ SYSFS_PMCSETUP(dscr, SPRN_DSCR);
 SYSFS_PMCSETUP(pir, SPRN_PIR);
 
 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
-static DEVICE_ATTR(spurr, 0600, show_spurr, NULL);
+static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
 static DEVICE_ATTR(purr, 0600, show_purr, store_purr);
 static DEVICE_ATTR(pir, 0400, show_pir, NULL);
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index f77fa22754bc..5fc29ad7e26f 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -1049,10 +1049,8 @@ static int __init rtc_init(void)
                 return -ENODEV;
 
         pdev = platform_device_register_simple("rtc-generic", -1, NULL, 0);
-        if (IS_ERR(pdev))
-                return PTR_ERR(pdev);
 
-        return 0;
+        return PTR_RET(pdev);
 }
 
 module_init(rtc_init);
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 37cc40ef5043..83efa2f7d926 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -970,7 +970,10 @@ static int emulate_instruction(struct pt_regs *regs)
 
 #ifdef CONFIG_PPC64
         /* Emulate the mfspr rD, DSCR. */
-        if (((instword & PPC_INST_MFSPR_DSCR_MASK) == PPC_INST_MFSPR_DSCR) &&
+        if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
+                PPC_INST_MFSPR_DSCR_USER) ||
+             ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
+                PPC_INST_MFSPR_DSCR)) &&
                         cpu_has_feature(CPU_FTR_DSCR)) {
                 PPC_WARN_EMULATED(mfdscr, regs);
                 rd = (instword >> 21) & 0x1f;
@@ -978,7 +981,10 @@ static int emulate_instruction(struct pt_regs *regs)
                 return 0;
         }
         /* Emulate the mtspr DSCR, rD. */
-        if (((instword & PPC_INST_MTSPR_DSCR_MASK) == PPC_INST_MTSPR_DSCR) &&
+        if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
+                PPC_INST_MTSPR_DSCR_USER) ||
+             ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
+                PPC_INST_MTSPR_DSCR)) &&
                         cpu_has_feature(CPU_FTR_DSCR)) {
                 PPC_WARN_EMULATED(mtdscr, regs);
                 rd = (instword >> 21) & 0x1f;
diff --git a/arch/powerpc/kernel/udbg.c b/arch/powerpc/kernel/udbg.c
index f9748498fe58..13b867093499 100644
--- a/arch/powerpc/kernel/udbg.c
+++ b/arch/powerpc/kernel/udbg.c
@@ -156,15 +156,13 @@ static struct console udbg_console = {
         .index  = 0,
 };
 
-static int early_console_initialized;
-
 /*
  * Called by setup_system after ppc_md->probe and ppc_md->early_init.
  * Call it again after setting udbg_putc in ppc_md->setup_arch.
  */
 void __init register_early_udbg_console(void)
 {
-        if (early_console_initialized)
+        if (early_console)
                 return;
 
         if (!udbg_putc)
@@ -174,7 +172,7 @@ void __init register_early_udbg_console(void)
                 printk(KERN_INFO "early console immortal !\n");
                 udbg_console.flags &= ~CON_BOOT;
         }
-        early_console_initialized = 1;
+        early_console = &udbg_console;
         register_console(&udbg_console);
 }
 
diff --git a/arch/powerpc/kernel/uprobes.c b/arch/powerpc/kernel/uprobes.c
index bc77834dbf43..59f419b935f2 100644
--- a/arch/powerpc/kernel/uprobes.c
+++ b/arch/powerpc/kernel/uprobes.c
@@ -31,6 +31,16 @@
 #define UPROBE_TRAP_NR  UINT_MAX
 
 /**
+ * is_trap_insn - check if the instruction is a trap variant
+ * @insn: instruction to be checked.
+ * Returns true if @insn is a trap variant.
+ */
+bool is_trap_insn(uprobe_opcode_t *insn)
+{
+        return (is_trap(*insn));
+}
+
+/**
  * arch_uprobe_analyze_insn
  * @mm: the probed address space.
  * @arch_uprobe: the probepoint information.
@@ -43,12 +53,6 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe,
         if (addr & 0x03)
                 return -EINVAL;
 
-        /*
-         * We currently don't support a uprobe on an already
-         * existing breakpoint instruction underneath
-         */
-        if (is_trap(auprobe->ainsn))
-                return -ENOTSUPP;
         return 0;
 }
 
@@ -188,3 +192,16 @@ bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
 
         return false;
 }
+
+unsigned long
+arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs)
+{
+        unsigned long orig_ret_vaddr;
+
+        orig_ret_vaddr = regs->link;
+
+        /* Replace the return addr with trampoline addr */
+        regs->link = trampoline_vaddr;
+
+        return orig_ret_vaddr;
+}
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c
index 1b2076f049ce..d4f463ac65b1 100644
--- a/arch/powerpc/kernel/vdso.c
+++ b/arch/powerpc/kernel/vdso.c
@@ -113,6 +113,10 @@ static struct vdso_patch_def vdso_patches[] = {
                 CPU_FTR_USE_TB, 0,
                 "__kernel_get_tbfreq", NULL
         },
+        {
+                CPU_FTR_USE_TB, 0,
+                "__kernel_time", NULL
+        },
 };
 
 /*
diff --git a/arch/powerpc/kernel/vdso32/gettimeofday.S b/arch/powerpc/kernel/vdso32/gettimeofday.S
index 4ee09ee2e836..27e2f623210b 100644
--- a/arch/powerpc/kernel/vdso32/gettimeofday.S
+++ b/arch/powerpc/kernel/vdso32/gettimeofday.S
@@ -181,6 +181,32 @@ V_FUNCTION_END(__kernel_clock_getres)
 
 
 /*
+ * Exact prototype of time()
+ *
+ * time_t time(time *t);
+ *
+ */
+V_FUNCTION_BEGIN(__kernel_time)
+  .cfi_startproc
+        mflr    r12
+  .cfi_register lr,r12
+
+        mr      r11,r3                  /* r11 holds t */
+        bl      __get_datapage@local
+        mr      r9, r3                  /* datapage ptr in r9 */
+
+        lwz     r3,STAMP_XTIME+TSPEC_TV_SEC(r9)
+
+        cmplwi  r11,0                   /* check if t is NULL */
+        beq     2f
+        stw     r3,0(r11)               /* store result at *t */
+2:      mtlr    r12
+        crclr   cr0*4+so
+        blr
+  .cfi_endproc
+V_FUNCTION_END(__kernel_time)
+
+/*
  * This is the core of clock_gettime() and gettimeofday(),
  * it returns the current time in r3 (seconds) and r4.
  * On entry, r7 gives the resolution of r4, either USEC_PER_SEC
diff --git a/arch/powerpc/kernel/vdso32/vdso32.lds.S b/arch/powerpc/kernel/vdso32/vdso32.lds.S
index 43200ba2e570..f223409629b9 100644
--- a/arch/powerpc/kernel/vdso32/vdso32.lds.S
+++ b/arch/powerpc/kernel/vdso32/vdso32.lds.S
@@ -150,6 +150,7 @@ VERSION
 #ifdef CONFIG_PPC64
                 __kernel_getcpu;
 #endif
+                __kernel_time;
 
         local: *;
         };
diff --git a/arch/powerpc/kernel/vdso64/gettimeofday.S b/arch/powerpc/kernel/vdso64/gettimeofday.S
index e97a9a0dc4ac..a76b4af37ef2 100644
--- a/arch/powerpc/kernel/vdso64/gettimeofday.S
+++ b/arch/powerpc/kernel/vdso64/gettimeofday.S
@@ -164,6 +164,32 @@ V_FUNCTION_BEGIN(__kernel_clock_getres)
   .cfi_endproc
 V_FUNCTION_END(__kernel_clock_getres)
 
+/*
+ * Exact prototype of time()
+ *
+ * time_t time(time *t);
+ *
+ */
+V_FUNCTION_BEGIN(__kernel_time)
+  .cfi_startproc
+        mflr    r12
+  .cfi_register lr,r12
+
+        mr      r11,r3                  /* r11 holds t */
+        bl      V_LOCAL_FUNC(__get_datapage)
+
+        ld      r4,STAMP_XTIME+TSPC64_TV_SEC(r3)
+
+        cmpldi  r11,0                   /* check if t is NULL */
+        beq     2f
+        std     r4,0(r11)               /* store result at *t */
+2:      mtlr    r12
+        crclr   cr0*4+so
+        mr      r3,r4
+        blr
+  .cfi_endproc
+V_FUNCTION_END(__kernel_time)
+
 
 /*
  * This is the core of clock_gettime() and gettimeofday(),
diff --git a/arch/powerpc/kernel/vdso64/vdso64.lds.S b/arch/powerpc/kernel/vdso64/vdso64.lds.S
index e6c1758f3588..e4863819663b 100644
--- a/arch/powerpc/kernel/vdso64/vdso64.lds.S
+++ b/arch/powerpc/kernel/vdso64/vdso64.lds.S
@@ -147,6 +147,7 @@ VERSION
                 __kernel_sync_dicache_p5;
                 __kernel_sigtramp_rt64;
                 __kernel_getcpu;
+                __kernel_time;
 
         local: *;
         };
diff --git a/arch/powerpc/kvm/44x.c b/arch/powerpc/kvm/44x.c
index 3d7fd21c65f9..2f5c6b6d6877 100644
--- a/arch/powerpc/kvm/44x.c
+++ b/arch/powerpc/kvm/44x.c
@@ -124,6 +124,18 @@ int kvmppc_core_set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
         return kvmppc_set_sregs_ivor(vcpu, sregs);
 }
 
+int kvmppc_get_one_reg(struct kvm_vcpu *vcpu, u64 id,
+                        union kvmppc_one_reg *val)
+{
+        return -EINVAL;
+}
+
+int kvmppc_set_one_reg(struct kvm_vcpu *vcpu, u64 id,
+                       union kvmppc_one_reg *val)
+{
+        return -EINVAL;
+}
+
 struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id)
 {
         struct kvmppc_vcpu_44x *vcpu_44x;
diff --git a/arch/powerpc/kvm/Kconfig b/arch/powerpc/kvm/Kconfig
index 63c67ec72e43..eb643f862579 100644
--- a/arch/powerpc/kvm/Kconfig
+++ b/arch/powerpc/kvm/Kconfig
@@ -136,21 +136,41 @@ config KVM_E500V2
           If unsure, say N.
 
 config KVM_E500MC
-        bool "KVM support for PowerPC E500MC/E5500 processors"
+        bool "KVM support for PowerPC E500MC/E5500/E6500 processors"
         depends on PPC_E500MC
         select KVM
         select KVM_MMIO
         select KVM_BOOKE_HV
         select MMU_NOTIFIER
         ---help---
-          Support running unmodified E500MC/E5500 (32-bit) guest kernels in
-          virtual machines on E500MC/E5500 host processors.
+          Support running unmodified E500MC/E5500/E6500 guest kernels in
+          virtual machines on E500MC/E5500/E6500 host processors.
 
           This module provides access to the hardware capabilities through
           a character device node named /dev/kvm.
 
           If unsure, say N.
 
+config KVM_MPIC
+        bool "KVM in-kernel MPIC emulation"
+        depends on KVM && E500
+        select HAVE_KVM_IRQCHIP
+        select HAVE_KVM_IRQ_ROUTING
+        select HAVE_KVM_MSI
+        help
+          Enable support for emulating MPIC devices inside the
+          host kernel, rather than relying on userspace to emulate.
+          Currently, support is limited to certain versions of
+          Freescale's MPIC implementation.
+
+config KVM_XICS
+        bool "KVM in-kernel XICS emulation"
+        depends on KVM_BOOK3S_64 && !KVM_MPIC
+        ---help---
+          Include support for the XICS (eXternal Interrupt Controller
+          Specification) interrupt controller architecture used on
+          IBM POWER (pSeries) servers.
+
 source drivers/vhost/Kconfig
 
 endif # VIRTUALIZATION
diff --git a/arch/powerpc/kvm/Makefile b/arch/powerpc/kvm/Makefile
index b772eded8c26..422de3f4d46c 100644
--- a/arch/powerpc/kvm/Makefile
+++ b/arch/powerpc/kvm/Makefile
@@ -72,12 +72,18 @@ kvm-book3s_64-objs-$(CONFIG_KVM_BOOK3S_64_HV) := \
         book3s_hv.o \
         book3s_hv_interrupts.o \
         book3s_64_mmu_hv.o
+kvm-book3s_64-builtin-xics-objs-$(CONFIG_KVM_XICS) := \
+        book3s_hv_rm_xics.o
 kvm-book3s_64-builtin-objs-$(CONFIG_KVM_BOOK3S_64_HV) := \
         book3s_hv_rmhandlers.o \
         book3s_hv_rm_mmu.o \
         book3s_64_vio_hv.o \
         book3s_hv_ras.o \
-        book3s_hv_builtin.o
+        book3s_hv_builtin.o \
+        $(kvm-book3s_64-builtin-xics-objs-y)
+
+kvm-book3s_64-objs-$(CONFIG_KVM_XICS) += \
+        book3s_xics.o
 
 kvm-book3s_64-module-objs := \
         ../../../virt/kvm/kvm_main.o \
@@ -86,6 +92,7 @@ kvm-book3s_64-module-objs := \
         emulate.o \
         book3s.o \
         book3s_64_vio.o \
+        book3s_rtas.o \
         $(kvm-book3s_64-objs-y)
 
 kvm-objs-$(CONFIG_KVM_BOOK3S_64) := $(kvm-book3s_64-module-objs)
@@ -103,6 +110,9 @@ kvm-book3s_32-objs := \
         book3s_32_mmu.o
 kvm-objs-$(CONFIG_KVM_BOOK3S_32) := $(kvm-book3s_32-objs)
 
+kvm-objs-$(CONFIG_KVM_MPIC) += mpic.o
+kvm-objs-$(CONFIG_HAVE_KVM_IRQ_ROUTING) += $(addprefix ../../../virt/kvm/, irqchip.o)
+
 kvm-objs := $(kvm-objs-m) $(kvm-objs-y)
 
 obj-$(CONFIG_KVM_440) += kvm.o
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
index a4b645285240..700df6f1d32c 100644
--- a/arch/powerpc/kvm/book3s.c
+++ b/arch/powerpc/kvm/book3s.c
@@ -104,7 +104,7 @@ static int kvmppc_book3s_vec2irqprio(unsigned int vec)
         return prio;
 }
 
-static void kvmppc_book3s_dequeue_irqprio(struct kvm_vcpu *vcpu,
+void kvmppc_book3s_dequeue_irqprio(struct kvm_vcpu *vcpu,
                                           unsigned int vec)
 {
         unsigned long old_pending = vcpu->arch.pending_exceptions;
@@ -160,8 +160,7 @@ void kvmppc_core_queue_external(struct kvm_vcpu *vcpu,
         kvmppc_book3s_queue_irqprio(vcpu, vec);
 }
 
-void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu,
-                                  struct kvm_interrupt *irq)
+void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu)
 {
         kvmppc_book3s_dequeue_irqprio(vcpu, BOOK3S_INTERRUPT_EXTERNAL);
         kvmppc_book3s_dequeue_irqprio(vcpu, BOOK3S_INTERRUPT_EXTERNAL_LEVEL);
@@ -530,6 +529,21 @@ int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
                         val = get_reg_val(reg->id, vcpu->arch.vscr.u[3]);
                         break;
 #endif /* CONFIG_ALTIVEC */
+                case KVM_REG_PPC_DEBUG_INST: {
+                        u32 opcode = INS_TW;
+                        r = copy_to_user((u32 __user *)(long)reg->addr,
+                                         &opcode, sizeof(u32));
+                        break;
+                }
+#ifdef CONFIG_KVM_XICS
+                case KVM_REG_PPC_ICP_STATE:
+                        if (!vcpu->arch.icp) {
+                                r = -ENXIO;
+                                break;
+                        }
+                        val = get_reg_val(reg->id, kvmppc_xics_get_icp(vcpu));
+                        break;
+#endif /* CONFIG_KVM_XICS */
                 default:
                         r = -EINVAL;
                         break;
@@ -592,6 +606,16 @@ int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
                         vcpu->arch.vscr.u[3] = set_reg_val(reg->id, val);
                         break;
 #endif /* CONFIG_ALTIVEC */
+#ifdef CONFIG_KVM_XICS
+                case KVM_REG_PPC_ICP_STATE:
+                        if (!vcpu->arch.icp) {
+                                r = -ENXIO;
+                                break;
+                        }
+                        r = kvmppc_xics_set_icp(vcpu,
+                                                set_reg_val(reg->id, val));
+                        break;
+#endif /* CONFIG_KVM_XICS */
                 default:
                         r = -EINVAL;
                         break;
@@ -607,6 +631,12 @@ int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
         return 0;
 }
 
+int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
+                                        struct kvm_guest_debug *dbg)
+{
+        return -EINVAL;
+}
+
 void kvmppc_decrementer_func(unsigned long data)
 {
         struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c b/arch/powerpc/kvm/book3s_64_mmu_host.c
index 5d7d29a313eb..3a9a1aceb14f 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_host.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_host.c
@@ -143,7 +143,7 @@ map_again:
                 }
 
         ret = ppc_md.hpte_insert(hpteg, vpn, hpaddr, rflags, vflags,
-                                 MMU_PAGE_4K, MMU_SEGSIZE_256M);
+                                 MMU_PAGE_4K, MMU_PAGE_4K, MMU_SEGSIZE_256M);
 
         if (ret < 0) {
                 /* If we couldn't map a primary PTE, try a secondary */
diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c b/arch/powerpc/kvm/book3s_64_mmu_hv.c
index 8cc18abd6dde..5880dfb31074 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_hv.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_hv.c
@@ -893,7 +893,10 @@ static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
                         /* Harvest R and C */
                         rcbits = hptep[1] & (HPTE_R_R | HPTE_R_C);
                         *rmapp |= rcbits << KVMPPC_RMAP_RC_SHIFT;
-                        rev[i].guest_rpte = ptel | rcbits;
+                        if (rcbits & ~rev[i].guest_rpte) {
+                                rev[i].guest_rpte = ptel | rcbits;
+                                note_hpte_modification(kvm, &rev[i]);
+                        }
                 }
                 unlock_rmap(rmapp);
                 hptep[0] &= ~HPTE_V_HVLOCK;
@@ -976,7 +979,10 @@ static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
                 /* Now check and modify the HPTE */
                 if ((hptep[0] & HPTE_V_VALID) && (hptep[1] & HPTE_R_R)) {
                         kvmppc_clear_ref_hpte(kvm, hptep, i);
-                        rev[i].guest_rpte |= HPTE_R_R;
+                        if (!(rev[i].guest_rpte & HPTE_R_R)) {
+                                rev[i].guest_rpte |= HPTE_R_R;
+                                note_hpte_modification(kvm, &rev[i]);
+                        }
                         ret = 1;
                 }
                 hptep[0] &= ~HPTE_V_HVLOCK;
@@ -1080,7 +1086,10 @@ static int kvm_test_clear_dirty(struct kvm *kvm, unsigned long *rmapp)
                         hptep[1] &= ~HPTE_R_C;
                         eieio();
                         hptep[0] = (hptep[0] & ~HPTE_V_ABSENT) | HPTE_V_VALID;
-                        rev[i].guest_rpte |= HPTE_R_C;
+                        if (!(rev[i].guest_rpte & HPTE_R_C)) {
+                                rev[i].guest_rpte |= HPTE_R_C;
+                                note_hpte_modification(kvm, &rev[i]);
+                        }
                         ret = 1;
                 }
                 hptep[0] &= ~HPTE_V_HVLOCK;
@@ -1090,11 +1099,30 @@ static int kvm_test_clear_dirty(struct kvm *kvm, unsigned long *rmapp)
         return ret;
 }
 
+static void harvest_vpa_dirty(struct kvmppc_vpa *vpa,
+                              struct kvm_memory_slot *memslot,
+                              unsigned long *map)
+{
+        unsigned long gfn;
+
+        if (!vpa->dirty || !vpa->pinned_addr)
+                return;
+        gfn = vpa->gpa >> PAGE_SHIFT;
+        if (gfn < memslot->base_gfn ||
+            gfn >= memslot->base_gfn + memslot->npages)
+                return;
+
+        vpa->dirty = false;
+        if (map)
+                __set_bit_le(gfn - memslot->base_gfn, map);
+}
+
 long kvmppc_hv_get_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot,
                              unsigned long *map)
 {
         unsigned long i;
         unsigned long *rmapp;
+        struct kvm_vcpu *vcpu;
 
         preempt_disable();
         rmapp = memslot->arch.rmap;
@@ -1103,6 +1131,15 @@ long kvmppc_hv_get_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot,
                         __set_bit_le(i, map);
                 ++rmapp;
         }
+
+        /* Harvest dirty bits from VPA and DTL updates */
+        /* Note: we never modify the SLB shadow buffer areas */
+        kvm_for_each_vcpu(i, vcpu, kvm) {
+                spin_lock(&vcpu->arch.vpa_update_lock);
+                harvest_vpa_dirty(&vcpu->arch.vpa, memslot, map);
+                harvest_vpa_dirty(&vcpu->arch.dtl, memslot, map);
+                spin_unlock(&vcpu->arch.vpa_update_lock);
+        }
         preempt_enable();
         return 0;
 }
@@ -1114,7 +1151,7 @@ void *kvmppc_pin_guest_page(struct kvm *kvm, unsigned long gpa,
         unsigned long gfn = gpa >> PAGE_SHIFT;
         struct page *page, *pages[1];
         int npages;
-        unsigned long hva, psize, offset;
+        unsigned long hva, offset;
         unsigned long pa;
         unsigned long *physp;
         int srcu_idx;
@@ -1146,14 +1183,9 @@ void *kvmppc_pin_guest_page(struct kvm *kvm, unsigned long gpa,
         }
         srcu_read_unlock(&kvm->srcu, srcu_idx);
 
-        psize = PAGE_SIZE;
-        if (PageHuge(page)) {
-                page = compound_head(page);
-                psize <<= compound_order(page);
-        }
-        offset = gpa & (psize - 1);
+        offset = gpa & (PAGE_SIZE - 1);
         if (nb_ret)
-                *nb_ret = psize - offset;
+                *nb_ret = PAGE_SIZE - offset;
         return page_address(page) + offset;
 
  err:
@@ -1161,11 +1193,31 @@ void *kvmppc_pin_guest_page(struct kvm *kvm, unsigned long gpa,
         return NULL;
 }
 
-void kvmppc_unpin_guest_page(struct kvm *kvm, void *va)
+void kvmppc_unpin_guest_page(struct kvm *kvm, void *va, unsigned long gpa,
+                             bool dirty)
 {
         struct page *page = virt_to_page(va);
+        struct kvm_memory_slot *memslot;
+        unsigned long gfn;
+        unsigned long *rmap;
+        int srcu_idx;
 
         put_page(page);
+
+        if (!dirty || !kvm->arch.using_mmu_notifiers)
+                return;
+
+        /* We need to mark this page dirty in the rmap chain */
+        gfn = gpa >> PAGE_SHIFT;
+        srcu_idx = srcu_read_lock(&kvm->srcu);
+        memslot = gfn_to_memslot(kvm, gfn);
+        if (memslot) {
+                rmap = &memslot->arch.rmap[gfn - memslot->base_gfn];
+                lock_rmap(rmap);
+                *rmap |= KVMPPC_RMAP_CHANGED;
+                unlock_rmap(rmap);
+        }
+        srcu_read_unlock(&kvm->srcu, srcu_idx);
 }
 
 /*
@@ -1193,16 +1245,36 @@ struct kvm_htab_ctx {
 
 #define HPTE_SIZE       (2 * sizeof(unsigned long))
 
+/*
+ * Returns 1 if this HPT entry has been modified or has pending
+ * R/C bit changes.
+ */
+static int hpte_dirty(struct revmap_entry *revp, unsigned long *hptp)
+{
+        unsigned long rcbits_unset;
+
+        if (revp->guest_rpte & HPTE_GR_MODIFIED)
+                return 1;
+
+        /* Also need to consider changes in reference and changed bits */
+        rcbits_unset = ~revp->guest_rpte & (HPTE_R_R | HPTE_R_C);
+        if ((hptp[0] & HPTE_V_VALID) && (hptp[1] & rcbits_unset))
+                return 1;
+
+        return 0;
+}
+
 static long record_hpte(unsigned long flags, unsigned long *hptp,
                         unsigned long *hpte, struct revmap_entry *revp,
                         int want_valid, int first_pass)
 {
         unsigned long v, r;
+        unsigned long rcbits_unset;
         int ok = 1;
         int valid, dirty;
 
         /* Unmodified entries are uninteresting except on the first pass */
-        dirty = !!(revp->guest_rpte & HPTE_GR_MODIFIED);
+        dirty = hpte_dirty(revp, hptp);
         if (!first_pass && !dirty)
                 return 0;
 
@@ -1223,16 +1295,28 @@ static long record_hpte(unsigned long flags, unsigned long *hptp,
                 while (!try_lock_hpte(hptp, HPTE_V_HVLOCK))
                         cpu_relax();
                 v = hptp[0];
+
+                /* re-evaluate valid and dirty from synchronized HPTE value */
+                valid = !!(v & HPTE_V_VALID);
+                dirty = !!(revp->guest_rpte & HPTE_GR_MODIFIED);
+
+                /* Harvest R and C into guest view if necessary */
+                rcbits_unset = ~revp->guest_rpte & (HPTE_R_R | HPTE_R_C);
+                if (valid && (rcbits_unset & hptp[1])) {
+                        revp->guest_rpte |= (hptp[1] & (HPTE_R_R | HPTE_R_C)) |
+                                HPTE_GR_MODIFIED;
+                        dirty = 1;
+                }
+
                 if (v & HPTE_V_ABSENT) {
                         v &= ~HPTE_V_ABSENT;
                         v |= HPTE_V_VALID;
+                        valid = 1;
                 }
-                /* re-evaluate valid and dirty from synchronized HPTE value */
-                valid = !!(v & HPTE_V_VALID);
                 if ((flags & KVM_GET_HTAB_BOLTED_ONLY) && !(v & HPTE_V_BOLTED))
                         valid = 0;
-                r = revp->guest_rpte | (hptp[1] & (HPTE_R_R | HPTE_R_C));
-                dirty = !!(revp->guest_rpte & HPTE_GR_MODIFIED);
+
+                r = revp->guest_rpte;
                 /* only clear modified if this is the right sort of entry */
                 if (valid == want_valid && dirty) {
                         r &= ~HPTE_GR_MODIFIED;
@@ -1288,7 +1372,7 @@ static ssize_t kvm_htab_read(struct file *file, char __user *buf,
                 /* Skip uninteresting entries, i.e. clean on not-first pass */
                 if (!first_pass) {
                         while (i < kvm->arch.hpt_npte &&
-                               !(revp->guest_rpte & HPTE_GR_MODIFIED)) {
+                               !hpte_dirty(revp, hptp)) {
                                 ++i;
                                 hptp += 2;
                                 ++revp;
@@ -1467,7 +1551,7 @@ static int kvm_htab_release(struct inode *inode, struct file *filp)
         return 0;
 }
 
-static struct file_operations kvm_htab_fops = {
+static const struct file_operations kvm_htab_fops = {
         .read           = kvm_htab_read,
         .write          = kvm_htab_write,
         .llseek         = default_llseek,
diff --git a/arch/powerpc/kvm/book3s_64_vio.c b/arch/powerpc/kvm/book3s_64_vio.c
index 72ffc899c082..b2d3f3b2de72 100644
--- a/arch/powerpc/kvm/book3s_64_vio.c
+++ b/arch/powerpc/kvm/book3s_64_vio.c
@@ -92,7 +92,7 @@ static int kvm_spapr_tce_release(struct inode *inode, struct file *filp)
         return 0;
 }
 
-static struct file_operations kvm_spapr_tce_fops = {
+static const struct file_operations kvm_spapr_tce_fops = {
         .mmap           = kvm_spapr_tce_mmap,
         .release        = kvm_spapr_tce_release,
 };
diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
index 836c56975e21..1f6344c4408d 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -194,7 +194,9 @@ int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
                                 run->papr_hcall.args[i] = gpr;
                         }
 
-                        emulated = EMULATE_DO_PAPR;
+                        run->exit_reason = KVM_EXIT_PAPR_HCALL;
+                        vcpu->arch.hcall_needed = 1;
+                        emulated = EMULATE_EXIT_USER;
                         break;
                 }
 #endif
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 80dcc53a1aba..9de24f8e03c7 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -66,6 +66,31 @@
 static void kvmppc_end_cede(struct kvm_vcpu *vcpu);
 static int kvmppc_hv_setup_htab_rma(struct kvm_vcpu *vcpu);
 
+void kvmppc_fast_vcpu_kick(struct kvm_vcpu *vcpu)
+{
+        int me;
+        int cpu = vcpu->cpu;
+        wait_queue_head_t *wqp;
+
+        wqp = kvm_arch_vcpu_wq(vcpu);
+        if (waitqueue_active(wqp)) {
+                wake_up_interruptible(wqp);
+                ++vcpu->stat.halt_wakeup;
+        }
+
+        me = get_cpu();
+
+        /* CPU points to the first thread of the core */
+        if (cpu != me && cpu >= 0 && cpu < nr_cpu_ids) {
+                int real_cpu = cpu + vcpu->arch.ptid;
+                if (paca[real_cpu].kvm_hstate.xics_phys)
+                        xics_wake_cpu(real_cpu);
+                else if (cpu_online(cpu))
+                        smp_send_reschedule(cpu);
+        }
+        put_cpu();
+}
+
 /*
  * We use the vcpu_load/put functions to measure stolen time.
  * Stolen time is counted as time when either the vcpu is able to
@@ -259,7 +284,7 @@ static unsigned long do_h_register_vpa(struct kvm_vcpu *vcpu,
                         len = ((struct reg_vpa *)va)->length.hword;
                 else
                         len = ((struct reg_vpa *)va)->length.word;
-                kvmppc_unpin_guest_page(kvm, va);
+                kvmppc_unpin_guest_page(kvm, va, vpa, false);
 
                 /* Check length */
                 if (len > nb || len < sizeof(struct reg_vpa))
@@ -359,13 +384,13 @@ static void kvmppc_update_vpa(struct kvm_vcpu *vcpu, struct kvmppc_vpa *vpap)
                 va = NULL;
                 nb = 0;
                 if (gpa)
-                        va = kvmppc_pin_guest_page(kvm, vpap->next_gpa, &nb);
+                        va = kvmppc_pin_guest_page(kvm, gpa, &nb);
                 spin_lock(&vcpu->arch.vpa_update_lock);
                 if (gpa == vpap->next_gpa)
                         break;
                 /* sigh... unpin that one and try again */
                 if (va)
-                        kvmppc_unpin_guest_page(kvm, va);
+                        kvmppc_unpin_guest_page(kvm, va, gpa, false);
         }
 
         vpap->update_pending = 0;
@@ -375,12 +400,15 @@ static void kvmppc_update_vpa(struct kvm_vcpu *vcpu, struct kvmppc_vpa *vpap)
                  * has changed the mappings underlying guest memory,
                  * so unregister the region.
                  */
-                kvmppc_unpin_guest_page(kvm, va);
+                kvmppc_unpin_guest_page(kvm, va, gpa, false);
                 va = NULL;
         }
         if (vpap->pinned_addr)
-                kvmppc_unpin_guest_page(kvm, vpap->pinned_addr);
+                kvmppc_unpin_guest_page(kvm, vpap->pinned_addr, vpap->gpa,
+                                        vpap->dirty);
+        vpap->gpa = gpa;
         vpap->pinned_addr = va;
+        vpap->dirty = false;
         if (va)
                 vpap->pinned_end = va + vpap->len;
 }
@@ -472,6 +500,7 @@ static void kvmppc_create_dtl_entry(struct kvm_vcpu *vcpu,
         /* order writing *dt vs. writing vpa->dtl_idx */
         smp_wmb();
         vpa->dtl_idx = ++vcpu->arch.dtl_index;
+        vcpu->arch.dtl.dirty = true;
 }
 
 int kvmppc_pseries_do_hcall(struct kvm_vcpu *vcpu)
@@ -479,7 +508,7 @@ int kvmppc_pseries_do_hcall(struct kvm_vcpu *vcpu)
         unsigned long req = kvmppc_get_gpr(vcpu, 3);
         unsigned long target, ret = H_SUCCESS;
         struct kvm_vcpu *tvcpu;
-        int idx;
+        int idx, rc;
 
         switch (req) {
         case H_ENTER:
@@ -515,6 +544,28 @@ int kvmppc_pseries_do_hcall(struct kvm_vcpu *vcpu)
                                         kvmppc_get_gpr(vcpu, 5),
                                         kvmppc_get_gpr(vcpu, 6));
                 break;
+        case H_RTAS:
+                if (list_empty(&vcpu->kvm->arch.rtas_tokens))
+                        return RESUME_HOST;
+
+                rc = kvmppc_rtas_hcall(vcpu);
+
+                if (rc == -ENOENT)
+                        return RESUME_HOST;
+                else if (rc == 0)
+                        break;
+
+                /* Send the error out to userspace via KVM_RUN */
+                return rc;
+
+        case H_XIRR:
+        case H_CPPR:
+        case H_EOI:
+        case H_IPI:
+                if (kvmppc_xics_enabled(vcpu)) {
+                        ret = kvmppc_xics_hcall(vcpu, req);
+                        break;
+                } /* fallthrough */
         default:
                 return RESUME_HOST;
         }
@@ -913,15 +964,19 @@ out:
         return ERR_PTR(err);
 }
 
+static void unpin_vpa(struct kvm *kvm, struct kvmppc_vpa *vpa)
+{
+        if (vpa->pinned_addr)
+                kvmppc_unpin_guest_page(kvm, vpa->pinned_addr, vpa->gpa,
+                                        vpa->dirty);
+}
+
 void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu)
 {
         spin_lock(&vcpu->arch.vpa_update_lock);
-        if (vcpu->arch.dtl.pinned_addr)
-                kvmppc_unpin_guest_page(vcpu->kvm, vcpu->arch.dtl.pinned_addr);
-        if (vcpu->arch.slb_shadow.pinned_addr)
-                kvmppc_unpin_guest_page(vcpu->kvm, vcpu->arch.slb_shadow.pinned_addr);
-        if (vcpu->arch.vpa.pinned_addr)
-                kvmppc_unpin_guest_page(vcpu->kvm, vcpu->arch.vpa.pinned_addr);
+        unpin_vpa(vcpu->kvm, &vcpu->arch.dtl);
+        unpin_vpa(vcpu->kvm, &vcpu->arch.slb_shadow);
+        unpin_vpa(vcpu->kvm, &vcpu->arch.vpa);
         spin_unlock(&vcpu->arch.vpa_update_lock);
         kvm_vcpu_uninit(vcpu);
         kmem_cache_free(kvm_vcpu_cache, vcpu);
@@ -955,7 +1010,6 @@ static void kvmppc_end_cede(struct kvm_vcpu *vcpu)
 }
 
 extern int __kvmppc_vcore_entry(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu);
-extern void xics_wake_cpu(int cpu);
 
 static void kvmppc_remove_runnable(struct kvmppc_vcore *vc,
                                    struct kvm_vcpu *vcpu)
@@ -1330,9 +1384,12 @@ static int kvmppc_run_vcpu(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
                         break;
                 vc->runner = vcpu;
                 n_ceded = 0;
-                list_for_each_entry(v, &vc->runnable_threads, arch.run_list)
+                list_for_each_entry(v, &vc->runnable_threads, arch.run_list) {
                         if (!v->arch.pending_exceptions)
                                 n_ceded += v->arch.ceded;
+                        else
+                                v->arch.ceded = 0;
+                }
                 if (n_ceded == vc->n_runnable)
                         kvmppc_vcore_blocked(vc);
                 else
@@ -1483,7 +1540,7 @@ static int kvm_rma_release(struct inode *inode, struct file *filp)
         return 0;
 }
 
-static struct file_operations kvm_rma_fops = {
+static const struct file_operations kvm_rma_fops = {
         .mmap           = kvm_rma_mmap,
         .release        = kvm_rma_release,
 };
@@ -1515,7 +1572,13 @@ static void kvmppc_add_seg_page_size(struct kvm_ppc_one_seg_page_size **sps,
         (*sps)->page_shift = def->shift;
         (*sps)->slb_enc = def->sllp;
         (*sps)->enc[0].page_shift = def->shift;
-        (*sps)->enc[0].pte_enc = def->penc;
+        /*
+         * Only return base page encoding. We don't want to return
+         * all the supporting pte_enc, because our H_ENTER doesn't
+         * support MPSS yet. Once they do, we can start passing all
+         * support pte_enc here
+         */
+        (*sps)->enc[0].pte_enc = def->penc[linux_psize];
         (*sps)++;
 }
 
@@ -1639,12 +1702,12 @@ int kvmppc_core_prepare_memory_region(struct kvm *kvm,
 
 void kvmppc_core_commit_memory_region(struct kvm *kvm,
                                       struct kvm_userspace_memory_region *mem,
-                                      struct kvm_memory_slot old)
+                                      const struct kvm_memory_slot *old)
 {
         unsigned long npages = mem->memory_size >> PAGE_SHIFT;
         struct kvm_memory_slot *memslot;
 
-        if (npages && old.npages) {
+        if (npages && old->npages) {
                 /*
                  * If modifying a memslot, reset all the rmap dirty bits.
                  * If this is a new memslot, we don't need to do anything
@@ -1821,6 +1884,7 @@ int kvmppc_core_init_vm(struct kvm *kvm)
         cpumask_setall(&kvm->arch.need_tlb_flush);
 
         INIT_LIST_HEAD(&kvm->arch.spapr_tce_tables);
+        INIT_LIST_HEAD(&kvm->arch.rtas_tokens);
 
         kvm->arch.rma = NULL;
 
@@ -1866,6 +1930,8 @@ void kvmppc_core_destroy_vm(struct kvm *kvm)
                 kvm->arch.rma = NULL;
         }
 
+        kvmppc_rtas_tokens_free(kvm);
+
         kvmppc_free_hpt(kvm);
         WARN_ON(!list_empty(&kvm->arch.spapr_tce_tables));
 }
diff --git a/arch/powerpc/kvm/book3s_hv_interrupts.S b/arch/powerpc/kvm/book3s_hv_interrupts.S
index 84035a528c80..37f1cc417ca0 100644
--- a/arch/powerpc/kvm/book3s_hv_interrupts.S
+++ b/arch/powerpc/kvm/book3s_hv_interrupts.S
@@ -122,11 +122,16 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
         add     r8,r8,r7
         std     r8,HSTATE_DECEXP(r13)
 
+#ifdef CONFIG_SMP
         /*
          * On PPC970, if the guest vcpu has an external interrupt pending,
          * send ourselves an IPI so as to interrupt the guest once it
          * enables interrupts.  (It must have interrupts disabled,
          * otherwise we would already have delivered the interrupt.)
+         *
+         * XXX If this is a UP build, smp_send_reschedule is not available,
+         * so the interrupt will be delayed until the next time the vcpu
+         * enters the guest with interrupts enabled.
          */
 BEGIN_FTR_SECTION
         ld      r0, VCPU_PENDING_EXC(r4)
@@ -141,6 +146,7 @@ BEGIN_FTR_SECTION
         mr      r4, r31
 32:
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
+#endif /* CONFIG_SMP */
 
         /* Jump to partition switch code */
         bl      .kvmppc_hv_entry_trampoline
diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
index 19c93bae1aea..6dcbb49105a4 100644
--- a/arch/powerpc/kvm/book3s_hv_rm_mmu.c
+++ b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
@@ -97,17 +97,6 @@ void kvmppc_add_revmap_chain(struct kvm *kvm, struct revmap_entry *rev,
 }
 EXPORT_SYMBOL_GPL(kvmppc_add_revmap_chain);
 
-/*
- * Note modification of an HPTE; set the HPTE modified bit
- * if anyone is interested.
- */
-static inline void note_hpte_modification(struct kvm *kvm,
-                                          struct revmap_entry *rev)
-{
-        if (atomic_read(&kvm->arch.hpte_mod_interest))
-                rev->guest_rpte |= HPTE_GR_MODIFIED;
-}
-
 /* Remove this HPTE from the chain for a real page */
 static void remove_revmap_chain(struct kvm *kvm, long pte_index,
                                 struct revmap_entry *rev,
diff --git a/arch/powerpc/kvm/book3s_hv_rm_xics.c b/arch/powerpc/kvm/book3s_hv_rm_xics.c
new file mode 100644
index 000000000000..b4b0082f761c
--- /dev/null
+++ b/arch/powerpc/kvm/book3s_hv_rm_xics.c
@@ -0,0 +1,406 @@
+/*
+ * Copyright 2012 Michael Ellerman, IBM Corporation.
+ * Copyright 2012 Benjamin Herrenschmidt, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/kvm_host.h>
+#include <linux/err.h>
+
+#include <asm/kvm_book3s.h>
+#include <asm/kvm_ppc.h>
+#include <asm/hvcall.h>
+#include <asm/xics.h>
+#include <asm/debug.h>
+#include <asm/synch.h>
+#include <asm/ppc-opcode.h>
+
+#include "book3s_xics.h"
+
+#define DEBUG_PASSUP
+
+static inline void rm_writeb(unsigned long paddr, u8 val)
+{
+        __asm__ __volatile__("sync; stbcix %0,0,%1"
+                : : "r" (val), "r" (paddr) : "memory");
+}
+
+static void icp_rm_set_vcpu_irq(struct kvm_vcpu *vcpu,
+                                struct kvm_vcpu *this_vcpu)
+{
+        struct kvmppc_icp *this_icp = this_vcpu->arch.icp;
+        unsigned long xics_phys;
+        int cpu;
+
+        /* Mark the target VCPU as having an interrupt pending */
+        vcpu->stat.queue_intr++;
+        set_bit(BOOK3S_IRQPRIO_EXTERNAL_LEVEL, &vcpu->arch.pending_exceptions);
+
+        /* Kick self ? Just set MER and return */
+        if (vcpu == this_vcpu) {
+                mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) | LPCR_MER);
+                return;
+        }
+
+        /* Check if the core is loaded, if not, too hard */
+        cpu = vcpu->cpu;
+        if (cpu < 0 || cpu >= nr_cpu_ids) {
+                this_icp->rm_action |= XICS_RM_KICK_VCPU;
+                this_icp->rm_kick_target = vcpu;
+                return;
+        }
+        /* In SMT cpu will always point to thread 0, we adjust it */
+        cpu += vcpu->arch.ptid;
+
+        /* Not too hard, then poke the target */
+        xics_phys = paca[cpu].kvm_hstate.xics_phys;
+        rm_writeb(xics_phys + XICS_MFRR, IPI_PRIORITY);
+}
+
+static void icp_rm_clr_vcpu_irq(struct kvm_vcpu *vcpu)
+{
+        /* Note: Only called on self ! */
+        clear_bit(BOOK3S_IRQPRIO_EXTERNAL_LEVEL,
+                  &vcpu->arch.pending_exceptions);
+        mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) & ~LPCR_MER);
+}
+
+static inline bool icp_rm_try_update(struct kvmppc_icp *icp,
+                                     union kvmppc_icp_state old,
+                                     union kvmppc_icp_state new)
+{
+        struct kvm_vcpu *this_vcpu = local_paca->kvm_hstate.kvm_vcpu;
+        bool success;
+
+        /* Calculate new output value */
+        new.out_ee = (new.xisr && (new.pending_pri < new.cppr));
+
+        /* Attempt atomic update */
+        success = cmpxchg64(&icp->state.raw, old.raw, new.raw) == old.raw;
+        if (!success)
+                goto bail;
+
+        /*
+         * Check for output state update
+         *
+         * Note that this is racy since another processor could be updating
+         * the state already. This is why we never clear the interrupt output
+         * here, we only ever set it. The clear only happens prior to doing
+         * an update and only by the processor itself. Currently we do it
+         * in Accept (H_XIRR) and Up_Cppr (H_XPPR).
+         *
+         * We also do not try to figure out whether the EE state has changed,
+         * we unconditionally set it if the new state calls for it. The reason
+         * for that is that we opportunistically remove the pending interrupt
+         * flag when raising CPPR, so we need to set it back here if an
+         * interrupt is still pending.
+         */
+        if (new.out_ee)
+                icp_rm_set_vcpu_irq(icp->vcpu, this_vcpu);
+
+        /* Expose the state change for debug purposes */
+        this_vcpu->arch.icp->rm_dbgstate = new;
+        this_vcpu->arch.icp->rm_dbgtgt = icp->vcpu;
+
+ bail:
+        return success;
+}
+
+static inline int check_too_hard(struct kvmppc_xics *xics,
+                                 struct kvmppc_icp *icp)
+{
+        return (xics->real_mode_dbg || icp->rm_action) ? H_TOO_HARD : H_SUCCESS;
+}
+
+static void icp_rm_down_cppr(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
+                             u8 new_cppr)
+{
+        union kvmppc_icp_state old_state, new_state;
+        bool resend;
+
+        /*
+         * This handles several related states in one operation:
+         *
+         * ICP State: Down_CPPR
+         *
+         * Load CPPR with new value and if the XISR is 0
+         * then check for resends:
+         *
+         * ICP State: Resend
+         *
+         * If MFRR is more favored than CPPR, check for IPIs
+         * and notify ICS of a potential resend. This is done
+         * asynchronously (when used in real mode, we will have
+         * to exit here).
+         *
+         * We do not handle the complete Check_IPI as documented
+         * here. In the PAPR, this state will be used for both
+         * Set_MFRR and Down_CPPR. However, we know that we aren't
+         * changing the MFRR state here so we don't need to handle
+         * the case of an MFRR causing a reject of a pending irq,
+         * this will have been handled when the MFRR was set in the
+         * first place.
+         *
+         * Thus we don't have to handle rejects, only resends.
+         *
+         * When implementing real mode for HV KVM, resend will lead to
+         * a H_TOO_HARD return and the whole transaction will be handled
+         * in virtual mode.
+         */
+        do {
+                old_state = new_state = ACCESS_ONCE(icp->state);
+
+                /* Down_CPPR */
+                new_state.cppr = new_cppr;
+
+                /*
+                 * Cut down Resend / Check_IPI / IPI
+                 *
+                 * The logic is that we cannot have a pending interrupt
+                 * trumped by an IPI at this point (see above), so we
+                 * know that either the pending interrupt is already an
+                 * IPI (in which case we don't care to override it) or
+                 * it's either more favored than us or non existent
+                 */
+                if (new_state.mfrr < new_cppr &&
+                    new_state.mfrr <= new_state.pending_pri) {
+                        new_state.pending_pri = new_state.mfrr;
+                        new_state.xisr = XICS_IPI;
+                }
+
+                /* Latch/clear resend bit */
+                resend = new_state.need_resend;
+                new_state.need_resend = 0;
+
+        } while (!icp_rm_try_update(icp, old_state, new_state));
+
+        /*
+         * Now handle resend checks. Those are asynchronous to the ICP
+         * state update in HW (ie bus transactions) so we can handle them
+         * separately here as well.
+         */
+        if (resend)
+                icp->rm_action |= XICS_RM_CHECK_RESEND;
+}
+
+
+unsigned long kvmppc_rm_h_xirr(struct kvm_vcpu *vcpu)
+{
+        union kvmppc_icp_state old_state, new_state;
+        struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
+        struct kvmppc_icp *icp = vcpu->arch.icp;
+        u32 xirr;
+
+        if (!xics || !xics->real_mode)
+                return H_TOO_HARD;
+
+        /* First clear the interrupt */
+        icp_rm_clr_vcpu_irq(icp->vcpu);
+
+        /*
+         * ICP State: Accept_Interrupt
+         *
+         * Return the pending interrupt (if any) along with the
+         * current CPPR, then clear the XISR & set CPPR to the
+         * pending priority
+         */
+        do {
+                old_state = new_state = ACCESS_ONCE(icp->state);
+
+                xirr = old_state.xisr | (((u32)old_state.cppr) << 24);
+                if (!old_state.xisr)
+                        break;
+                new_state.cppr = new_state.pending_pri;
+                new_state.pending_pri = 0xff;
+                new_state.xisr = 0;
+
+        } while (!icp_rm_try_update(icp, old_state, new_state));
+
+        /* Return the result in GPR4 */
+        vcpu->arch.gpr[4] = xirr;
+
+        return check_too_hard(xics, icp);
+}
+
+int kvmppc_rm_h_ipi(struct kvm_vcpu *vcpu, unsigned long server,
+                    unsigned long mfrr)
+{
+        union kvmppc_icp_state old_state, new_state;
+        struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
+        struct kvmppc_icp *icp, *this_icp = vcpu->arch.icp;
+        u32 reject;
+        bool resend;
+        bool local;
+
+        if (!xics || !xics->real_mode)
+                return H_TOO_HARD;
+
+        local = this_icp->server_num == server;
+        if (local)
+                icp = this_icp;
+        else
+                icp = kvmppc_xics_find_server(vcpu->kvm, server);
+        if (!icp)
+                return H_PARAMETER;
+
+        /*
+         * ICP state: Set_MFRR
+         *
+         * If the CPPR is more favored than the new MFRR, then
+         * nothing needs to be done as there can be no XISR to
+         * reject.
+         *
+         * If the CPPR is less favored, then we might be replacing
+         * an interrupt, and thus need to possibly reject it as in
+         *
+         * ICP state: Check_IPI
+         */
+        do {
+                old_state = new_state = ACCESS_ONCE(icp->state);
+
+                /* Set_MFRR */
+                new_state.mfrr = mfrr;
+
+                /* Check_IPI */
+                reject = 0;
+                resend = false;
+                if (mfrr < new_state.cppr) {
+                        /* Reject a pending interrupt if not an IPI */
+                        if (mfrr <= new_state.pending_pri)
+                                reject = new_state.xisr;
+                        new_state.pending_pri = mfrr;
+                        new_state.xisr = XICS_IPI;
+                }
+
+                if (mfrr > old_state.mfrr && mfrr > new_state.cppr) {
+                        resend = new_state.need_resend;
+                        new_state.need_resend = 0;
+                }
+        } while (!icp_rm_try_update(icp, old_state, new_state));
+
+        /* Pass rejects to virtual mode */
+        if (reject && reject != XICS_IPI) {
+                this_icp->rm_action |= XICS_RM_REJECT;
+                this_icp->rm_reject = reject;
+        }
+
+        /* Pass resends to virtual mode */
+        if (resend)
+                this_icp->rm_action |= XICS_RM_CHECK_RESEND;
+
+        return check_too_hard(xics, this_icp);
+}
+
+int kvmppc_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr)
+{
+        union kvmppc_icp_state old_state, new_state;
+        struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
+        struct kvmppc_icp *icp = vcpu->arch.icp;
+        u32 reject;
+
+        if (!xics || !xics->real_mode)
+                return H_TOO_HARD;
+
+        /*
+         * ICP State: Set_CPPR
+         *
+         * We can safely compare the new value with the current
+         * value outside of the transaction as the CPPR is only
+         * ever changed by the processor on itself
+         */
+        if (cppr > icp->state.cppr) {
+                icp_rm_down_cppr(xics, icp, cppr);
+                goto bail;
+        } else if (cppr == icp->state.cppr)
+                return H_SUCCESS;
+
+        /*
+         * ICP State: Up_CPPR
+         *
+         * The processor is raising its priority, this can result
+         * in a rejection of a pending interrupt:
+         *
+         * ICP State: Reject_Current
+         *
+         * We can remove EE from the current processor, the update
+         * transaction will set it again if needed
+         */
+        icp_rm_clr_vcpu_irq(icp->vcpu);
+
+        do {
+                old_state = new_state = ACCESS_ONCE(icp->state);
+
+                reject = 0;
+                new_state.cppr = cppr;
+
+                if (cppr <= new_state.pending_pri) {
+                        reject = new_state.xisr;
+                        new_state.xisr = 0;
+                        new_state.pending_pri = 0xff;
+                }
+
+        } while (!icp_rm_try_update(icp, old_state, new_state));
+
+        /* Pass rejects to virtual mode */
+        if (reject && reject != XICS_IPI) {
+                icp->rm_action |= XICS_RM_REJECT;
+                icp->rm_reject = reject;
+        }
+ bail:
+        return check_too_hard(xics, icp);
+}
+
+int kvmppc_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
+{
+        struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
+        struct kvmppc_icp *icp = vcpu->arch.icp;
+        struct kvmppc_ics *ics;
+        struct ics_irq_state *state;
+        u32 irq = xirr & 0x00ffffff;
+        u16 src;
+
+        if (!xics || !xics->real_mode)
+                return H_TOO_HARD;
+
+        /*
+         * ICP State: EOI
+         *
+         * Note: If EOI is incorrectly used by SW to lower the CPPR
+         * value (ie more favored), we do not check for rejection of
+         * a pending interrupt, this is a SW error and PAPR sepcifies
+         * that we don't have to deal with it.
+         *
+         * The sending of an EOI to the ICS is handled after the
+         * CPPR update
+         *
+         * ICP State: Down_CPPR which we handle
+         * in a separate function as it's shared with H_CPPR.
+         */
+        icp_rm_down_cppr(xics, icp, xirr >> 24);
+
+        /* IPIs have no EOI */
+        if (irq == XICS_IPI)
+                goto bail;
+        /*
+         * EOI handling: If the interrupt is still asserted, we need to
+         * resend it. We can take a lockless "peek" at the ICS state here.
+         *
+         * "Message" interrupts will never have "asserted" set
+         */
+        ics = kvmppc_xics_find_ics(xics, irq, &src);
+        if (!ics)
+                goto bail;
+        state = &ics->irq_state[src];
+
+        /* Still asserted, resend it, we make it look like a reject */
+        if (state->asserted) {
+                icp->rm_action |= XICS_RM_REJECT;
+                icp->rm_reject = irq;
+        }
+ bail:
+        return check_too_hard(xics, icp);
+}
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index e33d11f1b977..b02f91e4c70d 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -79,10 +79,6 @@ _GLOBAL(kvmppc_hv_entry_trampoline)
  *                                                                            *
  *****************************************************************************/
 
-#define XICS_XIRR               4
-#define XICS_QIRR               0xc
-#define XICS_IPI                2       /* interrupt source # for IPIs */
-
 /*
  * We come in here when wakened from nap mode on a secondary hw thread.
  * Relocation is off and most register values are lost.
@@ -101,50 +97,51 @@ kvm_start_guest:
         li      r0,1
         stb     r0,PACA_NAPSTATELOST(r13)
 
-        /* get vcpu pointer, NULL if we have no vcpu to run */
-        ld      r4,HSTATE_KVM_VCPU(r13)
-        cmpdi   cr1,r4,0
+        /* were we napping due to cede? */
+        lbz     r0,HSTATE_NAPPING(r13)
+        cmpwi   r0,0
+        bne     kvm_end_cede
+
+        /*
+         * We weren't napping due to cede, so this must be a secondary
+         * thread being woken up to run a guest, or being woken up due
+         * to a stray IPI.  (Or due to some machine check or hypervisor
+         * maintenance interrupt while the core is in KVM.)
+         */
 
         /* Check the wake reason in SRR1 to see why we got here */
         mfspr   r3,SPRN_SRR1
         rlwinm  r3,r3,44-31,0x7         /* extract wake reason field */
         cmpwi   r3,4                    /* was it an external interrupt? */
-        bne     27f
-
-        /*
-         * External interrupt - for now assume it is an IPI, since we
-         * should never get any other interrupts sent to offline threads.
-         * Only do this for secondary threads.
-         */
-        beq     cr1,25f
-        lwz     r3,VCPU_PTID(r4)
-        cmpwi   r3,0
-        beq     27f
-25:     ld      r5,HSTATE_XICS_PHYS(r13)
-        li      r0,0xff
-        li      r6,XICS_QIRR
-        li      r7,XICS_XIRR
+        bne     27f                     /* if not */
+        ld      r5,HSTATE_XICS_PHYS(r13)
+        li      r7,XICS_XIRR            /* if it was an external interrupt, */
         lwzcix  r8,r5,r7                /* get and ack the interrupt */
         sync
         clrldi. r9,r8,40                /* get interrupt source ID. */
-        beq     27f                     /* none there? */
-        cmpwi   r9,XICS_IPI
-        bne     26f
+        beq     28f                     /* none there? */
+        cmpwi   r9,XICS_IPI             /* was it an IPI? */
+        bne     29f
+        li      r0,0xff
+        li      r6,XICS_MFRR
         stbcix  r0,r5,r6                /* clear IPI */
-26:     stwcix  r8,r5,r7                /* EOI the interrupt */
-
-27:     /* XXX should handle hypervisor maintenance interrupts etc. here */
+        stwcix  r8,r5,r7                /* EOI the interrupt */
+        sync                            /* order loading of vcpu after that */
 
-        /* reload vcpu pointer after clearing the IPI */
+        /* get vcpu pointer, NULL if we have no vcpu to run */
         ld      r4,HSTATE_KVM_VCPU(r13)
         cmpdi   r4,0
         /* if we have no vcpu to run, go back to sleep */
         beq     kvm_no_guest
+        b       kvmppc_hv_entry
 
-        /* were we napping due to cede? */
-        lbz     r0,HSTATE_NAPPING(r13)
-        cmpwi   r0,0
-        bne     kvm_end_cede
+27:     /* XXX should handle hypervisor maintenance interrupts etc. here */
+        b       kvm_no_guest
+28:     /* SRR1 said external but ICP said nope?? */
+        b       kvm_no_guest
+29:     /* External non-IPI interrupt to offline secondary thread? help?? */
+        stw     r8,HSTATE_SAVED_XIRR(r13)
+        b       kvm_no_guest
 
 .global kvmppc_hv_entry
 kvmppc_hv_entry:
@@ -260,6 +257,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
         lwz     r5, LPPACA_YIELDCOUNT(r3)
         addi    r5, r5, 1
         stw     r5, LPPACA_YIELDCOUNT(r3)
+        li      r6, 1
+        stb     r6, VCPU_VPA_DIRTY(r4)
 25:
         /* Load up DAR and DSISR */
         ld      r5, VCPU_DAR(r4)
@@ -485,20 +484,20 @@ toc_tlbie_lock:
         mtctr   r6
         mtxer   r7
 
+        ld      r10, VCPU_PC(r4)
+        ld      r11, VCPU_MSR(r4)
 kvmppc_cede_reentry:            /* r4 = vcpu, r13 = paca */
         ld      r6, VCPU_SRR0(r4)
         ld      r7, VCPU_SRR1(r4)
-        ld      r10, VCPU_PC(r4)
-        ld      r11, VCPU_MSR(r4)       /* r11 = vcpu->arch.msr & ~MSR_HV */
 
+        /* r11 = vcpu->arch.msr & ~MSR_HV */
         rldicl  r11, r11, 63 - MSR_HV_LG, 1
         rotldi  r11, r11, 1 + MSR_HV_LG
         ori     r11, r11, MSR_ME
 
         /* Check if we can deliver an external or decrementer interrupt now */
         ld      r0,VCPU_PENDING_EXC(r4)
-        li      r8,(1 << BOOK3S_IRQPRIO_EXTERNAL)
-        oris    r8,r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
+        lis     r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
         and     r0,r0,r8
         cmpdi   cr1,r0,0
         andi.   r0,r11,MSR_EE
@@ -526,10 +525,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
         /* Move SRR0 and SRR1 into the respective regs */
 5:      mtspr   SPRN_SRR0, r6
         mtspr   SPRN_SRR1, r7
-        li      r0,0
-        stb     r0,VCPU_CEDED(r4)       /* cancel cede */
 
 fast_guest_return:
+        li      r0,0
+        stb     r0,VCPU_CEDED(r4)       /* cancel cede */
         mtspr   SPRN_HSRR0,r10
         mtspr   SPRN_HSRR1,r11
 
@@ -676,17 +675,99 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
         cmpwi   r12,BOOK3S_INTERRUPT_SYSCALL
         beq     hcall_try_real_mode
 
-        /* Check for mediated interrupts (could be done earlier really ...) */
+        /* Only handle external interrupts here on arch 206 and later */
 BEGIN_FTR_SECTION
-        cmpwi   r12,BOOK3S_INTERRUPT_EXTERNAL
-        bne+    1f
-        andi.   r0,r11,MSR_EE
-        beq     1f
-        mfspr   r5,SPRN_LPCR
-        andi.   r0,r5,LPCR_MER
-        bne     bounce_ext_interrupt
-1:
-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
+        b       ext_interrupt_to_host
+END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
+
+        /* External interrupt ? */
+        cmpwi   r12, BOOK3S_INTERRUPT_EXTERNAL
+        bne+    ext_interrupt_to_host
+
+        /* External interrupt, first check for host_ipi. If this is
+         * set, we know the host wants us out so let's do it now
+         */
+do_ext_interrupt:
+        lbz     r0, HSTATE_HOST_IPI(r13)
+        cmpwi   r0, 0
+        bne     ext_interrupt_to_host
+
+        /* Now read the interrupt from the ICP */
+        ld      r5, HSTATE_XICS_PHYS(r13)
+        li      r7, XICS_XIRR
+        cmpdi   r5, 0
+        beq-    ext_interrupt_to_host
+        lwzcix  r3, r5, r7
+        rlwinm. r0, r3, 0, 0xffffff
+        sync
+        beq     3f              /* if nothing pending in the ICP */
+
+        /* We found something in the ICP...
+         *
+         * If it's not an IPI, stash it in the PACA and return to
+         * the host, we don't (yet) handle directing real external
+         * interrupts directly to the guest
+         */
+        cmpwi   r0, XICS_IPI
+        bne     ext_stash_for_host
+
+        /* It's an IPI, clear the MFRR and EOI it */
+        li      r0, 0xff
+        li      r6, XICS_MFRR
+        stbcix  r0, r5, r6              /* clear the IPI */
+        stwcix  r3, r5, r7              /* EOI it */
+        sync
+
+        /* We need to re-check host IPI now in case it got set in the
+         * meantime. If it's clear, we bounce the interrupt to the
+         * guest
+         */
+        lbz     r0, HSTATE_HOST_IPI(r13)
+        cmpwi   r0, 0
+        bne-    1f
+
+        /* Allright, looks like an IPI for the guest, we need to set MER */
+3:
+        /* Check if any CPU is heading out to the host, if so head out too */
+        ld      r5, HSTATE_KVM_VCORE(r13)
+        lwz     r0, VCORE_ENTRY_EXIT(r5)
+        cmpwi   r0, 0x100
+        bge     ext_interrupt_to_host
+
+        /* See if there is a pending interrupt for the guest */
+        mfspr   r8, SPRN_LPCR
+        ld      r0, VCPU_PENDING_EXC(r9)
+        /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
+        rldicl. r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
+        rldimi  r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
+        beq     2f
+
+        /* And if the guest EE is set, we can deliver immediately, else
+         * we return to the guest with MER set
+         */
+        andi.   r0, r11, MSR_EE
+        beq     2f
+        mtspr   SPRN_SRR0, r10
+        mtspr   SPRN_SRR1, r11
+        li      r10, BOOK3S_INTERRUPT_EXTERNAL
+        li      r11, (MSR_ME << 1) | 1  /* synthesize MSR_SF | MSR_ME */
+        rotldi  r11, r11, 63
+2:      mr      r4, r9
+        mtspr   SPRN_LPCR, r8
+        b       fast_guest_return
+
+        /* We raced with the host, we need to resend that IPI, bummer */
+1:      li      r0, IPI_PRIORITY
+        stbcix  r0, r5, r6              /* set the IPI */
+        sync
+        b       ext_interrupt_to_host
+
+ext_stash_for_host:
+        /* It's not an IPI and it's for the host, stash it in the PACA
+         * before exit, it will be picked up by the host ICP driver
+         */
+        stw     r3, HSTATE_SAVED_XIRR(r13)
+ext_interrupt_to_host:
 
 guest_exit_cont:                /* r9 = vcpu, r12 = trap, r13 = paca */
         /* Save DEC */
@@ -829,7 +910,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
         beq     44f
         ld      r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
         li      r0,IPI_PRIORITY
-        li      r7,XICS_QIRR
+        li      r7,XICS_MFRR
         stbcix  r0,r7,r8                /* trigger the IPI */
 44:     srdi.   r3,r3,1
         addi    r6,r6,PACA_SIZE
@@ -1018,6 +1099,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
         lwz     r3, LPPACA_YIELDCOUNT(r8)
         addi    r3, r3, 1
         stw     r3, LPPACA_YIELDCOUNT(r8)
+        li      r3, 1
+        stb     r3, VCPU_VPA_DIRTY(r9)
 25:
         /* Save PMU registers if requested */
         /* r8 and cr0.eq are live here */
@@ -1350,11 +1433,19 @@ hcall_real_table:
         .long   0               /* 0x58 */
         .long   0               /* 0x5c */
         .long   0               /* 0x60 */
-        .long   0               /* 0x64 */
-        .long   0               /* 0x68 */
-        .long   0               /* 0x6c */
-        .long   0               /* 0x70 */
-        .long   0               /* 0x74 */
+#ifdef CONFIG_KVM_XICS
+        .long   .kvmppc_rm_h_eoi - hcall_real_table
+        .long   .kvmppc_rm_h_cppr - hcall_real_table
+        .long   .kvmppc_rm_h_ipi - hcall_real_table
+        .long   0               /* 0x70 - H_IPOLL */
+        .long   .kvmppc_rm_h_xirr - hcall_real_table
+#else
+        .long   0               /* 0x64 - H_EOI */
+        .long   0               /* 0x68 - H_CPPR */
+        .long   0               /* 0x6c - H_IPI */
+        .long   0               /* 0x70 - H_IPOLL */
+        .long   0               /* 0x74 - H_XIRR */
+#endif
         .long   0               /* 0x78 */
         .long   0               /* 0x7c */
         .long   0               /* 0x80 */
@@ -1405,15 +1496,6 @@ ignore_hdec:
         mr      r4,r9
         b       fast_guest_return
 
-bounce_ext_interrupt:
-        mr      r4,r9
-        mtspr   SPRN_SRR0,r10
-        mtspr   SPRN_SRR1,r11
-        li      r10,BOOK3S_INTERRUPT_EXTERNAL
-        li      r11,(MSR_ME << 1) | 1   /* synthesize MSR_SF | MSR_ME */
-        rotldi  r11,r11,63
-        b       fast_guest_return
-
 _GLOBAL(kvmppc_h_set_dabr)
         std     r4,VCPU_DABR(r3)
         /* Work around P7 bug where DABR can get corrupted on mtspr */
@@ -1519,6 +1601,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
         b       .
 
 kvm_end_cede:
+        /* get vcpu pointer */
+        ld      r4, HSTATE_KVM_VCPU(r13)
+
         /* Woken by external or decrementer interrupt */
         ld      r1, HSTATE_HOST_R1(r13)
 
@@ -1558,6 +1643,16 @@ kvm_end_cede:
         li      r0,0
         stb     r0,HSTATE_NAPPING(r13)
 
+        /* Check the wake reason in SRR1 to see why we got here */
+        mfspr   r3, SPRN_SRR1
+        rlwinm  r3, r3, 44-31, 0x7      /* extract wake reason field */
+        cmpwi   r3, 4                   /* was it an external interrupt? */
+        li      r12, BOOK3S_INTERRUPT_EXTERNAL
+        mr      r9, r4
+        ld      r10, VCPU_PC(r9)
+        ld      r11, VCPU_MSR(r9)
+        beq     do_ext_interrupt        /* if so */
+
         /* see if any other thread is already exiting */
         lwz     r0,VCORE_ENTRY_EXIT(r5)
         cmpwi   r0,0x100
@@ -1577,8 +1672,7 @@ kvm_cede_prodded:
 
         /* we've ceded but we want to give control to the host */
 kvm_cede_exit:
-        li      r3,H_TOO_HARD
-        blr
+        b       hcall_real_fallback
 
         /* Try to handle a machine check in real mode */
 machine_check_realmode:
@@ -1626,7 +1720,7 @@ secondary_nap:
         beq     37f
         sync
         li      r0, 0xff
-        li      r6, XICS_QIRR
+        li      r6, XICS_MFRR
         stbcix  r0, r5, r6              /* clear the IPI */
         stwcix  r3, r5, r7              /* EOI it */
 37:     sync
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index 5e93438afb06..bdc40b8e77d9 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -762,9 +762,7 @@ program_interrupt:
                         run->exit_reason = KVM_EXIT_MMIO;
                         r = RESUME_HOST_NV;
                         break;
-                case EMULATE_DO_PAPR:
-                        run->exit_reason = KVM_EXIT_PAPR_HCALL;
-                        vcpu->arch.hcall_needed = 1;
+                case EMULATE_EXIT_USER:
                         r = RESUME_HOST_NV;
                         break;
                 default:
@@ -1039,7 +1037,7 @@ struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id)
         if (!vcpu_book3s)
                 goto out;
 
-        vcpu_book3s->shadow_vcpu = (struct kvmppc_book3s_shadow_vcpu *)
+        vcpu_book3s->shadow_vcpu =
                 kzalloc(sizeof(*vcpu_book3s->shadow_vcpu), GFP_KERNEL);
         if (!vcpu_book3s->shadow_vcpu)
                 goto free_vcpu;
@@ -1283,7 +1281,7 @@ int kvmppc_core_prepare_memory_region(struct kvm *kvm,
 
 void kvmppc_core_commit_memory_region(struct kvm *kvm,
                                 struct kvm_userspace_memory_region *mem,
-                                struct kvm_memory_slot old)
+                                const struct kvm_memory_slot *old)
 {
 }
 
@@ -1298,6 +1296,7 @@ int kvmppc_core_init_vm(struct kvm *kvm)
 {
 #ifdef CONFIG_PPC64
         INIT_LIST_HEAD(&kvm->arch.spapr_tce_tables);
+        INIT_LIST_HEAD(&kvm->arch.rtas_tokens);
 #endif
 
         if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
diff --git a/arch/powerpc/kvm/book3s_pr_papr.c b/arch/powerpc/kvm/book3s_pr_papr.c
index ee02b30878ed..b24309c6c2d5 100644
--- a/arch/powerpc/kvm/book3s_pr_papr.c
+++ b/arch/powerpc/kvm/book3s_pr_papr.c
@@ -227,6 +227,13 @@ static int kvmppc_h_pr_put_tce(struct kvm_vcpu *vcpu)
         return EMULATE_DONE;
 }
 
+static int kvmppc_h_pr_xics_hcall(struct kvm_vcpu *vcpu, u32 cmd)
+{
+        long rc = kvmppc_xics_hcall(vcpu, cmd);
+        kvmppc_set_gpr(vcpu, 3, rc);
+        return EMULATE_DONE;
+}
+
 int kvmppc_h_pr(struct kvm_vcpu *vcpu, unsigned long cmd)
 {
         switch (cmd) {
@@ -246,6 +253,20 @@ int kvmppc_h_pr(struct kvm_vcpu *vcpu, unsigned long cmd)
                 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
                 vcpu->stat.halt_wakeup++;
                 return EMULATE_DONE;
+        case H_XIRR:
+        case H_CPPR:
+        case H_EOI:
+        case H_IPI:
+                if (kvmppc_xics_enabled(vcpu))
+                        return kvmppc_h_pr_xics_hcall(vcpu, cmd);
+                break;
+        case H_RTAS:
+                if (list_empty(&vcpu->kvm->arch.rtas_tokens))
+                        return RESUME_HOST;
+                if (kvmppc_rtas_hcall(vcpu))
+                        break;
+                kvmppc_set_gpr(vcpu, 3, 0);
+                return EMULATE_DONE;
         }
 
         return EMULATE_FAIL;
diff --git a/arch/powerpc/kvm/book3s_rtas.c b/arch/powerpc/kvm/book3s_rtas.c
new file mode 100644
index 000000000000..3219ba895246
--- /dev/null
+++ b/arch/powerpc/kvm/book3s_rtas.c
@@ -0,0 +1,274 @@
+/*
+ * Copyright 2012 Michael Ellerman, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/kvm_host.h>
+#include <linux/kvm.h>
+#include <linux/err.h>
+
+#include <asm/uaccess.h>
+#include <asm/kvm_book3s.h>
+#include <asm/kvm_ppc.h>
+#include <asm/hvcall.h>
+#include <asm/rtas.h>
+
+#ifdef CONFIG_KVM_XICS
+static void kvm_rtas_set_xive(struct kvm_vcpu *vcpu, struct rtas_args *args)
+{
+        u32 irq, server, priority;
+        int rc;
+
+        if (args->nargs != 3 || args->nret != 1) {
+                rc = -3;
+                goto out;
+        }
+
+        irq = args->args[0];
+        server = args->args[1];
+        priority = args->args[2];
+
+        rc = kvmppc_xics_set_xive(vcpu->kvm, irq, server, priority);
+        if (rc)
+                rc = -3;
+out:
+        args->rets[0] = rc;
+}
+
+static void kvm_rtas_get_xive(struct kvm_vcpu *vcpu, struct rtas_args *args)
+{
+        u32 irq, server, priority;
+        int rc;
+
+        if (args->nargs != 1 || args->nret != 3) {
+                rc = -3;
+                goto out;
+        }
+
+        irq = args->args[0];
+
+        server = priority = 0;
+        rc = kvmppc_xics_get_xive(vcpu->kvm, irq, &server, &priority);
+        if (rc) {
+                rc = -3;
+                goto out;
+        }
+
+        args->rets[1] = server;
+        args->rets[2] = priority;
+out:
+        args->rets[0] = rc;
+}
+
+static void kvm_rtas_int_off(struct kvm_vcpu *vcpu, struct rtas_args *args)
+{
+        u32 irq;
+        int rc;
+
+        if (args->nargs != 1 || args->nret != 1) {
+                rc = -3;
+                goto out;
+        }
+
+        irq = args->args[0];
+
+        rc = kvmppc_xics_int_off(vcpu->kvm, irq);
+        if (rc)
+                rc = -3;
+out:
+        args->rets[0] = rc;
+}
+
+static void kvm_rtas_int_on(struct kvm_vcpu *vcpu, struct rtas_args *args)
+{
+        u32 irq;
+        int rc;
+
+        if (args->nargs != 1 || args->nret != 1) {
+                rc = -3;
+                goto out;
+        }
+
+        irq = args->args[0];
+
+        rc = kvmppc_xics_int_on(vcpu->kvm, irq);
+        if (rc)
+                rc = -3;
+out:
+        args->rets[0] = rc;
+}
+#endif /* CONFIG_KVM_XICS */
+
+struct rtas_handler {
+        void (*handler)(struct kvm_vcpu *vcpu, struct rtas_args *args);
+        char *name;
+};
+
+static struct rtas_handler rtas_handlers[] = {
+#ifdef CONFIG_KVM_XICS
+        { .name = "ibm,set-xive", .handler = kvm_rtas_set_xive },
+        { .name = "ibm,get-xive", .handler = kvm_rtas_get_xive },
+        { .name = "ibm,int-off",  .handler = kvm_rtas_int_off },
+        { .name = "ibm,int-on",   .handler = kvm_rtas_int_on },
+#endif
+};
+
+struct rtas_token_definition {
+        struct list_head list;
+        struct rtas_handler *handler;
+        u64 token;
+};
+
+static int rtas_name_matches(char *s1, char *s2)
+{
+        struct kvm_rtas_token_args args;
+        return !strncmp(s1, s2, sizeof(args.name));
+}
+
+static int rtas_token_undefine(struct kvm *kvm, char *name)
+{
+        struct rtas_token_definition *d, *tmp;
+
+        lockdep_assert_held(&kvm->lock);
+
+        list_for_each_entry_safe(d, tmp, &kvm->arch.rtas_tokens, list) {
+                if (rtas_name_matches(d->handler->name, name)) {
+                        list_del(&d->list);
+                        kfree(d);
+                        return 0;
+                }
+        }
+
+        /* It's not an error to undefine an undefined token */
+        return 0;
+}
+
+static int rtas_token_define(struct kvm *kvm, char *name, u64 token)
+{
+        struct rtas_token_definition *d;
+        struct rtas_handler *h = NULL;
+        bool found;
+        int i;
+
+        lockdep_assert_held(&kvm->lock);
+
+        list_for_each_entry(d, &kvm->arch.rtas_tokens, list) {
+                if (d->token == token)
+                        return -EEXIST;
+        }
+
+        found = false;
+        for (i = 0; i < ARRAY_SIZE(rtas_handlers); i++) {
+                h = &rtas_handlers[i];
+                if (rtas_name_matches(h->name, name)) {
+                        found = true;
+                        break;
+                }
+        }
+
+        if (!found)
+                return -ENOENT;
+
+        d = kzalloc(sizeof(*d), GFP_KERNEL);
+        if (!d)
+                return -ENOMEM;
+
+        d->handler = h;
+        d->token = token;
+
+        list_add_tail(&d->list, &kvm->arch.rtas_tokens);
+
+        return 0;
+}
+
+int kvm_vm_ioctl_rtas_define_token(struct kvm *kvm, void __user *argp)
+{
+        struct kvm_rtas_token_args args;
+        int rc;
+
+        if (copy_from_user(&args, argp, sizeof(args)))
+                return -EFAULT;
+
+        mutex_lock(&kvm->lock);
+
+        if (args.token)
+                rc = rtas_token_define(kvm, args.name, args.token);
+        else
+                rc = rtas_token_undefine(kvm, args.name);
+
+        mutex_unlock(&kvm->lock);
+
+        return rc;
+}
+
+int kvmppc_rtas_hcall(struct kvm_vcpu *vcpu)
+{
+        struct rtas_token_definition *d;
+        struct rtas_args args;
+        rtas_arg_t *orig_rets;
+        gpa_t args_phys;
+        int rc;
+
+        /* r4 contains the guest physical address of the RTAS args */
+        args_phys = kvmppc_get_gpr(vcpu, 4);
+
+        rc = kvm_read_guest(vcpu->kvm, args_phys, &args, sizeof(args));
+        if (rc)
+                goto fail;
+
+        /*
+         * args->rets is a pointer into args->args. Now that we've
+         * copied args we need to fix it up to point into our copy,
+         * not the guest args. We also need to save the original
+         * value so we can restore it on the way out.
+         */
+        orig_rets = args.rets;
+        args.rets = &args.args[args.nargs];
+
+        mutex_lock(&vcpu->kvm->lock);
+
+        rc = -ENOENT;
+        list_for_each_entry(d, &vcpu->kvm->arch.rtas_tokens, list) {
+                if (d->token == args.token) {
+                        d->handler->handler(vcpu, &args);
+                        rc = 0;
+                        break;
+                }
+        }
+
+        mutex_unlock(&vcpu->kvm->lock);
+
+        if (rc == 0) {
+                args.rets = orig_rets;
+                rc = kvm_write_guest(vcpu->kvm, args_phys, &args, sizeof(args));
+                if (rc)
+                        goto fail;
+        }
+
+        return rc;
+
+fail:
+        /*
+         * We only get here if the guest has called RTAS with a bogus
+         * args pointer. That means we can't get to the args, and so we
+         * can't fail the RTAS call. So fail right out to userspace,
+         * which should kill the guest.
+         */
+        return rc;
+}
+
+void kvmppc_rtas_tokens_free(struct kvm *kvm)
+{
+        struct rtas_token_definition *d, *tmp;
+
+        lockdep_assert_held(&kvm->lock);
+
+        list_for_each_entry_safe(d, tmp, &kvm->arch.rtas_tokens, list) {
+                list_del(&d->list);
+                kfree(d);
+        }
+}
diff --git a/arch/powerpc/kvm/book3s_xics.c b/arch/powerpc/kvm/book3s_xics.c
new file mode 100644
index 000000000000..f7a103756618
--- /dev/null
+++ b/arch/powerpc/kvm/book3s_xics.c
@@ -0,0 +1,1270 @@
+/*
+ * Copyright 2012 Michael Ellerman, IBM Corporation.
+ * Copyright 2012 Benjamin Herrenschmidt, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/kvm_host.h>
+#include <linux/err.h>
+#include <linux/gfp.h>
+#include <linux/anon_inodes.h>
+
+#include <asm/uaccess.h>
+#include <asm/kvm_book3s.h>
+#include <asm/kvm_ppc.h>
+#include <asm/hvcall.h>
+#include <asm/xics.h>
+#include <asm/debug.h>
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+#include "book3s_xics.h"
+
+#if 1
+#define XICS_DBG(fmt...) do { } while (0)
+#else
+#define XICS_DBG(fmt...) trace_printk(fmt)
+#endif
+
+#define ENABLE_REALMODE true
+#define DEBUG_REALMODE  false
+
+/*
+ * LOCKING
+ * =======
+ *
+ * Each ICS has a mutex protecting the information about the IRQ
+ * sources and avoiding simultaneous deliveries if the same interrupt.
+ *
+ * ICP operations are done via a single compare & swap transaction
+ * (most ICP state fits in the union kvmppc_icp_state)
+ */
+
+/*
+ * TODO
+ * ====
+ *
+ * - To speed up resends, keep a bitmap of "resend" set bits in the
+ *   ICS
+ *
+ * - Speed up server# -> ICP lookup (array ? hash table ?)
+ *
+ * - Make ICS lockless as well, or at least a per-interrupt lock or hashed
+ *   locks array to improve scalability
+ */
+
+/* -- ICS routines -- */
+
+static void icp_deliver_irq(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
+                            u32 new_irq);
+
+static int ics_deliver_irq(struct kvmppc_xics *xics, u32 irq, u32 level,
+                           bool report_status)
+{
+        struct ics_irq_state *state;
+        struct kvmppc_ics *ics;
+        u16 src;
+
+        XICS_DBG("ics deliver %#x (level: %d)\n", irq, level);
+
+        ics = kvmppc_xics_find_ics(xics, irq, &src);
+        if (!ics) {
+                XICS_DBG("ics_deliver_irq: IRQ 0x%06x not found !\n", irq);
+                return -EINVAL;
+        }
+        state = &ics->irq_state[src];
+        if (!state->exists)
+                return -EINVAL;
+
+        if (report_status)
+                return state->asserted;
+
+        /*
+         * We set state->asserted locklessly. This should be fine as
+         * we are the only setter, thus concurrent access is undefined
+         * to begin with.
+         */
+        if (level == KVM_INTERRUPT_SET_LEVEL)
+                state->asserted = 1;
+        else if (level == KVM_INTERRUPT_UNSET) {
+                state->asserted = 0;
+                return 0;
+        }
+
+        /* Attempt delivery */
+        icp_deliver_irq(xics, NULL, irq);
+
+        return state->asserted;
+}
+
+static void ics_check_resend(struct kvmppc_xics *xics, struct kvmppc_ics *ics,
+                             struct kvmppc_icp *icp)
+{
+        int i;
+
+        mutex_lock(&ics->lock);
+
+        for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) {
+                struct ics_irq_state *state = &ics->irq_state[i];
+
+                if (!state->resend)
+                        continue;
+
+                XICS_DBG("resend %#x prio %#x\n", state->number,
+                              state->priority);
+
+                mutex_unlock(&ics->lock);
+                icp_deliver_irq(xics, icp, state->number);
+                mutex_lock(&ics->lock);
+        }
+
+        mutex_unlock(&ics->lock);
+}
+
+static bool write_xive(struct kvmppc_xics *xics, struct kvmppc_ics *ics,
+                       struct ics_irq_state *state,
+                       u32 server, u32 priority, u32 saved_priority)
+{
+        bool deliver;
+
+        mutex_lock(&ics->lock);
+
+        state->server = server;
+        state->priority = priority;
+        state->saved_priority = saved_priority;
+        deliver = false;
+        if ((state->masked_pending || state->resend) && priority != MASKED) {
+                state->masked_pending = 0;
+                deliver = true;
+        }
+
+        mutex_unlock(&ics->lock);
+
+        return deliver;
+}
+
+int kvmppc_xics_set_xive(struct kvm *kvm, u32 irq, u32 server, u32 priority)
+{
+        struct kvmppc_xics *xics = kvm->arch.xics;
+        struct kvmppc_icp *icp;
+        struct kvmppc_ics *ics;
+        struct ics_irq_state *state;
+        u16 src;
+
+        if (!xics)
+                return -ENODEV;
+
+        ics = kvmppc_xics_find_ics(xics, irq, &src);
+        if (!ics)
+                return -EINVAL;
+        state = &ics->irq_state[src];
+
+        icp = kvmppc_xics_find_server(kvm, server);
+        if (!icp)
+                return -EINVAL;
+
+        XICS_DBG("set_xive %#x server %#x prio %#x MP:%d RS:%d\n",
+                 irq, server, priority,
+                 state->masked_pending, state->resend);
+
+        if (write_xive(xics, ics, state, server, priority, priority))
+                icp_deliver_irq(xics, icp, irq);
+
+        return 0;
+}
+
+int kvmppc_xics_get_xive(struct kvm *kvm, u32 irq, u32 *server, u32 *priority)
+{
+        struct kvmppc_xics *xics = kvm->arch.xics;
+        struct kvmppc_ics *ics;
+        struct ics_irq_state *state;
+        u16 src;
+
+        if (!xics)
+                return -ENODEV;
+
+        ics = kvmppc_xics_find_ics(xics, irq, &src);
+        if (!ics)
+                return -EINVAL;
+        state = &ics->irq_state[src];
+
+        mutex_lock(&ics->lock);
+        *server = state->server;
+        *priority = state->priority;
+        mutex_unlock(&ics->lock);
+
+        return 0;
+}
+
+int kvmppc_xics_int_on(struct kvm *kvm, u32 irq)
+{
+        struct kvmppc_xics *xics = kvm->arch.xics;
+        struct kvmppc_icp *icp;
+        struct kvmppc_ics *ics;
+        struct ics_irq_state *state;
+        u16 src;
+
+        if (!xics)
+                return -ENODEV;
+
+        ics = kvmppc_xics_find_ics(xics, irq, &src);
+        if (!ics)
+                return -EINVAL;
+        state = &ics->irq_state[src];
+
+        icp = kvmppc_xics_find_server(kvm, state->server);
+        if (!icp)
+                return -EINVAL;
+
+        if (write_xive(xics, ics, state, state->server, state->saved_priority,
+                       state->saved_priority))
+                icp_deliver_irq(xics, icp, irq);
+
+        return 0;
+}
+
+int kvmppc_xics_int_off(struct kvm *kvm, u32 irq)
+{
+        struct kvmppc_xics *xics = kvm->arch.xics;
+        struct kvmppc_ics *ics;
+        struct ics_irq_state *state;
+        u16 src;
+
+        if (!xics)
+                return -ENODEV;
+
+        ics = kvmppc_xics_find_ics(xics, irq, &src);
+        if (!ics)
+                return -EINVAL;
+        state = &ics->irq_state[src];
+
+        write_xive(xics, ics, state, state->server, MASKED, state->priority);
+
+        return 0;
+}
+
+/* -- ICP routines, including hcalls -- */
+
+static inline bool icp_try_update(struct kvmppc_icp *icp,
+                                  union kvmppc_icp_state old,
+                                  union kvmppc_icp_state new,
+                                  bool change_self)
+{
+        bool success;
+
+        /* Calculate new output value */
+        new.out_ee = (new.xisr && (new.pending_pri < new.cppr));
+
+        /* Attempt atomic update */
+        success = cmpxchg64(&icp->state.raw, old.raw, new.raw) == old.raw;
+        if (!success)
+                goto bail;
+
+        XICS_DBG("UPD [%04x] - C:%02x M:%02x PP: %02x PI:%06x R:%d O:%d\n",
+                 icp->server_num,
+                 old.cppr, old.mfrr, old.pending_pri, old.xisr,
+                 old.need_resend, old.out_ee);
+        XICS_DBG("UPD        - C:%02x M:%02x PP: %02x PI:%06x R:%d O:%d\n",
+                 new.cppr, new.mfrr, new.pending_pri, new.xisr,
+                 new.need_resend, new.out_ee);
+        /*
+         * Check for output state update
+         *
+         * Note that this is racy since another processor could be updating
+         * the state already. This is why we never clear the interrupt output
+         * here, we only ever set it. The clear only happens prior to doing
+         * an update and only by the processor itself. Currently we do it
+         * in Accept (H_XIRR) and Up_Cppr (H_XPPR).
+         *
+         * We also do not try to figure out whether the EE state has changed,
+         * we unconditionally set it if the new state calls for it. The reason
+         * for that is that we opportunistically remove the pending interrupt
+         * flag when raising CPPR, so we need to set it back here if an
+         * interrupt is still pending.
+         */
+        if (new.out_ee) {
+                kvmppc_book3s_queue_irqprio(icp->vcpu,
+                                            BOOK3S_INTERRUPT_EXTERNAL_LEVEL);
+                if (!change_self)
+                        kvmppc_fast_vcpu_kick(icp->vcpu);
+        }
+ bail:
+        return success;
+}
+
+static void icp_check_resend(struct kvmppc_xics *xics,
+                             struct kvmppc_icp *icp)
+{
+        u32 icsid;
+
+        /* Order this load with the test for need_resend in the caller */
+        smp_rmb();
+        for_each_set_bit(icsid, icp->resend_map, xics->max_icsid + 1) {
+                struct kvmppc_ics *ics = xics->ics[icsid];
+
+                if (!test_and_clear_bit(icsid, icp->resend_map))
+                        continue;
+                if (!ics)
+                        continue;
+                ics_check_resend(xics, ics, icp);
+        }
+}
+
+static bool icp_try_to_deliver(struct kvmppc_icp *icp, u32 irq, u8 priority,
+                               u32 *reject)
+{
+        union kvmppc_icp_state old_state, new_state;
+        bool success;
+
+        XICS_DBG("try deliver %#x(P:%#x) to server %#x\n", irq, priority,
+                 icp->server_num);
+
+        do {
+                old_state = new_state = ACCESS_ONCE(icp->state);
+
+                *reject = 0;
+
+                /* See if we can deliver */
+                success = new_state.cppr > priority &&
+                        new_state.mfrr > priority &&
+                        new_state.pending_pri > priority;
+
+                /*
+                 * If we can, check for a rejection and perform the
+                 * delivery
+                 */
+                if (success) {
+                        *reject = new_state.xisr;
+                        new_state.xisr = irq;
+                        new_state.pending_pri = priority;
+                } else {
+                        /*
+                         * If we failed to deliver we set need_resend
+                         * so a subsequent CPPR state change causes us
+                         * to try a new delivery.
+                         */
+                        new_state.need_resend = true;
+                }
+
+        } while (!icp_try_update(icp, old_state, new_state, false));
+
+        return success;
+}
+
+static void icp_deliver_irq(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
+                            u32 new_irq)
+{
+        struct ics_irq_state *state;
+        struct kvmppc_ics *ics;
+        u32 reject;
+        u16 src;
+
+        /*
+         * This is used both for initial delivery of an interrupt and
+         * for subsequent rejection.
+         *
+         * Rejection can be racy vs. resends. We have evaluated the
+         * rejection in an atomic ICP transaction which is now complete,
+         * so potentially the ICP can already accept the interrupt again.
+         *
+         * So we need to retry the delivery. Essentially the reject path
+         * boils down to a failed delivery. Always.
+         *
+         * Now the interrupt could also have moved to a different target,
+         * thus we may need to re-do the ICP lookup as well
+         */
+
+ again:
+        /* Get the ICS state and lock it */
+        ics = kvmppc_xics_find_ics(xics, new_irq, &src);
+        if (!ics) {
+                XICS_DBG("icp_deliver_irq: IRQ 0x%06x not found !\n", new_irq);
+                return;
+        }
+        state = &ics->irq_state[src];
+
+        /* Get a lock on the ICS */
+        mutex_lock(&ics->lock);
+
+        /* Get our server */
+        if (!icp || state->server != icp->server_num) {
+                icp = kvmppc_xics_find_server(xics->kvm, state->server);
+                if (!icp) {
+                        pr_warn("icp_deliver_irq: IRQ 0x%06x server 0x%x not found !\n",
+                                new_irq, state->server);
+                        goto out;
+                }
+        }
+
+        /* Clear the resend bit of that interrupt */
+        state->resend = 0;
+
+        /*
+         * If masked, bail out
+         *
+         * Note: PAPR doesn't mention anything about masked pending
+         * when doing a resend, only when doing a delivery.
+         *
+         * However that would have the effect of losing a masked
+         * interrupt that was rejected and isn't consistent with
+         * the whole masked_pending business which is about not
+         * losing interrupts that occur while masked.
+         *
+         * I don't differenciate normal deliveries and resends, this
+         * implementation will differ from PAPR and not lose such
+         * interrupts.
+         */
+        if (state->priority == MASKED) {
+                XICS_DBG("irq %#x masked pending\n", new_irq);
+                state->masked_pending = 1;
+                goto out;
+        }
+
+        /*
+         * Try the delivery, this will set the need_resend flag
+         * in the ICP as part of the atomic transaction if the
+         * delivery is not possible.
+         *
+         * Note that if successful, the new delivery might have itself
+         * rejected an interrupt that was "delivered" before we took the
+         * icp mutex.
+         *
+         * In this case we do the whole sequence all over again for the
+         * new guy. We cannot assume that the rejected interrupt is less
+         * favored than the new one, and thus doesn't need to be delivered,
+         * because by the time we exit icp_try_to_deliver() the target
+         * processor may well have alrady consumed & completed it, and thus
+         * the rejected interrupt might actually be already acceptable.
+         */
+        if (icp_try_to_deliver(icp, new_irq, state->priority, &reject)) {
+                /*
+                 * Delivery was successful, did we reject somebody else ?
+                 */
+                if (reject && reject != XICS_IPI) {
+                        mutex_unlock(&ics->lock);
+                        new_irq = reject;
+                        goto again;
+                }
+        } else {
+                /*
+                 * We failed to deliver the interrupt we need to set the
+                 * resend map bit and mark the ICS state as needing a resend
+                 */
+                set_bit(ics->icsid, icp->resend_map);
+                state->resend = 1;
+
+                /*
+                 * If the need_resend flag got cleared in the ICP some time
+                 * between icp_try_to_deliver() atomic update and now, then
+                 * we know it might have missed the resend_map bit. So we
+                 * retry
+                 */
+                smp_mb();
+                if (!icp->state.need_resend) {
+                        mutex_unlock(&ics->lock);
+                        goto again;
+                }
+        }
+ out:
+        mutex_unlock(&ics->lock);
+}
+
+static void icp_down_cppr(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
+                          u8 new_cppr)
+{
+        union kvmppc_icp_state old_state, new_state;
+        bool resend;
+
+        /*
+         * This handles several related states in one operation:
+         *
+         * ICP State: Down_CPPR
+         *
+         * Load CPPR with new value and if the XISR is 0
+         * then check for resends:
+         *
+         * ICP State: Resend
+         *
+         * If MFRR is more favored than CPPR, check for IPIs
+         * and notify ICS of a potential resend. This is done
+         * asynchronously (when used in real mode, we will have
+         * to exit here).
+         *
+         * We do not handle the complete Check_IPI as documented
+         * here. In the PAPR, this state will be used for both
+         * Set_MFRR and Down_CPPR. However, we know that we aren't
+         * changing the MFRR state here so we don't need to handle
+         * the case of an MFRR causing a reject of a pending irq,
+         * this will have been handled when the MFRR was set in the
+         * first place.
+         *
+         * Thus we don't have to handle rejects, only resends.
+         *
+         * When implementing real mode for HV KVM, resend will lead to
+         * a H_TOO_HARD return and the whole transaction will be handled
+         * in virtual mode.
+         */
+        do {
+                old_state = new_state = ACCESS_ONCE(icp->state);
+
+                /* Down_CPPR */
+                new_state.cppr = new_cppr;
+
+                /*
+                 * Cut down Resend / Check_IPI / IPI
+                 *
+                 * The logic is that we cannot have a pending interrupt
+                 * trumped by an IPI at this point (see above), so we
+                 * know that either the pending interrupt is already an
+                 * IPI (in which case we don't care to override it) or
+                 * it's either more favored than us or non existent
+                 */
+                if (new_state.mfrr < new_cppr &&
+                    new_state.mfrr <= new_state.pending_pri) {
+                        WARN_ON(new_state.xisr != XICS_IPI &&
+                                new_state.xisr != 0);
+                        new_state.pending_pri = new_state.mfrr;
+                        new_state.xisr = XICS_IPI;
+                }
+
+                /* Latch/clear resend bit */
+                resend = new_state.need_resend;
+                new_state.need_resend = 0;
+
+        } while (!icp_try_update(icp, old_state, new_state, true));
+
+        /*
+         * Now handle resend checks. Those are asynchronous to the ICP
+         * state update in HW (ie bus transactions) so we can handle them
+         * separately here too
+         */
+        if (resend)
+                icp_check_resend(xics, icp);
+}
+
+static noinline unsigned long kvmppc_h_xirr(struct kvm_vcpu *vcpu)
+{
+        union kvmppc_icp_state old_state, new_state;
+        struct kvmppc_icp *icp = vcpu->arch.icp;
+        u32 xirr;
+
+        /* First, remove EE from the processor */
+        kvmppc_book3s_dequeue_irqprio(icp->vcpu,
+                                      BOOK3S_INTERRUPT_EXTERNAL_LEVEL);
+
+        /*
+         * ICP State: Accept_Interrupt
+         *
+         * Return the pending interrupt (if any) along with the
+         * current CPPR, then clear the XISR & set CPPR to the
+         * pending priority
+         */
+        do {
+                old_state = new_state = ACCESS_ONCE(icp->state);
+
+                xirr = old_state.xisr | (((u32)old_state.cppr) << 24);
+                if (!old_state.xisr)
+                        break;
+                new_state.cppr = new_state.pending_pri;
+                new_state.pending_pri = 0xff;
+                new_state.xisr = 0;
+
+        } while (!icp_try_update(icp, old_state, new_state, true));
+
+        XICS_DBG("h_xirr vcpu %d xirr %#x\n", vcpu->vcpu_id, xirr);
+
+        return xirr;
+}
+
+static noinline int kvmppc_h_ipi(struct kvm_vcpu *vcpu, unsigned long server,
+                                 unsigned long mfrr)
+{
+        union kvmppc_icp_state old_state, new_state;
+        struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
+        struct kvmppc_icp *icp;
+        u32 reject;
+        bool resend;
+        bool local;
+
+        XICS_DBG("h_ipi vcpu %d to server %lu mfrr %#lx\n",
+                 vcpu->vcpu_id, server, mfrr);
+
+        icp = vcpu->arch.icp;
+        local = icp->server_num == server;
+        if (!local) {
+                icp = kvmppc_xics_find_server(vcpu->kvm, server);
+                if (!icp)
+                        return H_PARAMETER;
+        }
+
+        /*
+         * ICP state: Set_MFRR
+         *
+         * If the CPPR is more favored than the new MFRR, then
+         * nothing needs to be rejected as there can be no XISR to
+         * reject.  If the MFRR is being made less favored then
+         * there might be a previously-rejected interrupt needing
+         * to be resent.
+         *
+         * If the CPPR is less favored, then we might be replacing
+         * an interrupt, and thus need to possibly reject it as in
+         *
+         * ICP state: Check_IPI
+         */
+        do {
+                old_state = new_state = ACCESS_ONCE(icp->state);
+
+                /* Set_MFRR */
+                new_state.mfrr = mfrr;
+
+                /* Check_IPI */
+                reject = 0;
+                resend = false;
+                if (mfrr < new_state.cppr) {
+                        /* Reject a pending interrupt if not an IPI */
+                        if (mfrr <= new_state.pending_pri)
+                                reject = new_state.xisr;
+                        new_state.pending_pri = mfrr;
+                        new_state.xisr = XICS_IPI;
+                }
+
+                if (mfrr > old_state.mfrr && mfrr > new_state.cppr) {
+                        resend = new_state.need_resend;
+                        new_state.need_resend = 0;
+                }
+        } while (!icp_try_update(icp, old_state, new_state, local));
+
+        /* Handle reject */
+        if (reject && reject != XICS_IPI)
+                icp_deliver_irq(xics, icp, reject);
+
+        /* Handle resend */
+        if (resend)
+                icp_check_resend(xics, icp);
+
+        return H_SUCCESS;
+}
+
+static noinline void kvmppc_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr)
+{
+        union kvmppc_icp_state old_state, new_state;
+        struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
+        struct kvmppc_icp *icp = vcpu->arch.icp;
+        u32 reject;
+
+        XICS_DBG("h_cppr vcpu %d cppr %#lx\n", vcpu->vcpu_id, cppr);
+
+        /*
+         * ICP State: Set_CPPR
+         *
+         * We can safely compare the new value with the current
+         * value outside of the transaction as the CPPR is only
+         * ever changed by the processor on itself
+         */
+        if (cppr > icp->state.cppr)
+                icp_down_cppr(xics, icp, cppr);
+        else if (cppr == icp->state.cppr)
+                return;
+
+        /*
+         * ICP State: Up_CPPR
+         *
+         * The processor is raising its priority, this can result
+         * in a rejection of a pending interrupt:
+         *
+         * ICP State: Reject_Current
+         *
+         * We can remove EE from the current processor, the update
+         * transaction will set it again if needed
+         */
+        kvmppc_book3s_dequeue_irqprio(icp->vcpu,
+                                      BOOK3S_INTERRUPT_EXTERNAL_LEVEL);
+
+        do {
+                old_state = new_state = ACCESS_ONCE(icp->state);
+
+                reject = 0;
+                new_state.cppr = cppr;
+
+                if (cppr <= new_state.pending_pri) {
+                        reject = new_state.xisr;
+                        new_state.xisr = 0;
+                        new_state.pending_pri = 0xff;
+                }
+
+        } while (!icp_try_update(icp, old_state, new_state, true));
+
+        /*
+         * Check for rejects. They are handled by doing a new delivery
+         * attempt (see comments in icp_deliver_irq).
+         */
+        if (reject && reject != XICS_IPI)
+                icp_deliver_irq(xics, icp, reject);
+}
+
+static noinline int kvmppc_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
+{
+        struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
+        struct kvmppc_icp *icp = vcpu->arch.icp;
+        struct kvmppc_ics *ics;
+        struct ics_irq_state *state;
+        u32 irq = xirr & 0x00ffffff;
+        u16 src;
+
+        XICS_DBG("h_eoi vcpu %d eoi %#lx\n", vcpu->vcpu_id, xirr);
+
+        /*
+         * ICP State: EOI
+         *
+         * Note: If EOI is incorrectly used by SW to lower the CPPR
+         * value (ie more favored), we do not check for rejection of
+         * a pending interrupt, this is a SW error and PAPR sepcifies
+         * that we don't have to deal with it.
+         *
+         * The sending of an EOI to the ICS is handled after the
+         * CPPR update
+         *
+         * ICP State: Down_CPPR which we handle
+         * in a separate function as it's shared with H_CPPR.
+         */
+        icp_down_cppr(xics, icp, xirr >> 24);
+
+        /* IPIs have no EOI */
+        if (irq == XICS_IPI)
+                return H_SUCCESS;
+        /*
+         * EOI handling: If the interrupt is still asserted, we need to
+         * resend it. We can take a lockless "peek" at the ICS state here.
+         *
+         * "Message" interrupts will never have "asserted" set
+         */
+        ics = kvmppc_xics_find_ics(xics, irq, &src);
+        if (!ics) {
+                XICS_DBG("h_eoi: IRQ 0x%06x not found !\n", irq);
+                return H_PARAMETER;
+        }
+        state = &ics->irq_state[src];
+
+        /* Still asserted, resend it */
+        if (state->asserted)
+                icp_deliver_irq(xics, icp, irq);
+
+        return H_SUCCESS;
+}
+
+static noinline int kvmppc_xics_rm_complete(struct kvm_vcpu *vcpu, u32 hcall)
+{
+        struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
+        struct kvmppc_icp *icp = vcpu->arch.icp;
+
+        XICS_DBG("XICS_RM: H_%x completing, act: %x state: %lx tgt: %p\n",
+                 hcall, icp->rm_action, icp->rm_dbgstate.raw, icp->rm_dbgtgt);
+
+        if (icp->rm_action & XICS_RM_KICK_VCPU)
+                kvmppc_fast_vcpu_kick(icp->rm_kick_target);
+        if (icp->rm_action & XICS_RM_CHECK_RESEND)
+                icp_check_resend(xics, icp);
+        if (icp->rm_action & XICS_RM_REJECT)
+                icp_deliver_irq(xics, icp, icp->rm_reject);
+
+        icp->rm_action = 0;
+
+        return H_SUCCESS;
+}
+
+int kvmppc_xics_hcall(struct kvm_vcpu *vcpu, u32 req)
+{
+        struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
+        unsigned long res;
+        int rc = H_SUCCESS;
+
+        /* Check if we have an ICP */
+        if (!xics || !vcpu->arch.icp)
+                return H_HARDWARE;
+
+        /* Check for real mode returning too hard */
+        if (xics->real_mode)
+                return kvmppc_xics_rm_complete(vcpu, req);
+
+        switch (req) {
+        case H_XIRR:
+                res = kvmppc_h_xirr(vcpu);
+                kvmppc_set_gpr(vcpu, 4, res);
+                break;
+        case H_CPPR:
+                kvmppc_h_cppr(vcpu, kvmppc_get_gpr(vcpu, 4));
+                break;
+        case H_EOI:
+                rc = kvmppc_h_eoi(vcpu, kvmppc_get_gpr(vcpu, 4));
+                break;
+        case H_IPI:
+                rc = kvmppc_h_ipi(vcpu, kvmppc_get_gpr(vcpu, 4),
+                                  kvmppc_get_gpr(vcpu, 5));
+                break;
+        }
+
+        return rc;
+}
+
+
+/* -- Initialisation code etc. -- */
+
+static int xics_debug_show(struct seq_file *m, void *private)
+{
+        struct kvmppc_xics *xics = m->private;
+        struct kvm *kvm = xics->kvm;
+        struct kvm_vcpu *vcpu;
+        int icsid, i;
+
+        if (!kvm)
+                return 0;
+
+        seq_printf(m, "=========\nICP state\n=========\n");
+
+        kvm_for_each_vcpu(i, vcpu, kvm) {
+                struct kvmppc_icp *icp = vcpu->arch.icp;
+                union kvmppc_icp_state state;
+
+                if (!icp)
+                        continue;
+
+                state.raw = ACCESS_ONCE(icp->state.raw);
+                seq_printf(m, "cpu server %#lx XIRR:%#x PPRI:%#x CPPR:%#x MFRR:%#x OUT:%d NR:%d\n",
+                           icp->server_num, state.xisr,
+                           state.pending_pri, state.cppr, state.mfrr,
+                           state.out_ee, state.need_resend);
+        }
+
+        for (icsid = 0; icsid <= KVMPPC_XICS_MAX_ICS_ID; icsid++) {
+                struct kvmppc_ics *ics = xics->ics[icsid];
+
+                if (!ics)
+                        continue;
+
+                seq_printf(m, "=========\nICS state for ICS 0x%x\n=========\n",
+                           icsid);
+
+                mutex_lock(&ics->lock);
+
+                for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) {
+                        struct ics_irq_state *irq = &ics->irq_state[i];
+
+                        seq_printf(m, "irq 0x%06x: server %#x prio %#x save prio %#x asserted %d resend %d masked pending %d\n",
+                                   irq->number, irq->server, irq->priority,
+                                   irq->saved_priority, irq->asserted,
+                                   irq->resend, irq->masked_pending);
+
+                }
+                mutex_unlock(&ics->lock);
+        }
+        return 0;
+}
+
+static int xics_debug_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, xics_debug_show, inode->i_private);
+}
+
+static const struct file_operations xics_debug_fops = {
+        .open = xics_debug_open,
+        .read = seq_read,
+        .llseek = seq_lseek,
+        .release = single_release,
+};
+
+static void xics_debugfs_init(struct kvmppc_xics *xics)
+{
+        char *name;
+
+        name = kasprintf(GFP_KERNEL, "kvm-xics-%p", xics);
+        if (!name) {
+                pr_err("%s: no memory for name\n", __func__);
+                return;
+        }
+
+        xics->dentry = debugfs_create_file(name, S_IRUGO, powerpc_debugfs_root,
+                                           xics, &xics_debug_fops);
+
+        pr_debug("%s: created %s\n", __func__, name);
+        kfree(name);
+}
+
+static struct kvmppc_ics *kvmppc_xics_create_ics(struct kvm *kvm,
+                                        struct kvmppc_xics *xics, int irq)
+{
+        struct kvmppc_ics *ics;
+        int i, icsid;
+
+        icsid = irq >> KVMPPC_XICS_ICS_SHIFT;
+
+        mutex_lock(&kvm->lock);
+
+        /* ICS already exists - somebody else got here first */
+        if (xics->ics[icsid])
+                goto out;
+
+        /* Create the ICS */
+        ics = kzalloc(sizeof(struct kvmppc_ics), GFP_KERNEL);
+        if (!ics)
+                goto out;
+
+        mutex_init(&ics->lock);
+        ics->icsid = icsid;
+
+        for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) {
+                ics->irq_state[i].number = (icsid << KVMPPC_XICS_ICS_SHIFT) | i;
+                ics->irq_state[i].priority = MASKED;
+                ics->irq_state[i].saved_priority = MASKED;
+        }
+        smp_wmb();
+        xics->ics[icsid] = ics;
+
+        if (icsid > xics->max_icsid)
+                xics->max_icsid = icsid;
+
+ out:
+        mutex_unlock(&kvm->lock);
+        return xics->ics[icsid];
+}
+
+int kvmppc_xics_create_icp(struct kvm_vcpu *vcpu, unsigned long server_num)
+{
+        struct kvmppc_icp *icp;
+
+        if (!vcpu->kvm->arch.xics)
+                return -ENODEV;
+
+        if (kvmppc_xics_find_server(vcpu->kvm, server_num))
+                return -EEXIST;
+
+        icp = kzalloc(sizeof(struct kvmppc_icp), GFP_KERNEL);
+        if (!icp)
+                return -ENOMEM;
+
+        icp->vcpu = vcpu;
+        icp->server_num = server_num;
+        icp->state.mfrr = MASKED;
+        icp->state.pending_pri = MASKED;
+        vcpu->arch.icp = icp;
+
+        XICS_DBG("created server for vcpu %d\n", vcpu->vcpu_id);
+
+        return 0;
+}
+
+u64 kvmppc_xics_get_icp(struct kvm_vcpu *vcpu)
+{
+        struct kvmppc_icp *icp = vcpu->arch.icp;
+        union kvmppc_icp_state state;
+
+        if (!icp)
+                return 0;
+        state = icp->state;
+        return ((u64)state.cppr << KVM_REG_PPC_ICP_CPPR_SHIFT) |
+                ((u64)state.xisr << KVM_REG_PPC_ICP_XISR_SHIFT) |
+                ((u64)state.mfrr << KVM_REG_PPC_ICP_MFRR_SHIFT) |
+                ((u64)state.pending_pri << KVM_REG_PPC_ICP_PPRI_SHIFT);
+}
+
+int kvmppc_xics_set_icp(struct kvm_vcpu *vcpu, u64 icpval)
+{
+        struct kvmppc_icp *icp = vcpu->arch.icp;
+        struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
+        union kvmppc_icp_state old_state, new_state;
+        struct kvmppc_ics *ics;
+        u8 cppr, mfrr, pending_pri;
+        u32 xisr;
+        u16 src;
+        bool resend;
+
+        if (!icp || !xics)
+                return -ENOENT;
+
+        cppr = icpval >> KVM_REG_PPC_ICP_CPPR_SHIFT;
+        xisr = (icpval >> KVM_REG_PPC_ICP_XISR_SHIFT) &
+                KVM_REG_PPC_ICP_XISR_MASK;
+        mfrr = icpval >> KVM_REG_PPC_ICP_MFRR_SHIFT;
+        pending_pri = icpval >> KVM_REG_PPC_ICP_PPRI_SHIFT;
+
+        /* Require the new state to be internally consistent */
+        if (xisr == 0) {
+                if (pending_pri != 0xff)
+                        return -EINVAL;
+        } else if (xisr == XICS_IPI) {
+                if (pending_pri != mfrr || pending_pri >= cppr)
+                        return -EINVAL;
+        } else {
+                if (pending_pri >= mfrr || pending_pri >= cppr)
+                        return -EINVAL;
+                ics = kvmppc_xics_find_ics(xics, xisr, &src);
+                if (!ics)
+                        return -EINVAL;
+        }
+
+        new_state.raw = 0;
+        new_state.cppr = cppr;
+        new_state.xisr = xisr;
+        new_state.mfrr = mfrr;
+        new_state.pending_pri = pending_pri;
+
+        /*
+         * Deassert the CPU interrupt request.
+         * icp_try_update will reassert it if necessary.
+         */
+        kvmppc_book3s_dequeue_irqprio(icp->vcpu,
+                                      BOOK3S_INTERRUPT_EXTERNAL_LEVEL);
+
+        /*
+         * Note that if we displace an interrupt from old_state.xisr,
+         * we don't mark it as rejected.  We expect userspace to set
+         * the state of the interrupt sources to be consistent with
+         * the ICP states (either before or afterwards, which doesn't
+         * matter).  We do handle resends due to CPPR becoming less
+         * favoured because that is necessary to end up with a
+         * consistent state in the situation where userspace restores
+         * the ICS states before the ICP states.
+         */
+        do {
+                old_state = ACCESS_ONCE(icp->state);
+
+                if (new_state.mfrr <= old_state.mfrr) {
+                        resend = false;
+                        new_state.need_resend = old_state.need_resend;
+                } else {
+                        resend = old_state.need_resend;
+                        new_state.need_resend = 0;
+                }
+        } while (!icp_try_update(icp, old_state, new_state, false));
+
+        if (resend)
+                icp_check_resend(xics, icp);
+
+        return 0;
+}
+
+static int xics_get_source(struct kvmppc_xics *xics, long irq, u64 addr)
+{
+        int ret;
+        struct kvmppc_ics *ics;
+        struct ics_irq_state *irqp;
+        u64 __user *ubufp = (u64 __user *) addr;
+        u16 idx;
+        u64 val, prio;
+
+        ics = kvmppc_xics_find_ics(xics, irq, &idx);
+        if (!ics)
+                return -ENOENT;
+
+        irqp = &ics->irq_state[idx];
+        mutex_lock(&ics->lock);
+        ret = -ENOENT;
+        if (irqp->exists) {
+                val = irqp->server;
+                prio = irqp->priority;
+                if (prio == MASKED) {
+                        val |= KVM_XICS_MASKED;
+                        prio = irqp->saved_priority;
+                }
+                val |= prio << KVM_XICS_PRIORITY_SHIFT;
+                if (irqp->asserted)
+                        val |= KVM_XICS_LEVEL_SENSITIVE | KVM_XICS_PENDING;
+                else if (irqp->masked_pending || irqp->resend)
+                        val |= KVM_XICS_PENDING;
+                ret = 0;
+        }
+        mutex_unlock(&ics->lock);
+
+        if (!ret && put_user(val, ubufp))
+                ret = -EFAULT;
+
+        return ret;
+}
+
+static int xics_set_source(struct kvmppc_xics *xics, long irq, u64 addr)
+{
+        struct kvmppc_ics *ics;
+        struct ics_irq_state *irqp;
+        u64 __user *ubufp = (u64 __user *) addr;
+        u16 idx;
+        u64 val;
+        u8 prio;
+        u32 server;
+
+        if (irq < KVMPPC_XICS_FIRST_IRQ || irq >= KVMPPC_XICS_NR_IRQS)
+                return -ENOENT;
+
+        ics = kvmppc_xics_find_ics(xics, irq, &idx);
+        if (!ics) {
+                ics = kvmppc_xics_create_ics(xics->kvm, xics, irq);
+                if (!ics)
+                        return -ENOMEM;
+        }
+        irqp = &ics->irq_state[idx];
+        if (get_user(val, ubufp))
+                return -EFAULT;
+
+        server = val & KVM_XICS_DESTINATION_MASK;
+        prio = val >> KVM_XICS_PRIORITY_SHIFT;
+        if (prio != MASKED &&
+            kvmppc_xics_find_server(xics->kvm, server) == NULL)
+                return -EINVAL;
+
+        mutex_lock(&ics->lock);
+        irqp->server = server;
+        irqp->saved_priority = prio;
+        if (val & KVM_XICS_MASKED)
+                prio = MASKED;
+        irqp->priority = prio;
+        irqp->resend = 0;
+        irqp->masked_pending = 0;
+        irqp->asserted = 0;
+        if ((val & KVM_XICS_PENDING) && (val & KVM_XICS_LEVEL_SENSITIVE))
+                irqp->asserted = 1;
+        irqp->exists = 1;
+        mutex_unlock(&ics->lock);
+
+        if (val & KVM_XICS_PENDING)
+                icp_deliver_irq(xics, NULL, irqp->number);
+
+        return 0;
+}
+
+int kvm_set_irq(struct kvm *kvm, int irq_source_id, u32 irq, int level,
+                bool line_status)
+{
+        struct kvmppc_xics *xics = kvm->arch.xics;
+
+        return ics_deliver_irq(xics, irq, level, line_status);
+}
+
+static int xics_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
+{
+        struct kvmppc_xics *xics = dev->private;
+
+        switch (attr->group) {
+        case KVM_DEV_XICS_GRP_SOURCES:
+                return xics_set_source(xics, attr->attr, attr->addr);
+        }
+        return -ENXIO;
+}
+
+static int xics_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
+{
+        struct kvmppc_xics *xics = dev->private;
+
+        switch (attr->group) {
+        case KVM_DEV_XICS_GRP_SOURCES:
+                return xics_get_source(xics, attr->attr, attr->addr);
+        }
+        return -ENXIO;
+}
+
+static int xics_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
+{
+        switch (attr->group) {
+        case KVM_DEV_XICS_GRP_SOURCES:
+                if (attr->attr >= KVMPPC_XICS_FIRST_IRQ &&
+                    attr->attr < KVMPPC_XICS_NR_IRQS)
+                        return 0;
+                break;
+        }
+        return -ENXIO;
+}
+
+static void kvmppc_xics_free(struct kvm_device *dev)
+{
+        struct kvmppc_xics *xics = dev->private;
+        int i;
+        struct kvm *kvm = xics->kvm;
+
+        debugfs_remove(xics->dentry);
+
+        if (kvm)
+                kvm->arch.xics = NULL;
+
+        for (i = 0; i <= xics->max_icsid; i++)
+                kfree(xics->ics[i]);
+        kfree(xics);
+        kfree(dev);
+}
+
+static int kvmppc_xics_create(struct kvm_device *dev, u32 type)
+{
+        struct kvmppc_xics *xics;
+        struct kvm *kvm = dev->kvm;
+        int ret = 0;
+
+        xics = kzalloc(sizeof(*xics), GFP_KERNEL);
+        if (!xics)
+                return -ENOMEM;
+
+        dev->private = xics;
+        xics->dev = dev;
+        xics->kvm = kvm;
+
+        /* Already there ? */
+        mutex_lock(&kvm->lock);
+        if (kvm->arch.xics)
+                ret = -EEXIST;
+        else
+                kvm->arch.xics = xics;
+        mutex_unlock(&kvm->lock);
+
+        if (ret)
+                return ret;
+
+        xics_debugfs_init(xics);
+
+#ifdef CONFIG_KVM_BOOK3S_64_HV
+        if (cpu_has_feature(CPU_FTR_ARCH_206)) {
+                /* Enable real mode support */
+                xics->real_mode = ENABLE_REALMODE;
+                xics->real_mode_dbg = DEBUG_REALMODE;
+        }
+#endif /* CONFIG_KVM_BOOK3S_64_HV */
+
+        return 0;
+}
+
+struct kvm_device_ops kvm_xics_ops = {
+        .name = "kvm-xics",
+        .create = kvmppc_xics_create,
+        .destroy = kvmppc_xics_free,
+        .set_attr = xics_set_attr,
+        .get_attr = xics_get_attr,
+        .has_attr = xics_has_attr,
+};
+
+int kvmppc_xics_connect_vcpu(struct kvm_device *dev, struct kvm_vcpu *vcpu,
+                             u32 xcpu)
+{
+        struct kvmppc_xics *xics = dev->private;
+        int r = -EBUSY;
+
+        if (dev->ops != &kvm_xics_ops)
+                return -EPERM;
+        if (xics->kvm != vcpu->kvm)
+                return -EPERM;
+        if (vcpu->arch.irq_type)
+                return -EBUSY;
+
+        r = kvmppc_xics_create_icp(vcpu, xcpu);
+        if (!r)
+                vcpu->arch.irq_type = KVMPPC_IRQ_XICS;
+
+        return r;
+}
+
+void kvmppc_xics_free_icp(struct kvm_vcpu *vcpu)
+{
+        if (!vcpu->arch.icp)
+                return;
+        kfree(vcpu->arch.icp);
+        vcpu->arch.icp = NULL;
+        vcpu->arch.irq_type = KVMPPC_IRQ_DEFAULT;
+}
diff --git a/arch/powerpc/kvm/book3s_xics.h b/arch/powerpc/kvm/book3s_xics.h
new file mode 100644
index 000000000000..dd9326c5c19b
--- /dev/null
+++ b/arch/powerpc/kvm/book3s_xics.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2012 Michael Ellerman, IBM Corporation.
+ * Copyright 2012 Benjamin Herrenschmidt, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _KVM_PPC_BOOK3S_XICS_H
+#define _KVM_PPC_BOOK3S_XICS_H
+
+/*
+ * We use a two-level tree to store interrupt source information.
+ * There are up to 1024 ICS nodes, each of which can represent
+ * 1024 sources.
+ */
+#define KVMPPC_XICS_MAX_ICS_ID  1023
+#define KVMPPC_XICS_ICS_SHIFT   10
+#define KVMPPC_XICS_IRQ_PER_ICS (1 << KVMPPC_XICS_ICS_SHIFT)
+#define KVMPPC_XICS_SRC_MASK    (KVMPPC_XICS_IRQ_PER_ICS - 1)
+
+/*
+ * Interrupt source numbers below this are reserved, for example
+ * 0 is "no interrupt", and 2 is used for IPIs.
+ */
+#define KVMPPC_XICS_FIRST_IRQ   16
+#define KVMPPC_XICS_NR_IRQS     ((KVMPPC_XICS_MAX_ICS_ID + 1) * \
+                                 KVMPPC_XICS_IRQ_PER_ICS)
+
+/* Priority value to use for disabling an interrupt */
+#define MASKED  0xff
+
+/* State for one irq source */
+struct ics_irq_state {
+        u32 number;
+        u32 server;
+        u8  priority;
+        u8  saved_priority;
+        u8  resend;
+        u8  masked_pending;
+        u8  asserted; /* Only for LSI */
+        u8  exists;
+};
+
+/* Atomic ICP state, updated with a single compare & swap */
+union kvmppc_icp_state {
+        unsigned long raw;
+        struct {
+                u8 out_ee:1;
+                u8 need_resend:1;
+                u8 cppr;
+                u8 mfrr;
+                u8 pending_pri;
+                u32 xisr;
+        };
+};
+
+/* One bit per ICS */
+#define ICP_RESEND_MAP_SIZE     (KVMPPC_XICS_MAX_ICS_ID / BITS_PER_LONG + 1)
+
+struct kvmppc_icp {
+        struct kvm_vcpu *vcpu;
+        unsigned long server_num;
+        union kvmppc_icp_state state;
+        unsigned long resend_map[ICP_RESEND_MAP_SIZE];
+
+        /* Real mode might find something too hard, here's the action
+         * it might request from virtual mode
+         */
+#define XICS_RM_KICK_VCPU       0x1
+#define XICS_RM_CHECK_RESEND    0x2
+#define XICS_RM_REJECT          0x4
+        u32 rm_action;
+        struct kvm_vcpu *rm_kick_target;
+        u32  rm_reject;
+
+        /* Debug stuff for real mode */
+        union kvmppc_icp_state rm_dbgstate;
+        struct kvm_vcpu *rm_dbgtgt;
+};
+
+struct kvmppc_ics {
+        struct mutex lock;
+        u16 icsid;
+        struct ics_irq_state irq_state[KVMPPC_XICS_IRQ_PER_ICS];
+};
+
+struct kvmppc_xics {
+        struct kvm *kvm;
+        struct kvm_device *dev;
+        struct dentry *dentry;
+        u32 max_icsid;
+        bool real_mode;
+        bool real_mode_dbg;
+        struct kvmppc_ics *ics[KVMPPC_XICS_MAX_ICS_ID + 1];
+};
+
+static inline struct kvmppc_icp *kvmppc_xics_find_server(struct kvm *kvm,
+                                                         u32 nr)
+{
+        struct kvm_vcpu *vcpu = NULL;
+        int i;
+
+        kvm_for_each_vcpu(i, vcpu, kvm) {
+                if (vcpu->arch.icp && nr == vcpu->arch.icp->server_num)
+                        return vcpu->arch.icp;
+        }
+        return NULL;
+}
+
+static inline struct kvmppc_ics *kvmppc_xics_find_ics(struct kvmppc_xics *xics,
+                                                      u32 irq, u16 *source)
+{
+        u32 icsid = irq >> KVMPPC_XICS_ICS_SHIFT;
+        u16 src = irq & KVMPPC_XICS_SRC_MASK;
+        struct kvmppc_ics *ics;
+
+        if (source)
+                *source = src;
+        if (icsid > KVMPPC_XICS_MAX_ICS_ID)
+                return NULL;
+        ics = xics->ics[icsid];
+        if (!ics)
+                return NULL;
+        return ics;
+}
+
+
+#endif /* _KVM_PPC_BOOK3S_XICS_H */
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index 020923e43134..1020119226db 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -222,8 +222,7 @@ void kvmppc_core_queue_external(struct kvm_vcpu *vcpu,
         kvmppc_booke_queue_irqprio(vcpu, prio);
 }
 
-void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu,
-                                  struct kvm_interrupt *irq)
+void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu)
 {
         clear_bit(BOOKE_IRQPRIO_EXTERNAL, &vcpu->arch.pending_exceptions);
         clear_bit(BOOKE_IRQPRIO_EXTERNAL_LEVEL, &vcpu->arch.pending_exceptions);
@@ -347,7 +346,7 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
                 keep_irq = true;
         }
 
-        if ((priority == BOOKE_IRQPRIO_EXTERNAL) && vcpu->arch.epr_enabled)
+        if ((priority == BOOKE_IRQPRIO_EXTERNAL) && vcpu->arch.epr_flags)
                 update_epr = true;
 
         switch (priority) {
@@ -428,8 +427,14 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
                         set_guest_esr(vcpu, vcpu->arch.queued_esr);
                 if (update_dear == true)
                         set_guest_dear(vcpu, vcpu->arch.queued_dear);
-                if (update_epr == true)
-                        kvm_make_request(KVM_REQ_EPR_EXIT, vcpu);
+                if (update_epr == true) {
+                        if (vcpu->arch.epr_flags & KVMPPC_EPR_USER)
+                                kvm_make_request(KVM_REQ_EPR_EXIT, vcpu);
+                        else if (vcpu->arch.epr_flags & KVMPPC_EPR_KERNEL) {
+                                BUG_ON(vcpu->arch.irq_type != KVMPPC_IRQ_MPIC);
+                                kvmppc_mpic_set_epr(vcpu);
+                        }
+                }
 
                 new_msr &= msr_mask;
 #if defined(CONFIG_64BIT)
@@ -746,6 +751,9 @@ static int emulation_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
                 kvmppc_core_queue_program(vcpu, ESR_PIL);
                 return RESUME_HOST;
 
+        case EMULATE_EXIT_USER:
+                return RESUME_HOST;
+
         default:
                 BUG();
         }
@@ -1148,6 +1156,18 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
         return r;
 }
 
+static void kvmppc_set_tsr(struct kvm_vcpu *vcpu, u32 new_tsr)
+{
+        u32 old_tsr = vcpu->arch.tsr;
+
+        vcpu->arch.tsr = new_tsr;
+
+        if ((old_tsr ^ vcpu->arch.tsr) & (TSR_ENW | TSR_WIS))
+                arm_next_watchdog(vcpu);
+
+        update_timer_ints(vcpu);
+}
+
 /* Initial guest state: 16MB mapping 0 -> 0, PC = 0, MSR = 0, R1 = 16MB */
 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
 {
@@ -1287,16 +1307,8 @@ static int set_sregs_base(struct kvm_vcpu *vcpu,
                 kvmppc_emulate_dec(vcpu);
         }
 
-        if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_TSR) {
-                u32 old_tsr = vcpu->arch.tsr;
-
-                vcpu->arch.tsr = sregs->u.e.tsr;
-
-                if ((old_tsr ^ vcpu->arch.tsr) & (TSR_ENW | TSR_WIS))
-                        arm_next_watchdog(vcpu);
-
-                update_timer_ints(vcpu);
-        }
+        if (sregs->u.e.update_special & KVM_SREGS_E_UPDATE_TSR)
+                kvmppc_set_tsr(vcpu, sregs->u.e.tsr);
 
         return 0;
 }
@@ -1409,84 +1421,134 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
 
 int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
 {
-        int r = -EINVAL;
+        int r = 0;
+        union kvmppc_one_reg val;
+        int size;
+        long int i;
+
+        size = one_reg_size(reg->id);
+        if (size > sizeof(val))
+                return -EINVAL;
 
         switch (reg->id) {
         case KVM_REG_PPC_IAC1:
         case KVM_REG_PPC_IAC2:
         case KVM_REG_PPC_IAC3:
-        case KVM_REG_PPC_IAC4: {
-                int iac = reg->id - KVM_REG_PPC_IAC1;
-                r = copy_to_user((u64 __user *)(long)reg->addr,
-                                 &vcpu->arch.dbg_reg.iac[iac], sizeof(u64));
+        case KVM_REG_PPC_IAC4:
+                i = reg->id - KVM_REG_PPC_IAC1;
+                val = get_reg_val(reg->id, vcpu->arch.dbg_reg.iac[i]);
                 break;
-        }
         case KVM_REG_PPC_DAC1:
-        case KVM_REG_PPC_DAC2: {
-                int dac = reg->id - KVM_REG_PPC_DAC1;
-                r = copy_to_user((u64 __user *)(long)reg->addr,
-                                 &vcpu->arch.dbg_reg.dac[dac], sizeof(u64));
+        case KVM_REG_PPC_DAC2:
+                i = reg->id - KVM_REG_PPC_DAC1;
+                val = get_reg_val(reg->id, vcpu->arch.dbg_reg.dac[i]);
                 break;
-        }
         case KVM_REG_PPC_EPR: {
                 u32 epr = get_guest_epr(vcpu);
-                r = put_user(epr, (u32 __user *)(long)reg->addr);
+                val = get_reg_val(reg->id, epr);
                 break;
         }
 #if defined(CONFIG_64BIT)
         case KVM_REG_PPC_EPCR:
-                r = put_user(vcpu->arch.epcr, (u32 __user *)(long)reg->addr);
+                val = get_reg_val(reg->id, vcpu->arch.epcr);
                 break;
 #endif
+        case KVM_REG_PPC_TCR:
+                val = get_reg_val(reg->id, vcpu->arch.tcr);
+                break;
+        case KVM_REG_PPC_TSR:
+                val = get_reg_val(reg->id, vcpu->arch.tsr);
+                break;
+        case KVM_REG_PPC_DEBUG_INST:
+                val = get_reg_val(reg->id, KVMPPC_INST_EHPRIV);
+                break;
         default:
+                r = kvmppc_get_one_reg(vcpu, reg->id, &val);
                 break;
         }
+
+        if (r)
+                return r;
+
+        if (copy_to_user((char __user *)(unsigned long)reg->addr, &val, size))
+                r = -EFAULT;
+
         return r;
 }
 
 int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, struct kvm_one_reg *reg)
 {
-        int r = -EINVAL;
+        int r = 0;
+        union kvmppc_one_reg val;
+        int size;
+        long int i;
+
+        size = one_reg_size(reg->id);
+        if (size > sizeof(val))
+                return -EINVAL;
+
+        if (copy_from_user(&val, (char __user *)(unsigned long)reg->addr, size))
+                return -EFAULT;
 
         switch (reg->id) {
         case KVM_REG_PPC_IAC1:
         case KVM_REG_PPC_IAC2:
         case KVM_REG_PPC_IAC3:
-        case KVM_REG_PPC_IAC4: {
-                int iac = reg->id - KVM_REG_PPC_IAC1;
-                r = copy_from_user(&vcpu->arch.dbg_reg.iac[iac],
-                             (u64 __user *)(long)reg->addr, sizeof(u64));
+        case KVM_REG_PPC_IAC4:
+                i = reg->id - KVM_REG_PPC_IAC1;
+                vcpu->arch.dbg_reg.iac[i] = set_reg_val(reg->id, val);
                 break;
-        }
         case KVM_REG_PPC_DAC1:
-        case KVM_REG_PPC_DAC2: {
-                int dac = reg->id - KVM_REG_PPC_DAC1;
-                r = copy_from_user(&vcpu->arch.dbg_reg.dac[dac],
-                             (u64 __user *)(long)reg->addr, sizeof(u64));
+        case KVM_REG_PPC_DAC2:
+                i = reg->id - KVM_REG_PPC_DAC1;
+                vcpu->arch.dbg_reg.dac[i] = set_reg_val(reg->id, val);
                 break;
-        }
         case KVM_REG_PPC_EPR: {
-                u32 new_epr;
-                r = get_user(new_epr, (u32 __user *)(long)reg->addr);
-                if (!r)
-                        kvmppc_set_epr(vcpu, new_epr);
+                u32 new_epr = set_reg_val(reg->id, val);
+                kvmppc_set_epr(vcpu, new_epr);
                 break;
         }
 #if defined(CONFIG_64BIT)
         case KVM_REG_PPC_EPCR: {
-                u32 new_epcr;
-                r = get_user(new_epcr, (u32 __user *)(long)reg->addr);
-                if (r == 0)
-                        kvmppc_set_epcr(vcpu, new_epcr);
+                u32 new_epcr = set_reg_val(reg->id, val);
+                kvmppc_set_epcr(vcpu, new_epcr);
                 break;
         }
 #endif
+        case KVM_REG_PPC_OR_TSR: {
+                u32 tsr_bits = set_reg_val(reg->id, val);
+                kvmppc_set_tsr_bits(vcpu, tsr_bits);
+                break;
+        }
+        case KVM_REG_PPC_CLEAR_TSR: {
+                u32 tsr_bits = set_reg_val(reg->id, val);
+                kvmppc_clr_tsr_bits(vcpu, tsr_bits);
+                break;
+        }
+        case KVM_REG_PPC_TSR: {
+                u32 tsr = set_reg_val(reg->id, val);
+                kvmppc_set_tsr(vcpu, tsr);
+                break;
+        }
+        case KVM_REG_PPC_TCR: {
+                u32 tcr = set_reg_val(reg->id, val);
+                kvmppc_set_tcr(vcpu, tcr);
+                break;
+        }
         default:
+                r = kvmppc_set_one_reg(vcpu, reg->id, &val);
                 break;
         }
+
         return r;
 }
 
+int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
+                                         struct kvm_guest_debug *dbg)
+{
+        return -EINVAL;
+}
+
 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
 {
         return -ENOTSUPP;
@@ -1531,7 +1593,7 @@ int kvmppc_core_prepare_memory_region(struct kvm *kvm,
 
 void kvmppc_core_commit_memory_region(struct kvm *kvm,
                                 struct kvm_userspace_memory_region *mem,
-                                struct kvm_memory_slot old)
+                                const struct kvm_memory_slot *old)
 {
 }
 
diff --git a/arch/powerpc/kvm/booke_interrupts.S b/arch/powerpc/kvm/booke_interrupts.S
index f4bb55c96517..2c6deb5ef2fe 100644
--- a/arch/powerpc/kvm/booke_interrupts.S
+++ b/arch/powerpc/kvm/booke_interrupts.S
@@ -54,8 +54,7 @@
                        (1<<BOOKE_INTERRUPT_DTLB_MISS) | \
                        (1<<BOOKE_INTERRUPT_ALIGNMENT))
 
-.macro KVM_HANDLER ivor_nr scratch srr0
-_GLOBAL(kvmppc_handler_\ivor_nr)
+.macro __KVM_HANDLER ivor_nr scratch srr0
         /* Get pointer to vcpu and record exit number. */
         mtspr   \scratch , r4
         mfspr   r4, SPRN_SPRG_THREAD
@@ -76,6 +75,43 @@ _GLOBAL(kvmppc_handler_\ivor_nr)
         bctr
 .endm
 
+.macro KVM_HANDLER ivor_nr scratch srr0
+_GLOBAL(kvmppc_handler_\ivor_nr)
+        __KVM_HANDLER \ivor_nr \scratch \srr0
+.endm
+
+.macro KVM_DBG_HANDLER ivor_nr scratch srr0
+_GLOBAL(kvmppc_handler_\ivor_nr)
+        mtspr   \scratch, r4
+        mfspr   r4, SPRN_SPRG_THREAD
+        lwz     r4, THREAD_KVM_VCPU(r4)
+        stw     r3, VCPU_CRIT_SAVE(r4)
+        mfcr    r3
+        mfspr   r4, SPRN_CSRR1
+        andi.   r4, r4, MSR_PR
+        bne     1f
+        /* debug interrupt happened in enter/exit path */
+        mfspr   r4, SPRN_CSRR1
+        rlwinm  r4, r4, 0, ~MSR_DE
+        mtspr   SPRN_CSRR1, r4
+        lis     r4, 0xffff
+        ori     r4, r4, 0xffff
+        mtspr   SPRN_DBSR, r4
+        mfspr   r4, SPRN_SPRG_THREAD
+        lwz     r4, THREAD_KVM_VCPU(r4)
+        mtcr    r3
+        lwz     r3, VCPU_CRIT_SAVE(r4)
+        mfspr   r4, \scratch
+        rfci
+1:      /* debug interrupt happened in guest */
+        mtcr    r3
+        mfspr   r4, SPRN_SPRG_THREAD
+        lwz     r4, THREAD_KVM_VCPU(r4)
+        lwz     r3, VCPU_CRIT_SAVE(r4)
+        mfspr   r4, \scratch
+        __KVM_HANDLER \ivor_nr \scratch \srr0
+.endm
+
 .macro KVM_HANDLER_ADDR ivor_nr
         .long   kvmppc_handler_\ivor_nr
 .endm
@@ -100,7 +136,7 @@ KVM_HANDLER BOOKE_INTERRUPT_FIT SPRN_SPRG_RSCRATCH0 SPRN_SRR0
 KVM_HANDLER BOOKE_INTERRUPT_WATCHDOG SPRN_SPRG_RSCRATCH_CRIT SPRN_CSRR0
 KVM_HANDLER BOOKE_INTERRUPT_DTLB_MISS SPRN_SPRG_RSCRATCH0 SPRN_SRR0
 KVM_HANDLER BOOKE_INTERRUPT_ITLB_MISS SPRN_SPRG_RSCRATCH0 SPRN_SRR0
-KVM_HANDLER BOOKE_INTERRUPT_DEBUG SPRN_SPRG_RSCRATCH_CRIT SPRN_CSRR0
+KVM_DBG_HANDLER BOOKE_INTERRUPT_DEBUG SPRN_SPRG_RSCRATCH_CRIT SPRN_CSRR0
 KVM_HANDLER BOOKE_INTERRUPT_SPE_UNAVAIL SPRN_SPRG_RSCRATCH0 SPRN_SRR0
 KVM_HANDLER BOOKE_INTERRUPT_SPE_FP_DATA SPRN_SPRG_RSCRATCH0 SPRN_SRR0
 KVM_HANDLER BOOKE_INTERRUPT_SPE_FP_ROUND SPRN_SPRG_RSCRATCH0 SPRN_SRR0
diff --git a/arch/powerpc/kvm/e500.c b/arch/powerpc/kvm/e500.c
index 6dd4de7802bf..ce6b73c29612 100644
--- a/arch/powerpc/kvm/e500.c
+++ b/arch/powerpc/kvm/e500.c
@@ -425,6 +425,20 @@ int kvmppc_core_set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
         return kvmppc_set_sregs_ivor(vcpu, sregs);
 }
 
+int kvmppc_get_one_reg(struct kvm_vcpu *vcpu, u64 id,
+                        union kvmppc_one_reg *val)
+{
+        int r = kvmppc_get_one_reg_e500_tlb(vcpu, id, val);
+        return r;
+}
+
+int kvmppc_set_one_reg(struct kvm_vcpu *vcpu, u64 id,
+                       union kvmppc_one_reg *val)
+{
+        int r = kvmppc_get_one_reg_e500_tlb(vcpu, id, val);
+        return r;
+}
+
 struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id)
 {
         struct kvmppc_vcpu_e500 *vcpu_e500;
diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h
index 33db48a8ce24..c2e5e98453a6 100644
--- a/arch/powerpc/kvm/e500.h
+++ b/arch/powerpc/kvm/e500.h
@@ -23,6 +23,10 @@
 #include <asm/mmu-book3e.h>
 #include <asm/tlb.h>
 
+enum vcpu_ftr {
+        VCPU_FTR_MMU_V2
+};
+
 #define E500_PID_NUM   3
 #define E500_TLB_NUM   2
 
@@ -131,6 +135,10 @@ void kvmppc_e500_tlb_uninit(struct kvmppc_vcpu_e500 *vcpu_e500);
 void kvmppc_get_sregs_e500_tlb(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs);
 int kvmppc_set_sregs_e500_tlb(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs);
 
+int kvmppc_get_one_reg_e500_tlb(struct kvm_vcpu *vcpu, u64 id,
+                                union kvmppc_one_reg *val);
+int kvmppc_set_one_reg_e500_tlb(struct kvm_vcpu *vcpu, u64 id,
+                               union kvmppc_one_reg *val);
 
 #ifdef CONFIG_KVM_E500V2
 unsigned int kvmppc_e500_get_sid(struct kvmppc_vcpu_e500 *vcpu_e500,
@@ -295,4 +303,18 @@ static inline unsigned int get_tlbmiss_tid(struct kvm_vcpu *vcpu)
 #define get_tlb_sts(gtlbe)              (MAS1_TS)
 #endif /* !BOOKE_HV */
 
+static inline bool has_feature(const struct kvm_vcpu *vcpu,
+                               enum vcpu_ftr ftr)
+{
+        bool has_ftr;
+        switch (ftr) {
+        case VCPU_FTR_MMU_V2:
+                has_ftr = ((vcpu->arch.mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2);
+                break;
+        default:
+                return false;
+        }
+        return has_ftr;
+}
+
 #endif /* KVM_E500_H */
diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c
index e78f353a836a..b10a01243abd 100644
--- a/arch/powerpc/kvm/e500_emulate.c
+++ b/arch/powerpc/kvm/e500_emulate.c
@@ -284,6 +284,16 @@ int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
         case SPRN_TLB1CFG:
                 *spr_val = vcpu->arch.tlbcfg[1];
                 break;
+        case SPRN_TLB0PS:
+                if (!has_feature(vcpu, VCPU_FTR_MMU_V2))
+                        return EMULATE_FAIL;
+                *spr_val = vcpu->arch.tlbps[0];
+                break;
+        case SPRN_TLB1PS:
+                if (!has_feature(vcpu, VCPU_FTR_MMU_V2))
+                        return EMULATE_FAIL;
+                *spr_val = vcpu->arch.tlbps[1];
+                break;
         case SPRN_L1CSR0:
                 *spr_val = vcpu_e500->l1csr0;
                 break;
@@ -307,6 +317,15 @@ int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
         case SPRN_MMUCFG:
                 *spr_val = vcpu->arch.mmucfg;
                 break;
+        case SPRN_EPTCFG:
+                if (!has_feature(vcpu, VCPU_FTR_MMU_V2))
+                        return EMULATE_FAIL;
+                /*
+                 * Legacy Linux guests access EPTCFG register even if the E.PT
+                 * category is disabled in the VM. Give them a chance to live.
+                 */
+                *spr_val = vcpu->arch.eptcfg;
+                break;
 
         /* extra exceptions */
         case SPRN_IVOR32:
diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc/kvm/e500_mmu.c
index 5c4475983f78..c41a5a96b558 100644
--- a/arch/powerpc/kvm/e500_mmu.c
+++ b/arch/powerpc/kvm/e500_mmu.c
@@ -596,6 +596,140 @@ int kvmppc_set_sregs_e500_tlb(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
         return 0;
 }
 
+int kvmppc_get_one_reg_e500_tlb(struct kvm_vcpu *vcpu, u64 id,
+                                union kvmppc_one_reg *val)
+{
+        int r = 0;
+        long int i;
+
+        switch (id) {
+        case KVM_REG_PPC_MAS0:
+                *val = get_reg_val(id, vcpu->arch.shared->mas0);
+                break;
+        case KVM_REG_PPC_MAS1:
+                *val = get_reg_val(id, vcpu->arch.shared->mas1);
+                break;
+        case KVM_REG_PPC_MAS2:
+                *val = get_reg_val(id, vcpu->arch.shared->mas2);
+                break;
+        case KVM_REG_PPC_MAS7_3:
+                *val = get_reg_val(id, vcpu->arch.shared->mas7_3);
+                break;
+        case KVM_REG_PPC_MAS4:
+                *val = get_reg_val(id, vcpu->arch.shared->mas4);
+                break;
+        case KVM_REG_PPC_MAS6:
+                *val = get_reg_val(id, vcpu->arch.shared->mas6);
+                break;
+        case KVM_REG_PPC_MMUCFG:
+                *val = get_reg_val(id, vcpu->arch.mmucfg);
+                break;
+        case KVM_REG_PPC_EPTCFG:
+                *val = get_reg_val(id, vcpu->arch.eptcfg);
+                break;
+        case KVM_REG_PPC_TLB0CFG:
+        case KVM_REG_PPC_TLB1CFG:
+        case KVM_REG_PPC_TLB2CFG:
+        case KVM_REG_PPC_TLB3CFG:
+                i = id - KVM_REG_PPC_TLB0CFG;
+                *val = get_reg_val(id, vcpu->arch.tlbcfg[i]);
+                break;
+        case KVM_REG_PPC_TLB0PS:
+        case KVM_REG_PPC_TLB1PS:
+        case KVM_REG_PPC_TLB2PS:
+        case KVM_REG_PPC_TLB3PS:
+                i = id - KVM_REG_PPC_TLB0PS;
+                *val = get_reg_val(id, vcpu->arch.tlbps[i]);
+                break;
+        default:
+                r = -EINVAL;
+                break;
+        }
+
+        return r;
+}
+
+int kvmppc_set_one_reg_e500_tlb(struct kvm_vcpu *vcpu, u64 id,
+                               union kvmppc_one_reg *val)
+{
+        int r = 0;
+        long int i;
+
+        switch (id) {
+        case KVM_REG_PPC_MAS0:
+                vcpu->arch.shared->mas0 = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_MAS1:
+                vcpu->arch.shared->mas1 = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_MAS2:
+                vcpu->arch.shared->mas2 = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_MAS7_3:
+                vcpu->arch.shared->mas7_3 = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_MAS4:
+                vcpu->arch.shared->mas4 = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_MAS6:
+                vcpu->arch.shared->mas6 = set_reg_val(id, *val);
+                break;
+        /* Only allow MMU registers to be set to the config supported by KVM */
+        case KVM_REG_PPC_MMUCFG: {
+                u32 reg = set_reg_val(id, *val);
+                if (reg != vcpu->arch.mmucfg)
+                        r = -EINVAL;
+                break;
+        }
+        case KVM_REG_PPC_EPTCFG: {
+                u32 reg = set_reg_val(id, *val);
+                if (reg != vcpu->arch.eptcfg)
+                        r = -EINVAL;
+                break;
+        }
+        case KVM_REG_PPC_TLB0CFG:
+        case KVM_REG_PPC_TLB1CFG:
+        case KVM_REG_PPC_TLB2CFG:
+        case KVM_REG_PPC_TLB3CFG: {
+                /* MMU geometry (N_ENTRY/ASSOC) can be set only using SW_TLB */
+                u32 reg = set_reg_val(id, *val);
+                i = id - KVM_REG_PPC_TLB0CFG;
+                if (reg != vcpu->arch.tlbcfg[i])
+                        r = -EINVAL;
+                break;
+        }
+        case KVM_REG_PPC_TLB0PS:
+        case KVM_REG_PPC_TLB1PS:
+        case KVM_REG_PPC_TLB2PS:
+        case KVM_REG_PPC_TLB3PS: {
+                u32 reg = set_reg_val(id, *val);
+                i = id - KVM_REG_PPC_TLB0PS;
+                if (reg != vcpu->arch.tlbps[i])
+                        r = -EINVAL;
+                break;
+        }
+        default:
+                r = -EINVAL;
+                break;
+        }
+
+        return r;
+}
+
+static int vcpu_mmu_geometry_update(struct kvm_vcpu *vcpu,
+                struct kvm_book3e_206_tlb_params *params)
+{
+        vcpu->arch.tlbcfg[0] &= ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
+        if (params->tlb_sizes[0] <= 2048)
+                vcpu->arch.tlbcfg[0] |= params->tlb_sizes[0];
+        vcpu->arch.tlbcfg[0] |= params->tlb_ways[0] << TLBnCFG_ASSOC_SHIFT;
+
+        vcpu->arch.tlbcfg[1] &= ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
+        vcpu->arch.tlbcfg[1] |= params->tlb_sizes[1];
+        vcpu->arch.tlbcfg[1] |= params->tlb_ways[1] << TLBnCFG_ASSOC_SHIFT;
+        return 0;
+}
+
 int kvm_vcpu_ioctl_config_tlb(struct kvm_vcpu *vcpu,
                               struct kvm_config_tlb *cfg)
 {
@@ -692,16 +826,8 @@ int kvm_vcpu_ioctl_config_tlb(struct kvm_vcpu *vcpu,
         vcpu_e500->gtlb_offset[0] = 0;
         vcpu_e500->gtlb_offset[1] = params.tlb_sizes[0];
 
-        vcpu->arch.mmucfg = mfspr(SPRN_MMUCFG) & ~MMUCFG_LPIDSIZE;
-
-        vcpu->arch.tlbcfg[0] &= ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
-        if (params.tlb_sizes[0] <= 2048)
-                vcpu->arch.tlbcfg[0] |= params.tlb_sizes[0];
-        vcpu->arch.tlbcfg[0] |= params.tlb_ways[0] << TLBnCFG_ASSOC_SHIFT;
-
-        vcpu->arch.tlbcfg[1] &= ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
-        vcpu->arch.tlbcfg[1] |= params.tlb_sizes[1];
-        vcpu->arch.tlbcfg[1] |= params.tlb_ways[1] << TLBnCFG_ASSOC_SHIFT;
+        /* Update vcpu's MMU geometry based on SW_TLB input */
+        vcpu_mmu_geometry_update(vcpu, &params);
 
         vcpu_e500->shared_tlb_pages = pages;
         vcpu_e500->num_shared_tlb_pages = num_pages;
@@ -737,6 +863,39 @@ int kvm_vcpu_ioctl_dirty_tlb(struct kvm_vcpu *vcpu,
         return 0;
 }
 
+/* Vcpu's MMU default configuration */
+static int vcpu_mmu_init(struct kvm_vcpu *vcpu,
+                       struct kvmppc_e500_tlb_params *params)
+{
+        /* Initialize RASIZE, PIDSIZE, NTLBS and MAVN fields with host values*/
+        vcpu->arch.mmucfg = mfspr(SPRN_MMUCFG) & ~MMUCFG_LPIDSIZE;
+
+        /* Initialize TLBnCFG fields with host values and SW_TLB geometry*/
+        vcpu->arch.tlbcfg[0] = mfspr(SPRN_TLB0CFG) &
+                             ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
+        vcpu->arch.tlbcfg[0] |= params[0].entries;
+        vcpu->arch.tlbcfg[0] |= params[0].ways << TLBnCFG_ASSOC_SHIFT;
+
+        vcpu->arch.tlbcfg[1] = mfspr(SPRN_TLB1CFG) &
+                             ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
+        vcpu->arch.tlbcfg[1] |= params[1].entries;
+        vcpu->arch.tlbcfg[1] |= params[1].ways << TLBnCFG_ASSOC_SHIFT;
+
+        if (has_feature(vcpu, VCPU_FTR_MMU_V2)) {
+                vcpu->arch.tlbps[0] = mfspr(SPRN_TLB0PS);
+                vcpu->arch.tlbps[1] = mfspr(SPRN_TLB1PS);
+
+                vcpu->arch.mmucfg &= ~MMUCFG_LRAT;
+
+                /* Guest mmu emulation currently doesn't handle E.PT */
+                vcpu->arch.eptcfg = 0;
+                vcpu->arch.tlbcfg[0] &= ~TLBnCFG_PT;
+                vcpu->arch.tlbcfg[1] &= ~TLBnCFG_IND;
+        }
+
+        return 0;
+}
+
 int kvmppc_e500_tlb_init(struct kvmppc_vcpu_e500 *vcpu_e500)
 {
         struct kvm_vcpu *vcpu = &vcpu_e500->vcpu;
@@ -781,18 +940,7 @@ int kvmppc_e500_tlb_init(struct kvmppc_vcpu_e500 *vcpu_e500)
         if (!vcpu_e500->g2h_tlb1_map)
                 goto err;
 
-        /* Init TLB configuration register */
-        vcpu->arch.tlbcfg[0] = mfspr(SPRN_TLB0CFG) &
-                             ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
-        vcpu->arch.tlbcfg[0] |= vcpu_e500->gtlb_params[0].entries;
-        vcpu->arch.tlbcfg[0] |=
-                vcpu_e500->gtlb_params[0].ways << TLBnCFG_ASSOC_SHIFT;
-
-        vcpu->arch.tlbcfg[1] = mfspr(SPRN_TLB1CFG) &
-                             ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
-        vcpu->arch.tlbcfg[1] |= vcpu_e500->gtlb_params[1].entries;
-        vcpu->arch.tlbcfg[1] |=
-                vcpu_e500->gtlb_params[1].ways << TLBnCFG_ASSOC_SHIFT;
+        vcpu_mmu_init(vcpu, vcpu_e500->gtlb_params);
 
         kvmppc_recalc_tlb1map_range(vcpu_e500);
         return 0;
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index 2f4baa074b2e..753cc99eff2b 100644
--- a/arch/powerpc/kvm/e500mc.c
+++ b/arch/powerpc/kvm/e500mc.c
@@ -177,6 +177,8 @@ int kvmppc_core_check_processor_compat(void)
                 r = 0;
         else if (strcmp(cur_cpu_spec->cpu_name, "e5500") == 0)
                 r = 0;
+        else if (strcmp(cur_cpu_spec->cpu_name, "e6500") == 0)
+                r = 0;
         else
                 r = -ENOTSUPP;
 
@@ -260,6 +262,20 @@ int kvmppc_core_set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
         return kvmppc_set_sregs_ivor(vcpu, sregs);
 }
 
+int kvmppc_get_one_reg(struct kvm_vcpu *vcpu, u64 id,
+                        union kvmppc_one_reg *val)
+{
+        int r = kvmppc_get_one_reg_e500_tlb(vcpu, id, val);
+        return r;
+}
+
+int kvmppc_set_one_reg(struct kvm_vcpu *vcpu, u64 id,
+                       union kvmppc_one_reg *val)
+{
+        int r = kvmppc_set_one_reg_e500_tlb(vcpu, id, val);
+        return r;
+}
+
 struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id)
 {
         struct kvmppc_vcpu_e500 *vcpu_e500;
diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c
index 7a73b6f72a8b..631a2650e4e4 100644
--- a/arch/powerpc/kvm/emulate.c
+++ b/arch/powerpc/kvm/emulate.c
@@ -38,6 +38,7 @@
 
 #define OP_31_XOP_TRAP      4
 #define OP_31_XOP_LWZX      23
+#define OP_31_XOP_DCBST     54
 #define OP_31_XOP_TRAP_64   68
 #define OP_31_XOP_DCBF      86
 #define OP_31_XOP_LBZX      87
@@ -370,6 +371,7 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu)
                         emulated = kvmppc_emulate_mtspr(vcpu, sprn, rs);
                         break;
 
+                case OP_31_XOP_DCBST:
                 case OP_31_XOP_DCBF:
                 case OP_31_XOP_DCBI:
                         /* Do nothing. The guest is performing dcbi because
diff --git a/arch/powerpc/kvm/irq.h b/arch/powerpc/kvm/irq.h
new file mode 100644
index 000000000000..5a9a10b90762
--- /dev/null
+++ b/arch/powerpc/kvm/irq.h
@@ -0,0 +1,20 @@
+#ifndef __IRQ_H
+#define __IRQ_H
+
+#include <linux/kvm_host.h>
+
+static inline int irqchip_in_kernel(struct kvm *kvm)
+{
+        int ret = 0;
+
+#ifdef CONFIG_KVM_MPIC
+        ret = ret || (kvm->arch.mpic != NULL);
+#endif
+#ifdef CONFIG_KVM_XICS
+        ret = ret || (kvm->arch.xics != NULL);
+#endif
+        smp_rmb();
+        return ret;
+}
+
+#endif
diff --git a/arch/powerpc/kvm/mpic.c b/arch/powerpc/kvm/mpic.c
new file mode 100644
index 000000000000..2861ae9eaae6
--- /dev/null
+++ b/arch/powerpc/kvm/mpic.c
@@ -0,0 +1,1853 @@
+/*
+ * OpenPIC emulation
+ *
+ * Copyright (c) 2004 Jocelyn Mayer
+ *               2011 Alexander Graf
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <linux/slab.h>
+#include <linux/mutex.h>
+#include <linux/kvm_host.h>
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/anon_inodes.h>
+#include <asm/uaccess.h>
+#include <asm/mpic.h>
+#include <asm/kvm_para.h>
+#include <asm/kvm_host.h>
+#include <asm/kvm_ppc.h>
+#include "iodev.h"
+
+#define MAX_CPU     32
+#define MAX_SRC     256
+#define MAX_TMR     4
+#define MAX_IPI     4
+#define MAX_MSI     8
+#define MAX_IRQ     (MAX_SRC + MAX_IPI + MAX_TMR)
+#define VID         0x03        /* MPIC version ID */
+
+/* OpenPIC capability flags */
+#define OPENPIC_FLAG_IDR_CRIT     (1 << 0)
+#define OPENPIC_FLAG_ILR          (2 << 0)
+
+/* OpenPIC address map */
+#define OPENPIC_REG_SIZE             0x40000
+#define OPENPIC_GLB_REG_START        0x0
+#define OPENPIC_GLB_REG_SIZE         0x10F0
+#define OPENPIC_TMR_REG_START        0x10F0
+#define OPENPIC_TMR_REG_SIZE         0x220
+#define OPENPIC_MSI_REG_START        0x1600
+#define OPENPIC_MSI_REG_SIZE         0x200
+#define OPENPIC_SUMMARY_REG_START    0x3800
+#define OPENPIC_SUMMARY_REG_SIZE     0x800
+#define OPENPIC_SRC_REG_START        0x10000
+#define OPENPIC_SRC_REG_SIZE         (MAX_SRC * 0x20)
+#define OPENPIC_CPU_REG_START        0x20000
+#define OPENPIC_CPU_REG_SIZE         (0x100 + ((MAX_CPU - 1) * 0x1000))
+
+struct fsl_mpic_info {
+        int max_ext;
+};
+
+static struct fsl_mpic_info fsl_mpic_20 = {
+        .max_ext = 12,
+};
+
+static struct fsl_mpic_info fsl_mpic_42 = {
+        .max_ext = 12,
+};
+
+#define FRR_NIRQ_SHIFT    16
+#define FRR_NCPU_SHIFT     8
+#define FRR_VID_SHIFT      0
+
+#define VID_REVISION_1_2   2
+#define VID_REVISION_1_3   3
+
+#define VIR_GENERIC      0x00000000     /* Generic Vendor ID */
+
+#define GCR_RESET        0x80000000
+#define GCR_MODE_PASS    0x00000000
+#define GCR_MODE_MIXED   0x20000000
+#define GCR_MODE_PROXY   0x60000000
+
+#define TBCR_CI           0x80000000    /* count inhibit */
+#define TCCR_TOG          0x80000000    /* toggles when decrement to zero */
+
+#define IDR_EP_SHIFT      31
+#define IDR_EP_MASK       (1 << IDR_EP_SHIFT)
+#define IDR_CI0_SHIFT     30
+#define IDR_CI1_SHIFT     29
+#define IDR_P1_SHIFT      1
+#define IDR_P0_SHIFT      0
+
+#define ILR_INTTGT_MASK   0x000000ff
+#define ILR_INTTGT_INT    0x00
+#define ILR_INTTGT_CINT   0x01  /* critical */
+#define ILR_INTTGT_MCP    0x02  /* machine check */
+#define NUM_OUTPUTS       3
+
+#define MSIIR_OFFSET       0x140
+#define MSIIR_SRS_SHIFT    29
+#define MSIIR_SRS_MASK     (0x7 << MSIIR_SRS_SHIFT)
+#define MSIIR_IBS_SHIFT    24
+#define MSIIR_IBS_MASK     (0x1f << MSIIR_IBS_SHIFT)
+
+static int get_current_cpu(void)
+{
+#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
+        struct kvm_vcpu *vcpu = current->thread.kvm_vcpu;
+        return vcpu ? vcpu->arch.irq_cpu_id : -1;
+#else
+        /* XXX */
+        return -1;
+#endif
+}
+
+static int openpic_cpu_write_internal(void *opaque, gpa_t addr,
+                                      u32 val, int idx);
+static int openpic_cpu_read_internal(void *opaque, gpa_t addr,
+                                     u32 *ptr, int idx);
+
+enum irq_type {
+        IRQ_TYPE_NORMAL = 0,
+        IRQ_TYPE_FSLINT,        /* FSL internal interrupt -- level only */
+        IRQ_TYPE_FSLSPECIAL,    /* FSL timer/IPI interrupt, edge, no polarity */
+};
+
+struct irq_queue {
+        /* Round up to the nearest 64 IRQs so that the queue length
+         * won't change when moving between 32 and 64 bit hosts.
+         */
+        unsigned long queue[BITS_TO_LONGS((MAX_IRQ + 63) & ~63)];
+        int next;
+        int priority;
+};
+
+struct irq_source {
+        uint32_t ivpr;          /* IRQ vector/priority register */
+        uint32_t idr;           /* IRQ destination register */
+        uint32_t destmask;      /* bitmap of CPU destinations */
+        int last_cpu;
+        int output;             /* IRQ level, e.g. ILR_INTTGT_INT */
+        int pending;            /* TRUE if IRQ is pending */
+        enum irq_type type;
+        bool level:1;           /* level-triggered */
+        bool nomask:1;  /* critical interrupts ignore mask on some FSL MPICs */
+};
+
+#define IVPR_MASK_SHIFT       31
+#define IVPR_MASK_MASK        (1 << IVPR_MASK_SHIFT)
+#define IVPR_ACTIVITY_SHIFT   30
+#define IVPR_ACTIVITY_MASK    (1 << IVPR_ACTIVITY_SHIFT)
+#define IVPR_MODE_SHIFT       29
+#define IVPR_MODE_MASK        (1 << IVPR_MODE_SHIFT)
+#define IVPR_POLARITY_SHIFT   23
+#define IVPR_POLARITY_MASK    (1 << IVPR_POLARITY_SHIFT)
+#define IVPR_SENSE_SHIFT      22
+#define IVPR_SENSE_MASK       (1 << IVPR_SENSE_SHIFT)
+
+#define IVPR_PRIORITY_MASK     (0xF << 16)
+#define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16))
+#define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
+
+/* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */
+#define IDR_EP      0x80000000  /* external pin */
+#define IDR_CI      0x40000000  /* critical interrupt */
+
+struct irq_dest {
+        struct kvm_vcpu *vcpu;
+
+        int32_t ctpr;           /* CPU current task priority */
+        struct irq_queue raised;
+        struct irq_queue servicing;
+
+        /* Count of IRQ sources asserting on non-INT outputs */
+        uint32_t outputs_active[NUM_OUTPUTS];
+};
+
+#define MAX_MMIO_REGIONS 10
+
+struct openpic {
+        struct kvm *kvm;
+        struct kvm_device *dev;
+        struct kvm_io_device mmio;
+        const struct mem_reg *mmio_regions[MAX_MMIO_REGIONS];
+        int num_mmio_regions;
+
+        gpa_t reg_base;
+        spinlock_t lock;
+
+        /* Behavior control */
+        struct fsl_mpic_info *fsl;
+        uint32_t model;
+        uint32_t flags;
+        uint32_t nb_irqs;
+        uint32_t vid;
+        uint32_t vir;           /* Vendor identification register */
+        uint32_t vector_mask;
+        uint32_t tfrr_reset;
+        uint32_t ivpr_reset;
+        uint32_t idr_reset;
+        uint32_t brr1;
+        uint32_t mpic_mode_mask;
+
+        /* Global registers */
+        uint32_t frr;           /* Feature reporting register */
+        uint32_t gcr;           /* Global configuration register  */
+        uint32_t pir;           /* Processor initialization register */
+        uint32_t spve;          /* Spurious vector register */
+        uint32_t tfrr;          /* Timer frequency reporting register */
+        /* Source registers */
+        struct irq_source src[MAX_IRQ];
+        /* Local registers per output pin */
+        struct irq_dest dst[MAX_CPU];
+        uint32_t nb_cpus;
+        /* Timer registers */
+        struct {
+                uint32_t tccr;  /* Global timer current count register */
+                uint32_t tbcr;  /* Global timer base count register */
+        } timers[MAX_TMR];
+        /* Shared MSI registers */
+        struct {
+                uint32_t msir;  /* Shared Message Signaled Interrupt Register */
+        } msi[MAX_MSI];
+        uint32_t max_irq;
+        uint32_t irq_ipi0;
+        uint32_t irq_tim0;
+        uint32_t irq_msi;
+};
+
+
+static void mpic_irq_raise(struct openpic *opp, struct irq_dest *dst,
+                           int output)
+{
+        struct kvm_interrupt irq = {
+                .irq = KVM_INTERRUPT_SET_LEVEL,
+        };
+
+        if (!dst->vcpu) {
+                pr_debug("%s: destination cpu %d does not exist\n",
+                         __func__, (int)(dst - &opp->dst[0]));
+                return;
+        }
+
+        pr_debug("%s: cpu %d output %d\n", __func__, dst->vcpu->arch.irq_cpu_id,
+                output);
+
+        if (output != ILR_INTTGT_INT)   /* TODO */
+                return;
+
+        kvm_vcpu_ioctl_interrupt(dst->vcpu, &irq);
+}
+
+static void mpic_irq_lower(struct openpic *opp, struct irq_dest *dst,
+                           int output)
+{
+        if (!dst->vcpu) {
+                pr_debug("%s: destination cpu %d does not exist\n",
+                         __func__, (int)(dst - &opp->dst[0]));
+                return;
+        }
+
+        pr_debug("%s: cpu %d output %d\n", __func__, dst->vcpu->arch.irq_cpu_id,
+                output);
+
+        if (output != ILR_INTTGT_INT)   /* TODO */
+                return;
+
+        kvmppc_core_dequeue_external(dst->vcpu);
+}
+
+static inline void IRQ_setbit(struct irq_queue *q, int n_IRQ)
+{
+        set_bit(n_IRQ, q->queue);
+}
+
+static inline void IRQ_resetbit(struct irq_queue *q, int n_IRQ)
+{
+        clear_bit(n_IRQ, q->queue);
+}
+
+static inline int IRQ_testbit(struct irq_queue *q, int n_IRQ)
+{
+        return test_bit(n_IRQ, q->queue);
+}
+
+static void IRQ_check(struct openpic *opp, struct irq_queue *q)
+{
+        int irq = -1;
+        int next = -1;
+        int priority = -1;
+
+        for (;;) {
+                irq = find_next_bit(q->queue, opp->max_irq, irq + 1);
+                if (irq == opp->max_irq)
+                        break;
+
+                pr_debug("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n",
+                        irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority);
+
+                if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) {
+                        next = irq;
+                        priority = IVPR_PRIORITY(opp->src[irq].ivpr);
+                }
+        }
+
+        q->next = next;
+        q->priority = priority;
+}
+
+static int IRQ_get_next(struct openpic *opp, struct irq_queue *q)
+{
+        /* XXX: optimize */
+        IRQ_check(opp, q);
+
+        return q->next;
+}
+
+static void IRQ_local_pipe(struct openpic *opp, int n_CPU, int n_IRQ,
+                           bool active, bool was_active)
+{
+        struct irq_dest *dst;
+        struct irq_source *src;
+        int priority;
+
+        dst = &opp->dst[n_CPU];
+        src = &opp->src[n_IRQ];
+
+        pr_debug("%s: IRQ %d active %d was %d\n",
+                __func__, n_IRQ, active, was_active);
+
+        if (src->output != ILR_INTTGT_INT) {
+                pr_debug("%s: output %d irq %d active %d was %d count %d\n",
+                        __func__, src->output, n_IRQ, active, was_active,
+                        dst->outputs_active[src->output]);
+
+                /* On Freescale MPIC, critical interrupts ignore priority,
+                 * IACK, EOI, etc.  Before MPIC v4.1 they also ignore
+                 * masking.
+                 */
+                if (active) {
+                        if (!was_active &&
+                            dst->outputs_active[src->output]++ == 0) {
+                                pr_debug("%s: Raise OpenPIC output %d cpu %d irq %d\n",
+                                        __func__, src->output, n_CPU, n_IRQ);
+                                mpic_irq_raise(opp, dst, src->output);
+                        }
+                } else {
+                        if (was_active &&
+                            --dst->outputs_active[src->output] == 0) {
+                                pr_debug("%s: Lower OpenPIC output %d cpu %d irq %d\n",
+                                        __func__, src->output, n_CPU, n_IRQ);
+                                mpic_irq_lower(opp, dst, src->output);
+                        }
+                }
+
+                return;
+        }
+
+        priority = IVPR_PRIORITY(src->ivpr);
+
+        /* Even if the interrupt doesn't have enough priority,
+         * it is still raised, in case ctpr is lowered later.
+         */
+        if (active)
+                IRQ_setbit(&dst->raised, n_IRQ);
+        else
+                IRQ_resetbit(&dst->raised, n_IRQ);
+
+        IRQ_check(opp, &dst->raised);
+
+        if (active && priority <= dst->ctpr) {
+                pr_debug("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n",
+                        __func__, n_IRQ, priority, dst->ctpr, n_CPU);
+                active = 0;
+        }
+
+        if (active) {
+                if (IRQ_get_next(opp, &dst->servicing) >= 0 &&
+                    priority <= dst->servicing.priority) {
+                        pr_debug("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
+                                __func__, n_IRQ, dst->servicing.next, n_CPU);
+                } else {
+                        pr_debug("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n",
+                                __func__, n_CPU, n_IRQ, dst->raised.next);
+                        mpic_irq_raise(opp, dst, ILR_INTTGT_INT);
+                }
+        } else {
+                IRQ_get_next(opp, &dst->servicing);
+                if (dst->raised.priority > dst->ctpr &&
+                    dst->raised.priority > dst->servicing.priority) {
+                        pr_debug("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n",
+                                __func__, n_IRQ, dst->raised.next,
+                                dst->raised.priority, dst->ctpr,
+                                dst->servicing.priority, n_CPU);
+                        /* IRQ line stays asserted */
+                } else {
+                        pr_debug("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n",
+                                __func__, n_IRQ, dst->ctpr,
+                                dst->servicing.priority, n_CPU);
+                        mpic_irq_lower(opp, dst, ILR_INTTGT_INT);
+                }
+        }
+}
+
+/* update pic state because registers for n_IRQ have changed value */
+static void openpic_update_irq(struct openpic *opp, int n_IRQ)
+{
+        struct irq_source *src;
+        bool active, was_active;
+        int i;
+
+        src = &opp->src[n_IRQ];
+        active = src->pending;
+
+        if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) {
+                /* Interrupt source is disabled */
+                pr_debug("%s: IRQ %d is disabled\n", __func__, n_IRQ);
+                active = false;
+        }
+
+        was_active = !!(src->ivpr & IVPR_ACTIVITY_MASK);
+
+        /*
+         * We don't have a similar check for already-active because
+         * ctpr may have changed and we need to withdraw the interrupt.
+         */
+        if (!active && !was_active) {
+                pr_debug("%s: IRQ %d is already inactive\n", __func__, n_IRQ);
+                return;
+        }
+
+        if (active)
+                src->ivpr |= IVPR_ACTIVITY_MASK;
+        else
+                src->ivpr &= ~IVPR_ACTIVITY_MASK;
+
+        if (src->destmask == 0) {
+                /* No target */
+                pr_debug("%s: IRQ %d has no target\n", __func__, n_IRQ);
+                return;
+        }
+
+        if (src->destmask == (1 << src->last_cpu)) {
+                /* Only one CPU is allowed to receive this IRQ */
+                IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active);
+        } else if (!(src->ivpr & IVPR_MODE_MASK)) {
+                /* Directed delivery mode */
+                for (i = 0; i < opp->nb_cpus; i++) {
+                        if (src->destmask & (1 << i)) {
+                                IRQ_local_pipe(opp, i, n_IRQ, active,
+                                               was_active);
+                        }
+                }
+        } else {
+                /* Distributed delivery mode */
+                for (i = src->last_cpu + 1; i != src->last_cpu; i++) {
+                        if (i == opp->nb_cpus)
+                                i = 0;
+
+                        if (src->destmask & (1 << i)) {
+                                IRQ_local_pipe(opp, i, n_IRQ, active,
+                                               was_active);
+                                src->last_cpu = i;
+                                break;
+                        }
+                }
+        }
+}
+
+static void openpic_set_irq(void *opaque, int n_IRQ, int level)
+{
+        struct openpic *opp = opaque;
+        struct irq_source *src;
+
+        if (n_IRQ >= MAX_IRQ) {
+                WARN_ONCE(1, "%s: IRQ %d out of range\n", __func__, n_IRQ);
+                return;
+        }
+
+        src = &opp->src[n_IRQ];
+        pr_debug("openpic: set irq %d = %d ivpr=0x%08x\n",
+                n_IRQ, level, src->ivpr);
+        if (src->level) {
+                /* level-sensitive irq */
+                src->pending = level;
+                openpic_update_irq(opp, n_IRQ);
+        } else {
+                /* edge-sensitive irq */
+                if (level) {
+                        src->pending = 1;
+                        openpic_update_irq(opp, n_IRQ);
+                }
+
+                if (src->output != ILR_INTTGT_INT) {
+                        /* Edge-triggered interrupts shouldn't be used
+                         * with non-INT delivery, but just in case,
+                         * try to make it do something sane rather than
+                         * cause an interrupt storm.  This is close to
+                         * what you'd probably see happen in real hardware.
+                         */
+                        src->pending = 0;
+                        openpic_update_irq(opp, n_IRQ);
+                }
+        }
+}
+
+static void openpic_reset(struct openpic *opp)
+{
+        int i;
+
+        opp->gcr = GCR_RESET;
+        /* Initialise controller registers */
+        opp->frr = ((opp->nb_irqs - 1) << FRR_NIRQ_SHIFT) |
+            (opp->vid << FRR_VID_SHIFT);
+
+        opp->pir = 0;
+        opp->spve = -1 & opp->vector_mask;
+        opp->tfrr = opp->tfrr_reset;
+        /* Initialise IRQ sources */
+        for (i = 0; i < opp->max_irq; i++) {
+                opp->src[i].ivpr = opp->ivpr_reset;
+                opp->src[i].idr = opp->idr_reset;
+
+                switch (opp->src[i].type) {
+                case IRQ_TYPE_NORMAL:
+                        opp->src[i].level =
+                            !!(opp->ivpr_reset & IVPR_SENSE_MASK);
+                        break;
+
+                case IRQ_TYPE_FSLINT:
+                        opp->src[i].ivpr |= IVPR_POLARITY_MASK;
+                        break;
+
+                case IRQ_TYPE_FSLSPECIAL:
+                        break;
+                }
+        }
+        /* Initialise IRQ destinations */
+        for (i = 0; i < MAX_CPU; i++) {
+                opp->dst[i].ctpr = 15;
+                memset(&opp->dst[i].raised, 0, sizeof(struct irq_queue));
+                opp->dst[i].raised.next = -1;
+                memset(&opp->dst[i].servicing, 0, sizeof(struct irq_queue));
+                opp->dst[i].servicing.next = -1;
+        }
+        /* Initialise timers */
+        for (i = 0; i < MAX_TMR; i++) {
+                opp->timers[i].tccr = 0;
+                opp->timers[i].tbcr = TBCR_CI;
+        }
+        /* Go out of RESET state */
+        opp->gcr = 0;
+}
+
+static inline uint32_t read_IRQreg_idr(struct openpic *opp, int n_IRQ)
+{
+        return opp->src[n_IRQ].idr;
+}
+
+static inline uint32_t read_IRQreg_ilr(struct openpic *opp, int n_IRQ)
+{
+        if (opp->flags & OPENPIC_FLAG_ILR)
+                return opp->src[n_IRQ].output;
+
+        return 0xffffffff;
+}
+
+static inline uint32_t read_IRQreg_ivpr(struct openpic *opp, int n_IRQ)
+{
+        return opp->src[n_IRQ].ivpr;
+}
+
+static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ,
+                                    uint32_t val)
+{
+        struct irq_source *src = &opp->src[n_IRQ];
+        uint32_t normal_mask = (1UL << opp->nb_cpus) - 1;
+        uint32_t crit_mask = 0;
+        uint32_t mask = normal_mask;
+        int crit_shift = IDR_EP_SHIFT - opp->nb_cpus;
+        int i;
+
+        if (opp->flags & OPENPIC_FLAG_IDR_CRIT) {
+                crit_mask = mask << crit_shift;
+                mask |= crit_mask | IDR_EP;
+        }
+
+        src->idr = val & mask;
+        pr_debug("Set IDR %d to 0x%08x\n", n_IRQ, src->idr);
+
+        if (opp->flags & OPENPIC_FLAG_IDR_CRIT) {
+                if (src->idr & crit_mask) {
+                        if (src->idr & normal_mask) {
+                                pr_debug("%s: IRQ configured for multiple output types, using critical\n",
+                                        __func__);
+                        }
+
+                        src->output = ILR_INTTGT_CINT;
+                        src->nomask = true;
+                        src->destmask = 0;
+
+                        for (i = 0; i < opp->nb_cpus; i++) {
+                                int n_ci = IDR_CI0_SHIFT - i;
+
+                                if (src->idr & (1UL << n_ci))
+                                        src->destmask |= 1UL << i;
+                        }
+                } else {
+                        src->output = ILR_INTTGT_INT;
+                        src->nomask = false;
+                        src->destmask = src->idr & normal_mask;
+                }
+        } else {
+                src->destmask = src->idr;
+        }
+}
+
+static inline void write_IRQreg_ilr(struct openpic *opp, int n_IRQ,
+                                    uint32_t val)
+{
+        if (opp->flags & OPENPIC_FLAG_ILR) {
+                struct irq_source *src = &opp->src[n_IRQ];
+
+                src->output = val & ILR_INTTGT_MASK;
+                pr_debug("Set ILR %d to 0x%08x, output %d\n", n_IRQ, src->idr,
+                        src->output);
+
+                /* TODO: on MPIC v4.0 only, set nomask for non-INT */
+        }
+}
+
+static inline void write_IRQreg_ivpr(struct openpic *opp, int n_IRQ,
+                                     uint32_t val)
+{
+        uint32_t mask;
+
+        /* NOTE when implementing newer FSL MPIC models: starting with v4.0,
+         * the polarity bit is read-only on internal interrupts.
+         */
+        mask = IVPR_MASK_MASK | IVPR_PRIORITY_MASK | IVPR_SENSE_MASK |
+            IVPR_POLARITY_MASK | opp->vector_mask;
+
+        /* ACTIVITY bit is read-only */
+        opp->src[n_IRQ].ivpr =
+            (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask);
+
+        /* For FSL internal interrupts, The sense bit is reserved and zero,
+         * and the interrupt is always level-triggered.  Timers and IPIs
+         * have no sense or polarity bits, and are edge-triggered.
+         */
+        switch (opp->src[n_IRQ].type) {
+        case IRQ_TYPE_NORMAL:
+                opp->src[n_IRQ].level =
+                    !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK);
+                break;
+
+        case IRQ_TYPE_FSLINT:
+                opp->src[n_IRQ].ivpr &= ~IVPR_SENSE_MASK;
+                break;
+
+        case IRQ_TYPE_FSLSPECIAL:
+                opp->src[n_IRQ].ivpr &= ~(IVPR_POLARITY_MASK | IVPR_SENSE_MASK);
+                break;
+        }
+
+        openpic_update_irq(opp, n_IRQ);
+        pr_debug("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val,
+                opp->src[n_IRQ].ivpr);
+}
+
+static void openpic_gcr_write(struct openpic *opp, uint64_t val)
+{
+        if (val & GCR_RESET) {
+                openpic_reset(opp);
+                return;
+        }
+
+        opp->gcr &= ~opp->mpic_mode_mask;
+        opp->gcr |= val & opp->mpic_mode_mask;
+}
+
+static int openpic_gbl_write(void *opaque, gpa_t addr, u32 val)
+{
+        struct openpic *opp = opaque;
+        int err = 0;
+
+        pr_debug("%s: addr %#llx <= %08x\n", __func__, addr, val);
+        if (addr & 0xF)
+                return 0;
+
+        switch (addr) {
+        case 0x00:      /* Block Revision Register1 (BRR1) is Readonly */
+                break;
+        case 0x40:
+        case 0x50:
+        case 0x60:
+        case 0x70:
+        case 0x80:
+        case 0x90:
+        case 0xA0:
+        case 0xB0:
+                err = openpic_cpu_write_internal(opp, addr, val,
+                                                 get_current_cpu());
+                break;
+        case 0x1000:            /* FRR */
+                break;
+        case 0x1020:            /* GCR */
+                openpic_gcr_write(opp, val);
+                break;
+        case 0x1080:            /* VIR */
+                break;
+        case 0x1090:            /* PIR */
+                /*
+                 * This register is used to reset a CPU core --
+                 * let userspace handle it.
+                 */
+                err = -ENXIO;
+                break;
+        case 0x10A0:            /* IPI_IVPR */
+        case 0x10B0:
+        case 0x10C0:
+        case 0x10D0: {
+                int idx;
+                idx = (addr - 0x10A0) >> 4;
+                write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val);
+                break;
+        }
+        case 0x10E0:            /* SPVE */
+                opp->spve = val & opp->vector_mask;
+                break;
+        default:
+                break;
+        }
+
+        return err;
+}
+
+static int openpic_gbl_read(void *opaque, gpa_t addr, u32 *ptr)
+{
+        struct openpic *opp = opaque;
+        u32 retval;
+        int err = 0;
+
+        pr_debug("%s: addr %#llx\n", __func__, addr);
+        retval = 0xFFFFFFFF;
+        if (addr & 0xF)
+                goto out;
+
+        switch (addr) {
+        case 0x1000:            /* FRR */
+                retval = opp->frr;
+                retval |= (opp->nb_cpus - 1) << FRR_NCPU_SHIFT;
+                break;
+        case 0x1020:            /* GCR */
+                retval = opp->gcr;
+                break;
+        case 0x1080:            /* VIR */
+                retval = opp->vir;
+                break;
+        case 0x1090:            /* PIR */
+                retval = 0x00000000;
+                break;
+        case 0x00:              /* Block Revision Register1 (BRR1) */
+                retval = opp->brr1;
+                break;
+        case 0x40:
+        case 0x50:
+        case 0x60:
+        case 0x70:
+        case 0x80:
+        case 0x90:
+        case 0xA0:
+        case 0xB0:
+                err = openpic_cpu_read_internal(opp, addr,
+                        &retval, get_current_cpu());
+                break;
+        case 0x10A0:            /* IPI_IVPR */
+        case 0x10B0:
+        case 0x10C0:
+        case 0x10D0:
+                {
+                        int idx;
+                        idx = (addr - 0x10A0) >> 4;
+                        retval = read_IRQreg_ivpr(opp, opp->irq_ipi0 + idx);
+                }
+                break;
+        case 0x10E0:            /* SPVE */
+                retval = opp->spve;
+                break;
+        default:
+                break;
+        }
+
+out:
+        pr_debug("%s: => 0x%08x\n", __func__, retval);
+        *ptr = retval;
+        return err;
+}
+
+static int openpic_tmr_write(void *opaque, gpa_t addr, u32 val)
+{
+        struct openpic *opp = opaque;
+        int idx;
+
+        addr += 0x10f0;
+
+        pr_debug("%s: addr %#llx <= %08x\n", __func__, addr, val);
+        if (addr & 0xF)
+                return 0;
+
+        if (addr == 0x10f0) {
+                /* TFRR */
+                opp->tfrr = val;
+                return 0;
+        }
+
+        idx = (addr >> 6) & 0x3;
+        addr = addr & 0x30;
+
+        switch (addr & 0x30) {
+        case 0x00:              /* TCCR */
+                break;
+        case 0x10:              /* TBCR */
+                if ((opp->timers[idx].tccr & TCCR_TOG) != 0 &&
+                    (val & TBCR_CI) == 0 &&
+                    (opp->timers[idx].tbcr & TBCR_CI) != 0)
+                        opp->timers[idx].tccr &= ~TCCR_TOG;
+
+                opp->timers[idx].tbcr = val;
+                break;
+        case 0x20:              /* TVPR */
+                write_IRQreg_ivpr(opp, opp->irq_tim0 + idx, val);
+                break;
+        case 0x30:              /* TDR */
+                write_IRQreg_idr(opp, opp->irq_tim0 + idx, val);
+                break;
+        }
+
+        return 0;
+}
+
+static int openpic_tmr_read(void *opaque, gpa_t addr, u32 *ptr)
+{
+        struct openpic *opp = opaque;
+        uint32_t retval = -1;
+        int idx;
+
+        pr_debug("%s: addr %#llx\n", __func__, addr);
+        if (addr & 0xF)
+                goto out;
+
+        idx = (addr >> 6) & 0x3;
+        if (addr == 0x0) {
+                /* TFRR */
+                retval = opp->tfrr;
+                goto out;
+        }
+
+        switch (addr & 0x30) {
+        case 0x00:              /* TCCR */
+                retval = opp->timers[idx].tccr;
+                break;
+        case 0x10:              /* TBCR */
+                retval = opp->timers[idx].tbcr;
+                break;
+        case 0x20:              /* TIPV */
+                retval = read_IRQreg_ivpr(opp, opp->irq_tim0 + idx);
+                break;
+        case 0x30:              /* TIDE (TIDR) */
+                retval = read_IRQreg_idr(opp, opp->irq_tim0 + idx);
+                break;
+        }
+
+out:
+        pr_debug("%s: => 0x%08x\n", __func__, retval);
+        *ptr = retval;
+        return 0;
+}
+
+static int openpic_src_write(void *opaque, gpa_t addr, u32 val)
+{
+        struct openpic *opp = opaque;
+        int idx;
+
+        pr_debug("%s: addr %#llx <= %08x\n", __func__, addr, val);
+
+        addr = addr & 0xffff;
+        idx = addr >> 5;
+
+        switch (addr & 0x1f) {
+        case 0x00:
+                write_IRQreg_ivpr(opp, idx, val);
+                break;
+        case 0x10:
+                write_IRQreg_idr(opp, idx, val);
+                break;
+        case 0x18:
+                write_IRQreg_ilr(opp, idx, val);
+                break;
+        }
+
+        return 0;
+}
+
+static int openpic_src_read(void *opaque, gpa_t addr, u32 *ptr)
+{
+        struct openpic *opp = opaque;
+        uint32_t retval;
+        int idx;
+
+        pr_debug("%s: addr %#llx\n", __func__, addr);
+        retval = 0xFFFFFFFF;
+
+        addr = addr & 0xffff;
+        idx = addr >> 5;
+
+        switch (addr & 0x1f) {
+        case 0x00:
+                retval = read_IRQreg_ivpr(opp, idx);
+                break;
+        case 0x10:
+                retval = read_IRQreg_idr(opp, idx);
+                break;
+        case 0x18:
+                retval = read_IRQreg_ilr(opp, idx);
+                break;
+        }
+
+        pr_debug("%s: => 0x%08x\n", __func__, retval);
+        *ptr = retval;
+        return 0;
+}
+
+static int openpic_msi_write(void *opaque, gpa_t addr, u32 val)
+{
+        struct openpic *opp = opaque;
+        int idx = opp->irq_msi;
+        int srs, ibs;
+
+        pr_debug("%s: addr %#llx <= 0x%08x\n", __func__, addr, val);
+        if (addr & 0xF)
+                return 0;
+
+        switch (addr) {
+        case MSIIR_OFFSET:
+                srs = val >> MSIIR_SRS_SHIFT;
+                idx += srs;
+                ibs = (val & MSIIR_IBS_MASK) >> MSIIR_IBS_SHIFT;
+                opp->msi[srs].msir |= 1 << ibs;
+                openpic_set_irq(opp, idx, 1);
+                break;
+        default:
+                /* most registers are read-only, thus ignored */
+                break;
+        }
+
+        return 0;
+}
+
+static int openpic_msi_read(void *opaque, gpa_t addr, u32 *ptr)
+{
+        struct openpic *opp = opaque;
+        uint32_t r = 0;
+        int i, srs;
+
+        pr_debug("%s: addr %#llx\n", __func__, addr);
+        if (addr & 0xF)
+                return -ENXIO;
+
+        srs = addr >> 4;
+
+        switch (addr) {
+        case 0x00:
+        case 0x10:
+        case 0x20:
+        case 0x30:
+        case 0x40:
+        case 0x50:
+        case 0x60:
+        case 0x70:              /* MSIRs */
+                r = opp->msi[srs].msir;
+                /* Clear on read */
+                opp->msi[srs].msir = 0;
+                openpic_set_irq(opp, opp->irq_msi + srs, 0);
+                break;
+        case 0x120:             /* MSISR */
+                for (i = 0; i < MAX_MSI; i++)
+                        r |= (opp->msi[i].msir ? 1 : 0) << i;
+                break;
+        }
+
+        pr_debug("%s: => 0x%08x\n", __func__, r);
+        *ptr = r;
+        return 0;
+}
+
+static int openpic_summary_read(void *opaque, gpa_t addr, u32 *ptr)
+{
+        uint32_t r = 0;
+
+        pr_debug("%s: addr %#llx\n", __func__, addr);
+
+        /* TODO: EISR/EIMR */
+
+        *ptr = r;
+        return 0;
+}
+
+static int openpic_summary_write(void *opaque, gpa_t addr, u32 val)
+{
+        pr_debug("%s: addr %#llx <= 0x%08x\n", __func__, addr, val);
+
+        /* TODO: EISR/EIMR */
+        return 0;
+}
+
+static int openpic_cpu_write_internal(void *opaque, gpa_t addr,
+                                      u32 val, int idx)
+{
+        struct openpic *opp = opaque;
+        struct irq_source *src;
+        struct irq_dest *dst;
+        int s_IRQ, n_IRQ;
+
+        pr_debug("%s: cpu %d addr %#llx <= 0x%08x\n", __func__, idx,
+                addr, val);
+
+        if (idx < 0)
+                return 0;
+
+        if (addr & 0xF)
+                return 0;
+
+        dst = &opp->dst[idx];
+        addr &= 0xFF0;
+        switch (addr) {
+        case 0x40:              /* IPIDR */
+        case 0x50:
+        case 0x60:
+        case 0x70:
+                idx = (addr - 0x40) >> 4;
+                /* we use IDE as mask which CPUs to deliver the IPI to still. */
+                opp->src[opp->irq_ipi0 + idx].destmask |= val;
+                openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
+                openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
+                break;
+        case 0x80:              /* CTPR */
+                dst->ctpr = val & 0x0000000F;
+
+                pr_debug("%s: set CPU %d ctpr to %d, raised %d servicing %d\n",
+                        __func__, idx, dst->ctpr, dst->raised.priority,
+                        dst->servicing.priority);
+
+                if (dst->raised.priority <= dst->ctpr) {
+                        pr_debug("%s: Lower OpenPIC INT output cpu %d due to ctpr\n",
+                                __func__, idx);
+                        mpic_irq_lower(opp, dst, ILR_INTTGT_INT);
+                } else if (dst->raised.priority > dst->servicing.priority) {
+                        pr_debug("%s: Raise OpenPIC INT output cpu %d irq %d\n",
+                                __func__, idx, dst->raised.next);
+                        mpic_irq_raise(opp, dst, ILR_INTTGT_INT);
+                }
+
+                break;
+        case 0x90:              /* WHOAMI */
+                /* Read-only register */
+                break;
+        case 0xA0:              /* IACK */
+                /* Read-only register */
+                break;
+        case 0xB0: {            /* EOI */
+                int notify_eoi;
+
+                pr_debug("EOI\n");
+                s_IRQ = IRQ_get_next(opp, &dst->servicing);
+
+                if (s_IRQ < 0) {
+                        pr_debug("%s: EOI with no interrupt in service\n",
+                                __func__);
+                        break;
+                }
+
+                IRQ_resetbit(&dst->servicing, s_IRQ);
+                /* Notify listeners that the IRQ is over */
+                notify_eoi = s_IRQ;
+                /* Set up next servicing IRQ */
+                s_IRQ = IRQ_get_next(opp, &dst->servicing);
+                /* Check queued interrupts. */
+                n_IRQ = IRQ_get_next(opp, &dst->raised);
+                src = &opp->src[n_IRQ];
+                if (n_IRQ != -1 &&
+                    (s_IRQ == -1 ||
+                     IVPR_PRIORITY(src->ivpr) > dst->servicing.priority)) {
+                        pr_debug("Raise OpenPIC INT output cpu %d irq %d\n",
+                                idx, n_IRQ);
+                        mpic_irq_raise(opp, dst, ILR_INTTGT_INT);
+                }
+
+                spin_unlock(&opp->lock);
+                kvm_notify_acked_irq(opp->kvm, 0, notify_eoi);
+                spin_lock(&opp->lock);
+
+                break;
+        }
+        default:
+                break;
+        }
+
+        return 0;
+}
+
+static int openpic_cpu_write(void *opaque, gpa_t addr, u32 val)
+{
+        struct openpic *opp = opaque;
+
+        return openpic_cpu_write_internal(opp, addr, val,
+                                         (addr & 0x1f000) >> 12);
+}
+
+static uint32_t openpic_iack(struct openpic *opp, struct irq_dest *dst,
+                             int cpu)
+{
+        struct irq_source *src;
+        int retval, irq;
+
+        pr_debug("Lower OpenPIC INT output\n");
+        mpic_irq_lower(opp, dst, ILR_INTTGT_INT);
+
+        irq = IRQ_get_next(opp, &dst->raised);
+        pr_debug("IACK: irq=%d\n", irq);
+
+        if (irq == -1)
+                /* No more interrupt pending */
+                return opp->spve;
+
+        src = &opp->src[irq];
+        if (!(src->ivpr & IVPR_ACTIVITY_MASK) ||
+            !(IVPR_PRIORITY(src->ivpr) > dst->ctpr)) {
+                pr_err("%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n",
+                        __func__, irq, dst->ctpr, src->ivpr);
+                openpic_update_irq(opp, irq);
+                retval = opp->spve;
+        } else {
+                /* IRQ enter servicing state */
+                IRQ_setbit(&dst->servicing, irq);
+                retval = IVPR_VECTOR(opp, src->ivpr);
+        }
+
+        if (!src->level) {
+                /* edge-sensitive IRQ */
+                src->ivpr &= ~IVPR_ACTIVITY_MASK;
+                src->pending = 0;
+                IRQ_resetbit(&dst->raised, irq);
+        }
+
+        if ((irq >= opp->irq_ipi0) && (irq < (opp->irq_ipi0 + MAX_IPI))) {
+                src->destmask &= ~(1 << cpu);
+                if (src->destmask && !src->level) {
+                        /* trigger on CPUs that didn't know about it yet */
+                        openpic_set_irq(opp, irq, 1);
+                        openpic_set_irq(opp, irq, 0);
+                        /* if all CPUs knew about it, set active bit again */
+                        src->ivpr |= IVPR_ACTIVITY_MASK;
+                }
+        }
+
+        return retval;
+}
+
+void kvmppc_mpic_set_epr(struct kvm_vcpu *vcpu)
+{
+        struct openpic *opp = vcpu->arch.mpic;
+        int cpu = vcpu->arch.irq_cpu_id;
+        unsigned long flags;
+
+        spin_lock_irqsave(&opp->lock, flags);
+
+        if ((opp->gcr & opp->mpic_mode_mask) == GCR_MODE_PROXY)
+                kvmppc_set_epr(vcpu, openpic_iack(opp, &opp->dst[cpu], cpu));
+
+        spin_unlock_irqrestore(&opp->lock, flags);
+}
+
+static int openpic_cpu_read_internal(void *opaque, gpa_t addr,
+                                     u32 *ptr, int idx)
+{
+        struct openpic *opp = opaque;
+        struct irq_dest *dst;
+        uint32_t retval;
+
+        pr_debug("%s: cpu %d addr %#llx\n", __func__, idx, addr);
+        retval = 0xFFFFFFFF;
+
+        if (idx < 0)
+                goto out;
+
+        if (addr & 0xF)
+                goto out;
+
+        dst = &opp->dst[idx];
+        addr &= 0xFF0;
+        switch (addr) {
+        case 0x80:              /* CTPR */
+                retval = dst->ctpr;
+                break;
+        case 0x90:              /* WHOAMI */
+                retval = idx;
+                break;
+        case 0xA0:              /* IACK */
+                retval = openpic_iack(opp, dst, idx);
+                break;
+        case 0xB0:              /* EOI */
+                retval = 0;
+                break;
+        default:
+                break;
+        }
+        pr_debug("%s: => 0x%08x\n", __func__, retval);
+
+out:
+        *ptr = retval;
+        return 0;
+}
+
+static int openpic_cpu_read(void *opaque, gpa_t addr, u32 *ptr)
+{
+        struct openpic *opp = opaque;
+
+        return openpic_cpu_read_internal(opp, addr, ptr,
+                                         (addr & 0x1f000) >> 12);
+}
+
+struct mem_reg {
+        int (*read)(void *opaque, gpa_t addr, u32 *ptr);
+        int (*write)(void *opaque, gpa_t addr, u32 val);
+        gpa_t start_addr;
+        int size;
+};
+
+static const struct mem_reg openpic_gbl_mmio = {
+        .write = openpic_gbl_write,
+        .read = openpic_gbl_read,
+        .start_addr = OPENPIC_GLB_REG_START,
+        .size = OPENPIC_GLB_REG_SIZE,
+};
+
+static const struct mem_reg openpic_tmr_mmio = {
+        .write = openpic_tmr_write,
+        .read = openpic_tmr_read,
+        .start_addr = OPENPIC_TMR_REG_START,
+        .size = OPENPIC_TMR_REG_SIZE,
+};
+
+static const struct mem_reg openpic_cpu_mmio = {
+        .write = openpic_cpu_write,
+        .read = openpic_cpu_read,
+        .start_addr = OPENPIC_CPU_REG_START,
+        .size = OPENPIC_CPU_REG_SIZE,
+};
+
+static const struct mem_reg openpic_src_mmio = {
+        .write = openpic_src_write,
+        .read = openpic_src_read,
+        .start_addr = OPENPIC_SRC_REG_START,
+        .size = OPENPIC_SRC_REG_SIZE,
+};
+
+static const struct mem_reg openpic_msi_mmio = {
+        .read = openpic_msi_read,
+        .write = openpic_msi_write,
+        .start_addr = OPENPIC_MSI_REG_START,
+        .size = OPENPIC_MSI_REG_SIZE,
+};
+
+static const struct mem_reg openpic_summary_mmio = {
+        .read = openpic_summary_read,
+        .write = openpic_summary_write,
+        .start_addr = OPENPIC_SUMMARY_REG_START,
+        .size = OPENPIC_SUMMARY_REG_SIZE,
+};
+
+static void add_mmio_region(struct openpic *opp, const struct mem_reg *mr)
+{
+        if (opp->num_mmio_regions >= MAX_MMIO_REGIONS) {
+                WARN(1, "kvm mpic: too many mmio regions\n");
+                return;
+        }
+
+        opp->mmio_regions[opp->num_mmio_regions++] = mr;
+}
+
+static void fsl_common_init(struct openpic *opp)
+{
+        int i;
+        int virq = MAX_SRC;
+
+        add_mmio_region(opp, &openpic_msi_mmio);
+        add_mmio_region(opp, &openpic_summary_mmio);
+
+        opp->vid = VID_REVISION_1_2;
+        opp->vir = VIR_GENERIC;
+        opp->vector_mask = 0xFFFF;
+        opp->tfrr_reset = 0;
+        opp->ivpr_reset = IVPR_MASK_MASK;
+        opp->idr_reset = 1 << 0;
+        opp->max_irq = MAX_IRQ;
+
+        opp->irq_ipi0 = virq;
+        virq += MAX_IPI;
+        opp->irq_tim0 = virq;
+        virq += MAX_TMR;
+
+        BUG_ON(virq > MAX_IRQ);
+
+        opp->irq_msi = 224;
+
+        for (i = 0; i < opp->fsl->max_ext; i++)
+                opp->src[i].level = false;
+
+        /* Internal interrupts, including message and MSI */
+        for (i = 16; i < MAX_SRC; i++) {
+                opp->src[i].type = IRQ_TYPE_FSLINT;
+                opp->src[i].level = true;
+        }
+
+        /* timers and IPIs */
+        for (i = MAX_SRC; i < virq; i++) {
+                opp->src[i].type = IRQ_TYPE_FSLSPECIAL;
+                opp->src[i].level = false;
+        }
+}
+
+static int kvm_mpic_read_internal(struct openpic *opp, gpa_t addr, u32 *ptr)
+{
+        int i;
+
+        for (i = 0; i < opp->num_mmio_regions; i++) {
+                const struct mem_reg *mr = opp->mmio_regions[i];
+
+                if (mr->start_addr > addr || addr >= mr->start_addr + mr->size)
+                        continue;
+
+                return mr->read(opp, addr - mr->start_addr, ptr);
+        }
+
+        return -ENXIO;
+}
+
+static int kvm_mpic_write_internal(struct openpic *opp, gpa_t addr, u32 val)
+{
+        int i;
+
+        for (i = 0; i < opp->num_mmio_regions; i++) {
+                const struct mem_reg *mr = opp->mmio_regions[i];
+
+                if (mr->start_addr > addr || addr >= mr->start_addr + mr->size)
+                        continue;
+
+                return mr->write(opp, addr - mr->start_addr, val);
+        }
+
+        return -ENXIO;
+}
+
+static int kvm_mpic_read(struct kvm_io_device *this, gpa_t addr,
+                         int len, void *ptr)
+{
+        struct openpic *opp = container_of(this, struct openpic, mmio);
+        int ret;
+        union {
+                u32 val;
+                u8 bytes[4];
+        } u;
+
+        if (addr & (len - 1)) {
+                pr_debug("%s: bad alignment %llx/%d\n",
+                         __func__, addr, len);
+                return -EINVAL;
+        }
+
+        spin_lock_irq(&opp->lock);
+        ret = kvm_mpic_read_internal(opp, addr - opp->reg_base, &u.val);
+        spin_unlock_irq(&opp->lock);
+
+        /*
+         * Technically only 32-bit accesses are allowed, but be nice to
+         * people dumping registers a byte at a time -- it works in real
+         * hardware (reads only, not writes).
+         */
+        if (len == 4) {
+                *(u32 *)ptr = u.val;
+                pr_debug("%s: addr %llx ret %d len 4 val %x\n",
+                         __func__, addr, ret, u.val);
+        } else if (len == 1) {
+                *(u8 *)ptr = u.bytes[addr & 3];
+                pr_debug("%s: addr %llx ret %d len 1 val %x\n",
+                         __func__, addr, ret, u.bytes[addr & 3]);
+        } else {
+                pr_debug("%s: bad length %d\n", __func__, len);
+                return -EINVAL;
+        }
+
+        return ret;
+}
+
+static int kvm_mpic_write(struct kvm_io_device *this, gpa_t addr,
+                          int len, const void *ptr)
+{
+        struct openpic *opp = container_of(this, struct openpic, mmio);
+        int ret;
+
+        if (len != 4) {
+                pr_debug("%s: bad length %d\n", __func__, len);
+                return -EOPNOTSUPP;
+        }
+        if (addr & 3) {
+                pr_debug("%s: bad alignment %llx/%d\n", __func__, addr, len);
+                return -EOPNOTSUPP;
+        }
+
+        spin_lock_irq(&opp->lock);
+        ret = kvm_mpic_write_internal(opp, addr - opp->reg_base,
+                                      *(const u32 *)ptr);
+        spin_unlock_irq(&opp->lock);
+
+        pr_debug("%s: addr %llx ret %d val %x\n",
+                 __func__, addr, ret, *(const u32 *)ptr);
+
+        return ret;
+}
+
+static const struct kvm_io_device_ops mpic_mmio_ops = {
+        .read = kvm_mpic_read,
+        .write = kvm_mpic_write,
+};
+
+static void map_mmio(struct openpic *opp)
+{
+        kvm_iodevice_init(&opp->mmio, &mpic_mmio_ops);
+
+        kvm_io_bus_register_dev(opp->kvm, KVM_MMIO_BUS,
+                                opp->reg_base, OPENPIC_REG_SIZE,
+                                &opp->mmio);
+}
+
+static void unmap_mmio(struct openpic *opp)
+{
+        kvm_io_bus_unregister_dev(opp->kvm, KVM_MMIO_BUS, &opp->mmio);
+}
+
+static int set_base_addr(struct openpic *opp, struct kvm_device_attr *attr)
+{
+        u64 base;
+
+        if (copy_from_user(&base, (u64 __user *)(long)attr->addr, sizeof(u64)))
+                return -EFAULT;
+
+        if (base & 0x3ffff) {
+                pr_debug("kvm mpic %s: KVM_DEV_MPIC_BASE_ADDR %08llx not aligned\n",
+                         __func__, base);
+                return -EINVAL;
+        }
+
+        if (base == opp->reg_base)
+                return 0;
+
+        mutex_lock(&opp->kvm->slots_lock);
+
+        unmap_mmio(opp);
+        opp->reg_base = base;
+
+        pr_debug("kvm mpic %s: KVM_DEV_MPIC_BASE_ADDR %08llx\n",
+                 __func__, base);
+
+        if (base == 0)
+                goto out;
+
+        map_mmio(opp);
+
+out:
+        mutex_unlock(&opp->kvm->slots_lock);
+        return 0;
+}
+
+#define ATTR_SET                0
+#define ATTR_GET                1
+
+static int access_reg(struct openpic *opp, gpa_t addr, u32 *val, int type)
+{
+        int ret;
+
+        if (addr & 3)
+                return -ENXIO;
+
+        spin_lock_irq(&opp->lock);
+
+        if (type == ATTR_SET)
+                ret = kvm_mpic_write_internal(opp, addr, *val);
+        else
+                ret = kvm_mpic_read_internal(opp, addr, val);
+
+        spin_unlock_irq(&opp->lock);
+
+        pr_debug("%s: type %d addr %llx val %x\n", __func__, type, addr, *val);
+
+        return ret;
+}
+
+static int mpic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
+{
+        struct openpic *opp = dev->private;
+        u32 attr32;
+
+        switch (attr->group) {
+        case KVM_DEV_MPIC_GRP_MISC:
+                switch (attr->attr) {
+                case KVM_DEV_MPIC_BASE_ADDR:
+                        return set_base_addr(opp, attr);
+                }
+
+                break;
+
+        case KVM_DEV_MPIC_GRP_REGISTER:
+                if (get_user(attr32, (u32 __user *)(long)attr->addr))
+                        return -EFAULT;
+
+                return access_reg(opp, attr->attr, &attr32, ATTR_SET);
+
+        case KVM_DEV_MPIC_GRP_IRQ_ACTIVE:
+                if (attr->attr > MAX_SRC)
+                        return -EINVAL;
+
+                if (get_user(attr32, (u32 __user *)(long)attr->addr))
+                        return -EFAULT;
+
+                if (attr32 != 0 && attr32 != 1)
+                        return -EINVAL;
+
+                spin_lock_irq(&opp->lock);
+                openpic_set_irq(opp, attr->attr, attr32);
+                spin_unlock_irq(&opp->lock);
+                return 0;
+        }
+
+        return -ENXIO;
+}
+
+static int mpic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
+{
+        struct openpic *opp = dev->private;
+        u64 attr64;
+        u32 attr32;
+        int ret;
+
+        switch (attr->group) {
+        case KVM_DEV_MPIC_GRP_MISC:
+                switch (attr->attr) {
+                case KVM_DEV_MPIC_BASE_ADDR:
+                        mutex_lock(&opp->kvm->slots_lock);
+                        attr64 = opp->reg_base;
+                        mutex_unlock(&opp->kvm->slots_lock);
+
+                        if (copy_to_user((u64 __user *)(long)attr->addr,
+                                         &attr64, sizeof(u64)))
+                                return -EFAULT;
+
+                        return 0;
+                }
+
+                break;
+
+        case KVM_DEV_MPIC_GRP_REGISTER:
+                ret = access_reg(opp, attr->attr, &attr32, ATTR_GET);
+                if (ret)
+                        return ret;
+
+                if (put_user(attr32, (u32 __user *)(long)attr->addr))
+                        return -EFAULT;
+
+                return 0;
+
+        case KVM_DEV_MPIC_GRP_IRQ_ACTIVE:
+                if (attr->attr > MAX_SRC)
+                        return -EINVAL;
+
+                spin_lock_irq(&opp->lock);
+                attr32 = opp->src[attr->attr].pending;
+                spin_unlock_irq(&opp->lock);
+
+                if (put_user(attr32, (u32 __user *)(long)attr->addr))
+                        return -EFAULT;
+
+                return 0;
+        }
+
+        return -ENXIO;
+}
+
+static int mpic_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
+{
+        switch (attr->group) {
+        case KVM_DEV_MPIC_GRP_MISC:
+                switch (attr->attr) {
+                case KVM_DEV_MPIC_BASE_ADDR:
+                        return 0;
+                }
+
+                break;
+
+        case KVM_DEV_MPIC_GRP_REGISTER:
+                return 0;
+
+        case KVM_DEV_MPIC_GRP_IRQ_ACTIVE:
+                if (attr->attr > MAX_SRC)
+                        break;
+
+                return 0;
+        }
+
+        return -ENXIO;
+}
+
+static void mpic_destroy(struct kvm_device *dev)
+{
+        struct openpic *opp = dev->private;
+
+        dev->kvm->arch.mpic = NULL;
+        kfree(opp);
+}
+
+static int mpic_set_default_irq_routing(struct openpic *opp)
+{
+        struct kvm_irq_routing_entry *routing;
+
+        /* Create a nop default map, so that dereferencing it still works */
+        routing = kzalloc((sizeof(*routing)), GFP_KERNEL);
+        if (!routing)
+                return -ENOMEM;
+
+        kvm_set_irq_routing(opp->kvm, routing, 0, 0);
+
+        kfree(routing);
+        return 0;
+}
+
+static int mpic_create(struct kvm_device *dev, u32 type)
+{
+        struct openpic *opp;
+        int ret;
+
+        /* We only support one MPIC at a time for now */
+        if (dev->kvm->arch.mpic)
+                return -EINVAL;
+
+        opp = kzalloc(sizeof(struct openpic), GFP_KERNEL);
+        if (!opp)
+                return -ENOMEM;
+
+        dev->private = opp;
+        opp->kvm = dev->kvm;
+        opp->dev = dev;
+        opp->model = type;
+        spin_lock_init(&opp->lock);
+
+        add_mmio_region(opp, &openpic_gbl_mmio);
+        add_mmio_region(opp, &openpic_tmr_mmio);
+        add_mmio_region(opp, &openpic_src_mmio);
+        add_mmio_region(opp, &openpic_cpu_mmio);
+
+        switch (opp->model) {
+        case KVM_DEV_TYPE_FSL_MPIC_20:
+                opp->fsl = &fsl_mpic_20;
+                opp->brr1 = 0x00400200;
+                opp->flags |= OPENPIC_FLAG_IDR_CRIT;
+                opp->nb_irqs = 80;
+                opp->mpic_mode_mask = GCR_MODE_MIXED;
+
+                fsl_common_init(opp);
+
+                break;
+
+        case KVM_DEV_TYPE_FSL_MPIC_42:
+                opp->fsl = &fsl_mpic_42;
+                opp->brr1 = 0x00400402;
+                opp->flags |= OPENPIC_FLAG_ILR;
+                opp->nb_irqs = 196;
+                opp->mpic_mode_mask = GCR_MODE_PROXY;
+
+                fsl_common_init(opp);
+
+                break;
+
+        default:
+                ret = -ENODEV;
+                goto err;
+        }
+
+        ret = mpic_set_default_irq_routing(opp);
+        if (ret)
+                goto err;
+
+        openpic_reset(opp);
+
+        smp_wmb();
+        dev->kvm->arch.mpic = opp;
+
+        return 0;
+
+err:
+        kfree(opp);
+        return ret;
+}
+
+struct kvm_device_ops kvm_mpic_ops = {
+        .name = "kvm-mpic",
+        .create = mpic_create,
+        .destroy = mpic_destroy,
+        .set_attr = mpic_set_attr,
+        .get_attr = mpic_get_attr,
+        .has_attr = mpic_has_attr,
+};
+
+int kvmppc_mpic_connect_vcpu(struct kvm_device *dev, struct kvm_vcpu *vcpu,
+                             u32 cpu)
+{
+        struct openpic *opp = dev->private;
+        int ret = 0;
+
+        if (dev->ops != &kvm_mpic_ops)
+                return -EPERM;
+        if (opp->kvm != vcpu->kvm)
+                return -EPERM;
+        if (cpu < 0 || cpu >= MAX_CPU)
+                return -EPERM;
+
+        spin_lock_irq(&opp->lock);
+
+        if (opp->dst[cpu].vcpu) {
+                ret = -EEXIST;
+                goto out;
+        }
+        if (vcpu->arch.irq_type) {
+                ret = -EBUSY;
+                goto out;
+        }
+
+        opp->dst[cpu].vcpu = vcpu;
+        opp->nb_cpus = max(opp->nb_cpus, cpu + 1);
+
+        vcpu->arch.mpic = opp;
+        vcpu->arch.irq_cpu_id = cpu;
+        vcpu->arch.irq_type = KVMPPC_IRQ_MPIC;
+
+        /* This might need to be changed if GCR gets extended */
+        if (opp->mpic_mode_mask == GCR_MODE_PROXY)
+                vcpu->arch.epr_flags |= KVMPPC_EPR_KERNEL;
+
+out:
+        spin_unlock_irq(&opp->lock);
+        return ret;
+}
+
+/*
+ * This should only happen immediately before the mpic is destroyed,
+ * so we shouldn't need to worry about anything still trying to
+ * access the vcpu pointer.
+ */
+void kvmppc_mpic_disconnect_vcpu(struct openpic *opp, struct kvm_vcpu *vcpu)
+{
+        BUG_ON(!opp->dst[vcpu->arch.irq_cpu_id].vcpu);
+
+        opp->dst[vcpu->arch.irq_cpu_id].vcpu = NULL;
+}
+
+/*
+ * Return value:
+ *  < 0   Interrupt was ignored (masked or not delivered for other reasons)
+ *  = 0   Interrupt was coalesced (previous irq is still pending)
+ *  > 0   Number of CPUs interrupt was delivered to
+ */
+static int mpic_set_irq(struct kvm_kernel_irq_routing_entry *e,
+                        struct kvm *kvm, int irq_source_id, int level,
+                        bool line_status)
+{
+        u32 irq = e->irqchip.pin;
+        struct openpic *opp = kvm->arch.mpic;
+        unsigned long flags;
+
+        spin_lock_irqsave(&opp->lock, flags);
+        openpic_set_irq(opp, irq, level);
+        spin_unlock_irqrestore(&opp->lock, flags);
+
+        /* All code paths we care about don't check for the return value */
+        return 0;
+}
+
+int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e,
+                struct kvm *kvm, int irq_source_id, int level, bool line_status)
+{
+        struct openpic *opp = kvm->arch.mpic;
+        unsigned long flags;
+
+        spin_lock_irqsave(&opp->lock, flags);
+
+        /*
+         * XXX We ignore the target address for now, as we only support
+         *     a single MSI bank.
+         */
+        openpic_msi_write(kvm->arch.mpic, MSIIR_OFFSET, e->msi.data);
+        spin_unlock_irqrestore(&opp->lock, flags);
+
+        /* All code paths we care about don't check for the return value */
+        return 0;
+}
+
+int kvm_set_routing_entry(struct kvm_irq_routing_table *rt,
+                          struct kvm_kernel_irq_routing_entry *e,
+                          const struct kvm_irq_routing_entry *ue)
+{
+        int r = -EINVAL;
+
+        switch (ue->type) {
+        case KVM_IRQ_ROUTING_IRQCHIP:
+                e->set = mpic_set_irq;
+                e->irqchip.irqchip = ue->u.irqchip.irqchip;
+                e->irqchip.pin = ue->u.irqchip.pin;
+                if (e->irqchip.pin >= KVM_IRQCHIP_NUM_PINS)
+                        goto out;
+                rt->chip[ue->u.irqchip.irqchip][e->irqchip.pin] = ue->gsi;
+                break;
+        case KVM_IRQ_ROUTING_MSI:
+                e->set = kvm_set_msi;
+                e->msi.address_lo = ue->u.msi.address_lo;
+                e->msi.address_hi = ue->u.msi.address_hi;
+                e->msi.data = ue->u.msi.data;
+                break;
+        default:
+                goto out;
+        }
+
+        r = 0;
+out:
+        return r;
+}
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 934413cd3a1b..6316ee336e88 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc/kvm/powerpc.c
@@ -25,6 +25,7 @@
 #include <linux/hrtimer.h>
 #include <linux/fs.h>
 #include <linux/slab.h>
+#include <linux/file.h>
 #include <asm/cputable.h>
 #include <asm/uaccess.h>
 #include <asm/kvm_ppc.h>
@@ -32,6 +33,7 @@
 #include <asm/cputhreads.h>
 #include <asm/irqflags.h>
 #include "timing.h"
+#include "irq.h"
 #include "../mm/mmu_decl.h"
 
 #define CREATE_TRACE_POINTS
@@ -317,6 +319,7 @@ int kvm_dev_ioctl_check_extension(long ext)
         case KVM_CAP_ENABLE_CAP:
         case KVM_CAP_ONE_REG:
         case KVM_CAP_IOEVENTFD:
+        case KVM_CAP_DEVICE_CTRL:
                 r = 1;
                 break;
 #ifndef CONFIG_KVM_BOOK3S_64_HV
@@ -326,6 +329,9 @@ int kvm_dev_ioctl_check_extension(long ext)
 #if defined(CONFIG_KVM_E500V2) || defined(CONFIG_KVM_E500MC)
         case KVM_CAP_SW_TLB:
 #endif
+#ifdef CONFIG_KVM_MPIC
+        case KVM_CAP_IRQ_MPIC:
+#endif
                 r = 1;
                 break;
         case KVM_CAP_COALESCED_MMIO:
@@ -335,6 +341,10 @@ int kvm_dev_ioctl_check_extension(long ext)
 #ifdef CONFIG_PPC_BOOK3S_64
         case KVM_CAP_SPAPR_TCE:
         case KVM_CAP_PPC_ALLOC_HTAB:
+        case KVM_CAP_PPC_RTAS:
+#ifdef CONFIG_KVM_XICS
+        case KVM_CAP_IRQ_XICS:
+#endif
                 r = 1;
                 break;
 #endif /* CONFIG_PPC_BOOK3S_64 */
@@ -411,18 +421,17 @@ int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
 }
 
 int kvm_arch_prepare_memory_region(struct kvm *kvm,
-                                   struct kvm_memory_slot *memslot,
-                                   struct kvm_memory_slot old,
-                                   struct kvm_userspace_memory_region *mem,
-                                   bool user_alloc)
+                                   struct kvm_memory_slot *memslot,
+                                   struct kvm_userspace_memory_region *mem,
+                                   enum kvm_mr_change change)
 {
         return kvmppc_core_prepare_memory_region(kvm, memslot, mem);
 }
 
 void kvm_arch_commit_memory_region(struct kvm *kvm,
-               struct kvm_userspace_memory_region *mem,
-               struct kvm_memory_slot old,
-               bool user_alloc)
+                                   struct kvm_userspace_memory_region *mem,
+                                   const struct kvm_memory_slot *old,
+                                   enum kvm_mr_change change)
 {
         kvmppc_core_commit_memory_region(kvm, mem, old);
 }
@@ -460,6 +469,16 @@ void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
         tasklet_kill(&vcpu->arch.tasklet);
 
         kvmppc_remove_vcpu_debugfs(vcpu);
+
+        switch (vcpu->arch.irq_type) {
+        case KVMPPC_IRQ_MPIC:
+                kvmppc_mpic_disconnect_vcpu(vcpu->arch.mpic, vcpu);
+                break;
+        case KVMPPC_IRQ_XICS:
+                kvmppc_xics_free_icp(vcpu);
+                break;
+        }
+
         kvmppc_core_vcpu_free(vcpu);
 }
 
@@ -532,12 +551,6 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
 #endif
 }
 
-int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
-                                        struct kvm_guest_debug *dbg)
-{
-        return -EINVAL;
-}
-
 static void kvmppc_complete_dcr_load(struct kvm_vcpu *vcpu,
                                      struct kvm_run *run)
 {
@@ -612,6 +625,8 @@ static void kvmppc_complete_mmio_load(struct kvm_vcpu *vcpu,
 int kvmppc_handle_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
                        unsigned int rt, unsigned int bytes, int is_bigendian)
 {
+        int idx, ret;
+
         if (bytes > sizeof(run->mmio.data)) {
                 printk(KERN_ERR "%s: bad MMIO length: %d\n", __func__,
                        run->mmio.len);
@@ -627,8 +642,14 @@ int kvmppc_handle_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
         vcpu->mmio_is_write = 0;
         vcpu->arch.mmio_sign_extend = 0;
 
-        if (!kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, run->mmio.phys_addr,
-                             bytes, &run->mmio.data)) {
+        idx = srcu_read_lock(&vcpu->kvm->srcu);
+
+        ret = kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, run->mmio.phys_addr,
+                              bytes, &run->mmio.data);
+
+        srcu_read_unlock(&vcpu->kvm->srcu, idx);
+
+        if (!ret) {
                 kvmppc_complete_mmio_load(vcpu, run);
                 vcpu->mmio_needed = 0;
                 return EMULATE_DONE;
@@ -653,6 +674,7 @@ int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
                         u64 val, unsigned int bytes, int is_bigendian)
 {
         void *data = run->mmio.data;
+        int idx, ret;
 
         if (bytes > sizeof(run->mmio.data)) {
                 printk(KERN_ERR "%s: bad MMIO length: %d\n", __func__,
@@ -682,9 +704,14 @@ int kvmppc_handle_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
                 }
         }
 
-        if (!kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, run->mmio.phys_addr,
-                              bytes, &run->mmio.data)) {
-                kvmppc_complete_mmio_load(vcpu, run);
+        idx = srcu_read_lock(&vcpu->kvm->srcu);
+
+        ret = kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, run->mmio.phys_addr,
+                               bytes, &run->mmio.data);
+
+        srcu_read_unlock(&vcpu->kvm->srcu, idx);
+
+        if (!ret) {
                 vcpu->mmio_needed = 0;
                 return EMULATE_DONE;
         }
@@ -740,7 +767,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, struct kvm_interrupt *irq)
 {
         if (irq->irq == KVM_INTERRUPT_UNSET) {
-                kvmppc_core_dequeue_external(vcpu, irq);
+                kvmppc_core_dequeue_external(vcpu);
                 return 0;
         }
 
@@ -770,7 +797,10 @@ static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
                 break;
         case KVM_CAP_PPC_EPR:
                 r = 0;
-                vcpu->arch.epr_enabled = cap->args[0];
+                if (cap->args[0])
+                        vcpu->arch.epr_flags |= KVMPPC_EPR_USER;
+                else
+                        vcpu->arch.epr_flags &= ~KVMPPC_EPR_USER;
                 break;
 #ifdef CONFIG_BOOKE
         case KVM_CAP_PPC_BOOKE_WATCHDOG:
@@ -791,6 +821,44 @@ static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
                 break;
         }
 #endif
+#ifdef CONFIG_KVM_MPIC
+        case KVM_CAP_IRQ_MPIC: {
+                struct file *filp;
+                struct kvm_device *dev;
+
+                r = -EBADF;
+                filp = fget(cap->args[0]);
+                if (!filp)
+                        break;
+
+                r = -EPERM;
+                dev = kvm_device_from_filp(filp);
+                if (dev)
+                        r = kvmppc_mpic_connect_vcpu(dev, vcpu, cap->args[1]);
+
+                fput(filp);
+                break;
+        }
+#endif
+#ifdef CONFIG_KVM_XICS
+        case KVM_CAP_IRQ_XICS: {
+                struct file *filp;
+                struct kvm_device *dev;
+
+                r = -EBADF;
+                filp = fget(cap->args[0]);
+                if (!filp)
+                        break;
+
+                r = -EPERM;
+                dev = kvm_device_from_filp(filp);
+                if (dev)
+                        r = kvmppc_xics_connect_vcpu(dev, vcpu, cap->args[1]);
+
+                fput(filp);
+                break;
+        }
+#endif /* CONFIG_KVM_XICS */
         default:
                 r = -EINVAL;
                 break;
@@ -913,9 +981,22 @@ static int kvm_vm_ioctl_get_pvinfo(struct kvm_ppc_pvinfo *pvinfo)
         return 0;
 }
 
+int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
+                          bool line_status)
+{
+        if (!irqchip_in_kernel(kvm))
+                return -ENXIO;
+
+        irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
+                                        irq_event->irq, irq_event->level,
+                                        line_status);
+        return 0;
+}
+
 long kvm_arch_vm_ioctl(struct file *filp,
                        unsigned int ioctl, unsigned long arg)
 {
+        struct kvm *kvm __maybe_unused = filp->private_data;
         void __user *argp = (void __user *)arg;
         long r;
 
@@ -934,7 +1015,6 @@ long kvm_arch_vm_ioctl(struct file *filp,
 #ifdef CONFIG_PPC_BOOK3S_64
         case KVM_CREATE_SPAPR_TCE: {
                 struct kvm_create_spapr_tce create_tce;
-                struct kvm *kvm = filp->private_data;
 
                 r = -EFAULT;
                 if (copy_from_user(&create_tce, argp, sizeof(create_tce)))
@@ -946,8 +1026,8 @@ long kvm_arch_vm_ioctl(struct file *filp,
 
 #ifdef CONFIG_KVM_BOOK3S_64_HV
         case KVM_ALLOCATE_RMA: {
-                struct kvm *kvm = filp->private_data;
                 struct kvm_allocate_rma rma;
+                struct kvm *kvm = filp->private_data;
 
                 r = kvm_vm_ioctl_allocate_rma(kvm, &rma);
                 if (r >= 0 && copy_to_user(argp, &rma, sizeof(rma)))
@@ -956,7 +1036,6 @@ long kvm_arch_vm_ioctl(struct file *filp,
         }
 
         case KVM_PPC_ALLOCATE_HTAB: {
-                struct kvm *kvm = filp->private_data;
                 u32 htab_order;
 
                 r = -EFAULT;
@@ -973,7 +1052,6 @@ long kvm_arch_vm_ioctl(struct file *filp,
         }
 
         case KVM_PPC_GET_HTAB_FD: {
-                struct kvm *kvm = filp->private_data;
                 struct kvm_get_htab_fd ghf;
 
                 r = -EFAULT;
@@ -986,7 +1064,6 @@ long kvm_arch_vm_ioctl(struct file *filp,
 
 #ifdef CONFIG_PPC_BOOK3S_64
         case KVM_PPC_GET_SMMU_INFO: {
-                struct kvm *kvm = filp->private_data;
                 struct kvm_ppc_smmu_info info;
 
                 memset(&info, 0, sizeof(info));
@@ -995,6 +1072,12 @@ long kvm_arch_vm_ioctl(struct file *filp,
                         r = -EFAULT;
                 break;
         }
+        case KVM_PPC_RTAS_DEFINE_TOKEN: {
+                struct kvm *kvm = filp->private_data;
+
+                r = kvm_vm_ioctl_rtas_define_token(kvm, argp);
+                break;
+        }
 #endif /* CONFIG_PPC_BOOK3S_64 */
         default:
                 r = -ENOTTY;
diff --git a/arch/powerpc/mm/gup.c b/arch/powerpc/mm/gup.c
index d7efdbf640c7..4b921affa495 100644
--- a/arch/powerpc/mm/gup.c
+++ b/arch/powerpc/mm/gup.c
@@ -68,7 +68,11 @@ static int gup_pmd_range(pud_t pud, unsigned long addr, unsigned long end,
                 next = pmd_addr_end(addr, end);
                 if (pmd_none(pmd))
                         return 0;
-                if (is_hugepd(pmdp)) {
+                if (pmd_huge(pmd)) {
+                        if (!gup_hugepte((pte_t *)pmdp, PMD_SIZE, addr, next,
+                                         write, pages, nr))
+                                return 0;
+                } else if (is_hugepd(pmdp)) {
                         if (!gup_hugepd((hugepd_t *)pmdp, PMD_SHIFT,
                                         addr, next, write, pages, nr))
                                 return 0;
@@ -92,7 +96,11 @@ static int gup_pud_range(pgd_t pgd, unsigned long addr, unsigned long end,
                 next = pud_addr_end(addr, end);
                 if (pud_none(pud))
                         return 0;
-                if (is_hugepd(pudp)) {
+                if (pud_huge(pud)) {
+                        if (!gup_hugepte((pte_t *)pudp, PUD_SIZE, addr, next,
+                                         write, pages, nr))
+                                return 0;
+                } else if (is_hugepd(pudp)) {
                         if (!gup_hugepd((hugepd_t *)pudp, PUD_SHIFT,
                                         addr, next, write, pages, nr))
                                 return 0;
@@ -153,7 +161,11 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write,
                 next = pgd_addr_end(addr, end);
                 if (pgd_none(pgd))
                         goto slow;
-                if (is_hugepd(pgdp)) {
+                if (pgd_huge(pgd)) {
+                        if (!gup_hugepte((pte_t *)pgdp, PGDIR_SIZE, addr, next,
+                                         write, pages, &nr))
+                                goto slow;
+                } else if (is_hugepd(pgdp)) {
                         if (!gup_hugepd((hugepd_t *)pgdp, PGDIR_SHIFT,
                                         addr, next, write, pages, &nr))
                                 goto slow;
diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S
index 7443481a315c..0e980acae67c 100644
--- a/arch/powerpc/mm/hash_low_64.S
+++ b/arch/powerpc/mm/hash_low_64.S
@@ -196,7 +196,8 @@ htab_insert_pte:
         mr      r4,r29                  /* Retrieve vpn */
         li      r7,0                    /* !bolted, !secondary */
         li      r8,MMU_PAGE_4K          /* page size */
-        ld      r9,STK_PARAM(R9)(r1)    /* segment size */
+        li      r9,MMU_PAGE_4K          /* actual page size */
+        ld      r10,STK_PARAM(R9)(r1)   /* segment size */
 _GLOBAL(htab_call_hpte_insert1)
         bl      .                       /* Patched by htab_finish_init() */
         cmpdi   0,r3,0
@@ -219,7 +220,8 @@ _GLOBAL(htab_call_hpte_insert1)
         mr      r4,r29                  /* Retrieve vpn */
         li      r7,HPTE_V_SECONDARY     /* !bolted, secondary */
         li      r8,MMU_PAGE_4K          /* page size */
-        ld      r9,STK_PARAM(R9)(r1)    /* segment size */
+        li      r9,MMU_PAGE_4K          /* actual page size */
+        ld      r10,STK_PARAM(R9)(r1)   /* segment size */
 _GLOBAL(htab_call_hpte_insert2)
         bl      .                       /* Patched by htab_finish_init() */
         cmpdi   0,r3,0
@@ -490,7 +492,7 @@ END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
         beq     htab_inval_old_hpte
 
         ld      r6,STK_PARAM(R6)(r1)
-        ori     r26,r6,0x8000           /* Load the hidx mask */
+        ori     r26,r6,PTE_PAGE_HIDX_OFFSET /* Load the hidx mask. */
         ld      r26,0(r26)
         addi    r5,r25,36               /* Check actual HPTE_SUB bit, this */
         rldcr.  r0,r31,r5,0             /* must match pgtable.h definition */
@@ -515,7 +517,8 @@ htab_special_pfn:
         mr      r4,r29                  /* Retrieve vpn */
         li      r7,0                    /* !bolted, !secondary */
         li      r8,MMU_PAGE_4K          /* page size */
-        ld      r9,STK_PARAM(R9)(r1)    /* segment size */
+        li      r9,MMU_PAGE_4K          /* actual page size */
+        ld      r10,STK_PARAM(R9)(r1)   /* segment size */
 _GLOBAL(htab_call_hpte_insert1)
         bl      .                       /* patched by htab_finish_init() */
         cmpdi   0,r3,0
@@ -542,7 +545,8 @@ _GLOBAL(htab_call_hpte_insert1)
         mr      r4,r29                  /* Retrieve vpn */
         li      r7,HPTE_V_SECONDARY     /* !bolted, secondary */
         li      r8,MMU_PAGE_4K          /* page size */
-        ld      r9,STK_PARAM(R9)(r1)    /* segment size */
+        li      r9,MMU_PAGE_4K          /* actual page size */
+        ld      r10,STK_PARAM(R9)(r1)   /* segment size */
 _GLOBAL(htab_call_hpte_insert2)
         bl      .                       /* patched by htab_finish_init() */
         cmpdi   0,r3,0
@@ -607,7 +611,7 @@ htab_pte_insert_ok:
         sld     r4,r4,r5
         andc    r26,r26,r4
         or      r26,r26,r3
-        ori     r5,r6,0x8000
+        ori     r5,r6,PTE_PAGE_HIDX_OFFSET
         std     r26,0(r5)
         lwsync
         std     r30,0(r6)
@@ -840,7 +844,8 @@ ht64_insert_pte:
         mr      r4,r29                  /* Retrieve vpn */
         li      r7,0                    /* !bolted, !secondary */
         li      r8,MMU_PAGE_64K
-        ld      r9,STK_PARAM(R9)(r1)    /* segment size */
+        li      r9,MMU_PAGE_64K         /* actual page size */
+        ld      r10,STK_PARAM(R9)(r1)   /* segment size */
 _GLOBAL(ht64_call_hpte_insert1)
         bl      .                       /* patched by htab_finish_init() */
         cmpdi   0,r3,0
@@ -863,7 +868,8 @@ _GLOBAL(ht64_call_hpte_insert1)
         mr      r4,r29                  /* Retrieve vpn */
         li      r7,HPTE_V_SECONDARY     /* !bolted, secondary */
         li      r8,MMU_PAGE_64K
-        ld      r9,STK_PARAM(R9)(r1)    /* segment size */
+        li      r9,MMU_PAGE_64K         /* actual page size */
+        ld      r10,STK_PARAM(R9)(r1)   /* segment size */
 _GLOBAL(ht64_call_hpte_insert2)
         bl      .                       /* patched by htab_finish_init() */
         cmpdi   0,r3,0
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index ffc1e00f7a22..6a2aead5b0e5 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -39,7 +39,7 @@
 
 DEFINE_RAW_SPINLOCK(native_tlbie_lock);
 
-static inline void __tlbie(unsigned long vpn, int psize, int ssize)
+static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
 {
         unsigned long va;
         unsigned int penc;
@@ -61,17 +61,31 @@ static inline void __tlbie(unsigned long vpn, int psize, int ssize)
 
         switch (psize) {
         case MMU_PAGE_4K:
+                /* clear out bits after (52) [0....52.....63] */
+                va &= ~((1ul << (64 - 52)) - 1);
                 va |= ssize << 8;
+                va |= mmu_psize_defs[apsize].sllp << 6;
                 asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
                              : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
                              : "memory");
                 break;
         default:
                 /* We need 14 to 14 + i bits of va */
-                penc = mmu_psize_defs[psize].penc;
-                va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
+                penc = mmu_psize_defs[psize].penc[apsize];
+                va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
                 va |= penc << 12;
                 va |= ssize << 8;
+                /* Add AVAL part */
+                if (psize != apsize) {
+                        /*
+                         * MPSS, 64K base page size and 16MB parge page size
+                         * We don't need all the bits, but rest of the bits
+                         * must be ignored by the processor.
+                         * vpn cover upto 65 bits of va. (0...65) and we need
+                         * 58..64 bits of va.
+                         */
+                        va |= (vpn & 0xfe);
+                }
                 va |= 1; /* L */
                 asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
                              : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
@@ -80,7 +94,7 @@ static inline void __tlbie(unsigned long vpn, int psize, int ssize)
         }
 }
 
-static inline void __tlbiel(unsigned long vpn, int psize, int ssize)
+static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
 {
         unsigned long va;
         unsigned int penc;
@@ -96,16 +110,30 @@ static inline void __tlbiel(unsigned long vpn, int psize, int ssize)
 
         switch (psize) {
         case MMU_PAGE_4K:
+                /* clear out bits after(52) [0....52.....63] */
+                va &= ~((1ul << (64 - 52)) - 1);
                 va |= ssize << 8;
+                va |= mmu_psize_defs[apsize].sllp << 6;
                 asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)"
                              : : "r"(va) : "memory");
                 break;
         default:
                 /* We need 14 to 14 + i bits of va */
-                penc = mmu_psize_defs[psize].penc;
-                va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
+                penc = mmu_psize_defs[psize].penc[apsize];
+                va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
                 va |= penc << 12;
                 va |= ssize << 8;
+                /* Add AVAL part */
+                if (psize != apsize) {
+                        /*
+                         * MPSS, 64K base page size and 16MB parge page size
+                         * We don't need all the bits, but rest of the bits
+                         * must be ignored by the processor.
+                         * vpn cover upto 65 bits of va. (0...65) and we need
+                         * 58..64 bits of va.
+                         */
+                        va |= (vpn & 0xfe);
+                }
                 va |= 1; /* L */
                 asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
                              : : "r"(va) : "memory");
@@ -114,7 +142,8 @@ static inline void __tlbiel(unsigned long vpn, int psize, int ssize)
 
 }
 
-static inline void tlbie(unsigned long vpn, int psize, int ssize, int local)
+static inline void tlbie(unsigned long vpn, int psize, int apsize,
+                         int ssize, int local)
 {
         unsigned int use_local = local && mmu_has_feature(MMU_FTR_TLBIEL);
         int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
@@ -125,10 +154,10 @@ static inline void tlbie(unsigned long vpn, int psize, int ssize, int local)
                 raw_spin_lock(&native_tlbie_lock);
         asm volatile("ptesync": : :"memory");
         if (use_local) {
-                __tlbiel(vpn, psize, ssize);
+                __tlbiel(vpn, psize, apsize, ssize);
                 asm volatile("ptesync": : :"memory");
         } else {
-                __tlbie(vpn, psize, ssize);
+                __tlbie(vpn, psize, apsize, ssize);
                 asm volatile("eieio; tlbsync; ptesync": : :"memory");
         }
         if (lock_tlbie && !use_local)
@@ -156,7 +185,7 @@ static inline void native_unlock_hpte(struct hash_pte *hptep)
 
 static long native_hpte_insert(unsigned long hpte_group, unsigned long vpn,
                         unsigned long pa, unsigned long rflags,
-                        unsigned long vflags, int psize, int ssize)
+                        unsigned long vflags, int psize, int apsize, int ssize)
 {
         struct hash_pte *hptep = htab_address + hpte_group;
         unsigned long hpte_v, hpte_r;
@@ -183,8 +212,8 @@ static long native_hpte_insert(unsigned long hpte_group, unsigned long vpn,
         if (i == HPTES_PER_GROUP)
                 return -1;
 
-        hpte_v = hpte_encode_v(vpn, psize, ssize) | vflags | HPTE_V_VALID;
-        hpte_r = hpte_encode_r(pa, psize) | rflags;
+        hpte_v = hpte_encode_v(vpn, psize, apsize, ssize) | vflags | HPTE_V_VALID;
+        hpte_r = hpte_encode_r(pa, psize, apsize) | rflags;
 
         if (!(vflags & HPTE_V_BOLTED)) {
                 DBG_LOW(" i=%x hpte_v=%016lx, hpte_r=%016lx\n",
@@ -244,6 +273,51 @@ static long native_hpte_remove(unsigned long hpte_group)
         return i;
 }
 
+static inline int __hpte_actual_psize(unsigned int lp, int psize)
+{
+        int i, shift;
+        unsigned int mask;
+
+        /* start from 1 ignoring MMU_PAGE_4K */
+        for (i = 1; i < MMU_PAGE_COUNT; i++) {
+
+                /* invalid penc */
+                if (mmu_psize_defs[psize].penc[i] == -1)
+                        continue;
+                /*
+                 * encoding bits per actual page size
+                 *        PTE LP     actual page size
+                 *    rrrr rrrz         >=8KB
+                 *    rrrr rrzz         >=16KB
+                 *    rrrr rzzz         >=32KB
+                 *    rrrr zzzz         >=64KB
+                 * .......
+                 */
+                shift = mmu_psize_defs[i].shift - LP_SHIFT;
+                if (shift > LP_BITS)
+                        shift = LP_BITS;
+                mask = (1 << shift) - 1;
+                if ((lp & mask) == mmu_psize_defs[psize].penc[i])
+                        return i;
+        }
+        return -1;
+}
+
+static inline int hpte_actual_psize(struct hash_pte *hptep, int psize)
+{
+        /* Look at the 8 bit LP value */
+        unsigned int lp = (hptep->r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
+
+        if (!(hptep->v & HPTE_V_VALID))
+                return -1;
+
+        /* First check if it is large page */
+        if (!(hptep->v & HPTE_V_LARGE))
+                return MMU_PAGE_4K;
+
+        return __hpte_actual_psize(lp, psize);
+}
+
 static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
                                  unsigned long vpn, int psize, int ssize,
                                  int local)
@@ -251,8 +325,9 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
         struct hash_pte *hptep = htab_address + slot;
         unsigned long hpte_v, want_v;
         int ret = 0;
+        int actual_psize;
 
-        want_v = hpte_encode_v(vpn, psize, ssize);
+        want_v = hpte_encode_avpn(vpn, psize, ssize);
 
         DBG_LOW("    update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)",
                 vpn, want_v & HPTE_V_AVPN, slot, newpp);
@@ -260,9 +335,13 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
         native_lock_hpte(hptep);
 
         hpte_v = hptep->v;
-
+        actual_psize = hpte_actual_psize(hptep, psize);
+        if (actual_psize < 0) {
+                native_unlock_hpte(hptep);
+                return -1;
+        }
         /* Even if we miss, we need to invalidate the TLB */
-        if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) {
+        if (!HPTE_V_COMPARE(hpte_v, want_v)) {
                 DBG_LOW(" -> miss\n");
                 ret = -1;
         } else {
@@ -274,7 +353,7 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
         native_unlock_hpte(hptep);
 
         /* Ensure it is out of the tlb too. */
-        tlbie(vpn, psize, ssize, local);
+        tlbie(vpn, psize, actual_psize, ssize, local);
 
         return ret;
 }
@@ -288,7 +367,7 @@ static long native_hpte_find(unsigned long vpn, int psize, int ssize)
         unsigned long want_v, hpte_v;
 
         hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, ssize);
-        want_v = hpte_encode_v(vpn, psize, ssize);
+        want_v = hpte_encode_avpn(vpn, psize, ssize);
 
         /* Bolted mappings are only ever in the primary group */
         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
@@ -315,6 +394,7 @@ static long native_hpte_find(unsigned long vpn, int psize, int ssize)
 static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
                                        int psize, int ssize)
 {
+        int actual_psize;
         unsigned long vpn;
         unsigned long vsid;
         long slot;
@@ -327,13 +407,16 @@ static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
         if (slot == -1)
                 panic("could not find page to bolt\n");
         hptep = htab_address + slot;
+        actual_psize = hpte_actual_psize(hptep, psize);
+        if (actual_psize < 0)
+                return;
 
         /* Update the HPTE */
         hptep->r = (hptep->r & ~(HPTE_R_PP | HPTE_R_N)) |
                 (newpp & (HPTE_R_PP | HPTE_R_N));
 
         /* Ensure it is out of the tlb too. */
-        tlbie(vpn, psize, ssize, 0);
+        tlbie(vpn, psize, actual_psize, ssize, 0);
 }
 
 static void native_hpte_invalidate(unsigned long slot, unsigned long vpn,
@@ -343,64 +426,60 @@ static void native_hpte_invalidate(unsigned long slot, unsigned long vpn,
         unsigned long hpte_v;
         unsigned long want_v;
         unsigned long flags;
+        int actual_psize;
 
         local_irq_save(flags);
 
         DBG_LOW("    invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot);
 
-        want_v = hpte_encode_v(vpn, psize, ssize);
+        want_v = hpte_encode_avpn(vpn, psize, ssize);
         native_lock_hpte(hptep);
         hpte_v = hptep->v;
 
+        actual_psize = hpte_actual_psize(hptep, psize);
+        if (actual_psize < 0) {
+                native_unlock_hpte(hptep);
+                local_irq_restore(flags);
+                return;
+        }
         /* Even if we miss, we need to invalidate the TLB */
-        if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
+        if (!HPTE_V_COMPARE(hpte_v, want_v))
                 native_unlock_hpte(hptep);
         else
                 /* Invalidate the hpte. NOTE: this also unlocks it */
                 hptep->v = 0;
 
         /* Invalidate the TLB */
-        tlbie(vpn, psize, ssize, local);
+        tlbie(vpn, psize, actual_psize, ssize, local);
 
         local_irq_restore(flags);
 }
 
-#define LP_SHIFT        12
-#define LP_BITS         8
-#define LP_MASK(i)      ((0xFF >> (i)) << LP_SHIFT)
-
 static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
-                        int *psize, int *ssize, unsigned long *vpn)
+                        int *psize, int *apsize, int *ssize, unsigned long *vpn)
 {
         unsigned long avpn, pteg, vpi;
-        unsigned long hpte_r = hpte->r;
         unsigned long hpte_v = hpte->v;
         unsigned long vsid, seg_off;
-        int i, size, shift, penc;
+        int size, a_size, shift;
+        /* Look at the 8 bit LP value */
+        unsigned int lp = (hpte->r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
 
-        if (!(hpte_v & HPTE_V_LARGE))
-                size = MMU_PAGE_4K;
-        else {
-                for (i = 0; i < LP_BITS; i++) {
-                        if ((hpte_r & LP_MASK(i+1)) == LP_MASK(i+1))
-                                break;
-                }
-                penc = LP_MASK(i+1) >> LP_SHIFT;
+        if (!(hpte_v & HPTE_V_LARGE)) {
+                size   = MMU_PAGE_4K;
+                a_size = MMU_PAGE_4K;
+        } else {
                 for (size = 0; size < MMU_PAGE_COUNT; size++) {
 
-                        /* 4K pages are not represented by LP */
-                        if (size == MMU_PAGE_4K)
-                                continue;
-
                         /* valid entries have a shift value */
                         if (!mmu_psize_defs[size].shift)
                                 continue;
 
-                        if (penc == mmu_psize_defs[size].penc)
+                        a_size = __hpte_actual_psize(lp, size);
+                        if (a_size != -1)
                                 break;
                 }
         }
-
         /* This works for all page sizes, and for 256M and 1T segments */
         *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT;
         shift = mmu_psize_defs[size].shift;
@@ -433,7 +512,8 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
         default:
                 *vpn = size = 0;
         }
-        *psize = size;
+        *psize  = size;
+        *apsize = a_size;
 }
 
 /*
@@ -451,7 +531,7 @@ static void native_hpte_clear(void)
         struct hash_pte *hptep = htab_address;
         unsigned long hpte_v;
         unsigned long pteg_count;
-        int psize, ssize;
+        int psize, apsize, ssize;
 
         pteg_count = htab_hash_mask + 1;
 
@@ -477,9 +557,9 @@ static void native_hpte_clear(void)
                  * already hold the native_tlbie_lock.
                  */
                 if (hpte_v & HPTE_V_VALID) {
-                        hpte_decode(hptep, slot, &psize, &ssize, &vpn);
+                        hpte_decode(hptep, slot, &psize, &apsize, &ssize, &vpn);
                         hptep->v = 0;
-                        __tlbie(vpn, psize, ssize);
+                        __tlbie(vpn, psize, apsize, ssize);
                 }
         }
 
@@ -520,7 +600,7 @@ static void native_flush_hash_range(unsigned long number, int local)
                         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
                         slot += hidx & _PTEIDX_GROUP_IX;
                         hptep = htab_address + slot;
-                        want_v = hpte_encode_v(vpn, psize, ssize);
+                        want_v = hpte_encode_avpn(vpn, psize, ssize);
                         native_lock_hpte(hptep);
                         hpte_v = hptep->v;
                         if (!HPTE_V_COMPARE(hpte_v, want_v) ||
@@ -540,7 +620,7 @@ static void native_flush_hash_range(unsigned long number, int local)
 
                         pte_iterate_hashed_subpages(pte, psize,
                                                     vpn, index, shift) {
-                                __tlbiel(vpn, psize, ssize);
+                                __tlbiel(vpn, psize, psize, ssize);
                         } pte_iterate_hashed_end();
                 }
                 asm volatile("ptesync":::"memory");
@@ -557,7 +637,7 @@ static void native_flush_hash_range(unsigned long number, int local)
 
                         pte_iterate_hashed_subpages(pte, psize,
                                                     vpn, index, shift) {
-                                __tlbie(vpn, psize, ssize);
+                                __tlbie(vpn, psize, psize, ssize);
                         } pte_iterate_hashed_end();
                 }
                 asm volatile("eieio; tlbsync; ptesync":::"memory");
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index f410c3e12c1e..88ac0eeaadde 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -126,7 +126,7 @@ static struct mmu_psize_def mmu_psize_defaults_old[] = {
         [MMU_PAGE_4K] = {
                 .shift  = 12,
                 .sllp   = 0,
-                .penc   = 0,
+                .penc   = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
                 .avpnm  = 0,
                 .tlbiel = 0,
         },
@@ -140,14 +140,15 @@ static struct mmu_psize_def mmu_psize_defaults_gp[] = {
         [MMU_PAGE_4K] = {
                 .shift  = 12,
                 .sllp   = 0,
-                .penc   = 0,
+                .penc   = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
                 .avpnm  = 0,
                 .tlbiel = 1,
         },
         [MMU_PAGE_16M] = {
                 .shift  = 24,
                 .sllp   = SLB_VSID_L,
-                .penc   = 0,
+                .penc   = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
+                            [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
                 .avpnm  = 0x1UL,
                 .tlbiel = 0,
         },
@@ -209,7 +210,7 @@ int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
 
                 BUG_ON(!ppc_md.hpte_insert);
                 ret = ppc_md.hpte_insert(hpteg, vpn, paddr, tprot,
-                                         HPTE_V_BOLTED, psize, ssize);
+                                         HPTE_V_BOLTED, psize, psize, ssize);
 
                 if (ret < 0)
                         break;
@@ -276,6 +277,30 @@ static void __init htab_init_seg_sizes(void)
         of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
 }
 
+static int __init get_idx_from_shift(unsigned int shift)
+{
+        int idx = -1;
+
+        switch (shift) {
+        case 0xc:
+                idx = MMU_PAGE_4K;
+                break;
+        case 0x10:
+                idx = MMU_PAGE_64K;
+                break;
+        case 0x14:
+                idx = MMU_PAGE_1M;
+                break;
+        case 0x18:
+                idx = MMU_PAGE_16M;
+                break;
+        case 0x22:
+                idx = MMU_PAGE_16G;
+                break;
+        }
+        return idx;
+}
+
 static int __init htab_dt_scan_page_sizes(unsigned long node,
                                           const char *uname, int depth,
                                           void *data)
@@ -291,64 +316,65 @@ static int __init htab_dt_scan_page_sizes(unsigned long node,
         prop = (u32 *)of_get_flat_dt_prop(node,
                                           "ibm,segment-page-sizes", &size);
         if (prop != NULL) {
-                DBG("Page sizes from device-tree:\n");
+                pr_info("Page sizes from device-tree:\n");
                 size /= 4;
                 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
                 while(size > 0) {
-                        unsigned int shift = prop[0];
+                        unsigned int base_shift = prop[0];
                         unsigned int slbenc = prop[1];
                         unsigned int lpnum = prop[2];
-                        unsigned int lpenc = 0;
                         struct mmu_psize_def *def;
-                        int idx = -1;
+                        int idx, base_idx;
 
                         size -= 3; prop += 3;
-                        while(size > 0 && lpnum) {
-                                if (prop[0] == shift)
-                                        lpenc = prop[1];
-                                prop += 2; size -= 2;
-                                lpnum--;
+                        base_idx = get_idx_from_shift(base_shift);
+                        if (base_idx < 0) {
+                                /*
+                                 * skip the pte encoding also
+                                 */
+                                prop += lpnum * 2; size -= lpnum * 2;
+                                continue;
                         }
-                        switch(shift) {
-                        case 0xc:
-                                idx = MMU_PAGE_4K;
-                                break;
-                        case 0x10:
-                                idx = MMU_PAGE_64K;
-                                break;
-                        case 0x14:
-                                idx = MMU_PAGE_1M;
-                                break;
-                        case 0x18:
-                                idx = MMU_PAGE_16M;
+                        def = &mmu_psize_defs[base_idx];
+                        if (base_idx == MMU_PAGE_16M)
                                 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
-                                break;
-                        case 0x22:
-                                idx = MMU_PAGE_16G;
-                                break;
-                        }
-                        if (idx < 0)
-                                continue;
-                        def = &mmu_psize_defs[idx];
-                        def->shift = shift;
-                        if (shift <= 23)
+
+                        def->shift = base_shift;
+                        if (base_shift <= 23)
                                 def->avpnm = 0;
                         else
-                                def->avpnm = (1 << (shift - 23)) - 1;
+                                def->avpnm = (1 << (base_shift - 23)) - 1;
                         def->sllp = slbenc;
-                        def->penc = lpenc;
-                        /* We don't know for sure what's up with tlbiel, so
+                        /*
+                         * We don't know for sure what's up with tlbiel, so
                          * for now we only set it for 4K and 64K pages
                          */
-                        if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
+                        if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
                                 def->tlbiel = 1;
                         else
                                 def->tlbiel = 0;
 
-                        DBG(" %d: shift=%02x, sllp=%04lx, avpnm=%08lx, "
-                            "tlbiel=%d, penc=%d\n",
-                            idx, shift, def->sllp, def->avpnm, def->tlbiel,
-                            def->penc);
+                        while (size > 0 && lpnum) {
+                                unsigned int shift = prop[0];
+                                int penc  = prop[1];
+
+                                prop += 2; size -= 2;
+                                lpnum--;
+
+                                idx = get_idx_from_shift(shift);
+                                if (idx < 0)
+                                        continue;
+
+                                if (penc == -1)
+                                        pr_err("Invalid penc for base_shift=%d "
+                                               "shift=%d\n", base_shift, shift);
+
+                                def->penc[idx] = penc;
+                                pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
+                                        " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
+                                        base_shift, shift, def->sllp,
+                                        def->avpnm, def->tlbiel, def->penc[idx]);
+                        }
                 }
                 return 1;
         }
@@ -397,10 +423,21 @@ static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
 }
 #endif /* CONFIG_HUGETLB_PAGE */
 
+static void mmu_psize_set_default_penc(void)
+{
+        int bpsize, apsize;
+        for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
+                for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
+                        mmu_psize_defs[bpsize].penc[apsize] = -1;
+}
+
 static void __init htab_init_page_sizes(void)
 {
         int rc;
 
+        /* se the invalid penc to -1 */
+        mmu_psize_set_default_penc();
+
         /* Default to 4K pages only */
         memcpy(mmu_psize_defs, mmu_psize_defaults_old,
                sizeof(mmu_psize_defaults_old));
@@ -899,14 +936,14 @@ static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
 
 void hash_failure_debug(unsigned long ea, unsigned long access,
                         unsigned long vsid, unsigned long trap,
-                        int ssize, int psize, unsigned long pte)
+                        int ssize, int psize, int lpsize, unsigned long pte)
 {
         if (!printk_ratelimit())
                 return;
         pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
                 ea, access, current->comm);
-        pr_info("    trap=0x%lx vsid=0x%lx ssize=%d psize=%d pte=0x%lx\n",
-                trap, vsid, ssize, psize, pte);
+        pr_info("    trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
+                trap, vsid, ssize, psize, lpsize, pte);
 }
 
 /* Result code is:
@@ -1079,7 +1116,7 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
          */
         if (rc == -1)
                 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
-                                   pte_val(*ptep));
+                                   psize, pte_val(*ptep));
 #ifndef CONFIG_PPC_64K_PAGES
         DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
 #else
@@ -1157,7 +1194,9 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
          */
         if (rc == -1)
                 hash_failure_debug(ea, access, vsid, trap, ssize,
-                                   mm->context.user_psize, pte_val(*ptep));
+                                   mm->context.user_psize,
+                                   mm->context.user_psize,
+                                   pte_val(*ptep));
 
         local_irq_restore(flags);
 }
@@ -1191,6 +1230,7 @@ void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
          * unmapping it first, it may see the speculated version.
          */
         if (local && cpu_has_feature(CPU_FTR_TM) &&
+            current->thread.regs &&
             MSR_TM_ACTIVE(current->thread.regs->msr)) {
                 tm_enable();
                 tm_abort(TM_CAUSE_TLBI);
@@ -1230,24 +1270,60 @@ void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
                 bad_page_fault(regs, address, SIGBUS);
 }
 
+long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
+                           unsigned long pa, unsigned long rflags,
+                           unsigned long vflags, int psize, int ssize)
+{
+        unsigned long hpte_group;
+        long slot;
+
+repeat:
+        hpte_group = ((hash & htab_hash_mask) *
+                       HPTES_PER_GROUP) & ~0x7UL;
+
+        /* Insert into the hash table, primary slot */
+        slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
+                                  psize, psize, ssize);
+
+        /* Primary is full, try the secondary */
+        if (unlikely(slot == -1)) {
+                hpte_group = ((~hash & htab_hash_mask) *
+                              HPTES_PER_GROUP) & ~0x7UL;
+                slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags,
+                                          vflags | HPTE_V_SECONDARY,
+                                          psize, psize, ssize);
+                if (slot == -1) {
+                        if (mftb() & 0x1)
+                                hpte_group = ((hash & htab_hash_mask) *
+                                              HPTES_PER_GROUP)&~0x7UL;
+
+                        ppc_md.hpte_remove(hpte_group);
+                        goto repeat;
+                }
+        }
+
+        return slot;
+}
+
 #ifdef CONFIG_DEBUG_PAGEALLOC
 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
 {
-        unsigned long hash, hpteg;
+        unsigned long hash;
         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
         unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
         unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
-        int ret;
+        long ret;
 
         hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
-        hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
 
         /* Don't create HPTE entries for bad address */
         if (!vsid)
                 return;
-        ret = ppc_md.hpte_insert(hpteg, vpn, __pa(vaddr),
-                                 mode, HPTE_V_BOLTED,
-                                 mmu_linear_psize, mmu_kernel_ssize);
+
+        ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
+                                    HPTE_V_BOLTED,
+                                    mmu_linear_psize, mmu_kernel_ssize);
+
         BUG_ON (ret < 0);
         spin_lock(&linear_map_hash_lock);
         BUG_ON(linear_map_hash_slots[lmi] & 0x80);
diff --git a/arch/powerpc/mm/hugetlbpage-hash64.c b/arch/powerpc/mm/hugetlbpage-hash64.c
index cecad348f604..0f1d94a1fb82 100644
--- a/arch/powerpc/mm/hugetlbpage-hash64.c
+++ b/arch/powerpc/mm/hugetlbpage-hash64.c
@@ -14,6 +14,10 @@
 #include <asm/cacheflush.h>
 #include <asm/machdep.h>
 
+extern long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
+                                  unsigned long pa, unsigned long rlags,
+                                  unsigned long vflags, int psize, int ssize);
+
 int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
                      pte_t *ptep, unsigned long trap, int local, int ssize,
                      unsigned int shift, unsigned int mmu_psize)
@@ -83,14 +87,9 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
 
         if (likely(!(old_pte & _PAGE_HASHPTE))) {
                 unsigned long hash = hpt_hash(vpn, shift, ssize);
-                unsigned long hpte_group;
 
                 pa = pte_pfn(__pte(old_pte)) << PAGE_SHIFT;
 
-repeat:
-                hpte_group = ((hash & htab_hash_mask) *
-                              HPTES_PER_GROUP) & ~0x7UL;
-
                 /* clear HPTE slot informations in new PTE */
 #ifdef CONFIG_PPC_64K_PAGES
                 new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | _PAGE_HPTE_SUB0;
@@ -101,26 +100,8 @@ repeat:
                 rflags |= (new_pte & (_PAGE_WRITETHRU | _PAGE_NO_CACHE |
                                       _PAGE_COHERENT | _PAGE_GUARDED));
 
-                /* Insert into the hash table, primary slot */
-                slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, 0,
-                                          mmu_psize, ssize);
-
-                /* Primary is full, try the secondary */
-                if (unlikely(slot == -1)) {
-                        hpte_group = ((~hash & htab_hash_mask) *
-                                      HPTES_PER_GROUP) & ~0x7UL;
-                        slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags,
-                                                  HPTE_V_SECONDARY,
-                                                  mmu_psize, ssize);
-                        if (slot == -1) {
-                                if (mftb() & 0x1)
-                                        hpte_group = ((hash & htab_hash_mask) *
-                                                      HPTES_PER_GROUP)&~0x7UL;
-
-                                ppc_md.hpte_remove(hpte_group);
-                                goto repeat;
-                        }
-                }
+                slot = hpte_insert_repeating(hash, vpn, pa, rflags, 0,
+                                             mmu_psize, ssize);
 
                 /*
                  * Hypervisor failure. Restore old pte and return -1
@@ -129,7 +110,7 @@ repeat:
                 if (unlikely(slot == -2)) {
                         *ptep = __pte(old_pte);
                         hash_failure_debug(ea, access, vsid, trap, ssize,
-                                           mmu_psize, old_pte);
+                                           mmu_psize, mmu_psize, old_pte);
                         return -1;
                 }
 
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 1a6de0a7d8eb..237c8e5f2640 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -48,30 +48,71 @@ static u64 gpage_freearray[MAX_NUMBER_GPAGES];
 static unsigned nr_gpages;
 #endif
 
-static inline int shift_to_mmu_psize(unsigned int shift)
+#define hugepd_none(hpd)        ((hpd).pd == 0)
+
+#ifdef CONFIG_PPC_BOOK3S_64
+/*
+ * At this point we do the placement change only for BOOK3S 64. This would
+ * possibly work on other subarchs.
+ */
+
+/*
+ * We have PGD_INDEX_SIZ = 12 and PTE_INDEX_SIZE = 8, so that we can have
+ * 16GB hugepage pte in PGD and 16MB hugepage pte at PMD;
+ */
+int pmd_huge(pmd_t pmd)
 {
-        int psize;
+        /*
+         * leaf pte for huge page, bottom two bits != 00
+         */
+        return ((pmd_val(pmd) & 0x3) != 0x0);
+}
 
-        for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
-                if (mmu_psize_defs[psize].shift == shift)
-                        return psize;
-        return -1;
+int pud_huge(pud_t pud)
+{
+        /*
+         * leaf pte for huge page, bottom two bits != 00
+         */
+        return ((pud_val(pud) & 0x3) != 0x0);
 }
 
-static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
+int pgd_huge(pgd_t pgd)
 {
-        if (mmu_psize_defs[mmu_psize].shift)
-                return mmu_psize_defs[mmu_psize].shift;
-        BUG();
+        /*
+         * leaf pte for huge page, bottom two bits != 00
+         */
+        return ((pgd_val(pgd) & 0x3) != 0x0);
+}
+#else
+int pmd_huge(pmd_t pmd)
+{
+        return 0;
 }
 
-#define hugepd_none(hpd)        ((hpd).pd == 0)
+int pud_huge(pud_t pud)
+{
+        return 0;
+}
+
+int pgd_huge(pgd_t pgd)
+{
+        return 0;
+}
+#endif
 
+/*
+ * We have 4 cases for pgds and pmds:
+ * (1) invalid (all zeroes)
+ * (2) pointer to next table, as normal; bottom 6 bits == 0
+ * (3) leaf pte for huge page, bottom two bits != 00
+ * (4) hugepd pointer, bottom two bits == 00, next 4 bits indicate size of table
+ */
 pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea, unsigned *shift)
 {
         pgd_t *pg;
         pud_t *pu;
         pmd_t *pm;
+        pte_t *ret_pte;
         hugepd_t *hpdp = NULL;
         unsigned pdshift = PGDIR_SHIFT;
 
@@ -79,30 +120,43 @@ pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea, unsigned *shift
                 *shift = 0;
 
         pg = pgdir + pgd_index(ea);
-        if (is_hugepd(pg)) {
+
+        if (pgd_huge(*pg)) {
+                ret_pte = (pte_t *) pg;
+                goto out;
+        } else if (is_hugepd(pg))
                 hpdp = (hugepd_t *)pg;
-        } else if (!pgd_none(*pg)) {
+        else if (!pgd_none(*pg)) {
                 pdshift = PUD_SHIFT;
                 pu = pud_offset(pg, ea);
-                if (is_hugepd(pu))
+
+                if (pud_huge(*pu)) {
+                        ret_pte = (pte_t *) pu;
+                        goto out;
+                } else if (is_hugepd(pu))
                         hpdp = (hugepd_t *)pu;
                 else if (!pud_none(*pu)) {
                         pdshift = PMD_SHIFT;
                         pm = pmd_offset(pu, ea);
-                        if (is_hugepd(pm))
+
+                        if (pmd_huge(*pm)) {
+                                ret_pte = (pte_t *) pm;
+                                goto out;
+                        } else if (is_hugepd(pm))
                                 hpdp = (hugepd_t *)pm;
-                        else if (!pmd_none(*pm)) {
+                        else if (!pmd_none(*pm))
                                 return pte_offset_kernel(pm, ea);
-                        }
                 }
         }
-
         if (!hpdp)
                 return NULL;
 
+        ret_pte = hugepte_offset(hpdp, ea, pdshift);
+        pdshift = hugepd_shift(*hpdp);
+out:
         if (shift)
-                *shift = hugepd_shift(*hpdp);
-        return hugepte_offset(hpdp, ea, pdshift);
+                *shift = pdshift;
+        return ret_pte;
 }
 EXPORT_SYMBOL_GPL(find_linux_pte_or_hugepte);
 
@@ -145,6 +199,7 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
                 if (unlikely(!hugepd_none(*hpdp)))
                         break;
                 else
+                        /* We use the old format for PPC_FSL_BOOK3E */
                         hpdp->pd = ((unsigned long)new & ~PD_HUGE) | pshift;
         }
         /* If we bailed from the for loop early, an error occurred, clean up */
@@ -156,9 +211,15 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
 #else
         if (!hugepd_none(*hpdp))
                 kmem_cache_free(cachep, new);
-        else
+        else {
+#ifdef CONFIG_PPC_BOOK3S_64
+                hpdp->pd = (unsigned long)new |
+                            (shift_to_mmu_psize(pshift) << 2);
+#else
                 hpdp->pd = ((unsigned long)new & ~PD_HUGE) | pshift;
 #endif
+        }
+#endif
         spin_unlock(&mm->page_table_lock);
         return 0;
 }
@@ -175,6 +236,61 @@ static int __hugepte_alloc(struct mm_struct *mm, hugepd_t *hpdp,
 #define HUGEPD_PUD_SHIFT PMD_SHIFT
 #endif
 
+#ifdef CONFIG_PPC_BOOK3S_64
+/*
+ * At this point we do the placement change only for BOOK3S 64. This would
+ * possibly work on other subarchs.
+ */
+pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz)
+{
+        pgd_t *pg;
+        pud_t *pu;
+        pmd_t *pm;
+        hugepd_t *hpdp = NULL;
+        unsigned pshift = __ffs(sz);
+        unsigned pdshift = PGDIR_SHIFT;
+
+        addr &= ~(sz-1);
+        pg = pgd_offset(mm, addr);
+
+        if (pshift == PGDIR_SHIFT)
+                /* 16GB huge page */
+                return (pte_t *) pg;
+        else if (pshift > PUD_SHIFT)
+                /*
+                 * We need to use hugepd table
+                 */
+                hpdp = (hugepd_t *)pg;
+        else {
+                pdshift = PUD_SHIFT;
+                pu = pud_alloc(mm, pg, addr);
+                if (pshift == PUD_SHIFT)
+                        return (pte_t *)pu;
+                else if (pshift > PMD_SHIFT)
+                        hpdp = (hugepd_t *)pu;
+                else {
+                        pdshift = PMD_SHIFT;
+                        pm = pmd_alloc(mm, pu, addr);
+                        if (pshift == PMD_SHIFT)
+                                /* 16MB hugepage */
+                                return (pte_t *)pm;
+                        else
+                                hpdp = (hugepd_t *)pm;
+                }
+        }
+        if (!hpdp)
+                return NULL;
+
+        BUG_ON(!hugepd_none(*hpdp) && !hugepd_ok(*hpdp));
+
+        if (hugepd_none(*hpdp) && __hugepte_alloc(mm, hpdp, addr, pdshift, pshift))
+                return NULL;
+
+        return hugepte_offset(hpdp, addr, pdshift);
+}
+
+#else
+
 pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz)
 {
         pgd_t *pg;
@@ -212,6 +328,7 @@ pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr, unsigned long sz
 
         return hugepte_offset(hpdp, addr, pdshift);
 }
+#endif
 
 #ifdef CONFIG_PPC_FSL_BOOK3E
 /* Build list of addresses of gigantic pages.  This function is used in early
@@ -475,7 +592,7 @@ static void hugetlb_free_pmd_range(struct mmu_gather *tlb, pud_t *pud,
         do {
                 pmd = pmd_offset(pud, addr);
                 next = pmd_addr_end(addr, end);
-                if (pmd_none(*pmd))
+                if (pmd_none_or_clear_bad(pmd))
                         continue;
 #ifdef CONFIG_PPC_FSL_BOOK3E
                 /*
@@ -628,16 +745,6 @@ follow_huge_addr(struct mm_struct *mm, unsigned long address, int write)
         return page;
 }
 
-int pmd_huge(pmd_t pmd)
-{
-        return 0;
-}
-
-int pud_huge(pud_t pud)
-{
-        return 0;
-}
-
 struct page *
 follow_huge_pmd(struct mm_struct *mm, unsigned long address,
                 pmd_t *pmd, int write)
@@ -646,8 +753,8 @@ follow_huge_pmd(struct mm_struct *mm, unsigned long address,
         return NULL;
 }
 
-static noinline int gup_hugepte(pte_t *ptep, unsigned long sz, unsigned long addr,
-                       unsigned long end, int write, struct page **pages, int *nr)
+int gup_hugepte(pte_t *ptep, unsigned long sz, unsigned long addr,
+                unsigned long end, int write, struct page **pages, int *nr)
 {
         unsigned long mask;
         unsigned long pte_end;
@@ -742,7 +849,7 @@ unsigned long hugetlb_get_unmapped_area(struct file *file, unsigned long addr,
         struct hstate *hstate = hstate_file(file);
         int mmu_psize = shift_to_mmu_psize(huge_page_shift(hstate));
 
-        return slice_get_unmapped_area(addr, len, flags, mmu_psize, 1, 0);
+        return slice_get_unmapped_area(addr, len, flags, mmu_psize, 1);
 }
 #endif
 
@@ -883,11 +990,16 @@ static int __init hugetlbpage_init(void)
                         pdshift = PUD_SHIFT;
                 else
                         pdshift = PGDIR_SHIFT;
-
-                pgtable_cache_add(pdshift - shift, NULL);
-                if (!PGT_CACHE(pdshift - shift))
-                        panic("hugetlbpage_init(): could not create "
-                              "pgtable cache for %d bit pagesize\n", shift);
+                /*
+                 * if we have pdshift and shift value same, we don't
+                 * use pgt cache for hugepd.
+                 */
+                if (pdshift != shift) {
+                        pgtable_cache_add(pdshift - shift, NULL);
+                        if (!PGT_CACHE(pdshift - shift))
+                                panic("hugetlbpage_init(): could not create "
+                                      "pgtable cache for %d bit pagesize\n", shift);
+                }
         }
 
         /* Set default large page size. Currently, we pick 16M or 1M
diff --git a/arch/powerpc/mm/icswx.c b/arch/powerpc/mm/icswx.c
index 8cdbd8634a58..915412e4d5ba 100644
--- a/arch/powerpc/mm/icswx.c
+++ b/arch/powerpc/mm/icswx.c
@@ -67,7 +67,7 @@
 
 void switch_cop(struct mm_struct *next)
 {
-#ifdef CONFIG_ICSWX_PID
+#ifdef CONFIG_PPC_ICSWX_PID
         mtspr(SPRN_PID, next->context.cop_pid);
 #endif
         mtspr(SPRN_ACOP, next->context.acop);
diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c
index 7e2246fb2f31..c2787bf779ca 100644
--- a/arch/powerpc/mm/init_64.c
+++ b/arch/powerpc/mm/init_64.c
@@ -129,8 +129,7 @@ void pgtable_cache_add(unsigned shift, void (*ctor)(void *))
         align = max_t(unsigned long, align, minalign);
         name = kasprintf(GFP_KERNEL, "pgtable-2^%d", shift);
         new = kmem_cache_create(name, table_size, align, 0, ctor);
-        PGT_CACHE(shift) = new;
-
+        pgtable_cache[shift - 1] = new;
         pr_debug("Allocated pgtable cache for order %d\n", shift);
 }
 
@@ -263,19 +262,14 @@ static __meminit void vmemmap_list_populate(unsigned long phys,
         vmemmap_list = vmem_back;
 }
 
-int __meminit vmemmap_populate(struct page *start_page,
-                               unsigned long nr_pages, int node)
+int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node)
 {
-        unsigned long start = (unsigned long)start_page;
-        unsigned long end = (unsigned long)(start_page + nr_pages);
         unsigned long page_size = 1 << mmu_psize_defs[mmu_vmemmap_psize].shift;
 
         /* Align to the page size of the linear mapping. */
         start = _ALIGN_DOWN(start, page_size);
 
-        pr_debug("vmemmap_populate page %p, %ld pages, node %d\n",
-                 start_page, nr_pages, node);
-        pr_debug(" -> map %lx..%lx\n", start, end);
+        pr_debug("vmemmap_populate %lx..%lx, node %d\n", start, end, node);
 
         for (; start < end; start += page_size) {
                 void *p;
@@ -298,7 +292,7 @@ int __meminit vmemmap_populate(struct page *start_page,
         return 0;
 }
 
-void vmemmap_free(struct page *memmap, unsigned long nr_pages)
+void vmemmap_free(unsigned long start, unsigned long end)
 {
 }
 
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index f1f7409a4183..0988a26e0413 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -66,10 +66,9 @@ unsigned long long memory_limit;
 
 #ifdef CONFIG_HIGHMEM
 pte_t *kmap_pte;
+EXPORT_SYMBOL(kmap_pte);
 pgprot_t kmap_prot;
-
 EXPORT_SYMBOL(kmap_prot);
-EXPORT_SYMBOL(kmap_pte);
 
 static inline pte_t *virt_to_kpte(unsigned long vaddr)
 {
@@ -352,13 +351,9 @@ void __init mem_init(void)
                         struct page *page = pfn_to_page(pfn);
                         if (memblock_is_reserved(paddr))
                                 continue;
-                        ClearPageReserved(page);
-                        init_page_count(page);
-                        __free_page(page);
-                        totalhigh_pages++;
+                        free_highmem_page(page);
                         reservedpages--;
                 }
-                totalram_pages += totalhigh_pages;
                 printk(KERN_DEBUG "High memory: %luk\n",
                        totalhigh_pages << (PAGE_SHIFT-10));
         }
@@ -405,39 +400,14 @@ void __init mem_init(void)
 
 void free_initmem(void)
 {
-        unsigned long addr;
-
         ppc_md.progress = ppc_printk_progress;
-
-        addr = (unsigned long)__init_begin;
-        for (; addr < (unsigned long)__init_end; addr += PAGE_SIZE) {
-                memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
-                ClearPageReserved(virt_to_page(addr));
-                init_page_count(virt_to_page(addr));
-                free_page(addr);
-                totalram_pages++;
-        }
-        pr_info("Freeing unused kernel memory: %luk freed\n",
-                ((unsigned long)__init_end -
-                (unsigned long)__init_begin) >> 10);
+        free_initmem_default(POISON_FREE_INITMEM);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-        if (start >= end)
-                return;
-
-        start = _ALIGN_DOWN(start, PAGE_SIZE);
-        end = _ALIGN_UP(end, PAGE_SIZE);
-        pr_info("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
-
-        for (; start < end; start += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(start));
-                init_page_count(virt_to_page(start));
-                free_page(start);
-                totalram_pages++;
-        }
+        free_reserved_area(start, end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/powerpc/mm/mmu_context_hash64.c b/arch/powerpc/mm/mmu_context_hash64.c
index d1d1b92c5b99..178876aef40f 100644
--- a/arch/powerpc/mm/mmu_context_hash64.c
+++ b/arch/powerpc/mm/mmu_context_hash64.c
@@ -23,6 +23,7 @@
 #include <linux/slab.h>
 
 #include <asm/mmu_context.h>
+#include <asm/pgalloc.h>
 
 #include "icswx.h"
 
@@ -85,6 +86,9 @@ int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
         spin_lock_init(mm->context.cop_lockp);
 #endif /* CONFIG_PPC_ICSWX */
 
+#ifdef CONFIG_PPC_64K_PAGES
+        mm->context.pte_frag = NULL;
+#endif
         return 0;
 }
 
@@ -96,13 +100,46 @@ void __destroy_context(int context_id)
 }
 EXPORT_SYMBOL_GPL(__destroy_context);
 
+#ifdef CONFIG_PPC_64K_PAGES
+static void destroy_pagetable_page(struct mm_struct *mm)
+{
+        int count;
+        void *pte_frag;
+        struct page *page;
+
+        pte_frag = mm->context.pte_frag;
+        if (!pte_frag)
+                return;
+
+        page = virt_to_page(pte_frag);
+        /* drop all the pending references */
+        count = ((unsigned long)pte_frag & ~PAGE_MASK) >> PTE_FRAG_SIZE_SHIFT;
+        /* We allow PTE_FRAG_NR fragments from a PTE page */
+        count = atomic_sub_return(PTE_FRAG_NR - count, &page->_count);
+        if (!count) {
+                pgtable_page_dtor(page);
+                free_hot_cold_page(page, 0);
+        }
+}
+
+#else
+static inline void destroy_pagetable_page(struct mm_struct *mm)
+{
+        return;
+}
+#endif
+
+
 void destroy_context(struct mm_struct *mm)
 {
+
 #ifdef CONFIG_PPC_ICSWX
         drop_cop(mm->context.acop, mm);
         kfree(mm->context.cop_lockp);
         mm->context.cop_lockp = NULL;
 #endif /* CONFIG_PPC_ICSWX */
+
+        destroy_pagetable_page(mm);
         __destroy_context(mm->context.id);
         subpage_prot_free(mm);
         mm->context.id = MMU_NO_CONTEXT;
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index bba87ca2b4d7..88c0425dc0a8 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -22,6 +22,11 @@
 #include <linux/pfn.h>
 #include <linux/cpuset.h>
 #include <linux/node.h>
+#include <linux/stop_machine.h>
+#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
+#include <linux/uaccess.h>
+#include <linux/slab.h>
 #include <asm/sparsemem.h>
 #include <asm/prom.h>
 #include <asm/smp.h>
@@ -29,6 +34,7 @@
 #include <asm/paca.h>
 #include <asm/hvcall.h>
 #include <asm/setup.h>
+#include <asm/vdso.h>
 
 static int numa_enabled = 1;
 
@@ -62,14 +68,11 @@ static int distance_lookup_table[MAX_NUMNODES][MAX_DISTANCE_REF_POINTS];
  */
 static void __init setup_node_to_cpumask_map(void)
 {
-        unsigned int node, num = 0;
+        unsigned int node;
 
         /* setup nr_node_ids if not done yet */
-        if (nr_node_ids == MAX_NUMNODES) {
-                for_each_node_mask(node, node_possible_map)
-                        num = node;
-                nr_node_ids = num + 1;
-        }
+        if (nr_node_ids == MAX_NUMNODES)
+                setup_nr_node_ids();
 
         /* allocate the map */
         for (node = 0; node < nr_node_ids; node++)
@@ -79,7 +82,7 @@ static void __init setup_node_to_cpumask_map(void)
         dbg("Node to cpumask map for %d nodes\n", nr_node_ids);
 }
 
-static int __cpuinit fake_numa_create_new_node(unsigned long end_pfn,
+static int __init fake_numa_create_new_node(unsigned long end_pfn,
                                                 unsigned int *nid)
 {
         unsigned long long mem;
@@ -201,7 +204,7 @@ int __node_distance(int a, int b)
         int distance = LOCAL_DISTANCE;
 
         if (!form1_affinity)
-                return distance;
+                return ((a == b) ? LOCAL_DISTANCE : REMOTE_DISTANCE);
 
         for (i = 0; i < distance_ref_points_depth; i++) {
                 if (distance_lookup_table[a][i] == distance_lookup_table[b][i])
@@ -291,9 +294,7 @@ EXPORT_SYMBOL_GPL(of_node_to_nid);
 static int __init find_min_common_depth(void)
 {
         int depth;
-        struct device_node *chosen;
         struct device_node *root;
-        const char *vec5;
 
         if (firmware_has_feature(FW_FEATURE_OPAL))
                 root = of_find_node_by_path("/ibm,opal");
@@ -325,24 +326,10 @@ static int __init find_min_common_depth(void)
 
         distance_ref_points_depth /= sizeof(int);
 
-#define VEC5_AFFINITY_BYTE      5
-#define VEC5_AFFINITY           0x80
-
-        if (firmware_has_feature(FW_FEATURE_OPAL))
+        if (firmware_has_feature(FW_FEATURE_OPAL) ||
+            firmware_has_feature(FW_FEATURE_TYPE1_AFFINITY)) {
+                dbg("Using form 1 affinity\n");
                 form1_affinity = 1;
-        else {
-                chosen = of_find_node_by_path("/chosen");
-                if (chosen) {
-                        vec5 = of_get_property(chosen,
-                                               "ibm,architecture-vec-5", NULL);
-                        if (vec5 && (vec5[VEC5_AFFINITY_BYTE] &
-                                                        VEC5_AFFINITY)) {
-                                dbg("Using form 1 affinity\n");
-                                form1_affinity = 1;
-                        }
-
-                        of_node_put(chosen);
-                }
         }
 
         if (form1_affinity) {
@@ -1270,10 +1257,18 @@ u64 memory_hotplug_max(void)
 
 /* Virtual Processor Home Node (VPHN) support */
 #ifdef CONFIG_PPC_SPLPAR
+struct topology_update_data {
+        struct topology_update_data *next;
+        unsigned int cpu;
+        int old_nid;
+        int new_nid;
+};
+
 static u8 vphn_cpu_change_counts[NR_CPUS][MAX_DISTANCE_REF_POINTS];
 static cpumask_t cpu_associativity_changes_mask;
 static int vphn_enabled;
-static void set_topology_timer(void);
+static int prrn_enabled;
+static void reset_topology_timer(void);
 
 /*
  * Store the current values of the associativity change counters in the
@@ -1309,11 +1304,9 @@ static void setup_cpu_associativity_change_counters(void)
  */
 static int update_cpu_associativity_changes_mask(void)
 {
-        int cpu, nr_cpus = 0;
+        int cpu;
         cpumask_t *changes = &cpu_associativity_changes_mask;
 
-        cpumask_clear(changes);
-
         for_each_possible_cpu(cpu) {
                 int i, changed = 0;
                 u8 *counts = vphn_cpu_change_counts[cpu];
@@ -1327,11 +1320,10 @@ static int update_cpu_associativity_changes_mask(void)
                 }
                 if (changed) {
                         cpumask_set_cpu(cpu, changes);
-                        nr_cpus++;
                 }
         }
 
-        return nr_cpus;
+        return cpumask_weight(changes);
 }
 
 /*
@@ -1423,40 +1415,84 @@ static long vphn_get_associativity(unsigned long cpu,
 }
 
 /*
+ * Update the CPU maps and sysfs entries for a single CPU when its NUMA
+ * characteristics change. This function doesn't perform any locking and is
+ * only safe to call from stop_machine().
+ */
+static int update_cpu_topology(void *data)
+{
+        struct topology_update_data *update;
+        unsigned long cpu;
+
+        if (!data)
+                return -EINVAL;
+
+        cpu = get_cpu();
+
+        for (update = data; update; update = update->next) {
+                if (cpu != update->cpu)
+                        continue;
+
+                unregister_cpu_under_node(update->cpu, update->old_nid);
+                unmap_cpu_from_node(update->cpu);
+                map_cpu_to_node(update->cpu, update->new_nid);
+                vdso_getcpu_init();
+                register_cpu_under_node(update->cpu, update->new_nid);
+        }
+
+        return 0;
+}
+
+/*
  * Update the node maps and sysfs entries for each cpu whose home node
  * has changed. Returns 1 when the topology has changed, and 0 otherwise.
  */
 int arch_update_cpu_topology(void)
 {
-        int cpu, nid, old_nid, changed = 0;
+        unsigned int cpu, changed = 0;
+        struct topology_update_data *updates, *ud;
         unsigned int associativity[VPHN_ASSOC_BUFSIZE] = {0};
+        cpumask_t updated_cpus;
         struct device *dev;
+        int weight, i = 0;
+
+        weight = cpumask_weight(&cpu_associativity_changes_mask);
+        if (!weight)
+                return 0;
+
+        updates = kzalloc(weight * (sizeof(*updates)), GFP_KERNEL);
+        if (!updates)
+                return 0;
 
-        for_each_cpu(cpu,&cpu_associativity_changes_mask) {
+        cpumask_clear(&updated_cpus);
+
+        for_each_cpu(cpu, &cpu_associativity_changes_mask) {
+                ud = &updates[i++];
+                ud->cpu = cpu;
                 vphn_get_associativity(cpu, associativity);
-                nid = associativity_to_nid(associativity);
+                ud->new_nid = associativity_to_nid(associativity);
 
-                if (nid < 0 || !node_online(nid))
-                        nid = first_online_node;
+                if (ud->new_nid < 0 || !node_online(ud->new_nid))
+                        ud->new_nid = first_online_node;
 
-                old_nid = numa_cpu_lookup_table[cpu];
+                ud->old_nid = numa_cpu_lookup_table[cpu];
+                cpumask_set_cpu(cpu, &updated_cpus);
 
-                /* Disable hotplug while we update the cpu
-                 * masks and sysfs.
-                 */
-                get_online_cpus();
-                unregister_cpu_under_node(cpu, old_nid);
-                unmap_cpu_from_node(cpu);
-                map_cpu_to_node(cpu, nid);
-                register_cpu_under_node(cpu, nid);
-                put_online_cpus();
-
-                dev = get_cpu_device(cpu);
+                if (i < weight)
+                        ud->next = &updates[i];
+        }
+
+        stop_machine(update_cpu_topology, &updates[0], &updated_cpus);
+
+        for (ud = &updates[0]; ud; ud = ud->next) {
+                dev = get_cpu_device(ud->cpu);
                 if (dev)
                         kobject_uevent(&dev->kobj, KOBJ_CHANGE);
+                cpumask_clear_cpu(ud->cpu, &cpu_associativity_changes_mask);
                 changed = 1;
         }
 
+        kfree(updates);
         return changed;
 }
 
@@ -1473,49 +1509,165 @@ void topology_schedule_update(void)
 
 static void topology_timer_fn(unsigned long ignored)
 {
-        if (!vphn_enabled)
-                return;
-        if (update_cpu_associativity_changes_mask() > 0)
+        if (prrn_enabled && cpumask_weight(&cpu_associativity_changes_mask))
                 topology_schedule_update();
-        set_topology_timer();
+        else if (vphn_enabled) {
+                if (update_cpu_associativity_changes_mask() > 0)
+                        topology_schedule_update();
+                reset_topology_timer();
+        }
 }
 static struct timer_list topology_timer =
         TIMER_INITIALIZER(topology_timer_fn, 0, 0);
 
-static void set_topology_timer(void)
+static void reset_topology_timer(void)
 {
         topology_timer.data = 0;
         topology_timer.expires = jiffies + 60 * HZ;
-        add_timer(&topology_timer);
+        mod_timer(&topology_timer, topology_timer.expires);
+}
+
+#ifdef CONFIG_SMP
+
+static void stage_topology_update(int core_id)
+{
+        cpumask_or(&cpu_associativity_changes_mask,
+                &cpu_associativity_changes_mask, cpu_sibling_mask(core_id));
+        reset_topology_timer();
 }
 
+static int dt_update_callback(struct notifier_block *nb,
+                                unsigned long action, void *data)
+{
+        struct of_prop_reconfig *update;
+        int rc = NOTIFY_DONE;
+
+        switch (action) {
+        case OF_RECONFIG_UPDATE_PROPERTY:
+                update = (struct of_prop_reconfig *)data;
+                if (!of_prop_cmp(update->dn->type, "cpu") &&
+                    !of_prop_cmp(update->prop->name, "ibm,associativity")) {
+                        u32 core_id;
+                        of_property_read_u32(update->dn, "reg", &core_id);
+                        stage_topology_update(core_id);
+                        rc = NOTIFY_OK;
+                }
+                break;
+        }
+
+        return rc;
+}
+
+static struct notifier_block dt_update_nb = {
+        .notifier_call = dt_update_callback,
+};
+
+#endif
+
 /*
- * Start polling for VPHN associativity changes.
+ * Start polling for associativity changes.
  */
 int start_topology_update(void)
 {
         int rc = 0;
 
-        /* Disabled until races with load balancing are fixed */
-        if (0 && firmware_has_feature(FW_FEATURE_VPHN) &&
-            get_lppaca()->shared_proc) {
-                vphn_enabled = 1;
-                setup_cpu_associativity_change_counters();
-                init_timer_deferrable(&topology_timer);
-                set_topology_timer();
-                rc = 1;
+        if (firmware_has_feature(FW_FEATURE_PRRN)) {
+                if (!prrn_enabled) {
+                        prrn_enabled = 1;
+                        vphn_enabled = 0;
+#ifdef CONFIG_SMP
+                        rc = of_reconfig_notifier_register(&dt_update_nb);
+#endif
+                }
+        } else if (firmware_has_feature(FW_FEATURE_VPHN) &&
+                   get_lppaca()->shared_proc) {
+                if (!vphn_enabled) {
+                        prrn_enabled = 0;
+                        vphn_enabled = 1;
+                        setup_cpu_associativity_change_counters();
+                        init_timer_deferrable(&topology_timer);
+                        reset_topology_timer();
+                }
         }
 
         return rc;
 }
-__initcall(start_topology_update);
 
 /*
  * Disable polling for VPHN associativity changes.
  */
 int stop_topology_update(void)
 {
-        vphn_enabled = 0;
-        return del_timer_sync(&topology_timer);
+        int rc = 0;
+
+        if (prrn_enabled) {
+                prrn_enabled = 0;
+#ifdef CONFIG_SMP
+                rc = of_reconfig_notifier_unregister(&dt_update_nb);
+#endif
+        } else if (vphn_enabled) {
+                vphn_enabled = 0;
+                rc = del_timer_sync(&topology_timer);
+        }
+
+        return rc;
+}
+
+int prrn_is_enabled(void)
+{
+        return prrn_enabled;
+}
+
+static int topology_read(struct seq_file *file, void *v)
+{
+        if (vphn_enabled || prrn_enabled)
+                seq_puts(file, "on\n");
+        else
+                seq_puts(file, "off\n");
+
+        return 0;
+}
+
+static int topology_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, topology_read, NULL);
+}
+
+static ssize_t topology_write(struct file *file, const char __user *buf,
+                              size_t count, loff_t *off)
+{
+        char kbuf[4]; /* "on" or "off" plus null. */
+        int read_len;
+
+        read_len = count < 3 ? count : 3;
+        if (copy_from_user(kbuf, buf, read_len))
+                return -EINVAL;
+
+        kbuf[read_len] = '\0';
+
+        if (!strncmp(kbuf, "on", 2))
+                start_topology_update();
+        else if (!strncmp(kbuf, "off", 3))
+                stop_topology_update();
+        else
+                return -EINVAL;
+
+        return count;
+}
+
+static const struct file_operations topology_ops = {
+        .read = seq_read,
+        .write = topology_write,
+        .open = topology_open,
+        .release = single_release
+};
+
+static int topology_update_init(void)
+{
+        start_topology_update();
+        proc_create("powerpc/topology_updates", 644, NULL, &topology_ops);
+
+        return 0;
 }
+device_initcall(topology_update_init);
 #endif /* CONFIG_PPC_SPLPAR */
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index 654258f165ae..a854096e1023 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -337,3 +337,121 @@ EXPORT_SYMBOL(__ioremap_at);
 EXPORT_SYMBOL(iounmap);
 EXPORT_SYMBOL(__iounmap);
 EXPORT_SYMBOL(__iounmap_at);
+
+#ifdef CONFIG_PPC_64K_PAGES
+static pte_t *get_from_cache(struct mm_struct *mm)
+{
+        void *pte_frag, *ret;
+
+        spin_lock(&mm->page_table_lock);
+        ret = mm->context.pte_frag;
+        if (ret) {
+                pte_frag = ret + PTE_FRAG_SIZE;
+                /*
+                 * If we have taken up all the fragments mark PTE page NULL
+                 */
+                if (((unsigned long)pte_frag & ~PAGE_MASK) == 0)
+                        pte_frag = NULL;
+                mm->context.pte_frag = pte_frag;
+        }
+        spin_unlock(&mm->page_table_lock);
+        return (pte_t *)ret;
+}
+
+static pte_t *__alloc_for_cache(struct mm_struct *mm, int kernel)
+{
+        void *ret = NULL;
+        struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
+                                       __GFP_REPEAT | __GFP_ZERO);
+        if (!page)
+                return NULL;
+
+        ret = page_address(page);
+        spin_lock(&mm->page_table_lock);
+        /*
+         * If we find pgtable_page set, we return
+         * the allocated page with single fragement
+         * count.
+         */
+        if (likely(!mm->context.pte_frag)) {
+                atomic_set(&page->_count, PTE_FRAG_NR);
+                mm->context.pte_frag = ret + PTE_FRAG_SIZE;
+        }
+        spin_unlock(&mm->page_table_lock);
+
+        if (!kernel)
+                pgtable_page_ctor(page);
+
+        return (pte_t *)ret;
+}
+
+pte_t *page_table_alloc(struct mm_struct *mm, unsigned long vmaddr, int kernel)
+{
+        pte_t *pte;
+
+        pte = get_from_cache(mm);
+        if (pte)
+                return pte;
+
+        return __alloc_for_cache(mm, kernel);
+}
+
+void page_table_free(struct mm_struct *mm, unsigned long *table, int kernel)
+{
+        struct page *page = virt_to_page(table);
+        if (put_page_testzero(page)) {
+                if (!kernel)
+                        pgtable_page_dtor(page);
+                free_hot_cold_page(page, 0);
+        }
+}
+
+#ifdef CONFIG_SMP
+static void page_table_free_rcu(void *table)
+{
+        struct page *page = virt_to_page(table);
+        if (put_page_testzero(page)) {
+                pgtable_page_dtor(page);
+                free_hot_cold_page(page, 0);
+        }
+}
+
+void pgtable_free_tlb(struct mmu_gather *tlb, void *table, int shift)
+{
+        unsigned long pgf = (unsigned long)table;
+
+        BUG_ON(shift > MAX_PGTABLE_INDEX_SIZE);
+        pgf |= shift;
+        tlb_remove_table(tlb, (void *)pgf);
+}
+
+void __tlb_remove_table(void *_table)
+{
+        void *table = (void *)((unsigned long)_table & ~MAX_PGTABLE_INDEX_SIZE);
+        unsigned shift = (unsigned long)_table & MAX_PGTABLE_INDEX_SIZE;
+
+        if (!shift)
+                /* PTE page needs special handling */
+                page_table_free_rcu(table);
+        else {
+                BUG_ON(shift > MAX_PGTABLE_INDEX_SIZE);
+                kmem_cache_free(PGT_CACHE(shift), table);
+        }
+}
+#else
+void pgtable_free_tlb(struct mmu_gather *tlb, void *table, int shift)
+{
+        if (!shift) {
+                /* PTE page needs special handling */
+                struct page *page = virt_to_page(table);
+                if (put_page_testzero(page)) {
+                        pgtable_page_dtor(page);
+                        free_hot_cold_page(page, 0);
+                }
+        } else {
+                BUG_ON(shift > MAX_PGTABLE_INDEX_SIZE);
+                kmem_cache_free(PGT_CACHE(shift), table);
+        }
+}
+#endif
+#endif /* CONFIG_PPC_64K_PAGES */
diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
index cf9dada734b6..3e99c149271a 100644
--- a/arch/powerpc/mm/slice.c
+++ b/arch/powerpc/mm/slice.c
@@ -237,134 +237,112 @@ static void slice_convert(struct mm_struct *mm, struct slice_mask mask, int psiz
 #endif
 }
 
+/*
+ * Compute which slice addr is part of;
+ * set *boundary_addr to the start or end boundary of that slice
+ * (depending on 'end' parameter);
+ * return boolean indicating if the slice is marked as available in the
+ * 'available' slice_mark.
+ */
+static bool slice_scan_available(unsigned long addr,
+                                 struct slice_mask available,
+                                 int end,
+                                 unsigned long *boundary_addr)
+{
+        unsigned long slice;
+        if (addr < SLICE_LOW_TOP) {
+                slice = GET_LOW_SLICE_INDEX(addr);
+                *boundary_addr = (slice + end) << SLICE_LOW_SHIFT;
+                return !!(available.low_slices & (1u << slice));
+        } else {
+                slice = GET_HIGH_SLICE_INDEX(addr);
+                *boundary_addr = (slice + end) ?
+                        ((slice + end) << SLICE_HIGH_SHIFT) : SLICE_LOW_TOP;
+                return !!(available.high_slices & (1u << slice));
+        }
+}
+
 static unsigned long slice_find_area_bottomup(struct mm_struct *mm,
                                               unsigned long len,
                                               struct slice_mask available,
-                                              int psize, int use_cache)
+                                              int psize)
 {
-        struct vm_area_struct *vma;
-        unsigned long start_addr, addr;
-        struct slice_mask mask;
         int pshift = max_t(int, mmu_psize_defs[psize].shift, PAGE_SHIFT);
-
-        if (use_cache) {
-                if (len <= mm->cached_hole_size) {
-                        start_addr = addr = TASK_UNMAPPED_BASE;
-                        mm->cached_hole_size = 0;
-                } else
-                        start_addr = addr = mm->free_area_cache;
-        } else
-                start_addr = addr = TASK_UNMAPPED_BASE;
-
-full_search:
-        for (;;) {
-                addr = _ALIGN_UP(addr, 1ul << pshift);
-                if ((TASK_SIZE - len) < addr)
-                        break;
-                vma = find_vma(mm, addr);
-                BUG_ON(vma && (addr >= vma->vm_end));
-
-                mask = slice_range_to_mask(addr, len);
-                if (!slice_check_fit(mask, available)) {
-                        if (addr < SLICE_LOW_TOP)
-                                addr = _ALIGN_UP(addr + 1,  1ul << SLICE_LOW_SHIFT);
-                        else
-                                addr = _ALIGN_UP(addr + 1,  1ul << SLICE_HIGH_SHIFT);
+        unsigned long addr, found, next_end;
+        struct vm_unmapped_area_info info;
+
+        info.flags = 0;
+        info.length = len;
+        info.align_mask = PAGE_MASK & ((1ul << pshift) - 1);
+        info.align_offset = 0;
+
+        addr = TASK_UNMAPPED_BASE;
+        while (addr < TASK_SIZE) {
+                info.low_limit = addr;
+                if (!slice_scan_available(addr, available, 1, &addr))
                         continue;
+
+ next_slice:
+                /*
+                 * At this point [info.low_limit; addr) covers
+                 * available slices only and ends at a slice boundary.
+                 * Check if we need to reduce the range, or if we can
+                 * extend it to cover the next available slice.
+                 */
+                if (addr >= TASK_SIZE)
+                        addr = TASK_SIZE;
+                else if (slice_scan_available(addr, available, 1, &next_end)) {
+                        addr = next_end;
+                        goto next_slice;
                 }
-                if (!vma || addr + len <= vma->vm_start) {
-                        /*
-                         * Remember the place where we stopped the search:
-                         */
-                        if (use_cache)
-                                mm->free_area_cache = addr + len;
-                        return addr;
-                }
-                if (use_cache && (addr + mm->cached_hole_size) < vma->vm_start)
-                        mm->cached_hole_size = vma->vm_start - addr;
-                addr = vma->vm_end;
-        }
+                info.high_limit = addr;
 
-        /* Make sure we didn't miss any holes */
-        if (use_cache && start_addr != TASK_UNMAPPED_BASE) {
-                start_addr = addr = TASK_UNMAPPED_BASE;
-                mm->cached_hole_size = 0;
-                goto full_search;
+                found = vm_unmapped_area(&info);
+                if (!(found & ~PAGE_MASK))
+                        return found;
         }
+
         return -ENOMEM;
 }
 
 static unsigned long slice_find_area_topdown(struct mm_struct *mm,
                                              unsigned long len,
                                              struct slice_mask available,
-                                             int psize, int use_cache)
+                                             int psize)
 {
-        struct vm_area_struct *vma;
-        unsigned long addr;
-        struct slice_mask mask;
         int pshift = max_t(int, mmu_psize_defs[psize].shift, PAGE_SHIFT);
+        unsigned long addr, found, prev;
+        struct vm_unmapped_area_info info;
 
-        /* check if free_area_cache is useful for us */
-        if (use_cache) {
-                if (len <= mm->cached_hole_size) {
-                        mm->cached_hole_size = 0;
-                        mm->free_area_cache = mm->mmap_base;
-                }
-
-                /* either no address requested or can't fit in requested
-                 * address hole
-                 */
-                addr = mm->free_area_cache;
-
-                /* make sure it can fit in the remaining address space */
-                if (addr > len) {
-                        addr = _ALIGN_DOWN(addr - len, 1ul << pshift);
-                        mask = slice_range_to_mask(addr, len);
-                        if (slice_check_fit(mask, available) &&
-                            slice_area_is_free(mm, addr, len))
-                                        /* remember the address as a hint for
-                                         * next time
-                                         */
-                                        return (mm->free_area_cache = addr);
-                }
-        }
+        info.flags = VM_UNMAPPED_AREA_TOPDOWN;
+        info.length = len;
+        info.align_mask = PAGE_MASK & ((1ul << pshift) - 1);
+        info.align_offset = 0;
 
         addr = mm->mmap_base;
-        while (addr > len) {
-                /* Go down by chunk size */
-                addr = _ALIGN_DOWN(addr - len, 1ul << pshift);
-
-                /* Check for hit with different page size */
-                mask = slice_range_to_mask(addr, len);
-                if (!slice_check_fit(mask, available)) {
-                        if (addr < SLICE_LOW_TOP)
-                                addr = _ALIGN_DOWN(addr, 1ul << SLICE_LOW_SHIFT);
-                        else if (addr < (1ul << SLICE_HIGH_SHIFT))
-                                addr = SLICE_LOW_TOP;
-                        else
-                                addr = _ALIGN_DOWN(addr, 1ul << SLICE_HIGH_SHIFT);
+        while (addr > PAGE_SIZE) {
+                info.high_limit = addr;
+                if (!slice_scan_available(addr - 1, available, 0, &addr))
                         continue;
-                }
 
+ prev_slice:
                 /*
-                 * Lookup failure means no vma is above this address,
-                 * else if new region fits below vma->vm_start,
-                 * return with success:
+                 * At this point [addr; info.high_limit) covers
+                 * available slices only and starts at a slice boundary.
+                 * Check if we need to reduce the range, or if we can
+                 * extend it to cover the previous available slice.
                  */
-                vma = find_vma(mm, addr);
-                if (!vma || (addr + len) <= vma->vm_start) {
-                        /* remember the address as a hint for next time */
-                        if (use_cache)
-                                mm->free_area_cache = addr;
-                        return addr;
+                if (addr < PAGE_SIZE)
+                        addr = PAGE_SIZE;
+                else if (slice_scan_available(addr - 1, available, 0, &prev)) {
+                        addr = prev;
+                        goto prev_slice;
                 }
+                info.low_limit = addr;
 
-                /* remember the largest hole we saw so far */
-                if (use_cache && (addr + mm->cached_hole_size) < vma->vm_start)
-                        mm->cached_hole_size = vma->vm_start - addr;
-
-                /* try just below the current vma->vm_start */
-                addr = vma->vm_start;
+                found = vm_unmapped_area(&info);
+                if (!(found & ~PAGE_MASK))
+                        return found;
         }
 
         /*
@@ -373,28 +351,18 @@ static unsigned long slice_find_area_topdown(struct mm_struct *mm,
          * can happen with large stack limits and large mmap()
          * allocations.
          */
-        addr = slice_find_area_bottomup(mm, len, available, psize, 0);
-
-        /*
-         * Restore the topdown base:
-         */
-        if (use_cache) {
-                mm->free_area_cache = mm->mmap_base;
-                mm->cached_hole_size = ~0UL;
-        }
-
-        return addr;
+        return slice_find_area_bottomup(mm, len, available, psize);
 }
 
 
 static unsigned long slice_find_area(struct mm_struct *mm, unsigned long len,
                                      struct slice_mask mask, int psize,
-                                     int topdown, int use_cache)
+                                     int topdown)
 {
         if (topdown)
-                return slice_find_area_topdown(mm, len, mask, psize, use_cache);
+                return slice_find_area_topdown(mm, len, mask, psize);
         else
-                return slice_find_area_bottomup(mm, len, mask, psize, use_cache);
+                return slice_find_area_bottomup(mm, len, mask, psize);
 }
 
 #define or_mask(dst, src)       do {                    \
@@ -415,7 +383,7 @@ static unsigned long slice_find_area(struct mm_struct *mm, unsigned long len,
 
 unsigned long slice_get_unmapped_area(unsigned long addr, unsigned long len,
                                       unsigned long flags, unsigned int psize,
-                                      int topdown, int use_cache)
+                                      int topdown)
 {
         struct slice_mask mask = {0, 0};
         struct slice_mask good_mask;
@@ -430,8 +398,8 @@ unsigned long slice_get_unmapped_area(unsigned long addr, unsigned long len,
         BUG_ON(mm->task_size == 0);
 
         slice_dbg("slice_get_unmapped_area(mm=%p, psize=%d...\n", mm, psize);
-        slice_dbg(" addr=%lx, len=%lx, flags=%lx, topdown=%d, use_cache=%d\n",
-                  addr, len, flags, topdown, use_cache);
+        slice_dbg(" addr=%lx, len=%lx, flags=%lx, topdown=%d\n",
+                  addr, len, flags, topdown);
 
         if (len > mm->task_size)
                 return -ENOMEM;
@@ -503,8 +471,7 @@ unsigned long slice_get_unmapped_area(unsigned long addr, unsigned long len,
                 /* Now let's see if we can find something in the existing
                  * slices for that size
                  */
-                newaddr = slice_find_area(mm, len, good_mask, psize, topdown,
-                                          use_cache);
+                newaddr = slice_find_area(mm, len, good_mask, psize, topdown);
                 if (newaddr != -ENOMEM) {
                         /* Found within the good mask, we don't have to setup,
                          * we thus return directly
@@ -536,8 +503,7 @@ unsigned long slice_get_unmapped_area(unsigned long addr, unsigned long len,
          * anywhere in the good area.
          */
         if (addr) {
-                addr = slice_find_area(mm, len, good_mask, psize, topdown,
-                                       use_cache);
+                addr = slice_find_area(mm, len, good_mask, psize, topdown);
                 if (addr != -ENOMEM) {
                         slice_dbg(" found area at 0x%lx\n", addr);
                         return addr;
@@ -547,15 +513,14 @@ unsigned long slice_get_unmapped_area(unsigned long addr, unsigned long len,
         /* Now let's see if we can find something in the existing slices
          * for that size plus free slices
          */
-        addr = slice_find_area(mm, len, potential_mask, psize, topdown,
-                               use_cache);
+        addr = slice_find_area(mm, len, potential_mask, psize, topdown);
 
 #ifdef CONFIG_PPC_64K_PAGES
         if (addr == -ENOMEM && psize == MMU_PAGE_64K) {
                 /* retry the search with 4k-page slices included */
                 or_mask(potential_mask, compat_mask);
                 addr = slice_find_area(mm, len, potential_mask, psize,
-                                       topdown, use_cache);
+                                       topdown);
         }
 #endif
 
@@ -586,8 +551,7 @@ unsigned long arch_get_unmapped_area(struct file *filp,
                                      unsigned long flags)
 {
         return slice_get_unmapped_area(addr, len, flags,
-                                       current->mm->context.user_psize,
-                                       0, 1);
+                                       current->mm->context.user_psize, 0);
 }
 
 unsigned long arch_get_unmapped_area_topdown(struct file *filp,
@@ -597,8 +561,7 @@ unsigned long arch_get_unmapped_area_topdown(struct file *filp,
                                              const unsigned long flags)
 {
         return slice_get_unmapped_area(addr0, len, flags,
-                                       current->mm->context.user_psize,
-                                       1, 1);
+                                       current->mm->context.user_psize, 1);
 }
 
 unsigned int get_slice_psize(struct mm_struct *mm, unsigned long addr)
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index df32a838dcfa..6888cad5103d 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -414,9 +414,9 @@ static void setup_page_sizes(void)
 
 #ifdef CONFIG_PPC_FSL_BOOK3E
         unsigned int mmucfg = mfspr(SPRN_MMUCFG);
+        int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E);
 
-        if (((mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) &&
-                (mmu_has_feature(MMU_FTR_TYPE_FSL_E))) {
+        if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
                 unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG);
                 unsigned int min_pg, max_pg;
 
@@ -442,6 +442,20 @@ static void setup_page_sizes(void)
 
                 goto no_indirect;
         }
+
+        if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
+                u32 tlb1ps = mfspr(SPRN_TLB1PS);
+
+                for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
+                        struct mmu_psize_def *def = &mmu_psize_defs[psize];
+
+                        if (tlb1ps & (1U << (def->shift - 10))) {
+                                def->flags |= MMU_PAGE_SIZE_DIRECT;
+                        }
+                }
+
+                goto no_indirect;
+        }
 #endif
 
         tlb0cfg = mfspr(SPRN_TLB0CFG);
diff --git a/arch/powerpc/perf/Makefile b/arch/powerpc/perf/Makefile
index af3fac23768c..510fae10513d 100644
--- a/arch/powerpc/perf/Makefile
+++ b/arch/powerpc/perf/Makefile
@@ -2,9 +2,10 @@ subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
 
 obj-$(CONFIG_PERF_EVENTS)       += callchain.o
 
-obj-$(CONFIG_PPC_PERF_CTRS)     += core-book3s.o
+obj-$(CONFIG_PPC_PERF_CTRS)     += core-book3s.o bhrb.o
 obj64-$(CONFIG_PPC_PERF_CTRS)   += power4-pmu.o ppc970-pmu.o power5-pmu.o \
-                                   power5+-pmu.o power6-pmu.o power7-pmu.o
+                                   power5+-pmu.o power6-pmu.o power7-pmu.o \
+                                   power8-pmu.o
 obj32-$(CONFIG_PPC_PERF_CTRS)   += mpc7450-pmu.o
 
 obj-$(CONFIG_FSL_EMB_PERF_EVENT) += core-fsl-emb.o
diff --git a/arch/powerpc/perf/bhrb.S b/arch/powerpc/perf/bhrb.S
new file mode 100644
index 000000000000..d85f9a58ddbc
--- /dev/null
+++ b/arch/powerpc/perf/bhrb.S
@@ -0,0 +1,44 @@
+/*
+ * Basic assembly code to read BHRB entries
+ *
+ * Copyright 2013 Anshuman Khandual, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <asm/ppc_asm.h>
+#include <asm/ppc-opcode.h>
+
+        .text
+
+.balign 8
+
+/* r3 = n  (where n = [0-31])
+ * The maximum number of BHRB entries supported with PPC_MFBHRBE instruction
+ * is 1024. We have limited number of table entries here as POWER8 implements
+ * 32 BHRB entries.
+ */
+
+/* .global read_bhrb */
+_GLOBAL(read_bhrb)
+        cmpldi  r3,31
+        bgt     1f
+        ld      r4,bhrb_table@got(r2)
+        sldi    r3,r3,3
+        add     r3,r4,r3
+        mtctr   r3
+        bctr
+1:      li      r3,0
+        blr
+
+#define MFBHRB_TABLE1(n) PPC_MFBHRBE(R3,n); blr
+#define MFBHRB_TABLE2(n) MFBHRB_TABLE1(n); MFBHRB_TABLE1(n+1)
+#define MFBHRB_TABLE4(n) MFBHRB_TABLE2(n); MFBHRB_TABLE2(n+2)
+#define MFBHRB_TABLE8(n) MFBHRB_TABLE4(n); MFBHRB_TABLE4(n+4)
+#define MFBHRB_TABLE16(n) MFBHRB_TABLE8(n); MFBHRB_TABLE8(n+8)
+#define MFBHRB_TABLE32(n) MFBHRB_TABLE16(n); MFBHRB_TABLE16(n+16)
+
+bhrb_table:
+        MFBHRB_TABLE32(0)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 65362e98eb26..c627843c5b2e 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -19,6 +19,11 @@
 #include <asm/firmware.h>
 #include <asm/ptrace.h>
 
+#define BHRB_MAX_ENTRIES        32
+#define BHRB_TARGET             0x0000000000000002
+#define BHRB_PREDICTION         0x0000000000000001
+#define BHRB_EA                 0xFFFFFFFFFFFFFFFC
+
 struct cpu_hw_events {
         int n_events;
         int n_percpu;
@@ -38,7 +43,15 @@ struct cpu_hw_events {
 
         unsigned int group_flag;
         int n_txn_start;
+
+        /* BHRB bits */
+        u64                             bhrb_filter;    /* BHRB HW branch filter */
+        int                             bhrb_users;
+        void                            *bhrb_context;
+        struct  perf_branch_stack       bhrb_stack;
+        struct  perf_branch_entry       bhrb_entries[BHRB_MAX_ENTRIES];
 };
+
 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
 
 struct power_pmu *ppmu;
@@ -89,6 +102,11 @@ static inline int siar_valid(struct pt_regs *regs)
 
 #endif /* CONFIG_PPC32 */
 
+static bool regs_use_siar(struct pt_regs *regs)
+{
+        return !!(regs->result & 1);
+}
+
 /*
  * Things that are specific to 64-bit implementations.
  */
@@ -98,11 +116,12 @@ static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
 {
         unsigned long mmcra = regs->dsisr;
 
-        if ((mmcra & MMCRA_SAMPLE_ENABLE) && !(ppmu->flags & PPMU_ALT_SIPR)) {
+        if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) {
                 unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
                 if (slot > 1)
                         return 4 * (slot - 1);
         }
+
         return 0;
 }
 
@@ -130,24 +149,35 @@ static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
                 *addrp = mfspr(SPRN_SDAR);
 }
 
-static bool mmcra_sihv(unsigned long mmcra)
+static bool regs_sihv(struct pt_regs *regs)
 {
         unsigned long sihv = MMCRA_SIHV;
 
+        if (ppmu->flags & PPMU_HAS_SIER)
+                return !!(regs->dar & SIER_SIHV);
+
         if (ppmu->flags & PPMU_ALT_SIPR)
                 sihv = POWER6_MMCRA_SIHV;
 
-        return !!(mmcra & sihv);
+        return !!(regs->dsisr & sihv);
 }
 
-static bool mmcra_sipr(unsigned long mmcra)
+static bool regs_sipr(struct pt_regs *regs)
 {
         unsigned long sipr = MMCRA_SIPR;
 
+        if (ppmu->flags & PPMU_HAS_SIER)
+                return !!(regs->dar & SIER_SIPR);
+
         if (ppmu->flags & PPMU_ALT_SIPR)
                 sipr = POWER6_MMCRA_SIPR;
 
-        return !!(mmcra & sipr);
+        return !!(regs->dsisr & sipr);
+}
+
+static bool regs_no_sipr(struct pt_regs *regs)
+{
+        return !!(regs->result & 2);
 }
 
 static inline u32 perf_flags_from_msr(struct pt_regs *regs)
@@ -161,8 +191,7 @@ static inline u32 perf_flags_from_msr(struct pt_regs *regs)
 
 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
 {
-        unsigned long mmcra = regs->dsisr;
-        unsigned long use_siar = regs->result;
+        bool use_siar = regs_use_siar(regs);
 
         if (!use_siar)
                 return perf_flags_from_msr(regs);
@@ -173,7 +202,7 @@ static inline u32 perf_get_misc_flags(struct pt_regs *regs)
          * SIAR which should give slightly more reliable
          * results
          */
-        if (ppmu->flags & PPMU_NO_SIPR) {
+        if (regs_no_sipr(regs)) {
                 unsigned long siar = mfspr(SPRN_SIAR);
                 if (siar >= PAGE_OFFSET)
                         return PERF_RECORD_MISC_KERNEL;
@@ -181,16 +210,19 @@ static inline u32 perf_get_misc_flags(struct pt_regs *regs)
         }
 
         /* PR has priority over HV, so order below is important */
-        if (mmcra_sipr(mmcra))
+        if (regs_sipr(regs))
                 return PERF_RECORD_MISC_USER;
-        if (mmcra_sihv(mmcra) && (freeze_events_kernel != MMCR0_FCHV))
+
+        if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV))
                 return PERF_RECORD_MISC_HYPERVISOR;
+
         return PERF_RECORD_MISC_KERNEL;
 }
 
 /*
  * Overload regs->dsisr to store MMCRA so we only need to read it once
  * on each interrupt.
+ * Overload regs->dar to store SIER if we have it.
  * Overload regs->result to specify whether we should use the MSR (result
  * is zero) or the SIAR (result is non zero).
  */
@@ -200,6 +232,24 @@ static inline void perf_read_regs(struct pt_regs *regs)
         int marked = mmcra & MMCRA_SAMPLE_ENABLE;
         int use_siar;
 
+        regs->dsisr = mmcra;
+        regs->result = 0;
+
+        if (ppmu->flags & PPMU_NO_SIPR)
+                regs->result |= 2;
+
+        /*
+         * On power8 if we're in random sampling mode, the SIER is updated.
+         * If we're in continuous sampling mode, we don't have SIPR.
+         */
+        if (ppmu->flags & PPMU_HAS_SIER) {
+                if (marked)
+                        regs->dar = mfspr(SPRN_SIER);
+                else
+                        regs->result |= 2;
+        }
+
+
         /*
          * If this isn't a PMU exception (eg a software event) the SIAR is
          * not valid. Use pt_regs.
@@ -223,13 +273,12 @@ static inline void perf_read_regs(struct pt_regs *regs)
                 use_siar = 1;
         else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING))
                 use_siar = 0;
-        else if (!(ppmu->flags & PPMU_NO_SIPR) && mmcra_sipr(mmcra))
+        else if (!regs_no_sipr(regs) && regs_sipr(regs))
                 use_siar = 0;
         else
                 use_siar = 1;
 
-        regs->dsisr = mmcra;
-        regs->result = use_siar;
+        regs->result |= use_siar;
 }
 
 /*
@@ -822,6 +871,9 @@ static void power_pmu_enable(struct pmu *pmu)
         }
 
  out:
+        if (cpuhw->bhrb_users)
+                ppmu->config_bhrb(cpuhw->bhrb_filter);
+
         local_irq_restore(flags);
 }
 
@@ -852,6 +904,47 @@ static int collect_events(struct perf_event *group, int max_count,
         return n;
 }
 
+/* Reset all possible BHRB entries */
+static void power_pmu_bhrb_reset(void)
+{
+        asm volatile(PPC_CLRBHRB);
+}
+
+void power_pmu_bhrb_enable(struct perf_event *event)
+{
+        struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
+
+        if (!ppmu->bhrb_nr)
+                return;
+
+        /* Clear BHRB if we changed task context to avoid data leaks */
+        if (event->ctx->task && cpuhw->bhrb_context != event->ctx) {
+                power_pmu_bhrb_reset();
+                cpuhw->bhrb_context = event->ctx;
+        }
+        cpuhw->bhrb_users++;
+}
+
+void power_pmu_bhrb_disable(struct perf_event *event)
+{
+        struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
+
+        if (!ppmu->bhrb_nr)
+                return;
+
+        cpuhw->bhrb_users--;
+        WARN_ON_ONCE(cpuhw->bhrb_users < 0);
+
+        if (!cpuhw->disabled && !cpuhw->bhrb_users) {
+                /* BHRB cannot be turned off when other
+                 * events are active on the PMU.
+                 */
+
+                /* avoid stale pointer */
+                cpuhw->bhrb_context = NULL;
+        }
+}
+
 /*
  * Add a event to the PMU.
  * If all events are not already frozen, then we disable and
@@ -911,6 +1004,9 @@ nocheck:
 
         ret = 0;
  out:
+        if (has_branch_stack(event))
+                power_pmu_bhrb_enable(event);
+
         perf_pmu_enable(event->pmu);
         local_irq_restore(flags);
         return ret;
@@ -963,6 +1059,9 @@ static void power_pmu_del(struct perf_event *event, int ef_flags)
                 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
         }
 
+        if (has_branch_stack(event))
+                power_pmu_bhrb_disable(event);
+
         perf_pmu_enable(event->pmu);
         local_irq_restore(flags);
 }
@@ -1081,6 +1180,15 @@ int power_pmu_commit_txn(struct pmu *pmu)
         return 0;
 }
 
+/* Called from ctxsw to prevent one process's branch entries to
+ * mingle with the other process's entries during context switch.
+ */
+void power_pmu_flush_branch_stack(void)
+{
+        if (ppmu->bhrb_nr)
+                power_pmu_bhrb_reset();
+}
+
 /*
  * Return 1 if we might be able to put event on a limited PMC,
  * or 0 if not.
@@ -1195,9 +1303,11 @@ static int power_pmu_event_init(struct perf_event *event)
         if (!ppmu)
                 return -ENOENT;
 
-        /* does not support taken branch sampling */
-        if (has_branch_stack(event))
-                return -EOPNOTSUPP;
+        if (has_branch_stack(event)) {
+                /* PMU has BHRB enabled */
+                if (!(ppmu->flags & PPMU_BHRB))
+                        return -EOPNOTSUPP;
+        }
 
         switch (event->attr.type) {
         case PERF_TYPE_HARDWARE:
@@ -1278,6 +1388,15 @@ static int power_pmu_event_init(struct perf_event *event)
 
         cpuhw = &get_cpu_var(cpu_hw_events);
         err = power_check_constraints(cpuhw, events, cflags, n + 1);
+
+        if (has_branch_stack(event)) {
+                cpuhw->bhrb_filter = ppmu->bhrb_filter_map(
+                                        event->attr.branch_sample_type);
+
+                if(cpuhw->bhrb_filter == -1)
+                        return -EOPNOTSUPP;
+        }
+
         put_cpu_var(cpu_hw_events);
         if (err)
                 return -EINVAL;
@@ -1336,8 +1455,79 @@ struct pmu power_pmu = {
         .cancel_txn     = power_pmu_cancel_txn,
         .commit_txn     = power_pmu_commit_txn,
         .event_idx      = power_pmu_event_idx,
+        .flush_branch_stack = power_pmu_flush_branch_stack,
 };
 
+/* Processing BHRB entries */
+void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw)
+{
+        u64 val;
+        u64 addr;
+        int r_index, u_index, target, pred;
+
+        r_index = 0;
+        u_index = 0;
+        while (r_index < ppmu->bhrb_nr) {
+                /* Assembly read function */
+                val = read_bhrb(r_index);
+
+                /* Terminal marker: End of valid BHRB entries */
+                if (val == 0) {
+                        break;
+                } else {
+                        /* BHRB field break up */
+                        addr = val & BHRB_EA;
+                        pred = val & BHRB_PREDICTION;
+                        target = val & BHRB_TARGET;
+
+                        /* Probable Missed entry: Not applicable for POWER8 */
+                        if ((addr == 0) && (target == 0) && (pred == 1)) {
+                                r_index++;
+                                continue;
+                        }
+
+                        /* Real Missed entry: Power8 based missed entry */
+                        if ((addr == 0) && (target == 1) && (pred == 1)) {
+                                r_index++;
+                                continue;
+                        }
+
+                        /* Reserved condition: Not a valid entry  */
+                        if ((addr == 0) && (target == 1) && (pred == 0)) {
+                                r_index++;
+                                continue;
+                        }
+
+                        /* Is a target address */
+                        if (val & BHRB_TARGET) {
+                                /* First address cannot be a target address */
+                                if (r_index == 0) {
+                                        r_index++;
+                                        continue;
+                                }
+
+                                /* Update target address for the previous entry */
+                                cpuhw->bhrb_entries[u_index - 1].to = addr;
+                                cpuhw->bhrb_entries[u_index - 1].mispred = pred;
+                                cpuhw->bhrb_entries[u_index - 1].predicted = ~pred;
+
+                                /* Dont increment u_index */
+                                r_index++;
+                        } else {
+                                /* Update address, flags for current entry */
+                                cpuhw->bhrb_entries[u_index].from = addr;
+                                cpuhw->bhrb_entries[u_index].mispred = pred;
+                                cpuhw->bhrb_entries[u_index].predicted = ~pred;
+
+                                /* Successfully popullated one entry */
+                                u_index++;
+                                r_index++;
+                        }
+                }
+        }
+        cpuhw->bhrb_stack.nr = u_index;
+        return;
+}
 
 /*
  * A counter has overflowed; update its count and record
@@ -1397,6 +1587,13 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
                 if (event->attr.sample_type & PERF_SAMPLE_ADDR)
                         perf_get_data_addr(regs, &data.addr);
 
+                if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) {
+                        struct cpu_hw_events *cpuhw;
+                        cpuhw = &__get_cpu_var(cpu_hw_events);
+                        power_pmu_bhrb_read(cpuhw);
+                        data.br_stack = &cpuhw->bhrb_stack;
+                }
+
                 if (perf_event_overflow(event, &data, regs))
                         power_pmu_stop(event, 0);
         }
@@ -1422,7 +1619,7 @@ unsigned long perf_misc_flags(struct pt_regs *regs)
  */
 unsigned long perf_instruction_pointer(struct pt_regs *regs)
 {
-        unsigned long use_siar = regs->result;
+        bool use_siar = regs_use_siar(regs);
 
         if (use_siar && siar_valid(regs))
                 return mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
diff --git a/arch/powerpc/perf/power5+-pmu.c b/arch/powerpc/perf/power5+-pmu.c
index a8757baa28f3..b03b6dc0172d 100644
--- a/arch/powerpc/perf/power5+-pmu.c
+++ b/arch/powerpc/perf/power5+-pmu.c
@@ -671,7 +671,7 @@ static struct power_pmu power5p_pmu = {
         .get_alternatives       = power5p_get_alternatives,
         .disable_pmc            = power5p_disable_pmc,
         .limited_pmc_event      = power5p_limited_pmc_event,
-        .flags                  = PPMU_LIMITED_PMC5_6,
+        .flags                  = PPMU_LIMITED_PMC5_6 | PPMU_HAS_SSLOT,
         .n_generic              = ARRAY_SIZE(power5p_generic_events),
         .generic_events         = power5p_generic_events,
         .cache_events           = &power5p_cache_events,
diff --git a/arch/powerpc/perf/power5-pmu.c b/arch/powerpc/perf/power5-pmu.c
index e7f06eb7a861..1e8ce423c3af 100644
--- a/arch/powerpc/perf/power5-pmu.c
+++ b/arch/powerpc/perf/power5-pmu.c
@@ -615,6 +615,7 @@ static struct power_pmu power5_pmu = {
         .n_generic              = ARRAY_SIZE(power5_generic_events),
         .generic_events         = power5_generic_events,
         .cache_events           = &power5_cache_events,
+        .flags                  = PPMU_HAS_SSLOT,
 };
 
 static int __init init_power5_pmu(void)
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
new file mode 100644
index 000000000000..f7d1c4fff303
--- /dev/null
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -0,0 +1,592 @@
+/*
+ * Performance counter support for POWER8 processors.
+ *
+ * Copyright 2009 Paul Mackerras, IBM Corporation.
+ * Copyright 2013 Michael Ellerman, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/perf_event.h>
+#include <asm/firmware.h>
+
+
+/*
+ * Some power8 event codes.
+ */
+#define PM_CYC                          0x0001e
+#define PM_GCT_NOSLOT_CYC               0x100f8
+#define PM_CMPLU_STALL                  0x4000a
+#define PM_INST_CMPL                    0x00002
+#define PM_BRU_FIN                      0x10068
+#define PM_BR_MPRED_CMPL                0x400f6
+
+
+/*
+ * Raw event encoding for POWER8:
+ *
+ *        60        56        52        48        44        40        36        32
+ * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
+ *                                     [      thresh_cmp     ]   [  thresh_ctl   ]
+ *                                                                       |
+ *                                       thresh start/stop OR FAB match -*
+ *
+ *        28        24        20        16        12         8         4         0
+ * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
+ *   [   ] [  sample ]   [cache]   [ pmc ]   [unit ]   c     m   [    pmcxsel    ]
+ *     |        |           |                          |     |
+ *     |        |           |                          |     *- mark
+ *     |        |           *- L1/L2/L3 cache_sel      |
+ *     |        |                                      |
+ *     |        *- sampling mode for marked events     *- combine
+ *     |
+ *     *- thresh_sel
+ *
+ * Below uses IBM bit numbering.
+ *
+ * MMCR1[x:y] = unit    (PMCxUNIT)
+ * MMCR1[x]   = combine (PMCxCOMB)
+ *
+ * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
+ *      # PM_MRK_FAB_RSP_MATCH
+ *      MMCR1[20:27] = thresh_ctl   (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
+ * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
+ *      # PM_MRK_FAB_RSP_MATCH_CYC
+ *      MMCR1[20:27] = thresh_ctl   (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
+ * else
+ *      MMCRA[48:55] = thresh_ctl   (THRESH START/END)
+ *
+ * if thresh_sel:
+ *      MMCRA[45:47] = thresh_sel
+ *
+ * if thresh_cmp:
+ *      MMCRA[22:24] = thresh_cmp[0:2]
+ *      MMCRA[25:31] = thresh_cmp[3:9]
+ *
+ * if unit == 6 or unit == 7
+ *      MMCRC[53:55] = cache_sel[1:3]      (L2EVENT_SEL)
+ * else if unit == 8 or unit == 9:
+ *      if cache_sel[0] == 0: # L3 bank
+ *              MMCRC[47:49] = cache_sel[1:3]  (L3EVENT_SEL0)
+ *      else if cache_sel[0] == 1:
+ *              MMCRC[50:51] = cache_sel[2:3]  (L3EVENT_SEL1)
+ * else if cache_sel[1]: # L1 event
+ *      MMCR1[16] = cache_sel[2]
+ *     MMCR1[17] = cache_sel[3]
+ *
+ * if mark:
+ *      MMCRA[63]    = 1                (SAMPLE_ENABLE)
+ *      MMCRA[57:59] = sample[0:2]      (RAND_SAMP_ELIG)
+ *     MMCRA[61:62] = sample[3:4]      (RAND_SAMP_MODE)
+ *
+ */
+
+#define EVENT_THR_CMP_SHIFT     40      /* Threshold CMP value */
+#define EVENT_THR_CMP_MASK      0x3ff
+#define EVENT_THR_CTL_SHIFT     32      /* Threshold control value (start/stop) */
+#define EVENT_THR_CTL_MASK      0xffull
+#define EVENT_THR_SEL_SHIFT     29      /* Threshold select value */
+#define EVENT_THR_SEL_MASK      0x7
+#define EVENT_THRESH_SHIFT      29      /* All threshold bits */
+#define EVENT_THRESH_MASK       0x1fffffull
+#define EVENT_SAMPLE_SHIFT      24      /* Sampling mode & eligibility */
+#define EVENT_SAMPLE_MASK       0x1f
+#define EVENT_CACHE_SEL_SHIFT   20      /* L2/L3 cache select */
+#define EVENT_CACHE_SEL_MASK    0xf
+#define EVENT_IS_L1             (4 << EVENT_CACHE_SEL_SHIFT)
+#define EVENT_PMC_SHIFT         16      /* PMC number (1-based) */
+#define EVENT_PMC_MASK          0xf
+#define EVENT_UNIT_SHIFT        12      /* Unit */
+#define EVENT_UNIT_MASK         0xf
+#define EVENT_COMBINE_SHIFT     11      /* Combine bit */
+#define EVENT_COMBINE_MASK      0x1
+#define EVENT_MARKED_SHIFT      8       /* Marked bit */
+#define EVENT_MARKED_MASK       0x1
+#define EVENT_IS_MARKED         (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT)
+#define EVENT_PSEL_MASK         0xff    /* PMCxSEL value */
+
+/* MMCRA IFM bits - POWER8 */
+#define POWER8_MMCRA_IFM1               0x0000000040000000UL
+#define POWER8_MMCRA_IFM2               0x0000000080000000UL
+#define POWER8_MMCRA_IFM3               0x00000000C0000000UL
+
+#define ONLY_PLM \
+        (PERF_SAMPLE_BRANCH_USER        |\
+         PERF_SAMPLE_BRANCH_KERNEL      |\
+         PERF_SAMPLE_BRANCH_HV)
+
+/*
+ * Layout of constraint bits:
+ *
+ *        60        56        52        48        44        40        36        32
+ * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
+ *   [   fab_match   ]         [       thresh_cmp      ] [   thresh_ctl    ] [   ]
+ *                                                                             |
+ *                                                                 thresh_sel -*
+ *
+ *        28        24        20        16        12         8         4         0
+ * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
+ *                       [ ]   [  sample ]   [     ]   [6] [5]   [4] [3]   [2] [1]
+ *                        |                     |
+ *      L1 I/D qualifier -*                     |      Count of events for each PMC.
+ *                                              |        p1, p2, p3, p4, p5, p6.
+ *                     nc - number of counters -*
+ *
+ * The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
+ * we want the low bit of each field to be added to any existing value.
+ *
+ * Everything else is a value field.
+ */
+
+#define CNST_FAB_MATCH_VAL(v)   (((v) & EVENT_THR_CTL_MASK) << 56)
+#define CNST_FAB_MATCH_MASK     CNST_FAB_MATCH_VAL(EVENT_THR_CTL_MASK)
+
+/* We just throw all the threshold bits into the constraint */
+#define CNST_THRESH_VAL(v)      (((v) & EVENT_THRESH_MASK) << 32)
+#define CNST_THRESH_MASK        CNST_THRESH_VAL(EVENT_THRESH_MASK)
+
+#define CNST_L1_QUAL_VAL(v)     (((v) & 3) << 22)
+#define CNST_L1_QUAL_MASK       CNST_L1_QUAL_VAL(3)
+
+#define CNST_SAMPLE_VAL(v)      (((v) & EVENT_SAMPLE_MASK) << 16)
+#define CNST_SAMPLE_MASK        CNST_SAMPLE_VAL(EVENT_SAMPLE_MASK)
+
+/*
+ * For NC we are counting up to 4 events. This requires three bits, and we need
+ * the fifth event to overflow and set the 4th bit. To achieve that we bias the
+ * fields by 3 in test_adder.
+ */
+#define CNST_NC_SHIFT           12
+#define CNST_NC_VAL             (1 << CNST_NC_SHIFT)
+#define CNST_NC_MASK            (8 << CNST_NC_SHIFT)
+#define POWER8_TEST_ADDER       (3 << CNST_NC_SHIFT)
+
+/*
+ * For the per-PMC fields we have two bits. The low bit is added, so if two
+ * events ask for the same PMC the sum will overflow, setting the high bit,
+ * indicating an error. So our mask sets the high bit.
+ */
+#define CNST_PMC_SHIFT(pmc)     ((pmc - 1) * 2)
+#define CNST_PMC_VAL(pmc)       (1 << CNST_PMC_SHIFT(pmc))
+#define CNST_PMC_MASK(pmc)      (2 << CNST_PMC_SHIFT(pmc))
+
+/* Our add_fields is defined as: */
+#define POWER8_ADD_FIELDS       \
+        CNST_PMC_VAL(1) | CNST_PMC_VAL(2) | CNST_PMC_VAL(3) | \
+        CNST_PMC_VAL(4) | CNST_PMC_VAL(5) | CNST_PMC_VAL(6) | CNST_NC_VAL
+
+
+/* Bits in MMCR1 for POWER8 */
+#define MMCR1_UNIT_SHIFT(pmc)           (60 - (4 * ((pmc) - 1)))
+#define MMCR1_COMBINE_SHIFT(pmc)        (35 - ((pmc) - 1))
+#define MMCR1_PMCSEL_SHIFT(pmc)         (24 - (((pmc) - 1)) * 8)
+#define MMCR1_DC_QUAL_SHIFT             47
+#define MMCR1_IC_QUAL_SHIFT             46
+
+/* Bits in MMCRA for POWER8 */
+#define MMCRA_SAMP_MODE_SHIFT           1
+#define MMCRA_SAMP_ELIG_SHIFT           4
+#define MMCRA_THR_CTL_SHIFT             8
+#define MMCRA_THR_SEL_SHIFT             16
+#define MMCRA_THR_CMP_SHIFT             32
+#define MMCRA_SDAR_MODE_TLB             (1ull << 42)
+
+
+static inline bool event_is_fab_match(u64 event)
+{
+        /* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */
+        event &= 0xff0fe;
+
+        /* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */
+        return (event == 0x30056 || event == 0x4f052);
+}
+
+static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
+{
+        unsigned int unit, pmc, cache;
+        unsigned long mask, value;
+
+        mask = value = 0;
+
+        pmc   = (event >> EVENT_PMC_SHIFT)       & EVENT_PMC_MASK;
+        unit  = (event >> EVENT_UNIT_SHIFT)      & EVENT_UNIT_MASK;
+        cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK;
+
+        if (pmc) {
+                if (pmc > 6)
+                        return -1;
+
+                mask  |= CNST_PMC_MASK(pmc);
+                value |= CNST_PMC_VAL(pmc);
+
+                if (pmc >= 5 && event != 0x500fa && event != 0x600f4)
+                        return -1;
+        }
+
+        if (pmc <= 4) {
+                /*
+                 * Add to number of counters in use. Note this includes events with
+                 * a PMC of 0 - they still need a PMC, it's just assigned later.
+                 * Don't count events on PMC 5 & 6, there is only one valid event
+                 * on each of those counters, and they are handled above.
+                 */
+                mask  |= CNST_NC_MASK;
+                value |= CNST_NC_VAL;
+        }
+
+        if (unit >= 6 && unit <= 9) {
+                /*
+                 * L2/L3 events contain a cache selector field, which is
+                 * supposed to be programmed into MMCRC. However MMCRC is only
+                 * HV writable, and there is no API for guest kernels to modify
+                 * it. The solution is for the hypervisor to initialise the
+                 * field to zeroes, and for us to only ever allow events that
+                 * have a cache selector of zero.
+                 */
+                if (cache)
+                        return -1;
+
+        } else if (event & EVENT_IS_L1) {
+                mask  |= CNST_L1_QUAL_MASK;
+                value |= CNST_L1_QUAL_VAL(cache);
+        }
+
+        if (event & EVENT_IS_MARKED) {
+                mask  |= CNST_SAMPLE_MASK;
+                value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
+        }
+
+        /*
+         * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
+         * the threshold control bits are used for the match value.
+         */
+        if (event_is_fab_match(event)) {
+                mask  |= CNST_FAB_MATCH_MASK;
+                value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
+        } else {
+                /*
+                 * Check the mantissa upper two bits are not zero, unless the
+                 * exponent is also zero. See the THRESH_CMP_MANTISSA doc.
+                 */
+                unsigned int cmp, exp;
+
+                cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
+                exp = cmp >> 7;
+
+                if (exp && (cmp & 0x60) == 0)
+                        return -1;
+
+                mask  |= CNST_THRESH_MASK;
+                value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
+        }
+
+        *maskp = mask;
+        *valp = value;
+
+        return 0;
+}
+
+static int power8_compute_mmcr(u64 event[], int n_ev,
+                               unsigned int hwc[], unsigned long mmcr[])
+{
+        unsigned long mmcra, mmcr1, unit, combine, psel, cache, val;
+        unsigned int pmc, pmc_inuse;
+        int i;
+
+        pmc_inuse = 0;
+
+        /* First pass to count resource use */
+        for (i = 0; i < n_ev; ++i) {
+                pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
+                if (pmc)
+                        pmc_inuse |= 1 << pmc;
+        }
+
+        /* In continous sampling mode, update SDAR on TLB miss */
+        mmcra = MMCRA_SDAR_MODE_TLB;
+        mmcr1 = 0;
+
+        /* Second pass: assign PMCs, set all MMCR1 fields */
+        for (i = 0; i < n_ev; ++i) {
+                pmc     = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
+                unit    = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
+                combine = (event[i] >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK;
+                psel    =  event[i] & EVENT_PSEL_MASK;
+
+                if (!pmc) {
+                        for (pmc = 1; pmc <= 4; ++pmc) {
+                                if (!(pmc_inuse & (1 << pmc)))
+                                        break;
+                        }
+
+                        pmc_inuse |= 1 << pmc;
+                }
+
+                if (pmc <= 4) {
+                        mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc);
+                        mmcr1 |= combine << MMCR1_COMBINE_SHIFT(pmc);
+                        mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc);
+                }
+
+                if (event[i] & EVENT_IS_L1) {
+                        cache = event[i] >> EVENT_CACHE_SEL_SHIFT;
+                        mmcr1 |= (cache & 1) << MMCR1_IC_QUAL_SHIFT;
+                        cache >>= 1;
+                        mmcr1 |= (cache & 1) << MMCR1_DC_QUAL_SHIFT;
+                }
+
+                if (event[i] & EVENT_IS_MARKED) {
+                        mmcra |= MMCRA_SAMPLE_ENABLE;
+
+                        val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
+                        if (val) {
+                                mmcra |= (val &  3) << MMCRA_SAMP_MODE_SHIFT;
+                                mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT;
+                        }
+                }
+
+                /*
+                 * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
+                 * the threshold bits are used for the match value.
+                 */
+                if (event_is_fab_match(event[i])) {
+                        mmcr1 |= (event[i] >> EVENT_THR_CTL_SHIFT) &
+                                  EVENT_THR_CTL_MASK;
+                } else {
+                        val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
+                        mmcra |= val << MMCRA_THR_CTL_SHIFT;
+                        val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
+                        mmcra |= val << MMCRA_THR_SEL_SHIFT;
+                        val = (event[i] >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
+                        mmcra |= val << MMCRA_THR_CMP_SHIFT;
+                }
+
+                hwc[i] = pmc - 1;
+        }
+
+        /* Return MMCRx values */
+        mmcr[0] = 0;
+
+        /* pmc_inuse is 1-based */
+        if (pmc_inuse & 2)
+                mmcr[0] = MMCR0_PMC1CE;
+
+        if (pmc_inuse & 0x7c)
+                mmcr[0] |= MMCR0_PMCjCE;
+
+        mmcr[1] = mmcr1;
+        mmcr[2] = mmcra;
+
+        return 0;
+}
+
+#define MAX_ALT 2
+
+/* Table of alternatives, sorted by column 0 */
+static const unsigned int event_alternatives[][MAX_ALT] = {
+        { 0x10134, 0x301e2 },           /* PM_MRK_ST_CMPL */
+        { 0x10138, 0x40138 },           /* PM_BR_MRK_2PATH */
+        { 0x18082, 0x3e05e },           /* PM_L3_CO_MEPF */
+        { 0x1d14e, 0x401e8 },           /* PM_MRK_DATA_FROM_L2MISS */
+        { 0x1e054, 0x4000a },           /* PM_CMPLU_STALL */
+        { 0x20036, 0x40036 },           /* PM_BR_2PATH */
+        { 0x200f2, 0x300f2 },           /* PM_INST_DISP */
+        { 0x200f4, 0x600f4 },           /* PM_RUN_CYC */
+        { 0x2013c, 0x3012e },           /* PM_MRK_FILT_MATCH */
+        { 0x3e054, 0x400f0 },           /* PM_LD_MISS_L1 */
+        { 0x400fa, 0x500fa },           /* PM_RUN_INST_CMPL */
+};
+
+/*
+ * Scan the alternatives table for a match and return the
+ * index into the alternatives table if found, else -1.
+ */
+static int find_alternative(u64 event)
+{
+        int i, j;
+
+        for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
+                if (event < event_alternatives[i][0])
+                        break;
+
+                for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
+                        if (event == event_alternatives[i][j])
+                                return i;
+        }
+
+        return -1;
+}
+
+static int power8_get_alternatives(u64 event, unsigned int flags, u64 alt[])
+{
+        int i, j, num_alt = 0;
+        u64 alt_event;
+
+        alt[num_alt++] = event;
+
+        i = find_alternative(event);
+        if (i >= 0) {
+                /* Filter out the original event, it's already in alt[0] */
+                for (j = 0; j < MAX_ALT; ++j) {
+                        alt_event = event_alternatives[i][j];
+                        if (alt_event && alt_event != event)
+                                alt[num_alt++] = alt_event;
+                }
+        }
+
+        if (flags & PPMU_ONLY_COUNT_RUN) {
+                /*
+                 * We're only counting in RUN state, so PM_CYC is equivalent to
+                 * PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL.
+                 */
+                j = num_alt;
+                for (i = 0; i < num_alt; ++i) {
+                        switch (alt[i]) {
+                        case 0x1e:      /* PM_CYC */
+                                alt[j++] = 0x600f4;     /* PM_RUN_CYC */
+                                break;
+                        case 0x600f4:   /* PM_RUN_CYC */
+                                alt[j++] = 0x1e;
+                                break;
+                        case 0x2:       /* PM_PPC_CMPL */
+                                alt[j++] = 0x500fa;     /* PM_RUN_INST_CMPL */
+                                break;
+                        case 0x500fa:   /* PM_RUN_INST_CMPL */
+                                alt[j++] = 0x2; /* PM_PPC_CMPL */
+                                break;
+                        }
+                }
+                num_alt = j;
+        }
+
+        return num_alt;
+}
+
+static void power8_disable_pmc(unsigned int pmc, unsigned long mmcr[])
+{
+        if (pmc <= 3)
+                mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));
+}
+
+PMU_FORMAT_ATTR(event,          "config:0-49");
+PMU_FORMAT_ATTR(pmcxsel,        "config:0-7");
+PMU_FORMAT_ATTR(mark,           "config:8");
+PMU_FORMAT_ATTR(combine,        "config:11");
+PMU_FORMAT_ATTR(unit,           "config:12-15");
+PMU_FORMAT_ATTR(pmc,            "config:16-19");
+PMU_FORMAT_ATTR(cache_sel,      "config:20-23");
+PMU_FORMAT_ATTR(sample_mode,    "config:24-28");
+PMU_FORMAT_ATTR(thresh_sel,     "config:29-31");
+PMU_FORMAT_ATTR(thresh_stop,    "config:32-35");
+PMU_FORMAT_ATTR(thresh_start,   "config:36-39");
+PMU_FORMAT_ATTR(thresh_cmp,     "config:40-49");
+
+static struct attribute *power8_pmu_format_attr[] = {
+        &format_attr_event.attr,
+        &format_attr_pmcxsel.attr,
+        &format_attr_mark.attr,
+        &format_attr_combine.attr,
+        &format_attr_unit.attr,
+        &format_attr_pmc.attr,
+        &format_attr_cache_sel.attr,
+        &format_attr_sample_mode.attr,
+        &format_attr_thresh_sel.attr,
+        &format_attr_thresh_stop.attr,
+        &format_attr_thresh_start.attr,
+        &format_attr_thresh_cmp.attr,
+        NULL,
+};
+
+struct attribute_group power8_pmu_format_group = {
+        .name = "format",
+        .attrs = power8_pmu_format_attr,
+};
+
+static const struct attribute_group *power8_pmu_attr_groups[] = {
+        &power8_pmu_format_group,
+        NULL,
+};
+
+static int power8_generic_events[] = {
+        [PERF_COUNT_HW_CPU_CYCLES] =                    PM_CYC,
+        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =       PM_GCT_NOSLOT_CYC,
+        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =        PM_CMPLU_STALL,
+        [PERF_COUNT_HW_INSTRUCTIONS] =                  PM_INST_CMPL,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =           PM_BRU_FIN,
+        [PERF_COUNT_HW_BRANCH_MISSES] =                 PM_BR_MPRED_CMPL,
+};
+
+static u64 power8_bhrb_filter_map(u64 branch_sample_type)
+{
+        u64 pmu_bhrb_filter = 0;
+        u64 br_privilege = branch_sample_type & ONLY_PLM;
+
+        /* BHRB and regular PMU events share the same prvillege state
+         * filter configuration. BHRB is always recorded along with a
+         * regular PMU event. So privilege state filter criteria for BHRB
+         * and the companion PMU events has to be the same. As a default
+         * "perf record" tool sets all privillege bits ON when no filter
+         * criteria is provided in the command line. So as along as all
+         * privillege bits are ON or they are OFF, we are good to go.
+         */
+        if ((br_privilege != 7) && (br_privilege != 0))
+                return -1;
+
+        /* No branch filter requested */
+        if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
+                return pmu_bhrb_filter;
+
+        /* Invalid branch filter options - HW does not support */
+        if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
+                return -1;
+
+        if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
+                return -1;
+
+        if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
+                pmu_bhrb_filter |= POWER8_MMCRA_IFM1;
+                return pmu_bhrb_filter;
+        }
+
+        /* Every thing else is unsupported */
+        return -1;
+}
+
+static void power8_config_bhrb(u64 pmu_bhrb_filter)
+{
+        /* Enable BHRB filter in PMU */
+        mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
+}
+
+static struct power_pmu power8_pmu = {
+        .name                   = "POWER8",
+        .n_counter              = 6,
+        .max_alternatives       = MAX_ALT + 1,
+        .add_fields             = POWER8_ADD_FIELDS,
+        .test_adder             = POWER8_TEST_ADDER,
+        .compute_mmcr           = power8_compute_mmcr,
+        .config_bhrb            = power8_config_bhrb,
+        .bhrb_filter_map        = power8_bhrb_filter_map,
+        .get_constraint         = power8_get_constraint,
+        .get_alternatives       = power8_get_alternatives,
+        .disable_pmc            = power8_disable_pmc,
+        .flags                  = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_BHRB,
+        .n_generic              = ARRAY_SIZE(power8_generic_events),
+        .generic_events         = power8_generic_events,
+        .attr_groups            = power8_pmu_attr_groups,
+        .bhrb_nr                = 32,
+};
+
+static int __init init_power8_pmu(void)
+{
+        if (!cur_cpu_spec->oprofile_cpu_type ||
+            strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power8"))
+                return -ENODEV;
+
+        return register_power_pmu(&power8_pmu);
+}
+early_initcall(init_power8_pmu);
diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig
index a392d12dd21f..bd40bbb15e14 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -20,7 +20,6 @@ config HOTFOOT
         bool "Hotfoot"
         depends on 40x
         default n
-        select 405EP
         select PPC40x_SIMPLE
         select PCI
         help
@@ -105,9 +104,6 @@ config 405GP
         select IBM405_ERR51
         select IBM_EMAC_ZMII
 
-config 405EP
-        bool
-
 config 405EX
         bool
         select IBM_EMAC_EMAC4
@@ -119,9 +115,6 @@ config 405EZ
         select IBM_EMAC_MAL_CLR_ICINTSTAT
         select IBM_EMAC_MAL_COMMON_ERR
 
-config 405GPR
-        bool
-
 config XILINX_VIRTEX
         bool
         select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index 0effe9f5a1ea..7be93367d92f 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -274,6 +274,8 @@ config 440EPX
         select IBM_EMAC_EMAC4
         select IBM_EMAC_RGMII
         select IBM_EMAC_ZMII
+        select USB_EHCI_BIG_ENDIAN_MMIO
+        select USB_EHCI_BIG_ENDIAN_DESC
 
 config 440GRX
         bool
diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig
index c16999802ecf..fc9c1cbfcb1d 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -7,6 +7,8 @@ config PPC_MPC512x
         select PPC_PCI_CHOICE
         select FSL_PCI if PCI
         select ARCH_WANT_OPTIONAL_GPIOLIB
+        select USB_EHCI_BIG_ENDIAN_MMIO
+        select USB_EHCI_BIG_ENDIAN_DESC
 
 config MPC5121_ADS
         bool "Freescale MPC5121E ADS"
@@ -15,16 +17,16 @@ config MPC5121_ADS
         help
           This option enables support for the MPC5121E ADS board.
 
-config MPC5121_GENERIC
-        bool "Generic support for simple MPC5121 based boards"
+config MPC512x_GENERIC
+        bool "Generic support for simple MPC512x based boards"
         depends on PPC_MPC512x
         select DEFAULT_UIMAGE
         help
-          This option enables support for simple MPC5121 based boards
+          This option enables support for simple MPC512x based boards
           which do not need custom platform specific setup.
 
           Compatible boards include:  Protonic LVT base boards (ZANMCU
-          and VICVT2).
+          and VICVT2), Freescale MPC5125 Tower system.
 
 config PDM360NG
         bool "ifm PDM360NG board"
diff --git a/arch/powerpc/platforms/512x/Makefile b/arch/powerpc/platforms/512x/Makefile
index 4efc1c4b6fb5..72fb9340e09f 100644
--- a/arch/powerpc/platforms/512x/Makefile
+++ b/arch/powerpc/platforms/512x/Makefile
@@ -3,5 +3,5 @@
 #
 obj-y                           += clock.o mpc512x_shared.o
 obj-$(CONFIG_MPC5121_ADS)       += mpc5121_ads.o mpc5121_ads_cpld.o
-obj-$(CONFIG_MPC5121_GENERIC)   += mpc5121_generic.o
+obj-$(CONFIG_MPC512x_GENERIC)   += mpc512x_generic.o
 obj-$(CONFIG_PDM360NG)          += pdm360ng.o
diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c
index 52d57d281724..e504166e089a 100644
--- a/arch/powerpc/platforms/512x/clock.c
+++ b/arch/powerpc/platforms/512x/clock.c
@@ -29,6 +29,8 @@
 #include <asm/mpc5121.h>
 #include <asm/clk_interface.h>
 
+#include "mpc512x.h"
+
 #undef CLK_DEBUG
 
 static int clocks_initialized;
@@ -683,8 +685,13 @@ static void psc_clks_init(void)
         struct device_node *np;
         struct platform_device *ofdev;
         u32 reg;
+        const char *psc_compat;
+
+        psc_compat = mpc512x_select_psc_compat();
+        if (!psc_compat)
+                return;
 
-        for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
+        for_each_compatible_node(np, NULL, psc_compat) {
                 if (!of_property_read_u32(np, "reg", &reg)) {
                         int pscnum = (reg & 0xf00) >> 8;
                         struct clk *clk = psc_dev_clk(pscnum);
diff --git a/arch/powerpc/platforms/512x/mpc512x.h b/arch/powerpc/platforms/512x/mpc512x.h
index c32b399eb952..0a8e60023944 100644
--- a/arch/powerpc/platforms/512x/mpc512x.h
+++ b/arch/powerpc/platforms/512x/mpc512x.h
@@ -15,6 +15,7 @@ extern void __init mpc512x_init_IRQ(void);
 extern void __init mpc512x_init(void);
 extern int __init mpc5121_clk_init(void);
 void __init mpc512x_declare_of_platform_devices(void);
+extern const char *mpc512x_select_psc_compat(void);
 extern void mpc512x_restart(char *cmd);
 
 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
diff --git a/arch/powerpc/platforms/512x/mpc5121_generic.c b/arch/powerpc/platforms/512x/mpc512x_generic.c
index ca1ca6669990..5fb919b30924 100644
--- a/arch/powerpc/platforms/512x/mpc5121_generic.c
+++ b/arch/powerpc/platforms/512x/mpc512x_generic.c
@@ -4,7 +4,7 @@
  * Author: John Rigby, <jrigby@freescale.com>
  *
  * Description:
- * MPC5121 SoC setup
+ * MPC512x SoC setup
  *
  * This is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by
@@ -28,20 +28,22 @@
  */
 static const char * const board[] __initconst = {
         "prt,prtlvt",
+        "fsl,mpc5125ads",
+        "ifm,ac14xx",
         NULL
 };
 
 /*
  * Called very early, MMU is off, device-tree isn't unflattened
  */
-static int __init mpc5121_generic_probe(void)
+static int __init mpc512x_generic_probe(void)
 {
         return of_flat_dt_match(of_get_flat_dt_root(), board);
 }
 
-define_machine(mpc5121_generic) {
-        .name                   = "MPC5121 generic",
-        .probe                  = mpc5121_generic_probe,
+define_machine(mpc512x_generic) {
+        .name                   = "MPC512x generic",
+        .probe                  = mpc512x_generic_probe,
         .init                   = mpc512x_init,
         .init_early             = mpc512x_init_diu,
         .setup_arch             = mpc512x_setup_diu,
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index d30235b7e3f7..6eb94ab99d39 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -172,12 +172,9 @@ static struct fsl_diu_shared_fb __attribute__ ((__aligned__(8))) diu_shared_fb;
 
 static inline void mpc512x_free_bootmem(struct page *page)
 {
-        __ClearPageReserved(page);
         BUG_ON(PageTail(page));
         BUG_ON(atomic_read(&page->_count) > 1);
-        atomic_set(&page->_count, 1);
-        __free_page(page);
-        totalram_pages++;
+        free_reserved_page(page);
 }
 
 void mpc512x_release_bootmem(void)
@@ -330,26 +327,34 @@ void __init mpc512x_init_IRQ(void)
 static struct of_device_id __initdata of_bus_ids[] = {
         { .compatible = "fsl,mpc5121-immr", },
         { .compatible = "fsl,mpc5121-localbus", },
+        { .compatible = "fsl,mpc5121-mbx", },
+        { .compatible = "fsl,mpc5121-nfc", },
+        { .compatible = "fsl,mpc5121-sram", },
+        { .compatible = "fsl,mpc5121-pci", },
+        { .compatible = "gpio-leds", },
         {},
 };
 
 void __init mpc512x_declare_of_platform_devices(void)
 {
-        struct device_node *np;
-
         if (of_platform_bus_probe(NULL, of_bus_ids, NULL))
                 printk(KERN_ERR __FILE__ ": "
                         "Error while probing of_platform bus\n");
-
-        np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-nfc");
-        if (np) {
-                of_platform_device_create(np, NULL, NULL);
-                of_node_put(np);
-        }
 }
 
 #define DEFAULT_FIFO_SIZE 16
 
+const char *mpc512x_select_psc_compat(void)
+{
+        if (of_machine_is_compatible("fsl,mpc5121"))
+                return "fsl,mpc5121-psc";
+
+        if (of_machine_is_compatible("fsl,mpc5125"))
+                return "fsl,mpc5125-psc";
+
+        return NULL;
+}
+
 static unsigned int __init get_fifo_size(struct device_node *np,
                                          char *prop_name)
 {
@@ -375,9 +380,16 @@ void __init mpc512x_psc_fifo_init(void)
         void __iomem *psc;
         unsigned int tx_fifo_size;
         unsigned int rx_fifo_size;
+        const char *psc_compat;
         int fifobase = 0; /* current fifo address in 32 bit words */
 
-        for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
+        psc_compat = mpc512x_select_psc_compat();
+        if (!psc_compat) {
+                pr_err("%s: no compatible devices found\n", __func__);
+                return;
+        }
+
+        for_each_compatible_node(np, NULL, psc_compat) {
                 tx_fifo_size = get_fifo_size(np, "fsl,tx-fifo-size");
                 rx_fifo_size = get_fifo_size(np, "fsl,rx-fifo-size");
 
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index a0dcd577fb0d..8f02b05f4c96 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -305,6 +305,40 @@ config PPC_QEMU_E500
           unset based on the emulated CPU (or actual host CPU in the case
           of KVM).
 
+if PPC64
+
+config T4240_QDS
+        bool "Freescale T4240 QDS"
+        select DEFAULT_UIMAGE
+        select E500
+        select PPC_E500MC
+        select PHYS_64BIT
+        select SWIOTLB
+        select ARCH_REQUIRE_GPIOLIB
+        select GPIO_MPC8XXX
+        select HAS_RAPIDIO
+        select PPC_EPAPR_HV_PIC
+        help
+          This option enables support for the T4240 QDS board
+
+config B4_QDS
+        bool "Freescale B4 QDS"
+        select DEFAULT_UIMAGE
+        select E500
+        select PPC_E500MC
+        select PHYS_64BIT
+        select SWIOTLB
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        select HAS_RAPIDIO
+        select PPC_EPAPR_HV_PIC
+        help
+          This option enables support for the B4 QDS board
+          The B4 application development system B4 QDS is a complete
+          debugging environment intended for engineers developing
+          applications for the B4.
+
+endif
 endif # FSL_SOC_BOOKE
 
 config TQM85xx
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 07d0dbb141c0..2eab37ea4a9d 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -22,6 +22,8 @@ obj-$(CONFIG_P3041_DS)    += p3041_ds.o corenet_ds.o
 obj-$(CONFIG_P4080_DS)    += p4080_ds.o corenet_ds.o
 obj-$(CONFIG_P5020_DS)    += p5020_ds.o corenet_ds.o
 obj-$(CONFIG_P5040_DS)    += p5040_ds.o corenet_ds.o
+obj-$(CONFIG_T4240_QDS)   += t4240_qds.o corenet_ds.o
+obj-$(CONFIG_B4_QDS)      += b4_qds.o corenet_ds.o
 obj-$(CONFIG_STX_GP3)     += stx_gp3.o
 obj-$(CONFIG_TQM85xx)     += tqm85xx.o
 obj-$(CONFIG_SBC8548)     += sbc8548.o
diff --git a/arch/powerpc/platforms/85xx/b4_qds.c b/arch/powerpc/platforms/85xx/b4_qds.c
new file mode 100644
index 000000000000..0c6702f8b88e
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/b4_qds.c
@@ -0,0 +1,102 @@
+/*
+ * B4 QDS Setup
+ * Should apply for QDS platform of B4860 and it's personalities.
+ * viz B4860/B4420/B4220QDS
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/phy.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <linux/of_platform.h>
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include <asm/ehv_pic.h>
+
+#include "corenet_ds.h"
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init b4_qds_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+#ifdef CONFIG_SMP
+        extern struct smp_ops_t smp_85xx_ops;
+#endif
+
+        if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS")) ||
+                (of_flat_dt_is_compatible(root, "fsl,B4420QDS")) ||
+                        (of_flat_dt_is_compatible(root, "fsl,B4220QDS")))
+                return 1;
+
+        /* Check if we're running under the Freescale hypervisor */
+        if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS-hv")) ||
+                (of_flat_dt_is_compatible(root, "fsl,B4420QDS-hv")) ||
+                        (of_flat_dt_is_compatible(root, "fsl,B4220QDS-hv"))) {
+                ppc_md.init_IRQ = ehv_pic_init;
+                ppc_md.get_irq = ehv_pic_get_irq;
+                ppc_md.restart = fsl_hv_restart;
+                ppc_md.power_off = fsl_hv_halt;
+                ppc_md.halt = fsl_hv_halt;
+#ifdef CONFIG_SMP
+                /*
+                 * Disable the timebase sync operations because we can't write
+                 * to the timebase registers under the hypervisor.
+                  */
+                smp_85xx_ops.give_timebase = NULL;
+                smp_85xx_ops.take_timebase = NULL;
+#endif
+                return 1;
+        }
+
+        return 0;
+}
+
+define_machine(b4_qds) {
+        .name                   = "B4 QDS",
+        .probe                  = b4_qds_probe,
+        .setup_arch             = corenet_ds_setup_arch,
+        .init_IRQ               = corenet_ds_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
+#ifdef CONFIG_PPC64
+        .get_irq                = mpic_get_irq,
+#else
+        .get_irq                = mpic_get_coreint_irq,
+#endif
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+#ifdef CONFIG_PPC64
+        .power_save             = book3e_idle,
+#else
+        .power_save             = e500_idle,
+#endif
+};
+
+machine_arch_initcall(b4_qds, corenet_ds_publish_devices);
+
+#ifdef CONFIG_SWIOTLB
+machine_arch_initcall(b4_qds, swiotlb_setup_bus_notifier);
+#endif
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c
index 6f355d8c92f6..c59c617eee93 100644
--- a/arch/powerpc/platforms/85xx/corenet_ds.c
+++ b/arch/powerpc/platforms/85xx/corenet_ds.c
@@ -40,7 +40,7 @@ void __init corenet_ds_pic_init(void)
         if (ppc_md.get_irq == mpic_get_coreint_irq)
                 flags |= MPIC_ENABLE_COREINT;
 
-        mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC  ");
+        mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC  ");
         BUG_ON(mpic == NULL);
 
         mpic_init(mpic);
@@ -83,6 +83,9 @@ static const struct of_device_id of_device_ids[] = {
         {
                 .compatible     = "fsl,qoriq-pcie-v2.4",
         },
+        {
+                .compatible     = "fsl,qoriq-pcie-v3.0",
+        },
         /* The following two are for the Freescale hypervisor */
         {
                 .name           = "hypervisor",
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index 148c2f2d9780..6a1759939c6b 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -201,7 +201,7 @@ static int __cpuinit smp_85xx_kick_cpu(int nr)
                  * We don't set the BPTR register here since it already points
                  * to the boot page properly.
                  */
-                mpic_reset_core(hw_cpu);
+                mpic_reset_core(nr);
 
                 /*
                  * wait until core is ready...
diff --git a/arch/powerpc/platforms/85xx/t4240_qds.c b/arch/powerpc/platforms/85xx/t4240_qds.c
new file mode 100644
index 000000000000..5998e9f33304
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/t4240_qds.c
@@ -0,0 +1,98 @@
+/*
+ * T4240 QDS Setup
+ *
+ * Maintained by Kumar Gala (see MAINTAINERS for contact information)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/phy.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <linux/of_platform.h>
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include <asm/ehv_pic.h>
+
+#include "corenet_ds.h"
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init t4240_qds_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+#ifdef CONFIG_SMP
+        extern struct smp_ops_t smp_85xx_ops;
+#endif
+
+        if (of_flat_dt_is_compatible(root, "fsl,T4240QDS"))
+                return 1;
+
+        /* Check if we're running under the Freescale hypervisor */
+        if (of_flat_dt_is_compatible(root, "fsl,T4240QDS-hv")) {
+                ppc_md.init_IRQ = ehv_pic_init;
+                ppc_md.get_irq = ehv_pic_get_irq;
+                ppc_md.restart = fsl_hv_restart;
+                ppc_md.power_off = fsl_hv_halt;
+                ppc_md.halt = fsl_hv_halt;
+#ifdef CONFIG_SMP
+                /*
+                 * Disable the timebase sync operations because we can't write
+                 * to the timebase registers under the hypervisor.
+                  */
+                smp_85xx_ops.give_timebase = NULL;
+                smp_85xx_ops.take_timebase = NULL;
+#endif
+                return 1;
+        }
+
+        return 0;
+}
+
+define_machine(t4240_qds) {
+        .name                   = "T4240 QDS",
+        .probe                  = t4240_qds_probe,
+        .setup_arch             = corenet_ds_setup_arch,
+        .init_IRQ               = corenet_ds_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
+#ifdef CONFIG_PPC64
+        .get_irq                = mpic_get_irq,
+#else
+        .get_irq                = mpic_get_coreint_irq,
+#endif
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+#ifdef CONFIG_PPC64
+        .power_save             = book3e_idle,
+#else
+        .power_save             = e500_idle,
+#endif
+};
+
+machine_arch_initcall(t4240_qds, corenet_ds_publish_devices);
+
+#ifdef CONFIG_SWIOTLB
+machine_arch_initcall(t4240_qds, swiotlb_setup_bus_notifier);
+#endif
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 52de8bccfb30..34d224be93ba 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -6,7 +6,6 @@ source "arch/powerpc/platforms/chrp/Kconfig"
 source "arch/powerpc/platforms/512x/Kconfig"
 source "arch/powerpc/platforms/52xx/Kconfig"
 source "arch/powerpc/platforms/powermac/Kconfig"
-source "arch/powerpc/platforms/prep/Kconfig"
 source "arch/powerpc/platforms/maple/Kconfig"
 source "arch/powerpc/platforms/pasemi/Kconfig"
 source "arch/powerpc/platforms/ps3/Kconfig"
@@ -233,7 +232,7 @@ endmenu
 
 config PPC601_SYNC_FIX
         bool "Workarounds for PPC601 bugs"
-        depends on 6xx && (PPC_PREP || PPC_PMAC)
+        depends on 6xx && PPC_PMAC
         help
           Some versions of the PPC601 (the first PowerPC chip) have bugs which
           mean that extra synchronization instructions are required near
@@ -344,7 +343,6 @@ config FSL_ULI1575
 
 config CPM
         bool
-        select PPC_CLOCK
 
 config OF_RTC
         bool
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 18e3b76c78d7..54f3936001aa 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -230,7 +230,7 @@ config PHYS_64BIT
 
 config ALTIVEC
         bool "AltiVec Support"
-        depends on 6xx || POWER4
+        depends on 6xx || POWER4 || (PPC_E500MC && PPC64)
         ---help---
           This option enables kernel support for the Altivec extensions to the
           PowerPC processor. The kernel currently supports saving and restoring
diff --git a/arch/powerpc/platforms/cell/Kconfig b/arch/powerpc/platforms/cell/Kconfig
index 53aaefeb3386..9978f594cac0 100644
--- a/arch/powerpc/platforms/cell/Kconfig
+++ b/arch/powerpc/platforms/cell/Kconfig
@@ -113,34 +113,10 @@ config CBE_THERM
         default m
         depends on CBE_RAS && SPU_BASE
 
-config CBE_CPUFREQ
-        tristate "CBE frequency scaling"
-        depends on CBE_RAS && CPU_FREQ
-        default m
-        help
-          This adds the cpufreq driver for Cell BE processors.
-          For details, take a look at <file:Documentation/cpu-freq/>.
-          If you don't have such processor, say N
-
-config CBE_CPUFREQ_PMI_ENABLE
-        bool "CBE frequency scaling using PMI interface"
-        depends on CBE_CPUFREQ
-        default n
-        help
-          Select this, if you want to use the PMI interface
-          to switch frequencies. Using PMI, the
-          processor will not only be able to run at lower speed,
-          but also at lower core voltage.
-
-config CBE_CPUFREQ_PMI
-        tristate
-        depends on CBE_CPUFREQ_PMI_ENABLE
-        default CBE_CPUFREQ
-
 config PPC_PMI
         tristate
         default y
-        depends on CBE_CPUFREQ_PMI || PPC_IBM_CELL_POWERBUTTON
+        depends on CPU_FREQ_CBE_PMI || PPC_IBM_CELL_POWERBUTTON
         help
           PMI (Platform Management Interrupt) is a way to
           communicate with the BMC (Baseboard Management Controller).
diff --git a/arch/powerpc/platforms/cell/Makefile b/arch/powerpc/platforms/cell/Makefile
index a4a89350bcfc..fe053e7c73ee 100644
--- a/arch/powerpc/platforms/cell/Makefile
+++ b/arch/powerpc/platforms/cell/Makefile
@@ -5,9 +5,6 @@ obj-$(CONFIG_PPC_CELL_NATIVE)		+= iommu.o setup.o spider-pic.o \
 obj-$(CONFIG_CBE_RAS)                   += ras.o
 
 obj-$(CONFIG_CBE_THERM)                 += cbe_thermal.o
-obj-$(CONFIG_CBE_CPUFREQ_PMI)           += cbe_cpufreq_pmi.o
-obj-$(CONFIG_CBE_CPUFREQ)               += cbe-cpufreq.o
-cbe-cpufreq-y                           += cbe_cpufreq_pervasive.o cbe_cpufreq.o
 obj-$(CONFIG_CBE_CPUFREQ_SPU_GOVERNOR)  += cpufreq_spudemand.o
 
 obj-$(CONFIG_PPC_IBM_CELL_POWERBUTTON)  += cbe_powerbutton.o
diff --git a/arch/powerpc/platforms/cell/beat_htab.c b/arch/powerpc/platforms/cell/beat_htab.c
index 0f6f83988b3d..246e1d8b3af3 100644
--- a/arch/powerpc/platforms/cell/beat_htab.c
+++ b/arch/powerpc/platforms/cell/beat_htab.c
@@ -90,7 +90,7 @@ static inline unsigned int beat_read_mask(unsigned hpte_group)
 static long beat_lpar_hpte_insert(unsigned long hpte_group,
                                   unsigned long vpn, unsigned long pa,
                                   unsigned long rflags, unsigned long vflags,
-                                  int psize, int ssize)
+                                  int psize, int apsize, int ssize)
 {
         unsigned long lpar_rc;
         u64 hpte_v, hpte_r, slot;
@@ -103,9 +103,9 @@ static long beat_lpar_hpte_insert(unsigned long hpte_group,
                         "rflags=%lx, vflags=%lx, psize=%d)\n",
                 hpte_group, va, pa, rflags, vflags, psize);
 
-        hpte_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M) |
+        hpte_v = hpte_encode_v(vpn, psize, apsize, MMU_SEGSIZE_256M) |
                 vflags | HPTE_V_VALID;
-        hpte_r = hpte_encode_r(pa, psize) | rflags;
+        hpte_r = hpte_encode_r(pa, psize, apsize) | rflags;
 
         if (!(vflags & HPTE_V_BOLTED))
                 DBG_LOW(" hpte_v=%016lx, hpte_r=%016lx\n", hpte_v, hpte_r);
@@ -191,7 +191,7 @@ static long beat_lpar_hpte_updatepp(unsigned long slot,
         u64 dummy0, dummy1;
         unsigned long want_v;
 
-        want_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M);
+        want_v = hpte_encode_avpn(vpn, psize, MMU_SEGSIZE_256M);
 
         DBG_LOW("    update: "
                 "avpnv=%016lx, slot=%016lx, psize: %d, newpp %016lx ... ",
@@ -228,7 +228,7 @@ static long beat_lpar_hpte_find(unsigned long vpn, int psize)
         unsigned long want_v, hpte_v;
 
         hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, MMU_SEGSIZE_256M);
-        want_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M);
+        want_v = hpte_encode_avpn(vpn, psize, MMU_SEGSIZE_256M);
 
         for (j = 0; j < 2; j++) {
                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
@@ -283,7 +283,7 @@ static void beat_lpar_hpte_invalidate(unsigned long slot, unsigned long vpn,
 
         DBG_LOW("    inval : slot=%lx, va=%016lx, psize: %d, local: %d\n",
                 slot, va, psize, local);
-        want_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M);
+        want_v = hpte_encode_avpn(vpn, psize, MMU_SEGSIZE_256M);
 
         raw_spin_lock_irqsave(&beat_htab_lock, flags);
         dummy1 = beat_lpar_hpte_getword0(slot);
@@ -314,7 +314,7 @@ void __init hpte_init_beat(void)
 static long beat_lpar_hpte_insert_v3(unsigned long hpte_group,
                                   unsigned long vpn, unsigned long pa,
                                   unsigned long rflags, unsigned long vflags,
-                                  int psize, int ssize)
+                                  int psize, int apsize, int ssize)
 {
         unsigned long lpar_rc;
         u64 hpte_v, hpte_r, slot;
@@ -327,9 +327,9 @@ static long beat_lpar_hpte_insert_v3(unsigned long hpte_group,
                         "rflags=%lx, vflags=%lx, psize=%d)\n",
                 hpte_group, vpn, pa, rflags, vflags, psize);
 
-        hpte_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M) |
+        hpte_v = hpte_encode_v(vpn, psize, apsize, MMU_SEGSIZE_256M) |
                 vflags | HPTE_V_VALID;
-        hpte_r = hpte_encode_r(pa, psize) | rflags;
+        hpte_r = hpte_encode_r(pa, psize, apsize) | rflags;
 
         if (!(vflags & HPTE_V_BOLTED))
                 DBG_LOW(" hpte_v=%016lx, hpte_r=%016lx\n", hpte_v, hpte_r);
@@ -372,8 +372,8 @@ static long beat_lpar_hpte_updatepp_v3(unsigned long slot,
         unsigned long want_v;
         unsigned long pss;
 
-        want_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M);
-        pss = (psize == MMU_PAGE_4K) ? -1UL : mmu_psize_defs[psize].penc;
+        want_v = hpte_encode_avpn(vpn, psize, MMU_SEGSIZE_256M);
+        pss = (psize == MMU_PAGE_4K) ? -1UL : mmu_psize_defs[psize].penc[psize];
 
         DBG_LOW("    update: "
                 "avpnv=%016lx, slot=%016lx, psize: %d, newpp %016lx ... ",
@@ -402,8 +402,8 @@ static void beat_lpar_hpte_invalidate_v3(unsigned long slot, unsigned long vpn,
 
         DBG_LOW("    inval : slot=%lx, vpn=%016lx, psize: %d, local: %d\n",
                 slot, vpn, psize, local);
-        want_v = hpte_encode_v(vpn, psize, MMU_SEGSIZE_256M);
-        pss = (psize == MMU_PAGE_4K) ? -1UL : mmu_psize_defs[psize].penc;
+        want_v = hpte_encode_avpn(vpn, psize, MMU_SEGSIZE_256M);
+        pss = (psize == MMU_PAGE_4K) ? -1UL : mmu_psize_defs[psize].penc[psize];
 
         lpar_rc = beat_invalidate_htab_entry3(0, slot, want_v, pss);
 
diff --git a/arch/powerpc/platforms/cell/cbe_cpufreq.c b/arch/powerpc/platforms/cell/cbe_cpufreq.c
deleted file mode 100644
index d4c39e32f147..000000000000
--- a/arch/powerpc/platforms/cell/cbe_cpufreq.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * cpufreq driver for the cell processor
- *
- * (C) Copyright IBM Deutschland Entwicklung GmbH 2005-2007
- *
- * Author: Christian Krafft <krafft@de.ibm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/cpufreq.h>
-#include <linux/module.h>
-#include <linux/of_platform.h>
-
-#include <asm/machdep.h>
-#include <asm/prom.h>
-#include <asm/cell-regs.h>
-#include "cbe_cpufreq.h"
-
-static DEFINE_MUTEX(cbe_switch_mutex);
-
-
-/* the CBE supports an 8 step frequency scaling */
-static struct cpufreq_frequency_table cbe_freqs[] = {
-        {1,     0},
-        {2,     0},
-        {3,     0},
-        {4,     0},
-        {5,     0},
-        {6,     0},
-        {8,     0},
-        {10,    0},
-        {0,     CPUFREQ_TABLE_END},
-};
-
-/*
- * hardware specific functions
- */
-
-static int set_pmode(unsigned int cpu, unsigned int slow_mode)
-{
-        int rc;
-
-        if (cbe_cpufreq_has_pmi)
-                rc = cbe_cpufreq_set_pmode_pmi(cpu, slow_mode);
-        else
-                rc = cbe_cpufreq_set_pmode(cpu, slow_mode);
-
-        pr_debug("register contains slow mode %d\n", cbe_cpufreq_get_pmode(cpu));
-
-        return rc;
-}
-
-/*
- * cpufreq functions
- */
-
-static int cbe_cpufreq_cpu_init(struct cpufreq_policy *policy)
-{
-        const u32 *max_freqp;
-        u32 max_freq;
-        int i, cur_pmode;
-        struct device_node *cpu;
-
-        cpu = of_get_cpu_node(policy->cpu, NULL);
-
-        if (!cpu)
-                return -ENODEV;
-
-        pr_debug("init cpufreq on CPU %d\n", policy->cpu);
-
-        /*
-         * Let's check we can actually get to the CELL regs
-         */
-        if (!cbe_get_cpu_pmd_regs(policy->cpu) ||
-            !cbe_get_cpu_mic_tm_regs(policy->cpu)) {
-                pr_info("invalid CBE regs pointers for cpufreq\n");
-                return -EINVAL;
-        }
-
-        max_freqp = of_get_property(cpu, "clock-frequency", NULL);
-
-        of_node_put(cpu);
-
-        if (!max_freqp)
-                return -EINVAL;
-
-        /* we need the freq in kHz */
-        max_freq = *max_freqp / 1000;
-
-        pr_debug("max clock-frequency is at %u kHz\n", max_freq);
-        pr_debug("initializing frequency table\n");
-
-        /* initialize frequency table */
-        for (i=0; cbe_freqs[i].frequency!=CPUFREQ_TABLE_END; i++) {
-                cbe_freqs[i].frequency = max_freq / cbe_freqs[i].index;
-                pr_debug("%d: %d\n", i, cbe_freqs[i].frequency);
-        }
-
-        /* if DEBUG is enabled set_pmode() measures the latency
-         * of a transition */
-        policy->cpuinfo.transition_latency = 25000;
-
-        cur_pmode = cbe_cpufreq_get_pmode(policy->cpu);
-        pr_debug("current pmode is at %d\n",cur_pmode);
-
-        policy->cur = cbe_freqs[cur_pmode].frequency;
-
-#ifdef CONFIG_SMP
-        cpumask_copy(policy->cpus, cpu_sibling_mask(policy->cpu));
-#endif
-
-        cpufreq_frequency_table_get_attr(cbe_freqs, policy->cpu);
-
-        /* this ensures that policy->cpuinfo_min
-         * and policy->cpuinfo_max are set correctly */
-        return cpufreq_frequency_table_cpuinfo(policy, cbe_freqs);
-}
-
-static int cbe_cpufreq_cpu_exit(struct cpufreq_policy *policy)
-{
-        cpufreq_frequency_table_put_attr(policy->cpu);
-        return 0;
-}
-
-static int cbe_cpufreq_verify(struct cpufreq_policy *policy)
-{
-        return cpufreq_frequency_table_verify(policy, cbe_freqs);
-}
-
-static int cbe_cpufreq_target(struct cpufreq_policy *policy,
-                              unsigned int target_freq,
-                              unsigned int relation)
-{
-        int rc;
-        struct cpufreq_freqs freqs;
-        unsigned int cbe_pmode_new;
-
-        cpufreq_frequency_table_target(policy,
-                                       cbe_freqs,
-                                       target_freq,
-                                       relation,
-                                       &cbe_pmode_new);
-
-        freqs.old = policy->cur;
-        freqs.new = cbe_freqs[cbe_pmode_new].frequency;
-        freqs.cpu = policy->cpu;
-
-        mutex_lock(&cbe_switch_mutex);
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
-        pr_debug("setting frequency for cpu %d to %d kHz, " \
-                 "1/%d of max frequency\n",
-                 policy->cpu,
-                 cbe_freqs[cbe_pmode_new].frequency,
-                 cbe_freqs[cbe_pmode_new].index);
-
-        rc = set_pmode(policy->cpu, cbe_pmode_new);
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-        mutex_unlock(&cbe_switch_mutex);
-
-        return rc;
-}
-
-static struct cpufreq_driver cbe_cpufreq_driver = {
-        .verify         = cbe_cpufreq_verify,
-        .target         = cbe_cpufreq_target,
-        .init           = cbe_cpufreq_cpu_init,
-        .exit           = cbe_cpufreq_cpu_exit,
-        .name           = "cbe-cpufreq",
-        .owner          = THIS_MODULE,
-        .flags          = CPUFREQ_CONST_LOOPS,
-};
-
-/*
- * module init and destoy
- */
-
-static int __init cbe_cpufreq_init(void)
-{
-        if (!machine_is(cell))
-                return -ENODEV;
-
-        return cpufreq_register_driver(&cbe_cpufreq_driver);
-}
-
-static void __exit cbe_cpufreq_exit(void)
-{
-        cpufreq_unregister_driver(&cbe_cpufreq_driver);
-}
-
-module_init(cbe_cpufreq_init);
-module_exit(cbe_cpufreq_exit);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Christian Krafft <krafft@de.ibm.com>");
diff --git a/arch/powerpc/platforms/cell/cbe_cpufreq.h b/arch/powerpc/platforms/cell/cbe_cpufreq.h
deleted file mode 100644
index c1d86bfa92ff..000000000000
--- a/arch/powerpc/platforms/cell/cbe_cpufreq.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * cbe_cpufreq.h
- *
- * This file contains the definitions used by the cbe_cpufreq driver.
- *
- * (C) Copyright IBM Deutschland Entwicklung GmbH 2005-2007
- *
- * Author: Christian Krafft <krafft@de.ibm.com>
- *
- */
-
-#include <linux/cpufreq.h>
-#include <linux/types.h>
-
-int cbe_cpufreq_set_pmode(int cpu, unsigned int pmode);
-int cbe_cpufreq_get_pmode(int cpu);
-
-int cbe_cpufreq_set_pmode_pmi(int cpu, unsigned int pmode);
-
-#if defined(CONFIG_CBE_CPUFREQ_PMI) || defined(CONFIG_CBE_CPUFREQ_PMI_MODULE)
-extern bool cbe_cpufreq_has_pmi;
-#else
-#define cbe_cpufreq_has_pmi (0)
-#endif
diff --git a/arch/powerpc/platforms/cell/cbe_cpufreq_pervasive.c b/arch/powerpc/platforms/cell/cbe_cpufreq_pervasive.c
deleted file mode 100644
index 20472e487b6f..000000000000
--- a/arch/powerpc/platforms/cell/cbe_cpufreq_pervasive.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * pervasive backend for the cbe_cpufreq driver
- *
- * This driver makes use of the pervasive unit to
- * engage the desired frequency.
- *
- * (C) Copyright IBM Deutschland Entwicklung GmbH 2005-2007
- *
- * Author: Christian Krafft <krafft@de.ibm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/time.h>
-#include <asm/machdep.h>
-#include <asm/hw_irq.h>
-#include <asm/cell-regs.h>
-
-#include "cbe_cpufreq.h"
-
-/* to write to MIC register */
-static u64 MIC_Slow_Fast_Timer_table[] = {
-        [0 ... 7] = 0x007fc00000000000ull,
-};
-
-/* more values for the MIC */
-static u64 MIC_Slow_Next_Timer_table[] = {
-        0x0000240000000000ull,
-        0x0000268000000000ull,
-        0x000029C000000000ull,
-        0x00002D0000000000ull,
-        0x0000300000000000ull,
-        0x0000334000000000ull,
-        0x000039C000000000ull,
-        0x00003FC000000000ull,
-};
-
-
-int cbe_cpufreq_set_pmode(int cpu, unsigned int pmode)
-{
-        struct cbe_pmd_regs __iomem *pmd_regs;
-        struct cbe_mic_tm_regs __iomem *mic_tm_regs;
-        unsigned long flags;
-        u64 value;
-#ifdef DEBUG
-        long time;
-#endif
-
-        local_irq_save(flags);
-
-        mic_tm_regs = cbe_get_cpu_mic_tm_regs(cpu);
-        pmd_regs = cbe_get_cpu_pmd_regs(cpu);
-
-#ifdef DEBUG
-        time = jiffies;
-#endif
-
-        out_be64(&mic_tm_regs->slow_fast_timer_0, MIC_Slow_Fast_Timer_table[pmode]);
-        out_be64(&mic_tm_regs->slow_fast_timer_1, MIC_Slow_Fast_Timer_table[pmode]);
-
-        out_be64(&mic_tm_regs->slow_next_timer_0, MIC_Slow_Next_Timer_table[pmode]);
-        out_be64(&mic_tm_regs->slow_next_timer_1, MIC_Slow_Next_Timer_table[pmode]);
-
-        value = in_be64(&pmd_regs->pmcr);
-        /* set bits to zero */
-        value &= 0xFFFFFFFFFFFFFFF8ull;
-        /* set bits to next pmode */
-        value |= pmode;
-
-        out_be64(&pmd_regs->pmcr, value);
-
-#ifdef DEBUG
-        /* wait until new pmode appears in status register */
-        value = in_be64(&pmd_regs->pmsr) & 0x07;
-        while (value != pmode) {
-                cpu_relax();
-                value = in_be64(&pmd_regs->pmsr) & 0x07;
-        }
-
-        time = jiffies  - time;
-        time = jiffies_to_msecs(time);
-        pr_debug("had to wait %lu ms for a transition using " \
-                 "pervasive unit\n", time);
-#endif
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-
-int cbe_cpufreq_get_pmode(int cpu)
-{
-        int ret;
-        struct cbe_pmd_regs __iomem *pmd_regs;
-
-        pmd_regs = cbe_get_cpu_pmd_regs(cpu);
-        ret = in_be64(&pmd_regs->pmsr) & 0x07;
-
-        return ret;
-}
-
diff --git a/arch/powerpc/platforms/cell/cbe_cpufreq_pmi.c b/arch/powerpc/platforms/cell/cbe_cpufreq_pmi.c
deleted file mode 100644
index 60a07a4f9326..000000000000
--- a/arch/powerpc/platforms/cell/cbe_cpufreq_pmi.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * pmi backend for the cbe_cpufreq driver
- *
- * (C) Copyright IBM Deutschland Entwicklung GmbH 2005-2007
- *
- * Author: Christian Krafft <krafft@de.ibm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/timer.h>
-#include <linux/module.h>
-#include <linux/of_platform.h>
-
-#include <asm/processor.h>
-#include <asm/prom.h>
-#include <asm/pmi.h>
-#include <asm/cell-regs.h>
-
-#ifdef DEBUG
-#include <asm/time.h>
-#endif
-
-#include "cbe_cpufreq.h"
-
-static u8 pmi_slow_mode_limit[MAX_CBE];
-
-bool cbe_cpufreq_has_pmi = false;
-EXPORT_SYMBOL_GPL(cbe_cpufreq_has_pmi);
-
-/*
- * hardware specific functions
- */
-
-int cbe_cpufreq_set_pmode_pmi(int cpu, unsigned int pmode)
-{
-        int ret;
-        pmi_message_t pmi_msg;
-#ifdef DEBUG
-        long time;
-#endif
-        pmi_msg.type = PMI_TYPE_FREQ_CHANGE;
-        pmi_msg.data1 = cbe_cpu_to_node(cpu);
-        pmi_msg.data2 = pmode;
-
-#ifdef DEBUG
-        time = jiffies;
-#endif
-        pmi_send_message(pmi_msg);
-
-#ifdef DEBUG
-        time = jiffies  - time;
-        time = jiffies_to_msecs(time);
-        pr_debug("had to wait %lu ms for a transition using " \
-                 "PMI\n", time);
-#endif
-        ret = pmi_msg.data2;
-        pr_debug("PMI returned slow mode %d\n", ret);
-
-        return ret;
-}
-EXPORT_SYMBOL_GPL(cbe_cpufreq_set_pmode_pmi);
-
-
-static void cbe_cpufreq_handle_pmi(pmi_message_t pmi_msg)
-{
-        u8 node, slow_mode;
-
-        BUG_ON(pmi_msg.type != PMI_TYPE_FREQ_CHANGE);
-
-        node = pmi_msg.data1;
-        slow_mode = pmi_msg.data2;
-
-        pmi_slow_mode_limit[node] = slow_mode;
-
-        pr_debug("cbe_handle_pmi: node: %d max_freq: %d\n", node, slow_mode);
-}
-
-static int pmi_notifier(struct notifier_block *nb,
-                                       unsigned long event, void *data)
-{
-        struct cpufreq_policy *policy = data;
-        struct cpufreq_frequency_table *cbe_freqs;
-        u8 node;
-
-        /* Should this really be called for CPUFREQ_ADJUST, CPUFREQ_INCOMPATIBLE
-         * and CPUFREQ_NOTIFY policy events?)
-         */
-        if (event == CPUFREQ_START)
-                return 0;
-
-        cbe_freqs = cpufreq_frequency_get_table(policy->cpu);
-        node = cbe_cpu_to_node(policy->cpu);
-
-        pr_debug("got notified, event=%lu, node=%u\n", event, node);
-
-        if (pmi_slow_mode_limit[node] != 0) {
-                pr_debug("limiting node %d to slow mode %d\n",
-                         node, pmi_slow_mode_limit[node]);
-
-                cpufreq_verify_within_limits(policy, 0,
-
-                        cbe_freqs[pmi_slow_mode_limit[node]].frequency);
-        }
-
-        return 0;
-}
-
-static struct notifier_block pmi_notifier_block = {
-        .notifier_call = pmi_notifier,
-};
-
-static struct pmi_handler cbe_pmi_handler = {
-        .type                   = PMI_TYPE_FREQ_CHANGE,
-        .handle_pmi_message     = cbe_cpufreq_handle_pmi,
-};
-
-
-
-static int __init cbe_cpufreq_pmi_init(void)
-{
-        cbe_cpufreq_has_pmi = pmi_register_handler(&cbe_pmi_handler) == 0;
-
-        if (!cbe_cpufreq_has_pmi)
-                return -ENODEV;
-
-        cpufreq_register_notifier(&pmi_notifier_block, CPUFREQ_POLICY_NOTIFIER);
-
-        return 0;
-}
-
-static void __exit cbe_cpufreq_pmi_exit(void)
-{
-        cpufreq_unregister_notifier(&pmi_notifier_block, CPUFREQ_POLICY_NOTIFIER);
-        pmi_unregister_handler(&cbe_pmi_handler);
-}
-
-module_init(cbe_cpufreq_pmi_init);
-module_exit(cbe_cpufreq_pmi_exit);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Christian Krafft <krafft@de.ibm.com>");
diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c
index e56bb651da1a..946306b1bb4e 100644
--- a/arch/powerpc/platforms/cell/iommu.c
+++ b/arch/powerpc/platforms/cell/iommu.c
@@ -550,7 +550,7 @@ static struct iommu_table *cell_get_iommu_table(struct device *dev)
          */
         iommu = cell_iommu_for_node(dev_to_node(dev));
         if (iommu == NULL || list_empty(&iommu->windows)) {
-                printk(KERN_ERR "iommu: missing iommu for %s (node %d)\n",
+                dev_err(dev, "iommu: missing iommu for %s (node %d)\n",
                        of_node_full_name(dev->of_node), dev_to_node(dev));
                 return NULL;
         }
diff --git a/arch/powerpc/platforms/cell/pmu.c b/arch/powerpc/platforms/cell/pmu.c
index 59c1a1694104..348a27b12512 100644
--- a/arch/powerpc/platforms/cell/pmu.c
+++ b/arch/powerpc/platforms/cell/pmu.c
@@ -382,7 +382,7 @@ static int __init cbe_init_pm_irq(void)
         unsigned int irq;
         int rc, node;
 
-        for_each_node(node) {
+        for_each_online_node(node) {
                 irq = irq_create_mapping(NULL, IIC_IRQ_IOEX_PMI |
                                                (node << IIC_IRQ_NODE_SHIFT));
                 if (irq == NO_IRQ) {
diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c
index 8b1213993b10..f85db3a69b4a 100644
--- a/arch/powerpc/platforms/cell/spu_base.c
+++ b/arch/powerpc/platforms/cell/spu_base.c
@@ -715,7 +715,7 @@ static ssize_t spu_stat_show(struct device *dev,
                 spu->stats.libassist);
 }
 
-static DEVICE_ATTR(stat, 0644, spu_stat_show, NULL);
+static DEVICE_ATTR(stat, 0444, spu_stat_show, NULL);
 
 #ifdef CONFIG_KEXEC
 
diff --git a/arch/powerpc/platforms/cell/spufs/file.c b/arch/powerpc/platforms/cell/spufs/file.c
index 68c57d38745a..90986923a53a 100644
--- a/arch/powerpc/platforms/cell/spufs/file.c
+++ b/arch/powerpc/platforms/cell/spufs/file.c
@@ -149,7 +149,6 @@ static int __fops ## _open(struct inode *inode, struct file *file)	\
         return spufs_attr_open(inode, file, __get, __set, __fmt);       \
 }                                                                       \
 static const struct file_operations __fops = {                          \
-        .owner   = THIS_MODULE,                                         \
         .open    = __fops ## _open,                                     \
         .release = spufs_attr_release,                                  \
         .read    = spufs_attr_read,                                     \
@@ -352,7 +351,7 @@ static unsigned long spufs_get_unmapped_area(struct file *file,
 
         /* Else, try to obtain a 64K pages slice */
         return slice_get_unmapped_area(addr, len, flags,
-                                       MMU_PAGE_64K, 1, 0);
+                                       MMU_PAGE_64K, 1);
 }
 #endif /* CONFIG_SPU_FS_64K_LS */
 
@@ -2591,7 +2590,6 @@ static unsigned int spufs_switch_log_poll(struct file *file, poll_table *wait)
 }
 
 static const struct file_operations spufs_switch_log_fops = {
-        .owner          = THIS_MODULE,
         .open           = spufs_switch_log_open,
         .read           = spufs_switch_log_read,
         .poll           = spufs_switch_log_poll,
diff --git a/arch/powerpc/platforms/cell/spufs/inode.c b/arch/powerpc/platforms/cell/spufs/inode.c
index 3f3bb4cdbbec..35f77a42bedf 100644
--- a/arch/powerpc/platforms/cell/spufs/inode.c
+++ b/arch/powerpc/platforms/cell/spufs/inode.c
@@ -99,6 +99,7 @@ spufs_new_inode(struct super_block *sb, umode_t mode)
         if (!inode)
                 goto out;
 
+        inode->i_ino = get_next_ino();
         inode->i_mode = mode;
         inode->i_uid = current_fsuid();
         inode->i_gid = current_fsgid();
diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig
index 5a8f50a9afa7..302ba43d73a1 100644
--- a/arch/powerpc/platforms/embedded6xx/Kconfig
+++ b/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -9,7 +9,6 @@ config LINKSTATION
         select FSL_SOC
         select PPC_UDBG_16550 if SERIAL_8250
         select DEFAULT_UIMAGE
-        select MPC10X_OPENPIC
         select MPC10X_BRIDGE
         help
           Select LINKSTATION if configuring for one of PPC- (MPC8241)
@@ -24,7 +23,6 @@ config STORCENTER
         select MPIC
         select FSL_SOC
         select PPC_UDBG_16550 if SERIAL_8250
-        select MPC10X_OPENPIC
         select MPC10X_BRIDGE
         help
           Select STORCENTER if configuring for the iomega StorCenter
@@ -84,9 +82,6 @@ config MV64X60
         select PPC_INDIRECT_PCI
         select CHECK_CACHE_COHERENCY
 
-config MPC10X_OPENPIC
-        bool
-
 config GAMECUBE_COMMON
         bool
 
diff --git a/arch/powerpc/platforms/embedded6xx/mpc10x.h b/arch/powerpc/platforms/embedded6xx/mpc10x.h
index b30a6a3b5bd2..b290b63661f1 100644
--- a/arch/powerpc/platforms/embedded6xx/mpc10x.h
+++ b/arch/powerpc/platforms/embedded6xx/mpc10x.h
@@ -81,17 +81,6 @@
 #define MPC10X_MAPB_PCI_MEM_OFFSET      (MPC10X_MAPB_ISA_MEM_BASE -     \
                                          MPC10X_MAPB_PCI_MEM_START)
 
-/* Set hose members to values appropriate for the mem map used */
-#define MPC10X_SETUP_HOSE(hose, map) {                                  \
-        (hose)->pci_mem_offset = MPC10X_MAP##map##_PCI_MEM_OFFSET;      \
-        (hose)->io_space.start = MPC10X_MAP##map##_PCI_IO_START;        \
-        (hose)->io_space.end = MPC10X_MAP##map##_PCI_IO_END;            \
-        (hose)->mem_space.start = MPC10X_MAP##map##_PCI_MEM_START;      \
-        (hose)->mem_space.end = MPC10X_MAP##map##_PCI_MEM_END;          \
-        (hose)->io_base_virt = (void *)MPC10X_MAP##map##_ISA_IO_BASE;   \
-}
-
-
 /* Miscellaneous Configuration register offsets */
 #define MPC10X_CFG_PIR_REG              0x09
 #define MPC10X_CFG_PIR_HOST_BRIDGE      0x00
diff --git a/arch/powerpc/platforms/pasemi/cpufreq.c b/arch/powerpc/platforms/pasemi/cpufreq.c
index 890f30e70f98..be1e7958909e 100644
--- a/arch/powerpc/platforms/pasemi/cpufreq.c
+++ b/arch/powerpc/platforms/pasemi/cpufreq.c
@@ -273,10 +273,9 @@ static int pas_cpufreq_target(struct cpufreq_policy *policy,
 
         freqs.old = policy->cur;
         freqs.new = pas_freqs[pas_astate_new].frequency;
-        freqs.cpu = policy->cpu;
 
         mutex_lock(&pas_switch_mutex);
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+        cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
 
         pr_debug("setting frequency for cpu %d to %d kHz, 1/%d of max frequency\n",
                  policy->cpu,
@@ -288,7 +287,7 @@ static int pas_cpufreq_target(struct cpufreq_policy *policy,
         for_each_online_cpu(i)
                 set_astate(i, pas_astate_new);
 
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+        cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
         mutex_unlock(&pas_switch_mutex);
 
         ppc_proc_freq = freqs.new * 1000ul;
diff --git a/arch/powerpc/platforms/powermac/cpufreq_32.c b/arch/powerpc/platforms/powermac/cpufreq_32.c
index 311b804353b1..3104fad82480 100644
--- a/arch/powerpc/platforms/powermac/cpufreq_32.c
+++ b/arch/powerpc/platforms/powermac/cpufreq_32.c
@@ -335,7 +335,8 @@ static int pmu_set_cpu_speed(int low_speed)
         return 0;
 }
 
-static int do_set_cpu_speed(int speed_mode, int notify)
+static int do_set_cpu_speed(struct cpufreq_policy *policy, int speed_mode,
+                int notify)
 {
         struct cpufreq_freqs freqs;
         unsigned long l3cr;
@@ -343,13 +344,12 @@ static int do_set_cpu_speed(int speed_mode, int notify)
 
         freqs.old = cur_freq;
         freqs.new = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
-        freqs.cpu = smp_processor_id();
 
         if (freqs.old == freqs.new)
                 return 0;
 
         if (notify)
-                cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+                cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
         if (speed_mode == CPUFREQ_LOW &&
             cpu_has_feature(CPU_FTR_L3CR)) {
                 l3cr = _get_L3CR();
@@ -366,7 +366,7 @@ static int do_set_cpu_speed(int speed_mode, int notify)
                         _set_L3CR(prev_l3cr);
         }
         if (notify)
-                cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+                cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
         cur_freq = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
 
         return 0;
@@ -393,7 +393,7 @@ static int pmac_cpufreq_target(	struct cpufreq_policy *policy,
                         target_freq, relation, &newstate))
                 return -EINVAL;
 
-        rc = do_set_cpu_speed(newstate, 1);
+        rc = do_set_cpu_speed(policy, newstate, 1);
 
         ppc_proc_freq = cur_freq * 1000ul;
         return rc;
@@ -442,7 +442,7 @@ static int pmac_cpufreq_suspend(struct cpufreq_policy *policy)
         no_schedule = 1;
         sleep_freq = cur_freq;
         if (cur_freq == low_freq && !is_pmu_based)
-                do_set_cpu_speed(CPUFREQ_HIGH, 0);
+                do_set_cpu_speed(policy, CPUFREQ_HIGH, 0);
         return 0;
 }
 
@@ -458,7 +458,7 @@ static int pmac_cpufreq_resume(struct cpufreq_policy *policy)
          * is that we force a switch to whatever it was, which is
          * probably high speed due to our suspend() routine
          */
-        do_set_cpu_speed(sleep_freq == low_freq ?
+        do_set_cpu_speed(policy, sleep_freq == low_freq ?
                          CPUFREQ_LOW : CPUFREQ_HIGH, 0);
 
         ppc_proc_freq = cur_freq * 1000ul;
diff --git a/arch/powerpc/platforms/powermac/cpufreq_64.c b/arch/powerpc/platforms/powermac/cpufreq_64.c
index 9650c6029c82..7ba423431cfe 100644
--- a/arch/powerpc/platforms/powermac/cpufreq_64.c
+++ b/arch/powerpc/platforms/powermac/cpufreq_64.c
@@ -339,11 +339,10 @@ static int g5_cpufreq_target(struct cpufreq_policy *policy,
 
         freqs.old = g5_cpu_freqs[g5_pmode_cur].frequency;
         freqs.new = g5_cpu_freqs[newstate].frequency;
-        freqs.cpu = 0;
 
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+        cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
         rc = g5_switch_freq(newstate);
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+        cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
 
         mutex_unlock(&g5_switch_mutex);
 
diff --git a/arch/powerpc/platforms/powermac/pci.c b/arch/powerpc/platforms/powermac/pci.c
index 2b8af75abc23..cf7009b8c7b6 100644
--- a/arch/powerpc/platforms/powermac/pci.c
+++ b/arch/powerpc/platforms/powermac/pci.c
@@ -824,6 +824,7 @@ static void __init parse_region_decode(struct pci_controller *hose,
                         hose->mem_resources[cur].name = hose->dn->full_name;
                         hose->mem_resources[cur].start = base;
                         hose->mem_resources[cur].end = end;
+                        hose->mem_offset[cur] = 0;
                         DBG("  %d: 0x%08lx-0x%08lx\n", cur, base, end);
                 } else {
                         DBG("   :           -0x%08lx\n", end);
@@ -866,7 +867,6 @@ static void __init setup_u3_ht(struct pci_controller* hose)
         hose->io_resource.start = 0;
         hose->io_resource.end = 0x003fffff;
         hose->io_resource.flags = IORESOURCE_IO;
-        hose->pci_mem_offset = 0;
         hose->first_busno = 0;
         hose->last_busno = 0xef;
 
diff --git a/arch/powerpc/platforms/powernv/Kconfig b/arch/powerpc/platforms/powernv/Kconfig
index 74fea5c21839..d3e840d643af 100644
--- a/arch/powerpc/platforms/powernv/Kconfig
+++ b/arch/powerpc/platforms/powernv/Kconfig
@@ -8,6 +8,11 @@ config PPC_POWERNV
         select PPC_PCI_CHOICE if EMBEDDED
         default y
 
+config POWERNV_MSI
+        bool "Support PCI MSI on PowerNV platform"
+        depends on PCI_MSI
+        default y
+
 config PPC_POWERNV_RTAS
         depends on PPC_POWERNV
         bool "Support for RTAS based PowerNV platforms such as BML"
diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S
index 3bb07e5e43cd..6fabe92eafb6 100644
--- a/arch/powerpc/platforms/powernv/opal-wrappers.S
+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
@@ -107,3 +107,4 @@ OPAL_CALL(opal_pci_mask_pe_error,		OPAL_PCI_MASK_PE_ERROR);
 OPAL_CALL(opal_set_slot_led_status,             OPAL_SET_SLOT_LED_STATUS);
 OPAL_CALL(opal_get_epow_status,                 OPAL_GET_EPOW_STATUS);
 OPAL_CALL(opal_set_system_attention_led,        OPAL_SET_SYSTEM_ATTENTION_LED);
+OPAL_CALL(opal_pci_msi_eoi,                     OPAL_PCI_MSI_EOI);
diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
index aaa0dba49471..ade4463226c6 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -34,7 +34,6 @@ int __init early_init_dt_scan_opal(unsigned long node,
 {
         const void *basep, *entryp;
         unsigned long basesz, entrysz;
-        u64 glue;
 
         if (depth != 1 || strcmp(uname, "ibm,opal") != 0)
                 return 0;
@@ -61,6 +60,16 @@ int __init early_init_dt_scan_opal(unsigned long node,
                 printk("OPAL V1 detected !\n");
         }
 
+        return 1;
+}
+
+static int __init opal_register_exception_handlers(void)
+{
+        u64 glue;
+
+        if (!(powerpc_firmware_features & FW_FEATURE_OPAL))
+                return -ENODEV;
+
         /* Hookup some exception handlers. We use the fwnmi area at 0x7000
          * to provide the glue space to OPAL
          */
@@ -74,9 +83,11 @@ int __init early_init_dt_scan_opal(unsigned long node,
         glue += 128;
         opal_register_exception_handler(OPAL_SOFTPATCH_HANDLER, 0, glue);
 
-        return 1;
+        return 0;
 }
 
+early_initcall(opal_register_exception_handlers);
+
 int opal_get_chars(uint32_t vtermno, char *buf, int count)
 {
         s64 len, rc;
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index 8e90e8906df3..1da578b7c1bf 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -26,10 +26,12 @@
 #include <asm/prom.h>
 #include <asm/pci-bridge.h>
 #include <asm/machdep.h>
+#include <asm/msi_bitmap.h>
 #include <asm/ppc-pci.h>
 #include <asm/opal.h>
 #include <asm/iommu.h>
 #include <asm/tce.h>
+#include <asm/xics.h>
 
 #include "powernv.h"
 #include "pci.h"
@@ -87,6 +89,7 @@ static int pnv_ioda_alloc_pe(struct pnv_phb *phb)
                         return IODA_INVALID_PE;
         } while(test_and_set_bit(pe, phb->ioda.pe_alloc));
 
+        phb->ioda.pe_array[pe].phb = phb;
         phb->ioda.pe_array[pe].pe_number = pe;
         return pe;
 }
@@ -431,22 +434,102 @@ static void pnv_pci_ioda_setup_PEs(void)
         }
 }
 
-static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *dev)
+static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
 {
-        /* We delay DMA setup after we have assigned all PE# */
+        struct pci_dn *pdn = pnv_ioda_get_pdn(pdev);
+        struct pnv_ioda_pe *pe;
+
+        /*
+         * The function can be called while the PE#
+         * hasn't been assigned. Do nothing for the
+         * case.
+         */
+        if (!pdn || pdn->pe_number == IODA_INVALID_PE)
+                return;
+
+        pe = &phb->ioda.pe_array[pdn->pe_number];
+        set_iommu_table_base(&pdev->dev, &pe->tce32_table);
 }
 
-static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
+static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl,
+                                         u64 *startp, u64 *endp)
 {
-        struct pci_dev *dev;
+        u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
+        unsigned long start, end, inc;
+
+        start = __pa(startp);
+        end = __pa(endp);
+
+        /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
+        if (tbl->it_busno) {
+                start <<= 12;
+                end <<= 12;
+                inc = 128 << 12;
+                start |= tbl->it_busno;
+                end |= tbl->it_busno;
+        } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
+                /* p7ioc-style invalidation, 2 TCEs per write */
+                start |= (1ull << 63);
+                end |= (1ull << 63);
+                inc = 16;
+        } else {
+                /* Default (older HW) */
+                inc = 128;
+        }
 
-        list_for_each_entry(dev, &bus->devices, bus_list) {
-                set_iommu_table_base(&dev->dev, &pe->tce32_table);
-                if (dev->subordinate)
-                        pnv_ioda_setup_bus_dma(pe, dev->subordinate);
+        end |= inc - 1; /* round up end to be different than start */
+
+        mb(); /* Ensure above stores are visible */
+        while (start <= end) {
+                __raw_writeq(start, invalidate);
+                start += inc;
+        }
+
+        /*
+         * The iommu layer will do another mb() for us on build()
+         * and we don't care on free()
+         */
+}
+
+static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe,
+                                         struct iommu_table *tbl,
+                                         u64 *startp, u64 *endp)
+{
+        unsigned long start, end, inc;
+        u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
+
+        /* We'll invalidate DMA address in PE scope */
+        start = 0x2ul << 60;
+        start |= (pe->pe_number & 0xFF);
+        end = start;
+
+        /* Figure out the start, end and step */
+        inc = tbl->it_offset + (((u64)startp - tbl->it_base) / sizeof(u64));
+        start |= (inc << 12);
+        inc = tbl->it_offset + (((u64)endp - tbl->it_base) / sizeof(u64));
+        end |= (inc << 12);
+        inc = (0x1ul << 12);
+        mb();
+
+        while (start <= end) {
+                __raw_writeq(start, invalidate);
+                start += inc;
         }
 }
 
+void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
+                                 u64 *startp, u64 *endp)
+{
+        struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe,
+                                              tce32_table);
+        struct pnv_phb *phb = pe->phb;
+
+        if (phb->type == PNV_PHB_IODA1)
+                pnv_pci_ioda1_tce_invalidate(tbl, startp, endp);
+        else
+                pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp);
+}
+
 static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
                                       struct pnv_ioda_pe *pe, unsigned int base,
                                       unsigned int segs)
@@ -518,16 +601,11 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
                  */
                 tbl->it_busno = 0;
                 tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8);
-                tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE
-                        | TCE_PCI_SWINV_PAIR;
+                tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE |
+                               TCE_PCI_SWINV_PAIR;
         }
         iommu_init_table(tbl, phb->hose->node);
 
-        if (pe->pdev)
-                set_iommu_table_base(&pe->pdev->dev, tbl);
-        else
-                pnv_ioda_setup_bus_dma(pe, pe->pbus);
-
         return;
  fail:
         /* XXX Failure: Try to fallback to 64-bit only ? */
@@ -537,6 +615,76 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
                 __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
 }
 
+static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
+                                       struct pnv_ioda_pe *pe)
+{
+        struct page *tce_mem = NULL;
+        void *addr;
+        const __be64 *swinvp;
+        struct iommu_table *tbl;
+        unsigned int tce_table_size, end;
+        int64_t rc;
+
+        /* We shouldn't already have a 32-bit DMA associated */
+        if (WARN_ON(pe->tce32_seg >= 0))
+                return;
+
+        /* The PE will reserve all possible 32-bits space */
+        pe->tce32_seg = 0;
+        end = (1 << ilog2(phb->ioda.m32_pci_base));
+        tce_table_size = (end / 0x1000) * 8;
+        pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
+                end);
+
+        /* Allocate TCE table */
+        tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
+                                   get_order(tce_table_size));
+        if (!tce_mem) {
+                pe_err(pe, "Failed to allocate a 32-bit TCE memory\n");
+                goto fail;
+        }
+        addr = page_address(tce_mem);
+        memset(addr, 0, tce_table_size);
+
+        /*
+         * Map TCE table through TVT. The TVE index is the PE number
+         * shifted by 1 bit for 32-bits DMA space.
+         */
+        rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
+                                        pe->pe_number << 1, 1, __pa(addr),
+                                        tce_table_size, 0x1000);
+        if (rc) {
+                pe_err(pe, "Failed to configure 32-bit TCE table,"
+                       " err %ld\n", rc);
+                goto fail;
+        }
+
+        /* Setup linux iommu table */
+        tbl = &pe->tce32_table;
+        pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0);
+
+        /* OPAL variant of PHB3 invalidated TCEs */
+        swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
+        if (swinvp) {
+                /* We need a couple more fields -- an address and a data
+                 * to or.  Since the bus is only printed out on table free
+                 * errors, and on the first pass the data will be a relative
+                 * bus number, print that out instead.
+                 */
+                tbl->it_busno = 0;
+                tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8);
+                tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
+        }
+        iommu_init_table(tbl, phb->hose->node);
+
+        return;
+fail:
+        if (pe->tce32_seg >= 0)
+                pe->tce32_seg = -1;
+        if (tce_mem)
+                __free_pages(tce_mem, get_order(tce_table_size));
+}
+
 static void pnv_ioda_setup_dma(struct pnv_phb *phb)
 {
         struct pci_controller *hose = phb->hose;
@@ -579,20 +727,49 @@ static void pnv_ioda_setup_dma(struct pnv_phb *phb)
                         if (segs > remaining)
                                 segs = remaining;
                 }
-                pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
-                        pe->dma_weight, segs);
-                pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs);
+
+                /*
+                 * For IODA2 compliant PHB3, we needn't care about the weight.
+                 * The all available 32-bits DMA space will be assigned to
+                 * the specific PE.
+                 */
+                if (phb->type == PNV_PHB_IODA1) {
+                        pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
+                                pe->dma_weight, segs);
+                        pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs);
+                } else {
+                        pe_info(pe, "Assign DMA32 space\n");
+                        segs = 0;
+                        pnv_pci_ioda2_setup_dma_pe(phb, pe);
+                }
+
                 remaining -= segs;
                 base += segs;
         }
 }
 
 #ifdef CONFIG_PCI_MSI
+static void pnv_ioda2_msi_eoi(struct irq_data *d)
+{
+        unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
+        struct irq_chip *chip = irq_data_get_irq_chip(d);
+        struct pnv_phb *phb = container_of(chip, struct pnv_phb,
+                                           ioda.irq_chip);
+        int64_t rc;
+
+        rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
+        WARN_ON_ONCE(rc);
+
+        icp_native_eoi(d);
+}
+
 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
-                                  unsigned int hwirq, unsigned int is_64,
-                                  struct msi_msg *msg)
+                                  unsigned int hwirq, unsigned int virq,
+                                  unsigned int is_64, struct msi_msg *msg)
 {
         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
+        struct irq_data *idata;
+        struct irq_chip *ichip;
         unsigned int xive_num = hwirq - phb->msi_base;
         uint64_t addr64;
         uint32_t addr32, data;
@@ -637,6 +814,23 @@ static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
         }
         msg->data = data;
 
+        /*
+         * Change the IRQ chip for the MSI interrupts on PHB3.
+         * The corresponding IRQ chip should be populated for
+         * the first time.
+         */
+        if (phb->type == PNV_PHB_IODA2) {
+                if (!phb->ioda.irq_chip_init) {
+                        idata = irq_get_irq_data(virq);
+                        ichip = irq_data_get_irq_chip(idata);
+                        phb->ioda.irq_chip_init = 1;
+                        phb->ioda.irq_chip = *ichip;
+                        phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
+                }
+
+                irq_set_chip(virq, &phb->ioda.irq_chip);
+        }
+
         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
                  " address=%x_%08x data=%x PE# %d\n",
                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
@@ -647,7 +841,7 @@ static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
 
 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
 {
-        unsigned int bmap_size;
+        unsigned int count;
         const __be32 *prop = of_get_property(phb->hose->dn,
                                              "ibm,opal-msi-ranges", NULL);
         if (!prop) {
@@ -658,18 +852,17 @@ static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
                 return;
 
         phb->msi_base = be32_to_cpup(prop);
-        phb->msi_count = be32_to_cpup(prop + 1);
-        bmap_size = BITS_TO_LONGS(phb->msi_count) * sizeof(unsigned long);
-        phb->msi_map = zalloc_maybe_bootmem(bmap_size, GFP_KERNEL);
-        if (!phb->msi_map) {
+        count = be32_to_cpup(prop + 1);
+        if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
                        phb->hose->global_number);
                 return;
         }
+
         phb->msi_setup = pnv_pci_ioda_msi_setup;
         phb->msi32_support = 1;
         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
-                phb->msi_count, phb->msi_base);
+                count, phb->msi_base);
 }
 #else
 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
@@ -722,11 +915,14 @@ static void pnv_ioda_setup_pe_seg(struct pci_controller *hose,
                                 index++;
                         }
                 } else if (res->flags & IORESOURCE_MEM) {
+                        /* WARNING: Assumes M32 is mem region 0 in PHB. We need to
+                         * harden that algorithm when we start supporting M64
+                         */
                         region.start = res->start -
-                                       hose->pci_mem_offset -
+                                       hose->mem_offset[0] -
                                        phb->ioda.m32_pci_base;
                         region.end   = res->end -
-                                       hose->pci_mem_offset -
+                                       hose->mem_offset[0] -
                                        phb->ioda.m32_pci_base;
                         index = region.start / phb->ioda.m32_segsize;
 
@@ -852,18 +1048,19 @@ static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
         return phb->ioda.pe_rmap[(bus->number << 8) | devfn];
 }
 
-void __init pnv_pci_init_ioda1_phb(struct device_node *np)
+void __init pnv_pci_init_ioda_phb(struct device_node *np, int ioda_type)
 {
         struct pci_controller *hose;
         static int primary = 1;
         struct pnv_phb *phb;
         unsigned long size, m32map_off, iomap_off, pemap_off;
         const u64 *prop64;
+        const u32 *prop32;
         u64 phb_id;
         void *aux;
         long rc;
 
-        pr_info(" Initializing IODA OPAL PHB %s\n", np->full_name);
+        pr_info(" Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
 
         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
         if (!prop64) {
@@ -890,47 +1087,46 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
         hose->last_busno = 0xff;
         hose->private_data = phb;
         phb->opal_id = phb_id;
-        phb->type = PNV_PHB_IODA1;
+        phb->type = ioda_type;
 
         /* Detect specific models for error handling */
         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
                 phb->model = PNV_PHB_MODEL_P7IOC;
+        else if (of_device_is_compatible(np, "ibm,power8-pciex"))
+                phb->model = PNV_PHB_MODEL_PHB3;
         else
                 phb->model = PNV_PHB_MODEL_UNKNOWN;
 
-        /* We parse "ranges" now since we need to deduce the register base
-         * from the IO base
-         */
+        /* Parse 32-bit and IO ranges (if any) */
         pci_process_bridge_OF_ranges(phb->hose, np, primary);
         primary = 0;
 
-        /* Magic formula from Milton */
+        /* Get registers */
         phb->regs = of_iomap(np, 0);
         if (phb->regs == NULL)
                 pr_err("  Failed to map registers !\n");
 
-
-        /* XXX This is hack-a-thon. This needs to be changed so that:
-         *  - we obtain stuff like PE# etc... from device-tree
-         *  - we properly re-allocate M32 ourselves
-         *    (the OFW one isn't very good)
-         */
-
         /* Initialize more IODA stuff */
-        phb->ioda.total_pe = 128;
+        prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
+        if (!prop32)
+                phb->ioda.total_pe = 1;
+        else
+                phb->ioda.total_pe = *prop32;
 
         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
-        /* OFW Has already off top 64k of M32 space (MSI space) */
+        /* FW Has already off top 64k of M32 space (MSI space) */
         phb->ioda.m32_size += 0x10000;
 
         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe;
-        phb->ioda.m32_pci_base = hose->mem_resources[0].start -
-                hose->pci_mem_offset;
+        phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
         phb->ioda.io_size = hose->pci_io_size;
         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe;
         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
 
-        /* Allocate aux data & arrays */
+        /* Allocate aux data & arrays
+         *
+         * XXX TODO: Don't allocate io segmap on PHB3
+         */
         size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
         m32map_off = size;
         size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]);
@@ -960,7 +1156,7 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
         hose->mem_resources[2].start = 0;
         hose->mem_resources[2].end = 0;
 
-#if 0
+#if 0 /* We should really do that ... */
         rc = opal_pci_set_phb_mem_window(opal->phb_id,
                                          window_type,
                                          window_num,
@@ -974,16 +1170,6 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
                 phb->ioda.m32_size, phb->ioda.m32_segsize,
                 phb->ioda.io_size, phb->ioda.io_segsize);
 
-        if (phb->regs)  {
-                pr_devel(" BUID     = 0x%016llx\n", in_be64(phb->regs + 0x100));
-                pr_devel(" PHB2_CR  = 0x%016llx\n", in_be64(phb->regs + 0x160));
-                pr_devel(" IO_BAR   = 0x%016llx\n", in_be64(phb->regs + 0x170));
-                pr_devel(" IO_BAMR  = 0x%016llx\n", in_be64(phb->regs + 0x178));
-                pr_devel(" IO_SAR   = 0x%016llx\n", in_be64(phb->regs + 0x180));
-                pr_devel(" M32_BAR  = 0x%016llx\n", in_be64(phb->regs + 0x190));
-                pr_devel(" M32_BAMR = 0x%016llx\n", in_be64(phb->regs + 0x198));
-                pr_devel(" M32_SAR  = 0x%016llx\n", in_be64(phb->regs + 0x1a0));
-        }
         phb->hose->ops = &pnv_pci_ops;
 
         /* Setup RID -> PE mapping function */
@@ -1011,7 +1197,18 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
         rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET);
         if (rc)
                 pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
-        opal_pci_set_pe(phb_id, 0, 0, 7, 1, 1 , OPAL_MAP_PE);
+
+        /*
+         * On IODA1 map everything to PE#0, on IODA2 we assume the IODA reset
+         * has cleared the RTT which has the same effect
+         */
+        if (ioda_type == PNV_PHB_IODA1)
+                opal_pci_set_pe(phb_id, 0, 0, 7, 1, 1 , OPAL_MAP_PE);
+}
+
+void pnv_pci_init_ioda2_phb(struct device_node *np)
+{
+        pnv_pci_init_ioda_phb(np, PNV_PHB_IODA2);
 }
 
 void __init pnv_pci_init_ioda_hub(struct device_node *np)
@@ -1034,6 +1231,6 @@ void __init pnv_pci_init_ioda_hub(struct device_node *np)
         for_each_child_of_node(np, phbn) {
                 /* Look for IODA1 PHBs */
                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
-                        pnv_pci_init_ioda1_phb(phbn);
+                        pnv_pci_init_ioda_phb(phbn, PNV_PHB_IODA1);
         }
 }
diff --git a/arch/powerpc/platforms/powernv/pci-p5ioc2.c b/arch/powerpc/platforms/powernv/pci-p5ioc2.c
index 7db8771a40f5..92b37a0186c9 100644
--- a/arch/powerpc/platforms/powernv/pci-p5ioc2.c
+++ b/arch/powerpc/platforms/powernv/pci-p5ioc2.c
@@ -26,6 +26,7 @@
 #include <asm/prom.h>
 #include <asm/pci-bridge.h>
 #include <asm/machdep.h>
+#include <asm/msi_bitmap.h>
 #include <asm/ppc-pci.h>
 #include <asm/opal.h>
 #include <asm/iommu.h>
@@ -41,8 +42,8 @@
 
 #ifdef CONFIG_PCI_MSI
 static int pnv_pci_p5ioc2_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
-                                    unsigned int hwirq, unsigned int is_64,
-                                    struct msi_msg *msg)
+                                    unsigned int hwirq, unsigned int virq,
+                                    unsigned int is_64, struct msi_msg *msg)
 {
         if (WARN_ON(!is_64))
                 return -ENXIO;
@@ -55,7 +56,7 @@ static int pnv_pci_p5ioc2_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
 
 static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb)
 {
-        unsigned int bmap_size;
+        unsigned int count;
         const __be32 *prop = of_get_property(phb->hose->dn,
                                              "ibm,opal-msi-ranges", NULL);
         if (!prop)
@@ -67,10 +68,8 @@ static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb)
         if (of_device_is_compatible(phb->hose->dn, "ibm,p5ioc2-pcix"))
                 return;
         phb->msi_base = be32_to_cpup(prop);
-        phb->msi_count = be32_to_cpup(prop + 1);
-        bmap_size = BITS_TO_LONGS(phb->msi_count) * sizeof(unsigned long);
-        phb->msi_map = zalloc_maybe_bootmem(bmap_size, GFP_KERNEL);
-        if (!phb->msi_map) {
+        count = be32_to_cpup(prop + 1);
+        if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
                        phb->hose->global_number);
                 return;
@@ -78,7 +77,7 @@ static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb)
         phb->msi_setup = pnv_pci_p5ioc2_msi_setup;
         phb->msi32_support = 0;
         pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
-                phb->msi_count, phb->msi_base);
+                count, phb->msi_base);
 }
 #else
 static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb) { }
diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index b8b8e0bd9897..55dfca844ddf 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -26,6 +26,7 @@
 #include <asm/prom.h>
 #include <asm/pci-bridge.h>
 #include <asm/machdep.h>
+#include <asm/msi_bitmap.h>
 #include <asm/ppc-pci.h>
 #include <asm/opal.h>
 #include <asm/iommu.h>
@@ -47,43 +48,7 @@ static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type)
         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
         struct pnv_phb *phb = hose->private_data;
 
-        return (phb && phb->msi_map) ? 0 : -ENODEV;
-}
-
-static unsigned int pnv_get_one_msi(struct pnv_phb *phb)
-{
-        unsigned long flags;
-        unsigned int id, rc;
-
-        spin_lock_irqsave(&phb->lock, flags);
-
-        id = find_next_zero_bit(phb->msi_map, phb->msi_count, phb->msi_next);
-        if (id >= phb->msi_count && phb->msi_next)
-                id = find_next_zero_bit(phb->msi_map, phb->msi_count, 0);
-        if (id >= phb->msi_count) {
-                rc = 0;
-                goto out;
-        }
-        __set_bit(id, phb->msi_map);
-        rc = id + phb->msi_base;
-out:
-        spin_unlock_irqrestore(&phb->lock, flags);
-        return rc;
-}
-
-static void pnv_put_msi(struct pnv_phb *phb, unsigned int hwirq)
-{
-        unsigned long flags;
-        unsigned int id;
-
-        if (WARN_ON(hwirq < phb->msi_base ||
-                    hwirq >= (phb->msi_base + phb->msi_count)))
-                return;
-        id = hwirq - phb->msi_base;
-
-        spin_lock_irqsave(&phb->lock, flags);
-        __clear_bit(id, phb->msi_map);
-        spin_unlock_irqrestore(&phb->lock, flags);
+        return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV;
 }
 
 static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
@@ -92,7 +57,8 @@ static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
         struct pnv_phb *phb = hose->private_data;
         struct msi_desc *entry;
         struct msi_msg msg;
-        unsigned int hwirq, virq;
+        int hwirq;
+        unsigned int virq;
         int rc;
 
         if (WARN_ON(!phb))
@@ -104,25 +70,25 @@ static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
                                 pci_name(pdev));
                         return -ENXIO;
                 }
-                hwirq = pnv_get_one_msi(phb);
-                if (!hwirq) {
+                hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1);
+                if (hwirq < 0) {
                         pr_warn("%s: Failed to find a free MSI\n",
                                 pci_name(pdev));
                         return -ENOSPC;
                 }
-                virq = irq_create_mapping(NULL, hwirq);
+                virq = irq_create_mapping(NULL, phb->msi_base + hwirq);
                 if (virq == NO_IRQ) {
                         pr_warn("%s: Failed to map MSI to linux irq\n",
                                 pci_name(pdev));
-                        pnv_put_msi(phb, hwirq);
+                        msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
                         return -ENOMEM;
                 }
-                rc = phb->msi_setup(phb, pdev, hwirq, entry->msi_attrib.is_64,
-                                    &msg);
+                rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq,
+                                    virq, entry->msi_attrib.is_64, &msg);
                 if (rc) {
                         pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));
                         irq_dispose_mapping(virq);
-                        pnv_put_msi(phb, hwirq);
+                        msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
                         return rc;
                 }
                 irq_set_msi_desc(virq, entry);
@@ -144,7 +110,8 @@ static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
                 if (entry->irq == NO_IRQ)
                         continue;
                 irq_set_msi_desc(entry->irq, NULL);
-                pnv_put_msi(phb, virq_to_hw(entry->irq));
+                msi_bitmap_free_hwirqs(&phb->msi_bmp,
+                        virq_to_hw(entry->irq) - phb->msi_base, 1);
                 irq_dispose_mapping(entry->irq);
         }
 }
@@ -362,48 +329,6 @@ struct pci_ops pnv_pci_ops = {
         .write = pnv_pci_write_config,
 };
 
-
-static void pnv_tce_invalidate(struct iommu_table *tbl,
-                               u64 *startp, u64 *endp)
-{
-        u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
-        unsigned long start, end, inc;
-
-        start = __pa(startp);
-        end = __pa(endp);
-
-
-        /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
-        if (tbl->it_busno) {
-                start <<= 12;
-                end <<= 12;
-                inc = 128 << 12;
-                start |= tbl->it_busno;
-                end |= tbl->it_busno;
-        }
-        /* p7ioc-style invalidation, 2 TCEs per write */
-        else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
-                start |= (1ull << 63);
-                end |= (1ull << 63);
-                inc = 16;
-        }
-        /* Default (older HW) */
-        else
-                inc = 128;
-
-        end |= inc - 1;         /* round up end to be different than start */
-
-        mb(); /* Ensure above stores are visible */
-        while (start <= end) {
-                __raw_writeq(start, invalidate);
-                start += inc;
-        }
-        /* The iommu layer will do another mb() for us on build() and
-         * we don't care on free()
-         */
-}
-
-
 static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
                          unsigned long uaddr, enum dma_data_direction direction,
                          struct dma_attrs *attrs)
@@ -428,7 +353,7 @@ static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
          * of flags if that becomes the case
          */
         if (tbl->it_type & TCE_PCI_SWINV_CREATE)
-                pnv_tce_invalidate(tbl, tces, tcep - 1);
+                pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
 
         return 0;
 }
@@ -442,8 +367,8 @@ static void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
         while (npages--)
                 *(tcep++) = 0;
 
-        if (tbl->it_type & TCE_PCI_SWINV_FREE)
-                pnv_tce_invalidate(tbl, tces, tcep - 1);
+        if (tbl->it_type & TCE_PCI_SWINV_CREATE)
+                pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
 }
 
 static unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
@@ -525,7 +450,7 @@ static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
                 pnv_pci_dma_fallback_setup(hose, pdev);
 }
 
-/* Fixup wrong class code in p7ioc root complex */
+/* Fixup wrong class code in p7ioc and p8 root complex */
 static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
 {
         dev->class = PCI_CLASS_BRIDGE_PCI << 8;
@@ -591,6 +516,10 @@ void __init pnv_pci_init(void)
                 if (!found_ioda)
                         for_each_compatible_node(np, NULL, "ibm,p5ioc2")
                                 pnv_pci_init_p5ioc2_hub(np);
+
+                /* Look for ioda2 built-in PHB3's */
+                for_each_compatible_node(np, NULL, "ibm,ioda2-phb")
+                        pnv_pci_init_ioda2_phb(np);
         }
 
         /* Setup the linkage between OF nodes and PHBs */
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index 7cfb7c883deb..48dc4bb856a1 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -4,9 +4,9 @@
 struct pci_dn;
 
 enum pnv_phb_type {
-        PNV_PHB_P5IOC2,
-        PNV_PHB_IODA1,
-        PNV_PHB_IODA2,
+        PNV_PHB_P5IOC2  = 0,
+        PNV_PHB_IODA1   = 1,
+        PNV_PHB_IODA2   = 2,
 };
 
 /* Precise PHB model for error management */
@@ -14,6 +14,7 @@ enum pnv_phb_model {
         PNV_PHB_MODEL_UNKNOWN,
         PNV_PHB_MODEL_P5IOC2,
         PNV_PHB_MODEL_P7IOC,
+        PNV_PHB_MODEL_PHB3,
 };
 
 #define PNV_PCI_DIAG_BUF_SIZE   4096
@@ -22,8 +23,10 @@ enum pnv_phb_model {
 #define PNV_IODA_PE_BUS_ALL     (1 << 2)        /* PE has subordinate buses     */
 
 /* Data associated with a PE, including IOMMU tracking etc.. */
+struct pnv_phb;
 struct pnv_ioda_pe {
         unsigned long           flags;
+        struct pnv_phb          *phb;
 
         /* A PE can be associated with a single device or an
          * entire bus (& children). In the former case, pdev
@@ -73,15 +76,13 @@ struct pnv_phb {
         spinlock_t              lock;
 
 #ifdef CONFIG_PCI_MSI
-        unsigned long           *msi_map;
         unsigned int            msi_base;
-        unsigned int            msi_count;
-        unsigned int            msi_next;
         unsigned int            msi32_support;
+        struct msi_bitmap       msi_bmp;
 #endif
         int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
-                         unsigned int hwirq, unsigned int is_64,
-                         struct msi_msg *msg);
+                         unsigned int hwirq, unsigned int virq,
+                         unsigned int is_64, struct msi_msg *msg);
         void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
         void (*fixup_phb)(struct pci_controller *hose);
         u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
@@ -109,6 +110,10 @@ struct pnv_phb {
                         unsigned int            *io_segmap;
                         struct pnv_ioda_pe      *pe_array;
 
+                        /* IRQ chip */
+                        int                     irq_chip_init;
+                        struct irq_chip         irq_chip;
+
                         /* Sorted list of used PE's based
                          * on the sequence of creation
                          */
@@ -150,6 +155,7 @@ extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
                                       u64 dma_offset);
 extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
 extern void pnv_pci_init_ioda_hub(struct device_node *np);
-
-
+extern void pnv_pci_init_ioda2_phb(struct device_node *np);
+extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
+                                        u64 *startp, u64 *endp);
 #endif /* __POWERNV_PCI_H */
diff --git a/arch/powerpc/platforms/powernv/smp.c b/arch/powerpc/platforms/powernv/smp.c
index 0bdc735db16f..6a3ecca5b725 100644
--- a/arch/powerpc/platforms/powernv/smp.c
+++ b/arch/powerpc/platforms/powernv/smp.c
@@ -77,9 +77,11 @@ int pnv_smp_kick_cpu(int nr)
         if (!paca[nr].cpu_start && firmware_has_feature(FW_FEATURE_OPALv2)) {
                 pr_devel("OPAL: Starting CPU %d (HW 0x%x)...\n", nr, pcpu);
                 rc = opal_start_cpu(pcpu, start_here);
-                if (rc != OPAL_SUCCESS)
+                if (rc != OPAL_SUCCESS) {
                         pr_warn("OPAL Error %ld starting CPU %d\n",
                                 rc, nr);
+                        return -ENODEV;
+                }
         }
         return smp_generic_kick_cpu(nr);
 }
diff --git a/arch/powerpc/platforms/prep/Kconfig b/arch/powerpc/platforms/prep/Kconfig
deleted file mode 100644
index 1547f66235d9..000000000000
--- a/arch/powerpc/platforms/prep/Kconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-config PPC_PREP
-        bool "PowerPC Reference Platform (PReP) based machines"
-        depends on 6xx && BROKEN
-        select HAVE_PCSPKR_PLATFORM
-        select MPIC
-        select PPC_I8259
-        select PPC_INDIRECT_PCI
-        select PPC_UDBG_16550
-        select PPC_NATIVE
-        default n
-
-config PREP_RESIDUAL
-        bool "Support for PReP Residual Data"
-        depends on PPC_PREP
-        help
-          Some PReP systems have residual data passed to the kernel by the
-          firmware.  This allows detection of memory size, devices present and
-          other useful pieces of information.  Sometimes this information is
-          not present or incorrect, in which case it could lead to the machine 
-          behaving incorrectly.  If this happens, either disable PREP_RESIDUAL
-          or pass the 'noresidual' option to the kernel.
-
-          If you are running a PReP system, say Y here, otherwise say N.
diff --git a/arch/powerpc/platforms/ps3/htab.c b/arch/powerpc/platforms/ps3/htab.c
index 6cc58201db8c..177a2f70700c 100644
--- a/arch/powerpc/platforms/ps3/htab.c
+++ b/arch/powerpc/platforms/ps3/htab.c
@@ -46,7 +46,7 @@ static DEFINE_SPINLOCK(ps3_htab_lock);
 
 static long ps3_hpte_insert(unsigned long hpte_group, unsigned long vpn,
         unsigned long pa, unsigned long rflags, unsigned long vflags,
-        int psize, int ssize)
+        int psize, int apsize, int ssize)
 {
         int result;
         u64 hpte_v, hpte_r;
@@ -62,8 +62,8 @@ static long ps3_hpte_insert(unsigned long hpte_group, unsigned long vpn,
          */
         vflags &= ~HPTE_V_SECONDARY;
 
-        hpte_v = hpte_encode_v(vpn, psize, ssize) | vflags | HPTE_V_VALID;
-        hpte_r = hpte_encode_r(ps3_mm_phys_to_lpar(pa), psize) | rflags;
+        hpte_v = hpte_encode_v(vpn, psize, apsize, ssize) | vflags | HPTE_V_VALID;
+        hpte_r = hpte_encode_r(ps3_mm_phys_to_lpar(pa), psize, apsize) | rflags;
 
         spin_lock_irqsave(&ps3_htab_lock, flags);
 
@@ -117,7 +117,7 @@ static long ps3_hpte_updatepp(unsigned long slot, unsigned long newpp,
         unsigned long flags;
         long ret;
 
-        want_v = hpte_encode_v(vpn, psize, ssize);
+        want_v = hpte_encode_avpn(vpn, psize, ssize);
 
         spin_lock_irqsave(&ps3_htab_lock, flags);
 
diff --git a/arch/powerpc/platforms/ps3/time.c b/arch/powerpc/platforms/ps3/time.c
index 40b5cb433005..cba1e6be68e5 100644
--- a/arch/powerpc/platforms/ps3/time.c
+++ b/arch/powerpc/platforms/ps3/time.c
@@ -89,10 +89,8 @@ static int __init ps3_rtc_init(void)
                 return -ENODEV;
 
         pdev = platform_device_register_simple("rtc-ps3", -1, NULL, 0);
-        if (IS_ERR(pdev))
-                return PTR_ERR(pdev);
 
-        return 0;
+        return PTR_RET(pdev);
 }
 
 module_init(ps3_rtc_init);
diff --git a/arch/powerpc/platforms/pseries/firmware.c b/arch/powerpc/platforms/pseries/firmware.c
index aa3693f7fb27..8c80588abacc 100644
--- a/arch/powerpc/platforms/pseries/firmware.c
+++ b/arch/powerpc/platforms/pseries/firmware.c
@@ -28,18 +28,18 @@
 
 #include "pseries.h"
 
-typedef struct {
+struct hypertas_fw_feature {
     unsigned long val;
     char * name;
-} firmware_feature_t;
+};
 
 /*
  * The names in this table match names in rtas/ibm,hypertas-functions.  If the
  * entry ends in a '*', only upto the '*' is matched.  Otherwise the entire
  * string must match.
  */
-static __initdata firmware_feature_t
-firmware_features_table[FIRMWARE_MAX_FEATURES] = {
+static __initdata struct hypertas_fw_feature
+hypertas_fw_features_table[] = {
         {FW_FEATURE_PFT,                "hcall-pft"},
         {FW_FEATURE_TCE,                "hcall-tce"},
         {FW_FEATURE_SPRG0,              "hcall-sprg0"},
@@ -69,20 +69,18 @@ firmware_features_table[FIRMWARE_MAX_FEATURES] = {
  * device-tree/ibm,hypertas-functions.  Ultimately this functionality may
  * be moved into prom.c prom_init().
  */
-void __init fw_feature_init(const char *hypertas, unsigned long len)
+void __init fw_hypertas_feature_init(const char *hypertas, unsigned long len)
 {
         const char *s;
         int i;
 
-        pr_debug(" -> fw_feature_init()\n");
+        pr_debug(" -> fw_hypertas_feature_init()\n");
 
         for (s = hypertas; s < hypertas + len; s += strlen(s) + 1) {
-                for (i = 0; i < FIRMWARE_MAX_FEATURES; i++) {
-                        const char *name = firmware_features_table[i].name;
+                for (i = 0; i < ARRAY_SIZE(hypertas_fw_features_table); i++) {
+                        const char *name = hypertas_fw_features_table[i].name;
                         size_t size;
-                        /* check value against table of strings */
-                        if (!name)
-                                continue;
+
                         /*
                          * If there is a '*' at the end of name, only check
                          * upto there
@@ -96,10 +94,40 @@ void __init fw_feature_init(const char *hypertas, unsigned long len)
 
                         /* we have a match */
                         powerpc_firmware_features |=
-                                firmware_features_table[i].val;
+                                hypertas_fw_features_table[i].val;
                         break;
                 }
         }
 
-        pr_debug(" <- fw_feature_init()\n");
+        pr_debug(" <- fw_hypertas_feature_init()\n");
+}
+
+struct vec5_fw_feature {
+        unsigned long   val;
+        unsigned int    feature;
+};
+
+static __initdata struct vec5_fw_feature
+vec5_fw_features_table[] = {
+        {FW_FEATURE_TYPE1_AFFINITY,     OV5_TYPE1_AFFINITY},
+        {FW_FEATURE_PRRN,               OV5_PRRN},
+};
+
+void __init fw_vec5_feature_init(const char *vec5, unsigned long len)
+{
+        unsigned int index, feat;
+        int i;
+
+        pr_debug(" -> fw_vec5_feature_init()\n");
+
+        for (i = 0; i < ARRAY_SIZE(vec5_fw_features_table); i++) {
+                index = OV5_INDX(vec5_fw_features_table[i].feature);
+                feat = OV5_FEAT(vec5_fw_features_table[i].feature);
+
+                if (vec5[index] & feat)
+                        powerpc_firmware_features |=
+                                vec5_fw_features_table[i].val;
+        }
+
+        pr_debug(" <- fw_vec5_feature_init()\n");
 }
diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c
index 2372c609fa2b..9a432de363b8 100644
--- a/arch/powerpc/platforms/pseries/hotplug-memory.c
+++ b/arch/powerpc/platforms/pseries/hotplug-memory.c
@@ -72,6 +72,7 @@ unsigned long memory_block_size_bytes(void)
         return get_memblock_size();
 }
 
+#ifdef CONFIG_MEMORY_HOTREMOVE
 static int pseries_remove_memblock(unsigned long base, unsigned int memblock_size)
 {
         unsigned long start, start_pfn;
@@ -153,6 +154,17 @@ static int pseries_remove_memory(struct device_node *np)
         ret = pseries_remove_memblock(base, lmb_size);
         return ret;
 }
+#else
+static inline int pseries_remove_memblock(unsigned long base,
+                                          unsigned int memblock_size)
+{
+        return -EOPNOTSUPP;
+}
+static inline int pseries_remove_memory(struct device_node *np)
+{
+        return -EOPNOTSUPP;
+}
+#endif /* CONFIG_MEMORY_HOTREMOVE */
 
 static int pseries_add_memory(struct device_node *np)
 {
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
index 1b2a174e7c59..86ae364900d6 100644
--- a/arch/powerpc/platforms/pseries/iommu.c
+++ b/arch/powerpc/platforms/pseries/iommu.c
@@ -924,6 +924,13 @@ static void restore_default_window(struct pci_dev *dev,
         __restore_default_window(pci_dev_to_eeh_dev(dev), ddw_restore_token);
 }
 
+struct failed_ddw_pdn {
+        struct device_node *pdn;
+        struct list_head list;
+};
+
+static LIST_HEAD(failed_ddw_pdn_list);
+
 /*
  * If the PE supports dynamic dma windows, and there is space for a table
  * that can map all pages in a linear offset, then setup such a table,
@@ -951,6 +958,7 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
         struct dynamic_dma_window_prop *ddwprop;
         const void *dma_window = NULL;
         unsigned long liobn, offset, size;
+        struct failed_ddw_pdn *fpdn;
 
         mutex_lock(&direct_window_init_mutex);
 
@@ -959,6 +967,18 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
                 goto out_unlock;
 
         /*
+         * If we already went through this for a previous function of
+         * the same device and failed, we don't want to muck with the
+         * DMA window again, as it will race with in-flight operations
+         * and can lead to EEHs. The above mutex protects access to the
+         * list.
+         */
+        list_for_each_entry(fpdn, &failed_ddw_pdn_list, list) {
+                if (!strcmp(fpdn->pdn->full_name, pdn->full_name))
+                        goto out_unlock;
+        }
+
+        /*
          * the ibm,ddw-applicable property holds the tokens for:
          * ibm,query-pe-dma-window
          * ibm,create-pe-dma-window
@@ -1114,6 +1134,12 @@ out_restore_window:
         if (ddw_restore_token)
                 restore_default_window(dev, ddw_restore_token);
 
+        fpdn = kzalloc(sizeof(*fpdn), GFP_KERNEL);
+        if (!fpdn)
+                goto out_unlock;
+        fpdn->pdn = pdn;
+        list_add(&fpdn->list, &failed_ddw_pdn_list);
+
 out_unlock:
         mutex_unlock(&direct_window_init_mutex);
         return dma_addr;
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index 299731e9036b..6d62072a7d5a 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -109,7 +109,7 @@ void vpa_init(int cpu)
 static long pSeries_lpar_hpte_insert(unsigned long hpte_group,
                                      unsigned long vpn, unsigned long pa,
                                      unsigned long rflags, unsigned long vflags,
-                                     int psize, int ssize)
+                                     int psize, int apsize, int ssize)
 {
         unsigned long lpar_rc;
         unsigned long flags;
@@ -121,8 +121,8 @@ static long pSeries_lpar_hpte_insert(unsigned long hpte_group,
                          "pa=%016lx, rflags=%lx, vflags=%lx, psize=%d)\n",
                          hpte_group, vpn,  pa, rflags, vflags, psize);
 
-        hpte_v = hpte_encode_v(vpn, psize, ssize) | vflags | HPTE_V_VALID;
-        hpte_r = hpte_encode_r(pa, psize) | rflags;
+        hpte_v = hpte_encode_v(vpn, psize, apsize, ssize) | vflags | HPTE_V_VALID;
+        hpte_r = hpte_encode_r(pa, psize, apsize) | rflags;
 
         if (!(vflags & HPTE_V_BOLTED))
                 pr_devel(" hpte_v=%016lx, hpte_r=%016lx\n", hpte_v, hpte_r);
@@ -155,7 +155,7 @@ static long pSeries_lpar_hpte_insert(unsigned long hpte_group,
          */
         if (unlikely(lpar_rc != H_SUCCESS)) {
                 if (!(vflags & HPTE_V_BOLTED))
-                        pr_devel(" lpar err %lu\n", lpar_rc);
+                        pr_devel(" lpar err %ld\n", lpar_rc);
                 return -2;
         }
         if (!(vflags & HPTE_V_BOLTED))
diff --git a/arch/powerpc/platforms/pseries/mobility.c b/arch/powerpc/platforms/pseries/mobility.c
index 6573808cc5f3..3d01eee9ffb1 100644
--- a/arch/powerpc/platforms/pseries/mobility.c
+++ b/arch/powerpc/platforms/pseries/mobility.c
@@ -37,14 +37,16 @@ struct update_props_workarea {
 #define UPDATE_DT_NODE  0x02000000
 #define ADD_DT_NODE     0x03000000
 
-static int mobility_rtas_call(int token, char *buf)
+#define MIGRATION_SCOPE (1)
+
+static int mobility_rtas_call(int token, char *buf, s32 scope)
 {
         int rc;
 
         spin_lock(&rtas_data_buf_lock);
 
         memcpy(rtas_data_buf, buf, RTAS_DATA_BUF_SIZE);
-        rc = rtas_call(token, 2, 1, NULL, rtas_data_buf, 1);
+        rc = rtas_call(token, 2, 1, NULL, rtas_data_buf, scope);
         memcpy(buf, rtas_data_buf, RTAS_DATA_BUF_SIZE);
 
         spin_unlock(&rtas_data_buf_lock);
@@ -123,7 +125,7 @@ static int update_dt_property(struct device_node *dn, struct property **prop,
         return 0;
 }
 
-static int update_dt_node(u32 phandle)
+static int update_dt_node(u32 phandle, s32 scope)
 {
         struct update_props_workarea *upwa;
         struct device_node *dn;
@@ -132,6 +134,7 @@ static int update_dt_node(u32 phandle)
         char *prop_data;
         char *rtas_buf;
         int update_properties_token;
+        u32 vd;
 
         update_properties_token = rtas_token("ibm,update-properties");
         if (update_properties_token == RTAS_UNKNOWN_SERVICE)
@@ -151,19 +154,31 @@ static int update_dt_node(u32 phandle)
         upwa->phandle = phandle;
 
         do {
-                rc = mobility_rtas_call(update_properties_token, rtas_buf);
+                rc = mobility_rtas_call(update_properties_token, rtas_buf,
+                                        scope);
                 if (rc < 0)
                         break;
 
                 prop_data = rtas_buf + sizeof(*upwa);
 
-                for (i = 0; i < upwa->nprops; i++) {
+                /* The first element of the buffer is the path of the node
+                 * being updated in the form of a 8 byte string length
+                 * followed by the string. Skip past this to get to the
+                 * properties being updated.
+                 */
+                vd = *prop_data++;
+                prop_data += vd;
+
+                /* The path we skipped over is counted as one of the elements
+                 * returned so start counting at one.
+                 */
+                for (i = 1; i < upwa->nprops; i++) {
                         char *prop_name;
-                        u32 vd;
 
-                        prop_name = prop_data + 1;
+                        prop_name = prop_data;
                         prop_data += strlen(prop_name) + 1;
-                        vd = *prop_data++;
+                        vd = *(u32 *)prop_data;
+                        prop_data += sizeof(vd);
 
                         switch (vd) {
                         case 0x00000000:
@@ -219,7 +234,7 @@ static int add_dt_node(u32 parent_phandle, u32 drc_index)
         return rc;
 }
 
-static int pseries_devicetree_update(void)
+int pseries_devicetree_update(s32 scope)
 {
         char *rtas_buf;
         u32 *data;
@@ -235,7 +250,7 @@ static int pseries_devicetree_update(void)
                 return -ENOMEM;
 
         do {
-                rc = mobility_rtas_call(update_nodes_token, rtas_buf);
+                rc = mobility_rtas_call(update_nodes_token, rtas_buf, scope);
                 if (rc && rc != 1)
                         break;
 
@@ -256,7 +271,7 @@ static int pseries_devicetree_update(void)
                                         delete_dt_node(phandle);
                                         break;
                                 case UPDATE_DT_NODE:
-                                        update_dt_node(phandle);
+                                        update_dt_node(phandle, scope);
                                         break;
                                 case ADD_DT_NODE:
                                         drc_index = *data++;
@@ -276,7 +291,7 @@ void post_mobility_fixup(void)
         int rc;
         int activate_fw_token;
 
-        rc = pseries_devicetree_update();
+        rc = pseries_devicetree_update(MIGRATION_SCOPE);
         if (rc) {
                 printk(KERN_ERR "Initial post-mobility device tree update "
                        "failed: %d\n", rc);
@@ -292,7 +307,7 @@ void post_mobility_fixup(void)
 
         rc = rtas_call(activate_fw_token, 0, 1, NULL);
         if (!rc) {
-                rc = pseries_devicetree_update();
+                rc = pseries_devicetree_update(MIGRATION_SCOPE);
                 if (rc)
                         printk(KERN_ERR "Secondary post-mobility device tree "
                                "update failed: %d\n", rc);
diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c
index e5b084723131..420524e6f8c9 100644
--- a/arch/powerpc/platforms/pseries/msi.c
+++ b/arch/powerpc/platforms/pseries/msi.c
@@ -24,6 +24,7 @@ static int query_token, change_token;
 #define RTAS_RESET_FN           2
 #define RTAS_CHANGE_MSI_FN      3
 #define RTAS_CHANGE_MSIX_FN     4
+#define RTAS_CHANGE_32MSI_FN    5
 
 static struct pci_dn *get_pdn(struct pci_dev *pdev)
 {
@@ -58,7 +59,8 @@ static int rtas_change_msi(struct pci_dn *pdn, u32 func, u32 num_irqs)
 
         seq_num = 1;
         do {
-                if (func == RTAS_CHANGE_MSI_FN || func == RTAS_CHANGE_MSIX_FN)
+                if (func == RTAS_CHANGE_MSI_FN || func == RTAS_CHANGE_MSIX_FN ||
+                    func == RTAS_CHANGE_32MSI_FN)
                         rc = rtas_call(change_token, 6, 4, rtas_ret, addr,
                                         BUID_HI(buid), BUID_LO(buid),
                                         func, num_irqs, seq_num);
@@ -426,9 +428,12 @@ static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec_in, int type)
          */
 again:
         if (type == PCI_CAP_ID_MSI) {
-                rc = rtas_change_msi(pdn, RTAS_CHANGE_MSI_FN, nvec);
+                if (pdn->force_32bit_msi)
+                        rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSI_FN, nvec);
+                else
+                        rc = rtas_change_msi(pdn, RTAS_CHANGE_MSI_FN, nvec);
 
-                if (rc < 0) {
+                if (rc < 0 && !pdn->force_32bit_msi) {
                         pr_debug("rtas_msi: trying the old firmware call.\n");
                         rc = rtas_change_msi(pdn, RTAS_CHANGE_FN, nvec);
                 }
@@ -512,3 +517,13 @@ static int rtas_msi_init(void)
         return 0;
 }
 arch_initcall(rtas_msi_init);
+
+static void quirk_radeon(struct pci_dev *dev)
+{
+        struct pci_dn *pdn = get_pdn(dev);
+
+        if (pdn)
+                pdn->force_32bit_msi = 1;
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x68f2, quirk_radeon);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0xaa68, quirk_radeon);
diff --git a/arch/powerpc/platforms/pseries/pci.c b/arch/powerpc/platforms/pseries/pci.c
index 0b580f413a9a..5f93856cdf47 100644
--- a/arch/powerpc/platforms/pseries/pci.c
+++ b/arch/powerpc/platforms/pseries/pci.c
@@ -108,3 +108,56 @@ static void fixup_winbond_82c105(struct pci_dev* dev)
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
                          fixup_winbond_82c105);
+
+int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
+{
+        struct device_node *dn, *pdn;
+        struct pci_bus *bus;
+        const uint32_t *pcie_link_speed_stats;
+
+        bus = bridge->bus;
+
+        dn = pcibios_get_phb_of_node(bus);
+        if (!dn)
+                return 0;
+
+        for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) {
+                pcie_link_speed_stats = (const uint32_t *) of_get_property(pdn,
+                        "ibm,pcie-link-speed-stats", NULL);
+                if (pcie_link_speed_stats)
+                        break;
+        }
+
+        of_node_put(pdn);
+
+        if (!pcie_link_speed_stats) {
+                pr_err("no ibm,pcie-link-speed-stats property\n");
+                return 0;
+        }
+
+        switch (pcie_link_speed_stats[0]) {
+        case 0x01:
+                bus->max_bus_speed = PCIE_SPEED_2_5GT;
+                break;
+        case 0x02:
+                bus->max_bus_speed = PCIE_SPEED_5_0GT;
+                break;
+        default:
+                bus->max_bus_speed = PCI_SPEED_UNKNOWN;
+                break;
+        }
+
+        switch (pcie_link_speed_stats[1]) {
+        case 0x01:
+                bus->cur_bus_speed = PCIE_SPEED_2_5GT;
+                break;
+        case 0x02:
+                bus->cur_bus_speed = PCIE_SPEED_5_0GT;
+                break;
+        default:
+                bus->cur_bus_speed = PCI_SPEED_UNKNOWN;
+                break;
+        }
+
+        return 0;
+}
diff --git a/arch/powerpc/platforms/pseries/plpar_wrappers.h b/arch/powerpc/platforms/pseries/plpar_wrappers.h
index f368668d97b3..f35787b6a5e0 100644
--- a/arch/powerpc/platforms/pseries/plpar_wrappers.h
+++ b/arch/powerpc/platforms/pseries/plpar_wrappers.h
@@ -58,40 +58,39 @@ static inline long extended_cede_processor(unsigned long latency_hint)
 static inline long vpa_call(unsigned long flags, unsigned long cpu,
                 unsigned long vpa)
 {
-        /* flags are in bits 16-18 (counting from most significant bit) */
-        flags = flags << (63 - 18);
+        flags = flags << H_VPA_FUNC_SHIFT;
 
         return plpar_hcall_norets(H_REGISTER_VPA, flags, cpu, vpa);
 }
 
 static inline long unregister_vpa(unsigned long cpu)
 {
-        return vpa_call(0x5, cpu, 0);
+        return vpa_call(H_VPA_DEREG_VPA, cpu, 0);
 }
 
 static inline long register_vpa(unsigned long cpu, unsigned long vpa)
 {
-        return vpa_call(0x1, cpu, vpa);
+        return vpa_call(H_VPA_REG_VPA, cpu, vpa);
 }
 
 static inline long unregister_slb_shadow(unsigned long cpu)
 {
-        return vpa_call(0x7, cpu, 0);
+        return vpa_call(H_VPA_DEREG_SLB, cpu, 0);
 }
 
 static inline long register_slb_shadow(unsigned long cpu, unsigned long vpa)
 {
-        return vpa_call(0x3, cpu, vpa);
+        return vpa_call(H_VPA_REG_SLB, cpu, vpa);
 }
 
 static inline long unregister_dtl(unsigned long cpu)
 {
-        return vpa_call(0x6, cpu, 0);
+        return vpa_call(H_VPA_DEREG_DTL, cpu, 0);
 }
 
 static inline long register_dtl(unsigned long cpu, unsigned long vpa)
 {
-        return vpa_call(0x2, cpu, vpa);
+        return vpa_call(H_VPA_REG_DTL, cpu, vpa);
 }
 
 static inline long plpar_page_set_loaned(unsigned long vpa)
diff --git a/arch/powerpc/platforms/pseries/processor_idle.c b/arch/powerpc/platforms/pseries/processor_idle.c
index 4d806b419606..4644efa06941 100644
--- a/arch/powerpc/platforms/pseries/processor_idle.c
+++ b/arch/powerpc/platforms/pseries/processor_idle.c
@@ -23,8 +23,8 @@
 #include "pseries.h"
 
 struct cpuidle_driver pseries_idle_driver = {
-        .name =         "pseries_idle",
-        .owner =        THIS_MODULE,
+        .name             = "pseries_idle",
+        .owner            = THIS_MODULE,
 };
 
 #define MAX_IDLE_STATE_COUNT    2
@@ -33,10 +33,8 @@ static int max_idle_state = MAX_IDLE_STATE_COUNT - 1;
 static struct cpuidle_device __percpu *pseries_cpuidle_devices;
 static struct cpuidle_state *cpuidle_state_table;
 
-static inline void idle_loop_prolog(unsigned long *in_purr, ktime_t *kt_before)
+static inline void idle_loop_prolog(unsigned long *in_purr)
 {
-
-        *kt_before = ktime_get();
         *in_purr = mfspr(SPRN_PURR);
         /*
          * Indicate to the HV that we are idle. Now would be
@@ -45,12 +43,10 @@ static inline void idle_loop_prolog(unsigned long *in_purr, ktime_t *kt_before)
         get_lppaca()->idle = 1;
 }
 
-static inline  s64 idle_loop_epilog(unsigned long in_purr, ktime_t kt_before)
+static inline void idle_loop_epilog(unsigned long in_purr)
 {
         get_lppaca()->wait_state_cycles += mfspr(SPRN_PURR) - in_purr;
         get_lppaca()->idle = 0;
-
-        return ktime_to_us(ktime_sub(ktime_get(), kt_before));
 }
 
 static int snooze_loop(struct cpuidle_device *dev,
@@ -58,10 +54,9 @@ static int snooze_loop(struct cpuidle_device *dev,
                         int index)
 {
         unsigned long in_purr;
-        ktime_t kt_before;
         int cpu = dev->cpu;
 
-        idle_loop_prolog(&in_purr, &kt_before);
+        idle_loop_prolog(&in_purr);
         local_irq_enable();
         set_thread_flag(TIF_POLLING_NRFLAG);
 
@@ -75,8 +70,8 @@ static int snooze_loop(struct cpuidle_device *dev,
         clear_thread_flag(TIF_POLLING_NRFLAG);
         smp_mb();
 
-        dev->last_residency =
-                (int)idle_loop_epilog(in_purr, kt_before);
+        idle_loop_epilog(in_purr);
+
         return index;
 }
 
@@ -102,9 +97,8 @@ static int dedicated_cede_loop(struct cpuidle_device *dev,
                                 int index)
 {
         unsigned long in_purr;
-        ktime_t kt_before;
 
-        idle_loop_prolog(&in_purr, &kt_before);
+        idle_loop_prolog(&in_purr);
         get_lppaca()->donate_dedicated_cpu = 1;
 
         ppc64_runlatch_off();
@@ -112,8 +106,9 @@ static int dedicated_cede_loop(struct cpuidle_device *dev,
         check_and_cede_processor();
 
         get_lppaca()->donate_dedicated_cpu = 0;
-        dev->last_residency =
-                (int)idle_loop_epilog(in_purr, kt_before);
+
+        idle_loop_epilog(in_purr);
+
         return index;
 }
 
@@ -122,9 +117,8 @@ static int shared_cede_loop(struct cpuidle_device *dev,
                         int index)
 {
         unsigned long in_purr;
-        ktime_t kt_before;
 
-        idle_loop_prolog(&in_purr, &kt_before);
+        idle_loop_prolog(&in_purr);
 
         /*
          * Yield the processor to the hypervisor.  We return if
@@ -135,8 +129,8 @@ static int shared_cede_loop(struct cpuidle_device *dev,
          */
         check_and_cede_processor();
 
-        dev->last_residency =
-                (int)idle_loop_epilog(in_purr, kt_before);
+        idle_loop_epilog(in_purr);
+
         return index;
 }
 
diff --git a/arch/powerpc/platforms/pseries/pseries.h b/arch/powerpc/platforms/pseries/pseries.h
index 9a3dda07566f..c2a3a258001c 100644
--- a/arch/powerpc/platforms/pseries/pseries.h
+++ b/arch/powerpc/platforms/pseries/pseries.h
@@ -19,7 +19,10 @@ extern void request_event_sources_irqs(struct device_node *np,
 
 #include <linux/of.h>
 
-extern void __init fw_feature_init(const char *hypertas, unsigned long len);
+extern void __init fw_hypertas_feature_init(const char *hypertas,
+                                            unsigned long len);
+extern void __init fw_vec5_feature_init(const char *hypertas,
+                                        unsigned long len);
 
 struct pt_regs;
 
@@ -60,4 +63,8 @@ extern int dlpar_detach_node(struct device_node *);
 /* Snooze Delay, pseries_idle */
 DECLARE_PER_CPU(long, smt_snooze_delay);
 
+/* PCI root bridge prepare function override for pseries */
+struct pci_host_bridge;
+int pseries_root_bridge_prepare(struct pci_host_bridge *bridge);
+
 #endif /* _PSERIES_PSERIES_H */
diff --git a/arch/powerpc/platforms/pseries/reconfig.c b/arch/powerpc/platforms/pseries/reconfig.c
index d6491bd481d0..f93cdf55628c 100644
--- a/arch/powerpc/platforms/pseries/reconfig.c
+++ b/arch/powerpc/platforms/pseries/reconfig.c
@@ -452,7 +452,7 @@ static int proc_ppc64_create_ofdt(void)
 
         ent = proc_create("powerpc/ofdt", S_IWUSR, NULL, &ofdt_fops);
         if (ent)
-                ent->size = 0;
+                proc_set_size(ent, 0);
 
         return 0;
 }
diff --git a/arch/powerpc/platforms/pseries/scanlog.c b/arch/powerpc/platforms/pseries/scanlog.c
index 47f3cda2a68b..b502ab61aafa 100644
--- a/arch/powerpc/platforms/pseries/scanlog.c
+++ b/arch/powerpc/platforms/pseries/scanlog.c
@@ -41,13 +41,12 @@
 
 
 static unsigned int ibm_scan_log_dump;                  /* RTAS token */
-static struct proc_dir_entry *proc_ppc64_scan_log_dump; /* The proc file */
+static unsigned int *scanlog_buffer;                    /* The data buffer */
 
 static ssize_t scanlog_read(struct file *file, char __user *buf,
                             size_t count, loff_t *ppos)
 {
-        struct proc_dir_entry *dp = PDE(file_inode(file));
-        unsigned int *data = (unsigned int *)dp->data;
+        unsigned int *data = scanlog_buffer;
         int status;
         unsigned long len, off;
         unsigned int wait_time;
@@ -135,8 +134,7 @@ static ssize_t scanlog_write(struct file * file, const char __user * buf,
 
 static int scanlog_open(struct inode * inode, struct file * file)
 {
-        struct proc_dir_entry *dp = PDE(inode);
-        unsigned int *data = (unsigned int *)dp->data;
+        unsigned int *data = scanlog_buffer;
 
         if (data[0] != 0) {
                 /* This imperfect test stops a second copy of the
@@ -152,11 +150,9 @@ static int scanlog_open(struct inode * inode, struct file * file)
 
 static int scanlog_release(struct inode * inode, struct file * file)
 {
-        struct proc_dir_entry *dp = PDE(inode);
-        unsigned int *data = (unsigned int *)dp->data;
+        unsigned int *data = scanlog_buffer;
 
         data[0] = 0;
-
         return 0;
 }
 
@@ -172,7 +168,6 @@ const struct file_operations scanlog_fops = {
 static int __init scanlog_init(void)
 {
         struct proc_dir_entry *ent;
-        void *data;
         int err = -ENOMEM;
 
         ibm_scan_log_dump = rtas_token("ibm,scan-log-dump");
@@ -180,29 +175,24 @@ static int __init scanlog_init(void)
                 return -ENODEV;
 
         /* Ideally we could allocate a buffer < 4G */
-        data = kzalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
-        if (!data)
+        scanlog_buffer = kzalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
+        if (!scanlog_buffer)
                 goto err;
 
-        ent = proc_create_data("powerpc/rtas/scan-log-dump", S_IRUSR, NULL,
-                               &scanlog_fops, data);
+        ent = proc_create("powerpc/rtas/scan-log-dump", S_IRUSR, NULL,
+                          &scanlog_fops);
         if (!ent)
                 goto err;
-
-        proc_ppc64_scan_log_dump = ent;
-
         return 0;
 err:
-        kfree(data);
+        kfree(scanlog_buffer);
         return err;
 }
 
 static void __exit scanlog_cleanup(void)
 {
-        if (proc_ppc64_scan_log_dump) {
-                kfree(proc_ppc64_scan_log_dump->data);
-                remove_proc_entry("scan-log-dump", proc_ppc64_scan_log_dump->parent);
-        }
+        remove_proc_entry("powerpc/rtas/scan-log-dump", NULL);
+        kfree(scanlog_buffer);
 }
 
 module_init(scanlog_init);
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 8bcc9ca6682f..c11c8238797c 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -466,6 +466,8 @@ static void __init pSeries_setup_arch(void)
         else
                 ppc_md.enable_pmcs = power4_enable_pmcs;
 
+        ppc_md.pcibios_root_bridge_prepare = pseries_root_bridge_prepare;
+
         if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
                 long rc;
                 if ((rc = pSeries_enable_reloc_on_exc()) != H_SUCCESS) {
@@ -628,25 +630,39 @@ static void __init pSeries_init_early(void)
  * Called very early, MMU is off, device-tree isn't unflattened
  */
 
-static int __init pSeries_probe_hypertas(unsigned long node,
-                                         const char *uname, int depth,
-                                         void *data)
+static int __init pseries_probe_fw_features(unsigned long node,
+                                            const char *uname, int depth,
+                                            void *data)
 {
-        const char *hypertas;
+        const char *prop;
         unsigned long len;
+        static int hypertas_found;
+        static int vec5_found;
 
-        if (depth != 1 ||
-            (strcmp(uname, "rtas") != 0 && strcmp(uname, "rtas@0") != 0))
+        if (depth != 1)
                 return 0;
 
-        hypertas = of_get_flat_dt_prop(node, "ibm,hypertas-functions", &len);
-        if (!hypertas)
-                return 1;
+        if (!strcmp(uname, "rtas") || !strcmp(uname, "rtas@0")) {
+                prop = of_get_flat_dt_prop(node, "ibm,hypertas-functions",
+                                           &len);
+                if (prop) {
+                        powerpc_firmware_features |= FW_FEATURE_LPAR;
+                        fw_hypertas_feature_init(prop, len);
+                }
 
-        powerpc_firmware_features |= FW_FEATURE_LPAR;
-        fw_feature_init(hypertas, len);
+                hypertas_found = 1;
+        }
 
-        return 1;
+        if (!strcmp(uname, "chosen")) {
+                prop = of_get_flat_dt_prop(node, "ibm,architecture-vec-5",
+                                           &len);
+                if (prop)
+                        fw_vec5_feature_init(prop, len);
+
+                vec5_found = 1;
+        }
+
+        return hypertas_found && vec5_found;
 }
 
 static int __init pSeries_probe(void)
@@ -669,7 +685,7 @@ static int __init pSeries_probe(void)
         pr_debug("pSeries detected, looking for LPAR capability...\n");
 
         /* Now try to figure out if we are running on LPAR */
-        of_scan_flat_dt(pSeries_probe_hypertas, NULL);
+        of_scan_flat_dt(pseries_probe_fw_features, NULL);
 
         if (firmware_has_feature(FW_FEATURE_LPAR))
                 hpte_init_lpar();
diff --git a/arch/powerpc/platforms/wsp/Kconfig b/arch/powerpc/platforms/wsp/Kconfig
index 79d2225b7608..422a175b10ee 100644
--- a/arch/powerpc/platforms/wsp/Kconfig
+++ b/arch/powerpc/platforms/wsp/Kconfig
@@ -9,7 +9,6 @@ config PPC_WSP
         select PCI
         select PPC_IO_WORKAROUNDS if PCI
         select PPC_INDIRECT_PIO if PCI
-        select PPC_WSP_COPRO
         default n
 
 menu "WSP platform selection"
@@ -29,7 +28,3 @@ config PPC_CHROMA
         default y
 
 endmenu
-
-config PPC_A2_DD2
-        bool "Support for DD2 based A2/WSP systems"
-        depends on PPC_A2
diff --git a/arch/powerpc/platforms/wsp/wsp_pci.c b/arch/powerpc/platforms/wsp/wsp_pci.c
index 8e22f561d171..62cb527493e7 100644
--- a/arch/powerpc/platforms/wsp/wsp_pci.c
+++ b/arch/powerpc/platforms/wsp/wsp_pci.c
@@ -502,7 +502,7 @@ static void __init wsp_pcie_configure_hw(struct pci_controller *hose)
                  (~(hose->mem_resources[0].end -
                     hose->mem_resources[0].start)) & 0x3ffffff0000ul);
         out_be64(hose->cfg_data + PCIE_REG_M32A_START_ADDR,
-                 (hose->mem_resources[0].start - hose->pci_mem_offset) | 1);
+                 (hose->mem_resources[0].start - hose->mem_offset[0]) | 1);
 
         /* Clear all TVT entries
          *
diff --git a/arch/powerpc/sysdev/Kconfig b/arch/powerpc/sysdev/Kconfig
index a84fecf63c4d..ab4cb5476472 100644
--- a/arch/powerpc/sysdev/Kconfig
+++ b/arch/powerpc/sysdev/Kconfig
@@ -19,6 +19,7 @@ config PPC_MSI_BITMAP
         default y if MPIC
         default y if FSL_PCI
         default y if PPC4xx_MSI
+        default y if POWERNV_MSI
 
 source "arch/powerpc/sysdev/xics/Kconfig"
 
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 178c99427b1c..ab02db3d02d8 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -333,6 +333,8 @@ static int fsl_of_msi_remove(struct platform_device *ofdev)
         return 0;
 }
 
+static struct lock_class_key fsl_msi_irq_class;
+
 static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
                                int offset, int irq_index)
 {
@@ -351,7 +353,7 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
                 dev_err(&dev->dev, "No memory for MSI cascade data\n");
                 return -ENOMEM;
         }
-
+        irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class);
         msi->msi_virqs[irq_index] = virt_msir;
         cascade_data->index = offset;
         cascade_data->msi_data = msi;
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 682084dba19b..028ac1f71b51 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -54,16 +54,63 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
         return;
 }
 
-static int __init fsl_pcie_check_link(struct pci_controller *hose)
+static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
+                                    int, int, u32 *);
+
+static int fsl_pcie_check_link(struct pci_controller *hose)
 {
-        u32 val;
+        u32 val = 0;
+
+        if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
+                if (hose->ops->read == fsl_indirect_read_config) {
+                        struct pci_bus bus;
+                        bus.number = 0;
+                        bus.sysdata = hose;
+                        bus.ops = hose->ops;
+                        indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
+                } else
+                        early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
+                if (val < PCIE_LTSSM_L0)
+                        return 1;
+        } else {
+                struct ccsr_pci __iomem *pci = hose->private_data;
+                /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
+                val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
+                                >> PEX_CSR0_LTSSM_SHIFT;
+                if (val != PEX_CSR0_LTSSM_L0)
+                        return 1;
+        }
 
-        early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
-        if (val < PCIE_LTSSM_L0)
-                return 1;
         return 0;
 }
 
+static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
+                                    int offset, int len, u32 *val)
+{
+        struct pci_controller *hose = pci_bus_to_host(bus);
+
+        if (fsl_pcie_check_link(hose))
+                hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
+        else
+                hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
+
+        return indirect_read_config(bus, devfn, offset, len, val);
+}
+
+static struct pci_ops fsl_indirect_pci_ops =
+{
+        .read = fsl_indirect_read_config,
+        .write = indirect_write_config,
+};
+
+static void __init fsl_setup_indirect_pci(struct pci_controller* hose,
+                                          resource_size_t cfg_addr,
+                                          resource_size_t cfg_data, u32 flags)
+{
+        setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
+        hose->ops = &fsl_indirect_pci_ops;
+}
+
 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
 
 #define MAX_PHYS_ADDR_BITS      40
@@ -106,7 +153,7 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
                 flags |= 0x10000000; /* enable relaxed ordering */
 
         for (i = 0; size > 0; i++) {
-                unsigned int bits = min(__ilog2(size),
+                unsigned int bits = min(ilog2(size),
                                         __ffs(pci_addr | phys_addr));
 
                 if (index + i >= 5)
@@ -126,13 +173,12 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
 }
 
 /* atmu setup for fsl pci/pcie controller */
-static void setup_pci_atmu(struct pci_controller *hose,
-                                  struct resource *rsrc)
+static void setup_pci_atmu(struct pci_controller *hose)
 {
-        struct ccsr_pci __iomem *pci;
+        struct ccsr_pci __iomem *pci = hose->private_data;
         int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
         u64 mem, sz, paddr_hi = 0;
-        u64 paddr_lo = ULLONG_MAX;
+        u64 offset = 0, paddr_lo = ULLONG_MAX;
         u32 pcicsrbar = 0, pcicsrbar_sz;
         u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
                         PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
@@ -140,15 +186,6 @@ static void setup_pci_atmu(struct pci_controller *hose,
         const u64 *reg;
         int len;
 
-        pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
-                 (u64)rsrc->start, (u64)resource_size(rsrc));
-
-        pci = ioremap(rsrc->start, resource_size(rsrc));
-        if (!pci) {
-            dev_err(hose->parent, "Unable to map ATMU registers\n");
-            return;
-        }
-
         if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
                 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
                         win_idx = 2;
@@ -171,8 +208,9 @@ static void setup_pci_atmu(struct pci_controller *hose,
                 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
                 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
 
-                n = setup_one_atmu(pci, j, &hose->mem_resources[i],
-                                   hose->pci_mem_offset);
+                /* We assume all memory resources have the same offset */
+                offset = hose->mem_offset[i];
+                n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
 
                 if (n < 0 || j >= 5) {
                         pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
@@ -196,23 +234,23 @@ static void setup_pci_atmu(struct pci_controller *hose,
                         out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
                         /* Enable, IO R/W */
                         out_be32(&pci->pow[j].powar, 0x80088000
-                                | (__ilog2(hose->io_resource.end
+                                | (ilog2(hose->io_resource.end
                                 - hose->io_resource.start + 1) - 1));
                 }
         }
 
         /* convert to pci address space */
-        paddr_hi -= hose->pci_mem_offset;
-        paddr_lo -= hose->pci_mem_offset;
+        paddr_hi -= offset;
+        paddr_lo -= offset;
 
         if (paddr_hi == paddr_lo) {
                 pr_err("%s: No outbound window space\n", name);
-                goto out;
+                return;
         }
 
         if (paddr_lo == 0) {
                 pr_err("%s: No space for inbound window\n", name);
-                goto out;
+                return;
         }
 
         /* setup PCSRBAR/PEXCSRBAR */
@@ -261,7 +299,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
         }
 
         sz = min(mem, paddr_lo);
-        mem_log = __ilog2_u64(sz);
+        mem_log = ilog2(sz);
 
         /* PCIe can overmap inbound & outbound since RX & TX are separated */
         if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
@@ -290,7 +328,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
                  * SWIOTLB and access the full range of memory
                  */
                 if (sz != mem) {
-                        mem_log = __ilog2_u64(mem);
+                        mem_log = ilog2(mem);
 
                         /* Size window up if we dont fit in exact power-of-2 */
                         if ((1ull << mem_log) != mem)
@@ -327,7 +365,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
                 sz -= 1ull << mem_log;
 
                 if (sz) {
-                        mem_log = __ilog2_u64(sz);
+                        mem_log = ilog2(sz);
                         piwar |= (mem_log - 1);
 
                         out_be32(&pci->piw[win_idx].pitar,  paddr >> 12);
@@ -358,9 +396,6 @@ static void setup_pci_atmu(struct pci_controller *hose,
                 pr_info("%s: DMA window size is 0x%llx\n", name,
                         (u64)hose->dma_window_size);
         }
-
-out:
-        iounmap(pci);
 }
 
 static void __init setup_pci_cmd(struct pci_controller *hose)
@@ -429,6 +464,7 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
         const int *bus_range;
         u8 hdr_type, progif;
         struct device_node *dev;
+        struct ccsr_pci __iomem *pci;
 
         dev = pdev->dev.of_node;
 
@@ -461,8 +497,18 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
         hose->first_busno = bus_range ? bus_range[0] : 0x0;
         hose->last_busno = bus_range ? bus_range[1] : 0xff;
 
-        setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
-                PPC_INDIRECT_TYPE_BIG_ENDIAN);
+        pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
+                 (u64)rsrc.start, (u64)resource_size(&rsrc));
+
+        pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
+        if (!hose->private_data)
+                goto no_bridge;
+
+        fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
+                               PPC_INDIRECT_TYPE_BIG_ENDIAN);
+
+        if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
+                hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
 
         if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
                 /* For PCIE read HEADER_TYPE to identify controler mode */
@@ -500,11 +546,12 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
         pci_process_bridge_OF_ranges(hose, dev, is_primary);
 
         /* Setup PEX window registers */
-        setup_pci_atmu(hose, &rsrc);
+        setup_pci_atmu(hose);
 
         return 0;
 
 no_bridge:
+        iounmap(hose->private_data);
         /* unmap cfg_data & cfg_addr separately if not on same page */
         if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
             ((unsigned long)hose->cfg_addr & PAGE_MASK))
@@ -681,6 +728,7 @@ static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
         WARN_ON(hose->dn->data);
         hose->dn->data = pcie;
         hose->ops = &mpc83xx_pcie_ops;
+        hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
 
         out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
         out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
@@ -766,8 +814,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
                 if (ret)
                         goto err0;
         } else {
-                setup_indirect_pci(hose, rsrc_cfg.start,
-                                   rsrc_cfg.start + 4, 0);
+                fsl_setup_indirect_pci(hose, rsrc_cfg.start,
+                                       rsrc_cfg.start + 4, 0);
         }
 
         printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
@@ -836,6 +884,7 @@ static const struct of_device_id pci_ids[] = {
         { .compatible = "fsl,qoriq-pcie-v2.2", },
         { .compatible = "fsl,qoriq-pcie-v2.3", },
         { .compatible = "fsl,qoriq-pcie-v2.4", },
+        { .compatible = "fsl,qoriq-pcie-v3.0", },
 
         /*
          * The following entries are for compatibility with older device
@@ -927,7 +976,7 @@ static int fsl_pci_resume(struct device *dev)
                 return -ENODEV;
         }
 
-        setup_pci_atmu(hose, &pci_rsrc);
+        setup_pci_atmu(hose);
 
         return 0;
 }
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index c495c00c8740..72b5625330e2 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -14,9 +14,12 @@
 #ifndef __POWERPC_FSL_PCI_H
 #define __POWERPC_FSL_PCI_H
 
+struct platform_device;
+
 #define PCIE_LTSSM      0x0404          /* PCIE Link Training and Status */
 #define PCIE_LTSSM_L0   0x16            /* L0 state */
 #define PCIE_IP_REV_2_2         0x02080202 /* PCIE IP block version Rev2.2 */
+#define PCIE_IP_REV_3_0         0x02080300 /* PCIE IP block version Rev3.0 */
 #define PIWAR_EN                0x80000000      /* Enable */
 #define PIWAR_PF                0x20000000      /* prefetch */
 #define PIWAR_TGI_LOCAL         0x00f00000      /* target - local memory */
@@ -89,6 +92,16 @@ struct ccsr_pci {
         __be32  pex_err_cap_r1;         /* 0x.e2c - PCIE error capture register 0 */
         __be32  pex_err_cap_r2;         /* 0x.e30 - PCIE error capture register 0 */
         __be32  pex_err_cap_r3;         /* 0x.e34 - PCIE error capture register 0 */
+        u8      res_e38[200];
+        __be32  pdb_stat;               /* 0x.f00 - PCIE Debug Status */
+        u8      res_f04[16];
+        __be32  pex_csr0;               /* 0x.f14 - PEX Control/Status register 0*/
+#define PEX_CSR0_LTSSM_MASK     0xFC
+#define PEX_CSR0_LTSSM_SHIFT    2
+#define PEX_CSR0_LTSSM_L0       0x11
+        __be32  pex_csr1;               /* 0x.f18 - PEX Control/Status register 1*/
+        u8      res_f1c[228];
+
 };
 
 extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c
index 82fdad885d20..c6c8b526a4f6 100644
--- a/arch/powerpc/sysdev/indirect_pci.c
+++ b/arch/powerpc/sysdev/indirect_pci.c
@@ -20,9 +20,8 @@
 #include <asm/pci-bridge.h>
 #include <asm/machdep.h>
 
-static int
-indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
-                     int len, u32 *val)
+int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
+                         int offset, int len, u32 *val)
 {
         struct pci_controller *hose = pci_bus_to_host(bus);
         volatile void __iomem *cfg_data;
@@ -78,9 +77,8 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
         return PCIBIOS_SUCCESSFUL;
 }
 
-static int
-indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
-                      int len, u32 val)
+int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
+                          int offset, int len, u32 val)
 {
         struct pci_controller *hose = pci_bus_to_host(bus);
         volatile void __iomem *cfg_data;
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index d30e6a676c89..ee21b5e71aec 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1001,8 +1001,12 @@ static int mpic_host_map(struct irq_domain *h, unsigned int virq,
 
         if (hw == mpic->spurious_vec)
                 return -EINVAL;
-        if (mpic->protected && test_bit(hw, mpic->protected))
-                return -EINVAL;
+        if (mpic->protected && test_bit(hw, mpic->protected)) {
+                pr_warning("mpic: Mapping of source 0x%x failed, "
+                           "source protected by firmware !\n",\
+                           (unsigned int)hw);
+                return -EPERM;
+        }
 
 #ifdef CONFIG_SMP
         else if (hw >= mpic->ipi_vecs[0]) {
@@ -1029,8 +1033,12 @@ static int mpic_host_map(struct irq_domain *h, unsigned int virq,
         if (mpic_map_error_int(mpic, virq, hw))
                 return 0;
 
-        if (hw >= mpic->num_sources)
+        if (hw >= mpic->num_sources) {
+                pr_warning("mpic: Mapping of source 0x%x failed, "
+                           "source out of range !\n",\
+                           (unsigned int)hw);
                 return -EINVAL;
+        }
 
         mpic_msi_reserve_hwirq(mpic, hw);
 
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index 56e8b3c3c890..64603a10b863 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -257,6 +257,7 @@ static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
         /* Setup outbound memory windows */
         for (i = j = 0; i < 3; i++) {
                 struct resource *res = &hose->mem_resources[i];
+                resource_size_t offset = hose->mem_offset[i];
 
                 /* we only care about memory windows */
                 if (!(res->flags & IORESOURCE_MEM))
@@ -270,7 +271,7 @@ static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
                 /* Configure the resource */
                 if (ppc4xx_setup_one_pci_PMM(hose, reg,
                                              res->start,
-                                             res->start - hose->pci_mem_offset,
+                                             res->start - offset,
                                              resource_size(res),
                                              res->flags,
                                              j) == 0) {
@@ -279,7 +280,7 @@ static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
                         /* If the resource PCI address is 0 then we have our
                          * ISA memory hole
                          */
-                        if (res->start == hose->pci_mem_offset)
+                        if (res->start == offset)
                                 found_isa_hole = 1;
                 }
         }
@@ -457,6 +458,7 @@ static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
         /* Setup outbound memory windows */
         for (i = j = 0; i < 3; i++) {
                 struct resource *res = &hose->mem_resources[i];
+                resource_size_t offset = hose->mem_offset[i];
 
                 /* we only care about memory windows */
                 if (!(res->flags & IORESOURCE_MEM))
@@ -470,7 +472,7 @@ static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
                 /* Configure the resource */
                 if (ppc4xx_setup_one_pcix_POM(hose, reg,
                                               res->start,
-                                              res->start - hose->pci_mem_offset,
+                                              res->start - offset,
                                               resource_size(res),
                                               res->flags,
                                               j) == 0) {
@@ -479,7 +481,7 @@ static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
                         /* If the resource PCI address is 0 then we have our
                          * ISA memory hole
                          */
-                        if (res->start == hose->pci_mem_offset)
+                        if (res->start == offset)
                                 found_isa_hole = 1;
                 }
         }
@@ -1792,6 +1794,7 @@ static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
         /* Setup outbound memory windows */
         for (i = j = 0; i < 3; i++) {
                 struct resource *res = &hose->mem_resources[i];
+                resource_size_t offset = hose->mem_offset[i];
 
                 /* we only care about memory windows */
                 if (!(res->flags & IORESOURCE_MEM))
@@ -1805,7 +1808,7 @@ static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
                 /* Configure the resource */
                 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
                                                res->start,
-                                               res->start - hose->pci_mem_offset,
+                                               res->start - offset,
                                                resource_size(res),
                                                res->flags,
                                                j) == 0) {
@@ -1814,7 +1817,7 @@ static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
                         /* If the resource PCI address is 0 then we have our
                          * ISA memory hole
                          */
-                        if (res->start == hose->pci_mem_offset)
+                        if (res->start == offset)
                                 found_isa_hole = 1;
                 }
         }
diff --git a/arch/powerpc/sysdev/qe_lib/Kconfig b/arch/powerpc/sysdev/qe_lib/Kconfig
index 41ac3dfac98e..3c251993bacd 100644
--- a/arch/powerpc/sysdev/qe_lib/Kconfig
+++ b/arch/powerpc/sysdev/qe_lib/Kconfig
@@ -22,6 +22,6 @@ config UCC
 
 config QE_USB
         bool
-        default y if USB_GADGET_FSL_QE
+        default y if USB_FSL_QE
         help
           QE USB Controller support
diff --git a/arch/powerpc/sysdev/rtc_cmos_setup.c b/arch/powerpc/sysdev/rtc_cmos_setup.c
index 9afba924e94f..af79e1ea74b6 100644
--- a/arch/powerpc/sysdev/rtc_cmos_setup.c
+++ b/arch/powerpc/sysdev/rtc_cmos_setup.c
@@ -62,10 +62,7 @@ static int  __init add_rtc(void)
         pd = platform_device_register_simple("rtc_cmos", -1,
                                              &res[0], num_res);
 
-        if (IS_ERR(pd))
-                return PTR_ERR(pd);
-
-        return 0;
+        return PTR_RET(pd);
 }
 fs_initcall(add_rtc);
 
diff --git a/arch/powerpc/sysdev/xics/icp-native.c b/arch/powerpc/sysdev/xics/icp-native.c
index 48861d3fcd07..7cd728b3b5e4 100644
--- a/arch/powerpc/sysdev/xics/icp-native.c
+++ b/arch/powerpc/sysdev/xics/icp-native.c
@@ -51,6 +51,12 @@ static struct icp_ipl __iomem *icp_native_regs[NR_CPUS];
 static inline unsigned int icp_native_get_xirr(void)
 {
         int cpu = smp_processor_id();
+        unsigned int xirr;
+
+        /* Handled an interrupt latched by KVM */
+        xirr = kvmppc_get_xics_latch();
+        if (xirr)
+                return xirr;
 
         return in_be32(&icp_native_regs[cpu]->xirr.word);
 }
@@ -81,7 +87,7 @@ static void icp_native_set_cpu_priority(unsigned char cppr)
         iosync();
 }
 
-static void icp_native_eoi(struct irq_data *d)
+void icp_native_eoi(struct irq_data *d)
 {
         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
 
@@ -138,6 +144,7 @@ static unsigned int icp_native_get_irq(void)
 
 static void icp_native_cause_ipi(int cpu, unsigned long data)
 {
+        kvmppc_set_host_ipi(cpu, 1);
         icp_native_set_qirr(cpu, IPI_PRIORITY);
 }
 
@@ -151,6 +158,7 @@ static irqreturn_t icp_native_ipi_action(int irq, void *dev_id)
 {
         int cpu = smp_processor_id();
 
+        kvmppc_set_host_ipi(cpu, 0);
         icp_native_set_qirr(cpu, 0xff);
 
         return smp_ipi_demux();
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 13f85defabed..96bf5bd30fbc 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -1430,7 +1430,7 @@ static void excprint(struct pt_regs *fp)
         printf("    sp: %lx\n", fp->gpr[1]);
         printf("   msr: %lx\n", fp->msr);
 
-        if (trap == 0x300 || trap == 0x380 || trap == 0x600) {
+        if (trap == 0x300 || trap == 0x380 || trap == 0x600 || trap == 0x200) {
                 printf("   dar: %lx\n", fp->dar);
                 if (trap != 0x380)
                         printf(" dsisr: %lx\n", fp->dsisr);
@@ -2947,7 +2947,7 @@ static void sysrq_handle_xmon(int key)
 
 static struct sysrq_key_op sysrq_xmon_op = {
         .handler =      sysrq_handle_xmon,
-        .help_msg =     "Xmon",
+        .help_msg =     "xmon(x)",
         .action_msg =   "Entering xmon",
 };
 
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index eb8fb629f00b..2c9789da0e24 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -91,6 +91,7 @@ config S390
         select ARCH_INLINE_WRITE_UNLOCK_BH
         select ARCH_INLINE_WRITE_UNLOCK_IRQ
         select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE
+        select ARCH_HAS_DEBUG_STRICT_USER_COPY_CHECKS
         select ARCH_SAVE_PAGE_KEYS if HIBERNATION
         select ARCH_WANT_IPC_PARSE_VERSION
         select BUILDTIME_EXTABLE_SORT
@@ -131,7 +132,6 @@ config S390
         select HAVE_PERF_EVENTS
         select HAVE_REGS_AND_STACK_ACCESS_API
         select HAVE_SYSCALL_TRACEPOINTS
-        select HAVE_SYSCALL_WRAPPERS
         select HAVE_UID16 if 32BIT
         select HAVE_VIRT_CPU_ACCOUNTING
         select VIRT_TO_BUS
@@ -375,19 +375,6 @@ config PACK_STACK
 
           Say Y if you are unsure.
 
-config SMALL_STACK
-        def_bool n
-        prompt "Use 8kb for kernel stack instead of 16kb"
-        depends on PACK_STACK && 64BIT && !LOCKDEP
-        help
-          If you say Y here and the compiler supports the -mkernel-backchain
-          option the kernel will use a smaller kernel stack size. The reduced
-          size is 8kb instead of 16kb. This allows to run more threads on a
-          system and reduces the pressure on the memory management for higher
-          order page allocations.
-
-          Say N if you are unsure.
-
 config CHECK_STACK
         def_bool y
         prompt "Detect kernel stack overflow"
diff --git a/arch/s390/Kconfig.debug b/arch/s390/Kconfig.debug
index fc32a2df4974..c56878e1245f 100644
--- a/arch/s390/Kconfig.debug
+++ b/arch/s390/Kconfig.debug
@@ -17,20 +17,6 @@ config STRICT_DEVMEM
 
           If you are unsure, say Y.
 
-config DEBUG_STRICT_USER_COPY_CHECKS
-        def_bool n
-        prompt "Strict user copy size checks"
-        ---help---
-          Enabling this option turns a certain set of sanity checks for user
-          copy operations into compile time warnings.
-
-          The copy_from_user() etc checks are there to help test if there
-          are sufficient security checks on the length argument of
-          the copy operation, by having gcc prove that the argument is
-          within bounds.
-
-          If unsure, or if you run an older (pre 4.4) gcc, say N.
-
 config S390_PTDUMP
         bool "Export kernel pagetable layout to userspace via debugfs"
         depends on DEBUG_KERNEL
diff --git a/arch/s390/Makefile b/arch/s390/Makefile
index 7e3ce78d4290..a7d68a467ce8 100644
--- a/arch/s390/Makefile
+++ b/arch/s390/Makefile
@@ -55,22 +55,12 @@ cflags-$(CONFIG_FRAME_POINTER) += -fno-optimize-sibling-calls
 ifeq ($(call cc-option-yn,-mkernel-backchain),y)
 cflags-$(CONFIG_PACK_STACK)  += -mkernel-backchain -D__PACK_STACK
 aflags-$(CONFIG_PACK_STACK)  += -D__PACK_STACK
-cflags-$(CONFIG_SMALL_STACK) += -D__SMALL_STACK
-aflags-$(CONFIG_SMALL_STACK) += -D__SMALL_STACK
-ifdef CONFIG_SMALL_STACK
-STACK_SIZE := $(shell echo $$(($(STACK_SIZE)/2)) )
-endif
 endif
 
 # new style option for packed stacks
 ifeq ($(call cc-option-yn,-mpacked-stack),y)
 cflags-$(CONFIG_PACK_STACK)  += -mpacked-stack -D__PACK_STACK
 aflags-$(CONFIG_PACK_STACK)  += -D__PACK_STACK
-cflags-$(CONFIG_SMALL_STACK) += -D__SMALL_STACK
-aflags-$(CONFIG_SMALL_STACK) += -D__SMALL_STACK
-ifdef CONFIG_SMALL_STACK
-STACK_SIZE := $(shell echo $$(($(STACK_SIZE)/2)) )
-endif
 endif
 
 ifeq ($(call cc-option-yn,-mstack-size=8192 -mstack-guard=128),y)
diff --git a/arch/s390/hypfs/hypfs_dbfs.c b/arch/s390/hypfs/hypfs_dbfs.c
index 9fd4a40c6752..bb5dd496614f 100644
--- a/arch/s390/hypfs/hypfs_dbfs.c
+++ b/arch/s390/hypfs/hypfs_dbfs.c
@@ -105,9 +105,7 @@ void hypfs_dbfs_remove_file(struct hypfs_dbfs_file *df)
 int hypfs_dbfs_init(void)
 {
         dbfs_dir = debugfs_create_dir("s390_hypfs", NULL);
-        if (IS_ERR(dbfs_dir))
-                return PTR_ERR(dbfs_dir);
-        return 0;
+        return PTR_RET(dbfs_dir);
 }
 
 void hypfs_dbfs_exit(void)
diff --git a/arch/s390/include/asm/bitops.h b/arch/s390/include/asm/bitops.h
index 15422933c60b..4d8604e311f3 100644
--- a/arch/s390/include/asm/bitops.h
+++ b/arch/s390/include/asm/bitops.h
@@ -61,8 +61,6 @@ extern const char _sb_findmap[];
 
 #ifndef CONFIG_64BIT
 
-#define __BITOPS_ALIGN          3
-#define __BITOPS_WORDSIZE       32
 #define __BITOPS_OR             "or"
 #define __BITOPS_AND            "nr"
 #define __BITOPS_XOR            "xr"
@@ -81,8 +79,6 @@ extern const char _sb_findmap[];
 
 #else /* CONFIG_64BIT */
 
-#define __BITOPS_ALIGN          7
-#define __BITOPS_WORDSIZE       64
 #define __BITOPS_OR             "ogr"
 #define __BITOPS_AND            "ngr"
 #define __BITOPS_XOR            "xgr"
@@ -101,8 +97,7 @@ extern const char _sb_findmap[];
 
 #endif /* CONFIG_64BIT */
 
-#define __BITOPS_WORDS(bits) (((bits)+__BITOPS_WORDSIZE-1)/__BITOPS_WORDSIZE)
-#define __BITOPS_BARRIER() asm volatile("" : : : "memory")
+#define __BITOPS_WORDS(bits) (((bits) + BITS_PER_LONG - 1) / BITS_PER_LONG)
 
 #ifdef CONFIG_SMP
 /*
@@ -114,9 +109,9 @@ static inline void set_bit_cs(unsigned long nr, volatile unsigned long *ptr)
 
         addr = (unsigned long) ptr;
         /* calculate address for CS */
-        addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
+        addr += (nr ^ (nr & (BITS_PER_LONG - 1))) >> 3;
         /* make OR mask */
-        mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
+        mask = 1UL << (nr & (BITS_PER_LONG - 1));
         /* Do the atomic update. */
         __BITOPS_LOOP(old, new, addr, mask, __BITOPS_OR);
 }
@@ -130,9 +125,9 @@ static inline void clear_bit_cs(unsigned long nr, volatile unsigned long *ptr)
 
         addr = (unsigned long) ptr;
         /* calculate address for CS */
-        addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
+        addr += (nr ^ (nr & (BITS_PER_LONG - 1))) >> 3;
         /* make AND mask */
-        mask = ~(1UL << (nr & (__BITOPS_WORDSIZE - 1)));
+        mask = ~(1UL << (nr & (BITS_PER_LONG - 1)));
         /* Do the atomic update. */
         __BITOPS_LOOP(old, new, addr, mask, __BITOPS_AND);
 }
@@ -146,9 +141,9 @@ static inline void change_bit_cs(unsigned long nr, volatile unsigned long *ptr)
 
         addr = (unsigned long) ptr;
         /* calculate address for CS */
-        addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
+        addr += (nr ^ (nr & (BITS_PER_LONG - 1))) >> 3;
         /* make XOR mask */
-        mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
+        mask = 1UL << (nr & (BITS_PER_LONG - 1));
         /* Do the atomic update. */
         __BITOPS_LOOP(old, new, addr, mask, __BITOPS_XOR);
 }
@@ -163,12 +158,12 @@ test_and_set_bit_cs(unsigned long nr, volatile unsigned long *ptr)
 
         addr = (unsigned long) ptr;
         /* calculate address for CS */
-        addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
+        addr += (nr ^ (nr & (BITS_PER_LONG - 1))) >> 3;
         /* make OR/test mask */
-        mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
+        mask = 1UL << (nr & (BITS_PER_LONG - 1));
         /* Do the atomic update. */
         __BITOPS_LOOP(old, new, addr, mask, __BITOPS_OR);
-        __BITOPS_BARRIER();
+        barrier();
         return (old & mask) != 0;
 }
 
@@ -182,12 +177,12 @@ test_and_clear_bit_cs(unsigned long nr, volatile unsigned long *ptr)
 
         addr = (unsigned long) ptr;
         /* calculate address for CS */
-        addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
+        addr += (nr ^ (nr & (BITS_PER_LONG - 1))) >> 3;
         /* make AND/test mask */
-        mask = ~(1UL << (nr & (__BITOPS_WORDSIZE - 1)));
+        mask = ~(1UL << (nr & (BITS_PER_LONG - 1)));
         /* Do the atomic update. */
         __BITOPS_LOOP(old, new, addr, mask, __BITOPS_AND);
-        __BITOPS_BARRIER();
+        barrier();
         return (old ^ new) != 0;
 }
 
@@ -201,12 +196,12 @@ test_and_change_bit_cs(unsigned long nr, volatile unsigned long *ptr)
 
         addr = (unsigned long) ptr;
         /* calculate address for CS */
-        addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
+        addr += (nr ^ (nr & (BITS_PER_LONG - 1))) >> 3;
         /* make XOR/test mask */
-        mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
+        mask = 1UL << (nr & (BITS_PER_LONG - 1));
         /* Do the atomic update. */
         __BITOPS_LOOP(old, new, addr, mask, __BITOPS_XOR);
-        __BITOPS_BARRIER();
+        barrier();
         return (old & mask) != 0;
 }
 #endif /* CONFIG_SMP */
@@ -218,7 +213,7 @@ static inline void __set_bit(unsigned long nr, volatile unsigned long *ptr)
 {
         unsigned long addr;
 
-        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        addr = (unsigned long) ptr + ((nr ^ (BITS_PER_LONG - 8)) >> 3);
         asm volatile(
                 "       oc      %O0(1,%R0),%1"
                 : "=Q" (*(char *) addr) : "Q" (_oi_bitmap[nr & 7]) : "cc" );
@@ -229,7 +224,7 @@ __constant_set_bit(const unsigned long nr, volatile unsigned long *ptr)
 {
         unsigned long addr;
 
-        addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        addr = ((unsigned long) ptr) + ((nr ^ (BITS_PER_LONG - 8)) >> 3);
         *(unsigned char *) addr |= 1 << (nr & 7);
 }
 
@@ -246,7 +241,7 @@ __clear_bit(unsigned long nr, volatile unsigned long *ptr)
 {
         unsigned long addr;
 
-        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        addr = (unsigned long) ptr + ((nr ^ (BITS_PER_LONG - 8)) >> 3);
         asm volatile(
                 "       nc      %O0(1,%R0),%1"
                 : "=Q" (*(char *) addr) : "Q" (_ni_bitmap[nr & 7]) : "cc" );
@@ -257,7 +252,7 @@ __constant_clear_bit(const unsigned long nr, volatile unsigned long *ptr)
 {
         unsigned long addr;
 
-        addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        addr = ((unsigned long) ptr) + ((nr ^ (BITS_PER_LONG - 8)) >> 3);
         *(unsigned char *) addr &= ~(1 << (nr & 7));
 }
 
@@ -273,7 +268,7 @@ static inline void __change_bit(unsigned long nr, volatile unsigned long *ptr)
 {
         unsigned long addr;
 
-        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        addr = (unsigned long) ptr + ((nr ^ (BITS_PER_LONG - 8)) >> 3);
         asm volatile(
                 "       xc      %O0(1,%R0),%1"
                 : "=Q" (*(char *) addr) : "Q" (_oi_bitmap[nr & 7]) : "cc" );
@@ -284,7 +279,7 @@ __constant_change_bit(const unsigned long nr, volatile unsigned long *ptr)
 {
         unsigned long addr;
 
-        addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        addr = ((unsigned long) ptr) + ((nr ^ (BITS_PER_LONG - 8)) >> 3);
         *(unsigned char *) addr ^= 1 << (nr & 7);
 }
 
@@ -302,7 +297,7 @@ test_and_set_bit_simple(unsigned long nr, volatile unsigned long *ptr)
         unsigned long addr;
         unsigned char ch;
 
-        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        addr = (unsigned long) ptr + ((nr ^ (BITS_PER_LONG - 8)) >> 3);
         ch = *(unsigned char *) addr;
         asm volatile(
                 "       oc      %O0(1,%R0),%1"
@@ -321,7 +316,7 @@ test_and_clear_bit_simple(unsigned long nr, volatile unsigned long *ptr)
         unsigned long addr;
         unsigned char ch;
 
-        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        addr = (unsigned long) ptr + ((nr ^ (BITS_PER_LONG - 8)) >> 3);
         ch = *(unsigned char *) addr;
         asm volatile(
                 "       nc      %O0(1,%R0),%1"
@@ -340,7 +335,7 @@ test_and_change_bit_simple(unsigned long nr, volatile unsigned long *ptr)
         unsigned long addr;
         unsigned char ch;
 
-        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        addr = (unsigned long) ptr + ((nr ^ (BITS_PER_LONG - 8)) >> 3);
         ch = *(unsigned char *) addr;
         asm volatile(
                 "       xc      %O0(1,%R0),%1"
@@ -376,7 +371,7 @@ static inline int __test_bit(unsigned long nr, const volatile unsigned long *ptr
         unsigned long addr;
         unsigned char ch;
 
-        addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
+        addr = (unsigned long) ptr + ((nr ^ (BITS_PER_LONG - 8)) >> 3);
         ch = *(volatile unsigned char *) addr;
         return (ch >> (nr & 7)) & 1;
 }
@@ -384,7 +379,7 @@ static inline int __test_bit(unsigned long nr, const volatile unsigned long *ptr
 static inline int 
 __constant_test_bit(unsigned long nr, const volatile unsigned long *addr) {
     return (((volatile char *) addr)
-            [(nr^(__BITOPS_WORDSIZE-8))>>3] & (1<<(nr&7))) != 0;
+            [(nr^(BITS_PER_LONG-8))>>3] & (1<<(nr&7))) != 0;
 }
 
 #define test_bit(nr,addr) \
@@ -693,18 +688,18 @@ static inline int find_next_bit_left(const unsigned long *addr,
 
         if (offset >= size)
                 return size;
-        bit = offset & (__BITOPS_WORDSIZE - 1);
+        bit = offset & (BITS_PER_LONG - 1);
         offset -= bit;
         size -= offset;
-        p = addr + offset / __BITOPS_WORDSIZE;
+        p = addr + offset / BITS_PER_LONG;
         if (bit) {
                 set = __flo_word(0, *p & (~0UL << bit));
                 if (set >= size)
                         return size + offset;
-                if (set < __BITOPS_WORDSIZE)
+                if (set < BITS_PER_LONG)
                         return set + offset;
-                offset += __BITOPS_WORDSIZE;
-                size -= __BITOPS_WORDSIZE;
+                offset += BITS_PER_LONG;
+                size -= BITS_PER_LONG;
                 p++;
         }
         return offset + find_first_bit_left(p, size);
@@ -736,22 +731,22 @@ static inline int find_next_zero_bit (const unsigned long * addr,
 
         if (offset >= size)
                 return size;
-        bit = offset & (__BITOPS_WORDSIZE - 1);
+        bit = offset & (BITS_PER_LONG - 1);
         offset -= bit;
         size -= offset;
-        p = addr + offset / __BITOPS_WORDSIZE;
+        p = addr + offset / BITS_PER_LONG;
         if (bit) {
                 /*
-                 * __ffz_word returns __BITOPS_WORDSIZE
+                 * __ffz_word returns BITS_PER_LONG
                  * if no zero bit is present in the word.
                  */
                 set = __ffz_word(bit, *p >> bit);
                 if (set >= size)
                         return size + offset;
-                if (set < __BITOPS_WORDSIZE)
+                if (set < BITS_PER_LONG)
                         return set + offset;
-                offset += __BITOPS_WORDSIZE;
-                size -= __BITOPS_WORDSIZE;
+                offset += BITS_PER_LONG;
+                size -= BITS_PER_LONG;
                 p++;
         }
         return offset + find_first_zero_bit(p, size);
@@ -773,22 +768,22 @@ static inline int find_next_bit (const unsigned long * addr,
 
         if (offset >= size)
                 return size;
-        bit = offset & (__BITOPS_WORDSIZE - 1);
+        bit = offset & (BITS_PER_LONG - 1);
         offset -= bit;
         size -= offset;
-        p = addr + offset / __BITOPS_WORDSIZE;
+        p = addr + offset / BITS_PER_LONG;
         if (bit) {
                 /*
-                 * __ffs_word returns __BITOPS_WORDSIZE
+                 * __ffs_word returns BITS_PER_LONG
                  * if no one bit is present in the word.
                  */
                 set = __ffs_word(0, *p & (~0UL << bit));
                 if (set >= size)
                         return size + offset;
-                if (set < __BITOPS_WORDSIZE)
+                if (set < BITS_PER_LONG)
                         return set + offset;
-                offset += __BITOPS_WORDSIZE;
-                size -= __BITOPS_WORDSIZE;
+                offset += BITS_PER_LONG;
+                size -= BITS_PER_LONG;
                 p++;
         }
         return offset + find_first_bit(p, size);
@@ -843,22 +838,22 @@ static inline int find_next_zero_bit_le(void *vaddr, unsigned long size,
 
         if (offset >= size)
                 return size;
-        bit = offset & (__BITOPS_WORDSIZE - 1);
+        bit = offset & (BITS_PER_LONG - 1);
         offset -= bit;
         size -= offset;
-        p = addr + offset / __BITOPS_WORDSIZE;
+        p = addr + offset / BITS_PER_LONG;
         if (bit) {
                 /*
-                 * s390 version of ffz returns __BITOPS_WORDSIZE
+                 * s390 version of ffz returns BITS_PER_LONG
                  * if no zero bit is present in the word.
                  */
                 set = __ffz_word(bit, __load_ulong_le(p, 0) >> bit);
                 if (set >= size)
                         return size + offset;
-                if (set < __BITOPS_WORDSIZE)
+                if (set < BITS_PER_LONG)
                         return set + offset;
-                offset += __BITOPS_WORDSIZE;
-                size -= __BITOPS_WORDSIZE;
+                offset += BITS_PER_LONG;
+                size -= BITS_PER_LONG;
                 p++;
         }
         return offset + find_first_zero_bit_le(p, size);
@@ -885,22 +880,22 @@ static inline int find_next_bit_le(void *vaddr, unsigned long size,
 
         if (offset >= size)
                 return size;
-        bit = offset & (__BITOPS_WORDSIZE - 1);
+        bit = offset & (BITS_PER_LONG - 1);
         offset -= bit;
         size -= offset;
-        p = addr + offset / __BITOPS_WORDSIZE;
+        p = addr + offset / BITS_PER_LONG;
         if (bit) {
                 /*
-                 * s390 version of ffz returns __BITOPS_WORDSIZE
+                 * s390 version of ffz returns BITS_PER_LONG
                  * if no zero bit is present in the word.
                  */
                 set = __ffs_word(0, __load_ulong_le(p, 0) & (~0UL << bit));
                 if (set >= size)
                         return size + offset;
-                if (set < __BITOPS_WORDSIZE)
+                if (set < BITS_PER_LONG)
                         return set + offset;
-                offset += __BITOPS_WORDSIZE;
-                size -= __BITOPS_WORDSIZE;
+                offset += BITS_PER_LONG;
+                size -= BITS_PER_LONG;
                 p++;
         }
         return offset + find_first_bit_le(p, size);
diff --git a/arch/s390/include/asm/ccwdev.h b/arch/s390/include/asm/ccwdev.h
index e6061617a50b..f201af8be580 100644
--- a/arch/s390/include/asm/ccwdev.h
+++ b/arch/s390/include/asm/ccwdev.h
@@ -220,7 +220,8 @@ extern void ccw_device_get_id(struct ccw_device *, struct ccw_dev_id *);
 #define to_ccwdrv(n) container_of(n, struct ccw_driver, driver)
 
 extern struct ccw_device *ccw_device_probe_console(void);
-extern int ccw_device_force_console(void);
+extern void ccw_device_wait_idle(struct ccw_device *);
+extern int ccw_device_force_console(struct ccw_device *);
 
 int ccw_device_siosl(struct ccw_device *);
 
diff --git a/arch/s390/include/asm/cio.h b/arch/s390/include/asm/cio.h
index ad2b924167d7..ffb898961c8d 100644
--- a/arch/s390/include/asm/cio.h
+++ b/arch/s390/include/asm/cio.h
@@ -296,8 +296,6 @@ static inline int ccw_dev_id_is_equal(struct ccw_dev_id *dev_id1,
         return 0;
 }
 
-extern void wait_cons_dev(void);
-
 extern void css_schedule_reprobe(void);
 
 extern void reipl_ccw_dev(struct ccw_dev_id *id);
diff --git a/arch/s390/include/asm/compat.h b/arch/s390/include/asm/compat.h
index f8c6df6cd1f0..c1e7c646727c 100644
--- a/arch/s390/include/asm/compat.h
+++ b/arch/s390/include/asm/compat.h
@@ -70,6 +70,22 @@ typedef u32		compat_ulong_t;
 typedef u64             compat_u64;
 typedef u32             compat_uptr_t;
 
+typedef struct {
+        u32 mask;
+        u32 addr;
+} __aligned(8) psw_compat_t;
+
+typedef struct {
+        psw_compat_t psw;
+        u32 gprs[NUM_GPRS];
+        u32 acrs[NUM_ACRS];
+        u32 orig_gpr2;
+} s390_compat_regs;
+
+typedef struct {
+        u32 gprs_high[NUM_GPRS];
+} s390_compat_regs_high;
+
 struct compat_timespec {
         compat_time_t   tv_sec;
         s32             tv_nsec;
@@ -124,18 +140,33 @@ struct compat_flock64 {
 };
 
 struct compat_statfs {
-        s32             f_type;
-        s32             f_bsize;
-        s32             f_blocks;
-        s32             f_bfree;
-        s32             f_bavail;
-        s32             f_files;
-        s32             f_ffree;
+        u32             f_type;
+        u32             f_bsize;
+        u32             f_blocks;
+        u32             f_bfree;
+        u32             f_bavail;
+        u32             f_files;
+        u32             f_ffree;
+        compat_fsid_t   f_fsid;
+        u32             f_namelen;
+        u32             f_frsize;
+        u32             f_flags;
+        u32             f_spare[4];
+};
+
+struct compat_statfs64 {
+        u32             f_type;
+        u32             f_bsize;
+        u64             f_blocks;
+        u64             f_bfree;
+        u64             f_bavail;
+        u64             f_files;
+        u64             f_ffree;
         compat_fsid_t   f_fsid;
-        s32             f_namelen;
-        s32             f_frsize;
-        s32             f_flags;
-        s32             f_spare[5];
+        u32             f_namelen;
+        u32             f_frsize;
+        u32             f_flags;
+        u32             f_spare[4];
 };
 
 #define COMPAT_RLIM_OLD_INFINITY        0x7fffffff
@@ -248,8 +279,6 @@ static inline int is_compat_task(void)
         return is_32bit_task();
 }
 
-#endif
-
 static inline void __user *arch_compat_alloc_user_space(long len)
 {
         unsigned long stack;
@@ -260,6 +289,8 @@ static inline void __user *arch_compat_alloc_user_space(long len)
         return (void __user *) (stack - len);
 }
 
+#endif
+
 struct compat_ipc64_perm {
         compat_key_t key;
         __compat_uid32_t uid;
diff --git a/arch/s390/include/asm/elf.h b/arch/s390/include/asm/elf.h
index 1bfdf24b85a2..78f4f8711d58 100644
--- a/arch/s390/include/asm/elf.h
+++ b/arch/s390/include/asm/elf.h
@@ -119,6 +119,8 @@
  */
 
 #include <asm/ptrace.h>
+#include <asm/compat.h>
+#include <asm/syscall.h>
 #include <asm/user.h>
 
 typedef s390_fp_regs elf_fpregset_t;
@@ -180,18 +182,31 @@ extern unsigned long elf_hwcap;
 extern char elf_platform[];
 #define ELF_PLATFORM (elf_platform)
 
-#ifdef CONFIG_64BIT
+#ifndef CONFIG_COMPAT
+#define SET_PERSONALITY(ex) \
+do {                                                            \
+        set_personality(PER_LINUX |                             \
+                (current->personality & (~PER_MASK)));          \
+        current_thread_info()->sys_call_table =                 \
+                (unsigned long) &sys_call_table;                \
+} while (0)
+#else /* CONFIG_COMPAT */
 #define SET_PERSONALITY(ex)                                     \
 do {                                                            \
         if (personality(current->personality) != PER_LINUX32)   \
                 set_personality(PER_LINUX |                     \
                         (current->personality & ~PER_MASK));    \
-        if ((ex).e_ident[EI_CLASS] == ELFCLASS32)               \
+        if ((ex).e_ident[EI_CLASS] == ELFCLASS32) {             \
                 set_thread_flag(TIF_31BIT);                     \
-        else                                                    \
+                current_thread_info()->sys_call_table =         \
+                        (unsigned long) &sys_call_table_emu;    \
+        } else {                                                \
                 clear_thread_flag(TIF_31BIT);                   \
+                current_thread_info()->sys_call_table =         \
+                        (unsigned long) &sys_call_table;        \
+        }                                                       \
 } while (0)
-#endif /* CONFIG_64BIT */
+#endif /* CONFIG_COMPAT */
 
 #define STACK_RND_MASK  0x7ffUL
 
diff --git a/arch/s390/include/asm/hugetlb.h b/arch/s390/include/asm/hugetlb.h
index 593753ee07f3..bd90359d6d22 100644
--- a/arch/s390/include/asm/hugetlb.h
+++ b/arch/s390/include/asm/hugetlb.h
@@ -114,7 +114,7 @@ static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
 #define huge_ptep_set_wrprotect(__mm, __addr, __ptep)                   \
 ({                                                                      \
         pte_t __pte = huge_ptep_get(__ptep);                            \
-        if (pte_write(__pte)) {                                         \
+        if (huge_pte_write(__pte)) {                                    \
                 huge_ptep_invalidate(__mm, __addr, __ptep);             \
                 set_huge_pte_at(__mm, __addr, __ptep,                   \
                                 huge_pte_wrprotect(__pte));             \
@@ -127,4 +127,58 @@ static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
         huge_ptep_invalidate(vma->vm_mm, address, ptep);
 }
 
+static inline pte_t mk_huge_pte(struct page *page, pgprot_t pgprot)
+{
+        pte_t pte;
+        pmd_t pmd;
+
+        pmd = mk_pmd_phys(page_to_phys(page), pgprot);
+        pte_val(pte) = pmd_val(pmd);
+        return pte;
+}
+
+static inline int huge_pte_write(pte_t pte)
+{
+        pmd_t pmd;
+
+        pmd_val(pmd) = pte_val(pte);
+        return pmd_write(pmd);
+}
+
+static inline int huge_pte_dirty(pte_t pte)
+{
+        /* No dirty bit in the segment table entry. */
+        return 0;
+}
+
+static inline pte_t huge_pte_mkwrite(pte_t pte)
+{
+        pmd_t pmd;
+
+        pmd_val(pmd) = pte_val(pte);
+        pte_val(pte) = pmd_val(pmd_mkwrite(pmd));
+        return pte;
+}
+
+static inline pte_t huge_pte_mkdirty(pte_t pte)
+{
+        /* No dirty bit in the segment table entry. */
+        return pte;
+}
+
+static inline pte_t huge_pte_modify(pte_t pte, pgprot_t newprot)
+{
+        pmd_t pmd;
+
+        pmd_val(pmd) = pte_val(pte);
+        pte_val(pte) = pmd_val(pmd_modify(pmd, newprot));
+        return pte;
+}
+
+static inline void huge_pte_clear(struct mm_struct *mm, unsigned long addr,
+                                  pte_t *ptep)
+{
+        pmd_clear((pmd_t *) ptep);
+}
+
 #endif /* _ASM_S390_HUGETLB_H */
diff --git a/arch/s390/include/asm/pci.h b/arch/s390/include/asm/pci.h
index 05333b7f0469..6c1801235db9 100644
--- a/arch/s390/include/asm/pci.h
+++ b/arch/s390/include/asm/pci.h
@@ -140,6 +140,7 @@ static inline bool zdev_enabled(struct zpci_dev *zdev)
 struct zpci_dev *zpci_alloc_device(void);
 int zpci_create_device(struct zpci_dev *);
 int zpci_enable_device(struct zpci_dev *);
+int zpci_disable_device(struct zpci_dev *);
 void zpci_stop_device(struct zpci_dev *);
 void zpci_free_device(struct zpci_dev *);
 int zpci_scan_device(struct zpci_dev *);
diff --git a/arch/s390/include/asm/pci_debug.h b/arch/s390/include/asm/pci_debug.h
index 6bbec4265b6e..1ca5d1047c71 100644
--- a/arch/s390/include/asm/pci_debug.h
+++ b/arch/s390/include/asm/pci_debug.h
@@ -7,14 +7,11 @@ extern debug_info_t *pci_debug_msg_id;
 extern debug_info_t *pci_debug_err_id;
 
 #ifdef CONFIG_PCI_DEBUG
-#define zpci_dbg(fmt, args...)                                                  \
-        do {                                                                    \
-                if (pci_debug_msg_id->level >= 2)                               \
-                        debug_sprintf_event(pci_debug_msg_id, 2, fmt , ## args);\
-        } while (0)
+#define zpci_dbg(imp, fmt, args...)                             \
+        debug_sprintf_event(pci_debug_msg_id, imp, fmt, ##args)
 
 #else /* !CONFIG_PCI_DEBUG */
-#define zpci_dbg(fmt, args...) do { } while (0)
+#define zpci_dbg(imp, fmt, args...) do { } while (0)
 #endif
 
 #define zpci_err(text...)                                                       \
diff --git a/arch/s390/include/asm/pci_insn.h b/arch/s390/include/asm/pci_insn.h
index 1486a98d5dad..e6a2bdd4d705 100644
--- a/arch/s390/include/asm/pci_insn.h
+++ b/arch/s390/include/asm/pci_insn.h
@@ -1,10 +1,6 @@
 #ifndef _ASM_S390_PCI_INSN_H
 #define _ASM_S390_PCI_INSN_H
 
-#include <linux/delay.h>
-
-#define ZPCI_INSN_BUSY_DELAY    1       /* 1 microsecond */
-
 /* Load/Store status codes */
 #define ZPCI_PCI_ST_FUNC_NOT_ENABLED            4
 #define ZPCI_PCI_ST_FUNC_IN_ERR                 8
@@ -82,199 +78,12 @@ struct zpci_fib {
         u64 reserved7;
 } __packed;
 
-/* Modify PCI Function Controls */
-static inline u8 __mpcifc(u64 req, struct zpci_fib *fib, u8 *status)
-{
-        u8 cc;
-
-        asm volatile (
-                "       .insn   rxy,0xe300000000d0,%[req],%[fib]\n"
-                "       ipm     %[cc]\n"
-                "       srl     %[cc],28\n"
-                : [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib)
-                : : "cc");
-        *status = req >> 24 & 0xff;
-        return cc;
-}
-
-static inline int mpcifc_instr(u64 req, struct zpci_fib *fib)
-{
-        u8 cc, status;
-
-        do {
-                cc = __mpcifc(req, fib, &status);
-                if (cc == 2)
-                        msleep(ZPCI_INSN_BUSY_DELAY);
-        } while (cc == 2);
-
-        if (cc)
-                printk_once(KERN_ERR "%s: error cc: %d  status: %d\n",
-                             __func__, cc, status);
-        return (cc) ? -EIO : 0;
-}
-
-/* Refresh PCI Translations */
-static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)
-{
-        register u64 __addr asm("2") = addr;
-        register u64 __range asm("3") = range;
-        u8 cc;
-
-        asm volatile (
-                "       .insn   rre,0xb9d30000,%[fn],%[addr]\n"
-                "       ipm     %[cc]\n"
-                "       srl     %[cc],28\n"
-                : [cc] "=d" (cc), [fn] "+d" (fn)
-                : [addr] "d" (__addr), "d" (__range)
-                : "cc");
-        *status = fn >> 24 & 0xff;
-        return cc;
-}
-
-static inline int rpcit_instr(u64 fn, u64 addr, u64 range)
-{
-        u8 cc, status;
-
-        do {
-                cc = __rpcit(fn, addr, range, &status);
-                if (cc == 2)
-                        udelay(ZPCI_INSN_BUSY_DELAY);
-        } while (cc == 2);
-
-        if (cc)
-                printk_once(KERN_ERR "%s: error cc: %d  status: %d  dma_addr: %Lx  size: %Lx\n",
-                            __func__, cc, status, addr, range);
-        return (cc) ? -EIO : 0;
-}
-
-/* Store PCI function controls */
-static inline u8 __stpcifc(u32 handle, u8 space, struct zpci_fib *fib, u8 *status)
-{
-        u64 fn = (u64) handle << 32 | space << 16;
-        u8 cc;
-
-        asm volatile (
-                "       .insn   rxy,0xe300000000d4,%[fn],%[fib]\n"
-                "       ipm     %[cc]\n"
-                "       srl     %[cc],28\n"
-                : [cc] "=d" (cc), [fn] "+d" (fn), [fib] "=m" (*fib)
-                : : "cc");
-        *status = fn >> 24 & 0xff;
-        return cc;
-}
-
-/* Set Interruption Controls */
-static inline void sic_instr(u16 ctl, char *unused, u8 isc)
-{
-        asm volatile (
-                "       .insn   rsy,0xeb00000000d1,%[ctl],%[isc],%[u]\n"
-                : : [ctl] "d" (ctl), [isc] "d" (isc << 27), [u] "Q" (*unused));
-}
-
-/* PCI Load */
-static inline u8 __pcilg(u64 *data, u64 req, u64 offset, u8 *status)
-{
-        register u64 __req asm("2") = req;
-        register u64 __offset asm("3") = offset;
-        u64 __data;
-        u8 cc;
-
-        asm volatile (
-                "       .insn   rre,0xb9d20000,%[data],%[req]\n"
-                "       ipm     %[cc]\n"
-                "       srl     %[cc],28\n"
-                : [cc] "=d" (cc), [data] "=d" (__data), [req] "+d" (__req)
-                :  "d" (__offset)
-                : "cc");
-        *status = __req >> 24 & 0xff;
-        *data = __data;
-        return cc;
-}
-
-static inline int pcilg_instr(u64 *data, u64 req, u64 offset)
-{
-        u8 cc, status;
-
-        do {
-                cc = __pcilg(data, req, offset, &status);
-                if (cc == 2)
-                        udelay(ZPCI_INSN_BUSY_DELAY);
-        } while (cc == 2);
-
-        if (cc) {
-                printk_once(KERN_ERR "%s: error cc: %d  status: %d  req: %Lx  offset: %Lx\n",
-                            __func__, cc, status, req, offset);
-                /* TODO: on IO errors set data to 0xff...
-                 * here or in users of pcilg (le conversion)?
-                 */
-        }
-        return (cc) ? -EIO : 0;
-}
-
-/* PCI Store */
-static inline u8 __pcistg(u64 data, u64 req, u64 offset, u8 *status)
-{
-        register u64 __req asm("2") = req;
-        register u64 __offset asm("3") = offset;
-        u8 cc;
-
-        asm volatile (
-                "       .insn   rre,0xb9d00000,%[data],%[req]\n"
-                "       ipm     %[cc]\n"
-                "       srl     %[cc],28\n"
-                : [cc] "=d" (cc), [req] "+d" (__req)
-                : "d" (__offset), [data] "d" (data)
-                : "cc");
-        *status = __req >> 24 & 0xff;
-        return cc;
-}
-
-static inline int pcistg_instr(u64 data, u64 req, u64 offset)
-{
-        u8 cc, status;
-
-        do {
-                cc = __pcistg(data, req, offset, &status);
-                if (cc == 2)
-                        udelay(ZPCI_INSN_BUSY_DELAY);
-        } while (cc == 2);
-
-        if (cc)
-                printk_once(KERN_ERR "%s: error cc: %d  status: %d  req: %Lx  offset: %Lx\n",
-                        __func__, cc, status, req, offset);
-        return (cc) ? -EIO : 0;
-}
-
-/* PCI Store Block */
-static inline u8 __pcistb(const u64 *data, u64 req, u64 offset, u8 *status)
-{
-        u8 cc;
-
-        asm volatile (
-                "       .insn   rsy,0xeb00000000d0,%[req],%[offset],%[data]\n"
-                "       ipm     %[cc]\n"
-                "       srl     %[cc],28\n"
-                : [cc] "=d" (cc), [req] "+d" (req)
-                : [offset] "d" (offset), [data] "Q" (*data)
-                : "cc");
-        *status = req >> 24 & 0xff;
-        return cc;
-}
-
-static inline int pcistb_instr(const u64 *data, u64 req, u64 offset)
-{
-        u8 cc, status;
-
-        do {
-                cc = __pcistb(data, req, offset, &status);
-                if (cc == 2)
-                        udelay(ZPCI_INSN_BUSY_DELAY);
-        } while (cc == 2);
 
-        if (cc)
-                printk_once(KERN_ERR "%s: error cc: %d  status: %d  req: %Lx  offset: %Lx\n",
-                            __func__, cc, status, req, offset);
-        return (cc) ? -EIO : 0;
-}
+int s390pci_mod_fc(u64 req, struct zpci_fib *fib);
+int s390pci_refresh_trans(u64 fn, u64 addr, u64 range);
+int s390pci_load(u64 *data, u64 req, u64 offset);
+int s390pci_store(u64 data, u64 req, u64 offset);
+int s390pci_store_block(const u64 *data, u64 req, u64 offset);
+void set_irq_ctrl(u16 ctl, char *unused, u8 isc);
 
 #endif
diff --git a/arch/s390/include/asm/pci_io.h b/arch/s390/include/asm/pci_io.h
index 5fd81f31d6c7..83a9caa6ae53 100644
--- a/arch/s390/include/asm/pci_io.h
+++ b/arch/s390/include/asm/pci_io.h
@@ -36,7 +36,7 @@ static inline RETTYPE zpci_read_##RETTYPE(const volatile void __iomem *addr)	\
         u64 data;                                                               \
         int rc;                                                                 \
                                                                                 \
-        rc = pcilg_instr(&data, req, ZPCI_OFFSET(addr));                        \
+        rc = s390pci_load(&data, req, ZPCI_OFFSET(addr));                       \
         if (rc)                                                                 \
                 data = -1ULL;                                                   \
         return (RETTYPE) data;                                                  \
@@ -50,7 +50,7 @@ static inline void zpci_write_##VALTYPE(VALTYPE val,				\
         u64 req = ZPCI_CREATE_REQ(entry->fh, entry->bar, LENGTH);               \
         u64 data = (VALTYPE) val;                                               \
                                                                                 \
-        pcistg_instr(data, req, ZPCI_OFFSET(addr));                             \
+        s390pci_store(data, req, ZPCI_OFFSET(addr));                            \
 }
 
 zpci_read(8, u64)
@@ -83,15 +83,18 @@ static inline int zpci_write_single(u64 req, const u64 *data, u64 offset, u8 len
                 val = 0;                /* let FW report error */
                 break;
         }
-        return pcistg_instr(val, req, offset);
+        return s390pci_store(val, req, offset);
 }
 
 static inline int zpci_read_single(u64 req, u64 *dst, u64 offset, u8 len)
 {
         u64 data;
-        u8 cc;
+        int cc;
+
+        cc = s390pci_load(&data, req, offset);
+        if (cc)
+                goto out;
 
-        cc = pcilg_instr(&data,  req, offset);
         switch (len) {
         case 1:
                 *((u8 *) dst) = (u8) data;
@@ -106,12 +109,13 @@ static inline int zpci_read_single(u64 req, u64 *dst, u64 offset, u8 len)
                 *((u64 *) dst) = (u64) data;
                 break;
         }
+out:
         return cc;
 }
 
 static inline int zpci_write_block(u64 req, const u64 *data, u64 offset)
 {
-        return pcistb_instr(data, req, offset);
+        return s390pci_store_block(data, req, offset);
 }
 
 static inline u8 zpci_get_max_write_size(u64 src, u64 dst, int len, int max)
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index 3cb47cf02530..4105b8221fdd 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -306,6 +306,7 @@ extern unsigned long MODULES_END;
 #define RCP_HC_BIT      0x00200000UL
 #define RCP_GR_BIT      0x00040000UL
 #define RCP_GC_BIT      0x00020000UL
+#define RCP_IN_BIT      0x00008000UL    /* IPTE notify bit */
 
 /* User dirty / referenced bit for KVM's migration feature */
 #define KVM_UR_BIT      0x00008000UL
@@ -373,6 +374,7 @@ extern unsigned long MODULES_END;
 #define RCP_HC_BIT      0x0020000000000000UL
 #define RCP_GR_BIT      0x0004000000000000UL
 #define RCP_GC_BIT      0x0002000000000000UL
+#define RCP_IN_BIT      0x0000800000000000UL    /* IPTE notify bit */
 
 /* User dirty / referenced bit for KVM's migration feature */
 #define KVM_UR_BIT      0x0000800000000000UL
@@ -424,6 +426,13 @@ extern unsigned long MODULES_END;
 #define __S110  PAGE_RW
 #define __S111  PAGE_RW
 
+/*
+ * Segment entry (large page) protection definitions.
+ */
+#define SEGMENT_NONE    __pgprot(_HPAGE_TYPE_NONE)
+#define SEGMENT_RO      __pgprot(_HPAGE_TYPE_RO)
+#define SEGMENT_RW      __pgprot(_HPAGE_TYPE_RW)
+
 static inline int mm_exclusive(struct mm_struct *mm)
 {
         return likely(mm == current->active_mm &&
@@ -739,35 +748,67 @@ struct gmap {
 
 /**
  * struct gmap_rmap - reverse mapping for segment table entries
- * @next: pointer to the next gmap_rmap structure in the list
+ * @gmap: pointer to the gmap_struct
  * @entry: pointer to a segment table entry
+ * @vmaddr: virtual address in the guest address space
  */
 struct gmap_rmap {
         struct list_head list;
+        struct gmap *gmap;
         unsigned long *entry;
+        unsigned long vmaddr;
 };
 
 /**
  * struct gmap_pgtable - gmap information attached to a page table
  * @vmaddr: address of the 1MB segment in the process virtual memory
- * @mapper: list of segment table entries maping a page table
+ * @mapper: list of segment table entries mapping a page table
  */
 struct gmap_pgtable {
         unsigned long vmaddr;
         struct list_head mapper;
 };
 
+/**
+ * struct gmap_notifier - notify function block for page invalidation
+ * @notifier_call: address of callback function
+ */
+struct gmap_notifier {
+        struct list_head list;
+        void (*notifier_call)(struct gmap *gmap, unsigned long address);
+};
+
 struct gmap *gmap_alloc(struct mm_struct *mm);
 void gmap_free(struct gmap *gmap);
 void gmap_enable(struct gmap *gmap);
 void gmap_disable(struct gmap *gmap);
 int gmap_map_segment(struct gmap *gmap, unsigned long from,
-                     unsigned long to, unsigned long length);
+                     unsigned long to, unsigned long len);
 int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len);
+unsigned long __gmap_translate(unsigned long address, struct gmap *);
+unsigned long gmap_translate(unsigned long address, struct gmap *);
 unsigned long __gmap_fault(unsigned long address, struct gmap *);
 unsigned long gmap_fault(unsigned long address, struct gmap *);
 void gmap_discard(unsigned long from, unsigned long to, struct gmap *);
 
+void gmap_register_ipte_notifier(struct gmap_notifier *);
+void gmap_unregister_ipte_notifier(struct gmap_notifier *);
+int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len);
+void gmap_do_ipte_notify(struct mm_struct *, unsigned long addr, pte_t *);
+
+static inline pgste_t pgste_ipte_notify(struct mm_struct *mm,
+                                        unsigned long addr,
+                                        pte_t *ptep, pgste_t pgste)
+{
+#ifdef CONFIG_PGSTE
+        if (pgste_val(pgste) & RCP_IN_BIT) {
+                pgste_val(pgste) &= ~RCP_IN_BIT;
+                gmap_do_ipte_notify(mm, addr, ptep);
+        }
+#endif
+        return pgste;
+}
+
 /*
  * Certain architectures need to do special things when PTEs
  * within a page table are directly modified.  Thus, the following
@@ -912,26 +953,6 @@ static inline pte_t pte_mkspecial(pte_t pte)
 #ifdef CONFIG_HUGETLB_PAGE
 static inline pte_t pte_mkhuge(pte_t pte)
 {
-        /*
-         * PROT_NONE needs to be remapped from the pte type to the ste type.
-         * The HW invalid bit is also different for pte and ste. The pte
-         * invalid bit happens to be the same as the ste _SEGMENT_ENTRY_LARGE
-         * bit, so we don't have to clear it.
-         */
-        if (pte_val(pte) & _PAGE_INVALID) {
-                if (pte_val(pte) & _PAGE_SWT)
-                        pte_val(pte) |= _HPAGE_TYPE_NONE;
-                pte_val(pte) |= _SEGMENT_ENTRY_INV;
-        }
-        /*
-         * Clear SW pte bits, there are no SW bits in a segment table entry.
-         */
-        pte_val(pte) &= ~(_PAGE_SWT | _PAGE_SWX | _PAGE_SWC |
-                          _PAGE_SWR | _PAGE_SWW);
-        /*
-         * Also set the change-override bit because we don't need dirty bit
-         * tracking for hugetlbfs pages.
-         */
         pte_val(pte) |= (_SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_CO);
         return pte;
 }
@@ -1043,8 +1064,10 @@ static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
         pte_t pte;
 
         mm->context.flush_mm = 1;
-        if (mm_has_pgste(mm))
+        if (mm_has_pgste(mm)) {
                 pgste = pgste_get_lock(ptep);
+                pgste = pgste_ipte_notify(mm, address, ptep, pgste);
+        }
 
         pte = *ptep;
         if (!mm_exclusive(mm))
@@ -1063,11 +1086,14 @@ static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
                                            unsigned long address,
                                            pte_t *ptep)
 {
+        pgste_t pgste;
         pte_t pte;
 
         mm->context.flush_mm = 1;
-        if (mm_has_pgste(mm))
-                pgste_get_lock(ptep);
+        if (mm_has_pgste(mm)) {
+                pgste = pgste_get_lock(ptep);
+                pgste_ipte_notify(mm, address, ptep, pgste);
+        }
 
         pte = *ptep;
         if (!mm_exclusive(mm))
@@ -1093,8 +1119,10 @@ static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
         pgste_t pgste;
         pte_t pte;
 
-        if (mm_has_pgste(vma->vm_mm))
+        if (mm_has_pgste(vma->vm_mm)) {
                 pgste = pgste_get_lock(ptep);
+                pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste);
+        }
 
         pte = *ptep;
         __ptep_ipte(address, ptep);
@@ -1122,8 +1150,11 @@ static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
         pgste_t pgste;
         pte_t pte;
 
-        if (mm_has_pgste(mm))
+        if (mm_has_pgste(mm)) {
                 pgste = pgste_get_lock(ptep);
+                if (!full)
+                        pgste = pgste_ipte_notify(mm, address, ptep, pgste);
+        }
 
         pte = *ptep;
         if (!full)
@@ -1146,8 +1177,10 @@ static inline pte_t ptep_set_wrprotect(struct mm_struct *mm,
 
         if (pte_write(pte)) {
                 mm->context.flush_mm = 1;
-                if (mm_has_pgste(mm))
+                if (mm_has_pgste(mm)) {
                         pgste = pgste_get_lock(ptep);
+                        pgste = pgste_ipte_notify(mm, address, ptep, pgste);
+                }
 
                 if (!mm_exclusive(mm))
                         __ptep_ipte(address, ptep);
@@ -1171,8 +1204,10 @@ static inline int ptep_set_access_flags(struct vm_area_struct *vma,
 
         if (pte_same(*ptep, entry))
                 return 0;
-        if (mm_has_pgste(vma->vm_mm))
+        if (mm_has_pgste(vma->vm_mm)) {
                 pgste = pgste_get_lock(ptep);
+                pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste);
+        }
 
         __ptep_ipte(address, ptep);
 
@@ -1276,31 +1311,7 @@ static inline void __pmd_idte(unsigned long address, pmd_t *pmdp)
         }
 }
 
-#ifdef CONFIG_TRANSPARENT_HUGEPAGE
-
-#define SEGMENT_NONE    __pgprot(_HPAGE_TYPE_NONE)
-#define SEGMENT_RO      __pgprot(_HPAGE_TYPE_RO)
-#define SEGMENT_RW      __pgprot(_HPAGE_TYPE_RW)
-
-#define __HAVE_ARCH_PGTABLE_DEPOSIT
-extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pgtable_t pgtable);
-
-#define __HAVE_ARCH_PGTABLE_WITHDRAW
-extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm);
-
-static inline int pmd_trans_splitting(pmd_t pmd)
-{
-        return pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT;
-}
-
-static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
-                              pmd_t *pmdp, pmd_t entry)
-{
-        if (!(pmd_val(entry) & _SEGMENT_ENTRY_INV) && MACHINE_HAS_EDAT1)
-                pmd_val(entry) |= _SEGMENT_ENTRY_CO;
-        *pmdp = entry;
-}
-
+#if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)
 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot)
 {
         /*
@@ -1321,10 +1332,11 @@ static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
         return pmd;
 }
 
-static inline pmd_t pmd_mkhuge(pmd_t pmd)
+static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot)
 {
-        pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE;
-        return pmd;
+        pmd_t __pmd;
+        pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot);
+        return __pmd;
 }
 
 static inline pmd_t pmd_mkwrite(pmd_t pmd)
@@ -1334,6 +1346,34 @@ static inline pmd_t pmd_mkwrite(pmd_t pmd)
                 pmd_val(pmd) &= ~_SEGMENT_ENTRY_RO;
         return pmd;
 }
+#endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */
+
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+
+#define __HAVE_ARCH_PGTABLE_DEPOSIT
+extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pgtable_t pgtable);
+
+#define __HAVE_ARCH_PGTABLE_WITHDRAW
+extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm);
+
+static inline int pmd_trans_splitting(pmd_t pmd)
+{
+        return pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT;
+}
+
+static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
+                              pmd_t *pmdp, pmd_t entry)
+{
+        if (!(pmd_val(entry) & _SEGMENT_ENTRY_INV) && MACHINE_HAS_EDAT1)
+                pmd_val(entry) |= _SEGMENT_ENTRY_CO;
+        *pmdp = entry;
+}
+
+static inline pmd_t pmd_mkhuge(pmd_t pmd)
+{
+        pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE;
+        return pmd;
+}
 
 static inline pmd_t pmd_wrprotect(pmd_t pmd)
 {
@@ -1430,13 +1470,6 @@ static inline void pmdp_set_wrprotect(struct mm_struct *mm,
         }
 }
 
-static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot)
-{
-        pmd_t __pmd;
-        pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot);
-        return __pmd;
-}
-
 #define pfn_pmd(pfn, pgprot)    mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot))
 #define mk_pmd(page, pgprot)    pfn_pmd(page_to_pfn(page), (pgprot))
 
diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h
index 94e749c90230..6b499870662f 100644
--- a/arch/s390/include/asm/processor.h
+++ b/arch/s390/include/asm/processor.h
@@ -161,7 +161,8 @@ extern unsigned long thread_saved_pc(struct task_struct *t);
 
 extern void show_code(struct pt_regs *regs);
 extern void print_fn_code(unsigned char *code, unsigned long len);
-extern int insn_to_mnemonic(unsigned char *instruction, char buf[8]);
+extern int insn_to_mnemonic(unsigned char *instruction, char *buf,
+                            unsigned int len);
 
 unsigned long get_wchan(struct task_struct *p);
 #define task_pt_regs(tsk) ((struct pt_regs *) \
diff --git a/arch/s390/include/asm/ptrace.h b/arch/s390/include/asm/ptrace.h
index 3ee5da3bc10c..559512a455da 100644
--- a/arch/s390/include/asm/ptrace.h
+++ b/arch/s390/include/asm/ptrace.h
@@ -9,9 +9,7 @@
 #include <uapi/asm/ptrace.h>
 
 #ifndef __ASSEMBLY__
-#ifndef __s390x__
-#else /* __s390x__ */
-#endif /* __s390x__ */
+
 extern long psw_kernel_bits;
 extern long psw_user_bits;
 
@@ -77,8 +75,6 @@ struct per_struct_kernel {
 #define PER_CONTROL_SUSPENSION          0x00400000UL
 #define PER_CONTROL_ALTERATION          0x00200000UL
 
-#ifdef __s390x__
-#endif /* __s390x__ */
 /*
  * These are defined as per linux/ptrace.h, which see.
  */
diff --git a/arch/s390/include/asm/setup.h b/arch/s390/include/asm/setup.h
index ff67d730c00c..59880dbaf360 100644
--- a/arch/s390/include/asm/setup.h
+++ b/arch/s390/include/asm/setup.h
@@ -33,8 +33,6 @@
 
 #define CHUNK_READ_WRITE 0
 #define CHUNK_READ_ONLY  1
-#define CHUNK_OLDMEM     4
-#define CHUNK_CRASHK     5
 
 struct mem_chunk {
         unsigned long addr;
@@ -43,13 +41,12 @@ struct mem_chunk {
 };
 
 extern struct mem_chunk memory_chunk[];
-extern unsigned long real_memory_size;
 extern int memory_end_set;
 extern unsigned long memory_end;
 
-void detect_memory_layout(struct mem_chunk chunk[]);
-void create_mem_hole(struct mem_chunk memory_chunk[], unsigned long addr,
-                     unsigned long size, int type);
+void detect_memory_layout(struct mem_chunk chunk[], unsigned long maxsize);
+void create_mem_hole(struct mem_chunk mem_chunk[], unsigned long addr,
+                     unsigned long size);
 
 #define PRIMARY_SPACE_MODE      0
 #define ACCESS_REGISTER_MODE    1
diff --git a/arch/s390/include/asm/syscall.h b/arch/s390/include/asm/syscall.h
index fe7b99759e12..cd29d2f4e4f3 100644
--- a/arch/s390/include/asm/syscall.h
+++ b/arch/s390/include/asm/syscall.h
@@ -23,6 +23,7 @@
  * type here is what we want [need] for both 32 bit and 64 bit systems.
  */
 extern const unsigned int sys_call_table[];
+extern const unsigned int sys_call_table_emu[];
 
 static inline long syscall_get_nr(struct task_struct *task,
                                   struct pt_regs *regs)
diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/thread_info.h
index 9e2cfe0349c3..eb5f64d26d06 100644
--- a/arch/s390/include/asm/thread_info.h
+++ b/arch/s390/include/asm/thread_info.h
@@ -14,13 +14,8 @@
 #define THREAD_ORDER 1
 #define ASYNC_ORDER  1
 #else /* CONFIG_64BIT */
-#ifndef __SMALL_STACK
 #define THREAD_ORDER 2
 #define ASYNC_ORDER  2
-#else
-#define THREAD_ORDER 1
-#define ASYNC_ORDER  1
-#endif
 #endif /* CONFIG_64BIT */
 
 #define THREAD_SIZE (PAGE_SIZE << THREAD_ORDER)
@@ -41,6 +36,7 @@ struct thread_info {
         struct task_struct      *task;          /* main task structure */
         struct exec_domain      *exec_domain;   /* execution domain */
         unsigned long           flags;          /* low level flags */
+        unsigned long           sys_call_table; /* System call table address */
         unsigned int            cpu;            /* current CPU */
         int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
         struct restart_block    restart_block;
diff --git a/arch/s390/include/asm/unistd.h b/arch/s390/include/asm/unistd.h
index a6667a952969..651886353551 100644
--- a/arch/s390/include/asm/unistd.h
+++ b/arch/s390/include/asm/unistd.h
@@ -54,12 +54,4 @@
 #define __ARCH_WANT_SYS_VFORK
 #define __ARCH_WANT_SYS_CLONE
 
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
-
 #endif /* _ASM_S390_UNISTD_H_ */
diff --git a/arch/s390/include/uapi/asm/Kbuild b/arch/s390/include/uapi/asm/Kbuild
index 7bf68fff7c5d..9ccd1905bdad 100644
--- a/arch/s390/include/uapi/asm/Kbuild
+++ b/arch/s390/include/uapi/asm/Kbuild
@@ -44,5 +44,6 @@ header-y += termios.h
 header-y += types.h
 header-y += ucontext.h
 header-y += unistd.h
+header-y += virtio-ccw.h
 header-y += vtoc.h
 header-y += zcrypt.h
diff --git a/arch/s390/include/uapi/asm/ptrace.h b/arch/s390/include/uapi/asm/ptrace.h
index a5ca214b34fd..3aa9f1ec5b29 100644
--- a/arch/s390/include/uapi/asm/ptrace.h
+++ b/arch/s390/include/uapi/asm/ptrace.h
@@ -215,12 +215,6 @@ typedef struct
         unsigned long addr;
 } __attribute__ ((aligned(8))) psw_t;
 
-typedef struct
-{
-        __u32   mask;
-        __u32   addr;
-} __attribute__ ((aligned(8))) psw_compat_t;
-
 #ifndef __s390x__
 
 #define PSW_MASK_PER            0x40000000UL
@@ -295,20 +289,6 @@ typedef struct
         unsigned long orig_gpr2;
 } s390_regs;
 
-typedef struct
-{
-        psw_compat_t    psw;
-        __u32           gprs[NUM_GPRS];
-        __u32           acrs[NUM_ACRS];
-        __u32           orig_gpr2;
-} s390_compat_regs;
-
-typedef struct
-{
-        __u32           gprs_high[NUM_GPRS];
-} s390_compat_regs_high;
-
-
 /*
  * Now for the user space program event recording (trace) definitions.
  * The following structures are used only for the ptrace interface, don't
diff --git a/arch/s390/include/uapi/asm/statfs.h b/arch/s390/include/uapi/asm/statfs.h
index 5acca0a34c20..a61d538756f2 100644
--- a/arch/s390/include/uapi/asm/statfs.h
+++ b/arch/s390/include/uapi/asm/statfs.h
@@ -7,9 +7,6 @@
 #ifndef _S390_STATFS_H
 #define _S390_STATFS_H
 
-#ifndef __s390x__
-#include <asm-generic/statfs.h>
-#else
 /*
  * We can't use <asm-generic/statfs.h> because in 64-bit mode
  * we mix ints of different sizes in our struct statfs.
@@ -21,49 +18,33 @@ typedef __kernel_fsid_t	fsid_t;
 #endif
 
 struct statfs {
-        int  f_type;
-        int  f_bsize;
-        long f_blocks;
-        long f_bfree;
-        long f_bavail;
-        long f_files;
-        long f_ffree;
+        unsigned int    f_type;
+        unsigned int    f_bsize;
+        unsigned long   f_blocks;
+        unsigned long   f_bfree;
+        unsigned long   f_bavail;
+        unsigned long   f_files;
+        unsigned long   f_ffree;
         __kernel_fsid_t f_fsid;
-        int  f_namelen;
-        int  f_frsize;
-        int  f_flags;
-        int  f_spare[4];
+        unsigned int    f_namelen;
+        unsigned int    f_frsize;
+        unsigned int    f_flags;
+        unsigned int    f_spare[4];
 };
 
 struct statfs64 {
-        int  f_type;
-        int  f_bsize;
-        long f_blocks;
-        long f_bfree;
-        long f_bavail;
-        long f_files;
-        long f_ffree;
+        unsigned int    f_type;
+        unsigned int    f_bsize;
+        unsigned long   f_blocks;
+        unsigned long   f_bfree;
+        unsigned long   f_bavail;
+        unsigned long   f_files;
+        unsigned long   f_ffree;
         __kernel_fsid_t f_fsid;
-        int  f_namelen;
-        int  f_frsize;
-        int  f_flags;
-        int  f_spare[4];
+        unsigned int    f_namelen;
+        unsigned int    f_frsize;
+        unsigned int    f_flags;
+        unsigned int    f_spare[4];
 };
 
-struct compat_statfs64 {
-        __u32 f_type;
-        __u32 f_bsize;
-        __u64 f_blocks;
-        __u64 f_bfree;
-        __u64 f_bavail;
-        __u64 f_files;
-        __u64 f_ffree;
-        __kernel_fsid_t f_fsid;
-        __u32 f_namelen;
-        __u32 f_frsize;
-        __u32 f_flags;
-        __u32 f_spare[4];
-};
-
-#endif /* __s390x__ */
 #endif
diff --git a/arch/s390/include/uapi/asm/virtio-ccw.h b/arch/s390/include/uapi/asm/virtio-ccw.h
new file mode 100644
index 000000000000..a9a4ebf79fa7
--- /dev/null
+++ b/arch/s390/include/uapi/asm/virtio-ccw.h
@@ -0,0 +1,21 @@
+/*
+ * Definitions for virtio-ccw devices.
+ *
+ * Copyright IBM Corp. 2013
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License (version 2 only)
+ * as published by the Free Software Foundation.
+ *
+ *  Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
+ */
+#ifndef __KVM_VIRTIO_CCW_H
+#define __KVM_VIRTIO_CCW_H
+
+/* Alignment of vring buffers. */
+#define KVM_VIRTIO_CCW_RING_ALIGN 4096
+
+/* Subcode for diagnose 500 (virtio hypercall). */
+#define KVM_S390_VIRTIO_CCW_NOTIFY 3
+
+#endif
diff --git a/arch/s390/kernel/Makefile b/arch/s390/kernel/Makefile
index 2ac311ef5c9b..4bb2a4656163 100644
--- a/arch/s390/kernel/Makefile
+++ b/arch/s390/kernel/Makefile
@@ -14,16 +14,25 @@ endif
 CFLAGS_smp.o    := -Wno-nonnull
 
 #
+# Disable tailcall optimizations for stack / callchain walking functions
+# since this might generate broken code when accessing register 15 and
+# passing its content to other functions.
+#
+CFLAGS_stacktrace.o     += -fno-optimize-sibling-calls
+CFLAGS_dumpstack.o      += -fno-optimize-sibling-calls
+
+#
 # Pass UTS_MACHINE for user_regset definition
 #
 CFLAGS_ptrace.o         += -DUTS_MACHINE='"$(UTS_MACHINE)"'
 
 CFLAGS_sysinfo.o += -Iinclude/math-emu -Iarch/s390/math-emu -w
 
-obj-y   :=  bitmap.o traps.o time.o process.o base.o early.o setup.o vtime.o \
-            processor.o sys_s390.o ptrace.o signal.o cpcmd.o ebcdic.o nmi.o \
-            debug.o irq.o ipl.o dis.o diag.o mem_detect.o sclp.o vdso.o \
-            sysinfo.o jump_label.o lgr.o os_info.o machine_kexec.o pgm_check.o
+obj-y   := bitmap.o traps.o time.o process.o base.o early.o setup.o vtime.o
+obj-y   += processor.o sys_s390.o ptrace.o signal.o cpcmd.o ebcdic.o nmi.o
+obj-y   += debug.o irq.o ipl.o dis.o diag.o sclp.o vdso.o
+obj-y   += sysinfo.o jump_label.o lgr.o os_info.o machine_kexec.o pgm_check.o
+obj-y   += dumpstack.o
 
 obj-y   += $(if $(CONFIG_64BIT),entry64.o,entry.o)
 obj-y   += $(if $(CONFIG_64BIT),reipl64.o,reipl.o)
diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c
index fface87056eb..7a82f9f70100 100644
--- a/arch/s390/kernel/asm-offsets.c
+++ b/arch/s390/kernel/asm-offsets.c
@@ -35,6 +35,7 @@ int main(void)
         DEFINE(__TI_task, offsetof(struct thread_info, task));
         DEFINE(__TI_domain, offsetof(struct thread_info, exec_domain));
         DEFINE(__TI_flags, offsetof(struct thread_info, flags));
+        DEFINE(__TI_sysc_table, offsetof(struct thread_info, sys_call_table));
         DEFINE(__TI_cpu, offsetof(struct thread_info, cpu));
         DEFINE(__TI_precount, offsetof(struct thread_info, preempt_count));
         DEFINE(__TI_user_timer, offsetof(struct thread_info, user_timer));
diff --git a/arch/s390/kernel/compat_linux.c b/arch/s390/kernel/compat_linux.c
index 19f26de27fae..8b6e4f5288a2 100644
--- a/arch/s390/kernel/compat_linux.c
+++ b/arch/s390/kernel/compat_linux.c
@@ -288,51 +288,13 @@ asmlinkage long sys32_getegid16(void)
         return high2lowgid(from_kgid_munged(current_user_ns(), current_egid()));
 }
 
-/*
- * sys32_ipc() is the de-multiplexer for the SysV IPC calls in 32bit emulation.
- *
- * This is really horribly ugly.
- */
 #ifdef CONFIG_SYSVIPC
-asmlinkage long sys32_ipc(u32 call, int first, int second, int third, u32 ptr)
+COMPAT_SYSCALL_DEFINE5(s390_ipc, uint, call, int, first, unsigned long, second,
+                unsigned long, third, compat_uptr_t, ptr)
 {
         if (call >> 16)         /* hack for backward compatibility */
                 return -EINVAL;
-        switch (call) {
-        case SEMTIMEDOP:
-                return compat_sys_semtimedop(first, compat_ptr(ptr),
-                                             second, compat_ptr(third));
-        case SEMOP:
-                /* struct sembuf is the same on 32 and 64bit :)) */
-                return sys_semtimedop(first, compat_ptr(ptr),
-                                      second, NULL);
-        case SEMGET:
-                return sys_semget(first, second, third);
-        case SEMCTL:
-                return compat_sys_semctl(first, second, third,
-                                         compat_ptr(ptr));
-        case MSGSND:
-                return compat_sys_msgsnd(first, second, third,
-                                         compat_ptr(ptr));
-        case MSGRCV:
-                return compat_sys_msgrcv(first, second, 0, third,
-                                         0, compat_ptr(ptr));
-        case MSGGET:
-                return sys_msgget((key_t) first, second);
-        case MSGCTL:
-                return compat_sys_msgctl(first, second, compat_ptr(ptr));
-        case SHMAT:
-                return compat_sys_shmat(first, second, third,
-                                        0, compat_ptr(ptr));
-        case SHMDT:
-                return sys_shmdt(compat_ptr(ptr));
-        case SHMGET:
-                return sys_shmget(first, (unsigned)second, third);
-        case SHMCTL:
-                return compat_sys_shmctl(first, second, compat_ptr(ptr));
-        }
-
-        return -ENOSYS;
+        return compat_sys_ipc(call, first, second, third, ptr, third);
 }
 #endif
 
@@ -373,48 +335,6 @@ asmlinkage compat_ssize_t sys32_readahead(int fd, u32 offhi, u32 offlo, s32 coun
         return sys_readahead(fd, ((loff_t)AA(offhi) << 32) | AA(offlo), count);
 }
 
-asmlinkage long sys32_sendfile(int out_fd, int in_fd, compat_off_t __user *offset, size_t count)
-{
-        mm_segment_t old_fs = get_fs();
-        int ret;
-        off_t of;
-        
-        if (offset && get_user(of, offset))
-                return -EFAULT;
-                
-        set_fs(KERNEL_DS);
-        ret = sys_sendfile(out_fd, in_fd,
-                           offset ? (off_t __force __user *) &of : NULL, count);
-        set_fs(old_fs);
-        
-        if (offset && put_user(of, offset))
-                return -EFAULT;
-                
-        return ret;
-}
-
-asmlinkage long sys32_sendfile64(int out_fd, int in_fd,
-                                compat_loff_t __user *offset, s32 count)
-{
-        mm_segment_t old_fs = get_fs();
-        int ret;
-        loff_t lof;
-        
-        if (offset && get_user(lof, offset))
-                return -EFAULT;
-                
-        set_fs(KERNEL_DS);
-        ret = sys_sendfile64(out_fd, in_fd,
-                             offset ? (loff_t __force __user *) &lof : NULL,
-                             count);
-        set_fs(old_fs);
-        
-        if (offset && put_user(lof, offset))
-                return -EFAULT;
-                
-        return ret;
-}
-
 struct stat64_emu31 {
         unsigned long long  st_dev;
         unsigned int    __pad1;
diff --git a/arch/s390/kernel/compat_linux.h b/arch/s390/kernel/compat_linux.h
index 00d92a5a6f6c..976518c0592a 100644
--- a/arch/s390/kernel/compat_linux.h
+++ b/arch/s390/kernel/compat_linux.h
@@ -94,7 +94,6 @@ long sys32_getuid16(void);
 long sys32_geteuid16(void);
 long sys32_getgid16(void);
 long sys32_getegid16(void);
-long sys32_ipc(u32 call, int first, int second, int third, u32 ptr);
 long sys32_truncate64(const char __user * path, unsigned long high,
                       unsigned long low);
 long sys32_ftruncate64(unsigned int fd, unsigned long high, unsigned long low);
@@ -106,10 +105,6 @@ long sys32_pread64(unsigned int fd, char __user *ubuf, size_t count,
 long sys32_pwrite64(unsigned int fd, const char __user *ubuf,
                     size_t count, u32 poshi, u32 poslo);
 compat_ssize_t sys32_readahead(int fd, u32 offhi, u32 offlo, s32 count);
-long sys32_sendfile(int out_fd, int in_fd, compat_off_t __user *offset,
-                    size_t count);
-long sys32_sendfile64(int out_fd, int in_fd, compat_loff_t __user *offset,
-                      s32 count);
 long sys32_stat64(const char __user * filename, struct stat64_emu31 __user * statbuf);
 long sys32_lstat64(const char __user * filename,
                    struct stat64_emu31 __user * statbuf);
diff --git a/arch/s390/kernel/compat_signal.c b/arch/s390/kernel/compat_signal.c
index 6de049fbe62d..c439ac9ced09 100644
--- a/arch/s390/kernel/compat_signal.c
+++ b/arch/s390/kernel/compat_signal.c
@@ -362,6 +362,7 @@ static int setup_frame32(int sig, struct k_sigaction *ka,
                 /* set extra registers only for synchronous signals */
                 regs->gprs[4] = regs->int_code & 127;
                 regs->gprs[5] = regs->int_parm_long;
+                regs->gprs[6] = task_thread_info(current)->last_break;
         }
 
         /* Place signal number on stack to allow backtrace from handler.  */
@@ -421,6 +422,7 @@ static int setup_rt_frame32(int sig, struct k_sigaction *ka, siginfo_t *info,
         regs->gprs[2] = map_signal(sig);
         regs->gprs[3] = (__force __u64) &frame->info;
         regs->gprs[4] = (__force __u64) &frame->uc;
+        regs->gprs[5] = task_thread_info(current)->last_break;
         return 0;
 
 give_sigsegv:
diff --git a/arch/s390/kernel/compat_wrapper.S b/arch/s390/kernel/compat_wrapper.S
index 3c98c4dc5aca..2d72d9e96c15 100644
--- a/arch/s390/kernel/compat_wrapper.S
+++ b/arch/s390/kernel/compat_wrapper.S
@@ -258,11 +258,6 @@ ENTRY(sys32_mmap2_wrapper)
         llgtr   %r2,%r2                 # struct mmap_arg_struct_emu31 *
         jg      sys32_mmap2                     # branch to system call
 
-ENTRY(compat_sys_getrusage_wrapper)
-        lgfr    %r2,%r2                 # int
-        llgtr   %r3,%r3                 # struct rusage_emu31 *
-        jg      compat_sys_getrusage    # branch to system call
-
 ENTRY(compat_sys_gettimeofday_wrapper)
         llgtr   %r2,%r2                 # struct timeval_emu31 *
         llgtr   %r3,%r3                 # struct timezone *
@@ -393,14 +388,6 @@ ENTRY(compat_sys_sysinfo_wrapper)
         llgtr   %r2,%r2                 # struct sysinfo_emu31 *
         jg      compat_sys_sysinfo      # branch to system call
 
-ENTRY(sys32_ipc_wrapper)
-        llgfr   %r2,%r2                 # uint
-        lgfr    %r3,%r3                 # int
-        lgfr    %r4,%r4                 # int
-        lgfr    %r5,%r5                 # int
-        llgfr   %r6,%r6                 # u32
-        jg      sys32_ipc               # branch to system call
-
 ENTRY(sys32_fsync_wrapper)
         llgfr   %r2,%r2                 # unsigned int
         jg      sys_fsync               # branch to system call
@@ -666,13 +653,6 @@ ENTRY(sys32_capset_wrapper)
         llgtr   %r3,%r3                 # const cap_user_data_t
         jg      sys_capset              # branch to system call
 
-ENTRY(sys32_sendfile_wrapper)
-        lgfr    %r2,%r2                 # int
-        lgfr    %r3,%r3                 # int
-        llgtr   %r4,%r4                 # __kernel_off_emu31_t *
-        llgfr   %r5,%r5                 # size_t
-        jg      sys32_sendfile          # branch to system call
-
 #sys32_vfork_wrapper                    # done in vfork_glue
 
 ENTRY(sys32_truncate64_wrapper)
@@ -938,13 +918,6 @@ ENTRY(sys_epoll_wait_wrapper)
         lgfr    %r5,%r5                 # int
         jg      sys_epoll_wait          # branch to system call
 
-ENTRY(sys32_lookup_dcookie_wrapper)
-        sllg    %r2,%r2,32              # get high word of 64bit dcookie
-        or      %r2,%r3                 # get low word of 64bit dcookie
-        llgtr   %r3,%r4                 # char *
-        llgfr   %r4,%r5                 # size_t
-        jg      sys_lookup_dcookie
-
 ENTRY(sys32_fadvise64_wrapper)
         lgfr    %r2,%r2                 # int
         sllg    %r3,%r3,32              # get high word of 64bit loff_t
@@ -1264,29 +1237,12 @@ ENTRY(sys_tee_wrapper)
         llgfr   %r5,%r5                 # unsigned int
         jg      sys_tee
 
-ENTRY(compat_sys_vmsplice_wrapper)
-        lgfr    %r2,%r2                 # int
-        llgtr   %r3,%r3                 # compat_iovec *
-        llgfr   %r4,%r4                 # unsigned int
-        llgfr   %r5,%r5                 # unsigned int
-        jg      compat_sys_vmsplice
-
 ENTRY(sys_getcpu_wrapper)
         llgtr   %r2,%r2                 # unsigned *
         llgtr   %r3,%r3                 # unsigned *
         llgtr   %r4,%r4                 # struct getcpu_cache *
         jg      sys_getcpu
 
-ENTRY(compat_sys_epoll_pwait_wrapper)
-        lgfr    %r2,%r2                 # int
-        llgtr   %r3,%r3                 # struct compat_epoll_event *
-        lgfr    %r4,%r4                 # int
-        lgfr    %r5,%r5                 # int
-        llgtr   %r6,%r6                 # compat_sigset_t *
-        llgf    %r0,164(%r15)           # compat_size_t
-        stg     %r0,160(%r15)
-        jg      compat_sys_epoll_pwait
-
 ENTRY(compat_sys_utimes_wrapper)
         llgtr   %r2,%r2                 # char *
         llgtr   %r3,%r3                 # struct compat_timeval *
@@ -1299,12 +1255,6 @@ ENTRY(compat_sys_utimensat_wrapper)
         lgfr    %r5,%r5                 # int
         jg      compat_sys_utimensat
 
-ENTRY(compat_sys_signalfd_wrapper)
-        lgfr    %r2,%r2                 # int
-        llgtr   %r3,%r3                 # compat_sigset_t *
-        llgfr   %r4,%r4                 # compat_size_t
-        jg      compat_sys_signalfd
-
 ENTRY(sys_eventfd_wrapper)
         llgfr   %r2,%r2                 # unsigned int
         jg      sys_eventfd
@@ -1323,13 +1273,6 @@ ENTRY(sys_timerfd_create_wrapper)
         lgfr    %r3,%r3                 # int
         jg      sys_timerfd_create
 
-ENTRY(compat_sys_signalfd4_wrapper)
-        lgfr    %r2,%r2                 # int
-        llgtr   %r3,%r3                 # compat_sigset_t *
-        llgfr   %r4,%r4                 # compat_size_t
-        lgfr    %r5,%r5                 # int
-        jg      compat_sys_signalfd4
-
 ENTRY(sys_eventfd2_wrapper)
         llgfr   %r2,%r2                 # unsigned int
         lgfr    %r3,%r3                 # int
@@ -1361,13 +1304,6 @@ ENTRY(sys32_readahead_wrapper)
         lgfr    %r5,%r5                 # s32
         jg      sys32_readahead         # branch to system call
 
-ENTRY(sys32_sendfile64_wrapper)
-        lgfr    %r2,%r2                 # int
-        lgfr    %r3,%r3                 # int
-        llgtr   %r4,%r4                 # compat_loff_t *
-        lgfr    %r5,%r5                 # s32
-        jg      sys32_sendfile64        # branch to system call
-
 ENTRY(sys_tkill_wrapper)
         lgfr    %r2,%r2                 # pid_t
         lgfr    %r3,%r3                 # int
@@ -1387,22 +1323,6 @@ ENTRY(compat_sys_keyctl_wrapper)
         llgfr   %r6,%r6                 # u32
         jg      compat_sys_keyctl       # branch to system call
 
-ENTRY(compat_sys_preadv_wrapper)
-        llgfr   %r2,%r2                 # unsigned long
-        llgtr   %r3,%r3                 # compat_iovec *
-        llgfr   %r4,%r4                 # unsigned long
-        llgfr   %r5,%r5                 # u32
-        llgfr   %r6,%r6                 # u32
-        jg      compat_sys_preadv       # branch to system call
-
-ENTRY(compat_sys_pwritev_wrapper)
-        llgfr   %r2,%r2                 # unsigned long
-        llgtr   %r3,%r3                 # compat_iovec *
-        llgfr   %r4,%r4                 # unsigned long
-        llgfr   %r5,%r5                 # u32
-        llgfr   %r6,%r6                 # u32
-        jg      compat_sys_pwritev      # branch to system call
-
 ENTRY(sys_perf_event_open_wrapper)
         llgtr   %r2,%r2                 # const struct perf_event_attr *
         lgfr    %r3,%r3                 # pid_t
diff --git a/arch/s390/kernel/crash_dump.c b/arch/s390/kernel/crash_dump.c
index fb8d8781a011..f703d91bf720 100644
--- a/arch/s390/kernel/crash_dump.c
+++ b/arch/s390/kernel/crash_dump.c
@@ -88,8 +88,8 @@ static struct mem_chunk *get_memory_layout(void)
         struct mem_chunk *chunk_array;
 
         chunk_array = kzalloc_panic(MEMORY_CHUNKS * sizeof(struct mem_chunk));
-        detect_memory_layout(chunk_array);
-        create_mem_hole(chunk_array, OLDMEM_BASE, OLDMEM_SIZE, CHUNK_CRASHK);
+        detect_memory_layout(chunk_array, 0);
+        create_mem_hole(chunk_array, OLDMEM_BASE, OLDMEM_SIZE);
         return chunk_array;
 }
 
@@ -344,7 +344,7 @@ static int loads_init(Elf64_Phdr *phdr, u64 loads_offset)
         for (i = 0; i < MEMORY_CHUNKS; i++) {
                 mem_chunk = &chunk_array[i];
                 if (mem_chunk->size == 0)
-                        break;
+                        continue;
                 if (chunk_array[i].type != CHUNK_READ_WRITE &&
                     chunk_array[i].type != CHUNK_READ_ONLY)
                         continue;
diff --git a/arch/s390/kernel/dis.c b/arch/s390/kernel/dis.c
index 3ad5e9540160..7f4a4a8c847c 100644
--- a/arch/s390/kernel/dis.c
+++ b/arch/s390/kernel/dis.c
@@ -1696,14 +1696,15 @@ static struct insn *find_insn(unsigned char *code)
  * insn_to_mnemonic - decode an s390 instruction
  * @instruction: instruction to decode
  * @buf: buffer to fill with mnemonic
+ * @len: length of buffer
  *
  * Decode the instruction at @instruction and store the corresponding
- * mnemonic into @buf.
+ * mnemonic into @buf of length @len.
  * @buf is left unchanged if the instruction could not be decoded.
  * Returns:
  *  %0 on success, %-ENOENT if the instruction was not found.
  */
-int insn_to_mnemonic(unsigned char *instruction, char buf[8])
+int insn_to_mnemonic(unsigned char *instruction, char *buf, unsigned int len)
 {
         struct insn *insn;
 
@@ -1711,10 +1712,10 @@ int insn_to_mnemonic(unsigned char *instruction, char buf[8])
         if (!insn)
                 return -ENOENT;
         if (insn->name[0] == '\0')
-                snprintf(buf, 8, "%s",
+                snprintf(buf, len, "%s",
                          long_insn_name[(int) insn->name[1]]);
         else
-                snprintf(buf, 8, "%.5s", insn->name);
+                snprintf(buf, len, "%.5s", insn->name);
         return 0;
 }
 EXPORT_SYMBOL_GPL(insn_to_mnemonic);
diff --git a/arch/s390/kernel/dumpstack.c b/arch/s390/kernel/dumpstack.c
new file mode 100644
index 000000000000..298297477257
--- /dev/null
+++ b/arch/s390/kernel/dumpstack.c
@@ -0,0 +1,212 @@
+/*
+ * Stack dumping functions
+ *
+ *  Copyright IBM Corp. 1999, 2013
+ */
+
+#include <linux/kallsyms.h>
+#include <linux/hardirq.h>
+#include <linux/kprobes.h>
+#include <linux/utsname.h>
+#include <linux/export.h>
+#include <linux/kdebug.h>
+#include <linux/ptrace.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <asm/processor.h>
+#include <asm/debug.h>
+#include <asm/ipl.h>
+
+#ifndef CONFIG_64BIT
+#define LONG "%08lx "
+#define FOURLONG "%08lx %08lx %08lx %08lx\n"
+static int kstack_depth_to_print = 12;
+#else /* CONFIG_64BIT */
+#define LONG "%016lx "
+#define FOURLONG "%016lx %016lx %016lx %016lx\n"
+static int kstack_depth_to_print = 20;
+#endif /* CONFIG_64BIT */
+
+/*
+ * For show_trace we have tree different stack to consider:
+ *   - the panic stack which is used if the kernel stack has overflown
+ *   - the asynchronous interrupt stack (cpu related)
+ *   - the synchronous kernel stack (process related)
+ * The stack trace can start at any of the three stack and can potentially
+ * touch all of them. The order is: panic stack, async stack, sync stack.
+ */
+static unsigned long
+__show_trace(unsigned long sp, unsigned long low, unsigned long high)
+{
+        struct stack_frame *sf;
+        struct pt_regs *regs;
+
+        while (1) {
+                sp = sp & PSW_ADDR_INSN;
+                if (sp < low || sp > high - sizeof(*sf))
+                        return sp;
+                sf = (struct stack_frame *) sp;
+                printk("([<%016lx>] ", sf->gprs[8] & PSW_ADDR_INSN);
+                print_symbol("%s)\n", sf->gprs[8] & PSW_ADDR_INSN);
+                /* Follow the backchain. */
+                while (1) {
+                        low = sp;
+                        sp = sf->back_chain & PSW_ADDR_INSN;
+                        if (!sp)
+                                break;
+                        if (sp <= low || sp > high - sizeof(*sf))
+                                return sp;
+                        sf = (struct stack_frame *) sp;
+                        printk(" [<%016lx>] ", sf->gprs[8] & PSW_ADDR_INSN);
+                        print_symbol("%s\n", sf->gprs[8] & PSW_ADDR_INSN);
+                }
+                /* Zero backchain detected, check for interrupt frame. */
+                sp = (unsigned long) (sf + 1);
+                if (sp <= low || sp > high - sizeof(*regs))
+                        return sp;
+                regs = (struct pt_regs *) sp;
+                printk(" [<%016lx>] ", regs->psw.addr & PSW_ADDR_INSN);
+                print_symbol("%s\n", regs->psw.addr & PSW_ADDR_INSN);
+                low = sp;
+                sp = regs->gprs[15];
+        }
+}
+
+static void show_trace(struct task_struct *task, unsigned long *stack)
+{
+        register unsigned long __r15 asm ("15");
+        unsigned long sp;
+
+        sp = (unsigned long) stack;
+        if (!sp)
+                sp = task ? task->thread.ksp : __r15;
+        printk("Call Trace:\n");
+#ifdef CONFIG_CHECK_STACK
+        sp = __show_trace(sp, S390_lowcore.panic_stack - 4096,
+                          S390_lowcore.panic_stack);
+#endif
+        sp = __show_trace(sp, S390_lowcore.async_stack - ASYNC_SIZE,
+                          S390_lowcore.async_stack);
+        if (task)
+                __show_trace(sp, (unsigned long) task_stack_page(task),
+                             (unsigned long) task_stack_page(task) + THREAD_SIZE);
+        else
+                __show_trace(sp, S390_lowcore.thread_info,
+                             S390_lowcore.thread_info + THREAD_SIZE);
+        if (!task)
+                task = current;
+        debug_show_held_locks(task);
+}
+
+void show_stack(struct task_struct *task, unsigned long *sp)
+{
+        register unsigned long *__r15 asm ("15");
+        unsigned long *stack;
+        int i;
+
+        if (!sp)
+                stack = task ? (unsigned long *) task->thread.ksp : __r15;
+        else
+                stack = sp;
+
+        for (i = 0; i < kstack_depth_to_print; i++) {
+                if (((addr_t) stack & (THREAD_SIZE-1)) == 0)
+                        break;
+                if ((i * sizeof(long) % 32) == 0)
+                        printk("%s       ", i == 0 ? "" : "\n");
+                printk(LONG, *stack++);
+        }
+        printk("\n");
+        show_trace(task, sp);
+}
+
+static void show_last_breaking_event(struct pt_regs *regs)
+{
+#ifdef CONFIG_64BIT
+        printk("Last Breaking-Event-Address:\n");
+        printk(" [<%016lx>] ", regs->args[0] & PSW_ADDR_INSN);
+        print_symbol("%s\n", regs->args[0] & PSW_ADDR_INSN);
+#endif
+}
+
+static inline int mask_bits(struct pt_regs *regs, unsigned long bits)
+{
+        return (regs->psw.mask & bits) / ((~bits + 1) & bits);
+}
+
+void show_registers(struct pt_regs *regs)
+{
+        char *mode;
+
+        mode = user_mode(regs) ? "User" : "Krnl";
+        printk("%s PSW : %p %p",
+               mode, (void *) regs->psw.mask,
+               (void *) regs->psw.addr);
+        print_symbol(" (%s)\n", regs->psw.addr & PSW_ADDR_INSN);
+        printk("           R:%x T:%x IO:%x EX:%x Key:%x M:%x W:%x "
+               "P:%x AS:%x CC:%x PM:%x", mask_bits(regs, PSW_MASK_PER),
+               mask_bits(regs, PSW_MASK_DAT), mask_bits(regs, PSW_MASK_IO),
+               mask_bits(regs, PSW_MASK_EXT), mask_bits(regs, PSW_MASK_KEY),
+               mask_bits(regs, PSW_MASK_MCHECK), mask_bits(regs, PSW_MASK_WAIT),
+               mask_bits(regs, PSW_MASK_PSTATE), mask_bits(regs, PSW_MASK_ASC),
+               mask_bits(regs, PSW_MASK_CC), mask_bits(regs, PSW_MASK_PM));
+#ifdef CONFIG_64BIT
+        printk(" EA:%x", mask_bits(regs, PSW_MASK_EA | PSW_MASK_BA));
+#endif
+        printk("\n%s GPRS: " FOURLONG, mode,
+               regs->gprs[0], regs->gprs[1], regs->gprs[2], regs->gprs[3]);
+        printk("           " FOURLONG,
+               regs->gprs[4], regs->gprs[5], regs->gprs[6], regs->gprs[7]);
+        printk("           " FOURLONG,
+               regs->gprs[8], regs->gprs[9], regs->gprs[10], regs->gprs[11]);
+        printk("           " FOURLONG,
+               regs->gprs[12], regs->gprs[13], regs->gprs[14], regs->gprs[15]);
+        show_code(regs);
+}
+
+void show_regs(struct pt_regs *regs)
+{
+        show_regs_print_info(KERN_DEFAULT);
+        show_registers(regs);
+        /* Show stack backtrace if pt_regs is from kernel mode */
+        if (!user_mode(regs))
+                show_trace(NULL, (unsigned long *) regs->gprs[15]);
+        show_last_breaking_event(regs);
+}
+
+static DEFINE_SPINLOCK(die_lock);
+
+void die(struct pt_regs *regs, const char *str)
+{
+        static int die_counter;
+
+        oops_enter();
+        lgr_info_log();
+        debug_stop_all();
+        console_verbose();
+        spin_lock_irq(&die_lock);
+        bust_spinlocks(1);
+        printk("%s: %04x [#%d] ", str, regs->int_code & 0xffff, ++die_counter);
+#ifdef CONFIG_PREEMPT
+        printk("PREEMPT ");
+#endif
+#ifdef CONFIG_SMP
+        printk("SMP ");
+#endif
+#ifdef CONFIG_DEBUG_PAGEALLOC
+        printk("DEBUG_PAGEALLOC");
+#endif
+        printk("\n");
+        notify_die(DIE_OOPS, str, regs, 0, regs->int_code & 0xffff, SIGSEGV);
+        print_modules();
+        show_regs(regs);
+        bust_spinlocks(0);
+        add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
+        spin_unlock_irq(&die_lock);
+        if (in_interrupt())
+                panic("Fatal exception in interrupt");
+        if (panic_on_oops)
+                panic("Fatal exception: panic_on_oops");
+        oops_exit();
+        do_exit(SIGSEGV);
+}
diff --git a/arch/s390/kernel/early.c b/arch/s390/kernel/early.c
index bda011e2f8ae..dc8770d7173c 100644
--- a/arch/s390/kernel/early.c
+++ b/arch/s390/kernel/early.c
@@ -482,7 +482,6 @@ void __init startup_init(void)
         detect_machine_facilities();
         setup_topology();
         sclp_facilities_detect();
-        detect_memory_layout(memory_chunk);
 #ifdef CONFIG_DYNAMIC_FTRACE
         S390_lowcore.ftrace_func = (unsigned long)ftrace_caller;
 #endif
diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S
index 94feff7d6132..4d5e6f8a7978 100644
--- a/arch/s390/kernel/entry.S
+++ b/arch/s390/kernel/entry.S
@@ -45,6 +45,7 @@ _TIF_TRACE    = (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \
 
 STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER
 STACK_SIZE  = 1 << STACK_SHIFT
+STACK_INIT  = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE
 
 #define BASED(name) name-system_call(%r13)
 
@@ -97,10 +98,10 @@ STACK_SIZE  = 1 << STACK_SHIFT
         sra     %r14,\shift
         jnz     1f
         CHECK_STACK 1<<\shift,\savearea
+        ahi     %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
         j       2f
 1:      l       %r15,\stack             # load target stack
-2:      ahi     %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
-        la      %r11,STACK_FRAME_OVERHEAD(%r15)
+2:      la      %r11,STACK_FRAME_OVERHEAD(%r15)
         .endm
 
         .macro  ADD64 high,low,timer
@@ -150,7 +151,7 @@ ENTRY(__switch_to)
         l       %r4,__THREAD_info(%r2)          # get thread_info of prev
         l       %r5,__THREAD_info(%r3)          # get thread_info of next
         lr      %r15,%r5
-        ahi     %r15,STACK_SIZE                 # end of kernel stack of next
+        ahi     %r15,STACK_INIT                 # end of kernel stack of next
         st      %r3,__LC_CURRENT                # store task struct of next
         st      %r5,__LC_THREAD_INFO            # store thread info of next
         st      %r15,__LC_KERNEL_STACK          # store end of kernel stack
@@ -178,7 +179,6 @@ sysc_stm:
         l       %r13,__LC_SVC_NEW_PSW+4
 sysc_per:
         l       %r15,__LC_KERNEL_STACK
-        ahi     %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
         la      %r11,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs
 sysc_vtime:
         UPDATE_VTIME %r8,%r9,__LC_SYNC_ENTER_TIMER
@@ -188,6 +188,7 @@ sysc_vtime:
         mvc     __PT_INT_CODE(4,%r11),__LC_SVC_ILC
 sysc_do_svc:
         oi      __TI_flags+3(%r12),_TIF_SYSCALL
+        l       %r10,__TI_sysc_table(%r12)      # 31 bit system call table
         lh      %r8,__PT_INT_CODE+2(%r11)
         sla     %r8,2                           # shift and test for svc0
         jnz     sysc_nr_ok
@@ -198,7 +199,6 @@ sysc_do_svc:
         lr      %r8,%r1
         sla     %r8,2
 sysc_nr_ok:
-        l       %r10,BASED(.Lsys_call_table)    # 31 bit system call table
         xc      __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15)
         st      %r2,__PT_ORIG_GPR2(%r11)
         st      %r7,STACK_FRAME_OVERHEAD(%r15)
@@ -359,11 +359,11 @@ ENTRY(pgm_check_handler)
         tm      __LC_PGM_ILC+3,0x80     # check for per exception
         jnz     pgm_svcper              # -> single stepped svc
 0:      CHECK_STACK STACK_SIZE,__LC_SAVE_AREA_SYNC
+        ahi     %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
         j       2f
 1:      UPDATE_VTIME %r14,%r15,__LC_SYNC_ENTER_TIMER
         l       %r15,__LC_KERNEL_STACK
-2:      ahi     %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
-        la      %r11,STACK_FRAME_OVERHEAD(%r15)
+2:      la      %r11,STACK_FRAME_OVERHEAD(%r15)
         stm     %r0,%r7,__PT_R0(%r11)
         mvc     __PT_R8(32,%r11),__LC_SAVE_AREA_SYNC
         stm     %r8,%r9,__PT_PSW(%r11)
@@ -485,7 +485,6 @@ io_work:
 #
 io_work_user:
         l       %r1,__LC_KERNEL_STACK
-        ahi     %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
         mvc     STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
         xc      __SF_BACKCHAIN(4,%r1),__SF_BACKCHAIN(%r1)
         la      %r11,STACK_FRAME_OVERHEAD(%r1)
@@ -646,7 +645,6 @@ mcck_skip:
         tm      __PT_PSW+1(%r11),0x01   # returning to user ?
         jno     mcck_return
         l       %r1,__LC_KERNEL_STACK   # switch to kernel stack
-        ahi     %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
         mvc     STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
         xc      __SF_BACKCHAIN(4,%r1),__SF_BACKCHAIN(%r1)
         la      %r11,STACK_FRAME_OVERHEAD(%r15)
@@ -674,6 +672,7 @@ mcck_panic:
         sra     %r14,PAGE_SHIFT
         jz      0f
         l       %r15,__LC_PANIC_STACK
+        j       mcck_skip
 0:      ahi     %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
         j       mcck_skip
 
@@ -714,12 +713,10 @@ ENTRY(restart_int_handler)
  */
 stack_overflow:
         l       %r15,__LC_PANIC_STACK   # change to panic stack
-        ahi     %r15,-__PT_SIZE         # create pt_regs
-        stm     %r0,%r7,__PT_R0(%r15)
-        stm     %r8,%r9,__PT_PSW(%r15)
+        la      %r11,STACK_FRAME_OVERHEAD(%r15)
+        stm     %r0,%r7,__PT_R0(%r11)
+        stm     %r8,%r9,__PT_PSW(%r11)
         mvc     __PT_R8(32,%r11),0(%r14)
-        lr      %r15,%r11
-        ahi     %r15,-STACK_FRAME_OVERHEAD
         l       %r1,BASED(1f)
         xc      __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15)
         lr      %r2,%r11                # pass pointer to pt_regs
@@ -799,15 +796,14 @@ cleanup_system_call:
         mvc     __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
         # set up saved register 11
         l       %r15,__LC_KERNEL_STACK
-        ahi     %r15,-__PT_SIZE
-        st      %r15,12(%r11)           # r11 pt_regs pointer
+        la      %r9,STACK_FRAME_OVERHEAD(%r15)
+        st      %r9,12(%r11)            # r11 pt_regs pointer
         # fill pt_regs
-        mvc     __PT_R8(32,%r15),__LC_SAVE_AREA_SYNC
-        stm     %r0,%r7,__PT_R0(%r15)
-        mvc     __PT_PSW(8,%r15),__LC_SVC_OLD_PSW
-        mvc     __PT_INT_CODE(4,%r15),__LC_SVC_ILC
+        mvc     __PT_R8(32,%r9),__LC_SAVE_AREA_SYNC
+        stm     %r0,%r7,__PT_R0(%r9)
+        mvc     __PT_PSW(8,%r9),__LC_SVC_OLD_PSW
+        mvc     __PT_INT_CODE(4,%r9),__LC_SVC_ILC
         # setup saved register 15
-        ahi     %r15,-STACK_FRAME_OVERHEAD
         st      %r15,28(%r11)           # r15 stack pointer
         # set new psw address and exit
         l       %r9,BASED(cleanup_table+4)      # sysc_do_svc + 0x80000000
@@ -910,7 +906,6 @@ cleanup_idle_wait:
 .Ltrace_enter:          .long   do_syscall_trace_enter
 .Ltrace_exit:           .long   do_syscall_trace_exit
 .Lschedule_tail:        .long   schedule_tail
-.Lsys_call_table:       .long   sys_call_table
 .Lsysc_per:             .long   sysc_per + 0x80000000
 #ifdef CONFIG_TRACE_IRQFLAGS
 .Lhardirqs_on:          .long   trace_hardirqs_on_caller
diff --git a/arch/s390/kernel/entry.h b/arch/s390/kernel/entry.h
index c3a736a3ed44..aa0ab02e9595 100644
--- a/arch/s390/kernel/entry.h
+++ b/arch/s390/kernel/entry.h
@@ -7,6 +7,7 @@
 #include <asm/cputime.h>
 
 extern void *restart_stack;
+extern unsigned long suspend_zero_pages;
 
 void system_call(void);
 void pgm_check_handler(void);
diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S
index 2e6d60c55f90..4c17eece707e 100644
--- a/arch/s390/kernel/entry64.S
+++ b/arch/s390/kernel/entry64.S
@@ -39,6 +39,7 @@ __PT_R15     =	__PT_GPRS + 120
 
 STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER
 STACK_SIZE  = 1 << STACK_SHIFT
+STACK_INIT = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE
 
 _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
                  _TIF_MCCK_PENDING | _TIF_PER_TRAP )
@@ -124,10 +125,10 @@ _TIF_EXIT_SIE = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_MCCK_PENDING)
         srag    %r14,%r14,\shift
         jnz     1f
         CHECK_STACK 1<<\shift,\savearea
+        aghi    %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
         j       2f
 1:      lg      %r15,\stack             # load target stack
-2:      aghi    %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
-        la      %r11,STACK_FRAME_OVERHEAD(%r15)
+2:      la      %r11,STACK_FRAME_OVERHEAD(%r15)
         .endm
 
         .macro UPDATE_VTIME scratch,enter_timer
@@ -177,7 +178,7 @@ ENTRY(__switch_to)
         lg      %r4,__THREAD_info(%r2)          # get thread_info of prev
         lg      %r5,__THREAD_info(%r3)          # get thread_info of next
         lgr     %r15,%r5
-        aghi    %r15,STACK_SIZE                 # end of kernel stack of next
+        aghi    %r15,STACK_INIT                 # end of kernel stack of next
         stg     %r3,__LC_CURRENT                # store task struct of next
         stg     %r5,__LC_THREAD_INFO            # store thread info of next
         stg     %r15,__LC_KERNEL_STACK          # store end of kernel stack
@@ -203,10 +204,8 @@ sysc_stmg:
         stmg    %r8,%r15,__LC_SAVE_AREA_SYNC
         lg      %r10,__LC_LAST_BREAK
         lg      %r12,__LC_THREAD_INFO
-        larl    %r13,system_call
 sysc_per:
         lg      %r15,__LC_KERNEL_STACK
-        aghi    %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
         la      %r11,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs
 sysc_vtime:
         UPDATE_VTIME %r13,__LC_SYNC_ENTER_TIMER
@@ -217,6 +216,7 @@ sysc_vtime:
         mvc     __PT_INT_CODE(4,%r11),__LC_SVC_ILC
 sysc_do_svc:
         oi      __TI_flags+7(%r12),_TIF_SYSCALL
+        lg      %r10,__TI_sysc_table(%r12)      # address of system call table
         llgh    %r8,__PT_INT_CODE+2(%r11)
         slag    %r8,%r8,2                       # shift and test for svc 0
         jnz     sysc_nr_ok
@@ -227,13 +227,6 @@ sysc_do_svc:
         sth     %r1,__PT_INT_CODE+2(%r11)
         slag    %r8,%r1,2
 sysc_nr_ok:
-        larl    %r10,sys_call_table             # 64 bit system call table
-#ifdef CONFIG_COMPAT
-        tm      __TI_flags+5(%r12),(_TIF_31BIT>>16)
-        jno     sysc_noemu
-        larl    %r10,sys_call_table_emu         # 31 bit system call table
-sysc_noemu:
-#endif
         xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
         stg     %r2,__PT_ORIG_GPR2(%r11)
         stg     %r7,STACK_FRAME_OVERHEAD(%r15)
@@ -389,6 +382,7 @@ ENTRY(pgm_check_handler)
         tm      __LC_PGM_ILC+3,0x80     # check for per exception
         jnz     pgm_svcper              # -> single stepped svc
 0:      CHECK_STACK STACK_SIZE,__LC_SAVE_AREA_SYNC
+        aghi    %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
         j       2f
 1:      UPDATE_VTIME %r14,__LC_SYNC_ENTER_TIMER
         LAST_BREAK %r14
@@ -398,8 +392,7 @@ ENTRY(pgm_check_handler)
         tm      __LC_PGM_ILC+2,0x02     # check for transaction abort
         jz      2f
         mvc     __THREAD_trap_tdb(256,%r14),0(%r13)
-2:      aghi    %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
-        la      %r11,STACK_FRAME_OVERHEAD(%r15)
+2:      la      %r11,STACK_FRAME_OVERHEAD(%r15)
         stmg    %r0,%r7,__PT_R0(%r11)
         mvc     __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
         stmg    %r8,%r9,__PT_PSW(%r11)
@@ -526,7 +519,6 @@ io_work:
 #
 io_work_user:
         lg      %r1,__LC_KERNEL_STACK
-        aghi    %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
         mvc     STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
         xc      __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
         la      %r11,STACK_FRAME_OVERHEAD(%r1)
@@ -688,7 +680,6 @@ mcck_skip:
         tm      __PT_PSW+1(%r11),0x01   # returning to user ?
         jno     mcck_return
         lg      %r1,__LC_KERNEL_STACK   # switch to kernel stack
-        aghi    %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
         mvc     STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
         xc      __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
         la      %r11,STACK_FRAME_OVERHEAD(%r1)
@@ -755,14 +746,12 @@ ENTRY(restart_int_handler)
  * Setup a pt_regs so that show_trace can provide a good call trace.
  */
 stack_overflow:
-        lg      %r11,__LC_PANIC_STACK   # change to panic stack
-        aghi    %r11,-__PT_SIZE         # create pt_regs
+        lg      %r15,__LC_PANIC_STACK   # change to panic stack
+        la      %r11,STACK_FRAME_OVERHEAD(%r15)
         stmg    %r0,%r7,__PT_R0(%r11)
         stmg    %r8,%r9,__PT_PSW(%r11)
         mvc     __PT_R8(64,%r11),0(%r14)
         stg     %r10,__PT_ORIG_GPR2(%r11) # store last break to orig_gpr2
-        lgr     %r15,%r11
-        aghi    %r15,-STACK_FRAME_OVERHEAD
         xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
         lgr     %r2,%r11                # pass pointer to pt_regs
         jg      kernel_stack_overflow
@@ -846,15 +835,14 @@ cleanup_system_call:
         mvc     __TI_last_break(8,%r12),16(%r11)
 0:      # set up saved register r11
         lg      %r15,__LC_KERNEL_STACK
-        aghi    %r15,-__PT_SIZE
-        stg     %r15,24(%r11)           # r11 pt_regs pointer
+        la      %r9,STACK_FRAME_OVERHEAD(%r15)
+        stg     %r9,24(%r11)            # r11 pt_regs pointer
         # fill pt_regs
-        mvc     __PT_R8(64,%r15),__LC_SAVE_AREA_SYNC
-        stmg    %r0,%r7,__PT_R0(%r15)
-        mvc     __PT_PSW(16,%r15),__LC_SVC_OLD_PSW
-        mvc     __PT_INT_CODE(4,%r15),__LC_SVC_ILC
+        mvc     __PT_R8(64,%r9),__LC_SAVE_AREA_SYNC
+        stmg    %r0,%r7,__PT_R0(%r9)
+        mvc     __PT_PSW(16,%r9),__LC_SVC_OLD_PSW
+        mvc     __PT_INT_CODE(4,%r9),__LC_SVC_ILC
         # setup saved register r15
-        aghi    %r15,-STACK_FRAME_OVERHEAD
         stg     %r15,56(%r11)           # r15 stack pointer
         # set new psw address and exit
         larl    %r9,sysc_do_svc
@@ -1011,6 +999,7 @@ sys_call_table:
 #ifdef CONFIG_COMPAT
 
 #define SYSCALL(esa,esame,emu)  .long emu
+        .globl  sys_call_table_emu
 sys_call_table_emu:
 #include "syscalls.S"
 #undef SYSCALL
diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c
index 1630f439cd2a..f7fb58903f6a 100644
--- a/arch/s390/kernel/irq.c
+++ b/arch/s390/kernel/irq.c
@@ -33,7 +33,7 @@ struct irq_class {
 };
 
 /*
- * The list of "main" irq classes on s390. This is the list of interrrupts
+ * The list of "main" irq classes on s390. This is the list of interrupts
  * that appear both in /proc/stat ("intr" line) and /proc/interrupts.
  * Historically only external and I/O interrupts have been part of /proc/stat.
  * We can't add the split external and I/O sub classes since the first field
@@ -162,10 +162,8 @@ asmlinkage void do_softirq(void)
 #ifdef CONFIG_PROC_FS
 void init_irq_proc(void)
 {
-        struct proc_dir_entry *root_irq_dir;
-
-        root_irq_dir = proc_mkdir("irq", NULL);
-        create_prof_cpu_mask(root_irq_dir);
+        if (proc_mkdir("irq", NULL))
+                create_prof_cpu_mask();
 }
 #endif
 
diff --git a/arch/s390/kernel/machine_kexec.c b/arch/s390/kernel/machine_kexec.c
index b3de27700016..ac2178161ec3 100644
--- a/arch/s390/kernel/machine_kexec.c
+++ b/arch/s390/kernel/machine_kexec.c
@@ -13,6 +13,7 @@
 #include <linux/reboot.h>
 #include <linux/ftrace.h>
 #include <linux/debug_locks.h>
+#include <linux/suspend.h>
 #include <asm/cio.h>
 #include <asm/setup.h>
 #include <asm/pgtable.h>
@@ -67,6 +68,35 @@ void setup_regs(void)
         memcpy((void *) SAVE_AREA_BASE, (void *) sa, sizeof(struct save_area));
 }
 
+/*
+ * PM notifier callback for kdump
+ */
+static int machine_kdump_pm_cb(struct notifier_block *nb, unsigned long action,
+                               void *ptr)
+{
+        switch (action) {
+        case PM_SUSPEND_PREPARE:
+        case PM_HIBERNATION_PREPARE:
+                if (crashk_res.start)
+                        crash_map_reserved_pages();
+                break;
+        case PM_POST_SUSPEND:
+        case PM_POST_HIBERNATION:
+                if (crashk_res.start)
+                        crash_unmap_reserved_pages();
+                break;
+        default:
+                return NOTIFY_DONE;
+        }
+        return NOTIFY_OK;
+}
+
+static int __init machine_kdump_pm_init(void)
+{
+        pm_notifier(machine_kdump_pm_cb, 0);
+        return 0;
+}
+arch_initcall(machine_kdump_pm_init);
 #endif
 
 /*
diff --git a/arch/s390/kernel/mem_detect.c b/arch/s390/kernel/mem_detect.c
deleted file mode 100644
index 22d502e885ed..000000000000
--- a/arch/s390/kernel/mem_detect.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright IBM Corp. 2008, 2009
- *
- * Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <asm/ipl.h>
-#include <asm/sclp.h>
-#include <asm/setup.h>
-
-#define ADDR2G (1ULL << 31)
-
-static void find_memory_chunks(struct mem_chunk chunk[])
-{
-        unsigned long long memsize, rnmax, rzm;
-        unsigned long addr = 0, size;
-        int i = 0, type;
-
-        rzm = sclp_get_rzm();
-        rnmax = sclp_get_rnmax();
-        memsize = rzm * rnmax;
-        if (!rzm)
-                rzm = 1ULL << 17;
-        if (sizeof(long) == 4) {
-                rzm = min(ADDR2G, rzm);
-                memsize = memsize ? min(ADDR2G, memsize) : ADDR2G;
-        }
-        do {
-                size = 0;
-                type = tprot(addr);
-                do {
-                        size += rzm;
-                        if (memsize && addr + size >= memsize)
-                                break;
-                } while (type == tprot(addr + size));
-                if (type == CHUNK_READ_WRITE || type == CHUNK_READ_ONLY) {
-                        chunk[i].addr = addr;
-                        chunk[i].size = size;
-                        chunk[i].type = type;
-                        i++;
-                }
-                addr += size;
-        } while (addr < memsize && i < MEMORY_CHUNKS);
-}
-
-void detect_memory_layout(struct mem_chunk chunk[])
-{
-        unsigned long flags, cr0;
-
-        memset(chunk, 0, MEMORY_CHUNKS * sizeof(struct mem_chunk));
-        /* Disable IRQs, DAT and low address protection so tprot does the
-         * right thing and we don't get scheduled away with low address
-         * protection disabled.
-         */
-        flags = __arch_local_irq_stnsm(0xf8);
-        __ctl_store(cr0, 0, 0);
-        __ctl_clear_bit(0, 28);
-        find_memory_chunks(chunk);
-        __ctl_load(cr0, 0, 0);
-        arch_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(detect_memory_layout);
-
-/*
- * Move memory chunks array from index "from" to index "to"
- */
-static void mem_chunk_move(struct mem_chunk chunk[], int to, int from)
-{
-        int cnt = MEMORY_CHUNKS - to;
-
-        memmove(&chunk[to], &chunk[from], cnt * sizeof(struct mem_chunk));
-}
-
-/*
- * Initialize memory chunk
- */
-static void mem_chunk_init(struct mem_chunk *chunk, unsigned long addr,
-                           unsigned long size, int type)
-{
-        chunk->type = type;
-        chunk->addr = addr;
-        chunk->size = size;
-}
-
-/*
- * Create memory hole with given address, size, and type
- */
-void create_mem_hole(struct mem_chunk chunk[], unsigned long addr,
-                     unsigned long size, int type)
-{
-        unsigned long lh_start, lh_end, lh_size, ch_start, ch_end, ch_size;
-        int i, ch_type;
-
-        for (i = 0; i < MEMORY_CHUNKS; i++) {
-                if (chunk[i].size == 0)
-                        continue;
-
-                /* Define chunk properties */
-                ch_start = chunk[i].addr;
-                ch_size = chunk[i].size;
-                ch_end = ch_start + ch_size - 1;
-                ch_type = chunk[i].type;
-
-                /* Is memory chunk hit by memory hole? */
-                if (addr + size <= ch_start)
-                        continue; /* No: memory hole in front of chunk */
-                if (addr > ch_end)
-                        continue; /* No: memory hole after chunk */
-
-                /* Yes: Define local hole properties */
-                lh_start = max(addr, chunk[i].addr);
-                lh_end = min(addr + size - 1, ch_end);
-                lh_size = lh_end - lh_start + 1;
-
-                if (lh_start == ch_start && lh_end == ch_end) {
-                        /* Hole covers complete memory chunk */
-                        mem_chunk_init(&chunk[i], lh_start, lh_size, type);
-                } else if (lh_end == ch_end) {
-                        /* Hole starts in memory chunk and convers chunk end */
-                        mem_chunk_move(chunk, i + 1, i);
-                        mem_chunk_init(&chunk[i], ch_start, ch_size - lh_size,
-                                       ch_type);
-                        mem_chunk_init(&chunk[i + 1], lh_start, lh_size, type);
-                        i += 1;
-                } else if (lh_start == ch_start) {
-                        /* Hole ends in memory chunk */
-                        mem_chunk_move(chunk, i + 1, i);
-                        mem_chunk_init(&chunk[i], lh_start, lh_size, type);
-                        mem_chunk_init(&chunk[i + 1], lh_end + 1,
-                                       ch_size - lh_size, ch_type);
-                        break;
-                } else {
-                        /* Hole splits memory chunk */
-                        mem_chunk_move(chunk, i + 2, i);
-                        mem_chunk_init(&chunk[i], ch_start,
-                                       lh_start - ch_start, ch_type);
-                        mem_chunk_init(&chunk[i + 1], lh_start, lh_size, type);
-                        mem_chunk_init(&chunk[i + 2], lh_end + 1,
-                                       ch_end - lh_end, ch_type);
-                        break;
-                }
-        }
-}
diff --git a/arch/s390/kernel/os_info.c b/arch/s390/kernel/os_info.c
index 46480d81df00..d112fc66f993 100644
--- a/arch/s390/kernel/os_info.c
+++ b/arch/s390/kernel/os_info.c
@@ -10,6 +10,7 @@
 
 #include <linux/crash_dump.h>
 #include <linux/kernel.h>
+#include <linux/slab.h>
 #include <asm/checksum.h>
 #include <asm/lowcore.h>
 #include <asm/os_info.h>
diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c
index 536d64579d9a..2bc3eddae34a 100644
--- a/arch/s390/kernel/process.c
+++ b/arch/s390/kernel/process.c
@@ -61,18 +61,8 @@ unsigned long thread_saved_pc(struct task_struct *tsk)
         return sf->gprs[8];
 }
 
-/*
- * The idle loop on a S390...
- */
-static void default_idle(void)
+void arch_cpu_idle(void)
 {
-        if (cpu_is_offline(smp_processor_id()))
-                cpu_die();
-        local_irq_disable();
-        if (need_resched()) {
-                local_irq_enable();
-                return;
-        }
         local_mcck_disable();
         if (test_thread_flag(TIF_MCCK_PENDING)) {
                 local_mcck_enable();
@@ -83,19 +73,15 @@ static void default_idle(void)
         vtime_stop_cpu();
 }
 
-void cpu_idle(void)
+void arch_cpu_idle_exit(void)
 {
-        for (;;) {
-                tick_nohz_idle_enter();
-                rcu_idle_enter();
-                while (!need_resched() && !test_thread_flag(TIF_MCCK_PENDING))
-                        default_idle();
-                rcu_idle_exit();
-                tick_nohz_idle_exit();
-                if (test_thread_flag(TIF_MCCK_PENDING))
-                        s390_handle_mcck();
-                schedule_preempt_disabled();
-        }
+        if (test_thread_flag(TIF_MCCK_PENDING))
+                s390_handle_mcck();
+}
+
+void arch_cpu_idle_dead(void)
+{
+        cpu_die();
 }
 
 extern void __kprobes kernel_thread_starter(void);
diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
index 29268859d8ee..0a49095104c9 100644
--- a/arch/s390/kernel/setup.c
+++ b/arch/s390/kernel/setup.c
@@ -226,25 +226,17 @@ static void __init conmode_default(void)
 }
 
 #ifdef CONFIG_ZFCPDUMP
-static void __init setup_zfcpdump(unsigned int console_devno)
+static void __init setup_zfcpdump(void)
 {
-        static char str[41];
-
         if (ipl_info.type != IPL_TYPE_FCP_DUMP)
                 return;
         if (OLDMEM_BASE)
                 return;
-        if (console_devno != -1)
-                sprintf(str, " cio_ignore=all,!0.0.%04x,!0.0.%04x",
-                        ipl_info.data.fcp.dev_id.devno, console_devno);
-        else
-                sprintf(str, " cio_ignore=all,!0.0.%04x",
-                        ipl_info.data.fcp.dev_id.devno);
-        strcat(boot_command_line, str);
+        strcat(boot_command_line, " cio_ignore=all,!ipldev,!condev");
         console_loglevel = 2;
 }
 #else
-static inline void setup_zfcpdump(unsigned int console_devno) {}
+static inline void setup_zfcpdump(void) {}
 #endif /* CONFIG_ZFCPDUMP */
 
  /*
@@ -377,11 +369,14 @@ static void __init setup_lowcore(void)
                 PSW_MASK_DAT | PSW_MASK_MCHECK;
         lc->io_new_psw.addr = PSW_ADDR_AMODE | (unsigned long) io_int_handler;
         lc->clock_comparator = -1ULL;
-        lc->kernel_stack = ((unsigned long) &init_thread_union) + THREAD_SIZE;
+        lc->kernel_stack = ((unsigned long) &init_thread_union)
+                + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs);
         lc->async_stack = (unsigned long)
-                __alloc_bootmem(ASYNC_SIZE, ASYNC_SIZE, 0) + ASYNC_SIZE;
+                __alloc_bootmem(ASYNC_SIZE, ASYNC_SIZE, 0)
+                + ASYNC_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs);
         lc->panic_stack = (unsigned long)
-                __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, 0) + PAGE_SIZE;
+                __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, 0)
+                + PAGE_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs);
         lc->current_task = (unsigned long) init_thread_union.thread_info.task;
         lc->thread_info = (unsigned long) &init_thread_union;
         lc->machine_flags = S390_lowcore.machine_flags;
@@ -468,14 +463,10 @@ static void __init setup_resources(void)
         for (i = 0; i < MEMORY_CHUNKS; i++) {
                 if (!memory_chunk[i].size)
                         continue;
-                if (memory_chunk[i].type == CHUNK_OLDMEM ||
-                    memory_chunk[i].type == CHUNK_CRASHK)
-                        continue;
                 res = alloc_bootmem_low(sizeof(*res));
                 res->flags = IORESOURCE_BUSY | IORESOURCE_MEM;
                 switch (memory_chunk[i].type) {
                 case CHUNK_READ_WRITE:
-                case CHUNK_CRASHK:
                         res->name = "System RAM";
                         break;
                 case CHUNK_READ_ONLY:
@@ -507,12 +498,10 @@ static void __init setup_resources(void)
         }
 }
 
-unsigned long real_memory_size;
-EXPORT_SYMBOL_GPL(real_memory_size);
-
 static void __init setup_memory_end(void)
 {
         unsigned long vmax, vmalloc_size, tmp;
+        unsigned long real_memory_size = 0;
         int i;
 
 
@@ -522,7 +511,6 @@ static void __init setup_memory_end(void)
                 memory_end_set = 1;
         }
 #endif
-        real_memory_size = 0;
         memory_end &= PAGE_MASK;
 
         /*
@@ -535,6 +523,8 @@ static void __init setup_memory_end(void)
                 unsigned long align;
 
                 chunk = &memory_chunk[i];
+                if (!chunk->size)
+                        continue;
                 align = 1UL << (MAX_ORDER + PAGE_SHIFT - 1);
                 start = (chunk->addr + align - 1) & ~(align - 1);
                 end = (chunk->addr + chunk->size) & ~(align - 1);
@@ -585,6 +575,8 @@ static void __init setup_memory_end(void)
         for (i = 0; i < MEMORY_CHUNKS; i++) {
                 struct mem_chunk *chunk = &memory_chunk[i];
 
+                if (!chunk->size)
+                        continue;
                 if (chunk->addr >= memory_end) {
                         memset(chunk, 0, sizeof(*chunk));
                         continue;
@@ -685,15 +677,6 @@ static int __init verify_crash_base(unsigned long crash_base,
 }
 
 /*
- * Reserve kdump memory by creating a memory hole in the mem_chunk array
- */
-static void __init reserve_kdump_bootmem(unsigned long addr, unsigned long size,
-                                         int type)
-{
-        create_mem_hole(memory_chunk, addr, size, type);
-}
-
-/*
  * When kdump is enabled, we have to ensure that no memory from
  * the area [0 - crashkernel memory size] and
  * [crashk_res.start - crashk_res.end] is set offline.
@@ -724,16 +707,22 @@ static struct notifier_block kdump_mem_nb = {
 static void reserve_oldmem(void)
 {
 #ifdef CONFIG_CRASH_DUMP
+        unsigned long real_size = 0;
+        int i;
+
         if (!OLDMEM_BASE)
                 return;
+        for (i = 0; i < MEMORY_CHUNKS; i++) {
+                struct mem_chunk *chunk = &memory_chunk[i];
 
-        reserve_kdump_bootmem(OLDMEM_BASE, OLDMEM_SIZE, CHUNK_OLDMEM);
-        reserve_kdump_bootmem(OLDMEM_SIZE, memory_end - OLDMEM_SIZE,
-                              CHUNK_OLDMEM);
-        if (OLDMEM_BASE + OLDMEM_SIZE == real_memory_size)
+                real_size = max(real_size, chunk->addr + chunk->size);
+        }
+        create_mem_hole(memory_chunk, OLDMEM_BASE, OLDMEM_SIZE);
+        create_mem_hole(memory_chunk, OLDMEM_SIZE, real_size - OLDMEM_SIZE);
+        if (OLDMEM_BASE + OLDMEM_SIZE == real_size)
                 saved_max_pfn = PFN_DOWN(OLDMEM_BASE) - 1;
         else
-                saved_max_pfn = PFN_DOWN(real_memory_size) - 1;
+                saved_max_pfn = PFN_DOWN(real_size) - 1;
 #endif
 }
 
@@ -772,7 +761,7 @@ static void __init reserve_crashkernel(void)
         crashk_res.start = crash_base;
         crashk_res.end = crash_base + crash_size - 1;
         insert_resource(&iomem_resource, &crashk_res);
-        reserve_kdump_bootmem(crash_base, crash_size, CHUNK_CRASHK);
+        create_mem_hole(memory_chunk, crash_base, crash_size);
         pr_info("Reserving %lluMB of memory at %lluMB "
                 "for crashkernel (System RAM: %luMB)\n",
                 crash_size >> 20, crash_base >> 20, memory_end >> 20);
@@ -844,11 +833,10 @@ static void __init setup_memory(void)
          * Register RAM areas with the bootmem allocator.
          */
 
-        for (i = 0; i < MEMORY_CHUNKS && memory_chunk[i].size > 0; i++) {
+        for (i = 0; i < MEMORY_CHUNKS; i++) {
                 unsigned long start_chunk, end_chunk, pfn;
 
-                if (memory_chunk[i].type != CHUNK_READ_WRITE &&
-                    memory_chunk[i].type != CHUNK_CRASHK)
+                if (!memory_chunk[i].size)
                         continue;
                 start_chunk = PFN_DOWN(memory_chunk[i].addr);
                 end_chunk = start_chunk + PFN_DOWN(memory_chunk[i].size);
@@ -1064,12 +1052,12 @@ void __init setup_arch(char **cmdline_p)
                 memcpy(&uaccess, &uaccess_std, sizeof(uaccess));
 
         parse_early_param();
-
+        detect_memory_layout(memory_chunk, memory_end);
         os_info_init();
         setup_ipl();
+        reserve_oldmem();
         setup_memory_end();
         setup_addressing_mode();
-        reserve_oldmem();
         reserve_crashkernel();
         setup_memory();
         setup_resources();
@@ -1094,5 +1082,5 @@ void __init setup_arch(char **cmdline_p)
         set_preferred_console();
 
         /* Setup zfcpdump support */
-        setup_zfcpdump(console_devno);
+        setup_zfcpdump();
 }
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index 549c9d173c0f..8074cb4b7cbf 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -181,8 +181,10 @@ static int __cpuinit pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu)
         lc = pcpu->lowcore;
         memcpy(lc, &S390_lowcore, 512);
         memset((char *) lc + 512, 0, sizeof(*lc) - 512);
-        lc->async_stack = pcpu->async_stack + ASYNC_SIZE;
-        lc->panic_stack = pcpu->panic_stack + PAGE_SIZE;
+        lc->async_stack = pcpu->async_stack + ASYNC_SIZE
+                - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs);
+        lc->panic_stack = pcpu->panic_stack + PAGE_SIZE
+                - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs);
         lc->cpu_nr = cpu;
 #ifndef CONFIG_64BIT
         if (MACHINE_HAS_IEEE) {
@@ -253,7 +255,8 @@ static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk)
         struct _lowcore *lc = pcpu->lowcore;
         struct thread_info *ti = task_thread_info(tsk);
 
-        lc->kernel_stack = (unsigned long) task_stack_page(tsk) + THREAD_SIZE;
+        lc->kernel_stack = (unsigned long) task_stack_page(tsk)
+                + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs);
         lc->thread_info = (unsigned long) task_thread_info(tsk);
         lc->current_task = (unsigned long) tsk;
         lc->user_timer = ti->user_timer;
@@ -711,8 +714,7 @@ static void __cpuinit smp_start_secondary(void *cpuvoid)
         set_cpu_online(smp_processor_id(), true);
         inc_irq_stat(CPU_RST);
         local_irq_enable();
-        /* cpu_idle will call schedule for us */
-        cpu_idle();
+        cpu_startup_entry(CPUHP_ONLINE);
 }
 
 /* Upping and downing of CPUs */
@@ -810,8 +812,10 @@ void __init smp_prepare_boot_cpu(void)
         pcpu->state = CPU_STATE_CONFIGURED;
         pcpu->address = boot_cpu_address;
         pcpu->lowcore = (struct _lowcore *)(unsigned long) store_prefix();
-        pcpu->async_stack = S390_lowcore.async_stack - ASYNC_SIZE;
-        pcpu->panic_stack = S390_lowcore.panic_stack - PAGE_SIZE;
+        pcpu->async_stack = S390_lowcore.async_stack - ASYNC_SIZE
+                + STACK_FRAME_OVERHEAD + sizeof(struct pt_regs);
+        pcpu->panic_stack = S390_lowcore.panic_stack - PAGE_SIZE
+                + STACK_FRAME_OVERHEAD + sizeof(struct pt_regs);
         S390_lowcore.percpu_offset = __per_cpu_offset[0];
         smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN);
         set_cpu_present(0, true);
diff --git a/arch/s390/kernel/suspend.c b/arch/s390/kernel/suspend.c
index aa1494d0e380..c479d2f9605b 100644
--- a/arch/s390/kernel/suspend.c
+++ b/arch/s390/kernel/suspend.c
@@ -41,6 +41,7 @@ struct page_key_data {
 static struct page_key_data *page_key_data;
 static struct page_key_data *page_key_rp, *page_key_wp;
 static unsigned long page_key_rx, page_key_wx;
+unsigned long suspend_zero_pages;
 
 /*
  * For each page in the hibernation image one additional byte is
@@ -149,6 +150,36 @@ int pfn_is_nosave(unsigned long pfn)
         return 0;
 }
 
+/*
+ * PM notifier callback for suspend
+ */
+static int suspend_pm_cb(struct notifier_block *nb, unsigned long action,
+                         void *ptr)
+{
+        switch (action) {
+        case PM_SUSPEND_PREPARE:
+        case PM_HIBERNATION_PREPARE:
+                suspend_zero_pages = __get_free_pages(GFP_KERNEL, LC_ORDER);
+                if (!suspend_zero_pages)
+                        return NOTIFY_BAD;
+                break;
+        case PM_POST_SUSPEND:
+        case PM_POST_HIBERNATION:
+                free_pages(suspend_zero_pages, LC_ORDER);
+                break;
+        default:
+                return NOTIFY_DONE;
+        }
+        return NOTIFY_OK;
+}
+
+static int __init suspend_pm_init(void)
+{
+        pm_notifier(suspend_pm_cb, 0);
+        return 0;
+}
+arch_initcall(suspend_pm_init);
+
 void save_processor_state(void)
 {
         /* swsusp_arch_suspend() actually saves all cpu register contents.
diff --git a/arch/s390/kernel/swsusp_asm64.S b/arch/s390/kernel/swsusp_asm64.S
index d4ca4e0617b5..c487be4cfc81 100644
--- a/arch/s390/kernel/swsusp_asm64.S
+++ b/arch/s390/kernel/swsusp_asm64.S
@@ -36,8 +36,8 @@ ENTRY(swsusp_arch_suspend)
         /* Store prefix register on stack */
         stpx    __SF_EMPTY(%r15)
 
-        /* Save prefix register contents for lowcore */
-        llgf    %r4,__SF_EMPTY(%r15)
+        /* Save prefix register contents for lowcore copy */
+        llgf    %r10,__SF_EMPTY(%r15)
 
         /* Get pointer to save area */
         lghi    %r1,0x1000
@@ -91,7 +91,18 @@ ENTRY(swsusp_arch_suspend)
         xc      __SF_EMPTY(4,%r15),__SF_EMPTY(%r15)
         spx     __SF_EMPTY(%r15)
 
+        /* Save absolute zero pages */
+        larl    %r2,suspend_zero_pages
+        lg      %r2,0(%r2)
+        lghi    %r4,0
+        lghi    %r3,2*PAGE_SIZE
+        lghi    %r5,2*PAGE_SIZE
+1:      mvcle   %r2,%r4,0
+        jo      1b
+
+        /* Copy lowcore to absolute zero lowcore */
         lghi    %r2,0
+        lgr     %r4,%r10
         lghi    %r3,2*PAGE_SIZE
         lghi    %r5,2*PAGE_SIZE
 1:      mvcle   %r2,%r4,0
@@ -248,8 +259,20 @@ restore_registers:
         /* Load old stack */
         lg      %r15,0x2f8(%r13)
 
+        /* Save prefix register */
+        mvc __SF_EMPTY(4,%r15),0x318(%r13)
+
+        /* Restore absolute zero pages */
+        lghi    %r2,0
+        larl    %r4,suspend_zero_pages
+        lg      %r4,0(%r4)
+        lghi    %r3,2*PAGE_SIZE
+        lghi    %r5,2*PAGE_SIZE
+1:      mvcle   %r2,%r4,0
+        jo      1b
+
         /* Restore prefix register */
-        spx     0x318(%r13)
+        spx     __SF_EMPTY(%r15)
 
         /* Activate DAT */
         stosm   __SF_EMPTY(%r15),0x04
diff --git a/arch/s390/kernel/sys_s390.c b/arch/s390/kernel/sys_s390.c
index d0964d22adb5..23eb222c1658 100644
--- a/arch/s390/kernel/sys_s390.c
+++ b/arch/s390/kernel/sys_s390.c
@@ -132,19 +132,9 @@ SYSCALL_DEFINE1(s390_fadvise64_64, struct fadvise64_64_args __user *, args)
  * to
  *   %r2: fd, %r3: mode, %r4/%r5: offset, 96(%r15)-103(%r15): len
  */
-SYSCALL_DEFINE(s390_fallocate)(int fd, int mode, loff_t offset,
-                               u32 len_high, u32 len_low)
+SYSCALL_DEFINE5(s390_fallocate, int, fd, int, mode, loff_t, offset,
+                               u32, len_high, u32, len_low)
 {
         return sys_fallocate(fd, mode, offset, ((u64)len_high << 32) | len_low);
 }
-#ifdef CONFIG_HAVE_SYSCALL_WRAPPERS
-asmlinkage long SyS_s390_fallocate(long fd, long mode, loff_t offset,
-                                   long len_high, long len_low)
-{
-        return SYSC_s390_fallocate((int) fd, (int) mode, offset,
-                                   (u32) len_high, (u32) len_low);
-}
-SYSCALL_ALIAS(sys_s390_fallocate, SyS_s390_fallocate);
-#endif
-
 #endif
diff --git a/arch/s390/kernel/syscalls.S b/arch/s390/kernel/syscalls.S
index 630b935d1284..9f214e992eed 100644
--- a/arch/s390/kernel/syscalls.S
+++ b/arch/s390/kernel/syscalls.S
@@ -85,7 +85,7 @@ SYSCALL(sys_sigpending,sys_sigpending,compat_sys_sigpending_wrapper)
 SYSCALL(sys_sethostname,sys_sethostname,sys32_sethostname_wrapper)
 SYSCALL(sys_setrlimit,sys_setrlimit,compat_sys_setrlimit_wrapper)       /* 75 */
 SYSCALL(sys_old_getrlimit,sys_getrlimit,compat_sys_old_getrlimit_wrapper)
-SYSCALL(sys_getrusage,sys_getrusage,compat_sys_getrusage_wrapper)
+SYSCALL(sys_getrusage,sys_getrusage,compat_sys_getrusage)
 SYSCALL(sys_gettimeofday,sys_gettimeofday,compat_sys_gettimeofday_wrapper)
 SYSCALL(sys_settimeofday,sys_settimeofday,compat_sys_settimeofday_wrapper)
 SYSCALL(sys_getgroups16,sys_ni_syscall,sys32_getgroups16_wrapper)       /* 80 old getgroups16 syscall */
@@ -118,14 +118,14 @@ SYSCALL(sys_newstat,sys_newstat,compat_sys_newstat_wrapper)
 SYSCALL(sys_newlstat,sys_newlstat,compat_sys_newlstat_wrapper)
 SYSCALL(sys_newfstat,sys_newfstat,compat_sys_newfstat_wrapper)
 NI_SYSCALL                                                      /* old uname syscall */
-SYSCALL(sys_lookup_dcookie,sys_lookup_dcookie,sys32_lookup_dcookie_wrapper)     /* 110 */
+SYSCALL(sys_lookup_dcookie,sys_lookup_dcookie,compat_sys_lookup_dcookie)        /* 110 */
 SYSCALL(sys_vhangup,sys_vhangup,sys_vhangup)
 NI_SYSCALL                                                      /* old "idle" system call */
 NI_SYSCALL                                                      /* vm86old for i386 */
 SYSCALL(sys_wait4,sys_wait4,compat_sys_wait4)
 SYSCALL(sys_swapoff,sys_swapoff,sys32_swapoff_wrapper)          /* 115 */
 SYSCALL(sys_sysinfo,sys_sysinfo,compat_sys_sysinfo_wrapper)
-SYSCALL(sys_s390_ipc,sys_s390_ipc,sys32_ipc_wrapper)
+SYSCALL(sys_s390_ipc,sys_s390_ipc,compat_sys_s390_ipc)
 SYSCALL(sys_fsync,sys_fsync,sys32_fsync_wrapper)
 SYSCALL(sys_sigreturn,sys_sigreturn,sys32_sigreturn)
 SYSCALL(sys_clone,sys_clone,sys_clone_wrapper)                  /* 120 */
@@ -195,7 +195,7 @@ SYSCALL(sys_getcwd,sys_getcwd,sys32_getcwd_wrapper)
 SYSCALL(sys_capget,sys_capget,sys32_capget_wrapper)
 SYSCALL(sys_capset,sys_capset,sys32_capset_wrapper)             /* 185 */
 SYSCALL(sys_sigaltstack,sys_sigaltstack,compat_sys_sigaltstack)
-SYSCALL(sys_sendfile,sys_sendfile64,sys32_sendfile_wrapper)
+SYSCALL(sys_sendfile,sys_sendfile64,compat_sys_sendfile)
 NI_SYSCALL                                                      /* streams1 */
 NI_SYSCALL                                                      /* streams2 */
 SYSCALL(sys_vfork,sys_vfork,sys_vfork)                          /* 190 */
@@ -231,7 +231,7 @@ SYSCALL(sys_madvise,sys_madvise,sys32_madvise_wrapper)
 SYSCALL(sys_getdents64,sys_getdents64,sys32_getdents64_wrapper) /* 220 */
 SYSCALL(sys_fcntl64,sys_ni_syscall,compat_sys_fcntl64_wrapper)
 SYSCALL(sys_readahead,sys_readahead,sys32_readahead_wrapper)
-SYSCALL(sys_sendfile64,sys_ni_syscall,sys32_sendfile64_wrapper)
+SYSCALL(sys_sendfile64,sys_ni_syscall,compat_sys_sendfile64)
 SYSCALL(sys_setxattr,sys_setxattr,sys32_setxattr_wrapper)
 SYSCALL(sys_lsetxattr,sys_lsetxattr,sys32_lsetxattr_wrapper)    /* 225 */
 SYSCALL(sys_fsetxattr,sys_fsetxattr,sys32_fsetxattr_wrapper)
@@ -317,27 +317,27 @@ SYSCALL(sys_get_robust_list,sys_get_robust_list,compat_sys_get_robust_list)
 SYSCALL(sys_splice,sys_splice,sys_splice_wrapper)
 SYSCALL(sys_sync_file_range,sys_sync_file_range,sys_sync_file_range_wrapper)
 SYSCALL(sys_tee,sys_tee,sys_tee_wrapper)
-SYSCALL(sys_vmsplice,sys_vmsplice,compat_sys_vmsplice_wrapper)
+SYSCALL(sys_vmsplice,sys_vmsplice,compat_sys_vmsplice)
 NI_SYSCALL                                                      /* 310 sys_move_pages */
 SYSCALL(sys_getcpu,sys_getcpu,sys_getcpu_wrapper)
-SYSCALL(sys_epoll_pwait,sys_epoll_pwait,compat_sys_epoll_pwait_wrapper)
+SYSCALL(sys_epoll_pwait,sys_epoll_pwait,compat_sys_epoll_pwait)
 SYSCALL(sys_utimes,sys_utimes,compat_sys_utimes_wrapper)
 SYSCALL(sys_s390_fallocate,sys_fallocate,sys_fallocate_wrapper)
 SYSCALL(sys_utimensat,sys_utimensat,compat_sys_utimensat_wrapper)       /* 315 */
-SYSCALL(sys_signalfd,sys_signalfd,compat_sys_signalfd_wrapper)
+SYSCALL(sys_signalfd,sys_signalfd,compat_sys_signalfd)
 NI_SYSCALL                                              /* 317 old sys_timer_fd */
 SYSCALL(sys_eventfd,sys_eventfd,sys_eventfd_wrapper)
 SYSCALL(sys_timerfd_create,sys_timerfd_create,sys_timerfd_create_wrapper)
 SYSCALL(sys_timerfd_settime,sys_timerfd_settime,compat_sys_timerfd_settime) /* 320 */
 SYSCALL(sys_timerfd_gettime,sys_timerfd_gettime,compat_sys_timerfd_gettime)
-SYSCALL(sys_signalfd4,sys_signalfd4,compat_sys_signalfd4_wrapper)
+SYSCALL(sys_signalfd4,sys_signalfd4,compat_sys_signalfd4)
 SYSCALL(sys_eventfd2,sys_eventfd2,sys_eventfd2_wrapper)
 SYSCALL(sys_inotify_init1,sys_inotify_init1,sys_inotify_init1_wrapper)
 SYSCALL(sys_pipe2,sys_pipe2,sys_pipe2_wrapper) /* 325 */
 SYSCALL(sys_dup3,sys_dup3,sys_dup3_wrapper)
 SYSCALL(sys_epoll_create1,sys_epoll_create1,sys_epoll_create1_wrapper)
-SYSCALL(sys_preadv,sys_preadv,compat_sys_preadv_wrapper)
-SYSCALL(sys_pwritev,sys_pwritev,compat_sys_pwritev_wrapper)
+SYSCALL(sys_preadv,sys_preadv,compat_sys_preadv)
+SYSCALL(sys_pwritev,sys_pwritev,compat_sys_pwritev)
 SYSCALL(sys_rt_tgsigqueueinfo,sys_rt_tgsigqueueinfo,compat_sys_rt_tgsigqueueinfo) /* 330 */
 SYSCALL(sys_perf_event_open,sys_perf_event_open,sys_perf_event_open_wrapper)
 SYSCALL(sys_fanotify_init,sys_fanotify_init,sys_fanotify_init_wrapper)
diff --git a/arch/s390/kernel/traps.c b/arch/s390/kernel/traps.c
index 13dd63fba367..c5762324d9ee 100644
--- a/arch/s390/kernel/traps.c
+++ b/arch/s390/kernel/traps.c
@@ -12,49 +12,16 @@
  * 'Traps.c' handles hardware traps and faults after we have saved some
  * state in 'asm.s'.
  */
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/errno.h>
+#include <linux/kprobes.h>
+#include <linux/kdebug.h>
+#include <linux/module.h>
 #include <linux/ptrace.h>
-#include <linux/timer.h>
+#include <linux/sched.h>
 #include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/seq_file.h>
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/kdebug.h>
-#include <linux/kallsyms.h>
-#include <linux/reboot.h>
-#include <linux/kprobes.h>
-#include <linux/bug.h>
-#include <linux/utsname.h>
-#include <asm/uaccess.h>
-#include <asm/io.h>
-#include <linux/atomic.h>
-#include <asm/mathemu.h>
-#include <asm/cpcmd.h>
-#include <asm/lowcore.h>
-#include <asm/debug.h>
-#include <asm/ipl.h>
 #include "entry.h"
 
 int show_unhandled_signals = 1;
 
-#define stack_pointer ({ void **sp; asm("la %0,0(15)" : "=&d" (sp)); sp; })
-
-#ifndef CONFIG_64BIT
-#define LONG "%08lx "
-#define FOURLONG "%08lx %08lx %08lx %08lx\n"
-static int kstack_depth_to_print = 12;
-#else /* CONFIG_64BIT */
-#define LONG "%016lx "
-#define FOURLONG "%016lx %016lx %016lx %016lx\n"
-static int kstack_depth_to_print = 20;
-#endif /* CONFIG_64BIT */
-
 static inline void __user *get_trap_ip(struct pt_regs *regs)
 {
 #ifdef CONFIG_64BIT
@@ -72,215 +39,6 @@ static inline void __user *get_trap_ip(struct pt_regs *regs)
 #endif
 }
 
-/*
- * For show_trace we have tree different stack to consider:
- *   - the panic stack which is used if the kernel stack has overflown
- *   - the asynchronous interrupt stack (cpu related)
- *   - the synchronous kernel stack (process related)
- * The stack trace can start at any of the three stack and can potentially
- * touch all of them. The order is: panic stack, async stack, sync stack.
- */
-static unsigned long
-__show_trace(unsigned long sp, unsigned long low, unsigned long high)
-{
-        struct stack_frame *sf;
-        struct pt_regs *regs;
-
-        while (1) {
-                sp = sp & PSW_ADDR_INSN;
-                if (sp < low || sp > high - sizeof(*sf))
-                        return sp;
-                sf = (struct stack_frame *) sp;
-                printk("([<%016lx>] ", sf->gprs[8] & PSW_ADDR_INSN);
-                print_symbol("%s)\n", sf->gprs[8] & PSW_ADDR_INSN);
-                /* Follow the backchain. */
-                while (1) {
-                        low = sp;
-                        sp = sf->back_chain & PSW_ADDR_INSN;
-                        if (!sp)
-                                break;
-                        if (sp <= low || sp > high - sizeof(*sf))
-                                return sp;
-                        sf = (struct stack_frame *) sp;
-                        printk(" [<%016lx>] ", sf->gprs[8] & PSW_ADDR_INSN);
-                        print_symbol("%s\n", sf->gprs[8] & PSW_ADDR_INSN);
-                }
-                /* Zero backchain detected, check for interrupt frame. */
-                sp = (unsigned long) (sf + 1);
-                if (sp <= low || sp > high - sizeof(*regs))
-                        return sp;
-                regs = (struct pt_regs *) sp;
-                printk(" [<%016lx>] ", regs->psw.addr & PSW_ADDR_INSN);
-                print_symbol("%s\n", regs->psw.addr & PSW_ADDR_INSN);
-                low = sp;
-                sp = regs->gprs[15];
-        }
-}
-
-static void show_trace(struct task_struct *task, unsigned long *stack)
-{
-        register unsigned long __r15 asm ("15");
-        unsigned long sp;
-
-        sp = (unsigned long) stack;
-        if (!sp)
-                sp = task ? task->thread.ksp : __r15;
-        printk("Call Trace:\n");
-#ifdef CONFIG_CHECK_STACK
-        sp = __show_trace(sp, S390_lowcore.panic_stack - 4096,
-                          S390_lowcore.panic_stack);
-#endif
-        sp = __show_trace(sp, S390_lowcore.async_stack - ASYNC_SIZE,
-                          S390_lowcore.async_stack);
-        if (task)
-                __show_trace(sp, (unsigned long) task_stack_page(task),
-                             (unsigned long) task_stack_page(task) + THREAD_SIZE);
-        else
-                __show_trace(sp, S390_lowcore.thread_info,
-                             S390_lowcore.thread_info + THREAD_SIZE);
-        if (!task)
-                task = current;
-        debug_show_held_locks(task);
-}
-
-void show_stack(struct task_struct *task, unsigned long *sp)
-{
-        register unsigned long * __r15 asm ("15");
-        unsigned long *stack;
-        int i;
-
-        if (!sp)
-                stack = task ? (unsigned long *) task->thread.ksp : __r15;
-        else
-                stack = sp;
-
-        for (i = 0; i < kstack_depth_to_print; i++) {
-                if (((addr_t) stack & (THREAD_SIZE-1)) == 0)
-                        break;
-                if ((i * sizeof(long) % 32) == 0)
-                        printk("%s       ", i == 0 ? "" : "\n");
-                printk(LONG, *stack++);
-        }
-        printk("\n");
-        show_trace(task, sp);
-}
-
-static void show_last_breaking_event(struct pt_regs *regs)
-{
-#ifdef CONFIG_64BIT
-        printk("Last Breaking-Event-Address:\n");
-        printk(" [<%016lx>] ", regs->args[0] & PSW_ADDR_INSN);
-        print_symbol("%s\n", regs->args[0] & PSW_ADDR_INSN);
-#endif
-}
-
-/*
- * The architecture-independent dump_stack generator
- */
-void dump_stack(void)
-{
-        printk("CPU: %d %s %s %.*s\n",
-               task_thread_info(current)->cpu, print_tainted(),
-               init_utsname()->release,
-               (int)strcspn(init_utsname()->version, " "),
-               init_utsname()->version);
-        printk("Process %s (pid: %d, task: %p, ksp: %p)\n",
-               current->comm, current->pid, current,
-               (void *) current->thread.ksp);
-        show_stack(NULL, NULL);
-}
-EXPORT_SYMBOL(dump_stack);
-
-static inline int mask_bits(struct pt_regs *regs, unsigned long bits)
-{
-        return (regs->psw.mask & bits) / ((~bits + 1) & bits);
-}
-
-void show_registers(struct pt_regs *regs)
-{
-        char *mode;
-
-        mode = user_mode(regs) ? "User" : "Krnl";
-        printk("%s PSW : %p %p",
-               mode, (void *) regs->psw.mask,
-               (void *) regs->psw.addr);
-        print_symbol(" (%s)\n", regs->psw.addr & PSW_ADDR_INSN);
-        printk("           R:%x T:%x IO:%x EX:%x Key:%x M:%x W:%x "
-               "P:%x AS:%x CC:%x PM:%x", mask_bits(regs, PSW_MASK_PER),
-               mask_bits(regs, PSW_MASK_DAT), mask_bits(regs, PSW_MASK_IO),
-               mask_bits(regs, PSW_MASK_EXT), mask_bits(regs, PSW_MASK_KEY),
-               mask_bits(regs, PSW_MASK_MCHECK), mask_bits(regs, PSW_MASK_WAIT),
-               mask_bits(regs, PSW_MASK_PSTATE), mask_bits(regs, PSW_MASK_ASC),
-               mask_bits(regs, PSW_MASK_CC), mask_bits(regs, PSW_MASK_PM));
-#ifdef CONFIG_64BIT
-        printk(" EA:%x", mask_bits(regs, PSW_MASK_EA | PSW_MASK_BA));
-#endif
-        printk("\n%s GPRS: " FOURLONG, mode,
-               regs->gprs[0], regs->gprs[1], regs->gprs[2], regs->gprs[3]);
-        printk("           " FOURLONG,
-               regs->gprs[4], regs->gprs[5], regs->gprs[6], regs->gprs[7]);
-        printk("           " FOURLONG,
-               regs->gprs[8], regs->gprs[9], regs->gprs[10], regs->gprs[11]);
-        printk("           " FOURLONG,
-               regs->gprs[12], regs->gprs[13], regs->gprs[14], regs->gprs[15]);
-
-        show_code(regs);
-}       
-
-void show_regs(struct pt_regs *regs)
-{
-        printk("CPU: %d %s %s %.*s\n",
-               task_thread_info(current)->cpu, print_tainted(),
-               init_utsname()->release,
-               (int)strcspn(init_utsname()->version, " "),
-               init_utsname()->version);
-        printk("Process %s (pid: %d, task: %p, ksp: %p)\n",
-               current->comm, current->pid, current,
-               (void *) current->thread.ksp);
-        show_registers(regs);
-        /* Show stack backtrace if pt_regs is from kernel mode */
-        if (!user_mode(regs))
-                show_trace(NULL, (unsigned long *) regs->gprs[15]);
-        show_last_breaking_event(regs);
-}
-
-static DEFINE_SPINLOCK(die_lock);
-
-void die(struct pt_regs *regs, const char *str)
-{
-        static int die_counter;
-
-        oops_enter();
-        lgr_info_log();
-        debug_stop_all();
-        console_verbose();
-        spin_lock_irq(&die_lock);
-        bust_spinlocks(1);
-        printk("%s: %04x [#%d] ", str, regs->int_code & 0xffff, ++die_counter);
-#ifdef CONFIG_PREEMPT
-        printk("PREEMPT ");
-#endif
-#ifdef CONFIG_SMP
-        printk("SMP ");
-#endif
-#ifdef CONFIG_DEBUG_PAGEALLOC
-        printk("DEBUG_PAGEALLOC");
-#endif
-        printk("\n");
-        notify_die(DIE_OOPS, str, regs, 0, regs->int_code & 0xffff, SIGSEGV);
-        print_modules();
-        show_regs(regs);
-        bust_spinlocks(0);
-        add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
-        spin_unlock_irq(&die_lock);
-        if (in_interrupt())
-                panic("Fatal exception in interrupt");
-        if (panic_on_oops)
-                panic("Fatal exception: panic_on_oops");
-        oops_exit();
-        do_exit(SIGSEGV);
-}
-
 static inline void report_user_fault(struct pt_regs *regs, int signr)
 {
         if ((task_pid_nr(current) > 1) && !show_unhandled_signals)
diff --git a/arch/s390/kernel/vtime.c b/arch/s390/kernel/vtime.c
index a0042acbd989..3fb09359eda6 100644
--- a/arch/s390/kernel/vtime.c
+++ b/arch/s390/kernel/vtime.c
@@ -158,8 +158,6 @@ void __kprobes vtime_stop_cpu(void)
         unsigned long psw_mask;
 
         trace_hardirqs_on();
-        /* Don't trace preempt off for idle. */
-        stop_critical_timings();
 
         /* Wait for external, I/O or machine check interrupt. */
         psw_mask = psw_kernel_bits | PSW_MASK_WAIT | PSW_MASK_DAT |
@@ -169,9 +167,6 @@ void __kprobes vtime_stop_cpu(void)
         /* Call the assembler magic in entry.S */
         psw_idle(idle, psw_mask);
 
-        /* Reenable preemption tracer. */
-        start_critical_timings();
-
         /* Account time spent with enabled wait psw loaded as idle time. */
         idle->sequence++;
         smp_wmb();
diff --git a/arch/s390/kvm/Kconfig b/arch/s390/kvm/Kconfig
index 60f9f8ae0fc8..70b46eacf8e1 100644
--- a/arch/s390/kvm/Kconfig
+++ b/arch/s390/kvm/Kconfig
@@ -22,6 +22,7 @@ config KVM
         select PREEMPT_NOTIFIERS
         select ANON_INODES
         select HAVE_KVM_CPU_RELAX_INTERCEPT
+        select HAVE_KVM_EVENTFD
         ---help---
           Support hosting paravirtualized guest machines using the SIE
           virtualization capability on the mainframe. This should work
diff --git a/arch/s390/kvm/Makefile b/arch/s390/kvm/Makefile
index 3975722bb19d..8fe9d65a4585 100644
--- a/arch/s390/kvm/Makefile
+++ b/arch/s390/kvm/Makefile
@@ -6,7 +6,7 @@
 # it under the terms of the GNU General Public License (version 2 only)
 # as published by the Free Software Foundation.
 
-common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o)
+common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o eventfd.o)
 
 ccflags-y := -Ivirt/kvm -Iarch/s390/kvm
 
diff --git a/arch/s390/kvm/diag.c b/arch/s390/kvm/diag.c
index a390687feb13..1c01a9912989 100644
--- a/arch/s390/kvm/diag.c
+++ b/arch/s390/kvm/diag.c
@@ -13,6 +13,7 @@
 
 #include <linux/kvm.h>
 #include <linux/kvm_host.h>
+#include <asm/virtio-ccw.h>
 #include "kvm-s390.h"
 #include "trace.h"
 #include "trace-s390.h"
@@ -104,6 +105,29 @@ static int __diag_ipl_functions(struct kvm_vcpu *vcpu)
         return -EREMOTE;
 }
 
+static int __diag_virtio_hypercall(struct kvm_vcpu *vcpu)
+{
+        int ret, idx;
+
+        /* No virtio-ccw notification? Get out quickly. */
+        if (!vcpu->kvm->arch.css_support ||
+            (vcpu->run->s.regs.gprs[1] != KVM_S390_VIRTIO_CCW_NOTIFY))
+                return -EOPNOTSUPP;
+
+        idx = srcu_read_lock(&vcpu->kvm->srcu);
+        /*
+         * The layout is as follows:
+         * - gpr 2 contains the subchannel id (passed as addr)
+         * - gpr 3 contains the virtqueue index (passed as datamatch)
+         */
+        ret = kvm_io_bus_write(vcpu->kvm, KVM_VIRTIO_CCW_NOTIFY_BUS,
+                                vcpu->run->s.regs.gprs[2],
+                                8, &vcpu->run->s.regs.gprs[3]);
+        srcu_read_unlock(&vcpu->kvm->srcu, idx);
+        /* kvm_io_bus_write returns -EOPNOTSUPP if it found no match. */
+        return ret < 0 ? ret : 0;
+}
+
 int kvm_s390_handle_diag(struct kvm_vcpu *vcpu)
 {
         int code = (vcpu->arch.sie_block->ipb & 0xfff0000) >> 16;
@@ -118,6 +142,8 @@ int kvm_s390_handle_diag(struct kvm_vcpu *vcpu)
                 return __diag_time_slice_end_directed(vcpu);
         case 0x308:
                 return __diag_ipl_functions(vcpu);
+        case 0x500:
+                return __diag_virtio_hypercall(vcpu);
         default:
                 return -EOPNOTSUPP;
         }
diff --git a/arch/s390/kvm/gaccess.h b/arch/s390/kvm/gaccess.h
index 4703f129e95e..302e0e52b009 100644
--- a/arch/s390/kvm/gaccess.h
+++ b/arch/s390/kvm/gaccess.h
@@ -18,369 +18,86 @@
 #include <asm/uaccess.h>
 #include "kvm-s390.h"
 
-static inline void __user *__guestaddr_to_user(struct kvm_vcpu *vcpu,
-                                               unsigned long guestaddr)
+static inline void __user *__gptr_to_uptr(struct kvm_vcpu *vcpu,
+                                          void __user *gptr,
+                                          int prefixing)
 {
         unsigned long prefix  = vcpu->arch.sie_block->prefix;
-
-        if (guestaddr < 2 * PAGE_SIZE)
-                guestaddr += prefix;
-        else if ((guestaddr >= prefix) && (guestaddr < prefix + 2 * PAGE_SIZE))
-                guestaddr -= prefix;
-
-        return (void __user *) gmap_fault(guestaddr, vcpu->arch.gmap);
-}
-
-static inline int get_guest_u64(struct kvm_vcpu *vcpu, unsigned long guestaddr,
-                                u64 *result)
-{
-        void __user *uptr = __guestaddr_to_user(vcpu, guestaddr);
-
-        BUG_ON(guestaddr & 7);
-
-        if (IS_ERR((void __force *) uptr))
-                return PTR_ERR((void __force *) uptr);
-
-        return get_user(*result, (unsigned long __user *) uptr);
-}
-
-static inline int get_guest_u32(struct kvm_vcpu *vcpu, unsigned long guestaddr,
-                                u32 *result)
-{
-        void __user *uptr = __guestaddr_to_user(vcpu, guestaddr);
-
-        BUG_ON(guestaddr & 3);
-
-        if (IS_ERR((void __force *) uptr))
-                return PTR_ERR((void __force *) uptr);
-
-        return get_user(*result, (u32 __user *) uptr);
-}
-
-static inline int get_guest_u16(struct kvm_vcpu *vcpu, unsigned long guestaddr,
-                                u16 *result)
-{
-        void __user *uptr = __guestaddr_to_user(vcpu, guestaddr);
-
-        BUG_ON(guestaddr & 1);
-
-        if (IS_ERR(uptr))
-                return PTR_ERR(uptr);
-
-        return get_user(*result, (u16 __user *) uptr);
-}
-
-static inline int get_guest_u8(struct kvm_vcpu *vcpu, unsigned long guestaddr,
-                               u8 *result)
-{
-        void __user *uptr = __guestaddr_to_user(vcpu, guestaddr);
-
-        if (IS_ERR((void __force *) uptr))
-                return PTR_ERR((void __force *) uptr);
-
-        return get_user(*result, (u8 __user *) uptr);
-}
-
-static inline int put_guest_u64(struct kvm_vcpu *vcpu, unsigned long guestaddr,
-                                u64 value)
-{
-        void __user *uptr = __guestaddr_to_user(vcpu, guestaddr);
-
-        BUG_ON(guestaddr & 7);
-
-        if (IS_ERR((void __force *) uptr))
-                return PTR_ERR((void __force *) uptr);
-
-        return put_user(value, (u64 __user *) uptr);
-}
-
-static inline int put_guest_u32(struct kvm_vcpu *vcpu, unsigned long guestaddr,
-                                u32 value)
-{
-        void __user *uptr = __guestaddr_to_user(vcpu, guestaddr);
-
-        BUG_ON(guestaddr & 3);
-
-        if (IS_ERR((void __force *) uptr))
-                return PTR_ERR((void __force *) uptr);
-
-        return put_user(value, (u32 __user *) uptr);
-}
-
-static inline int put_guest_u16(struct kvm_vcpu *vcpu, unsigned long guestaddr,
-                                u16 value)
-{
-        void __user *uptr = __guestaddr_to_user(vcpu, guestaddr);
-
-        BUG_ON(guestaddr & 1);
-
-        if (IS_ERR((void __force *) uptr))
-                return PTR_ERR((void __force *) uptr);
-
-        return put_user(value, (u16 __user *) uptr);
-}
-
-static inline int put_guest_u8(struct kvm_vcpu *vcpu, unsigned long guestaddr,
-                               u8 value)
-{
-        void __user *uptr = __guestaddr_to_user(vcpu, guestaddr);
-
-        if (IS_ERR((void __force *) uptr))
-                return PTR_ERR((void __force *) uptr);
-
-        return put_user(value, (u8 __user *) uptr);
-}
-
-
-static inline int __copy_to_guest_slow(struct kvm_vcpu *vcpu,
-                                       unsigned long guestdest,
-                                       void *from, unsigned long n)
-{
-        int rc;
-        unsigned long i;
-        u8 *data = from;
-
-        for (i = 0; i < n; i++) {
-                rc = put_guest_u8(vcpu, guestdest++, *(data++));
-                if (rc < 0)
-                        return rc;
+        unsigned long gaddr = (unsigned long) gptr;
+        unsigned long uaddr;
+
+        if (prefixing) {
+                if (gaddr < 2 * PAGE_SIZE)
+                        gaddr += prefix;
+                else if ((gaddr >= prefix) && (gaddr < prefix + 2 * PAGE_SIZE))
+                        gaddr -= prefix;
         }
-        return 0;
-}
-
-static inline int __copy_to_guest_fast(struct kvm_vcpu *vcpu,
-                                       unsigned long guestdest,
-                                       void *from, unsigned long n)
-{
-        int r;
+        uaddr = gmap_fault(gaddr, vcpu->arch.gmap);
+        if (IS_ERR_VALUE(uaddr))
+                uaddr = -EFAULT;
+        return (void __user *)uaddr;
+}
+
+#define get_guest(vcpu, x, gptr)                                \
+({                                                              \
+        __typeof__(gptr) __uptr = __gptr_to_uptr(vcpu, gptr, 1);\
+        int __mask = sizeof(__typeof__(*(gptr))) - 1;           \
+        int __ret = PTR_RET((void __force *)__uptr);            \
+                                                                \
+        if (!__ret) {                                           \
+                BUG_ON((unsigned long)__uptr & __mask);         \
+                __ret = get_user(x, __uptr);                    \
+        }                                                       \
+        __ret;                                                  \
+})
+
+#define put_guest(vcpu, x, gptr)                                \
+({                                                              \
+        __typeof__(gptr) __uptr = __gptr_to_uptr(vcpu, gptr, 1);\
+        int __mask = sizeof(__typeof__(*(gptr))) - 1;           \
+        int __ret = PTR_RET((void __force *)__uptr);            \
+                                                                \
+        if (!__ret) {                                           \
+                BUG_ON((unsigned long)__uptr & __mask);         \
+                __ret = put_user(x, __uptr);                    \
+        }                                                       \
+        __ret;                                                  \
+})
+
+static inline int __copy_guest(struct kvm_vcpu *vcpu, unsigned long to,
+                               unsigned long from, unsigned long len,
+                               int to_guest, int prefixing)
+{
+        unsigned long _len, rc;
         void __user *uptr;
-        unsigned long size;
-
-        if (guestdest + n < guestdest)
-                return -EFAULT;
-
-        /* simple case: all within one segment table entry? */
-        if ((guestdest & PMD_MASK) == ((guestdest+n) & PMD_MASK)) {
-                uptr = (void __user *) gmap_fault(guestdest, vcpu->arch.gmap);
-
-                if (IS_ERR((void __force *) uptr))
-                        return PTR_ERR((void __force *) uptr);
-
-                r = copy_to_user(uptr, from, n);
-
-                if (r)
-                        r = -EFAULT;
-
-                goto out;
-        }
-
-        /* copy first segment */
-        uptr = (void __user *)gmap_fault(guestdest, vcpu->arch.gmap);
-
-        if (IS_ERR((void __force *) uptr))
-                return PTR_ERR((void __force *) uptr);
 
-        size = PMD_SIZE - (guestdest & ~PMD_MASK);
-
-        r = copy_to_user(uptr, from, size);
-
-        if (r) {
-                r = -EFAULT;
-                goto out;
-        }
-        from += size;
-        n -= size;
-        guestdest += size;
-
-        /* copy full segments */
-        while (n >= PMD_SIZE) {
-                uptr = (void __user *)gmap_fault(guestdest, vcpu->arch.gmap);
-
-                if (IS_ERR((void __force *) uptr))
-                        return PTR_ERR((void __force *) uptr);
-
-                r = copy_to_user(uptr, from, PMD_SIZE);
-
-                if (r) {
-                        r = -EFAULT;
-                        goto out;
-                }
-                from += PMD_SIZE;
-                n -= PMD_SIZE;
-                guestdest += PMD_SIZE;
-        }
-
-        /* copy the tail segment */
-        if (n) {
-                uptr = (void __user *)gmap_fault(guestdest, vcpu->arch.gmap);
-
-                if (IS_ERR((void __force *) uptr))
-                        return PTR_ERR((void __force *) uptr);
-
-                r = copy_to_user(uptr, from, n);
-
-                if (r)
-                        r = -EFAULT;
-        }
-out:
-        return r;
-}
-
-static inline int copy_to_guest_absolute(struct kvm_vcpu *vcpu,
-                                         unsigned long guestdest,
-                                         void *from, unsigned long n)
-{
-        return __copy_to_guest_fast(vcpu, guestdest, from, n);
-}
-
-static inline int copy_to_guest(struct kvm_vcpu *vcpu, unsigned long guestdest,
-                                void *from, unsigned long n)
-{
-        unsigned long prefix  = vcpu->arch.sie_block->prefix;
-
-        if ((guestdest < 2 * PAGE_SIZE) && (guestdest + n > 2 * PAGE_SIZE))
-                goto slowpath;
-
-        if ((guestdest < prefix) && (guestdest + n > prefix))
-                goto slowpath;
-
-        if ((guestdest < prefix + 2 * PAGE_SIZE)
-            && (guestdest + n > prefix + 2 * PAGE_SIZE))
-                goto slowpath;
-
-        if (guestdest < 2 * PAGE_SIZE)
-                guestdest += prefix;
-        else if ((guestdest >= prefix) && (guestdest < prefix + 2 * PAGE_SIZE))
-                guestdest -= prefix;
-
-        return __copy_to_guest_fast(vcpu, guestdest, from, n);
-slowpath:
-        return __copy_to_guest_slow(vcpu, guestdest, from, n);
-}
-
-static inline int __copy_from_guest_slow(struct kvm_vcpu *vcpu, void *to,
-                                         unsigned long guestsrc,
-                                         unsigned long n)
-{
-        int rc;
-        unsigned long i;
-        u8 *data = to;
-
-        for (i = 0; i < n; i++) {
-                rc = get_guest_u8(vcpu, guestsrc++, data++);
-                if (rc < 0)
-                        return rc;
+        while (len) {
+                uptr = to_guest ? (void __user *)to : (void __user *)from;
+                uptr = __gptr_to_uptr(vcpu, uptr, prefixing);
+                if (IS_ERR((void __force *)uptr))
+                        return -EFAULT;
+                _len = PAGE_SIZE - ((unsigned long)uptr & (PAGE_SIZE - 1));
+                _len = min(_len, len);
+                if (to_guest)
+                        rc = copy_to_user((void __user *) uptr, (void *)from, _len);
+                else
+                        rc = copy_from_user((void *)to, (void __user *)uptr, _len);
+                if (rc)
+                        return -EFAULT;
+                len -= _len;
+                from += _len;
+                to += _len;
         }
         return 0;
 }
 
-static inline int __copy_from_guest_fast(struct kvm_vcpu *vcpu, void *to,
-                                         unsigned long guestsrc,
-                                         unsigned long n)
-{
-        int r;
-        void __user *uptr;
-        unsigned long size;
-
-        if (guestsrc + n < guestsrc)
-                return -EFAULT;
-
-        /* simple case: all within one segment table entry? */
-        if ((guestsrc & PMD_MASK) == ((guestsrc+n) & PMD_MASK)) {
-                uptr = (void __user *) gmap_fault(guestsrc, vcpu->arch.gmap);
-
-                if (IS_ERR((void __force *) uptr))
-                        return PTR_ERR((void __force *) uptr);
-
-                r = copy_from_user(to, uptr, n);
-
-                if (r)
-                        r = -EFAULT;
-
-                goto out;
-        }
-
-        /* copy first segment */
-        uptr = (void __user *)gmap_fault(guestsrc, vcpu->arch.gmap);
-
-        if (IS_ERR((void __force *) uptr))
-                return PTR_ERR((void __force *) uptr);
-
-        size = PMD_SIZE - (guestsrc & ~PMD_MASK);
-
-        r = copy_from_user(to, uptr, size);
-
-        if (r) {
-                r = -EFAULT;
-                goto out;
-        }
-        to += size;
-        n -= size;
-        guestsrc += size;
-
-        /* copy full segments */
-        while (n >= PMD_SIZE) {
-                uptr = (void __user *)gmap_fault(guestsrc, vcpu->arch.gmap);
-
-                if (IS_ERR((void __force *) uptr))
-                        return PTR_ERR((void __force *) uptr);
-
-                r = copy_from_user(to, uptr, PMD_SIZE);
-
-                if (r) {
-                        r = -EFAULT;
-                        goto out;
-                }
-                to += PMD_SIZE;
-                n -= PMD_SIZE;
-                guestsrc += PMD_SIZE;
-        }
-
-        /* copy the tail segment */
-        if (n) {
-                uptr = (void __user *)gmap_fault(guestsrc, vcpu->arch.gmap);
-
-                if (IS_ERR((void __force *) uptr))
-                        return PTR_ERR((void __force *) uptr);
-
-                r = copy_from_user(to, uptr, n);
-
-                if (r)
-                        r = -EFAULT;
-        }
-out:
-        return r;
-}
-
-static inline int copy_from_guest_absolute(struct kvm_vcpu *vcpu, void *to,
-                                           unsigned long guestsrc,
-                                           unsigned long n)
-{
-        return __copy_from_guest_fast(vcpu, to, guestsrc, n);
-}
-
-static inline int copy_from_guest(struct kvm_vcpu *vcpu, void *to,
-                                  unsigned long guestsrc, unsigned long n)
-{
-        unsigned long prefix  = vcpu->arch.sie_block->prefix;
-
-        if ((guestsrc < 2 * PAGE_SIZE) && (guestsrc + n > 2 * PAGE_SIZE))
-                goto slowpath;
+#define copy_to_guest(vcpu, to, from, size) \
+        __copy_guest(vcpu, to, (unsigned long)from, size, 1, 1)
+#define copy_from_guest(vcpu, to, from, size) \
+        __copy_guest(vcpu, (unsigned long)to, from, size, 0, 1)
+#define copy_to_guest_absolute(vcpu, to, from, size) \
+        __copy_guest(vcpu, to, (unsigned long)from, size, 1, 0)
+#define copy_from_guest_absolute(vcpu, to, from, size) \
+        __copy_guest(vcpu, (unsigned long)to, from, size, 0, 0)
 
-        if ((guestsrc < prefix) && (guestsrc + n > prefix))
-                goto slowpath;
-
-        if ((guestsrc < prefix + 2 * PAGE_SIZE)
-            && (guestsrc + n > prefix + 2 * PAGE_SIZE))
-                goto slowpath;
-
-        if (guestsrc < 2 * PAGE_SIZE)
-                guestsrc += prefix;
-        else if ((guestsrc >= prefix) && (guestsrc < prefix + 2 * PAGE_SIZE))
-                guestsrc -= prefix;
-
-        return __copy_from_guest_fast(vcpu, to, guestsrc, n);
-slowpath:
-        return __copy_from_guest_slow(vcpu, to, guestsrc, n);
-}
-#endif
+#endif /* __KVM_S390_GACCESS_H */
diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c
index f26ff1e31bdb..b7d1b2edeeb3 100644
--- a/arch/s390/kvm/intercept.c
+++ b/arch/s390/kvm/intercept.c
@@ -43,12 +43,10 @@ static int handle_lctlg(struct kvm_vcpu *vcpu)
         trace_kvm_s390_handle_lctl(vcpu, 1, reg1, reg3, useraddr);
 
         do {
-                rc = get_guest_u64(vcpu, useraddr,
-                                   &vcpu->arch.sie_block->gcr[reg]);
-                if (rc == -EFAULT) {
-                        kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
-                        break;
-                }
+                rc = get_guest(vcpu, vcpu->arch.sie_block->gcr[reg],
+                               (u64 __user *) useraddr);
+                if (rc)
+                        return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
                 useraddr += 8;
                 if (reg == reg3)
                         break;
@@ -78,11 +76,9 @@ static int handle_lctl(struct kvm_vcpu *vcpu)
 
         reg = reg1;
         do {
-                rc = get_guest_u32(vcpu, useraddr, &val);
-                if (rc == -EFAULT) {
-                        kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
-                        break;
-                }
+                rc = get_guest(vcpu, val, (u32 __user *) useraddr);
+                if (rc)
+                        return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
                 vcpu->arch.sie_block->gcr[reg] &= 0xffffffff00000000ul;
                 vcpu->arch.sie_block->gcr[reg] |= val;
                 useraddr += 4;
diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c
index 37116a77cb4b..5c948177529e 100644
--- a/arch/s390/kvm/interrupt.c
+++ b/arch/s390/kvm/interrupt.c
@@ -180,7 +180,7 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
                                    struct kvm_s390_interrupt_info *inti)
 {
         const unsigned short table[] = { 2, 4, 4, 6 };
-        int rc, exception = 0;
+        int rc = 0;
 
         switch (inti->type) {
         case KVM_S390_INT_EMERGENCY:
@@ -188,74 +188,41 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
                 vcpu->stat.deliver_emergency_signal++;
                 trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type,
                                                  inti->emerg.code, 0);
-                rc = put_guest_u16(vcpu, __LC_EXT_INT_CODE, 0x1201);
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = put_guest_u16(vcpu, __LC_EXT_CPU_ADDR, inti->emerg.code);
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = copy_to_guest(vcpu, __LC_EXT_OLD_PSW,
-                         &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
-                        __LC_EXT_NEW_PSW, sizeof(psw_t));
-                if (rc == -EFAULT)
-                        exception = 1;
+                rc  = put_guest(vcpu, 0x1201, (u16 __user *)__LC_EXT_INT_CODE);
+                rc |= put_guest(vcpu, inti->emerg.code,
+                                (u16 __user *)__LC_EXT_CPU_ADDR);
+                rc |= copy_to_guest(vcpu, __LC_EXT_OLD_PSW,
+                                    &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
+                rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
+                                      __LC_EXT_NEW_PSW, sizeof(psw_t));
                 break;
-
         case KVM_S390_INT_EXTERNAL_CALL:
                 VCPU_EVENT(vcpu, 4, "%s", "interrupt: sigp ext call");
                 vcpu->stat.deliver_external_call++;
                 trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type,
                                                  inti->extcall.code, 0);
-                rc = put_guest_u16(vcpu, __LC_EXT_INT_CODE, 0x1202);
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = put_guest_u16(vcpu, __LC_EXT_CPU_ADDR, inti->extcall.code);
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = copy_to_guest(vcpu, __LC_EXT_OLD_PSW,
-                         &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
-                        __LC_EXT_NEW_PSW, sizeof(psw_t));
-                if (rc == -EFAULT)
-                        exception = 1;
+                rc  = put_guest(vcpu, 0x1202, (u16 __user *)__LC_EXT_INT_CODE);
+                rc |= put_guest(vcpu, inti->extcall.code,
+                                (u16 __user *)__LC_EXT_CPU_ADDR);
+                rc |= copy_to_guest(vcpu, __LC_EXT_OLD_PSW,
+                                    &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
+                rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
+                                      __LC_EXT_NEW_PSW, sizeof(psw_t));
                 break;
-
         case KVM_S390_INT_SERVICE:
                 VCPU_EVENT(vcpu, 4, "interrupt: sclp parm:%x",
                            inti->ext.ext_params);
                 vcpu->stat.deliver_service_signal++;
                 trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type,
                                                  inti->ext.ext_params, 0);
-                rc = put_guest_u16(vcpu, __LC_EXT_INT_CODE, 0x2401);
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = copy_to_guest(vcpu, __LC_EXT_OLD_PSW,
-                         &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
-                        __LC_EXT_NEW_PSW, sizeof(psw_t));
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = put_guest_u32(vcpu, __LC_EXT_PARAMS, inti->ext.ext_params);
-                if (rc == -EFAULT)
-                        exception = 1;
+                rc  = put_guest(vcpu, 0x2401, (u16 __user *)__LC_EXT_INT_CODE);
+                rc |= copy_to_guest(vcpu, __LC_EXT_OLD_PSW,
+                                    &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
+                rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
+                                      __LC_EXT_NEW_PSW, sizeof(psw_t));
+                rc |= put_guest(vcpu, inti->ext.ext_params,
+                                (u32 __user *)__LC_EXT_PARAMS);
                 break;
-
         case KVM_S390_INT_VIRTIO:
                 VCPU_EVENT(vcpu, 4, "interrupt: virtio parm:%x,parm64:%llx",
                            inti->ext.ext_params, inti->ext.ext_params2);
@@ -263,34 +230,17 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
                 trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type,
                                                  inti->ext.ext_params,
                                                  inti->ext.ext_params2);
-                rc = put_guest_u16(vcpu, __LC_EXT_INT_CODE, 0x2603);
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = put_guest_u16(vcpu, __LC_EXT_CPU_ADDR, 0x0d00);
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = copy_to_guest(vcpu, __LC_EXT_OLD_PSW,
-                         &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
-                        __LC_EXT_NEW_PSW, sizeof(psw_t));
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = put_guest_u32(vcpu, __LC_EXT_PARAMS, inti->ext.ext_params);
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = put_guest_u64(vcpu, __LC_EXT_PARAMS2,
-                                   inti->ext.ext_params2);
-                if (rc == -EFAULT)
-                        exception = 1;
+                rc  = put_guest(vcpu, 0x2603, (u16 __user *)__LC_EXT_INT_CODE);
+                rc |= put_guest(vcpu, 0x0d00, (u16 __user *)__LC_EXT_CPU_ADDR);
+                rc |= copy_to_guest(vcpu, __LC_EXT_OLD_PSW,
+                                    &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
+                rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
+                                      __LC_EXT_NEW_PSW, sizeof(psw_t));
+                rc |= put_guest(vcpu, inti->ext.ext_params,
+                                (u32 __user *)__LC_EXT_PARAMS);
+                rc |= put_guest(vcpu, inti->ext.ext_params2,
+                                (u64 __user *)__LC_EXT_PARAMS2);
                 break;
-
         case KVM_S390_SIGP_STOP:
                 VCPU_EVENT(vcpu, 4, "%s", "interrupt: cpu stop");
                 vcpu->stat.deliver_stop_signal++;
@@ -313,18 +263,14 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
                 vcpu->stat.deliver_restart_signal++;
                 trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type,
                                                  0, 0);
-                rc = copy_to_guest(vcpu, offsetof(struct _lowcore,
-                  restart_old_psw), &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
-                        offsetof(struct _lowcore, restart_psw), sizeof(psw_t));
-                if (rc == -EFAULT)
-                        exception = 1;
+                rc  = copy_to_guest(vcpu,
+                                    offsetof(struct _lowcore, restart_old_psw),
+                                    &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
+                rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
+                                      offsetof(struct _lowcore, restart_psw),
+                                      sizeof(psw_t));
                 atomic_clear_mask(CPUSTAT_STOPPED, &vcpu->arch.sie_block->cpuflags);
                 break;
-
         case KVM_S390_PROGRAM_INT:
                 VCPU_EVENT(vcpu, 4, "interrupt: pgm check code:%x, ilc:%x",
                            inti->pgm.code,
@@ -332,24 +278,13 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
                 vcpu->stat.deliver_program_int++;
                 trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type,
                                                  inti->pgm.code, 0);
-                rc = put_guest_u16(vcpu, __LC_PGM_INT_CODE, inti->pgm.code);
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = put_guest_u16(vcpu, __LC_PGM_ILC,
-                        table[vcpu->arch.sie_block->ipa >> 14]);
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = copy_to_guest(vcpu, __LC_PGM_OLD_PSW,
-                         &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
-                        __LC_PGM_NEW_PSW, sizeof(psw_t));
-                if (rc == -EFAULT)
-                        exception = 1;
+                rc  = put_guest(vcpu, inti->pgm.code, (u16 __user *)__LC_PGM_INT_CODE);
+                rc |= put_guest(vcpu, table[vcpu->arch.sie_block->ipa >> 14],
+                                (u16 __user *)__LC_PGM_ILC);
+                rc |= copy_to_guest(vcpu, __LC_PGM_OLD_PSW,
+                                    &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
+                rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
+                                      __LC_PGM_NEW_PSW, sizeof(psw_t));
                 break;
 
         case KVM_S390_MCHK:
@@ -358,24 +293,13 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
                 trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type,
                                                  inti->mchk.cr14,
                                                  inti->mchk.mcic);
-                rc = kvm_s390_vcpu_store_status(vcpu,
-                                                KVM_S390_STORE_STATUS_PREFIXED);
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = put_guest_u64(vcpu, __LC_MCCK_CODE, inti->mchk.mcic);
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = copy_to_guest(vcpu, __LC_MCK_OLD_PSW,
-                                   &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
-                                     __LC_MCK_NEW_PSW, sizeof(psw_t));
-                if (rc == -EFAULT)
-                        exception = 1;
+                rc  = kvm_s390_vcpu_store_status(vcpu,
+                                                 KVM_S390_STORE_STATUS_PREFIXED);
+                rc |= put_guest(vcpu, inti->mchk.mcic, (u64 __user *) __LC_MCCK_CODE);
+                rc |= copy_to_guest(vcpu, __LC_MCK_OLD_PSW,
+                                    &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
+                rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
+                                      __LC_MCK_NEW_PSW, sizeof(psw_t));
                 break;
 
         case KVM_S390_INT_IO_MIN...KVM_S390_INT_IO_MAX:
@@ -388,67 +312,44 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
                 vcpu->stat.deliver_io_int++;
                 trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type,
                                                  param0, param1);
-                rc = put_guest_u16(vcpu, __LC_SUBCHANNEL_ID,
-                                   inti->io.subchannel_id);
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = put_guest_u16(vcpu, __LC_SUBCHANNEL_NR,
-                                   inti->io.subchannel_nr);
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = put_guest_u32(vcpu, __LC_IO_INT_PARM,
-                                   inti->io.io_int_parm);
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = put_guest_u32(vcpu, __LC_IO_INT_WORD,
-                                   inti->io.io_int_word);
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = copy_to_guest(vcpu, __LC_IO_OLD_PSW,
-                                   &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
-                if (rc == -EFAULT)
-                        exception = 1;
-
-                rc = copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
-                                     __LC_IO_NEW_PSW, sizeof(psw_t));
-                if (rc == -EFAULT)
-                        exception = 1;
+                rc  = put_guest(vcpu, inti->io.subchannel_id,
+                                (u16 __user *) __LC_SUBCHANNEL_ID);
+                rc |= put_guest(vcpu, inti->io.subchannel_nr,
+                                (u16 __user *) __LC_SUBCHANNEL_NR);
+                rc |= put_guest(vcpu, inti->io.io_int_parm,
+                                (u32 __user *) __LC_IO_INT_PARM);
+                rc |= put_guest(vcpu, inti->io.io_int_word,
+                                (u32 __user *) __LC_IO_INT_WORD);
+                rc |= copy_to_guest(vcpu, __LC_IO_OLD_PSW,
+                                    &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
+                rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
+                                      __LC_IO_NEW_PSW, sizeof(psw_t));
                 break;
         }
         default:
                 BUG();
         }
-        if (exception) {
+        if (rc) {
                 printk("kvm: The guest lowcore is not mapped during interrupt "
-                        "delivery, killing userspace\n");
+                       "delivery, killing userspace\n");
                 do_exit(SIGKILL);
         }
 }
 
 static int __try_deliver_ckc_interrupt(struct kvm_vcpu *vcpu)
 {
-        int rc, exception = 0;
+        int rc;
 
         if (psw_extint_disabled(vcpu))
                 return 0;
         if (!(vcpu->arch.sie_block->gcr[0] & 0x800ul))
                 return 0;
-        rc = put_guest_u16(vcpu, __LC_EXT_INT_CODE, 0x1004);
-        if (rc == -EFAULT)
-                exception = 1;
-        rc = copy_to_guest(vcpu, __LC_EXT_OLD_PSW,
-                 &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
-        if (rc == -EFAULT)
-                exception = 1;
-        rc = copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
-                __LC_EXT_NEW_PSW, sizeof(psw_t));
-        if (rc == -EFAULT)
-                exception = 1;
-        if (exception) {
+        rc  = put_guest(vcpu, 0x1004, (u16 __user *)__LC_EXT_INT_CODE);
+        rc |= copy_to_guest(vcpu, __LC_EXT_OLD_PSW,
+                            &vcpu->arch.sie_block->gpsw, sizeof(psw_t));
+        rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw,
+                              __LC_EXT_NEW_PSW, sizeof(psw_t));
+        if (rc) {
                 printk("kvm: The guest lowcore is not mapped during interrupt "
                         "delivery, killing userspace\n");
                 do_exit(SIGKILL);
diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c
index 4cf35a0a79e7..c1c7c683fa26 100644
--- a/arch/s390/kvm/kvm-s390.c
+++ b/arch/s390/kvm/kvm-s390.c
@@ -142,12 +142,16 @@ int kvm_dev_ioctl_check_extension(long ext)
         case KVM_CAP_ONE_REG:
         case KVM_CAP_ENABLE_CAP:
         case KVM_CAP_S390_CSS_SUPPORT:
+        case KVM_CAP_IOEVENTFD:
                 r = 1;
                 break;
         case KVM_CAP_NR_VCPUS:
         case KVM_CAP_MAX_VCPUS:
                 r = KVM_MAX_VCPUS;
                 break;
+        case KVM_CAP_NR_MEMSLOTS:
+                r = KVM_USER_MEM_SLOTS;
+                break;
         case KVM_CAP_S390_COW:
                 r = MACHINE_HAS_ESOP;
                 break;
@@ -632,8 +636,7 @@ static int __vcpu_run(struct kvm_vcpu *vcpu)
                 } else {
                         VCPU_EVENT(vcpu, 3, "%s", "fault in sie instruction");
                         trace_kvm_s390_sie_fault(vcpu);
-                        kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
-                        rc = 0;
+                        rc = kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
                 }
         }
         VCPU_EVENT(vcpu, 6, "exit sie icptcode %d",
@@ -974,22 +977,13 @@ int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
 /* Section: memory related */
 int kvm_arch_prepare_memory_region(struct kvm *kvm,
                                    struct kvm_memory_slot *memslot,
-                                   struct kvm_memory_slot old,
                                    struct kvm_userspace_memory_region *mem,
-                                   bool user_alloc)
+                                   enum kvm_mr_change change)
 {
-        /* A few sanity checks. We can have exactly one memory slot which has
-           to start at guest virtual zero and which has to be located at a
-           page boundary in userland and which has to end at a page boundary.
-           The memory in userland is ok to be fragmented into various different
-           vmas. It is okay to mmap() and munmap() stuff in this slot after
-           doing this call at any time */
-
-        if (mem->slot)
-                return -EINVAL;
-
-        if (mem->guest_phys_addr)
-                return -EINVAL;
+        /* A few sanity checks. We can have memory slots which have to be
+           located/ended at a segment boundary (1MB). The memory in userland is
+           ok to be fragmented into various different vmas. It is okay to mmap()
+           and munmap() stuff in this slot after doing this call at any time */
 
         if (mem->userspace_addr & 0xffffful)
                 return -EINVAL;
@@ -997,19 +991,26 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
         if (mem->memory_size & 0xffffful)
                 return -EINVAL;
 
-        if (!user_alloc)
-                return -EINVAL;
-
         return 0;
 }
 
 void kvm_arch_commit_memory_region(struct kvm *kvm,
                                 struct kvm_userspace_memory_region *mem,
-                                struct kvm_memory_slot old,
-                                bool user_alloc)
+                                const struct kvm_memory_slot *old,
+                                enum kvm_mr_change change)
 {
         int rc;
 
+        /* If the basics of the memslot do not change, we do not want
+         * to update the gmap. Every update causes several unnecessary
+         * segment translation exceptions. This is usually handled just
+         * fine by the normal fault handler + gmap, but it will also
+         * cause faults on the prefix page of running guest CPUs.
+         */
+        if (old->userspace_addr == mem->userspace_addr &&
+            old->base_gfn * PAGE_SIZE == mem->guest_phys_addr &&
+            old->npages * PAGE_SIZE == mem->memory_size)
+                return;
 
         rc = gmap_map_segment(kvm->arch.gmap, mem->userspace_addr,
                 mem->guest_phys_addr, mem->memory_size);
diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h
index 4d89d64a8161..efc14f687265 100644
--- a/arch/s390/kvm/kvm-s390.h
+++ b/arch/s390/kvm/kvm-s390.h
@@ -110,12 +110,12 @@ enum hrtimer_restart kvm_s390_idle_wakeup(struct hrtimer *timer);
 void kvm_s390_tasklet(unsigned long parm);
 void kvm_s390_deliver_pending_interrupts(struct kvm_vcpu *vcpu);
 void kvm_s390_deliver_pending_machine_checks(struct kvm_vcpu *vcpu);
-int kvm_s390_inject_vm(struct kvm *kvm,
-                struct kvm_s390_interrupt *s390int);
-int kvm_s390_inject_vcpu(struct kvm_vcpu *vcpu,
-                struct kvm_s390_interrupt *s390int);
-int kvm_s390_inject_program_int(struct kvm_vcpu *vcpu, u16 code);
-int kvm_s390_inject_sigp_stop(struct kvm_vcpu *vcpu, int action);
+int __must_check kvm_s390_inject_vm(struct kvm *kvm,
+                                    struct kvm_s390_interrupt *s390int);
+int __must_check kvm_s390_inject_vcpu(struct kvm_vcpu *vcpu,
+                                      struct kvm_s390_interrupt *s390int);
+int __must_check kvm_s390_inject_program_int(struct kvm_vcpu *vcpu, u16 code);
+int __must_check kvm_s390_inject_sigp_stop(struct kvm_vcpu *vcpu, int action);
 struct kvm_s390_interrupt_info *kvm_s390_get_io_int(struct kvm *kvm,
                                                     u64 cr6, u64 schid);
 
diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c
index 0ef9894606e5..6bbd7b5a0bbe 100644
--- a/arch/s390/kvm/priv.c
+++ b/arch/s390/kvm/priv.c
@@ -14,6 +14,8 @@
 #include <linux/kvm.h>
 #include <linux/gfp.h>
 #include <linux/errno.h>
+#include <linux/compat.h>
+#include <asm/asm-offsets.h>
 #include <asm/current.h>
 #include <asm/debug.h>
 #include <asm/ebcdic.h>
@@ -35,31 +37,24 @@ static int handle_set_prefix(struct kvm_vcpu *vcpu)
         operand2 = kvm_s390_get_base_disp_s(vcpu);
 
         /* must be word boundary */
-        if (operand2 & 3) {
-                kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
-                goto out;
-        }
+        if (operand2 & 3)
+                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
 
         /* get the value */
-        if (get_guest_u32(vcpu, operand2, &address)) {
-                kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
-                goto out;
-        }
+        if (get_guest(vcpu, address, (u32 __user *) operand2))
+                return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
 
         address = address & 0x7fffe000u;
 
         /* make sure that the new value is valid memory */
         if (copy_from_guest_absolute(vcpu, &tmp, address, 1) ||
-           (copy_from_guest_absolute(vcpu, &tmp, address + PAGE_SIZE, 1))) {
-                kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
-                goto out;
-        }
+           (copy_from_guest_absolute(vcpu, &tmp, address + PAGE_SIZE, 1)))
+                return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
 
         kvm_s390_set_prefix(vcpu, address);
 
         VCPU_EVENT(vcpu, 5, "setting prefix to %x", address);
         trace_kvm_s390_handle_prefix(vcpu, 1, address);
-out:
         return 0;
 }
 
@@ -73,49 +68,37 @@ static int handle_store_prefix(struct kvm_vcpu *vcpu)
         operand2 = kvm_s390_get_base_disp_s(vcpu);
 
         /* must be word boundary */
-        if (operand2 & 3) {
-                kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
-                goto out;
-        }
+        if (operand2 & 3)
+                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
 
         address = vcpu->arch.sie_block->prefix;
         address = address & 0x7fffe000u;
 
         /* get the value */
-        if (put_guest_u32(vcpu, operand2, address)) {
-                kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
-                goto out;
-        }
+        if (put_guest(vcpu, address, (u32 __user *)operand2))
+                return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
 
         VCPU_EVENT(vcpu, 5, "storing prefix to %x", address);
         trace_kvm_s390_handle_prefix(vcpu, 0, address);
-out:
         return 0;
 }
 
 static int handle_store_cpu_address(struct kvm_vcpu *vcpu)
 {
         u64 useraddr;
-        int rc;
 
         vcpu->stat.instruction_stap++;
 
         useraddr = kvm_s390_get_base_disp_s(vcpu);
 
-        if (useraddr & 1) {
-                kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
-                goto out;
-        }
+        if (useraddr & 1)
+                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
 
-        rc = put_guest_u16(vcpu, useraddr, vcpu->vcpu_id);
-        if (rc == -EFAULT) {
-                kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
-                goto out;
-        }
+        if (put_guest(vcpu, vcpu->vcpu_id, (u16 __user *)useraddr))
+                return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
 
         VCPU_EVENT(vcpu, 5, "storing cpu address to %llx", useraddr);
         trace_kvm_s390_handle_stap(vcpu, useraddr);
-out:
         return 0;
 }
 
@@ -129,36 +112,38 @@ static int handle_skey(struct kvm_vcpu *vcpu)
 
 static int handle_tpi(struct kvm_vcpu *vcpu)
 {
-        u64 addr;
         struct kvm_s390_interrupt_info *inti;
+        u64 addr;
         int cc;
 
         addr = kvm_s390_get_base_disp_s(vcpu);
-
+        if (addr & 3)
+                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
+        cc = 0;
         inti = kvm_s390_get_io_int(vcpu->kvm, vcpu->run->s.regs.crs[6], 0);
-        if (inti) {
-                if (addr) {
-                        /*
-                         * Store the two-word I/O interruption code into the
-                         * provided area.
-                         */
-                        put_guest_u16(vcpu, addr, inti->io.subchannel_id);
-                        put_guest_u16(vcpu, addr + 2, inti->io.subchannel_nr);
-                        put_guest_u32(vcpu, addr + 4, inti->io.io_int_parm);
-                } else {
-                        /*
-                         * Store the three-word I/O interruption code into
-                         * the appropriate lowcore area.
-                         */
-                        put_guest_u16(vcpu, 184, inti->io.subchannel_id);
-                        put_guest_u16(vcpu, 186, inti->io.subchannel_nr);
-                        put_guest_u32(vcpu, 188, inti->io.io_int_parm);
-                        put_guest_u32(vcpu, 192, inti->io.io_int_word);
-                }
-                cc = 1;
-        } else
-                cc = 0;
+        if (!inti)
+                goto no_interrupt;
+        cc = 1;
+        if (addr) {
+                /*
+                 * Store the two-word I/O interruption code into the
+                 * provided area.
+                 */
+                put_guest(vcpu, inti->io.subchannel_id, (u16 __user *) addr);
+                put_guest(vcpu, inti->io.subchannel_nr, (u16 __user *) (addr + 2));
+                put_guest(vcpu, inti->io.io_int_parm, (u32 __user *) (addr + 4));
+        } else {
+                /*
+                 * Store the three-word I/O interruption code into
+                 * the appropriate lowcore area.
+                 */
+                put_guest(vcpu, inti->io.subchannel_id, (u16 __user *) __LC_SUBCHANNEL_ID);
+                put_guest(vcpu, inti->io.subchannel_nr, (u16 __user *) __LC_SUBCHANNEL_NR);
+                put_guest(vcpu, inti->io.io_int_parm, (u32 __user *) __LC_IO_INT_PARM);
+                put_guest(vcpu, inti->io.io_int_word, (u32 __user *) __LC_IO_INT_WORD);
+        }
         kfree(inti);
+no_interrupt:
         /* Set condition code and we're done. */
         vcpu->arch.sie_block->gpsw.mask &= ~(3ul << 44);
         vcpu->arch.sie_block->gpsw.mask |= (cc & 3ul) << 44;
@@ -230,13 +215,10 @@ static int handle_stfl(struct kvm_vcpu *vcpu)
 
         rc = copy_to_guest(vcpu, offsetof(struct _lowcore, stfl_fac_list),
                            &facility_list, sizeof(facility_list));
-        if (rc == -EFAULT)
-                kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
-        else {
-                VCPU_EVENT(vcpu, 5, "store facility list value %x",
-                           facility_list);
-                trace_kvm_s390_handle_stfl(vcpu, facility_list);
-        }
+        if (rc)
+                return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
+        VCPU_EVENT(vcpu, 5, "store facility list value %x", facility_list);
+        trace_kvm_s390_handle_stfl(vcpu, facility_list);
         return 0;
 }
 
@@ -249,112 +231,80 @@ static void handle_new_psw(struct kvm_vcpu *vcpu)
 
 #define PSW_MASK_ADDR_MODE (PSW_MASK_EA | PSW_MASK_BA)
 #define PSW_MASK_UNASSIGNED 0xb80800fe7fffffffUL
-#define PSW_ADDR_24 0x00000000000fffffUL
+#define PSW_ADDR_24 0x0000000000ffffffUL
 #define PSW_ADDR_31 0x000000007fffffffUL
 
+static int is_valid_psw(psw_t *psw) {
+        if (psw->mask & PSW_MASK_UNASSIGNED)
+                return 0;
+        if ((psw->mask & PSW_MASK_ADDR_MODE) == PSW_MASK_BA) {
+                if (psw->addr & ~PSW_ADDR_31)
+                        return 0;
+        }
+        if (!(psw->mask & PSW_MASK_ADDR_MODE) && (psw->addr & ~PSW_ADDR_24))
+                return 0;
+        if ((psw->mask & PSW_MASK_ADDR_MODE) ==  PSW_MASK_EA)
+                return 0;
+        return 1;
+}
+
 int kvm_s390_handle_lpsw(struct kvm_vcpu *vcpu)
 {
-        u64 addr;
+        psw_t *gpsw = &vcpu->arch.sie_block->gpsw;
         psw_compat_t new_psw;
+        u64 addr;
 
-        if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
+        if (gpsw->mask & PSW_MASK_PSTATE)
                 return kvm_s390_inject_program_int(vcpu,
                                                    PGM_PRIVILEGED_OPERATION);
-
         addr = kvm_s390_get_base_disp_s(vcpu);
-
-        if (addr & 7) {
-                kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
-                goto out;
-        }
-
-        if (copy_from_guest(vcpu, &new_psw, addr, sizeof(new_psw))) {
-                kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
-                goto out;
-        }
-
-        if (!(new_psw.mask & PSW32_MASK_BASE)) {
-                kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
-                goto out;
-        }
-
-        vcpu->arch.sie_block->gpsw.mask =
-                (new_psw.mask & ~PSW32_MASK_BASE) << 32;
-        vcpu->arch.sie_block->gpsw.addr = new_psw.addr;
-
-        if ((vcpu->arch.sie_block->gpsw.mask & PSW_MASK_UNASSIGNED) ||
-            (!(vcpu->arch.sie_block->gpsw.mask & PSW_MASK_ADDR_MODE) &&
-             (vcpu->arch.sie_block->gpsw.addr & ~PSW_ADDR_24)) ||
-            ((vcpu->arch.sie_block->gpsw.mask & PSW_MASK_ADDR_MODE) ==
-             PSW_MASK_EA)) {
-                kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
-                goto out;
-        }
-
+        if (addr & 7)
+                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
+        if (copy_from_guest(vcpu, &new_psw, addr, sizeof(new_psw)))
+                return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
+        if (!(new_psw.mask & PSW32_MASK_BASE))
+                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
+        gpsw->mask = (new_psw.mask & ~PSW32_MASK_BASE) << 32;
+        gpsw->mask |= new_psw.addr & PSW32_ADDR_AMODE;
+        gpsw->addr = new_psw.addr & ~PSW32_ADDR_AMODE;
+        if (!is_valid_psw(gpsw))
+                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
         handle_new_psw(vcpu);
-out:
         return 0;
 }
 
 static int handle_lpswe(struct kvm_vcpu *vcpu)
 {
-        u64 addr;
         psw_t new_psw;
+        u64 addr;
 
         addr = kvm_s390_get_base_disp_s(vcpu);
-
-        if (addr & 7) {
-                kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
-                goto out;
-        }
-
-        if (copy_from_guest(vcpu, &new_psw, addr, sizeof(new_psw))) {
-                kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
-                goto out;
-        }
-
-        vcpu->arch.sie_block->gpsw.mask = new_psw.mask;
-        vcpu->arch.sie_block->gpsw.addr = new_psw.addr;
-
-        if ((vcpu->arch.sie_block->gpsw.mask & PSW_MASK_UNASSIGNED) ||
-            (((vcpu->arch.sie_block->gpsw.mask & PSW_MASK_ADDR_MODE) ==
-              PSW_MASK_BA) &&
-             (vcpu->arch.sie_block->gpsw.addr & ~PSW_ADDR_31)) ||
-            (!(vcpu->arch.sie_block->gpsw.mask & PSW_MASK_ADDR_MODE) &&
-             (vcpu->arch.sie_block->gpsw.addr & ~PSW_ADDR_24)) ||
-            ((vcpu->arch.sie_block->gpsw.mask & PSW_MASK_ADDR_MODE) ==
-             PSW_MASK_EA)) {
-                kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
-                goto out;
-        }
-
+        if (addr & 7)
+                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
+        if (copy_from_guest(vcpu, &new_psw, addr, sizeof(new_psw)))
+                return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
+        vcpu->arch.sie_block->gpsw = new_psw;
+        if (!is_valid_psw(&vcpu->arch.sie_block->gpsw))
+                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
         handle_new_psw(vcpu);
-out:
         return 0;
 }
 
 static int handle_stidp(struct kvm_vcpu *vcpu)
 {
         u64 operand2;
-        int rc;
 
         vcpu->stat.instruction_stidp++;
 
         operand2 = kvm_s390_get_base_disp_s(vcpu);
 
-        if (operand2 & 7) {
-                kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
-                goto out;
-        }
+        if (operand2 & 7)
+                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
 
-        rc = put_guest_u64(vcpu, operand2, vcpu->arch.stidp_data);
-        if (rc == -EFAULT) {
-                kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
-                goto out;
-        }
+        if (put_guest(vcpu, vcpu->arch.stidp_data, (u64 __user *)operand2))
+                return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
 
         VCPU_EVENT(vcpu, 5, "%s", "store cpu id");
-out:
         return 0;
 }
 
@@ -394,8 +344,9 @@ static int handle_stsi(struct kvm_vcpu *vcpu)
         int fc = (vcpu->run->s.regs.gprs[0] & 0xf0000000) >> 28;
         int sel1 = vcpu->run->s.regs.gprs[0] & 0xff;
         int sel2 = vcpu->run->s.regs.gprs[1] & 0xffff;
+        unsigned long mem = 0;
         u64 operand2;
-        unsigned long mem;
+        int rc = 0;
 
         vcpu->stat.instruction_stsi++;
         VCPU_EVENT(vcpu, 4, "stsi: fc: %x sel1: %x sel2: %x", fc, sel1, sel2);
@@ -414,37 +365,37 @@ static int handle_stsi(struct kvm_vcpu *vcpu)
         case 2:
                 mem = get_zeroed_page(GFP_KERNEL);
                 if (!mem)
-                        goto out_fail;
+                        goto out_no_data;
                 if (stsi((void *) mem, fc, sel1, sel2))
-                        goto out_mem;
+                        goto out_no_data;
                 break;
         case 3:
                 if (sel1 != 2 || sel2 != 2)
-                        goto out_fail;
+                        goto out_no_data;
                 mem = get_zeroed_page(GFP_KERNEL);
                 if (!mem)
-                        goto out_fail;
+                        goto out_no_data;
                 handle_stsi_3_2_2(vcpu, (void *) mem);
                 break;
         default:
-                goto out_fail;
+                goto out_no_data;
         }
 
         if (copy_to_guest_absolute(vcpu, operand2, (void *) mem, PAGE_SIZE)) {
-                kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
-                goto out_mem;
+                rc = kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
+                goto out_exception;
         }
         trace_kvm_s390_handle_stsi(vcpu, fc, sel1, sel2, operand2);
         free_page(mem);
         vcpu->arch.sie_block->gpsw.mask &= ~(3ul << 44);
         vcpu->run->s.regs.gprs[0] = 0;
         return 0;
-out_mem:
-        free_page(mem);
-out_fail:
+out_no_data:
         /* condition code 3 */
         vcpu->arch.sie_block->gpsw.mask |= 3ul << 44;
-        return 0;
+out_exception:
+        free_page(mem);
+        return rc;
 }
 
 static const intercept_handler_t b2_handlers[256] = {
@@ -575,20 +526,13 @@ static int handle_tprot(struct kvm_vcpu *vcpu)
         if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_DAT)
                 return -EOPNOTSUPP;
 
-
-        /* we must resolve the address without holding the mmap semaphore.
-         * This is ok since the userspace hypervisor is not supposed to change
-         * the mapping while the guest queries the memory. Otherwise the guest
-         * might crash or get wrong info anyway. */
-        user_address = (unsigned long) __guestaddr_to_user(vcpu, address1);
-
         down_read(&current->mm->mmap_sem);
+        user_address = __gmap_translate(address1, vcpu->arch.gmap);
+        if (IS_ERR_VALUE(user_address))
+                goto out_inject;
         vma = find_vma(current->mm, user_address);
-        if (!vma) {
-                up_read(&current->mm->mmap_sem);
-                return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
-        }
-
+        if (!vma)
+                goto out_inject;
         vcpu->arch.sie_block->gpsw.mask &= ~(3ul << 44);
         if (!(vma->vm_flags & VM_WRITE) && (vma->vm_flags & VM_READ))
                 vcpu->arch.sie_block->gpsw.mask |= (1ul << 44);
@@ -597,6 +541,10 @@ static int handle_tprot(struct kvm_vcpu *vcpu)
 
         up_read(&current->mm->mmap_sem);
         return 0;
+
+out_inject:
+        up_read(&current->mm->mmap_sem);
+        return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
 }
 
 int kvm_s390_handle_e5(struct kvm_vcpu *vcpu)
diff --git a/arch/s390/kvm/trace.h b/arch/s390/kvm/trace.h
index 2b29e62351d3..c2f582bb1cb2 100644
--- a/arch/s390/kvm/trace.h
+++ b/arch/s390/kvm/trace.h
@@ -67,7 +67,7 @@ TRACE_EVENT(kvm_s390_sie_fault,
 #define sie_intercept_code                              \
         {0x04, "Instruction"},                          \
         {0x08, "Program interruption"},                 \
-        {0x0C, "Instruction and program interuption"},  \
+        {0x0C, "Instruction and program interruption"}, \
         {0x10, "External request"},                     \
         {0x14, "External interruption"},                \
         {0x18, "I/O request"},                          \
@@ -117,7 +117,7 @@ TRACE_EVENT(kvm_s390_intercept_instruction,
                            __entry->instruction,
                            insn_to_mnemonic((unsigned char *)
                                             &__entry->instruction,
-                                         __entry->insn) ?
+                                         __entry->insn, sizeof(__entry->insn)) ?
                            "unknown" : __entry->insn)
         );
 
diff --git a/arch/s390/lib/Makefile b/arch/s390/lib/Makefile
index 6ab0d0b5cec8..20b0e97a7df2 100644
--- a/arch/s390/lib/Makefile
+++ b/arch/s390/lib/Makefile
@@ -3,7 +3,6 @@
 #
 
 lib-y += delay.o string.o uaccess_std.o uaccess_pt.o
-obj-y += usercopy.o
 obj-$(CONFIG_32BIT) += div64.o qrnnd.o ucmpdi2.o mem32.o
 obj-$(CONFIG_64BIT) += mem64.o
 lib-$(CONFIG_64BIT) += uaccess_mvcos.o
diff --git a/arch/s390/lib/uaccess_pt.c b/arch/s390/lib/uaccess_pt.c
index 466fb3383960..50ea137a2d3c 100644
--- a/arch/s390/lib/uaccess_pt.c
+++ b/arch/s390/lib/uaccess_pt.c
@@ -89,16 +89,19 @@ static unsigned long follow_table(struct mm_struct *mm,
                 if (unlikely(*table & _REGION_ENTRY_INV))
                         return -0x39UL;
                 table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
+                /* fallthrough */
         case _ASCE_TYPE_REGION2:
                 table = table + ((address >> 42) & 0x7ff);
                 if (unlikely(*table & _REGION_ENTRY_INV))
                         return -0x3aUL;
                 table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
+                /* fallthrough */
         case _ASCE_TYPE_REGION3:
                 table = table + ((address >> 31) & 0x7ff);
                 if (unlikely(*table & _REGION_ENTRY_INV))
                         return -0x3bUL;
                 table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
+                /* fallthrough */
         case _ASCE_TYPE_SEGMENT:
                 table = table + ((address >> 20) & 0x7ff);
                 if (unlikely(*table & _SEGMENT_ENTRY_INV))
diff --git a/arch/s390/lib/usercopy.c b/arch/s390/lib/usercopy.c
deleted file mode 100644
index 14b363fec8a2..000000000000
--- a/arch/s390/lib/usercopy.c
+++ /dev/null
@@ -1,8 +0,0 @@
-#include <linux/module.h>
-#include <linux/bug.h>
-
-void copy_from_user_overflow(void)
-{
-        WARN(1, "Buffer overflow detected!\n");
-}
-EXPORT_SYMBOL(copy_from_user_overflow);
diff --git a/arch/s390/mm/Makefile b/arch/s390/mm/Makefile
index 640bea12303c..839592ca265c 100644
--- a/arch/s390/mm/Makefile
+++ b/arch/s390/mm/Makefile
@@ -3,7 +3,7 @@
 #
 
 obj-y           := init.o fault.o extmem.o mmap.o vmem.o pgtable.o maccess.o
-obj-y           += page-states.o gup.o extable.o pageattr.o
+obj-y           += page-states.o gup.o extable.o pageattr.o mem_detect.o
 
 obj-$(CONFIG_CMM)               += cmm.o
 obj-$(CONFIG_HUGETLB_PAGE)      += hugetlbpage.o
diff --git a/arch/s390/mm/cmm.c b/arch/s390/mm/cmm.c
index 479e94282910..9d84a1feefef 100644
--- a/arch/s390/mm/cmm.c
+++ b/arch/s390/mm/cmm.c
@@ -458,12 +458,10 @@ static int __init cmm_init(void)
         if (rc)
                 goto out_pm;
         cmm_thread_ptr = kthread_run(cmm_thread, NULL, "cmmthread");
-        rc = IS_ERR(cmm_thread_ptr) ? PTR_ERR(cmm_thread_ptr) : 0;
-        if (rc)
-                goto out_kthread;
-        return 0;
+        if (!IS_ERR(cmm_thread_ptr))
+                return 0;
 
-out_kthread:
+        rc = PTR_ERR(cmm_thread_ptr);
         unregister_pm_notifier(&cmm_power_notifier);
 out_pm:
         unregister_oom_notifier(&cmm_oom_nb);
diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c
index 2fb9e63b8fc4..047c3e4c59a2 100644
--- a/arch/s390/mm/fault.c
+++ b/arch/s390/mm/fault.c
@@ -395,8 +395,13 @@ void __kprobes do_protection_exception(struct pt_regs *regs)
         int fault;
 
         trans_exc_code = regs->int_parm_long;
-        /* Protection exception is suppressing, decrement psw address. */
-        regs->psw.addr = __rewind_psw(regs->psw, regs->int_code >> 16);
+        /*
+         * Protection exceptions are suppressing, decrement psw address.
+         * The exception to this rule are aborted transactions, for these
+         * the PSW already points to the correct location.
+         */
+        if (!(regs->int_code & 0x200))
+                regs->psw.addr = __rewind_psw(regs->psw, regs->int_code >> 16);
         /*
          * Check for low-address protection.  This needs to be treated
          * as a special case because the translation exception code
diff --git a/arch/s390/mm/hugetlbpage.c b/arch/s390/mm/hugetlbpage.c
index 532525ec88c1..121089d57802 100644
--- a/arch/s390/mm/hugetlbpage.c
+++ b/arch/s390/mm/hugetlbpage.c
@@ -39,7 +39,7 @@ int arch_prepare_hugepage(struct page *page)
         if (!ptep)
                 return -ENOMEM;
 
-        pte = mk_pte(page, PAGE_RW);
+        pte_val(pte) = addr;
         for (i = 0; i < PTRS_PER_PTE; i++) {
                 set_pte_at(&init_mm, addr + i * PAGE_SIZE, ptep + i, pte);
                 pte_val(pte) += PAGE_SIZE;
diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c
index 49ce6bb2c641..89ebae4008f2 100644
--- a/arch/s390/mm/init.c
+++ b/arch/s390/mm/init.c
@@ -21,6 +21,7 @@
 #include <linux/init.h>
 #include <linux/pagemap.h>
 #include <linux/bootmem.h>
+#include <linux/memory.h>
 #include <linux/pfn.h>
 #include <linux/poison.h>
 #include <linux/initrd.h>
@@ -36,17 +37,17 @@
 #include <asm/tlbflush.h>
 #include <asm/sections.h>
 #include <asm/ctl_reg.h>
+#include <asm/sclp.h>
 
 pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__((__aligned__(PAGE_SIZE)));
 
 unsigned long empty_zero_page, zero_page_mask;
 EXPORT_SYMBOL(empty_zero_page);
 
-static unsigned long __init setup_zero_pages(void)
+static void __init setup_zero_pages(void)
 {
         struct cpuid cpu_id;
         unsigned int order;
-        unsigned long size;
         struct page *page;
         int i;
 
@@ -63,10 +64,18 @@ static unsigned long __init setup_zero_pages(void)
                 break;
         case 0x2097:    /* z10 */
         case 0x2098:    /* z10 */
-        default:
+        case 0x2817:    /* z196 */
+        case 0x2818:    /* z196 */
                 order = 2;
                 break;
+        case 0x2827:    /* zEC12 */
+        default:
+                order = 5;
+                break;
         }
+        /* Limit number of empty zero pages for small memory sizes */
+        if (order > 2 && totalram_pages <= 16384)
+                order = 2;
 
         empty_zero_page = __get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
         if (!empty_zero_page)
@@ -75,14 +84,11 @@ static unsigned long __init setup_zero_pages(void)
         page = virt_to_page((void *) empty_zero_page);
         split_page(page, order);
         for (i = 1 << order; i > 0; i--) {
-                SetPageReserved(page);
+                mark_page_reserved(page);
                 page++;
         }
 
-        size = PAGE_SIZE << order;
-        zero_page_mask = (size - 1) & PAGE_MASK;
-
-        return 1UL << order;
+        zero_page_mask = ((PAGE_SIZE << order) - 1) & PAGE_MASK;
 }
 
 /*
@@ -139,7 +145,7 @@ void __init mem_init(void)
 
         /* this will put all low memory onto the freelists */
         totalram_pages += free_all_bootmem();
-        totalram_pages -= setup_zero_pages();   /* Setup zeroed pages. */
+        setup_zero_pages();     /* Setup zeroed pages. */
 
         reservedpages = 0;
 
@@ -158,34 +164,15 @@ void __init mem_init(void)
                PFN_ALIGN((unsigned long)&_eshared) - 1);
 }
 
-void free_init_pages(char *what, unsigned long begin, unsigned long end)
-{
-        unsigned long addr = begin;
-
-        if (begin >= end)
-                return;
-        for (; addr < end; addr += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(addr));
-                init_page_count(virt_to_page(addr));
-                memset((void *)(addr & PAGE_MASK), POISON_FREE_INITMEM,
-                       PAGE_SIZE);
-                free_page(addr);
-                totalram_pages++;
-        }
-        printk(KERN_INFO "Freeing %s: %luk freed\n", what, (end - begin) >> 10);
-}
-
 void free_initmem(void)
 {
-        free_init_pages("unused kernel memory",
-                        (unsigned long)&__init_begin,
-                        (unsigned long)&__init_end);
+        free_initmem_default(0);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_init_pages("initrd memory", start, end);
+        free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
 }
 #endif
 
@@ -229,6 +216,15 @@ int arch_add_memory(int nid, u64 start, u64 size)
         return rc;
 }
 
+unsigned long memory_block_size_bytes(void)
+{
+        /*
+         * Make sure the memory block size is always greater
+         * or equal than the memory increment size.
+         */
+        return max_t(unsigned long, MIN_MEMORY_BLOCK_SIZE, sclp_get_rzm());
+}
+
 #ifdef CONFIG_MEMORY_HOTREMOVE
 int arch_remove_memory(u64 start, u64 size)
 {
diff --git a/arch/s390/mm/mem_detect.c b/arch/s390/mm/mem_detect.c
new file mode 100644
index 000000000000..3cbd3b8bf311
--- /dev/null
+++ b/arch/s390/mm/mem_detect.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright IBM Corp. 2008, 2009
+ *
+ * Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <asm/ipl.h>
+#include <asm/sclp.h>
+#include <asm/setup.h>
+
+#define ADDR2G (1ULL << 31)
+
+static void find_memory_chunks(struct mem_chunk chunk[], unsigned long maxsize)
+{
+        unsigned long long memsize, rnmax, rzm;
+        unsigned long addr = 0, size;
+        int i = 0, type;
+
+        rzm = sclp_get_rzm();
+        rnmax = sclp_get_rnmax();
+        memsize = rzm * rnmax;
+        if (!rzm)
+                rzm = 1ULL << 17;
+        if (sizeof(long) == 4) {
+                rzm = min(ADDR2G, rzm);
+                memsize = memsize ? min(ADDR2G, memsize) : ADDR2G;
+        }
+        if (maxsize)
+                memsize = memsize ? min((unsigned long)memsize, maxsize) : maxsize;
+        do {
+                size = 0;
+                type = tprot(addr);
+                do {
+                        size += rzm;
+                        if (memsize && addr + size >= memsize)
+                                break;
+                } while (type == tprot(addr + size));
+                if (type == CHUNK_READ_WRITE || type == CHUNK_READ_ONLY) {
+                        if (memsize && (addr + size > memsize))
+                                size = memsize - addr;
+                        chunk[i].addr = addr;
+                        chunk[i].size = size;
+                        chunk[i].type = type;
+                        i++;
+                }
+                addr += size;
+        } while (addr < memsize && i < MEMORY_CHUNKS);
+}
+
+/**
+ * detect_memory_layout - fill mem_chunk array with memory layout data
+ * @chunk: mem_chunk array to be filled
+ * @maxsize: maximum address where memory detection should stop
+ *
+ * Fills the passed in memory chunk array with the memory layout of the
+ * machine. The array must have a size of at least MEMORY_CHUNKS and will
+ * be fully initialized afterwards.
+ * If the maxsize paramater has a value > 0 memory detection will stop at
+ * that address. It is guaranteed that all chunks have an ending address
+ * that is smaller than maxsize.
+ * If maxsize is 0 all memory will be detected.
+ */
+void detect_memory_layout(struct mem_chunk chunk[], unsigned long maxsize)
+{
+        unsigned long flags, flags_dat, cr0;
+
+        memset(chunk, 0, MEMORY_CHUNKS * sizeof(struct mem_chunk));
+        /*
+         * Disable IRQs, DAT and low address protection so tprot does the
+         * right thing and we don't get scheduled away with low address
+         * protection disabled.
+         */
+        local_irq_save(flags);
+        flags_dat = __arch_local_irq_stnsm(0xfb);
+        /*
+         * In case DAT was enabled, make sure chunk doesn't reside in vmalloc
+         * space. We have disabled DAT and any access to vmalloc area will
+         * cause an exception.
+         * If DAT was disabled we are called from early ipl code.
+         */
+        if (test_bit(5, &flags_dat)) {
+                if (WARN_ON_ONCE(is_vmalloc_or_module_addr(chunk)))
+                        goto out;
+        }
+        __ctl_store(cr0, 0, 0);
+        __ctl_clear_bit(0, 28);
+        find_memory_chunks(chunk, maxsize);
+        __ctl_load(cr0, 0, 0);
+out:
+        __arch_local_irq_ssm(flags_dat);
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(detect_memory_layout);
+
+/*
+ * Create memory hole with given address and size.
+ */
+void create_mem_hole(struct mem_chunk mem_chunk[], unsigned long addr,
+                     unsigned long size)
+{
+        int i;
+
+        for (i = 0; i < MEMORY_CHUNKS; i++) {
+                struct mem_chunk *chunk = &mem_chunk[i];
+
+                if (chunk->size == 0)
+                        continue;
+                if (addr > chunk->addr + chunk->size)
+                        continue;
+                if (addr + size <= chunk->addr)
+                        continue;
+                /* Split */
+                if ((addr > chunk->addr) &&
+                    (addr + size < chunk->addr + chunk->size)) {
+                        struct mem_chunk *new = chunk + 1;
+
+                        memmove(new, chunk, (MEMORY_CHUNKS-i-1) * sizeof(*new));
+                        new->addr = addr + size;
+                        new->size = chunk->addr + chunk->size - new->addr;
+                        chunk->size = addr - chunk->addr;
+                        continue;
+                } else if ((addr <= chunk->addr) &&
+                           (addr + size >= chunk->addr + chunk->size)) {
+                        memset(chunk, 0 , sizeof(*chunk));
+                } else if (addr + size < chunk->addr + chunk->size) {
+                        chunk->size =  chunk->addr + chunk->size - addr - size;
+                        chunk->addr = addr + size;
+                } else if (addr > chunk->addr) {
+                        chunk->size = addr - chunk->addr;
+                }
+        }
+}
diff --git a/arch/s390/mm/pageattr.c b/arch/s390/mm/pageattr.c
index d21040ed5e59..80adfbf75065 100644
--- a/arch/s390/mm/pageattr.c
+++ b/arch/s390/mm/pageattr.c
@@ -9,31 +9,25 @@
 #include <asm/pgtable.h>
 #include <asm/page.h>
 
+static inline unsigned long sske_frame(unsigned long addr, unsigned char skey)
+{
+        asm volatile(".insn rrf,0xb22b0000,%[skey],%[addr],9,0"
+                     : [addr] "+a" (addr) : [skey] "d" (skey));
+        return addr;
+}
+
 void storage_key_init_range(unsigned long start, unsigned long end)
 {
-        unsigned long boundary, function, size;
+        unsigned long boundary, size;
 
         while (start < end) {
-                if (MACHINE_HAS_EDAT2) {
-                        /* set storage keys for a 2GB frame */
-                        function = 0x22000 | PAGE_DEFAULT_KEY;
-                        size = 1UL << 31;
-                        boundary = (start + size) & ~(size - 1);
-                        if (boundary <= end) {
-                                do {
-                                        start = pfmf(function, start);
-                                } while (start < boundary);
-                                continue;
-                        }
-                }
                 if (MACHINE_HAS_EDAT1) {
                         /* set storage keys for a 1MB frame */
-                        function = 0x21000 | PAGE_DEFAULT_KEY;
                         size = 1UL << 20;
                         boundary = (start + size) & ~(size - 1);
                         if (boundary <= end) {
                                 do {
-                                        start = pfmf(function, start);
+                                        start = sske_frame(start, PAGE_DEFAULT_KEY);
                                 } while (start < boundary);
                                 continue;
                         }
diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c
index ae44d2a34313..7805ddca833d 100644
--- a/arch/s390/mm/pgtable.c
+++ b/arch/s390/mm/pgtable.c
@@ -379,75 +379,184 @@ out_unmap:
 }
 EXPORT_SYMBOL_GPL(gmap_map_segment);
 
-/*
- * this function is assumed to be called with mmap_sem held
- */
-unsigned long __gmap_fault(unsigned long address, struct gmap *gmap)
+static unsigned long *gmap_table_walk(unsigned long address, struct gmap *gmap)
 {
-        unsigned long *table, vmaddr, segment;
-        struct mm_struct *mm;
-        struct gmap_pgtable *mp;
-        struct gmap_rmap *rmap;
-        struct vm_area_struct *vma;
-        struct page *page;
-        pgd_t *pgd;
-        pud_t *pud;
-        pmd_t *pmd;
+        unsigned long *table;
 
-        current->thread.gmap_addr = address;
-        mm = gmap->mm;
-        /* Walk the gmap address space page table */
         table = gmap->table + ((address >> 53) & 0x7ff);
         if (unlikely(*table & _REGION_ENTRY_INV))
-                return -EFAULT;
+                return ERR_PTR(-EFAULT);
         table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
         table = table + ((address >> 42) & 0x7ff);
         if (unlikely(*table & _REGION_ENTRY_INV))
-                return -EFAULT;
+                return ERR_PTR(-EFAULT);
         table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
         table = table + ((address >> 31) & 0x7ff);
         if (unlikely(*table & _REGION_ENTRY_INV))
-                return -EFAULT;
+                return ERR_PTR(-EFAULT);
         table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
         table = table + ((address >> 20) & 0x7ff);
+        return table;
+}
 
+/**
+ * __gmap_translate - translate a guest address to a user space address
+ * @address: guest address
+ * @gmap: pointer to guest mapping meta data structure
+ *
+ * Returns user space address which corresponds to the guest address or
+ * -EFAULT if no such mapping exists.
+ * This function does not establish potentially missing page table entries.
+ * The mmap_sem of the mm that belongs to the address space must be held
+ * when this function gets called.
+ */
+unsigned long __gmap_translate(unsigned long address, struct gmap *gmap)
+{
+        unsigned long *segment_ptr, vmaddr, segment;
+        struct gmap_pgtable *mp;
+        struct page *page;
+
+        current->thread.gmap_addr = address;
+        segment_ptr = gmap_table_walk(address, gmap);
+        if (IS_ERR(segment_ptr))
+                return PTR_ERR(segment_ptr);
         /* Convert the gmap address to an mm address. */
-        segment = *table;
-        if (likely(!(segment & _SEGMENT_ENTRY_INV))) {
+        segment = *segment_ptr;
+        if (!(segment & _SEGMENT_ENTRY_INV)) {
                 page = pfn_to_page(segment >> PAGE_SHIFT);
                 mp = (struct gmap_pgtable *) page->index;
                 return mp->vmaddr | (address & ~PMD_MASK);
         } else if (segment & _SEGMENT_ENTRY_RO) {
                 vmaddr = segment & _SEGMENT_ENTRY_ORIGIN;
-                vma = find_vma(mm, vmaddr);
-                if (!vma || vma->vm_start > vmaddr)
-                        return -EFAULT;
-
-                /* Walk the parent mm page table */
-                pgd = pgd_offset(mm, vmaddr);
-                pud = pud_alloc(mm, pgd, vmaddr);
-                if (!pud)
-                        return -ENOMEM;
-                pmd = pmd_alloc(mm, pud, vmaddr);
-                if (!pmd)
-                        return -ENOMEM;
-                if (!pmd_present(*pmd) &&
-                    __pte_alloc(mm, vma, pmd, vmaddr))
-                        return -ENOMEM;
-                /* pmd now points to a valid segment table entry. */
-                rmap = kmalloc(sizeof(*rmap), GFP_KERNEL|__GFP_REPEAT);
-                if (!rmap)
-                        return -ENOMEM;
-                /* Link gmap segment table entry location to page table. */
-                page = pmd_page(*pmd);
-                mp = (struct gmap_pgtable *) page->index;
-                rmap->entry = table;
-                spin_lock(&mm->page_table_lock);
+                return vmaddr | (address & ~PMD_MASK);
+        }
+        return -EFAULT;
+}
+EXPORT_SYMBOL_GPL(__gmap_translate);
+
+/**
+ * gmap_translate - translate a guest address to a user space address
+ * @address: guest address
+ * @gmap: pointer to guest mapping meta data structure
+ *
+ * Returns user space address which corresponds to the guest address or
+ * -EFAULT if no such mapping exists.
+ * This function does not establish potentially missing page table entries.
+ */
+unsigned long gmap_translate(unsigned long address, struct gmap *gmap)
+{
+        unsigned long rc;
+
+        down_read(&gmap->mm->mmap_sem);
+        rc = __gmap_translate(address, gmap);
+        up_read(&gmap->mm->mmap_sem);
+        return rc;
+}
+EXPORT_SYMBOL_GPL(gmap_translate);
+
+static int gmap_connect_pgtable(unsigned long address, unsigned long segment,
+                                unsigned long *segment_ptr, struct gmap *gmap)
+{
+        unsigned long vmaddr;
+        struct vm_area_struct *vma;
+        struct gmap_pgtable *mp;
+        struct gmap_rmap *rmap;
+        struct mm_struct *mm;
+        struct page *page;
+        pgd_t *pgd;
+        pud_t *pud;
+        pmd_t *pmd;
+
+        mm = gmap->mm;
+        vmaddr = segment & _SEGMENT_ENTRY_ORIGIN;
+        vma = find_vma(mm, vmaddr);
+        if (!vma || vma->vm_start > vmaddr)
+                return -EFAULT;
+        /* Walk the parent mm page table */
+        pgd = pgd_offset(mm, vmaddr);
+        pud = pud_alloc(mm, pgd, vmaddr);
+        if (!pud)
+                return -ENOMEM;
+        pmd = pmd_alloc(mm, pud, vmaddr);
+        if (!pmd)
+                return -ENOMEM;
+        if (!pmd_present(*pmd) &&
+            __pte_alloc(mm, vma, pmd, vmaddr))
+                return -ENOMEM;
+        /* pmd now points to a valid segment table entry. */
+        rmap = kmalloc(sizeof(*rmap), GFP_KERNEL|__GFP_REPEAT);
+        if (!rmap)
+                return -ENOMEM;
+        /* Link gmap segment table entry location to page table. */
+        page = pmd_page(*pmd);
+        mp = (struct gmap_pgtable *) page->index;
+        rmap->gmap = gmap;
+        rmap->entry = segment_ptr;
+        rmap->vmaddr = address;
+        spin_lock(&mm->page_table_lock);
+        if (*segment_ptr == segment) {
                 list_add(&rmap->list, &mp->mapper);
-                spin_unlock(&mm->page_table_lock);
                 /* Set gmap segment table entry to page table. */
-                *table = pmd_val(*pmd) & PAGE_MASK;
-                return vmaddr | (address & ~PMD_MASK);
+                *segment_ptr = pmd_val(*pmd) & PAGE_MASK;
+                rmap = NULL;
+        }
+        spin_unlock(&mm->page_table_lock);
+        kfree(rmap);
+        return 0;
+}
+
+static void gmap_disconnect_pgtable(struct mm_struct *mm, unsigned long *table)
+{
+        struct gmap_rmap *rmap, *next;
+        struct gmap_pgtable *mp;
+        struct page *page;
+        int flush;
+
+        flush = 0;
+        spin_lock(&mm->page_table_lock);
+        page = pfn_to_page(__pa(table) >> PAGE_SHIFT);
+        mp = (struct gmap_pgtable *) page->index;
+        list_for_each_entry_safe(rmap, next, &mp->mapper, list) {
+                *rmap->entry =
+                        _SEGMENT_ENTRY_INV | _SEGMENT_ENTRY_RO | mp->vmaddr;
+                list_del(&rmap->list);
+                kfree(rmap);
+                flush = 1;
+        }
+        spin_unlock(&mm->page_table_lock);
+        if (flush)
+                __tlb_flush_global();
+}
+
+/*
+ * this function is assumed to be called with mmap_sem held
+ */
+unsigned long __gmap_fault(unsigned long address, struct gmap *gmap)
+{
+        unsigned long *segment_ptr, segment;
+        struct gmap_pgtable *mp;
+        struct page *page;
+        int rc;
+
+        current->thread.gmap_addr = address;
+        segment_ptr = gmap_table_walk(address, gmap);
+        if (IS_ERR(segment_ptr))
+                return -EFAULT;
+        /* Convert the gmap address to an mm address. */
+        while (1) {
+                segment = *segment_ptr;
+                if (!(segment & _SEGMENT_ENTRY_INV)) {
+                        /* Page table is present */
+                        page = pfn_to_page(segment >> PAGE_SHIFT);
+                        mp = (struct gmap_pgtable *) page->index;
+                        return mp->vmaddr | (address & ~PMD_MASK);
+                }
+                if (!(segment & _SEGMENT_ENTRY_RO))
+                        /* Nothing mapped in the gmap address space. */
+                        break;
+                rc = gmap_connect_pgtable(address, segment, segment_ptr, gmap);
+                if (rc)
+                        return rc;
         }
         return -EFAULT;
 }
@@ -511,27 +620,116 @@ void gmap_discard(unsigned long from, unsigned long to, struct gmap *gmap)
 }
 EXPORT_SYMBOL_GPL(gmap_discard);
 
-void gmap_unmap_notifier(struct mm_struct *mm, unsigned long *table)
+static LIST_HEAD(gmap_notifier_list);
+static DEFINE_SPINLOCK(gmap_notifier_lock);
+
+/**
+ * gmap_register_ipte_notifier - register a pte invalidation callback
+ * @nb: pointer to the gmap notifier block
+ */
+void gmap_register_ipte_notifier(struct gmap_notifier *nb)
 {
-        struct gmap_rmap *rmap, *next;
+        spin_lock(&gmap_notifier_lock);
+        list_add(&nb->list, &gmap_notifier_list);
+        spin_unlock(&gmap_notifier_lock);
+}
+EXPORT_SYMBOL_GPL(gmap_register_ipte_notifier);
+
+/**
+ * gmap_unregister_ipte_notifier - remove a pte invalidation callback
+ * @nb: pointer to the gmap notifier block
+ */
+void gmap_unregister_ipte_notifier(struct gmap_notifier *nb)
+{
+        spin_lock(&gmap_notifier_lock);
+        list_del_init(&nb->list);
+        spin_unlock(&gmap_notifier_lock);
+}
+EXPORT_SYMBOL_GPL(gmap_unregister_ipte_notifier);
+
+/**
+ * gmap_ipte_notify - mark a range of ptes for invalidation notification
+ * @gmap: pointer to guest mapping meta data structure
+ * @address: virtual address in the guest address space
+ * @len: size of area
+ *
+ * Returns 0 if for each page in the given range a gmap mapping exists and
+ * the invalidation notification could be set. If the gmap mapping is missing
+ * for one or more pages -EFAULT is returned. If no memory could be allocated
+ * -ENOMEM is returned. This function establishes missing page table entries.
+ */
+int gmap_ipte_notify(struct gmap *gmap, unsigned long start, unsigned long len)
+{
+        unsigned long addr;
+        spinlock_t *ptl;
+        pte_t *ptep, entry;
+        pgste_t pgste;
+        int rc = 0;
+
+        if ((start & ~PAGE_MASK) || (len & ~PAGE_MASK))
+                return -EINVAL;
+        down_read(&gmap->mm->mmap_sem);
+        while (len) {
+                /* Convert gmap address and connect the page tables */
+                addr = __gmap_fault(start, gmap);
+                if (IS_ERR_VALUE(addr)) {
+                        rc = addr;
+                        break;
+                }
+                /* Get the page mapped */
+                if (get_user_pages(current, gmap->mm, addr, 1, 1, 0,
+                                   NULL, NULL) != 1) {
+                        rc = -EFAULT;
+                        break;
+                }
+                /* Walk the process page table, lock and get pte pointer */
+                ptep = get_locked_pte(gmap->mm, addr, &ptl);
+                if (unlikely(!ptep))
+                        continue;
+                /* Set notification bit in the pgste of the pte */
+                entry = *ptep;
+                if ((pte_val(entry) & (_PAGE_INVALID | _PAGE_RO)) == 0) {
+                        pgste = pgste_get_lock(ptep);
+                        pgste_val(pgste) |= RCP_IN_BIT;
+                        pgste_set_unlock(ptep, pgste);
+                        start += PAGE_SIZE;
+                        len -= PAGE_SIZE;
+                }
+                spin_unlock(ptl);
+        }
+        up_read(&gmap->mm->mmap_sem);
+        return rc;
+}
+EXPORT_SYMBOL_GPL(gmap_ipte_notify);
+
+/**
+ * gmap_do_ipte_notify - call all invalidation callbacks for a specific pte.
+ * @mm: pointer to the process mm_struct
+ * @addr: virtual address in the process address space
+ * @pte: pointer to the page table entry
+ *
+ * This function is assumed to be called with the page table lock held
+ * for the pte to notify.
+ */
+void gmap_do_ipte_notify(struct mm_struct *mm, unsigned long addr, pte_t *pte)
+{
+        unsigned long segment_offset;
+        struct gmap_notifier *nb;
         struct gmap_pgtable *mp;
+        struct gmap_rmap *rmap;
         struct page *page;
-        int flush;
 
-        flush = 0;
-        spin_lock(&mm->page_table_lock);
-        page = pfn_to_page(__pa(table) >> PAGE_SHIFT);
+        segment_offset = ((unsigned long) pte) & (255 * sizeof(pte_t));
+        segment_offset = segment_offset * (4096 / sizeof(pte_t));
+        page = pfn_to_page(__pa(pte) >> PAGE_SHIFT);
         mp = (struct gmap_pgtable *) page->index;
-        list_for_each_entry_safe(rmap, next, &mp->mapper, list) {
-                *rmap->entry =
-                        _SEGMENT_ENTRY_INV | _SEGMENT_ENTRY_RO | mp->vmaddr;
-                list_del(&rmap->list);
-                kfree(rmap);
-                flush = 1;
+        spin_lock(&gmap_notifier_lock);
+        list_for_each_entry(rmap, &mp->mapper, list) {
+                list_for_each_entry(nb, &gmap_notifier_list, list)
+                        nb->notifier_call(rmap->gmap,
+                                          rmap->vmaddr + segment_offset);
         }
-        spin_unlock(&mm->page_table_lock);
-        if (flush)
-                __tlb_flush_global();
+        spin_unlock(&gmap_notifier_lock);
 }
 
 static inline unsigned long *page_table_alloc_pgste(struct mm_struct *mm,
@@ -586,8 +784,8 @@ static inline void page_table_free_pgste(unsigned long *table)
 {
 }
 
-static inline void gmap_unmap_notifier(struct mm_struct *mm,
-                                          unsigned long *table)
+static inline void gmap_disconnect_pgtable(struct mm_struct *mm,
+                                           unsigned long *table)
 {
 }
 
@@ -653,7 +851,7 @@ void page_table_free(struct mm_struct *mm, unsigned long *table)
         unsigned int bit, mask;
 
         if (mm_has_pgste(mm)) {
-                gmap_unmap_notifier(mm, table);
+                gmap_disconnect_pgtable(mm, table);
                 return page_table_free_pgste(table);
         }
         /* Free 1K/2K page table fragment of a 4K page */
@@ -696,7 +894,7 @@ void page_table_free_rcu(struct mmu_gather *tlb, unsigned long *table)
 
         mm = tlb->mm;
         if (mm_has_pgste(mm)) {
-                gmap_unmap_notifier(mm, table);
+                gmap_disconnect_pgtable(mm, table);
                 table = (unsigned long *) (__pa(table) | FRAG_MASK);
                 tlb_remove_table(tlb, table);
                 return;
diff --git a/arch/s390/mm/vmem.c b/arch/s390/mm/vmem.c
index ffab84db6907..8b268fcc4612 100644
--- a/arch/s390/mm/vmem.c
+++ b/arch/s390/mm/vmem.c
@@ -191,19 +191,16 @@ static void vmem_remove_range(unsigned long start, unsigned long size)
 /*
  * Add a backed mem_map array to the virtual mem_map array.
  */
-int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
+int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node)
 {
-        unsigned long address, start_addr, end_addr;
+        unsigned long address = start;
         pgd_t *pg_dir;
         pud_t *pu_dir;
         pmd_t *pm_dir;
         pte_t *pt_dir;
         int ret = -ENOMEM;
 
-        start_addr = (unsigned long) start;
-        end_addr = (unsigned long) (start + nr);
-
-        for (address = start_addr; address < end_addr;) {
+        for (address = start; address < end;) {
                 pg_dir = pgd_offset_k(address);
                 if (pgd_none(*pg_dir)) {
                         pu_dir = vmem_pud_alloc();
@@ -262,14 +259,14 @@ int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
                 }
                 address += PAGE_SIZE;
         }
-        memset(start, 0, nr * sizeof(struct page));
+        memset((void *)start, 0, end - start);
         ret = 0;
 out:
-        flush_tlb_kernel_range(start_addr, end_addr);
+        flush_tlb_kernel_range(start, end);
         return ret;
 }
 
-void vmemmap_free(struct page *memmap, unsigned long nr_pages)
+void vmemmap_free(unsigned long start, unsigned long end)
 {
 }
 
@@ -378,9 +375,8 @@ void __init vmem_map_init(void)
 
         ro_start = PFN_ALIGN((unsigned long)&_stext);
         ro_end = (unsigned long)&_eshared & PAGE_MASK;
-        for (i = 0; i < MEMORY_CHUNKS && memory_chunk[i].size > 0; i++) {
-                if (memory_chunk[i].type == CHUNK_CRASHK ||
-                    memory_chunk[i].type == CHUNK_OLDMEM)
+        for (i = 0; i < MEMORY_CHUNKS; i++) {
+                if (!memory_chunk[i].size)
                         continue;
                 start = memory_chunk[i].addr;
                 end = memory_chunk[i].addr + memory_chunk[i].size;
@@ -415,9 +411,6 @@ static int __init vmem_convert_memory_chunk(void)
         for (i = 0; i < MEMORY_CHUNKS; i++) {
                 if (!memory_chunk[i].size)
                         continue;
-                if (memory_chunk[i].type == CHUNK_CRASHK ||
-                    memory_chunk[i].type == CHUNK_OLDMEM)
-                        continue;
                 seg = kzalloc(sizeof(*seg), GFP_KERNEL);
                 if (!seg)
                         panic("Out of memory...\n");
diff --git a/arch/s390/net/bpf_jit_comp.c b/arch/s390/net/bpf_jit_comp.c
index 0972e91cced2..82f165f8078c 100644
--- a/arch/s390/net/bpf_jit_comp.c
+++ b/arch/s390/net/bpf_jit_comp.c
@@ -747,10 +747,9 @@ void bpf_jit_compile(struct sk_filter *fp)
 
         if (!bpf_jit_enable)
                 return;
-        addrs = kmalloc(fp->len * sizeof(*addrs), GFP_KERNEL);
+        addrs = kcalloc(fp->len, sizeof(*addrs), GFP_KERNEL);
         if (addrs == NULL)
                 return;
-        memset(addrs, 0, fp->len * sizeof(*addrs));
         memset(&jit, 0, sizeof(cjit));
         memset(&cjit, 0, sizeof(cjit));
 
diff --git a/arch/s390/oprofile/init.c b/arch/s390/oprofile/init.c
index 584b93674ea4..ffeb17ce7f31 100644
--- a/arch/s390/oprofile/init.c
+++ b/arch/s390/oprofile/init.c
@@ -440,6 +440,7 @@ static int oprofile_hwsampler_init(struct oprofile_operations *ops)
                 switch (id.machine) {
                 case 0x2097: case 0x2098: ops->cpu_type = "s390/z10"; break;
                 case 0x2817: case 0x2818: ops->cpu_type = "s390/z196"; break;
+                case 0x2827:              ops->cpu_type = "s390/zEC12"; break;
                 default: return -ENODEV;
                 }
         }
diff --git a/arch/s390/pci/Makefile b/arch/s390/pci/Makefile
index f0f426a113ce..086a2e37935d 100644
--- a/arch/s390/pci/Makefile
+++ b/arch/s390/pci/Makefile
@@ -2,5 +2,5 @@
 # Makefile for the s390 PCI subsystem.
 #
 
-obj-$(CONFIG_PCI)       += pci.o pci_dma.o pci_clp.o pci_msi.o \
-                           pci_sysfs.o pci_event.o pci_debug.o
+obj-$(CONFIG_PCI)       += pci.o pci_dma.o pci_clp.o pci_msi.o pci_sysfs.o \
+                           pci_event.o pci_debug.o pci_insn.o
diff --git a/arch/s390/pci/pci.c b/arch/s390/pci/pci.c
index 27b4c17855b9..e6f15b5d8b7d 100644
--- a/arch/s390/pci/pci.c
+++ b/arch/s390/pci/pci.c
@@ -99,9 +99,6 @@ static int __read_mostly aisb_max;
 static struct kmem_cache *zdev_irq_cache;
 static struct kmem_cache *zdev_fmb_cache;
 
-debug_info_t *pci_debug_msg_id;
-debug_info_t *pci_debug_err_id;
-
 static inline int irq_to_msi_nr(unsigned int irq)
 {
         return irq & ZPCI_MSI_MASK;
@@ -179,7 +176,7 @@ static int zpci_register_airq(struct zpci_dev *zdev, unsigned int aisb,
         fib->aisb = (u64) bucket->aisb + aisb / 8;
         fib->aisbo = aisb & ZPCI_MSI_MASK;
 
-        rc = mpcifc_instr(req, fib);
+        rc = s390pci_mod_fc(req, fib);
         pr_debug("%s mpcifc returned noi: %d\n", __func__, fib->noi);
 
         free_page((unsigned long) fib);
@@ -209,7 +206,7 @@ static int mod_pci(struct zpci_dev *zdev, int fn, u8 dmaas, struct mod_pci_args
         fib->iota = args->iota;
         fib->fmb_addr = args->fmb_addr;
 
-        rc = mpcifc_instr(req, fib);
+        rc = s390pci_mod_fc(req, fib);
         free_page((unsigned long) fib);
         return rc;
 }
@@ -249,10 +246,9 @@ int zpci_fmb_enable_device(struct zpci_dev *zdev)
         if (zdev->fmb)
                 return -EINVAL;
 
-        zdev->fmb = kmem_cache_alloc(zdev_fmb_cache, GFP_KERNEL);
+        zdev->fmb = kmem_cache_zalloc(zdev_fmb_cache, GFP_KERNEL);
         if (!zdev->fmb)
                 return -ENOMEM;
-        memset(zdev->fmb, 0, sizeof(*zdev->fmb));
         WARN_ON((u64) zdev->fmb & 0xf);
 
         args.fmb_addr = virt_to_phys(zdev->fmb);
@@ -284,12 +280,12 @@ static int zpci_cfg_load(struct zpci_dev *zdev, int offset, u32 *val, u8 len)
         u64 data;
         int rc;
 
-        rc = pcilg_instr(&data, req, offset);
-        data = data << ((8 - len) * 8);
-        data = le64_to_cpu(data);
-        if (!rc)
+        rc = s390pci_load(&data, req, offset);
+        if (!rc) {
+                data = data << ((8 - len) * 8);
+                data = le64_to_cpu(data);
                 *val = (u32) data;
-        else
+        } else
                 *val = 0xffffffff;
         return rc;
 }
@@ -302,7 +298,7 @@ static int zpci_cfg_store(struct zpci_dev *zdev, int offset, u32 val, u8 len)
 
         data = cpu_to_le64(data);
         data = data >> ((8 - len) * 8);
-        rc = pcistg_instr(data, req, offset);
+        rc = s390pci_store(data, req, offset);
         return rc;
 }
 
@@ -409,20 +405,28 @@ static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
                     int size, u32 *val)
 {
         struct zpci_dev *zdev = get_zdev_by_bus(bus);
+        int ret;
 
         if (!zdev || devfn != ZPCI_DEVFN)
-                return 0;
-        return zpci_cfg_load(zdev, where, val, size);
+                ret = -ENODEV;
+        else
+                ret = zpci_cfg_load(zdev, where, val, size);
+
+        return ret;
 }
 
 static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
                      int size, u32 val)
 {
         struct zpci_dev *zdev = get_zdev_by_bus(bus);
+        int ret;
 
         if (!zdev || devfn != ZPCI_DEVFN)
-                return 0;
-        return zpci_cfg_store(zdev, where, val, size);
+                ret = -ENODEV;
+        else
+                ret = zpci_cfg_store(zdev, where, val, size);
+
+        return ret;
 }
 
 static struct pci_ops pci_root_ops = {
@@ -474,7 +478,7 @@ scan:
         }
 
         /* enable interrupts again */
-        sic_instr(SIC_IRQ_MODE_SINGLE, NULL, PCI_ISC);
+        set_irq_ctrl(SIC_IRQ_MODE_SINGLE, NULL, PCI_ISC);
 
         /* check again to not lose initiative */
         rmb();
@@ -596,19 +600,6 @@ static void zpci_map_resources(struct zpci_dev *zdev)
         }
 };
 
-static void zpci_unmap_resources(struct pci_dev *pdev)
-{
-        resource_size_t len;
-        int i;
-
-        for (i = 0; i < PCI_BAR_COUNT; i++) {
-                len = pci_resource_len(pdev, i);
-                if (!len)
-                        continue;
-                pci_iounmap(pdev, (void *) pdev->resource[i].start);
-        }
-};
-
 struct zpci_dev *zpci_alloc_device(void)
 {
         struct zpci_dev *zdev;
@@ -636,32 +627,6 @@ void zpci_free_device(struct zpci_dev *zdev)
         kfree(zdev);
 }
 
-/* Called on removal of pci_dev, leaves zpci and bus device */
-static void zpci_remove_device(struct pci_dev *pdev)
-{
-        struct zpci_dev *zdev = get_zdev(pdev);
-
-        dev_info(&pdev->dev, "Removing device %u\n", zdev->domain);
-        zdev->state = ZPCI_FN_STATE_CONFIGURED;
-        zpci_dma_exit_device(zdev);
-        zpci_fmb_disable_device(zdev);
-        zpci_sysfs_remove_device(&pdev->dev);
-        zpci_unmap_resources(pdev);
-        list_del(&zdev->entry);         /* can be called from init */
-        zdev->pdev = NULL;
-}
-
-static void zpci_scan_devices(void)
-{
-        struct zpci_dev *zdev;
-
-        mutex_lock(&zpci_list_lock);
-        list_for_each_entry(zdev, &zpci_list, entry)
-                if (zdev->state == ZPCI_FN_STATE_CONFIGURED)
-                        zpci_scan_device(zdev);
-        mutex_unlock(&zpci_list_lock);
-}
-
 /*
  * Too late for any s390 specific setup, since interrupts must be set up
  * already which requires DMA setup too and the pci scan will access the
@@ -688,12 +653,6 @@ int pcibios_enable_device(struct pci_dev *pdev, int mask)
         return 0;
 }
 
-void pcibios_disable_device(struct pci_dev *pdev)
-{
-        zpci_remove_device(pdev);
-        pdev->sysdata = NULL;
-}
-
 int pcibios_add_platform_entries(struct pci_dev *pdev)
 {
         return zpci_sysfs_add_device(&pdev->dev);
@@ -789,7 +748,7 @@ static int __init zpci_irq_init(void)
         spin_lock_init(&bucket->lock);
         /* set summary to 1 to be called every time for the ISC */
         *zpci_irq_si = 1;
-        sic_instr(SIC_IRQ_MODE_SINGLE, NULL, PCI_ISC);
+        set_irq_ctrl(SIC_IRQ_MODE_SINGLE, NULL, PCI_ISC);
         return 0;
 
 out_ai:
@@ -872,7 +831,19 @@ static void zpci_free_iomap(struct zpci_dev *zdev, int entry)
         spin_unlock(&zpci_iomap_lock);
 }
 
-static int zpci_create_device_bus(struct zpci_dev *zdev)
+int pcibios_add_device(struct pci_dev *pdev)
+{
+        struct zpci_dev *zdev = get_zdev(pdev);
+
+        zdev->pdev = pdev;
+        zpci_debug_init_device(zdev);
+        zpci_fmb_enable_device(zdev);
+        zpci_map_resources(zdev);
+
+        return 0;
+}
+
+static int zpci_scan_bus(struct zpci_dev *zdev)
 {
         struct resource *res;
         LIST_HEAD(resources);
@@ -909,8 +880,8 @@ static int zpci_create_device_bus(struct zpci_dev *zdev)
                 pci_add_resource(&resources, res);
         }
 
-        zdev->bus = pci_create_root_bus(NULL, ZPCI_BUS_NR, &pci_root_ops,
-                                        zdev, &resources);
+        zdev->bus = pci_scan_root_bus(NULL, ZPCI_BUS_NR, &pci_root_ops,
+                                      zdev, &resources);
         if (!zdev->bus)
                 return -EIO;
 
@@ -959,6 +930,13 @@ out:
 }
 EXPORT_SYMBOL_GPL(zpci_enable_device);
 
+int zpci_disable_device(struct zpci_dev *zdev)
+{
+        zpci_dma_exit_device(zdev);
+        return clp_disable_fh(zdev);
+}
+EXPORT_SYMBOL_GPL(zpci_disable_device);
+
 int zpci_create_device(struct zpci_dev *zdev)
 {
         int rc;
@@ -967,9 +945,16 @@ int zpci_create_device(struct zpci_dev *zdev)
         if (rc)
                 goto out;
 
-        rc = zpci_create_device_bus(zdev);
+        if (zdev->state == ZPCI_FN_STATE_CONFIGURED) {
+                rc = zpci_enable_device(zdev);
+                if (rc)
+                        goto out_free;
+
+                zdev->state = ZPCI_FN_STATE_ONLINE;
+        }
+        rc = zpci_scan_bus(zdev);
         if (rc)
-                goto out_bus;
+                goto out_disable;
 
         mutex_lock(&zpci_list_lock);
         list_add_tail(&zdev->entry, &zpci_list);
@@ -977,21 +962,12 @@ int zpci_create_device(struct zpci_dev *zdev)
                 hotplug_ops->create_slot(zdev);
         mutex_unlock(&zpci_list_lock);
 
-        if (zdev->state == ZPCI_FN_STATE_STANDBY)
-                return 0;
-
-        rc = zpci_enable_device(zdev);
-        if (rc)
-                goto out_start;
         return 0;
 
-out_start:
-        mutex_lock(&zpci_list_lock);
-        list_del(&zdev->entry);
-        if (hotplug_ops)
-                hotplug_ops->remove_slot(zdev);
-        mutex_unlock(&zpci_list_lock);
-out_bus:
+out_disable:
+        if (zdev->state == ZPCI_FN_STATE_ONLINE)
+                zpci_disable_device(zdev);
+out_free:
         zpci_free_domain(zdev);
 out:
         return rc;
@@ -1016,15 +992,9 @@ int zpci_scan_device(struct zpci_dev *zdev)
                 goto out;
         }
 
-        zpci_debug_init_device(zdev);
-        zpci_fmb_enable_device(zdev);
-        zpci_map_resources(zdev);
         pci_bus_add_devices(zdev->bus);
 
-        /* now that pdev was added to the bus mark it as used */
-        zdev->state = ZPCI_FN_STATE_ONLINE;
         return 0;
-
 out:
         zpci_dma_exit_device(zdev);
         clp_disable_fh(zdev);
@@ -1087,13 +1057,13 @@ void zpci_deregister_hp_ops(void)
 }
 EXPORT_SYMBOL_GPL(zpci_deregister_hp_ops);
 
-unsigned int s390_pci_probe = 1;
+unsigned int s390_pci_probe;
 EXPORT_SYMBOL_GPL(s390_pci_probe);
 
 char * __init pcibios_setup(char *str)
 {
-        if (!strcmp(str, "off")) {
-                s390_pci_probe = 0;
+        if (!strcmp(str, "on")) {
+                s390_pci_probe = 1;
                 return NULL;
         }
         return str;
@@ -1138,7 +1108,6 @@ static int __init pci_base_init(void)
         if (rc)
                 goto out_find;
 
-        zpci_scan_devices();
         return 0;
 
 out_find:
diff --git a/arch/s390/pci/pci_clp.c b/arch/s390/pci/pci_clp.c
index f339fe2feb15..bd34359d1546 100644
--- a/arch/s390/pci/pci_clp.c
+++ b/arch/s390/pci/pci_clp.c
@@ -13,6 +13,7 @@
 #include <linux/err.h>
 #include <linux/delay.h>
 #include <linux/pci.h>
+#include <asm/pci_debug.h>
 #include <asm/pci_clp.h>
 
 /*
@@ -144,6 +145,7 @@ int clp_add_pci_device(u32 fid, u32 fh, int configured)
         struct zpci_dev *zdev;
         int rc;
 
+        zpci_dbg(3, "add fid:%x, fh:%x, c:%d\n", fid, fh, configured);
         zdev = zpci_alloc_device();
         if (IS_ERR(zdev))
                 return PTR_ERR(zdev);
@@ -204,8 +206,8 @@ static int clp_set_pci_fn(u32 *fh, u8 nr_dma_as, u8 command)
         if (!rc && rrb->response.hdr.rsp == CLP_RC_OK)
                 *fh = rrb->response.fh;
         else {
-                pr_err("Set PCI FN failed with response: %x  cc: %d\n",
-                        rrb->response.hdr.rsp, rc);
+                zpci_dbg(0, "SPF fh:%x, cc:%d, resp:%x\n", *fh, rc,
+                         rrb->response.hdr.rsp);
                 rc = -EIO;
         }
         clp_free_block(rrb);
@@ -221,6 +223,8 @@ int clp_enable_fh(struct zpci_dev *zdev, u8 nr_dma_as)
         if (!rc)
                 /* Success -> store enabled handle in zdev */
                 zdev->fh = fh;
+
+        zpci_dbg(3, "ena fid:%x, fh:%x, rc:%d\n", zdev->fid, zdev->fh, rc);
         return rc;
 }
 
@@ -237,9 +241,8 @@ int clp_disable_fh(struct zpci_dev *zdev)
         if (!rc)
                 /* Success -> store disabled handle in zdev */
                 zdev->fh = fh;
-        else
-                dev_err(&zdev->pdev->dev,
-                        "Failed to disable fn handle: 0x%x\n", fh);
+
+        zpci_dbg(3, "dis fid:%x, fh:%x, rc:%d\n", zdev->fid, zdev->fh, rc);
         return rc;
 }
 
diff --git a/arch/s390/pci/pci_debug.c b/arch/s390/pci/pci_debug.c
index a5d07bc2a547..771b82359af4 100644
--- a/arch/s390/pci/pci_debug.c
+++ b/arch/s390/pci/pci_debug.c
@@ -11,12 +11,17 @@
 #include <linux/kernel.h>
 #include <linux/seq_file.h>
 #include <linux/debugfs.h>
+#include <linux/export.h>
 #include <linux/pci.h>
 #include <asm/debug.h>
 
 #include <asm/pci_dma.h>
 
 static struct dentry *debugfs_root;
+debug_info_t *pci_debug_msg_id;
+EXPORT_SYMBOL_GPL(pci_debug_msg_id);
+debug_info_t *pci_debug_err_id;
+EXPORT_SYMBOL_GPL(pci_debug_err_id);
 
 static char *pci_perf_names[] = {
         /* hardware counters */
@@ -168,7 +173,6 @@ int __init zpci_debug_init(void)
                 return -EINVAL;
         debug_register_view(pci_debug_msg_id, &debug_sprintf_view);
         debug_set_level(pci_debug_msg_id, 3);
-        zpci_dbg("Debug view initialized\n");
 
         /* error log */
         pci_debug_err_id = debug_register("pci_error", 2, 1, 16);
@@ -176,7 +180,6 @@ int __init zpci_debug_init(void)
                 return -EINVAL;
         debug_register_view(pci_debug_err_id, &debug_hex_ascii_view);
         debug_set_level(pci_debug_err_id, 6);
-        zpci_err("Debug view initialized\n");
 
         debugfs_root = debugfs_create_dir("pci", NULL);
         return 0;
diff --git a/arch/s390/pci/pci_dma.c b/arch/s390/pci/pci_dma.c
index a547419907c3..f8e69d5bc0a9 100644
--- a/arch/s390/pci/pci_dma.c
+++ b/arch/s390/pci/pci_dma.c
@@ -169,8 +169,9 @@ static int dma_update_trans(struct zpci_dev *zdev, unsigned long pa,
                  * needs to be redone!
                  */
                 goto no_refresh;
-        rc = rpcit_instr((u64) zdev->fh << 32, start_dma_addr,
-                          nr_pages * PAGE_SIZE);
+
+        rc = s390pci_refresh_trans((u64) zdev->fh << 32, start_dma_addr,
+                                   nr_pages * PAGE_SIZE);
 
 no_refresh:
         spin_unlock_irqrestore(&zdev->dma_table_lock, irq_flags);
@@ -268,8 +269,6 @@ static dma_addr_t s390_dma_map_pages(struct device *dev, struct page *page,
         int flags = ZPCI_PTE_VALID;
         dma_addr_t dma_addr;
 
-        WARN_ON_ONCE(offset > PAGE_SIZE);
-
         /* This rounds up number of pages based on size and offset */
         nr_pages = iommu_num_pages(pa, size, PAGE_SIZE);
         iommu_page_index = dma_alloc_iommu(zdev, nr_pages);
@@ -291,7 +290,7 @@ static dma_addr_t s390_dma_map_pages(struct device *dev, struct page *page,
 
         if (!dma_update_trans(zdev, pa, dma_addr, size, flags)) {
                 atomic64_add(nr_pages, (atomic64_t *) &zdev->fmb->mapped_pages);
-                return dma_addr + offset;
+                return dma_addr + (offset & ~PAGE_MASK);
         }
 
 out_free:
diff --git a/arch/s390/pci/pci_insn.c b/arch/s390/pci/pci_insn.c
new file mode 100644
index 000000000000..22eeb9d7ffeb
--- /dev/null
+++ b/arch/s390/pci/pci_insn.c
@@ -0,0 +1,202 @@
+/*
+ * s390 specific pci instructions
+ *
+ * Copyright IBM Corp. 2013
+ */
+
+#include <linux/export.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <asm/pci_insn.h>
+#include <asm/processor.h>
+
+#define ZPCI_INSN_BUSY_DELAY    1       /* 1 microsecond */
+
+/* Modify PCI Function Controls */
+static inline u8 __mpcifc(u64 req, struct zpci_fib *fib, u8 *status)
+{
+        u8 cc;
+
+        asm volatile (
+                "       .insn   rxy,0xe300000000d0,%[req],%[fib]\n"
+                "       ipm     %[cc]\n"
+                "       srl     %[cc],28\n"
+                : [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib)
+                : : "cc");
+        *status = req >> 24 & 0xff;
+        return cc;
+}
+
+int s390pci_mod_fc(u64 req, struct zpci_fib *fib)
+{
+        u8 cc, status;
+
+        do {
+                cc = __mpcifc(req, fib, &status);
+                if (cc == 2)
+                        msleep(ZPCI_INSN_BUSY_DELAY);
+        } while (cc == 2);
+
+        if (cc)
+                printk_once(KERN_ERR "%s: error cc: %d  status: %d\n",
+                             __func__, cc, status);
+        return (cc) ? -EIO : 0;
+}
+
+/* Refresh PCI Translations */
+static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)
+{
+        register u64 __addr asm("2") = addr;
+        register u64 __range asm("3") = range;
+        u8 cc;
+
+        asm volatile (
+                "       .insn   rre,0xb9d30000,%[fn],%[addr]\n"
+                "       ipm     %[cc]\n"
+                "       srl     %[cc],28\n"
+                : [cc] "=d" (cc), [fn] "+d" (fn)
+                : [addr] "d" (__addr), "d" (__range)
+                : "cc");
+        *status = fn >> 24 & 0xff;
+        return cc;
+}
+
+int s390pci_refresh_trans(u64 fn, u64 addr, u64 range)
+{
+        u8 cc, status;
+
+        do {
+                cc = __rpcit(fn, addr, range, &status);
+                if (cc == 2)
+                        udelay(ZPCI_INSN_BUSY_DELAY);
+        } while (cc == 2);
+
+        if (cc)
+                printk_once(KERN_ERR "%s: error cc: %d  status: %d  dma_addr: %Lx  size: %Lx\n",
+                            __func__, cc, status, addr, range);
+        return (cc) ? -EIO : 0;
+}
+
+/* Set Interruption Controls */
+void set_irq_ctrl(u16 ctl, char *unused, u8 isc)
+{
+        asm volatile (
+                "       .insn   rsy,0xeb00000000d1,%[ctl],%[isc],%[u]\n"
+                : : [ctl] "d" (ctl), [isc] "d" (isc << 27), [u] "Q" (*unused));
+}
+
+/* PCI Load */
+static inline int __pcilg(u64 *data, u64 req, u64 offset, u8 *status)
+{
+        register u64 __req asm("2") = req;
+        register u64 __offset asm("3") = offset;
+        int cc = -ENXIO;
+        u64 __data;
+
+        asm volatile (
+                "       .insn   rre,0xb9d20000,%[data],%[req]\n"
+                "0:     ipm     %[cc]\n"
+                "       srl     %[cc],28\n"
+                "1:\n"
+                EX_TABLE(0b, 1b)
+                : [cc] "+d" (cc), [data] "=d" (__data), [req] "+d" (__req)
+                :  "d" (__offset)
+                : "cc");
+        *status = __req >> 24 & 0xff;
+        if (!cc)
+                *data = __data;
+
+        return cc;
+}
+
+int s390pci_load(u64 *data, u64 req, u64 offset)
+{
+        u8 status;
+        int cc;
+
+        do {
+                cc = __pcilg(data, req, offset, &status);
+                if (cc == 2)
+                        udelay(ZPCI_INSN_BUSY_DELAY);
+        } while (cc == 2);
+
+        if (cc)
+                printk_once(KERN_ERR "%s: error cc: %d  status: %d  req: %Lx  offset: %Lx\n",
+                            __func__, cc, status, req, offset);
+        return (cc > 0) ? -EIO : cc;
+}
+EXPORT_SYMBOL_GPL(s390pci_load);
+
+/* PCI Store */
+static inline int __pcistg(u64 data, u64 req, u64 offset, u8 *status)
+{
+        register u64 __req asm("2") = req;
+        register u64 __offset asm("3") = offset;
+        int cc = -ENXIO;
+
+        asm volatile (
+                "       .insn   rre,0xb9d00000,%[data],%[req]\n"
+                "0:     ipm     %[cc]\n"
+                "       srl     %[cc],28\n"
+                "1:\n"
+                EX_TABLE(0b, 1b)
+                : [cc] "+d" (cc), [req] "+d" (__req)
+                : "d" (__offset), [data] "d" (data)
+                : "cc");
+        *status = __req >> 24 & 0xff;
+        return cc;
+}
+
+int s390pci_store(u64 data, u64 req, u64 offset)
+{
+        u8 status;
+        int cc;
+
+        do {
+                cc = __pcistg(data, req, offset, &status);
+                if (cc == 2)
+                        udelay(ZPCI_INSN_BUSY_DELAY);
+        } while (cc == 2);
+
+        if (cc)
+                printk_once(KERN_ERR "%s: error cc: %d  status: %d  req: %Lx  offset: %Lx\n",
+                        __func__, cc, status, req, offset);
+        return (cc > 0) ? -EIO : cc;
+}
+EXPORT_SYMBOL_GPL(s390pci_store);
+
+/* PCI Store Block */
+static inline int __pcistb(const u64 *data, u64 req, u64 offset, u8 *status)
+{
+        int cc = -ENXIO;
+
+        asm volatile (
+                "       .insn   rsy,0xeb00000000d0,%[req],%[offset],%[data]\n"
+                "0:     ipm     %[cc]\n"
+                "       srl     %[cc],28\n"
+                "1:\n"
+                EX_TABLE(0b, 1b)
+                : [cc] "+d" (cc), [req] "+d" (req)
+                : [offset] "d" (offset), [data] "Q" (*data)
+                : "cc");
+        *status = req >> 24 & 0xff;
+        return cc;
+}
+
+int s390pci_store_block(const u64 *data, u64 req, u64 offset)
+{
+        u8 status;
+        int cc;
+
+        do {
+                cc = __pcistb(data, req, offset, &status);
+                if (cc == 2)
+                        udelay(ZPCI_INSN_BUSY_DELAY);
+        } while (cc == 2);
+
+        if (cc)
+                printk_once(KERN_ERR "%s: error cc: %d  status: %d  req: %Lx  offset: %Lx\n",
+                            __func__, cc, status, req, offset);
+        return (cc > 0) ? -EIO : cc;
+}
+EXPORT_SYMBOL_GPL(s390pci_store_block);
diff --git a/arch/s390/pci/pci_msi.c b/arch/s390/pci/pci_msi.c
index 0297931335e1..b097aed05a9b 100644
--- a/arch/s390/pci/pci_msi.c
+++ b/arch/s390/pci/pci_msi.c
@@ -18,8 +18,9 @@
 
 /* mapping of irq numbers to msi_desc */
 static struct hlist_head *msi_hash;
-static unsigned int msihash_shift = 6;
-#define msi_hashfn(nr)  hash_long(nr, msihash_shift)
+static const unsigned int msi_hash_bits = 8;
+#define MSI_HASH_BUCKETS (1U << msi_hash_bits)
+#define msi_hashfn(nr)  hash_long(nr, msi_hash_bits)
 
 static DEFINE_SPINLOCK(msi_map_lock);
 
@@ -74,6 +75,7 @@ int zpci_setup_msi_irq(struct zpci_dev *zdev, struct msi_desc *msi,
         map->irq = nr;
         map->msi = msi;
         zdev->msi_map[nr & ZPCI_MSI_MASK] = map;
+        INIT_HLIST_NODE(&map->msi_chain);
 
         pr_debug("%s hashing irq: %u  to bucket nr: %llu\n",
                 __func__, nr, msi_hashfn(nr));
@@ -125,11 +127,11 @@ int __init zpci_msihash_init(void)
 {
         unsigned int i;
 
-        msi_hash = kmalloc(256 * sizeof(*msi_hash), GFP_KERNEL);
+        msi_hash = kmalloc(MSI_HASH_BUCKETS * sizeof(*msi_hash), GFP_KERNEL);
         if (!msi_hash)
                 return -ENOMEM;
 
-        for (i = 0; i < (1U << msihash_shift); i++)
+        for (i = 0; i < MSI_HASH_BUCKETS; i++)
                 INIT_HLIST_HEAD(&msi_hash[i]);
         return 0;
 }
diff --git a/arch/score/kernel/process.c b/arch/score/kernel/process.c
index 79568466b578..f4c6d02421d3 100644
--- a/arch/score/kernel/process.c
+++ b/arch/score/kernel/process.c
@@ -41,24 +41,6 @@ void machine_halt(void) {}
 /* If or when software machine-power-off is implemented, add code here. */
 void machine_power_off(void) {}
 
-/*
- * The idle thread. There's no useful work to be
- * done, so just try to conserve power and have a
- * low exit latency (ie sit in a loop waiting for
- * somebody to say that they'd like to reschedule)
- */
-void __noreturn cpu_idle(void)
-{
-        /* endless idle loop with no priority at all */
-        while (1) {
-                rcu_idle_enter();
-                while (!need_resched())
-                        barrier();
-                rcu_idle_exit();
-                schedule_preempt_disabled();
-        }
-}
-
 void ret_from_fork(void);
 void ret_from_kernel_thread(void);
 
diff --git a/arch/score/kernel/traps.c b/arch/score/kernel/traps.c
index 0e46fb19a848..1517a7dcd6d9 100644
--- a/arch/score/kernel/traps.c
+++ b/arch/score/kernel/traps.c
@@ -117,6 +117,8 @@ static void show_code(unsigned int *pc)
  */
 void show_regs(struct pt_regs *regs)
 {
+        show_regs_print_info(KERN_DEFAULT);
+
         printk("r0 : %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
                 regs->regs[0], regs->regs[1], regs->regs[2], regs->regs[3],
                 regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]);
@@ -149,16 +151,6 @@ static void show_registers(struct pt_regs *regs)
         printk(KERN_NOTICE "\n");
 }
 
-/*
- * The architecture-independent dump_stack generator
- */
-void dump_stack(void)
-{
-        show_stack(current_thread_info()->task,
-                   (long *) get_irq_regs()->regs[0]);
-}
-EXPORT_SYMBOL(dump_stack);
-
 void __die(const char *str, struct pt_regs *regs, const char *file,
         const char *func, unsigned long line)
 {
diff --git a/arch/score/mm/init.c b/arch/score/mm/init.c
index cee6bce1e30c..d8f988a37d16 100644
--- a/arch/score/mm/init.c
+++ b/arch/score/mm/init.c
@@ -31,7 +31,7 @@
 #include <linux/mm.h>
 #include <linux/mman.h>
 #include <linux/pagemap.h>
-#include <linux/proc_fs.h>
+#include <linux/kcore.h>
 #include <linux/sched.h>
 #include <linux/initrd.h>
 
@@ -43,7 +43,7 @@ EXPORT_SYMBOL_GPL(empty_zero_page);
 
 static struct kcore_list kcore_mem, kcore_vmalloc;
 
-static unsigned long setup_zero_page(void)
+static void setup_zero_page(void)
 {
         struct page *page;
 
@@ -52,9 +52,7 @@ static unsigned long setup_zero_page(void)
                 panic("Oh boy, that early out of memory?");
 
         page = virt_to_page((void *) empty_zero_page);
-        SetPageReserved(page);
-
-        return 1UL;
+        mark_page_reserved(page);
 }
 
 #ifndef CONFIG_NEED_MULTIPLE_NODES
@@ -84,7 +82,7 @@ void __init mem_init(void)
 
         high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
         totalram_pages += free_all_bootmem();
-        totalram_pages -= setup_zero_page();    /* Setup zeroed pages. */
+        setup_zero_page();      /* Setup zeroed pages. */
         reservedpages = 0;
 
         for (tmp = 0; tmp < max_low_pfn; tmp++)
@@ -109,37 +107,16 @@ void __init mem_init(void)
 }
 #endif /* !CONFIG_NEED_MULTIPLE_NODES */
 
-static void free_init_pages(const char *what, unsigned long begin, unsigned long end)
-{
-        unsigned long pfn;
-
-        for (pfn = PFN_UP(begin); pfn < PFN_DOWN(end); pfn++) {
-                struct page *page = pfn_to_page(pfn);
-                void *addr = phys_to_virt(PFN_PHYS(pfn));
-
-                ClearPageReserved(page);
-                init_page_count(page);
-                memset(addr, POISON_FREE_INITMEM, PAGE_SIZE);
-                __free_page(page);
-                totalram_pages++;
-        }
-        printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
-}
-
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_init_pages("initrd memory",
-                virt_to_phys((void *) start),
-                virt_to_phys((void *) end));
+        free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
 }
 #endif
 
 void __init_refok free_initmem(void)
 {
-        free_init_pages("unused kernel memory",
-        __pa(&__init_begin),
-        __pa(&__init_end));
+        free_initmem_default(POISON_FREE_INITMEM);
 }
 
 unsigned long pgd_current;
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 5e859633ce69..78d8ace57272 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -33,6 +33,7 @@ config SUPERH
         select GENERIC_ATOMIC64
         select GENERIC_IRQ_SHOW
         select GENERIC_SMP_IDLE_THREAD
+        select GENERIC_IDLE_POLL_SETUP
         select GENERIC_CLOCKEVENTS
         select GENERIC_CMOS_UPDATE if SH_SH03 || SH_DREAMCAST
         select GENERIC_STRNCPY_FROM_USER
@@ -148,9 +149,6 @@ config ARCH_HAS_ILOG2_U32
 config ARCH_HAS_ILOG2_U64
         def_bool n
 
-config ARCH_HAS_DEFAULT_IDLE
-        def_bool y
-
 config NO_IOPORT
         def_bool !PCI
         depends on !SH_CAYMAN && !SH_SH4202_MICRODEV && !SH_SHMIN && \
@@ -624,25 +622,7 @@ config SH_CLK_CPG_LEGACY
 endmenu
 
 menu "CPU Frequency scaling"
-
 source "drivers/cpufreq/Kconfig"
-
-config SH_CPU_FREQ
-        tristate "SuperH CPU Frequency driver"
-        depends on CPU_FREQ
-        select CPU_FREQ_TABLE
-        help
-          This adds the cpufreq driver for SuperH. Any CPU that supports
-          clock rate rounding through the clock framework can use this
-          driver. While it will make the kernel slightly larger, this is
-          harmless for CPUs that don't support rate rounding. The driver
-          will also generate a notice in the boot log before disabling
-          itself if the CPU in question is not capable of rate rounding.
-
-          For details, take a look at <file:Documentation/cpu-freq>.
-
-          If unsure, say N.
-
 endmenu
 
 source "arch/sh/drivers/Kconfig"
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index aaff7671101b..764530c85aa9 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -254,11 +254,13 @@ static int usbhs_get_id(struct platform_device *pdev)
         return gpio_get_value(GPIO_PTB3);
 }
 
-static void usbhs_phy_reset(struct platform_device *pdev)
+static int usbhs_phy_reset(struct platform_device *pdev)
 {
         /* enable vbus if HOST */
         if (!gpio_get_value(GPIO_PTB3))
                 gpio_set_value(GPIO_PTB5, 1);
+
+        return 0;
 }
 
 static struct renesas_usbhs_platform_info usbhs_info = {
diff --git a/arch/sh/drivers/dma/dma-api.c b/arch/sh/drivers/dma/dma-api.c
index f46848f088e4..c0eec08d8f95 100644
--- a/arch/sh/drivers/dma/dma-api.c
+++ b/arch/sh/drivers/dma/dma-api.c
@@ -13,6 +13,7 @@
 #include <linux/module.h>
 #include <linux/spinlock.h>
 #include <linux/proc_fs.h>
+#include <linux/seq_file.h>
 #include <linux/list.h>
 #include <linux/platform_device.h>
 #include <linux/mm.h>
@@ -308,11 +309,9 @@ int dma_extend(unsigned int chan, unsigned long op, void *param)
 }
 EXPORT_SYMBOL(dma_extend);
 
-static int dma_read_proc(char *buf, char **start, off_t off,
-                         int len, int *eof, void *data)
+static int dma_proc_show(struct seq_file *m, void *v)
 {
-        struct dma_info *info;
-        char *p = buf;
+        struct dma_info *info = v;
 
         if (list_empty(&registered_dmac_list))
                 return 0;
@@ -332,14 +331,26 @@ static int dma_read_proc(char *buf, char **start, off_t off,
                         if (!(channel->flags & DMA_CONFIGURED))
                                 continue;
 
-                        p += sprintf(p, "%2d: %14s    %s\n", i,
-                                     info->name, channel->dev_id);
+                        seq_printf(m, "%2d: %14s    %s\n", i,
+                                   info->name, channel->dev_id);
                 }
         }
 
-        return p - buf;
+        return 0;
+}
+
+static int dma_proc_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, dma_proc_show, NULL);
 }
 
+static const struct file_operations dma_proc_fops = {
+        .open           = dma_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
 int register_dmac(struct dma_info *info)
 {
         unsigned int total_channels, i;
@@ -412,8 +423,7 @@ EXPORT_SYMBOL(unregister_dmac);
 static int __init dma_api_init(void)
 {
         printk(KERN_NOTICE "DMA: Registering DMA API.\n");
-        return create_proc_read_entry("dma", 0, 0, dma_read_proc, 0)
-                    ? 0 : -ENOMEM;
+        return proc_create("dma", 0, NULL, &dma_proc_fops) ? 0 : -ENOMEM;
 }
 subsys_initcall(dma_api_init);
 
diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index c2c85f6cd738..a162a7f86b2e 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -35,7 +35,7 @@ static unsigned int nr_ports;
 
 static struct sh7786_pcie_hwops {
         int (*core_init)(void);
-        async_func_ptr *port_init_hw;
+        async_func_t port_init_hw;
 } *sh7786_pcie_hwops;
 
 static struct resource sh7786_pci0_resources[] = {
diff --git a/arch/sh/include/asm/hugetlb.h b/arch/sh/include/asm/hugetlb.h
index b3808c7d67b2..699255d6d1c6 100644
--- a/arch/sh/include/asm/hugetlb.h
+++ b/arch/sh/include/asm/hugetlb.h
@@ -3,6 +3,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/page.h>
+#include <asm-generic/hugetlb.h>
 
 
 static inline int is_hugepage_only_range(struct mm_struct *mm,
diff --git a/arch/sh/include/asm/suspend.h b/arch/sh/include/asm/suspend.h
index e14567a7e9a1..70ae0b2888ab 100644
--- a/arch/sh/include/asm/suspend.h
+++ b/arch/sh/include/asm/suspend.h
@@ -14,9 +14,9 @@ struct swsusp_arch_regs {
 void sh_mobile_call_standby(unsigned long mode);
 
 #ifdef CONFIG_CPU_IDLE
-void sh_mobile_setup_cpuidle(void);
+int sh_mobile_setup_cpuidle(void);
 #else
-static inline void sh_mobile_setup_cpuidle(void) {}
+static inline int sh_mobile_setup_cpuidle(void) { return 0; }
 #endif
 
 /* notifier chains for pre/post sleep hooks */
diff --git a/arch/sh/include/asm/thread_info.h b/arch/sh/include/asm/thread_info.h
index 7d5ac4e48485..45a93669289d 100644
--- a/arch/sh/include/asm/thread_info.h
+++ b/arch/sh/include/asm/thread_info.h
@@ -207,8 +207,6 @@ static inline bool test_and_clear_restore_sigmask(void)
         return true;
 }
 
-#define tsk_is_polling(t) test_tsk_thread_flag(t, TIF_POLLING_NRFLAG)
-
 #endif  /* !__ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/arch/sh/include/asm/unistd.h b/arch/sh/include/asm/unistd.h
index 5e90fa2b7eed..e77816c4b9bc 100644
--- a/arch/sh/include/asm/unistd.h
+++ b/arch/sh/include/asm/unistd.h
@@ -30,12 +30,4 @@
 # define __ARCH_WANT_SYS_VFORK
 # define __ARCH_WANT_SYS_CLONE
 
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-# define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
-
 #include <uapi/asm/unistd.h>
diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile
index f259b37874e9..261c8bfd75ce 100644
--- a/arch/sh/kernel/Makefile
+++ b/arch/sh/kernel/Makefile
@@ -31,7 +31,6 @@ obj-$(CONFIG_VSYSCALL)		+= vsyscall/
 obj-$(CONFIG_SMP)               += smp.o
 obj-$(CONFIG_SH_STANDARD_BIOS)  += sh_bios.o
 obj-$(CONFIG_KGDB)              += kgdb.o
-obj-$(CONFIG_SH_CPU_FREQ)       += cpufreq.o
 obj-$(CONFIG_MODULES)           += sh_ksyms_$(BITS).o module.o
 obj-$(CONFIG_KEXEC)             += machine_kexec.o relocate_kernel.o
 obj-$(CONFIG_CRASH_DUMP)        += crash_dump.o
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
index 96c6c2634cb4..eef17dcc3a41 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
@@ -8,12 +8,23 @@
  * for more details.
  */
 
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7203_pfc_resources[] = {
+        [0] = {
+                .start  = 0xfffe3800,
+                .end    = 0xfffe3a9f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7203", NULL, 0);
+        return sh_pfc_register("pfc-sh7203", sh7203_pfc_resources,
+                               ARRAY_SIZE(sh7203_pfc_resources));
 }
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
index b1b7c1bae127..569decbd6d93 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
@@ -8,12 +8,23 @@
  * for more details.
  */
 
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7264_pfc_resources[] = {
+        [0] = {
+                .start  = 0xfffe3800,
+                .end    = 0xfffe393f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7264", NULL, 0);
+        return sh_pfc_register("pfc-sh7264", sh7264_pfc_resources,
+                               ARRAY_SIZE(sh7264_pfc_resources));
 }
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
index dc2a86830456..1825b0bd523d 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
@@ -13,8 +13,17 @@
 #include <linux/kernel.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7269_pfc_resources[] = {
+        [0] = {
+                .start  = 0xfffe3800,
+                .end    = 0xfffe391f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7269", NULL, 0);
+        return sh_pfc_register("pfc-sh7269", sh7269_pfc_resources,
+                               ARRAY_SIZE(sh7269_pfc_resources));
 }
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c b/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
index 7d3744ac7b08..26e90a66ebb7 100644
--- a/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
@@ -8,13 +8,23 @@
  * for more details.
  */
 
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7720_pfc_resources[] = {
+        [0] = {
+                .start  = 0xa4050100,
+                .end    = 0xa405016f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7720", NULL, 0);
+        return sh_pfc_register("pfc-sh7720", sh7720_pfc_resources,
+                               ARRAY_SIZE(sh7720_pfc_resources));
 }
-
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
index d9bcc4290997..271bbc864929 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
@@ -1,10 +1,20 @@
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7722_pfc_resources[] = {
+        [0] = {
+                .start  = 0xa4050100,
+                .end    = 0xa405018f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7722", NULL, 0);
+        return sh_pfc_register("pfc-sh7722", sh7722_pfc_resources,
+                               ARRAY_SIZE(sh7722_pfc_resources));
 }
-
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
index bcec7ad7f783..99c637d5bf7a 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
@@ -8,13 +8,23 @@
  * for more details.
  */
 
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7723_pfc_resources[] = {
+        [0] = {
+                .start  = 0xa4050100,
+                .end    = 0xa405016f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7723", NULL, 0);
+        return sh_pfc_register("pfc-sh7723", sh7723_pfc_resources,
+                               ARRAY_SIZE(sh7723_pfc_resources));
 }
-
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
index 5c3541d6aed8..63be4749e341 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
@@ -13,12 +13,23 @@
  * for more details.
  */
 
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7724_pfc_resources[] = {
+        [0] = {
+                .start  = 0xa4050100,
+                .end    = 0xa405016f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7724", NULL, 0);
+        return sh_pfc_register("pfc-sh7724", sh7724_pfc_resources,
+                               ARRAY_SIZE(sh7724_pfc_resources));
 }
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
index cda6bd177b8c..567745d44221 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
@@ -13,12 +13,23 @@
  * for more details.
  */
 
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7757_pfc_resources[] = {
+        [0] = {
+                .start  = 0xffec0000,
+                .end    = 0xffec008f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7757", NULL, 0);
+        return sh_pfc_register("pfc-sh7757", sh7757_pfc_resources,
+                               ARRAY_SIZE(sh7757_pfc_resources));
 }
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c
index 01055b809f64..e336ab8b5125 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c
@@ -8,13 +8,23 @@
  * for more details.
  */
 
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7785_pfc_resources[] = {
+        [0] = {
+                .start  = 0xffe70000,
+                .end    = 0xffe7008f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7785", NULL, 0);
+        return sh_pfc_register("pfc-sh7785", sh7785_pfc_resources,
+                               ARRAY_SIZE(sh7785_pfc_resources));
 }
-
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
index 3061778d55da..9a459556a2f7 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
@@ -13,13 +13,23 @@
  * for more details.
  */
 
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
+static struct resource sh7786_pfc_resources[] = {
+        [0] = {
+                .start  = 0xffcc0000,
+                .end    = 0xffcc008f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-sh7786", NULL, 0);
+        return sh_pfc_register("pfc-sh7786", sh7786_pfc_resources,
+                               ARRAY_SIZE(sh7786_pfc_resources));
 }
-
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
index ace84acc55ea..444bf25c60fa 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
@@ -7,12 +7,23 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  */
+#include <linux/bug.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/ioport.h>
 #include <cpu/pfc.h>
 
-static int __init shx3_pinmux_setup(void)
+static struct resource shx3_pfc_resources[] = {
+        [0] = {
+                .start  = 0xffc70000,
+                .end    = 0xffc7001f,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static int __init plat_pinmux_setup(void)
 {
-        return sh_pfc_register("pfc-shx3", NULL, 0);
+        return sh_pfc_register("pfc-shx3", shx3_pfc_resources,
+                               ARRAY_SIZE(shx3_pfc_resources));
 }
-arch_initcall(shx3_pinmux_setup);
+arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/shmobile/cpuidle.c b/arch/sh/kernel/cpu/shmobile/cpuidle.c
index 1ddc876d3b26..d30622592116 100644
--- a/arch/sh/kernel/cpu/shmobile/cpuidle.c
+++ b/arch/sh/kernel/cpu/shmobile/cpuidle.c
@@ -51,70 +51,53 @@ static int cpuidle_sleep_enter(struct cpuidle_device *dev,
         return k;
 }
 
-static struct cpuidle_device cpuidle_dev;
 static struct cpuidle_driver cpuidle_driver = {
-        .name                   = "sh_idle",
-        .owner                  = THIS_MODULE,
-        .en_core_tk_irqen       = 1,
+        .name   = "sh_idle",
+        .owner  = THIS_MODULE,
+        .states = {
+                {
+                        .exit_latency = 1,
+                        .target_residency = 1 * 2,
+                        .power_usage = 3,
+                        .flags = CPUIDLE_FLAG_TIME_VALID,
+                        .enter = cpuidle_sleep_enter,
+                        .name = "C1",
+                        .desc = "SuperH Sleep Mode",
+                },
+                {
+                        .exit_latency = 100,
+                        .target_residency = 1 * 2,
+                        .power_usage = 1,
+                        .flags = CPUIDLE_FLAG_TIME_VALID,
+                        .enter = cpuidle_sleep_enter,
+                        .name = "C2",
+                        .desc = "SuperH Sleep Mode [SF]",
+                        .disabled = true,
+                },
+                {
+                        .exit_latency = 2300,
+                        .target_residency = 1 * 2,
+                        .power_usage = 1,
+                        .flags = CPUIDLE_FLAG_TIME_VALID,
+                        .enter = cpuidle_sleep_enter,
+                        .name = "C3",
+                        .desc = "SuperH Mobile Standby Mode [SF]",
+                        .disabled = true,
+                },
+        },
+        .safe_state_index = 0,
+        .state_count = 3,
 };
 
-void sh_mobile_setup_cpuidle(void)
+int __init sh_mobile_setup_cpuidle(void)
 {
-        struct cpuidle_device *dev = &cpuidle_dev;
-        struct cpuidle_driver *drv = &cpuidle_driver;
-        struct cpuidle_state *state;
-        int i;
+        int ret;
 
+        if (sh_mobile_sleep_supported & SUSP_SH_SF)
+                cpuidle_driver.states[1].disabled = false;
 
-        for (i = 0; i < CPUIDLE_STATE_MAX; i++) {
-                drv->states[i].name[0] = '\0';
-                drv->states[i].desc[0] = '\0';
-        }
+        if (sh_mobile_sleep_supported & SUSP_SH_STANDBY)
+                cpuidle_driver.states[2].disabled = false;
 
-        i = CPUIDLE_DRIVER_STATE_START;
-
-        state = &drv->states[i++];
-        snprintf(state->name, CPUIDLE_NAME_LEN, "C1");
-        strncpy(state->desc, "SuperH Sleep Mode", CPUIDLE_DESC_LEN);
-        state->exit_latency = 1;
-        state->target_residency = 1 * 2;
-        state->power_usage = 3;
-        state->flags = 0;
-        state->flags |= CPUIDLE_FLAG_TIME_VALID;
-        state->enter = cpuidle_sleep_enter;
-
-        drv->safe_state_index = i-1;
-
-        if (sh_mobile_sleep_supported & SUSP_SH_SF) {
-                state = &drv->states[i++];
-                snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
-                strncpy(state->desc, "SuperH Sleep Mode [SF]",
-                        CPUIDLE_DESC_LEN);
-                state->exit_latency = 100;
-                state->target_residency = 1 * 2;
-                state->power_usage = 1;
-                state->flags = 0;
-                state->flags |= CPUIDLE_FLAG_TIME_VALID;
-                state->enter = cpuidle_sleep_enter;
-        }
-
-        if (sh_mobile_sleep_supported & SUSP_SH_STANDBY) {
-                state = &drv->states[i++];
-                snprintf(state->name, CPUIDLE_NAME_LEN, "C3");
-                strncpy(state->desc, "SuperH Mobile Standby Mode [SF]",
-                        CPUIDLE_DESC_LEN);
-                state->exit_latency = 2300;
-                state->target_residency = 1 * 2;
-                state->power_usage = 1;
-                state->flags = 0;
-                state->flags |= CPUIDLE_FLAG_TIME_VALID;
-                state->enter = cpuidle_sleep_enter;
-        }
-
-        drv->state_count = i;
-        dev->state_count = i;
-
-        cpuidle_register_driver(&cpuidle_driver);
-
-        cpuidle_register_device(dev);
+        return cpuidle_register(&cpuidle_driver);
 }
diff --git a/arch/sh/kernel/cpu/shmobile/pm.c b/arch/sh/kernel/cpu/shmobile/pm.c
index 08d27fac8d08..ac37b7234f85 100644
--- a/arch/sh/kernel/cpu/shmobile/pm.c
+++ b/arch/sh/kernel/cpu/shmobile/pm.c
@@ -150,8 +150,7 @@ static const struct platform_suspend_ops sh_pm_ops = {
 static int __init sh_pm_init(void)
 {
         suspend_set_ops(&sh_pm_ops);
-        sh_mobile_setup_cpuidle();
-        return 0;
+        return sh_mobile_setup_cpuidle();
 }
 
 late_initcall(sh_pm_init);
diff --git a/arch/sh/kernel/cpufreq.c b/arch/sh/kernel/cpufreq.c
deleted file mode 100644
index e68b45b6f3f9..000000000000
--- a/arch/sh/kernel/cpufreq.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * arch/sh/kernel/cpufreq.c
- *
- * cpufreq driver for the SuperH processors.
- *
- * Copyright (C) 2002 - 2012 Paul Mundt
- * Copyright (C) 2002 M. R. Brown
- *
- * Clock framework bits from arch/avr32/mach-at32ap/cpufreq.c
- *
- *   Copyright (C) 2004-2007 Atmel Corporation
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#define pr_fmt(fmt) "cpufreq: " fmt
-
-#include <linux/types.h>
-#include <linux/cpufreq.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/cpumask.h>
-#include <linux/cpu.h>
-#include <linux/smp.h>
-#include <linux/sched.h>        /* set_cpus_allowed() */
-#include <linux/clk.h>
-#include <linux/percpu.h>
-#include <linux/sh_clk.h>
-
-static DEFINE_PER_CPU(struct clk, sh_cpuclk);
-
-static unsigned int sh_cpufreq_get(unsigned int cpu)
-{
-        return (clk_get_rate(&per_cpu(sh_cpuclk, cpu)) + 500) / 1000;
-}
-
-/*
- * Here we notify other drivers of the proposed change and the final change.
- */
-static int sh_cpufreq_target(struct cpufreq_policy *policy,
-                             unsigned int target_freq,
-                             unsigned int relation)
-{
-        unsigned int cpu = policy->cpu;
-        struct clk *cpuclk = &per_cpu(sh_cpuclk, cpu);
-        cpumask_t cpus_allowed;
-        struct cpufreq_freqs freqs;
-        struct device *dev;
-        long freq;
-
-        if (!cpu_online(cpu))
-                return -ENODEV;
-
-        cpus_allowed = current->cpus_allowed;
-        set_cpus_allowed_ptr(current, cpumask_of(cpu));
-
-        BUG_ON(smp_processor_id() != cpu);
-
-        dev = get_cpu_device(cpu);
-
-        /* Convert target_freq from kHz to Hz */
-        freq = clk_round_rate(cpuclk, target_freq * 1000);
-
-        if (freq < (policy->min * 1000) || freq > (policy->max * 1000))
-                return -EINVAL;
-
-        dev_dbg(dev, "requested frequency %u Hz\n", target_freq * 1000);
-
-        freqs.cpu       = cpu;
-        freqs.old       = sh_cpufreq_get(cpu);
-        freqs.new       = (freq + 500) / 1000;
-        freqs.flags     = 0;
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-        set_cpus_allowed_ptr(current, &cpus_allowed);
-        clk_set_rate(cpuclk, freq);
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
-        dev_dbg(dev, "set frequency %lu Hz\n", freq);
-
-        return 0;
-}
-
-static int sh_cpufreq_verify(struct cpufreq_policy *policy)
-{
-        struct clk *cpuclk = &per_cpu(sh_cpuclk, policy->cpu);
-        struct cpufreq_frequency_table *freq_table;
-
-        freq_table = cpuclk->nr_freqs ? cpuclk->freq_table : NULL;
-        if (freq_table)
-                return cpufreq_frequency_table_verify(policy, freq_table);
-
-        cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
-                                     policy->cpuinfo.max_freq);
-
-        policy->min = (clk_round_rate(cpuclk, 1) + 500) / 1000;
-        policy->max = (clk_round_rate(cpuclk, ~0UL) + 500) / 1000;
-
-        cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
-                                     policy->cpuinfo.max_freq);
-
-        return 0;
-}
-
-static int sh_cpufreq_cpu_init(struct cpufreq_policy *policy)
-{
-        unsigned int cpu = policy->cpu;
-        struct clk *cpuclk = &per_cpu(sh_cpuclk, cpu);
-        struct cpufreq_frequency_table *freq_table;
-        struct device *dev;
-
-        if (!cpu_online(cpu))
-                return -ENODEV;
-
-        dev = get_cpu_device(cpu);
-
-        cpuclk = clk_get(dev, "cpu_clk");
-        if (IS_ERR(cpuclk)) {
-                dev_err(dev, "couldn't get CPU clk\n");
-                return PTR_ERR(cpuclk);
-        }
-
-        policy->cur = policy->min = policy->max = sh_cpufreq_get(cpu);
-
-        freq_table = cpuclk->nr_freqs ? cpuclk->freq_table : NULL;
-        if (freq_table) {
-                int result;
-
-                result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
-                if (!result)
-                        cpufreq_frequency_table_get_attr(freq_table, cpu);
-        } else {
-                dev_notice(dev, "no frequency table found, falling back "
-                           "to rate rounding.\n");
-
-                policy->cpuinfo.min_freq =
-                        (clk_round_rate(cpuclk, 1) + 500) / 1000;
-                policy->cpuinfo.max_freq =
-                        (clk_round_rate(cpuclk, ~0UL) + 500) / 1000;
-        }
-
-        policy->min = policy->cpuinfo.min_freq;
-        policy->max = policy->cpuinfo.max_freq;
-
-        policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
-
-        dev_info(dev, "CPU Frequencies - Minimum %u.%03u MHz, "
-               "Maximum %u.%03u MHz.\n",
-               policy->min / 1000, policy->min % 1000,
-               policy->max / 1000, policy->max % 1000);
-
-        return 0;
-}
-
-static int sh_cpufreq_cpu_exit(struct cpufreq_policy *policy)
-{
-        unsigned int cpu = policy->cpu;
-        struct clk *cpuclk = &per_cpu(sh_cpuclk, cpu);
-
-        cpufreq_frequency_table_put_attr(cpu);
-        clk_put(cpuclk);
-
-        return 0;
-}
-
-static struct freq_attr *sh_freq_attr[] = {
-        &cpufreq_freq_attr_scaling_available_freqs,
-        NULL,
-};
-
-static struct cpufreq_driver sh_cpufreq_driver = {
-        .owner          = THIS_MODULE,
-        .name           = "sh",
-        .get            = sh_cpufreq_get,
-        .target         = sh_cpufreq_target,
-        .verify         = sh_cpufreq_verify,
-        .init           = sh_cpufreq_cpu_init,
-        .exit           = sh_cpufreq_cpu_exit,
-        .attr           = sh_freq_attr,
-};
-
-static int __init sh_cpufreq_module_init(void)
-{
-        pr_notice("SuperH CPU frequency driver.\n");
-        return cpufreq_register_driver(&sh_cpufreq_driver);
-}
-
-static void __exit sh_cpufreq_module_exit(void)
-{
-        cpufreq_unregister_driver(&sh_cpufreq_driver);
-}
-
-module_init(sh_cpufreq_module_init);
-module_exit(sh_cpufreq_module_exit);
-
-MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>");
-MODULE_DESCRIPTION("cpufreq driver for SuperH");
-MODULE_LICENSE("GPL");
diff --git a/arch/sh/kernel/dumpstack.c b/arch/sh/kernel/dumpstack.c
index 7617dc4129ac..b959f5592604 100644
--- a/arch/sh/kernel/dumpstack.c
+++ b/arch/sh/kernel/dumpstack.c
@@ -158,9 +158,3 @@ void show_stack(struct task_struct *tsk, unsigned long *sp)
                  (unsigned long)task_stack_page(tsk));
         show_trace(tsk, sp, NULL);
 }
-
-void dump_stack(void)
-{
-        show_stack(NULL, NULL);
-}
-EXPORT_SYMBOL(dump_stack);
diff --git a/arch/sh/kernel/idle.c b/arch/sh/kernel/idle.c
index 3d5a1b387cc0..2ea4483fd722 100644
--- a/arch/sh/kernel/idle.c
+++ b/arch/sh/kernel/idle.c
@@ -24,98 +24,24 @@
 
 static void (*sh_idle)(void);
 
-static int hlt_counter;
-
-static int __init nohlt_setup(char *__unused)
-{
-        hlt_counter = 1;
-        return 1;
-}
-__setup("nohlt", nohlt_setup);
-
-static int __init hlt_setup(char *__unused)
-{
-        hlt_counter = 0;
-        return 1;
-}
-__setup("hlt", hlt_setup);
-
-static inline int hlt_works(void)
-{
-        return !hlt_counter;
-}
-
-/*
- * On SMP it's slightly faster (but much more power-consuming!)
- * to poll the ->work.need_resched flag instead of waiting for the
- * cross-CPU IPI to arrive. Use this option with caution.
- */
-static void poll_idle(void)
+void default_idle(void)
 {
+        set_bl_bit();
         local_irq_enable();
-        while (!need_resched())
-                cpu_relax();
+        /* Isn't this racy ? */
+        cpu_sleep();
+        clear_bl_bit();
 }
 
-void default_idle(void)
+void arch_cpu_idle_dead(void)
 {
-        if (hlt_works()) {
-                clear_thread_flag(TIF_POLLING_NRFLAG);
-                smp_mb__after_clear_bit();
-
-                set_bl_bit();
-                if (!need_resched()) {
-                        local_irq_enable();
-                        cpu_sleep();
-                } else
-                        local_irq_enable();
-
-                set_thread_flag(TIF_POLLING_NRFLAG);
-                clear_bl_bit();
-        } else
-                poll_idle();
+        play_dead();
 }
 
-/*
- * The idle thread. There's no useful work to be done, so just try to conserve
- * power and have a low exit latency (ie sit in a loop waiting for somebody to
- * say that they'd like to reschedule)
- */
-void cpu_idle(void)
+void arch_cpu_idle(void)
 {
-        unsigned int cpu = smp_processor_id();
-
-        set_thread_flag(TIF_POLLING_NRFLAG);
-
-        /* endless idle loop with no priority at all */
-        while (1) {
-                tick_nohz_idle_enter();
-                rcu_idle_enter();
-
-                while (!need_resched()) {
-                        check_pgt_cache();
-                        rmb();
-
-                        if (cpu_is_offline(cpu))
-                                play_dead();
-
-                        local_irq_disable();
-                        /* Don't trace irqs off for idle */
-                        stop_critical_timings();
-                        if (cpuidle_idle_call())
-                                sh_idle();
-                        /*
-                         * Sanity check to ensure that sh_idle() returns
-                         * with IRQs enabled
-                         */
-                        WARN_ON(irqs_disabled());
-                        start_critical_timings();
-                }
-
-                rcu_idle_exit();
-                tick_nohz_idle_exit();
-                schedule_preempt_disabled();
-        }
+        if (cpuidle_idle_call())
+                sh_idle();
 }
 
 void __init select_idle_routine(void)
@@ -123,13 +49,8 @@ void __init select_idle_routine(void)
         /*
          * If a platform has set its own idle routine, leave it alone.
          */
-        if (sh_idle)
-                return;
-
-        if (hlt_works())
+        if (!sh_idle)
                 sh_idle = default_idle;
-        else
-                sh_idle = poll_idle;
 }
 
 void stop_this_cpu(void *unused)
diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c
index 73eb66fc6253..ebd3933005b4 100644
--- a/arch/sh/kernel/process_32.c
+++ b/arch/sh/kernel/process_32.c
@@ -32,11 +32,7 @@
 void show_regs(struct pt_regs * regs)
 {
         printk("\n");
-        printk("Pid : %d, Comm: \t\t%s\n", task_pid_nr(current), current->comm);
-        printk("CPU : %d        \t\t%s  (%s %.*s)\n\n",
-               smp_processor_id(), print_tainted(), init_utsname()->release,
-               (int)strcspn(init_utsname()->version, " "),
-               init_utsname()->version);
+        show_regs_print_info(KERN_DEFAULT);
 
         print_symbol("PC is at %s\n", instruction_pointer(regs));
         print_symbol("PR is at %s\n", regs->pr);
diff --git a/arch/sh/kernel/process_64.c b/arch/sh/kernel/process_64.c
index e611c85144b1..174d124b419e 100644
--- a/arch/sh/kernel/process_64.c
+++ b/arch/sh/kernel/process_64.c
@@ -40,6 +40,7 @@ void show_regs(struct pt_regs *regs)
         unsigned long long ah, al, bh, bl, ch, cl;
 
         printk("\n");
+        show_regs_print_info(KERN_DEFAULT);
 
         ah = (regs->pc) >> 32;
         al = (regs->pc) & 0xffffffff;
diff --git a/arch/sh/kernel/sh_bios.c b/arch/sh/kernel/sh_bios.c
index 47475cca068a..fe584e516964 100644
--- a/arch/sh/kernel/sh_bios.c
+++ b/arch/sh/kernel/sh_bios.c
@@ -104,6 +104,7 @@ void sh_bios_vbr_reload(void)
                 );
 }
 
+#ifdef CONFIG_EARLY_PRINTK
 /*
  *      Print a string through the BIOS
  */
@@ -144,8 +145,6 @@ static struct console bios_console = {
         .index          = -1,
 };
 
-static struct console *early_console;
-
 static int __init setup_early_printk(char *buf)
 {
         int keep_early = 0;
@@ -170,3 +169,4 @@ static int __init setup_early_printk(char *buf)
         return 0;
 }
 early_param("earlyprintk", setup_early_printk);
+#endif
diff --git a/arch/sh/kernel/smp.c b/arch/sh/kernel/smp.c
index 2062aa88af41..45696451f0ea 100644
--- a/arch/sh/kernel/smp.c
+++ b/arch/sh/kernel/smp.c
@@ -203,7 +203,7 @@ asmlinkage void __cpuinit start_secondary(void)
         set_cpu_online(cpu, true);
         per_cpu(cpu_state, cpu) = CPU_ONLINE;
 
-        cpu_idle();
+        cpu_startup_entry(CPUHP_ONLINE);
 }
 
 extern struct {
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 5a43a871e097..dba285e86808 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -137,13 +137,6 @@ config ARCH_SPARSEMEM_ENABLE
 config ARCH_SPARSEMEM_DEFAULT
         def_bool y
 
-config MAX_ACTIVE_REGIONS
-        int
-        default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
-        default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \
-                       CPU_SUBTYPE_SH7785)
-        default "1"
-
 config ARCH_SELECT_MEMORY_MODEL
         def_bool y
 
diff --git a/arch/sh/mm/alignment.c b/arch/sh/mm/alignment.c
index aea14855e656..ec2b25302427 100644
--- a/arch/sh/mm/alignment.c
+++ b/arch/sh/mm/alignment.c
@@ -140,7 +140,7 @@ static int alignment_proc_open(struct inode *inode, struct file *file)
 static ssize_t alignment_proc_write(struct file *file,
                 const char __user *buffer, size_t count, loff_t *pos)
 {
-        int *data = PDE(file_inode(file))->data;
+        int *data = PDE_DATA(file_inode(file));
         char mode;
 
         if (count > 0) {
diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c
index 105794037143..20f9ead650d3 100644
--- a/arch/sh/mm/init.c
+++ b/arch/sh/mm/init.c
@@ -417,15 +417,13 @@ void __init mem_init(void)
 
         for_each_online_node(nid) {
                 pg_data_t *pgdat = NODE_DATA(nid);
-                unsigned long node_pages = 0;
                 void *node_high_memory;
 
                 num_physpages += pgdat->node_present_pages;
 
                 if (pgdat->node_spanned_pages)
-                        node_pages = free_all_bootmem_node(pgdat);
+                        totalram_pages += free_all_bootmem_node(pgdat);
 
-                totalram_pages += node_pages;
 
                 node_high_memory = (void *)__va((pgdat->node_start_pfn +
                                                  pgdat->node_spanned_pages) <<
@@ -501,31 +499,13 @@ void __init mem_init(void)
 
 void free_initmem(void)
 {
-        unsigned long addr;
-
-        addr = (unsigned long)(&__init_begin);
-        for (; addr < (unsigned long)(&__init_end); addr += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(addr));
-                init_page_count(virt_to_page(addr));
-                free_page(addr);
-                totalram_pages++;
-        }
-        printk("Freeing unused kernel memory: %ldk freed\n",
-               ((unsigned long)&__init_end -
-                (unsigned long)&__init_begin) >> 10);
+        free_initmem_default(0);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        unsigned long p;
-        for (p = start; p < end; p += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(p));
-                init_page_count(virt_to_page(p));
-                free_page(p);
-                totalram_pages++;
-        }
-        printk("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
+        free_reserved_area(start, end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 3d361f236308..a639c0d07b8b 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -62,7 +62,6 @@ config SPARC64
         select HAVE_RCU_TABLE_FREE if SMP
         select HAVE_MEMBLOCK
         select HAVE_MEMBLOCK_NODE_MAP
-        select HAVE_SYSCALL_WRAPPERS
         select HAVE_ARCH_TRANSPARENT_HUGEPAGE
         select HAVE_DYNAMIC_FTRACE
         select HAVE_FTRACE_MCOUNT_RECORD
@@ -100,6 +99,9 @@ config HAVE_LATENCYTOP_SUPPORT
         bool
         default y if SPARC64
 
+config ARCH_HIBERNATION_POSSIBLE
+        def_bool y if SPARC64
+
 config AUDIT_ARCH
         bool
         default y
@@ -254,29 +256,6 @@ config HOTPLUG_CPU
 
 if SPARC64
 source "drivers/cpufreq/Kconfig"
-
-config US3_FREQ
-        tristate "UltraSPARC-III CPU Frequency driver"
-        depends on CPU_FREQ
-        select CPU_FREQ_TABLE
-        help
-          This adds the CPUFreq driver for UltraSPARC-III processors.
-
-          For details, take a look at <file:Documentation/cpu-freq>.
-
-          If in doubt, say N.
-
-config US2E_FREQ
-        tristate "UltraSPARC-IIe CPU Frequency driver"
-        depends on CPU_FREQ
-        select CPU_FREQ_TABLE
-        help
-          This adds the CPUFreq driver for UltraSPARC-IIe processors.
-
-          For details, take a look at <file:Documentation/cpu-freq>.
-
-          If in doubt, say N.
-
 endif
 
 config US3_MC
@@ -327,6 +306,10 @@ config ARCH_SPARSEMEM_DEFAULT
 
 source "mm/Kconfig"
 
+if SPARC64
+source "kernel/power/Kconfig"
+endif
+
 config SCHED_SMT
         bool "SMT (Hyperthreading) scheduler support"
         depends on SPARC64 && SMP
@@ -407,6 +390,8 @@ config SERIAL_CONSOLE
 config SPARC_LEON
         bool "Sparc Leon processor family"
         depends on SPARC32
+        select USB_EHCI_BIG_ENDIAN_MMIO
+        select USB_EHCI_BIG_ENDIAN_DESC
         ---help---
           If you say Y here if you are running on a SPARC-LEON processor.
           The LEON processor is a synthesizable VHDL model of the
@@ -494,7 +479,18 @@ config LEON_PCI
         depends on PCI && SPARC_LEON
         default y
 
-config GRPCI2
+config SPARC_GRPCI1
+        bool "GRPCI Host Bridge Support"
+        depends on LEON_PCI
+        default y
+        help
+          Say Y here to include the GRPCI Host Bridge Driver. The GRPCI
+          PCI host controller is typically found in GRLIB SPARC32/LEON
+          systems. The driver has one property (all_pci_errors) controlled
+          from the bootloader that makes the GRPCI to generate interrupts
+          on detected PCI Parity and System errors.
+
+config SPARC_GRPCI2
         bool "GRPCI2 Host Bridge Support"
         depends on LEON_PCI
         default y
diff --git a/arch/sparc/Makefile b/arch/sparc/Makefile
index 541b8b075c7d..9ff423678cbc 100644
--- a/arch/sparc/Makefile
+++ b/arch/sparc/Makefile
@@ -57,6 +57,7 @@ core-y                 += arch/sparc/
 libs-y                 += arch/sparc/prom/
 libs-y                 += arch/sparc/lib/
 
+drivers-$(CONFIG_PM) += arch/sparc/power/
 drivers-$(CONFIG_OPROFILE)      += arch/sparc/oprofile/
 
 boot := arch/sparc/boot
diff --git a/arch/sparc/include/asm/cmpxchg_64.h b/arch/sparc/include/asm/cmpxchg_64.h
index b30eb37294c5..4adefe8e2885 100644
--- a/arch/sparc/include/asm/cmpxchg_64.h
+++ b/arch/sparc/include/asm/cmpxchg_64.h
@@ -141,5 +141,6 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr,
         BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
         cmpxchg_local((ptr), (o), (n));                                 \
   })
+#define cmpxchg64(ptr, o, n)    cmpxchg64_local((ptr), (o), (n))
 
 #endif /* __ARCH_SPARC64_CMPXCHG__ */
diff --git a/arch/sparc/include/asm/head_32.h b/arch/sparc/include/asm/head_32.h
index a76874838f61..5f1dbe315bc8 100644
--- a/arch/sparc/include/asm/head_32.h
+++ b/arch/sparc/include/asm/head_32.h
@@ -55,15 +55,15 @@
 
 /* The Get Condition Codes software trap for userland. */
 #define GETCC_TRAP \
-        b getcc_trap_handler; mov %psr, %l0; nop; nop;
+        b getcc_trap_handler; rd %psr, %l0; nop; nop;
 
 /* The Set Condition Codes software trap for userland. */
 #define SETCC_TRAP \
-        b setcc_trap_handler; mov %psr, %l0; nop; nop;
+        b setcc_trap_handler; rd %psr, %l0; nop; nop;
 
 /* The Get PSR software trap for userland. */
 #define GETPSR_TRAP \
-        mov %psr, %i0; jmp %l2; rett %l2 + 4; nop;
+        rd %psr, %i0; jmp %l2; rett %l2 + 4; nop;
 
 /* This is for hard interrupts from level 1-14, 15 is non-maskable (nmi) and
  * gets handled with another macro.
diff --git a/arch/sparc/include/asm/hibernate.h b/arch/sparc/include/asm/hibernate.h
new file mode 100644
index 000000000000..2ec34f842249
--- /dev/null
+++ b/arch/sparc/include/asm/hibernate.h
@@ -0,0 +1,23 @@
+/*
+ * hibernate.h:  Hibernaton support specific for sparc64.
+ *
+ * Copyright (C) 2013 Kirill V Tkhai (tkhai@yandex.ru)
+ */
+
+#ifndef ___SPARC_HIBERNATE_H
+#define ___SPARC_HIBERNATE_H
+
+struct saved_context {
+        unsigned long fp;
+        unsigned long cwp;
+        unsigned long wstate;
+
+        unsigned long tick;
+        unsigned long pstate;
+
+        unsigned long g4;
+        unsigned long g5;
+        unsigned long g6;
+};
+
+#endif
diff --git a/arch/sparc/include/asm/hugetlb.h b/arch/sparc/include/asm/hugetlb.h
index 7eb57d245044..e4cab465b81f 100644
--- a/arch/sparc/include/asm/hugetlb.h
+++ b/arch/sparc/include/asm/hugetlb.h
@@ -2,6 +2,7 @@
 #define _ASM_SPARC64_HUGETLB_H
 
 #include <asm/page.h>
+#include <asm-generic/hugetlb.h>
 
 
 void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
diff --git a/arch/sparc/include/asm/leon_pci.h b/arch/sparc/include/asm/leon_pci.h
index f48527ebdd8f..bfd3ab3092b5 100644
--- a/arch/sparc/include/asm/leon_pci.h
+++ b/arch/sparc/include/asm/leon_pci.h
@@ -12,6 +12,7 @@ struct leon_pci_info {
         struct pci_ops *ops;
         struct resource io_space;
         struct resource mem_space;
+        struct resource busn;
         int (*map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
 };
 
diff --git a/arch/sparc/include/asm/mmu_context_64.h b/arch/sparc/include/asm/mmu_context_64.h
index 9191ca62ed9c..3d528f06e4b0 100644
--- a/arch/sparc/include/asm/mmu_context_64.h
+++ b/arch/sparc/include/asm/mmu_context_64.h
@@ -68,7 +68,7 @@ extern void smp_tsb_sync(struct mm_struct *mm);
 
 extern void __flush_tlb_mm(unsigned long, unsigned long);
 
-/* Switch the current MM context.  Interrupts are disabled.  */
+/* Switch the current MM context. */
 static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk)
 {
         unsigned long ctx_valid, flags;
diff --git a/arch/sparc/include/asm/processor_64.h b/arch/sparc/include/asm/processor_64.h
index cce72ce4c334..4c3f7f01c709 100644
--- a/arch/sparc/include/asm/processor_64.h
+++ b/arch/sparc/include/asm/processor_64.h
@@ -18,9 +18,6 @@
 #include <asm/ptrace.h>
 #include <asm/page.h>
 
-/* Don't hold the runqueue lock over context switch */
-#define __ARCH_WANT_UNLOCKED_CTXSW
-
 /* The sparc has no problems with write protection */
 #define wp_works_ok 1
 #define wp_works_ok__is_a_macro /* for versions in ksyms.c */
diff --git a/arch/sparc/include/asm/thread_info_32.h b/arch/sparc/include/asm/thread_info_32.h
index 25849ae3e900..dd3807599bb9 100644
--- a/arch/sparc/include/asm/thread_info_32.h
+++ b/arch/sparc/include/asm/thread_info_32.h
@@ -132,8 +132,6 @@ register struct thread_info *current_thread_info_reg asm("g6");
 #define _TIF_DO_NOTIFY_RESUME_MASK      (_TIF_NOTIFY_RESUME | \
                                          _TIF_SIGPENDING)
 
-#define tsk_is_polling(t) test_tsk_thread_flag(t, TIF_POLLING_NRFLAG)
-
 #endif /* __KERNEL__ */
 
 #endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/sparc/include/asm/thread_info_64.h b/arch/sparc/include/asm/thread_info_64.h
index 269bd92313df..d5e504251079 100644
--- a/arch/sparc/include/asm/thread_info_64.h
+++ b/arch/sparc/include/asm/thread_info_64.h
@@ -256,8 +256,6 @@ static inline bool test_and_clear_restore_sigmask(void)
         return true;
 }
 
-#define tsk_is_polling(t) test_tsk_thread_flag(t, TIF_POLLING_NRFLAG)
-
 #define thread32_stack_is_64bit(__SP) (((__SP) & 0x1) != 0)
 #define test_thread_64bit_stack(__SP) \
         ((test_thread_flag(TIF_32BIT) && !thread32_stack_is_64bit(__SP)) ? \
diff --git a/arch/sparc/include/asm/unistd.h b/arch/sparc/include/asm/unistd.h
index 5356810bd7e7..dfa53fdd5cbc 100644
--- a/arch/sparc/include/asm/unistd.h
+++ b/arch/sparc/include/asm/unistd.h
@@ -45,12 +45,4 @@
 #define __ARCH_WANT_COMPAT_SYS_SENDFILE
 #endif
 
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
-
 #endif /* _SPARC_UNISTD_H */
diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile
index 6cf591b7e1c6..d432fb20358e 100644
--- a/arch/sparc/kernel/Makefile
+++ b/arch/sparc/kernel/Makefile
@@ -74,7 +74,8 @@ obj-y                     += dma.o
 
 obj-$(CONFIG_PCIC_PCI)    += pcic.o
 obj-$(CONFIG_LEON_PCI)    += leon_pci.o
-obj-$(CONFIG_GRPCI2)      += leon_pci_grpci2.o
+obj-$(CONFIG_SPARC_GRPCI2)+= leon_pci_grpci2.o
+obj-$(CONFIG_SPARC_GRPCI1)+= leon_pci_grpci1.o
 
 obj-$(CONFIG_SMP)         += trampoline_$(BITS).o smp_$(BITS).o
 obj-$(CONFIG_SPARC32_SMP) += sun4m_smp.o sun4d_smp.o leon_smp.o
@@ -102,9 +103,6 @@ obj-$(CONFIG_PCI_MSI)        += pci_msi.o
 
 obj-$(CONFIG_COMPAT)         += sys32.o sys_sparc32.o signal32.o
 
-# sparc64 cpufreq
-obj-$(CONFIG_US3_FREQ)  += us3_cpufreq.o
-obj-$(CONFIG_US2E_FREQ) += us2e_cpufreq.o
 obj-$(CONFIG_US3_MC)    += chmc.o
 
 obj-$(CONFIG_KPROBES)   += kprobes.o
diff --git a/arch/sparc/kernel/asm-offsets.c b/arch/sparc/kernel/asm-offsets.c
index 68f7e1118e9b..961b87f99e69 100644
--- a/arch/sparc/kernel/asm-offsets.c
+++ b/arch/sparc/kernel/asm-offsets.c
@@ -14,6 +14,8 @@
 // #include <linux/mm.h>
 #include <linux/kbuild.h>
 
+#include <asm/hibernate.h>
+
 #ifdef CONFIG_SPARC32
 int sparc32_foo(void)
 {
@@ -24,6 +26,19 @@ int sparc32_foo(void)
 #else
 int sparc64_foo(void)
 {
+#ifdef CONFIG_HIBERNATION
+        BLANK();
+        OFFSET(SC_REG_FP, saved_context, fp);
+        OFFSET(SC_REG_CWP, saved_context, cwp);
+        OFFSET(SC_REG_WSTATE, saved_context, wstate);
+
+        OFFSET(SC_REG_TICK, saved_context, tick);
+        OFFSET(SC_REG_PSTATE, saved_context, pstate);
+
+        OFFSET(SC_REG_G4, saved_context, g4);
+        OFFSET(SC_REG_G5, saved_context, g5);
+        OFFSET(SC_REG_G6, saved_context, g6);
+#endif
         return 0;
 }
 #endif
diff --git a/arch/sparc/kernel/hvtramp.S b/arch/sparc/kernel/hvtramp.S
index 9365432904d6..605c960b2fa6 100644
--- a/arch/sparc/kernel/hvtramp.S
+++ b/arch/sparc/kernel/hvtramp.S
@@ -128,8 +128,7 @@ hv_cpu_startup:
 
         call            smp_callin
          nop
-        call            cpu_idle
-         mov            0, %o0
+
         call            cpu_panic
          nop
 
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c
index 0f094db918c7..2096468de9b2 100644
--- a/arch/sparc/kernel/ioport.c
+++ b/arch/sparc/kernel/ioport.c
@@ -693,7 +693,7 @@ static int sparc_io_proc_show(struct seq_file *m, void *v)
 
 static int sparc_io_proc_open(struct inode *inode, struct file *file)
 {
-        return single_open(file, sparc_io_proc_show, PDE(inode)->data);
+        return single_open(file, sparc_io_proc_show, PDE_DATA(inode));
 }
 
 static const struct file_operations sparc_io_proc_fops = {
diff --git a/arch/sparc/kernel/leon_kernel.c b/arch/sparc/kernel/leon_kernel.c
index 87f60ee65433..7c0231dabe44 100644
--- a/arch/sparc/kernel/leon_kernel.c
+++ b/arch/sparc/kernel/leon_kernel.c
@@ -213,6 +213,7 @@ unsigned int leon_build_device_irq(unsigned int real_irq,
 {
         unsigned int irq;
         unsigned long mask;
+        struct irq_desc *desc;
 
         irq = 0;
         mask = leon_get_irqmask(real_irq);
@@ -226,9 +227,12 @@ unsigned int leon_build_device_irq(unsigned int real_irq,
         if (do_ack)
                 mask |= LEON_DO_ACK_HW;
 
-        irq_set_chip_and_handler_name(irq, &leon_irq,
-                                      flow_handler, name);
-        irq_set_chip_data(irq, (void *)mask);
+        desc = irq_to_desc(irq);
+        if (!desc || !desc->handle_irq || desc->handle_irq == handle_bad_irq) {
+                irq_set_chip_and_handler_name(irq, &leon_irq,
+                                              flow_handler, name);
+                irq_set_chip_data(irq, (void *)mask);
+        }
 
 out:
         return irq;
diff --git a/arch/sparc/kernel/leon_pci.c b/arch/sparc/kernel/leon_pci.c
index 852dc8430528..88aaaa57bb64 100644
--- a/arch/sparc/kernel/leon_pci.c
+++ b/arch/sparc/kernel/leon_pci.c
@@ -29,6 +29,8 @@ void leon_pci_init(struct platform_device *ofdev, struct leon_pci_info *info)
         pci_add_resource_offset(&resources, &info->io_space,
                                 info->io_space.start - 0x1000);
         pci_add_resource(&resources, &info->mem_space);
+        info->busn.flags = IORESOURCE_BUS;
+        pci_add_resource(&resources, &info->busn);
 
         root_bus = pci_scan_root_bus(&ofdev->dev, 0, info->ops, info,
                                      &resources);
diff --git a/arch/sparc/kernel/leon_pci_grpci1.c b/arch/sparc/kernel/leon_pci_grpci1.c
new file mode 100644
index 000000000000..7739a54315e2
--- /dev/null
+++ b/arch/sparc/kernel/leon_pci_grpci1.c
@@ -0,0 +1,724 @@
+/*
+ * leon_pci_grpci1.c: GRPCI1 Host PCI driver
+ *
+ * Copyright (C) 2013 Aeroflex Gaisler AB
+ *
+ * This GRPCI1 driver does not support PCI interrupts taken from
+ * GPIO pins. Interrupt generation at PCI parity and system error
+ * detection is by default turned off since some GRPCI1 cores does
+ * not support detection. It can be turned on from the bootloader
+ * using the all_pci_errors property.
+ *
+ * Contributors: Daniel Hellstrom <daniel@gaisler.com>
+ */
+
+#include <linux/of_device.h>
+#include <linux/export.h>
+#include <linux/kernel.h>
+#include <linux/of_irq.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+
+#include <asm/leon_pci.h>
+#include <asm/sections.h>
+#include <asm/vaddrs.h>
+#include <asm/leon.h>
+#include <asm/io.h>
+
+#include "irq.h"
+
+/* Enable/Disable Debugging Configuration Space Access */
+#undef GRPCI1_DEBUG_CFGACCESS
+
+/*
+ * GRPCI1 APB Register MAP
+ */
+struct grpci1_regs {
+        unsigned int cfg_stat;          /* 0x00 Configuration / Status */
+        unsigned int bar0;              /* 0x04 BAR0 (RO) */
+        unsigned int page0;             /* 0x08 PAGE0 (RO) */
+        unsigned int bar1;              /* 0x0C BAR1 (RO) */
+        unsigned int page1;             /* 0x10 PAGE1 */
+        unsigned int iomap;             /* 0x14 IO Map */
+        unsigned int stat_cmd;          /* 0x18 PCI Status & Command (RO) */
+        unsigned int irq;               /* 0x1C Interrupt register */
+};
+
+#define REGLOAD(a)      (be32_to_cpu(__raw_readl(&(a))))
+#define REGSTORE(a, v)  (__raw_writel(cpu_to_be32(v), &(a)))
+
+#define PAGE0_BTEN_BIT    0
+#define PAGE0_BTEN        (1 << PAGE0_BTEN_BIT)
+
+#define CFGSTAT_HOST_BIT  13
+#define CFGSTAT_CTO_BIT   8
+#define CFGSTAT_HOST      (1 << CFGSTAT_HOST_BIT)
+#define CFGSTAT_CTO       (1 << CFGSTAT_CTO_BIT)
+
+#define IRQ_DPE (1 << 9)
+#define IRQ_SSE (1 << 8)
+#define IRQ_RMA (1 << 7)
+#define IRQ_RTA (1 << 6)
+#define IRQ_STA (1 << 5)
+#define IRQ_DPED (1 << 4)
+#define IRQ_INTD (1 << 3)
+#define IRQ_INTC (1 << 2)
+#define IRQ_INTB (1 << 1)
+#define IRQ_INTA (1 << 0)
+#define IRQ_DEF_ERRORS (IRQ_RMA | IRQ_RTA | IRQ_STA)
+#define IRQ_ALL_ERRORS (IRQ_DPED | IRQ_DEF_ERRORS | IRQ_SSE | IRQ_DPE)
+#define IRQ_INTX (IRQ_INTA | IRQ_INTB | IRQ_INTC | IRQ_INTD)
+#define IRQ_MASK_BIT 16
+
+#define DEF_PCI_ERRORS (PCI_STATUS_SIG_TARGET_ABORT | \
+                        PCI_STATUS_REC_TARGET_ABORT | \
+                        PCI_STATUS_REC_MASTER_ABORT)
+#define ALL_PCI_ERRORS (PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY | \
+                        PCI_STATUS_SIG_SYSTEM_ERROR | DEF_PCI_ERRORS)
+
+#define TGT 256
+
+struct grpci1_priv {
+        struct leon_pci_info    info; /* must be on top of this structure */
+        struct grpci1_regs      *regs;          /* GRPCI register map */
+        struct device           *dev;
+        int                     pci_err_mask;   /* STATUS register error mask */
+        int                     irq;            /* LEON irqctrl GRPCI IRQ */
+        unsigned char           irq_map[4];     /* GRPCI nexus PCI INTX# IRQs */
+        unsigned int            irq_err;        /* GRPCI nexus Virt Error IRQ */
+
+        /* AHB PCI Windows */
+        unsigned long           pci_area;       /* MEMORY */
+        unsigned long           pci_area_end;
+        unsigned long           pci_io;         /* I/O */
+        unsigned long           pci_conf;       /* CONFIGURATION */
+        unsigned long           pci_conf_end;
+        unsigned long           pci_io_va;
+};
+
+static struct grpci1_priv *grpci1priv;
+
+static int grpci1_cfg_w32(struct grpci1_priv *priv, unsigned int bus,
+                                unsigned int devfn, int where, u32 val);
+
+int grpci1_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        struct grpci1_priv *priv = dev->bus->sysdata;
+        int irq_group;
+
+        /* Use default IRQ decoding on PCI BUS0 according slot numbering */
+        irq_group = slot & 0x3;
+        pin = ((pin - 1) + irq_group) & 0x3;
+
+        return priv->irq_map[pin];
+}
+
+static int grpci1_cfg_r32(struct grpci1_priv *priv, unsigned int bus,
+                                unsigned int devfn, int where, u32 *val)
+{
+        u32 *pci_conf, tmp, cfg;
+
+        if (where & 0x3)
+                return -EINVAL;
+
+        if (bus == 0) {
+                devfn += (0x8 * 6); /* start at AD16=Device0 */
+        } else if (bus == TGT) {
+                bus = 0;
+                devfn = 0; /* special case: bridge controller itself */
+        }
+
+        /* Select bus */
+        cfg = REGLOAD(priv->regs->cfg_stat);
+        REGSTORE(priv->regs->cfg_stat, (cfg & ~(0xf << 23)) | (bus << 23));
+
+        /* do read access */
+        pci_conf = (u32 *) (priv->pci_conf | (devfn << 8) | (where & 0xfc));
+        tmp = LEON3_BYPASS_LOAD_PA(pci_conf);
+
+        /* check if master abort was received */
+        if (REGLOAD(priv->regs->cfg_stat) & CFGSTAT_CTO) {
+                *val = 0xffffffff;
+                /* Clear Master abort bit in PCI cfg space (is set) */
+                tmp = REGLOAD(priv->regs->stat_cmd);
+                grpci1_cfg_w32(priv, TGT, 0, PCI_COMMAND, tmp);
+        } else {
+                /* Bus always little endian (unaffected by byte-swapping) */
+                *val = flip_dword(tmp);
+        }
+
+        return 0;
+}
+
+static int grpci1_cfg_r16(struct grpci1_priv *priv, unsigned int bus,
+                                unsigned int devfn, int where, u32 *val)
+{
+        u32 v;
+        int ret;
+
+        if (where & 0x1)
+                return -EINVAL;
+        ret = grpci1_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
+        *val = 0xffff & (v >> (8 * (where & 0x3)));
+        return ret;
+}
+
+static int grpci1_cfg_r8(struct grpci1_priv *priv, unsigned int bus,
+                                unsigned int devfn, int where, u32 *val)
+{
+        u32 v;
+        int ret;
+
+        ret = grpci1_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
+        *val = 0xff & (v >> (8 * (where & 3)));
+
+        return ret;
+}
+
+static int grpci1_cfg_w32(struct grpci1_priv *priv, unsigned int bus,
+                                unsigned int devfn, int where, u32 val)
+{
+        unsigned int *pci_conf;
+        u32 cfg;
+
+        if (where & 0x3)
+                return -EINVAL;
+
+        if (bus == 0) {
+                devfn += (0x8 * 6); /* start at AD16=Device0 */
+        } else if (bus == TGT) {
+                bus = 0;
+                devfn = 0; /* special case: bridge controller itself */
+        }
+
+        /* Select bus */
+        cfg = REGLOAD(priv->regs->cfg_stat);
+        REGSTORE(priv->regs->cfg_stat, (cfg & ~(0xf << 23)) | (bus << 23));
+
+        pci_conf = (unsigned int *) (priv->pci_conf |
+                                                (devfn << 8) | (where & 0xfc));
+        LEON3_BYPASS_STORE_PA(pci_conf, flip_dword(val));
+
+        return 0;
+}
+
+static int grpci1_cfg_w16(struct grpci1_priv *priv, unsigned int bus,
+                                unsigned int devfn, int where, u32 val)
+{
+        int ret;
+        u32 v;
+
+        if (where & 0x1)
+                return -EINVAL;
+        ret = grpci1_cfg_r32(priv, bus, devfn, where&~3, &v);
+        if (ret)
+                return ret;
+        v = (v & ~(0xffff << (8 * (where & 0x3)))) |
+            ((0xffff & val) << (8 * (where & 0x3)));
+        return grpci1_cfg_w32(priv, bus, devfn, where & ~0x3, v);
+}
+
+static int grpci1_cfg_w8(struct grpci1_priv *priv, unsigned int bus,
+                                unsigned int devfn, int where, u32 val)
+{
+        int ret;
+        u32 v;
+
+        ret = grpci1_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
+        if (ret != 0)
+                return ret;
+        v = (v & ~(0xff << (8 * (where & 0x3)))) |
+            ((0xff & val) << (8 * (where & 0x3)));
+        return grpci1_cfg_w32(priv, bus, devfn, where & ~0x3, v);
+}
+
+/* Read from Configuration Space. When entering here the PCI layer has taken
+ * the pci_lock spinlock and IRQ is off.
+ */
+static int grpci1_read_config(struct pci_bus *bus, unsigned int devfn,
+                              int where, int size, u32 *val)
+{
+        struct grpci1_priv *priv = grpci1priv;
+        unsigned int busno = bus->number;
+        int ret;
+
+        if (PCI_SLOT(devfn) > 15 || busno > 15) {
+                *val = ~0;
+                return 0;
+        }
+
+        switch (size) {
+        case 1:
+                ret = grpci1_cfg_r8(priv, busno, devfn, where, val);
+                break;
+        case 2:
+                ret = grpci1_cfg_r16(priv, busno, devfn, where, val);
+                break;
+        case 4:
+                ret = grpci1_cfg_r32(priv, busno, devfn, where, val);
+                break;
+        default:
+                ret = -EINVAL;
+                break;
+        }
+
+#ifdef GRPCI1_DEBUG_CFGACCESS
+        printk(KERN_INFO
+                "grpci1_read_config: [%02x:%02x:%x] ofs=%d val=%x size=%d\n",
+                busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where, *val, size);
+#endif
+
+        return ret;
+}
+
+/* Write to Configuration Space. When entering here the PCI layer has taken
+ * the pci_lock spinlock and IRQ is off.
+ */
+static int grpci1_write_config(struct pci_bus *bus, unsigned int devfn,
+                               int where, int size, u32 val)
+{
+        struct grpci1_priv *priv = grpci1priv;
+        unsigned int busno = bus->number;
+
+        if (PCI_SLOT(devfn) > 15 || busno > 15)
+                return 0;
+
+#ifdef GRPCI1_DEBUG_CFGACCESS
+        printk(KERN_INFO
+                "grpci1_write_config: [%02x:%02x:%x] ofs=%d size=%d val=%x\n",
+                busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val);
+#endif
+
+        switch (size) {
+        default:
+                return -EINVAL;
+        case 1:
+                return grpci1_cfg_w8(priv, busno, devfn, where, val);
+        case 2:
+                return grpci1_cfg_w16(priv, busno, devfn, where, val);
+        case 4:
+                return grpci1_cfg_w32(priv, busno, devfn, where, val);
+        }
+}
+
+static struct pci_ops grpci1_ops = {
+        .read =         grpci1_read_config,
+        .write =        grpci1_write_config,
+};
+
+/* GENIRQ IRQ chip implementation for grpci1 irqmode=0..2. In configuration
+ * 3 where all PCI Interrupts has a separate IRQ on the system IRQ controller
+ * this is not needed and the standard IRQ controller can be used.
+ */
+
+static void grpci1_mask_irq(struct irq_data *data)
+{
+        u32 irqidx;
+        struct grpci1_priv *priv = grpci1priv;
+
+        irqidx = (u32)data->chip_data - 1;
+        if (irqidx > 3) /* only mask PCI interrupts here */
+                return;
+        irqidx += IRQ_MASK_BIT;
+
+        REGSTORE(priv->regs->irq, REGLOAD(priv->regs->irq) & ~(1 << irqidx));
+}
+
+static void grpci1_unmask_irq(struct irq_data *data)
+{
+        u32 irqidx;
+        struct grpci1_priv *priv = grpci1priv;
+
+        irqidx = (u32)data->chip_data - 1;
+        if (irqidx > 3) /* only unmask PCI interrupts here */
+                return;
+        irqidx += IRQ_MASK_BIT;
+
+        REGSTORE(priv->regs->irq, REGLOAD(priv->regs->irq) | (1 << irqidx));
+}
+
+static unsigned int grpci1_startup_irq(struct irq_data *data)
+{
+        grpci1_unmask_irq(data);
+        return 0;
+}
+
+static void grpci1_shutdown_irq(struct irq_data *data)
+{
+        grpci1_mask_irq(data);
+}
+
+static struct irq_chip grpci1_irq = {
+        .name           = "grpci1",
+        .irq_startup    = grpci1_startup_irq,
+        .irq_shutdown   = grpci1_shutdown_irq,
+        .irq_mask       = grpci1_mask_irq,
+        .irq_unmask     = grpci1_unmask_irq,
+};
+
+/* Handle one or multiple IRQs from the PCI core */
+static void grpci1_pci_flow_irq(unsigned int irq, struct irq_desc *desc)
+{
+        struct grpci1_priv *priv = grpci1priv;
+        int i, ack = 0;
+        unsigned int irqreg;
+
+        irqreg = REGLOAD(priv->regs->irq);
+        irqreg = (irqreg >> IRQ_MASK_BIT) & irqreg;
+
+        /* Error Interrupt? */
+        if (irqreg & IRQ_ALL_ERRORS) {
+                generic_handle_irq(priv->irq_err);
+                ack = 1;
+        }
+
+        /* PCI Interrupt? */
+        if (irqreg & IRQ_INTX) {
+                /* Call respective PCI Interrupt handler */
+                for (i = 0; i < 4; i++) {
+                        if (irqreg & (1 << i))
+                                generic_handle_irq(priv->irq_map[i]);
+                }
+                ack = 1;
+        }
+
+        /*
+         * Call "first level" IRQ chip end-of-irq handler. It will ACK LEON IRQ
+         * Controller, this must be done after IRQ sources have been handled to
+         * avoid double IRQ generation
+         */
+        if (ack)
+                desc->irq_data.chip->irq_eoi(&desc->irq_data);
+}
+
+/* Create a virtual IRQ */
+static unsigned int grpci1_build_device_irq(unsigned int irq)
+{
+        unsigned int virq = 0, pil;
+
+        pil = 1 << 8;
+        virq = irq_alloc(irq, pil);
+        if (virq == 0)
+                goto out;
+
+        irq_set_chip_and_handler_name(virq, &grpci1_irq, handle_simple_irq,
+                                      "pcilvl");
+        irq_set_chip_data(virq, (void *)irq);
+
+out:
+        return virq;
+}
+
+/*
+ * Initialize mappings AMBA<->PCI, clear IRQ state, setup PCI interface
+ *
+ * Target BARs:
+ *  BAR0: unused in this implementation
+ *  BAR1: peripheral DMA to host's memory (size at least 256MByte)
+ *  BAR2..BAR5: not implemented in hardware
+ */
+void grpci1_hw_init(struct grpci1_priv *priv)
+{
+        u32 ahbadr, bar_sz, data, pciadr;
+        struct grpci1_regs *regs = priv->regs;
+
+        /* set 1:1 mapping between AHB -> PCI memory space */
+        REGSTORE(regs->cfg_stat, priv->pci_area & 0xf0000000);
+
+        /* map PCI accesses to target BAR1 to Linux kernel memory 1:1 */
+        ahbadr = 0xf0000000 & (u32)__pa(PAGE_ALIGN((unsigned long) &_end));
+        REGSTORE(regs->page1, ahbadr);
+
+        /* translate I/O accesses to 0, I/O Space always @ PCI low 64Kbytes */
+        REGSTORE(regs->iomap, REGLOAD(regs->iomap) & 0x0000ffff);
+
+        /* disable and clear pending interrupts */
+        REGSTORE(regs->irq, 0);
+
+        /* Setup BAR0 outside access range so that it does not conflict with
+         * peripheral DMA. There is no need to set up the PAGE0 register.
+         */
+        grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
+        grpci1_cfg_r32(priv, TGT, 0, PCI_BASE_ADDRESS_0, &bar_sz);
+        bar_sz = ~bar_sz + 1;
+        pciadr = priv->pci_area - bar_sz;
+        grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, pciadr);
+
+        /*
+         * Setup the Host's PCI Target BAR1 for other peripherals to access,
+         * and do DMA to the host's memory.
+         */
+        grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_1, ahbadr);
+
+        /*
+         * Setup Latency Timer and cache line size. Default cache line
+         * size will result in poor performance (256 word fetches), 0xff
+         * will set it according to the max size of the PCI FIFO.
+         */
+        grpci1_cfg_w8(priv, TGT, 0, PCI_CACHE_LINE_SIZE, 0xff);
+        grpci1_cfg_w8(priv, TGT, 0, PCI_LATENCY_TIMER, 0x40);
+
+        /* set as bus master, enable pci memory responses, clear status bits */
+        grpci1_cfg_r32(priv, TGT, 0, PCI_COMMAND, &data);
+        data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+        grpci1_cfg_w32(priv, TGT, 0, PCI_COMMAND, data);
+}
+
+static irqreturn_t grpci1_jump_interrupt(int irq, void *arg)
+{
+        struct grpci1_priv *priv = arg;
+        dev_err(priv->dev, "Jump IRQ happened\n");
+        return IRQ_NONE;
+}
+
+/* Handle GRPCI1 Error Interrupt */
+static irqreturn_t grpci1_err_interrupt(int irq, void *arg)
+{
+        struct grpci1_priv *priv = arg;
+        u32 status;
+
+        grpci1_cfg_r16(priv, TGT, 0, PCI_STATUS, &status);
+        status &= priv->pci_err_mask;
+
+        if (status == 0)
+                return IRQ_NONE;
+
+        if (status & PCI_STATUS_PARITY)
+                dev_err(priv->dev, "Data Parity Error\n");
+
+        if (status & PCI_STATUS_SIG_TARGET_ABORT)
+                dev_err(priv->dev, "Signalled Target Abort\n");
+
+        if (status & PCI_STATUS_REC_TARGET_ABORT)
+                dev_err(priv->dev, "Received Target Abort\n");
+
+        if (status & PCI_STATUS_REC_MASTER_ABORT)
+                dev_err(priv->dev, "Received Master Abort\n");
+
+        if (status & PCI_STATUS_SIG_SYSTEM_ERROR)
+                dev_err(priv->dev, "Signalled System Error\n");
+
+        if (status & PCI_STATUS_DETECTED_PARITY)
+                dev_err(priv->dev, "Parity Error\n");
+
+        /* Clear handled INT TYPE IRQs */
+        grpci1_cfg_w16(priv, TGT, 0, PCI_STATUS, status);
+
+        return IRQ_HANDLED;
+}
+
+static int grpci1_of_probe(struct platform_device *ofdev)
+{
+        struct grpci1_regs *regs;
+        struct grpci1_priv *priv;
+        int err, len;
+        const int *tmp;
+        u32 cfg, size, err_mask;
+        struct resource *res;
+
+        if (grpci1priv) {
+                dev_err(&ofdev->dev, "only one GRPCI1 supported\n");
+                return -ENODEV;
+        }
+
+        if (ofdev->num_resources < 3) {
+                dev_err(&ofdev->dev, "not enough APB/AHB resources\n");
+                return -EIO;
+        }
+
+        priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL);
+        if (!priv) {
+                dev_err(&ofdev->dev, "memory allocation failed\n");
+                return -ENOMEM;
+        }
+        platform_set_drvdata(ofdev, priv);
+        priv->dev = &ofdev->dev;
+
+        /* find device register base address */
+        res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
+        regs = devm_request_and_ioremap(&ofdev->dev, res);
+        if (!regs) {
+                dev_err(&ofdev->dev, "io-regs mapping failed\n");
+                return -EADDRNOTAVAIL;
+        }
+
+        /*
+         * check that we're in Host Slot and that we can act as a Host Bridge
+         * and not only as target/peripheral.
+         */
+        cfg = REGLOAD(regs->cfg_stat);
+        if ((cfg & CFGSTAT_HOST) == 0) {
+                dev_err(&ofdev->dev, "not in host system slot\n");
+                return -EIO;
+        }
+
+        /* check that BAR1 support 256 MByte so that we can map kernel space */
+        REGSTORE(regs->page1, 0xffffffff);
+        size = ~REGLOAD(regs->page1) + 1;
+        if (size < 0x10000000) {
+                dev_err(&ofdev->dev, "BAR1 must be at least 256MByte\n");
+                return -EIO;
+        }
+
+        /* hardware must support little-endian PCI (byte-twisting) */
+        if ((REGLOAD(regs->page0) & PAGE0_BTEN) == 0) {
+                dev_err(&ofdev->dev, "byte-twisting is required\n");
+                return -EIO;
+        }
+
+        priv->regs = regs;
+        priv->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
+        dev_info(&ofdev->dev, "host found at 0x%p, irq%d\n", regs, priv->irq);
+
+        /* Find PCI Memory, I/O and Configuration Space Windows */
+        priv->pci_area = ofdev->resource[1].start;
+        priv->pci_area_end = ofdev->resource[1].end+1;
+        priv->pci_io = ofdev->resource[2].start;
+        priv->pci_conf = ofdev->resource[2].start + 0x10000;
+        priv->pci_conf_end = priv->pci_conf + 0x10000;
+        priv->pci_io_va = (unsigned long)ioremap(priv->pci_io, 0x10000);
+        if (!priv->pci_io_va) {
+                dev_err(&ofdev->dev, "unable to map PCI I/O area\n");
+                return -EIO;
+        }
+
+        printk(KERN_INFO
+                "GRPCI1: MEMORY SPACE [0x%08lx - 0x%08lx]\n"
+                "        I/O    SPACE [0x%08lx - 0x%08lx]\n"
+                "        CONFIG SPACE [0x%08lx - 0x%08lx]\n",
+                priv->pci_area, priv->pci_area_end-1,
+                priv->pci_io, priv->pci_conf-1,
+                priv->pci_conf, priv->pci_conf_end-1);
+
+        /*
+         * I/O Space resources in I/O Window mapped into Virtual Adr Space
+         * We never use low 4KB because some devices seem have problems using
+         * address 0.
+         */
+        priv->info.io_space.name = "GRPCI1 PCI I/O Space";
+        priv->info.io_space.start = priv->pci_io_va + 0x1000;
+        priv->info.io_space.end = priv->pci_io_va + 0x10000 - 1;
+        priv->info.io_space.flags = IORESOURCE_IO;
+
+        /*
+         * grpci1 has no prefetchable memory, map everything as
+         * non-prefetchable memory
+         */
+        priv->info.mem_space.name = "GRPCI1 PCI MEM Space";
+        priv->info.mem_space.start = priv->pci_area;
+        priv->info.mem_space.end = priv->pci_area_end - 1;
+        priv->info.mem_space.flags = IORESOURCE_MEM;
+
+        if (request_resource(&iomem_resource, &priv->info.mem_space) < 0) {
+                dev_err(&ofdev->dev, "unable to request PCI memory area\n");
+                err = -ENOMEM;
+                goto err1;
+        }
+
+        if (request_resource(&ioport_resource, &priv->info.io_space) < 0) {
+                dev_err(&ofdev->dev, "unable to request PCI I/O area\n");
+                err = -ENOMEM;
+                goto err2;
+        }
+
+        /* setup maximum supported PCI buses */
+        priv->info.busn.name = "GRPCI1 busn";
+        priv->info.busn.start = 0;
+        priv->info.busn.end = 15;
+
+        grpci1priv = priv;
+
+        /* Initialize hardware */
+        grpci1_hw_init(priv);
+
+        /*
+         * Get PCI Interrupt to System IRQ mapping and setup IRQ handling
+         * Error IRQ. All PCI and PCI-Error interrupts are shared using the
+         * same system IRQ.
+         */
+        leon_update_virq_handling(priv->irq, grpci1_pci_flow_irq, "pcilvl", 0);
+
+        priv->irq_map[0] = grpci1_build_device_irq(1);
+        priv->irq_map[1] = grpci1_build_device_irq(2);
+        priv->irq_map[2] = grpci1_build_device_irq(3);
+        priv->irq_map[3] = grpci1_build_device_irq(4);
+        priv->irq_err = grpci1_build_device_irq(5);
+
+        printk(KERN_INFO "        PCI INTA..D#: IRQ%d, IRQ%d, IRQ%d, IRQ%d\n",
+                priv->irq_map[0], priv->irq_map[1], priv->irq_map[2],
+                priv->irq_map[3]);
+
+        /* Enable IRQs on LEON IRQ controller */
+        err = devm_request_irq(&ofdev->dev, priv->irq, grpci1_jump_interrupt, 0,
+                                "GRPCI1_JUMP", priv);
+        if (err) {
+                dev_err(&ofdev->dev, "ERR IRQ request failed: %d\n", err);
+                goto err3;
+        }
+
+        /* Setup IRQ handler for access errors */
+        err = devm_request_irq(&ofdev->dev, priv->irq_err,
+                                grpci1_err_interrupt, IRQF_SHARED, "GRPCI1_ERR",
+                                priv);
+        if (err) {
+                dev_err(&ofdev->dev, "ERR VIRQ request failed: %d\n", err);
+                goto err3;
+        }
+
+        tmp = of_get_property(ofdev->dev.of_node, "all_pci_errors", &len);
+        if (tmp && (len == 4)) {
+                priv->pci_err_mask = ALL_PCI_ERRORS;
+                err_mask = IRQ_ALL_ERRORS << IRQ_MASK_BIT;
+        } else {
+                priv->pci_err_mask = DEF_PCI_ERRORS;
+                err_mask = IRQ_DEF_ERRORS << IRQ_MASK_BIT;
+        }
+
+        /*
+         * Enable Error Interrupts. PCI interrupts are unmasked once request_irq
+         * is called by the PCI Device drivers
+         */
+        REGSTORE(regs->irq, err_mask);
+
+        /* Init common layer and scan buses */
+        priv->info.ops = &grpci1_ops;
+        priv->info.map_irq = grpci1_map_irq;
+        leon_pci_init(ofdev, &priv->info);
+
+        return 0;
+
+err3:
+        release_resource(&priv->info.io_space);
+err2:
+        release_resource(&priv->info.mem_space);
+err1:
+        iounmap((void *)priv->pci_io_va);
+        grpci1priv = NULL;
+        return err;
+}
+
+static struct of_device_id grpci1_of_match[] = {
+        {
+         .name = "GAISLER_PCIFBRG",
+         },
+        {
+         .name = "01_014",
+         },
+        {},
+};
+
+static struct platform_driver grpci1_of_driver = {
+        .driver = {
+                .name = "grpci1",
+                .owner = THIS_MODULE,
+                .of_match_table = grpci1_of_match,
+        },
+        .probe = grpci1_of_probe,
+};
+
+static int __init grpci1_init(void)
+{
+        return platform_driver_register(&grpci1_of_driver);
+}
+
+subsys_initcall(grpci1_init);
diff --git a/arch/sparc/kernel/leon_pci_grpci2.c b/arch/sparc/kernel/leon_pci_grpci2.c
index 4d1487138d26..5f0402aab7fb 100644
--- a/arch/sparc/kernel/leon_pci_grpci2.c
+++ b/arch/sparc/kernel/leon_pci_grpci2.c
@@ -799,6 +799,11 @@ static int grpci2_of_probe(struct platform_device *ofdev)
         if (request_resource(&ioport_resource, &priv->info.io_space) < 0)
                 goto err4;
 
+        /* setup maximum supported PCI buses */
+        priv->info.busn.name = "GRPCI2 busn";
+        priv->info.busn.start = 0;
+        priv->info.busn.end = 255;
+
         grpci2_hw_init(priv);
 
         /*
diff --git a/arch/sparc/kernel/leon_pmc.c b/arch/sparc/kernel/leon_pmc.c
index 708bca435219..bdf53d9a8d46 100644
--- a/arch/sparc/kernel/leon_pmc.c
+++ b/arch/sparc/kernel/leon_pmc.c
@@ -48,7 +48,7 @@ void pmc_leon_idle_fixup(void)
          */
         register unsigned int address = (unsigned int)leon3_irqctrl_regs;
         __asm__ __volatile__ (
-                "mov    %%g0, %%asr19\n"
+                "wr     %%g0, %%asr19\n"
                 "lda    [%0] %1, %%g0\n"
                 :
                 : "r"(address), "i"(ASI_LEON_BYPASS));
@@ -61,7 +61,7 @@ void pmc_leon_idle_fixup(void)
 void pmc_leon_idle(void)
 {
         /* For systems without power-down, this will be no-op */
-        __asm__ __volatile__ ("mov      %g0, %asr19\n\t");
+        __asm__ __volatile__ ("wr       %g0, %asr19\n\t");
 }
 
 /* Install LEON Power Down function */
diff --git a/arch/sparc/kernel/process_32.c b/arch/sparc/kernel/process_32.c
index 62eede13831a..fdd819dfdacf 100644
--- a/arch/sparc/kernel/process_32.c
+++ b/arch/sparc/kernel/process_32.c
@@ -64,23 +64,12 @@ extern void fpsave(unsigned long *, unsigned long *, void *, unsigned long *);
 struct task_struct *last_task_used_math = NULL;
 struct thread_info *current_set[NR_CPUS];
 
-/*
- * the idle loop on a Sparc... ;)
- */
-void cpu_idle(void)
+/* Idle loop support. */
+void arch_cpu_idle(void)
 {
-        set_thread_flag(TIF_POLLING_NRFLAG);
-
-        /* endless idle loop with no priority at all */
-        for (;;) {
-                while (!need_resched()) {
-                        if (sparc_idle)
-                                (*sparc_idle)();
-                        else
-                                cpu_relax();
-                }
-                schedule_preempt_disabled();
-        }
+        if (sparc_idle)
+                (*sparc_idle)();
+        local_irq_enable();
 }
 
 /* XXX cli/sti -> local_irq_xxx here, check this works once SMP is fixed. */
@@ -123,6 +112,8 @@ void show_regs(struct pt_regs *r)
 {
         struct reg_window32 *rw = (struct reg_window32 *) r->u_regs[14];
 
+        show_regs_print_info(KERN_DEFAULT);
+
         printk("PSR: %08lx PC: %08lx NPC: %08lx Y: %08lx    %s\n",
                r->psr, r->pc, r->npc, r->y, print_tainted());
         printk("PC: <%pS>\n", (void *) r->pc);
@@ -153,11 +144,13 @@ void show_stack(struct task_struct *tsk, unsigned long *_ksp)
         struct reg_window32 *rw;
         int count = 0;
 
-        if (tsk != NULL)
-                task_base = (unsigned long) task_stack_page(tsk);
-        else
-                task_base = (unsigned long) current_thread_info();
+        if (!tsk)
+                tsk = current;
 
+        if (tsk == current && !_ksp)
+                __asm__ __volatile__("mov       %%fp, %0" : "=r" (_ksp));
+
+        task_base = (unsigned long) task_stack_page(tsk);
         fp = (unsigned long) _ksp;
         do {
                 /* Bogus frame pointer? */
@@ -173,17 +166,6 @@ void show_stack(struct task_struct *tsk, unsigned long *_ksp)
         printk("\n");
 }
 
-void dump_stack(void)
-{
-        unsigned long *ksp;
-
-        __asm__ __volatile__("mov       %%fp, %0"
-                             : "=r" (ksp));
-        show_stack(current, ksp);
-}
-
-EXPORT_SYMBOL(dump_stack);
-
 /*
  * Note: sparc64 has a pretty intricated thread_saved_pc, check it out.
  */
diff --git a/arch/sparc/kernel/process_64.c b/arch/sparc/kernel/process_64.c
index cdb80b2adbe0..baebab215492 100644
--- a/arch/sparc/kernel/process_64.c
+++ b/arch/sparc/kernel/process_64.c
@@ -52,20 +52,17 @@
 
 #include "kstack.h"
 
-static void sparc64_yield(int cpu)
+/* Idle loop support on sparc64. */
+void arch_cpu_idle(void)
 {
         if (tlb_type != hypervisor) {
                 touch_nmi_watchdog();
-                return;
-        }
-
-        clear_thread_flag(TIF_POLLING_NRFLAG);
-        smp_mb__after_clear_bit();
-
-        while (!need_resched() && !cpu_is_offline(cpu)) {
+        } else {
                 unsigned long pstate;
 
-                /* Disable interrupts. */
+                /* The sun4v sleeping code requires that we have PSTATE.IE cleared over
+                 * the cpu sleep hypervisor call.
+                 */
                 __asm__ __volatile__(
                         "rdpr %%pstate, %0\n\t"
                         "andn %0, %1, %0\n\t"
@@ -73,7 +70,7 @@ static void sparc64_yield(int cpu)
                         : "=&r" (pstate)
                         : "i" (PSTATE_IE));
 
-                if (!need_resched() && !cpu_is_offline(cpu))
+                if (!need_resched() && !cpu_is_offline(smp_processor_id()))
                         sun4v_cpu_yield();
 
                 /* Re-enable interrupts. */
@@ -84,36 +81,16 @@ static void sparc64_yield(int cpu)
                         : "=&r" (pstate)
                         : "i" (PSTATE_IE));
         }
-
-        set_thread_flag(TIF_POLLING_NRFLAG);
+        local_irq_enable();
 }
 
-/* The idle loop on sparc64. */
-void cpu_idle(void)
-{
-        int cpu = smp_processor_id();
-
-        set_thread_flag(TIF_POLLING_NRFLAG);
-
-        while(1) {
-                tick_nohz_idle_enter();
-                rcu_idle_enter();
-
-                while (!need_resched() && !cpu_is_offline(cpu))
-                        sparc64_yield(cpu);
-
-                rcu_idle_exit();
-                tick_nohz_idle_exit();
-
 #ifdef CONFIG_HOTPLUG_CPU
-                if (cpu_is_offline(cpu)) {
-                        sched_preempt_enable_no_resched();
-                        cpu_play_dead();
-                }
-#endif
-                schedule_preempt_disabled();
-        }
+void arch_cpu_idle_dead()
+{
+        sched_preempt_enable_no_resched();
+        cpu_play_dead();
 }
+#endif
 
 #ifdef CONFIG_COMPAT
 static void show_regwindow32(struct pt_regs *regs)
@@ -186,6 +163,8 @@ static void show_regwindow(struct pt_regs *regs)
 
 void show_regs(struct pt_regs *regs)
 {
+        show_regs_print_info(KERN_DEFAULT);
+
         printk("TSTATE: %016lx TPC: %016lx TNPC: %016lx Y: %08x    %s\n", regs->tstate,
                regs->tpc, regs->tnpc, regs->y, print_tainted());
         printk("TPC: <%pS>\n", (void *) regs->tpc);
@@ -315,7 +294,7 @@ static void sysrq_handle_globreg(int key)
 
 static struct sysrq_key_op sparc_globalreg_op = {
         .handler        = sysrq_handle_globreg,
-        .help_msg       = "global-regs(Y)",
+        .help_msg       = "global-regs(y)",
         .action_msg     = "Show Global CPU Regs",
 };
 
@@ -385,7 +364,7 @@ static void sysrq_handle_globpmu(int key)
 
 static struct sysrq_key_op sparc_globalpmu_op = {
         .handler        = sysrq_handle_globpmu,
-        .help_msg       = "global-pmu(X)",
+        .help_msg       = "global-pmu(x)",
         .action_msg     = "Show Global PMU Regs",
 };
 
diff --git a/arch/sparc/kernel/smp_32.c b/arch/sparc/kernel/smp_32.c
index 9e7e6d718367..e3f2b81c23f1 100644
--- a/arch/sparc/kernel/smp_32.c
+++ b/arch/sparc/kernel/smp_32.c
@@ -369,7 +369,7 @@ void __cpuinit sparc_start_secondary(void *arg)
         local_irq_enable();
 
         wmb();
-        cpu_idle();
+        cpu_startup_entry(CPUHP_ONLINE);
 
         /* We should never reach here! */
         BUG();
diff --git a/arch/sparc/kernel/smp_64.c b/arch/sparc/kernel/smp_64.c
index ca64d2a86ec0..77539eda928c 100644
--- a/arch/sparc/kernel/smp_64.c
+++ b/arch/sparc/kernel/smp_64.c
@@ -127,6 +127,8 @@ void __cpuinit smp_callin(void)
 
         /* idle thread is expected to have preempt disabled */
         preempt_disable();
+
+        cpu_startup_entry(CPUHP_ONLINE);
 }
 
 void cpu_panic(void)
diff --git a/arch/sparc/kernel/sun4d_irq.c b/arch/sparc/kernel/sun4d_irq.c
index e490ac9327c7..f8933be3ca8b 100644
--- a/arch/sparc/kernel/sun4d_irq.c
+++ b/arch/sparc/kernel/sun4d_irq.c
@@ -6,6 +6,7 @@
  */
 
 #include <linux/kernel_stat.h>
+#include <linux/slab.h>
 #include <linux/seq_file.h>
 
 #include <asm/timer.h>
diff --git a/arch/sparc/kernel/sys32.S b/arch/sparc/kernel/sys32.S
index 240a3cecc11e..2e680b5245c9 100644
--- a/arch/sparc/kernel/sys32.S
+++ b/arch/sparc/kernel/sys32.S
@@ -36,7 +36,6 @@ STUB:	sra	REG1, 0, REG1; \
         jmpl    %g1 + %lo(SYSCALL), %g0; \
         sra     REG3, 0, REG3
 
-SIGN1(sys32_getrusage, compat_sys_getrusage, %o0)
 SIGN1(sys32_readahead, compat_sys_readahead, %o0)
 SIGN2(sys32_fadvise64, compat_sys_fadvise64, %o0, %o4)
 SIGN2(sys32_fadvise64_64, compat_sys_fadvise64_64, %o0, %o5)
@@ -46,12 +45,9 @@ SIGN1(sys32_io_submit, compat_sys_io_submit, %o1)
 SIGN1(sys32_mq_open, compat_sys_mq_open, %o1)
 SIGN1(sys32_select, compat_sys_select, %o0)
 SIGN3(sys32_futex, compat_sys_futex, %o1, %o2, %o5)
-SIGN2(sys32_sendfile, compat_sys_sendfile, %o0, %o1)
 SIGN1(sys32_recvfrom, compat_sys_recvfrom, %o0)
 SIGN1(sys32_recvmsg, compat_sys_recvmsg, %o0)
 SIGN1(sys32_sendmsg, compat_sys_sendmsg, %o0)
-SIGN2(sys32_sync_file_range, compat_sync_file_range, %o0, %o5)
-SIGN1(sys32_vmsplice, compat_sys_vmsplice, %o0)
 
         .globl          sys32_mmap2
 sys32_mmap2:
diff --git a/arch/sparc/kernel/sys_sparc32.c b/arch/sparc/kernel/sys_sparc32.c
index f38f2280fade..3d0ddbc005fe 100644
--- a/arch/sparc/kernel/sys_sparc32.c
+++ b/arch/sparc/kernel/sys_sparc32.c
@@ -49,71 +49,6 @@
 #include <asm/mmu_context.h>
 #include <asm/compat_signal.h>
 
-#ifdef CONFIG_SYSVIPC                                                        
-asmlinkage long compat_sys_ipc(u32 call, u32 first, u32 second, u32 third, compat_uptr_t ptr, u32 fifth)
-{
-        int version;
-
-        version = call >> 16; /* hack for backward compatibility */
-        call &= 0xffff;
-
-        switch (call) {
-        case SEMTIMEDOP:
-                if (fifth)
-                        /* sign extend semid */
-                        return compat_sys_semtimedop((int)first,
-                                                     compat_ptr(ptr), second,
-                                                     compat_ptr(fifth));
-                /* else fall through for normal semop() */
-        case SEMOP:
-                /* struct sembuf is the same on 32 and 64bit :)) */
-                /* sign extend semid */
-                return sys_semtimedop((int)first, compat_ptr(ptr), second,
-                                      NULL);
-        case SEMGET:
-                /* sign extend key, nsems */
-                return sys_semget((int)first, (int)second, third);
-        case SEMCTL:
-                /* sign extend semid, semnum */
-                return compat_sys_semctl((int)first, (int)second, third,
-                                         compat_ptr(ptr));
-
-        case MSGSND:
-                /* sign extend msqid */
-                return compat_sys_msgsnd((int)first, (int)second, third,
-                                         compat_ptr(ptr));
-        case MSGRCV:
-                /* sign extend msqid, msgtyp */
-                return compat_sys_msgrcv((int)first, second, (int)fifth,
-                                         third, version, compat_ptr(ptr));
-        case MSGGET:
-                /* sign extend key */
-                return sys_msgget((int)first, second);
-        case MSGCTL:
-                /* sign extend msqid */
-                return compat_sys_msgctl((int)first, second, compat_ptr(ptr));
-
-        case SHMAT:
-                /* sign extend shmid */
-                return compat_sys_shmat((int)first, second, third, version,
-                                        compat_ptr(ptr));
-        case SHMDT:
-                return sys_shmdt(compat_ptr(ptr));
-        case SHMGET:
-                /* sign extend key_t */
-                return sys_shmget((int)first, second, third);
-        case SHMCTL:
-                /* sign extend shmid */
-                return compat_sys_shmctl((int)first, second, compat_ptr(ptr));
-
-        default:
-                return -ENOSYS;
-        }
-
-        return -ENOSYS;
-}
-#endif
-
 asmlinkage long sys32_truncate64(const char __user * path, unsigned long high, unsigned long low)
 {
         if ((int)high < 0)
@@ -303,15 +238,7 @@ long compat_sys_fadvise64_64(int fd,
                                 advice);
 }
 
-long sys32_lookup_dcookie(unsigned long cookie_high,
-                          unsigned long cookie_low,
-                          char __user *buf, size_t len)
-{
-        return sys_lookup_dcookie((cookie_high << 32) | cookie_low,
-                                  buf, len);
-}
-
-long compat_sync_file_range(int fd, unsigned long off_high, unsigned long off_low, unsigned long nb_high, unsigned long nb_low, int flags)
+long sys32_sync_file_range(unsigned int fd, unsigned long off_high, unsigned long off_low, unsigned long nb_high, unsigned long nb_low, unsigned int flags)
 {
         return sys_sync_file_range(fd,
                                    (off_high << 32) | off_low,
diff --git a/arch/sparc/kernel/sys_sparc_64.c b/arch/sparc/kernel/sys_sparc_64.c
index 708bc29d36a8..2daaaa6eda23 100644
--- a/arch/sparc/kernel/sys_sparc_64.c
+++ b/arch/sparc/kernel/sys_sparc_64.c
@@ -353,7 +353,7 @@ SYSCALL_DEFINE6(sparc_ipc, unsigned int, call, int, first, unsigned long, second
                 case SEMCTL: {
                         err = sys_semctl(first, second,
                                          (int)third | IPC_64,
-                                         (union semun) ptr);
+                                         (unsigned long) ptr);
                         goto out;
                 }
                 default:
@@ -470,10 +470,6 @@ SYSCALL_DEFINE2(64_munmap, unsigned long, addr, size_t, len)
 
         return vm_munmap(addr, len);
 }
-
-extern unsigned long do_mremap(unsigned long addr,
-        unsigned long old_len, unsigned long new_len,
-        unsigned long flags, unsigned long new_addr);
                 
 SYSCALL_DEFINE5(64_mremap, unsigned long, addr, unsigned long, old_len,
                 unsigned long, new_len, unsigned long, flags,
diff --git a/arch/sparc/kernel/systbls_64.S b/arch/sparc/kernel/systbls_64.S
index 088134834dab..8fd932080215 100644
--- a/arch/sparc/kernel/systbls_64.S
+++ b/arch/sparc/kernel/systbls_64.S
@@ -23,9 +23,9 @@ sys_call_table32:
 /*10*/  .word sys_unlink, sunos_execv, sys_chdir, sys_chown16, sys_mknod
 /*15*/  .word sys_chmod, sys_lchown16, sys_brk, sys_nis_syscall, compat_sys_lseek
 /*20*/  .word sys_getpid, sys_capget, sys_capset, sys_setuid16, sys_getuid16
-/*25*/  .word sys32_vmsplice, compat_sys_ptrace, sys_alarm, compat_sys_sigaltstack, sys_pause
+/*25*/  .word compat_sys_vmsplice, compat_sys_ptrace, sys_alarm, compat_sys_sigaltstack, sys_pause
 /*30*/  .word compat_sys_utime, sys_lchown, sys_fchown, sys_access, sys_nice
-        .word sys_chown, sys_sync, sys_kill, compat_sys_newstat, sys32_sendfile
+        .word sys_chown, sys_sync, sys_kill, compat_sys_newstat, compat_sys_sendfile
 /*40*/  .word compat_sys_newlstat, sys_dup, sys_sparc_pipe, compat_sys_times, sys_getuid
         .word sys_umount, sys_setgid16, sys_getgid16, sys_signal, sys_geteuid16
 /*50*/  .word sys_getegid16, sys_acct, sys_nis_syscall, sys_getgid, compat_sys_ioctl
@@ -41,7 +41,7 @@ sys_call_table32:
 /*100*/ .word sys_getpriority, sys32_rt_sigreturn, compat_sys_rt_sigaction, compat_sys_rt_sigprocmask, compat_sys_rt_sigpending
         .word compat_sys_rt_sigtimedwait, compat_sys_rt_sigqueueinfo, compat_sys_rt_sigsuspend, sys_setresuid, sys_getresuid
 /*110*/ .word sys_setresgid, sys_getresgid, sys_setregid, sys_nis_syscall, sys_nis_syscall
-        .word sys_getgroups, compat_sys_gettimeofday, sys32_getrusage, sys_nis_syscall, sys_getcwd
+        .word sys_getgroups, compat_sys_gettimeofday, compat_sys_getrusage, sys_nis_syscall, sys_getcwd
 /*120*/ .word compat_sys_readv, compat_sys_writev, compat_sys_settimeofday, sys_fchown16, sys_fchmod
         .word sys_nis_syscall, sys_setreuid16, sys_setregid16, sys_rename, compat_sys_truncate
 /*130*/ .word compat_sys_ftruncate, sys_flock, compat_sys_lstat64, sys_nis_syscall, sys_nis_syscall
@@ -59,7 +59,7 @@ sys_call_table32:
 /*190*/ .word sys_init_module, sys_sparc64_personality, sys_remap_file_pages, sys_epoll_create, sys_epoll_ctl
         .word sys_epoll_wait, sys_ioprio_set, sys_getppid, compat_sys_sparc_sigaction, sys_sgetmask
 /*200*/ .word sys_ssetmask, sys_sigsuspend, compat_sys_newlstat, sys_uselib, compat_sys_old_readdir
-        .word sys32_readahead, sys32_socketcall, sys_syslog, sys32_lookup_dcookie, sys32_fadvise64
+        .word sys32_readahead, sys32_socketcall, sys_syslog, compat_sys_lookup_dcookie, sys32_fadvise64
 /*210*/ .word sys32_fadvise64_64, sys_tgkill, sys_waitpid, sys_swapoff, compat_sys_sysinfo
         .word compat_sys_ipc, sys32_sigreturn, sys_clone, sys_ioprio_get, compat_sys_adjtimex
 /*220*/ .word compat_sys_sigprocmask, sys_ni_syscall, sys_delete_module, sys_ni_syscall, sys_getpgid
diff --git a/arch/sparc/kernel/trampoline_64.S b/arch/sparc/kernel/trampoline_64.S
index da1b781b5e65..2e973a26fbda 100644
--- a/arch/sparc/kernel/trampoline_64.S
+++ b/arch/sparc/kernel/trampoline_64.S
@@ -407,8 +407,7 @@ after_lock_tlb:
 
         call            smp_callin
          nop
-        call            cpu_idle
-         mov            0, %o0
+
         call            cpu_panic
          nop
 1:      b,a,pt          %xcc, 1b
diff --git a/arch/sparc/kernel/traps_64.c b/arch/sparc/kernel/traps_64.c
index 8d38ca97aa23..b3f833ab90eb 100644
--- a/arch/sparc/kernel/traps_64.c
+++ b/arch/sparc/kernel/traps_64.c
@@ -2350,13 +2350,6 @@ void show_stack(struct task_struct *tsk, unsigned long *_ksp)
         } while (++count < 16);
 }
 
-void dump_stack(void)
-{
-        show_stack(current, NULL);
-}
-
-EXPORT_SYMBOL(dump_stack);
-
 static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
 {
         unsigned long fp = rw->ins[6];
diff --git a/arch/sparc/kernel/us2e_cpufreq.c b/arch/sparc/kernel/us2e_cpufreq.c
deleted file mode 100644
index 489fc15f3194..000000000000
--- a/arch/sparc/kernel/us2e_cpufreq.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/* us2e_cpufreq.c: UltraSPARC-IIe cpu frequency support
- *
- * Copyright (C) 2003 David S. Miller (davem@redhat.com)
- *
- * Many thanks to Dominik Brodowski for fixing up the cpufreq
- * infrastructure in order to make this driver easier to implement.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/smp.h>
-#include <linux/cpufreq.h>
-#include <linux/threads.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-
-#include <asm/asi.h>
-#include <asm/timer.h>
-
-static struct cpufreq_driver *cpufreq_us2e_driver;
-
-struct us2e_freq_percpu_info {
-        struct cpufreq_frequency_table table[6];
-};
-
-/* Indexed by cpu number. */
-static struct us2e_freq_percpu_info *us2e_freq_table;
-
-#define HBIRD_MEM_CNTL0_ADDR    0x1fe0000f010UL
-#define HBIRD_ESTAR_MODE_ADDR   0x1fe0000f080UL
-
-/* UltraSPARC-IIe has five dividers: 1, 2, 4, 6, and 8.  These are controlled
- * in the ESTAR mode control register.
- */
-#define ESTAR_MODE_DIV_1        0x0000000000000000UL
-#define ESTAR_MODE_DIV_2        0x0000000000000001UL
-#define ESTAR_MODE_DIV_4        0x0000000000000003UL
-#define ESTAR_MODE_DIV_6        0x0000000000000002UL
-#define ESTAR_MODE_DIV_8        0x0000000000000004UL
-#define ESTAR_MODE_DIV_MASK     0x0000000000000007UL
-
-#define MCTRL0_SREFRESH_ENAB    0x0000000000010000UL
-#define MCTRL0_REFR_COUNT_MASK  0x0000000000007f00UL
-#define MCTRL0_REFR_COUNT_SHIFT 8
-#define MCTRL0_REFR_INTERVAL    7800
-#define MCTRL0_REFR_CLKS_P_CNT  64
-
-static unsigned long read_hbreg(unsigned long addr)
-{
-        unsigned long ret;
-
-        __asm__ __volatile__("ldxa      [%1] %2, %0"
-                             : "=&r" (ret)
-                             : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
-        return ret;
-}
-
-static void write_hbreg(unsigned long addr, unsigned long val)
-{
-        __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
-                             "membar    #Sync"
-                             : /* no outputs */
-                             : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
-                             : "memory");
-        if (addr == HBIRD_ESTAR_MODE_ADDR) {
-                /* Need to wait 16 clock cycles for the PLL to lock.  */
-                udelay(1);
-        }
-}
-
-static void self_refresh_ctl(int enable)
-{
-        unsigned long mctrl = read_hbreg(HBIRD_MEM_CNTL0_ADDR);
-
-        if (enable)
-                mctrl |= MCTRL0_SREFRESH_ENAB;
-        else
-                mctrl &= ~MCTRL0_SREFRESH_ENAB;
-        write_hbreg(HBIRD_MEM_CNTL0_ADDR, mctrl);
-        (void) read_hbreg(HBIRD_MEM_CNTL0_ADDR);
-}
-
-static void frob_mem_refresh(int cpu_slowing_down,
-                             unsigned long clock_tick,
-                             unsigned long old_divisor, unsigned long divisor)
-{
-        unsigned long old_refr_count, refr_count, mctrl;
-
-        refr_count  = (clock_tick * MCTRL0_REFR_INTERVAL);
-        refr_count /= (MCTRL0_REFR_CLKS_P_CNT * divisor * 1000000000UL);
-
-        mctrl = read_hbreg(HBIRD_MEM_CNTL0_ADDR);
-        old_refr_count = (mctrl & MCTRL0_REFR_COUNT_MASK)
-                >> MCTRL0_REFR_COUNT_SHIFT;
-
-        mctrl &= ~MCTRL0_REFR_COUNT_MASK;
-        mctrl |= refr_count << MCTRL0_REFR_COUNT_SHIFT;
-        write_hbreg(HBIRD_MEM_CNTL0_ADDR, mctrl);
-        mctrl = read_hbreg(HBIRD_MEM_CNTL0_ADDR);
-
-        if (cpu_slowing_down && !(mctrl & MCTRL0_SREFRESH_ENAB)) {
-                unsigned long usecs;
-
-                /* We have to wait for both refresh counts (old
-                 * and new) to go to zero.
-                 */
-                usecs = (MCTRL0_REFR_CLKS_P_CNT *
-                         (refr_count + old_refr_count) *
-                         1000000UL *
-                         old_divisor) / clock_tick;
-                udelay(usecs + 1UL);
-        }
-}
-
-static void us2e_transition(unsigned long estar, unsigned long new_bits,
-                            unsigned long clock_tick,
-                            unsigned long old_divisor, unsigned long divisor)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        estar &= ~ESTAR_MODE_DIV_MASK;
-
-        /* This is based upon the state transition diagram in the IIe manual.  */
-        if (old_divisor == 2 && divisor == 1) {
-                self_refresh_ctl(0);
-                write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits);
-                frob_mem_refresh(0, clock_tick, old_divisor, divisor);
-        } else if (old_divisor == 1 && divisor == 2) {
-                frob_mem_refresh(1, clock_tick, old_divisor, divisor);
-                write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits);
-                self_refresh_ctl(1);
-        } else if (old_divisor == 1 && divisor > 2) {
-                us2e_transition(estar, ESTAR_MODE_DIV_2, clock_tick,
-                                1, 2);
-                us2e_transition(estar, new_bits, clock_tick,
-                                2, divisor);
-        } else if (old_divisor > 2 && divisor == 1) {
-                us2e_transition(estar, ESTAR_MODE_DIV_2, clock_tick,
-                                old_divisor, 2);
-                us2e_transition(estar, new_bits, clock_tick,
-                                2, divisor);
-        } else if (old_divisor < divisor) {
-                frob_mem_refresh(0, clock_tick, old_divisor, divisor);
-                write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits);
-        } else if (old_divisor > divisor) {
-                write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits);
-                frob_mem_refresh(1, clock_tick, old_divisor, divisor);
-        } else {
-                BUG();
-        }
-
-        local_irq_restore(flags);
-}
-
-static unsigned long index_to_estar_mode(unsigned int index)
-{
-        switch (index) {
-        case 0:
-                return ESTAR_MODE_DIV_1;
-
-        case 1:
-                return ESTAR_MODE_DIV_2;
-
-        case 2:
-                return ESTAR_MODE_DIV_4;
-
-        case 3:
-                return ESTAR_MODE_DIV_6;
-
-        case 4:
-                return ESTAR_MODE_DIV_8;
-
-        default:
-                BUG();
-        }
-}
-
-static unsigned long index_to_divisor(unsigned int index)
-{
-        switch (index) {
-        case 0:
-                return 1;
-
-        case 1:
-                return 2;
-
-        case 2:
-                return 4;
-
-        case 3:
-                return 6;
-
-        case 4:
-                return 8;
-
-        default:
-                BUG();
-        }
-}
-
-static unsigned long estar_to_divisor(unsigned long estar)
-{
-        unsigned long ret;
-
-        switch (estar & ESTAR_MODE_DIV_MASK) {
-        case ESTAR_MODE_DIV_1:
-                ret = 1;
-                break;
-        case ESTAR_MODE_DIV_2:
-                ret = 2;
-                break;
-        case ESTAR_MODE_DIV_4:
-                ret = 4;
-                break;
-        case ESTAR_MODE_DIV_6:
-                ret = 6;
-                break;
-        case ESTAR_MODE_DIV_8:
-                ret = 8;
-                break;
-        default:
-                BUG();
-        }
-
-        return ret;
-}
-
-static unsigned int us2e_freq_get(unsigned int cpu)
-{
-        cpumask_t cpus_allowed;
-        unsigned long clock_tick, estar;
-
-        if (!cpu_online(cpu))
-                return 0;
-
-        cpumask_copy(&cpus_allowed, tsk_cpus_allowed(current));
-        set_cpus_allowed_ptr(current, cpumask_of(cpu));
-
-        clock_tick = sparc64_get_clock_tick(cpu) / 1000;
-        estar = read_hbreg(HBIRD_ESTAR_MODE_ADDR);
-
-        set_cpus_allowed_ptr(current, &cpus_allowed);
-
-        return clock_tick / estar_to_divisor(estar);
-}
-
-static void us2e_set_cpu_divider_index(unsigned int cpu, unsigned int index)
-{
-        unsigned long new_bits, new_freq;
-        unsigned long clock_tick, divisor, old_divisor, estar;
-        cpumask_t cpus_allowed;
-        struct cpufreq_freqs freqs;
-
-        if (!cpu_online(cpu))
-                return;
-
-        cpumask_copy(&cpus_allowed, tsk_cpus_allowed(current));
-        set_cpus_allowed_ptr(current, cpumask_of(cpu));
-
-        new_freq = clock_tick = sparc64_get_clock_tick(cpu) / 1000;
-        new_bits = index_to_estar_mode(index);
-        divisor = index_to_divisor(index);
-        new_freq /= divisor;
-
-        estar = read_hbreg(HBIRD_ESTAR_MODE_ADDR);
-
-        old_divisor = estar_to_divisor(estar);
-
-        freqs.old = clock_tick / old_divisor;
-        freqs.new = new_freq;
-        freqs.cpu = cpu;
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
-        if (old_divisor != divisor)
-                us2e_transition(estar, new_bits, clock_tick * 1000,
-                                old_divisor, divisor);
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
-        set_cpus_allowed_ptr(current, &cpus_allowed);
-}
-
-static int us2e_freq_target(struct cpufreq_policy *policy,
-                          unsigned int target_freq,
-                          unsigned int relation)
-{
-        unsigned int new_index = 0;
-
-        if (cpufreq_frequency_table_target(policy,
-                                           &us2e_freq_table[policy->cpu].table[0],
-                                           target_freq, relation, &new_index))
-                return -EINVAL;
-
-        us2e_set_cpu_divider_index(policy->cpu, new_index);
-
-        return 0;
-}
-
-static int us2e_freq_verify(struct cpufreq_policy *policy)
-{
-        return cpufreq_frequency_table_verify(policy,
-                                              &us2e_freq_table[policy->cpu].table[0]);
-}
-
-static int __init us2e_freq_cpu_init(struct cpufreq_policy *policy)
-{
-        unsigned int cpu = policy->cpu;
-        unsigned long clock_tick = sparc64_get_clock_tick(cpu) / 1000;
-        struct cpufreq_frequency_table *table =
-                &us2e_freq_table[cpu].table[0];
-
-        table[0].index = 0;
-        table[0].frequency = clock_tick / 1;
-        table[1].index = 1;
-        table[1].frequency = clock_tick / 2;
-        table[2].index = 2;
-        table[2].frequency = clock_tick / 4;
-        table[2].index = 3;
-        table[2].frequency = clock_tick / 6;
-        table[2].index = 4;
-        table[2].frequency = clock_tick / 8;
-        table[2].index = 5;
-        table[3].frequency = CPUFREQ_TABLE_END;
-
-        policy->cpuinfo.transition_latency = 0;
-        policy->cur = clock_tick;
-
-        return cpufreq_frequency_table_cpuinfo(policy, table);
-}
-
-static int us2e_freq_cpu_exit(struct cpufreq_policy *policy)
-{
-        if (cpufreq_us2e_driver)
-                us2e_set_cpu_divider_index(policy->cpu, 0);
-
-        return 0;
-}
-
-static int __init us2e_freq_init(void)
-{
-        unsigned long manuf, impl, ver;
-        int ret;
-
-        if (tlb_type != spitfire)
-                return -ENODEV;
-
-        __asm__("rdpr %%ver, %0" : "=r" (ver));
-        manuf = ((ver >> 48) & 0xffff);
-        impl  = ((ver >> 32) & 0xffff);
-
-        if (manuf == 0x17 && impl == 0x13) {
-                struct cpufreq_driver *driver;
-
-                ret = -ENOMEM;
-                driver = kzalloc(sizeof(struct cpufreq_driver), GFP_KERNEL);
-                if (!driver)
-                        goto err_out;
-
-                us2e_freq_table = kzalloc(
-                        (NR_CPUS * sizeof(struct us2e_freq_percpu_info)),
-                        GFP_KERNEL);
-                if (!us2e_freq_table)
-                        goto err_out;
-
-                driver->init = us2e_freq_cpu_init;
-                driver->verify = us2e_freq_verify;
-                driver->target = us2e_freq_target;
-                driver->get = us2e_freq_get;
-                driver->exit = us2e_freq_cpu_exit;
-                driver->owner = THIS_MODULE,
-                strcpy(driver->name, "UltraSPARC-IIe");
-
-                cpufreq_us2e_driver = driver;
-                ret = cpufreq_register_driver(driver);
-                if (ret)
-                        goto err_out;
-
-                return 0;
-
-err_out:
-                if (driver) {
-                        kfree(driver);
-                        cpufreq_us2e_driver = NULL;
-                }
-                kfree(us2e_freq_table);
-                us2e_freq_table = NULL;
-                return ret;
-        }
-
-        return -ENODEV;
-}
-
-static void __exit us2e_freq_exit(void)
-{
-        if (cpufreq_us2e_driver) {
-                cpufreq_unregister_driver(cpufreq_us2e_driver);
-                kfree(cpufreq_us2e_driver);
-                cpufreq_us2e_driver = NULL;
-                kfree(us2e_freq_table);
-                us2e_freq_table = NULL;
-        }
-}
-
-MODULE_AUTHOR("David S. Miller <davem@redhat.com>");
-MODULE_DESCRIPTION("cpufreq driver for UltraSPARC-IIe");
-MODULE_LICENSE("GPL");
-
-module_init(us2e_freq_init);
-module_exit(us2e_freq_exit);
diff --git a/arch/sparc/kernel/us3_cpufreq.c b/arch/sparc/kernel/us3_cpufreq.c
deleted file mode 100644
index eb1624b931d9..000000000000
--- a/arch/sparc/kernel/us3_cpufreq.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/* us3_cpufreq.c: UltraSPARC-III cpu frequency support
- *
- * Copyright (C) 2003 David S. Miller (davem@redhat.com)
- *
- * Many thanks to Dominik Brodowski for fixing up the cpufreq
- * infrastructure in order to make this driver easier to implement.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/smp.h>
-#include <linux/cpufreq.h>
-#include <linux/threads.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-
-#include <asm/head.h>
-#include <asm/timer.h>
-
-static struct cpufreq_driver *cpufreq_us3_driver;
-
-struct us3_freq_percpu_info {
-        struct cpufreq_frequency_table table[4];
-};
-
-/* Indexed by cpu number. */
-static struct us3_freq_percpu_info *us3_freq_table;
-
-/* UltraSPARC-III has three dividers: 1, 2, and 32.  These are controlled
- * in the Safari config register.
- */
-#define SAFARI_CFG_DIV_1        0x0000000000000000UL
-#define SAFARI_CFG_DIV_2        0x0000000040000000UL
-#define SAFARI_CFG_DIV_32       0x0000000080000000UL
-#define SAFARI_CFG_DIV_MASK     0x00000000C0000000UL
-
-static unsigned long read_safari_cfg(void)
-{
-        unsigned long ret;
-
-        __asm__ __volatile__("ldxa      [%%g0] %1, %0"
-                             : "=&r" (ret)
-                             : "i" (ASI_SAFARI_CONFIG));
-        return ret;
-}
-
-static void write_safari_cfg(unsigned long val)
-{
-        __asm__ __volatile__("stxa      %0, [%%g0] %1\n\t"
-                             "membar    #Sync"
-                             : /* no outputs */
-                             : "r" (val), "i" (ASI_SAFARI_CONFIG)
-                             : "memory");
-}
-
-static unsigned long get_current_freq(unsigned int cpu, unsigned long safari_cfg)
-{
-        unsigned long clock_tick = sparc64_get_clock_tick(cpu) / 1000;
-        unsigned long ret;
-
-        switch (safari_cfg & SAFARI_CFG_DIV_MASK) {
-        case SAFARI_CFG_DIV_1:
-                ret = clock_tick / 1;
-                break;
-        case SAFARI_CFG_DIV_2:
-                ret = clock_tick / 2;
-                break;
-        case SAFARI_CFG_DIV_32:
-                ret = clock_tick / 32;
-                break;
-        default:
-                BUG();
-        }
-
-        return ret;
-}
-
-static unsigned int us3_freq_get(unsigned int cpu)
-{
-        cpumask_t cpus_allowed;
-        unsigned long reg;
-        unsigned int ret;
-
-        if (!cpu_online(cpu))
-                return 0;
-
-        cpumask_copy(&cpus_allowed, tsk_cpus_allowed(current));
-        set_cpus_allowed_ptr(current, cpumask_of(cpu));
-
-        reg = read_safari_cfg();
-        ret = get_current_freq(cpu, reg);
-
-        set_cpus_allowed_ptr(current, &cpus_allowed);
-
-        return ret;
-}
-
-static void us3_set_cpu_divider_index(unsigned int cpu, unsigned int index)
-{
-        unsigned long new_bits, new_freq, reg;
-        cpumask_t cpus_allowed;
-        struct cpufreq_freqs freqs;
-
-        if (!cpu_online(cpu))
-                return;
-
-        cpumask_copy(&cpus_allowed, tsk_cpus_allowed(current));
-        set_cpus_allowed_ptr(current, cpumask_of(cpu));
-
-        new_freq = sparc64_get_clock_tick(cpu) / 1000;
-        switch (index) {
-        case 0:
-                new_bits = SAFARI_CFG_DIV_1;
-                new_freq /= 1;
-                break;
-        case 1:
-                new_bits = SAFARI_CFG_DIV_2;
-                new_freq /= 2;
-                break;
-        case 2:
-                new_bits = SAFARI_CFG_DIV_32;
-                new_freq /= 32;
-                break;
-
-        default:
-                BUG();
-        }
-
-        reg = read_safari_cfg();
-
-        freqs.old = get_current_freq(cpu, reg);
-        freqs.new = new_freq;
-        freqs.cpu = cpu;
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
-        reg &= ~SAFARI_CFG_DIV_MASK;
-        reg |= new_bits;
-        write_safari_cfg(reg);
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
-        set_cpus_allowed_ptr(current, &cpus_allowed);
-}
-
-static int us3_freq_target(struct cpufreq_policy *policy,
-                          unsigned int target_freq,
-                          unsigned int relation)
-{
-        unsigned int new_index = 0;
-
-        if (cpufreq_frequency_table_target(policy,
-                                           &us3_freq_table[policy->cpu].table[0],
-                                           target_freq,
-                                           relation,
-                                           &new_index))
-                return -EINVAL;
-
-        us3_set_cpu_divider_index(policy->cpu, new_index);
-
-        return 0;
-}
-
-static int us3_freq_verify(struct cpufreq_policy *policy)
-{
-        return cpufreq_frequency_table_verify(policy,
-                                              &us3_freq_table[policy->cpu].table[0]);
-}
-
-static int __init us3_freq_cpu_init(struct cpufreq_policy *policy)
-{
-        unsigned int cpu = policy->cpu;
-        unsigned long clock_tick = sparc64_get_clock_tick(cpu) / 1000;
-        struct cpufreq_frequency_table *table =
-                &us3_freq_table[cpu].table[0];
-
-        table[0].index = 0;
-        table[0].frequency = clock_tick / 1;
-        table[1].index = 1;
-        table[1].frequency = clock_tick / 2;
-        table[2].index = 2;
-        table[2].frequency = clock_tick / 32;
-        table[3].index = 0;
-        table[3].frequency = CPUFREQ_TABLE_END;
-
-        policy->cpuinfo.transition_latency = 0;
-        policy->cur = clock_tick;
-
-        return cpufreq_frequency_table_cpuinfo(policy, table);
-}
-
-static int us3_freq_cpu_exit(struct cpufreq_policy *policy)
-{
-        if (cpufreq_us3_driver)
-                us3_set_cpu_divider_index(policy->cpu, 0);
-
-        return 0;
-}
-
-static int __init us3_freq_init(void)
-{
-        unsigned long manuf, impl, ver;
-        int ret;
-
-        if (tlb_type != cheetah && tlb_type != cheetah_plus)
-                return -ENODEV;
-
-        __asm__("rdpr %%ver, %0" : "=r" (ver));
-        manuf = ((ver >> 48) & 0xffff);
-        impl  = ((ver >> 32) & 0xffff);
-
-        if (manuf == CHEETAH_MANUF &&
-            (impl == CHEETAH_IMPL ||
-             impl == CHEETAH_PLUS_IMPL ||
-             impl == JAGUAR_IMPL ||
-             impl == PANTHER_IMPL)) {
-                struct cpufreq_driver *driver;
-
-                ret = -ENOMEM;
-                driver = kzalloc(sizeof(struct cpufreq_driver), GFP_KERNEL);
-                if (!driver)
-                        goto err_out;
-
-                us3_freq_table = kzalloc(
-                        (NR_CPUS * sizeof(struct us3_freq_percpu_info)),
-                        GFP_KERNEL);
-                if (!us3_freq_table)
-                        goto err_out;
-
-                driver->init = us3_freq_cpu_init;
-                driver->verify = us3_freq_verify;
-                driver->target = us3_freq_target;
-                driver->get = us3_freq_get;
-                driver->exit = us3_freq_cpu_exit;
-                driver->owner = THIS_MODULE,
-                strcpy(driver->name, "UltraSPARC-III");
-
-                cpufreq_us3_driver = driver;
-                ret = cpufreq_register_driver(driver);
-                if (ret)
-                        goto err_out;
-
-                return 0;
-
-err_out:
-                if (driver) {
-                        kfree(driver);
-                        cpufreq_us3_driver = NULL;
-                }
-                kfree(us3_freq_table);
-                us3_freq_table = NULL;
-                return ret;
-        }
-
-        return -ENODEV;
-}
-
-static void __exit us3_freq_exit(void)
-{
-        if (cpufreq_us3_driver) {
-                cpufreq_unregister_driver(cpufreq_us3_driver);
-                kfree(cpufreq_us3_driver);
-                cpufreq_us3_driver = NULL;
-                kfree(us3_freq_table);
-                us3_freq_table = NULL;
-        }
-}
-
-MODULE_AUTHOR("David S. Miller <davem@redhat.com>");
-MODULE_DESCRIPTION("cpufreq driver for UltraSPARC-III");
-MODULE_LICENSE("GPL");
-
-module_init(us3_freq_init);
-module_exit(us3_freq_exit);
diff --git a/arch/sparc/kernel/vio.c b/arch/sparc/kernel/vio.c
index 3e244f31e56b..8647fcc5ca6c 100644
--- a/arch/sparc/kernel/vio.c
+++ b/arch/sparc/kernel/vio.c
@@ -342,6 +342,7 @@ static void vio_remove(struct mdesc_handle *hp, u64 node)
                 printk(KERN_INFO "VIO: Removing device %s\n", dev_name(dev));
 
                 device_unregister(dev);
+                put_device(dev);
         }
 }
 
diff --git a/arch/sparc/lib/Makefile b/arch/sparc/lib/Makefile
index 8410065f2862..dbe119b63b48 100644
--- a/arch/sparc/lib/Makefile
+++ b/arch/sparc/lib/Makefile
@@ -45,4 +45,3 @@ obj-y                 += iomap.o
 obj-$(CONFIG_SPARC32) += atomic32.o ucmpdi2.o
 obj-y                 += ksyms.o
 obj-$(CONFIG_SPARC64) += PeeCeeI.o
-obj-y                 += usercopy.o
diff --git a/arch/sparc/lib/usercopy.c b/arch/sparc/lib/usercopy.c
deleted file mode 100644
index 5c4284ce1c03..000000000000
--- a/arch/sparc/lib/usercopy.c
+++ /dev/null
@@ -1,9 +0,0 @@
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/bug.h>
-
-void copy_from_user_overflow(void)
-{
-        WARN(1, "Buffer overflow detected!\n");
-}
-EXPORT_SYMBOL(copy_from_user_overflow);
diff --git a/arch/sparc/mm/init_32.c b/arch/sparc/mm/init_32.c
index 48e0c030e8f5..4490c397bb5b 100644
--- a/arch/sparc/mm/init_32.c
+++ b/arch/sparc/mm/init_32.c
@@ -282,14 +282,8 @@ static void map_high_region(unsigned long start_pfn, unsigned long end_pfn)
         printk("mapping high region %08lx - %08lx\n", start_pfn, end_pfn);
 #endif
 
-        for (tmp = start_pfn; tmp < end_pfn; tmp++) {
-                struct page *page = pfn_to_page(tmp);
-
-                ClearPageReserved(page);
-                init_page_count(page);
-                __free_page(page);
-                totalhigh_pages++;
-        }
+        for (tmp = start_pfn; tmp < end_pfn; tmp++)
+                free_highmem_page(pfn_to_page(tmp));
 }
 
 void __init mem_init(void)
@@ -347,8 +341,6 @@ void __init mem_init(void)
                 map_high_region(start_pfn, end_pfn);
         }
         
-        totalram_pages += totalhigh_pages;
-
         codepages = (((unsigned long) &_etext) - ((unsigned long)&_start));
         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
         datapages = (((unsigned long) &_edata) - ((unsigned long)&_etext));
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index 1588d33d5492..cf72a8a5b3aa 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -681,10 +681,9 @@ void get_new_mmu_context(struct mm_struct *mm)
 {
         unsigned long ctx, new_ctx;
         unsigned long orig_pgsz_bits;
-        unsigned long flags;
         int new_version;
 
-        spin_lock_irqsave(&ctx_alloc_lock, flags);
+        spin_lock(&ctx_alloc_lock);
         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
@@ -720,7 +719,7 @@ void get_new_mmu_context(struct mm_struct *mm)
 out:
         tlb_context_cache = new_ctx;
         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
-        spin_unlock_irqrestore(&ctx_alloc_lock, flags);
+        spin_unlock(&ctx_alloc_lock);
 
         if (unlikely(new_version))
                 smp_new_mmu_context_version();
@@ -2125,7 +2124,6 @@ void free_initmem(void)
                         ClearPageReserved(p);
                         init_page_count(p);
                         __free_page(p);
-                        num_physpages++;
                         totalram_pages++;
                 }
         }
@@ -2142,7 +2140,6 @@ void free_initrd_mem(unsigned long start, unsigned long end)
                 ClearPageReserved(p);
                 init_page_count(p);
                 __free_page(p);
-                num_physpages++;
                 totalram_pages++;
         }
 }
@@ -2181,10 +2178,9 @@ unsigned long vmemmap_table[VMEMMAP_SIZE];
 static long __meminitdata addr_start, addr_end;
 static int __meminitdata node_start;
 
-int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
+int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
+                               int node)
 {
-        unsigned long vstart = (unsigned long) start;
-        unsigned long vend = (unsigned long) (start + nr);
         unsigned long phys_start = (vstart - VMEMMAP_BASE);
         unsigned long phys_end = (vend - VMEMMAP_BASE);
         unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
@@ -2236,7 +2232,7 @@ void __meminit vmemmap_populate_print_last(void)
         }
 }
 
-void vmemmap_free(struct page *memmap, unsigned long nr_pages)
+void vmemmap_free(unsigned long start, unsigned long end)
 {
 }
 
diff --git a/arch/sparc/mm/tlb.c b/arch/sparc/mm/tlb.c
index 272aa4f7657e..83d89bcb44af 100644
--- a/arch/sparc/mm/tlb.c
+++ b/arch/sparc/mm/tlb.c
@@ -87,7 +87,7 @@ static void tlb_batch_add_one(struct mm_struct *mm, unsigned long vaddr,
         if (!tb->active) {
                 global_flush_tlb_page(mm, vaddr);
                 flush_tsb_user_page(mm, vaddr);
-                return;
+                goto out;
         }
 
         if (nr == 0)
@@ -98,6 +98,7 @@ static void tlb_batch_add_one(struct mm_struct *mm, unsigned long vaddr,
         if (nr >= TLB_BATCH_NR)
                 flush_tlb_pending();
 
+out:
         put_cpu_var(tlb_batch);
 }
 
diff --git a/arch/sparc/power/Makefile b/arch/sparc/power/Makefile
new file mode 100644
index 000000000000..3201ace0ddbd
--- /dev/null
+++ b/arch/sparc/power/Makefile
@@ -0,0 +1,3 @@
+# Makefile for Sparc-specific hibernate files.
+
+obj-$(CONFIG_HIBERNATION)       += hibernate.o hibernate_asm.o
diff --git a/arch/sparc/power/hibernate.c b/arch/sparc/power/hibernate.c
new file mode 100644
index 000000000000..42b0b8ce699a
--- /dev/null
+++ b/arch/sparc/power/hibernate.c
@@ -0,0 +1,42 @@
+/*
+ * hibernate.c:  Hibernaton support specific for sparc64.
+ *
+ * Copyright (C) 2013 Kirill V Tkhai (tkhai@yandex.ru)
+ */
+
+#include <linux/mm.h>
+
+#include <asm/hibernate.h>
+#include <asm/visasm.h>
+#include <asm/page.h>
+#include <asm/tlb.h>
+
+/* References to section boundaries */
+extern const void __nosave_begin, __nosave_end;
+
+struct saved_context saved_context;
+
+/*
+ *      pfn_is_nosave - check if given pfn is in the 'nosave' section
+ */
+
+int pfn_is_nosave(unsigned long pfn)
+{
+        unsigned long nosave_begin_pfn = PFN_DOWN((unsigned long)&__nosave_begin);
+        unsigned long nosave_end_pfn = PFN_DOWN((unsigned long)&__nosave_end);
+
+        return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
+}
+
+void save_processor_state(void)
+{
+        save_and_clear_fpu();
+}
+
+void restore_processor_state(void)
+{
+        struct mm_struct *mm = current->active_mm;
+
+        load_secondary_context(mm);
+        tsb_context_switch(mm);
+}
diff --git a/arch/sparc/power/hibernate_asm.S b/arch/sparc/power/hibernate_asm.S
new file mode 100644
index 000000000000..79942166df84
--- /dev/null
+++ b/arch/sparc/power/hibernate_asm.S
@@ -0,0 +1,131 @@
+/*
+ * hibernate_asm.S:  Hibernaton support specific for sparc64.
+ *
+ * Copyright (C) 2013 Kirill V Tkhai (tkhai@yandex.ru)
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/asm-offsets.h>
+#include <asm/cpudata.h>
+#include <asm/page.h>
+
+ENTRY(swsusp_arch_suspend)
+        save    %sp, -128, %sp
+        save    %sp, -128, %sp
+        flushw
+
+        setuw   saved_context, %g3
+
+        /* Save window regs */
+        rdpr    %cwp, %g2
+        stx     %g2, [%g3 + SC_REG_CWP]
+        rdpr    %wstate, %g2
+        stx     %g2, [%g3 + SC_REG_WSTATE]
+        stx     %fp, [%g3 + SC_REG_FP]
+
+        /* Save state regs */
+        rdpr    %tick, %g2
+        stx     %g2, [%g3 + SC_REG_TICK]
+        rdpr    %pstate, %g2
+        stx     %g2, [%g3 + SC_REG_PSTATE]
+
+        /* Save global regs */
+        stx     %g4, [%g3 + SC_REG_G4]
+        stx     %g5, [%g3 + SC_REG_G5]
+        stx     %g6, [%g3 + SC_REG_G6]
+
+        call    swsusp_save
+         nop
+
+        mov     %o0, %i0
+        restore
+
+        mov     %o0, %i0
+        ret
+         restore
+
+ENTRY(swsusp_arch_resume)
+        /* Write restore_pblist to %l0 */
+        sethi   %hi(restore_pblist), %l0
+        ldx     [%l0 + %lo(restore_pblist)], %l0
+
+        call    __flush_tlb_all
+         nop
+
+        /* Write PAGE_OFFSET to %g7 */
+        sethi   %uhi(PAGE_OFFSET), %g7
+        sllx    %g7, 32, %g7
+
+        setuw   (PAGE_SIZE-8), %g3
+
+        /* Use MMU Bypass */
+        rd      %asi, %g1
+        wr      %g0, ASI_PHYS_USE_EC, %asi
+
+        ba      fill_itlb
+         nop
+
+pbe_loop:
+        cmp     %l0, %g0
+        be      restore_ctx
+         sub    %l0, %g7, %l0
+
+        ldxa    [%l0    ] %asi, %l1 /* address */
+        ldxa    [%l0 + 8] %asi, %l2 /* orig_address */
+
+        /* phys addr */
+        sub     %l1, %g7, %l1
+        sub     %l2, %g7, %l2
+
+        mov     %g3, %l3 /* PAGE_SIZE-8 */
+copy_loop:
+        ldxa    [%l1 + %l3] ASI_PHYS_USE_EC, %g2
+        stxa    %g2, [%l2 + %l3] ASI_PHYS_USE_EC
+        cmp     %l3, %g0
+        bne     copy_loop
+         sub    %l3, 8, %l3
+
+        /* next pbe */
+        ba      pbe_loop
+         ldxa   [%l0 + 16] %asi, %l0
+
+restore_ctx:
+        setuw   saved_context, %g3
+
+        /* Restore window regs */
+        wrpr    %g0, 0, %canrestore
+        wrpr    %g0, 0, %otherwin
+        wrpr    %g0, 6, %cansave
+        wrpr    %g0, 0, %cleanwin
+
+        ldxa    [%g3 + SC_REG_CWP] %asi, %g2
+        wrpr    %g2, %cwp
+        ldxa    [%g3 + SC_REG_WSTATE] %asi, %g2
+        wrpr    %g2, %wstate
+        ldxa    [%g3 + SC_REG_FP] %asi, %fp
+
+        /* Restore state regs */
+        ldxa    [%g3 + SC_REG_PSTATE] %asi, %g2
+        wrpr    %g2, %pstate
+        ldxa    [%g3 + SC_REG_TICK] %asi, %g2
+        wrpr    %g2, %tick
+
+        /* Restore global regs */
+        ldxa    [%g3 + SC_REG_G4] %asi, %g4
+        ldxa    [%g3 + SC_REG_G5] %asi, %g5
+        ldxa    [%g3 + SC_REG_G6] %asi, %g6
+
+        wr      %g1, %g0, %asi
+
+        restore
+        restore
+
+        wrpr    %g0, 14, %pil
+
+        retl
+         mov    %g0, %o0
+
+fill_itlb:
+        ba      pbe_loop
+         wrpr   %g0, 15, %pil
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index 25877aebc685..5b6a40dd5556 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
@@ -16,12 +16,15 @@ config TILE
         select GENERIC_PENDING_IRQ if SMP
         select GENERIC_IRQ_SHOW
         select HAVE_DEBUG_BUGVERBOSE
-        select HAVE_SYSCALL_WRAPPERS if TILEGX
         select VIRT_TO_BUS
         select SYS_HYPERVISOR
+        select ARCH_HAS_DEBUG_STRICT_USER_COPY_CHECKS
         select ARCH_HAVE_NMI_SAFE_CMPXCHG
         select GENERIC_CLOCKEVENTS
         select MODULES_USE_ELF_RELA
+        select HAVE_ARCH_TRACEHOOK
+        select HAVE_SYSCALL_TRACEPOINTS
+        select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
 
 # FIXME: investigate whether we need/want these options.
 #       select HAVE_IOREMAP_PROT
@@ -40,9 +43,6 @@ config MMU
 config GENERIC_CSUM
         def_bool y
 
-config SEMAPHORE_SLEEPERS
-        def_bool y
-
 config HAVE_ARCH_ALLOC_REMAP
         def_bool y
 
@@ -67,12 +67,6 @@ config HUGETLB_SUPER_PAGES
 config RWSEM_GENERIC_SPINLOCK
         def_bool y
 
-# We have a very flat architecture from a migration point of view,
-# so save boot time by presetting this (particularly useful on tile-sim).
-config DEFAULT_MIGRATION_COST
-        int
-        default "10000000"
-
 # We only support gcc 4.4 and above, so this should work.
 config ARCH_SUPPORTS_OPTIMIZED_INLINING
         def_bool y
@@ -114,13 +108,6 @@ config STRICT_DEVMEM
 config SMP
         def_bool y
 
-# Allow checking for compile-time determined overflow errors in
-# copy_from_user().  There are still unprovable places in the
-# generic code as of 2.6.34, so this option is not really compatible
-# with -Werror, which is more useful in general.
-config DEBUG_COPY_FROM_USER
-        def_bool n
-
 config HVC_TILE
         depends on TTY
         select HVC_DRIVER
@@ -420,11 +407,6 @@ endmenu
 
 menu "Executable file formats"
 
-# only elf supported
-config KCORE_ELF
-        def_bool y
-        depends on PROC_FS
-
 source "fs/Kconfig.binfmt"
 
 endmenu
diff --git a/arch/tile/include/asm/atomic.h b/arch/tile/include/asm/atomic.h
index f2461429a4a4..e71387ab20ca 100644
--- a/arch/tile/include/asm/atomic.h
+++ b/arch/tile/include/asm/atomic.h
@@ -131,4 +131,25 @@ static inline int atomic_read(const atomic_t *v)
 #include <asm/atomic_64.h>
 #endif
 
+#ifndef __ASSEMBLY__
+
+static inline long long atomic64_dec_if_positive(atomic64_t *v)
+{
+        long long c, old, dec;
+
+        c = atomic64_read(v);
+        for (;;) {
+                dec = c - 1;
+                if (unlikely(dec < 0))
+                        break;
+                old = atomic64_cmpxchg((v), c, dec);
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return dec;
+}
+
+#endif /* __ASSEMBLY__ */
+
 #endif /* _ASM_TILE_ATOMIC_H */
diff --git a/arch/tile/include/asm/hugetlb.h b/arch/tile/include/asm/hugetlb.h
index 0f885af2b621..3257733003f8 100644
--- a/arch/tile/include/asm/hugetlb.h
+++ b/arch/tile/include/asm/hugetlb.h
@@ -16,6 +16,7 @@
 #define _ASM_TILE_HUGETLB_H
 
 #include <asm/page.h>
+#include <asm-generic/hugetlb.h>
 
 
 static inline int is_hugepage_only_range(struct mm_struct *mm,
diff --git a/arch/tile/include/asm/ptrace.h b/arch/tile/include/asm/ptrace.h
index 2e83fc1b9467..fd412260aff7 100644
--- a/arch/tile/include/asm/ptrace.h
+++ b/arch/tile/include/asm/ptrace.h
@@ -44,7 +44,8 @@ typedef unsigned long pt_reg_t;
 struct pt_regs *get_pt_regs(struct pt_regs *);
 
 /* Trace the current syscall. */
-extern void do_syscall_trace(void);
+extern int do_syscall_trace_enter(struct pt_regs *regs);
+extern void do_syscall_trace_exit(struct pt_regs *regs);
 
 #define arch_has_single_step()  (1)
 
diff --git a/arch/tile/include/asm/syscall.h b/arch/tile/include/asm/syscall.h
index d35e0dcb67b1..9644b88f133d 100644
--- a/arch/tile/include/asm/syscall.h
+++ b/arch/tile/include/asm/syscall.h
@@ -22,6 +22,12 @@
 #include <linux/err.h>
 #include <arch/abi.h>
 
+/* The array of function pointers for syscalls. */
+extern void *sys_call_table[];
+#ifdef CONFIG_COMPAT
+extern void *compat_sys_call_table[];
+#endif
+
 /*
  * Only the low 32 bits of orig_r0 are meaningful, so we return int.
  * This importantly ignores the high bits on 64-bit, so comparisons
diff --git a/arch/tile/include/asm/syscalls.h b/arch/tile/include/asm/syscalls.h
index 78886e2417a6..07b298450ef2 100644
--- a/arch/tile/include/asm/syscalls.h
+++ b/arch/tile/include/asm/syscalls.h
@@ -24,12 +24,6 @@
 #include <linux/types.h>
 #include <linux/compat.h>
 
-/* The array of function pointers for syscalls. */
-extern void *sys_call_table[];
-#ifdef CONFIG_COMPAT
-extern void *compat_sys_call_table[];
-#endif
-
 /*
  * Note that by convention, any syscall which requires the current
  * register set takes an additional "struct pt_regs *" pointer; a
diff --git a/arch/tile/include/asm/thread_info.h b/arch/tile/include/asm/thread_info.h
index e9c670d7a7fe..d1733dee98a2 100644
--- a/arch/tile/include/asm/thread_info.h
+++ b/arch/tile/include/asm/thread_info.h
@@ -124,6 +124,7 @@ extern void _cpu_idle(void);
 #define TIF_SECCOMP             6       /* secure computing */
 #define TIF_MEMDIE              7       /* OOM killer at work */
 #define TIF_NOTIFY_RESUME       8       /* callback before returning to user */
+#define TIF_SYSCALL_TRACEPOINT  9       /* syscall tracepoint instrumentation */
 
 #define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
@@ -134,12 +135,19 @@ extern void _cpu_idle(void);
 #define _TIF_SECCOMP            (1<<TIF_SECCOMP)
 #define _TIF_MEMDIE             (1<<TIF_MEMDIE)
 #define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
+#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
 
 /* Work to do on any return to user space. */
 #define _TIF_ALLWORK_MASK \
   (_TIF_SIGPENDING|_TIF_NEED_RESCHED|_TIF_SINGLESTEP|\
    _TIF_ASYNC_TLB|_TIF_NOTIFY_RESUME)
 
+/* Work to do at syscall entry. */
+#define _TIF_SYSCALL_ENTRY_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT)
+
+/* Work to do at syscall exit. */
+#define _TIF_SYSCALL_EXIT_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT)
+
 /*
  * Thread-synchronous status.
  *
@@ -153,8 +161,6 @@ extern void _cpu_idle(void);
 #define TS_POLLING              0x0004  /* in idle loop but not sleeping */
 #define TS_RESTORE_SIGMASK      0x0008  /* restore signal mask in do_signal */
 
-#define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING)
-
 #ifndef __ASSEMBLY__
 #define HAVE_SET_RESTORE_SIGMASK        1
 static inline void set_restore_sigmask(void)
diff --git a/arch/tile/include/asm/uaccess.h b/arch/tile/include/asm/uaccess.h
index 9ab078a4605d..8a082bc6bca5 100644
--- a/arch/tile/include/asm/uaccess.h
+++ b/arch/tile/include/asm/uaccess.h
@@ -395,7 +395,12 @@ _copy_from_user(void *to, const void __user *from, unsigned long n)
         return n;
 }
 
-#ifdef CONFIG_DEBUG_COPY_FROM_USER
+#ifdef CONFIG_DEBUG_STRICT_USER_COPY_CHECKS
+/*
+ * There are still unprovable places in the generic code as of 2.6.34, so this
+ * option is not really compatible with -Werror, which is more useful in
+ * general.
+ */
 extern void copy_from_user_overflow(void)
         __compiletime_warning("copy_from_user() size is not provably correct");
 
diff --git a/arch/tile/include/uapi/asm/unistd.h b/arch/tile/include/uapi/asm/unistd.h
index cd7b6dd9d471..3866397aaf5a 100644
--- a/arch/tile/include/uapi/asm/unistd.h
+++ b/arch/tile/include/uapi/asm/unistd.h
@@ -20,6 +20,8 @@
 /* Use the standard ABI for syscalls. */
 #include <asm-generic/unistd.h>
 
+#define NR_syscalls __NR_syscalls
+
 /* Additional Tilera-specific syscalls. */
 #define __NR_cacheflush (__NR_arch_specific_syscall + 1)
 __SYSCALL(__NR_cacheflush, sys_cacheflush)
diff --git a/arch/tile/kernel/compat.c b/arch/tile/kernel/compat.c
index 6ea4cdb3c6a0..ed378416b86a 100644
--- a/arch/tile/kernel/compat.c
+++ b/arch/tile/kernel/compat.c
@@ -56,12 +56,6 @@ COMPAT_SYSCALL_DEFINE6(pwrite64, unsigned int, fd, char __user *, ubuf,
         return sys_pwrite64(fd, ubuf, count, ((loff_t)high << 32) | low);
 }
 
-COMPAT_SYSCALL_DEFINE4(lookup_dcookie, u32, low, u32, high,
-                       char __user *, buf, size_t, len)
-{
-        return sys_lookup_dcookie(((loff_t)high << 32) | low, buf, len);
-}
-
 COMPAT_SYSCALL_DEFINE6(sync_file_range2, int, fd, unsigned int, flags,
                        u32, offset_lo, u32, offset_hi,
                        u32, nbytes_lo, u32, nbytes_hi)
diff --git a/arch/tile/kernel/early_printk.c b/arch/tile/kernel/early_printk.c
index afb9c9a0d887..34d72a151bf3 100644
--- a/arch/tile/kernel/early_printk.c
+++ b/arch/tile/kernel/early_printk.c
@@ -17,6 +17,7 @@
 #include <linux/init.h>
 #include <linux/string.h>
 #include <linux/irqflags.h>
+#include <linux/printk.h>
 #include <asm/setup.h>
 #include <hv/hypervisor.h>
 
@@ -33,25 +34,8 @@ static struct console early_hv_console = {
 };
 
 /* Direct interface for emergencies */
-static struct console *early_console = &early_hv_console;
-static int early_console_initialized;
 static int early_console_complete;
 
-static void early_vprintk(const char *fmt, va_list ap)
-{
-        char buf[512];
-        int n = vscnprintf(buf, sizeof(buf), fmt, ap);
-        early_console->write(early_console, buf, n);
-}
-
-void early_printk(const char *fmt, ...)
-{
-        va_list ap;
-        va_start(ap, fmt);
-        early_vprintk(fmt, ap);
-        va_end(ap);
-}
-
 void early_panic(const char *fmt, ...)
 {
         va_list ap;
@@ -69,14 +53,13 @@ static int __initdata keep_early;
 
 static int __init setup_early_printk(char *str)
 {
-        if (early_console_initialized)
+        if (early_console)
                 return 1;
 
         if (str != NULL && strncmp(str, "keep", 4) == 0)
                 keep_early = 1;
 
         early_console = &early_hv_console;
-        early_console_initialized = 1;
         register_console(early_console);
 
         return 0;
@@ -85,12 +68,12 @@ static int __init setup_early_printk(char *str)
 void __init disable_early_printk(void)
 {
         early_console_complete = 1;
-        if (!early_console_initialized || !early_console)
+        if (!early_console)
                 return;
         if (!keep_early) {
                 early_printk("disabling early console\n");
                 unregister_console(early_console);
-                early_console_initialized = 0;
+                early_console = NULL;
         } else {
                 early_printk("keeping early console\n");
         }
@@ -98,7 +81,7 @@ void __init disable_early_printk(void)
 
 void warn_early_printk(void)
 {
-        if (early_console_complete || early_console_initialized)
+        if (early_console_complete || early_console)
                 return;
         early_printk("\
 Machine shutting down before console output is fully initialized.\n\
diff --git a/arch/tile/kernel/hardwall.c b/arch/tile/kernel/hardwall.c
index 20273ee37deb..38ac189d9575 100644
--- a/arch/tile/kernel/hardwall.c
+++ b/arch/tile/kernel/hardwall.c
@@ -914,7 +914,7 @@ static int hardwall_proc_show(struct seq_file *sf, void *v)
 static int hardwall_proc_open(struct inode *inode,
                               struct file *file)
 {
-        return single_open(file, hardwall_proc_show, PDE(inode)->data);
+        return single_open(file, hardwall_proc_show, PDE_DATA(inode));
 }
 
 static const struct file_operations hardwall_proc_fops = {
diff --git a/arch/tile/kernel/intvec_32.S b/arch/tile/kernel/intvec_32.S
index f212bf7cea86..cb52d66343ed 100644
--- a/arch/tile/kernel/intvec_32.S
+++ b/arch/tile/kernel/intvec_32.S
@@ -1201,7 +1201,10 @@ handle_syscall:
         lw      r30, r31
         andi    r30, r30, _TIF_SYSCALL_TRACE
         bzt     r30, .Lrestore_syscall_regs
-        jal     do_syscall_trace
+        {
+         PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
+         jal    do_syscall_trace_enter
+        }
         FEEDBACK_REENTER(handle_syscall)
 
         /*
@@ -1252,7 +1255,10 @@ handle_syscall:
         lw      r30, r31
         andi    r30, r30, _TIF_SYSCALL_TRACE
         bzt     r30, 1f
-        jal     do_syscall_trace
+        {
+         PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
+         jal    do_syscall_trace_exit
+        }
         FEEDBACK_REENTER(handle_syscall)
 1:      {
          movei  r30, 0               /* not an NMI */
diff --git a/arch/tile/kernel/intvec_64.S b/arch/tile/kernel/intvec_64.S
index 4ea080902654..85d483957027 100644
--- a/arch/tile/kernel/intvec_64.S
+++ b/arch/tile/kernel/intvec_64.S
@@ -1000,13 +1000,19 @@ handle_syscall:
 
         /* Trace syscalls, if requested. */
         addi    r31, r31, THREAD_INFO_FLAGS_OFFSET
-        ld      r30, r31
-        andi    r30, r30, _TIF_SYSCALL_TRACE
+        {
+         ld     r30, r31
+         moveli r32, _TIF_SYSCALL_ENTRY_WORK
+        }
+        and     r30, r30, r32
         {
          addi   r30, r31, THREAD_INFO_STATUS_OFFSET - THREAD_INFO_FLAGS_OFFSET
          beqzt  r30, .Lrestore_syscall_regs
         }
-        jal     do_syscall_trace
+        {
+         PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
+         jal    do_syscall_trace_enter
+        }
         FEEDBACK_REENTER(handle_syscall)
 
         /*
@@ -1071,13 +1077,19 @@ handle_syscall:
         FEEDBACK_REENTER(handle_syscall)
 
         /* Do syscall trace again, if requested. */
-        ld      r30, r31
-        andi    r0, r30, _TIF_SYSCALL_TRACE
+        {
+         ld      r30, r31
+         moveli  r32, _TIF_SYSCALL_EXIT_WORK
+        }
+        and      r0, r30, r32
         {
          andi    r0, r30, _TIF_SINGLESTEP
          beqzt   r0, 1f
         }
-        jal     do_syscall_trace
+        {
+         PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
+         jal    do_syscall_trace_exit
+        }
         FEEDBACK_REENTER(handle_syscall)
         andi    r0, r30, _TIF_SINGLESTEP
 
diff --git a/arch/tile/kernel/process.c b/arch/tile/kernel/process.c
index caf93ae11793..8ac304484f98 100644
--- a/arch/tile/kernel/process.c
+++ b/arch/tile/kernel/process.c
@@ -40,13 +40,11 @@
 #include <arch/abi.h>
 #include <arch/sim_def.h>
 
-
 /*
  * Use the (x86) "idle=poll" option to prefer low latency when leaving the
  * idle loop over low power while in the idle loop, e.g. if we have
  * one thread per core and we want to get threads out of futex waits fast.
  */
-static int no_idle_nap;
 static int __init idle_setup(char *str)
 {
         if (!str)
@@ -54,64 +52,19 @@ static int __init idle_setup(char *str)
 
         if (!strcmp(str, "poll")) {
                 pr_info("using polling idle threads.\n");
-                no_idle_nap = 1;
-        } else if (!strcmp(str, "halt"))
-                no_idle_nap = 0;
-        else
-                return -1;
-
-        return 0;
+                cpu_idle_poll_ctrl(true);
+                return 0;
+        } else if (!strcmp(str, "halt")) {
+                return 0;
+        }
+        return -1;
 }
 early_param("idle", idle_setup);
 
-/*
- * The idle thread. There's no useful work to be
- * done, so just try to conserve power and have a
- * low exit latency (ie sit in a loop waiting for
- * somebody to say that they'd like to reschedule)
- */
-void cpu_idle(void)
+void arch_cpu_idle(void)
 {
-        int cpu = smp_processor_id();
-
-
-        current_thread_info()->status |= TS_POLLING;
-
-        if (no_idle_nap) {
-                while (1) {
-                        while (!need_resched())
-                                cpu_relax();
-                        schedule();
-                }
-        }
-
-        /* endless idle loop with no priority at all */
-        while (1) {
-                tick_nohz_idle_enter();
-                rcu_idle_enter();
-                while (!need_resched()) {
-                        if (cpu_is_offline(cpu))
-                                BUG();  /* no HOTPLUG_CPU */
-
-                        local_irq_disable();
-                        __get_cpu_var(irq_stat).idle_timestamp = jiffies;
-                        current_thread_info()->status &= ~TS_POLLING;
-                        /*
-                         * TS_POLLING-cleared state must be visible before we
-                         * test NEED_RESCHED:
-                         */
-                        smp_mb();
-
-                        if (!need_resched())
-                                _cpu_idle();
-                        else
-                                local_irq_enable();
-                        current_thread_info()->status |= TS_POLLING;
-                }
-                rcu_idle_exit();
-                tick_nohz_idle_exit();
-                schedule_preempt_disabled();
-        }
+        __get_cpu_var(irq_stat).idle_timestamp = jiffies;
+        _cpu_idle();
 }
 
 /*
@@ -620,8 +573,7 @@ void show_regs(struct pt_regs *regs)
         int i;
 
         pr_err("\n");
-        pr_err(" Pid: %d, comm: %20s, CPU: %d\n",
-               tsk->pid, tsk->comm, smp_processor_id());
+        show_regs_print_info(KERN_ERR);
 #ifdef __tilegx__
         for (i = 0; i < 51; i += 3)
                 pr_err(" r%-2d: "REGFMT" r%-2d: "REGFMT" r%-2d: "REGFMT"\n",
diff --git a/arch/tile/kernel/ptrace.c b/arch/tile/kernel/ptrace.c
index 9835312d5a91..0f83ed4602b2 100644
--- a/arch/tile/kernel/ptrace.c
+++ b/arch/tile/kernel/ptrace.c
@@ -21,9 +21,13 @@
 #include <linux/uaccess.h>
 #include <linux/regset.h>
 #include <linux/elf.h>
+#include <linux/tracehook.h>
 #include <asm/traps.h>
 #include <arch/chip.h>
 
+#define CREATE_TRACE_POINTS
+#include <trace/events/syscalls.h>
+
 void user_enable_single_step(struct task_struct *child)
 {
         set_tsk_thread_flag(child, TIF_SINGLESTEP);
@@ -246,29 +250,26 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
 }
 #endif
 
-void do_syscall_trace(void)
+int do_syscall_trace_enter(struct pt_regs *regs)
 {
-        if (!test_thread_flag(TIF_SYSCALL_TRACE))
-                return;
+        if (test_thread_flag(TIF_SYSCALL_TRACE)) {
+                if (tracehook_report_syscall_entry(regs))
+                        regs->regs[TREG_SYSCALL_NR] = -1;
+        }
 
-        if (!(current->ptrace & PT_PTRACED))
-                return;
+        if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
+                trace_sys_enter(regs, regs->regs[TREG_SYSCALL_NR]);
 
-        /*
-         * The 0x80 provides a way for the tracing parent to distinguish
-         * between a syscall stop and SIGTRAP delivery
-         */
-        ptrace_notify(SIGTRAP|((current->ptrace & PT_TRACESYSGOOD) ? 0x80 : 0));
+        return regs->regs[TREG_SYSCALL_NR];
+}
 
-        /*
-         * this isn't the same as continuing with a signal, but it will do
-         * for normal use.  strace only continues with a signal if the
-         * stopping signal is not SIGTRAP.  -brl
-         */
-        if (current->exit_code) {
-                send_sig(current->exit_code, current, 1);
-                current->exit_code = 0;
-        }
+void do_syscall_trace_exit(struct pt_regs *regs)
+{
+        if (test_thread_flag(TIF_SYSCALL_TRACE))
+                tracehook_report_syscall_exit(regs, 0);
+
+        if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
+                trace_sys_exit(regs, regs->regs[0]);
 }
 
 void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs, int error_code)
diff --git a/arch/tile/kernel/smpboot.c b/arch/tile/kernel/smpboot.c
index e686c5ac90be..44bab29bf2f3 100644
--- a/arch/tile/kernel/smpboot.c
+++ b/arch/tile/kernel/smpboot.c
@@ -207,9 +207,7 @@ void __cpuinit online_secondary(void)
         /* Set up tile-timer clock-event device on this cpu */
         setup_tile_timer();
 
-        preempt_enable();
-
-        cpu_idle();
+        cpu_startup_entry(CPUHP_ONLINE);
 }
 
 int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
diff --git a/arch/tile/kernel/time.c b/arch/tile/kernel/time.c
index f6f50f2a5e37..5ac397ec6986 100644
--- a/arch/tile/kernel/time.c
+++ b/arch/tile/kernel/time.c
@@ -230,6 +230,10 @@ int setup_profiling_timer(unsigned int multiplier)
  */
 cycles_t ns2cycles(unsigned long nsecs)
 {
-        struct clock_event_device *dev = &__get_cpu_var(tile_timer);
+        /*
+         * We do not have to disable preemption here as each core has the same
+         * clock frequency.
+         */
+        struct clock_event_device *dev = &__raw_get_cpu_var(tile_timer);
         return ((u64)nsecs * dev->mult) >> dev->shift;
 }
diff --git a/arch/tile/lib/uaccess.c b/arch/tile/lib/uaccess.c
index f8d398c9ee7f..030abe3ee4f1 100644
--- a/arch/tile/lib/uaccess.c
+++ b/arch/tile/lib/uaccess.c
@@ -22,11 +22,3 @@ int __range_ok(unsigned long addr, unsigned long size)
                  is_arch_mappable_range(addr, size));
 }
 EXPORT_SYMBOL(__range_ok);
-
-#ifdef CONFIG_DEBUG_COPY_FROM_USER
-void copy_from_user_overflow(void)
-{
-       WARN(1, "Buffer overflow detected!\n");
-}
-EXPORT_SYMBOL(copy_from_user_overflow);
-#endif
diff --git a/arch/tile/mm/pgtable.c b/arch/tile/mm/pgtable.c
index b3b4972c2451..dfd63ce87327 100644
--- a/arch/tile/mm/pgtable.c
+++ b/arch/tile/mm/pgtable.c
@@ -592,12 +592,7 @@ void iounmap(volatile void __iomem *addr_in)
            in parallel. Reuse of the virtual address is prevented by
            leaving it in the global lists until we're done with it.
            cpa takes care of the direct mappings. */
-        read_lock(&vmlist_lock);
-        for (p = vmlist; p; p = p->next) {
-                if (p->addr == addr)
-                        break;
-        }
-        read_unlock(&vmlist_lock);
+        p = find_vm_area((void *)addr);
 
         if (!p) {
                 pr_err("iounmap: bad address %p\n", addr);
diff --git a/arch/um/drivers/chan_kern.c b/arch/um/drivers/chan_kern.c
index 80b47cb71e0a..acbe6c67afba 100644
--- a/arch/um/drivers/chan_kern.c
+++ b/arch/um/drivers/chan_kern.c
@@ -568,11 +568,7 @@ void chan_interrupt(struct line *line, int irq)
                 reactivate_fd(chan->fd, irq);
         if (err == -EIO) {
                 if (chan->primary) {
-                        struct tty_struct *tty = tty_port_tty_get(&line->port);
-                        if (tty != NULL) {
-                                tty_hangup(tty);
-                                tty_kref_put(tty);
-                        }
+                        tty_port_tty_hangup(&line->port, false);
                         if (line->chan_out != chan)
                                 close_one_chan(line->chan_out, 1);
                 }
diff --git a/arch/um/drivers/line.c b/arch/um/drivers/line.c
index be541cf69fd2..8035145f043b 100644
--- a/arch/um/drivers/line.c
+++ b/arch/um/drivers/line.c
@@ -248,7 +248,6 @@ static irqreturn_t line_write_interrupt(int irq, void *data)
 {
         struct chan *chan = data;
         struct line *line = chan->line;
-        struct tty_struct *tty;
         int err;
 
         /*
@@ -267,12 +266,7 @@ static irqreturn_t line_write_interrupt(int irq, void *data)
         }
         spin_unlock(&line->lock);
 
-        tty = tty_port_tty_get(&line->port);
-        if (tty == NULL)
-                return IRQ_NONE;
-
-        tty_wakeup(tty);
-        tty_kref_put(tty);
+        tty_port_tty_wakeup(&line->port);
 
         return IRQ_HANDLED;
 }
diff --git a/arch/um/drivers/mconsole_kern.c b/arch/um/drivers/mconsole_kern.c
index 4bd82ac0210f..d7d21851e60c 100644
--- a/arch/um/drivers/mconsole_kern.c
+++ b/arch/um/drivers/mconsole_kern.c
@@ -782,8 +782,7 @@ static int create_proc_mconsole(void)
 
         ent = proc_create("mconsole", 0200, NULL, &mconsole_proc_fops);
         if (ent == NULL) {
-                printk(KERN_INFO "create_proc_mconsole : create_proc_entry "
-                       "failed\n");
+                printk(KERN_INFO "create_proc_mconsole : proc_create failed\n");
                 return 0;
         }
         return 0;
diff --git a/arch/um/include/shared/common-offsets.h b/arch/um/include/shared/common-offsets.h
index 2df313b6a586..c92306809029 100644
--- a/arch/um/include/shared/common-offsets.h
+++ b/arch/um/include/shared/common-offsets.h
@@ -30,8 +30,8 @@ DEFINE(UM_NSEC_PER_USEC, NSEC_PER_USEC);
 #ifdef CONFIG_PRINTK
 DEFINE(UML_CONFIG_PRINTK, CONFIG_PRINTK);
 #endif
-#ifdef CONFIG_NO_HZ
-DEFINE(UML_CONFIG_NO_HZ, CONFIG_NO_HZ);
+#ifdef CONFIG_NO_HZ_COMMON
+DEFINE(UML_CONFIG_NO_HZ_COMMON, CONFIG_NO_HZ_COMMON);
 #endif
 #ifdef CONFIG_UML_X86
 DEFINE(UML_CONFIG_UML_X86, CONFIG_UML_X86);
diff --git a/arch/um/kernel/early_printk.c b/arch/um/kernel/early_printk.c
index 49480f092456..4a0800bc37b2 100644
--- a/arch/um/kernel/early_printk.c
+++ b/arch/um/kernel/early_printk.c
@@ -16,7 +16,7 @@ static void early_console_write(struct console *con, const char *s, unsigned int
         um_early_printk(s, n);
 }
 
-static struct console early_console = {
+static struct console early_console_dev = {
         .name = "earlycon",
         .write = early_console_write,
         .flags = CON_BOOT,
@@ -25,8 +25,10 @@ static struct console early_console = {
 
 static int __init setup_early_printk(char *buf)
 {
-        register_console(&early_console);
-
+        if (!early_console) {
+                early_console = &early_console_dev;
+                register_console(&early_console_dev);
+        }
         return 0;
 }
 
diff --git a/arch/um/kernel/mem.c b/arch/um/kernel/mem.c
index 5abcbfbe7e25..9df292b270a8 100644
--- a/arch/um/kernel/mem.c
+++ b/arch/um/kernel/mem.c
@@ -42,17 +42,12 @@ static unsigned long brk_end;
 static void setup_highmem(unsigned long highmem_start,
                           unsigned long highmem_len)
 {
-        struct page *page;
         unsigned long highmem_pfn;
         int i;
 
         highmem_pfn = __pa(highmem_start) >> PAGE_SHIFT;
-        for (i = 0; i < highmem_len >> PAGE_SHIFT; i++) {
-                page = &mem_map[highmem_pfn + i];
-                ClearPageReserved(page);
-                init_page_count(page);
-                __free_page(page);
-        }
+        for (i = 0; i < highmem_len >> PAGE_SHIFT; i++)
+                free_highmem_page(&mem_map[highmem_pfn + i]);
 }
 #endif
 
@@ -73,18 +68,13 @@ void __init mem_init(void)
         totalram_pages = free_all_bootmem();
         max_low_pfn = totalram_pages;
 #ifdef CONFIG_HIGHMEM
-        totalhigh_pages = highmem >> PAGE_SHIFT;
-        totalram_pages += totalhigh_pages;
+        setup_highmem(end_iomem, highmem);
 #endif
         num_physpages = totalram_pages;
         max_pfn = totalram_pages;
         printk(KERN_INFO "Memory: %luk available\n",
                nr_free_pages() << (PAGE_SHIFT-10));
         kmalloc_ok = 1;
-
-#ifdef CONFIG_HIGHMEM
-        setup_highmem(end_iomem, highmem);
-#endif
 }
 
 /*
@@ -254,15 +244,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        if (start < end)
-                printk(KERN_INFO "Freeing initrd memory: %ldk freed\n",
-                       (end - start) >> 10);
-        for (; start < end; start += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(start));
-                init_page_count(virt_to_page(start));
-                free_page(start);
-                totalram_pages++;
-        }
+        free_reserved_area(start, end, 0, "initrd");
 }
 #endif
 
diff --git a/arch/um/kernel/process.c b/arch/um/kernel/process.c
index b462b13c5bae..bbcef522bcb1 100644
--- a/arch/um/kernel/process.c
+++ b/arch/um/kernel/process.c
@@ -210,33 +210,14 @@ void initial_thread_cb(void (*proc)(void *), void *arg)
         kmalloc_ok = save_kmalloc_ok;
 }
 
-void default_idle(void)
+void arch_cpu_idle(void)
 {
         unsigned long long nsecs;
 
-        while (1) {
-                /* endless idle loop with no priority at all */
-
-                /*
-                 * although we are an idle CPU, we do not want to
-                 * get into the scheduler unnecessarily.
-                 */
-                if (need_resched())
-                        schedule();
-
-                tick_nohz_idle_enter();
-                rcu_idle_enter();
-                nsecs = disable_timer();
-                idle_sleep(nsecs);
-                rcu_idle_exit();
-                tick_nohz_idle_exit();
-        }
-}
-
-void cpu_idle(void)
-{
         cpu_tasks[current_thread_info()->cpu].pid = os_getpid();
-        default_idle();
+        nsecs = disable_timer();
+        idle_sleep(nsecs);
+        local_irq_enable();
 }
 
 int __cant_sleep(void) {
diff --git a/arch/um/kernel/sysrq.c b/arch/um/kernel/sysrq.c
index e562ff80409a..7d101a2a1541 100644
--- a/arch/um/kernel/sysrq.c
+++ b/arch/um/kernel/sysrq.c
@@ -35,18 +35,6 @@ void show_trace(struct task_struct *task, unsigned long * stack)
 }
 #endif
 
-/*
- * stack dumps generator - this is used by arch-independent code.
- * And this is identical to i386 currently.
- */
-void dump_stack(void)
-{
-        unsigned long stack;
-
-        show_trace(current, &stack);
-}
-EXPORT_SYMBOL(dump_stack);
-
 /*Stolen from arch/i386/kernel/traps.c */
 static const int kstack_depth_to_print = 24;
 
diff --git a/arch/um/os-Linux/time.c b/arch/um/os-Linux/time.c
index fac388cb464f..e9824d5dd7d5 100644
--- a/arch/um/os-Linux/time.c
+++ b/arch/um/os-Linux/time.c
@@ -79,7 +79,7 @@ long long os_nsecs(void)
         return timeval_to_ns(&tv);
 }
 
-#ifdef UML_CONFIG_NO_HZ
+#ifdef UML_CONFIG_NO_HZ_COMMON
 static int after_sleep_interval(struct timespec *ts)
 {
         return 0;
diff --git a/arch/um/sys-ppc/sysrq.c b/arch/um/sys-ppc/sysrq.c
index f889449f9285..1ff1ad7f27da 100644
--- a/arch/um/sys-ppc/sysrq.c
+++ b/arch/um/sys-ppc/sysrq.c
@@ -11,6 +11,8 @@
 void show_regs(struct pt_regs_subarch *regs)
 {
         printk("\n");
+        show_regs_print_info(KERN_DEFAULT);
+
         printk("show_regs(): insert regs here.\n");
 #if 0
         printk("\n");
diff --git a/arch/unicore32/kernel/Makefile b/arch/unicore32/kernel/Makefile
index fa497e0efe5a..607a72f2ae35 100644
--- a/arch/unicore32/kernel/Makefile
+++ b/arch/unicore32/kernel/Makefile
@@ -9,7 +9,6 @@ obj-y				+= setup.o signal.o sys.o stacktrace.o traps.o
 obj-$(CONFIG_MODULES)           += ksyms.o module.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
 
-obj-$(CONFIG_CPU_FREQ)          += cpu-ucv2.o
 obj-$(CONFIG_UNICORE_FPU_F64)   += fpu-ucf64.o
 
 # obj-y for architecture PKUnity v3
diff --git a/arch/unicore32/kernel/cpu-ucv2.c b/arch/unicore32/kernel/cpu-ucv2.c
deleted file mode 100644
index 4a99f62584c7..000000000000
--- a/arch/unicore32/kernel/cpu-ucv2.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * linux/arch/unicore32/kernel/cpu-ucv2.c: clock scaling for the UniCore-II
- *
- * Code specific to PKUnity SoC and UniCore ISA
- *
- *      Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn>
- *      Copyright (C) 2001-2010 Guan Xuetao
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/cpufreq.h>
-
-#include <mach/hardware.h>
-
-static struct cpufreq_driver ucv2_driver;
-
-/* make sure that only the "userspace" governor is run
- * -- anything else wouldn't make sense on this platform, anyway.
- */
-int ucv2_verify_speed(struct cpufreq_policy *policy)
-{
-        if (policy->cpu)
-                return -EINVAL;
-
-        cpufreq_verify_within_limits(policy,
-                        policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
-
-        return 0;
-}
-
-static unsigned int ucv2_getspeed(unsigned int cpu)
-{
-        struct clk *mclk = clk_get(NULL, "MAIN_CLK");
-
-        if (cpu)
-                return 0;
-        return clk_get_rate(mclk)/1000;
-}
-
-static int ucv2_target(struct cpufreq_policy *policy,
-                         unsigned int target_freq,
-                         unsigned int relation)
-{
-        unsigned int cur = ucv2_getspeed(0);
-        struct cpufreq_freqs freqs;
-        struct clk *mclk = clk_get(NULL, "MAIN_CLK");
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
-        if (!clk_set_rate(mclk, target_freq * 1000)) {
-                freqs.old = cur;
-                freqs.new = target_freq;
-                freqs.cpu = 0;
-        }
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
-        return 0;
-}
-
-static int __init ucv2_cpu_init(struct cpufreq_policy *policy)
-{
-        if (policy->cpu != 0)
-                return -EINVAL;
-        policy->cur = ucv2_getspeed(0);
-        policy->min = policy->cpuinfo.min_freq = 250000;
-        policy->max = policy->cpuinfo.max_freq = 1000000;
-        policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
-        return 0;
-}
-
-static struct cpufreq_driver ucv2_driver = {
-        .flags          = CPUFREQ_STICKY,
-        .verify         = ucv2_verify_speed,
-        .target         = ucv2_target,
-        .get            = ucv2_getspeed,
-        .init           = ucv2_cpu_init,
-        .name           = "UniCore-II",
-};
-
-static int __init ucv2_cpufreq_init(void)
-{
-        return cpufreq_register_driver(&ucv2_driver);
-}
-
-arch_initcall(ucv2_cpufreq_init);
diff --git a/arch/unicore32/kernel/early_printk.c b/arch/unicore32/kernel/early_printk.c
index 3922255f1fa8..9be0d5d02a9a 100644
--- a/arch/unicore32/kernel/early_printk.c
+++ b/arch/unicore32/kernel/early_printk.c
@@ -33,21 +33,17 @@ static struct console early_ocd_console = {
         .index =        -1,
 };
 
-/* Direct interface for emergencies */
-static struct console *early_console = &early_ocd_console;
-
-static int __initdata keep_early;
-
 static int __init setup_early_printk(char *buf)
 {
-        if (!buf)
+        int keep_early;
+
+        if (!buf || early_console)
                 return 0;
 
         if (strstr(buf, "keep"))
                 keep_early = 1;
 
-        if (!strncmp(buf, "ocd", 3))
-                early_console = &early_ocd_console;
+        early_console = &early_ocd_console;
 
         if (keep_early)
                 early_console->flags &= ~CON_BOOT;
diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c
index 872d7e22d847..c9447691bdac 100644
--- a/arch/unicore32/kernel/process.c
+++ b/arch/unicore32/kernel/process.c
@@ -45,25 +45,10 @@ static const char * const processor_modes[] = {
         "UK18", "UK19", "UK1A", "EXTN", "UK1C", "UK1D", "UK1E", "SUSR"
 };
 
-void cpu_idle(void)
+void arch_cpu_idle(void)
 {
-        /* endless idle loop with no priority at all */
-        while (1) {
-                tick_nohz_idle_enter();
-                rcu_idle_enter();
-                while (!need_resched()) {
-                        local_irq_disable();
-                        stop_critical_timings();
-                        cpu_do_idle();
-                        local_irq_enable();
-                        start_critical_timings();
-                }
-                rcu_idle_exit();
-                tick_nohz_idle_exit();
-                preempt_enable_no_resched();
-                schedule();
-                preempt_disable();
-        }
+        cpu_do_idle();
+        local_irq_enable();
 }
 
 static char reboot_mode = 'h';
@@ -159,11 +144,7 @@ void __show_regs(struct pt_regs *regs)
         unsigned long flags;
         char buf[64];
 
-        printk(KERN_DEFAULT "CPU: %d    %s  (%s %.*s)\n",
-                raw_smp_processor_id(), print_tainted(),
-                init_utsname()->release,
-                (int)strcspn(init_utsname()->version, " "),
-                init_utsname()->version);
+        show_regs_print_info(KERN_DEFAULT);
         print_symbol("PC is at %s\n", instruction_pointer(regs));
         print_symbol("LR is at %s\n", regs->UCreg_lr);
         printk(KERN_DEFAULT "pc : [<%08lx>]    lr : [<%08lx>]    psr: %08lx\n"
diff --git a/arch/unicore32/kernel/traps.c b/arch/unicore32/kernel/traps.c
index 0870b68d2ad9..c54e32410ead 100644
--- a/arch/unicore32/kernel/traps.c
+++ b/arch/unicore32/kernel/traps.c
@@ -170,12 +170,6 @@ static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
                 c_backtrace(fp, mode);
 }
 
-void dump_stack(void)
-{
-        dump_backtrace(NULL, NULL);
-}
-EXPORT_SYMBOL(dump_stack);
-
 void show_stack(struct task_struct *tsk, unsigned long *sp)
 {
         dump_backtrace(NULL, tsk);
diff --git a/arch/unicore32/mm/init.c b/arch/unicore32/mm/init.c
index de186bde8975..63df12d71ce3 100644
--- a/arch/unicore32/mm/init.c
+++ b/arch/unicore32/mm/init.c
@@ -66,6 +66,9 @@ void show_mem(unsigned int filter)
         printk(KERN_DEFAULT "Mem-info:\n");
         show_free_areas(filter);
 
+        if (filter & SHOW_MEM_FILTER_PAGE_COUNT)
+                return;
+
         for_each_bank(i, mi) {
                 struct membank *bank = &mi->bank[i];
                 unsigned int pfn1, pfn2;
@@ -313,24 +316,6 @@ void __init bootmem_init(void)
         max_pfn = max_high - PHYS_PFN_OFFSET;
 }
 
-static inline int free_area(unsigned long pfn, unsigned long end, char *s)
-{
-        unsigned int pages = 0, size = (end - pfn) << (PAGE_SHIFT - 10);
-
-        for (; pfn < end; pfn++) {
-                struct page *page = pfn_to_page(pfn);
-                ClearPageReserved(page);
-                init_page_count(page);
-                __free_page(page);
-                pages++;
-        }
-
-        if (size && s)
-                printk(KERN_INFO "Freeing %s memory: %dK\n", s, size);
-
-        return pages;
-}
-
 static inline void
 free_memmap(unsigned long start_pfn, unsigned long end_pfn)
 {
@@ -404,9 +389,9 @@ void __init mem_init(void)
 
         max_mapnr   = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map;
 
-        /* this will put all unused low memory onto the freelists */
         free_unused_memmap(&meminfo);
 
+        /* this will put all unused low memory onto the freelists */
         totalram_pages += free_all_bootmem();
 
         reserved_pages = free_pages = 0;
@@ -491,9 +476,7 @@ void __init mem_init(void)
 
 void free_initmem(void)
 {
-        totalram_pages += free_area(__phys_to_pfn(__pa(__init_begin)),
-                                    __phys_to_pfn(__pa(__init_end)),
-                                    "init");
+        free_initmem_default(0);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
@@ -503,9 +486,7 @@ static int keep_initrd;
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
         if (!keep_initrd)
-                totalram_pages += free_area(__phys_to_pfn(__pa(start)),
-                                            __phys_to_pfn(__pa(end)),
-                                            "initrd");
+                free_reserved_area(start, end, 0, "initrd");
 }
 
 static int __init keepinitrd_setup(char *__unused)
diff --git a/arch/unicore32/mm/ioremap.c b/arch/unicore32/mm/ioremap.c
index b7a605597b08..13068ee22f33 100644
--- a/arch/unicore32/mm/ioremap.c
+++ b/arch/unicore32/mm/ioremap.c
@@ -235,7 +235,7 @@ EXPORT_SYMBOL(__uc32_ioremap_cached);
 void __uc32_iounmap(volatile void __iomem *io_addr)
 {
         void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr);
-        struct vm_struct **p, *tmp;
+        struct vm_struct *vm;
 
         /*
          * If this is a section based mapping we need to handle it
@@ -244,17 +244,10 @@ void __uc32_iounmap(volatile void __iomem *io_addr)
          * all the mappings before the area can be reclaimed
          * by someone else.
          */
-        write_lock(&vmlist_lock);
-        for (p = &vmlist ; (tmp = *p) ; p = &tmp->next) {
-                if ((tmp->flags & VM_IOREMAP) && (tmp->addr == addr)) {
-                        if (tmp->flags & VM_UNICORE_SECTION_MAPPING) {
-                                unmap_area_sections((unsigned long)tmp->addr,
-                                                    tmp->size);
-                        }
-                        break;
-                }
-        }
-        write_unlock(&vmlist_lock);
+        vm = find_vm_area(addr);
+        if (vm && (vm->flags & VM_IOREMAP) &&
+                (vm->flags & VM_UNICORE_SECTION_MAPPING))
+                unmap_area_sections((unsigned long)vm->addr, vm->size);
 
         vunmap(addr);
 }
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 15b5cef4aa38..5db2117ae288 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -20,6 +20,7 @@ config X86_64
 ### Arch settings
 config X86
         def_bool y
+        select ARCH_HAS_DEBUG_STRICT_USER_COPY_CHECKS
         select HAVE_AOUT if X86_32
         select HAVE_UNSTABLE_SCHED_CLOCK
         select ARCH_SUPPORTS_NUMA_BALANCING
@@ -120,6 +121,7 @@ config X86
         select OLD_SIGSUSPEND3 if X86_32 || IA32_EMULATION
         select OLD_SIGACTION if X86_32
         select COMPAT_OLD_SIGACTION if IA32_EMULATION
+        select RTC_LIB
 
 config INSTRUCTION_DECODER
         def_bool y
@@ -188,9 +190,6 @@ config GENERIC_CALIBRATE_DELAY
 config ARCH_HAS_CPU_RELAX
         def_bool y
 
-config ARCH_HAS_DEFAULT_IDLE
-        def_bool y
-
 config ARCH_HAS_CACHE_LINE_SIZE
         def_bool y
 
@@ -389,7 +388,7 @@ config X86_NUMACHIP
 
 config X86_VSMP
         bool "ScaleMP vSMP"
-        select PARAVIRT_GUEST
+        select HYPERVISOR_GUEST
         select PARAVIRT
         depends on X86_64 && PCI
         depends on X86_EXTENDED_PLATFORM
@@ -596,44 +595,17 @@ config SCHED_OMIT_FRAME_POINTER
 
           If in doubt, say "Y".
 
-menuconfig PARAVIRT_GUEST
-        bool "Paravirtualized guest support"
-        ---help---
-          Say Y here to get to see options related to running Linux under
-          various hypervisors.  This option alone does not add any kernel code.
-
-          If you say N, all options in this submenu will be skipped and disabled.
-
-if PARAVIRT_GUEST
-
-config PARAVIRT_TIME_ACCOUNTING
-        bool "Paravirtual steal time accounting"
-        select PARAVIRT
-        default n
+menuconfig HYPERVISOR_GUEST
+        bool "Linux guest support"
         ---help---
-          Select this option to enable fine granularity task steal time
-          accounting. Time spent executing other tasks in parallel with
-          the current vCPU is discounted from the vCPU power. To account for
-          that, there can be a small performance impact.
-
-          If in doubt, say N here.
-
-source "arch/x86/xen/Kconfig"
+          Say Y here to enable options for running Linux under various hyper-
+          visors. This option enables basic hypervisor detection and platform
+          setup.
 
-config KVM_GUEST
-        bool "KVM Guest support (including kvmclock)"
-        select PARAVIRT
-        select PARAVIRT
-        select PARAVIRT_CLOCK
-        default y if PARAVIRT_GUEST
-        ---help---
-          This option enables various optimizations for running under the KVM
-          hypervisor. It includes a paravirtualized clock, so that instead
-          of relying on a PIT (or probably other) emulation by the
-          underlying device model, the host provides the guest with
-          timing infrastructure such as time of day, and system time
+          If you say N, all options in this submenu will be skipped and
+          disabled, and Linux guest support won't be built in.
 
-source "arch/x86/lguest/Kconfig"
+if HYPERVISOR_GUEST
 
 config PARAVIRT
         bool "Enable paravirtualization code"
@@ -643,6 +615,13 @@ config PARAVIRT
           over full virtualization.  However, when run without a hypervisor
           the kernel is theoretically slower and slightly larger.
 
+config PARAVIRT_DEBUG
+        bool "paravirt-ops debugging"
+        depends on PARAVIRT && DEBUG_KERNEL
+        ---help---
+          Enable to debug paravirt_ops internals.  Specifically, BUG if
+          a paravirt_op is missing when it is called.
+
 config PARAVIRT_SPINLOCKS
         bool "Paravirtualization layer for spinlocks"
         depends on PARAVIRT && SMP
@@ -656,17 +635,38 @@ config PARAVIRT_SPINLOCKS
 
           If you are unsure how to answer this question, answer N.
 
-config PARAVIRT_CLOCK
-        bool
+source "arch/x86/xen/Kconfig"
 
-endif
+config KVM_GUEST
+        bool "KVM Guest support (including kvmclock)"
+        depends on PARAVIRT
+        select PARAVIRT_CLOCK
+        default y
+        ---help---
+          This option enables various optimizations for running under the KVM
+          hypervisor. It includes a paravirtualized clock, so that instead
+          of relying on a PIT (or probably other) emulation by the
+          underlying device model, the host provides the guest with
+          timing infrastructure such as time of day, and system time
 
-config PARAVIRT_DEBUG
-        bool "paravirt-ops debugging"
-        depends on PARAVIRT && DEBUG_KERNEL
+source "arch/x86/lguest/Kconfig"
+
+config PARAVIRT_TIME_ACCOUNTING
+        bool "Paravirtual steal time accounting"
+        depends on PARAVIRT
+        default n
         ---help---
-          Enable to debug paravirt_ops internals.  Specifically, BUG if
-          a paravirt_op is missing when it is called.
+          Select this option to enable fine granularity task steal time
+          accounting. Time spent executing other tasks in parallel with
+          the current vCPU is discounted from the vCPU power. To account for
+          that, there can be a small performance impact.
+
+          If in doubt, say N here.
+
+config PARAVIRT_CLOCK
+        bool
+
+endif #HYPERVISOR_GUEST
 
 config NO_BOOTMEM
         def_bool y
diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug
index b322f124ee3c..c198b7e13e7b 100644
--- a/arch/x86/Kconfig.debug
+++ b/arch/x86/Kconfig.debug
@@ -131,7 +131,7 @@ config DOUBLEFAULT
 
 config DEBUG_TLBFLUSH
         bool "Set upper limit of TLB entries to flush one-by-one"
-        depends on DEBUG_KERNEL && (X86_64 || X86_INVLPG)
+        depends on DEBUG_KERNEL
         ---help---
 
         X86-only for now.
@@ -292,20 +292,6 @@ config OPTIMIZE_INLINING
 
           If unsure, say N.
 
-config DEBUG_STRICT_USER_COPY_CHECKS
-        bool "Strict copy size checks"
-        depends on DEBUG_KERNEL && !TRACE_BRANCH_PROFILING
-        ---help---
-          Enabling this option turns a certain set of sanity checks for user
-          copy operations into compile time failures.
-
-          The copy_from_user() etc checks are there to help test if there
-          are sufficient security checks on the length argument of
-          the copy operation, by having gcc prove that the argument is
-          within bounds.
-
-          If unsure, or if you run an older (pre 4.4) gcc, say N.
-
 config DEBUG_NMI_SELFTEST
         bool "NMI Selftest"
         depends on DEBUG_KERNEL && X86_LOCAL_APIC
diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c
index 8615f7581820..35ee62fccf98 100644
--- a/arch/x86/boot/compressed/eboot.c
+++ b/arch/x86/boot/compressed/eboot.c
@@ -258,7 +258,7 @@ static efi_status_t setup_efi_vars(struct boot_params *params)
         u64 store_size, remaining_size, var_size;
         efi_status_t status;
 
-        if (!sys_table->runtime->query_variable_info)
+        if (sys_table->runtime->hdr.revision < EFI_2_00_SYSTEM_TABLE_REVISION)
                 return EFI_UNSUPPORTED;
 
         data = (struct setup_data *)(unsigned long)params->hdr.setup_data;
@@ -266,7 +266,7 @@ static efi_status_t setup_efi_vars(struct boot_params *params)
         while (data && data->next)
                 data = (struct setup_data *)(unsigned long)data->next;
 
-        status = efi_call_phys4(sys_table->runtime->query_variable_info,
+        status = efi_call_phys4((void *)sys_table->runtime->query_variable_info,
                                 EFI_VARIABLE_NON_VOLATILE |
                                 EFI_VARIABLE_BOOTSERVICE_ACCESS |
                                 EFI_VARIABLE_RUNTIME_ACCESS, &store_size,
diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
index c1d383d1fb7e..16f24e6dad79 100644
--- a/arch/x86/boot/compressed/head_64.S
+++ b/arch/x86/boot/compressed/head_64.S
@@ -52,7 +52,7 @@ ENTRY(startup_32)
         jnz 1f
 
         cli
-        movl    $(__KERNEL_DS), %eax
+        movl    $(__BOOT_DS), %eax
         movl    %eax, %ds
         movl    %eax, %es
         movl    %eax, %ss
diff --git a/arch/x86/crypto/Makefile b/arch/x86/crypto/Makefile
index 63947a8f9f0f..a3a0ed80f17c 100644
--- a/arch/x86/crypto/Makefile
+++ b/arch/x86/crypto/Makefile
@@ -2,6 +2,10 @@
 # Arch-specific CryptoAPI modules.
 #
 
+avx_supported := $(call as-instr,vpxor %xmm0$(comma)%xmm0$(comma)%xmm0,yes,no)
+avx2_supported := $(call as-instr,vpgatherdd %ymm0$(comma)(%eax$(comma)%ymm1\
+                                        $(comma)4)$(comma)%ymm2,yes,no)
+
 obj-$(CONFIG_CRYPTO_ABLK_HELPER_X86) += ablk_helper.o
 obj-$(CONFIG_CRYPTO_GLUE_HELPER_X86) += glue_helper.o
 
@@ -12,22 +16,37 @@ obj-$(CONFIG_CRYPTO_SERPENT_SSE2_586) += serpent-sse2-i586.o
 
 obj-$(CONFIG_CRYPTO_AES_X86_64) += aes-x86_64.o
 obj-$(CONFIG_CRYPTO_CAMELLIA_X86_64) += camellia-x86_64.o
-obj-$(CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64) += camellia-aesni-avx-x86_64.o
-obj-$(CONFIG_CRYPTO_CAST5_AVX_X86_64) += cast5-avx-x86_64.o
-obj-$(CONFIG_CRYPTO_CAST6_AVX_X86_64) += cast6-avx-x86_64.o
 obj-$(CONFIG_CRYPTO_BLOWFISH_X86_64) += blowfish-x86_64.o
 obj-$(CONFIG_CRYPTO_TWOFISH_X86_64) += twofish-x86_64.o
 obj-$(CONFIG_CRYPTO_TWOFISH_X86_64_3WAY) += twofish-x86_64-3way.o
-obj-$(CONFIG_CRYPTO_TWOFISH_AVX_X86_64) += twofish-avx-x86_64.o
 obj-$(CONFIG_CRYPTO_SALSA20_X86_64) += salsa20-x86_64.o
 obj-$(CONFIG_CRYPTO_SERPENT_SSE2_X86_64) += serpent-sse2-x86_64.o
-obj-$(CONFIG_CRYPTO_SERPENT_AVX_X86_64) += serpent-avx-x86_64.o
 obj-$(CONFIG_CRYPTO_AES_NI_INTEL) += aesni-intel.o
 obj-$(CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL) += ghash-clmulni-intel.o
 
 obj-$(CONFIG_CRYPTO_CRC32C_INTEL) += crc32c-intel.o
 obj-$(CONFIG_CRYPTO_SHA1_SSSE3) += sha1-ssse3.o
 obj-$(CONFIG_CRYPTO_CRC32_PCLMUL) += crc32-pclmul.o
+obj-$(CONFIG_CRYPTO_SHA256_SSSE3) += sha256-ssse3.o
+obj-$(CONFIG_CRYPTO_SHA512_SSSE3) += sha512-ssse3.o
+
+# These modules require assembler to support AVX.
+ifeq ($(avx_supported),yes)
+        obj-$(CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64) += \
+                                                camellia-aesni-avx-x86_64.o
+        obj-$(CONFIG_CRYPTO_CAST5_AVX_X86_64) += cast5-avx-x86_64.o
+        obj-$(CONFIG_CRYPTO_CAST6_AVX_X86_64) += cast6-avx-x86_64.o
+        obj-$(CONFIG_CRYPTO_TWOFISH_AVX_X86_64) += twofish-avx-x86_64.o
+        obj-$(CONFIG_CRYPTO_SERPENT_AVX_X86_64) += serpent-avx-x86_64.o
+endif
+
+# These modules require assembler to support AVX2.
+ifeq ($(avx2_supported),yes)
+        obj-$(CONFIG_CRYPTO_BLOWFISH_AVX2_X86_64) += blowfish-avx2.o
+        obj-$(CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64) += camellia-aesni-avx2.o
+        obj-$(CONFIG_CRYPTO_SERPENT_AVX2_X86_64) += serpent-avx2.o
+        obj-$(CONFIG_CRYPTO_TWOFISH_AVX2_X86_64) += twofish-avx2.o
+endif
 
 aes-i586-y := aes-i586-asm_32.o aes_glue.o
 twofish-i586-y := twofish-i586-asm_32.o twofish_glue.o
@@ -36,21 +55,35 @@ serpent-sse2-i586-y := serpent-sse2-i586-asm_32.o serpent_sse2_glue.o
 
 aes-x86_64-y := aes-x86_64-asm_64.o aes_glue.o
 camellia-x86_64-y := camellia-x86_64-asm_64.o camellia_glue.o
-camellia-aesni-avx-x86_64-y := camellia-aesni-avx-asm_64.o \
-                               camellia_aesni_avx_glue.o
-cast5-avx-x86_64-y := cast5-avx-x86_64-asm_64.o cast5_avx_glue.o
-cast6-avx-x86_64-y := cast6-avx-x86_64-asm_64.o cast6_avx_glue.o
 blowfish-x86_64-y := blowfish-x86_64-asm_64.o blowfish_glue.o
 twofish-x86_64-y := twofish-x86_64-asm_64.o twofish_glue.o
 twofish-x86_64-3way-y := twofish-x86_64-asm_64-3way.o twofish_glue_3way.o
-twofish-avx-x86_64-y := twofish-avx-x86_64-asm_64.o twofish_avx_glue.o
 salsa20-x86_64-y := salsa20-x86_64-asm_64.o salsa20_glue.o
 serpent-sse2-x86_64-y := serpent-sse2-x86_64-asm_64.o serpent_sse2_glue.o
-serpent-avx-x86_64-y := serpent-avx-x86_64-asm_64.o serpent_avx_glue.o
+
+ifeq ($(avx_supported),yes)
+        camellia-aesni-avx-x86_64-y := camellia-aesni-avx-asm_64.o \
+                                        camellia_aesni_avx_glue.o
+        cast5-avx-x86_64-y := cast5-avx-x86_64-asm_64.o cast5_avx_glue.o
+        cast6-avx-x86_64-y := cast6-avx-x86_64-asm_64.o cast6_avx_glue.o
+        twofish-avx-x86_64-y := twofish-avx-x86_64-asm_64.o \
+                                twofish_avx_glue.o
+        serpent-avx-x86_64-y := serpent-avx-x86_64-asm_64.o \
+                                serpent_avx_glue.o
+endif
+
+ifeq ($(avx2_supported),yes)
+        blowfish-avx2-y := blowfish-avx2-asm_64.o blowfish_avx2_glue.o
+        camellia-aesni-avx2-y := camellia-aesni-avx2-asm_64.o camellia_aesni_avx2_glue.o
+        serpent-avx2-y := serpent-avx2-asm_64.o serpent_avx2_glue.o
+        twofish-avx2-y := twofish-avx2-asm_64.o twofish_avx2_glue.o
+endif
 
 aesni-intel-y := aesni-intel_asm.o aesni-intel_glue.o fpu.o
 ghash-clmulni-intel-y := ghash-clmulni-intel_asm.o ghash-clmulni-intel_glue.o
 sha1-ssse3-y := sha1_ssse3_asm.o sha1_ssse3_glue.o
 crc32c-intel-y := crc32c-intel_glue.o
-crc32c-intel-$(CONFIG_CRYPTO_CRC32C_X86_64) += crc32c-pcl-intel-asm_64.o
+crc32c-intel-$(CONFIG_64BIT) += crc32c-pcl-intel-asm_64.o
 crc32-pclmul-y := crc32-pclmul_asm.o crc32-pclmul_glue.o
+sha256-ssse3-y := sha256-ssse3-asm.o sha256-avx-asm.o sha256-avx2-asm.o sha256_ssse3_glue.o
+sha512-ssse3-y := sha512-ssse3-asm.o sha512-avx-asm.o sha512-avx2-asm.o sha512_ssse3_glue.o
diff --git a/arch/x86/crypto/aesni-intel_asm.S b/arch/x86/crypto/aesni-intel_asm.S
index 04b797767b9e..62fe22cd4cba 100644
--- a/arch/x86/crypto/aesni-intel_asm.S
+++ b/arch/x86/crypto/aesni-intel_asm.S
@@ -34,6 +34,10 @@
 
 #ifdef __x86_64__
 .data
+.align 16
+.Lgf128mul_x_ble_mask:
+        .octa 0x00000000000000010000000000000087
+
 POLY:   .octa 0xC2000000000000000000000000000001
 TWOONE: .octa 0x00000001000000000000000000000001
 
@@ -105,6 +109,8 @@ enc:        .octa 0x2
 #define CTR     %xmm11
 #define INC     %xmm12
 
+#define GF128MUL_MASK %xmm10
+
 #ifdef __x86_64__
 #define AREG    %rax
 #define KEYP    %rdi
@@ -2636,4 +2642,115 @@ ENTRY(aesni_ctr_enc)
 .Lctr_enc_just_ret:
         ret
 ENDPROC(aesni_ctr_enc)
+
+/*
+ * _aesni_gf128mul_x_ble:               internal ABI
+ *      Multiply in GF(2^128) for XTS IVs
+ * input:
+ *      IV:     current IV
+ *      GF128MUL_MASK == mask with 0x87 and 0x01
+ * output:
+ *      IV:     next IV
+ * changed:
+ *      CTR:    == temporary value
+ */
+#define _aesni_gf128mul_x_ble() \
+        pshufd $0x13, IV, CTR; \
+        paddq IV, IV; \
+        psrad $31, CTR; \
+        pand GF128MUL_MASK, CTR; \
+        pxor CTR, IV;
+
+/*
+ * void aesni_xts_crypt8(struct crypto_aes_ctx *ctx, const u8 *dst, u8 *src,
+ *                       bool enc, u8 *iv)
+ */
+ENTRY(aesni_xts_crypt8)
+        cmpb $0, %cl
+        movl $0, %ecx
+        movl $240, %r10d
+        leaq _aesni_enc4, %r11
+        leaq _aesni_dec4, %rax
+        cmovel %r10d, %ecx
+        cmoveq %rax, %r11
+
+        movdqa .Lgf128mul_x_ble_mask, GF128MUL_MASK
+        movups (IVP), IV
+
+        mov 480(KEYP), KLEN
+        addq %rcx, KEYP
+
+        movdqa IV, STATE1
+        pxor 0x00(INP), STATE1
+        movdqu IV, 0x00(OUTP)
+
+        _aesni_gf128mul_x_ble()
+        movdqa IV, STATE2
+        pxor 0x10(INP), STATE2
+        movdqu IV, 0x10(OUTP)
+
+        _aesni_gf128mul_x_ble()
+        movdqa IV, STATE3
+        pxor 0x20(INP), STATE3
+        movdqu IV, 0x20(OUTP)
+
+        _aesni_gf128mul_x_ble()
+        movdqa IV, STATE4
+        pxor 0x30(INP), STATE4
+        movdqu IV, 0x30(OUTP)
+
+        call *%r11
+
+        pxor 0x00(OUTP), STATE1
+        movdqu STATE1, 0x00(OUTP)
+
+        _aesni_gf128mul_x_ble()
+        movdqa IV, STATE1
+        pxor 0x40(INP), STATE1
+        movdqu IV, 0x40(OUTP)
+
+        pxor 0x10(OUTP), STATE2
+        movdqu STATE2, 0x10(OUTP)
+
+        _aesni_gf128mul_x_ble()
+        movdqa IV, STATE2
+        pxor 0x50(INP), STATE2
+        movdqu IV, 0x50(OUTP)
+
+        pxor 0x20(OUTP), STATE3
+        movdqu STATE3, 0x20(OUTP)
+
+        _aesni_gf128mul_x_ble()
+        movdqa IV, STATE3
+        pxor 0x60(INP), STATE3
+        movdqu IV, 0x60(OUTP)
+
+        pxor 0x30(OUTP), STATE4
+        movdqu STATE4, 0x30(OUTP)
+
+        _aesni_gf128mul_x_ble()
+        movdqa IV, STATE4
+        pxor 0x70(INP), STATE4
+        movdqu IV, 0x70(OUTP)
+
+        _aesni_gf128mul_x_ble()
+        movups IV, (IVP)
+
+        call *%r11
+
+        pxor 0x40(OUTP), STATE1
+        movdqu STATE1, 0x40(OUTP)
+
+        pxor 0x50(OUTP), STATE2
+        movdqu STATE2, 0x50(OUTP)
+
+        pxor 0x60(OUTP), STATE3
+        movdqu STATE3, 0x60(OUTP)
+
+        pxor 0x70(OUTP), STATE4
+        movdqu STATE4, 0x70(OUTP)
+
+        ret
+ENDPROC(aesni_xts_crypt8)
+
 #endif
diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c
index a0795da22c02..f80e668785c0 100644
--- a/arch/x86/crypto/aesni-intel_glue.c
+++ b/arch/x86/crypto/aesni-intel_glue.c
@@ -39,6 +39,9 @@
 #include <crypto/internal/aead.h>
 #include <linux/workqueue.h>
 #include <linux/spinlock.h>
+#ifdef CONFIG_X86_64
+#include <asm/crypto/glue_helper.h>
+#endif
 
 #if defined(CONFIG_CRYPTO_PCBC) || defined(CONFIG_CRYPTO_PCBC_MODULE)
 #define HAS_PCBC
@@ -102,6 +105,9 @@ void crypto_fpu_exit(void);
 asmlinkage void aesni_ctr_enc(struct crypto_aes_ctx *ctx, u8 *out,
                               const u8 *in, unsigned int len, u8 *iv);
 
+asmlinkage void aesni_xts_crypt8(struct crypto_aes_ctx *ctx, u8 *out,
+                                 const u8 *in, bool enc, u8 *iv);
+
 /* asmlinkage void aesni_gcm_enc()
  * void *ctx,  AES Key schedule. Starts on a 16 byte boundary.
  * u8 *out, Ciphertext output. Encrypt in-place is allowed.
@@ -510,6 +516,78 @@ static void aesni_xts_tweak(void *ctx, u8 *out, const u8 *in)
         aesni_enc(ctx, out, in);
 }
 
+#ifdef CONFIG_X86_64
+
+static void aesni_xts_enc(void *ctx, u128 *dst, const u128 *src, le128 *iv)
+{
+        glue_xts_crypt_128bit_one(ctx, dst, src, iv, GLUE_FUNC_CAST(aesni_enc));
+}
+
+static void aesni_xts_dec(void *ctx, u128 *dst, const u128 *src, le128 *iv)
+{
+        glue_xts_crypt_128bit_one(ctx, dst, src, iv, GLUE_FUNC_CAST(aesni_dec));
+}
+
+static void aesni_xts_enc8(void *ctx, u128 *dst, const u128 *src, le128 *iv)
+{
+        aesni_xts_crypt8(ctx, (u8 *)dst, (const u8 *)src, true, (u8 *)iv);
+}
+
+static void aesni_xts_dec8(void *ctx, u128 *dst, const u128 *src, le128 *iv)
+{
+        aesni_xts_crypt8(ctx, (u8 *)dst, (const u8 *)src, false, (u8 *)iv);
+}
+
+static const struct common_glue_ctx aesni_enc_xts = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = 1,
+
+        .funcs = { {
+                .num_blocks = 8,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(aesni_xts_enc8) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(aesni_xts_enc) }
+        } }
+};
+
+static const struct common_glue_ctx aesni_dec_xts = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = 1,
+
+        .funcs = { {
+                .num_blocks = 8,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(aesni_xts_dec8) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(aesni_xts_dec) }
+        } }
+};
+
+static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct aesni_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+
+        return glue_xts_crypt_128bit(&aesni_enc_xts, desc, dst, src, nbytes,
+                                     XTS_TWEAK_CAST(aesni_xts_tweak),
+                                     aes_ctx(ctx->raw_tweak_ctx),
+                                     aes_ctx(ctx->raw_crypt_ctx));
+}
+
+static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct aesni_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+
+        return glue_xts_crypt_128bit(&aesni_dec_xts, desc, dst, src, nbytes,
+                                     XTS_TWEAK_CAST(aesni_xts_tweak),
+                                     aes_ctx(ctx->raw_tweak_ctx),
+                                     aes_ctx(ctx->raw_crypt_ctx));
+}
+
+#else
+
 static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
                        struct scatterlist *src, unsigned int nbytes)
 {
@@ -560,6 +638,8 @@ static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
         return ret;
 }
 
+#endif
+
 #ifdef CONFIG_X86_64
 static int rfc4106_init(struct crypto_tfm *tfm)
 {
diff --git a/arch/x86/crypto/blowfish-avx2-asm_64.S b/arch/x86/crypto/blowfish-avx2-asm_64.S
new file mode 100644
index 000000000000..784452e0d05d
--- /dev/null
+++ b/arch/x86/crypto/blowfish-avx2-asm_64.S
@@ -0,0 +1,449 @@
+/*
+ * x86_64/AVX2 assembler optimized version of Blowfish
+ *
+ * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/linkage.h>
+
+.file "blowfish-avx2-asm_64.S"
+
+.data
+.align 32
+
+.Lprefetch_mask:
+.long 0*64
+.long 1*64
+.long 2*64
+.long 3*64
+.long 4*64
+.long 5*64
+.long 6*64
+.long 7*64
+
+.Lbswap32_mask:
+.long 0x00010203
+.long 0x04050607
+.long 0x08090a0b
+.long 0x0c0d0e0f
+
+.Lbswap128_mask:
+        .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
+.Lbswap_iv_mask:
+        .byte 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0
+
+.text
+/* structure of crypto context */
+#define p       0
+#define s0      ((16 + 2) * 4)
+#define s1      ((16 + 2 + (1 * 256)) * 4)
+#define s2      ((16 + 2 + (2 * 256)) * 4)
+#define s3      ((16 + 2 + (3 * 256)) * 4)
+
+/* register macros */
+#define CTX     %rdi
+#define RIO      %rdx
+
+#define RS0     %rax
+#define RS1     %r8
+#define RS2     %r9
+#define RS3     %r10
+
+#define RLOOP   %r11
+#define RLOOPd  %r11d
+
+#define RXr0    %ymm8
+#define RXr1    %ymm9
+#define RXr2    %ymm10
+#define RXr3    %ymm11
+#define RXl0    %ymm12
+#define RXl1    %ymm13
+#define RXl2    %ymm14
+#define RXl3    %ymm15
+
+/* temp regs */
+#define RT0     %ymm0
+#define RT0x    %xmm0
+#define RT1     %ymm1
+#define RT1x    %xmm1
+#define RIDX0   %ymm2
+#define RIDX1   %ymm3
+#define RIDX1x  %xmm3
+#define RIDX2   %ymm4
+#define RIDX3   %ymm5
+
+/* vpgatherdd mask and '-1' */
+#define RNOT    %ymm6
+
+/* byte mask, (-1 >> 24) */
+#define RBYTE   %ymm7
+
+/***********************************************************************
+ * 32-way AVX2 blowfish
+ ***********************************************************************/
+#define F(xl, xr) \
+        vpsrld $24, xl, RIDX0; \
+        vpsrld $16, xl, RIDX1; \
+        vpsrld $8, xl, RIDX2; \
+        vpand RBYTE, RIDX1, RIDX1; \
+        vpand RBYTE, RIDX2, RIDX2; \
+        vpand RBYTE, xl, RIDX3; \
+        \
+        vpgatherdd RNOT, (RS0, RIDX0, 4), RT0; \
+        vpcmpeqd RNOT, RNOT, RNOT; \
+        vpcmpeqd RIDX0, RIDX0, RIDX0; \
+        \
+        vpgatherdd RNOT, (RS1, RIDX1, 4), RT1; \
+        vpcmpeqd RIDX1, RIDX1, RIDX1; \
+        vpaddd RT0, RT1, RT0; \
+        \
+        vpgatherdd RIDX0, (RS2, RIDX2, 4), RT1; \
+        vpxor RT0, RT1, RT0; \
+        \
+        vpgatherdd RIDX1, (RS3, RIDX3, 4), RT1; \
+        vpcmpeqd RNOT, RNOT, RNOT; \
+        vpaddd RT0, RT1, RT0; \
+        \
+        vpxor RT0, xr, xr;
+
+#define add_roundkey(xl, nmem) \
+        vpbroadcastd nmem, RT0; \
+        vpxor RT0, xl ## 0, xl ## 0; \
+        vpxor RT0, xl ## 1, xl ## 1; \
+        vpxor RT0, xl ## 2, xl ## 2; \
+        vpxor RT0, xl ## 3, xl ## 3;
+
+#define round_enc() \
+        add_roundkey(RXr, p(CTX,RLOOP,4)); \
+        F(RXl0, RXr0); \
+        F(RXl1, RXr1); \
+        F(RXl2, RXr2); \
+        F(RXl3, RXr3); \
+        \
+        add_roundkey(RXl, p+4(CTX,RLOOP,4)); \
+        F(RXr0, RXl0); \
+        F(RXr1, RXl1); \
+        F(RXr2, RXl2); \
+        F(RXr3, RXl3);
+
+#define round_dec() \
+        add_roundkey(RXr, p+4*2(CTX,RLOOP,4)); \
+        F(RXl0, RXr0); \
+        F(RXl1, RXr1); \
+        F(RXl2, RXr2); \
+        F(RXl3, RXr3); \
+        \
+        add_roundkey(RXl, p+4(CTX,RLOOP,4)); \
+        F(RXr0, RXl0); \
+        F(RXr1, RXl1); \
+        F(RXr2, RXl2); \
+        F(RXr3, RXl3);
+
+#define init_round_constants() \
+        vpcmpeqd RNOT, RNOT, RNOT; \
+        leaq s0(CTX), RS0; \
+        leaq s1(CTX), RS1; \
+        leaq s2(CTX), RS2; \
+        leaq s3(CTX), RS3; \
+        vpsrld $24, RNOT, RBYTE;
+
+#define transpose_2x2(x0, x1, t0) \
+        vpunpckldq x0, x1, t0; \
+        vpunpckhdq x0, x1, x1; \
+        \
+        vpunpcklqdq t0, x1, x0; \
+        vpunpckhqdq t0, x1, x1;
+
+#define read_block(xl, xr) \
+        vbroadcasti128 .Lbswap32_mask, RT1; \
+        \
+        vpshufb RT1, xl ## 0, xl ## 0; \
+        vpshufb RT1, xr ## 0, xr ## 0; \
+        vpshufb RT1, xl ## 1, xl ## 1; \
+        vpshufb RT1, xr ## 1, xr ## 1; \
+        vpshufb RT1, xl ## 2, xl ## 2; \
+        vpshufb RT1, xr ## 2, xr ## 2; \
+        vpshufb RT1, xl ## 3, xl ## 3; \
+        vpshufb RT1, xr ## 3, xr ## 3; \
+        \
+        transpose_2x2(xl ## 0, xr ## 0, RT0); \
+        transpose_2x2(xl ## 1, xr ## 1, RT0); \
+        transpose_2x2(xl ## 2, xr ## 2, RT0); \
+        transpose_2x2(xl ## 3, xr ## 3, RT0);
+
+#define write_block(xl, xr) \
+        vbroadcasti128 .Lbswap32_mask, RT1; \
+        \
+        transpose_2x2(xl ## 0, xr ## 0, RT0); \
+        transpose_2x2(xl ## 1, xr ## 1, RT0); \
+        transpose_2x2(xl ## 2, xr ## 2, RT0); \
+        transpose_2x2(xl ## 3, xr ## 3, RT0); \
+        \
+        vpshufb RT1, xl ## 0, xl ## 0; \
+        vpshufb RT1, xr ## 0, xr ## 0; \
+        vpshufb RT1, xl ## 1, xl ## 1; \
+        vpshufb RT1, xr ## 1, xr ## 1; \
+        vpshufb RT1, xl ## 2, xl ## 2; \
+        vpshufb RT1, xr ## 2, xr ## 2; \
+        vpshufb RT1, xl ## 3, xl ## 3; \
+        vpshufb RT1, xr ## 3, xr ## 3;
+
+.align 8
+__blowfish_enc_blk32:
+        /* input:
+         *      %rdi: ctx, CTX
+         *      RXl0..4, RXr0..4: plaintext
+         * output:
+         *      RXl0..4, RXr0..4: ciphertext (RXl <=> RXr swapped)
+         */
+        init_round_constants();
+
+        read_block(RXl, RXr);
+
+        movl $1, RLOOPd;
+        add_roundkey(RXl, p+4*(0)(CTX));
+
+.align 4
+.L__enc_loop:
+        round_enc();
+
+        leal 2(RLOOPd), RLOOPd;
+        cmpl $17, RLOOPd;
+        jne .L__enc_loop;
+
+        add_roundkey(RXr, p+4*(17)(CTX));
+
+        write_block(RXl, RXr);
+
+        ret;
+ENDPROC(__blowfish_enc_blk32)
+
+.align 8
+__blowfish_dec_blk32:
+        /* input:
+         *      %rdi: ctx, CTX
+         *      RXl0..4, RXr0..4: ciphertext
+         * output:
+         *      RXl0..4, RXr0..4: plaintext (RXl <=> RXr swapped)
+         */
+        init_round_constants();
+
+        read_block(RXl, RXr);
+
+        movl $14, RLOOPd;
+        add_roundkey(RXl, p+4*(17)(CTX));
+
+.align 4
+.L__dec_loop:
+        round_dec();
+
+        addl $-2, RLOOPd;
+        jns .L__dec_loop;
+
+        add_roundkey(RXr, p+4*(0)(CTX));
+
+        write_block(RXl, RXr);
+
+        ret;
+ENDPROC(__blowfish_dec_blk32)
+
+ENTRY(blowfish_ecb_enc_32way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         */
+
+        vzeroupper;
+
+        vmovdqu 0*32(%rdx), RXl0;
+        vmovdqu 1*32(%rdx), RXr0;
+        vmovdqu 2*32(%rdx), RXl1;
+        vmovdqu 3*32(%rdx), RXr1;
+        vmovdqu 4*32(%rdx), RXl2;
+        vmovdqu 5*32(%rdx), RXr2;
+        vmovdqu 6*32(%rdx), RXl3;
+        vmovdqu 7*32(%rdx), RXr3;
+
+        call __blowfish_enc_blk32;
+
+        vmovdqu RXr0, 0*32(%rsi);
+        vmovdqu RXl0, 1*32(%rsi);
+        vmovdqu RXr1, 2*32(%rsi);
+        vmovdqu RXl1, 3*32(%rsi);
+        vmovdqu RXr2, 4*32(%rsi);
+        vmovdqu RXl2, 5*32(%rsi);
+        vmovdqu RXr3, 6*32(%rsi);
+        vmovdqu RXl3, 7*32(%rsi);
+
+        vzeroupper;
+
+        ret;
+ENDPROC(blowfish_ecb_enc_32way)
+
+ENTRY(blowfish_ecb_dec_32way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         */
+
+        vzeroupper;
+
+        vmovdqu 0*32(%rdx), RXl0;
+        vmovdqu 1*32(%rdx), RXr0;
+        vmovdqu 2*32(%rdx), RXl1;
+        vmovdqu 3*32(%rdx), RXr1;
+        vmovdqu 4*32(%rdx), RXl2;
+        vmovdqu 5*32(%rdx), RXr2;
+        vmovdqu 6*32(%rdx), RXl3;
+        vmovdqu 7*32(%rdx), RXr3;
+
+        call __blowfish_dec_blk32;
+
+        vmovdqu RXr0, 0*32(%rsi);
+        vmovdqu RXl0, 1*32(%rsi);
+        vmovdqu RXr1, 2*32(%rsi);
+        vmovdqu RXl1, 3*32(%rsi);
+        vmovdqu RXr2, 4*32(%rsi);
+        vmovdqu RXl2, 5*32(%rsi);
+        vmovdqu RXr3, 6*32(%rsi);
+        vmovdqu RXl3, 7*32(%rsi);
+
+        vzeroupper;
+
+        ret;
+ENDPROC(blowfish_ecb_dec_32way)
+
+ENTRY(blowfish_cbc_dec_32way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         */
+
+        vzeroupper;
+
+        vmovdqu 0*32(%rdx), RXl0;
+        vmovdqu 1*32(%rdx), RXr0;
+        vmovdqu 2*32(%rdx), RXl1;
+        vmovdqu 3*32(%rdx), RXr1;
+        vmovdqu 4*32(%rdx), RXl2;
+        vmovdqu 5*32(%rdx), RXr2;
+        vmovdqu 6*32(%rdx), RXl3;
+        vmovdqu 7*32(%rdx), RXr3;
+
+        call __blowfish_dec_blk32;
+
+        /* xor with src */
+        vmovq (%rdx), RT0x;
+        vpshufd $0x4f, RT0x, RT0x;
+        vinserti128 $1, 8(%rdx), RT0, RT0;
+        vpxor RT0, RXr0, RXr0;
+        vpxor 0*32+24(%rdx), RXl0, RXl0;
+        vpxor 1*32+24(%rdx), RXr1, RXr1;
+        vpxor 2*32+24(%rdx), RXl1, RXl1;
+        vpxor 3*32+24(%rdx), RXr2, RXr2;
+        vpxor 4*32+24(%rdx), RXl2, RXl2;
+        vpxor 5*32+24(%rdx), RXr3, RXr3;
+        vpxor 6*32+24(%rdx), RXl3, RXl3;
+
+        vmovdqu RXr0, (0*32)(%rsi);
+        vmovdqu RXl0, (1*32)(%rsi);
+        vmovdqu RXr1, (2*32)(%rsi);
+        vmovdqu RXl1, (3*32)(%rsi);
+        vmovdqu RXr2, (4*32)(%rsi);
+        vmovdqu RXl2, (5*32)(%rsi);
+        vmovdqu RXr3, (6*32)(%rsi);
+        vmovdqu RXl3, (7*32)(%rsi);
+
+        vzeroupper;
+
+        ret;
+ENDPROC(blowfish_cbc_dec_32way)
+
+ENTRY(blowfish_ctr_32way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         *      %rcx: iv (big endian, 64bit)
+         */
+
+        vzeroupper;
+
+        vpcmpeqd RT0, RT0, RT0;
+        vpsrldq $8, RT0, RT0; /* a: -1, b: 0, c: -1, d: 0 */
+
+        vpcmpeqd RT1x, RT1x, RT1x;
+        vpaddq RT1x, RT1x, RT1x; /* a: -2, b: -2 */
+        vpxor RIDX0, RIDX0, RIDX0;
+        vinserti128 $1, RT1x, RIDX0, RIDX0; /* a: 0, b: 0, c: -2, d: -2 */
+
+        vpaddq RIDX0, RT0, RT0; /* a: -1, b: 0, c: -3, d: -2 */
+
+        vpcmpeqd RT1, RT1, RT1;
+        vpaddq RT1, RT1, RT1; /* a: -2, b: -2, c: -2, d: -2 */
+        vpaddq RT1, RT1, RIDX2; /* a: -4, b: -4, c: -4, d: -4 */
+
+        vbroadcasti128 .Lbswap_iv_mask, RIDX0;
+        vbroadcasti128 .Lbswap128_mask, RIDX1;
+
+        /* load IV and byteswap */
+        vmovq (%rcx), RT1x;
+        vinserti128 $1, RT1x, RT1, RT1; /* a: BE, b: 0, c: BE, d: 0 */
+        vpshufb RIDX0, RT1, RT1; /* a: LE, b: LE, c: LE, d: LE */
+
+        /* construct IVs */
+        vpsubq RT0, RT1, RT1;           /* a: le1, b: le0, c: le3, d: le2 */
+        vpshufb RIDX1, RT1, RXl0;       /* a: be0, b: be1, c: be2, d: be3 */
+        vpsubq RIDX2, RT1, RT1;         /* le5, le4, le7, le6 */
+        vpshufb RIDX1, RT1, RXr0;       /* be4, be5, be6, be7 */
+        vpsubq RIDX2, RT1, RT1;
+        vpshufb RIDX1, RT1, RXl1;
+        vpsubq RIDX2, RT1, RT1;
+        vpshufb RIDX1, RT1, RXr1;
+        vpsubq RIDX2, RT1, RT1;
+        vpshufb RIDX1, RT1, RXl2;
+        vpsubq RIDX2, RT1, RT1;
+        vpshufb RIDX1, RT1, RXr2;
+        vpsubq RIDX2, RT1, RT1;
+        vpshufb RIDX1, RT1, RXl3;
+        vpsubq RIDX2, RT1, RT1;
+        vpshufb RIDX1, RT1, RXr3;
+
+        /* store last IV */
+        vpsubq RIDX2, RT1, RT1; /* a: le33, b: le32, ... */
+        vpshufb RIDX1x, RT1x, RT1x; /* a: be32, ... */
+        vmovq RT1x, (%rcx);
+
+        call __blowfish_enc_blk32;
+
+        /* dst = src ^ iv */
+        vpxor 0*32(%rdx), RXr0, RXr0;
+        vpxor 1*32(%rdx), RXl0, RXl0;
+        vpxor 2*32(%rdx), RXr1, RXr1;
+        vpxor 3*32(%rdx), RXl1, RXl1;
+        vpxor 4*32(%rdx), RXr2, RXr2;
+        vpxor 5*32(%rdx), RXl2, RXl2;
+        vpxor 6*32(%rdx), RXr3, RXr3;
+        vpxor 7*32(%rdx), RXl3, RXl3;
+        vmovdqu RXr0, (0*32)(%rsi);
+        vmovdqu RXl0, (1*32)(%rsi);
+        vmovdqu RXr1, (2*32)(%rsi);
+        vmovdqu RXl1, (3*32)(%rsi);
+        vmovdqu RXr2, (4*32)(%rsi);
+        vmovdqu RXl2, (5*32)(%rsi);
+        vmovdqu RXr3, (6*32)(%rsi);
+        vmovdqu RXl3, (7*32)(%rsi);
+
+        vzeroupper;
+
+        ret;
+ENDPROC(blowfish_ctr_32way)
diff --git a/arch/x86/crypto/blowfish_avx2_glue.c b/arch/x86/crypto/blowfish_avx2_glue.c
new file mode 100644
index 000000000000..4417e9aea78d
--- /dev/null
+++ b/arch/x86/crypto/blowfish_avx2_glue.c
@@ -0,0 +1,585 @@
+/*
+ * Glue Code for x86_64/AVX2 assembler optimized version of Blowfish
+ *
+ * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
+ *
+ * CBC & ECB parts based on code (crypto/cbc.c,ecb.c) by:
+ *   Copyright (c) 2006 Herbert Xu <herbert@gondor.apana.org.au>
+ * CTR part based on code (crypto/ctr.c) by:
+ *   (C) Copyright IBM Corp. 2007 - Joy Latten <latten@us.ibm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/crypto.h>
+#include <linux/err.h>
+#include <crypto/algapi.h>
+#include <crypto/blowfish.h>
+#include <crypto/cryptd.h>
+#include <crypto/ctr.h>
+#include <asm/i387.h>
+#include <asm/xcr.h>
+#include <asm/xsave.h>
+#include <asm/crypto/blowfish.h>
+#include <asm/crypto/ablk_helper.h>
+#include <crypto/scatterwalk.h>
+
+#define BF_AVX2_PARALLEL_BLOCKS 32
+
+/* 32-way AVX2 parallel cipher functions */
+asmlinkage void blowfish_ecb_enc_32way(struct bf_ctx *ctx, u8 *dst,
+                                       const u8 *src);
+asmlinkage void blowfish_ecb_dec_32way(struct bf_ctx *ctx, u8 *dst,
+                                       const u8 *src);
+asmlinkage void blowfish_cbc_dec_32way(struct bf_ctx *ctx, u8 *dst,
+                                       const u8 *src);
+asmlinkage void blowfish_ctr_32way(struct bf_ctx *ctx, u8 *dst, const u8 *src,
+                                   __be64 *iv);
+
+static inline bool bf_fpu_begin(bool fpu_enabled, unsigned int nbytes)
+{
+        if (fpu_enabled)
+                return true;
+
+        /* FPU is only used when chunk to be processed is large enough, so
+         * do not enable FPU until it is necessary.
+         */
+        if (nbytes < BF_BLOCK_SIZE * BF_AVX2_PARALLEL_BLOCKS)
+                return false;
+
+        kernel_fpu_begin();
+        return true;
+}
+
+static inline void bf_fpu_end(bool fpu_enabled)
+{
+        if (fpu_enabled)
+                kernel_fpu_end();
+}
+
+static int ecb_crypt(struct blkcipher_desc *desc, struct blkcipher_walk *walk,
+                     bool enc)
+{
+        bool fpu_enabled = false;
+        struct bf_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+        const unsigned int bsize = BF_BLOCK_SIZE;
+        unsigned int nbytes;
+        int err;
+
+        err = blkcipher_walk_virt(desc, walk);
+        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
+
+        while ((nbytes = walk->nbytes)) {
+                u8 *wsrc = walk->src.virt.addr;
+                u8 *wdst = walk->dst.virt.addr;
+
+                fpu_enabled = bf_fpu_begin(fpu_enabled, nbytes);
+
+                /* Process multi-block AVX2 batch */
+                if (nbytes >= bsize * BF_AVX2_PARALLEL_BLOCKS) {
+                        do {
+                                if (enc)
+                                        blowfish_ecb_enc_32way(ctx, wdst, wsrc);
+                                else
+                                        blowfish_ecb_dec_32way(ctx, wdst, wsrc);
+
+                                wsrc += bsize * BF_AVX2_PARALLEL_BLOCKS;
+                                wdst += bsize * BF_AVX2_PARALLEL_BLOCKS;
+                                nbytes -= bsize * BF_AVX2_PARALLEL_BLOCKS;
+                        } while (nbytes >= bsize * BF_AVX2_PARALLEL_BLOCKS);
+
+                        if (nbytes < bsize)
+                                goto done;
+                }
+
+                /* Process multi-block batch */
+                if (nbytes >= bsize * BF_PARALLEL_BLOCKS) {
+                        do {
+                                if (enc)
+                                        blowfish_enc_blk_4way(ctx, wdst, wsrc);
+                                else
+                                        blowfish_dec_blk_4way(ctx, wdst, wsrc);
+
+                                wsrc += bsize * BF_PARALLEL_BLOCKS;
+                                wdst += bsize * BF_PARALLEL_BLOCKS;
+                                nbytes -= bsize * BF_PARALLEL_BLOCKS;
+                        } while (nbytes >= bsize * BF_PARALLEL_BLOCKS);
+
+                        if (nbytes < bsize)
+                                goto done;
+                }
+
+                /* Handle leftovers */
+                do {
+                        if (enc)
+                                blowfish_enc_blk(ctx, wdst, wsrc);
+                        else
+                                blowfish_dec_blk(ctx, wdst, wsrc);
+
+                        wsrc += bsize;
+                        wdst += bsize;
+                        nbytes -= bsize;
+                } while (nbytes >= bsize);
+
+done:
+                err = blkcipher_walk_done(desc, walk, nbytes);
+        }
+
+        bf_fpu_end(fpu_enabled);
+        return err;
+}
+
+static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct blkcipher_walk walk;
+
+        blkcipher_walk_init(&walk, dst, src, nbytes);
+        return ecb_crypt(desc, &walk, true);
+}
+
+static int ecb_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct blkcipher_walk walk;
+
+        blkcipher_walk_init(&walk, dst, src, nbytes);
+        return ecb_crypt(desc, &walk, false);
+}
+
+static unsigned int __cbc_encrypt(struct blkcipher_desc *desc,
+                                  struct blkcipher_walk *walk)
+{
+        struct bf_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+        unsigned int bsize = BF_BLOCK_SIZE;
+        unsigned int nbytes = walk->nbytes;
+        u64 *src = (u64 *)walk->src.virt.addr;
+        u64 *dst = (u64 *)walk->dst.virt.addr;
+        u64 *iv = (u64 *)walk->iv;
+
+        do {
+                *dst = *src ^ *iv;
+                blowfish_enc_blk(ctx, (u8 *)dst, (u8 *)dst);
+                iv = dst;
+
+                src += 1;
+                dst += 1;
+                nbytes -= bsize;
+        } while (nbytes >= bsize);
+
+        *(u64 *)walk->iv = *iv;
+        return nbytes;
+}
+
+static int cbc_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct blkcipher_walk walk;
+        int err;
+
+        blkcipher_walk_init(&walk, dst, src, nbytes);
+        err = blkcipher_walk_virt(desc, &walk);
+
+        while ((nbytes = walk.nbytes)) {
+                nbytes = __cbc_encrypt(desc, &walk);
+                err = blkcipher_walk_done(desc, &walk, nbytes);
+        }
+
+        return err;
+}
+
+static unsigned int __cbc_decrypt(struct blkcipher_desc *desc,
+                                  struct blkcipher_walk *walk)
+{
+        struct bf_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+        const unsigned int bsize = BF_BLOCK_SIZE;
+        unsigned int nbytes = walk->nbytes;
+        u64 *src = (u64 *)walk->src.virt.addr;
+        u64 *dst = (u64 *)walk->dst.virt.addr;
+        u64 last_iv;
+        int i;
+
+        /* Start of the last block. */
+        src += nbytes / bsize - 1;
+        dst += nbytes / bsize - 1;
+
+        last_iv = *src;
+
+        /* Process multi-block AVX2 batch */
+        if (nbytes >= bsize * BF_AVX2_PARALLEL_BLOCKS) {
+                do {
+                        nbytes -= bsize * (BF_AVX2_PARALLEL_BLOCKS - 1);
+                        src -= BF_AVX2_PARALLEL_BLOCKS - 1;
+                        dst -= BF_AVX2_PARALLEL_BLOCKS - 1;
+
+                        blowfish_cbc_dec_32way(ctx, (u8 *)dst, (u8 *)src);
+
+                        nbytes -= bsize;
+                        if (nbytes < bsize)
+                                goto done;
+
+                        *dst ^= *(src - 1);
+                        src -= 1;
+                        dst -= 1;
+                } while (nbytes >= bsize * BF_AVX2_PARALLEL_BLOCKS);
+
+                if (nbytes < bsize)
+                        goto done;
+        }
+
+        /* Process multi-block batch */
+        if (nbytes >= bsize * BF_PARALLEL_BLOCKS) {
+                u64 ivs[BF_PARALLEL_BLOCKS - 1];
+
+                do {
+                        nbytes -= bsize * (BF_PARALLEL_BLOCKS - 1);
+                        src -= BF_PARALLEL_BLOCKS - 1;
+                        dst -= BF_PARALLEL_BLOCKS - 1;
+
+                        for (i = 0; i < BF_PARALLEL_BLOCKS - 1; i++)
+                                ivs[i] = src[i];
+
+                        blowfish_dec_blk_4way(ctx, (u8 *)dst, (u8 *)src);
+
+                        for (i = 0; i < BF_PARALLEL_BLOCKS - 1; i++)
+                                dst[i + 1] ^= ivs[i];
+
+                        nbytes -= bsize;
+                        if (nbytes < bsize)
+                                goto done;
+
+                        *dst ^= *(src - 1);
+                        src -= 1;
+                        dst -= 1;
+                } while (nbytes >= bsize * BF_PARALLEL_BLOCKS);
+
+                if (nbytes < bsize)
+                        goto done;
+        }
+
+        /* Handle leftovers */
+        for (;;) {
+                blowfish_dec_blk(ctx, (u8 *)dst, (u8 *)src);
+
+                nbytes -= bsize;
+                if (nbytes < bsize)
+                        break;
+
+                *dst ^= *(src - 1);
+                src -= 1;
+                dst -= 1;
+        }
+
+done:
+        *dst ^= *(u64 *)walk->iv;
+        *(u64 *)walk->iv = last_iv;
+
+        return nbytes;
+}
+
+static int cbc_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        bool fpu_enabled = false;
+        struct blkcipher_walk walk;
+        int err;
+
+        blkcipher_walk_init(&walk, dst, src, nbytes);
+        err = blkcipher_walk_virt(desc, &walk);
+        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
+
+        while ((nbytes = walk.nbytes)) {
+                fpu_enabled = bf_fpu_begin(fpu_enabled, nbytes);
+                nbytes = __cbc_decrypt(desc, &walk);
+                err = blkcipher_walk_done(desc, &walk, nbytes);
+        }
+
+        bf_fpu_end(fpu_enabled);
+        return err;
+}
+
+static void ctr_crypt_final(struct blkcipher_desc *desc,
+                            struct blkcipher_walk *walk)
+{
+        struct bf_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+        u8 *ctrblk = walk->iv;
+        u8 keystream[BF_BLOCK_SIZE];
+        u8 *src = walk->src.virt.addr;
+        u8 *dst = walk->dst.virt.addr;
+        unsigned int nbytes = walk->nbytes;
+
+        blowfish_enc_blk(ctx, keystream, ctrblk);
+        crypto_xor(keystream, src, nbytes);
+        memcpy(dst, keystream, nbytes);
+
+        crypto_inc(ctrblk, BF_BLOCK_SIZE);
+}
+
+static unsigned int __ctr_crypt(struct blkcipher_desc *desc,
+                                struct blkcipher_walk *walk)
+{
+        struct bf_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+        unsigned int bsize = BF_BLOCK_SIZE;
+        unsigned int nbytes = walk->nbytes;
+        u64 *src = (u64 *)walk->src.virt.addr;
+        u64 *dst = (u64 *)walk->dst.virt.addr;
+        int i;
+
+        /* Process multi-block AVX2 batch */
+        if (nbytes >= bsize * BF_AVX2_PARALLEL_BLOCKS) {
+                do {
+                        blowfish_ctr_32way(ctx, (u8 *)dst, (u8 *)src,
+                                           (__be64 *)walk->iv);
+
+                        src += BF_AVX2_PARALLEL_BLOCKS;
+                        dst += BF_AVX2_PARALLEL_BLOCKS;
+                        nbytes -= bsize * BF_AVX2_PARALLEL_BLOCKS;
+                } while (nbytes >= bsize * BF_AVX2_PARALLEL_BLOCKS);
+
+                if (nbytes < bsize)
+                        goto done;
+        }
+
+        /* Process four block batch */
+        if (nbytes >= bsize * BF_PARALLEL_BLOCKS) {
+                __be64 ctrblocks[BF_PARALLEL_BLOCKS];
+                u64 ctrblk = be64_to_cpu(*(__be64 *)walk->iv);
+
+                do {
+                        /* create ctrblks for parallel encrypt */
+                        for (i = 0; i < BF_PARALLEL_BLOCKS; i++) {
+                                if (dst != src)
+                                        dst[i] = src[i];
+
+                                ctrblocks[i] = cpu_to_be64(ctrblk++);
+                        }
+
+                        blowfish_enc_blk_xor_4way(ctx, (u8 *)dst,
+                                                  (u8 *)ctrblocks);
+
+                        src += BF_PARALLEL_BLOCKS;
+                        dst += BF_PARALLEL_BLOCKS;
+                        nbytes -= bsize * BF_PARALLEL_BLOCKS;
+                } while (nbytes >= bsize * BF_PARALLEL_BLOCKS);
+
+                *(__be64 *)walk->iv = cpu_to_be64(ctrblk);
+
+                if (nbytes < bsize)
+                        goto done;
+        }
+
+        /* Handle leftovers */
+        do {
+                u64 ctrblk;
+
+                if (dst != src)
+                        *dst = *src;
+
+                ctrblk = *(u64 *)walk->iv;
+                be64_add_cpu((__be64 *)walk->iv, 1);
+
+                blowfish_enc_blk_xor(ctx, (u8 *)dst, (u8 *)&ctrblk);
+
+                src += 1;
+                dst += 1;
+        } while ((nbytes -= bsize) >= bsize);
+
+done:
+        return nbytes;
+}
+
+static int ctr_crypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                     struct scatterlist *src, unsigned int nbytes)
+{
+        bool fpu_enabled = false;
+        struct blkcipher_walk walk;
+        int err;
+
+        blkcipher_walk_init(&walk, dst, src, nbytes);
+        err = blkcipher_walk_virt_block(desc, &walk, BF_BLOCK_SIZE);
+        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
+
+        while ((nbytes = walk.nbytes) >= BF_BLOCK_SIZE) {
+                fpu_enabled = bf_fpu_begin(fpu_enabled, nbytes);
+                nbytes = __ctr_crypt(desc, &walk);
+                err = blkcipher_walk_done(desc, &walk, nbytes);
+        }
+
+        bf_fpu_end(fpu_enabled);
+
+        if (walk.nbytes) {
+                ctr_crypt_final(desc, &walk);
+                err = blkcipher_walk_done(desc, &walk, 0);
+        }
+
+        return err;
+}
+
+static struct crypto_alg bf_algs[6] = { {
+        .cra_name               = "__ecb-blowfish-avx2",
+        .cra_driver_name        = "__driver-ecb-blowfish-avx2",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = BF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct bf_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = BF_MIN_KEY_SIZE,
+                        .max_keysize    = BF_MAX_KEY_SIZE,
+                        .setkey         = blowfish_setkey,
+                        .encrypt        = ecb_encrypt,
+                        .decrypt        = ecb_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "__cbc-blowfish-avx2",
+        .cra_driver_name        = "__driver-cbc-blowfish-avx2",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = BF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct bf_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = BF_MIN_KEY_SIZE,
+                        .max_keysize    = BF_MAX_KEY_SIZE,
+                        .setkey         = blowfish_setkey,
+                        .encrypt        = cbc_encrypt,
+                        .decrypt        = cbc_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "__ctr-blowfish-avx2",
+        .cra_driver_name        = "__driver-ctr-blowfish-avx2",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = 1,
+        .cra_ctxsize            = sizeof(struct bf_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = BF_MIN_KEY_SIZE,
+                        .max_keysize    = BF_MAX_KEY_SIZE,
+                        .ivsize         = BF_BLOCK_SIZE,
+                        .setkey         = blowfish_setkey,
+                        .encrypt        = ctr_crypt,
+                        .decrypt        = ctr_crypt,
+                },
+        },
+}, {
+        .cra_name               = "ecb(blowfish)",
+        .cra_driver_name        = "ecb-blowfish-avx2",
+        .cra_priority           = 400,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = BF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = BF_MIN_KEY_SIZE,
+                        .max_keysize    = BF_MAX_KEY_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "cbc(blowfish)",
+        .cra_driver_name        = "cbc-blowfish-avx2",
+        .cra_priority           = 400,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = BF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = BF_MIN_KEY_SIZE,
+                        .max_keysize    = BF_MAX_KEY_SIZE,
+                        .ivsize         = BF_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = __ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "ctr(blowfish)",
+        .cra_driver_name        = "ctr-blowfish-avx2",
+        .cra_priority           = 400,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = 1,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = BF_MIN_KEY_SIZE,
+                        .max_keysize    = BF_MAX_KEY_SIZE,
+                        .ivsize         = BF_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_encrypt,
+                        .geniv          = "chainiv",
+                },
+        },
+} };
+
+
+static int __init init(void)
+{
+        u64 xcr0;
+
+        if (!cpu_has_avx2 || !cpu_has_osxsave) {
+                pr_info("AVX2 instructions are not detected.\n");
+                return -ENODEV;
+        }
+
+        xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
+        if ((xcr0 & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM)) {
+                pr_info("AVX detected but unusable.\n");
+                return -ENODEV;
+        }
+
+        return crypto_register_algs(bf_algs, ARRAY_SIZE(bf_algs));
+}
+
+static void __exit fini(void)
+{
+        crypto_unregister_algs(bf_algs, ARRAY_SIZE(bf_algs));
+}
+
+module_init(init);
+module_exit(fini);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Blowfish Cipher Algorithm, AVX2 optimized");
+MODULE_ALIAS("blowfish");
+MODULE_ALIAS("blowfish-asm");
diff --git a/arch/x86/crypto/blowfish_glue.c b/arch/x86/crypto/blowfish_glue.c
index 50ec333b70e6..3548d76dbaa9 100644
--- a/arch/x86/crypto/blowfish_glue.c
+++ b/arch/x86/crypto/blowfish_glue.c
@@ -1,7 +1,7 @@
 /*
  * Glue Code for assembler optimized version of Blowfish
  *
- * Copyright (c) 2011 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
+ * Copyright © 2011-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
  *
  * CBC & ECB parts based on code (crypto/cbc.c,ecb.c) by:
  *   Copyright (c) 2006 Herbert Xu <herbert@gondor.apana.org.au>
@@ -32,40 +32,24 @@
 #include <linux/module.h>
 #include <linux/types.h>
 #include <crypto/algapi.h>
+#include <asm/crypto/blowfish.h>
 
 /* regular block cipher functions */
 asmlinkage void __blowfish_enc_blk(struct bf_ctx *ctx, u8 *dst, const u8 *src,
                                    bool xor);
+EXPORT_SYMBOL_GPL(__blowfish_enc_blk);
+
 asmlinkage void blowfish_dec_blk(struct bf_ctx *ctx, u8 *dst, const u8 *src);
+EXPORT_SYMBOL_GPL(blowfish_dec_blk);
 
 /* 4-way parallel cipher functions */
 asmlinkage void __blowfish_enc_blk_4way(struct bf_ctx *ctx, u8 *dst,
                                         const u8 *src, bool xor);
+EXPORT_SYMBOL_GPL(__blowfish_enc_blk_4way);
+
 asmlinkage void blowfish_dec_blk_4way(struct bf_ctx *ctx, u8 *dst,
                                       const u8 *src);
-
-static inline void blowfish_enc_blk(struct bf_ctx *ctx, u8 *dst, const u8 *src)
-{
-        __blowfish_enc_blk(ctx, dst, src, false);
-}
-
-static inline void blowfish_enc_blk_xor(struct bf_ctx *ctx, u8 *dst,
-                                        const u8 *src)
-{
-        __blowfish_enc_blk(ctx, dst, src, true);
-}
-
-static inline void blowfish_enc_blk_4way(struct bf_ctx *ctx, u8 *dst,
-                                         const u8 *src)
-{
-        __blowfish_enc_blk_4way(ctx, dst, src, false);
-}
-
-static inline void blowfish_enc_blk_xor_4way(struct bf_ctx *ctx, u8 *dst,
-                                      const u8 *src)
-{
-        __blowfish_enc_blk_4way(ctx, dst, src, true);
-}
+EXPORT_SYMBOL_GPL(blowfish_dec_blk_4way);
 
 static void blowfish_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
 {
diff --git a/arch/x86/crypto/camellia-aesni-avx-asm_64.S b/arch/x86/crypto/camellia-aesni-avx-asm_64.S
index cfc163469c71..ce71f9212409 100644
--- a/arch/x86/crypto/camellia-aesni-avx-asm_64.S
+++ b/arch/x86/crypto/camellia-aesni-avx-asm_64.S
@@ -1,7 +1,7 @@
 /*
  * x86_64/AVX/AES-NI assembler implementation of Camellia
  *
- * Copyright © 2012 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
+ * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -589,6 +589,10 @@ ENDPROC(roundsm16_x4_x5_x6_x7_x0_x1_x2_x3_y4_y5_y6_y7_y0_y1_y2_y3_ab)
 .Lbswap128_mask:
         .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
 
+/* For XTS mode IV generation */
+.Lxts_gf128mul_and_shl1_mask:
+        .byte 0x87, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0
+
 /*
  * pre-SubByte transform
  *
@@ -1090,3 +1094,177 @@ ENTRY(camellia_ctr_16way)
 
         ret;
 ENDPROC(camellia_ctr_16way)
+
+#define gf128mul_x_ble(iv, mask, tmp) \
+        vpsrad $31, iv, tmp; \
+        vpaddq iv, iv, iv; \
+        vpshufd $0x13, tmp, tmp; \
+        vpand mask, tmp, tmp; \
+        vpxor tmp, iv, iv;
+
+.align 8
+camellia_xts_crypt_16way:
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst (16 blocks)
+         *      %rdx: src (16 blocks)
+         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
+         *      %r8: index for input whitening key
+         *      %r9: pointer to  __camellia_enc_blk16 or __camellia_dec_blk16
+         */
+
+        subq $(16 * 16), %rsp;
+        movq %rsp, %rax;
+
+        vmovdqa .Lxts_gf128mul_and_shl1_mask, %xmm14;
+
+        /* load IV */
+        vmovdqu (%rcx), %xmm0;
+        vpxor 0 * 16(%rdx), %xmm0, %xmm15;
+        vmovdqu %xmm15, 15 * 16(%rax);
+        vmovdqu %xmm0, 0 * 16(%rsi);
+
+        /* construct IVs */
+        gf128mul_x_ble(%xmm0, %xmm14, %xmm15);
+        vpxor 1 * 16(%rdx), %xmm0, %xmm15;
+        vmovdqu %xmm15, 14 * 16(%rax);
+        vmovdqu %xmm0, 1 * 16(%rsi);
+
+        gf128mul_x_ble(%xmm0, %xmm14, %xmm15);
+        vpxor 2 * 16(%rdx), %xmm0, %xmm13;
+        vmovdqu %xmm0, 2 * 16(%rsi);
+
+        gf128mul_x_ble(%xmm0, %xmm14, %xmm15);
+        vpxor 3 * 16(%rdx), %xmm0, %xmm12;
+        vmovdqu %xmm0, 3 * 16(%rsi);
+
+        gf128mul_x_ble(%xmm0, %xmm14, %xmm15);
+        vpxor 4 * 16(%rdx), %xmm0, %xmm11;
+        vmovdqu %xmm0, 4 * 16(%rsi);
+
+        gf128mul_x_ble(%xmm0, %xmm14, %xmm15);
+        vpxor 5 * 16(%rdx), %xmm0, %xmm10;
+        vmovdqu %xmm0, 5 * 16(%rsi);
+
+        gf128mul_x_ble(%xmm0, %xmm14, %xmm15);
+        vpxor 6 * 16(%rdx), %xmm0, %xmm9;
+        vmovdqu %xmm0, 6 * 16(%rsi);
+
+        gf128mul_x_ble(%xmm0, %xmm14, %xmm15);
+        vpxor 7 * 16(%rdx), %xmm0, %xmm8;
+        vmovdqu %xmm0, 7 * 16(%rsi);
+
+        gf128mul_x_ble(%xmm0, %xmm14, %xmm15);
+        vpxor 8 * 16(%rdx), %xmm0, %xmm7;
+        vmovdqu %xmm0, 8 * 16(%rsi);
+
+        gf128mul_x_ble(%xmm0, %xmm14, %xmm15);
+        vpxor 9 * 16(%rdx), %xmm0, %xmm6;
+        vmovdqu %xmm0, 9 * 16(%rsi);
+
+        gf128mul_x_ble(%xmm0, %xmm14, %xmm15);
+        vpxor 10 * 16(%rdx), %xmm0, %xmm5;
+        vmovdqu %xmm0, 10 * 16(%rsi);
+
+        gf128mul_x_ble(%xmm0, %xmm14, %xmm15);
+        vpxor 11 * 16(%rdx), %xmm0, %xmm4;
+        vmovdqu %xmm0, 11 * 16(%rsi);
+
+        gf128mul_x_ble(%xmm0, %xmm14, %xmm15);
+        vpxor 12 * 16(%rdx), %xmm0, %xmm3;
+        vmovdqu %xmm0, 12 * 16(%rsi);
+
+        gf128mul_x_ble(%xmm0, %xmm14, %xmm15);
+        vpxor 13 * 16(%rdx), %xmm0, %xmm2;
+        vmovdqu %xmm0, 13 * 16(%rsi);
+
+        gf128mul_x_ble(%xmm0, %xmm14, %xmm15);
+        vpxor 14 * 16(%rdx), %xmm0, %xmm1;
+        vmovdqu %xmm0, 14 * 16(%rsi);
+
+        gf128mul_x_ble(%xmm0, %xmm14, %xmm15);
+        vpxor 15 * 16(%rdx), %xmm0, %xmm15;
+        vmovdqu %xmm15, 0 * 16(%rax);
+        vmovdqu %xmm0, 15 * 16(%rsi);
+
+        gf128mul_x_ble(%xmm0, %xmm14, %xmm15);
+        vmovdqu %xmm0, (%rcx);
+
+        /* inpack16_pre: */
+        vmovq (key_table)(CTX, %r8, 8), %xmm15;
+        vpshufb .Lpack_bswap, %xmm15, %xmm15;
+        vpxor 0 * 16(%rax), %xmm15, %xmm0;
+        vpxor %xmm1, %xmm15, %xmm1;
+        vpxor %xmm2, %xmm15, %xmm2;
+        vpxor %xmm3, %xmm15, %xmm3;
+        vpxor %xmm4, %xmm15, %xmm4;
+        vpxor %xmm5, %xmm15, %xmm5;
+        vpxor %xmm6, %xmm15, %xmm6;
+        vpxor %xmm7, %xmm15, %xmm7;
+        vpxor %xmm8, %xmm15, %xmm8;
+        vpxor %xmm9, %xmm15, %xmm9;
+        vpxor %xmm10, %xmm15, %xmm10;
+        vpxor %xmm11, %xmm15, %xmm11;
+        vpxor %xmm12, %xmm15, %xmm12;
+        vpxor %xmm13, %xmm15, %xmm13;
+        vpxor 14 * 16(%rax), %xmm15, %xmm14;
+        vpxor 15 * 16(%rax), %xmm15, %xmm15;
+
+        call *%r9;
+
+        addq $(16 * 16), %rsp;
+
+        vpxor 0 * 16(%rsi), %xmm7, %xmm7;
+        vpxor 1 * 16(%rsi), %xmm6, %xmm6;
+        vpxor 2 * 16(%rsi), %xmm5, %xmm5;
+        vpxor 3 * 16(%rsi), %xmm4, %xmm4;
+        vpxor 4 * 16(%rsi), %xmm3, %xmm3;
+        vpxor 5 * 16(%rsi), %xmm2, %xmm2;
+        vpxor 6 * 16(%rsi), %xmm1, %xmm1;
+        vpxor 7 * 16(%rsi), %xmm0, %xmm0;
+        vpxor 8 * 16(%rsi), %xmm15, %xmm15;
+        vpxor 9 * 16(%rsi), %xmm14, %xmm14;
+        vpxor 10 * 16(%rsi), %xmm13, %xmm13;
+        vpxor 11 * 16(%rsi), %xmm12, %xmm12;
+        vpxor 12 * 16(%rsi), %xmm11, %xmm11;
+        vpxor 13 * 16(%rsi), %xmm10, %xmm10;
+        vpxor 14 * 16(%rsi), %xmm9, %xmm9;
+        vpxor 15 * 16(%rsi), %xmm8, %xmm8;
+        write_output(%xmm7, %xmm6, %xmm5, %xmm4, %xmm3, %xmm2, %xmm1, %xmm0,
+                     %xmm15, %xmm14, %xmm13, %xmm12, %xmm11, %xmm10, %xmm9,
+                     %xmm8, %rsi);
+
+        ret;
+ENDPROC(camellia_xts_crypt_16way)
+
+ENTRY(camellia_xts_enc_16way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst (16 blocks)
+         *      %rdx: src (16 blocks)
+         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
+         */
+        xorl %r8d, %r8d; /* input whitening key, 0 for enc */
+
+        leaq __camellia_enc_blk16, %r9;
+
+        jmp camellia_xts_crypt_16way;
+ENDPROC(camellia_xts_enc_16way)
+
+ENTRY(camellia_xts_dec_16way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst (16 blocks)
+         *      %rdx: src (16 blocks)
+         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
+         */
+
+        cmpl $16, key_length(CTX);
+        movl $32, %r8d;
+        movl $24, %eax;
+        cmovel %eax, %r8d;  /* input whitening key, last for dec */
+
+        leaq __camellia_dec_blk16, %r9;
+
+        jmp camellia_xts_crypt_16way;
+ENDPROC(camellia_xts_dec_16way)
diff --git a/arch/x86/crypto/camellia-aesni-avx2-asm_64.S b/arch/x86/crypto/camellia-aesni-avx2-asm_64.S
new file mode 100644
index 000000000000..91a1878fcc3e
--- /dev/null
+++ b/arch/x86/crypto/camellia-aesni-avx2-asm_64.S
@@ -0,0 +1,1368 @@
+/*
+ * x86_64/AVX2/AES-NI assembler implementation of Camellia
+ *
+ * Copyright © 2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/linkage.h>
+
+#define CAMELLIA_TABLE_BYTE_LEN 272
+
+/* struct camellia_ctx: */
+#define key_table 0
+#define key_length CAMELLIA_TABLE_BYTE_LEN
+
+/* register macros */
+#define CTX %rdi
+#define RIO %r8
+
+/**********************************************************************
+  helper macros
+ **********************************************************************/
+#define filter_8bit(x, lo_t, hi_t, mask4bit, tmp0) \
+        vpand x, mask4bit, tmp0; \
+        vpandn x, mask4bit, x; \
+        vpsrld $4, x, x; \
+        \
+        vpshufb tmp0, lo_t, tmp0; \
+        vpshufb x, hi_t, x; \
+        vpxor tmp0, x, x;
+
+#define ymm0_x xmm0
+#define ymm1_x xmm1
+#define ymm2_x xmm2
+#define ymm3_x xmm3
+#define ymm4_x xmm4
+#define ymm5_x xmm5
+#define ymm6_x xmm6
+#define ymm7_x xmm7
+#define ymm8_x xmm8
+#define ymm9_x xmm9
+#define ymm10_x xmm10
+#define ymm11_x xmm11
+#define ymm12_x xmm12
+#define ymm13_x xmm13
+#define ymm14_x xmm14
+#define ymm15_x xmm15
+
+/*
+ * AES-NI instructions do not support ymmX registers, so we need splitting and
+ * merging.
+ */
+#define vaesenclast256(zero, yreg, tmp) \
+        vextracti128 $1, yreg, tmp##_x; \
+        vaesenclast zero##_x, yreg##_x, yreg##_x; \
+        vaesenclast zero##_x, tmp##_x, tmp##_x; \
+        vinserti128 $1, tmp##_x, yreg, yreg;
+
+/**********************************************************************
+  32-way camellia
+ **********************************************************************/
+
+/*
+ * IN:
+ *   x0..x7: byte-sliced AB state
+ *   mem_cd: register pointer storing CD state
+ *   key: index for key material
+ * OUT:
+ *   x0..x7: new byte-sliced CD state
+ */
+#define roundsm32(x0, x1, x2, x3, x4, x5, x6, x7, t0, t1, t2, t3, t4, t5, t6, \
+                  t7, mem_cd, key) \
+        /* \
+         * S-function with AES subbytes \
+         */ \
+        vbroadcasti128 .Linv_shift_row, t4; \
+        vpbroadcastb .L0f0f0f0f, t7; \
+        vbroadcasti128 .Lpre_tf_lo_s1, t0; \
+        vbroadcasti128 .Lpre_tf_hi_s1, t1; \
+        \
+        /* AES inverse shift rows */ \
+        vpshufb t4, x0, x0; \
+        vpshufb t4, x7, x7; \
+        vpshufb t4, x1, x1; \
+        vpshufb t4, x4, x4; \
+        vpshufb t4, x2, x2; \
+        vpshufb t4, x5, x5; \
+        vpshufb t4, x3, x3; \
+        vpshufb t4, x6, x6; \
+        \
+        /* prefilter sboxes 1, 2 and 3 */ \
+        vbroadcasti128 .Lpre_tf_lo_s4, t2; \
+        vbroadcasti128 .Lpre_tf_hi_s4, t3; \
+        filter_8bit(x0, t0, t1, t7, t6); \
+        filter_8bit(x7, t0, t1, t7, t6); \
+        filter_8bit(x1, t0, t1, t7, t6); \
+        filter_8bit(x4, t0, t1, t7, t6); \
+        filter_8bit(x2, t0, t1, t7, t6); \
+        filter_8bit(x5, t0, t1, t7, t6); \
+        \
+        /* prefilter sbox 4 */ \
+        vpxor t4##_x, t4##_x, t4##_x; \
+        filter_8bit(x3, t2, t3, t7, t6); \
+        filter_8bit(x6, t2, t3, t7, t6); \
+        \
+        /* AES subbytes + AES shift rows */ \
+        vbroadcasti128 .Lpost_tf_lo_s1, t0; \
+        vbroadcasti128 .Lpost_tf_hi_s1, t1; \
+        vaesenclast256(t4, x0, t5); \
+        vaesenclast256(t4, x7, t5); \
+        vaesenclast256(t4, x1, t5); \
+        vaesenclast256(t4, x4, t5); \
+        vaesenclast256(t4, x2, t5); \
+        vaesenclast256(t4, x5, t5); \
+        vaesenclast256(t4, x3, t5); \
+        vaesenclast256(t4, x6, t5); \
+        \
+        /* postfilter sboxes 1 and 4 */ \
+        vbroadcasti128 .Lpost_tf_lo_s3, t2; \
+        vbroadcasti128 .Lpost_tf_hi_s3, t3; \
+        filter_8bit(x0, t0, t1, t7, t6); \
+        filter_8bit(x7, t0, t1, t7, t6); \
+        filter_8bit(x3, t0, t1, t7, t6); \
+        filter_8bit(x6, t0, t1, t7, t6); \
+        \
+        /* postfilter sbox 3 */ \
+        vbroadcasti128 .Lpost_tf_lo_s2, t4; \
+        vbroadcasti128 .Lpost_tf_hi_s2, t5; \
+        filter_8bit(x2, t2, t3, t7, t6); \
+        filter_8bit(x5, t2, t3, t7, t6); \
+        \
+        vpbroadcastq key, t0; /* higher 64-bit duplicate ignored */ \
+        \
+        /* postfilter sbox 2 */ \
+        filter_8bit(x1, t4, t5, t7, t2); \
+        filter_8bit(x4, t4, t5, t7, t2); \
+        \
+        vpsrldq $1, t0, t1; \
+        vpsrldq $2, t0, t2; \
+        vpsrldq $3, t0, t3; \
+        vpsrldq $4, t0, t4; \
+        vpsrldq $5, t0, t5; \
+        vpsrldq $6, t0, t6; \
+        vpsrldq $7, t0, t7; \
+        vpbroadcastb t0##_x, t0; \
+        vpbroadcastb t1##_x, t1; \
+        vpbroadcastb t2##_x, t2; \
+        vpbroadcastb t3##_x, t3; \
+        vpbroadcastb t4##_x, t4; \
+        vpbroadcastb t6##_x, t6; \
+        vpbroadcastb t5##_x, t5; \
+        vpbroadcastb t7##_x, t7; \
+        \
+        /* P-function */ \
+        vpxor x5, x0, x0; \
+        vpxor x6, x1, x1; \
+        vpxor x7, x2, x2; \
+        vpxor x4, x3, x3; \
+        \
+        vpxor x2, x4, x4; \
+        vpxor x3, x5, x5; \
+        vpxor x0, x6, x6; \
+        vpxor x1, x7, x7; \
+        \
+        vpxor x7, x0, x0; \
+        vpxor x4, x1, x1; \
+        vpxor x5, x2, x2; \
+        vpxor x6, x3, x3; \
+        \
+        vpxor x3, x4, x4; \
+        vpxor x0, x5, x5; \
+        vpxor x1, x6, x6; \
+        vpxor x2, x7, x7; /* note: high and low parts swapped */ \
+        \
+        /* Add key material and result to CD (x becomes new CD) */ \
+        \
+        vpxor t7, x0, x0; \
+        vpxor 4 * 32(mem_cd), x0, x0; \
+        \
+        vpxor t6, x1, x1; \
+        vpxor 5 * 32(mem_cd), x1, x1; \
+        \
+        vpxor t5, x2, x2; \
+        vpxor 6 * 32(mem_cd), x2, x2; \
+        \
+        vpxor t4, x3, x3; \
+        vpxor 7 * 32(mem_cd), x3, x3; \
+        \
+        vpxor t3, x4, x4; \
+        vpxor 0 * 32(mem_cd), x4, x4; \
+        \
+        vpxor t2, x5, x5; \
+        vpxor 1 * 32(mem_cd), x5, x5; \
+        \
+        vpxor t1, x6, x6; \
+        vpxor 2 * 32(mem_cd), x6, x6; \
+        \
+        vpxor t0, x7, x7; \
+        vpxor 3 * 32(mem_cd), x7, x7;
+
+/*
+ * Size optimization... with inlined roundsm16 binary would be over 5 times
+ * larger and would only marginally faster.
+ */
+.align 8
+roundsm32_x0_x1_x2_x3_x4_x5_x6_x7_y0_y1_y2_y3_y4_y5_y6_y7_cd:
+        roundsm32(%ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+                  %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14, %ymm15,
+                  %rcx, (%r9));
+        ret;
+ENDPROC(roundsm32_x0_x1_x2_x3_x4_x5_x6_x7_y0_y1_y2_y3_y4_y5_y6_y7_cd)
+
+.align 8
+roundsm32_x4_x5_x6_x7_x0_x1_x2_x3_y4_y5_y6_y7_y0_y1_y2_y3_ab:
+        roundsm32(%ymm4, %ymm5, %ymm6, %ymm7, %ymm0, %ymm1, %ymm2, %ymm3,
+                  %ymm12, %ymm13, %ymm14, %ymm15, %ymm8, %ymm9, %ymm10, %ymm11,
+                  %rax, (%r9));
+        ret;
+ENDPROC(roundsm32_x4_x5_x6_x7_x0_x1_x2_x3_y4_y5_y6_y7_y0_y1_y2_y3_ab)
+
+/*
+ * IN/OUT:
+ *  x0..x7: byte-sliced AB state preloaded
+ *  mem_ab: byte-sliced AB state in memory
+ *  mem_cb: byte-sliced CD state in memory
+ */
+#define two_roundsm32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
+                      y6, y7, mem_ab, mem_cd, i, dir, store_ab) \
+        leaq (key_table + (i) * 8)(CTX), %r9; \
+        call roundsm32_x0_x1_x2_x3_x4_x5_x6_x7_y0_y1_y2_y3_y4_y5_y6_y7_cd; \
+        \
+        vmovdqu x0, 4 * 32(mem_cd); \
+        vmovdqu x1, 5 * 32(mem_cd); \
+        vmovdqu x2, 6 * 32(mem_cd); \
+        vmovdqu x3, 7 * 32(mem_cd); \
+        vmovdqu x4, 0 * 32(mem_cd); \
+        vmovdqu x5, 1 * 32(mem_cd); \
+        vmovdqu x6, 2 * 32(mem_cd); \
+        vmovdqu x7, 3 * 32(mem_cd); \
+        \
+        leaq (key_table + ((i) + (dir)) * 8)(CTX), %r9; \
+        call roundsm32_x4_x5_x6_x7_x0_x1_x2_x3_y4_y5_y6_y7_y0_y1_y2_y3_ab; \
+        \
+        store_ab(x0, x1, x2, x3, x4, x5, x6, x7, mem_ab);
+
+#define dummy_store(x0, x1, x2, x3, x4, x5, x6, x7, mem_ab) /* do nothing */
+
+#define store_ab_state(x0, x1, x2, x3, x4, x5, x6, x7, mem_ab) \
+        /* Store new AB state */ \
+        vmovdqu x4, 4 * 32(mem_ab); \
+        vmovdqu x5, 5 * 32(mem_ab); \
+        vmovdqu x6, 6 * 32(mem_ab); \
+        vmovdqu x7, 7 * 32(mem_ab); \
+        vmovdqu x0, 0 * 32(mem_ab); \
+        vmovdqu x1, 1 * 32(mem_ab); \
+        vmovdqu x2, 2 * 32(mem_ab); \
+        vmovdqu x3, 3 * 32(mem_ab);
+
+#define enc_rounds32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
+                      y6, y7, mem_ab, mem_cd, i) \
+        two_roundsm32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
+                      y6, y7, mem_ab, mem_cd, (i) + 2, 1, store_ab_state); \
+        two_roundsm32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
+                      y6, y7, mem_ab, mem_cd, (i) + 4, 1, store_ab_state); \
+        two_roundsm32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
+                      y6, y7, mem_ab, mem_cd, (i) + 6, 1, dummy_store);
+
+#define dec_rounds32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
+                      y6, y7, mem_ab, mem_cd, i) \
+        two_roundsm32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
+                      y6, y7, mem_ab, mem_cd, (i) + 7, -1, store_ab_state); \
+        two_roundsm32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
+                      y6, y7, mem_ab, mem_cd, (i) + 5, -1, store_ab_state); \
+        two_roundsm32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
+                      y6, y7, mem_ab, mem_cd, (i) + 3, -1, dummy_store);
+
+/*
+ * IN:
+ *  v0..3: byte-sliced 32-bit integers
+ * OUT:
+ *  v0..3: (IN <<< 1)
+ */
+#define rol32_1_32(v0, v1, v2, v3, t0, t1, t2, zero) \
+        vpcmpgtb v0, zero, t0; \
+        vpaddb v0, v0, v0; \
+        vpabsb t0, t0; \
+        \
+        vpcmpgtb v1, zero, t1; \
+        vpaddb v1, v1, v1; \
+        vpabsb t1, t1; \
+        \
+        vpcmpgtb v2, zero, t2; \
+        vpaddb v2, v2, v2; \
+        vpabsb t2, t2; \
+        \
+        vpor t0, v1, v1; \
+        \
+        vpcmpgtb v3, zero, t0; \
+        vpaddb v3, v3, v3; \
+        vpabsb t0, t0; \
+        \
+        vpor t1, v2, v2; \
+        vpor t2, v3, v3; \
+        vpor t0, v0, v0;
+
+/*
+ * IN:
+ *   r: byte-sliced AB state in memory
+ *   l: byte-sliced CD state in memory
+ * OUT:
+ *   x0..x7: new byte-sliced CD state
+ */
+#define fls32(l, l0, l1, l2, l3, l4, l5, l6, l7, r, t0, t1, t2, t3, tt0, \
+              tt1, tt2, tt3, kll, klr, krl, krr) \
+        /* \
+         * t0 = kll; \
+         * t0 &= ll; \
+         * lr ^= rol32(t0, 1); \
+         */ \
+        vpbroadcastd kll, t0; /* only lowest 32-bit used */ \
+        vpxor tt0, tt0, tt0; \
+        vpbroadcastb t0##_x, t3; \
+        vpsrldq $1, t0, t0; \
+        vpbroadcastb t0##_x, t2; \
+        vpsrldq $1, t0, t0; \
+        vpbroadcastb t0##_x, t1; \
+        vpsrldq $1, t0, t0; \
+        vpbroadcastb t0##_x, t0; \
+        \
+        vpand l0, t0, t0; \
+        vpand l1, t1, t1; \
+        vpand l2, t2, t2; \
+        vpand l3, t3, t3; \
+        \
+        rol32_1_32(t3, t2, t1, t0, tt1, tt2, tt3, tt0); \
+        \
+        vpxor l4, t0, l4; \
+        vmovdqu l4, 4 * 32(l); \
+        vpxor l5, t1, l5; \
+        vmovdqu l5, 5 * 32(l); \
+        vpxor l6, t2, l6; \
+        vmovdqu l6, 6 * 32(l); \
+        vpxor l7, t3, l7; \
+        vmovdqu l7, 7 * 32(l); \
+        \
+        /* \
+         * t2 = krr; \
+         * t2 |= rr; \
+         * rl ^= t2; \
+         */ \
+        \
+        vpbroadcastd krr, t0; /* only lowest 32-bit used */ \
+        vpbroadcastb t0##_x, t3; \
+        vpsrldq $1, t0, t0; \
+        vpbroadcastb t0##_x, t2; \
+        vpsrldq $1, t0, t0; \
+        vpbroadcastb t0##_x, t1; \
+        vpsrldq $1, t0, t0; \
+        vpbroadcastb t0##_x, t0; \
+        \
+        vpor 4 * 32(r), t0, t0; \
+        vpor 5 * 32(r), t1, t1; \
+        vpor 6 * 32(r), t2, t2; \
+        vpor 7 * 32(r), t3, t3; \
+        \
+        vpxor 0 * 32(r), t0, t0; \
+        vpxor 1 * 32(r), t1, t1; \
+        vpxor 2 * 32(r), t2, t2; \
+        vpxor 3 * 32(r), t3, t3; \
+        vmovdqu t0, 0 * 32(r); \
+        vmovdqu t1, 1 * 32(r); \
+        vmovdqu t2, 2 * 32(r); \
+        vmovdqu t3, 3 * 32(r); \
+        \
+        /* \
+         * t2 = krl; \
+         * t2 &= rl; \
+         * rr ^= rol32(t2, 1); \
+         */ \
+        vpbroadcastd krl, t0; /* only lowest 32-bit used */ \
+        vpbroadcastb t0##_x, t3; \
+        vpsrldq $1, t0, t0; \
+        vpbroadcastb t0##_x, t2; \
+        vpsrldq $1, t0, t0; \
+        vpbroadcastb t0##_x, t1; \
+        vpsrldq $1, t0, t0; \
+        vpbroadcastb t0##_x, t0; \
+        \
+        vpand 0 * 32(r), t0, t0; \
+        vpand 1 * 32(r), t1, t1; \
+        vpand 2 * 32(r), t2, t2; \
+        vpand 3 * 32(r), t3, t3; \
+        \
+        rol32_1_32(t3, t2, t1, t0, tt1, tt2, tt3, tt0); \
+        \
+        vpxor 4 * 32(r), t0, t0; \
+        vpxor 5 * 32(r), t1, t1; \
+        vpxor 6 * 32(r), t2, t2; \
+        vpxor 7 * 32(r), t3, t3; \
+        vmovdqu t0, 4 * 32(r); \
+        vmovdqu t1, 5 * 32(r); \
+        vmovdqu t2, 6 * 32(r); \
+        vmovdqu t3, 7 * 32(r); \
+        \
+        /* \
+         * t0 = klr; \
+         * t0 |= lr; \
+         * ll ^= t0; \
+         */ \
+        \
+        vpbroadcastd klr, t0; /* only lowest 32-bit used */ \
+        vpbroadcastb t0##_x, t3; \
+        vpsrldq $1, t0, t0; \
+        vpbroadcastb t0##_x, t2; \
+        vpsrldq $1, t0, t0; \
+        vpbroadcastb t0##_x, t1; \
+        vpsrldq $1, t0, t0; \
+        vpbroadcastb t0##_x, t0; \
+        \
+        vpor l4, t0, t0; \
+        vpor l5, t1, t1; \
+        vpor l6, t2, t2; \
+        vpor l7, t3, t3; \
+        \
+        vpxor l0, t0, l0; \
+        vmovdqu l0, 0 * 32(l); \
+        vpxor l1, t1, l1; \
+        vmovdqu l1, 1 * 32(l); \
+        vpxor l2, t2, l2; \
+        vmovdqu l2, 2 * 32(l); \
+        vpxor l3, t3, l3; \
+        vmovdqu l3, 3 * 32(l);
+
+#define transpose_4x4(x0, x1, x2, x3, t1, t2) \
+        vpunpckhdq x1, x0, t2; \
+        vpunpckldq x1, x0, x0; \
+        \
+        vpunpckldq x3, x2, t1; \
+        vpunpckhdq x3, x2, x2; \
+        \
+        vpunpckhqdq t1, x0, x1; \
+        vpunpcklqdq t1, x0, x0; \
+        \
+        vpunpckhqdq x2, t2, x3; \
+        vpunpcklqdq x2, t2, x2;
+
+#define byteslice_16x16b_fast(a0, b0, c0, d0, a1, b1, c1, d1, a2, b2, c2, d2, \
+                              a3, b3, c3, d3, st0, st1) \
+        vmovdqu d2, st0; \
+        vmovdqu d3, st1; \
+        transpose_4x4(a0, a1, a2, a3, d2, d3); \
+        transpose_4x4(b0, b1, b2, b3, d2, d3); \
+        vmovdqu st0, d2; \
+        vmovdqu st1, d3; \
+        \
+        vmovdqu a0, st0; \
+        vmovdqu a1, st1; \
+        transpose_4x4(c0, c1, c2, c3, a0, a1); \
+        transpose_4x4(d0, d1, d2, d3, a0, a1); \
+        \
+        vbroadcasti128 .Lshufb_16x16b, a0; \
+        vmovdqu st1, a1; \
+        vpshufb a0, a2, a2; \
+        vpshufb a0, a3, a3; \
+        vpshufb a0, b0, b0; \
+        vpshufb a0, b1, b1; \
+        vpshufb a0, b2, b2; \
+        vpshufb a0, b3, b3; \
+        vpshufb a0, a1, a1; \
+        vpshufb a0, c0, c0; \
+        vpshufb a0, c1, c1; \
+        vpshufb a0, c2, c2; \
+        vpshufb a0, c3, c3; \
+        vpshufb a0, d0, d0; \
+        vpshufb a0, d1, d1; \
+        vpshufb a0, d2, d2; \
+        vpshufb a0, d3, d3; \
+        vmovdqu d3, st1; \
+        vmovdqu st0, d3; \
+        vpshufb a0, d3, a0; \
+        vmovdqu d2, st0; \
+        \
+        transpose_4x4(a0, b0, c0, d0, d2, d3); \
+        transpose_4x4(a1, b1, c1, d1, d2, d3); \
+        vmovdqu st0, d2; \
+        vmovdqu st1, d3; \
+        \
+        vmovdqu b0, st0; \
+        vmovdqu b1, st1; \
+        transpose_4x4(a2, b2, c2, d2, b0, b1); \
+        transpose_4x4(a3, b3, c3, d3, b0, b1); \
+        vmovdqu st0, b0; \
+        vmovdqu st1, b1; \
+        /* does not adjust output bytes inside vectors */
+
+/* load blocks to registers and apply pre-whitening */
+#define inpack32_pre(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
+                     y6, y7, rio, key) \
+        vpbroadcastq key, x0; \
+        vpshufb .Lpack_bswap, x0, x0; \
+        \
+        vpxor 0 * 32(rio), x0, y7; \
+        vpxor 1 * 32(rio), x0, y6; \
+        vpxor 2 * 32(rio), x0, y5; \
+        vpxor 3 * 32(rio), x0, y4; \
+        vpxor 4 * 32(rio), x0, y3; \
+        vpxor 5 * 32(rio), x0, y2; \
+        vpxor 6 * 32(rio), x0, y1; \
+        vpxor 7 * 32(rio), x0, y0; \
+        vpxor 8 * 32(rio), x0, x7; \
+        vpxor 9 * 32(rio), x0, x6; \
+        vpxor 10 * 32(rio), x0, x5; \
+        vpxor 11 * 32(rio), x0, x4; \
+        vpxor 12 * 32(rio), x0, x3; \
+        vpxor 13 * 32(rio), x0, x2; \
+        vpxor 14 * 32(rio), x0, x1; \
+        vpxor 15 * 32(rio), x0, x0;
+
+/* byteslice pre-whitened blocks and store to temporary memory */
+#define inpack32_post(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
+                      y6, y7, mem_ab, mem_cd) \
+        byteslice_16x16b_fast(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, \
+                              y4, y5, y6, y7, (mem_ab), (mem_cd)); \
+        \
+        vmovdqu x0, 0 * 32(mem_ab); \
+        vmovdqu x1, 1 * 32(mem_ab); \
+        vmovdqu x2, 2 * 32(mem_ab); \
+        vmovdqu x3, 3 * 32(mem_ab); \
+        vmovdqu x4, 4 * 32(mem_ab); \
+        vmovdqu x5, 5 * 32(mem_ab); \
+        vmovdqu x6, 6 * 32(mem_ab); \
+        vmovdqu x7, 7 * 32(mem_ab); \
+        vmovdqu y0, 0 * 32(mem_cd); \
+        vmovdqu y1, 1 * 32(mem_cd); \
+        vmovdqu y2, 2 * 32(mem_cd); \
+        vmovdqu y3, 3 * 32(mem_cd); \
+        vmovdqu y4, 4 * 32(mem_cd); \
+        vmovdqu y5, 5 * 32(mem_cd); \
+        vmovdqu y6, 6 * 32(mem_cd); \
+        vmovdqu y7, 7 * 32(mem_cd);
+
+/* de-byteslice, apply post-whitening and store blocks */
+#define outunpack32(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, \
+                    y5, y6, y7, key, stack_tmp0, stack_tmp1) \
+        byteslice_16x16b_fast(y0, y4, x0, x4, y1, y5, x1, x5, y2, y6, x2, x6, \
+                              y3, y7, x3, x7, stack_tmp0, stack_tmp1); \
+        \
+        vmovdqu x0, stack_tmp0; \
+        \
+        vpbroadcastq key, x0; \
+        vpshufb .Lpack_bswap, x0, x0; \
+        \
+        vpxor x0, y7, y7; \
+        vpxor x0, y6, y6; \
+        vpxor x0, y5, y5; \
+        vpxor x0, y4, y4; \
+        vpxor x0, y3, y3; \
+        vpxor x0, y2, y2; \
+        vpxor x0, y1, y1; \
+        vpxor x0, y0, y0; \
+        vpxor x0, x7, x7; \
+        vpxor x0, x6, x6; \
+        vpxor x0, x5, x5; \
+        vpxor x0, x4, x4; \
+        vpxor x0, x3, x3; \
+        vpxor x0, x2, x2; \
+        vpxor x0, x1, x1; \
+        vpxor stack_tmp0, x0, x0;
+
+#define write_output(x0, x1, x2, x3, x4, x5, x6, x7, y0, y1, y2, y3, y4, y5, \
+                     y6, y7, rio) \
+        vmovdqu x0, 0 * 32(rio); \
+        vmovdqu x1, 1 * 32(rio); \
+        vmovdqu x2, 2 * 32(rio); \
+        vmovdqu x3, 3 * 32(rio); \
+        vmovdqu x4, 4 * 32(rio); \
+        vmovdqu x5, 5 * 32(rio); \
+        vmovdqu x6, 6 * 32(rio); \
+        vmovdqu x7, 7 * 32(rio); \
+        vmovdqu y0, 8 * 32(rio); \
+        vmovdqu y1, 9 * 32(rio); \
+        vmovdqu y2, 10 * 32(rio); \
+        vmovdqu y3, 11 * 32(rio); \
+        vmovdqu y4, 12 * 32(rio); \
+        vmovdqu y5, 13 * 32(rio); \
+        vmovdqu y6, 14 * 32(rio); \
+        vmovdqu y7, 15 * 32(rio);
+
+.data
+.align 32
+
+#define SHUFB_BYTES(idx) \
+        0 + (idx), 4 + (idx), 8 + (idx), 12 + (idx)
+
+.Lshufb_16x16b:
+        .byte SHUFB_BYTES(0), SHUFB_BYTES(1), SHUFB_BYTES(2), SHUFB_BYTES(3)
+        .byte SHUFB_BYTES(0), SHUFB_BYTES(1), SHUFB_BYTES(2), SHUFB_BYTES(3)
+
+.Lpack_bswap:
+        .long 0x00010203, 0x04050607, 0x80808080, 0x80808080
+        .long 0x00010203, 0x04050607, 0x80808080, 0x80808080
+
+/* For CTR-mode IV byteswap */
+.Lbswap128_mask:
+        .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
+
+/* For XTS mode */
+.Lxts_gf128mul_and_shl1_mask_0:
+        .byte 0x87, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0
+.Lxts_gf128mul_and_shl1_mask_1:
+        .byte 0x0e, 1, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0
+
+/*
+ * pre-SubByte transform
+ *
+ * pre-lookup for sbox1, sbox2, sbox3:
+ *   swap_bitendianness(
+ *       isom_map_camellia_to_aes(
+ *           camellia_f(
+ *               swap_bitendianess(in)
+ *           )
+ *       )
+ *   )
+ *
+ * (note: '⊕ 0xc5' inside camellia_f())
+ */
+.Lpre_tf_lo_s1:
+        .byte 0x45, 0xe8, 0x40, 0xed, 0x2e, 0x83, 0x2b, 0x86
+        .byte 0x4b, 0xe6, 0x4e, 0xe3, 0x20, 0x8d, 0x25, 0x88
+.Lpre_tf_hi_s1:
+        .byte 0x00, 0x51, 0xf1, 0xa0, 0x8a, 0xdb, 0x7b, 0x2a
+        .byte 0x09, 0x58, 0xf8, 0xa9, 0x83, 0xd2, 0x72, 0x23
+
+/*
+ * pre-SubByte transform
+ *
+ * pre-lookup for sbox4:
+ *   swap_bitendianness(
+ *       isom_map_camellia_to_aes(
+ *           camellia_f(
+ *               swap_bitendianess(in <<< 1)
+ *           )
+ *       )
+ *   )
+ *
+ * (note: '⊕ 0xc5' inside camellia_f())
+ */
+.Lpre_tf_lo_s4:
+        .byte 0x45, 0x40, 0x2e, 0x2b, 0x4b, 0x4e, 0x20, 0x25
+        .byte 0x14, 0x11, 0x7f, 0x7a, 0x1a, 0x1f, 0x71, 0x74
+.Lpre_tf_hi_s4:
+        .byte 0x00, 0xf1, 0x8a, 0x7b, 0x09, 0xf8, 0x83, 0x72
+        .byte 0xad, 0x5c, 0x27, 0xd6, 0xa4, 0x55, 0x2e, 0xdf
+
+/*
+ * post-SubByte transform
+ *
+ * post-lookup for sbox1, sbox4:
+ *  swap_bitendianness(
+ *      camellia_h(
+ *          isom_map_aes_to_camellia(
+ *              swap_bitendianness(
+ *                  aes_inverse_affine_transform(in)
+ *              )
+ *          )
+ *      )
+ *  )
+ *
+ * (note: '⊕ 0x6e' inside camellia_h())
+ */
+.Lpost_tf_lo_s1:
+        .byte 0x3c, 0xcc, 0xcf, 0x3f, 0x32, 0xc2, 0xc1, 0x31
+        .byte 0xdc, 0x2c, 0x2f, 0xdf, 0xd2, 0x22, 0x21, 0xd1
+.Lpost_tf_hi_s1:
+        .byte 0x00, 0xf9, 0x86, 0x7f, 0xd7, 0x2e, 0x51, 0xa8
+        .byte 0xa4, 0x5d, 0x22, 0xdb, 0x73, 0x8a, 0xf5, 0x0c
+
+/*
+ * post-SubByte transform
+ *
+ * post-lookup for sbox2:
+ *  swap_bitendianness(
+ *      camellia_h(
+ *          isom_map_aes_to_camellia(
+ *              swap_bitendianness(
+ *                  aes_inverse_affine_transform(in)
+ *              )
+ *          )
+ *      )
+ *  ) <<< 1
+ *
+ * (note: '⊕ 0x6e' inside camellia_h())
+ */
+.Lpost_tf_lo_s2:
+        .byte 0x78, 0x99, 0x9f, 0x7e, 0x64, 0x85, 0x83, 0x62
+        .byte 0xb9, 0x58, 0x5e, 0xbf, 0xa5, 0x44, 0x42, 0xa3
+.Lpost_tf_hi_s2:
+        .byte 0x00, 0xf3, 0x0d, 0xfe, 0xaf, 0x5c, 0xa2, 0x51
+        .byte 0x49, 0xba, 0x44, 0xb7, 0xe6, 0x15, 0xeb, 0x18
+
+/*
+ * post-SubByte transform
+ *
+ * post-lookup for sbox3:
+ *  swap_bitendianness(
+ *      camellia_h(
+ *          isom_map_aes_to_camellia(
+ *              swap_bitendianness(
+ *                  aes_inverse_affine_transform(in)
+ *              )
+ *          )
+ *      )
+ *  ) >>> 1
+ *
+ * (note: '⊕ 0x6e' inside camellia_h())
+ */
+.Lpost_tf_lo_s3:
+        .byte 0x1e, 0x66, 0xe7, 0x9f, 0x19, 0x61, 0xe0, 0x98
+        .byte 0x6e, 0x16, 0x97, 0xef, 0x69, 0x11, 0x90, 0xe8
+.Lpost_tf_hi_s3:
+        .byte 0x00, 0xfc, 0x43, 0xbf, 0xeb, 0x17, 0xa8, 0x54
+        .byte 0x52, 0xae, 0x11, 0xed, 0xb9, 0x45, 0xfa, 0x06
+
+/* For isolating SubBytes from AESENCLAST, inverse shift row */
+.Linv_shift_row:
+        .byte 0x00, 0x0d, 0x0a, 0x07, 0x04, 0x01, 0x0e, 0x0b
+        .byte 0x08, 0x05, 0x02, 0x0f, 0x0c, 0x09, 0x06, 0x03
+
+.align 4
+/* 4-bit mask */
+.L0f0f0f0f:
+        .long 0x0f0f0f0f
+
+.text
+
+.align 8
+__camellia_enc_blk32:
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rax: temporary storage, 512 bytes
+         *      %ymm0..%ymm15: 32 plaintext blocks
+         * output:
+         *      %ymm0..%ymm15: 32 encrypted blocks, order swapped:
+         *       7, 8, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8
+         */
+
+        leaq 8 * 32(%rax), %rcx;
+
+        inpack32_post(%ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+                      %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+                      %ymm15, %rax, %rcx);
+
+        enc_rounds32(%ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+                     %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+                     %ymm15, %rax, %rcx, 0);
+
+        fls32(%rax, %ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+              %rcx, %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+              %ymm15,
+              ((key_table + (8) * 8) + 0)(CTX),
+              ((key_table + (8) * 8) + 4)(CTX),
+              ((key_table + (8) * 8) + 8)(CTX),
+              ((key_table + (8) * 8) + 12)(CTX));
+
+        enc_rounds32(%ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+                     %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+                     %ymm15, %rax, %rcx, 8);
+
+        fls32(%rax, %ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+              %rcx, %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+              %ymm15,
+              ((key_table + (16) * 8) + 0)(CTX),
+              ((key_table + (16) * 8) + 4)(CTX),
+              ((key_table + (16) * 8) + 8)(CTX),
+              ((key_table + (16) * 8) + 12)(CTX));
+
+        enc_rounds32(%ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+                     %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+                     %ymm15, %rax, %rcx, 16);
+
+        movl $24, %r8d;
+        cmpl $16, key_length(CTX);
+        jne .Lenc_max32;
+
+.Lenc_done:
+        /* load CD for output */
+        vmovdqu 0 * 32(%rcx), %ymm8;
+        vmovdqu 1 * 32(%rcx), %ymm9;
+        vmovdqu 2 * 32(%rcx), %ymm10;
+        vmovdqu 3 * 32(%rcx), %ymm11;
+        vmovdqu 4 * 32(%rcx), %ymm12;
+        vmovdqu 5 * 32(%rcx), %ymm13;
+        vmovdqu 6 * 32(%rcx), %ymm14;
+        vmovdqu 7 * 32(%rcx), %ymm15;
+
+        outunpack32(%ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+                    %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+                    %ymm15, (key_table)(CTX, %r8, 8), (%rax), 1 * 32(%rax));
+
+        ret;
+
+.align 8
+.Lenc_max32:
+        movl $32, %r8d;
+
+        fls32(%rax, %ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+              %rcx, %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+              %ymm15,
+              ((key_table + (24) * 8) + 0)(CTX),
+              ((key_table + (24) * 8) + 4)(CTX),
+              ((key_table + (24) * 8) + 8)(CTX),
+              ((key_table + (24) * 8) + 12)(CTX));
+
+        enc_rounds32(%ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+                     %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+                     %ymm15, %rax, %rcx, 24);
+
+        jmp .Lenc_done;
+ENDPROC(__camellia_enc_blk32)
+
+.align 8
+__camellia_dec_blk32:
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rax: temporary storage, 512 bytes
+         *      %r8d: 24 for 16 byte key, 32 for larger
+         *      %ymm0..%ymm15: 16 encrypted blocks
+         * output:
+         *      %ymm0..%ymm15: 16 plaintext blocks, order swapped:
+         *       7, 8, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8
+         */
+
+        leaq 8 * 32(%rax), %rcx;
+
+        inpack32_post(%ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+                      %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+                      %ymm15, %rax, %rcx);
+
+        cmpl $32, %r8d;
+        je .Ldec_max32;
+
+.Ldec_max24:
+        dec_rounds32(%ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+                     %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+                     %ymm15, %rax, %rcx, 16);
+
+        fls32(%rax, %ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+              %rcx, %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+              %ymm15,
+              ((key_table + (16) * 8) + 8)(CTX),
+              ((key_table + (16) * 8) + 12)(CTX),
+              ((key_table + (16) * 8) + 0)(CTX),
+              ((key_table + (16) * 8) + 4)(CTX));
+
+        dec_rounds32(%ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+                     %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+                     %ymm15, %rax, %rcx, 8);
+
+        fls32(%rax, %ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+              %rcx, %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+              %ymm15,
+              ((key_table + (8) * 8) + 8)(CTX),
+              ((key_table + (8) * 8) + 12)(CTX),
+              ((key_table + (8) * 8) + 0)(CTX),
+              ((key_table + (8) * 8) + 4)(CTX));
+
+        dec_rounds32(%ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+                     %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+                     %ymm15, %rax, %rcx, 0);
+
+        /* load CD for output */
+        vmovdqu 0 * 32(%rcx), %ymm8;
+        vmovdqu 1 * 32(%rcx), %ymm9;
+        vmovdqu 2 * 32(%rcx), %ymm10;
+        vmovdqu 3 * 32(%rcx), %ymm11;
+        vmovdqu 4 * 32(%rcx), %ymm12;
+        vmovdqu 5 * 32(%rcx), %ymm13;
+        vmovdqu 6 * 32(%rcx), %ymm14;
+        vmovdqu 7 * 32(%rcx), %ymm15;
+
+        outunpack32(%ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+                    %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+                    %ymm15, (key_table)(CTX), (%rax), 1 * 32(%rax));
+
+        ret;
+
+.align 8
+.Ldec_max32:
+        dec_rounds32(%ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+                     %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+                     %ymm15, %rax, %rcx, 24);
+
+        fls32(%rax, %ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+              %rcx, %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+              %ymm15,
+              ((key_table + (24) * 8) + 8)(CTX),
+              ((key_table + (24) * 8) + 12)(CTX),
+              ((key_table + (24) * 8) + 0)(CTX),
+              ((key_table + (24) * 8) + 4)(CTX));
+
+        jmp .Ldec_max24;
+ENDPROC(__camellia_dec_blk32)
+
+ENTRY(camellia_ecb_enc_32way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst (32 blocks)
+         *      %rdx: src (32 blocks)
+         */
+
+        vzeroupper;
+
+        inpack32_pre(%ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+                     %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+                     %ymm15, %rdx, (key_table)(CTX));
+
+        /* now dst can be used as temporary buffer (even in src == dst case) */
+        movq    %rsi, %rax;
+
+        call __camellia_enc_blk32;
+
+        write_output(%ymm7, %ymm6, %ymm5, %ymm4, %ymm3, %ymm2, %ymm1, %ymm0,
+                     %ymm15, %ymm14, %ymm13, %ymm12, %ymm11, %ymm10, %ymm9,
+                     %ymm8, %rsi);
+
+        vzeroupper;
+
+        ret;
+ENDPROC(camellia_ecb_enc_32way)
+
+ENTRY(camellia_ecb_dec_32way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst (32 blocks)
+         *      %rdx: src (32 blocks)
+         */
+
+        vzeroupper;
+
+        cmpl $16, key_length(CTX);
+        movl $32, %r8d;
+        movl $24, %eax;
+        cmovel %eax, %r8d; /* max */
+
+        inpack32_pre(%ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+                     %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+                     %ymm15, %rdx, (key_table)(CTX, %r8, 8));
+
+        /* now dst can be used as temporary buffer (even in src == dst case) */
+        movq    %rsi, %rax;
+
+        call __camellia_dec_blk32;
+
+        write_output(%ymm7, %ymm6, %ymm5, %ymm4, %ymm3, %ymm2, %ymm1, %ymm0,
+                     %ymm15, %ymm14, %ymm13, %ymm12, %ymm11, %ymm10, %ymm9,
+                     %ymm8, %rsi);
+
+        vzeroupper;
+
+        ret;
+ENDPROC(camellia_ecb_dec_32way)
+
+ENTRY(camellia_cbc_dec_32way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst (32 blocks)
+         *      %rdx: src (32 blocks)
+         */
+
+        vzeroupper;
+
+        cmpl $16, key_length(CTX);
+        movl $32, %r8d;
+        movl $24, %eax;
+        cmovel %eax, %r8d; /* max */
+
+        inpack32_pre(%ymm0, %ymm1, %ymm2, %ymm3, %ymm4, %ymm5, %ymm6, %ymm7,
+                     %ymm8, %ymm9, %ymm10, %ymm11, %ymm12, %ymm13, %ymm14,
+                     %ymm15, %rdx, (key_table)(CTX, %r8, 8));
+
+        movq %rsp, %r10;
+        cmpq %rsi, %rdx;
+        je .Lcbc_dec_use_stack;
+
+        /* dst can be used as temporary storage, src is not overwritten. */
+        movq %rsi, %rax;
+        jmp .Lcbc_dec_continue;
+
+.Lcbc_dec_use_stack:
+        /*
+         * dst still in-use (because dst == src), so use stack for temporary
+         * storage.
+         */
+        subq $(16 * 32), %rsp;
+        movq %rsp, %rax;
+
+.Lcbc_dec_continue:
+        call __camellia_dec_blk32;
+
+        vmovdqu %ymm7, (%rax);
+        vpxor %ymm7, %ymm7, %ymm7;
+        vinserti128 $1, (%rdx), %ymm7, %ymm7;
+        vpxor (%rax), %ymm7, %ymm7;
+        movq %r10, %rsp;
+        vpxor (0 * 32 + 16)(%rdx), %ymm6, %ymm6;
+        vpxor (1 * 32 + 16)(%rdx), %ymm5, %ymm5;
+        vpxor (2 * 32 + 16)(%rdx), %ymm4, %ymm4;
+        vpxor (3 * 32 + 16)(%rdx), %ymm3, %ymm3;
+        vpxor (4 * 32 + 16)(%rdx), %ymm2, %ymm2;
+        vpxor (5 * 32 + 16)(%rdx), %ymm1, %ymm1;
+        vpxor (6 * 32 + 16)(%rdx), %ymm0, %ymm0;
+        vpxor (7 * 32 + 16)(%rdx), %ymm15, %ymm15;
+        vpxor (8 * 32 + 16)(%rdx), %ymm14, %ymm14;
+        vpxor (9 * 32 + 16)(%rdx), %ymm13, %ymm13;
+        vpxor (10 * 32 + 16)(%rdx), %ymm12, %ymm12;
+        vpxor (11 * 32 + 16)(%rdx), %ymm11, %ymm11;
+        vpxor (12 * 32 + 16)(%rdx), %ymm10, %ymm10;
+        vpxor (13 * 32 + 16)(%rdx), %ymm9, %ymm9;
+        vpxor (14 * 32 + 16)(%rdx), %ymm8, %ymm8;
+        write_output(%ymm7, %ymm6, %ymm5, %ymm4, %ymm3, %ymm2, %ymm1, %ymm0,
+                     %ymm15, %ymm14, %ymm13, %ymm12, %ymm11, %ymm10, %ymm9,
+                     %ymm8, %rsi);
+
+        vzeroupper;
+
+        ret;
+ENDPROC(camellia_cbc_dec_32way)
+
+#define inc_le128(x, minus_one, tmp) \
+        vpcmpeqq minus_one, x, tmp; \
+        vpsubq minus_one, x, x; \
+        vpslldq $8, tmp, tmp; \
+        vpsubq tmp, x, x;
+
+#define add2_le128(x, minus_one, minus_two, tmp1, tmp2) \
+        vpcmpeqq minus_one, x, tmp1; \
+        vpcmpeqq minus_two, x, tmp2; \
+        vpsubq minus_two, x, x; \
+        vpor tmp2, tmp1, tmp1; \
+        vpslldq $8, tmp1, tmp1; \
+        vpsubq tmp1, x, x;
+
+ENTRY(camellia_ctr_32way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst (32 blocks)
+         *      %rdx: src (32 blocks)
+         *      %rcx: iv (little endian, 128bit)
+         */
+
+        vzeroupper;
+
+        movq %rsp, %r10;
+        cmpq %rsi, %rdx;
+        je .Lctr_use_stack;
+
+        /* dst can be used as temporary storage, src is not overwritten. */
+        movq %rsi, %rax;
+        jmp .Lctr_continue;
+
+.Lctr_use_stack:
+        subq $(16 * 32), %rsp;
+        movq %rsp, %rax;
+
+.Lctr_continue:
+        vpcmpeqd %ymm15, %ymm15, %ymm15;
+        vpsrldq $8, %ymm15, %ymm15; /* ab: -1:0 ; cd: -1:0 */
+        vpaddq %ymm15, %ymm15, %ymm12; /* ab: -2:0 ; cd: -2:0 */
+
+        /* load IV and byteswap */
+        vmovdqu (%rcx), %xmm0;
+        vmovdqa %xmm0, %xmm1;
+        inc_le128(%xmm0, %xmm15, %xmm14);
+        vbroadcasti128 .Lbswap128_mask, %ymm14;
+        vinserti128 $1, %xmm0, %ymm1, %ymm0;
+        vpshufb %ymm14, %ymm0, %ymm13;
+        vmovdqu %ymm13, 15 * 32(%rax);
+
+        /* construct IVs */
+        add2_le128(%ymm0, %ymm15, %ymm12, %ymm11, %ymm13); /* ab:le2 ; cd:le3 */
+        vpshufb %ymm14, %ymm0, %ymm13;
+        vmovdqu %ymm13, 14 * 32(%rax);
+        add2_le128(%ymm0, %ymm15, %ymm12, %ymm11, %ymm13);
+        vpshufb %ymm14, %ymm0, %ymm13;
+        vmovdqu %ymm13, 13 * 32(%rax);
+        add2_le128(%ymm0, %ymm15, %ymm12, %ymm11, %ymm13);
+        vpshufb %ymm14, %ymm0, %ymm13;
+        vmovdqu %ymm13, 12 * 32(%rax);
+        add2_le128(%ymm0, %ymm15, %ymm12, %ymm11, %ymm13);
+        vpshufb %ymm14, %ymm0, %ymm13;
+        vmovdqu %ymm13, 11 * 32(%rax);
+        add2_le128(%ymm0, %ymm15, %ymm12, %ymm11, %ymm13);
+        vpshufb %ymm14, %ymm0, %ymm10;
+        add2_le128(%ymm0, %ymm15, %ymm12, %ymm11, %ymm13);
+        vpshufb %ymm14, %ymm0, %ymm9;
+        add2_le128(%ymm0, %ymm15, %ymm12, %ymm11, %ymm13);
+        vpshufb %ymm14, %ymm0, %ymm8;
+        add2_le128(%ymm0, %ymm15, %ymm12, %ymm11, %ymm13);
+        vpshufb %ymm14, %ymm0, %ymm7;
+        add2_le128(%ymm0, %ymm15, %ymm12, %ymm11, %ymm13);
+        vpshufb %ymm14, %ymm0, %ymm6;
+        add2_le128(%ymm0, %ymm15, %ymm12, %ymm11, %ymm13);
+        vpshufb %ymm14, %ymm0, %ymm5;
+        add2_le128(%ymm0, %ymm15, %ymm12, %ymm11, %ymm13);
+        vpshufb %ymm14, %ymm0, %ymm4;
+        add2_le128(%ymm0, %ymm15, %ymm12, %ymm11, %ymm13);
+        vpshufb %ymm14, %ymm0, %ymm3;
+        add2_le128(%ymm0, %ymm15, %ymm12, %ymm11, %ymm13);
+        vpshufb %ymm14, %ymm0, %ymm2;
+        add2_le128(%ymm0, %ymm15, %ymm12, %ymm11, %ymm13);
+        vpshufb %ymm14, %ymm0, %ymm1;
+        add2_le128(%ymm0, %ymm15, %ymm12, %ymm11, %ymm13);
+        vextracti128 $1, %ymm0, %xmm13;
+        vpshufb %ymm14, %ymm0, %ymm0;
+        inc_le128(%xmm13, %xmm15, %xmm14);
+        vmovdqu %xmm13, (%rcx);
+
+        /* inpack32_pre: */
+        vpbroadcastq (key_table)(CTX), %ymm15;
+        vpshufb .Lpack_bswap, %ymm15, %ymm15;
+        vpxor %ymm0, %ymm15, %ymm0;
+        vpxor %ymm1, %ymm15, %ymm1;
+        vpxor %ymm2, %ymm15, %ymm2;
+        vpxor %ymm3, %ymm15, %ymm3;
+        vpxor %ymm4, %ymm15, %ymm4;
+        vpxor %ymm5, %ymm15, %ymm5;
+        vpxor %ymm6, %ymm15, %ymm6;
+        vpxor %ymm7, %ymm15, %ymm7;
+        vpxor %ymm8, %ymm15, %ymm8;
+        vpxor %ymm9, %ymm15, %ymm9;
+        vpxor %ymm10, %ymm15, %ymm10;
+        vpxor 11 * 32(%rax), %ymm15, %ymm11;
+        vpxor 12 * 32(%rax), %ymm15, %ymm12;
+        vpxor 13 * 32(%rax), %ymm15, %ymm13;
+        vpxor 14 * 32(%rax), %ymm15, %ymm14;
+        vpxor 15 * 32(%rax), %ymm15, %ymm15;
+
+        call __camellia_enc_blk32;
+
+        movq %r10, %rsp;
+
+        vpxor 0 * 32(%rdx), %ymm7, %ymm7;
+        vpxor 1 * 32(%rdx), %ymm6, %ymm6;
+        vpxor 2 * 32(%rdx), %ymm5, %ymm5;
+        vpxor 3 * 32(%rdx), %ymm4, %ymm4;
+        vpxor 4 * 32(%rdx), %ymm3, %ymm3;
+        vpxor 5 * 32(%rdx), %ymm2, %ymm2;
+        vpxor 6 * 32(%rdx), %ymm1, %ymm1;
+        vpxor 7 * 32(%rdx), %ymm0, %ymm0;
+        vpxor 8 * 32(%rdx), %ymm15, %ymm15;
+        vpxor 9 * 32(%rdx), %ymm14, %ymm14;
+        vpxor 10 * 32(%rdx), %ymm13, %ymm13;
+        vpxor 11 * 32(%rdx), %ymm12, %ymm12;
+        vpxor 12 * 32(%rdx), %ymm11, %ymm11;
+        vpxor 13 * 32(%rdx), %ymm10, %ymm10;
+        vpxor 14 * 32(%rdx), %ymm9, %ymm9;
+        vpxor 15 * 32(%rdx), %ymm8, %ymm8;
+        write_output(%ymm7, %ymm6, %ymm5, %ymm4, %ymm3, %ymm2, %ymm1, %ymm0,
+                     %ymm15, %ymm14, %ymm13, %ymm12, %ymm11, %ymm10, %ymm9,
+                     %ymm8, %rsi);
+
+        vzeroupper;
+
+        ret;
+ENDPROC(camellia_ctr_32way)
+
+#define gf128mul_x_ble(iv, mask, tmp) \
+        vpsrad $31, iv, tmp; \
+        vpaddq iv, iv, iv; \
+        vpshufd $0x13, tmp, tmp; \
+        vpand mask, tmp, tmp; \
+        vpxor tmp, iv, iv;
+
+#define gf128mul_x2_ble(iv, mask1, mask2, tmp0, tmp1) \
+        vpsrad $31, iv, tmp0; \
+        vpaddq iv, iv, tmp1; \
+        vpsllq $2, iv, iv; \
+        vpshufd $0x13, tmp0, tmp0; \
+        vpsrad $31, tmp1, tmp1; \
+        vpand mask2, tmp0, tmp0; \
+        vpshufd $0x13, tmp1, tmp1; \
+        vpxor tmp0, iv, iv; \
+        vpand mask1, tmp1, tmp1; \
+        vpxor tmp1, iv, iv;
+
+.align 8
+camellia_xts_crypt_32way:
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst (32 blocks)
+         *      %rdx: src (32 blocks)
+         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
+         *      %r8: index for input whitening key
+         *      %r9: pointer to  __camellia_enc_blk32 or __camellia_dec_blk32
+         */
+
+        vzeroupper;
+
+        subq $(16 * 32), %rsp;
+        movq %rsp, %rax;
+
+        vbroadcasti128 .Lxts_gf128mul_and_shl1_mask_0, %ymm12;
+
+        /* load IV and construct second IV */
+        vmovdqu (%rcx), %xmm0;
+        vmovdqa %xmm0, %xmm15;
+        gf128mul_x_ble(%xmm0, %xmm12, %xmm13);
+        vbroadcasti128 .Lxts_gf128mul_and_shl1_mask_1, %ymm13;
+        vinserti128 $1, %xmm0, %ymm15, %ymm0;
+        vpxor 0 * 32(%rdx), %ymm0, %ymm15;
+        vmovdqu %ymm15, 15 * 32(%rax);
+        vmovdqu %ymm0, 0 * 32(%rsi);
+
+        /* construct IVs */
+        gf128mul_x2_ble(%ymm0, %ymm12, %ymm13, %ymm14, %ymm15);
+        vpxor 1 * 32(%rdx), %ymm0, %ymm15;
+        vmovdqu %ymm15, 14 * 32(%rax);
+        vmovdqu %ymm0, 1 * 32(%rsi);
+
+        gf128mul_x2_ble(%ymm0, %ymm12, %ymm13, %ymm14, %ymm15);
+        vpxor 2 * 32(%rdx), %ymm0, %ymm15;
+        vmovdqu %ymm15, 13 * 32(%rax);
+        vmovdqu %ymm0, 2 * 32(%rsi);
+
+        gf128mul_x2_ble(%ymm0, %ymm12, %ymm13, %ymm14, %ymm15);
+        vpxor 3 * 32(%rdx), %ymm0, %ymm15;
+        vmovdqu %ymm15, 12 * 32(%rax);
+        vmovdqu %ymm0, 3 * 32(%rsi);
+
+        gf128mul_x2_ble(%ymm0, %ymm12, %ymm13, %ymm14, %ymm15);
+        vpxor 4 * 32(%rdx), %ymm0, %ymm11;
+        vmovdqu %ymm0, 4 * 32(%rsi);
+
+        gf128mul_x2_ble(%ymm0, %ymm12, %ymm13, %ymm14, %ymm15);
+        vpxor 5 * 32(%rdx), %ymm0, %ymm10;
+        vmovdqu %ymm0, 5 * 32(%rsi);
+
+        gf128mul_x2_ble(%ymm0, %ymm12, %ymm13, %ymm14, %ymm15);
+        vpxor 6 * 32(%rdx), %ymm0, %ymm9;
+        vmovdqu %ymm0, 6 * 32(%rsi);
+
+        gf128mul_x2_ble(%ymm0, %ymm12, %ymm13, %ymm14, %ymm15);
+        vpxor 7 * 32(%rdx), %ymm0, %ymm8;
+        vmovdqu %ymm0, 7 * 32(%rsi);
+
+        gf128mul_x2_ble(%ymm0, %ymm12, %ymm13, %ymm14, %ymm15);
+        vpxor 8 * 32(%rdx), %ymm0, %ymm7;
+        vmovdqu %ymm0, 8 * 32(%rsi);
+
+        gf128mul_x2_ble(%ymm0, %ymm12, %ymm13, %ymm14, %ymm15);
+        vpxor 9 * 32(%rdx), %ymm0, %ymm6;
+        vmovdqu %ymm0, 9 * 32(%rsi);
+
+        gf128mul_x2_ble(%ymm0, %ymm12, %ymm13, %ymm14, %ymm15);
+        vpxor 10 * 32(%rdx), %ymm0, %ymm5;
+        vmovdqu %ymm0, 10 * 32(%rsi);
+
+        gf128mul_x2_ble(%ymm0, %ymm12, %ymm13, %ymm14, %ymm15);
+        vpxor 11 * 32(%rdx), %ymm0, %ymm4;
+        vmovdqu %ymm0, 11 * 32(%rsi);
+
+        gf128mul_x2_ble(%ymm0, %ymm12, %ymm13, %ymm14, %ymm15);
+        vpxor 12 * 32(%rdx), %ymm0, %ymm3;
+        vmovdqu %ymm0, 12 * 32(%rsi);
+
+        gf128mul_x2_ble(%ymm0, %ymm12, %ymm13, %ymm14, %ymm15);
+        vpxor 13 * 32(%rdx), %ymm0, %ymm2;
+        vmovdqu %ymm0, 13 * 32(%rsi);
+
+        gf128mul_x2_ble(%ymm0, %ymm12, %ymm13, %ymm14, %ymm15);
+        vpxor 14 * 32(%rdx), %ymm0, %ymm1;
+        vmovdqu %ymm0, 14 * 32(%rsi);
+
+        gf128mul_x2_ble(%ymm0, %ymm12, %ymm13, %ymm14, %ymm15);
+        vpxor 15 * 32(%rdx), %ymm0, %ymm15;
+        vmovdqu %ymm15, 0 * 32(%rax);
+        vmovdqu %ymm0, 15 * 32(%rsi);
+
+        vextracti128 $1, %ymm0, %xmm0;
+        gf128mul_x_ble(%xmm0, %xmm12, %xmm15);
+        vmovdqu %xmm0, (%rcx);
+
+        /* inpack32_pre: */
+        vpbroadcastq (key_table)(CTX, %r8, 8), %ymm15;
+        vpshufb .Lpack_bswap, %ymm15, %ymm15;
+        vpxor 0 * 32(%rax), %ymm15, %ymm0;
+        vpxor %ymm1, %ymm15, %ymm1;
+        vpxor %ymm2, %ymm15, %ymm2;
+        vpxor %ymm3, %ymm15, %ymm3;
+        vpxor %ymm4, %ymm15, %ymm4;
+        vpxor %ymm5, %ymm15, %ymm5;
+        vpxor %ymm6, %ymm15, %ymm6;
+        vpxor %ymm7, %ymm15, %ymm7;
+        vpxor %ymm8, %ymm15, %ymm8;
+        vpxor %ymm9, %ymm15, %ymm9;
+        vpxor %ymm10, %ymm15, %ymm10;
+        vpxor %ymm11, %ymm15, %ymm11;
+        vpxor 12 * 32(%rax), %ymm15, %ymm12;
+        vpxor 13 * 32(%rax), %ymm15, %ymm13;
+        vpxor 14 * 32(%rax), %ymm15, %ymm14;
+        vpxor 15 * 32(%rax), %ymm15, %ymm15;
+
+        call *%r9;
+
+        addq $(16 * 32), %rsp;
+
+        vpxor 0 * 32(%rsi), %ymm7, %ymm7;
+        vpxor 1 * 32(%rsi), %ymm6, %ymm6;
+        vpxor 2 * 32(%rsi), %ymm5, %ymm5;
+        vpxor 3 * 32(%rsi), %ymm4, %ymm4;
+        vpxor 4 * 32(%rsi), %ymm3, %ymm3;
+        vpxor 5 * 32(%rsi), %ymm2, %ymm2;
+        vpxor 6 * 32(%rsi), %ymm1, %ymm1;
+        vpxor 7 * 32(%rsi), %ymm0, %ymm0;
+        vpxor 8 * 32(%rsi), %ymm15, %ymm15;
+        vpxor 9 * 32(%rsi), %ymm14, %ymm14;
+        vpxor 10 * 32(%rsi), %ymm13, %ymm13;
+        vpxor 11 * 32(%rsi), %ymm12, %ymm12;
+        vpxor 12 * 32(%rsi), %ymm11, %ymm11;
+        vpxor 13 * 32(%rsi), %ymm10, %ymm10;
+        vpxor 14 * 32(%rsi), %ymm9, %ymm9;
+        vpxor 15 * 32(%rsi), %ymm8, %ymm8;
+        write_output(%ymm7, %ymm6, %ymm5, %ymm4, %ymm3, %ymm2, %ymm1, %ymm0,
+                     %ymm15, %ymm14, %ymm13, %ymm12, %ymm11, %ymm10, %ymm9,
+                     %ymm8, %rsi);
+
+        vzeroupper;
+
+        ret;
+ENDPROC(camellia_xts_crypt_32way)
+
+ENTRY(camellia_xts_enc_32way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst (32 blocks)
+         *      %rdx: src (32 blocks)
+         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
+         */
+
+        xorl %r8d, %r8d; /* input whitening key, 0 for enc */
+
+        leaq __camellia_enc_blk32, %r9;
+
+        jmp camellia_xts_crypt_32way;
+ENDPROC(camellia_xts_enc_32way)
+
+ENTRY(camellia_xts_dec_32way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst (32 blocks)
+         *      %rdx: src (32 blocks)
+         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
+         */
+
+        cmpl $16, key_length(CTX);
+        movl $32, %r8d;
+        movl $24, %eax;
+        cmovel %eax, %r8d;  /* input whitening key, last for dec */
+
+        leaq __camellia_dec_blk32, %r9;
+
+        jmp camellia_xts_crypt_32way;
+ENDPROC(camellia_xts_dec_32way)
diff --git a/arch/x86/crypto/camellia_aesni_avx2_glue.c b/arch/x86/crypto/camellia_aesni_avx2_glue.c
new file mode 100644
index 000000000000..414fe5d7946b
--- /dev/null
+++ b/arch/x86/crypto/camellia_aesni_avx2_glue.c
@@ -0,0 +1,586 @@
+/*
+ * Glue Code for x86_64/AVX2/AES-NI assembler optimized version of Camellia
+ *
+ * Copyright © 2013 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/crypto.h>
+#include <linux/err.h>
+#include <crypto/algapi.h>
+#include <crypto/ctr.h>
+#include <crypto/lrw.h>
+#include <crypto/xts.h>
+#include <asm/xcr.h>
+#include <asm/xsave.h>
+#include <asm/crypto/camellia.h>
+#include <asm/crypto/ablk_helper.h>
+#include <asm/crypto/glue_helper.h>
+
+#define CAMELLIA_AESNI_PARALLEL_BLOCKS 16
+#define CAMELLIA_AESNI_AVX2_PARALLEL_BLOCKS 32
+
+/* 32-way AVX2/AES-NI parallel cipher functions */
+asmlinkage void camellia_ecb_enc_32way(struct camellia_ctx *ctx, u8 *dst,
+                                       const u8 *src);
+asmlinkage void camellia_ecb_dec_32way(struct camellia_ctx *ctx, u8 *dst,
+                                       const u8 *src);
+
+asmlinkage void camellia_cbc_dec_32way(struct camellia_ctx *ctx, u8 *dst,
+                                       const u8 *src);
+asmlinkage void camellia_ctr_32way(struct camellia_ctx *ctx, u8 *dst,
+                                   const u8 *src, le128 *iv);
+
+asmlinkage void camellia_xts_enc_32way(struct camellia_ctx *ctx, u8 *dst,
+                                       const u8 *src, le128 *iv);
+asmlinkage void camellia_xts_dec_32way(struct camellia_ctx *ctx, u8 *dst,
+                                       const u8 *src, le128 *iv);
+
+static const struct common_glue_ctx camellia_enc = {
+        .num_funcs = 4,
+        .fpu_blocks_limit = CAMELLIA_AESNI_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = CAMELLIA_AESNI_AVX2_PARALLEL_BLOCKS,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(camellia_ecb_enc_32way) }
+        }, {
+                .num_blocks = CAMELLIA_AESNI_PARALLEL_BLOCKS,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(camellia_ecb_enc_16way) }
+        }, {
+                .num_blocks = 2,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(camellia_enc_blk_2way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(camellia_enc_blk) }
+        } }
+};
+
+static const struct common_glue_ctx camellia_ctr = {
+        .num_funcs = 4,
+        .fpu_blocks_limit = CAMELLIA_AESNI_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = CAMELLIA_AESNI_AVX2_PARALLEL_BLOCKS,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(camellia_ctr_32way) }
+        }, {
+                .num_blocks = CAMELLIA_AESNI_PARALLEL_BLOCKS,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(camellia_ctr_16way) }
+        }, {
+                .num_blocks = 2,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(camellia_crypt_ctr_2way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(camellia_crypt_ctr) }
+        } }
+};
+
+static const struct common_glue_ctx camellia_enc_xts = {
+        .num_funcs = 3,
+        .fpu_blocks_limit = CAMELLIA_AESNI_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = CAMELLIA_AESNI_AVX2_PARALLEL_BLOCKS,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(camellia_xts_enc_32way) }
+        }, {
+                .num_blocks = CAMELLIA_AESNI_PARALLEL_BLOCKS,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(camellia_xts_enc_16way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(camellia_xts_enc) }
+        } }
+};
+
+static const struct common_glue_ctx camellia_dec = {
+        .num_funcs = 4,
+        .fpu_blocks_limit = CAMELLIA_AESNI_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = CAMELLIA_AESNI_AVX2_PARALLEL_BLOCKS,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(camellia_ecb_dec_32way) }
+        }, {
+                .num_blocks = CAMELLIA_AESNI_PARALLEL_BLOCKS,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(camellia_ecb_dec_16way) }
+        }, {
+                .num_blocks = 2,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(camellia_dec_blk_2way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(camellia_dec_blk) }
+        } }
+};
+
+static const struct common_glue_ctx camellia_dec_cbc = {
+        .num_funcs = 4,
+        .fpu_blocks_limit = CAMELLIA_AESNI_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = CAMELLIA_AESNI_AVX2_PARALLEL_BLOCKS,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(camellia_cbc_dec_32way) }
+        }, {
+                .num_blocks = CAMELLIA_AESNI_PARALLEL_BLOCKS,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(camellia_cbc_dec_16way) }
+        }, {
+                .num_blocks = 2,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(camellia_decrypt_cbc_2way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(camellia_dec_blk) }
+        } }
+};
+
+static const struct common_glue_ctx camellia_dec_xts = {
+        .num_funcs = 3,
+        .fpu_blocks_limit = CAMELLIA_AESNI_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = CAMELLIA_AESNI_AVX2_PARALLEL_BLOCKS,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(camellia_xts_dec_32way) }
+        }, {
+                .num_blocks = CAMELLIA_AESNI_PARALLEL_BLOCKS,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(camellia_xts_dec_16way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(camellia_xts_dec) }
+        } }
+};
+
+static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_ecb_crypt_128bit(&camellia_enc, desc, dst, src, nbytes);
+}
+
+static int ecb_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_ecb_crypt_128bit(&camellia_dec, desc, dst, src, nbytes);
+}
+
+static int cbc_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_cbc_encrypt_128bit(GLUE_FUNC_CAST(camellia_enc_blk), desc,
+                                       dst, src, nbytes);
+}
+
+static int cbc_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_cbc_decrypt_128bit(&camellia_dec_cbc, desc, dst, src,
+                                       nbytes);
+}
+
+static int ctr_crypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                     struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_ctr_crypt_128bit(&camellia_ctr, desc, dst, src, nbytes);
+}
+
+static inline bool camellia_fpu_begin(bool fpu_enabled, unsigned int nbytes)
+{
+        return glue_fpu_begin(CAMELLIA_BLOCK_SIZE,
+                              CAMELLIA_AESNI_PARALLEL_BLOCKS, NULL, fpu_enabled,
+                              nbytes);
+}
+
+static inline void camellia_fpu_end(bool fpu_enabled)
+{
+        glue_fpu_end(fpu_enabled);
+}
+
+static int camellia_setkey(struct crypto_tfm *tfm, const u8 *in_key,
+                           unsigned int key_len)
+{
+        return __camellia_setkey(crypto_tfm_ctx(tfm), in_key, key_len,
+                                 &tfm->crt_flags);
+}
+
+struct crypt_priv {
+        struct camellia_ctx *ctx;
+        bool fpu_enabled;
+};
+
+static void encrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
+{
+        const unsigned int bsize = CAMELLIA_BLOCK_SIZE;
+        struct crypt_priv *ctx = priv;
+        int i;
+
+        ctx->fpu_enabled = camellia_fpu_begin(ctx->fpu_enabled, nbytes);
+
+        if (nbytes >= CAMELLIA_AESNI_AVX2_PARALLEL_BLOCKS * bsize) {
+                camellia_ecb_enc_32way(ctx->ctx, srcdst, srcdst);
+                srcdst += bsize * CAMELLIA_AESNI_AVX2_PARALLEL_BLOCKS;
+                nbytes -= bsize * CAMELLIA_AESNI_AVX2_PARALLEL_BLOCKS;
+        }
+
+        if (nbytes >= CAMELLIA_AESNI_PARALLEL_BLOCKS * bsize) {
+                camellia_ecb_enc_16way(ctx->ctx, srcdst, srcdst);
+                srcdst += bsize * CAMELLIA_AESNI_PARALLEL_BLOCKS;
+                nbytes -= bsize * CAMELLIA_AESNI_PARALLEL_BLOCKS;
+        }
+
+        while (nbytes >= CAMELLIA_PARALLEL_BLOCKS * bsize) {
+                camellia_enc_blk_2way(ctx->ctx, srcdst, srcdst);
+                srcdst += bsize * CAMELLIA_PARALLEL_BLOCKS;
+                nbytes -= bsize * CAMELLIA_PARALLEL_BLOCKS;
+        }
+
+        for (i = 0; i < nbytes / bsize; i++, srcdst += bsize)
+                camellia_enc_blk(ctx->ctx, srcdst, srcdst);
+}
+
+static void decrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
+{
+        const unsigned int bsize = CAMELLIA_BLOCK_SIZE;
+        struct crypt_priv *ctx = priv;
+        int i;
+
+        ctx->fpu_enabled = camellia_fpu_begin(ctx->fpu_enabled, nbytes);
+
+        if (nbytes >= CAMELLIA_AESNI_AVX2_PARALLEL_BLOCKS * bsize) {
+                camellia_ecb_dec_32way(ctx->ctx, srcdst, srcdst);
+                srcdst += bsize * CAMELLIA_AESNI_AVX2_PARALLEL_BLOCKS;
+                nbytes -= bsize * CAMELLIA_AESNI_AVX2_PARALLEL_BLOCKS;
+        }
+
+        if (nbytes >= CAMELLIA_AESNI_PARALLEL_BLOCKS * bsize) {
+                camellia_ecb_dec_16way(ctx->ctx, srcdst, srcdst);
+                srcdst += bsize * CAMELLIA_AESNI_PARALLEL_BLOCKS;
+                nbytes -= bsize * CAMELLIA_AESNI_PARALLEL_BLOCKS;
+        }
+
+        while (nbytes >= CAMELLIA_PARALLEL_BLOCKS * bsize) {
+                camellia_dec_blk_2way(ctx->ctx, srcdst, srcdst);
+                srcdst += bsize * CAMELLIA_PARALLEL_BLOCKS;
+                nbytes -= bsize * CAMELLIA_PARALLEL_BLOCKS;
+        }
+
+        for (i = 0; i < nbytes / bsize; i++, srcdst += bsize)
+                camellia_dec_blk(ctx->ctx, srcdst, srcdst);
+}
+
+static int lrw_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct camellia_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+        be128 buf[CAMELLIA_AESNI_AVX2_PARALLEL_BLOCKS];
+        struct crypt_priv crypt_ctx = {
+                .ctx = &ctx->camellia_ctx,
+                .fpu_enabled = false,
+        };
+        struct lrw_crypt_req req = {
+                .tbuf = buf,
+                .tbuflen = sizeof(buf),
+
+                .table_ctx = &ctx->lrw_table,
+                .crypt_ctx = &crypt_ctx,
+                .crypt_fn = encrypt_callback,
+        };
+        int ret;
+
+        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
+        ret = lrw_crypt(desc, dst, src, nbytes, &req);
+        camellia_fpu_end(crypt_ctx.fpu_enabled);
+
+        return ret;
+}
+
+static int lrw_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct camellia_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+        be128 buf[CAMELLIA_AESNI_AVX2_PARALLEL_BLOCKS];
+        struct crypt_priv crypt_ctx = {
+                .ctx = &ctx->camellia_ctx,
+                .fpu_enabled = false,
+        };
+        struct lrw_crypt_req req = {
+                .tbuf = buf,
+                .tbuflen = sizeof(buf),
+
+                .table_ctx = &ctx->lrw_table,
+                .crypt_ctx = &crypt_ctx,
+                .crypt_fn = decrypt_callback,
+        };
+        int ret;
+
+        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
+        ret = lrw_crypt(desc, dst, src, nbytes, &req);
+        camellia_fpu_end(crypt_ctx.fpu_enabled);
+
+        return ret;
+}
+
+static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct camellia_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+
+        return glue_xts_crypt_128bit(&camellia_enc_xts, desc, dst, src, nbytes,
+                                     XTS_TWEAK_CAST(camellia_enc_blk),
+                                     &ctx->tweak_ctx, &ctx->crypt_ctx);
+}
+
+static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct camellia_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+
+        return glue_xts_crypt_128bit(&camellia_dec_xts, desc, dst, src, nbytes,
+                                     XTS_TWEAK_CAST(camellia_enc_blk),
+                                     &ctx->tweak_ctx, &ctx->crypt_ctx);
+}
+
+static struct crypto_alg cmll_algs[10] = { {
+        .cra_name               = "__ecb-camellia-aesni-avx2",
+        .cra_driver_name        = "__driver-ecb-camellia-aesni-avx2",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = CAMELLIA_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct camellia_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = CAMELLIA_MIN_KEY_SIZE,
+                        .max_keysize    = CAMELLIA_MAX_KEY_SIZE,
+                        .setkey         = camellia_setkey,
+                        .encrypt        = ecb_encrypt,
+                        .decrypt        = ecb_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "__cbc-camellia-aesni-avx2",
+        .cra_driver_name        = "__driver-cbc-camellia-aesni-avx2",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = CAMELLIA_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct camellia_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = CAMELLIA_MIN_KEY_SIZE,
+                        .max_keysize    = CAMELLIA_MAX_KEY_SIZE,
+                        .setkey         = camellia_setkey,
+                        .encrypt        = cbc_encrypt,
+                        .decrypt        = cbc_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "__ctr-camellia-aesni-avx2",
+        .cra_driver_name        = "__driver-ctr-camellia-aesni-avx2",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = 1,
+        .cra_ctxsize            = sizeof(struct camellia_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = CAMELLIA_MIN_KEY_SIZE,
+                        .max_keysize    = CAMELLIA_MAX_KEY_SIZE,
+                        .ivsize         = CAMELLIA_BLOCK_SIZE,
+                        .setkey         = camellia_setkey,
+                        .encrypt        = ctr_crypt,
+                        .decrypt        = ctr_crypt,
+                },
+        },
+}, {
+        .cra_name               = "__lrw-camellia-aesni-avx2",
+        .cra_driver_name        = "__driver-lrw-camellia-aesni-avx2",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = CAMELLIA_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct camellia_lrw_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_exit               = lrw_camellia_exit_tfm,
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = CAMELLIA_MIN_KEY_SIZE +
+                                          CAMELLIA_BLOCK_SIZE,
+                        .max_keysize    = CAMELLIA_MAX_KEY_SIZE +
+                                          CAMELLIA_BLOCK_SIZE,
+                        .ivsize         = CAMELLIA_BLOCK_SIZE,
+                        .setkey         = lrw_camellia_setkey,
+                        .encrypt        = lrw_encrypt,
+                        .decrypt        = lrw_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "__xts-camellia-aesni-avx2",
+        .cra_driver_name        = "__driver-xts-camellia-aesni-avx2",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = CAMELLIA_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct camellia_xts_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = CAMELLIA_MIN_KEY_SIZE * 2,
+                        .max_keysize    = CAMELLIA_MAX_KEY_SIZE * 2,
+                        .ivsize         = CAMELLIA_BLOCK_SIZE,
+                        .setkey         = xts_camellia_setkey,
+                        .encrypt        = xts_encrypt,
+                        .decrypt        = xts_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "ecb(camellia)",
+        .cra_driver_name        = "ecb-camellia-aesni-avx2",
+        .cra_priority           = 500,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = CAMELLIA_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = CAMELLIA_MIN_KEY_SIZE,
+                        .max_keysize    = CAMELLIA_MAX_KEY_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "cbc(camellia)",
+        .cra_driver_name        = "cbc-camellia-aesni-avx2",
+        .cra_priority           = 500,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = CAMELLIA_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = CAMELLIA_MIN_KEY_SIZE,
+                        .max_keysize    = CAMELLIA_MAX_KEY_SIZE,
+                        .ivsize         = CAMELLIA_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = __ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "ctr(camellia)",
+        .cra_driver_name        = "ctr-camellia-aesni-avx2",
+        .cra_priority           = 500,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = 1,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = CAMELLIA_MIN_KEY_SIZE,
+                        .max_keysize    = CAMELLIA_MAX_KEY_SIZE,
+                        .ivsize         = CAMELLIA_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_encrypt,
+                        .geniv          = "chainiv",
+                },
+        },
+}, {
+        .cra_name               = "lrw(camellia)",
+        .cra_driver_name        = "lrw-camellia-aesni-avx2",
+        .cra_priority           = 500,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = CAMELLIA_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = CAMELLIA_MIN_KEY_SIZE +
+                                          CAMELLIA_BLOCK_SIZE,
+                        .max_keysize    = CAMELLIA_MAX_KEY_SIZE +
+                                          CAMELLIA_BLOCK_SIZE,
+                        .ivsize         = CAMELLIA_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "xts(camellia)",
+        .cra_driver_name        = "xts-camellia-aesni-avx2",
+        .cra_priority           = 500,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = CAMELLIA_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = CAMELLIA_MIN_KEY_SIZE * 2,
+                        .max_keysize    = CAMELLIA_MAX_KEY_SIZE * 2,
+                        .ivsize         = CAMELLIA_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+} };
+
+static int __init camellia_aesni_init(void)
+{
+        u64 xcr0;
+
+        if (!cpu_has_avx2 || !cpu_has_avx || !cpu_has_aes || !cpu_has_osxsave) {
+                pr_info("AVX2 or AES-NI instructions are not detected.\n");
+                return -ENODEV;
+        }
+
+        xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
+        if ((xcr0 & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM)) {
+                pr_info("AVX2 detected but unusable.\n");
+                return -ENODEV;
+        }
+
+        return crypto_register_algs(cmll_algs, ARRAY_SIZE(cmll_algs));
+}
+
+static void __exit camellia_aesni_fini(void)
+{
+        crypto_unregister_algs(cmll_algs, ARRAY_SIZE(cmll_algs));
+}
+
+module_init(camellia_aesni_init);
+module_exit(camellia_aesni_fini);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Camellia Cipher Algorithm, AES-NI/AVX2 optimized");
+MODULE_ALIAS("camellia");
+MODULE_ALIAS("camellia-asm");
diff --git a/arch/x86/crypto/camellia_aesni_avx_glue.c b/arch/x86/crypto/camellia_aesni_avx_glue.c
index 96cbb6068fce..37fd0c0a81ea 100644
--- a/arch/x86/crypto/camellia_aesni_avx_glue.c
+++ b/arch/x86/crypto/camellia_aesni_avx_glue.c
@@ -1,7 +1,7 @@
 /*
  * Glue Code for x86_64/AVX/AES-NI assembler optimized version of Camellia
  *
- * Copyright © 2012 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
+ * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -26,16 +26,44 @@
 
 #define CAMELLIA_AESNI_PARALLEL_BLOCKS 16
 
-/* 16-way AES-NI parallel cipher functions */
+/* 16-way parallel cipher functions (avx/aes-ni) */
 asmlinkage void camellia_ecb_enc_16way(struct camellia_ctx *ctx, u8 *dst,
                                        const u8 *src);
+EXPORT_SYMBOL_GPL(camellia_ecb_enc_16way);
+
 asmlinkage void camellia_ecb_dec_16way(struct camellia_ctx *ctx, u8 *dst,
                                        const u8 *src);
+EXPORT_SYMBOL_GPL(camellia_ecb_dec_16way);
 
 asmlinkage void camellia_cbc_dec_16way(struct camellia_ctx *ctx, u8 *dst,
                                        const u8 *src);
+EXPORT_SYMBOL_GPL(camellia_cbc_dec_16way);
+
 asmlinkage void camellia_ctr_16way(struct camellia_ctx *ctx, u8 *dst,
                                    const u8 *src, le128 *iv);
+EXPORT_SYMBOL_GPL(camellia_ctr_16way);
+
+asmlinkage void camellia_xts_enc_16way(struct camellia_ctx *ctx, u8 *dst,
+                                       const u8 *src, le128 *iv);
+EXPORT_SYMBOL_GPL(camellia_xts_enc_16way);
+
+asmlinkage void camellia_xts_dec_16way(struct camellia_ctx *ctx, u8 *dst,
+                                       const u8 *src, le128 *iv);
+EXPORT_SYMBOL_GPL(camellia_xts_dec_16way);
+
+void camellia_xts_enc(void *ctx, u128 *dst, const u128 *src, le128 *iv)
+{
+        glue_xts_crypt_128bit_one(ctx, dst, src, iv,
+                                  GLUE_FUNC_CAST(camellia_enc_blk));
+}
+EXPORT_SYMBOL_GPL(camellia_xts_enc);
+
+void camellia_xts_dec(void *ctx, u128 *dst, const u128 *src, le128 *iv)
+{
+        glue_xts_crypt_128bit_one(ctx, dst, src, iv,
+                                  GLUE_FUNC_CAST(camellia_dec_blk));
+}
+EXPORT_SYMBOL_GPL(camellia_xts_dec);
 
 static const struct common_glue_ctx camellia_enc = {
         .num_funcs = 3,
@@ -69,6 +97,19 @@ static const struct common_glue_ctx camellia_ctr = {
         } }
 };
 
+static const struct common_glue_ctx camellia_enc_xts = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = CAMELLIA_AESNI_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = CAMELLIA_AESNI_PARALLEL_BLOCKS,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(camellia_xts_enc_16way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(camellia_xts_enc) }
+        } }
+};
+
 static const struct common_glue_ctx camellia_dec = {
         .num_funcs = 3,
         .fpu_blocks_limit = CAMELLIA_AESNI_PARALLEL_BLOCKS,
@@ -101,6 +142,19 @@ static const struct common_glue_ctx camellia_dec_cbc = {
         } }
 };
 
+static const struct common_glue_ctx camellia_dec_xts = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = CAMELLIA_AESNI_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = CAMELLIA_AESNI_PARALLEL_BLOCKS,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(camellia_xts_dec_16way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(camellia_xts_dec) }
+        } }
+};
+
 static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
                        struct scatterlist *src, unsigned int nbytes)
 {
@@ -261,54 +315,20 @@ static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
                        struct scatterlist *src, unsigned int nbytes)
 {
         struct camellia_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        be128 buf[CAMELLIA_AESNI_PARALLEL_BLOCKS];
-        struct crypt_priv crypt_ctx = {
-                .ctx = &ctx->crypt_ctx,
-                .fpu_enabled = false,
-        };
-        struct xts_crypt_req req = {
-                .tbuf = buf,
-                .tbuflen = sizeof(buf),
 
-                .tweak_ctx = &ctx->tweak_ctx,
-                .tweak_fn = XTS_TWEAK_CAST(camellia_enc_blk),
-                .crypt_ctx = &crypt_ctx,
-                .crypt_fn = encrypt_callback,
-        };
-        int ret;
-
-        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
-        ret = xts_crypt(desc, dst, src, nbytes, &req);
-        camellia_fpu_end(crypt_ctx.fpu_enabled);
-
-        return ret;
+        return glue_xts_crypt_128bit(&camellia_enc_xts, desc, dst, src, nbytes,
+                                     XTS_TWEAK_CAST(camellia_enc_blk),
+                                     &ctx->tweak_ctx, &ctx->crypt_ctx);
 }
 
 static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
                        struct scatterlist *src, unsigned int nbytes)
 {
         struct camellia_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        be128 buf[CAMELLIA_AESNI_PARALLEL_BLOCKS];
-        struct crypt_priv crypt_ctx = {
-                .ctx = &ctx->crypt_ctx,
-                .fpu_enabled = false,
-        };
-        struct xts_crypt_req req = {
-                .tbuf = buf,
-                .tbuflen = sizeof(buf),
-
-                .tweak_ctx = &ctx->tweak_ctx,
-                .tweak_fn = XTS_TWEAK_CAST(camellia_enc_blk),
-                .crypt_ctx = &crypt_ctx,
-                .crypt_fn = decrypt_callback,
-        };
-        int ret;
 
-        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
-        ret = xts_crypt(desc, dst, src, nbytes, &req);
-        camellia_fpu_end(crypt_ctx.fpu_enabled);
-
-        return ret;
+        return glue_xts_crypt_128bit(&camellia_dec_xts, desc, dst, src, nbytes,
+                                     XTS_TWEAK_CAST(camellia_enc_blk),
+                                     &ctx->tweak_ctx, &ctx->crypt_ctx);
 }
 
 static struct crypto_alg cmll_algs[10] = { {
diff --git a/arch/x86/crypto/cast6-avx-x86_64-asm_64.S b/arch/x86/crypto/cast6-avx-x86_64-asm_64.S
index f93b6105a0ce..e3531f833951 100644
--- a/arch/x86/crypto/cast6-avx-x86_64-asm_64.S
+++ b/arch/x86/crypto/cast6-avx-x86_64-asm_64.S
@@ -4,7 +4,7 @@
  * Copyright (C) 2012 Johannes Goetzfried
  *     <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
  *
- * Copyright © 2012 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
+ * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -227,6 +227,8 @@
 .data
 
 .align 16
+.Lxts_gf128mul_and_shl1_mask:
+        .byte 0x87, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0
 .Lbswap_mask:
         .byte 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12
 .Lbswap128_mask:
@@ -424,3 +426,47 @@ ENTRY(cast6_ctr_8way)
 
         ret;
 ENDPROC(cast6_ctr_8way)
+
+ENTRY(cast6_xts_enc_8way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
+         */
+
+        movq %rsi, %r11;
+
+        /* regs <= src, dst <= IVs, regs <= regs xor IVs */
+        load_xts_8way(%rcx, %rdx, %rsi, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2,
+                      RX, RKR, RKM, .Lxts_gf128mul_and_shl1_mask);
+
+        call __cast6_enc_blk8;
+
+        /* dst <= regs xor IVs(in dst) */
+        store_xts_8way(%r11, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2);
+
+        ret;
+ENDPROC(cast6_xts_enc_8way)
+
+ENTRY(cast6_xts_dec_8way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
+         */
+
+        movq %rsi, %r11;
+
+        /* regs <= src, dst <= IVs, regs <= regs xor IVs */
+        load_xts_8way(%rcx, %rdx, %rsi, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2,
+                      RX, RKR, RKM, .Lxts_gf128mul_and_shl1_mask);
+
+        call __cast6_dec_blk8;
+
+        /* dst <= regs xor IVs(in dst) */
+        store_xts_8way(%r11, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2);
+
+        ret;
+ENDPROC(cast6_xts_dec_8way)
diff --git a/arch/x86/crypto/cast6_avx_glue.c b/arch/x86/crypto/cast6_avx_glue.c
index 92f7ca24790a..8d0dfb86a559 100644
--- a/arch/x86/crypto/cast6_avx_glue.c
+++ b/arch/x86/crypto/cast6_avx_glue.c
@@ -4,6 +4,8 @@
  * Copyright (C) 2012 Johannes Goetzfried
  *     <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
  *
+ * Copyright © 2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -50,6 +52,23 @@ asmlinkage void cast6_cbc_dec_8way(struct cast6_ctx *ctx, u8 *dst,
 asmlinkage void cast6_ctr_8way(struct cast6_ctx *ctx, u8 *dst, const u8 *src,
                                le128 *iv);
 
+asmlinkage void cast6_xts_enc_8way(struct cast6_ctx *ctx, u8 *dst,
+                                   const u8 *src, le128 *iv);
+asmlinkage void cast6_xts_dec_8way(struct cast6_ctx *ctx, u8 *dst,
+                                   const u8 *src, le128 *iv);
+
+static void cast6_xts_enc(void *ctx, u128 *dst, const u128 *src, le128 *iv)
+{
+        glue_xts_crypt_128bit_one(ctx, dst, src, iv,
+                                  GLUE_FUNC_CAST(__cast6_encrypt));
+}
+
+static void cast6_xts_dec(void *ctx, u128 *dst, const u128 *src, le128 *iv)
+{
+        glue_xts_crypt_128bit_one(ctx, dst, src, iv,
+                                  GLUE_FUNC_CAST(__cast6_decrypt));
+}
+
 static void cast6_crypt_ctr(void *ctx, u128 *dst, const u128 *src, le128 *iv)
 {
         be128 ctrblk;
@@ -87,6 +106,19 @@ static const struct common_glue_ctx cast6_ctr = {
         } }
 };
 
+static const struct common_glue_ctx cast6_enc_xts = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = CAST6_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = CAST6_PARALLEL_BLOCKS,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(cast6_xts_enc_8way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(cast6_xts_enc) }
+        } }
+};
+
 static const struct common_glue_ctx cast6_dec = {
         .num_funcs = 2,
         .fpu_blocks_limit = CAST6_PARALLEL_BLOCKS,
@@ -113,6 +145,19 @@ static const struct common_glue_ctx cast6_dec_cbc = {
         } }
 };
 
+static const struct common_glue_ctx cast6_dec_xts = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = CAST6_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = CAST6_PARALLEL_BLOCKS,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(cast6_xts_dec_8way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(cast6_xts_dec) }
+        } }
+};
+
 static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
                        struct scatterlist *src, unsigned int nbytes)
 {
@@ -307,54 +352,20 @@ static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
                        struct scatterlist *src, unsigned int nbytes)
 {
         struct cast6_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        be128 buf[CAST6_PARALLEL_BLOCKS];
-        struct crypt_priv crypt_ctx = {
-                .ctx = &ctx->crypt_ctx,
-                .fpu_enabled = false,
-        };
-        struct xts_crypt_req req = {
-                .tbuf = buf,
-                .tbuflen = sizeof(buf),
 
-                .tweak_ctx = &ctx->tweak_ctx,
-                .tweak_fn = XTS_TWEAK_CAST(__cast6_encrypt),
-                .crypt_ctx = &crypt_ctx,
-                .crypt_fn = encrypt_callback,
-        };
-        int ret;
-
-        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
-        ret = xts_crypt(desc, dst, src, nbytes, &req);
-        cast6_fpu_end(crypt_ctx.fpu_enabled);
-
-        return ret;
+        return glue_xts_crypt_128bit(&cast6_enc_xts, desc, dst, src, nbytes,
+                                     XTS_TWEAK_CAST(__cast6_encrypt),
+                                     &ctx->tweak_ctx, &ctx->crypt_ctx);
 }
 
 static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
                        struct scatterlist *src, unsigned int nbytes)
 {
         struct cast6_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        be128 buf[CAST6_PARALLEL_BLOCKS];
-        struct crypt_priv crypt_ctx = {
-                .ctx = &ctx->crypt_ctx,
-                .fpu_enabled = false,
-        };
-        struct xts_crypt_req req = {
-                .tbuf = buf,
-                .tbuflen = sizeof(buf),
-
-                .tweak_ctx = &ctx->tweak_ctx,
-                .tweak_fn = XTS_TWEAK_CAST(__cast6_encrypt),
-                .crypt_ctx = &crypt_ctx,
-                .crypt_fn = decrypt_callback,
-        };
-        int ret;
 
-        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
-        ret = xts_crypt(desc, dst, src, nbytes, &req);
-        cast6_fpu_end(crypt_ctx.fpu_enabled);
-
-        return ret;
+        return glue_xts_crypt_128bit(&cast6_dec_xts, desc, dst, src, nbytes,
+                                     XTS_TWEAK_CAST(__cast6_encrypt),
+                                     &ctx->tweak_ctx, &ctx->crypt_ctx);
 }
 
 static struct crypto_alg cast6_algs[10] = { {
diff --git a/arch/x86/crypto/crc32-pclmul_asm.S b/arch/x86/crypto/crc32-pclmul_asm.S
index c8335014a044..94c27df8a549 100644
--- a/arch/x86/crypto/crc32-pclmul_asm.S
+++ b/arch/x86/crypto/crc32-pclmul_asm.S
@@ -101,9 +101,8 @@
  *      uint crc32_pclmul_le_16(unsigned char const *buffer,
  *                           size_t len, uint crc32)
  */
-.globl crc32_pclmul_le_16
-.align 4, 0x90
-crc32_pclmul_le_16:/* buffer and buffer size are 16 bytes aligned */
+
+ENTRY(crc32_pclmul_le_16) /* buffer and buffer size are 16 bytes aligned */
         movdqa  (BUF), %xmm1
         movdqa  0x10(BUF), %xmm2
         movdqa  0x20(BUF), %xmm3
@@ -244,3 +243,4 @@ fold_64:
         pextrd  $0x01, %xmm1, %eax
 
         ret
+ENDPROC(crc32_pclmul_le_16)
diff --git a/arch/x86/crypto/crc32c-pcl-intel-asm_64.S b/arch/x86/crypto/crc32c-pcl-intel-asm_64.S
index cf1a7ec4cc3a..dbc4339b5417 100644
--- a/arch/x86/crypto/crc32c-pcl-intel-asm_64.S
+++ b/arch/x86/crypto/crc32c-pcl-intel-asm_64.S
@@ -1,9 +1,10 @@
 /*
  * Implement fast CRC32C with PCLMULQDQ instructions. (x86_64)
  *
- * The white paper on CRC32C calculations with PCLMULQDQ instruction can be
+ * The white papers on CRC32C calculations with PCLMULQDQ instruction can be
  * downloaded from:
- * http://download.intel.com/design/intarch/papers/323405.pdf
+ * http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/crc-iscsi-polynomial-crc32-instruction-paper.pdf
+ * http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/fast-crc-computation-paper.pdf
  *
  * Copyright (C) 2012 Intel Corporation.
  *
@@ -42,6 +43,7 @@
  * SOFTWARE.
  */
 
+#include <asm/inst.h>
 #include <linux/linkage.h>
 
 ## ISCSI CRC 32 Implementation with crc32 and pclmulqdq Instruction
@@ -225,10 +227,10 @@ LABEL crc_ %i
         movdqa  (bufp), %xmm0                   # 2 consts: K1:K2
 
         movq    crc_init, %xmm1                 # CRC for block 1
-        pclmulqdq $0x00,%xmm0,%xmm1             # Multiply by K2
+        PCLMULQDQ 0x00,%xmm0,%xmm1              # Multiply by K2
 
         movq    crc1, %xmm2                     # CRC for block 2
-        pclmulqdq $0x10, %xmm0, %xmm2           # Multiply by K1
+        PCLMULQDQ 0x10, %xmm0, %xmm2            # Multiply by K1
 
         pxor    %xmm2,%xmm1
         movq    %xmm1, %rax
diff --git a/arch/x86/crypto/glue_helper-asm-avx.S b/arch/x86/crypto/glue_helper-asm-avx.S
index f7b6ea2ddfdb..02ee2308fb38 100644
--- a/arch/x86/crypto/glue_helper-asm-avx.S
+++ b/arch/x86/crypto/glue_helper-asm-avx.S
@@ -1,7 +1,7 @@
 /*
  * Shared glue code for 128bit block ciphers, AVX assembler macros
  *
- * Copyright (c) 2012 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
+ * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -89,3 +89,62 @@
         vpxor (6*16)(src), x6, x6; \
         vpxor (7*16)(src), x7, x7; \
         store_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
+
+#define gf128mul_x_ble(iv, mask, tmp) \
+        vpsrad $31, iv, tmp; \
+        vpaddq iv, iv, iv; \
+        vpshufd $0x13, tmp, tmp; \
+        vpand mask, tmp, tmp; \
+        vpxor tmp, iv, iv;
+
+#define load_xts_8way(iv, src, dst, x0, x1, x2, x3, x4, x5, x6, x7, tiv, t0, \
+                      t1, xts_gf128mul_and_shl1_mask) \
+        vmovdqa xts_gf128mul_and_shl1_mask, t0; \
+        \
+        /* load IV */ \
+        vmovdqu (iv), tiv; \
+        vpxor (0*16)(src), tiv, x0; \
+        vmovdqu tiv, (0*16)(dst); \
+        \
+        /* construct and store IVs, also xor with source */ \
+        gf128mul_x_ble(tiv, t0, t1); \
+        vpxor (1*16)(src), tiv, x1; \
+        vmovdqu tiv, (1*16)(dst); \
+        \
+        gf128mul_x_ble(tiv, t0, t1); \
+        vpxor (2*16)(src), tiv, x2; \
+        vmovdqu tiv, (2*16)(dst); \
+        \
+        gf128mul_x_ble(tiv, t0, t1); \
+        vpxor (3*16)(src), tiv, x3; \
+        vmovdqu tiv, (3*16)(dst); \
+        \
+        gf128mul_x_ble(tiv, t0, t1); \
+        vpxor (4*16)(src), tiv, x4; \
+        vmovdqu tiv, (4*16)(dst); \
+        \
+        gf128mul_x_ble(tiv, t0, t1); \
+        vpxor (5*16)(src), tiv, x5; \
+        vmovdqu tiv, (5*16)(dst); \
+        \
+        gf128mul_x_ble(tiv, t0, t1); \
+        vpxor (6*16)(src), tiv, x6; \
+        vmovdqu tiv, (6*16)(dst); \
+        \
+        gf128mul_x_ble(tiv, t0, t1); \
+        vpxor (7*16)(src), tiv, x7; \
+        vmovdqu tiv, (7*16)(dst); \
+        \
+        gf128mul_x_ble(tiv, t0, t1); \
+        vmovdqu tiv, (iv);
+
+#define store_xts_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7) \
+        vpxor (0*16)(dst), x0, x0; \
+        vpxor (1*16)(dst), x1, x1; \
+        vpxor (2*16)(dst), x2, x2; \
+        vpxor (3*16)(dst), x3, x3; \
+        vpxor (4*16)(dst), x4, x4; \
+        vpxor (5*16)(dst), x5, x5; \
+        vpxor (6*16)(dst), x6, x6; \
+        vpxor (7*16)(dst), x7, x7; \
+        store_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
diff --git a/arch/x86/crypto/glue_helper-asm-avx2.S b/arch/x86/crypto/glue_helper-asm-avx2.S
new file mode 100644
index 000000000000..a53ac11dd385
--- /dev/null
+++ b/arch/x86/crypto/glue_helper-asm-avx2.S
@@ -0,0 +1,180 @@
+/*
+ * Shared glue code for 128bit block ciphers, AVX2 assembler macros
+ *
+ * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#define load_16way(src, x0, x1, x2, x3, x4, x5, x6, x7) \
+        vmovdqu (0*32)(src), x0; \
+        vmovdqu (1*32)(src), x1; \
+        vmovdqu (2*32)(src), x2; \
+        vmovdqu (3*32)(src), x3; \
+        vmovdqu (4*32)(src), x4; \
+        vmovdqu (5*32)(src), x5; \
+        vmovdqu (6*32)(src), x6; \
+        vmovdqu (7*32)(src), x7;
+
+#define store_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7) \
+        vmovdqu x0, (0*32)(dst); \
+        vmovdqu x1, (1*32)(dst); \
+        vmovdqu x2, (2*32)(dst); \
+        vmovdqu x3, (3*32)(dst); \
+        vmovdqu x4, (4*32)(dst); \
+        vmovdqu x5, (5*32)(dst); \
+        vmovdqu x6, (6*32)(dst); \
+        vmovdqu x7, (7*32)(dst);
+
+#define store_cbc_16way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7, t0) \
+        vpxor t0, t0, t0; \
+        vinserti128 $1, (src), t0, t0; \
+        vpxor t0, x0, x0; \
+        vpxor (0*32+16)(src), x1, x1; \
+        vpxor (1*32+16)(src), x2, x2; \
+        vpxor (2*32+16)(src), x3, x3; \
+        vpxor (3*32+16)(src), x4, x4; \
+        vpxor (4*32+16)(src), x5, x5; \
+        vpxor (5*32+16)(src), x6, x6; \
+        vpxor (6*32+16)(src), x7, x7; \
+        store_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
+
+#define inc_le128(x, minus_one, tmp) \
+        vpcmpeqq minus_one, x, tmp; \
+        vpsubq minus_one, x, x; \
+        vpslldq $8, tmp, tmp; \
+        vpsubq tmp, x, x;
+
+#define add2_le128(x, minus_one, minus_two, tmp1, tmp2) \
+        vpcmpeqq minus_one, x, tmp1; \
+        vpcmpeqq minus_two, x, tmp2; \
+        vpsubq minus_two, x, x; \
+        vpor tmp2, tmp1, tmp1; \
+        vpslldq $8, tmp1, tmp1; \
+        vpsubq tmp1, x, x;
+
+#define load_ctr_16way(iv, bswap, x0, x1, x2, x3, x4, x5, x6, x7, t0, t0x, t1, \
+                       t1x, t2, t2x, t3, t3x, t4, t5) \
+        vpcmpeqd t0, t0, t0; \
+        vpsrldq $8, t0, t0; /* ab: -1:0 ; cd: -1:0 */ \
+        vpaddq t0, t0, t4; /* ab: -2:0 ; cd: -2:0 */\
+        \
+        /* load IV and byteswap */ \
+        vmovdqu (iv), t2x; \
+        vmovdqa t2x, t3x; \
+        inc_le128(t2x, t0x, t1x); \
+        vbroadcasti128 bswap, t1; \
+        vinserti128 $1, t2x, t3, t2; /* ab: le0 ; cd: le1 */ \
+        vpshufb t1, t2, x0; \
+        \
+        /* construct IVs */ \
+        add2_le128(t2, t0, t4, t3, t5); /* ab: le2 ; cd: le3 */ \
+        vpshufb t1, t2, x1; \
+        add2_le128(t2, t0, t4, t3, t5); \
+        vpshufb t1, t2, x2; \
+        add2_le128(t2, t0, t4, t3, t5); \
+        vpshufb t1, t2, x3; \
+        add2_le128(t2, t0, t4, t3, t5); \
+        vpshufb t1, t2, x4; \
+        add2_le128(t2, t0, t4, t3, t5); \
+        vpshufb t1, t2, x5; \
+        add2_le128(t2, t0, t4, t3, t5); \
+        vpshufb t1, t2, x6; \
+        add2_le128(t2, t0, t4, t3, t5); \
+        vpshufb t1, t2, x7; \
+        vextracti128 $1, t2, t2x; \
+        inc_le128(t2x, t0x, t3x); \
+        vmovdqu t2x, (iv);
+
+#define store_ctr_16way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7) \
+        vpxor (0*32)(src), x0, x0; \
+        vpxor (1*32)(src), x1, x1; \
+        vpxor (2*32)(src), x2, x2; \
+        vpxor (3*32)(src), x3, x3; \
+        vpxor (4*32)(src), x4, x4; \
+        vpxor (5*32)(src), x5, x5; \
+        vpxor (6*32)(src), x6, x6; \
+        vpxor (7*32)(src), x7, x7; \
+        store_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
+
+#define gf128mul_x_ble(iv, mask, tmp) \
+        vpsrad $31, iv, tmp; \
+        vpaddq iv, iv, iv; \
+        vpshufd $0x13, tmp, tmp; \
+        vpand mask, tmp, tmp; \
+        vpxor tmp, iv, iv;
+
+#define gf128mul_x2_ble(iv, mask1, mask2, tmp0, tmp1) \
+        vpsrad $31, iv, tmp0; \
+        vpaddq iv, iv, tmp1; \
+        vpsllq $2, iv, iv; \
+        vpshufd $0x13, tmp0, tmp0; \
+        vpsrad $31, tmp1, tmp1; \
+        vpand mask2, tmp0, tmp0; \
+        vpshufd $0x13, tmp1, tmp1; \
+        vpxor tmp0, iv, iv; \
+        vpand mask1, tmp1, tmp1; \
+        vpxor tmp1, iv, iv;
+
+#define load_xts_16way(iv, src, dst, x0, x1, x2, x3, x4, x5, x6, x7, tiv, \
+                       tivx, t0, t0x, t1, t1x, t2, t2x, t3, \
+                       xts_gf128mul_and_shl1_mask_0, \
+                       xts_gf128mul_and_shl1_mask_1) \
+        vbroadcasti128 xts_gf128mul_and_shl1_mask_0, t1; \
+        \
+        /* load IV and construct second IV */ \
+        vmovdqu (iv), tivx; \
+        vmovdqa tivx, t0x; \
+        gf128mul_x_ble(tivx, t1x, t2x); \
+        vbroadcasti128 xts_gf128mul_and_shl1_mask_1, t2; \
+        vinserti128 $1, tivx, t0, tiv; \
+        vpxor (0*32)(src), tiv, x0; \
+        vmovdqu tiv, (0*32)(dst); \
+        \
+        /* construct and store IVs, also xor with source */ \
+        gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
+        vpxor (1*32)(src), tiv, x1; \
+        vmovdqu tiv, (1*32)(dst); \
+        \
+        gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
+        vpxor (2*32)(src), tiv, x2; \
+        vmovdqu tiv, (2*32)(dst); \
+        \
+        gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
+        vpxor (3*32)(src), tiv, x3; \
+        vmovdqu tiv, (3*32)(dst); \
+        \
+        gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
+        vpxor (4*32)(src), tiv, x4; \
+        vmovdqu tiv, (4*32)(dst); \
+        \
+        gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
+        vpxor (5*32)(src), tiv, x5; \
+        vmovdqu tiv, (5*32)(dst); \
+        \
+        gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
+        vpxor (6*32)(src), tiv, x6; \
+        vmovdqu tiv, (6*32)(dst); \
+        \
+        gf128mul_x2_ble(tiv, t1, t2, t0, t3); \
+        vpxor (7*32)(src), tiv, x7; \
+        vmovdqu tiv, (7*32)(dst); \
+        \
+        vextracti128 $1, tiv, tivx; \
+        gf128mul_x_ble(tivx, t1x, t2x); \
+        vmovdqu tivx, (iv);
+
+#define store_xts_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7) \
+        vpxor (0*32)(dst), x0, x0; \
+        vpxor (1*32)(dst), x1, x1; \
+        vpxor (2*32)(dst), x2, x2; \
+        vpxor (3*32)(dst), x3, x3; \
+        vpxor (4*32)(dst), x4, x4; \
+        vpxor (5*32)(dst), x5, x5; \
+        vpxor (6*32)(dst), x6, x6; \
+        vpxor (7*32)(dst), x7, x7; \
+        store_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
diff --git a/arch/x86/crypto/glue_helper.c b/arch/x86/crypto/glue_helper.c
index 22ce4f683e55..432f1d76ceb8 100644
--- a/arch/x86/crypto/glue_helper.c
+++ b/arch/x86/crypto/glue_helper.c
@@ -1,7 +1,7 @@
 /*
  * Shared glue code for 128bit block ciphers
  *
- * Copyright (c) 2012 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
+ * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
  *
  * CBC & ECB parts based on code (crypto/cbc.c,ecb.c) by:
  *   Copyright (c) 2006 Herbert Xu <herbert@gondor.apana.org.au>
@@ -304,4 +304,99 @@ int glue_ctr_crypt_128bit(const struct common_glue_ctx *gctx,
 }
 EXPORT_SYMBOL_GPL(glue_ctr_crypt_128bit);
 
+static unsigned int __glue_xts_crypt_128bit(const struct common_glue_ctx *gctx,
+                                            void *ctx,
+                                            struct blkcipher_desc *desc,
+                                            struct blkcipher_walk *walk)
+{
+        const unsigned int bsize = 128 / 8;
+        unsigned int nbytes = walk->nbytes;
+        u128 *src = (u128 *)walk->src.virt.addr;
+        u128 *dst = (u128 *)walk->dst.virt.addr;
+        unsigned int num_blocks, func_bytes;
+        unsigned int i;
+
+        /* Process multi-block batch */
+        for (i = 0; i < gctx->num_funcs; i++) {
+                num_blocks = gctx->funcs[i].num_blocks;
+                func_bytes = bsize * num_blocks;
+
+                if (nbytes >= func_bytes) {
+                        do {
+                                gctx->funcs[i].fn_u.xts(ctx, dst, src,
+                                                        (le128 *)walk->iv);
+
+                                src += num_blocks;
+                                dst += num_blocks;
+                                nbytes -= func_bytes;
+                        } while (nbytes >= func_bytes);
+
+                        if (nbytes < bsize)
+                                goto done;
+                }
+        }
+
+done:
+        return nbytes;
+}
+
+/* for implementations implementing faster XTS IV generator */
+int glue_xts_crypt_128bit(const struct common_glue_ctx *gctx,
+                          struct blkcipher_desc *desc, struct scatterlist *dst,
+                          struct scatterlist *src, unsigned int nbytes,
+                          void (*tweak_fn)(void *ctx, u8 *dst, const u8 *src),
+                          void *tweak_ctx, void *crypt_ctx)
+{
+        const unsigned int bsize = 128 / 8;
+        bool fpu_enabled = false;
+        struct blkcipher_walk walk;
+        int err;
+
+        blkcipher_walk_init(&walk, dst, src, nbytes);
+
+        err = blkcipher_walk_virt(desc, &walk);
+        nbytes = walk.nbytes;
+        if (!nbytes)
+                return err;
+
+        /* set minimum length to bsize, for tweak_fn */
+        fpu_enabled = glue_fpu_begin(bsize, gctx->fpu_blocks_limit,
+                                     desc, fpu_enabled,
+                                     nbytes < bsize ? bsize : nbytes);
+
+        /* calculate first value of T */
+        tweak_fn(tweak_ctx, walk.iv, walk.iv);
+
+        while (nbytes) {
+                nbytes = __glue_xts_crypt_128bit(gctx, crypt_ctx, desc, &walk);
+
+                err = blkcipher_walk_done(desc, &walk, nbytes);
+                nbytes = walk.nbytes;
+        }
+
+        glue_fpu_end(fpu_enabled);
+
+        return err;
+}
+EXPORT_SYMBOL_GPL(glue_xts_crypt_128bit);
+
+void glue_xts_crypt_128bit_one(void *ctx, u128 *dst, const u128 *src, le128 *iv,
+                               common_glue_func_t fn)
+{
+        le128 ivblk = *iv;
+
+        /* generate next IV */
+        le128_gf128mul_x_ble(iv, &ivblk);
+
+        /* CC <- T xor C */
+        u128_xor(dst, src, (u128 *)&ivblk);
+
+        /* PP <- D(Key2,CC) */
+        fn(ctx, (u8 *)dst, (u8 *)dst);
+
+        /* P <- T xor PP */
+        u128_xor(dst, dst, (u128 *)&ivblk);
+}
+EXPORT_SYMBOL_GPL(glue_xts_crypt_128bit_one);
+
 MODULE_LICENSE("GPL");
diff --git a/arch/x86/crypto/serpent-avx-x86_64-asm_64.S b/arch/x86/crypto/serpent-avx-x86_64-asm_64.S
index 43c938612b74..2f202f49872b 100644
--- a/arch/x86/crypto/serpent-avx-x86_64-asm_64.S
+++ b/arch/x86/crypto/serpent-avx-x86_64-asm_64.S
@@ -4,8 +4,7 @@
  * Copyright (C) 2012 Johannes Goetzfried
  *     <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
  *
- * Based on arch/x86/crypto/serpent-sse2-x86_64-asm_64.S by
- *  Copyright (C) 2011 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
+ * Copyright © 2011-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -34,6 +33,8 @@
 
 .Lbswap128_mask:
         .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
+.Lxts_gf128mul_and_shl1_mask:
+        .byte 0x87, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0
 
 .text
 
@@ -739,3 +740,43 @@ ENTRY(serpent_ctr_8way_avx)
 
         ret;
 ENDPROC(serpent_ctr_8way_avx)
+
+ENTRY(serpent_xts_enc_8way_avx)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
+         */
+
+        /* regs <= src, dst <= IVs, regs <= regs xor IVs */
+        load_xts_8way(%rcx, %rdx, %rsi, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2,
+                      RK0, RK1, RK2, .Lxts_gf128mul_and_shl1_mask);
+
+        call __serpent_enc_blk8_avx;
+
+        /* dst <= regs xor IVs(in dst) */
+        store_xts_8way(%rsi, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2);
+
+        ret;
+ENDPROC(serpent_xts_enc_8way_avx)
+
+ENTRY(serpent_xts_dec_8way_avx)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
+         */
+
+        /* regs <= src, dst <= IVs, regs <= regs xor IVs */
+        load_xts_8way(%rcx, %rdx, %rsi, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2,
+                      RK0, RK1, RK2, .Lxts_gf128mul_and_shl1_mask);
+
+        call __serpent_dec_blk8_avx;
+
+        /* dst <= regs xor IVs(in dst) */
+        store_xts_8way(%rsi, RC1, RD1, RB1, RE1, RC2, RD2, RB2, RE2);
+
+        ret;
+ENDPROC(serpent_xts_dec_8way_avx)
diff --git a/arch/x86/crypto/serpent-avx2-asm_64.S b/arch/x86/crypto/serpent-avx2-asm_64.S
new file mode 100644
index 000000000000..b222085cccac
--- /dev/null
+++ b/arch/x86/crypto/serpent-avx2-asm_64.S
@@ -0,0 +1,800 @@
+/*
+ * x86_64/AVX2 assembler optimized version of Serpent
+ *
+ * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
+ *
+ * Based on AVX assembler implementation of Serpent by:
+ *  Copyright © 2012 Johannes Goetzfried
+ *      <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/linkage.h>
+#include "glue_helper-asm-avx2.S"
+
+.file "serpent-avx2-asm_64.S"
+
+.data
+.align 16
+
+.Lbswap128_mask:
+        .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
+.Lxts_gf128mul_and_shl1_mask_0:
+        .byte 0x87, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0
+.Lxts_gf128mul_and_shl1_mask_1:
+        .byte 0x0e, 1, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0
+
+.text
+
+#define CTX %rdi
+
+#define RNOT %ymm0
+#define tp  %ymm1
+
+#define RA1 %ymm2
+#define RA2 %ymm3
+#define RB1 %ymm4
+#define RB2 %ymm5
+#define RC1 %ymm6
+#define RC2 %ymm7
+#define RD1 %ymm8
+#define RD2 %ymm9
+#define RE1 %ymm10
+#define RE2 %ymm11
+
+#define RK0 %ymm12
+#define RK1 %ymm13
+#define RK2 %ymm14
+#define RK3 %ymm15
+
+#define RK0x %xmm12
+#define RK1x %xmm13
+#define RK2x %xmm14
+#define RK3x %xmm15
+
+#define S0_1(x0, x1, x2, x3, x4)      \
+        vpor            x0,   x3, tp; \
+        vpxor           x3,   x0, x0; \
+        vpxor           x2,   x3, x4; \
+        vpxor           RNOT, x4, x4; \
+        vpxor           x1,   tp, x3; \
+        vpand           x0,   x1, x1; \
+        vpxor           x4,   x1, x1; \
+        vpxor           x0,   x2, x2;
+#define S0_2(x0, x1, x2, x3, x4)      \
+        vpxor           x3,   x0, x0; \
+        vpor            x0,   x4, x4; \
+        vpxor           x2,   x0, x0; \
+        vpand           x1,   x2, x2; \
+        vpxor           x2,   x3, x3; \
+        vpxor           RNOT, x1, x1; \
+        vpxor           x4,   x2, x2; \
+        vpxor           x2,   x1, x1;
+
+#define S1_1(x0, x1, x2, x3, x4)      \
+        vpxor           x0,   x1, tp; \
+        vpxor           x3,   x0, x0; \
+        vpxor           RNOT, x3, x3; \
+        vpand           tp,   x1, x4; \
+        vpor            tp,   x0, x0; \
+        vpxor           x2,   x3, x3; \
+        vpxor           x3,   x0, x0; \
+        vpxor           x3,   tp, x1;
+#define S1_2(x0, x1, x2, x3, x4)      \
+        vpxor           x4,   x3, x3; \
+        vpor            x4,   x1, x1; \
+        vpxor           x2,   x4, x4; \
+        vpand           x0,   x2, x2; \
+        vpxor           x1,   x2, x2; \
+        vpor            x0,   x1, x1; \
+        vpxor           RNOT, x0, x0; \
+        vpxor           x2,   x0, x0; \
+        vpxor           x1,   x4, x4;
+
+#define S2_1(x0, x1, x2, x3, x4)      \
+        vpxor           RNOT, x3, x3; \
+        vpxor           x0,   x1, x1; \
+        vpand           x2,   x0, tp; \
+        vpxor           x3,   tp, tp; \
+        vpor            x0,   x3, x3; \
+        vpxor           x1,   x2, x2; \
+        vpxor           x1,   x3, x3; \
+        vpand           tp,   x1, x1;
+#define S2_2(x0, x1, x2, x3, x4)      \
+        vpxor           x2,   tp, tp; \
+        vpand           x3,   x2, x2; \
+        vpor            x1,   x3, x3; \
+        vpxor           RNOT, tp, tp; \
+        vpxor           tp,   x3, x3; \
+        vpxor           tp,   x0, x4; \
+        vpxor           x2,   tp, x0; \
+        vpor            x2,   x1, x1;
+
+#define S3_1(x0, x1, x2, x3, x4)      \
+        vpxor           x3,   x1, tp; \
+        vpor            x0,   x3, x3; \
+        vpand           x0,   x1, x4; \
+        vpxor           x2,   x0, x0; \
+        vpxor           tp,   x2, x2; \
+        vpand           x3,   tp, x1; \
+        vpxor           x3,   x2, x2; \
+        vpor            x4,   x0, x0; \
+        vpxor           x3,   x4, x4;
+#define S3_2(x0, x1, x2, x3, x4)      \
+        vpxor           x0,   x1, x1; \
+        vpand           x3,   x0, x0; \
+        vpand           x4,   x3, x3; \
+        vpxor           x2,   x3, x3; \
+        vpor            x1,   x4, x4; \
+        vpand           x1,   x2, x2; \
+        vpxor           x3,   x4, x4; \
+        vpxor           x3,   x0, x0; \
+        vpxor           x2,   x3, x3;
+
+#define S4_1(x0, x1, x2, x3, x4)      \
+        vpand           x0,   x3, tp; \
+        vpxor           x3,   x0, x0; \
+        vpxor           x2,   tp, tp; \
+        vpor            x3,   x2, x2; \
+        vpxor           x1,   x0, x0; \
+        vpxor           tp,   x3, x4; \
+        vpor            x0,   x2, x2; \
+        vpxor           x1,   x2, x2;
+#define S4_2(x0, x1, x2, x3, x4)      \
+        vpand           x0,   x1, x1; \
+        vpxor           x4,   x1, x1; \
+        vpand           x2,   x4, x4; \
+        vpxor           tp,   x2, x2; \
+        vpxor           x0,   x4, x4; \
+        vpor            x1,   tp, x3; \
+        vpxor           RNOT, x1, x1; \
+        vpxor           x0,   x3, x3;
+
+#define S5_1(x0, x1, x2, x3, x4)      \
+        vpor            x0,   x1, tp; \
+        vpxor           tp,   x2, x2; \
+        vpxor           RNOT, x3, x3; \
+        vpxor           x0,   x1, x4; \
+        vpxor           x2,   x0, x0; \
+        vpand           x4,   tp, x1; \
+        vpor            x3,   x4, x4; \
+        vpxor           x0,   x4, x4;
+#define S5_2(x0, x1, x2, x3, x4)      \
+        vpand           x3,   x0, x0; \
+        vpxor           x3,   x1, x1; \
+        vpxor           x2,   x3, x3; \
+        vpxor           x1,   x0, x0; \
+        vpand           x4,   x2, x2; \
+        vpxor           x2,   x1, x1; \
+        vpand           x0,   x2, x2; \
+        vpxor           x2,   x3, x3;
+
+#define S6_1(x0, x1, x2, x3, x4)      \
+        vpxor           x0,   x3, x3; \
+        vpxor           x2,   x1, tp; \
+        vpxor           x0,   x2, x2; \
+        vpand           x3,   x0, x0; \
+        vpor            x3,   tp, tp; \
+        vpxor           RNOT, x1, x4; \
+        vpxor           tp,   x0, x0; \
+        vpxor           x2,   tp, x1;
+#define S6_2(x0, x1, x2, x3, x4)      \
+        vpxor           x4,   x3, x3; \
+        vpxor           x0,   x4, x4; \
+        vpand           x0,   x2, x2; \
+        vpxor           x1,   x4, x4; \
+        vpxor           x3,   x2, x2; \
+        vpand           x1,   x3, x3; \
+        vpxor           x0,   x3, x3; \
+        vpxor           x2,   x1, x1;
+
+#define S7_1(x0, x1, x2, x3, x4)      \
+        vpxor           RNOT, x1, tp; \
+        vpxor           RNOT, x0, x0; \
+        vpand           x2,   tp, x1; \
+        vpxor           x3,   x1, x1; \
+        vpor            tp,   x3, x3; \
+        vpxor           x2,   tp, x4; \
+        vpxor           x3,   x2, x2; \
+        vpxor           x0,   x3, x3; \
+        vpor            x1,   x0, x0;
+#define S7_2(x0, x1, x2, x3, x4)      \
+        vpand           x0,   x2, x2; \
+        vpxor           x4,   x0, x0; \
+        vpxor           x3,   x4, x4; \
+        vpand           x0,   x3, x3; \
+        vpxor           x1,   x4, x4; \
+        vpxor           x4,   x2, x2; \
+        vpxor           x1,   x3, x3; \
+        vpor            x0,   x4, x4; \
+        vpxor           x1,   x4, x4;
+
+#define SI0_1(x0, x1, x2, x3, x4)     \
+        vpxor           x0,   x1, x1; \
+        vpor            x1,   x3, tp; \
+        vpxor           x1,   x3, x4; \
+        vpxor           RNOT, x0, x0; \
+        vpxor           tp,   x2, x2; \
+        vpxor           x0,   tp, x3; \
+        vpand           x1,   x0, x0; \
+        vpxor           x2,   x0, x0;
+#define SI0_2(x0, x1, x2, x3, x4)     \
+        vpand           x3,   x2, x2; \
+        vpxor           x4,   x3, x3; \
+        vpxor           x3,   x2, x2; \
+        vpxor           x3,   x1, x1; \
+        vpand           x0,   x3, x3; \
+        vpxor           x0,   x1, x1; \
+        vpxor           x2,   x0, x0; \
+        vpxor           x3,   x4, x4;
+
+#define SI1_1(x0, x1, x2, x3, x4)     \
+        vpxor           x3,   x1, x1; \
+        vpxor           x2,   x0, tp; \
+        vpxor           RNOT, x2, x2; \
+        vpor            x1,   x0, x4; \
+        vpxor           x3,   x4, x4; \
+        vpand           x1,   x3, x3; \
+        vpxor           x2,   x1, x1; \
+        vpand           x4,   x2, x2;
+#define SI1_2(x0, x1, x2, x3, x4)     \
+        vpxor           x1,   x4, x4; \
+        vpor            x3,   x1, x1; \
+        vpxor           tp,   x3, x3; \
+        vpxor           tp,   x2, x2; \
+        vpor            x4,   tp, x0; \
+        vpxor           x4,   x2, x2; \
+        vpxor           x0,   x1, x1; \
+        vpxor           x1,   x4, x4;
+
+#define SI2_1(x0, x1, x2, x3, x4)     \
+        vpxor           x1,   x2, x2; \
+        vpxor           RNOT, x3, tp; \
+        vpor            x2,   tp, tp; \
+        vpxor           x3,   x2, x2; \
+        vpxor           x0,   x3, x4; \
+        vpxor           x1,   tp, x3; \
+        vpor            x2,   x1, x1; \
+        vpxor           x0,   x2, x2;
+#define SI2_2(x0, x1, x2, x3, x4)     \
+        vpxor           x4,   x1, x1; \
+        vpor            x3,   x4, x4; \
+        vpxor           x3,   x2, x2; \
+        vpxor           x2,   x4, x4; \
+        vpand           x1,   x2, x2; \
+        vpxor           x3,   x2, x2; \
+        vpxor           x4,   x3, x3; \
+        vpxor           x0,   x4, x4;
+
+#define SI3_1(x0, x1, x2, x3, x4)     \
+        vpxor           x1,   x2, x2; \
+        vpand           x2,   x1, tp; \
+        vpxor           x0,   tp, tp; \
+        vpor            x1,   x0, x0; \
+        vpxor           x3,   x1, x4; \
+        vpxor           x3,   x0, x0; \
+        vpor            tp,   x3, x3; \
+        vpxor           x2,   tp, x1;
+#define SI3_2(x0, x1, x2, x3, x4)     \
+        vpxor           x3,   x1, x1; \
+        vpxor           x2,   x0, x0; \
+        vpxor           x3,   x2, x2; \
+        vpand           x1,   x3, x3; \
+        vpxor           x0,   x1, x1; \
+        vpand           x2,   x0, x0; \
+        vpxor           x3,   x4, x4; \
+        vpxor           x0,   x3, x3; \
+        vpxor           x1,   x0, x0;
+
+#define SI4_1(x0, x1, x2, x3, x4)     \
+        vpxor           x3,   x2, x2; \
+        vpand           x1,   x0, tp; \
+        vpxor           x2,   tp, tp; \
+        vpor            x3,   x2, x2; \
+        vpxor           RNOT, x0, x4; \
+        vpxor           tp,   x1, x1; \
+        vpxor           x2,   tp, x0; \
+        vpand           x4,   x2, x2;
+#define SI4_2(x0, x1, x2, x3, x4)     \
+        vpxor           x0,   x2, x2; \
+        vpor            x4,   x0, x0; \
+        vpxor           x3,   x0, x0; \
+        vpand           x2,   x3, x3; \
+        vpxor           x3,   x4, x4; \
+        vpxor           x1,   x3, x3; \
+        vpand           x0,   x1, x1; \
+        vpxor           x1,   x4, x4; \
+        vpxor           x3,   x0, x0;
+
+#define SI5_1(x0, x1, x2, x3, x4)     \
+        vpor            x2,   x1, tp; \
+        vpxor           x1,   x2, x2; \
+        vpxor           x3,   tp, tp; \
+        vpand           x1,   x3, x3; \
+        vpxor           x3,   x2, x2; \
+        vpor            x0,   x3, x3; \
+        vpxor           RNOT, x0, x0; \
+        vpxor           x2,   x3, x3; \
+        vpor            x0,   x2, x2;
+#define SI5_2(x0, x1, x2, x3, x4)     \
+        vpxor           tp,   x1, x4; \
+        vpxor           x4,   x2, x2; \
+        vpand           x0,   x4, x4; \
+        vpxor           tp,   x0, x0; \
+        vpxor           x3,   tp, x1; \
+        vpand           x2,   x0, x0; \
+        vpxor           x3,   x2, x2; \
+        vpxor           x2,   x0, x0; \
+        vpxor           x4,   x2, x2; \
+        vpxor           x3,   x4, x4;
+
+#define SI6_1(x0, x1, x2, x3, x4)     \
+        vpxor           x2,   x0, x0; \
+        vpand           x3,   x0, tp; \
+        vpxor           x3,   x2, x2; \
+        vpxor           x2,   tp, tp; \
+        vpxor           x1,   x3, x3; \
+        vpor            x0,   x2, x2; \
+        vpxor           x3,   x2, x2; \
+        vpand           tp,   x3, x3;
+#define SI6_2(x0, x1, x2, x3, x4)     \
+        vpxor           RNOT, tp, tp; \
+        vpxor           x1,   x3, x3; \
+        vpand           x2,   x1, x1; \
+        vpxor           tp,   x0, x4; \
+        vpxor           x4,   x3, x3; \
+        vpxor           x2,   x4, x4; \
+        vpxor           x1,   tp, x0; \
+        vpxor           x0,   x2, x2;
+
+#define SI7_1(x0, x1, x2, x3, x4)     \
+        vpand           x0,   x3, tp; \
+        vpxor           x2,   x0, x0; \
+        vpor            x3,   x2, x2; \
+        vpxor           x1,   x3, x4; \
+        vpxor           RNOT, x0, x0; \
+        vpor            tp,   x1, x1; \
+        vpxor           x0,   x4, x4; \
+        vpand           x2,   x0, x0; \
+        vpxor           x1,   x0, x0;
+#define SI7_2(x0, x1, x2, x3, x4)     \
+        vpand           x2,   x1, x1; \
+        vpxor           x2,   tp, x3; \
+        vpxor           x3,   x4, x4; \
+        vpand           x3,   x2, x2; \
+        vpor            x0,   x3, x3; \
+        vpxor           x4,   x1, x1; \
+        vpxor           x4,   x3, x3; \
+        vpand           x0,   x4, x4; \
+        vpxor           x2,   x4, x4;
+
+#define get_key(i,j,t) \
+        vpbroadcastd (4*(i)+(j))*4(CTX), t;
+
+#define K2(x0, x1, x2, x3, x4, i) \
+        get_key(i, 0, RK0); \
+        get_key(i, 1, RK1); \
+        get_key(i, 2, RK2); \
+        get_key(i, 3, RK3); \
+        vpxor RK0,      x0 ## 1, x0 ## 1; \
+        vpxor RK1,      x1 ## 1, x1 ## 1; \
+        vpxor RK2,      x2 ## 1, x2 ## 1; \
+        vpxor RK3,      x3 ## 1, x3 ## 1; \
+                vpxor RK0,      x0 ## 2, x0 ## 2; \
+                vpxor RK1,      x1 ## 2, x1 ## 2; \
+                vpxor RK2,      x2 ## 2, x2 ## 2; \
+                vpxor RK3,      x3 ## 2, x3 ## 2;
+
+#define LK2(x0, x1, x2, x3, x4, i) \
+        vpslld $13,             x0 ## 1, x4 ## 1;          \
+        vpsrld $(32 - 13),      x0 ## 1, x0 ## 1;          \
+        vpor                    x4 ## 1, x0 ## 1, x0 ## 1; \
+        vpxor                   x0 ## 1, x1 ## 1, x1 ## 1; \
+        vpslld $3,              x2 ## 1, x4 ## 1;          \
+        vpsrld $(32 - 3),       x2 ## 1, x2 ## 1;          \
+        vpor                    x4 ## 1, x2 ## 1, x2 ## 1; \
+        vpxor                   x2 ## 1, x1 ## 1, x1 ## 1; \
+                vpslld $13,             x0 ## 2, x4 ## 2;          \
+                vpsrld $(32 - 13),      x0 ## 2, x0 ## 2;          \
+                vpor                    x4 ## 2, x0 ## 2, x0 ## 2; \
+                vpxor                   x0 ## 2, x1 ## 2, x1 ## 2; \
+                vpslld $3,              x2 ## 2, x4 ## 2;          \
+                vpsrld $(32 - 3),       x2 ## 2, x2 ## 2;          \
+                vpor                    x4 ## 2, x2 ## 2, x2 ## 2; \
+                vpxor                   x2 ## 2, x1 ## 2, x1 ## 2; \
+        vpslld $1,              x1 ## 1, x4 ## 1;          \
+        vpsrld $(32 - 1),       x1 ## 1, x1 ## 1;          \
+        vpor                    x4 ## 1, x1 ## 1, x1 ## 1; \
+        vpslld $3,              x0 ## 1, x4 ## 1;          \
+        vpxor                   x2 ## 1, x3 ## 1, x3 ## 1; \
+        vpxor                   x4 ## 1, x3 ## 1, x3 ## 1; \
+        get_key(i, 1, RK1); \
+                vpslld $1,              x1 ## 2, x4 ## 2;          \
+                vpsrld $(32 - 1),       x1 ## 2, x1 ## 2;          \
+                vpor                    x4 ## 2, x1 ## 2, x1 ## 2; \
+                vpslld $3,              x0 ## 2, x4 ## 2;          \
+                vpxor                   x2 ## 2, x3 ## 2, x3 ## 2; \
+                vpxor                   x4 ## 2, x3 ## 2, x3 ## 2; \
+                get_key(i, 3, RK3); \
+        vpslld $7,              x3 ## 1, x4 ## 1;          \
+        vpsrld $(32 - 7),       x3 ## 1, x3 ## 1;          \
+        vpor                    x4 ## 1, x3 ## 1, x3 ## 1; \
+        vpslld $7,              x1 ## 1, x4 ## 1;          \
+        vpxor                   x1 ## 1, x0 ## 1, x0 ## 1; \
+        vpxor                   x3 ## 1, x0 ## 1, x0 ## 1; \
+        vpxor                   x3 ## 1, x2 ## 1, x2 ## 1; \
+        vpxor                   x4 ## 1, x2 ## 1, x2 ## 1; \
+        get_key(i, 0, RK0); \
+                vpslld $7,              x3 ## 2, x4 ## 2;          \
+                vpsrld $(32 - 7),       x3 ## 2, x3 ## 2;          \
+                vpor                    x4 ## 2, x3 ## 2, x3 ## 2; \
+                vpslld $7,              x1 ## 2, x4 ## 2;          \
+                vpxor                   x1 ## 2, x0 ## 2, x0 ## 2; \
+                vpxor                   x3 ## 2, x0 ## 2, x0 ## 2; \
+                vpxor                   x3 ## 2, x2 ## 2, x2 ## 2; \
+                vpxor                   x4 ## 2, x2 ## 2, x2 ## 2; \
+                get_key(i, 2, RK2); \
+        vpxor                   RK1, x1 ## 1, x1 ## 1;     \
+        vpxor                   RK3, x3 ## 1, x3 ## 1;     \
+        vpslld $5,              x0 ## 1, x4 ## 1;          \
+        vpsrld $(32 - 5),       x0 ## 1, x0 ## 1;          \
+        vpor                    x4 ## 1, x0 ## 1, x0 ## 1; \
+        vpslld $22,             x2 ## 1, x4 ## 1;          \
+        vpsrld $(32 - 22),      x2 ## 1, x2 ## 1;          \
+        vpor                    x4 ## 1, x2 ## 1, x2 ## 1; \
+        vpxor                   RK0, x0 ## 1, x0 ## 1;     \
+        vpxor                   RK2, x2 ## 1, x2 ## 1;     \
+                vpxor                   RK1, x1 ## 2, x1 ## 2;     \
+                vpxor                   RK3, x3 ## 2, x3 ## 2;     \
+                vpslld $5,              x0 ## 2, x4 ## 2;          \
+                vpsrld $(32 - 5),       x0 ## 2, x0 ## 2;          \
+                vpor                    x4 ## 2, x0 ## 2, x0 ## 2; \
+                vpslld $22,             x2 ## 2, x4 ## 2;          \
+                vpsrld $(32 - 22),      x2 ## 2, x2 ## 2;          \
+                vpor                    x4 ## 2, x2 ## 2, x2 ## 2; \
+                vpxor                   RK0, x0 ## 2, x0 ## 2;     \
+                vpxor                   RK2, x2 ## 2, x2 ## 2;
+
+#define KL2(x0, x1, x2, x3, x4, i) \
+        vpxor                   RK0, x0 ## 1, x0 ## 1;     \
+        vpxor                   RK2, x2 ## 1, x2 ## 1;     \
+        vpsrld $5,              x0 ## 1, x4 ## 1;          \
+        vpslld $(32 - 5),       x0 ## 1, x0 ## 1;          \
+        vpor                    x4 ## 1, x0 ## 1, x0 ## 1; \
+        vpxor                   RK3, x3 ## 1, x3 ## 1;     \
+        vpxor                   RK1, x1 ## 1, x1 ## 1;     \
+        vpsrld $22,             x2 ## 1, x4 ## 1;          \
+        vpslld $(32 - 22),      x2 ## 1, x2 ## 1;          \
+        vpor                    x4 ## 1, x2 ## 1, x2 ## 1; \
+        vpxor                   x3 ## 1, x2 ## 1, x2 ## 1; \
+                vpxor                   RK0, x0 ## 2, x0 ## 2;     \
+                vpxor                   RK2, x2 ## 2, x2 ## 2;     \
+                vpsrld $5,              x0 ## 2, x4 ## 2;          \
+                vpslld $(32 - 5),       x0 ## 2, x0 ## 2;          \
+                vpor                    x4 ## 2, x0 ## 2, x0 ## 2; \
+                vpxor                   RK3, x3 ## 2, x3 ## 2;     \
+                vpxor                   RK1, x1 ## 2, x1 ## 2;     \
+                vpsrld $22,             x2 ## 2, x4 ## 2;          \
+                vpslld $(32 - 22),      x2 ## 2, x2 ## 2;          \
+                vpor                    x4 ## 2, x2 ## 2, x2 ## 2; \
+                vpxor                   x3 ## 2, x2 ## 2, x2 ## 2; \
+        vpxor                   x3 ## 1, x0 ## 1, x0 ## 1; \
+        vpslld $7,              x1 ## 1, x4 ## 1;          \
+        vpxor                   x1 ## 1, x0 ## 1, x0 ## 1; \
+        vpxor                   x4 ## 1, x2 ## 1, x2 ## 1; \
+        vpsrld $1,              x1 ## 1, x4 ## 1;          \
+        vpslld $(32 - 1),       x1 ## 1, x1 ## 1;          \
+        vpor                    x4 ## 1, x1 ## 1, x1 ## 1; \
+                vpxor                   x3 ## 2, x0 ## 2, x0 ## 2; \
+                vpslld $7,              x1 ## 2, x4 ## 2;          \
+                vpxor                   x1 ## 2, x0 ## 2, x0 ## 2; \
+                vpxor                   x4 ## 2, x2 ## 2, x2 ## 2; \
+                vpsrld $1,              x1 ## 2, x4 ## 2;          \
+                vpslld $(32 - 1),       x1 ## 2, x1 ## 2;          \
+                vpor                    x4 ## 2, x1 ## 2, x1 ## 2; \
+        vpsrld $7,              x3 ## 1, x4 ## 1;          \
+        vpslld $(32 - 7),       x3 ## 1, x3 ## 1;          \
+        vpor                    x4 ## 1, x3 ## 1, x3 ## 1; \
+        vpxor                   x0 ## 1, x1 ## 1, x1 ## 1; \
+        vpslld $3,              x0 ## 1, x4 ## 1;          \
+        vpxor                   x4 ## 1, x3 ## 1, x3 ## 1; \
+                vpsrld $7,              x3 ## 2, x4 ## 2;          \
+                vpslld $(32 - 7),       x3 ## 2, x3 ## 2;          \
+                vpor                    x4 ## 2, x3 ## 2, x3 ## 2; \
+                vpxor                   x0 ## 2, x1 ## 2, x1 ## 2; \
+                vpslld $3,              x0 ## 2, x4 ## 2;          \
+                vpxor                   x4 ## 2, x3 ## 2, x3 ## 2; \
+        vpsrld $13,             x0 ## 1, x4 ## 1;          \
+        vpslld $(32 - 13),      x0 ## 1, x0 ## 1;          \
+        vpor                    x4 ## 1, x0 ## 1, x0 ## 1; \
+        vpxor                   x2 ## 1, x1 ## 1, x1 ## 1; \
+        vpxor                   x2 ## 1, x3 ## 1, x3 ## 1; \
+        vpsrld $3,              x2 ## 1, x4 ## 1;          \
+        vpslld $(32 - 3),       x2 ## 1, x2 ## 1;          \
+        vpor                    x4 ## 1, x2 ## 1, x2 ## 1; \
+                vpsrld $13,             x0 ## 2, x4 ## 2;          \
+                vpslld $(32 - 13),      x0 ## 2, x0 ## 2;          \
+                vpor                    x4 ## 2, x0 ## 2, x0 ## 2; \
+                vpxor                   x2 ## 2, x1 ## 2, x1 ## 2; \
+                vpxor                   x2 ## 2, x3 ## 2, x3 ## 2; \
+                vpsrld $3,              x2 ## 2, x4 ## 2;          \
+                vpslld $(32 - 3),       x2 ## 2, x2 ## 2;          \
+                vpor                    x4 ## 2, x2 ## 2, x2 ## 2;
+
+#define S(SBOX, x0, x1, x2, x3, x4) \
+        SBOX ## _1(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
+        SBOX ## _2(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
+        SBOX ## _1(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2); \
+        SBOX ## _2(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2);
+
+#define SP(SBOX, x0, x1, x2, x3, x4, i) \
+        get_key(i, 0, RK0); \
+        SBOX ## _1(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
+        get_key(i, 2, RK2); \
+        SBOX ## _2(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
+        get_key(i, 3, RK3); \
+        SBOX ## _1(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2); \
+        get_key(i, 1, RK1); \
+        SBOX ## _2(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2); \
+
+#define transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
+        vpunpckldq              x1, x0, t0; \
+        vpunpckhdq              x1, x0, t2; \
+        vpunpckldq              x3, x2, t1; \
+        vpunpckhdq              x3, x2, x3; \
+        \
+        vpunpcklqdq             t1, t0, x0; \
+        vpunpckhqdq             t1, t0, x1; \
+        vpunpcklqdq             x3, t2, x2; \
+        vpunpckhqdq             x3, t2, x3;
+
+#define read_blocks(x0, x1, x2, x3, t0, t1, t2) \
+        transpose_4x4(x0, x1, x2, x3, t0, t1, t2)
+
+#define write_blocks(x0, x1, x2, x3, t0, t1, t2) \
+        transpose_4x4(x0, x1, x2, x3, t0, t1, t2)
+
+.align 8
+__serpent_enc_blk16:
+        /* input:
+         *      %rdi: ctx, CTX
+         *      RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2: plaintext
+         * output:
+         *      RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2: ciphertext
+         */
+
+        vpcmpeqd RNOT, RNOT, RNOT;
+
+        read_blocks(RA1, RB1, RC1, RD1, RK0, RK1, RK2);
+        read_blocks(RA2, RB2, RC2, RD2, RK0, RK1, RK2);
+
+                                                 K2(RA, RB, RC, RD, RE, 0);
+        S(S0, RA, RB, RC, RD, RE);              LK2(RC, RB, RD, RA, RE, 1);
+        S(S1, RC, RB, RD, RA, RE);              LK2(RE, RD, RA, RC, RB, 2);
+        S(S2, RE, RD, RA, RC, RB);              LK2(RB, RD, RE, RC, RA, 3);
+        S(S3, RB, RD, RE, RC, RA);              LK2(RC, RA, RD, RB, RE, 4);
+        S(S4, RC, RA, RD, RB, RE);              LK2(RA, RD, RB, RE, RC, 5);
+        S(S5, RA, RD, RB, RE, RC);              LK2(RC, RA, RD, RE, RB, 6);
+        S(S6, RC, RA, RD, RE, RB);              LK2(RD, RB, RA, RE, RC, 7);
+        S(S7, RD, RB, RA, RE, RC);              LK2(RC, RA, RE, RD, RB, 8);
+        S(S0, RC, RA, RE, RD, RB);              LK2(RE, RA, RD, RC, RB, 9);
+        S(S1, RE, RA, RD, RC, RB);              LK2(RB, RD, RC, RE, RA, 10);
+        S(S2, RB, RD, RC, RE, RA);              LK2(RA, RD, RB, RE, RC, 11);
+        S(S3, RA, RD, RB, RE, RC);              LK2(RE, RC, RD, RA, RB, 12);
+        S(S4, RE, RC, RD, RA, RB);              LK2(RC, RD, RA, RB, RE, 13);
+        S(S5, RC, RD, RA, RB, RE);              LK2(RE, RC, RD, RB, RA, 14);
+        S(S6, RE, RC, RD, RB, RA);              LK2(RD, RA, RC, RB, RE, 15);
+        S(S7, RD, RA, RC, RB, RE);              LK2(RE, RC, RB, RD, RA, 16);
+        S(S0, RE, RC, RB, RD, RA);              LK2(RB, RC, RD, RE, RA, 17);
+        S(S1, RB, RC, RD, RE, RA);              LK2(RA, RD, RE, RB, RC, 18);
+        S(S2, RA, RD, RE, RB, RC);              LK2(RC, RD, RA, RB, RE, 19);
+        S(S3, RC, RD, RA, RB, RE);              LK2(RB, RE, RD, RC, RA, 20);
+        S(S4, RB, RE, RD, RC, RA);              LK2(RE, RD, RC, RA, RB, 21);
+        S(S5, RE, RD, RC, RA, RB);              LK2(RB, RE, RD, RA, RC, 22);
+        S(S6, RB, RE, RD, RA, RC);              LK2(RD, RC, RE, RA, RB, 23);
+        S(S7, RD, RC, RE, RA, RB);              LK2(RB, RE, RA, RD, RC, 24);
+        S(S0, RB, RE, RA, RD, RC);              LK2(RA, RE, RD, RB, RC, 25);
+        S(S1, RA, RE, RD, RB, RC);              LK2(RC, RD, RB, RA, RE, 26);
+        S(S2, RC, RD, RB, RA, RE);              LK2(RE, RD, RC, RA, RB, 27);
+        S(S3, RE, RD, RC, RA, RB);              LK2(RA, RB, RD, RE, RC, 28);
+        S(S4, RA, RB, RD, RE, RC);              LK2(RB, RD, RE, RC, RA, 29);
+        S(S5, RB, RD, RE, RC, RA);              LK2(RA, RB, RD, RC, RE, 30);
+        S(S6, RA, RB, RD, RC, RE);              LK2(RD, RE, RB, RC, RA, 31);
+        S(S7, RD, RE, RB, RC, RA);               K2(RA, RB, RC, RD, RE, 32);
+
+        write_blocks(RA1, RB1, RC1, RD1, RK0, RK1, RK2);
+        write_blocks(RA2, RB2, RC2, RD2, RK0, RK1, RK2);
+
+        ret;
+ENDPROC(__serpent_enc_blk16)
+
+.align 8
+__serpent_dec_blk16:
+        /* input:
+         *      %rdi: ctx, CTX
+         *      RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2: ciphertext
+         * output:
+         *      RC1, RD1, RB1, RE1, RC2, RD2, RB2, RE2: plaintext
+         */
+
+        vpcmpeqd RNOT, RNOT, RNOT;
+
+        read_blocks(RA1, RB1, RC1, RD1, RK0, RK1, RK2);
+        read_blocks(RA2, RB2, RC2, RD2, RK0, RK1, RK2);
+
+                                                 K2(RA, RB, RC, RD, RE, 32);
+        SP(SI7, RA, RB, RC, RD, RE, 31);        KL2(RB, RD, RA, RE, RC, 31);
+        SP(SI6, RB, RD, RA, RE, RC, 30);        KL2(RA, RC, RE, RB, RD, 30);
+        SP(SI5, RA, RC, RE, RB, RD, 29);        KL2(RC, RD, RA, RE, RB, 29);
+        SP(SI4, RC, RD, RA, RE, RB, 28);        KL2(RC, RA, RB, RE, RD, 28);
+        SP(SI3, RC, RA, RB, RE, RD, 27);        KL2(RB, RC, RD, RE, RA, 27);
+        SP(SI2, RB, RC, RD, RE, RA, 26);        KL2(RC, RA, RE, RD, RB, 26);
+        SP(SI1, RC, RA, RE, RD, RB, 25);        KL2(RB, RA, RE, RD, RC, 25);
+        SP(SI0, RB, RA, RE, RD, RC, 24);        KL2(RE, RC, RA, RB, RD, 24);
+        SP(SI7, RE, RC, RA, RB, RD, 23);        KL2(RC, RB, RE, RD, RA, 23);
+        SP(SI6, RC, RB, RE, RD, RA, 22);        KL2(RE, RA, RD, RC, RB, 22);
+        SP(SI5, RE, RA, RD, RC, RB, 21);        KL2(RA, RB, RE, RD, RC, 21);
+        SP(SI4, RA, RB, RE, RD, RC, 20);        KL2(RA, RE, RC, RD, RB, 20);
+        SP(SI3, RA, RE, RC, RD, RB, 19);        KL2(RC, RA, RB, RD, RE, 19);
+        SP(SI2, RC, RA, RB, RD, RE, 18);        KL2(RA, RE, RD, RB, RC, 18);
+        SP(SI1, RA, RE, RD, RB, RC, 17);        KL2(RC, RE, RD, RB, RA, 17);
+        SP(SI0, RC, RE, RD, RB, RA, 16);        KL2(RD, RA, RE, RC, RB, 16);
+        SP(SI7, RD, RA, RE, RC, RB, 15);        KL2(RA, RC, RD, RB, RE, 15);
+        SP(SI6, RA, RC, RD, RB, RE, 14);        KL2(RD, RE, RB, RA, RC, 14);
+        SP(SI5, RD, RE, RB, RA, RC, 13);        KL2(RE, RC, RD, RB, RA, 13);
+        SP(SI4, RE, RC, RD, RB, RA, 12);        KL2(RE, RD, RA, RB, RC, 12);
+        SP(SI3, RE, RD, RA, RB, RC, 11);        KL2(RA, RE, RC, RB, RD, 11);
+        SP(SI2, RA, RE, RC, RB, RD, 10);        KL2(RE, RD, RB, RC, RA, 10);
+        SP(SI1, RE, RD, RB, RC, RA, 9);         KL2(RA, RD, RB, RC, RE, 9);
+        SP(SI0, RA, RD, RB, RC, RE, 8);         KL2(RB, RE, RD, RA, RC, 8);
+        SP(SI7, RB, RE, RD, RA, RC, 7);         KL2(RE, RA, RB, RC, RD, 7);
+        SP(SI6, RE, RA, RB, RC, RD, 6);         KL2(RB, RD, RC, RE, RA, 6);
+        SP(SI5, RB, RD, RC, RE, RA, 5);         KL2(RD, RA, RB, RC, RE, 5);
+        SP(SI4, RD, RA, RB, RC, RE, 4);         KL2(RD, RB, RE, RC, RA, 4);
+        SP(SI3, RD, RB, RE, RC, RA, 3);         KL2(RE, RD, RA, RC, RB, 3);
+        SP(SI2, RE, RD, RA, RC, RB, 2);         KL2(RD, RB, RC, RA, RE, 2);
+        SP(SI1, RD, RB, RC, RA, RE, 1);         KL2(RE, RB, RC, RA, RD, 1);
+        S(SI0, RE, RB, RC, RA, RD);              K2(RC, RD, RB, RE, RA, 0);
+
+        write_blocks(RC1, RD1, RB1, RE1, RK0, RK1, RK2);
+        write_blocks(RC2, RD2, RB2, RE2, RK0, RK1, RK2);
+
+        ret;
+ENDPROC(__serpent_dec_blk16)
+
+ENTRY(serpent_ecb_enc_16way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         */
+
+        vzeroupper;
+
+        load_16way(%rdx, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2);
+
+        call __serpent_enc_blk16;
+
+        store_16way(%rsi, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2);
+
+        vzeroupper;
+
+        ret;
+ENDPROC(serpent_ecb_enc_16way)
+
+ENTRY(serpent_ecb_dec_16way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         */
+
+        vzeroupper;
+
+        load_16way(%rdx, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2);
+
+        call __serpent_dec_blk16;
+
+        store_16way(%rsi, RC1, RD1, RB1, RE1, RC2, RD2, RB2, RE2);
+
+        vzeroupper;
+
+        ret;
+ENDPROC(serpent_ecb_dec_16way)
+
+ENTRY(serpent_cbc_dec_16way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         */
+
+        vzeroupper;
+
+        load_16way(%rdx, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2);
+
+        call __serpent_dec_blk16;
+
+        store_cbc_16way(%rdx, %rsi, RC1, RD1, RB1, RE1, RC2, RD2, RB2, RE2,
+                        RK0);
+
+        vzeroupper;
+
+        ret;
+ENDPROC(serpent_cbc_dec_16way)
+
+ENTRY(serpent_ctr_16way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst (16 blocks)
+         *      %rdx: src (16 blocks)
+         *      %rcx: iv (little endian, 128bit)
+         */
+
+        vzeroupper;
+
+        load_ctr_16way(%rcx, .Lbswap128_mask, RA1, RB1, RC1, RD1, RA2, RB2, RC2,
+                       RD2, RK0, RK0x, RK1, RK1x, RK2, RK2x, RK3, RK3x, RNOT,
+                       tp);
+
+        call __serpent_enc_blk16;
+
+        store_ctr_16way(%rdx, %rsi, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2);
+
+        vzeroupper;
+
+        ret;
+ENDPROC(serpent_ctr_16way)
+
+ENTRY(serpent_xts_enc_16way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst (16 blocks)
+         *      %rdx: src (16 blocks)
+         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
+         */
+
+        vzeroupper;
+
+        load_xts_16way(%rcx, %rdx, %rsi, RA1, RB1, RC1, RD1, RA2, RB2, RC2,
+                       RD2, RK0, RK0x, RK1, RK1x, RK2, RK2x, RK3, RK3x, RNOT,
+                       .Lxts_gf128mul_and_shl1_mask_0,
+                       .Lxts_gf128mul_and_shl1_mask_1);
+
+        call __serpent_enc_blk16;
+
+        store_xts_16way(%rsi, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2);
+
+        vzeroupper;
+
+        ret;
+ENDPROC(serpent_xts_enc_16way)
+
+ENTRY(serpent_xts_dec_16way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst (16 blocks)
+         *      %rdx: src (16 blocks)
+         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
+         */
+
+        vzeroupper;
+
+        load_xts_16way(%rcx, %rdx, %rsi, RA1, RB1, RC1, RD1, RA2, RB2, RC2,
+                       RD2, RK0, RK0x, RK1, RK1x, RK2, RK2x, RK3, RK3x, RNOT,
+                       .Lxts_gf128mul_and_shl1_mask_0,
+                       .Lxts_gf128mul_and_shl1_mask_1);
+
+        call __serpent_dec_blk16;
+
+        store_xts_16way(%rsi, RC1, RD1, RB1, RE1, RC2, RD2, RB2, RE2);
+
+        vzeroupper;
+
+        ret;
+ENDPROC(serpent_xts_dec_16way)
diff --git a/arch/x86/crypto/serpent_avx2_glue.c b/arch/x86/crypto/serpent_avx2_glue.c
new file mode 100644
index 000000000000..23aabc6c20a5
--- /dev/null
+++ b/arch/x86/crypto/serpent_avx2_glue.c
@@ -0,0 +1,562 @@
+/*
+ * Glue Code for x86_64/AVX2 assembler optimized version of Serpent
+ *
+ * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/crypto.h>
+#include <linux/err.h>
+#include <crypto/algapi.h>
+#include <crypto/ctr.h>
+#include <crypto/lrw.h>
+#include <crypto/xts.h>
+#include <crypto/serpent.h>
+#include <asm/xcr.h>
+#include <asm/xsave.h>
+#include <asm/crypto/serpent-avx.h>
+#include <asm/crypto/ablk_helper.h>
+#include <asm/crypto/glue_helper.h>
+
+#define SERPENT_AVX2_PARALLEL_BLOCKS 16
+
+/* 16-way AVX2 parallel cipher functions */
+asmlinkage void serpent_ecb_enc_16way(struct serpent_ctx *ctx, u8 *dst,
+                                      const u8 *src);
+asmlinkage void serpent_ecb_dec_16way(struct serpent_ctx *ctx, u8 *dst,
+                                      const u8 *src);
+asmlinkage void serpent_cbc_dec_16way(void *ctx, u128 *dst, const u128 *src);
+
+asmlinkage void serpent_ctr_16way(void *ctx, u128 *dst, const u128 *src,
+                                  le128 *iv);
+asmlinkage void serpent_xts_enc_16way(struct serpent_ctx *ctx, u8 *dst,
+                                      const u8 *src, le128 *iv);
+asmlinkage void serpent_xts_dec_16way(struct serpent_ctx *ctx, u8 *dst,
+                                      const u8 *src, le128 *iv);
+
+static const struct common_glue_ctx serpent_enc = {
+        .num_funcs = 3,
+        .fpu_blocks_limit = 8,
+
+        .funcs = { {
+                .num_blocks = 16,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(serpent_ecb_enc_16way) }
+        }, {
+                .num_blocks = 8,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(serpent_ecb_enc_8way_avx) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(__serpent_encrypt) }
+        } }
+};
+
+static const struct common_glue_ctx serpent_ctr = {
+        .num_funcs = 3,
+        .fpu_blocks_limit = 8,
+
+        .funcs = { {
+                .num_blocks = 16,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(serpent_ctr_16way) }
+        },  {
+                .num_blocks = 8,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(serpent_ctr_8way_avx) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(__serpent_crypt_ctr) }
+        } }
+};
+
+static const struct common_glue_ctx serpent_enc_xts = {
+        .num_funcs = 3,
+        .fpu_blocks_limit = 8,
+
+        .funcs = { {
+                .num_blocks = 16,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(serpent_xts_enc_16way) }
+        }, {
+                .num_blocks = 8,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(serpent_xts_enc_8way_avx) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(serpent_xts_enc) }
+        } }
+};
+
+static const struct common_glue_ctx serpent_dec = {
+        .num_funcs = 3,
+        .fpu_blocks_limit = 8,
+
+        .funcs = { {
+                .num_blocks = 16,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(serpent_ecb_dec_16way) }
+        }, {
+                .num_blocks = 8,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(serpent_ecb_dec_8way_avx) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(__serpent_decrypt) }
+        } }
+};
+
+static const struct common_glue_ctx serpent_dec_cbc = {
+        .num_funcs = 3,
+        .fpu_blocks_limit = 8,
+
+        .funcs = { {
+                .num_blocks = 16,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(serpent_cbc_dec_16way) }
+        }, {
+                .num_blocks = 8,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(serpent_cbc_dec_8way_avx) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(__serpent_decrypt) }
+        } }
+};
+
+static const struct common_glue_ctx serpent_dec_xts = {
+        .num_funcs = 3,
+        .fpu_blocks_limit = 8,
+
+        .funcs = { {
+                .num_blocks = 16,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(serpent_xts_dec_16way) }
+        }, {
+                .num_blocks = 8,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(serpent_xts_dec_8way_avx) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(serpent_xts_dec) }
+        } }
+};
+
+static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_ecb_crypt_128bit(&serpent_enc, desc, dst, src, nbytes);
+}
+
+static int ecb_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_ecb_crypt_128bit(&serpent_dec, desc, dst, src, nbytes);
+}
+
+static int cbc_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_cbc_encrypt_128bit(GLUE_FUNC_CAST(__serpent_encrypt), desc,
+                                       dst, src, nbytes);
+}
+
+static int cbc_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_cbc_decrypt_128bit(&serpent_dec_cbc, desc, dst, src,
+                                       nbytes);
+}
+
+static int ctr_crypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                     struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_ctr_crypt_128bit(&serpent_ctr, desc, dst, src, nbytes);
+}
+
+static inline bool serpent_fpu_begin(bool fpu_enabled, unsigned int nbytes)
+{
+        /* since reusing AVX functions, starts using FPU at 8 parallel blocks */
+        return glue_fpu_begin(SERPENT_BLOCK_SIZE, 8, NULL, fpu_enabled, nbytes);
+}
+
+static inline void serpent_fpu_end(bool fpu_enabled)
+{
+        glue_fpu_end(fpu_enabled);
+}
+
+struct crypt_priv {
+        struct serpent_ctx *ctx;
+        bool fpu_enabled;
+};
+
+static void encrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
+{
+        const unsigned int bsize = SERPENT_BLOCK_SIZE;
+        struct crypt_priv *ctx = priv;
+        int i;
+
+        ctx->fpu_enabled = serpent_fpu_begin(ctx->fpu_enabled, nbytes);
+
+        if (nbytes >= SERPENT_AVX2_PARALLEL_BLOCKS * bsize) {
+                serpent_ecb_enc_16way(ctx->ctx, srcdst, srcdst);
+                srcdst += bsize * SERPENT_AVX2_PARALLEL_BLOCKS;
+                nbytes -= bsize * SERPENT_AVX2_PARALLEL_BLOCKS;
+        }
+
+        while (nbytes >= SERPENT_PARALLEL_BLOCKS * bsize) {
+                serpent_ecb_enc_8way_avx(ctx->ctx, srcdst, srcdst);
+                srcdst += bsize * SERPENT_PARALLEL_BLOCKS;
+                nbytes -= bsize * SERPENT_PARALLEL_BLOCKS;
+        }
+
+        for (i = 0; i < nbytes / bsize; i++, srcdst += bsize)
+                __serpent_encrypt(ctx->ctx, srcdst, srcdst);
+}
+
+static void decrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
+{
+        const unsigned int bsize = SERPENT_BLOCK_SIZE;
+        struct crypt_priv *ctx = priv;
+        int i;
+
+        ctx->fpu_enabled = serpent_fpu_begin(ctx->fpu_enabled, nbytes);
+
+        if (nbytes >= SERPENT_AVX2_PARALLEL_BLOCKS * bsize) {
+                serpent_ecb_dec_16way(ctx->ctx, srcdst, srcdst);
+                srcdst += bsize * SERPENT_AVX2_PARALLEL_BLOCKS;
+                nbytes -= bsize * SERPENT_AVX2_PARALLEL_BLOCKS;
+        }
+
+        while (nbytes >= SERPENT_PARALLEL_BLOCKS * bsize) {
+                serpent_ecb_dec_8way_avx(ctx->ctx, srcdst, srcdst);
+                srcdst += bsize * SERPENT_PARALLEL_BLOCKS;
+                nbytes -= bsize * SERPENT_PARALLEL_BLOCKS;
+        }
+
+        for (i = 0; i < nbytes / bsize; i++, srcdst += bsize)
+                __serpent_decrypt(ctx->ctx, srcdst, srcdst);
+}
+
+static int lrw_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct serpent_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+        be128 buf[SERPENT_AVX2_PARALLEL_BLOCKS];
+        struct crypt_priv crypt_ctx = {
+                .ctx = &ctx->serpent_ctx,
+                .fpu_enabled = false,
+        };
+        struct lrw_crypt_req req = {
+                .tbuf = buf,
+                .tbuflen = sizeof(buf),
+
+                .table_ctx = &ctx->lrw_table,
+                .crypt_ctx = &crypt_ctx,
+                .crypt_fn = encrypt_callback,
+        };
+        int ret;
+
+        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
+        ret = lrw_crypt(desc, dst, src, nbytes, &req);
+        serpent_fpu_end(crypt_ctx.fpu_enabled);
+
+        return ret;
+}
+
+static int lrw_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct serpent_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+        be128 buf[SERPENT_AVX2_PARALLEL_BLOCKS];
+        struct crypt_priv crypt_ctx = {
+                .ctx = &ctx->serpent_ctx,
+                .fpu_enabled = false,
+        };
+        struct lrw_crypt_req req = {
+                .tbuf = buf,
+                .tbuflen = sizeof(buf),
+
+                .table_ctx = &ctx->lrw_table,
+                .crypt_ctx = &crypt_ctx,
+                .crypt_fn = decrypt_callback,
+        };
+        int ret;
+
+        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
+        ret = lrw_crypt(desc, dst, src, nbytes, &req);
+        serpent_fpu_end(crypt_ctx.fpu_enabled);
+
+        return ret;
+}
+
+static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct serpent_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+
+        return glue_xts_crypt_128bit(&serpent_enc_xts, desc, dst, src, nbytes,
+                                     XTS_TWEAK_CAST(__serpent_encrypt),
+                                     &ctx->tweak_ctx, &ctx->crypt_ctx);
+}
+
+static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct serpent_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+
+        return glue_xts_crypt_128bit(&serpent_dec_xts, desc, dst, src, nbytes,
+                                     XTS_TWEAK_CAST(__serpent_encrypt),
+                                     &ctx->tweak_ctx, &ctx->crypt_ctx);
+}
+
+static struct crypto_alg srp_algs[10] = { {
+        .cra_name               = "__ecb-serpent-avx2",
+        .cra_driver_name        = "__driver-ecb-serpent-avx2",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = SERPENT_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct serpent_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(srp_algs[0].cra_list),
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE,
+                        .setkey         = serpent_setkey,
+                        .encrypt        = ecb_encrypt,
+                        .decrypt        = ecb_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "__cbc-serpent-avx2",
+        .cra_driver_name        = "__driver-cbc-serpent-avx2",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = SERPENT_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct serpent_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(srp_algs[1].cra_list),
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE,
+                        .setkey         = serpent_setkey,
+                        .encrypt        = cbc_encrypt,
+                        .decrypt        = cbc_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "__ctr-serpent-avx2",
+        .cra_driver_name        = "__driver-ctr-serpent-avx2",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = 1,
+        .cra_ctxsize            = sizeof(struct serpent_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(srp_algs[2].cra_list),
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE,
+                        .ivsize         = SERPENT_BLOCK_SIZE,
+                        .setkey         = serpent_setkey,
+                        .encrypt        = ctr_crypt,
+                        .decrypt        = ctr_crypt,
+                },
+        },
+}, {
+        .cra_name               = "__lrw-serpent-avx2",
+        .cra_driver_name        = "__driver-lrw-serpent-avx2",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = SERPENT_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct serpent_lrw_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(srp_algs[3].cra_list),
+        .cra_exit               = lrw_serpent_exit_tfm,
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE +
+                                          SERPENT_BLOCK_SIZE,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE +
+                                          SERPENT_BLOCK_SIZE,
+                        .ivsize         = SERPENT_BLOCK_SIZE,
+                        .setkey         = lrw_serpent_setkey,
+                        .encrypt        = lrw_encrypt,
+                        .decrypt        = lrw_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "__xts-serpent-avx2",
+        .cra_driver_name        = "__driver-xts-serpent-avx2",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = SERPENT_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct serpent_xts_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(srp_algs[4].cra_list),
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE * 2,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE * 2,
+                        .ivsize         = SERPENT_BLOCK_SIZE,
+                        .setkey         = xts_serpent_setkey,
+                        .encrypt        = xts_encrypt,
+                        .decrypt        = xts_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "ecb(serpent)",
+        .cra_driver_name        = "ecb-serpent-avx2",
+        .cra_priority           = 600,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = SERPENT_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(srp_algs[5].cra_list),
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "cbc(serpent)",
+        .cra_driver_name        = "cbc-serpent-avx2",
+        .cra_priority           = 600,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = SERPENT_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(srp_algs[6].cra_list),
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE,
+                        .ivsize         = SERPENT_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = __ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "ctr(serpent)",
+        .cra_driver_name        = "ctr-serpent-avx2",
+        .cra_priority           = 600,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = 1,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(srp_algs[7].cra_list),
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE,
+                        .ivsize         = SERPENT_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_encrypt,
+                        .geniv          = "chainiv",
+                },
+        },
+}, {
+        .cra_name               = "lrw(serpent)",
+        .cra_driver_name        = "lrw-serpent-avx2",
+        .cra_priority           = 600,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = SERPENT_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(srp_algs[8].cra_list),
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE +
+                                          SERPENT_BLOCK_SIZE,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE +
+                                          SERPENT_BLOCK_SIZE,
+                        .ivsize         = SERPENT_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "xts(serpent)",
+        .cra_driver_name        = "xts-serpent-avx2",
+        .cra_priority           = 600,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = SERPENT_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(srp_algs[9].cra_list),
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE * 2,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE * 2,
+                        .ivsize         = SERPENT_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+} };
+
+static int __init init(void)
+{
+        u64 xcr0;
+
+        if (!cpu_has_avx2 || !cpu_has_osxsave) {
+                pr_info("AVX2 instructions are not detected.\n");
+                return -ENODEV;
+        }
+
+        xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
+        if ((xcr0 & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM)) {
+                pr_info("AVX detected but unusable.\n");
+                return -ENODEV;
+        }
+
+        return crypto_register_algs(srp_algs, ARRAY_SIZE(srp_algs));
+}
+
+static void __exit fini(void)
+{
+        crypto_unregister_algs(srp_algs, ARRAY_SIZE(srp_algs));
+}
+
+module_init(init);
+module_exit(fini);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Serpent Cipher Algorithm, AVX2 optimized");
+MODULE_ALIAS("serpent");
+MODULE_ALIAS("serpent-asm");
diff --git a/arch/x86/crypto/serpent_avx_glue.c b/arch/x86/crypto/serpent_avx_glue.c
index 52abaaf28e7f..9ae83cf8d21e 100644
--- a/arch/x86/crypto/serpent_avx_glue.c
+++ b/arch/x86/crypto/serpent_avx_glue.c
@@ -4,8 +4,7 @@
  * Copyright (C) 2012 Johannes Goetzfried
  *     <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
  *
- * Glue code based on serpent_sse2_glue.c by:
- *  Copyright (C) 2011 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
+ * Copyright © 2011-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -42,7 +41,32 @@
 #include <asm/crypto/ablk_helper.h>
 #include <asm/crypto/glue_helper.h>
 
-static void serpent_crypt_ctr(void *ctx, u128 *dst, const u128 *src, le128 *iv)
+/* 8-way parallel cipher functions */
+asmlinkage void serpent_ecb_enc_8way_avx(struct serpent_ctx *ctx, u8 *dst,
+                                         const u8 *src);
+EXPORT_SYMBOL_GPL(serpent_ecb_enc_8way_avx);
+
+asmlinkage void serpent_ecb_dec_8way_avx(struct serpent_ctx *ctx, u8 *dst,
+                                         const u8 *src);
+EXPORT_SYMBOL_GPL(serpent_ecb_dec_8way_avx);
+
+asmlinkage void serpent_cbc_dec_8way_avx(struct serpent_ctx *ctx, u8 *dst,
+                                         const u8 *src);
+EXPORT_SYMBOL_GPL(serpent_cbc_dec_8way_avx);
+
+asmlinkage void serpent_ctr_8way_avx(struct serpent_ctx *ctx, u8 *dst,
+                                     const u8 *src, le128 *iv);
+EXPORT_SYMBOL_GPL(serpent_ctr_8way_avx);
+
+asmlinkage void serpent_xts_enc_8way_avx(struct serpent_ctx *ctx, u8 *dst,
+                                         const u8 *src, le128 *iv);
+EXPORT_SYMBOL_GPL(serpent_xts_enc_8way_avx);
+
+asmlinkage void serpent_xts_dec_8way_avx(struct serpent_ctx *ctx, u8 *dst,
+                                         const u8 *src, le128 *iv);
+EXPORT_SYMBOL_GPL(serpent_xts_dec_8way_avx);
+
+void __serpent_crypt_ctr(void *ctx, u128 *dst, const u128 *src, le128 *iv)
 {
         be128 ctrblk;
 
@@ -52,6 +76,22 @@ static void serpent_crypt_ctr(void *ctx, u128 *dst, const u128 *src, le128 *iv)
         __serpent_encrypt(ctx, (u8 *)&ctrblk, (u8 *)&ctrblk);
         u128_xor(dst, src, (u128 *)&ctrblk);
 }
+EXPORT_SYMBOL_GPL(__serpent_crypt_ctr);
+
+void serpent_xts_enc(void *ctx, u128 *dst, const u128 *src, le128 *iv)
+{
+        glue_xts_crypt_128bit_one(ctx, dst, src, iv,
+                                  GLUE_FUNC_CAST(__serpent_encrypt));
+}
+EXPORT_SYMBOL_GPL(serpent_xts_enc);
+
+void serpent_xts_dec(void *ctx, u128 *dst, const u128 *src, le128 *iv)
+{
+        glue_xts_crypt_128bit_one(ctx, dst, src, iv,
+                                  GLUE_FUNC_CAST(__serpent_decrypt));
+}
+EXPORT_SYMBOL_GPL(serpent_xts_dec);
+
 
 static const struct common_glue_ctx serpent_enc = {
         .num_funcs = 2,
@@ -75,7 +115,20 @@ static const struct common_glue_ctx serpent_ctr = {
                 .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(serpent_ctr_8way_avx) }
         }, {
                 .num_blocks = 1,
-                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(serpent_crypt_ctr) }
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(__serpent_crypt_ctr) }
+        } }
+};
+
+static const struct common_glue_ctx serpent_enc_xts = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = SERPENT_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = SERPENT_PARALLEL_BLOCKS,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(serpent_xts_enc_8way_avx) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(serpent_xts_enc) }
         } }
 };
 
@@ -105,6 +158,19 @@ static const struct common_glue_ctx serpent_dec_cbc = {
         } }
 };
 
+static const struct common_glue_ctx serpent_dec_xts = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = SERPENT_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = SERPENT_PARALLEL_BLOCKS,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(serpent_xts_dec_8way_avx) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(serpent_xts_dec) }
+        } }
+};
+
 static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
                        struct scatterlist *src, unsigned int nbytes)
 {
@@ -187,13 +253,8 @@ static void decrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
                 __serpent_decrypt(ctx->ctx, srcdst, srcdst);
 }
 
-struct serpent_lrw_ctx {
-        struct lrw_table_ctx lrw_table;
-        struct serpent_ctx serpent_ctx;
-};
-
-static int lrw_serpent_setkey(struct crypto_tfm *tfm, const u8 *key,
-                              unsigned int keylen)
+int lrw_serpent_setkey(struct crypto_tfm *tfm, const u8 *key,
+                       unsigned int keylen)
 {
         struct serpent_lrw_ctx *ctx = crypto_tfm_ctx(tfm);
         int err;
@@ -206,6 +267,7 @@ static int lrw_serpent_setkey(struct crypto_tfm *tfm, const u8 *key,
         return lrw_init_table(&ctx->lrw_table, key + keylen -
                                                 SERPENT_BLOCK_SIZE);
 }
+EXPORT_SYMBOL_GPL(lrw_serpent_setkey);
 
 static int lrw_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
                        struct scatterlist *src, unsigned int nbytes)
@@ -259,20 +321,16 @@ static int lrw_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
         return ret;
 }
 
-static void lrw_exit_tfm(struct crypto_tfm *tfm)
+void lrw_serpent_exit_tfm(struct crypto_tfm *tfm)
 {
         struct serpent_lrw_ctx *ctx = crypto_tfm_ctx(tfm);
 
         lrw_free_table(&ctx->lrw_table);
 }
+EXPORT_SYMBOL_GPL(lrw_serpent_exit_tfm);
 
-struct serpent_xts_ctx {
-        struct serpent_ctx tweak_ctx;
-        struct serpent_ctx crypt_ctx;
-};
-
-static int xts_serpent_setkey(struct crypto_tfm *tfm, const u8 *key,
-                              unsigned int keylen)
+int xts_serpent_setkey(struct crypto_tfm *tfm, const u8 *key,
+                       unsigned int keylen)
 {
         struct serpent_xts_ctx *ctx = crypto_tfm_ctx(tfm);
         u32 *flags = &tfm->crt_flags;
@@ -294,59 +352,26 @@ static int xts_serpent_setkey(struct crypto_tfm *tfm, const u8 *key,
         /* second half of xts-key is for tweak */
         return __serpent_setkey(&ctx->tweak_ctx, key + keylen / 2, keylen / 2);
 }
+EXPORT_SYMBOL_GPL(xts_serpent_setkey);
 
 static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
                        struct scatterlist *src, unsigned int nbytes)
 {
         struct serpent_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        be128 buf[SERPENT_PARALLEL_BLOCKS];
-        struct crypt_priv crypt_ctx = {
-                .ctx = &ctx->crypt_ctx,
-                .fpu_enabled = false,
-        };
-        struct xts_crypt_req req = {
-                .tbuf = buf,
-                .tbuflen = sizeof(buf),
-
-                .tweak_ctx = &ctx->tweak_ctx,
-                .tweak_fn = XTS_TWEAK_CAST(__serpent_encrypt),
-                .crypt_ctx = &crypt_ctx,
-                .crypt_fn = encrypt_callback,
-        };
-        int ret;
-
-        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
-        ret = xts_crypt(desc, dst, src, nbytes, &req);
-        serpent_fpu_end(crypt_ctx.fpu_enabled);
 
-        return ret;
+        return glue_xts_crypt_128bit(&serpent_enc_xts, desc, dst, src, nbytes,
+                                     XTS_TWEAK_CAST(__serpent_encrypt),
+                                     &ctx->tweak_ctx, &ctx->crypt_ctx);
 }
 
 static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
                        struct scatterlist *src, unsigned int nbytes)
 {
         struct serpent_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        be128 buf[SERPENT_PARALLEL_BLOCKS];
-        struct crypt_priv crypt_ctx = {
-                .ctx = &ctx->crypt_ctx,
-                .fpu_enabled = false,
-        };
-        struct xts_crypt_req req = {
-                .tbuf = buf,
-                .tbuflen = sizeof(buf),
-
-                .tweak_ctx = &ctx->tweak_ctx,
-                .tweak_fn = XTS_TWEAK_CAST(__serpent_encrypt),
-                .crypt_ctx = &crypt_ctx,
-                .crypt_fn = decrypt_callback,
-        };
-        int ret;
 
-        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
-        ret = xts_crypt(desc, dst, src, nbytes, &req);
-        serpent_fpu_end(crypt_ctx.fpu_enabled);
-
-        return ret;
+        return glue_xts_crypt_128bit(&serpent_dec_xts, desc, dst, src, nbytes,
+                                     XTS_TWEAK_CAST(__serpent_encrypt),
+                                     &ctx->tweak_ctx, &ctx->crypt_ctx);
 }
 
 static struct crypto_alg serpent_algs[10] = { {
@@ -417,7 +442,7 @@ static struct crypto_alg serpent_algs[10] = { {
         .cra_alignmask          = 0,
         .cra_type               = &crypto_blkcipher_type,
         .cra_module             = THIS_MODULE,
-        .cra_exit               = lrw_exit_tfm,
+        .cra_exit               = lrw_serpent_exit_tfm,
         .cra_u = {
                 .blkcipher = {
                         .min_keysize    = SERPENT_MIN_KEY_SIZE +
diff --git a/arch/x86/crypto/sha256-avx-asm.S b/arch/x86/crypto/sha256-avx-asm.S
new file mode 100644
index 000000000000..56610c4bf31b
--- /dev/null
+++ b/arch/x86/crypto/sha256-avx-asm.S
@@ -0,0 +1,496 @@
+########################################################################
+# Implement fast SHA-256 with AVX1 instructions. (x86_64)
+#
+# Copyright (C) 2013 Intel Corporation.
+#
+# Authors:
+#     James Guilford <james.guilford@intel.com>
+#     Kirk Yap <kirk.s.yap@intel.com>
+#     Tim Chen <tim.c.chen@linux.intel.com>
+#
+# This software is available to you under a choice of one of two
+# licenses.  You may choose to be licensed under the terms of the GNU
+# General Public License (GPL) Version 2, available from the file
+# COPYING in the main directory of this source tree, or the
+# OpenIB.org BSD license below:
+#
+#     Redistribution and use in source and binary forms, with or
+#     without modification, are permitted provided that the following
+#     conditions are met:
+#
+#      - Redistributions of source code must retain the above
+#        copyright notice, this list of conditions and the following
+#        disclaimer.
+#
+#      - Redistributions in binary form must reproduce the above
+#        copyright notice, this list of conditions and the following
+#        disclaimer in the documentation and/or other materials
+#        provided with the distribution.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+########################################################################
+#
+# This code is described in an Intel White-Paper:
+# "Fast SHA-256 Implementations on Intel Architecture Processors"
+#
+# To find it, surf to http://www.intel.com/p/en_US/embedded
+# and search for that title.
+#
+########################################################################
+# This code schedules 1 block at a time, with 4 lanes per block
+########################################################################
+
+#ifdef CONFIG_AS_AVX
+#include <linux/linkage.h>
+
+## assume buffers not aligned
+#define    VMOVDQ vmovdqu
+
+################################ Define Macros
+
+# addm [mem], reg
+# Add reg to mem using reg-mem add and store
+.macro addm p1 p2
+        add     \p1, \p2
+        mov     \p2, \p1
+.endm
+
+
+.macro MY_ROR p1 p2
+        shld    $(32-(\p1)), \p2, \p2
+.endm
+
+################################
+
+# COPY_XMM_AND_BSWAP xmm, [mem], byte_flip_mask
+# Load xmm with mem and byte swap each dword
+.macro COPY_XMM_AND_BSWAP p1 p2 p3
+        VMOVDQ \p2, \p1
+        vpshufb \p3, \p1, \p1
+.endm
+
+################################
+
+X0 = %xmm4
+X1 = %xmm5
+X2 = %xmm6
+X3 = %xmm7
+
+XTMP0 = %xmm0
+XTMP1 = %xmm1
+XTMP2 = %xmm2
+XTMP3 = %xmm3
+XTMP4 = %xmm8
+XFER = %xmm9
+XTMP5 = %xmm11
+
+SHUF_00BA = %xmm10      # shuffle xBxA -> 00BA
+SHUF_DC00 = %xmm12      # shuffle xDxC -> DC00
+BYTE_FLIP_MASK = %xmm13
+
+NUM_BLKS = %rdx   # 3rd arg
+CTX = %rsi        # 2nd arg
+INP = %rdi        # 1st arg
+
+SRND = %rdi       # clobbers INP
+c = %ecx
+d = %r8d
+e = %edx
+TBL = %rbp
+a = %eax
+b = %ebx
+
+f = %r9d
+g = %r10d
+h = %r11d
+
+y0 = %r13d
+y1 = %r14d
+y2 = %r15d
+
+
+_INP_END_SIZE = 8
+_INP_SIZE = 8
+_XFER_SIZE = 8
+_XMM_SAVE_SIZE = 0
+
+_INP_END = 0
+_INP            = _INP_END  + _INP_END_SIZE
+_XFER           = _INP      + _INP_SIZE
+_XMM_SAVE       = _XFER     + _XFER_SIZE
+STACK_SIZE      = _XMM_SAVE + _XMM_SAVE_SIZE
+
+# rotate_Xs
+# Rotate values of symbols X0...X3
+.macro rotate_Xs
+X_ = X0
+X0 = X1
+X1 = X2
+X2 = X3
+X3 = X_
+.endm
+
+# ROTATE_ARGS
+# Rotate values of symbols a...h
+.macro ROTATE_ARGS
+TMP_ = h
+h = g
+g = f
+f = e
+e = d
+d = c
+c = b
+b = a
+a = TMP_
+.endm
+
+.macro FOUR_ROUNDS_AND_SCHED
+        ## compute s0 four at a time and s1 two at a time
+        ## compute W[-16] + W[-7] 4 at a time
+
+        mov     e, y0                   # y0 = e
+        MY_ROR  (25-11), y0             # y0 = e >> (25-11)
+        mov     a, y1                   # y1 = a
+        vpalignr $4, X2, X3, XTMP0      # XTMP0 = W[-7]
+        MY_ROR  (22-13), y1             # y1 = a >> (22-13)
+        xor     e, y0                   # y0 = e ^ (e >> (25-11))
+        mov     f, y2                   # y2 = f
+        MY_ROR  (11-6), y0              # y0 = (e >> (11-6)) ^ (e >> (25-6))
+        xor     a, y1                   # y1 = a ^ (a >> (22-13)
+        xor     g, y2                   # y2 = f^g
+        vpaddd  X0, XTMP0, XTMP0        # XTMP0 = W[-7] + W[-16]
+        xor     e, y0                   # y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
+        and     e, y2                   # y2 = (f^g)&e
+        MY_ROR  (13-2), y1              # y1 = (a >> (13-2)) ^ (a >> (22-2))
+        ## compute s0
+        vpalignr $4, X0, X1, XTMP1      # XTMP1 = W[-15]
+        xor     a, y1                   # y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
+        MY_ROR  6, y0                   # y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
+        xor     g, y2                   # y2 = CH = ((f^g)&e)^g
+        MY_ROR  2, y1                   # y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
+        add     y0, y2                  # y2 = S1 + CH
+        add     _XFER(%rsp), y2         # y2 = k + w + S1 + CH
+        mov     a, y0                   # y0 = a
+        add     y2, h                   # h = h + S1 + CH + k + w
+        mov     a, y2                   # y2 = a
+        vpsrld  $7, XTMP1, XTMP2
+        or      c, y0                   # y0 = a|c
+        add     h, d                    # d = d + h + S1 + CH + k + w
+        and     c, y2                   # y2 = a&c
+        vpslld  $(32-7), XTMP1, XTMP3
+        and     b, y0                   # y0 = (a|c)&b
+        add     y1, h                   # h = h + S1 + CH + k + w + S0
+        vpor    XTMP2, XTMP3, XTMP3     # XTMP1 = W[-15] MY_ROR 7
+        or      y2, y0                  # y0 = MAJ = (a|c)&b)|(a&c)
+        add     y0, h                   # h = h + S1 + CH + k + w + S0 + MAJ
+        ROTATE_ARGS
+        mov     e, y0                   # y0 = e
+        mov     a, y1                   # y1 = a
+        MY_ROR  (25-11), y0             # y0 = e >> (25-11)
+        xor     e, y0                   # y0 = e ^ (e >> (25-11))
+        mov     f, y2                   # y2 = f
+        MY_ROR  (22-13), y1             # y1 = a >> (22-13)
+        vpsrld  $18, XTMP1, XTMP2       #
+        xor     a, y1                   # y1 = a ^ (a >> (22-13)
+        MY_ROR  (11-6), y0              # y0 = (e >> (11-6)) ^ (e >> (25-6))
+        xor     g, y2                   # y2 = f^g
+        vpsrld  $3, XTMP1, XTMP4        # XTMP4 = W[-15] >> 3
+        MY_ROR  (13-2), y1              # y1 = (a >> (13-2)) ^ (a >> (22-2))
+        xor     e, y0                   # y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
+        and     e, y2                   # y2 = (f^g)&e
+        MY_ROR  6, y0                   # y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
+        vpslld  $(32-18), XTMP1, XTMP1
+        xor     a, y1                   # y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
+        xor     g, y2                   # y2 = CH = ((f^g)&e)^g
+        vpxor   XTMP1, XTMP3, XTMP3     #
+        add     y0, y2                  # y2 = S1 + CH
+        add     (1*4 + _XFER)(%rsp), y2 # y2 = k + w + S1 + CH
+        MY_ROR  2, y1                   # y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
+        vpxor   XTMP2, XTMP3, XTMP3     # XTMP1 = W[-15] MY_ROR 7 ^ W[-15] MY_ROR
+        mov     a, y0                   # y0 = a
+        add     y2, h                   # h = h + S1 + CH + k + w
+        mov     a, y2                   # y2 = a
+        vpxor   XTMP4, XTMP3, XTMP1     # XTMP1 = s0
+        or      c, y0                   # y0 = a|c
+        add     h, d                    # d = d + h + S1 + CH + k + w
+        and     c, y2                   # y2 = a&c
+        ## compute low s1
+        vpshufd $0b11111010, X3, XTMP2  # XTMP2 = W[-2] {BBAA}
+        and     b, y0                   # y0 = (a|c)&b
+        add     y1, h                   # h = h + S1 + CH + k + w + S0
+        vpaddd  XTMP1, XTMP0, XTMP0     # XTMP0 = W[-16] + W[-7] + s0
+        or      y2, y0                  # y0 = MAJ = (a|c)&b)|(a&c)
+        add     y0, h                   # h = h + S1 + CH + k + w + S0 + MAJ
+        ROTATE_ARGS
+        mov     e, y0                   # y0 = e
+        mov     a, y1                   # y1 = a
+        MY_ROR  (25-11), y0             # y0 = e >> (25-11)
+        xor     e, y0                   # y0 = e ^ (e >> (25-11))
+        MY_ROR  (22-13), y1             # y1 = a >> (22-13)
+        mov     f, y2                   # y2 = f
+        xor     a, y1                   # y1 = a ^ (a >> (22-13)
+        MY_ROR  (11-6), y0              # y0 = (e >> (11-6)) ^ (e >> (25-6))
+        vpsrld  $10, XTMP2, XTMP4       # XTMP4 = W[-2] >> 10 {BBAA}
+        xor     g, y2                   # y2 = f^g
+        vpsrlq  $19, XTMP2, XTMP3       # XTMP3 = W[-2] MY_ROR 19 {xBxA}
+        xor     e, y0                   # y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
+        and     e, y2                   # y2 = (f^g)&e
+        vpsrlq  $17, XTMP2, XTMP2       # XTMP2 = W[-2] MY_ROR 17 {xBxA}
+        MY_ROR  (13-2), y1              # y1 = (a >> (13-2)) ^ (a >> (22-2))
+        xor     a, y1                   # y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
+        xor     g, y2                   # y2 = CH = ((f^g)&e)^g
+        MY_ROR  6, y0                   # y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
+        vpxor   XTMP3, XTMP2, XTMP2     #
+        add     y0, y2                  # y2 = S1 + CH
+        MY_ROR  2, y1                   # y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
+        add     (2*4 + _XFER)(%rsp), y2 # y2 = k + w + S1 + CH
+        vpxor   XTMP2, XTMP4, XTMP4     # XTMP4 = s1 {xBxA}
+        mov     a, y0                   # y0 = a
+        add     y2, h                   # h = h + S1 + CH + k + w
+        mov     a, y2                   # y2 = a
+        vpshufb SHUF_00BA, XTMP4, XTMP4 # XTMP4 = s1 {00BA}
+        or      c, y0                   # y0 = a|c
+        add     h, d                    # d = d + h + S1 + CH + k + w
+        and     c, y2                   # y2 = a&c
+        vpaddd  XTMP4, XTMP0, XTMP0     # XTMP0 = {..., ..., W[1], W[0]}
+        and     b, y0                   # y0 = (a|c)&b
+        add     y1, h                   # h = h + S1 + CH + k + w + S0
+        ## compute high s1
+        vpshufd $0b01010000, XTMP0, XTMP2 # XTMP2 = W[-2] {DDCC}
+        or      y2, y0                  # y0 = MAJ = (a|c)&b)|(a&c)
+        add     y0, h                   # h = h + S1 + CH + k + w + S0 + MAJ
+        ROTATE_ARGS
+        mov     e, y0                   # y0 = e
+        MY_ROR  (25-11), y0             # y0 = e >> (25-11)
+        mov     a, y1                   # y1 = a
+        MY_ROR  (22-13), y1             # y1 = a >> (22-13)
+        xor     e, y0                   # y0 = e ^ (e >> (25-11))
+        mov     f, y2                   # y2 = f
+        MY_ROR  (11-6), y0              # y0 = (e >> (11-6)) ^ (e >> (25-6))
+        vpsrld  $10, XTMP2, XTMP5       # XTMP5 = W[-2] >> 10 {DDCC}
+        xor     a, y1                   # y1 = a ^ (a >> (22-13)
+        xor     g, y2                   # y2 = f^g
+        vpsrlq  $19, XTMP2, XTMP3       # XTMP3 = W[-2] MY_ROR 19 {xDxC}
+        xor     e, y0                   # y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
+        and     e, y2                   # y2 = (f^g)&e
+        MY_ROR  (13-2), y1              # y1 = (a >> (13-2)) ^ (a >> (22-2))
+        vpsrlq  $17, XTMP2, XTMP2       # XTMP2 = W[-2] MY_ROR 17 {xDxC}
+        xor     a, y1                   # y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
+        MY_ROR  6, y0                   # y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
+        xor     g, y2                   # y2 = CH = ((f^g)&e)^g
+        vpxor   XTMP3, XTMP2, XTMP2
+        MY_ROR  2, y1                   # y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
+        add     y0, y2                  # y2 = S1 + CH
+        add     (3*4 + _XFER)(%rsp), y2 # y2 = k + w + S1 + CH
+        vpxor   XTMP2, XTMP5, XTMP5     # XTMP5 = s1 {xDxC}
+        mov     a, y0                   # y0 = a
+        add     y2, h                   # h = h + S1 + CH + k + w
+        mov     a, y2                   # y2 = a
+        vpshufb SHUF_DC00, XTMP5, XTMP5 # XTMP5 = s1 {DC00}
+        or      c, y0                   # y0 = a|c
+        add     h, d                    # d = d + h + S1 + CH + k + w
+        and     c, y2                   # y2 = a&c
+        vpaddd  XTMP0, XTMP5, X0        # X0 = {W[3], W[2], W[1], W[0]}
+        and     b, y0                   # y0 = (a|c)&b
+        add     y1, h                   # h = h + S1 + CH + k + w + S0
+        or      y2, y0                  # y0 = MAJ = (a|c)&b)|(a&c)
+        add     y0, h                   # h = h + S1 + CH + k + w + S0 + MAJ
+        ROTATE_ARGS
+        rotate_Xs
+.endm
+
+## input is [rsp + _XFER + %1 * 4]
+.macro DO_ROUND round
+        mov     e, y0                   # y0 = e
+        MY_ROR  (25-11), y0             # y0 = e >> (25-11)
+        mov     a, y1                   # y1 = a
+        xor     e, y0                   # y0 = e ^ (e >> (25-11))
+        MY_ROR  (22-13), y1             # y1 = a >> (22-13)
+        mov     f, y2                   # y2 = f
+        xor     a, y1                   # y1 = a ^ (a >> (22-13)
+        MY_ROR  (11-6), y0              # y0 = (e >> (11-6)) ^ (e >> (25-6))
+        xor     g, y2                   # y2 = f^g
+        xor     e, y0                   # y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
+        MY_ROR  (13-2), y1              # y1 = (a >> (13-2)) ^ (a >> (22-2))
+        and     e, y2                   # y2 = (f^g)&e
+        xor     a, y1                   # y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
+        MY_ROR  6, y0                   # y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
+        xor     g, y2                   # y2 = CH = ((f^g)&e)^g
+        add     y0, y2                  # y2 = S1 + CH
+        MY_ROR  2, y1                   # y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
+        offset = \round * 4 + _XFER     #
+        add     offset(%rsp), y2        # y2 = k + w + S1 + CH
+        mov     a, y0                   # y0 = a
+        add     y2, h                   # h = h + S1 + CH + k + w
+        mov     a, y2                   # y2 = a
+        or      c, y0                   # y0 = a|c
+        add     h, d                    # d = d + h + S1 + CH + k + w
+        and     c, y2                   # y2 = a&c
+        and     b, y0                   # y0 = (a|c)&b
+        add     y1, h                   # h = h + S1 + CH + k + w + S0
+        or      y2, y0                  # y0 = MAJ = (a|c)&b)|(a&c)
+        add     y0, h                   # h = h + S1 + CH + k + w + S0 + MAJ
+        ROTATE_ARGS
+.endm
+
+########################################################################
+## void sha256_transform_avx(void *input_data, UINT32 digest[8], UINT64 num_blks)
+## arg 1 : pointer to input data
+## arg 2 : pointer to digest
+## arg 3 : Num blocks
+########################################################################
+.text
+ENTRY(sha256_transform_avx)
+.align 32
+        pushq   %rbx
+        pushq   %rbp
+        pushq   %r13
+        pushq   %r14
+        pushq   %r15
+        pushq   %r12
+
+        mov     %rsp, %r12
+        subq    $STACK_SIZE, %rsp       # allocate stack space
+        and     $~15, %rsp              # align stack pointer
+
+        shl     $6, NUM_BLKS            # convert to bytes
+        jz      done_hash
+        add     INP, NUM_BLKS           # pointer to end of data
+        mov     NUM_BLKS, _INP_END(%rsp)
+
+        ## load initial digest
+        mov     4*0(CTX), a
+        mov     4*1(CTX), b
+        mov     4*2(CTX), c
+        mov     4*3(CTX), d
+        mov     4*4(CTX), e
+        mov     4*5(CTX), f
+        mov     4*6(CTX), g
+        mov     4*7(CTX), h
+
+        vmovdqa  PSHUFFLE_BYTE_FLIP_MASK(%rip), BYTE_FLIP_MASK
+        vmovdqa  _SHUF_00BA(%rip), SHUF_00BA
+        vmovdqa  _SHUF_DC00(%rip), SHUF_DC00
+loop0:
+        lea     K256(%rip), TBL
+
+        ## byte swap first 16 dwords
+        COPY_XMM_AND_BSWAP      X0, 0*16(INP), BYTE_FLIP_MASK
+        COPY_XMM_AND_BSWAP      X1, 1*16(INP), BYTE_FLIP_MASK
+        COPY_XMM_AND_BSWAP      X2, 2*16(INP), BYTE_FLIP_MASK
+        COPY_XMM_AND_BSWAP      X3, 3*16(INP), BYTE_FLIP_MASK
+
+        mov     INP, _INP(%rsp)
+
+        ## schedule 48 input dwords, by doing 3 rounds of 16 each
+        mov     $3, SRND
+.align 16
+loop1:
+        vpaddd  (TBL), X0, XFER
+        vmovdqa XFER, _XFER(%rsp)
+        FOUR_ROUNDS_AND_SCHED
+
+        vpaddd  1*16(TBL), X0, XFER
+        vmovdqa XFER, _XFER(%rsp)
+        FOUR_ROUNDS_AND_SCHED
+
+        vpaddd  2*16(TBL), X0, XFER
+        vmovdqa XFER, _XFER(%rsp)
+        FOUR_ROUNDS_AND_SCHED
+
+        vpaddd  3*16(TBL), X0, XFER
+        vmovdqa XFER, _XFER(%rsp)
+        add     $4*16, TBL
+        FOUR_ROUNDS_AND_SCHED
+
+        sub     $1, SRND
+        jne     loop1
+
+        mov     $2, SRND
+loop2:
+        vpaddd  (TBL), X0, XFER
+        vmovdqa XFER, _XFER(%rsp)
+        DO_ROUND        0
+        DO_ROUND        1
+        DO_ROUND        2
+        DO_ROUND        3
+
+        vpaddd  1*16(TBL), X1, XFER
+        vmovdqa XFER, _XFER(%rsp)
+        add     $2*16, TBL
+        DO_ROUND        0
+        DO_ROUND        1
+        DO_ROUND        2
+        DO_ROUND        3
+
+        vmovdqa X2, X0
+        vmovdqa X3, X1
+
+        sub     $1, SRND
+        jne     loop2
+
+        addm    (4*0)(CTX),a
+        addm    (4*1)(CTX),b
+        addm    (4*2)(CTX),c
+        addm    (4*3)(CTX),d
+        addm    (4*4)(CTX),e
+        addm    (4*5)(CTX),f
+        addm    (4*6)(CTX),g
+        addm    (4*7)(CTX),h
+
+        mov     _INP(%rsp), INP
+        add     $64, INP
+        cmp     _INP_END(%rsp), INP
+        jne     loop0
+
+done_hash:
+
+        mov     %r12, %rsp
+
+        popq    %r12
+        popq    %r15
+        popq    %r14
+        popq    %r13
+        popq    %rbp
+        popq    %rbx
+        ret
+ENDPROC(sha256_transform_avx)
+
+.data
+.align 64
+K256:
+        .long 0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5
+        .long 0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5
+        .long 0xd807aa98,0x12835b01,0x243185be,0x550c7dc3
+        .long 0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174
+        .long 0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc
+        .long 0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da
+        .long 0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7
+        .long 0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967
+        .long 0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13
+        .long 0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85
+        .long 0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3
+        .long 0xd192e819,0xd6990624,0xf40e3585,0x106aa070
+        .long 0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5
+        .long 0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3
+        .long 0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208
+        .long 0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
+
+PSHUFFLE_BYTE_FLIP_MASK:
+        .octa 0x0c0d0e0f08090a0b0405060700010203
+
+# shuffle xBxA -> 00BA
+_SHUF_00BA:
+        .octa 0xFFFFFFFFFFFFFFFF0b0a090803020100
+
+# shuffle xDxC -> DC00
+_SHUF_DC00:
+        .octa 0x0b0a090803020100FFFFFFFFFFFFFFFF
+#endif
diff --git a/arch/x86/crypto/sha256-avx2-asm.S b/arch/x86/crypto/sha256-avx2-asm.S
new file mode 100644
index 000000000000..9e86944c539d
--- /dev/null
+++ b/arch/x86/crypto/sha256-avx2-asm.S
@@ -0,0 +1,772 @@
+########################################################################
+# Implement fast SHA-256 with AVX2 instructions. (x86_64)
+#
+# Copyright (C) 2013 Intel Corporation.
+#
+# Authors:
+#     James Guilford <james.guilford@intel.com>
+#     Kirk Yap <kirk.s.yap@intel.com>
+#     Tim Chen <tim.c.chen@linux.intel.com>
+#
+# This software is available to you under a choice of one of two
+# licenses.  You may choose to be licensed under the terms of the GNU
+# General Public License (GPL) Version 2, available from the file
+# COPYING in the main directory of this source tree, or the
+# OpenIB.org BSD license below:
+#
+#     Redistribution and use in source and binary forms, with or
+#     without modification, are permitted provided that the following
+#     conditions are met:
+#
+#      - Redistributions of source code must retain the above
+#        copyright notice, this list of conditions and the following
+#        disclaimer.
+#
+#      - Redistributions in binary form must reproduce the above
+#        copyright notice, this list of conditions and the following
+#        disclaimer in the documentation and/or other materials
+#        provided with the distribution.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+########################################################################
+#
+# This code is described in an Intel White-Paper:
+# "Fast SHA-256 Implementations on Intel Architecture Processors"
+#
+# To find it, surf to http://www.intel.com/p/en_US/embedded
+# and search for that title.
+#
+########################################################################
+# This code schedules 2 blocks at a time, with 4 lanes per block
+########################################################################
+
+#ifdef CONFIG_AS_AVX2
+#include <linux/linkage.h>
+
+## assume buffers not aligned
+#define VMOVDQ vmovdqu
+
+################################ Define Macros
+
+# addm [mem], reg
+# Add reg to mem using reg-mem add and store
+.macro addm p1 p2
+        add     \p1, \p2
+        mov     \p2, \p1
+.endm
+
+################################
+
+X0 = %ymm4
+X1 = %ymm5
+X2 = %ymm6
+X3 = %ymm7
+
+# XMM versions of above
+XWORD0 = %xmm4
+XWORD1 = %xmm5
+XWORD2 = %xmm6
+XWORD3 = %xmm7
+
+XTMP0 = %ymm0
+XTMP1 = %ymm1
+XTMP2 = %ymm2
+XTMP3 = %ymm3
+XTMP4 = %ymm8
+XFER  = %ymm9
+XTMP5 = %ymm11
+
+SHUF_00BA =     %ymm10 # shuffle xBxA -> 00BA
+SHUF_DC00 =     %ymm12 # shuffle xDxC -> DC00
+BYTE_FLIP_MASK = %ymm13
+
+X_BYTE_FLIP_MASK = %xmm13 # XMM version of BYTE_FLIP_MASK
+
+NUM_BLKS = %rdx # 3rd arg
+CTX     = %rsi  # 2nd arg
+INP     = %rdi  # 1st arg
+c       = %ecx
+d       = %r8d
+e       = %edx  # clobbers NUM_BLKS
+y3      = %edi  # clobbers INP
+
+
+TBL     = %rbp
+SRND    = CTX   # SRND is same register as CTX
+
+a = %eax
+b = %ebx
+f = %r9d
+g = %r10d
+h = %r11d
+old_h = %r11d
+
+T1 = %r12d
+y0 = %r13d
+y1 = %r14d
+y2 = %r15d
+
+
+_XFER_SIZE      = 2*64*4        # 2 blocks, 64 rounds, 4 bytes/round
+_XMM_SAVE_SIZE  = 0
+_INP_END_SIZE   = 8
+_INP_SIZE       = 8
+_CTX_SIZE       = 8
+_RSP_SIZE       = 8
+
+_XFER           = 0
+_XMM_SAVE       = _XFER     + _XFER_SIZE
+_INP_END        = _XMM_SAVE + _XMM_SAVE_SIZE
+_INP            = _INP_END  + _INP_END_SIZE
+_CTX            = _INP      + _INP_SIZE
+_RSP            = _CTX      + _CTX_SIZE
+STACK_SIZE      = _RSP      + _RSP_SIZE
+
+# rotate_Xs
+# Rotate values of symbols X0...X3
+.macro rotate_Xs
+        X_ = X0
+        X0 = X1
+        X1 = X2
+        X2 = X3
+        X3 = X_
+.endm
+
+# ROTATE_ARGS
+# Rotate values of symbols a...h
+.macro ROTATE_ARGS
+        old_h = h
+        TMP_ = h
+        h = g
+        g = f
+        f = e
+        e = d
+        d = c
+        c = b
+        b = a
+        a = TMP_
+.endm
+
+.macro FOUR_ROUNDS_AND_SCHED disp
+################################### RND N + 0 ############################
+
+        mov     a, y3           # y3 = a                                # MAJA
+        rorx    $25, e, y0      # y0 = e >> 25                          # S1A
+        rorx    $11, e, y1      # y1 = e >> 11                          # S1B
+
+        addl    \disp(%rsp, SRND), h            # h = k + w + h         # --
+        or      c, y3           # y3 = a|c                              # MAJA
+        vpalignr $4, X2, X3, XTMP0 # XTMP0 = W[-7]
+        mov     f, y2           # y2 = f                                # CH
+        rorx    $13, a, T1      # T1 = a >> 13                          # S0B
+
+        xor     y1, y0          # y0 = (e>>25) ^ (e>>11)                # S1
+        xor     g, y2           # y2 = f^g                              # CH
+        vpaddd  X0, XTMP0, XTMP0 # XTMP0 = W[-7] + W[-16]# y1 = (e >> 6)# S1
+        rorx    $6, e, y1       # y1 = (e >> 6)                         # S1
+
+        and     e, y2           # y2 = (f^g)&e                          # CH
+        xor     y1, y0          # y0 = (e>>25) ^ (e>>11) ^ (e>>6)       # S1
+        rorx    $22, a, y1      # y1 = a >> 22                          # S0A
+        add     h, d            # d = k + w + h + d                     # --
+
+        and     b, y3           # y3 = (a|c)&b                          # MAJA
+        vpalignr $4, X0, X1, XTMP1      # XTMP1 = W[-15]
+        xor     T1, y1          # y1 = (a>>22) ^ (a>>13)                # S0
+        rorx    $2, a, T1       # T1 = (a >> 2)                         # S0
+
+        xor     g, y2           # y2 = CH = ((f^g)&e)^g                 # CH
+        vpsrld  $7, XTMP1, XTMP2
+        xor     T1, y1          # y1 = (a>>22) ^ (a>>13) ^ (a>>2)       # S0
+        mov     a, T1           # T1 = a                                # MAJB
+        and     c, T1           # T1 = a&c                              # MAJB
+
+        add     y0, y2          # y2 = S1 + CH                          # --
+        vpslld  $(32-7), XTMP1, XTMP3
+        or      T1, y3          # y3 = MAJ = (a|c)&b)|(a&c)             # MAJ
+        add     y1, h           # h = k + w + h + S0                    # --
+
+        add     y2, d           # d = k + w + h + d + S1 + CH = d + t1  # --
+        vpor    XTMP2, XTMP3, XTMP3     # XTMP3 = W[-15] ror 7
+
+        vpsrld  $18, XTMP1, XTMP2
+        add     y2, h           # h = k + w + h + S0 + S1 + CH = t1 + S0# --
+        add     y3, h           # h = t1 + S0 + MAJ                     # --
+
+
+        ROTATE_ARGS
+
+################################### RND N + 1 ############################
+
+        mov     a, y3           # y3 = a                                # MAJA
+        rorx    $25, e, y0      # y0 = e >> 25                          # S1A
+        rorx    $11, e, y1      # y1 = e >> 11                          # S1B
+        offset = \disp + 1*4
+        addl    offset(%rsp, SRND), h   # h = k + w + h         # --
+        or      c, y3           # y3 = a|c                              # MAJA
+
+
+        vpsrld  $3, XTMP1, XTMP4 # XTMP4 = W[-15] >> 3
+        mov     f, y2           # y2 = f                                # CH
+        rorx    $13, a, T1      # T1 = a >> 13                          # S0B
+        xor     y1, y0          # y0 = (e>>25) ^ (e>>11)                # S1
+        xor     g, y2           # y2 = f^g                              # CH
+
+
+        rorx    $6, e, y1       # y1 = (e >> 6)                         # S1
+        xor     y1, y0          # y0 = (e>>25) ^ (e>>11) ^ (e>>6)       # S1
+        rorx    $22, a, y1      # y1 = a >> 22                          # S0A
+        and     e, y2           # y2 = (f^g)&e                          # CH
+        add     h, d            # d = k + w + h + d                     # --
+
+        vpslld  $(32-18), XTMP1, XTMP1
+        and     b, y3           # y3 = (a|c)&b                          # MAJA
+        xor     T1, y1          # y1 = (a>>22) ^ (a>>13)                # S0
+
+        vpxor   XTMP1, XTMP3, XTMP3
+        rorx    $2, a, T1       # T1 = (a >> 2)                         # S0
+        xor     g, y2           # y2 = CH = ((f^g)&e)^g                 # CH
+
+        vpxor   XTMP2, XTMP3, XTMP3     # XTMP3 = W[-15] ror 7 ^ W[-15] ror 18
+        xor     T1, y1          # y1 = (a>>22) ^ (a>>13) ^ (a>>2)       # S0
+        mov     a, T1           # T1 = a                                # MAJB
+        and     c, T1           # T1 = a&c                              # MAJB
+        add     y0, y2          # y2 = S1 + CH                          # --
+
+        vpxor   XTMP4, XTMP3, XTMP1     # XTMP1 = s0
+        vpshufd $0b11111010, X3, XTMP2  # XTMP2 = W[-2] {BBAA}
+        or      T1, y3          # y3 = MAJ = (a|c)&b)|(a&c)             # MAJ
+        add     y1, h           # h = k + w + h + S0                    # --
+
+        vpaddd  XTMP1, XTMP0, XTMP0     # XTMP0 = W[-16] + W[-7] + s0
+        add     y2, d           # d = k + w + h + d + S1 + CH = d + t1  # --
+        add     y2, h           # h = k + w + h + S0 + S1 + CH = t1 + S0# --
+        add     y3, h           # h = t1 + S0 + MAJ                     # --
+
+        vpsrld  $10, XTMP2, XTMP4 # XTMP4 = W[-2] >> 10 {BBAA}
+
+
+        ROTATE_ARGS
+
+################################### RND N + 2 ############################
+
+        mov     a, y3           # y3 = a                                # MAJA
+        rorx    $25, e, y0      # y0 = e >> 25                          # S1A
+        offset = \disp + 2*4
+        addl    offset(%rsp, SRND), h   # h = k + w + h         # --
+
+        vpsrlq  $19, XTMP2, XTMP3 # XTMP3 = W[-2] ror 19 {xBxA}
+        rorx    $11, e, y1      # y1 = e >> 11                          # S1B
+        or      c, y3           # y3 = a|c                              # MAJA
+        mov     f, y2           # y2 = f                                # CH
+        xor     g, y2           # y2 = f^g                              # CH
+
+        rorx    $13, a, T1      # T1 = a >> 13                          # S0B
+        xor     y1, y0          # y0 = (e>>25) ^ (e>>11)                # S1
+        vpsrlq  $17, XTMP2, XTMP2       # XTMP2 = W[-2] ror 17 {xBxA}
+        and     e, y2           # y2 = (f^g)&e                          # CH
+
+        rorx    $6, e, y1       # y1 = (e >> 6)                         # S1
+        vpxor   XTMP3, XTMP2, XTMP2
+        add     h, d            # d = k + w + h + d                     # --
+        and     b, y3           # y3 = (a|c)&b                          # MAJA
+
+        xor     y1, y0          # y0 = (e>>25) ^ (e>>11) ^ (e>>6)       # S1
+        rorx    $22, a, y1      # y1 = a >> 22                          # S0A
+        vpxor   XTMP2, XTMP4, XTMP4     # XTMP4 = s1 {xBxA}
+        xor     g, y2           # y2 = CH = ((f^g)&e)^g                 # CH
+
+        vpshufb SHUF_00BA, XTMP4, XTMP4 # XTMP4 = s1 {00BA}
+        xor     T1, y1          # y1 = (a>>22) ^ (a>>13)                # S0
+        rorx    $2, a ,T1       # T1 = (a >> 2)                         # S0
+        vpaddd  XTMP4, XTMP0, XTMP0     # XTMP0 = {..., ..., W[1], W[0]}
+
+        xor     T1, y1          # y1 = (a>>22) ^ (a>>13) ^ (a>>2)       # S0
+        mov     a, T1           # T1 = a                                # MAJB
+        and     c, T1           # T1 = a&c                              # MAJB
+        add     y0, y2          # y2 = S1 + CH                          # --
+        vpshufd $0b01010000, XTMP0, XTMP2       # XTMP2 = W[-2] {DDCC}
+
+        or      T1, y3          # y3 = MAJ = (a|c)&b)|(a&c)             # MAJ
+        add     y1,h            # h = k + w + h + S0                    # --
+        add     y2,d            # d = k + w + h + d + S1 + CH = d + t1  # --
+        add     y2,h            # h = k + w + h + S0 + S1 + CH = t1 + S0# --
+
+        add     y3,h            # h = t1 + S0 + MAJ                     # --
+
+
+        ROTATE_ARGS
+
+################################### RND N + 3 ############################
+
+        mov     a, y3           # y3 = a                                # MAJA
+        rorx    $25, e, y0      # y0 = e >> 25                          # S1A
+        rorx    $11, e, y1      # y1 = e >> 11                          # S1B
+        offset = \disp + 3*4
+        addl    offset(%rsp, SRND), h   # h = k + w + h         # --
+        or      c, y3           # y3 = a|c                              # MAJA
+
+
+        vpsrld  $10, XTMP2, XTMP5       # XTMP5 = W[-2] >> 10 {DDCC}
+        mov     f, y2           # y2 = f                                # CH
+        rorx    $13, a, T1      # T1 = a >> 13                          # S0B
+        xor     y1, y0          # y0 = (e>>25) ^ (e>>11)                # S1
+        xor     g, y2           # y2 = f^g                              # CH
+
+
+        vpsrlq  $19, XTMP2, XTMP3       # XTMP3 = W[-2] ror 19 {xDxC}
+        rorx    $6, e, y1       # y1 = (e >> 6)                         # S1
+        and     e, y2           # y2 = (f^g)&e                          # CH
+        add     h, d            # d = k + w + h + d                     # --
+        and     b, y3           # y3 = (a|c)&b                          # MAJA
+
+        vpsrlq  $17, XTMP2, XTMP2       # XTMP2 = W[-2] ror 17 {xDxC}
+        xor     y1, y0          # y0 = (e>>25) ^ (e>>11) ^ (e>>6)       # S1
+        xor     g, y2           # y2 = CH = ((f^g)&e)^g                 # CH
+
+        vpxor   XTMP3, XTMP2, XTMP2
+        rorx    $22, a, y1      # y1 = a >> 22                          # S0A
+        add     y0, y2          # y2 = S1 + CH                          # --
+
+        vpxor   XTMP2, XTMP5, XTMP5     # XTMP5 = s1 {xDxC}
+        xor     T1, y1          # y1 = (a>>22) ^ (a>>13)                # S0
+        add     y2, d           # d = k + w + h + d + S1 + CH = d + t1  # --
+
+        rorx    $2, a, T1       # T1 = (a >> 2)                         # S0
+        vpshufb SHUF_DC00, XTMP5, XTMP5 # XTMP5 = s1 {DC00}
+
+        vpaddd  XTMP0, XTMP5, X0        # X0 = {W[3], W[2], W[1], W[0]}
+        xor     T1, y1          # y1 = (a>>22) ^ (a>>13) ^ (a>>2)       # S0
+        mov     a, T1           # T1 = a                                # MAJB
+        and     c, T1           # T1 = a&c                              # MAJB
+        or      T1, y3          # y3 = MAJ = (a|c)&b)|(a&c)             # MAJ
+
+        add     y1, h           # h = k + w + h + S0                    # --
+        add     y2, h           # h = k + w + h + S0 + S1 + CH = t1 + S0# --
+        add     y3, h           # h = t1 + S0 + MAJ                     # --
+
+        ROTATE_ARGS
+        rotate_Xs
+.endm
+
+.macro DO_4ROUNDS disp
+################################### RND N + 0 ###########################
+
+        mov     f, y2           # y2 = f                                # CH
+        rorx    $25, e, y0      # y0 = e >> 25                          # S1A
+        rorx    $11, e, y1      # y1 = e >> 11                          # S1B
+        xor     g, y2           # y2 = f^g                              # CH
+
+        xor     y1, y0          # y0 = (e>>25) ^ (e>>11)                # S1
+        rorx    $6, e, y1       # y1 = (e >> 6)                         # S1
+        and     e, y2           # y2 = (f^g)&e                          # CH
+
+        xor     y1, y0          # y0 = (e>>25) ^ (e>>11) ^ (e>>6)       # S1
+        rorx    $13, a, T1      # T1 = a >> 13                          # S0B
+        xor     g, y2           # y2 = CH = ((f^g)&e)^g                 # CH
+        rorx    $22, a, y1      # y1 = a >> 22                          # S0A
+        mov     a, y3           # y3 = a                                # MAJA
+
+        xor     T1, y1          # y1 = (a>>22) ^ (a>>13)                # S0
+        rorx    $2, a, T1       # T1 = (a >> 2)                         # S0
+        addl    \disp(%rsp, SRND), h            # h = k + w + h # --
+        or      c, y3           # y3 = a|c                              # MAJA
+
+        xor     T1, y1          # y1 = (a>>22) ^ (a>>13) ^ (a>>2)       # S0
+        mov     a, T1           # T1 = a                                # MAJB
+        and     b, y3           # y3 = (a|c)&b                          # MAJA
+        and     c, T1           # T1 = a&c                              # MAJB
+        add     y0, y2          # y2 = S1 + CH                          # --
+
+
+        add     h, d            # d = k + w + h + d                     # --
+        or      T1, y3          # y3 = MAJ = (a|c)&b)|(a&c)             # MAJ
+        add     y1, h           # h = k + w + h + S0                    # --
+        add     y2, d           # d = k + w + h + d + S1 + CH = d + t1  # --
+
+        ROTATE_ARGS
+
+################################### RND N + 1 ###########################
+
+        add     y2, old_h       # h = k + w + h + S0 + S1 + CH = t1 + S0# --
+        mov     f, y2           # y2 = f                                # CH
+        rorx    $25, e, y0      # y0 = e >> 25                          # S1A
+        rorx    $11, e, y1      # y1 = e >> 11                          # S1B
+        xor     g, y2           # y2 = f^g                              # CH
+
+        xor     y1, y0          # y0 = (e>>25) ^ (e>>11)                # S1
+        rorx    $6, e, y1       # y1 = (e >> 6)                         # S1
+        and     e, y2           # y2 = (f^g)&e                          # CH
+        add     y3, old_h       # h = t1 + S0 + MAJ                     # --
+
+        xor     y1, y0          # y0 = (e>>25) ^ (e>>11) ^ (e>>6)       # S1
+        rorx    $13, a, T1      # T1 = a >> 13                          # S0B
+        xor     g, y2           # y2 = CH = ((f^g)&e)^g                 # CH
+        rorx    $22, a, y1      # y1 = a >> 22                          # S0A
+        mov     a, y3           # y3 = a                                # MAJA
+
+        xor     T1, y1          # y1 = (a>>22) ^ (a>>13)                # S0
+        rorx    $2, a, T1       # T1 = (a >> 2)                         # S0
+        offset = 4*1 + \disp
+        addl    offset(%rsp, SRND), h           # h = k + w + h # --
+        or      c, y3           # y3 = a|c                              # MAJA
+
+        xor     T1, y1          # y1 = (a>>22) ^ (a>>13) ^ (a>>2)       # S0
+        mov     a, T1           # T1 = a                                # MAJB
+        and     b, y3           # y3 = (a|c)&b                          # MAJA
+        and     c, T1           # T1 = a&c                              # MAJB
+        add     y0, y2          # y2 = S1 + CH                          # --
+
+
+        add     h, d            # d = k + w + h + d                     # --
+        or      T1, y3          # y3 = MAJ = (a|c)&b)|(a&c)             # MAJ
+        add     y1, h           # h = k + w + h + S0                    # --
+
+        add     y2, d           # d = k + w + h + d + S1 + CH = d + t1  # --
+
+        ROTATE_ARGS
+
+################################### RND N + 2 ##############################
+
+        add     y2, old_h       # h = k + w + h + S0 + S1 + CH = t1 + S0# --
+        mov     f, y2           # y2 = f                                # CH
+        rorx    $25, e, y0      # y0 = e >> 25                          # S1A
+        rorx    $11, e, y1      # y1 = e >> 11                          # S1B
+        xor     g, y2           # y2 = f^g                              # CH
+
+        xor     y1, y0          # y0 = (e>>25) ^ (e>>11)                # S1
+        rorx    $6, e, y1       # y1 = (e >> 6)                         # S1
+        and     e, y2           # y2 = (f^g)&e                          # CH
+        add     y3, old_h       # h = t1 + S0 + MAJ                     # --
+
+        xor     y1, y0          # y0 = (e>>25) ^ (e>>11) ^ (e>>6)       # S1
+        rorx    $13, a, T1      # T1 = a >> 13                          # S0B
+        xor     g, y2           # y2 = CH = ((f^g)&e)^g                 # CH
+        rorx    $22, a, y1      # y1 = a >> 22                          # S0A
+        mov     a, y3           # y3 = a                                # MAJA
+
+        xor     T1, y1          # y1 = (a>>22) ^ (a>>13)                # S0
+        rorx    $2, a, T1       # T1 = (a >> 2)                         # S0
+        offset = 4*2 + \disp
+        addl    offset(%rsp, SRND), h           # h = k + w + h # --
+        or      c, y3           # y3 = a|c                              # MAJA
+
+        xor     T1, y1          # y1 = (a>>22) ^ (a>>13) ^ (a>>2)       # S0
+        mov     a, T1           # T1 = a                                # MAJB
+        and     b, y3           # y3 = (a|c)&b                          # MAJA
+        and     c, T1           # T1 = a&c                              # MAJB
+        add     y0, y2          # y2 = S1 + CH                          # --
+
+
+        add     h, d            # d = k + w + h + d                     # --
+        or      T1, y3          # y3 = MAJ = (a|c)&b)|(a&c)             # MAJ
+        add     y1, h           # h = k + w + h + S0                    # --
+
+        add     y2, d           # d = k + w + h + d + S1 + CH = d + t1  # --
+
+        ROTATE_ARGS
+
+################################### RND N + 3 ###########################
+
+        add     y2, old_h       # h = k + w + h + S0 + S1 + CH = t1 + S0# --
+        mov     f, y2           # y2 = f                                # CH
+        rorx    $25, e, y0      # y0 = e >> 25                          # S1A
+        rorx    $11, e, y1      # y1 = e >> 11                          # S1B
+        xor     g, y2           # y2 = f^g                              # CH
+
+        xor     y1, y0          # y0 = (e>>25) ^ (e>>11)                # S1
+        rorx    $6, e, y1       # y1 = (e >> 6)                         # S1
+        and     e, y2           # y2 = (f^g)&e                          # CH
+        add     y3, old_h       # h = t1 + S0 + MAJ                     # --
+
+        xor     y1, y0          # y0 = (e>>25) ^ (e>>11) ^ (e>>6)       # S1
+        rorx    $13, a, T1      # T1 = a >> 13                          # S0B
+        xor     g, y2           # y2 = CH = ((f^g)&e)^g                 # CH
+        rorx    $22, a, y1      # y1 = a >> 22                          # S0A
+        mov     a, y3           # y3 = a                                # MAJA
+
+        xor     T1, y1          # y1 = (a>>22) ^ (a>>13)                # S0
+        rorx    $2, a, T1       # T1 = (a >> 2)                         # S0
+        offset = 4*3 + \disp
+        addl    offset(%rsp, SRND), h           # h = k + w + h # --
+        or      c, y3           # y3 = a|c                              # MAJA
+
+        xor     T1, y1          # y1 = (a>>22) ^ (a>>13) ^ (a>>2)       # S0
+        mov     a, T1           # T1 = a                                # MAJB
+        and     b, y3           # y3 = (a|c)&b                          # MAJA
+        and     c, T1           # T1 = a&c                              # MAJB
+        add     y0, y2          # y2 = S1 + CH                          # --
+
+
+        add     h, d            # d = k + w + h + d                     # --
+        or      T1, y3          # y3 = MAJ = (a|c)&b)|(a&c)             # MAJ
+        add     y1, h           # h = k + w + h + S0                    # --
+
+        add     y2, d           # d = k + w + h + d + S1 + CH = d + t1  # --
+
+
+        add     y2, h           # h = k + w + h + S0 + S1 + CH = t1 + S0# --
+
+        add     y3, h           # h = t1 + S0 + MAJ                     # --
+
+        ROTATE_ARGS
+
+.endm
+
+########################################################################
+## void sha256_transform_rorx(void *input_data, UINT32 digest[8], UINT64 num_blks)
+## arg 1 : pointer to input data
+## arg 2 : pointer to digest
+## arg 3 : Num blocks
+########################################################################
+.text
+ENTRY(sha256_transform_rorx)
+.align 32
+        pushq   %rbx
+        pushq   %rbp
+        pushq   %r12
+        pushq   %r13
+        pushq   %r14
+        pushq   %r15
+
+        mov     %rsp, %rax
+        subq    $STACK_SIZE, %rsp
+        and     $-32, %rsp      # align rsp to 32 byte boundary
+        mov     %rax, _RSP(%rsp)
+
+
+        shl     $6, NUM_BLKS    # convert to bytes
+        jz      done_hash
+        lea     -64(INP, NUM_BLKS), NUM_BLKS # pointer to last block
+        mov     NUM_BLKS, _INP_END(%rsp)
+
+        cmp     NUM_BLKS, INP
+        je      only_one_block
+
+        ## load initial digest
+        mov     (CTX), a
+        mov     4*1(CTX), b
+        mov     4*2(CTX), c
+        mov     4*3(CTX), d
+        mov     4*4(CTX), e
+        mov     4*5(CTX), f
+        mov     4*6(CTX), g
+        mov     4*7(CTX), h
+
+        vmovdqa  PSHUFFLE_BYTE_FLIP_MASK(%rip), BYTE_FLIP_MASK
+        vmovdqa  _SHUF_00BA(%rip), SHUF_00BA
+        vmovdqa  _SHUF_DC00(%rip), SHUF_DC00
+
+        mov     CTX, _CTX(%rsp)
+
+loop0:
+        lea     K256(%rip), TBL
+
+        ## Load first 16 dwords from two blocks
+        VMOVDQ  0*32(INP),XTMP0
+        VMOVDQ  1*32(INP),XTMP1
+        VMOVDQ  2*32(INP),XTMP2
+        VMOVDQ  3*32(INP),XTMP3
+
+        ## byte swap data
+        vpshufb BYTE_FLIP_MASK, XTMP0, XTMP0
+        vpshufb BYTE_FLIP_MASK, XTMP1, XTMP1
+        vpshufb BYTE_FLIP_MASK, XTMP2, XTMP2
+        vpshufb BYTE_FLIP_MASK, XTMP3, XTMP3
+
+        ## transpose data into high/low halves
+        vperm2i128      $0x20, XTMP2, XTMP0, X0
+        vperm2i128      $0x31, XTMP2, XTMP0, X1
+        vperm2i128      $0x20, XTMP3, XTMP1, X2
+        vperm2i128      $0x31, XTMP3, XTMP1, X3
+
+last_block_enter:
+        add     $64, INP
+        mov     INP, _INP(%rsp)
+
+        ## schedule 48 input dwords, by doing 3 rounds of 12 each
+        xor     SRND, SRND
+
+.align 16
+loop1:
+        vpaddd  0*32(TBL, SRND), X0, XFER
+        vmovdqa XFER, 0*32+_XFER(%rsp, SRND)
+        FOUR_ROUNDS_AND_SCHED   _XFER + 0*32
+
+        vpaddd  1*32(TBL, SRND), X0, XFER
+        vmovdqa XFER, 1*32+_XFER(%rsp, SRND)
+        FOUR_ROUNDS_AND_SCHED   _XFER + 1*32
+
+        vpaddd  2*32(TBL, SRND), X0, XFER
+        vmovdqa XFER, 2*32+_XFER(%rsp, SRND)
+        FOUR_ROUNDS_AND_SCHED   _XFER + 2*32
+
+        vpaddd  3*32(TBL, SRND), X0, XFER
+        vmovdqa XFER, 3*32+_XFER(%rsp, SRND)
+        FOUR_ROUNDS_AND_SCHED   _XFER + 3*32
+
+        add     $4*32, SRND
+        cmp     $3*4*32, SRND
+        jb      loop1
+
+loop2:
+        ## Do last 16 rounds with no scheduling
+        vpaddd  0*32(TBL, SRND), X0, XFER
+        vmovdqa XFER, 0*32+_XFER(%rsp, SRND)
+        DO_4ROUNDS      _XFER + 0*32
+        vpaddd  1*32(TBL, SRND), X1, XFER
+        vmovdqa XFER, 1*32+_XFER(%rsp, SRND)
+        DO_4ROUNDS      _XFER + 1*32
+        add     $2*32, SRND
+
+        vmovdqa X2, X0
+        vmovdqa X3, X1
+
+        cmp     $4*4*32, SRND
+        jb      loop2
+
+        mov     _CTX(%rsp), CTX
+        mov     _INP(%rsp), INP
+
+        addm    (4*0)(CTX),a
+        addm    (4*1)(CTX),b
+        addm    (4*2)(CTX),c
+        addm    (4*3)(CTX),d
+        addm    (4*4)(CTX),e
+        addm    (4*5)(CTX),f
+        addm    (4*6)(CTX),g
+        addm    (4*7)(CTX),h
+
+        cmp     _INP_END(%rsp), INP
+        ja      done_hash
+
+        #### Do second block using previously scheduled results
+        xor     SRND, SRND
+.align 16
+loop3:
+        DO_4ROUNDS       _XFER + 0*32 + 16
+        DO_4ROUNDS       _XFER + 1*32 + 16
+        add     $2*32, SRND
+        cmp     $4*4*32, SRND
+        jb      loop3
+
+        mov     _CTX(%rsp), CTX
+        mov     _INP(%rsp), INP
+        add     $64, INP
+
+        addm    (4*0)(CTX),a
+        addm    (4*1)(CTX),b
+        addm    (4*2)(CTX),c
+        addm    (4*3)(CTX),d
+        addm    (4*4)(CTX),e
+        addm    (4*5)(CTX),f
+        addm    (4*6)(CTX),g
+        addm    (4*7)(CTX),h
+
+        cmp     _INP_END(%rsp), INP
+        jb      loop0
+        ja      done_hash
+
+do_last_block:
+        #### do last block
+        lea     K256(%rip), TBL
+
+        VMOVDQ  0*16(INP),XWORD0
+        VMOVDQ  1*16(INP),XWORD1
+        VMOVDQ  2*16(INP),XWORD2
+        VMOVDQ  3*16(INP),XWORD3
+
+        vpshufb X_BYTE_FLIP_MASK, XWORD0, XWORD0
+        vpshufb X_BYTE_FLIP_MASK, XWORD1, XWORD1
+        vpshufb X_BYTE_FLIP_MASK, XWORD2, XWORD2
+        vpshufb X_BYTE_FLIP_MASK, XWORD3, XWORD3
+
+        jmp     last_block_enter
+
+only_one_block:
+
+        ## load initial digest
+        mov     (4*0)(CTX),a
+        mov     (4*1)(CTX),b
+        mov     (4*2)(CTX),c
+        mov     (4*3)(CTX),d
+        mov     (4*4)(CTX),e
+        mov     (4*5)(CTX),f
+        mov     (4*6)(CTX),g
+        mov     (4*7)(CTX),h
+
+        vmovdqa PSHUFFLE_BYTE_FLIP_MASK(%rip), BYTE_FLIP_MASK
+        vmovdqa _SHUF_00BA(%rip), SHUF_00BA
+        vmovdqa _SHUF_DC00(%rip), SHUF_DC00
+
+        mov     CTX, _CTX(%rsp)
+        jmp     do_last_block
+
+done_hash:
+
+        mov     _RSP(%rsp), %rsp
+
+        popq    %r15
+        popq    %r14
+        popq    %r13
+        popq    %r12
+        popq    %rbp
+        popq    %rbx
+        ret
+ENDPROC(sha256_transform_rorx)
+
+.data
+.align 64
+K256:
+        .long   0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5
+        .long   0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5
+        .long   0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5
+        .long   0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5
+        .long   0xd807aa98,0x12835b01,0x243185be,0x550c7dc3
+        .long   0xd807aa98,0x12835b01,0x243185be,0x550c7dc3
+        .long   0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174
+        .long   0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174
+        .long   0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc
+        .long   0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc
+        .long   0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da
+        .long   0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da
+        .long   0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7
+        .long   0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7
+        .long   0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967
+        .long   0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967
+        .long   0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13
+        .long   0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13
+        .long   0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85
+        .long   0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85
+        .long   0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3
+        .long   0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3
+        .long   0xd192e819,0xd6990624,0xf40e3585,0x106aa070
+        .long   0xd192e819,0xd6990624,0xf40e3585,0x106aa070
+        .long   0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5
+        .long   0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5
+        .long   0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3
+        .long   0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3
+        .long   0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208
+        .long   0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208
+        .long   0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
+        .long   0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
+
+PSHUFFLE_BYTE_FLIP_MASK:
+        .octa 0x0c0d0e0f08090a0b0405060700010203,0x0c0d0e0f08090a0b0405060700010203
+
+# shuffle xBxA -> 00BA
+_SHUF_00BA:
+        .octa 0xFFFFFFFFFFFFFFFF0b0a090803020100,0xFFFFFFFFFFFFFFFF0b0a090803020100
+
+# shuffle xDxC -> DC00
+_SHUF_DC00:
+        .octa 0x0b0a090803020100FFFFFFFFFFFFFFFF,0x0b0a090803020100FFFFFFFFFFFFFFFF
+#endif
diff --git a/arch/x86/crypto/sha256-ssse3-asm.S b/arch/x86/crypto/sha256-ssse3-asm.S
new file mode 100644
index 000000000000..98d3c391da81
--- /dev/null
+++ b/arch/x86/crypto/sha256-ssse3-asm.S
@@ -0,0 +1,506 @@
+########################################################################
+# Implement fast SHA-256 with SSSE3 instructions. (x86_64)
+#
+# Copyright (C) 2013 Intel Corporation.
+#
+# Authors:
+#     James Guilford <james.guilford@intel.com>
+#     Kirk Yap <kirk.s.yap@intel.com>
+#     Tim Chen <tim.c.chen@linux.intel.com>
+#
+# This software is available to you under a choice of one of two
+# licenses.  You may choose to be licensed under the terms of the GNU
+# General Public License (GPL) Version 2, available from the file
+# COPYING in the main directory of this source tree, or the
+# OpenIB.org BSD license below:
+#
+#     Redistribution and use in source and binary forms, with or
+#     without modification, are permitted provided that the following
+#     conditions are met:
+#
+#      - Redistributions of source code must retain the above
+#        copyright notice, this list of conditions and the following
+#        disclaimer.
+#
+#      - Redistributions in binary form must reproduce the above
+#        copyright notice, this list of conditions and the following
+#        disclaimer in the documentation and/or other materials
+#        provided with the distribution.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+########################################################################
+#
+# This code is described in an Intel White-Paper:
+# "Fast SHA-256 Implementations on Intel Architecture Processors"
+#
+# To find it, surf to http://www.intel.com/p/en_US/embedded
+# and search for that title.
+#
+########################################################################
+
+#include <linux/linkage.h>
+
+## assume buffers not aligned
+#define    MOVDQ movdqu
+
+################################ Define Macros
+
+# addm [mem], reg
+# Add reg to mem using reg-mem add and store
+.macro addm p1 p2
+        add     \p1, \p2
+        mov     \p2, \p1
+.endm
+
+################################
+
+# COPY_XMM_AND_BSWAP xmm, [mem], byte_flip_mask
+# Load xmm with mem and byte swap each dword
+.macro COPY_XMM_AND_BSWAP p1 p2 p3
+        MOVDQ \p2, \p1
+        pshufb \p3, \p1
+.endm
+
+################################
+
+X0 = %xmm4
+X1 = %xmm5
+X2 = %xmm6
+X3 = %xmm7
+
+XTMP0 = %xmm0
+XTMP1 = %xmm1
+XTMP2 = %xmm2
+XTMP3 = %xmm3
+XTMP4 = %xmm8
+XFER = %xmm9
+
+SHUF_00BA = %xmm10      # shuffle xBxA -> 00BA
+SHUF_DC00 = %xmm11      # shuffle xDxC -> DC00
+BYTE_FLIP_MASK = %xmm12
+
+NUM_BLKS = %rdx   # 3rd arg
+CTX = %rsi        # 2nd arg
+INP = %rdi        # 1st arg
+
+SRND = %rdi       # clobbers INP
+c = %ecx
+d = %r8d
+e = %edx
+TBL = %rbp
+a = %eax
+b = %ebx
+
+f = %r9d
+g = %r10d
+h = %r11d
+
+y0 = %r13d
+y1 = %r14d
+y2 = %r15d
+
+
+
+_INP_END_SIZE = 8
+_INP_SIZE = 8
+_XFER_SIZE = 8
+_XMM_SAVE_SIZE = 0
+
+_INP_END = 0
+_INP            = _INP_END  + _INP_END_SIZE
+_XFER           = _INP      + _INP_SIZE
+_XMM_SAVE       = _XFER     + _XFER_SIZE
+STACK_SIZE      = _XMM_SAVE + _XMM_SAVE_SIZE
+
+# rotate_Xs
+# Rotate values of symbols X0...X3
+.macro rotate_Xs
+X_ = X0
+X0 = X1
+X1 = X2
+X2 = X3
+X3 = X_
+.endm
+
+# ROTATE_ARGS
+# Rotate values of symbols a...h
+.macro ROTATE_ARGS
+TMP_ = h
+h = g
+g = f
+f = e
+e = d
+d = c
+c = b
+b = a
+a = TMP_
+.endm
+
+.macro FOUR_ROUNDS_AND_SCHED
+        ## compute s0 four at a time and s1 two at a time
+        ## compute W[-16] + W[-7] 4 at a time
+        movdqa  X3, XTMP0
+        mov     e, y0                   # y0 = e
+        ror     $(25-11), y0            # y0 = e >> (25-11)
+        mov     a, y1                   # y1 = a
+        palignr $4, X2, XTMP0           # XTMP0 = W[-7]
+        ror     $(22-13), y1            # y1 = a >> (22-13)
+        xor     e, y0                   # y0 = e ^ (e >> (25-11))
+        mov     f, y2                   # y2 = f
+        ror     $(11-6), y0             # y0 = (e >> (11-6)) ^ (e >> (25-6))
+        movdqa  X1, XTMP1
+        xor     a, y1                   # y1 = a ^ (a >> (22-13)
+        xor     g, y2                   # y2 = f^g
+        paddd   X0, XTMP0               # XTMP0 = W[-7] + W[-16]
+        xor     e, y0                   # y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
+        and     e, y2                   # y2 = (f^g)&e
+        ror     $(13-2), y1             # y1 = (a >> (13-2)) ^ (a >> (22-2))
+        ## compute s0
+        palignr $4, X0, XTMP1           # XTMP1 = W[-15]
+        xor     a, y1                   # y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
+        ror     $6, y0                  # y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
+        xor     g, y2                   # y2 = CH = ((f^g)&e)^g
+        movdqa  XTMP1, XTMP2            # XTMP2 = W[-15]
+        ror     $2, y1                  # y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
+        add     y0, y2                  # y2 = S1 + CH
+        add     _XFER(%rsp) , y2        # y2 = k + w + S1 + CH
+        movdqa  XTMP1, XTMP3            # XTMP3 = W[-15]
+        mov     a, y0                   # y0 = a
+        add     y2, h                   # h = h + S1 + CH + k + w
+        mov     a, y2                   # y2 = a
+        pslld   $(32-7), XTMP1          #
+        or      c, y0                   # y0 = a|c
+        add     h, d                    # d = d + h + S1 + CH + k + w
+        and     c, y2                   # y2 = a&c
+        psrld   $7, XTMP2               #
+        and     b, y0                   # y0 = (a|c)&b
+        add     y1, h                   # h = h + S1 + CH + k + w + S0
+        por     XTMP2, XTMP1            # XTMP1 = W[-15] ror 7
+        or      y2, y0                  # y0 = MAJ = (a|c)&b)|(a&c)
+        add     y0, h                   # h = h + S1 + CH + k + w + S0 + MAJ
+                                        #
+        ROTATE_ARGS                     #
+        movdqa  XTMP3, XTMP2            # XTMP2 = W[-15]
+        mov     e, y0                   # y0 = e
+        mov     a, y1                   # y1 = a
+        movdqa  XTMP3, XTMP4            # XTMP4 = W[-15]
+        ror     $(25-11), y0            # y0 = e >> (25-11)
+        xor     e, y0                   # y0 = e ^ (e >> (25-11))
+        mov     f, y2                   # y2 = f
+        ror     $(22-13), y1            # y1 = a >> (22-13)
+        pslld   $(32-18), XTMP3         #
+        xor     a, y1                   # y1 = a ^ (a >> (22-13)
+        ror     $(11-6), y0             # y0 = (e >> (11-6)) ^ (e >> (25-6))
+        xor     g, y2                   # y2 = f^g
+        psrld   $18, XTMP2              #
+        ror     $(13-2), y1             # y1 = (a >> (13-2)) ^ (a >> (22-2))
+        xor     e, y0                   # y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
+        and     e, y2                   # y2 = (f^g)&e
+        ror     $6, y0                  # y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
+        pxor    XTMP3, XTMP1
+        xor     a, y1                   # y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
+        xor     g, y2                   # y2 = CH = ((f^g)&e)^g
+        psrld   $3, XTMP4               # XTMP4 = W[-15] >> 3
+        add     y0, y2                  # y2 = S1 + CH
+        add     (1*4 + _XFER)(%rsp), y2 # y2 = k + w + S1 + CH
+        ror     $2, y1                  # y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
+        pxor    XTMP2, XTMP1            # XTMP1 = W[-15] ror 7 ^ W[-15] ror 18
+        mov     a, y0                   # y0 = a
+        add     y2, h                   # h = h + S1 + CH + k + w
+        mov     a, y2                   # y2 = a
+        pxor    XTMP4, XTMP1            # XTMP1 = s0
+        or      c, y0                   # y0 = a|c
+        add     h, d                    # d = d + h + S1 + CH + k + w
+        and     c, y2                   # y2 = a&c
+        ## compute low s1
+        pshufd  $0b11111010, X3, XTMP2   # XTMP2 = W[-2] {BBAA}
+        and     b, y0                   # y0 = (a|c)&b
+        add     y1, h                   # h = h + S1 + CH + k + w + S0
+        paddd   XTMP1, XTMP0            # XTMP0 = W[-16] + W[-7] + s0
+        or      y2, y0                  # y0 = MAJ = (a|c)&b)|(a&c)
+        add     y0, h                   # h = h + S1 + CH + k + w + S0 + MAJ
+
+        ROTATE_ARGS
+        movdqa  XTMP2, XTMP3            # XTMP3 = W[-2] {BBAA}
+        mov     e, y0                   # y0 = e
+        mov     a, y1                   # y1 = a
+        ror     $(25-11), y0            # y0 = e >> (25-11)
+        movdqa  XTMP2, XTMP4            # XTMP4 = W[-2] {BBAA}
+        xor     e, y0                   # y0 = e ^ (e >> (25-11))
+        ror     $(22-13), y1            # y1 = a >> (22-13)
+        mov     f, y2                   # y2 = f
+        xor     a, y1                   # y1 = a ^ (a >> (22-13)
+        ror     $(11-6), y0             # y0 = (e >> (11-6)) ^ (e >> (25-6))
+        psrlq   $17, XTMP2              # XTMP2 = W[-2] ror 17 {xBxA}
+        xor     g, y2                   # y2 = f^g
+        psrlq   $19, XTMP3              # XTMP3 = W[-2] ror 19 {xBxA}
+        xor     e, y0                   # y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
+        and     e, y2                   # y2 = (f^g)&e
+        psrld   $10, XTMP4              # XTMP4 = W[-2] >> 10 {BBAA}
+        ror     $(13-2), y1             # y1 = (a >> (13-2)) ^ (a >> (22-2))
+        xor     a, y1                   # y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
+        xor     g, y2                   # y2 = CH = ((f^g)&e)^g
+        ror     $6, y0                  # y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
+        pxor    XTMP3, XTMP2
+        add     y0, y2                  # y2 = S1 + CH
+        ror     $2, y1                  # y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
+        add     (2*4 + _XFER)(%rsp), y2 # y2 = k + w + S1 + CH
+        pxor    XTMP2, XTMP4            # XTMP4 = s1 {xBxA}
+        mov     a, y0                   # y0 = a
+        add     y2, h                   # h = h + S1 + CH + k + w
+        mov     a, y2                   # y2 = a
+        pshufb  SHUF_00BA, XTMP4        # XTMP4 = s1 {00BA}
+        or      c, y0                   # y0 = a|c
+        add     h, d                    # d = d + h + S1 + CH + k + w
+        and     c, y2                   # y2 = a&c
+        paddd   XTMP4, XTMP0            # XTMP0 = {..., ..., W[1], W[0]}
+        and     b, y0                   # y0 = (a|c)&b
+        add     y1, h                   # h = h + S1 + CH + k + w + S0
+        ## compute high s1
+        pshufd  $0b01010000, XTMP0, XTMP2 # XTMP2 = W[-2] {BBAA}
+        or      y2, y0                  # y0 = MAJ = (a|c)&b)|(a&c)
+        add     y0, h                   # h = h + S1 + CH + k + w + S0 + MAJ
+                                        #
+        ROTATE_ARGS                     #
+        movdqa  XTMP2, XTMP3            # XTMP3 = W[-2] {DDCC}
+        mov     e, y0                   # y0 = e
+        ror     $(25-11), y0            # y0 = e >> (25-11)
+        mov     a, y1                   # y1 = a
+        movdqa  XTMP2, X0               # X0    = W[-2] {DDCC}
+        ror     $(22-13), y1            # y1 = a >> (22-13)
+        xor     e, y0                   # y0 = e ^ (e >> (25-11))
+        mov     f, y2                   # y2 = f
+        ror     $(11-6), y0             # y0 = (e >> (11-6)) ^ (e >> (25-6))
+        psrlq   $17, XTMP2              # XTMP2 = W[-2] ror 17 {xDxC}
+        xor     a, y1                   # y1 = a ^ (a >> (22-13)
+        xor     g, y2                   # y2 = f^g
+        psrlq   $19, XTMP3              # XTMP3 = W[-2] ror 19 {xDxC}
+        xor     e, y0                   # y0 = e ^ (e >> (11-6)) ^ (e >> (25
+        and     e, y2                   # y2 = (f^g)&e
+        ror     $(13-2), y1             # y1 = (a >> (13-2)) ^ (a >> (22-2))
+        psrld   $10, X0                 # X0 = W[-2] >> 10 {DDCC}
+        xor     a, y1                   # y1 = a ^ (a >> (13-2)) ^ (a >> (22
+        ror     $6, y0                  # y0 = S1 = (e>>6) & (e>>11) ^ (e>>2
+        xor     g, y2                   # y2 = CH = ((f^g)&e)^g
+        pxor    XTMP3, XTMP2            #
+        ror     $2, y1                  # y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>2
+        add     y0, y2                  # y2 = S1 + CH
+        add     (3*4 + _XFER)(%rsp), y2 # y2 = k + w + S1 + CH
+        pxor    XTMP2, X0               # X0 = s1 {xDxC}
+        mov     a, y0                   # y0 = a
+        add     y2, h                   # h = h + S1 + CH + k + w
+        mov     a, y2                   # y2 = a
+        pshufb  SHUF_DC00, X0           # X0 = s1 {DC00}
+        or      c, y0                   # y0 = a|c
+        add     h, d                    # d = d + h + S1 + CH + k + w
+        and     c, y2                   # y2 = a&c
+        paddd   XTMP0, X0               # X0 = {W[3], W[2], W[1], W[0]}
+        and     b, y0                   # y0 = (a|c)&b
+        add     y1, h                   # h = h + S1 + CH + k + w + S0
+        or      y2, y0                  # y0 = MAJ = (a|c)&b)|(a&c)
+        add     y0, h                   # h = h + S1 + CH + k + w + S0 + MAJ
+
+        ROTATE_ARGS
+        rotate_Xs
+.endm
+
+## input is [rsp + _XFER + %1 * 4]
+.macro DO_ROUND round
+        mov     e, y0                 # y0 = e
+        ror     $(25-11), y0          # y0 = e >> (25-11)
+        mov     a, y1                 # y1 = a
+        xor     e, y0                 # y0 = e ^ (e >> (25-11))
+        ror     $(22-13), y1          # y1 = a >> (22-13)
+        mov     f, y2                 # y2 = f
+        xor     a, y1                 # y1 = a ^ (a >> (22-13)
+        ror     $(11-6), y0           # y0 = (e >> (11-6)) ^ (e >> (25-6))
+        xor     g, y2                 # y2 = f^g
+        xor     e, y0                 # y0 = e ^ (e >> (11-6)) ^ (e >> (25-6))
+        ror     $(13-2), y1           # y1 = (a >> (13-2)) ^ (a >> (22-2))
+        and     e, y2                 # y2 = (f^g)&e
+        xor     a, y1                 # y1 = a ^ (a >> (13-2)) ^ (a >> (22-2))
+        ror     $6, y0                # y0 = S1 = (e>>6) & (e>>11) ^ (e>>25)
+        xor     g, y2                 # y2 = CH = ((f^g)&e)^g
+        add     y0, y2                # y2 = S1 + CH
+        ror     $2, y1                # y1 = S0 = (a>>2) ^ (a>>13) ^ (a>>22)
+        offset = \round * 4 + _XFER
+        add     offset(%rsp), y2      # y2 = k + w + S1 + CH
+        mov     a, y0                 # y0 = a
+        add     y2, h                 # h = h + S1 + CH + k + w
+        mov     a, y2                 # y2 = a
+        or      c, y0                 # y0 = a|c
+        add     h, d                  # d = d + h + S1 + CH + k + w
+        and     c, y2                 # y2 = a&c
+        and     b, y0                 # y0 = (a|c)&b
+        add     y1, h                 # h = h + S1 + CH + k + w + S0
+        or      y2, y0                # y0 = MAJ = (a|c)&b)|(a&c)
+        add     y0, h                 # h = h + S1 + CH + k + w + S0 + MAJ
+        ROTATE_ARGS
+.endm
+
+########################################################################
+## void sha256_transform_ssse3(void *input_data, UINT32 digest[8], UINT64 num_blks)
+## arg 1 : pointer to input data
+## arg 2 : pointer to digest
+## arg 3 : Num blocks
+########################################################################
+.text
+ENTRY(sha256_transform_ssse3)
+.align 32
+        pushq   %rbx
+        pushq   %rbp
+        pushq   %r13
+        pushq   %r14
+        pushq   %r15
+        pushq   %r12
+
+        mov     %rsp, %r12
+        subq    $STACK_SIZE, %rsp
+        and     $~15, %rsp
+
+        shl     $6, NUM_BLKS             # convert to bytes
+        jz      done_hash
+        add     INP, NUM_BLKS
+        mov     NUM_BLKS, _INP_END(%rsp) # pointer to end of data
+
+        ## load initial digest
+        mov     4*0(CTX), a
+        mov     4*1(CTX), b
+        mov     4*2(CTX), c
+        mov     4*3(CTX), d
+        mov     4*4(CTX), e
+        mov     4*5(CTX), f
+        mov     4*6(CTX), g
+        mov     4*7(CTX), h
+
+        movdqa  PSHUFFLE_BYTE_FLIP_MASK(%rip), BYTE_FLIP_MASK
+        movdqa  _SHUF_00BA(%rip), SHUF_00BA
+        movdqa  _SHUF_DC00(%rip), SHUF_DC00
+
+loop0:
+        lea     K256(%rip), TBL
+
+        ## byte swap first 16 dwords
+        COPY_XMM_AND_BSWAP      X0, 0*16(INP), BYTE_FLIP_MASK
+        COPY_XMM_AND_BSWAP      X1, 1*16(INP), BYTE_FLIP_MASK
+        COPY_XMM_AND_BSWAP      X2, 2*16(INP), BYTE_FLIP_MASK
+        COPY_XMM_AND_BSWAP      X3, 3*16(INP), BYTE_FLIP_MASK
+
+        mov     INP, _INP(%rsp)
+
+        ## schedule 48 input dwords, by doing 3 rounds of 16 each
+        mov     $3, SRND
+.align 16
+loop1:
+        movdqa  (TBL), XFER
+        paddd   X0, XFER
+        movdqa  XFER, _XFER(%rsp)
+        FOUR_ROUNDS_AND_SCHED
+
+        movdqa  1*16(TBL), XFER
+        paddd   X0, XFER
+        movdqa  XFER, _XFER(%rsp)
+        FOUR_ROUNDS_AND_SCHED
+
+        movdqa  2*16(TBL), XFER
+        paddd   X0, XFER
+        movdqa  XFER, _XFER(%rsp)
+        FOUR_ROUNDS_AND_SCHED
+
+        movdqa  3*16(TBL), XFER
+        paddd   X0, XFER
+        movdqa  XFER, _XFER(%rsp)
+        add     $4*16, TBL
+        FOUR_ROUNDS_AND_SCHED
+
+        sub     $1, SRND
+        jne     loop1
+
+        mov     $2, SRND
+loop2:
+        paddd   (TBL), X0
+        movdqa  X0, _XFER(%rsp)
+        DO_ROUND        0
+        DO_ROUND        1
+        DO_ROUND        2
+        DO_ROUND        3
+        paddd   1*16(TBL), X1
+        movdqa  X1, _XFER(%rsp)
+        add     $2*16, TBL
+        DO_ROUND        0
+        DO_ROUND        1
+        DO_ROUND        2
+        DO_ROUND        3
+
+        movdqa  X2, X0
+        movdqa  X3, X1
+
+        sub     $1, SRND
+        jne     loop2
+
+        addm    (4*0)(CTX),a
+        addm    (4*1)(CTX),b
+        addm    (4*2)(CTX),c
+        addm    (4*3)(CTX),d
+        addm    (4*4)(CTX),e
+        addm    (4*5)(CTX),f
+        addm    (4*6)(CTX),g
+        addm    (4*7)(CTX),h
+
+        mov     _INP(%rsp), INP
+        add     $64, INP
+        cmp     _INP_END(%rsp), INP
+        jne     loop0
+
+done_hash:
+
+        mov     %r12, %rsp
+
+        popq    %r12
+        popq    %r15
+        popq    %r14
+        popq    %r13
+        popq    %rbp
+        popq    %rbx
+
+        ret
+ENDPROC(sha256_transform_ssse3)
+
+.data
+.align 64
+K256:
+        .long 0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5
+        .long 0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5
+        .long 0xd807aa98,0x12835b01,0x243185be,0x550c7dc3
+        .long 0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174
+        .long 0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc
+        .long 0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da
+        .long 0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7
+        .long 0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967
+        .long 0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13
+        .long 0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85
+        .long 0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3
+        .long 0xd192e819,0xd6990624,0xf40e3585,0x106aa070
+        .long 0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5
+        .long 0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3
+        .long 0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208
+        .long 0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
+
+PSHUFFLE_BYTE_FLIP_MASK:
+        .octa 0x0c0d0e0f08090a0b0405060700010203
+
+# shuffle xBxA -> 00BA
+_SHUF_00BA:
+        .octa 0xFFFFFFFFFFFFFFFF0b0a090803020100
+
+# shuffle xDxC -> DC00
+_SHUF_DC00:
+        .octa 0x0b0a090803020100FFFFFFFFFFFFFFFF
diff --git a/arch/x86/crypto/sha256_ssse3_glue.c b/arch/x86/crypto/sha256_ssse3_glue.c
new file mode 100644
index 000000000000..597d4da69656
--- /dev/null
+++ b/arch/x86/crypto/sha256_ssse3_glue.c
@@ -0,0 +1,275 @@
+/*
+ * Cryptographic API.
+ *
+ * Glue code for the SHA256 Secure Hash Algorithm assembler
+ * implementation using supplemental SSE3 / AVX / AVX2 instructions.
+ *
+ * This file is based on sha256_generic.c
+ *
+ * Copyright (C) 2013 Intel Corporation.
+ *
+ * Author:
+ *     Tim Chen <tim.c.chen@linux.intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+
+#define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
+
+#include <crypto/internal/hash.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/cryptohash.h>
+#include <linux/types.h>
+#include <crypto/sha.h>
+#include <asm/byteorder.h>
+#include <asm/i387.h>
+#include <asm/xcr.h>
+#include <asm/xsave.h>
+#include <linux/string.h>
+
+asmlinkage void sha256_transform_ssse3(const char *data, u32 *digest,
+                                     u64 rounds);
+#ifdef CONFIG_AS_AVX
+asmlinkage void sha256_transform_avx(const char *data, u32 *digest,
+                                     u64 rounds);
+#endif
+#ifdef CONFIG_AS_AVX2
+asmlinkage void sha256_transform_rorx(const char *data, u32 *digest,
+                                     u64 rounds);
+#endif
+
+static asmlinkage void (*sha256_transform_asm)(const char *, u32 *, u64);
+
+
+static int sha256_ssse3_init(struct shash_desc *desc)
+{
+        struct sha256_state *sctx = shash_desc_ctx(desc);
+
+        sctx->state[0] = SHA256_H0;
+        sctx->state[1] = SHA256_H1;
+        sctx->state[2] = SHA256_H2;
+        sctx->state[3] = SHA256_H3;
+        sctx->state[4] = SHA256_H4;
+        sctx->state[5] = SHA256_H5;
+        sctx->state[6] = SHA256_H6;
+        sctx->state[7] = SHA256_H7;
+        sctx->count = 0;
+
+        return 0;
+}
+
+static int __sha256_ssse3_update(struct shash_desc *desc, const u8 *data,
+                               unsigned int len, unsigned int partial)
+{
+        struct sha256_state *sctx = shash_desc_ctx(desc);
+        unsigned int done = 0;
+
+        sctx->count += len;
+
+        if (partial) {
+                done = SHA256_BLOCK_SIZE - partial;
+                memcpy(sctx->buf + partial, data, done);
+                sha256_transform_asm(sctx->buf, sctx->state, 1);
+        }
+
+        if (len - done >= SHA256_BLOCK_SIZE) {
+                const unsigned int rounds = (len - done) / SHA256_BLOCK_SIZE;
+
+                sha256_transform_asm(data + done, sctx->state, (u64) rounds);
+
+                done += rounds * SHA256_BLOCK_SIZE;
+        }
+
+        memcpy(sctx->buf, data + done, len - done);
+
+        return 0;
+}
+
+static int sha256_ssse3_update(struct shash_desc *desc, const u8 *data,
+                             unsigned int len)
+{
+        struct sha256_state *sctx = shash_desc_ctx(desc);
+        unsigned int partial = sctx->count % SHA256_BLOCK_SIZE;
+        int res;
+
+        /* Handle the fast case right here */
+        if (partial + len < SHA256_BLOCK_SIZE) {
+                sctx->count += len;
+                memcpy(sctx->buf + partial, data, len);
+
+                return 0;
+        }
+
+        if (!irq_fpu_usable()) {
+                res = crypto_sha256_update(desc, data, len);
+        } else {
+                kernel_fpu_begin();
+                res = __sha256_ssse3_update(desc, data, len, partial);
+                kernel_fpu_end();
+        }
+
+        return res;
+}
+
+
+/* Add padding and return the message digest. */
+static int sha256_ssse3_final(struct shash_desc *desc, u8 *out)
+{
+        struct sha256_state *sctx = shash_desc_ctx(desc);
+        unsigned int i, index, padlen;
+        __be32 *dst = (__be32 *)out;
+        __be64 bits;
+        static const u8 padding[SHA256_BLOCK_SIZE] = { 0x80, };
+
+        bits = cpu_to_be64(sctx->count << 3);
+
+        /* Pad out to 56 mod 64 and append length */
+        index = sctx->count % SHA256_BLOCK_SIZE;
+        padlen = (index < 56) ? (56 - index) : ((SHA256_BLOCK_SIZE+56)-index);
+
+        if (!irq_fpu_usable()) {
+                crypto_sha256_update(desc, padding, padlen);
+                crypto_sha256_update(desc, (const u8 *)&bits, sizeof(bits));
+        } else {
+                kernel_fpu_begin();
+                /* We need to fill a whole block for __sha256_ssse3_update() */
+                if (padlen <= 56) {
+                        sctx->count += padlen;
+                        memcpy(sctx->buf + index, padding, padlen);
+                } else {
+                        __sha256_ssse3_update(desc, padding, padlen, index);
+                }
+                __sha256_ssse3_update(desc, (const u8 *)&bits,
+                                        sizeof(bits), 56);
+                kernel_fpu_end();
+        }
+
+        /* Store state in digest */
+        for (i = 0; i < 8; i++)
+                dst[i] = cpu_to_be32(sctx->state[i]);
+
+        /* Wipe context */
+        memset(sctx, 0, sizeof(*sctx));
+
+        return 0;
+}
+
+static int sha256_ssse3_export(struct shash_desc *desc, void *out)
+{
+        struct sha256_state *sctx = shash_desc_ctx(desc);
+
+        memcpy(out, sctx, sizeof(*sctx));
+
+        return 0;
+}
+
+static int sha256_ssse3_import(struct shash_desc *desc, const void *in)
+{
+        struct sha256_state *sctx = shash_desc_ctx(desc);
+
+        memcpy(sctx, in, sizeof(*sctx));
+
+        return 0;
+}
+
+static struct shash_alg alg = {
+        .digestsize     =       SHA256_DIGEST_SIZE,
+        .init           =       sha256_ssse3_init,
+        .update         =       sha256_ssse3_update,
+        .final          =       sha256_ssse3_final,
+        .export         =       sha256_ssse3_export,
+        .import         =       sha256_ssse3_import,
+        .descsize       =       sizeof(struct sha256_state),
+        .statesize      =       sizeof(struct sha256_state),
+        .base           =       {
+                .cra_name       =       "sha256",
+                .cra_driver_name =      "sha256-ssse3",
+                .cra_priority   =       150,
+                .cra_flags      =       CRYPTO_ALG_TYPE_SHASH,
+                .cra_blocksize  =       SHA256_BLOCK_SIZE,
+                .cra_module     =       THIS_MODULE,
+        }
+};
+
+#ifdef CONFIG_AS_AVX
+static bool __init avx_usable(void)
+{
+        u64 xcr0;
+
+        if (!cpu_has_avx || !cpu_has_osxsave)
+                return false;
+
+        xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
+        if ((xcr0 & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM)) {
+                pr_info("AVX detected but unusable.\n");
+
+                return false;
+        }
+
+        return true;
+}
+#endif
+
+static int __init sha256_ssse3_mod_init(void)
+{
+        /* test for SSE3 first */
+        if (cpu_has_ssse3)
+                sha256_transform_asm = sha256_transform_ssse3;
+
+#ifdef CONFIG_AS_AVX
+        /* allow AVX to override SSSE3, it's a little faster */
+        if (avx_usable()) {
+#ifdef CONFIG_AS_AVX2
+                if (boot_cpu_has(X86_FEATURE_AVX2))
+                        sha256_transform_asm = sha256_transform_rorx;
+                else
+#endif
+                        sha256_transform_asm = sha256_transform_avx;
+        }
+#endif
+
+        if (sha256_transform_asm) {
+#ifdef CONFIG_AS_AVX
+                if (sha256_transform_asm == sha256_transform_avx)
+                        pr_info("Using AVX optimized SHA-256 implementation\n");
+#ifdef CONFIG_AS_AVX2
+                else if (sha256_transform_asm == sha256_transform_rorx)
+                        pr_info("Using AVX2 optimized SHA-256 implementation\n");
+#endif
+                else
+#endif
+                        pr_info("Using SSSE3 optimized SHA-256 implementation\n");
+                return crypto_register_shash(&alg);
+        }
+        pr_info("Neither AVX nor SSSE3 is available/usable.\n");
+
+        return -ENODEV;
+}
+
+static void __exit sha256_ssse3_mod_fini(void)
+{
+        crypto_unregister_shash(&alg);
+}
+
+module_init(sha256_ssse3_mod_init);
+module_exit(sha256_ssse3_mod_fini);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("SHA256 Secure Hash Algorithm, Supplemental SSE3 accelerated");
+
+MODULE_ALIAS("sha256");
diff --git a/arch/x86/crypto/sha512-avx-asm.S b/arch/x86/crypto/sha512-avx-asm.S
new file mode 100644
index 000000000000..974dde9bc6cd
--- /dev/null
+++ b/arch/x86/crypto/sha512-avx-asm.S
@@ -0,0 +1,423 @@
+########################################################################
+# Implement fast SHA-512 with AVX instructions. (x86_64)
+#
+# Copyright (C) 2013 Intel Corporation.
+#
+# Authors:
+#     James Guilford <james.guilford@intel.com>
+#     Kirk Yap <kirk.s.yap@intel.com>
+#     David Cote <david.m.cote@intel.com>
+#     Tim Chen <tim.c.chen@linux.intel.com>
+#
+# This software is available to you under a choice of one of two
+# licenses.  You may choose to be licensed under the terms of the GNU
+# General Public License (GPL) Version 2, available from the file
+# COPYING in the main directory of this source tree, or the
+# OpenIB.org BSD license below:
+#
+#     Redistribution and use in source and binary forms, with or
+#     without modification, are permitted provided that the following
+#     conditions are met:
+#
+#      - Redistributions of source code must retain the above
+#        copyright notice, this list of conditions and the following
+#        disclaimer.
+#
+#      - Redistributions in binary form must reproduce the above
+#        copyright notice, this list of conditions and the following
+#        disclaimer in the documentation and/or other materials
+#        provided with the distribution.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+########################################################################
+#
+# This code is described in an Intel White-Paper:
+# "Fast SHA-512 Implementations on Intel Architecture Processors"
+#
+# To find it, surf to http://www.intel.com/p/en_US/embedded
+# and search for that title.
+#
+########################################################################
+
+#ifdef CONFIG_AS_AVX
+#include <linux/linkage.h>
+
+.text
+
+# Virtual Registers
+# ARG1
+msg     = %rdi
+# ARG2
+digest  = %rsi
+# ARG3
+msglen  = %rdx
+T1      = %rcx
+T2      = %r8
+a_64    = %r9
+b_64    = %r10
+c_64    = %r11
+d_64    = %r12
+e_64    = %r13
+f_64    = %r14
+g_64    = %r15
+h_64    = %rbx
+tmp0    = %rax
+
+# Local variables (stack frame)
+
+# Message Schedule
+W_SIZE = 80*8
+# W[t] + K[t] | W[t+1] + K[t+1]
+WK_SIZE = 2*8
+RSPSAVE_SIZE = 1*8
+GPRSAVE_SIZE = 5*8
+
+frame_W = 0
+frame_WK = frame_W + W_SIZE
+frame_RSPSAVE = frame_WK + WK_SIZE
+frame_GPRSAVE = frame_RSPSAVE + RSPSAVE_SIZE
+frame_size = frame_GPRSAVE + GPRSAVE_SIZE
+
+# Useful QWORD "arrays" for simpler memory references
+# MSG, DIGEST, K_t, W_t are arrays
+# WK_2(t) points to 1 of 2 qwords at frame.WK depdending on t being odd/even
+
+# Input message (arg1)
+#define MSG(i)    8*i(msg)
+
+# Output Digest (arg2)
+#define DIGEST(i) 8*i(digest)
+
+# SHA Constants (static mem)
+#define K_t(i)    8*i+K512(%rip)
+
+# Message Schedule (stack frame)
+#define W_t(i)    8*i+frame_W(%rsp)
+
+# W[t]+K[t] (stack frame)
+#define WK_2(i)   8*((i%2))+frame_WK(%rsp)
+
+.macro RotateState
+        # Rotate symbols a..h right
+        TMP   = h_64
+        h_64  = g_64
+        g_64  = f_64
+        f_64  = e_64
+        e_64  = d_64
+        d_64  = c_64
+        c_64  = b_64
+        b_64  = a_64
+        a_64  = TMP
+.endm
+
+.macro RORQ p1 p2
+        # shld is faster than ror on Sandybridge
+        shld    $(64-\p2), \p1, \p1
+.endm
+
+.macro SHA512_Round rnd
+        # Compute Round %%t
+        mov     f_64, T1          # T1 = f
+        mov     e_64, tmp0        # tmp = e
+        xor     g_64, T1          # T1 = f ^ g
+        RORQ    tmp0, 23   # 41    # tmp = e ror 23
+        and     e_64, T1          # T1 = (f ^ g) & e
+        xor     e_64, tmp0        # tmp = (e ror 23) ^ e
+        xor     g_64, T1          # T1 = ((f ^ g) & e) ^ g = CH(e,f,g)
+        idx = \rnd
+        add     WK_2(idx), T1     # W[t] + K[t] from message scheduler
+        RORQ    tmp0, 4   # 18    # tmp = ((e ror 23) ^ e) ror 4
+        xor     e_64, tmp0        # tmp = (((e ror 23) ^ e) ror 4) ^ e
+        mov     a_64, T2          # T2 = a
+        add     h_64, T1          # T1 = CH(e,f,g) + W[t] + K[t] + h
+        RORQ    tmp0, 14  # 14    # tmp = ((((e ror23)^e)ror4)^e)ror14 = S1(e)
+        add     tmp0, T1          # T1 = CH(e,f,g) + W[t] + K[t] + S1(e)
+        mov     a_64, tmp0        # tmp = a
+        xor     c_64, T2          # T2 = a ^ c
+        and     c_64, tmp0        # tmp = a & c
+        and     b_64, T2          # T2 = (a ^ c) & b
+        xor     tmp0, T2          # T2 = ((a ^ c) & b) ^ (a & c) = Maj(a,b,c)
+        mov     a_64, tmp0        # tmp = a
+        RORQ    tmp0, 5  # 39     # tmp = a ror 5
+        xor     a_64, tmp0        # tmp = (a ror 5) ^ a
+        add     T1, d_64          # e(next_state) = d + T1
+        RORQ    tmp0, 6  # 34     # tmp = ((a ror 5) ^ a) ror 6
+        xor     a_64, tmp0        # tmp = (((a ror 5) ^ a) ror 6) ^ a
+        lea     (T1, T2), h_64    # a(next_state) = T1 + Maj(a,b,c)
+        RORQ    tmp0, 28  # 28    # tmp = ((((a ror5)^a)ror6)^a)ror28 = S0(a)
+        add     tmp0, h_64        # a(next_state) = T1 + Maj(a,b,c) S0(a)
+        RotateState
+.endm
+
+.macro SHA512_2Sched_2Round_avx rnd
+        # Compute rounds t-2 and t-1
+        # Compute message schedule QWORDS t and t+1
+
+        #   Two rounds are computed based on the values for K[t-2]+W[t-2] and
+        # K[t-1]+W[t-1] which were previously stored at WK_2 by the message
+        # scheduler.
+        #   The two new schedule QWORDS are stored at [W_t(t)] and [W_t(t+1)].
+        # They are then added to their respective SHA512 constants at
+        # [K_t(t)] and [K_t(t+1)] and stored at dqword [WK_2(t)]
+        #   For brievity, the comments following vectored instructions only refer to
+        # the first of a pair of QWORDS.
+        # Eg. XMM4=W[t-2] really means XMM4={W[t-2]|W[t-1]}
+        #   The computation of the message schedule and the rounds are tightly
+        # stitched to take advantage of instruction-level parallelism.
+
+        idx = \rnd - 2
+        vmovdqa W_t(idx), %xmm4         # XMM4 = W[t-2]
+        idx = \rnd - 15
+        vmovdqu W_t(idx), %xmm5         # XMM5 = W[t-15]
+        mov     f_64, T1
+        vpsrlq  $61, %xmm4, %xmm0       # XMM0 = W[t-2]>>61
+        mov     e_64, tmp0
+        vpsrlq  $1, %xmm5, %xmm6        # XMM6 = W[t-15]>>1
+        xor     g_64, T1
+        RORQ    tmp0, 23 # 41
+        vpsrlq  $19, %xmm4, %xmm1       # XMM1 = W[t-2]>>19
+        and     e_64, T1
+        xor     e_64, tmp0
+        vpxor   %xmm1, %xmm0, %xmm0     # XMM0 = W[t-2]>>61 ^ W[t-2]>>19
+        xor     g_64, T1
+        idx = \rnd
+        add     WK_2(idx), T1#
+        vpsrlq  $8, %xmm5, %xmm7        # XMM7 = W[t-15]>>8
+        RORQ    tmp0, 4 # 18
+        vpsrlq  $6, %xmm4, %xmm2        # XMM2 = W[t-2]>>6
+        xor     e_64, tmp0
+        mov     a_64, T2
+        add     h_64, T1
+        vpxor   %xmm7, %xmm6, %xmm6     # XMM6 = W[t-15]>>1 ^ W[t-15]>>8
+        RORQ    tmp0, 14 # 14
+        add     tmp0, T1
+        vpsrlq  $7, %xmm5, %xmm8        # XMM8 = W[t-15]>>7
+        mov     a_64, tmp0
+        xor     c_64, T2
+        vpsllq  $(64-61), %xmm4, %xmm3  # XMM3 = W[t-2]<<3
+        and     c_64, tmp0
+        and     b_64, T2
+        vpxor   %xmm3, %xmm2, %xmm2     # XMM2 = W[t-2]>>6 ^ W[t-2]<<3
+        xor     tmp0, T2
+        mov     a_64, tmp0
+        vpsllq  $(64-1), %xmm5, %xmm9   # XMM9 = W[t-15]<<63
+        RORQ    tmp0, 5 # 39
+        vpxor   %xmm9, %xmm8, %xmm8     # XMM8 = W[t-15]>>7 ^ W[t-15]<<63
+        xor     a_64, tmp0
+        add     T1, d_64
+        RORQ    tmp0, 6 # 34
+        xor     a_64, tmp0
+        vpxor   %xmm8, %xmm6, %xmm6     # XMM6 = W[t-15]>>1 ^ W[t-15]>>8 ^
+                                        #  W[t-15]>>7 ^ W[t-15]<<63
+        lea     (T1, T2), h_64
+        RORQ    tmp0, 28 # 28
+        vpsllq  $(64-19), %xmm4, %xmm4  # XMM4 = W[t-2]<<25
+        add     tmp0, h_64
+        RotateState
+        vpxor   %xmm4, %xmm0, %xmm0     # XMM0 = W[t-2]>>61 ^ W[t-2]>>19 ^
+                                        #        W[t-2]<<25
+        mov     f_64, T1
+        vpxor   %xmm2, %xmm0, %xmm0     # XMM0 = s1(W[t-2])
+        mov     e_64, tmp0
+        xor     g_64, T1
+        idx = \rnd - 16
+        vpaddq  W_t(idx), %xmm0, %xmm0  # XMM0 = s1(W[t-2]) + W[t-16]
+        idx = \rnd - 7
+        vmovdqu W_t(idx), %xmm1         # XMM1 = W[t-7]
+        RORQ    tmp0, 23 # 41
+        and     e_64, T1
+        xor     e_64, tmp0
+        xor     g_64, T1
+        vpsllq  $(64-8), %xmm5, %xmm5   # XMM5 = W[t-15]<<56
+        idx = \rnd + 1
+        add     WK_2(idx), T1
+        vpxor   %xmm5, %xmm6, %xmm6     # XMM6 = s0(W[t-15])
+        RORQ    tmp0, 4 # 18
+        vpaddq  %xmm6, %xmm0, %xmm0     # XMM0 = s1(W[t-2]) + W[t-16] + s0(W[t-15])
+        xor     e_64, tmp0
+        vpaddq  %xmm1, %xmm0, %xmm0     # XMM0 = W[t] = s1(W[t-2]) + W[t-7] +
+                                        #               s0(W[t-15]) + W[t-16]
+        mov     a_64, T2
+        add     h_64, T1
+        RORQ    tmp0, 14 # 14
+        add     tmp0, T1
+        idx = \rnd
+        vmovdqa %xmm0, W_t(idx)         # Store W[t]
+        vpaddq  K_t(idx), %xmm0, %xmm0  # Compute W[t]+K[t]
+        vmovdqa %xmm0, WK_2(idx)        # Store W[t]+K[t] for next rounds
+        mov     a_64, tmp0
+        xor     c_64, T2
+        and     c_64, tmp0
+        and     b_64, T2
+        xor     tmp0, T2
+        mov     a_64, tmp0
+        RORQ    tmp0, 5 # 39
+        xor     a_64, tmp0
+        add     T1, d_64
+        RORQ    tmp0, 6 # 34
+        xor     a_64, tmp0
+        lea     (T1, T2), h_64
+        RORQ    tmp0, 28 # 28
+        add     tmp0, h_64
+        RotateState
+.endm
+
+########################################################################
+# void sha512_transform_avx(const void* M, void* D, u64 L)
+# Purpose: Updates the SHA512 digest stored at D with the message stored in M.
+# The size of the message pointed to by M must be an integer multiple of SHA512
+# message blocks.
+# L is the message length in SHA512 blocks
+########################################################################
+ENTRY(sha512_transform_avx)
+        cmp $0, msglen
+        je nowork
+
+        # Allocate Stack Space
+        mov     %rsp, %rax
+        sub     $frame_size, %rsp
+        and     $~(0x20 - 1), %rsp
+        mov     %rax, frame_RSPSAVE(%rsp)
+
+        # Save GPRs
+        mov     %rbx, frame_GPRSAVE(%rsp)
+        mov     %r12, frame_GPRSAVE +8*1(%rsp)
+        mov     %r13, frame_GPRSAVE +8*2(%rsp)
+        mov     %r14, frame_GPRSAVE +8*3(%rsp)
+        mov     %r15, frame_GPRSAVE +8*4(%rsp)
+
+updateblock:
+
+        # Load state variables
+        mov     DIGEST(0), a_64
+        mov     DIGEST(1), b_64
+        mov     DIGEST(2), c_64
+        mov     DIGEST(3), d_64
+        mov     DIGEST(4), e_64
+        mov     DIGEST(5), f_64
+        mov     DIGEST(6), g_64
+        mov     DIGEST(7), h_64
+
+        t = 0
+        .rept 80/2 + 1
+        # (80 rounds) / (2 rounds/iteration) + (1 iteration)
+        # +1 iteration because the scheduler leads hashing by 1 iteration
+                .if t < 2
+                        # BSWAP 2 QWORDS
+                        vmovdqa  XMM_QWORD_BSWAP(%rip), %xmm1
+                        vmovdqu  MSG(t), %xmm0
+                        vpshufb  %xmm1, %xmm0, %xmm0    # BSWAP
+                        vmovdqa  %xmm0, W_t(t) # Store Scheduled Pair
+                        vpaddq   K_t(t), %xmm0, %xmm0 # Compute W[t]+K[t]
+                        vmovdqa  %xmm0, WK_2(t) # Store into WK for rounds
+                .elseif t < 16
+                        # BSWAP 2 QWORDS# Compute 2 Rounds
+                        vmovdqu  MSG(t), %xmm0
+                        vpshufb  %xmm1, %xmm0, %xmm0    # BSWAP
+                        SHA512_Round t-2    # Round t-2
+                        vmovdqa  %xmm0, W_t(t) # Store Scheduled Pair
+                        vpaddq   K_t(t), %xmm0, %xmm0 # Compute W[t]+K[t]
+                        SHA512_Round t-1    # Round t-1
+                        vmovdqa  %xmm0, WK_2(t)# Store W[t]+K[t] into WK
+                .elseif t < 79
+                        # Schedule 2 QWORDS# Compute 2 Rounds
+                        SHA512_2Sched_2Round_avx t
+                .else
+                        # Compute 2 Rounds
+                        SHA512_Round t-2
+                        SHA512_Round t-1
+                .endif
+                t = t+2
+        .endr
+
+        # Update digest
+        add     a_64, DIGEST(0)
+        add     b_64, DIGEST(1)
+        add     c_64, DIGEST(2)
+        add     d_64, DIGEST(3)
+        add     e_64, DIGEST(4)
+        add     f_64, DIGEST(5)
+        add     g_64, DIGEST(6)
+        add     h_64, DIGEST(7)
+
+        # Advance to next message block
+        add     $16*8, msg
+        dec     msglen
+        jnz     updateblock
+
+        # Restore GPRs
+        mov     frame_GPRSAVE(%rsp),      %rbx
+        mov     frame_GPRSAVE +8*1(%rsp), %r12
+        mov     frame_GPRSAVE +8*2(%rsp), %r13
+        mov     frame_GPRSAVE +8*3(%rsp), %r14
+        mov     frame_GPRSAVE +8*4(%rsp), %r15
+
+        # Restore Stack Pointer
+        mov     frame_RSPSAVE(%rsp), %rsp
+
+nowork:
+        ret
+ENDPROC(sha512_transform_avx)
+
+########################################################################
+### Binary Data
+
+.data
+
+.align 16
+
+# Mask for byte-swapping a couple of qwords in an XMM register using (v)pshufb.
+XMM_QWORD_BSWAP:
+        .octa 0x08090a0b0c0d0e0f0001020304050607
+
+# K[t] used in SHA512 hashing
+K512:
+        .quad 0x428a2f98d728ae22,0x7137449123ef65cd
+        .quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
+        .quad 0x3956c25bf348b538,0x59f111f1b605d019
+        .quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118
+        .quad 0xd807aa98a3030242,0x12835b0145706fbe
+        .quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
+        .quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1
+        .quad 0x9bdc06a725c71235,0xc19bf174cf692694
+        .quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3
+        .quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
+        .quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483
+        .quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5
+        .quad 0x983e5152ee66dfab,0xa831c66d2db43210
+        .quad 0xb00327c898fb213f,0xbf597fc7beef0ee4
+        .quad 0xc6e00bf33da88fc2,0xd5a79147930aa725
+        .quad 0x06ca6351e003826f,0x142929670a0e6e70
+        .quad 0x27b70a8546d22ffc,0x2e1b21385c26c926
+        .quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df
+        .quad 0x650a73548baf63de,0x766a0abb3c77b2a8
+        .quad 0x81c2c92e47edaee6,0x92722c851482353b
+        .quad 0xa2bfe8a14cf10364,0xa81a664bbc423001
+        .quad 0xc24b8b70d0f89791,0xc76c51a30654be30
+        .quad 0xd192e819d6ef5218,0xd69906245565a910
+        .quad 0xf40e35855771202a,0x106aa07032bbd1b8
+        .quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53
+        .quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8
+        .quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb
+        .quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3
+        .quad 0x748f82ee5defb2fc,0x78a5636f43172f60
+        .quad 0x84c87814a1f0ab72,0x8cc702081a6439ec
+        .quad 0x90befffa23631e28,0xa4506cebde82bde9
+        .quad 0xbef9a3f7b2c67915,0xc67178f2e372532b
+        .quad 0xca273eceea26619c,0xd186b8c721c0c207
+        .quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178
+        .quad 0x06f067aa72176fba,0x0a637dc5a2c898a6
+        .quad 0x113f9804bef90dae,0x1b710b35131c471b
+        .quad 0x28db77f523047d84,0x32caab7b40c72493
+        .quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c
+        .quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a
+        .quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817
+#endif
diff --git a/arch/x86/crypto/sha512-avx2-asm.S b/arch/x86/crypto/sha512-avx2-asm.S
new file mode 100644
index 000000000000..568b96105f5c
--- /dev/null
+++ b/arch/x86/crypto/sha512-avx2-asm.S
@@ -0,0 +1,743 @@
+########################################################################
+# Implement fast SHA-512 with AVX2 instructions. (x86_64)
+#
+# Copyright (C) 2013 Intel Corporation.
+#
+# Authors:
+#     James Guilford <james.guilford@intel.com>
+#     Kirk Yap <kirk.s.yap@intel.com>
+#     David Cote <david.m.cote@intel.com>
+#     Tim Chen <tim.c.chen@linux.intel.com>
+#
+# This software is available to you under a choice of one of two
+# licenses.  You may choose to be licensed under the terms of the GNU
+# General Public License (GPL) Version 2, available from the file
+# COPYING in the main directory of this source tree, or the
+# OpenIB.org BSD license below:
+#
+#     Redistribution and use in source and binary forms, with or
+#     without modification, are permitted provided that the following
+#     conditions are met:
+#
+#      - Redistributions of source code must retain the above
+#        copyright notice, this list of conditions and the following
+#        disclaimer.
+#
+#      - Redistributions in binary form must reproduce the above
+#        copyright notice, this list of conditions and the following
+#        disclaimer in the documentation and/or other materials
+#        provided with the distribution.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+########################################################################
+#
+# This code is described in an Intel White-Paper:
+# "Fast SHA-512 Implementations on Intel Architecture Processors"
+#
+# To find it, surf to http://www.intel.com/p/en_US/embedded
+# and search for that title.
+#
+########################################################################
+# This code schedules 1 blocks at a time, with 4 lanes per block
+########################################################################
+
+#ifdef CONFIG_AS_AVX2
+#include <linux/linkage.h>
+
+.text
+
+# Virtual Registers
+Y_0 = %ymm4
+Y_1 = %ymm5
+Y_2 = %ymm6
+Y_3 = %ymm7
+
+YTMP0 = %ymm0
+YTMP1 = %ymm1
+YTMP2 = %ymm2
+YTMP3 = %ymm3
+YTMP4 = %ymm8
+XFER  = YTMP0
+
+BYTE_FLIP_MASK  = %ymm9
+
+# 1st arg
+INP         = %rdi
+# 2nd arg
+CTX         = %rsi
+# 3rd arg
+NUM_BLKS    = %rdx
+
+c           = %rcx
+d           = %r8
+e           = %rdx
+y3          = %rdi
+
+TBL   = %rbp
+
+a     = %rax
+b     = %rbx
+
+f     = %r9
+g     = %r10
+h     = %r11
+old_h = %r11
+
+T1    = %r12
+y0    = %r13
+y1    = %r14
+y2    = %r15
+
+y4    = %r12
+
+# Local variables (stack frame)
+XFER_SIZE = 4*8
+SRND_SIZE = 1*8
+INP_SIZE = 1*8
+INPEND_SIZE = 1*8
+RSPSAVE_SIZE = 1*8
+GPRSAVE_SIZE = 6*8
+
+frame_XFER = 0
+frame_SRND = frame_XFER + XFER_SIZE
+frame_INP = frame_SRND + SRND_SIZE
+frame_INPEND = frame_INP + INP_SIZE
+frame_RSPSAVE = frame_INPEND + INPEND_SIZE
+frame_GPRSAVE = frame_RSPSAVE + RSPSAVE_SIZE
+frame_size = frame_GPRSAVE + GPRSAVE_SIZE
+
+## assume buffers not aligned
+#define VMOVDQ vmovdqu
+
+# addm [mem], reg
+# Add reg to mem using reg-mem add and store
+.macro addm p1 p2
+        add     \p1, \p2
+        mov     \p2, \p1
+.endm
+
+
+# COPY_YMM_AND_BSWAP ymm, [mem], byte_flip_mask
+# Load ymm with mem and byte swap each dword
+.macro COPY_YMM_AND_BSWAP p1 p2 p3
+        VMOVDQ \p2, \p1
+        vpshufb \p3, \p1, \p1
+.endm
+# rotate_Ys
+# Rotate values of symbols Y0...Y3
+.macro rotate_Ys
+        Y_ = Y_0
+        Y_0 = Y_1
+        Y_1 = Y_2
+        Y_2 = Y_3
+        Y_3 = Y_
+.endm
+
+# RotateState
+.macro RotateState
+        # Rotate symbols a..h right
+        old_h  = h
+        TMP_   = h
+        h      = g
+        g      = f
+        f      = e
+        e      = d
+        d      = c
+        c      = b
+        b      = a
+        a      = TMP_
+.endm
+
+# macro MY_VPALIGNR     YDST, YSRC1, YSRC2, RVAL
+# YDST = {YSRC1, YSRC2} >> RVAL*8
+.macro MY_VPALIGNR YDST YSRC1 YSRC2 RVAL
+        vperm2f128      $0x3, \YSRC2, \YSRC1, \YDST     # YDST = {YS1_LO, YS2_HI}
+        vpalignr        $\RVAL, \YSRC2, \YDST, \YDST    # YDST = {YDS1, YS2} >> RVAL*8
+.endm
+
+.macro FOUR_ROUNDS_AND_SCHED
+################################### RND N + 0 #########################################
+
+        # Extract w[t-7]
+        MY_VPALIGNR     YTMP0, Y_3, Y_2, 8              # YTMP0 = W[-7]
+        # Calculate w[t-16] + w[t-7]
+        vpaddq          Y_0, YTMP0, YTMP0               # YTMP0 = W[-7] + W[-16]
+        # Extract w[t-15]
+        MY_VPALIGNR     YTMP1, Y_1, Y_0, 8              # YTMP1 = W[-15]
+
+        # Calculate sigma0
+
+        # Calculate w[t-15] ror 1
+        vpsrlq          $1, YTMP1, YTMP2
+        vpsllq          $(64-1), YTMP1, YTMP3
+        vpor            YTMP2, YTMP3, YTMP3             # YTMP3 = W[-15] ror 1
+        # Calculate w[t-15] shr 7
+        vpsrlq          $7, YTMP1, YTMP4                # YTMP4 = W[-15] >> 7
+
+        mov     a, y3           # y3 = a                                # MAJA
+        rorx    $41, e, y0      # y0 = e >> 41                          # S1A
+        rorx    $18, e, y1      # y1 = e >> 18                          # S1B
+        add     frame_XFER(%rsp),h              # h = k + w + h         # --
+        or      c, y3           # y3 = a|c                              # MAJA
+        mov     f, y2           # y2 = f                                # CH
+        rorx    $34, a, T1      # T1 = a >> 34                          # S0B
+
+        xor     y1, y0          # y0 = (e>>41) ^ (e>>18)                # S1
+        xor     g, y2           # y2 = f^g                              # CH
+        rorx    $14, e, y1      # y1 = (e >> 14)                        # S1
+
+        and     e, y2           # y2 = (f^g)&e                          # CH
+        xor     y1, y0          # y0 = (e>>41) ^ (e>>18) ^ (e>>14)      # S1
+        rorx    $39, a, y1      # y1 = a >> 39                          # S0A
+        add     h, d            # d = k + w + h + d                     # --
+
+        and     b, y3           # y3 = (a|c)&b                          # MAJA
+        xor     T1, y1          # y1 = (a>>39) ^ (a>>34)                # S0
+        rorx    $28, a, T1      # T1 = (a >> 28)                        # S0
+
+        xor     g, y2           # y2 = CH = ((f^g)&e)^g                 # CH
+        xor     T1, y1          # y1 = (a>>39) ^ (a>>34) ^ (a>>28)      # S0
+        mov     a, T1           # T1 = a                                # MAJB
+        and     c, T1           # T1 = a&c                              # MAJB
+
+        add     y0, y2          # y2 = S1 + CH                          # --
+        or      T1, y3          # y3 = MAJ = (a|c)&b)|(a&c)             # MAJ
+        add     y1, h           # h = k + w + h + S0                    # --
+
+        add     y2, d           # d = k + w + h + d + S1 + CH = d + t1  # --
+
+        add     y2, h           # h = k + w + h + S0 + S1 + CH = t1 + S0# --
+        add     y3, h           # h = t1 + S0 + MAJ                     # --
+
+        RotateState
+
+################################### RND N + 1 #########################################
+
+        # Calculate w[t-15] ror 8
+        vpsrlq          $8, YTMP1, YTMP2
+        vpsllq          $(64-8), YTMP1, YTMP1
+        vpor            YTMP2, YTMP1, YTMP1             # YTMP1 = W[-15] ror 8
+        # XOR the three components
+        vpxor           YTMP4, YTMP3, YTMP3             # YTMP3 = W[-15] ror 1 ^ W[-15] >> 7
+        vpxor           YTMP1, YTMP3, YTMP1             # YTMP1 = s0
+
+
+        # Add three components, w[t-16], w[t-7] and sigma0
+        vpaddq          YTMP1, YTMP0, YTMP0             # YTMP0 = W[-16] + W[-7] + s0
+        # Move to appropriate lanes for calculating w[16] and w[17]
+        vperm2f128      $0x0, YTMP0, YTMP0, Y_0         # Y_0 = W[-16] + W[-7] + s0 {BABA}
+        # Move to appropriate lanes for calculating w[18] and w[19]
+        vpand           MASK_YMM_LO(%rip), YTMP0, YTMP0 # YTMP0 = W[-16] + W[-7] + s0 {DC00}
+
+        # Calculate w[16] and w[17] in both 128 bit lanes
+
+        # Calculate sigma1 for w[16] and w[17] on both 128 bit lanes
+        vperm2f128      $0x11, Y_3, Y_3, YTMP2          # YTMP2 = W[-2] {BABA}
+        vpsrlq          $6, YTMP2, YTMP4                # YTMP4 = W[-2] >> 6 {BABA}
+
+
+        mov     a, y3           # y3 = a                                # MAJA
+        rorx    $41, e, y0      # y0 = e >> 41                          # S1A
+        rorx    $18, e, y1      # y1 = e >> 18                          # S1B
+        add     1*8+frame_XFER(%rsp), h         # h = k + w + h         # --
+        or      c, y3           # y3 = a|c                              # MAJA
+
+
+        mov     f, y2           # y2 = f                                # CH
+        rorx    $34, a, T1      # T1 = a >> 34                          # S0B
+        xor     y1, y0          # y0 = (e>>41) ^ (e>>18)                # S1
+        xor     g, y2           # y2 = f^g                              # CH
+
+
+        rorx    $14, e, y1      # y1 = (e >> 14)                        # S1
+        xor     y1, y0          # y0 = (e>>41) ^ (e>>18) ^ (e>>14)      # S1
+        rorx    $39, a, y1      # y1 = a >> 39                          # S0A
+        and     e, y2           # y2 = (f^g)&e                          # CH
+        add     h, d            # d = k + w + h + d                     # --
+
+        and     b, y3           # y3 = (a|c)&b                          # MAJA
+        xor     T1, y1          # y1 = (a>>39) ^ (a>>34)                # S0
+
+        rorx    $28, a, T1      # T1 = (a >> 28)                        # S0
+        xor     g, y2           # y2 = CH = ((f^g)&e)^g                 # CH
+
+        xor     T1, y1          # y1 = (a>>39) ^ (a>>34) ^ (a>>28)      # S0
+        mov     a, T1           # T1 = a                                # MAJB
+        and     c, T1           # T1 = a&c                              # MAJB
+        add     y0, y2          # y2 = S1 + CH                          # --
+
+        or      T1, y3          # y3 = MAJ = (a|c)&b)|(a&c)             # MAJ
+        add     y1, h           # h = k + w + h + S0                    # --
+
+        add     y2, d           # d = k + w + h + d + S1 + CH = d + t1  # --
+        add     y2, h           # h = k + w + h + S0 + S1 + CH = t1 + S0# --
+        add     y3, h           # h = t1 + S0 + MAJ                     # --
+
+        RotateState
+
+
+################################### RND N + 2 #########################################
+
+        vpsrlq          $19, YTMP2, YTMP3               # YTMP3 = W[-2] >> 19 {BABA}
+        vpsllq          $(64-19), YTMP2, YTMP1          # YTMP1 = W[-2] << 19 {BABA}
+        vpor            YTMP1, YTMP3, YTMP3             # YTMP3 = W[-2] ror 19 {BABA}
+        vpxor           YTMP3, YTMP4, YTMP4             # YTMP4 = W[-2] ror 19 ^ W[-2] >> 6 {BABA}
+        vpsrlq          $61, YTMP2, YTMP3               # YTMP3 = W[-2] >> 61 {BABA}
+        vpsllq          $(64-61), YTMP2, YTMP1          # YTMP1 = W[-2] << 61 {BABA}
+        vpor            YTMP1, YTMP3, YTMP3             # YTMP3 = W[-2] ror 61 {BABA}
+        vpxor           YTMP3, YTMP4, YTMP4             # YTMP4 = s1 = (W[-2] ror 19) ^
+                                                        #  (W[-2] ror 61) ^ (W[-2] >> 6) {BABA}
+
+        # Add sigma1 to the other compunents to get w[16] and w[17]
+        vpaddq          YTMP4, Y_0, Y_0                 # Y_0 = {W[1], W[0], W[1], W[0]}
+
+        # Calculate sigma1 for w[18] and w[19] for upper 128 bit lane
+        vpsrlq          $6, Y_0, YTMP4                  # YTMP4 = W[-2] >> 6 {DC--}
+
+        mov     a, y3           # y3 = a                                # MAJA
+        rorx    $41, e, y0      # y0 = e >> 41                          # S1A
+        add     2*8+frame_XFER(%rsp), h         # h = k + w + h         # --
+
+        rorx    $18, e, y1      # y1 = e >> 18                          # S1B
+        or      c, y3           # y3 = a|c                              # MAJA
+        mov     f, y2           # y2 = f                                # CH
+        xor     g, y2           # y2 = f^g                              # CH
+
+        rorx    $34, a, T1      # T1 = a >> 34                          # S0B
+        xor     y1, y0          # y0 = (e>>41) ^ (e>>18)                # S1
+        and     e, y2           # y2 = (f^g)&e                          # CH
+
+        rorx    $14, e, y1      # y1 = (e >> 14)                        # S1
+        add     h, d            # d = k + w + h + d                     # --
+        and     b, y3           # y3 = (a|c)&b                          # MAJA
+
+        xor     y1, y0          # y0 = (e>>41) ^ (e>>18) ^ (e>>14)      # S1
+        rorx    $39, a, y1      # y1 = a >> 39                          # S0A
+        xor     g, y2           # y2 = CH = ((f^g)&e)^g                 # CH
+
+        xor     T1, y1          # y1 = (a>>39) ^ (a>>34)                # S0
+        rorx    $28, a, T1      # T1 = (a >> 28)                        # S0
+
+        xor     T1, y1          # y1 = (a>>39) ^ (a>>34) ^ (a>>28)      # S0
+        mov     a, T1           # T1 = a                                # MAJB
+        and     c, T1           # T1 = a&c                              # MAJB
+        add     y0, y2          # y2 = S1 + CH                          # --
+
+        or      T1, y3          # y3 = MAJ = (a|c)&b)|(a&c)             # MAJ
+        add     y1, h           # h = k + w + h + S0                    # --
+        add     y2, d           # d = k + w + h + d + S1 + CH = d + t1  # --
+        add     y2, h           # h = k + w + h + S0 + S1 + CH = t1 + S0# --
+
+        add     y3, h           # h = t1 + S0 + MAJ                     # --
+
+        RotateState
+
+################################### RND N + 3 #########################################
+
+        vpsrlq          $19, Y_0, YTMP3                 # YTMP3 = W[-2] >> 19 {DC--}
+        vpsllq          $(64-19), Y_0, YTMP1            # YTMP1 = W[-2] << 19 {DC--}
+        vpor            YTMP1, YTMP3, YTMP3             # YTMP3 = W[-2] ror 19 {DC--}
+        vpxor           YTMP3, YTMP4, YTMP4             # YTMP4 = W[-2] ror 19 ^ W[-2] >> 6 {DC--}
+        vpsrlq          $61, Y_0, YTMP3                 # YTMP3 = W[-2] >> 61 {DC--}
+        vpsllq          $(64-61), Y_0, YTMP1            # YTMP1 = W[-2] << 61 {DC--}
+        vpor            YTMP1, YTMP3, YTMP3             # YTMP3 = W[-2] ror 61 {DC--}
+        vpxor           YTMP3, YTMP4, YTMP4             # YTMP4 = s1 = (W[-2] ror 19) ^
+                                                        #  (W[-2] ror 61) ^ (W[-2] >> 6) {DC--}
+
+        # Add the sigma0 + w[t-7] + w[t-16] for w[18] and w[19]
+        # to newly calculated sigma1 to get w[18] and w[19]
+        vpaddq          YTMP4, YTMP0, YTMP2             # YTMP2 = {W[3], W[2], --, --}
+
+        # Form w[19, w[18], w17], w[16]
+        vpblendd                $0xF0, YTMP2, Y_0, Y_0          # Y_0 = {W[3], W[2], W[1], W[0]}
+
+        mov     a, y3           # y3 = a                                # MAJA
+        rorx    $41, e, y0      # y0 = e >> 41                          # S1A
+        rorx    $18, e, y1      # y1 = e >> 18                          # S1B
+        add     3*8+frame_XFER(%rsp), h         # h = k + w + h         # --
+        or      c, y3           # y3 = a|c                              # MAJA
+
+
+        mov     f, y2           # y2 = f                                # CH
+        rorx    $34, a, T1      # T1 = a >> 34                          # S0B
+        xor     y1, y0          # y0 = (e>>41) ^ (e>>18)                # S1
+        xor     g, y2           # y2 = f^g                              # CH
+
+
+        rorx    $14, e, y1      # y1 = (e >> 14)                        # S1
+        and     e, y2           # y2 = (f^g)&e                          # CH
+        add     h, d            # d = k + w + h + d                     # --
+        and     b, y3           # y3 = (a|c)&b                          # MAJA
+
+        xor     y1, y0          # y0 = (e>>41) ^ (e>>18) ^ (e>>14)      # S1
+        xor     g, y2           # y2 = CH = ((f^g)&e)^g                 # CH
+
+        rorx    $39, a, y1      # y1 = a >> 39                          # S0A
+        add     y0, y2          # y2 = S1 + CH                          # --
+
+        xor     T1, y1          # y1 = (a>>39) ^ (a>>34)                # S0
+        add     y2, d           # d = k + w + h + d + S1 + CH = d + t1  # --
+
+        rorx    $28, a, T1      # T1 = (a >> 28)                        # S0
+
+        xor     T1, y1          # y1 = (a>>39) ^ (a>>34) ^ (a>>28)      # S0
+        mov     a, T1           # T1 = a                                # MAJB
+        and     c, T1           # T1 = a&c                              # MAJB
+        or      T1, y3          # y3 = MAJ = (a|c)&b)|(a&c)             # MAJ
+
+        add     y1, h           # h = k + w + h + S0                    # --
+        add     y2, h           # h = k + w + h + S0 + S1 + CH = t1 + S0# --
+        add     y3, h           # h = t1 + S0 + MAJ                     # --
+
+        RotateState
+
+        rotate_Ys
+.endm
+
+.macro DO_4ROUNDS
+
+################################### RND N + 0 #########################################
+
+        mov     f, y2           # y2 = f                                # CH
+        rorx    $41, e, y0      # y0 = e >> 41                          # S1A
+        rorx    $18, e, y1      # y1 = e >> 18                          # S1B
+        xor     g, y2           # y2 = f^g                              # CH
+
+        xor     y1, y0          # y0 = (e>>41) ^ (e>>18)                # S1
+        rorx    $14, e, y1      # y1 = (e >> 14)                        # S1
+        and     e, y2           # y2 = (f^g)&e                          # CH
+
+        xor     y1, y0          # y0 = (e>>41) ^ (e>>18) ^ (e>>14)      # S1
+        rorx    $34, a, T1      # T1 = a >> 34                          # S0B
+        xor     g, y2           # y2 = CH = ((f^g)&e)^g                 # CH
+        rorx    $39, a, y1      # y1 = a >> 39                          # S0A
+        mov     a, y3           # y3 = a                                # MAJA
+
+        xor     T1, y1          # y1 = (a>>39) ^ (a>>34)                # S0
+        rorx    $28, a, T1      # T1 = (a >> 28)                        # S0
+        add     frame_XFER(%rsp), h             # h = k + w + h         # --
+        or      c, y3           # y3 = a|c                              # MAJA
+
+        xor     T1, y1          # y1 = (a>>39) ^ (a>>34) ^ (a>>28)      # S0
+        mov     a, T1           # T1 = a                                # MAJB
+        and     b, y3           # y3 = (a|c)&b                          # MAJA
+        and     c, T1           # T1 = a&c                              # MAJB
+        add     y0, y2          # y2 = S1 + CH                          # --
+
+        add     h, d            # d = k + w + h + d                     # --
+        or      T1, y3          # y3 = MAJ = (a|c)&b)|(a&c)             # MAJ
+        add     y1, h           # h = k + w + h + S0                    # --
+
+        add     y2, d           # d = k + w + h + d + S1 + CH = d + t1  # --
+
+        RotateState
+
+################################### RND N + 1 #########################################
+
+        add     y2, old_h       # h = k + w + h + S0 + S1 + CH = t1 + S0# --
+        mov     f, y2           # y2 = f                                # CH
+        rorx    $41, e, y0      # y0 = e >> 41                          # S1A
+        rorx    $18, e, y1      # y1 = e >> 18                          # S1B
+        xor     g, y2           # y2 = f^g                              # CH
+
+        xor     y1, y0          # y0 = (e>>41) ^ (e>>18)                # S1
+        rorx    $14, e, y1      # y1 = (e >> 14)                        # S1
+        and     e, y2           # y2 = (f^g)&e                          # CH
+        add     y3, old_h       # h = t1 + S0 + MAJ                     # --
+
+        xor     y1, y0          # y0 = (e>>41) ^ (e>>18) ^ (e>>14)      # S1
+        rorx    $34, a, T1      # T1 = a >> 34                          # S0B
+        xor     g, y2           # y2 = CH = ((f^g)&e)^g                 # CH
+        rorx    $39, a, y1      # y1 = a >> 39                          # S0A
+        mov     a, y3           # y3 = a                                # MAJA
+
+        xor     T1, y1          # y1 = (a>>39) ^ (a>>34)                # S0
+        rorx    $28, a, T1      # T1 = (a >> 28)                        # S0
+        add     8*1+frame_XFER(%rsp), h         # h = k + w + h         # --
+        or      c, y3           # y3 = a|c                              # MAJA
+
+        xor     T1, y1          # y1 = (a>>39) ^ (a>>34) ^ (a>>28)      # S0
+        mov     a, T1           # T1 = a                                # MAJB
+        and     b, y3           # y3 = (a|c)&b                          # MAJA
+        and     c, T1           # T1 = a&c                              # MAJB
+        add     y0, y2          # y2 = S1 + CH                          # --
+
+        add     h, d            # d = k + w + h + d                     # --
+        or      T1, y3          # y3 = MAJ = (a|c)&b)|(a&c)             # MAJ
+        add     y1, h           # h = k + w + h + S0                    # --
+
+        add     y2, d           # d = k + w + h + d + S1 + CH = d + t1  # --
+
+        RotateState
+
+################################### RND N + 2 #########################################
+
+        add     y2, old_h       # h = k + w + h + S0 + S1 + CH = t1 + S0# --
+        mov     f, y2           # y2 = f                                # CH
+        rorx    $41, e, y0      # y0 = e >> 41                          # S1A
+        rorx    $18, e, y1      # y1 = e >> 18                          # S1B
+        xor     g, y2           # y2 = f^g                              # CH
+
+        xor     y1, y0          # y0 = (e>>41) ^ (e>>18)                # S1
+        rorx    $14, e, y1      # y1 = (e >> 14)                        # S1
+        and     e, y2           # y2 = (f^g)&e                          # CH
+        add     y3, old_h       # h = t1 + S0 + MAJ                     # --
+
+        xor     y1, y0          # y0 = (e>>41) ^ (e>>18) ^ (e>>14)      # S1
+        rorx    $34, a, T1      # T1 = a >> 34                          # S0B
+        xor     g, y2           # y2 = CH = ((f^g)&e)^g                 # CH
+        rorx    $39, a, y1      # y1 = a >> 39                          # S0A
+        mov     a, y3           # y3 = a                                # MAJA
+
+        xor     T1, y1          # y1 = (a>>39) ^ (a>>34)                # S0
+        rorx    $28, a, T1      # T1 = (a >> 28)                        # S0
+        add     8*2+frame_XFER(%rsp), h         # h = k + w + h         # --
+        or      c, y3           # y3 = a|c                              # MAJA
+
+        xor     T1, y1          # y1 = (a>>39) ^ (a>>34) ^ (a>>28)      # S0
+        mov     a, T1           # T1 = a                                # MAJB
+        and     b, y3           # y3 = (a|c)&b                          # MAJA
+        and     c, T1           # T1 = a&c                              # MAJB
+        add     y0, y2          # y2 = S1 + CH                          # --
+
+        add     h, d            # d = k + w + h + d                     # --
+        or      T1, y3          # y3 = MAJ = (a|c)&b)|(a&c)             # MAJ
+        add     y1, h           # h = k + w + h + S0                    # --
+
+        add     y2, d           # d = k + w + h + d + S1 + CH = d + t1  # --
+
+        RotateState
+
+################################### RND N + 3 #########################################
+
+        add     y2, old_h       # h = k + w + h + S0 + S1 + CH = t1 + S0# --
+        mov     f, y2           # y2 = f                                # CH
+        rorx    $41, e, y0      # y0 = e >> 41                          # S1A
+        rorx    $18, e, y1      # y1 = e >> 18                          # S1B
+        xor     g, y2           # y2 = f^g                              # CH
+
+        xor     y1, y0          # y0 = (e>>41) ^ (e>>18)                # S1
+        rorx    $14, e, y1      # y1 = (e >> 14)                        # S1
+        and     e, y2           # y2 = (f^g)&e                          # CH
+        add     y3, old_h       # h = t1 + S0 + MAJ                     # --
+
+        xor     y1, y0          # y0 = (e>>41) ^ (e>>18) ^ (e>>14)      # S1
+        rorx    $34, a, T1      # T1 = a >> 34                          # S0B
+        xor     g, y2           # y2 = CH = ((f^g)&e)^g                 # CH
+        rorx    $39, a, y1      # y1 = a >> 39                          # S0A
+        mov     a, y3           # y3 = a                                # MAJA
+
+        xor     T1, y1          # y1 = (a>>39) ^ (a>>34)                # S0
+        rorx    $28, a, T1      # T1 = (a >> 28)                        # S0
+        add     8*3+frame_XFER(%rsp), h         # h = k + w + h         # --
+        or      c, y3           # y3 = a|c                              # MAJA
+
+        xor     T1, y1          # y1 = (a>>39) ^ (a>>34) ^ (a>>28)      # S0
+        mov     a, T1           # T1 = a                                # MAJB
+        and     b, y3           # y3 = (a|c)&b                          # MAJA
+        and     c, T1           # T1 = a&c                              # MAJB
+        add     y0, y2          # y2 = S1 + CH                          # --
+
+
+        add     h, d            # d = k + w + h + d                     # --
+        or      T1, y3          # y3 = MAJ = (a|c)&b)|(a&c)             # MAJ
+        add     y1, h           # h = k + w + h + S0                    # --
+
+        add     y2, d           # d = k + w + h + d + S1 + CH = d + t1  # --
+
+        add     y2, h           # h = k + w + h + S0 + S1 + CH = t1 + S0# --
+
+        add     y3, h           # h = t1 + S0 + MAJ                     # --
+
+        RotateState
+
+.endm
+
+########################################################################
+# void sha512_transform_rorx(const void* M, void* D, uint64_t L)#
+# Purpose: Updates the SHA512 digest stored at D with the message stored in M.
+# The size of the message pointed to by M must be an integer multiple of SHA512
+#   message blocks.
+# L is the message length in SHA512 blocks
+########################################################################
+ENTRY(sha512_transform_rorx)
+        # Allocate Stack Space
+        mov     %rsp, %rax
+        sub     $frame_size, %rsp
+        and     $~(0x20 - 1), %rsp
+        mov     %rax, frame_RSPSAVE(%rsp)
+
+        # Save GPRs
+        mov     %rbp, frame_GPRSAVE(%rsp)
+        mov     %rbx, 8*1+frame_GPRSAVE(%rsp)
+        mov     %r12, 8*2+frame_GPRSAVE(%rsp)
+        mov     %r13, 8*3+frame_GPRSAVE(%rsp)
+        mov     %r14, 8*4+frame_GPRSAVE(%rsp)
+        mov     %r15, 8*5+frame_GPRSAVE(%rsp)
+
+        shl     $7, NUM_BLKS    # convert to bytes
+        jz      done_hash
+        add     INP, NUM_BLKS   # pointer to end of data
+        mov     NUM_BLKS, frame_INPEND(%rsp)
+
+        ## load initial digest
+        mov     8*0(CTX),a
+        mov     8*1(CTX),b
+        mov     8*2(CTX),c
+        mov     8*3(CTX),d
+        mov     8*4(CTX),e
+        mov     8*5(CTX),f
+        mov     8*6(CTX),g
+        mov     8*7(CTX),h
+
+        vmovdqa PSHUFFLE_BYTE_FLIP_MASK(%rip), BYTE_FLIP_MASK
+
+loop0:
+        lea     K512(%rip), TBL
+
+        ## byte swap first 16 dwords
+        COPY_YMM_AND_BSWAP      Y_0, (INP), BYTE_FLIP_MASK
+        COPY_YMM_AND_BSWAP      Y_1, 1*32(INP), BYTE_FLIP_MASK
+        COPY_YMM_AND_BSWAP      Y_2, 2*32(INP), BYTE_FLIP_MASK
+        COPY_YMM_AND_BSWAP      Y_3, 3*32(INP), BYTE_FLIP_MASK
+
+        mov     INP, frame_INP(%rsp)
+
+        ## schedule 64 input dwords, by doing 12 rounds of 4 each
+        movq    $4, frame_SRND(%rsp)
+
+.align 16
+loop1:
+        vpaddq  (TBL), Y_0, XFER
+        vmovdqa XFER, frame_XFER(%rsp)
+        FOUR_ROUNDS_AND_SCHED
+
+        vpaddq  1*32(TBL), Y_0, XFER
+        vmovdqa XFER, frame_XFER(%rsp)
+        FOUR_ROUNDS_AND_SCHED
+
+        vpaddq  2*32(TBL), Y_0, XFER
+        vmovdqa XFER, frame_XFER(%rsp)
+        FOUR_ROUNDS_AND_SCHED
+
+        vpaddq  3*32(TBL), Y_0, XFER
+        vmovdqa XFER, frame_XFER(%rsp)
+        add     $(4*32), TBL
+        FOUR_ROUNDS_AND_SCHED
+
+        subq    $1, frame_SRND(%rsp)
+        jne     loop1
+
+        movq    $2, frame_SRND(%rsp)
+loop2:
+        vpaddq  (TBL), Y_0, XFER
+        vmovdqa XFER, frame_XFER(%rsp)
+        DO_4ROUNDS
+        vpaddq  1*32(TBL), Y_1, XFER
+        vmovdqa XFER, frame_XFER(%rsp)
+        add     $(2*32), TBL
+        DO_4ROUNDS
+
+        vmovdqa Y_2, Y_0
+        vmovdqa Y_3, Y_1
+
+        subq    $1, frame_SRND(%rsp)
+        jne     loop2
+
+        addm    8*0(CTX),a
+        addm    8*1(CTX),b
+        addm    8*2(CTX),c
+        addm    8*3(CTX),d
+        addm    8*4(CTX),e
+        addm    8*5(CTX),f
+        addm    8*6(CTX),g
+        addm    8*7(CTX),h
+
+        mov     frame_INP(%rsp), INP
+        add     $128, INP
+        cmp     frame_INPEND(%rsp), INP
+        jne     loop0
+
+done_hash:
+
+# Restore GPRs
+        mov     frame_GPRSAVE(%rsp)     ,%rbp
+        mov     8*1+frame_GPRSAVE(%rsp) ,%rbx
+        mov     8*2+frame_GPRSAVE(%rsp) ,%r12
+        mov     8*3+frame_GPRSAVE(%rsp) ,%r13
+        mov     8*4+frame_GPRSAVE(%rsp) ,%r14
+        mov     8*5+frame_GPRSAVE(%rsp) ,%r15
+
+        # Restore Stack Pointer
+        mov     frame_RSPSAVE(%rsp), %rsp
+        ret
+ENDPROC(sha512_transform_rorx)
+
+########################################################################
+### Binary Data
+
+.data
+
+.align 64
+# K[t] used in SHA512 hashing
+K512:
+        .quad   0x428a2f98d728ae22,0x7137449123ef65cd
+        .quad   0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
+        .quad   0x3956c25bf348b538,0x59f111f1b605d019
+        .quad   0x923f82a4af194f9b,0xab1c5ed5da6d8118
+        .quad   0xd807aa98a3030242,0x12835b0145706fbe
+        .quad   0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
+        .quad   0x72be5d74f27b896f,0x80deb1fe3b1696b1
+        .quad   0x9bdc06a725c71235,0xc19bf174cf692694
+        .quad   0xe49b69c19ef14ad2,0xefbe4786384f25e3
+        .quad   0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
+        .quad   0x2de92c6f592b0275,0x4a7484aa6ea6e483
+        .quad   0x5cb0a9dcbd41fbd4,0x76f988da831153b5
+        .quad   0x983e5152ee66dfab,0xa831c66d2db43210
+        .quad   0xb00327c898fb213f,0xbf597fc7beef0ee4
+        .quad   0xc6e00bf33da88fc2,0xd5a79147930aa725
+        .quad   0x06ca6351e003826f,0x142929670a0e6e70
+        .quad   0x27b70a8546d22ffc,0x2e1b21385c26c926
+        .quad   0x4d2c6dfc5ac42aed,0x53380d139d95b3df
+        .quad   0x650a73548baf63de,0x766a0abb3c77b2a8
+        .quad   0x81c2c92e47edaee6,0x92722c851482353b
+        .quad   0xa2bfe8a14cf10364,0xa81a664bbc423001
+        .quad   0xc24b8b70d0f89791,0xc76c51a30654be30
+        .quad   0xd192e819d6ef5218,0xd69906245565a910
+        .quad   0xf40e35855771202a,0x106aa07032bbd1b8
+        .quad   0x19a4c116b8d2d0c8,0x1e376c085141ab53
+        .quad   0x2748774cdf8eeb99,0x34b0bcb5e19b48a8
+        .quad   0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb
+        .quad   0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3
+        .quad   0x748f82ee5defb2fc,0x78a5636f43172f60
+        .quad   0x84c87814a1f0ab72,0x8cc702081a6439ec
+        .quad   0x90befffa23631e28,0xa4506cebde82bde9
+        .quad   0xbef9a3f7b2c67915,0xc67178f2e372532b
+        .quad   0xca273eceea26619c,0xd186b8c721c0c207
+        .quad   0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178
+        .quad   0x06f067aa72176fba,0x0a637dc5a2c898a6
+        .quad   0x113f9804bef90dae,0x1b710b35131c471b
+        .quad   0x28db77f523047d84,0x32caab7b40c72493
+        .quad   0x3c9ebe0a15c9bebc,0x431d67c49c100d4c
+        .quad   0x4cc5d4becb3e42b6,0x597f299cfc657e2a
+        .quad   0x5fcb6fab3ad6faec,0x6c44198c4a475817
+
+.align 32
+
+# Mask for byte-swapping a couple of qwords in an XMM register using (v)pshufb.
+PSHUFFLE_BYTE_FLIP_MASK:
+        .octa 0x08090a0b0c0d0e0f0001020304050607
+        .octa 0x18191a1b1c1d1e1f1011121314151617
+
+MASK_YMM_LO:
+        .octa 0x00000000000000000000000000000000
+        .octa 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
+#endif
diff --git a/arch/x86/crypto/sha512-ssse3-asm.S b/arch/x86/crypto/sha512-ssse3-asm.S
new file mode 100644
index 000000000000..fb56855d51f5
--- /dev/null
+++ b/arch/x86/crypto/sha512-ssse3-asm.S
@@ -0,0 +1,421 @@
+########################################################################
+# Implement fast SHA-512 with SSSE3 instructions. (x86_64)
+#
+# Copyright (C) 2013 Intel Corporation.
+#
+# Authors:
+#     James Guilford <james.guilford@intel.com>
+#     Kirk Yap <kirk.s.yap@intel.com>
+#     David Cote <david.m.cote@intel.com>
+#     Tim Chen <tim.c.chen@linux.intel.com>
+#
+# This software is available to you under a choice of one of two
+# licenses.  You may choose to be licensed under the terms of the GNU
+# General Public License (GPL) Version 2, available from the file
+# COPYING in the main directory of this source tree, or the
+# OpenIB.org BSD license below:
+#
+#     Redistribution and use in source and binary forms, with or
+#     without modification, are permitted provided that the following
+#     conditions are met:
+#
+#      - Redistributions of source code must retain the above
+#        copyright notice, this list of conditions and the following
+#        disclaimer.
+#
+#      - Redistributions in binary form must reproduce the above
+#        copyright notice, this list of conditions and the following
+#        disclaimer in the documentation and/or other materials
+#        provided with the distribution.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+########################################################################
+#
+# This code is described in an Intel White-Paper:
+# "Fast SHA-512 Implementations on Intel Architecture Processors"
+#
+# To find it, surf to http://www.intel.com/p/en_US/embedded
+# and search for that title.
+#
+########################################################################
+
+#include <linux/linkage.h>
+
+.text
+
+# Virtual Registers
+# ARG1
+msg =           %rdi
+# ARG2
+digest =        %rsi
+# ARG3
+msglen =        %rdx
+T1 =            %rcx
+T2 =            %r8
+a_64 =          %r9
+b_64 =          %r10
+c_64 =          %r11
+d_64 =          %r12
+e_64 =          %r13
+f_64 =          %r14
+g_64 =          %r15
+h_64 =          %rbx
+tmp0 =          %rax
+
+# Local variables (stack frame)
+
+W_SIZE = 80*8
+WK_SIZE = 2*8
+RSPSAVE_SIZE = 1*8
+GPRSAVE_SIZE = 5*8
+
+frame_W = 0
+frame_WK = frame_W + W_SIZE
+frame_RSPSAVE = frame_WK + WK_SIZE
+frame_GPRSAVE = frame_RSPSAVE + RSPSAVE_SIZE
+frame_size = frame_GPRSAVE + GPRSAVE_SIZE
+
+# Useful QWORD "arrays" for simpler memory references
+# MSG, DIGEST, K_t, W_t are arrays
+# WK_2(t) points to 1 of 2 qwords at frame.WK depdending on t being odd/even
+
+# Input message (arg1)
+#define MSG(i)    8*i(msg)
+
+# Output Digest (arg2)
+#define DIGEST(i) 8*i(digest)
+
+# SHA Constants (static mem)
+#define K_t(i)    8*i+K512(%rip)
+
+# Message Schedule (stack frame)
+#define W_t(i)    8*i+frame_W(%rsp)
+
+# W[t]+K[t] (stack frame)
+#define WK_2(i)   8*((i%2))+frame_WK(%rsp)
+
+.macro RotateState
+        # Rotate symbols a..h right
+        TMP   = h_64
+        h_64  = g_64
+        g_64  = f_64
+        f_64  = e_64
+        e_64  = d_64
+        d_64  = c_64
+        c_64  = b_64
+        b_64  = a_64
+        a_64  = TMP
+.endm
+
+.macro SHA512_Round rnd
+
+        # Compute Round %%t
+        mov     f_64, T1          # T1 = f
+        mov     e_64, tmp0        # tmp = e
+        xor     g_64, T1          # T1 = f ^ g
+        ror     $23, tmp0 # 41    # tmp = e ror 23
+        and     e_64, T1          # T1 = (f ^ g) & e
+        xor     e_64, tmp0        # tmp = (e ror 23) ^ e
+        xor     g_64, T1          # T1 = ((f ^ g) & e) ^ g = CH(e,f,g)
+        idx = \rnd
+        add     WK_2(idx), T1     # W[t] + K[t] from message scheduler
+        ror     $4, tmp0  # 18    # tmp = ((e ror 23) ^ e) ror 4
+        xor     e_64, tmp0        # tmp = (((e ror 23) ^ e) ror 4) ^ e
+        mov     a_64, T2          # T2 = a
+        add     h_64, T1          # T1 = CH(e,f,g) + W[t] + K[t] + h
+        ror     $14, tmp0 # 14    # tmp = ((((e ror23)^e)ror4)^e)ror14 = S1(e)
+        add     tmp0, T1          # T1 = CH(e,f,g) + W[t] + K[t] + S1(e)
+        mov     a_64, tmp0        # tmp = a
+        xor     c_64, T2          # T2 = a ^ c
+        and     c_64, tmp0        # tmp = a & c
+        and     b_64, T2          # T2 = (a ^ c) & b
+        xor     tmp0, T2          # T2 = ((a ^ c) & b) ^ (a & c) = Maj(a,b,c)
+        mov     a_64, tmp0        # tmp = a
+        ror     $5, tmp0 # 39     # tmp = a ror 5
+        xor     a_64, tmp0        # tmp = (a ror 5) ^ a
+        add     T1, d_64          # e(next_state) = d + T1
+        ror     $6, tmp0 # 34     # tmp = ((a ror 5) ^ a) ror 6
+        xor     a_64, tmp0        # tmp = (((a ror 5) ^ a) ror 6) ^ a
+        lea     (T1, T2), h_64    # a(next_state) = T1 + Maj(a,b,c)
+        ror     $28, tmp0 # 28    # tmp = ((((a ror5)^a)ror6)^a)ror28 = S0(a)
+        add     tmp0, h_64        # a(next_state) = T1 + Maj(a,b,c) S0(a)
+        RotateState
+.endm
+
+.macro SHA512_2Sched_2Round_sse rnd
+
+        # Compute rounds t-2 and t-1
+        # Compute message schedule QWORDS t and t+1
+
+        #   Two rounds are computed based on the values for K[t-2]+W[t-2] and
+        # K[t-1]+W[t-1] which were previously stored at WK_2 by the message
+        # scheduler.
+        #   The two new schedule QWORDS are stored at [W_t(%%t)] and [W_t(%%t+1)].
+        # They are then added to their respective SHA512 constants at
+        # [K_t(%%t)] and [K_t(%%t+1)] and stored at dqword [WK_2(%%t)]
+        #   For brievity, the comments following vectored instructions only refer to
+        # the first of a pair of QWORDS.
+        # Eg. XMM2=W[t-2] really means XMM2={W[t-2]|W[t-1]}
+        #   The computation of the message schedule and the rounds are tightly
+        # stitched to take advantage of instruction-level parallelism.
+        # For clarity, integer instructions (for the rounds calculation) are indented
+        # by one tab. Vectored instructions (for the message scheduler) are indented
+        # by two tabs.
+
+        mov     f_64, T1
+        idx = \rnd -2
+        movdqa  W_t(idx), %xmm2             # XMM2 = W[t-2]
+        xor     g_64, T1
+        and     e_64, T1
+        movdqa  %xmm2, %xmm0                # XMM0 = W[t-2]
+        xor     g_64, T1
+        idx = \rnd
+        add     WK_2(idx), T1
+        idx = \rnd - 15
+        movdqu  W_t(idx), %xmm5             # XMM5 = W[t-15]
+        mov     e_64, tmp0
+        ror     $23, tmp0 # 41
+        movdqa  %xmm5, %xmm3                # XMM3 = W[t-15]
+        xor     e_64, tmp0
+        ror     $4, tmp0 # 18
+        psrlq   $61-19, %xmm0               # XMM0 = W[t-2] >> 42
+        xor     e_64, tmp0
+        ror     $14, tmp0 # 14
+        psrlq   $(8-7), %xmm3               # XMM3 = W[t-15] >> 1
+        add     tmp0, T1
+        add     h_64, T1
+        pxor    %xmm2, %xmm0                # XMM0 = (W[t-2] >> 42) ^ W[t-2]
+        mov     a_64, T2
+        xor     c_64, T2
+        pxor    %xmm5, %xmm3                # XMM3 = (W[t-15] >> 1) ^ W[t-15]
+        and     b_64, T2
+        mov     a_64, tmp0
+        psrlq   $(19-6), %xmm0              # XMM0 = ((W[t-2]>>42)^W[t-2])>>13
+        and     c_64, tmp0
+        xor     tmp0, T2
+        psrlq   $(7-1), %xmm3               # XMM3 = ((W[t-15]>>1)^W[t-15])>>6
+        mov     a_64, tmp0
+        ror     $5, tmp0 # 39
+        pxor    %xmm2, %xmm0                # XMM0 = (((W[t-2]>>42)^W[t-2])>>13)^W[t-2]
+        xor     a_64, tmp0
+        ror     $6, tmp0 # 34
+        pxor    %xmm5, %xmm3                # XMM3 = (((W[t-15]>>1)^W[t-15])>>6)^W[t-15]
+        xor     a_64, tmp0
+        ror     $28, tmp0 # 28
+        psrlq   $6, %xmm0                   # XMM0 = ((((W[t-2]>>42)^W[t-2])>>13)^W[t-2])>>6
+        add     tmp0, T2
+        add     T1, d_64
+        psrlq   $1, %xmm3                   # XMM3 = (((W[t-15]>>1)^W[t-15])>>6)^W[t-15]>>1
+        lea     (T1, T2), h_64
+        RotateState
+        movdqa  %xmm2, %xmm1                # XMM1 = W[t-2]
+        mov     f_64, T1
+        xor     g_64, T1
+        movdqa  %xmm5, %xmm4                # XMM4 = W[t-15]
+        and     e_64, T1
+        xor     g_64, T1
+        psllq   $(64-19)-(64-61) , %xmm1    # XMM1 = W[t-2] << 42
+        idx = \rnd + 1
+        add     WK_2(idx), T1
+        mov     e_64, tmp0
+        psllq   $(64-1)-(64-8), %xmm4       # XMM4 = W[t-15] << 7
+        ror     $23, tmp0 # 41
+        xor     e_64, tmp0
+        pxor    %xmm2, %xmm1                # XMM1 = (W[t-2] << 42)^W[t-2]
+        ror     $4, tmp0 # 18
+        xor     e_64, tmp0
+        pxor    %xmm5, %xmm4                # XMM4 = (W[t-15]<<7)^W[t-15]
+        ror     $14, tmp0 # 14
+        add     tmp0, T1
+        psllq   $(64-61), %xmm1             # XMM1 = ((W[t-2] << 42)^W[t-2])<<3
+        add     h_64, T1
+        mov     a_64, T2
+        psllq   $(64-8), %xmm4              # XMM4 = ((W[t-15]<<7)^W[t-15])<<56
+        xor     c_64, T2
+        and     b_64, T2
+        pxor    %xmm1, %xmm0                # XMM0 = s1(W[t-2])
+        mov     a_64, tmp0
+        and     c_64, tmp0
+        idx = \rnd - 7
+        movdqu  W_t(idx), %xmm1             # XMM1 = W[t-7]
+        xor     tmp0, T2
+        pxor    %xmm4, %xmm3                # XMM3 = s0(W[t-15])
+        mov     a_64, tmp0
+        paddq   %xmm3, %xmm0                # XMM0 = s1(W[t-2]) + s0(W[t-15])
+        ror     $5, tmp0 # 39
+        idx =\rnd-16
+        paddq   W_t(idx), %xmm0             # XMM0 = s1(W[t-2]) + s0(W[t-15]) + W[t-16]
+        xor     a_64, tmp0
+        paddq   %xmm1, %xmm0                # XMM0 = s1(W[t-2]) + W[t-7] + s0(W[t-15]) + W[t-16]
+        ror     $6, tmp0 # 34
+        movdqa  %xmm0, W_t(\rnd)            # Store scheduled qwords
+        xor     a_64, tmp0
+        paddq   K_t(\rnd), %xmm0            # Compute W[t]+K[t]
+        ror     $28, tmp0 # 28
+        idx = \rnd
+        movdqa  %xmm0, WK_2(idx)            # Store W[t]+K[t] for next rounds
+        add     tmp0, T2
+        add     T1, d_64
+        lea     (T1, T2), h_64
+        RotateState
+.endm
+
+########################################################################
+# void sha512_transform_ssse3(const void* M, void* D, u64 L)#
+# Purpose: Updates the SHA512 digest stored at D with the message stored in M.
+# The size of the message pointed to by M must be an integer multiple of SHA512
+#   message blocks.
+# L is the message length in SHA512 blocks.
+########################################################################
+ENTRY(sha512_transform_ssse3)
+
+        cmp $0, msglen
+        je nowork
+
+        # Allocate Stack Space
+        mov     %rsp, %rax
+        sub     $frame_size, %rsp
+        and     $~(0x20 - 1), %rsp
+        mov     %rax, frame_RSPSAVE(%rsp)
+
+        # Save GPRs
+        mov     %rbx, frame_GPRSAVE(%rsp)
+        mov     %r12, frame_GPRSAVE +8*1(%rsp)
+        mov     %r13, frame_GPRSAVE +8*2(%rsp)
+        mov     %r14, frame_GPRSAVE +8*3(%rsp)
+        mov     %r15, frame_GPRSAVE +8*4(%rsp)
+
+updateblock:
+
+# Load state variables
+        mov     DIGEST(0), a_64
+        mov     DIGEST(1), b_64
+        mov     DIGEST(2), c_64
+        mov     DIGEST(3), d_64
+        mov     DIGEST(4), e_64
+        mov     DIGEST(5), f_64
+        mov     DIGEST(6), g_64
+        mov     DIGEST(7), h_64
+
+        t = 0
+        .rept 80/2 + 1
+        # (80 rounds) / (2 rounds/iteration) + (1 iteration)
+        # +1 iteration because the scheduler leads hashing by 1 iteration
+                .if t < 2
+                        # BSWAP 2 QWORDS
+                        movdqa  XMM_QWORD_BSWAP(%rip), %xmm1
+                        movdqu  MSG(t), %xmm0
+                        pshufb  %xmm1, %xmm0    # BSWAP
+                        movdqa  %xmm0, W_t(t)   # Store Scheduled Pair
+                        paddq   K_t(t), %xmm0   # Compute W[t]+K[t]
+                        movdqa  %xmm0, WK_2(t)  # Store into WK for rounds
+                .elseif t < 16
+                        # BSWAP 2 QWORDS# Compute 2 Rounds
+                        movdqu  MSG(t), %xmm0
+                        pshufb  %xmm1, %xmm0    # BSWAP
+                        SHA512_Round t-2        # Round t-2
+                        movdqa  %xmm0, W_t(t)   # Store Scheduled Pair
+                        paddq   K_t(t), %xmm0   # Compute W[t]+K[t]
+                        SHA512_Round t-1        # Round t-1
+                        movdqa  %xmm0, WK_2(t)  # Store W[t]+K[t] into WK
+                .elseif t < 79
+                        # Schedule 2 QWORDS# Compute 2 Rounds
+                        SHA512_2Sched_2Round_sse t
+                .else
+                        # Compute 2 Rounds
+                        SHA512_Round t-2
+                        SHA512_Round t-1
+                .endif
+                t = t+2
+        .endr
+
+        # Update digest
+        add     a_64, DIGEST(0)
+        add     b_64, DIGEST(1)
+        add     c_64, DIGEST(2)
+        add     d_64, DIGEST(3)
+        add     e_64, DIGEST(4)
+        add     f_64, DIGEST(5)
+        add     g_64, DIGEST(6)
+        add     h_64, DIGEST(7)
+
+        # Advance to next message block
+        add     $16*8, msg
+        dec     msglen
+        jnz     updateblock
+
+        # Restore GPRs
+        mov     frame_GPRSAVE(%rsp),      %rbx
+        mov     frame_GPRSAVE +8*1(%rsp), %r12
+        mov     frame_GPRSAVE +8*2(%rsp), %r13
+        mov     frame_GPRSAVE +8*3(%rsp), %r14
+        mov     frame_GPRSAVE +8*4(%rsp), %r15
+
+        # Restore Stack Pointer
+        mov     frame_RSPSAVE(%rsp), %rsp
+
+nowork:
+        ret
+ENDPROC(sha512_transform_ssse3)
+
+########################################################################
+### Binary Data
+
+.data
+
+.align 16
+
+# Mask for byte-swapping a couple of qwords in an XMM register using (v)pshufb.
+XMM_QWORD_BSWAP:
+        .octa 0x08090a0b0c0d0e0f0001020304050607
+
+# K[t] used in SHA512 hashing
+K512:
+        .quad 0x428a2f98d728ae22,0x7137449123ef65cd
+        .quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
+        .quad 0x3956c25bf348b538,0x59f111f1b605d019
+        .quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118
+        .quad 0xd807aa98a3030242,0x12835b0145706fbe
+        .quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
+        .quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1
+        .quad 0x9bdc06a725c71235,0xc19bf174cf692694
+        .quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3
+        .quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
+        .quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483
+        .quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5
+        .quad 0x983e5152ee66dfab,0xa831c66d2db43210
+        .quad 0xb00327c898fb213f,0xbf597fc7beef0ee4
+        .quad 0xc6e00bf33da88fc2,0xd5a79147930aa725
+        .quad 0x06ca6351e003826f,0x142929670a0e6e70
+        .quad 0x27b70a8546d22ffc,0x2e1b21385c26c926
+        .quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df
+        .quad 0x650a73548baf63de,0x766a0abb3c77b2a8
+        .quad 0x81c2c92e47edaee6,0x92722c851482353b
+        .quad 0xa2bfe8a14cf10364,0xa81a664bbc423001
+        .quad 0xc24b8b70d0f89791,0xc76c51a30654be30
+        .quad 0xd192e819d6ef5218,0xd69906245565a910
+        .quad 0xf40e35855771202a,0x106aa07032bbd1b8
+        .quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53
+        .quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8
+        .quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb
+        .quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3
+        .quad 0x748f82ee5defb2fc,0x78a5636f43172f60
+        .quad 0x84c87814a1f0ab72,0x8cc702081a6439ec
+        .quad 0x90befffa23631e28,0xa4506cebde82bde9
+        .quad 0xbef9a3f7b2c67915,0xc67178f2e372532b
+        .quad 0xca273eceea26619c,0xd186b8c721c0c207
+        .quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178
+        .quad 0x06f067aa72176fba,0x0a637dc5a2c898a6
+        .quad 0x113f9804bef90dae,0x1b710b35131c471b
+        .quad 0x28db77f523047d84,0x32caab7b40c72493
+        .quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c
+        .quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a
+        .quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817
diff --git a/arch/x86/crypto/sha512_ssse3_glue.c b/arch/x86/crypto/sha512_ssse3_glue.c
new file mode 100644
index 000000000000..6cbd8df348d2
--- /dev/null
+++ b/arch/x86/crypto/sha512_ssse3_glue.c
@@ -0,0 +1,282 @@
+/*
+ * Cryptographic API.
+ *
+ * Glue code for the SHA512 Secure Hash Algorithm assembler
+ * implementation using supplemental SSE3 / AVX / AVX2 instructions.
+ *
+ * This file is based on sha512_generic.c
+ *
+ * Copyright (C) 2013 Intel Corporation
+ * Author: Tim Chen <tim.c.chen@linux.intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+
+#define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
+
+#include <crypto/internal/hash.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/cryptohash.h>
+#include <linux/types.h>
+#include <crypto/sha.h>
+#include <asm/byteorder.h>
+#include <asm/i387.h>
+#include <asm/xcr.h>
+#include <asm/xsave.h>
+
+#include <linux/string.h>
+
+asmlinkage void sha512_transform_ssse3(const char *data, u64 *digest,
+                                     u64 rounds);
+#ifdef CONFIG_AS_AVX
+asmlinkage void sha512_transform_avx(const char *data, u64 *digest,
+                                     u64 rounds);
+#endif
+#ifdef CONFIG_AS_AVX2
+asmlinkage void sha512_transform_rorx(const char *data, u64 *digest,
+                                     u64 rounds);
+#endif
+
+static asmlinkage void (*sha512_transform_asm)(const char *, u64 *, u64);
+
+
+static int sha512_ssse3_init(struct shash_desc *desc)
+{
+        struct sha512_state *sctx = shash_desc_ctx(desc);
+
+        sctx->state[0] = SHA512_H0;
+        sctx->state[1] = SHA512_H1;
+        sctx->state[2] = SHA512_H2;
+        sctx->state[3] = SHA512_H3;
+        sctx->state[4] = SHA512_H4;
+        sctx->state[5] = SHA512_H5;
+        sctx->state[6] = SHA512_H6;
+        sctx->state[7] = SHA512_H7;
+        sctx->count[0] = sctx->count[1] = 0;
+
+        return 0;
+}
+
+static int __sha512_ssse3_update(struct shash_desc *desc, const u8 *data,
+                               unsigned int len, unsigned int partial)
+{
+        struct sha512_state *sctx = shash_desc_ctx(desc);
+        unsigned int done = 0;
+
+        sctx->count[0] += len;
+        if (sctx->count[0] < len)
+                sctx->count[1]++;
+
+        if (partial) {
+                done = SHA512_BLOCK_SIZE - partial;
+                memcpy(sctx->buf + partial, data, done);
+                sha512_transform_asm(sctx->buf, sctx->state, 1);
+        }
+
+        if (len - done >= SHA512_BLOCK_SIZE) {
+                const unsigned int rounds = (len - done) / SHA512_BLOCK_SIZE;
+
+                sha512_transform_asm(data + done, sctx->state, (u64) rounds);
+
+                done += rounds * SHA512_BLOCK_SIZE;
+        }
+
+        memcpy(sctx->buf, data + done, len - done);
+
+        return 0;
+}
+
+static int sha512_ssse3_update(struct shash_desc *desc, const u8 *data,
+                             unsigned int len)
+{
+        struct sha512_state *sctx = shash_desc_ctx(desc);
+        unsigned int partial = sctx->count[0] % SHA512_BLOCK_SIZE;
+        int res;
+
+        /* Handle the fast case right here */
+        if (partial + len < SHA512_BLOCK_SIZE) {
+                sctx->count[0] += len;
+                if (sctx->count[0] < len)
+                        sctx->count[1]++;
+                memcpy(sctx->buf + partial, data, len);
+
+                return 0;
+        }
+
+        if (!irq_fpu_usable()) {
+                res = crypto_sha512_update(desc, data, len);
+        } else {
+                kernel_fpu_begin();
+                res = __sha512_ssse3_update(desc, data, len, partial);
+                kernel_fpu_end();
+        }
+
+        return res;
+}
+
+
+/* Add padding and return the message digest. */
+static int sha512_ssse3_final(struct shash_desc *desc, u8 *out)
+{
+        struct sha512_state *sctx = shash_desc_ctx(desc);
+        unsigned int i, index, padlen;
+        __be64 *dst = (__be64 *)out;
+        __be64 bits[2];
+        static const u8 padding[SHA512_BLOCK_SIZE] = { 0x80, };
+
+        /* save number of bits */
+        bits[1] = cpu_to_be64(sctx->count[0] << 3);
+        bits[0] = cpu_to_be64(sctx->count[1] << 3) | sctx->count[0] >> 61;
+
+        /* Pad out to 112 mod 128 and append length */
+        index = sctx->count[0] & 0x7f;
+        padlen = (index < 112) ? (112 - index) : ((128+112) - index);
+
+        if (!irq_fpu_usable()) {
+                crypto_sha512_update(desc, padding, padlen);
+                crypto_sha512_update(desc, (const u8 *)&bits, sizeof(bits));
+        } else {
+                kernel_fpu_begin();
+                /* We need to fill a whole block for __sha512_ssse3_update() */
+                if (padlen <= 112) {
+                        sctx->count[0] += padlen;
+                        if (sctx->count[0] < padlen)
+                                sctx->count[1]++;
+                        memcpy(sctx->buf + index, padding, padlen);
+                } else {
+                        __sha512_ssse3_update(desc, padding, padlen, index);
+                }
+                __sha512_ssse3_update(desc, (const u8 *)&bits,
+                                        sizeof(bits), 112);
+                kernel_fpu_end();
+        }
+
+        /* Store state in digest */
+        for (i = 0; i < 8; i++)
+                dst[i] = cpu_to_be64(sctx->state[i]);
+
+        /* Wipe context */
+        memset(sctx, 0, sizeof(*sctx));
+
+        return 0;
+}
+
+static int sha512_ssse3_export(struct shash_desc *desc, void *out)
+{
+        struct sha512_state *sctx = shash_desc_ctx(desc);
+
+        memcpy(out, sctx, sizeof(*sctx));
+
+        return 0;
+}
+
+static int sha512_ssse3_import(struct shash_desc *desc, const void *in)
+{
+        struct sha512_state *sctx = shash_desc_ctx(desc);
+
+        memcpy(sctx, in, sizeof(*sctx));
+
+        return 0;
+}
+
+static struct shash_alg alg = {
+        .digestsize     =       SHA512_DIGEST_SIZE,
+        .init           =       sha512_ssse3_init,
+        .update         =       sha512_ssse3_update,
+        .final          =       sha512_ssse3_final,
+        .export         =       sha512_ssse3_export,
+        .import         =       sha512_ssse3_import,
+        .descsize       =       sizeof(struct sha512_state),
+        .statesize      =       sizeof(struct sha512_state),
+        .base           =       {
+                .cra_name       =       "sha512",
+                .cra_driver_name =      "sha512-ssse3",
+                .cra_priority   =       150,
+                .cra_flags      =       CRYPTO_ALG_TYPE_SHASH,
+                .cra_blocksize  =       SHA512_BLOCK_SIZE,
+                .cra_module     =       THIS_MODULE,
+        }
+};
+
+#ifdef CONFIG_AS_AVX
+static bool __init avx_usable(void)
+{
+        u64 xcr0;
+
+        if (!cpu_has_avx || !cpu_has_osxsave)
+                return false;
+
+        xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
+        if ((xcr0 & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM)) {
+                pr_info("AVX detected but unusable.\n");
+
+                return false;
+        }
+
+        return true;
+}
+#endif
+
+static int __init sha512_ssse3_mod_init(void)
+{
+        /* test for SSE3 first */
+        if (cpu_has_ssse3)
+                sha512_transform_asm = sha512_transform_ssse3;
+
+#ifdef CONFIG_AS_AVX
+        /* allow AVX to override SSSE3, it's a little faster */
+        if (avx_usable()) {
+#ifdef CONFIG_AS_AVX2
+                if (boot_cpu_has(X86_FEATURE_AVX2))
+                        sha512_transform_asm = sha512_transform_rorx;
+                else
+#endif
+                        sha512_transform_asm = sha512_transform_avx;
+        }
+#endif
+
+        if (sha512_transform_asm) {
+#ifdef CONFIG_AS_AVX
+                if (sha512_transform_asm == sha512_transform_avx)
+                        pr_info("Using AVX optimized SHA-512 implementation\n");
+#ifdef CONFIG_AS_AVX2
+                else if (sha512_transform_asm == sha512_transform_rorx)
+                        pr_info("Using AVX2 optimized SHA-512 implementation\n");
+#endif
+                else
+#endif
+                        pr_info("Using SSSE3 optimized SHA-512 implementation\n");
+                return crypto_register_shash(&alg);
+        }
+        pr_info("Neither AVX nor SSSE3 is available/usable.\n");
+
+        return -ENODEV;
+}
+
+static void __exit sha512_ssse3_mod_fini(void)
+{
+        crypto_unregister_shash(&alg);
+}
+
+module_init(sha512_ssse3_mod_init);
+module_exit(sha512_ssse3_mod_fini);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("SHA512 Secure Hash Algorithm, Supplemental SSE3 accelerated");
+
+MODULE_ALIAS("sha512");
diff --git a/arch/x86/crypto/twofish-avx-x86_64-asm_64.S b/arch/x86/crypto/twofish-avx-x86_64-asm_64.S
index 8d3e113b2c95..05058134c443 100644
--- a/arch/x86/crypto/twofish-avx-x86_64-asm_64.S
+++ b/arch/x86/crypto/twofish-avx-x86_64-asm_64.S
@@ -4,7 +4,7 @@
  * Copyright (C) 2012 Johannes Goetzfried
  *     <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
  *
- * Copyright © 2012 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
+ * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -33,6 +33,8 @@
 
 .Lbswap128_mask:
         .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
+.Lxts_gf128mul_and_shl1_mask:
+        .byte 0x87, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0
 
 .text
 
@@ -408,3 +410,47 @@ ENTRY(twofish_ctr_8way)
 
         ret;
 ENDPROC(twofish_ctr_8way)
+
+ENTRY(twofish_xts_enc_8way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
+         */
+
+        movq %rsi, %r11;
+
+        /* regs <= src, dst <= IVs, regs <= regs xor IVs */
+        load_xts_8way(%rcx, %rdx, %rsi, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2,
+                      RX0, RX1, RY0, .Lxts_gf128mul_and_shl1_mask);
+
+        call __twofish_enc_blk8;
+
+        /* dst <= regs xor IVs(in dst) */
+        store_xts_8way(%r11, RC1, RD1, RA1, RB1, RC2, RD2, RA2, RB2);
+
+        ret;
+ENDPROC(twofish_xts_enc_8way)
+
+ENTRY(twofish_xts_dec_8way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
+         */
+
+        movq %rsi, %r11;
+
+        /* regs <= src, dst <= IVs, regs <= regs xor IVs */
+        load_xts_8way(%rcx, %rdx, %rsi, RC1, RD1, RA1, RB1, RC2, RD2, RA2, RB2,
+                      RX0, RX1, RY0, .Lxts_gf128mul_and_shl1_mask);
+
+        call __twofish_dec_blk8;
+
+        /* dst <= regs xor IVs(in dst) */
+        store_xts_8way(%r11, RA1, RB1, RC1, RD1, RA2, RB2, RC2, RD2);
+
+        ret;
+ENDPROC(twofish_xts_dec_8way)
diff --git a/arch/x86/crypto/twofish-avx2-asm_64.S b/arch/x86/crypto/twofish-avx2-asm_64.S
new file mode 100644
index 000000000000..e1a83b9cd389
--- /dev/null
+++ b/arch/x86/crypto/twofish-avx2-asm_64.S
@@ -0,0 +1,600 @@
+/*
+ * x86_64/AVX2 assembler optimized version of Twofish
+ *
+ * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/linkage.h>
+#include "glue_helper-asm-avx2.S"
+
+.file "twofish-avx2-asm_64.S"
+
+.data
+.align 16
+
+.Lvpshufb_mask0:
+.long 0x80808000
+.long 0x80808004
+.long 0x80808008
+.long 0x8080800c
+
+.Lbswap128_mask:
+        .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
+.Lxts_gf128mul_and_shl1_mask_0:
+        .byte 0x87, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0
+.Lxts_gf128mul_and_shl1_mask_1:
+        .byte 0x0e, 1, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0
+
+.text
+
+/* structure of crypto context */
+#define s0      0
+#define s1      1024
+#define s2      2048
+#define s3      3072
+#define w       4096
+#define k       4128
+
+/* register macros */
+#define CTX     %rdi
+
+#define RS0     CTX
+#define RS1     %r8
+#define RS2     %r9
+#define RS3     %r10
+#define RK      %r11
+#define RW      %rax
+#define RROUND  %r12
+#define RROUNDd %r12d
+
+#define RA0     %ymm8
+#define RB0     %ymm9
+#define RC0     %ymm10
+#define RD0     %ymm11
+#define RA1     %ymm12
+#define RB1     %ymm13
+#define RC1     %ymm14
+#define RD1     %ymm15
+
+/* temp regs */
+#define RX0     %ymm0
+#define RY0     %ymm1
+#define RX1     %ymm2
+#define RY1     %ymm3
+#define RT0     %ymm4
+#define RIDX    %ymm5
+
+#define RX0x    %xmm0
+#define RY0x    %xmm1
+#define RX1x    %xmm2
+#define RY1x    %xmm3
+#define RT0x    %xmm4
+
+/* vpgatherdd mask and '-1' */
+#define RNOT    %ymm6
+
+/* byte mask, (-1 >> 24) */
+#define RBYTE   %ymm7
+
+/**********************************************************************
+  16-way AVX2 twofish
+ **********************************************************************/
+#define init_round_constants() \
+        vpcmpeqd RNOT, RNOT, RNOT; \
+        vpsrld $24, RNOT, RBYTE; \
+        leaq k(CTX), RK; \
+        leaq w(CTX), RW; \
+        leaq s1(CTX), RS1; \
+        leaq s2(CTX), RS2; \
+        leaq s3(CTX), RS3; \
+
+#define g16(ab, rs0, rs1, rs2, rs3, xy) \
+        vpand RBYTE, ab ## 0, RIDX; \
+        vpgatherdd RNOT, (rs0, RIDX, 4), xy ## 0; \
+        vpcmpeqd RNOT, RNOT, RNOT; \
+                \
+                vpand RBYTE, ab ## 1, RIDX; \
+                vpgatherdd RNOT, (rs0, RIDX, 4), xy ## 1; \
+                vpcmpeqd RNOT, RNOT, RNOT; \
+        \
+        vpsrld $8, ab ## 0, RIDX; \
+        vpand RBYTE, RIDX, RIDX; \
+        vpgatherdd RNOT, (rs1, RIDX, 4), RT0; \
+        vpcmpeqd RNOT, RNOT, RNOT; \
+        vpxor RT0, xy ## 0, xy ## 0; \
+                \
+                vpsrld $8, ab ## 1, RIDX; \
+                vpand RBYTE, RIDX, RIDX; \
+                vpgatherdd RNOT, (rs1, RIDX, 4), RT0; \
+                vpcmpeqd RNOT, RNOT, RNOT; \
+                vpxor RT0, xy ## 1, xy ## 1; \
+        \
+        vpsrld $16, ab ## 0, RIDX; \
+        vpand RBYTE, RIDX, RIDX; \
+        vpgatherdd RNOT, (rs2, RIDX, 4), RT0; \
+        vpcmpeqd RNOT, RNOT, RNOT; \
+        vpxor RT0, xy ## 0, xy ## 0; \
+                \
+                vpsrld $16, ab ## 1, RIDX; \
+                vpand RBYTE, RIDX, RIDX; \
+                vpgatherdd RNOT, (rs2, RIDX, 4), RT0; \
+                vpcmpeqd RNOT, RNOT, RNOT; \
+                vpxor RT0, xy ## 1, xy ## 1; \
+        \
+        vpsrld $24, ab ## 0, RIDX; \
+        vpgatherdd RNOT, (rs3, RIDX, 4), RT0; \
+        vpcmpeqd RNOT, RNOT, RNOT; \
+        vpxor RT0, xy ## 0, xy ## 0; \
+                \
+                vpsrld $24, ab ## 1, RIDX; \
+                vpgatherdd RNOT, (rs3, RIDX, 4), RT0; \
+                vpcmpeqd RNOT, RNOT, RNOT; \
+                vpxor RT0, xy ## 1, xy ## 1;
+
+#define g1_16(a, x) \
+        g16(a, RS0, RS1, RS2, RS3, x);
+
+#define g2_16(b, y) \
+        g16(b, RS1, RS2, RS3, RS0, y);
+
+#define encrypt_round_end16(a, b, c, d, nk) \
+        vpaddd RY0, RX0, RX0; \
+        vpaddd RX0, RY0, RY0; \
+        vpbroadcastd nk(RK,RROUND,8), RT0; \
+        vpaddd RT0, RX0, RX0; \
+        vpbroadcastd 4+nk(RK,RROUND,8), RT0; \
+        vpaddd RT0, RY0, RY0; \
+        \
+        vpxor RY0, d ## 0, d ## 0; \
+        \
+        vpxor RX0, c ## 0, c ## 0; \
+        vpsrld $1, c ## 0, RT0; \
+        vpslld $31, c ## 0, c ## 0; \
+        vpor RT0, c ## 0, c ## 0; \
+        \
+                vpaddd RY1, RX1, RX1; \
+                vpaddd RX1, RY1, RY1; \
+                vpbroadcastd nk(RK,RROUND,8), RT0; \
+                vpaddd RT0, RX1, RX1; \
+                vpbroadcastd 4+nk(RK,RROUND,8), RT0; \
+                vpaddd RT0, RY1, RY1; \
+                \
+                vpxor RY1, d ## 1, d ## 1; \
+                \
+                vpxor RX1, c ## 1, c ## 1; \
+                vpsrld $1, c ## 1, RT0; \
+                vpslld $31, c ## 1, c ## 1; \
+                vpor RT0, c ## 1, c ## 1; \
+
+#define encrypt_round16(a, b, c, d, nk) \
+        g2_16(b, RY); \
+        \
+        vpslld $1, b ## 0, RT0; \
+        vpsrld $31, b ## 0, b ## 0; \
+        vpor RT0, b ## 0, b ## 0; \
+        \
+                vpslld $1, b ## 1, RT0; \
+                vpsrld $31, b ## 1, b ## 1; \
+                vpor RT0, b ## 1, b ## 1; \
+        \
+        g1_16(a, RX); \
+        \
+        encrypt_round_end16(a, b, c, d, nk);
+
+#define encrypt_round_first16(a, b, c, d, nk) \
+        vpslld $1, d ## 0, RT0; \
+        vpsrld $31, d ## 0, d ## 0; \
+        vpor RT0, d ## 0, d ## 0; \
+        \
+                vpslld $1, d ## 1, RT0; \
+                vpsrld $31, d ## 1, d ## 1; \
+                vpor RT0, d ## 1, d ## 1; \
+        \
+        encrypt_round16(a, b, c, d, nk);
+
+#define encrypt_round_last16(a, b, c, d, nk) \
+        g2_16(b, RY); \
+        \
+        g1_16(a, RX); \
+        \
+        encrypt_round_end16(a, b, c, d, nk);
+
+#define decrypt_round_end16(a, b, c, d, nk) \
+        vpaddd RY0, RX0, RX0; \
+        vpaddd RX0, RY0, RY0; \
+        vpbroadcastd nk(RK,RROUND,8), RT0; \
+        vpaddd RT0, RX0, RX0; \
+        vpbroadcastd 4+nk(RK,RROUND,8), RT0; \
+        vpaddd RT0, RY0, RY0; \
+        \
+        vpxor RX0, c ## 0, c ## 0; \
+        \
+        vpxor RY0, d ## 0, d ## 0; \
+        vpsrld $1, d ## 0, RT0; \
+        vpslld $31, d ## 0, d ## 0; \
+        vpor RT0, d ## 0, d ## 0; \
+        \
+                vpaddd RY1, RX1, RX1; \
+                vpaddd RX1, RY1, RY1; \
+                vpbroadcastd nk(RK,RROUND,8), RT0; \
+                vpaddd RT0, RX1, RX1; \
+                vpbroadcastd 4+nk(RK,RROUND,8), RT0; \
+                vpaddd RT0, RY1, RY1; \
+                \
+                vpxor RX1, c ## 1, c ## 1; \
+                \
+                vpxor RY1, d ## 1, d ## 1; \
+                vpsrld $1, d ## 1, RT0; \
+                vpslld $31, d ## 1, d ## 1; \
+                vpor RT0, d ## 1, d ## 1;
+
+#define decrypt_round16(a, b, c, d, nk) \
+        g1_16(a, RX); \
+        \
+        vpslld $1, a ## 0, RT0; \
+        vpsrld $31, a ## 0, a ## 0; \
+        vpor RT0, a ## 0, a ## 0; \
+        \
+                vpslld $1, a ## 1, RT0; \
+                vpsrld $31, a ## 1, a ## 1; \
+                vpor RT0, a ## 1, a ## 1; \
+        \
+        g2_16(b, RY); \
+        \
+        decrypt_round_end16(a, b, c, d, nk);
+
+#define decrypt_round_first16(a, b, c, d, nk) \
+        vpslld $1, c ## 0, RT0; \
+        vpsrld $31, c ## 0, c ## 0; \
+        vpor RT0, c ## 0, c ## 0; \
+        \
+                vpslld $1, c ## 1, RT0; \
+                vpsrld $31, c ## 1, c ## 1; \
+                vpor RT0, c ## 1, c ## 1; \
+        \
+        decrypt_round16(a, b, c, d, nk)
+
+#define decrypt_round_last16(a, b, c, d, nk) \
+        g1_16(a, RX); \
+        \
+        g2_16(b, RY); \
+        \
+        decrypt_round_end16(a, b, c, d, nk);
+
+#define encrypt_cycle16() \
+        encrypt_round16(RA, RB, RC, RD, 0); \
+        encrypt_round16(RC, RD, RA, RB, 8);
+
+#define encrypt_cycle_first16() \
+        encrypt_round_first16(RA, RB, RC, RD, 0); \
+        encrypt_round16(RC, RD, RA, RB, 8);
+
+#define encrypt_cycle_last16() \
+        encrypt_round16(RA, RB, RC, RD, 0); \
+        encrypt_round_last16(RC, RD, RA, RB, 8);
+
+#define decrypt_cycle16(n) \
+        decrypt_round16(RC, RD, RA, RB, 8); \
+        decrypt_round16(RA, RB, RC, RD, 0);
+
+#define decrypt_cycle_first16(n) \
+        decrypt_round_first16(RC, RD, RA, RB, 8); \
+        decrypt_round16(RA, RB, RC, RD, 0);
+
+#define decrypt_cycle_last16(n) \
+        decrypt_round16(RC, RD, RA, RB, 8); \
+        decrypt_round_last16(RA, RB, RC, RD, 0);
+
+#define transpose_4x4(x0,x1,x2,x3,t1,t2) \
+        vpunpckhdq x1, x0, t2; \
+        vpunpckldq x1, x0, x0; \
+        \
+        vpunpckldq x3, x2, t1; \
+        vpunpckhdq x3, x2, x2; \
+        \
+        vpunpckhqdq t1, x0, x1; \
+        vpunpcklqdq t1, x0, x0; \
+        \
+        vpunpckhqdq x2, t2, x3; \
+        vpunpcklqdq x2, t2, x2;
+
+#define read_blocks8(offs,a,b,c,d) \
+        transpose_4x4(a, b, c, d, RX0, RY0);
+
+#define write_blocks8(offs,a,b,c,d) \
+        transpose_4x4(a, b, c, d, RX0, RY0);
+
+#define inpack_enc8(a,b,c,d) \
+        vpbroadcastd 4*0(RW), RT0; \
+        vpxor RT0, a, a; \
+        \
+        vpbroadcastd 4*1(RW), RT0; \
+        vpxor RT0, b, b; \
+        \
+        vpbroadcastd 4*2(RW), RT0; \
+        vpxor RT0, c, c; \
+        \
+        vpbroadcastd 4*3(RW), RT0; \
+        vpxor RT0, d, d;
+
+#define outunpack_enc8(a,b,c,d) \
+        vpbroadcastd 4*4(RW), RX0; \
+        vpbroadcastd 4*5(RW), RY0; \
+        vpxor RX0, c, RX0; \
+        vpxor RY0, d, RY0; \
+        \
+        vpbroadcastd 4*6(RW), RT0; \
+        vpxor RT0, a, c; \
+        vpbroadcastd 4*7(RW), RT0; \
+        vpxor RT0, b, d; \
+        \
+        vmovdqa RX0, a; \
+        vmovdqa RY0, b;
+
+#define inpack_dec8(a,b,c,d) \
+        vpbroadcastd 4*4(RW), RX0; \
+        vpbroadcastd 4*5(RW), RY0; \
+        vpxor RX0, a, RX0; \
+        vpxor RY0, b, RY0; \
+        \
+        vpbroadcastd 4*6(RW), RT0; \
+        vpxor RT0, c, a; \
+        vpbroadcastd 4*7(RW), RT0; \
+        vpxor RT0, d, b; \
+        \
+        vmovdqa RX0, c; \
+        vmovdqa RY0, d;
+
+#define outunpack_dec8(a,b,c,d) \
+        vpbroadcastd 4*0(RW), RT0; \
+        vpxor RT0, a, a; \
+        \
+        vpbroadcastd 4*1(RW), RT0; \
+        vpxor RT0, b, b; \
+        \
+        vpbroadcastd 4*2(RW), RT0; \
+        vpxor RT0, c, c; \
+        \
+        vpbroadcastd 4*3(RW), RT0; \
+        vpxor RT0, d, d;
+
+#define read_blocks16(a,b,c,d) \
+        read_blocks8(0, a ## 0, b ## 0, c ## 0, d ## 0); \
+        read_blocks8(8, a ## 1, b ## 1, c ## 1, d ## 1);
+
+#define write_blocks16(a,b,c,d) \
+        write_blocks8(0, a ## 0, b ## 0, c ## 0, d ## 0); \
+        write_blocks8(8, a ## 1, b ## 1, c ## 1, d ## 1);
+
+#define xor_blocks16(a,b,c,d) \
+        xor_blocks8(0, a ## 0, b ## 0, c ## 0, d ## 0); \
+        xor_blocks8(8, a ## 1, b ## 1, c ## 1, d ## 1);
+
+#define inpack_enc16(a,b,c,d) \
+        inpack_enc8(a ## 0, b ## 0, c ## 0, d ## 0); \
+        inpack_enc8(a ## 1, b ## 1, c ## 1, d ## 1);
+
+#define outunpack_enc16(a,b,c,d) \
+        outunpack_enc8(a ## 0, b ## 0, c ## 0, d ## 0); \
+        outunpack_enc8(a ## 1, b ## 1, c ## 1, d ## 1);
+
+#define inpack_dec16(a,b,c,d) \
+        inpack_dec8(a ## 0, b ## 0, c ## 0, d ## 0); \
+        inpack_dec8(a ## 1, b ## 1, c ## 1, d ## 1);
+
+#define outunpack_dec16(a,b,c,d) \
+        outunpack_dec8(a ## 0, b ## 0, c ## 0, d ## 0); \
+        outunpack_dec8(a ## 1, b ## 1, c ## 1, d ## 1);
+
+.align 8
+__twofish_enc_blk16:
+        /* input:
+         *      %rdi: ctx, CTX
+         *      RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1: plaintext
+         * output:
+         *      RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1: ciphertext
+         */
+        init_round_constants();
+
+        read_blocks16(RA, RB, RC, RD);
+        inpack_enc16(RA, RB, RC, RD);
+
+        xorl RROUNDd, RROUNDd;
+        encrypt_cycle_first16();
+        movl $2, RROUNDd;
+
+.align 4
+.L__enc_loop:
+        encrypt_cycle16();
+
+        addl $2, RROUNDd;
+        cmpl $14, RROUNDd;
+        jne .L__enc_loop;
+
+        encrypt_cycle_last16();
+
+        outunpack_enc16(RA, RB, RC, RD);
+        write_blocks16(RA, RB, RC, RD);
+
+        ret;
+ENDPROC(__twofish_enc_blk16)
+
+.align 8
+__twofish_dec_blk16:
+        /* input:
+         *      %rdi: ctx, CTX
+         *      RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1: ciphertext
+         * output:
+         *      RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1: plaintext
+         */
+        init_round_constants();
+
+        read_blocks16(RA, RB, RC, RD);
+        inpack_dec16(RA, RB, RC, RD);
+
+        movl $14, RROUNDd;
+        decrypt_cycle_first16();
+        movl $12, RROUNDd;
+
+.align 4
+.L__dec_loop:
+        decrypt_cycle16();
+
+        addl $-2, RROUNDd;
+        jnz .L__dec_loop;
+
+        decrypt_cycle_last16();
+
+        outunpack_dec16(RA, RB, RC, RD);
+        write_blocks16(RA, RB, RC, RD);
+
+        ret;
+ENDPROC(__twofish_dec_blk16)
+
+ENTRY(twofish_ecb_enc_16way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         */
+
+        vzeroupper;
+        pushq %r12;
+
+        load_16way(%rdx, RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1);
+
+        call __twofish_enc_blk16;
+
+        store_16way(%rsi, RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1);
+
+        popq %r12;
+        vzeroupper;
+
+        ret;
+ENDPROC(twofish_ecb_enc_16way)
+
+ENTRY(twofish_ecb_dec_16way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         */
+
+        vzeroupper;
+        pushq %r12;
+
+        load_16way(%rdx, RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1);
+
+        call __twofish_dec_blk16;
+
+        store_16way(%rsi, RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1);
+
+        popq %r12;
+        vzeroupper;
+
+        ret;
+ENDPROC(twofish_ecb_dec_16way)
+
+ENTRY(twofish_cbc_dec_16way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         */
+
+        vzeroupper;
+        pushq %r12;
+
+        load_16way(%rdx, RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1);
+
+        call __twofish_dec_blk16;
+
+        store_cbc_16way(%rdx, %rsi, RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1,
+                        RX0);
+
+        popq %r12;
+        vzeroupper;
+
+        ret;
+ENDPROC(twofish_cbc_dec_16way)
+
+ENTRY(twofish_ctr_16way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst (16 blocks)
+         *      %rdx: src (16 blocks)
+         *      %rcx: iv (little endian, 128bit)
+         */
+
+        vzeroupper;
+        pushq %r12;
+
+        load_ctr_16way(%rcx, .Lbswap128_mask, RA0, RB0, RC0, RD0, RA1, RB1, RC1,
+                       RD1, RX0, RX0x, RX1, RX1x, RY0, RY0x, RY1, RY1x, RNOT,
+                       RBYTE);
+
+        call __twofish_enc_blk16;
+
+        store_ctr_16way(%rdx, %rsi, RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1);
+
+        popq %r12;
+        vzeroupper;
+
+        ret;
+ENDPROC(twofish_ctr_16way)
+
+.align 8
+twofish_xts_crypt_16way:
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst (16 blocks)
+         *      %rdx: src (16 blocks)
+         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
+         *      %r8: pointer to __twofish_enc_blk16 or __twofish_dec_blk16
+         */
+
+        vzeroupper;
+        pushq %r12;
+
+        load_xts_16way(%rcx, %rdx, %rsi, RA0, RB0, RC0, RD0, RA1, RB1, RC1,
+                       RD1, RX0, RX0x, RX1, RX1x, RY0, RY0x, RY1, RY1x, RNOT,
+                       .Lxts_gf128mul_and_shl1_mask_0,
+                       .Lxts_gf128mul_and_shl1_mask_1);
+
+        call *%r8;
+
+        store_xts_16way(%rsi, RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1);
+
+        popq %r12;
+        vzeroupper;
+
+        ret;
+ENDPROC(twofish_xts_crypt_16way)
+
+ENTRY(twofish_xts_enc_16way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst (16 blocks)
+         *      %rdx: src (16 blocks)
+         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
+         */
+        leaq __twofish_enc_blk16, %r8;
+        jmp twofish_xts_crypt_16way;
+ENDPROC(twofish_xts_enc_16way)
+
+ENTRY(twofish_xts_dec_16way)
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst (16 blocks)
+         *      %rdx: src (16 blocks)
+         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
+         */
+        leaq __twofish_dec_blk16, %r8;
+        jmp twofish_xts_crypt_16way;
+ENDPROC(twofish_xts_dec_16way)
diff --git a/arch/x86/crypto/twofish_avx2_glue.c b/arch/x86/crypto/twofish_avx2_glue.c
new file mode 100644
index 000000000000..ce33b5be64ee
--- /dev/null
+++ b/arch/x86/crypto/twofish_avx2_glue.c
@@ -0,0 +1,584 @@
+/*
+ * Glue Code for x86_64/AVX2 assembler optimized version of Twofish
+ *
+ * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/crypto.h>
+#include <linux/err.h>
+#include <crypto/algapi.h>
+#include <crypto/ctr.h>
+#include <crypto/twofish.h>
+#include <crypto/lrw.h>
+#include <crypto/xts.h>
+#include <asm/xcr.h>
+#include <asm/xsave.h>
+#include <asm/crypto/twofish.h>
+#include <asm/crypto/ablk_helper.h>
+#include <asm/crypto/glue_helper.h>
+#include <crypto/scatterwalk.h>
+
+#define TF_AVX2_PARALLEL_BLOCKS 16
+
+/* 16-way AVX2 parallel cipher functions */
+asmlinkage void twofish_ecb_enc_16way(struct twofish_ctx *ctx, u8 *dst,
+                                      const u8 *src);
+asmlinkage void twofish_ecb_dec_16way(struct twofish_ctx *ctx, u8 *dst,
+                                      const u8 *src);
+asmlinkage void twofish_cbc_dec_16way(void *ctx, u128 *dst, const u128 *src);
+
+asmlinkage void twofish_ctr_16way(void *ctx, u128 *dst, const u128 *src,
+                                  le128 *iv);
+
+asmlinkage void twofish_xts_enc_16way(struct twofish_ctx *ctx, u8 *dst,
+                                      const u8 *src, le128 *iv);
+asmlinkage void twofish_xts_dec_16way(struct twofish_ctx *ctx, u8 *dst,
+                                      const u8 *src, le128 *iv);
+
+static inline void twofish_enc_blk_3way(struct twofish_ctx *ctx, u8 *dst,
+                                        const u8 *src)
+{
+        __twofish_enc_blk_3way(ctx, dst, src, false);
+}
+
+static const struct common_glue_ctx twofish_enc = {
+        .num_funcs = 4,
+        .fpu_blocks_limit = 8,
+
+        .funcs = { {
+                .num_blocks = 16,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_ecb_enc_16way) }
+        }, {
+                .num_blocks = 8,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_ecb_enc_8way) }
+        }, {
+                .num_blocks = 3,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_enc_blk_3way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_enc_blk) }
+        } }
+};
+
+static const struct common_glue_ctx twofish_ctr = {
+        .num_funcs = 4,
+        .fpu_blocks_limit = 8,
+
+        .funcs = { {
+                .num_blocks = 16,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(twofish_ctr_16way) }
+        },  {
+                .num_blocks = 8,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(twofish_ctr_8way) }
+        }, {
+                .num_blocks = 3,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(twofish_enc_blk_ctr_3way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(twofish_enc_blk_ctr) }
+        } }
+};
+
+static const struct common_glue_ctx twofish_enc_xts = {
+        .num_funcs = 3,
+        .fpu_blocks_limit = 8,
+
+        .funcs = { {
+                .num_blocks = 16,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(twofish_xts_enc_16way) }
+        }, {
+                .num_blocks = 8,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(twofish_xts_enc_8way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(twofish_xts_enc) }
+        } }
+};
+
+static const struct common_glue_ctx twofish_dec = {
+        .num_funcs = 4,
+        .fpu_blocks_limit = 8,
+
+        .funcs = { {
+                .num_blocks = 16,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_ecb_dec_16way) }
+        }, {
+                .num_blocks = 8,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_ecb_dec_8way) }
+        }, {
+                .num_blocks = 3,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_dec_blk_3way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_dec_blk) }
+        } }
+};
+
+static const struct common_glue_ctx twofish_dec_cbc = {
+        .num_funcs = 4,
+        .fpu_blocks_limit = 8,
+
+        .funcs = { {
+                .num_blocks = 16,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(twofish_cbc_dec_16way) }
+        }, {
+                .num_blocks = 8,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(twofish_cbc_dec_8way) }
+        }, {
+                .num_blocks = 3,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(twofish_dec_blk_cbc_3way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(twofish_dec_blk) }
+        } }
+};
+
+static const struct common_glue_ctx twofish_dec_xts = {
+        .num_funcs = 3,
+        .fpu_blocks_limit = 8,
+
+        .funcs = { {
+                .num_blocks = 16,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(twofish_xts_dec_16way) }
+        }, {
+                .num_blocks = 8,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(twofish_xts_dec_8way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(twofish_xts_dec) }
+        } }
+};
+
+static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_ecb_crypt_128bit(&twofish_enc, desc, dst, src, nbytes);
+}
+
+static int ecb_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_ecb_crypt_128bit(&twofish_dec, desc, dst, src, nbytes);
+}
+
+static int cbc_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_cbc_encrypt_128bit(GLUE_FUNC_CAST(twofish_enc_blk), desc,
+                                       dst, src, nbytes);
+}
+
+static int cbc_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_cbc_decrypt_128bit(&twofish_dec_cbc, desc, dst, src,
+                                       nbytes);
+}
+
+static int ctr_crypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                     struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_ctr_crypt_128bit(&twofish_ctr, desc, dst, src, nbytes);
+}
+
+static inline bool twofish_fpu_begin(bool fpu_enabled, unsigned int nbytes)
+{
+        /* since reusing AVX functions, starts using FPU at 8 parallel blocks */
+        return glue_fpu_begin(TF_BLOCK_SIZE, 8, NULL, fpu_enabled, nbytes);
+}
+
+static inline void twofish_fpu_end(bool fpu_enabled)
+{
+        glue_fpu_end(fpu_enabled);
+}
+
+struct crypt_priv {
+        struct twofish_ctx *ctx;
+        bool fpu_enabled;
+};
+
+static void encrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
+{
+        const unsigned int bsize = TF_BLOCK_SIZE;
+        struct crypt_priv *ctx = priv;
+        int i;
+
+        ctx->fpu_enabled = twofish_fpu_begin(ctx->fpu_enabled, nbytes);
+
+        while (nbytes >= TF_AVX2_PARALLEL_BLOCKS * bsize) {
+                twofish_ecb_enc_16way(ctx->ctx, srcdst, srcdst);
+                srcdst += bsize * TF_AVX2_PARALLEL_BLOCKS;
+                nbytes -= bsize * TF_AVX2_PARALLEL_BLOCKS;
+        }
+
+        while (nbytes >= 8 * bsize) {
+                twofish_ecb_enc_8way(ctx->ctx, srcdst, srcdst);
+                srcdst += bsize * 8;
+                nbytes -= bsize * 8;
+        }
+
+        while (nbytes >= 3 * bsize) {
+                twofish_enc_blk_3way(ctx->ctx, srcdst, srcdst);
+                srcdst += bsize * 3;
+                nbytes -= bsize * 3;
+        }
+
+        for (i = 0; i < nbytes / bsize; i++, srcdst += bsize)
+                twofish_enc_blk(ctx->ctx, srcdst, srcdst);
+}
+
+static void decrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
+{
+        const unsigned int bsize = TF_BLOCK_SIZE;
+        struct crypt_priv *ctx = priv;
+        int i;
+
+        ctx->fpu_enabled = twofish_fpu_begin(ctx->fpu_enabled, nbytes);
+
+        while (nbytes >= TF_AVX2_PARALLEL_BLOCKS * bsize) {
+                twofish_ecb_dec_16way(ctx->ctx, srcdst, srcdst);
+                srcdst += bsize * TF_AVX2_PARALLEL_BLOCKS;
+                nbytes -= bsize * TF_AVX2_PARALLEL_BLOCKS;
+        }
+
+        while (nbytes >= 8 * bsize) {
+                twofish_ecb_dec_8way(ctx->ctx, srcdst, srcdst);
+                srcdst += bsize * 8;
+                nbytes -= bsize * 8;
+        }
+
+        while (nbytes >= 3 * bsize) {
+                twofish_dec_blk_3way(ctx->ctx, srcdst, srcdst);
+                srcdst += bsize * 3;
+                nbytes -= bsize * 3;
+        }
+
+        for (i = 0; i < nbytes / bsize; i++, srcdst += bsize)
+                twofish_dec_blk(ctx->ctx, srcdst, srcdst);
+}
+
+static int lrw_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct twofish_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+        be128 buf[TF_AVX2_PARALLEL_BLOCKS];
+        struct crypt_priv crypt_ctx = {
+                .ctx = &ctx->twofish_ctx,
+                .fpu_enabled = false,
+        };
+        struct lrw_crypt_req req = {
+                .tbuf = buf,
+                .tbuflen = sizeof(buf),
+
+                .table_ctx = &ctx->lrw_table,
+                .crypt_ctx = &crypt_ctx,
+                .crypt_fn = encrypt_callback,
+        };
+        int ret;
+
+        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
+        ret = lrw_crypt(desc, dst, src, nbytes, &req);
+        twofish_fpu_end(crypt_ctx.fpu_enabled);
+
+        return ret;
+}
+
+static int lrw_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct twofish_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+        be128 buf[TF_AVX2_PARALLEL_BLOCKS];
+        struct crypt_priv crypt_ctx = {
+                .ctx = &ctx->twofish_ctx,
+                .fpu_enabled = false,
+        };
+        struct lrw_crypt_req req = {
+                .tbuf = buf,
+                .tbuflen = sizeof(buf),
+
+                .table_ctx = &ctx->lrw_table,
+                .crypt_ctx = &crypt_ctx,
+                .crypt_fn = decrypt_callback,
+        };
+        int ret;
+
+        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
+        ret = lrw_crypt(desc, dst, src, nbytes, &req);
+        twofish_fpu_end(crypt_ctx.fpu_enabled);
+
+        return ret;
+}
+
+static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct twofish_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+
+        return glue_xts_crypt_128bit(&twofish_enc_xts, desc, dst, src, nbytes,
+                                     XTS_TWEAK_CAST(twofish_enc_blk),
+                                     &ctx->tweak_ctx, &ctx->crypt_ctx);
+}
+
+static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct twofish_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+
+        return glue_xts_crypt_128bit(&twofish_dec_xts, desc, dst, src, nbytes,
+                                     XTS_TWEAK_CAST(twofish_enc_blk),
+                                     &ctx->tweak_ctx, &ctx->crypt_ctx);
+}
+
+static struct crypto_alg tf_algs[10] = { {
+        .cra_name               = "__ecb-twofish-avx2",
+        .cra_driver_name        = "__driver-ecb-twofish-avx2",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = TF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct twofish_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE,
+                        .max_keysize    = TF_MAX_KEY_SIZE,
+                        .setkey         = twofish_setkey,
+                        .encrypt        = ecb_encrypt,
+                        .decrypt        = ecb_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "__cbc-twofish-avx2",
+        .cra_driver_name        = "__driver-cbc-twofish-avx2",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = TF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct twofish_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE,
+                        .max_keysize    = TF_MAX_KEY_SIZE,
+                        .setkey         = twofish_setkey,
+                        .encrypt        = cbc_encrypt,
+                        .decrypt        = cbc_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "__ctr-twofish-avx2",
+        .cra_driver_name        = "__driver-ctr-twofish-avx2",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = 1,
+        .cra_ctxsize            = sizeof(struct twofish_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE,
+                        .max_keysize    = TF_MAX_KEY_SIZE,
+                        .ivsize         = TF_BLOCK_SIZE,
+                        .setkey         = twofish_setkey,
+                        .encrypt        = ctr_crypt,
+                        .decrypt        = ctr_crypt,
+                },
+        },
+}, {
+        .cra_name               = "__lrw-twofish-avx2",
+        .cra_driver_name        = "__driver-lrw-twofish-avx2",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = TF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct twofish_lrw_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_exit               = lrw_twofish_exit_tfm,
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE +
+                                          TF_BLOCK_SIZE,
+                        .max_keysize    = TF_MAX_KEY_SIZE +
+                                          TF_BLOCK_SIZE,
+                        .ivsize         = TF_BLOCK_SIZE,
+                        .setkey         = lrw_twofish_setkey,
+                        .encrypt        = lrw_encrypt,
+                        .decrypt        = lrw_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "__xts-twofish-avx2",
+        .cra_driver_name        = "__driver-xts-twofish-avx2",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = TF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct twofish_xts_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE * 2,
+                        .max_keysize    = TF_MAX_KEY_SIZE * 2,
+                        .ivsize         = TF_BLOCK_SIZE,
+                        .setkey         = xts_twofish_setkey,
+                        .encrypt        = xts_encrypt,
+                        .decrypt        = xts_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "ecb(twofish)",
+        .cra_driver_name        = "ecb-twofish-avx2",
+        .cra_priority           = 500,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = TF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE,
+                        .max_keysize    = TF_MAX_KEY_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "cbc(twofish)",
+        .cra_driver_name        = "cbc-twofish-avx2",
+        .cra_priority           = 500,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = TF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE,
+                        .max_keysize    = TF_MAX_KEY_SIZE,
+                        .ivsize         = TF_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = __ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "ctr(twofish)",
+        .cra_driver_name        = "ctr-twofish-avx2",
+        .cra_priority           = 500,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = 1,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE,
+                        .max_keysize    = TF_MAX_KEY_SIZE,
+                        .ivsize         = TF_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_encrypt,
+                        .geniv          = "chainiv",
+                },
+        },
+}, {
+        .cra_name               = "lrw(twofish)",
+        .cra_driver_name        = "lrw-twofish-avx2",
+        .cra_priority           = 500,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = TF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE +
+                                          TF_BLOCK_SIZE,
+                        .max_keysize    = TF_MAX_KEY_SIZE +
+                                          TF_BLOCK_SIZE,
+                        .ivsize         = TF_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "xts(twofish)",
+        .cra_driver_name        = "xts-twofish-avx2",
+        .cra_priority           = 500,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = TF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE * 2,
+                        .max_keysize    = TF_MAX_KEY_SIZE * 2,
+                        .ivsize         = TF_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+} };
+
+static int __init init(void)
+{
+        u64 xcr0;
+
+        if (!cpu_has_avx2 || !cpu_has_osxsave) {
+                pr_info("AVX2 instructions are not detected.\n");
+                return -ENODEV;
+        }
+
+        xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
+        if ((xcr0 & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM)) {
+                pr_info("AVX2 detected but unusable.\n");
+                return -ENODEV;
+        }
+
+        return crypto_register_algs(tf_algs, ARRAY_SIZE(tf_algs));
+}
+
+static void __exit fini(void)
+{
+        crypto_unregister_algs(tf_algs, ARRAY_SIZE(tf_algs));
+}
+
+module_init(init);
+module_exit(fini);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Twofish Cipher Algorithm, AVX2 optimized");
+MODULE_ALIAS("twofish");
+MODULE_ALIAS("twofish-asm");
diff --git a/arch/x86/crypto/twofish_avx_glue.c b/arch/x86/crypto/twofish_avx_glue.c
index 94ac91d26e47..2047a562f6b3 100644
--- a/arch/x86/crypto/twofish_avx_glue.c
+++ b/arch/x86/crypto/twofish_avx_glue.c
@@ -4,6 +4,8 @@
  * Copyright (C) 2012 Johannes Goetzfried
  *     <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
  *
+ * Copyright © 2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -48,13 +50,26 @@
 /* 8-way parallel cipher functions */
 asmlinkage void twofish_ecb_enc_8way(struct twofish_ctx *ctx, u8 *dst,
                                      const u8 *src);
+EXPORT_SYMBOL_GPL(twofish_ecb_enc_8way);
+
 asmlinkage void twofish_ecb_dec_8way(struct twofish_ctx *ctx, u8 *dst,
                                      const u8 *src);
+EXPORT_SYMBOL_GPL(twofish_ecb_dec_8way);
 
 asmlinkage void twofish_cbc_dec_8way(struct twofish_ctx *ctx, u8 *dst,
                                      const u8 *src);
+EXPORT_SYMBOL_GPL(twofish_cbc_dec_8way);
+
 asmlinkage void twofish_ctr_8way(struct twofish_ctx *ctx, u8 *dst,
                                  const u8 *src, le128 *iv);
+EXPORT_SYMBOL_GPL(twofish_ctr_8way);
+
+asmlinkage void twofish_xts_enc_8way(struct twofish_ctx *ctx, u8 *dst,
+                                     const u8 *src, le128 *iv);
+EXPORT_SYMBOL_GPL(twofish_xts_enc_8way);
+asmlinkage void twofish_xts_dec_8way(struct twofish_ctx *ctx, u8 *dst,
+                                     const u8 *src, le128 *iv);
+EXPORT_SYMBOL_GPL(twofish_xts_dec_8way);
 
 static inline void twofish_enc_blk_3way(struct twofish_ctx *ctx, u8 *dst,
                                         const u8 *src)
@@ -62,6 +77,20 @@ static inline void twofish_enc_blk_3way(struct twofish_ctx *ctx, u8 *dst,
         __twofish_enc_blk_3way(ctx, dst, src, false);
 }
 
+void twofish_xts_enc(void *ctx, u128 *dst, const u128 *src, le128 *iv)
+{
+        glue_xts_crypt_128bit_one(ctx, dst, src, iv,
+                                  GLUE_FUNC_CAST(twofish_enc_blk));
+}
+EXPORT_SYMBOL_GPL(twofish_xts_enc);
+
+void twofish_xts_dec(void *ctx, u128 *dst, const u128 *src, le128 *iv)
+{
+        glue_xts_crypt_128bit_one(ctx, dst, src, iv,
+                                  GLUE_FUNC_CAST(twofish_dec_blk));
+}
+EXPORT_SYMBOL_GPL(twofish_xts_dec);
+
 
 static const struct common_glue_ctx twofish_enc = {
         .num_funcs = 3,
@@ -95,6 +124,19 @@ static const struct common_glue_ctx twofish_ctr = {
         } }
 };
 
+static const struct common_glue_ctx twofish_enc_xts = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = TWOFISH_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = TWOFISH_PARALLEL_BLOCKS,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(twofish_xts_enc_8way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(twofish_xts_enc) }
+        } }
+};
+
 static const struct common_glue_ctx twofish_dec = {
         .num_funcs = 3,
         .fpu_blocks_limit = TWOFISH_PARALLEL_BLOCKS,
@@ -127,6 +169,19 @@ static const struct common_glue_ctx twofish_dec_cbc = {
         } }
 };
 
+static const struct common_glue_ctx twofish_dec_xts = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = TWOFISH_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = TWOFISH_PARALLEL_BLOCKS,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(twofish_xts_dec_8way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(twofish_xts_dec) }
+        } }
+};
+
 static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
                        struct scatterlist *src, unsigned int nbytes)
 {
@@ -275,54 +330,20 @@ static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
                        struct scatterlist *src, unsigned int nbytes)
 {
         struct twofish_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        be128 buf[TWOFISH_PARALLEL_BLOCKS];
-        struct crypt_priv crypt_ctx = {
-                .ctx = &ctx->crypt_ctx,
-                .fpu_enabled = false,
-        };
-        struct xts_crypt_req req = {
-                .tbuf = buf,
-                .tbuflen = sizeof(buf),
 
-                .tweak_ctx = &ctx->tweak_ctx,
-                .tweak_fn = XTS_TWEAK_CAST(twofish_enc_blk),
-                .crypt_ctx = &crypt_ctx,
-                .crypt_fn = encrypt_callback,
-        };
-        int ret;
-
-        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
-        ret = xts_crypt(desc, dst, src, nbytes, &req);
-        twofish_fpu_end(crypt_ctx.fpu_enabled);
-
-        return ret;
+        return glue_xts_crypt_128bit(&twofish_enc_xts, desc, dst, src, nbytes,
+                                     XTS_TWEAK_CAST(twofish_enc_blk),
+                                     &ctx->tweak_ctx, &ctx->crypt_ctx);
 }
 
 static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
                        struct scatterlist *src, unsigned int nbytes)
 {
         struct twofish_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        be128 buf[TWOFISH_PARALLEL_BLOCKS];
-        struct crypt_priv crypt_ctx = {
-                .ctx = &ctx->crypt_ctx,
-                .fpu_enabled = false,
-        };
-        struct xts_crypt_req req = {
-                .tbuf = buf,
-                .tbuflen = sizeof(buf),
-
-                .tweak_ctx = &ctx->tweak_ctx,
-                .tweak_fn = XTS_TWEAK_CAST(twofish_enc_blk),
-                .crypt_ctx = &crypt_ctx,
-                .crypt_fn = decrypt_callback,
-        };
-        int ret;
 
-        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
-        ret = xts_crypt(desc, dst, src, nbytes, &req);
-        twofish_fpu_end(crypt_ctx.fpu_enabled);
-
-        return ret;
+        return glue_xts_crypt_128bit(&twofish_dec_xts, desc, dst, src, nbytes,
+                                     XTS_TWEAK_CAST(twofish_enc_blk),
+                                     &ctx->tweak_ctx, &ctx->crypt_ctx);
 }
 
 static struct crypto_alg twofish_algs[10] = { {
diff --git a/arch/x86/ia32/Makefile b/arch/x86/ia32/Makefile
index 455646e0e532..e785b422b766 100644
--- a/arch/x86/ia32/Makefile
+++ b/arch/x86/ia32/Makefile
@@ -5,9 +5,6 @@
 obj-$(CONFIG_IA32_EMULATION) := ia32entry.o sys_ia32.o ia32_signal.o
 obj-$(CONFIG_IA32_EMULATION) += nosyscall.o syscall_ia32.o
 
-sysv-$(CONFIG_SYSVIPC) := ipc32.o
-obj-$(CONFIG_IA32_EMULATION) += $(sysv-y)
-
 obj-$(CONFIG_IA32_AOUT) += ia32_aout.o
 
 audit-class-$(CONFIG_AUDIT) := audit.o
diff --git a/arch/x86/ia32/ia32_aout.c b/arch/x86/ia32/ia32_aout.c
index 03abf9b70011..805078e08013 100644
--- a/arch/x86/ia32/ia32_aout.c
+++ b/arch/x86/ia32/ia32_aout.c
@@ -162,7 +162,6 @@ static int aout_core_dump(long signr, struct pt_regs *regs, struct file *file,
         fs = get_fs();
         set_fs(KERNEL_DS);
         has_dumped = 1;
-        current->flags |= PF_DUMPCORE;
         strncpy(dump.u_comm, current->comm, sizeof(current->comm));
         dump.u_ar0 = offsetof(struct user32, regs);
         dump.signal = signr;
@@ -323,11 +322,8 @@ static int load_aout_binary(struct linux_binprm *bprm)
 
         if (N_MAGIC(ex) == OMAGIC) {
                 unsigned long text_addr, map_size;
-                loff_t pos;
 
                 text_addr = N_TXTADDR(ex);
-
-                pos = 32;
                 map_size = ex.a_text+ex.a_data;
 
                 error = vm_brk(text_addr & PAGE_MASK, map_size);
@@ -337,15 +333,12 @@ static int load_aout_binary(struct linux_binprm *bprm)
                         return error;
                 }
 
-                error = bprm->file->f_op->read(bprm->file,
-                         (char __user *)text_addr,
-                          ex.a_text+ex.a_data, &pos);
+                error = read_code(bprm->file, text_addr, 32,
+                                  ex.a_text + ex.a_data);
                 if ((signed long)error < 0) {
                         send_sig(SIGKILL, current, 0);
                         return error;
                 }
-
-                flush_icache_range(text_addr, text_addr+ex.a_text+ex.a_data);
         } else {
 #ifdef WARN_OLD
                 static unsigned long error_time, error_time2;
@@ -367,15 +360,9 @@ static int load_aout_binary(struct linux_binprm *bprm)
 #endif
 
                 if (!bprm->file->f_op->mmap || (fd_offset & ~PAGE_MASK) != 0) {
-                        loff_t pos = fd_offset;
-
                         vm_brk(N_TXTADDR(ex), ex.a_text+ex.a_data);
-                        bprm->file->f_op->read(bprm->file,
-                                        (char __user *)N_TXTADDR(ex),
-                                        ex.a_text+ex.a_data, &pos);
-                        flush_icache_range((unsigned long) N_TXTADDR(ex),
-                                           (unsigned long) N_TXTADDR(ex) +
-                                           ex.a_text+ex.a_data);
+                        read_code(bprm->file, N_TXTADDR(ex), fd_offset,
+                                        ex.a_text+ex.a_data);
                         goto beyond_if;
                 }
 
@@ -452,8 +439,6 @@ static int load_aout_library(struct file *file)
         start_addr =  ex.a_entry & 0xfffff000;
 
         if ((N_TXTOFF(ex) & ~PAGE_MASK) != 0) {
-                loff_t pos = N_TXTOFF(ex);
-
 #ifdef WARN_OLD
                 static unsigned long error_time;
                 if (time_after(jiffies, error_time + 5*HZ)) {
@@ -466,12 +451,8 @@ static int load_aout_library(struct file *file)
 #endif
                 vm_brk(start_addr, ex.a_text + ex.a_data + ex.a_bss);
 
-                file->f_op->read(file, (char __user *)start_addr,
-                        ex.a_text + ex.a_data, &pos);
-                flush_icache_range((unsigned long) start_addr,
-                                   (unsigned long) start_addr + ex.a_text +
-                                   ex.a_data);
-
+                read_code(file, start_addr, N_TXTOFF(ex),
+                          ex.a_text + ex.a_data);
                 retval = 0;
                 goto out;
         }
diff --git a/arch/x86/ia32/ipc32.c b/arch/x86/ia32/ipc32.c
deleted file mode 100644
index 29cdcd02ead3..000000000000
--- a/arch/x86/ia32/ipc32.c
+++ /dev/null
@@ -1,54 +0,0 @@
-#include <linux/kernel.h>
-#include <linux/spinlock.h>
-#include <linux/list.h>
-#include <linux/syscalls.h>
-#include <linux/time.h>
-#include <linux/sem.h>
-#include <linux/msg.h>
-#include <linux/shm.h>
-#include <linux/ipc.h>
-#include <linux/compat.h>
-#include <asm/sys_ia32.h>
-
-asmlinkage long sys32_ipc(u32 call, int first, int second, int third,
-                          compat_uptr_t ptr, u32 fifth)
-{
-        int version;
-
-        version = call >> 16; /* hack for backward compatibility */
-        call &= 0xffff;
-
-        switch (call) {
-        case SEMOP:
-                /* struct sembuf is the same on 32 and 64bit :)) */
-                return sys_semtimedop(first, compat_ptr(ptr), second, NULL);
-        case SEMTIMEDOP:
-                return compat_sys_semtimedop(first, compat_ptr(ptr), second,
-                                                compat_ptr(fifth));
-        case SEMGET:
-                return sys_semget(first, second, third);
-        case SEMCTL:
-                return compat_sys_semctl(first, second, third, compat_ptr(ptr));
-
-        case MSGSND:
-                return compat_sys_msgsnd(first, second, third, compat_ptr(ptr));
-        case MSGRCV:
-                return compat_sys_msgrcv(first, second, fifth, third,
-                                         version, compat_ptr(ptr));
-        case MSGGET:
-                return sys_msgget((key_t) first, second);
-        case MSGCTL:
-                return compat_sys_msgctl(first, second, compat_ptr(ptr));
-
-        case SHMAT:
-                return compat_sys_shmat(first, second, third, version,
-                                        compat_ptr(ptr));
-        case SHMDT:
-                return sys_shmdt(compat_ptr(ptr));
-        case SHMGET:
-                return sys_shmget(first, (unsigned)second, third);
-        case SHMCTL:
-                return compat_sys_shmctl(first, second, compat_ptr(ptr));
-        }
-        return -ENOSYS;
-}
diff --git a/arch/x86/ia32/sys_ia32.c b/arch/x86/ia32/sys_ia32.c
index ad7a20cbc699..4e4907c67d92 100644
--- a/arch/x86/ia32/sys_ia32.c
+++ b/arch/x86/ia32/sys_ia32.c
@@ -166,12 +166,6 @@ asmlinkage long sys32_mmap(struct mmap_arg_struct32 __user *arg)
                                a.offset>>PAGE_SHIFT);
 }
 
-asmlinkage long sys32_mprotect(unsigned long start, size_t len,
-                               unsigned long prot)
-{
-        return sys_mprotect(start, len, prot);
-}
-
 asmlinkage long sys32_waitpid(compat_pid_t pid, unsigned int __user *stat_addr,
                               int options)
 {
@@ -194,35 +188,10 @@ asmlinkage long sys32_pwrite(unsigned int fd, const char __user *ubuf,
 }
 
 
-asmlinkage long sys32_sendfile(int out_fd, int in_fd,
-                               compat_off_t __user *offset, s32 count)
-{
-        mm_segment_t old_fs = get_fs();
-        int ret;
-        off_t of;
-
-        if (offset && get_user(of, offset))
-                return -EFAULT;
-
-        set_fs(KERNEL_DS);
-        ret = sys_sendfile(out_fd, in_fd, offset ? (off_t __user *)&of : NULL,
-                           count);
-        set_fs(old_fs);
-
-        if (offset && put_user(of, offset))
-                return -EFAULT;
-        return ret;
-}
-
 /*
  * Some system calls that need sign extended arguments. This could be
  * done by a generic wrapper.
  */
-long sys32_kill(int pid, int sig)
-{
-        return sys_kill(pid, sig);
-}
-
 long sys32_fadvise64_64(int fd, __u32 offset_low, __u32 offset_high,
                         __u32 len_low, __u32 len_high, int advice)
 {
@@ -246,12 +215,6 @@ long sys32_vm86_warning(void)
         return -ENOSYS;
 }
 
-long sys32_lookup_dcookie(u32 addr_low, u32 addr_high,
-                          char __user *buf, size_t len)
-{
-        return sys_lookup_dcookie(((u64)addr_high << 32) | addr_low, buf, len);
-}
-
 asmlinkage ssize_t sys32_readahead(int fd, unsigned off_lo, unsigned off_hi,
                                    size_t count)
 {
diff --git a/arch/x86/include/asm/bug.h b/arch/x86/include/asm/bug.h
index 11e1152222d0..2f03ff018d36 100644
--- a/arch/x86/include/asm/bug.h
+++ b/arch/x86/include/asm/bug.h
@@ -37,7 +37,4 @@ do {								\
 
 #include <asm-generic/bug.h>
 
-
-extern void show_regs_common(void);
-
 #endif /* _ASM_X86_BUG_H */
diff --git a/arch/x86/include/asm/cmpxchg.h b/arch/x86/include/asm/cmpxchg.h
index 8d871eaddb66..d47786acb016 100644
--- a/arch/x86/include/asm/cmpxchg.h
+++ b/arch/x86/include/asm/cmpxchg.h
@@ -35,7 +35,7 @@ extern void __add_wrong_size(void)
 
 /* 
  * An exchange-type operation, which takes a value and a pointer, and
- * returns a the old value.
+ * returns the old value.
  */
 #define __xchg_op(ptr, arg, op, lock)                                   \
         ({                                                              \
diff --git a/arch/x86/include/asm/context_tracking.h b/arch/x86/include/asm/context_tracking.h
index 1616562683e9..1fe49704b146 100644
--- a/arch/x86/include/asm/context_tracking.h
+++ b/arch/x86/include/asm/context_tracking.h
@@ -1,31 +1,10 @@
 #ifndef _ASM_X86_CONTEXT_TRACKING_H
 #define _ASM_X86_CONTEXT_TRACKING_H
 
-#ifndef __ASSEMBLY__
-#include <linux/context_tracking.h>
-#include <asm/ptrace.h>
-
-static inline void exception_enter(struct pt_regs *regs)
-{
-        user_exit();
-}
-
-static inline void exception_exit(struct pt_regs *regs)
-{
-#ifdef CONFIG_CONTEXT_TRACKING
-        if (user_mode(regs))
-                user_enter();
-#endif
-}
-
-#else /* __ASSEMBLY__ */
-
 #ifdef CONFIG_CONTEXT_TRACKING
 # define SCHEDULE_USER call schedule_user
 #else
 # define SCHEDULE_USER call schedule
 #endif
 
-#endif /* !__ASSEMBLY__ */
-
 #endif
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 93fe929d1cee..e99ac27f95b2 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -9,6 +9,7 @@
 #endif
 
 #define NCAPINTS        10      /* N 32-bit words worth of info */
+#define NBUGINTS        1       /* N 32-bit bug flags */
 
 /*
  * Note: If the comment begins with a quoted string, that string is used
@@ -100,6 +101,7 @@
 #define X86_FEATURE_AMD_DCM     (3*32+27) /* multi-node processor */
 #define X86_FEATURE_APERFMPERF  (3*32+28) /* APERFMPERF */
 #define X86_FEATURE_EAGER_FPU   (3*32+29) /* "eagerfpu" Non lazy FPU restore */
+#define X86_FEATURE_NONSTOP_TSC_S3 (3*32+30) /* TSC doesn't stop in S3 state */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3        (4*32+ 0) /* "pni" SSE-3 */
@@ -168,6 +170,7 @@
 #define X86_FEATURE_TOPOEXT     (6*32+22) /* topology extensions CPUID leafs */
 #define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */
 #define X86_FEATURE_PERFCTR_NB  (6*32+24) /* NB performance counter extensions */
+#define X86_FEATURE_PERFCTR_L2  (6*32+28) /* L2 performance counter extensions */
 
 /*
  * Auxiliary flags: Linux defined - For features scattered in various
@@ -182,6 +185,7 @@
 #define X86_FEATURE_PTS         (7*32+ 6) /* Intel Package Thermal Status */
 #define X86_FEATURE_DTHERM      (7*32+ 7) /* Digital Thermal Sensor */
 #define X86_FEATURE_HW_PSTATE   (7*32+ 8) /* AMD HW-PState */
+#define X86_FEATURE_PROC_FEEDBACK (7*32+ 9) /* AMD ProcFeedbackInterface */
 
 /* Virtualization flags: Linux defined, word 8 */
 #define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
@@ -216,6 +220,17 @@
 #define X86_FEATURE_ADX         (9*32+19) /* The ADCX and ADOX instructions */
 #define X86_FEATURE_SMAP        (9*32+20) /* Supervisor Mode Access Prevention */
 
+/*
+ * BUG word(s)
+ */
+#define X86_BUG(x)              (NCAPINTS*32 + (x))
+
+#define X86_BUG_F00F            X86_BUG(0) /* Intel F00F */
+#define X86_BUG_FDIV            X86_BUG(1) /* FPU FDIV */
+#define X86_BUG_COMA            X86_BUG(2) /* Cyrix 6x86 coma */
+#define X86_BUG_AMD_TLB_MMATCH  X86_BUG(3) /* AMD Erratum 383 */
+#define X86_BUG_AMD_APIC_C1E    X86_BUG(4) /* AMD Erratum 400 */
+
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 
 #include <asm/asm.h>
@@ -278,6 +293,7 @@ extern const char * const x86_power_flags[32];
 #define cpu_has_ssse3           boot_cpu_has(X86_FEATURE_SSSE3)
 #define cpu_has_aes             boot_cpu_has(X86_FEATURE_AES)
 #define cpu_has_avx             boot_cpu_has(X86_FEATURE_AVX)
+#define cpu_has_avx2            boot_cpu_has(X86_FEATURE_AVX2)
 #define cpu_has_ht              boot_cpu_has(X86_FEATURE_HT)
 #define cpu_has_mp              boot_cpu_has(X86_FEATURE_MP)
 #define cpu_has_nx              boot_cpu_has(X86_FEATURE_NX)
@@ -311,6 +327,7 @@ extern const char * const x86_power_flags[32];
 #define cpu_has_pclmulqdq       boot_cpu_has(X86_FEATURE_PCLMULQDQ)
 #define cpu_has_perfctr_core    boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
 #define cpu_has_perfctr_nb      boot_cpu_has(X86_FEATURE_PERFCTR_NB)
+#define cpu_has_perfctr_l2      boot_cpu_has(X86_FEATURE_PERFCTR_L2)
 #define cpu_has_cx8             boot_cpu_has(X86_FEATURE_CX8)
 #define cpu_has_cx16            boot_cpu_has(X86_FEATURE_CX16)
 #define cpu_has_eager_fpu       boot_cpu_has(X86_FEATURE_EAGER_FPU)
@@ -401,6 +418,13 @@ static __always_inline __pure bool __static_cpu_has(u16 bit)
 #define static_cpu_has(bit) boot_cpu_has(bit)
 #endif
 
+#define cpu_has_bug(c, bit)     cpu_has(c, (bit))
+#define set_cpu_bug(c, bit)     set_cpu_cap(c, (bit))
+#define clear_cpu_bug(c, bit)   clear_cpu_cap(c, (bit));
+
+#define static_cpu_has_bug(bit) static_cpu_has((bit))
+#define boot_cpu_has_bug(bit)   cpu_has_bug(&boot_cpu_data, (bit))
+
 #endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
 
 #endif /* _ASM_X86_CPUFEATURE_H */
diff --git a/arch/x86/include/asm/crypto/blowfish.h b/arch/x86/include/asm/crypto/blowfish.h
new file mode 100644
index 000000000000..f097b2face10
--- /dev/null
+++ b/arch/x86/include/asm/crypto/blowfish.h
@@ -0,0 +1,43 @@
+#ifndef ASM_X86_BLOWFISH_H
+#define ASM_X86_BLOWFISH_H
+
+#include <linux/crypto.h>
+#include <crypto/blowfish.h>
+
+#define BF_PARALLEL_BLOCKS 4
+
+/* regular block cipher functions */
+asmlinkage void __blowfish_enc_blk(struct bf_ctx *ctx, u8 *dst, const u8 *src,
+                                   bool xor);
+asmlinkage void blowfish_dec_blk(struct bf_ctx *ctx, u8 *dst, const u8 *src);
+
+/* 4-way parallel cipher functions */
+asmlinkage void __blowfish_enc_blk_4way(struct bf_ctx *ctx, u8 *dst,
+                                        const u8 *src, bool xor);
+asmlinkage void blowfish_dec_blk_4way(struct bf_ctx *ctx, u8 *dst,
+                                      const u8 *src);
+
+static inline void blowfish_enc_blk(struct bf_ctx *ctx, u8 *dst, const u8 *src)
+{
+        __blowfish_enc_blk(ctx, dst, src, false);
+}
+
+static inline void blowfish_enc_blk_xor(struct bf_ctx *ctx, u8 *dst,
+                                        const u8 *src)
+{
+        __blowfish_enc_blk(ctx, dst, src, true);
+}
+
+static inline void blowfish_enc_blk_4way(struct bf_ctx *ctx, u8 *dst,
+                                         const u8 *src)
+{
+        __blowfish_enc_blk_4way(ctx, dst, src, false);
+}
+
+static inline void blowfish_enc_blk_xor_4way(struct bf_ctx *ctx, u8 *dst,
+                                      const u8 *src)
+{
+        __blowfish_enc_blk_4way(ctx, dst, src, true);
+}
+
+#endif
diff --git a/arch/x86/include/asm/crypto/camellia.h b/arch/x86/include/asm/crypto/camellia.h
index 98038add801e..bb93333d9200 100644
--- a/arch/x86/include/asm/crypto/camellia.h
+++ b/arch/x86/include/asm/crypto/camellia.h
@@ -48,6 +48,22 @@ asmlinkage void __camellia_enc_blk_2way(struct camellia_ctx *ctx, u8 *dst,
 asmlinkage void camellia_dec_blk_2way(struct camellia_ctx *ctx, u8 *dst,
                                       const u8 *src);
 
+/* 16-way parallel cipher functions (avx/aes-ni) */
+asmlinkage void camellia_ecb_enc_16way(struct camellia_ctx *ctx, u8 *dst,
+                                       const u8 *src);
+asmlinkage void camellia_ecb_dec_16way(struct camellia_ctx *ctx, u8 *dst,
+                                       const u8 *src);
+
+asmlinkage void camellia_cbc_dec_16way(struct camellia_ctx *ctx, u8 *dst,
+                                       const u8 *src);
+asmlinkage void camellia_ctr_16way(struct camellia_ctx *ctx, u8 *dst,
+                                   const u8 *src, le128 *iv);
+
+asmlinkage void camellia_xts_enc_16way(struct camellia_ctx *ctx, u8 *dst,
+                                       const u8 *src, le128 *iv);
+asmlinkage void camellia_xts_dec_16way(struct camellia_ctx *ctx, u8 *dst,
+                                       const u8 *src, le128 *iv);
+
 static inline void camellia_enc_blk(struct camellia_ctx *ctx, u8 *dst,
                                     const u8 *src)
 {
@@ -79,4 +95,7 @@ extern void camellia_crypt_ctr(void *ctx, u128 *dst, const u128 *src,
 extern void camellia_crypt_ctr_2way(void *ctx, u128 *dst, const u128 *src,
                                     le128 *iv);
 
+extern void camellia_xts_enc(void *ctx, u128 *dst, const u128 *src, le128 *iv);
+extern void camellia_xts_dec(void *ctx, u128 *dst, const u128 *src, le128 *iv);
+
 #endif /* ASM_X86_CAMELLIA_H */
diff --git a/arch/x86/include/asm/crypto/glue_helper.h b/arch/x86/include/asm/crypto/glue_helper.h
index e2d65b061d27..1eef55596e82 100644
--- a/arch/x86/include/asm/crypto/glue_helper.h
+++ b/arch/x86/include/asm/crypto/glue_helper.h
@@ -14,10 +14,13 @@ typedef void (*common_glue_func_t)(void *ctx, u8 *dst, const u8 *src);
 typedef void (*common_glue_cbc_func_t)(void *ctx, u128 *dst, const u128 *src);
 typedef void (*common_glue_ctr_func_t)(void *ctx, u128 *dst, const u128 *src,
                                        le128 *iv);
+typedef void (*common_glue_xts_func_t)(void *ctx, u128 *dst, const u128 *src,
+                                       le128 *iv);
 
 #define GLUE_FUNC_CAST(fn) ((common_glue_func_t)(fn))
 #define GLUE_CBC_FUNC_CAST(fn) ((common_glue_cbc_func_t)(fn))
 #define GLUE_CTR_FUNC_CAST(fn) ((common_glue_ctr_func_t)(fn))
+#define GLUE_XTS_FUNC_CAST(fn) ((common_glue_xts_func_t)(fn))
 
 struct common_glue_func_entry {
         unsigned int num_blocks; /* number of blocks that @fn will process */
@@ -25,6 +28,7 @@ struct common_glue_func_entry {
                 common_glue_func_t ecb;
                 common_glue_cbc_func_t cbc;
                 common_glue_ctr_func_t ctr;
+                common_glue_xts_func_t xts;
         } fn_u;
 };
 
@@ -96,6 +100,16 @@ static inline void le128_inc(le128 *i)
         i->b = cpu_to_le64(b);
 }
 
+static inline void le128_gf128mul_x_ble(le128 *dst, const le128 *src)
+{
+        u64 a = le64_to_cpu(src->a);
+        u64 b = le64_to_cpu(src->b);
+        u64 _tt = ((s64)a >> 63) & 0x87;
+
+        dst->a = cpu_to_le64((a << 1) ^ (b >> 63));
+        dst->b = cpu_to_le64((b << 1) ^ _tt);
+}
+
 extern int glue_ecb_crypt_128bit(const struct common_glue_ctx *gctx,
                                  struct blkcipher_desc *desc,
                                  struct scatterlist *dst,
@@ -118,4 +132,14 @@ extern int glue_ctr_crypt_128bit(const struct common_glue_ctx *gctx,
                                  struct scatterlist *dst,
                                  struct scatterlist *src, unsigned int nbytes);
 
+extern int glue_xts_crypt_128bit(const struct common_glue_ctx *gctx,
+                                 struct blkcipher_desc *desc,
+                                 struct scatterlist *dst,
+                                 struct scatterlist *src, unsigned int nbytes,
+                                 common_glue_func_t tweak_fn, void *tweak_ctx,
+                                 void *crypt_ctx);
+
+extern void glue_xts_crypt_128bit_one(void *ctx, u128 *dst, const u128 *src,
+                                      le128 *iv, common_glue_func_t fn);
+
 #endif /* _CRYPTO_GLUE_HELPER_H */
diff --git a/arch/x86/include/asm/crypto/serpent-avx.h b/arch/x86/include/asm/crypto/serpent-avx.h
index 0da1d3e2a55c..33c2b8a435da 100644
--- a/arch/x86/include/asm/crypto/serpent-avx.h
+++ b/arch/x86/include/asm/crypto/serpent-avx.h
@@ -6,6 +6,16 @@
 
 #define SERPENT_PARALLEL_BLOCKS 8
 
+struct serpent_lrw_ctx {
+        struct lrw_table_ctx lrw_table;
+        struct serpent_ctx serpent_ctx;
+};
+
+struct serpent_xts_ctx {
+        struct serpent_ctx tweak_ctx;
+        struct serpent_ctx crypt_ctx;
+};
+
 asmlinkage void serpent_ecb_enc_8way_avx(struct serpent_ctx *ctx, u8 *dst,
                                          const u8 *src);
 asmlinkage void serpent_ecb_dec_8way_avx(struct serpent_ctx *ctx, u8 *dst,
@@ -16,4 +26,23 @@ asmlinkage void serpent_cbc_dec_8way_avx(struct serpent_ctx *ctx, u8 *dst,
 asmlinkage void serpent_ctr_8way_avx(struct serpent_ctx *ctx, u8 *dst,
                                      const u8 *src, le128 *iv);
 
+asmlinkage void serpent_xts_enc_8way_avx(struct serpent_ctx *ctx, u8 *dst,
+                                         const u8 *src, le128 *iv);
+asmlinkage void serpent_xts_dec_8way_avx(struct serpent_ctx *ctx, u8 *dst,
+                                         const u8 *src, le128 *iv);
+
+extern void __serpent_crypt_ctr(void *ctx, u128 *dst, const u128 *src,
+                                le128 *iv);
+
+extern void serpent_xts_enc(void *ctx, u128 *dst, const u128 *src, le128 *iv);
+extern void serpent_xts_dec(void *ctx, u128 *dst, const u128 *src, le128 *iv);
+
+extern int lrw_serpent_setkey(struct crypto_tfm *tfm, const u8 *key,
+                              unsigned int keylen);
+
+extern void lrw_serpent_exit_tfm(struct crypto_tfm *tfm);
+
+extern int xts_serpent_setkey(struct crypto_tfm *tfm, const u8 *key,
+                              unsigned int keylen);
+
 #endif
diff --git a/arch/x86/include/asm/crypto/twofish.h b/arch/x86/include/asm/crypto/twofish.h
index 878c51ceebb5..e655c6029b45 100644
--- a/arch/x86/include/asm/crypto/twofish.h
+++ b/arch/x86/include/asm/crypto/twofish.h
@@ -28,6 +28,20 @@ asmlinkage void __twofish_enc_blk_3way(struct twofish_ctx *ctx, u8 *dst,
 asmlinkage void twofish_dec_blk_3way(struct twofish_ctx *ctx, u8 *dst,
                                      const u8 *src);
 
+/* 8-way parallel cipher functions */
+asmlinkage void twofish_ecb_enc_8way(struct twofish_ctx *ctx, u8 *dst,
+                                     const u8 *src);
+asmlinkage void twofish_ecb_dec_8way(struct twofish_ctx *ctx, u8 *dst,
+                                     const u8 *src);
+asmlinkage void twofish_cbc_dec_8way(struct twofish_ctx *ctx, u8 *dst,
+                                     const u8 *src);
+asmlinkage void twofish_ctr_8way(struct twofish_ctx *ctx, u8 *dst,
+                                 const u8 *src, le128 *iv);
+asmlinkage void twofish_xts_enc_8way(struct twofish_ctx *ctx, u8 *dst,
+                                     const u8 *src, le128 *iv);
+asmlinkage void twofish_xts_dec_8way(struct twofish_ctx *ctx, u8 *dst,
+                                     const u8 *src, le128 *iv);
+
 /* helpers from twofish_x86_64-3way module */
 extern void twofish_dec_blk_cbc_3way(void *ctx, u128 *dst, const u128 *src);
 extern void twofish_enc_blk_ctr(void *ctx, u128 *dst, const u128 *src,
@@ -43,4 +57,8 @@ extern void lrw_twofish_exit_tfm(struct crypto_tfm *tfm);
 extern int xts_twofish_setkey(struct crypto_tfm *tfm, const u8 *key,
                               unsigned int keylen);
 
+/* helpers from twofish-avx module */
+extern void twofish_xts_enc(void *ctx, u128 *dst, const u128 *src, le128 *iv);
+extern void twofish_xts_dec(void *ctx, u128 *dst, const u128 *src, le128 *iv);
+
 #endif /* ASM_X86_TWOFISH_H */
diff --git a/arch/x86/include/asm/entry_arch.h b/arch/x86/include/asm/entry_arch.h
index 40afa0005c69..9bd4ecac72be 100644
--- a/arch/x86/include/asm/entry_arch.h
+++ b/arch/x86/include/asm/entry_arch.h
@@ -19,6 +19,10 @@ BUILD_INTERRUPT(reboot_interrupt,REBOOT_VECTOR)
 
 BUILD_INTERRUPT(x86_platform_ipi, X86_PLATFORM_IPI_VECTOR)
 
+#ifdef CONFIG_HAVE_KVM
+BUILD_INTERRUPT(kvm_posted_intr_ipi, POSTED_INTR_VECTOR)
+#endif
+
 /*
  * every pentium local APIC has two 'local interrupts', with a
  * soft-definable vector attached to both interrupts, one of
diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h
index a09c28571064..0dc7d9e21c34 100644
--- a/arch/x86/include/asm/fixmap.h
+++ b/arch/x86/include/asm/fixmap.h
@@ -104,12 +104,7 @@ enum fixed_addresses {
         FIX_LI_PCIA,    /* Lithium PCI Bridge A */
         FIX_LI_PCIB,    /* Lithium PCI Bridge B */
 #endif
-#ifdef CONFIG_X86_F00F_BUG
-        FIX_F00F_IDT,   /* Virtual mapping for IDT */
-#endif
-#ifdef CONFIG_X86_CYCLONE_TIMER
-        FIX_CYCLONE_TIMER, /*cyclone timer register*/
-#endif
+        FIX_RO_IDT,     /* Virtual mapping for read-only IDT */
 #ifdef CONFIG_X86_32
         FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
         FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
diff --git a/arch/x86/include/asm/hardirq.h b/arch/x86/include/asm/hardirq.h
index 81f04cee5f74..ab0ae1aa6d0a 100644
--- a/arch/x86/include/asm/hardirq.h
+++ b/arch/x86/include/asm/hardirq.h
@@ -12,6 +12,9 @@ typedef struct {
         unsigned int irq_spurious_count;
         unsigned int icr_read_retry_count;
 #endif
+#ifdef CONFIG_HAVE_KVM
+        unsigned int kvm_posted_intr_ipis;
+#endif
         unsigned int x86_platform_ipis; /* arch dependent */
         unsigned int apic_perf_irqs;
         unsigned int apic_irq_work_irqs;
diff --git a/arch/x86/include/asm/hugetlb.h b/arch/x86/include/asm/hugetlb.h
index bdd35dbd0605..a8091216963b 100644
--- a/arch/x86/include/asm/hugetlb.h
+++ b/arch/x86/include/asm/hugetlb.h
@@ -2,6 +2,7 @@
 #define _ASM_X86_HUGETLB_H
 
 #include <asm/page.h>
+#include <asm-generic/hugetlb.h>
 
 
 static inline int is_hugepage_only_range(struct mm_struct *mm,
diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h
index 10a78c3d3d5a..1da97efad08a 100644
--- a/arch/x86/include/asm/hw_irq.h
+++ b/arch/x86/include/asm/hw_irq.h
@@ -28,6 +28,7 @@
 /* Interrupt handlers registered during init_IRQ */
 extern void apic_timer_interrupt(void);
 extern void x86_platform_ipi(void);
+extern void kvm_posted_intr_ipi(void);
 extern void error_interrupt(void);
 extern void irq_work_interrupt(void);
 
diff --git a/arch/x86/include/asm/hypervisor.h b/arch/x86/include/asm/hypervisor.h
index 86095ed14135..2d4b5e6107cd 100644
--- a/arch/x86/include/asm/hypervisor.h
+++ b/arch/x86/include/asm/hypervisor.h
@@ -20,13 +20,11 @@
 #ifndef _ASM_X86_HYPERVISOR_H
 #define _ASM_X86_HYPERVISOR_H
 
+#ifdef CONFIG_HYPERVISOR_GUEST
+
 #include <asm/kvm_para.h>
 #include <asm/xen/hypervisor.h>
 
-extern void init_hypervisor(struct cpuinfo_x86 *c);
-extern void init_hypervisor_platform(void);
-extern bool hypervisor_x2apic_available(void);
-
 /*
  * x86 hypervisor information
  */
@@ -55,4 +53,12 @@ extern const struct hypervisor_x86 x86_hyper_ms_hyperv;
 extern const struct hypervisor_x86 x86_hyper_xen_hvm;
 extern const struct hypervisor_x86 x86_hyper_kvm;
 
-#endif
+extern void init_hypervisor(struct cpuinfo_x86 *c);
+extern void init_hypervisor_platform(void);
+extern bool hypervisor_x2apic_available(void);
+#else
+static inline void init_hypervisor(struct cpuinfo_x86 *c) { }
+static inline void init_hypervisor_platform(void) { }
+static inline bool hypervisor_x2apic_available(void) { return false; }
+#endif /* CONFIG_HYPERVISOR_GUEST */
+#endif /* _ASM_X86_HYPERVISOR_H */
diff --git a/arch/x86/include/asm/irq_remapping.h b/arch/x86/include/asm/irq_remapping.h
index 95fd3527f632..d806b228d2c0 100644
--- a/arch/x86/include/asm/irq_remapping.h
+++ b/arch/x86/include/asm/irq_remapping.h
@@ -24,10 +24,18 @@
 
 #include <asm/io_apic.h>
 
+struct IO_APIC_route_entry;
+struct io_apic_irq_attr;
+struct irq_chip;
+struct msi_msg;
+struct pci_dev;
+struct irq_cfg;
+
 #ifdef CONFIG_IRQ_REMAP
 
 extern void setup_irq_remapping_ops(void);
 extern int irq_remapping_supported(void);
+extern void set_irq_remapping_broken(void);
 extern int irq_remapping_prepare(void);
 extern int irq_remapping_enable(void);
 extern void irq_remapping_disable(void);
@@ -54,6 +62,7 @@ void irq_remap_modify_chip_defaults(struct irq_chip *chip);
 
 static inline void setup_irq_remapping_ops(void) { }
 static inline int irq_remapping_supported(void) { return 0; }
+static inline void set_irq_remapping_broken(void) { }
 static inline int irq_remapping_prepare(void) { return -ENODEV; }
 static inline int irq_remapping_enable(void) { return -ENODEV; }
 static inline void irq_remapping_disable(void) { }
diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_vectors.h
index aac5fa62a86c..5702d7e3111d 100644
--- a/arch/x86/include/asm/irq_vectors.h
+++ b/arch/x86/include/asm/irq_vectors.h
@@ -102,6 +102,11 @@
  */
 #define X86_PLATFORM_IPI_VECTOR         0xf7
 
+/* Vector for KVM to deliver posted interrupt IPI */
+#ifdef CONFIG_HAVE_KVM
+#define POSTED_INTR_VECTOR              0xf2
+#endif
+
 /*
  * IRQ work vector:
  */
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 4979778cc7fb..3741c653767c 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -31,7 +31,7 @@
 #include <asm/msr-index.h>
 #include <asm/asm.h>
 
-#define KVM_MAX_VCPUS 254
+#define KVM_MAX_VCPUS 255
 #define KVM_SOFT_MAX_VCPUS 160
 #define KVM_USER_MEM_SLOTS 125
 /* memory slots that are not exposed to userspace */
@@ -43,6 +43,8 @@
 #define KVM_PIO_PAGE_OFFSET 1
 #define KVM_COALESCED_MMIO_PAGE_OFFSET 2
 
+#define KVM_IRQCHIP_NUM_PINS  KVM_IOAPIC_NUM_PINS
+
 #define CR0_RESERVED_BITS                                               \
         (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
                           | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
@@ -94,9 +96,6 @@
 
 #define ASYNC_PF_PER_VCPU 64
 
-extern raw_spinlock_t kvm_lock;
-extern struct list_head vm_list;
-
 struct kvm_vcpu;
 struct kvm;
 struct kvm_async_pf;
@@ -230,6 +229,7 @@ struct kvm_mmu_page {
 #endif
 
         int write_flooding_count;
+        bool mmio_cached;
 };
 
 struct kvm_pio_request {
@@ -345,7 +345,6 @@ struct kvm_vcpu_arch {
         unsigned long apic_attention;
         int32_t apic_arb_prio;
         int mp_state;
-        int sipi_vector;
         u64 ia32_misc_enable_msr;
         bool tpr_access_reporting;
 
@@ -643,7 +642,7 @@ struct kvm_x86_ops {
         /* Create, but do not attach this VCPU */
         struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id);
         void (*vcpu_free)(struct kvm_vcpu *vcpu);
-        int (*vcpu_reset)(struct kvm_vcpu *vcpu);
+        void (*vcpu_reset)(struct kvm_vcpu *vcpu);
 
         void (*prepare_guest_switch)(struct kvm_vcpu *vcpu);
         void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
@@ -696,14 +695,16 @@ struct kvm_x86_ops {
         int (*nmi_allowed)(struct kvm_vcpu *vcpu);
         bool (*get_nmi_mask)(struct kvm_vcpu *vcpu);
         void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked);
-        void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
-        void (*enable_irq_window)(struct kvm_vcpu *vcpu);
+        int (*enable_nmi_window)(struct kvm_vcpu *vcpu);
+        int (*enable_irq_window)(struct kvm_vcpu *vcpu);
         void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
         int (*vm_has_apicv)(struct kvm *kvm);
         void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr);
         void (*hwapic_isr_update)(struct kvm *kvm, int isr);
         void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
         void (*set_virtual_x2apic_mode)(struct kvm_vcpu *vcpu, bool set);
+        void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector);
+        void (*sync_pir_to_irr)(struct kvm_vcpu *vcpu);
         int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
         int (*get_tdp_level)(void);
         u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
@@ -730,6 +731,7 @@ struct kvm_x86_ops {
         int (*check_intercept)(struct kvm_vcpu *vcpu,
                                struct x86_instruction_info *info,
                                enum x86_intercept_stage stage);
+        void (*handle_external_intr)(struct kvm_vcpu *vcpu);
 };
 
 struct kvm_arch_async_pf {
@@ -767,6 +769,7 @@ void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
                                      struct kvm_memory_slot *slot,
                                      gfn_t gfn_offset, unsigned long mask);
 void kvm_mmu_zap_all(struct kvm *kvm);
+void kvm_mmu_zap_mmio_sptes(struct kvm *kvm);
 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm);
 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages);
 
@@ -797,6 +800,7 @@ enum emulation_result {
 #define EMULTYPE_TRAP_UD            (1 << 1)
 #define EMULTYPE_SKIP               (1 << 2)
 #define EMULTYPE_RETRY              (1 << 3)
+#define EMULTYPE_NO_REEXECUTE       (1 << 4)
 int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2,
                             int emulation_type, void *insn, int insn_len);
 
@@ -807,6 +811,7 @@ static inline int emulate_instruction(struct kvm_vcpu *vcpu,
 }
 
 void kvm_enable_efer_bits(u64);
+bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer);
 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *data);
 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr);
 
@@ -819,6 +824,7 @@ int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu);
 
 void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg);
+void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector);
 
 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
                     int reason, bool has_error_code, u32 error_code);
@@ -973,7 +979,6 @@ enum {
  * Trap the fault and ignore the instruction if that happens.
  */
 asmlinkage void kvm_spurious_fault(void);
-extern bool kvm_rebooting;
 
 #define ____kvm_handle_fault_on_reboot(insn, cleanup_insn)      \
         "666: " insn "\n\t" \
@@ -1002,6 +1007,7 @@ int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v);
 int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu);
 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu);
 int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
+void kvm_vcpu_reset(struct kvm_vcpu *vcpu);
 
 void kvm_define_shared_msr(unsigned index, u32 msr);
 void kvm_set_shared_msr(unsigned index, u64 val, u64 mask);
@@ -1027,7 +1033,7 @@ void kvm_pmu_reset(struct kvm_vcpu *vcpu);
 void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu);
 bool kvm_pmu_msr(struct kvm_vcpu *vcpu, u32 msr);
 int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
-int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data);
+int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
 int kvm_pmu_read_pmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data);
 void kvm_handle_pmu_event(struct kvm_vcpu *vcpu);
 void kvm_deliver_pmi(struct kvm_vcpu *vcpu);
diff --git a/arch/x86/include/asm/lguest.h b/arch/x86/include/asm/lguest.h
index 0d97deba1e35..e2d4a4afa8c3 100644
--- a/arch/x86/include/asm/lguest.h
+++ b/arch/x86/include/asm/lguest.h
@@ -11,18 +11,11 @@
 
 #define GUEST_PL 1
 
-/* Every guest maps the core switcher code. */
-#define SHARED_SWITCHER_PAGES \
-        DIV_ROUND_UP(end_switcher_text - start_switcher_text, PAGE_SIZE)
-/* Pages for switcher itself, then two pages per cpu */
-#define TOTAL_SWITCHER_PAGES (SHARED_SWITCHER_PAGES + 2 * nr_cpu_ids)
-
-/* We map at -4M (-2M for PAE) for ease of mapping (one PTE page). */
-#ifdef CONFIG_X86_PAE
-#define SWITCHER_ADDR 0xFFE00000
-#else
-#define SWITCHER_ADDR 0xFFC00000
-#endif
+/* Page for Switcher text itself, then two pages per cpu */
+#define TOTAL_SWITCHER_PAGES (1 + 2 * nr_cpu_ids)
+
+/* Where we map the Switcher, in both Host and Guest. */
+extern unsigned long switcher_addr;
 
 /* Found in switcher.S */
 extern unsigned long default_idt_entries[];
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index f4076af1f4ed..fa5f71e021d5 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -146,13 +146,13 @@ DECLARE_PER_CPU(struct device *, mce_device);
 void mce_intel_feature_init(struct cpuinfo_x86 *c);
 void cmci_clear(void);
 void cmci_reenable(void);
-void cmci_rediscover(int dying);
+void cmci_rediscover(void);
 void cmci_recheck(void);
 #else
 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
 static inline void cmci_clear(void) {}
 static inline void cmci_reenable(void) {}
-static inline void cmci_rediscover(int dying) {}
+static inline void cmci_rediscover(void) {}
 static inline void cmci_recheck(void) {}
 #endif
 
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 9264802e2824..cb7502852acb 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -137,11 +137,11 @@ static inline unsigned long long native_read_pmc(int counter)
  * pointer indirection), this allows gcc to optimize better
  */
 
-#define rdmsr(msr, val1, val2)                                  \
+#define rdmsr(msr, low, high)                                   \
 do {                                                            \
         u64 __val = native_read_msr((msr));                     \
-        (void)((val1) = (u32)__val);                            \
-        (void)((val2) = (u32)(__val >> 32));                    \
+        (void)((low) = (u32)__val);                             \
+        (void)((high) = (u32)(__val >> 32));                    \
 } while (0)
 
 static inline void wrmsr(unsigned msr, unsigned low, unsigned high)
@@ -162,12 +162,12 @@ static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high)
 }
 
 /* rdmsr with exception handling */
-#define rdmsr_safe(msr, p1, p2)                                 \
+#define rdmsr_safe(msr, low, high)                              \
 ({                                                              \
         int __err;                                              \
         u64 __val = native_read_msr_safe((msr), &__err);        \
-        (*p1) = (u32)__val;                                     \
-        (*p2) = (u32)(__val >> 32);                             \
+        (*low) = (u32)__val;                                    \
+        (*high) = (u32)(__val >> 32);                           \
         __err;                                                  \
 })
 
@@ -208,7 +208,7 @@ do {                                                            \
 #define wrmsrl_safe(msr, val) wrmsr_safe((msr), (u32)(val),             \
                                              (u32)((val) >> 32))
 
-#define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2))
+#define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high))
 
 #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
 
diff --git a/arch/x86/include/asm/page_64_types.h b/arch/x86/include/asm/page_64_types.h
index 8b491e66eaa8..6c896fbe21db 100644
--- a/arch/x86/include/asm/page_64_types.h
+++ b/arch/x86/include/asm/page_64_types.h
@@ -48,6 +48,5 @@
  * arch/x86/kernel/head_64.S), and it is mapped here:
  */
 #define KERNEL_IMAGE_SIZE       (512 * 1024 * 1024)
-#define KERNEL_IMAGE_START      _AC(0xffffffff80000000, UL)
 
 #endif /* _ASM_X86_PAGE_64_DEFS_H */
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index 7361e47db79f..cfdc9ee4c900 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -262,10 +262,6 @@ static inline void set_ldt(const void *addr, unsigned entries)
 {
         PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries);
 }
-static inline void store_gdt(struct desc_ptr *dtr)
-{
-        PVOP_VCALL1(pv_cpu_ops.store_gdt, dtr);
-}
 static inline void store_idt(struct desc_ptr *dtr)
 {
         PVOP_VCALL1(pv_cpu_ops.store_idt, dtr);
diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h
index b3b0ec1dac86..0db1fcac668c 100644
--- a/arch/x86/include/asm/paravirt_types.h
+++ b/arch/x86/include/asm/paravirt_types.h
@@ -123,7 +123,7 @@ struct pv_cpu_ops {
         void (*load_tr_desc)(void);
         void (*load_gdt)(const struct desc_ptr *);
         void (*load_idt)(const struct desc_ptr *);
-        void (*store_gdt)(struct desc_ptr *);
+        /* store_gdt has been removed. */
         void (*store_idt)(struct desc_ptr *);
         void (*set_ldt)(const void *desc, unsigned entries);
         unsigned long (*store_tr)(void);
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index 4f7e67e2345e..85e13ccf15c4 100644
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -24,45 +24,45 @@
 #define ARCH_P4_CNTRVAL_MASK    ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
 #define ARCH_P4_UNFLAGGED_BIT   ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1))
 
-#define P4_ESCR_EVENT_MASK      0x7e000000U
+#define P4_ESCR_EVENT_MASK      0x7e000000ULL
 #define P4_ESCR_EVENT_SHIFT     25
-#define P4_ESCR_EVENTMASK_MASK  0x01fffe00U
+#define P4_ESCR_EVENTMASK_MASK  0x01fffe00ULL
 #define P4_ESCR_EVENTMASK_SHIFT 9
-#define P4_ESCR_TAG_MASK        0x000001e0U
+#define P4_ESCR_TAG_MASK        0x000001e0ULL
 #define P4_ESCR_TAG_SHIFT       5
-#define P4_ESCR_TAG_ENABLE      0x00000010U
-#define P4_ESCR_T0_OS           0x00000008U
-#define P4_ESCR_T0_USR          0x00000004U
-#define P4_ESCR_T1_OS           0x00000002U
-#define P4_ESCR_T1_USR          0x00000001U
+#define P4_ESCR_TAG_ENABLE      0x00000010ULL
+#define P4_ESCR_T0_OS           0x00000008ULL
+#define P4_ESCR_T0_USR          0x00000004ULL
+#define P4_ESCR_T1_OS           0x00000002ULL
+#define P4_ESCR_T1_USR          0x00000001ULL
 
 #define P4_ESCR_EVENT(v)        ((v) << P4_ESCR_EVENT_SHIFT)
 #define P4_ESCR_EMASK(v)        ((v) << P4_ESCR_EVENTMASK_SHIFT)
 #define P4_ESCR_TAG(v)          ((v) << P4_ESCR_TAG_SHIFT)
 
-#define P4_CCCR_OVF                     0x80000000U
-#define P4_CCCR_CASCADE                 0x40000000U
-#define P4_CCCR_OVF_PMI_T0              0x04000000U
-#define P4_CCCR_OVF_PMI_T1              0x08000000U
-#define P4_CCCR_FORCE_OVF               0x02000000U
-#define P4_CCCR_EDGE                    0x01000000U
-#define P4_CCCR_THRESHOLD_MASK          0x00f00000U
+#define P4_CCCR_OVF                     0x80000000ULL
+#define P4_CCCR_CASCADE                 0x40000000ULL
+#define P4_CCCR_OVF_PMI_T0              0x04000000ULL
+#define P4_CCCR_OVF_PMI_T1              0x08000000ULL
+#define P4_CCCR_FORCE_OVF               0x02000000ULL
+#define P4_CCCR_EDGE                    0x01000000ULL
+#define P4_CCCR_THRESHOLD_MASK          0x00f00000ULL
 #define P4_CCCR_THRESHOLD_SHIFT         20
-#define P4_CCCR_COMPLEMENT              0x00080000U
-#define P4_CCCR_COMPARE                 0x00040000U
-#define P4_CCCR_ESCR_SELECT_MASK        0x0000e000U
+#define P4_CCCR_COMPLEMENT              0x00080000ULL
+#define P4_CCCR_COMPARE                 0x00040000ULL
+#define P4_CCCR_ESCR_SELECT_MASK        0x0000e000ULL
 #define P4_CCCR_ESCR_SELECT_SHIFT       13
-#define P4_CCCR_ENABLE                  0x00001000U
-#define P4_CCCR_THREAD_SINGLE           0x00010000U
-#define P4_CCCR_THREAD_BOTH             0x00020000U
-#define P4_CCCR_THREAD_ANY              0x00030000U
-#define P4_CCCR_RESERVED                0x00000fffU
+#define P4_CCCR_ENABLE                  0x00001000ULL
+#define P4_CCCR_THREAD_SINGLE           0x00010000ULL
+#define P4_CCCR_THREAD_BOTH             0x00020000ULL
+#define P4_CCCR_THREAD_ANY              0x00030000ULL
+#define P4_CCCR_RESERVED                0x00000fffULL
 
 #define P4_CCCR_THRESHOLD(v)            ((v) << P4_CCCR_THRESHOLD_SHIFT)
 #define P4_CCCR_ESEL(v)                 ((v) << P4_CCCR_ESCR_SELECT_SHIFT)
 
 #define P4_GEN_ESCR_EMASK(class, name, bit)     \
-        class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT)
+        class##__##name = ((1ULL << bit) << P4_ESCR_EVENTMASK_SHIFT)
 #define P4_ESCR_EMASK_BIT(class, name)          class##__##name
 
 /*
@@ -107,7 +107,7 @@
  * P4_PEBS_CONFIG_MASK and related bits on
  * modification.)
  */
-#define P4_CONFIG_ALIASABLE             (1 << 9)
+#define P4_CONFIG_ALIASABLE             (1ULL << 9)
 
 /*
  * The bits we allow to pass for RAW events
@@ -784,17 +784,17 @@ enum P4_ESCR_EMASKS {
  * Note we have UOP and PEBS bits reserved for now
  * just in case if we will need them once
  */
-#define P4_PEBS_CONFIG_ENABLE           (1 << 7)
-#define P4_PEBS_CONFIG_UOP_TAG          (1 << 8)
-#define P4_PEBS_CONFIG_METRIC_MASK      0x3f
-#define P4_PEBS_CONFIG_MASK             0xff
+#define P4_PEBS_CONFIG_ENABLE           (1ULL << 7)
+#define P4_PEBS_CONFIG_UOP_TAG          (1ULL << 8)
+#define P4_PEBS_CONFIG_METRIC_MASK      0x3FLL
+#define P4_PEBS_CONFIG_MASK             0xFFLL
 
 /*
  * mem: Only counters MSR_IQ_COUNTER4 (16) and
  * MSR_IQ_COUNTER5 (17) are allowed for PEBS sampling
  */
-#define P4_PEBS_ENABLE                  0x02000000U
-#define P4_PEBS_ENABLE_UOP_TAG          0x01000000U
+#define P4_PEBS_ENABLE                  0x02000000ULL
+#define P4_PEBS_ENABLE_UOP_TAG          0x01000000ULL
 
 #define p4_config_unpack_metric(v)      (((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK)
 #define p4_config_unpack_pebs(v)        (((u64)(v)) & P4_PEBS_CONFIG_MASK)
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index 567b5d0632b2..e6423002c10b 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -351,7 +351,6 @@ static inline void update_page_count(int level, unsigned long pages) { }
  * as a pte too.
  */
 extern pte_t *lookup_address(unsigned long address, unsigned int *level);
-extern int __split_large_page(pte_t *kpte, unsigned long address, pte_t *pbase);
 extern phys_addr_t slow_virt_to_phys(void *__address);
 
 #endif  /* !__ASSEMBLY__ */
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 3270116b1488..22224b3b43bb 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -91,9 +91,6 @@ struct cpuinfo_x86 {
         /* Problems on some 486Dx4's and old 386's: */
         char                    hard_math;
         char                    rfu;
-        char                    fdiv_bug;
-        char                    f00f_bug;
-        char                    coma_bug;
         char                    pad0;
 #else
         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
@@ -107,7 +104,7 @@ struct cpuinfo_x86 {
         __u32                   extended_cpuid_level;
         /* Maximum supported CPUID level, -1=no CPUID: */
         int                     cpuid_level;
-        __u32                   x86_capability[NCAPINTS];
+        __u32                   x86_capability[NCAPINTS + NBUGINTS];
         char                    x86_vendor_id[16];
         char                    x86_model_id[64];
         /* in KB - valid for CPUS which support this call: */
@@ -973,26 +970,6 @@ unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
         return ratio;
 }
 
-/*
- * AMD errata checking
- */
-#ifdef CONFIG_CPU_SUP_AMD
-extern const int amd_erratum_383[];
-extern const int amd_erratum_400[];
-extern bool cpu_has_amd_erratum(const int *);
-
-#define AMD_LEGACY_ERRATUM(...)         { -1, __VA_ARGS__, 0 }
-#define AMD_OSVW_ERRATUM(osvw_id, ...)  { osvw_id, __VA_ARGS__, 0 }
-#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
-        ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
-#define AMD_MODEL_RANGE_FAMILY(range)   (((range) >> 24) & 0xff)
-#define AMD_MODEL_RANGE_START(range)    (((range) >> 12) & 0xfff)
-#define AMD_MODEL_RANGE_END(range)      ((range) & 0xfff)
-
-#else
-#define cpu_has_amd_erratum(x)  (false)
-#endif /* CONFIG_CPU_SUP_AMD */
-
 extern unsigned long arch_align_stack(unsigned long sp);
 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 
diff --git a/arch/x86/include/asm/rwsem.h b/arch/x86/include/asm/rwsem.h
index 2dbe4a721ce5..cad82c9c2fde 100644
--- a/arch/x86/include/asm/rwsem.h
+++ b/arch/x86/include/asm/rwsem.h
@@ -105,8 +105,8 @@ static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
         asm volatile("# beginning down_write\n\t"
                      LOCK_PREFIX "  xadd      %1,(%2)\n\t"
                      /* adds 0xffff0001, returns the old value */
-                     "  test      %1,%1\n\t"
-                     /* was the count 0 before? */
+                     "  test " __ASM_SEL(%w1,%k1) "," __ASM_SEL(%w1,%k1) "\n\t"
+                     /* was the active mask 0 before? */
                      "  jz        1f\n"
                      "  call call_rwsem_down_write_failed\n"
                      "1:\n"
@@ -126,11 +126,25 @@ static inline void __down_write(struct rw_semaphore *sem)
  */
 static inline int __down_write_trylock(struct rw_semaphore *sem)
 {
-        long ret = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
-                           RWSEM_ACTIVE_WRITE_BIAS);
-        if (ret == RWSEM_UNLOCKED_VALUE)
-                return 1;
-        return 0;
+        long result, tmp;
+        asm volatile("# beginning __down_write_trylock\n\t"
+                     "  mov          %0,%1\n\t"
+                     "1:\n\t"
+                     "  test " __ASM_SEL(%w1,%k1) "," __ASM_SEL(%w1,%k1) "\n\t"
+                     /* was the active mask 0 before? */
+                     "  jnz          2f\n\t"
+                     "  mov          %1,%2\n\t"
+                     "  add          %3,%2\n\t"
+                     LOCK_PREFIX "  cmpxchg  %2,%0\n\t"
+                     "  jnz          1b\n\t"
+                     "2:\n\t"
+                     "  sete         %b1\n\t"
+                     "  movzbl       %b1, %k1\n\t"
+                     "# ending __down_write_trylock\n\t"
+                     : "+m" (sem->count), "=&a" (result), "=&r" (tmp)
+                     : "er" (RWSEM_ACTIVE_WRITE_BIAS)
+                     : "memory", "cc");
+        return result;
 }
 
 /*
diff --git a/arch/x86/include/asm/suspend_32.h b/arch/x86/include/asm/suspend_32.h
index 487055c8c1aa..552d6c90a6d4 100644
--- a/arch/x86/include/asm/suspend_32.h
+++ b/arch/x86/include/asm/suspend_32.h
@@ -15,7 +15,7 @@ struct saved_context {
         unsigned long cr0, cr2, cr3, cr4;
         u64 misc_enable;
         bool misc_enable_saved;
-        struct desc_ptr gdt;
+        struct desc_ptr gdt_desc;
         struct desc_ptr idt;
         u16 ldt;
         u16 tss;
diff --git a/arch/x86/include/asm/suspend_64.h b/arch/x86/include/asm/suspend_64.h
index 09b0bf104156..bc6232834bab 100644
--- a/arch/x86/include/asm/suspend_64.h
+++ b/arch/x86/include/asm/suspend_64.h
@@ -25,9 +25,8 @@ struct saved_context {
         u64 misc_enable;
         bool misc_enable_saved;
         unsigned long efer;
-        u16 gdt_pad;
-        u16 gdt_limit;
-        unsigned long gdt_base;
+        u16 gdt_pad; /* Unused */
+        struct desc_ptr gdt_desc;
         u16 idt_pad;
         u16 idt_limit;
         unsigned long idt_base;
diff --git a/arch/x86/include/asm/sys_ia32.h b/arch/x86/include/asm/sys_ia32.h
index 8459efc39686..0ef202e232d6 100644
--- a/arch/x86/include/asm/sys_ia32.h
+++ b/arch/x86/include/asm/sys_ia32.h
@@ -30,23 +30,14 @@ asmlinkage long sys32_fstatat(unsigned int, const char __user *,
                               struct stat64 __user *, int);
 struct mmap_arg_struct32;
 asmlinkage long sys32_mmap(struct mmap_arg_struct32 __user *);
-asmlinkage long sys32_mprotect(unsigned long, size_t, unsigned long);
-
-asmlinkage long sys32_alarm(unsigned int);
 
 asmlinkage long sys32_waitpid(compat_pid_t, unsigned int __user *, int);
-asmlinkage long sys32_sysfs(int, u32, u32);
 
 asmlinkage long sys32_pread(unsigned int, char __user *, u32, u32, u32);
 asmlinkage long sys32_pwrite(unsigned int, const char __user *, u32, u32, u32);
 
-asmlinkage long sys32_personality(unsigned long);
-asmlinkage long sys32_sendfile(int, int, compat_off_t __user *, s32);
-
-long sys32_kill(int, int);
 long sys32_fadvise64_64(int, __u32, __u32, __u32, __u32, int);
 long sys32_vm86_warning(void);
-long sys32_lookup_dcookie(u32, u32, char __user *, size_t);
 
 asmlinkage ssize_t sys32_readahead(int, unsigned, unsigned, size_t);
 asmlinkage long sys32_sync_file_range(int, unsigned, unsigned,
@@ -59,9 +50,6 @@ asmlinkage long sys32_fallocate(int, int, unsigned,
 asmlinkage long sys32_sigreturn(void);
 asmlinkage long sys32_rt_sigreturn(void);
 
-/* ia32/ipc32.c */
-asmlinkage long sys32_ipc(u32, int, int, int, compat_uptr_t, u32);
-
 asmlinkage long sys32_fanotify_mark(int, unsigned int, u32, u32, int,
                                     const char __user *);
 
diff --git a/arch/x86/include/asm/syscalls.h b/arch/x86/include/asm/syscalls.h
index 6cf0a9cc60cd..5f87b35fd2ef 100644
--- a/arch/x86/include/asm/syscalls.h
+++ b/arch/x86/include/asm/syscalls.h
@@ -27,8 +27,8 @@ asmlinkage int sys_modify_ldt(int, void __user *, unsigned long);
 long sys_rt_sigreturn(void);
 
 /* kernel/tls.c */
-asmlinkage int sys_set_thread_area(struct user_desc __user *);
-asmlinkage int sys_get_thread_area(struct user_desc __user *);
+asmlinkage long sys_set_thread_area(struct user_desc __user *);
+asmlinkage long sys_get_thread_area(struct user_desc __user *);
 
 /* X86_32 only */
 #ifdef CONFIG_X86_32
diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
index 2cd056e3ada3..a1df6e84691f 100644
--- a/arch/x86/include/asm/thread_info.h
+++ b/arch/x86/include/asm/thread_info.h
@@ -241,8 +241,6 @@ static inline struct thread_info *current_thread_info(void)
                                            skip sending interrupt */
 #define TS_RESTORE_SIGMASK      0x0008  /* restore signal mask in do_signal() */
 
-#define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING)
-
 #ifndef __ASSEMBLY__
 #define HAVE_SET_RESTORE_SIGMASK        1
 static inline void set_restore_sigmask(void)
diff --git a/arch/x86/include/asm/unistd.h b/arch/x86/include/asm/unistd.h
index 3d5df1c4447f..c2a48139c340 100644
--- a/arch/x86/include/asm/unistd.h
+++ b/arch/x86/include/asm/unistd.h
@@ -50,12 +50,4 @@
 # define __ARCH_WANT_SYS_VFORK
 # define __ARCH_WANT_SYS_CLONE
 
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-# define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
-
 #endif /* _ASM_X86_UNISTD_H */
diff --git a/arch/x86/include/asm/uprobes.h b/arch/x86/include/asm/uprobes.h
index 8ff8be7835ab..6e5197910fd8 100644
--- a/arch/x86/include/asm/uprobes.h
+++ b/arch/x86/include/asm/uprobes.h
@@ -55,4 +55,5 @@ extern int  arch_uprobe_post_xol(struct arch_uprobe *aup, struct pt_regs *regs);
 extern bool arch_uprobe_xol_was_trapped(struct task_struct *tsk);
 extern int  arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data);
 extern void arch_uprobe_abort_xol(struct arch_uprobe *aup, struct pt_regs *regs);
+extern unsigned long arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs);
 #endif  /* _ASM_UPROBES_H */
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index b6fbf860e398..f3e01a2cbaa1 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -65,11 +65,16 @@
 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY    0x00000200
 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING       0x00000400
 #define SECONDARY_EXEC_ENABLE_INVPCID           0x00001000
+#define SECONDARY_EXEC_SHADOW_VMCS              0x00004000
 
 
 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
 #define PIN_BASED_NMI_EXITING                   0x00000008
 #define PIN_BASED_VIRTUAL_NMIS                  0x00000020
+#define PIN_BASED_VMX_PREEMPTION_TIMER          0x00000040
+#define PIN_BASED_POSTED_INTR                   0x00000080
+
+#define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR     0x00000016
 
 #define VM_EXIT_SAVE_DEBUG_CONTROLS             0x00000002
 #define VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
@@ -81,6 +86,8 @@
 #define VM_EXIT_LOAD_IA32_EFER                  0x00200000
 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER       0x00400000
 
+#define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR       0x00036dff
+
 #define VM_ENTRY_LOAD_DEBUG_CONTROLS            0x00000002
 #define VM_ENTRY_IA32E_MODE                     0x00000200
 #define VM_ENTRY_SMM                            0x00000400
@@ -89,9 +96,15 @@
 #define VM_ENTRY_LOAD_IA32_PAT                  0x00004000
 #define VM_ENTRY_LOAD_IA32_EFER                 0x00008000
 
+#define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR      0x000011ff
+
+#define VMX_MISC_PREEMPTION_TIMER_RATE_MASK     0x0000001f
+#define VMX_MISC_SAVE_EFER_LMA                  0x00000020
+
 /* VMCS Encodings */
 enum vmcs_field {
         VIRTUAL_PROCESSOR_ID            = 0x00000000,
+        POSTED_INTR_NV                  = 0x00000002,
         GUEST_ES_SELECTOR               = 0x00000800,
         GUEST_CS_SELECTOR               = 0x00000802,
         GUEST_SS_SELECTOR               = 0x00000804,
@@ -126,6 +139,8 @@ enum vmcs_field {
         VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
         APIC_ACCESS_ADDR                = 0x00002014,
         APIC_ACCESS_ADDR_HIGH           = 0x00002015,
+        POSTED_INTR_DESC_ADDR           = 0x00002016,
+        POSTED_INTR_DESC_ADDR_HIGH      = 0x00002017,
         EPT_POINTER                     = 0x0000201a,
         EPT_POINTER_HIGH                = 0x0000201b,
         EOI_EXIT_BITMAP0                = 0x0000201c,
@@ -136,6 +151,8 @@ enum vmcs_field {
         EOI_EXIT_BITMAP2_HIGH           = 0x00002021,
         EOI_EXIT_BITMAP3                = 0x00002022,
         EOI_EXIT_BITMAP3_HIGH           = 0x00002023,
+        VMREAD_BITMAP                   = 0x00002026,
+        VMWRITE_BITMAP                  = 0x00002028,
         GUEST_PHYSICAL_ADDRESS          = 0x00002400,
         GUEST_PHYSICAL_ADDRESS_HIGH     = 0x00002401,
         VMCS_LINK_POINTER               = 0x00002800,
@@ -209,6 +226,7 @@ enum vmcs_field {
         GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
         GUEST_ACTIVITY_STATE            = 0X00004826,
         GUEST_SYSENTER_CS               = 0x0000482A,
+        VMX_PREEMPTION_TIMER_VALUE      = 0x0000482E,
         HOST_IA32_SYSENTER_CS           = 0x00004c00,
         CR0_GUEST_HOST_MASK             = 0x00006000,
         CR4_GUEST_HOST_MASK             = 0x00006002,
diff --git a/arch/x86/include/uapi/asm/kvm.h b/arch/x86/include/uapi/asm/kvm.h
index a65ec29e6ffb..5d9a3033b3d7 100644
--- a/arch/x86/include/uapi/asm/kvm.h
+++ b/arch/x86/include/uapi/asm/kvm.h
@@ -29,7 +29,6 @@
 #define __KVM_HAVE_PIT
 #define __KVM_HAVE_IOAPIC
 #define __KVM_HAVE_IRQ_LINE
-#define __KVM_HAVE_DEVICE_ASSIGNMENT
 #define __KVM_HAVE_MSI
 #define __KVM_HAVE_USER_NMI
 #define __KVM_HAVE_GUEST_DEBUG
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index 7a060f4b411f..b3a4866661c5 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -72,6 +72,7 @@
 #define MSR_IA32_PEBS_ENABLE            0x000003f1
 #define MSR_IA32_DS_AREA                0x00000600
 #define MSR_IA32_PERF_CAPABILITIES      0x00000345
+#define MSR_PEBS_LD_LAT_THRESHOLD       0x000003f6
 
 #define MSR_MTRRfix64K_00000            0x00000250
 #define MSR_MTRRfix16K_80000            0x00000258
@@ -195,6 +196,10 @@
 #define MSR_AMD64_IBSBRTARGET           0xc001103b
 #define MSR_AMD64_IBS_REG_COUNT_MAX     8 /* includes MSR_AMD64_IBSBRTARGET */
 
+/* Fam 16h MSRs */
+#define MSR_F16H_L2I_PERF_CTL           0xc0010230
+#define MSR_F16H_L2I_PERF_CTR           0xc0010231
+
 /* Fam 15h MSRs */
 #define MSR_F15H_PERF_CTL               0xc0010200
 #define MSR_F15H_PERF_CTR               0xc0010201
@@ -523,6 +528,8 @@
 #define VMX_BASIC_MEM_TYPE_WB   6LLU
 #define VMX_BASIC_INOUT         0x0040000000000000LLU
 
+/* MSR_IA32_VMX_MISC bits */
+#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
 /* AMD-V MSRs */
 
 #define MSR_VM_CR                       0xc0010114
diff --git a/arch/x86/include/uapi/asm/vmx.h b/arch/x86/include/uapi/asm/vmx.h
index 2871fccfee68..d651082c7cf7 100644
--- a/arch/x86/include/uapi/asm/vmx.h
+++ b/arch/x86/include/uapi/asm/vmx.h
@@ -65,6 +65,7 @@
 #define EXIT_REASON_EOI_INDUCED         45
 #define EXIT_REASON_EPT_VIOLATION       48
 #define EXIT_REASON_EPT_MISCONFIG       49
+#define EXIT_REASON_PREEMPTION_TIMER    52
 #define EXIT_REASON_WBINVD              54
 #define EXIT_REASON_XSETBV              55
 #define EXIT_REASON_APIC_WRITE          56
@@ -110,7 +111,7 @@
         { EXIT_REASON_EOI_INDUCED,           "EOI_INDUCED" }, \
         { EXIT_REASON_INVALID_STATE,         "INVALID_STATE" }, \
         { EXIT_REASON_INVD,                  "INVD" }, \
-        { EXIT_REASON_INVPCID,               "INVPCID" }
-
+        { EXIT_REASON_INVPCID,               "INVPCID" }, \
+        { EXIT_REASON_PREEMPTION_TIMER,      "PREEMPTION_TIMER" }
 
 #endif /* _UAPIVMX_H */
diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c
index 0532f5d6e4ef..b44577bc9744 100644
--- a/arch/x86/kernel/acpi/sleep.c
+++ b/arch/x86/kernel/acpi/sleep.c
@@ -46,7 +46,7 @@ int acpi_suspend_lowlevel(void)
         header->pmode_behavior = 0;
 
 #ifndef CONFIG_64BIT
-        store_gdt((struct desc_ptr *)&header->pmode_gdt);
+        native_store_gdt((struct desc_ptr *)&header->pmode_gdt);
 
         if (!rdmsr_safe(MSR_EFER,
                         &header->pmode_efer_low,
diff --git a/arch/x86/kernel/acpi/wakeup_32.S b/arch/x86/kernel/acpi/wakeup_32.S
index 13ab720573e3..d1daa66ab162 100644
--- a/arch/x86/kernel/acpi/wakeup_32.S
+++ b/arch/x86/kernel/acpi/wakeup_32.S
@@ -1,4 +1,4 @@
-        .section .text..page_aligned
+        .text
 #include <linux/linkage.h>
 #include <asm/segment.h>
 #include <asm/page_types.h>
@@ -18,7 +18,6 @@ wakeup_pmode_return:
         movw    %ax, %gs
 
         # reload the gdt, as we need the full 32 bit address
-        lgdt    saved_gdt
         lidt    saved_idt
         lldt    saved_ldt
         ljmp    $(__KERNEL_CS), $1f
@@ -44,7 +43,6 @@ bogus_magic:
 
 
 save_registers:
-        sgdt    saved_gdt
         sidt    saved_idt
         sldt    saved_ldt
         str     saved_tss
@@ -93,7 +91,6 @@ ENTRY(saved_magic)	.long	0
 ENTRY(saved_eip)        .long   0
 
 # saved registers
-saved_gdt:      .long   0,0
 saved_idt:      .long   0,0
 saved_ldt:      .long   0
 saved_tss:      .long   0
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index ef5ccca79a6c..c15cf9a25e27 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -271,7 +271,7 @@ void __init_or_module apply_alternatives(struct alt_instr *start,
                 replacement = (u8 *)&a->repl_offset + a->repl_offset;
                 BUG_ON(a->replacementlen > a->instrlen);
                 BUG_ON(a->instrlen > sizeof(insnbuf));
-                BUG_ON(a->cpuid >= NCAPINTS*32);
+                BUG_ON(a->cpuid >= (NCAPINTS + NBUGINTS) * 32);
                 if (!boot_cpu_has(a->cpuid))
                         continue;
 
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index aadf3359e2a7..3048ded1b598 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -20,12 +20,14 @@ const struct pci_device_id amd_nb_misc_ids[] = {
         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
+        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
         {}
 };
 EXPORT_SYMBOL(amd_nb_misc_ids);
 
-static struct pci_device_id amd_nb_link_ids[] = {
+static const struct pci_device_id amd_nb_link_ids[] = {
         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
+        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
         {}
 };
 
@@ -81,7 +83,6 @@ int amd_cache_northbridges(void)
                         next_northbridge(link, amd_nb_link_ids);
         }
 
-        /* some CPU families (e.g. family 0x11) do not support GART */
         if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||
             boot_cpu_data.x86 == 0x15)
                 amd_northbridges.flags |= AMD_NB_GART;
diff --git a/arch/x86/kernel/aperture_64.c b/arch/x86/kernel/aperture_64.c
index d5fd66f0d4cd..fd972a3e4cbb 100644
--- a/arch/x86/kernel/aperture_64.c
+++ b/arch/x86/kernel/aperture_64.c
@@ -87,7 +87,7 @@ static u32 __init allocate_aperture(void)
          */
         addr = memblock_find_in_range(GART_MIN_ADDR, GART_MAX_ADDR,
                                       aper_size, aper_size);
-        if (!addr || addr + aper_size > GART_MAX_ADDR) {
+        if (!addr) {
                 printk(KERN_ERR
                         "Cannot allocate aperture memory hole (%lx,%uK)\n",
                                 addr, aper_size>>10);
diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c
index 66b5faffe14a..53a4e2744846 100644
--- a/arch/x86/kernel/apm_32.c
+++ b/arch/x86/kernel/apm_32.c
@@ -373,7 +373,6 @@ static int apm_cpu_idle(struct cpuidle_device *dev,
 static struct cpuidle_driver apm_idle_driver = {
         .name = "apm_idle",
         .owner = THIS_MODULE,
-        .en_core_tk_irqen = 1,
         .states = {
                 { /* entry 0 is for polling */ },
                 { /* entry 1 is for APM idle */
diff --git a/arch/x86/kernel/asm-offsets_32.c b/arch/x86/kernel/asm-offsets_32.c
index 85d98ab15cdc..0ef4bba2acb7 100644
--- a/arch/x86/kernel/asm-offsets_32.c
+++ b/arch/x86/kernel/asm-offsets_32.c
@@ -60,6 +60,9 @@ void foo(void)
         OFFSET(IA32_RT_SIGFRAME_sigcontext, rt_sigframe, uc.uc_mcontext);
         BLANK();
 
+        OFFSET(saved_context_gdt_desc, saved_context, gdt_desc);
+        BLANK();
+
         /* Offset from the sysenter stack to tss.sp0 */
         DEFINE(TSS_sysenter_sp0, offsetof(struct tss_struct, x86_tss.sp0) -
                  sizeof(struct tss_struct));
diff --git a/arch/x86/kernel/asm-offsets_64.c b/arch/x86/kernel/asm-offsets_64.c
index 1b4754f82ba7..e7c798b354fa 100644
--- a/arch/x86/kernel/asm-offsets_64.c
+++ b/arch/x86/kernel/asm-offsets_64.c
@@ -73,6 +73,7 @@ int main(void)
         ENTRY(cr3);
         ENTRY(cr4);
         ENTRY(cr8);
+        ENTRY(gdt_desc);
         BLANK();
 #undef ENTRY
 
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index a0e067d3d96c..b0684e4a73aa 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -14,7 +14,6 @@ CFLAGS_common.o		:= $(nostackp)
 
 obj-y                   := intel_cacheinfo.o scattered.o topology.o
 obj-y                   += proc.o capflags.o powerflags.o common.o
-obj-y                   += vmware.o hypervisor.o mshyperv.o
 obj-y                   += rdrand.o
 obj-y                   += match.o
 
@@ -31,7 +30,7 @@ obj-$(CONFIG_CPU_SUP_UMC_32)		+= umc.o
 obj-$(CONFIG_PERF_EVENTS)               += perf_event.o
 
 ifdef CONFIG_PERF_EVENTS
-obj-$(CONFIG_CPU_SUP_AMD)               += perf_event_amd.o
+obj-$(CONFIG_CPU_SUP_AMD)               += perf_event_amd.o perf_event_amd_uncore.o
 obj-$(CONFIG_CPU_SUP_INTEL)             += perf_event_p6.o perf_event_knc.o perf_event_p4.o
 obj-$(CONFIG_CPU_SUP_INTEL)             += perf_event_intel_lbr.o perf_event_intel_ds.o perf_event_intel.o
 obj-$(CONFIG_CPU_SUP_INTEL)             += perf_event_intel_uncore.o
@@ -42,11 +41,13 @@ obj-$(CONFIG_MTRR)			+= mtrr/
 
 obj-$(CONFIG_X86_LOCAL_APIC)            += perfctr-watchdog.o perf_event_amd_ibs.o
 
+obj-$(CONFIG_HYPERVISOR_GUEST)          += vmware.o hypervisor.o mshyperv.o
+
 quiet_cmd_mkcapflags = MKCAP   $@
-      cmd_mkcapflags = $(PERL) $(srctree)/$(src)/mkcapflags.pl $< $@
+      cmd_mkcapflags = $(CONFIG_SHELL) $(srctree)/$(src)/mkcapflags.sh $< $@
 
 cpufeature = $(src)/../../include/asm/cpufeature.h
 
 targets += capflags.c
-$(obj)/capflags.c: $(cpufeature) $(src)/mkcapflags.pl FORCE
+$(obj)/capflags.c: $(cpufeature) $(src)/mkcapflags.sh FORCE
         $(call if_changed,mkcapflags)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index fa96eb0d02fb..5013a48d1aff 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -20,11 +20,11 @@
 
 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
 {
-        struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
         u32 gprs[8] = { 0 };
         int err;
 
-        WARN_ONCE((c->x86 != 0xf), "%s should only be used on K8!\n", __func__);
+        WARN_ONCE((boot_cpu_data.x86 != 0xf),
+                  "%s should only be used on K8!\n", __func__);
 
         gprs[1] = msr;
         gprs[7] = 0x9c5a203a;
@@ -38,10 +38,10 @@ static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
 
 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
 {
-        struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
         u32 gprs[8] = { 0 };
 
-        WARN_ONCE((c->x86 != 0xf), "%s should only be used on K8!\n", __func__);
+        WARN_ONCE((boot_cpu_data.x86 != 0xf),
+                  "%s should only be used on K8!\n", __func__);
 
         gprs[0] = (u32)val;
         gprs[1] = msr;
@@ -192,11 +192,11 @@ static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c)
         /* Athlon 660/661 is valid. */
         if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
             (c->x86_mask == 1)))
-                goto valid_k7;
+                return;
 
         /* Duron 670 is valid */
         if ((c->x86_model == 7) && (c->x86_mask == 0))
-                goto valid_k7;
+                return;
 
         /*
          * Athlon 662, Duron 671, and Athlon >model 7 have capability
@@ -209,7 +209,7 @@ static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c)
             ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
              (c->x86_model > 7))
                 if (cpu_has_mp)
-                        goto valid_k7;
+                        return;
 
         /* If we get here, not a certified SMP capable AMD system. */
 
@@ -220,9 +220,6 @@ static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c)
         WARN_ONCE(1, "WARNING: This combination of AMD"
                 " processors is not suitable for SMP.\n");
         add_taint(TAINT_UNSAFE_SMP, LOCKDEP_NOW_UNRELIABLE);
-
-valid_k7:
-        ;
 }
 
 static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
@@ -513,6 +510,10 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
 #endif
 }
 
+static const int amd_erratum_383[];
+static const int amd_erratum_400[];
+static bool cpu_has_amd_erratum(const int *erratum);
+
 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 {
         u32 dummy;
@@ -727,8 +728,14 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                 rdmsrl_safe(MSR_AMD64_BU_CFG2, &value);
                 value &= ~(1ULL << 24);
                 wrmsrl_safe(MSR_AMD64_BU_CFG2, value);
+
+                if (cpu_has_amd_erratum(amd_erratum_383))
+                        set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
         }
 
+        if (cpu_has_amd_erratum(amd_erratum_400))
+                set_cpu_bug(c, X86_BUG_AMD_APIC_C1E);
+
         rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
 }
 
@@ -847,8 +854,7 @@ cpu_dev_register(amd_cpu_dev);
  * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
  * have an OSVW id assigned, which it takes as first argument. Both take a
  * variable number of family-specific model-stepping ranges created by
- * AMD_MODEL_RANGE(). Each erratum also has to be declared as extern const
- * int[] in arch/x86/include/asm/processor.h.
+ * AMD_MODEL_RANGE().
  *
  * Example:
  *
@@ -858,16 +864,22 @@ cpu_dev_register(amd_cpu_dev);
  *                         AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
  */
 
-const int amd_erratum_400[] =
+#define AMD_LEGACY_ERRATUM(...)         { -1, __VA_ARGS__, 0 }
+#define AMD_OSVW_ERRATUM(osvw_id, ...)  { osvw_id, __VA_ARGS__, 0 }
+#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
+        ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
+#define AMD_MODEL_RANGE_FAMILY(range)   (((range) >> 24) & 0xff)
+#define AMD_MODEL_RANGE_START(range)    (((range) >> 12) & 0xfff)
+#define AMD_MODEL_RANGE_END(range)      ((range) & 0xfff)
+
+static const int amd_erratum_400[] =
         AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
                             AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
-EXPORT_SYMBOL_GPL(amd_erratum_400);
 
-const int amd_erratum_383[] =
+static const int amd_erratum_383[] =
         AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
-EXPORT_SYMBOL_GPL(amd_erratum_383);
 
-bool cpu_has_amd_erratum(const int *erratum)
+static bool cpu_has_amd_erratum(const int *erratum)
 {
         struct cpuinfo_x86 *cpu = __this_cpu_ptr(&cpu_info);
         int osvw_id = *erratum++;
@@ -908,5 +920,3 @@ bool cpu_has_amd_erratum(const int *erratum)
 
         return false;
 }
-
-EXPORT_SYMBOL_GPL(cpu_has_amd_erratum);
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index af6455e3fcc9..4112be9a4659 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -59,7 +59,7 @@ static void __init check_fpu(void)
          * trap_init() enabled FXSR and company _before_ testing for FP
          * problems here.
          *
-         * Test for the divl bug..
+         * Test for the divl bug: http://en.wikipedia.org/wiki/Fdiv_bug
          */
         __asm__("fninit\n\t"
                 "fldl %1\n\t"
@@ -75,26 +75,12 @@ static void __init check_fpu(void)
 
         kernel_fpu_end();
 
-        boot_cpu_data.fdiv_bug = fdiv_bug;
-        if (boot_cpu_data.fdiv_bug)
+        if (fdiv_bug) {
+                set_cpu_bug(&boot_cpu_data, X86_BUG_FDIV);
                 pr_warn("Hmm, FPU with FDIV bug\n");
+        }
 }
 
-/*
- * Check whether we are able to run this kernel safely on SMP.
- *
- * - i386 is no longer supported.
- * - In order to run on anything without a TSC, we need to be
- *   compiled for a i486.
- */
-
-static void __init check_config(void)
-{
-        if (boot_cpu_data.x86 < 4)
-                panic("Kernel requires i486+ for 'invlpg' and other features");
-}
-
-
 void __init check_bugs(void)
 {
         identify_boot_cpu();
@@ -102,7 +88,17 @@ void __init check_bugs(void)
         pr_info("CPU: ");
         print_cpu_info(&boot_cpu_data);
 #endif
-        check_config();
+
+        /*
+         * Check whether we are able to run this kernel safely on SMP.
+         *
+         * - i386 is no longer supported.
+         * - In order to run on anything without a TSC, we need to be
+         *   compiled for a i486.
+         */
+        if (boot_cpu_data.x86 < 4)
+                panic("Kernel requires i486+ for 'invlpg' and other features");
+
         init_utsname()->machine[1] =
                 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
         alternative_instructions();
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index d814772c5bed..22018f70a671 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -920,6 +920,10 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
                 /* AND the already accumulated flags with these */
                 for (i = 0; i < NCAPINTS; i++)
                         boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
+
+                /* OR, i.e. replicate the bug flags */
+                for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
+                        c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
         }
 
         /* Init Machine Check Exception if available. */
diff --git a/arch/x86/kernel/cpu/cyrix.c b/arch/x86/kernel/cpu/cyrix.c
index 4fbd384fb645..d048d5ca43c1 100644
--- a/arch/x86/kernel/cpu/cyrix.c
+++ b/arch/x86/kernel/cpu/cyrix.c
@@ -249,7 +249,7 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
                 /* Emulate MTRRs using Cyrix's ARRs. */
                 set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
                 /* 6x86's contain this bug */
-                c->coma_bug = 1;
+                set_cpu_bug(c, X86_BUG_COMA);
                 break;
 
         case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */
@@ -317,7 +317,8 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
                         /* Enable MMX extensions (App note 108) */
                         setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7)|1);
                 } else {
-                        c->coma_bug = 1;      /* 6x86MX, it has the bug. */
+                        /* A 6x86MX - it has the bug. */
+                        set_cpu_bug(c, X86_BUG_COMA);
                 }
                 tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0;
                 Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7];
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 1905ce98bee0..9b0c441c03f5 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -96,6 +96,18 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
                         sched_clock_stable = 1;
         }
 
+        /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
+        if (c->x86 == 6) {
+                switch (c->x86_model) {
+                case 0x27:      /* Penwell */
+                case 0x35:      /* Cloverview */
+                        set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
+                        break;
+                default:
+                        break;
+                }
+        }
+
         /*
          * There is a known erratum on Pentium III and Core Solo
          * and Core Duo CPUs.
@@ -164,20 +176,6 @@ int __cpuinit ppro_with_ram_bug(void)
         return 0;
 }
 
-#ifdef CONFIG_X86_F00F_BUG
-static void __cpuinit trap_init_f00f_bug(void)
-{
-        __set_fixmap(FIX_F00F_IDT, __pa_symbol(idt_table), PAGE_KERNEL_RO);
-
-        /*
-         * Update the IDT descriptor and reload the IDT so that
-         * it uses the read-only mapped virtual address.
-         */
-        idt_descr.address = fix_to_virt(FIX_F00F_IDT);
-        load_idt(&idt_descr);
-}
-#endif
-
 static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
 {
         /* calling is from identify_secondary_cpu() ? */
@@ -206,16 +204,14 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
         /*
          * All current models of Pentium and Pentium with MMX technology CPUs
          * have the F0 0F bug, which lets nonprivileged users lock up the
-         * system.
-         * Note that the workaround only should be initialized once...
+         * system. Announce that the fault handler will be checking for it.
          */
-        c->f00f_bug = 0;
+        clear_cpu_bug(c, X86_BUG_F00F);
         if (!paravirt_enabled() && c->x86 == 5) {
                 static int f00f_workaround_enabled;
 
-                c->f00f_bug = 1;
+                set_cpu_bug(c, X86_BUG_F00F);
                 if (!f00f_workaround_enabled) {
-                        trap_init_f00f_bug();
                         printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
                         f00f_workaround_enabled = 1;
                 }
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 7bc126346ace..9239504b41cb 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -2358,7 +2358,7 @@ mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
 
         if (action == CPU_POST_DEAD) {
                 /* intentionally ignoring frozen here */
-                cmci_rediscover(cpu);
+                cmci_rediscover();
         }
 
         return NOTIFY_OK;
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 1ac581f38dfa..9cb52767999a 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -33,7 +33,6 @@
 #include <asm/mce.h>
 #include <asm/msr.h>
 
-#define NR_BANKS          6
 #define NR_BLOCKS         9
 #define THRESHOLD_MAX     0xFFF
 #define INT_TYPE_APIC     0x00020000
@@ -57,12 +56,7 @@ static const char * const th_names[] = {
         "execution_unit",
 };
 
-static DEFINE_PER_CPU(struct threshold_bank * [NR_BANKS], threshold_banks);
-
-static unsigned char shared_bank[NR_BANKS] = {
-        0, 0, 0, 0, 1
-};
-
+static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
 static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
 
 static void amd_threshold_interrupt(void);
@@ -79,6 +73,12 @@ struct thresh_restart {
         u16                     old_limit;
 };
 
+static inline bool is_shared_bank(int bank)
+{
+        /* Bank 4 is for northbridge reporting and is thus shared */
+        return (bank == 4);
+}
+
 static const char * const bank4_names(struct threshold_block *b)
 {
         switch (b->address) {
@@ -214,7 +214,7 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
         unsigned int bank, block;
         int offset = -1;
 
-        for (bank = 0; bank < NR_BANKS; ++bank) {
+        for (bank = 0; bank < mca_cfg.banks; ++bank) {
                 for (block = 0; block < NR_BLOCKS; ++block) {
                         if (block == 0)
                                 address = MSR_IA32_MC0_MISC + bank * 4;
@@ -276,7 +276,7 @@ static void amd_threshold_interrupt(void)
         mce_setup(&m);
 
         /* assume first bank caused it */
-        for (bank = 0; bank < NR_BANKS; ++bank) {
+        for (bank = 0; bank < mca_cfg.banks; ++bank) {
                 if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
                         continue;
                 for (block = 0; block < NR_BLOCKS; ++block) {
@@ -467,7 +467,7 @@ static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
         u32 low, high;
         int err;
 
-        if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
+        if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS))
                 return 0;
 
         if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
@@ -575,7 +575,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
         const char *name = th_names[bank];
         int err = 0;
 
-        if (shared_bank[bank]) {
+        if (is_shared_bank(bank)) {
                 nb = node_to_amd_nb(amd_get_nb_id(cpu));
 
                 /* threshold descriptor already initialized on this node? */
@@ -609,7 +609,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
 
         per_cpu(threshold_banks, cpu)[bank] = b;
 
-        if (shared_bank[bank]) {
+        if (is_shared_bank(bank)) {
                 atomic_set(&b->cpus, 1);
 
                 /* nb is already initialized, see above */
@@ -635,9 +635,17 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
 static __cpuinit int threshold_create_device(unsigned int cpu)
 {
         unsigned int bank;
+        struct threshold_bank **bp;
         int err = 0;
 
-        for (bank = 0; bank < NR_BANKS; ++bank) {
+        bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks,
+                     GFP_KERNEL);
+        if (!bp)
+                return -ENOMEM;
+
+        per_cpu(threshold_banks, cpu) = bp;
+
+        for (bank = 0; bank < mca_cfg.banks; ++bank) {
                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
                         continue;
                 err = threshold_create_bank(cpu, bank);
@@ -691,7 +699,7 @@ static void threshold_remove_bank(unsigned int cpu, int bank)
         if (!b->blocks)
                 goto free_out;
 
-        if (shared_bank[bank]) {
+        if (is_shared_bank(bank)) {
                 if (!atomic_dec_and_test(&b->cpus)) {
                         __threshold_remove_blocks(b);
                         per_cpu(threshold_banks, cpu)[bank] = NULL;
@@ -719,11 +727,12 @@ static void threshold_remove_device(unsigned int cpu)
 {
         unsigned int bank;
 
-        for (bank = 0; bank < NR_BANKS; ++bank) {
+        for (bank = 0; bank < mca_cfg.banks; ++bank) {
                 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
                         continue;
                 threshold_remove_bank(cpu, bank);
         }
+        kfree(per_cpu(threshold_banks, cpu));
 }
 
 /* get notified when a cpu comes on/off */
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
index 402c454fbff0..ae1697c2afe3 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -285,39 +285,24 @@ void cmci_clear(void)
         raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
 }
 
-static long cmci_rediscover_work_func(void *arg)
+static void cmci_rediscover_work_func(void *arg)
 {
         int banks;
 
         /* Recheck banks in case CPUs don't all have the same */
         if (cmci_supported(&banks))
                 cmci_discover(banks);
-
-        return 0;
 }
 
-/*
- * After a CPU went down cycle through all the others and rediscover
- * Must run in process context.
- */
-void cmci_rediscover(int dying)
+/* After a CPU went down cycle through all the others and rediscover */
+void cmci_rediscover(void)
 {
-        int cpu, banks;
+        int banks;
 
         if (!cmci_supported(&banks))
                 return;
 
-        for_each_online_cpu(cpu) {
-                if (cpu == dying)
-                        continue;
-
-                if (cpu == smp_processor_id()) {
-                        cmci_rediscover_work_func(NULL);
-                        continue;
-                }
-
-                work_on_cpu(cpu, cmci_rediscover_work_func, NULL);
-        }
+        on_each_cpu(cmci_rediscover_work_func, NULL, 1);
 }
 
 /*
diff --git a/arch/x86/kernel/cpu/mkcapflags.pl b/arch/x86/kernel/cpu/mkcapflags.pl
deleted file mode 100644
index 091972ef49de..000000000000
--- a/arch/x86/kernel/cpu/mkcapflags.pl
+++ /dev/null
@@ -1,48 +0,0 @@
-#!/usr/bin/perl -w
-#
-# Generate the x86_cap_flags[] array from include/asm-x86/cpufeature.h
-#
-
-($in, $out) = @ARGV;
-
-open(IN, "< $in\0")   or die "$0: cannot open: $in: $!\n";
-open(OUT, "> $out\0") or die "$0: cannot create: $out: $!\n";
-
-print OUT "#ifndef _ASM_X86_CPUFEATURE_H\n";
-print OUT "#include <asm/cpufeature.h>\n";
-print OUT "#endif\n";
-print OUT "\n";
-print OUT "const char * const x86_cap_flags[NCAPINTS*32] = {\n";
-
-%features = ();
-$err = 0;
-
-while (defined($line = <IN>)) {
-        if ($line =~ /^\s*\#\s*define\s+(X86_FEATURE_(\S+))\s+(.*)$/) {
-                $macro = $1;
-                $feature = "\L$2";
-                $tail = $3;
-                if ($tail =~ /\/\*\s*\"([^"]*)\".*\*\//) {
-                        $feature = "\L$1";
-                }
-
-                next if ($feature eq '');
-
-                if ($features{$feature}++) {
-                        print STDERR "$in: duplicate feature name: $feature\n";
-                        $err++;
-                }
-                printf OUT "\t%-32s = \"%s\",\n", "[$macro]", $feature;
-        }
-}
-print OUT "};\n";
-
-close(IN);
-close(OUT);
-
-if ($err) {
-        unlink($out);
-        exit(1);
-}
-
-exit(0);
diff --git a/arch/x86/kernel/cpu/mkcapflags.sh b/arch/x86/kernel/cpu/mkcapflags.sh
new file mode 100644
index 000000000000..2bf616505499
--- /dev/null
+++ b/arch/x86/kernel/cpu/mkcapflags.sh
@@ -0,0 +1,41 @@
+#!/bin/sh
+#
+# Generate the x86_cap_flags[] array from include/asm/cpufeature.h
+#
+
+IN=$1
+OUT=$2
+
+TABS="$(printf '\t\t\t\t\t')"
+trap 'rm "$OUT"' EXIT
+
+(
+        echo "#ifndef _ASM_X86_CPUFEATURE_H"
+        echo "#include <asm/cpufeature.h>"
+        echo "#endif"
+        echo ""
+        echo "const char * const x86_cap_flags[NCAPINTS*32] = {"
+
+        # Iterate through any input lines starting with #define X86_FEATURE_
+        sed -n -e 's/\t/ /g' -e 's/^ *# *define *X86_FEATURE_//p' $IN |
+        while read i
+        do
+                # Name is everything up to the first whitespace
+                NAME="$(echo "$i" | sed 's/ .*//')"
+
+                # If the /* comment */ starts with a quote string, grab that.
+                VALUE="$(echo "$i" | sed -n 's@.*/\* *\("[^"]*"\).*\*/@\1@p')"
+                [ -z "$VALUE" ] && VALUE="\"$NAME\""
+                [ "$VALUE" == '""' ] && continue
+
+                # Name is uppercase, VALUE is all lowercase
+                VALUE="$(echo "$VALUE" | tr A-Z a-z)"
+
+                TABCOUNT=$(( ( 5*8 - 14 - $(echo "$NAME" | wc -c) ) / 8 ))
+                printf "\t[%s]%.*s = %s,\n" \
+                        "X86_FEATURE_$NAME" "$TABCOUNT" "$TABS" "$VALUE"
+        done
+        echo "};"
+) > $OUT
+
+trap - EXIT
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index bf0f01aea994..1025f3c99d20 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -180,8 +180,9 @@ static void release_pmc_hardware(void) {}
 
 static bool check_hw_exists(void)
 {
-        u64 val, val_new = ~0;
-        int i, reg, ret = 0;
+        u64 val, val_fail, val_new= ~0;
+        int i, reg, reg_fail, ret = 0;
+        int bios_fail = 0;
 
         /*
          * Check to see if the BIOS enabled any of the counters, if so
@@ -192,8 +193,11 @@ static bool check_hw_exists(void)
                 ret = rdmsrl_safe(reg, &val);
                 if (ret)
                         goto msr_fail;
-                if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
-                        goto bios_fail;
+                if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
+                        bios_fail = 1;
+                        val_fail = val;
+                        reg_fail = reg;
+                }
         }
 
         if (x86_pmu.num_counters_fixed) {
@@ -202,8 +206,11 @@ static bool check_hw_exists(void)
                 if (ret)
                         goto msr_fail;
                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
-                        if (val & (0x03 << i*4))
-                                goto bios_fail;
+                        if (val & (0x03 << i*4)) {
+                                bios_fail = 1;
+                                val_fail = val;
+                                reg_fail = reg;
+                        }
                 }
         }
 
@@ -221,14 +228,13 @@ static bool check_hw_exists(void)
         if (ret || val != val_new)
                 goto msr_fail;
 
-        return true;
-
-bios_fail:
         /*
          * We still allow the PMU driver to operate:
          */
-        printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
-        printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val);
+        if (bios_fail) {
+                printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
+                printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
+        }
 
         return true;
 
@@ -1316,9 +1322,16 @@ static struct attribute_group x86_pmu_format_group = {
  */
 static void __init filter_events(struct attribute **attrs)
 {
+        struct device_attribute *d;
+        struct perf_pmu_events_attr *pmu_attr;
         int i, j;
 
         for (i = 0; attrs[i]; i++) {
+                d = (struct device_attribute *)attrs[i];
+                pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
+                /* str trumps id */
+                if (pmu_attr->event_str)
+                        continue;
                 if (x86_pmu.event_map(i))
                         continue;
 
@@ -1330,22 +1343,45 @@ static void __init filter_events(struct attribute **attrs)
         }
 }
 
-static ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
+/* Merge two pointer arrays */
+static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
+{
+        struct attribute **new;
+        int j, i;
+
+        for (j = 0; a[j]; j++)
+                ;
+        for (i = 0; b[i]; i++)
+                j++;
+        j++;
+
+        new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
+        if (!new)
+                return NULL;
+
+        j = 0;
+        for (i = 0; a[i]; i++)
+                new[j++] = a[i];
+        for (i = 0; b[i]; i++)
+                new[j++] = b[i];
+        new[j] = NULL;
+
+        return new;
+}
+
+ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
                           char *page)
 {
         struct perf_pmu_events_attr *pmu_attr = \
                 container_of(attr, struct perf_pmu_events_attr, attr);
-
         u64 config = x86_pmu.event_map(pmu_attr->id);
-        return x86_pmu.events_sysfs_show(page, config);
-}
 
-#define EVENT_VAR(_id)  event_attr_##_id
-#define EVENT_PTR(_id) &event_attr_##_id.attr.attr
+        /* string trumps id */
+        if (pmu_attr->event_str)
+                return sprintf(page, "%s", pmu_attr->event_str);
 
-#define EVENT_ATTR(_name, _id)                                          \
-        PMU_EVENT_ATTR(_name, EVENT_VAR(_id), PERF_COUNT_HW_##_id,      \
-                        events_sysfs_show)
+        return x86_pmu.events_sysfs_show(page, config);
+}
 
 EVENT_ATTR(cpu-cycles,                  CPU_CYCLES              );
 EVENT_ATTR(instructions,                INSTRUCTIONS            );
@@ -1459,16 +1495,27 @@ static int __init init_hw_perf_events(void)
 
         unconstrained = (struct event_constraint)
                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
-                                   0, x86_pmu.num_counters, 0);
+                                   0, x86_pmu.num_counters, 0, 0);
 
         x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
 
+        if (x86_pmu.event_attrs)
+                x86_pmu_events_group.attrs = x86_pmu.event_attrs;
+
         if (!x86_pmu.events_sysfs_show)
                 x86_pmu_events_group.attrs = &empty_attrs;
         else
                 filter_events(x86_pmu_events_group.attrs);
 
+        if (x86_pmu.cpu_events) {
+                struct attribute **tmp;
+
+                tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
+                if (!WARN_ON(!tmp))
+                        x86_pmu_events_group.attrs = tmp;
+        }
+
         pr_info("... version:                %d\n",     x86_pmu.version);
         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index 7f5c75c2afdd..ba9aadfa683b 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -46,6 +46,7 @@ enum extra_reg_type {
         EXTRA_REG_RSP_0 = 0,    /* offcore_response_0 */
         EXTRA_REG_RSP_1 = 1,    /* offcore_response_1 */
         EXTRA_REG_LBR   = 2,    /* lbr_select */
+        EXTRA_REG_LDLAT = 3,    /* ld_lat_threshold */
 
         EXTRA_REG_MAX           /* number of entries needed */
 };
@@ -59,7 +60,13 @@ struct event_constraint {
         u64     cmask;
         int     weight;
         int     overlap;
+        int     flags;
 };
+/*
+ * struct event_constraint flags
+ */
+#define PERF_X86_EVENT_PEBS_LDLAT       0x1 /* ld+ldlat data address sampling */
+#define PERF_X86_EVENT_PEBS_ST          0x2 /* st data address sampling */
 
 struct amd_nb {
         int nb_id;  /* NorthBridge id */
@@ -170,16 +177,17 @@ struct cpu_hw_events {
         void                            *kfree_on_online;
 };
 
-#define __EVENT_CONSTRAINT(c, n, m, w, o) {\
+#define __EVENT_CONSTRAINT(c, n, m, w, o, f) {\
         { .idxmsk64 = (n) },            \
         .code = (c),                    \
         .cmask = (m),                   \
         .weight = (w),                  \
         .overlap = (o),                 \
+        .flags = f,                     \
 }
 
 #define EVENT_CONSTRAINT(c, n, m)       \
-        __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0)
+        __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
 
 /*
  * The overlap flag marks event constraints with overlapping counter
@@ -203,7 +211,7 @@ struct cpu_hw_events {
  * and its counter masks must be kept at a minimum.
  */
 #define EVENT_CONSTRAINT_OVERLAP(c, n, m)       \
-        __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1)
+        __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
 
 /*
  * Constraint on the Event code.
@@ -231,6 +239,14 @@ struct cpu_hw_events {
 #define INTEL_UEVENT_CONSTRAINT(c, n)   \
         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
 
+#define INTEL_PLD_CONSTRAINT(c, n)      \
+        __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
+                           HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
+
+#define INTEL_PST_CONSTRAINT(c, n)      \
+        __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
+                          HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
+
 #define EVENT_CONSTRAINT_END            \
         EVENT_CONSTRAINT(0, 0, 0)
 
@@ -260,12 +276,22 @@ struct extra_reg {
         .msr = (ms),            \
         .config_mask = (m),     \
         .valid_mask = (vm),     \
-        .idx = EXTRA_REG_##i    \
+        .idx = EXTRA_REG_##i,   \
         }
 
 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx)      \
         EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
 
+#define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
+        EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
+                        ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
+
+#define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
+        INTEL_UEVENT_EXTRA_REG(c, \
+                               MSR_PEBS_LD_LAT_THRESHOLD, \
+                               0xffff, \
+                               LDLAT)
+
 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
 
 union perf_capabilities {
@@ -355,8 +381,10 @@ struct x86_pmu {
          */
         int             attr_rdpmc;
         struct attribute **format_attrs;
+        struct attribute **event_attrs;
 
         ssize_t         (*events_sysfs_show)(char *page, u64 config);
+        struct attribute **cpu_events;
 
         /*
          * CPU Hotplug hooks
@@ -421,6 +449,23 @@ do {									\
 #define ERF_NO_HT_SHARING       1
 #define ERF_HAS_RSP_1           2
 
+#define EVENT_VAR(_id)  event_attr_##_id
+#define EVENT_PTR(_id) &event_attr_##_id.attr.attr
+
+#define EVENT_ATTR(_name, _id)                                          \
+static struct perf_pmu_events_attr EVENT_VAR(_id) = {                   \
+        .attr           = __ATTR(_name, 0444, events_sysfs_show, NULL), \
+        .id             = PERF_COUNT_HW_##_id,                          \
+        .event_str      = NULL,                                         \
+};
+
+#define EVENT_ATTR_STR(_name, v, str)                                   \
+static struct perf_pmu_events_attr event_attr_##v = {                   \
+        .attr           = __ATTR(_name, 0444, events_sysfs_show, NULL), \
+        .id             = 0,                                            \
+        .event_str      = str,                                          \
+};
+
 extern struct x86_pmu x86_pmu __read_mostly;
 
 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
@@ -628,6 +673,9 @@ int p6_pmu_init(void);
 
 int knc_pmu_init(void);
 
+ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
+                          char *page);
+
 #else /* CONFIG_CPU_SUP_INTEL */
 
 static inline void reserve_ds_buffers(void)
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index dfdab42aed27..7e28d9467bb4 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -132,14 +132,11 @@ static u64 amd_pmu_event_map(int hw_event)
         return amd_perfmon_event_map[hw_event];
 }
 
-static struct event_constraint *amd_nb_event_constraint;
-
 /*
  * Previously calculated offsets
  */
 static unsigned int event_offsets[X86_PMC_IDX_MAX] __read_mostly;
 static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly;
-static unsigned int rdpmc_indexes[X86_PMC_IDX_MAX] __read_mostly;
 
 /*
  * Legacy CPUs:
@@ -147,14 +144,10 @@ static unsigned int rdpmc_indexes[X86_PMC_IDX_MAX] __read_mostly;
  *
  * CPUs with core performance counter extensions:
  *   6 counters starting at 0xc0010200 each offset by 2
- *
- * CPUs with north bridge performance counter extensions:
- *   4 additional counters starting at 0xc0010240 each offset by 2
- *   (indexed right above either one of the above core counters)
  */
 static inline int amd_pmu_addr_offset(int index, bool eventsel)
 {
-        int offset, first, base;
+        int offset;
 
         if (!index)
                 return index;
@@ -167,23 +160,7 @@ static inline int amd_pmu_addr_offset(int index, bool eventsel)
         if (offset)
                 return offset;
 
-        if (amd_nb_event_constraint &&
-            test_bit(index, amd_nb_event_constraint->idxmsk)) {
-                /*
-                 * calculate the offset of NB counters with respect to
-                 * base eventsel or perfctr
-                 */
-
-                first = find_first_bit(amd_nb_event_constraint->idxmsk,
-                                       X86_PMC_IDX_MAX);
-
-                if (eventsel)
-                        base = MSR_F15H_NB_PERF_CTL - x86_pmu.eventsel;
-                else
-                        base = MSR_F15H_NB_PERF_CTR - x86_pmu.perfctr;
-
-                offset = base + ((index - first) << 1);
-        } else if (!cpu_has_perfctr_core)
+        if (!cpu_has_perfctr_core)
                 offset = index;
         else
                 offset = index << 1;
@@ -196,36 +173,6 @@ static inline int amd_pmu_addr_offset(int index, bool eventsel)
         return offset;
 }
 
-static inline int amd_pmu_rdpmc_index(int index)
-{
-        int ret, first;
-
-        if (!index)
-                return index;
-
-        ret = rdpmc_indexes[index];
-
-        if (ret)
-                return ret;
-
-        if (amd_nb_event_constraint &&
-            test_bit(index, amd_nb_event_constraint->idxmsk)) {
-                /*
-                 * according to the mnual, ECX value of the NB counters is
-                 * the index of the NB counter (0, 1, 2 or 3) plus 6
-                 */
-
-                first = find_first_bit(amd_nb_event_constraint->idxmsk,
-                                       X86_PMC_IDX_MAX);
-                ret = index - first + 6;
-        } else
-                ret = index;
-
-        rdpmc_indexes[index] = ret;
-
-        return ret;
-}
-
 static int amd_core_hw_config(struct perf_event *event)
 {
         if (event->attr.exclude_host && event->attr.exclude_guest)
@@ -245,34 +192,6 @@ static int amd_core_hw_config(struct perf_event *event)
 }
 
 /*
- * NB counters do not support the following event select bits:
- *   Host/Guest only
- *   Counter mask
- *   Invert counter mask
- *   Edge detect
- *   OS/User mode
- */
-static int amd_nb_hw_config(struct perf_event *event)
-{
-        /* for NB, we only allow system wide counting mode */
-        if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
-                return -EINVAL;
-
-        if (event->attr.exclude_user || event->attr.exclude_kernel ||
-            event->attr.exclude_host || event->attr.exclude_guest)
-                return -EINVAL;
-
-        event->hw.config &= ~(ARCH_PERFMON_EVENTSEL_USR |
-                              ARCH_PERFMON_EVENTSEL_OS);
-
-        if (event->hw.config & ~(AMD64_RAW_EVENT_MASK_NB |
-                                 ARCH_PERFMON_EVENTSEL_INT))
-                return -EINVAL;
-
-        return 0;
-}
-
-/*
  * AMD64 events are detected based on their event codes.
  */
 static inline unsigned int amd_get_event_code(struct hw_perf_event *hwc)
@@ -285,11 +204,6 @@ static inline int amd_is_nb_event(struct hw_perf_event *hwc)
         return (hwc->config & 0xe0) == 0xe0;
 }
 
-static inline int amd_is_perfctr_nb_event(struct hw_perf_event *hwc)
-{
-        return amd_nb_event_constraint && amd_is_nb_event(hwc);
-}
-
 static inline int amd_has_nb(struct cpu_hw_events *cpuc)
 {
         struct amd_nb *nb = cpuc->amd_nb;
@@ -315,9 +229,6 @@ static int amd_pmu_hw_config(struct perf_event *event)
         if (event->attr.type == PERF_TYPE_RAW)
                 event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK;
 
-        if (amd_is_perfctr_nb_event(&event->hw))
-                return amd_nb_hw_config(event);
-
         return amd_core_hw_config(event);
 }
 
@@ -341,19 +252,6 @@ static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc,
         }
 }
 
-static void amd_nb_interrupt_hw_config(struct hw_perf_event *hwc)
-{
-        int core_id = cpu_data(smp_processor_id()).cpu_core_id;
-
-        /* deliver interrupts only to this core */
-        if (hwc->config & ARCH_PERFMON_EVENTSEL_INT) {
-                hwc->config |= AMD64_EVENTSEL_INT_CORE_ENABLE;
-                hwc->config &= ~AMD64_EVENTSEL_INT_CORE_SEL_MASK;
-                hwc->config |= (u64)(core_id) <<
-                        AMD64_EVENTSEL_INT_CORE_SEL_SHIFT;
-        }
-}
-
  /*
   * AMD64 NorthBridge events need special treatment because
   * counter access needs to be synchronized across all cores
@@ -441,9 +339,6 @@ __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *ev
         if (new == -1)
                 return &emptyconstraint;
 
-        if (amd_is_perfctr_nb_event(hwc))
-                amd_nb_interrupt_hw_config(hwc);
-
         return &nb->event_constraints[new];
 }
 
@@ -543,8 +438,7 @@ amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
         if (!(amd_has_nb(cpuc) && amd_is_nb_event(&event->hw)))
                 return &unconstrained;
 
-        return __amd_get_nb_event_constraints(cpuc, event,
-                                              amd_nb_event_constraint);
+        return __amd_get_nb_event_constraints(cpuc, event, NULL);
 }
 
 static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
@@ -643,9 +537,6 @@ static struct event_constraint amd_f15_PMC30 = EVENT_CONSTRAINT_OVERLAP(0, 0x09,
 static struct event_constraint amd_f15_PMC50 = EVENT_CONSTRAINT(0, 0x3F, 0);
 static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0);
 
-static struct event_constraint amd_NBPMC96 = EVENT_CONSTRAINT(0, 0x3C0, 0);
-static struct event_constraint amd_NBPMC74 = EVENT_CONSTRAINT(0, 0xF0, 0);
-
 static struct event_constraint *
 amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *event)
 {
@@ -711,8 +602,8 @@ amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *ev
                         return &amd_f15_PMC20;
                 }
         case AMD_EVENT_NB:
-                return __amd_get_nb_event_constraints(cpuc, event,
-                                                      amd_nb_event_constraint);
+                /* moved to perf_event_amd_uncore.c */
+                return &emptyconstraint;
         default:
                 return &emptyconstraint;
         }
@@ -738,7 +629,6 @@ static __initconst const struct x86_pmu amd_pmu = {
         .eventsel               = MSR_K7_EVNTSEL0,
         .perfctr                = MSR_K7_PERFCTR0,
         .addr_offset            = amd_pmu_addr_offset,
-        .rdpmc_index            = amd_pmu_rdpmc_index,
         .event_map              = amd_pmu_event_map,
         .max_events             = ARRAY_SIZE(amd_perfmon_event_map),
         .num_counters           = AMD64_NUM_COUNTERS,
@@ -790,23 +680,6 @@ static int setup_perfctr_core(void)
         return 0;
 }
 
-static int setup_perfctr_nb(void)
-{
-        if (!cpu_has_perfctr_nb)
-                return -ENODEV;
-
-        x86_pmu.num_counters += AMD64_NUM_COUNTERS_NB;
-
-        if (cpu_has_perfctr_core)
-                amd_nb_event_constraint = &amd_NBPMC96;
-        else
-                amd_nb_event_constraint = &amd_NBPMC74;
-
-        printk(KERN_INFO "perf: AMD northbridge performance counters detected\n");
-
-        return 0;
-}
-
 __init int amd_pmu_init(void)
 {
         /* Performance-monitoring supported from K7 and later: */
@@ -817,7 +690,6 @@ __init int amd_pmu_init(void)
 
         setup_event_constraints();
         setup_perfctr_core();
-        setup_perfctr_nb();
 
         /* Events are common for all AMDs */
         memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
diff --git a/arch/x86/kernel/cpu/perf_event_amd_uncore.c b/arch/x86/kernel/cpu/perf_event_amd_uncore.c
new file mode 100644
index 000000000000..c0c661adf03e
--- /dev/null
+++ b/arch/x86/kernel/cpu/perf_event_amd_uncore.c
@@ -0,0 +1,547 @@
+/*
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ *
+ * Author: Jacob Shin <jacob.shin@amd.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/perf_event.h>
+#include <linux/percpu.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/cpu.h>
+#include <linux/cpumask.h>
+
+#include <asm/cpufeature.h>
+#include <asm/perf_event.h>
+#include <asm/msr.h>
+
+#define NUM_COUNTERS_NB         4
+#define NUM_COUNTERS_L2         4
+#define MAX_COUNTERS            NUM_COUNTERS_NB
+
+#define RDPMC_BASE_NB           6
+#define RDPMC_BASE_L2           10
+
+#define COUNTER_SHIFT           16
+
+struct amd_uncore {
+        int id;
+        int refcnt;
+        int cpu;
+        int num_counters;
+        int rdpmc_base;
+        u32 msr_base;
+        cpumask_t *active_mask;
+        struct pmu *pmu;
+        struct perf_event *events[MAX_COUNTERS];
+        struct amd_uncore *free_when_cpu_online;
+};
+
+static struct amd_uncore * __percpu *amd_uncore_nb;
+static struct amd_uncore * __percpu *amd_uncore_l2;
+
+static struct pmu amd_nb_pmu;
+static struct pmu amd_l2_pmu;
+
+static cpumask_t amd_nb_active_mask;
+static cpumask_t amd_l2_active_mask;
+
+static bool is_nb_event(struct perf_event *event)
+{
+        return event->pmu->type == amd_nb_pmu.type;
+}
+
+static bool is_l2_event(struct perf_event *event)
+{
+        return event->pmu->type == amd_l2_pmu.type;
+}
+
+static struct amd_uncore *event_to_amd_uncore(struct perf_event *event)
+{
+        if (is_nb_event(event) && amd_uncore_nb)
+                return *per_cpu_ptr(amd_uncore_nb, event->cpu);
+        else if (is_l2_event(event) && amd_uncore_l2)
+                return *per_cpu_ptr(amd_uncore_l2, event->cpu);
+
+        return NULL;
+}
+
+static void amd_uncore_read(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        u64 prev, new;
+        s64 delta;
+
+        /*
+         * since we do not enable counter overflow interrupts,
+         * we do not have to worry about prev_count changing on us
+         */
+
+        prev = local64_read(&hwc->prev_count);
+        rdpmcl(hwc->event_base_rdpmc, new);
+        local64_set(&hwc->prev_count, new);
+        delta = (new << COUNTER_SHIFT) - (prev << COUNTER_SHIFT);
+        delta >>= COUNTER_SHIFT;
+        local64_add(delta, &event->count);
+}
+
+static void amd_uncore_start(struct perf_event *event, int flags)
+{
+        struct hw_perf_event *hwc = &event->hw;
+
+        if (flags & PERF_EF_RELOAD)
+                wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count));
+
+        hwc->state = 0;
+        wrmsrl(hwc->config_base, (hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE));
+        perf_event_update_userpage(event);
+}
+
+static void amd_uncore_stop(struct perf_event *event, int flags)
+{
+        struct hw_perf_event *hwc = &event->hw;
+
+        wrmsrl(hwc->config_base, hwc->config);
+        hwc->state |= PERF_HES_STOPPED;
+
+        if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
+                amd_uncore_read(event);
+                hwc->state |= PERF_HES_UPTODATE;
+        }
+}
+
+static int amd_uncore_add(struct perf_event *event, int flags)
+{
+        int i;
+        struct amd_uncore *uncore = event_to_amd_uncore(event);
+        struct hw_perf_event *hwc = &event->hw;
+
+        /* are we already assigned? */
+        if (hwc->idx != -1 && uncore->events[hwc->idx] == event)
+                goto out;
+
+        for (i = 0; i < uncore->num_counters; i++) {
+                if (uncore->events[i] == event) {
+                        hwc->idx = i;
+                        goto out;
+                }
+        }
+
+        /* if not, take the first available counter */
+        hwc->idx = -1;
+        for (i = 0; i < uncore->num_counters; i++) {
+                if (cmpxchg(&uncore->events[i], NULL, event) == NULL) {
+                        hwc->idx = i;
+                        break;
+                }
+        }
+
+out:
+        if (hwc->idx == -1)
+                return -EBUSY;
+
+        hwc->config_base = uncore->msr_base + (2 * hwc->idx);
+        hwc->event_base = uncore->msr_base + 1 + (2 * hwc->idx);
+        hwc->event_base_rdpmc = uncore->rdpmc_base + hwc->idx;
+        hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
+
+        if (flags & PERF_EF_START)
+                amd_uncore_start(event, PERF_EF_RELOAD);
+
+        return 0;
+}
+
+static void amd_uncore_del(struct perf_event *event, int flags)
+{
+        int i;
+        struct amd_uncore *uncore = event_to_amd_uncore(event);
+        struct hw_perf_event *hwc = &event->hw;
+
+        amd_uncore_stop(event, PERF_EF_UPDATE);
+
+        for (i = 0; i < uncore->num_counters; i++) {
+                if (cmpxchg(&uncore->events[i], event, NULL) == event)
+                        break;
+        }
+
+        hwc->idx = -1;
+}
+
+static int amd_uncore_event_init(struct perf_event *event)
+{
+        struct amd_uncore *uncore;
+        struct hw_perf_event *hwc = &event->hw;
+
+        if (event->attr.type != event->pmu->type)
+                return -ENOENT;
+
+        /*
+         * NB and L2 counters (MSRs) are shared across all cores that share the
+         * same NB / L2 cache. Interrupts can be directed to a single target
+         * core, however, event counts generated by processes running on other
+         * cores cannot be masked out. So we do not support sampling and
+         * per-thread events.
+         */
+        if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
+                return -EINVAL;
+
+        /* NB and L2 counters do not have usr/os/guest/host bits */
+        if (event->attr.exclude_user || event->attr.exclude_kernel ||
+            event->attr.exclude_host || event->attr.exclude_guest)
+                return -EINVAL;
+
+        /* and we do not enable counter overflow interrupts */
+        hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB;
+        hwc->idx = -1;
+
+        if (event->cpu < 0)
+                return -EINVAL;
+
+        uncore = event_to_amd_uncore(event);
+        if (!uncore)
+                return -ENODEV;
+
+        /*
+         * since request can come in to any of the shared cores, we will remap
+         * to a single common cpu.
+         */
+        event->cpu = uncore->cpu;
+
+        return 0;
+}
+
+static ssize_t amd_uncore_attr_show_cpumask(struct device *dev,
+                                            struct device_attribute *attr,
+                                            char *buf)
+{
+        int n;
+        cpumask_t *active_mask;
+        struct pmu *pmu = dev_get_drvdata(dev);
+
+        if (pmu->type == amd_nb_pmu.type)
+                active_mask = &amd_nb_active_mask;
+        else if (pmu->type == amd_l2_pmu.type)
+                active_mask = &amd_l2_active_mask;
+        else
+                return 0;
+
+        n = cpulist_scnprintf(buf, PAGE_SIZE - 2, active_mask);
+        buf[n++] = '\n';
+        buf[n] = '\0';
+        return n;
+}
+static DEVICE_ATTR(cpumask, S_IRUGO, amd_uncore_attr_show_cpumask, NULL);
+
+static struct attribute *amd_uncore_attrs[] = {
+        &dev_attr_cpumask.attr,
+        NULL,
+};
+
+static struct attribute_group amd_uncore_attr_group = {
+        .attrs = amd_uncore_attrs,
+};
+
+PMU_FORMAT_ATTR(event, "config:0-7,32-35");
+PMU_FORMAT_ATTR(umask, "config:8-15");
+
+static struct attribute *amd_uncore_format_attr[] = {
+        &format_attr_event.attr,
+        &format_attr_umask.attr,
+        NULL,
+};
+
+static struct attribute_group amd_uncore_format_group = {
+        .name = "format",
+        .attrs = amd_uncore_format_attr,
+};
+
+static const struct attribute_group *amd_uncore_attr_groups[] = {
+        &amd_uncore_attr_group,
+        &amd_uncore_format_group,
+        NULL,
+};
+
+static struct pmu amd_nb_pmu = {
+        .attr_groups    = amd_uncore_attr_groups,
+        .name           = "amd_nb",
+        .event_init     = amd_uncore_event_init,
+        .add            = amd_uncore_add,
+        .del            = amd_uncore_del,
+        .start          = amd_uncore_start,
+        .stop           = amd_uncore_stop,
+        .read           = amd_uncore_read,
+};
+
+static struct pmu amd_l2_pmu = {
+        .attr_groups    = amd_uncore_attr_groups,
+        .name           = "amd_l2",
+        .event_init     = amd_uncore_event_init,
+        .add            = amd_uncore_add,
+        .del            = amd_uncore_del,
+        .start          = amd_uncore_start,
+        .stop           = amd_uncore_stop,
+        .read           = amd_uncore_read,
+};
+
+static struct amd_uncore * __cpuinit amd_uncore_alloc(unsigned int cpu)
+{
+        return kzalloc_node(sizeof(struct amd_uncore), GFP_KERNEL,
+                        cpu_to_node(cpu));
+}
+
+static void __cpuinit amd_uncore_cpu_up_prepare(unsigned int cpu)
+{
+        struct amd_uncore *uncore;
+
+        if (amd_uncore_nb) {
+                uncore = amd_uncore_alloc(cpu);
+                uncore->cpu = cpu;
+                uncore->num_counters = NUM_COUNTERS_NB;
+                uncore->rdpmc_base = RDPMC_BASE_NB;
+                uncore->msr_base = MSR_F15H_NB_PERF_CTL;
+                uncore->active_mask = &amd_nb_active_mask;
+                uncore->pmu = &amd_nb_pmu;
+                *per_cpu_ptr(amd_uncore_nb, cpu) = uncore;
+        }
+
+        if (amd_uncore_l2) {
+                uncore = amd_uncore_alloc(cpu);
+                uncore->cpu = cpu;
+                uncore->num_counters = NUM_COUNTERS_L2;
+                uncore->rdpmc_base = RDPMC_BASE_L2;
+                uncore->msr_base = MSR_F16H_L2I_PERF_CTL;
+                uncore->active_mask = &amd_l2_active_mask;
+                uncore->pmu = &amd_l2_pmu;
+                *per_cpu_ptr(amd_uncore_l2, cpu) = uncore;
+        }
+}
+
+static struct amd_uncore *
+__cpuinit amd_uncore_find_online_sibling(struct amd_uncore *this,
+                                         struct amd_uncore * __percpu *uncores)
+{
+        unsigned int cpu;
+        struct amd_uncore *that;
+
+        for_each_online_cpu(cpu) {
+                that = *per_cpu_ptr(uncores, cpu);
+
+                if (!that)
+                        continue;
+
+                if (this == that)
+                        continue;
+
+                if (this->id == that->id) {
+                        that->free_when_cpu_online = this;
+                        this = that;
+                        break;
+                }
+        }
+
+        this->refcnt++;
+        return this;
+}
+
+static void __cpuinit amd_uncore_cpu_starting(unsigned int cpu)
+{
+        unsigned int eax, ebx, ecx, edx;
+        struct amd_uncore *uncore;
+
+        if (amd_uncore_nb) {
+                uncore = *per_cpu_ptr(amd_uncore_nb, cpu);
+                cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
+                uncore->id = ecx & 0xff;
+
+                uncore = amd_uncore_find_online_sibling(uncore, amd_uncore_nb);
+                *per_cpu_ptr(amd_uncore_nb, cpu) = uncore;
+        }
+
+        if (amd_uncore_l2) {
+                unsigned int apicid = cpu_data(cpu).apicid;
+                unsigned int nshared;
+
+                uncore = *per_cpu_ptr(amd_uncore_l2, cpu);
+                cpuid_count(0x8000001d, 2, &eax, &ebx, &ecx, &edx);
+                nshared = ((eax >> 14) & 0xfff) + 1;
+                uncore->id = apicid - (apicid % nshared);
+
+                uncore = amd_uncore_find_online_sibling(uncore, amd_uncore_l2);
+                *per_cpu_ptr(amd_uncore_l2, cpu) = uncore;
+        }
+}
+
+static void __cpuinit uncore_online(unsigned int cpu,
+                                    struct amd_uncore * __percpu *uncores)
+{
+        struct amd_uncore *uncore = *per_cpu_ptr(uncores, cpu);
+
+        kfree(uncore->free_when_cpu_online);
+        uncore->free_when_cpu_online = NULL;
+
+        if (cpu == uncore->cpu)
+                cpumask_set_cpu(cpu, uncore->active_mask);
+}
+
+static void __cpuinit amd_uncore_cpu_online(unsigned int cpu)
+{
+        if (amd_uncore_nb)
+                uncore_online(cpu, amd_uncore_nb);
+
+        if (amd_uncore_l2)
+                uncore_online(cpu, amd_uncore_l2);
+}
+
+static void __cpuinit uncore_down_prepare(unsigned int cpu,
+                                          struct amd_uncore * __percpu *uncores)
+{
+        unsigned int i;
+        struct amd_uncore *this = *per_cpu_ptr(uncores, cpu);
+
+        if (this->cpu != cpu)
+                return;
+
+        /* this cpu is going down, migrate to a shared sibling if possible */
+        for_each_online_cpu(i) {
+                struct amd_uncore *that = *per_cpu_ptr(uncores, i);
+
+                if (cpu == i)
+                        continue;
+
+                if (this == that) {
+                        perf_pmu_migrate_context(this->pmu, cpu, i);
+                        cpumask_clear_cpu(cpu, that->active_mask);
+                        cpumask_set_cpu(i, that->active_mask);
+                        that->cpu = i;
+                        break;
+                }
+        }
+}
+
+static void __cpuinit amd_uncore_cpu_down_prepare(unsigned int cpu)
+{
+        if (amd_uncore_nb)
+                uncore_down_prepare(cpu, amd_uncore_nb);
+
+        if (amd_uncore_l2)
+                uncore_down_prepare(cpu, amd_uncore_l2);
+}
+
+static void __cpuinit uncore_dead(unsigned int cpu,
+                                  struct amd_uncore * __percpu *uncores)
+{
+        struct amd_uncore *uncore = *per_cpu_ptr(uncores, cpu);
+
+        if (cpu == uncore->cpu)
+                cpumask_clear_cpu(cpu, uncore->active_mask);
+
+        if (!--uncore->refcnt)
+                kfree(uncore);
+        *per_cpu_ptr(amd_uncore_nb, cpu) = NULL;
+}
+
+static void __cpuinit amd_uncore_cpu_dead(unsigned int cpu)
+{
+        if (amd_uncore_nb)
+                uncore_dead(cpu, amd_uncore_nb);
+
+        if (amd_uncore_l2)
+                uncore_dead(cpu, amd_uncore_l2);
+}
+
+static int __cpuinit
+amd_uncore_cpu_notifier(struct notifier_block *self, unsigned long action,
+                        void *hcpu)
+{
+        unsigned int cpu = (long)hcpu;
+
+        switch (action & ~CPU_TASKS_FROZEN) {
+        case CPU_UP_PREPARE:
+                amd_uncore_cpu_up_prepare(cpu);
+                break;
+
+        case CPU_STARTING:
+                amd_uncore_cpu_starting(cpu);
+                break;
+
+        case CPU_ONLINE:
+                amd_uncore_cpu_online(cpu);
+                break;
+
+        case CPU_DOWN_PREPARE:
+                amd_uncore_cpu_down_prepare(cpu);
+                break;
+
+        case CPU_UP_CANCELED:
+        case CPU_DEAD:
+                amd_uncore_cpu_dead(cpu);
+                break;
+
+        default:
+                break;
+        }
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block amd_uncore_cpu_notifier_block __cpuinitdata = {
+        .notifier_call  = amd_uncore_cpu_notifier,
+        .priority       = CPU_PRI_PERF + 1,
+};
+
+static void __init init_cpu_already_online(void *dummy)
+{
+        unsigned int cpu = smp_processor_id();
+
+        amd_uncore_cpu_starting(cpu);
+        amd_uncore_cpu_online(cpu);
+}
+
+static int __init amd_uncore_init(void)
+{
+        unsigned int cpu;
+        int ret = -ENODEV;
+
+        if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
+                return -ENODEV;
+
+        if (!cpu_has_topoext)
+                return -ENODEV;
+
+        if (cpu_has_perfctr_nb) {
+                amd_uncore_nb = alloc_percpu(struct amd_uncore *);
+                perf_pmu_register(&amd_nb_pmu, amd_nb_pmu.name, -1);
+
+                printk(KERN_INFO "perf: AMD NB counters detected\n");
+                ret = 0;
+        }
+
+        if (cpu_has_perfctr_l2) {
+                amd_uncore_l2 = alloc_percpu(struct amd_uncore *);
+                perf_pmu_register(&amd_l2_pmu, amd_l2_pmu.name, -1);
+
+                printk(KERN_INFO "perf: AMD L2I counters detected\n");
+                ret = 0;
+        }
+
+        if (ret)
+                return -ENODEV;
+
+        get_online_cpus();
+        /* init cpus already online before registering for hotplug notifier */
+        for_each_online_cpu(cpu) {
+                amd_uncore_cpu_up_prepare(cpu);
+                smp_call_function_single(cpu, init_cpu_already_online, NULL, 1);
+        }
+
+        register_cpu_notifier(&amd_uncore_cpu_notifier_block);
+        put_online_cpus();
+
+        return 0;
+}
+device_initcall(amd_uncore_init);
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index cc45deb791b0..f60d41ff9a97 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -81,6 +81,7 @@ static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
 {
         INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
+        INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
         EVENT_EXTRA_END
 };
 
@@ -108,6 +109,8 @@ static struct event_constraint intel_snb_event_constraints[] __read_mostly =
         INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
         INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
+        INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
+        INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
         EVENT_CONSTRAINT_END
 };
 
@@ -125,10 +128,15 @@ static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
         INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
         INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
         INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
-        INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
-        INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
-        INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
-        INTEL_EVENT_CONSTRAINT(0xd3, 0xf), /*  MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
+        /*
+         * Errata BV98 -- MEM_*_RETIRED events can leak between counters of SMT
+         * siblings; disable these events because they can corrupt unrelated
+         * counters.
+         */
+        INTEL_EVENT_CONSTRAINT(0xd0, 0x0), /* MEM_UOPS_RETIRED.* */
+        INTEL_EVENT_CONSTRAINT(0xd1, 0x0), /* MEM_LOAD_UOPS_RETIRED.* */
+        INTEL_EVENT_CONSTRAINT(0xd2, 0x0), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
+        INTEL_EVENT_CONSTRAINT(0xd3, 0x0), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
         EVENT_CONSTRAINT_END
 };
 
@@ -136,6 +144,7 @@ static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
 {
         INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
         INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
+        INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
         EVENT_EXTRA_END
 };
 
@@ -155,6 +164,8 @@ static struct event_constraint intel_gen_event_constraints[] __read_mostly =
 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
         INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
         INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
+        INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
+        INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
         EVENT_EXTRA_END
 };
 
@@ -164,6 +175,21 @@ static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
         EVENT_EXTRA_END
 };
 
+EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
+EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
+EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
+
+struct attribute *nhm_events_attrs[] = {
+        EVENT_PTR(mem_ld_nhm),
+        NULL,
+};
+
+struct attribute *snb_events_attrs[] = {
+        EVENT_PTR(mem_ld_snb),
+        EVENT_PTR(mem_st_snb),
+        NULL,
+};
+
 static u64 intel_pmu_event_map(int hw_event)
 {
         return intel_perfmon_event_map[hw_event];
@@ -1398,8 +1424,11 @@ x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
 
         if (x86_pmu.event_constraints) {
                 for_each_event_constraint(c, x86_pmu.event_constraints) {
-                        if ((event->hw.config & c->cmask) == c->code)
+                        if ((event->hw.config & c->cmask) == c->code) {
+                                /* hw.flags zeroed at initialization */
+                                event->hw.flags |= c->flags;
                                 return c;
+                        }
                 }
         }
 
@@ -1444,6 +1473,7 @@ intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
                                         struct perf_event *event)
 {
+        event->hw.flags = 0;
         intel_put_shared_regs_event_constraints(cpuc, event);
 }
 
@@ -1767,6 +1797,8 @@ static void intel_pmu_flush_branch_stack(void)
 
 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
 
+PMU_FORMAT_ATTR(ldlat, "config1:0-15");
+
 static struct attribute *intel_arch3_formats_attr[] = {
         &format_attr_event.attr,
         &format_attr_umask.attr,
@@ -1777,6 +1809,7 @@ static struct attribute *intel_arch3_formats_attr[] = {
         &format_attr_cmask.attr,
 
         &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
+        &format_attr_ldlat.attr, /* PEBS load latency */
         NULL,
 };
 
@@ -2037,6 +2070,8 @@ __init int intel_pmu_init(void)
                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
                 x86_pmu.extra_regs = intel_nehalem_extra_regs;
 
+                x86_pmu.cpu_events = nhm_events_attrs;
+
                 /* UOPS_ISSUED.STALLED_CYCLES */
                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
@@ -2080,6 +2115,8 @@ __init int intel_pmu_init(void)
                 x86_pmu.extra_regs = intel_westmere_extra_regs;
                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
 
+                x86_pmu.cpu_events = nhm_events_attrs;
+
                 /* UOPS_ISSUED.STALLED_CYCLES */
                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
@@ -2111,6 +2148,8 @@ __init int intel_pmu_init(void)
                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
                 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
 
+                x86_pmu.cpu_events = snb_events_attrs;
+
                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
@@ -2140,6 +2179,8 @@ __init int intel_pmu_init(void)
                 x86_pmu.er_flags |= ERF_HAS_RSP_1;
                 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
 
+                x86_pmu.cpu_events = snb_events_attrs;
+
                 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
                 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
                         X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 26830f3af0df..60250f687052 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -24,6 +24,130 @@ struct pebs_record_32 {
 
  */
 
+union intel_x86_pebs_dse {
+        u64 val;
+        struct {
+                unsigned int ld_dse:4;
+                unsigned int ld_stlb_miss:1;
+                unsigned int ld_locked:1;
+                unsigned int ld_reserved:26;
+        };
+        struct {
+                unsigned int st_l1d_hit:1;
+                unsigned int st_reserved1:3;
+                unsigned int st_stlb_miss:1;
+                unsigned int st_locked:1;
+                unsigned int st_reserved2:26;
+        };
+};
+
+
+/*
+ * Map PEBS Load Latency Data Source encodings to generic
+ * memory data source information
+ */
+#define P(a, b) PERF_MEM_S(a, b)
+#define OP_LH (P(OP, LOAD) | P(LVL, HIT))
+#define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
+
+static const u64 pebs_data_source[] = {
+        P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
+        OP_LH | P(LVL, L1)  | P(SNOOP, NONE),   /* 0x01: L1 local */
+        OP_LH | P(LVL, LFB) | P(SNOOP, NONE),   /* 0x02: LFB hit */
+        OP_LH | P(LVL, L2)  | P(SNOOP, NONE),   /* 0x03: L2 hit */
+        OP_LH | P(LVL, L3)  | P(SNOOP, NONE),   /* 0x04: L3 hit */
+        OP_LH | P(LVL, L3)  | P(SNOOP, MISS),   /* 0x05: L3 hit, snoop miss */
+        OP_LH | P(LVL, L3)  | P(SNOOP, HIT),    /* 0x06: L3 hit, snoop hit */
+        OP_LH | P(LVL, L3)  | P(SNOOP, HITM),   /* 0x07: L3 hit, snoop hitm */
+        OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
+        OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
+        OP_LH | P(LVL, LOC_RAM)  | P(SNOOP, HIT),  /* 0x0a: L3 miss, shared */
+        OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT),  /* 0x0b: L3 miss, shared */
+        OP_LH | P(LVL, LOC_RAM)  | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
+        OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
+        OP_LH | P(LVL, IO)  | P(SNOOP, NONE), /* 0x0e: I/O */
+        OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
+};
+
+static u64 precise_store_data(u64 status)
+{
+        union intel_x86_pebs_dse dse;
+        u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
+
+        dse.val = status;
+
+        /*
+         * bit 4: TLB access
+         * 1 = stored missed 2nd level TLB
+         *
+         * so it either hit the walker or the OS
+         * otherwise hit 2nd level TLB
+         */
+        if (dse.st_stlb_miss)
+                val |= P(TLB, MISS);
+        else
+                val |= P(TLB, HIT);
+
+        /*
+         * bit 0: hit L1 data cache
+         * if not set, then all we know is that
+         * it missed L1D
+         */
+        if (dse.st_l1d_hit)
+                val |= P(LVL, HIT);
+        else
+                val |= P(LVL, MISS);
+
+        /*
+         * bit 5: Locked prefix
+         */
+        if (dse.st_locked)
+                val |= P(LOCK, LOCKED);
+
+        return val;
+}
+
+static u64 load_latency_data(u64 status)
+{
+        union intel_x86_pebs_dse dse;
+        u64 val;
+        int model = boot_cpu_data.x86_model;
+        int fam = boot_cpu_data.x86;
+
+        dse.val = status;
+
+        /*
+         * use the mapping table for bit 0-3
+         */
+        val = pebs_data_source[dse.ld_dse];
+
+        /*
+         * Nehalem models do not support TLB, Lock infos
+         */
+        if (fam == 0x6 && (model == 26 || model == 30
+            || model == 31 || model == 46)) {
+                val |= P(TLB, NA) | P(LOCK, NA);
+                return val;
+        }
+        /*
+         * bit 4: TLB access
+         * 0 = did not miss 2nd level TLB
+         * 1 = missed 2nd level TLB
+         */
+        if (dse.ld_stlb_miss)
+                val |= P(TLB, MISS) | P(TLB, L2);
+        else
+                val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
+
+        /*
+         * bit 5: locked prefix
+         */
+        if (dse.ld_locked)
+                val |= P(LOCK, LOCKED);
+
+        return val;
+}
+
 struct pebs_record_core {
         u64 flags, ip;
         u64 ax, bx, cx, dx;
@@ -365,7 +489,7 @@ struct event_constraint intel_atom_pebs_event_constraints[] = {
 };
 
 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
-        INTEL_EVENT_CONSTRAINT(0x0b, 0xf),    /* MEM_INST_RETIRED.* */
+        INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
         INTEL_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
         INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
         INTEL_EVENT_CONSTRAINT(0xc0, 0xf),    /* INST_RETIRED.ANY */
@@ -380,7 +504,7 @@ struct event_constraint intel_nehalem_pebs_event_constraints[] = {
 };
 
 struct event_constraint intel_westmere_pebs_event_constraints[] = {
-        INTEL_EVENT_CONSTRAINT(0x0b, 0xf),    /* MEM_INST_RETIRED.* */
+        INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
         INTEL_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
         INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
         INTEL_EVENT_CONSTRAINT(0xc0, 0xf),    /* INSTR_RETIRED.* */
@@ -400,7 +524,8 @@ struct event_constraint intel_snb_pebs_event_constraints[] = {
         INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
         INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
-        INTEL_EVENT_CONSTRAINT(0xcd, 0x8),    /* MEM_TRANS_RETIRED.* */
+        INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
+        INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
@@ -414,7 +539,8 @@ struct event_constraint intel_ivb_pebs_event_constraints[] = {
         INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
         INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
         INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
-        INTEL_EVENT_CONSTRAINT(0xcd, 0x8),    /* MEM_TRANS_RETIRED.* */
+        INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
+        INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
         INTEL_EVENT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
         INTEL_EVENT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
         INTEL_EVENT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
@@ -431,8 +557,10 @@ struct event_constraint *intel_pebs_constraints(struct perf_event *event)
 
         if (x86_pmu.pebs_constraints) {
                 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
-                        if ((event->hw.config & c->cmask) == c->code)
+                        if ((event->hw.config & c->cmask) == c->code) {
+                                event->hw.flags |= c->flags;
                                 return c;
+                        }
                 }
         }
 
@@ -447,6 +575,11 @@ void intel_pmu_pebs_enable(struct perf_event *event)
         hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
 
         cpuc->pebs_enabled |= 1ULL << hwc->idx;
+
+        if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
+                cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
+        else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
+                cpuc->pebs_enabled |= 1ULL << 63;
 }
 
 void intel_pmu_pebs_disable(struct perf_event *event)
@@ -559,20 +692,51 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
                                    struct pt_regs *iregs, void *__pebs)
 {
         /*
-         * We cast to pebs_record_core since that is a subset of
-         * both formats and we don't use the other fields in this
-         * routine.
+         * We cast to pebs_record_nhm to get the load latency data
+         * if extra_reg MSR_PEBS_LD_LAT_THRESHOLD used
          */
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-        struct pebs_record_core *pebs = __pebs;
+        struct pebs_record_nhm *pebs = __pebs;
         struct perf_sample_data data;
         struct pt_regs regs;
+        u64 sample_type;
+        int fll, fst;
 
         if (!intel_pmu_save_and_restart(event))
                 return;
 
+        fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
+        fst = event->hw.flags & PERF_X86_EVENT_PEBS_ST;
+
         perf_sample_data_init(&data, 0, event->hw.last_period);
 
+        data.period = event->hw.last_period;
+        sample_type = event->attr.sample_type;
+
+        /*
+         * if PEBS-LL or PreciseStore
+         */
+        if (fll || fst) {
+                if (sample_type & PERF_SAMPLE_ADDR)
+                        data.addr = pebs->dla;
+
+                /*
+                 * Use latency for weight (only avail with PEBS-LL)
+                 */
+                if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
+                        data.weight = pebs->lat;
+
+                /*
+                 * data.data_src encodes the data source
+                 */
+                if (sample_type & PERF_SAMPLE_DATA_SRC) {
+                        if (fll)
+                                data.data_src.val = load_latency_data(pebs->dse);
+                        else
+                                data.data_src.val = precise_store_data(pebs->dse);
+                }
+        }
+
         /*
          * We use the interrupt regs as a base because the PEBS record
          * does not contain a full regs set, specifically it seems to
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index da02e9cc3754..d978353c939b 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -310,7 +310,7 @@ void intel_pmu_lbr_read(void)
  * - in case there is no HW filter
  * - in case the HW filter has errata or limitations
  */
-static void intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
+static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
 {
         u64 br_type = event->attr.branch_sample_type;
         int mask = 0;
@@ -318,8 +318,11 @@ static void intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
         if (br_type & PERF_SAMPLE_BRANCH_USER)
                 mask |= X86_BR_USER;
 
-        if (br_type & PERF_SAMPLE_BRANCH_KERNEL)
+        if (br_type & PERF_SAMPLE_BRANCH_KERNEL) {
+                if (perf_paranoid_kernel() && !capable(CAP_SYS_ADMIN))
+                        return -EACCES;
                 mask |= X86_BR_KERNEL;
+        }
 
         /* we ignore BRANCH_HV here */
 
@@ -339,6 +342,8 @@ static void intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
          * be used by fixup code for some CPU
          */
         event->hw.branch_reg.reg = mask;
+
+        return 0;
 }
 
 /*
@@ -386,7 +391,9 @@ int intel_pmu_setup_lbr_filter(struct perf_event *event)
         /*
          * setup SW LBR filter
          */
-        intel_pmu_setup_sw_lbr_filter(event);
+        ret = intel_pmu_setup_sw_lbr_filter(event);
+        if (ret)
+                return ret;
 
         /*
          * setup HW LBR filter, if any
@@ -442,8 +449,18 @@ static int branch_type(unsigned long from, unsigned long to)
                         return X86_BR_NONE;
 
                 addr = buf;
-        } else
-                addr = (void *)from;
+        } else {
+                /*
+                 * The LBR logs any address in the IP, even if the IP just
+                 * faulted. This means userspace can control the from address.
+                 * Ensure we don't blindy read any address by validating it is
+                 * a known text address.
+                 */
+                if (kernel_text_address(from))
+                        addr = (void *)from;
+                else
+                        return X86_BR_NONE;
+        }
 
         /*
          * decoder needs to know the ABI especially
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
index b43200dbfe7e..52441a2af538 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
@@ -17,6 +17,9 @@ static struct event_constraint constraint_fixed =
 static struct event_constraint constraint_empty =
         EVENT_CONSTRAINT(0, 0, 0);
 
+#define __BITS_VALUE(x, i, n)  ((typeof(x))(((x) >> ((i) * (n))) & \
+                                ((1ULL << (n)) - 1)))
+
 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
 DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21");
 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
@@ -31,9 +34,13 @@ DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
 DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
 DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
 DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4");
+DEFINE_UNCORE_FORMAT_ATTR(filter_link, filter_link, "config1:5-8");
 DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17");
+DEFINE_UNCORE_FORMAT_ATTR(filter_nid2, filter_nid, "config1:32-47");
 DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22");
+DEFINE_UNCORE_FORMAT_ATTR(filter_state2, filter_state, "config1:17-22");
 DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31");
+DEFINE_UNCORE_FORMAT_ATTR(filter_opc2, filter_opc, "config1:52-60");
 DEFINE_UNCORE_FORMAT_ATTR(filter_band0, filter_band0, "config1:0-7");
 DEFINE_UNCORE_FORMAT_ATTR(filter_band1, filter_band1, "config1:8-15");
 DEFINE_UNCORE_FORMAT_ATTR(filter_band2, filter_band2, "config1:16-23");
@@ -110,6 +117,21 @@ static void uncore_put_constraint(struct intel_uncore_box *box, struct perf_even
         reg1->alloc = 0;
 }
 
+static u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx)
+{
+        struct intel_uncore_extra_reg *er;
+        unsigned long flags;
+        u64 config;
+
+        er = &box->shared_regs[idx];
+
+        raw_spin_lock_irqsave(&er->lock, flags);
+        config = er->config;
+        raw_spin_unlock_irqrestore(&er->lock, flags);
+
+        return config;
+}
+
 /* Sandy Bridge-EP uncore support */
 static struct intel_uncore_type snbep_uncore_cbox;
 static struct intel_uncore_type snbep_uncore_pcu;
@@ -205,7 +227,7 @@ static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box, struct p
         struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
 
         if (reg1->idx != EXTRA_REG_NONE)
-                wrmsrl(reg1->reg, reg1->config);
+                wrmsrl(reg1->reg, uncore_shared_reg_config(box, 0));
 
         wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
 }
@@ -226,29 +248,6 @@ static void snbep_uncore_msr_init_box(struct intel_uncore_box *box)
                 wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT);
 }
 
-static int snbep_uncore_hw_config(struct intel_uncore_box *box, struct perf_event *event)
-{
-        struct hw_perf_event *hwc = &event->hw;
-        struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
-
-        if (box->pmu->type == &snbep_uncore_cbox) {
-                reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER +
-                        SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
-                reg1->config = event->attr.config1 &
-                        SNBEP_CB0_MSR_PMON_BOX_FILTER_MASK;
-        } else {
-                if (box->pmu->type == &snbep_uncore_pcu) {
-                        reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER;
-                        reg1->config = event->attr.config1 & SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK;
-                } else {
-                        return 0;
-                }
-        }
-        reg1->idx = 0;
-
-        return 0;
-}
-
 static struct attribute *snbep_uncore_formats_attr[] = {
         &format_attr_event.attr,
         &format_attr_umask.attr,
@@ -345,16 +344,16 @@ static struct attribute_group snbep_uncore_qpi_format_group = {
         .attrs = snbep_uncore_qpi_formats_attr,
 };
 
+#define SNBEP_UNCORE_MSR_OPS_COMMON_INIT()                      \
+        .init_box       = snbep_uncore_msr_init_box,            \
+        .disable_box    = snbep_uncore_msr_disable_box,         \
+        .enable_box     = snbep_uncore_msr_enable_box,          \
+        .disable_event  = snbep_uncore_msr_disable_event,       \
+        .enable_event   = snbep_uncore_msr_enable_event,        \
+        .read_counter   = uncore_msr_read_counter
+
 static struct intel_uncore_ops snbep_uncore_msr_ops = {
-        .init_box       = snbep_uncore_msr_init_box,
-        .disable_box    = snbep_uncore_msr_disable_box,
-        .enable_box     = snbep_uncore_msr_enable_box,
-        .disable_event  = snbep_uncore_msr_disable_event,
-        .enable_event   = snbep_uncore_msr_enable_event,
-        .read_counter   = uncore_msr_read_counter,
-        .get_constraint = uncore_get_constraint,
-        .put_constraint = uncore_put_constraint,
-        .hw_config      = snbep_uncore_hw_config,
+        SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
 };
 
 static struct intel_uncore_ops snbep_uncore_pci_ops = {
@@ -372,6 +371,7 @@ static struct event_constraint snbep_uncore_cbox_constraints[] = {
         UNCORE_EVENT_CONSTRAINT(0x04, 0x3),
         UNCORE_EVENT_CONSTRAINT(0x05, 0x3),
         UNCORE_EVENT_CONSTRAINT(0x07, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x09, 0x3),
         UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
         UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
         UNCORE_EVENT_CONSTRAINT(0x13, 0x3),
@@ -421,6 +421,14 @@ static struct event_constraint snbep_uncore_r3qpi_constraints[] = {
         UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
         UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
         UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x2a, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x2b, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x2e, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x2f, 0x3),
         UNCORE_EVENT_CONSTRAINT(0x30, 0x3),
         UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
         UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
@@ -428,6 +436,8 @@ static struct event_constraint snbep_uncore_r3qpi_constraints[] = {
         UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
         UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
         UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
         EVENT_CONSTRAINT_END
 };
 
@@ -446,6 +456,145 @@ static struct intel_uncore_type snbep_uncore_ubox = {
         .format_group   = &snbep_uncore_ubox_format_group,
 };
 
+static struct extra_reg snbep_uncore_cbox_extra_regs[] = {
+        SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
+                                  SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x6),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x8),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x8),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0xc),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0xc),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x2),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x2),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x2),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x2),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x8),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x8),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0xc),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0xc),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x2),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x2),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x2),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x2),
+        EVENT_EXTRA_END
+};
+
+static void snbep_cbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
+        struct intel_uncore_extra_reg *er = &box->shared_regs[0];
+        int i;
+
+        if (uncore_box_is_fake(box))
+                return;
+
+        for (i = 0; i < 5; i++) {
+                if (reg1->alloc & (0x1 << i))
+                        atomic_sub(1 << (i * 6), &er->ref);
+        }
+        reg1->alloc = 0;
+}
+
+static struct event_constraint *
+__snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event,
+                            u64 (*cbox_filter_mask)(int fields))
+{
+        struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
+        struct intel_uncore_extra_reg *er = &box->shared_regs[0];
+        int i, alloc = 0;
+        unsigned long flags;
+        u64 mask;
+
+        if (reg1->idx == EXTRA_REG_NONE)
+                return NULL;
+
+        raw_spin_lock_irqsave(&er->lock, flags);
+        for (i = 0; i < 5; i++) {
+                if (!(reg1->idx & (0x1 << i)))
+                        continue;
+                if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i)))
+                        continue;
+
+                mask = cbox_filter_mask(0x1 << i);
+                if (!__BITS_VALUE(atomic_read(&er->ref), i, 6) ||
+                    !((reg1->config ^ er->config) & mask)) {
+                        atomic_add(1 << (i * 6), &er->ref);
+                        er->config &= ~mask;
+                        er->config |= reg1->config & mask;
+                        alloc |= (0x1 << i);
+                } else {
+                        break;
+                }
+        }
+        raw_spin_unlock_irqrestore(&er->lock, flags);
+        if (i < 5)
+                goto fail;
+
+        if (!uncore_box_is_fake(box))
+                reg1->alloc |= alloc;
+
+        return 0;
+fail:
+        for (; i >= 0; i--) {
+                if (alloc & (0x1 << i))
+                        atomic_sub(1 << (i * 6), &er->ref);
+        }
+        return &constraint_empty;
+}
+
+static u64 snbep_cbox_filter_mask(int fields)
+{
+        u64 mask = 0;
+
+        if (fields & 0x1)
+                mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_TID;
+        if (fields & 0x2)
+                mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_NID;
+        if (fields & 0x4)
+                mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE;
+        if (fields & 0x8)
+                mask |= SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC;
+
+        return mask;
+}
+
+static struct event_constraint *
+snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
+{
+        return __snbep_cbox_get_constraint(box, event, snbep_cbox_filter_mask);
+}
+
+static int snbep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
+        struct extra_reg *er;
+        int idx = 0;
+
+        for (er = snbep_uncore_cbox_extra_regs; er->msr; er++) {
+                if (er->event != (event->hw.config & er->config_mask))
+                        continue;
+                idx |= er->idx;
+        }
+
+        if (idx) {
+                reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER +
+                        SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
+                reg1->config = event->attr.config1 & snbep_cbox_filter_mask(idx);
+                reg1->idx = idx;
+        }
+        return 0;
+}
+
+static struct intel_uncore_ops snbep_uncore_cbox_ops = {
+        SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
+        .hw_config              = snbep_cbox_hw_config,
+        .get_constraint         = snbep_cbox_get_constraint,
+        .put_constraint         = snbep_cbox_put_constraint,
+};
+
 static struct intel_uncore_type snbep_uncore_cbox = {
         .name                   = "cbox",
         .num_counters           = 4,
@@ -458,10 +607,104 @@ static struct intel_uncore_type snbep_uncore_cbox = {
         .msr_offset             = SNBEP_CBO_MSR_OFFSET,
         .num_shared_regs        = 1,
         .constraints            = snbep_uncore_cbox_constraints,
-        .ops                    = &snbep_uncore_msr_ops,
+        .ops                    = &snbep_uncore_cbox_ops,
         .format_group           = &snbep_uncore_cbox_format_group,
 };
 
+static u64 snbep_pcu_alter_er(struct perf_event *event, int new_idx, bool modify)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
+        u64 config = reg1->config;
+
+        if (new_idx > reg1->idx)
+                config <<= 8 * (new_idx - reg1->idx);
+        else
+                config >>= 8 * (reg1->idx - new_idx);
+
+        if (modify) {
+                hwc->config += new_idx - reg1->idx;
+                reg1->config = config;
+                reg1->idx = new_idx;
+        }
+        return config;
+}
+
+static struct event_constraint *
+snbep_pcu_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
+        struct intel_uncore_extra_reg *er = &box->shared_regs[0];
+        unsigned long flags;
+        int idx = reg1->idx;
+        u64 mask, config1 = reg1->config;
+        bool ok = false;
+
+        if (reg1->idx == EXTRA_REG_NONE ||
+            (!uncore_box_is_fake(box) && reg1->alloc))
+                return NULL;
+again:
+        mask = 0xff << (idx * 8);
+        raw_spin_lock_irqsave(&er->lock, flags);
+        if (!__BITS_VALUE(atomic_read(&er->ref), idx, 8) ||
+            !((config1 ^ er->config) & mask)) {
+                atomic_add(1 << (idx * 8), &er->ref);
+                er->config &= ~mask;
+                er->config |= config1 & mask;
+                ok = true;
+        }
+        raw_spin_unlock_irqrestore(&er->lock, flags);
+
+        if (!ok) {
+                idx = (idx + 1) % 4;
+                if (idx != reg1->idx) {
+                        config1 = snbep_pcu_alter_er(event, idx, false);
+                        goto again;
+                }
+                return &constraint_empty;
+        }
+
+        if (!uncore_box_is_fake(box)) {
+                if (idx != reg1->idx)
+                        snbep_pcu_alter_er(event, idx, true);
+                reg1->alloc = 1;
+        }
+        return NULL;
+}
+
+static void snbep_pcu_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
+        struct intel_uncore_extra_reg *er = &box->shared_regs[0];
+
+        if (uncore_box_is_fake(box) || !reg1->alloc)
+                return;
+
+        atomic_sub(1 << (reg1->idx * 8), &er->ref);
+        reg1->alloc = 0;
+}
+
+static int snbep_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
+        int ev_sel = hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK;
+
+        if (ev_sel >= 0xb && ev_sel <= 0xe) {
+                reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER;
+                reg1->idx = ev_sel - 0xb;
+                reg1->config = event->attr.config1 & (0xff << reg1->idx);
+        }
+        return 0;
+}
+
+static struct intel_uncore_ops snbep_uncore_pcu_ops = {
+        SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
+        .hw_config              = snbep_pcu_hw_config,
+        .get_constraint         = snbep_pcu_get_constraint,
+        .put_constraint         = snbep_pcu_put_constraint,
+};
+
 static struct intel_uncore_type snbep_uncore_pcu = {
         .name                   = "pcu",
         .num_counters           = 4,
@@ -472,7 +715,7 @@ static struct intel_uncore_type snbep_uncore_pcu = {
         .event_mask             = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
         .box_ctl                = SNBEP_PCU_MSR_PMON_BOX_CTL,
         .num_shared_regs        = 1,
-        .ops                    = &snbep_uncore_msr_ops,
+        .ops                    = &snbep_uncore_pcu_ops,
         .format_group           = &snbep_uncore_pcu_format_group,
 };
 
@@ -544,55 +787,63 @@ static struct intel_uncore_type snbep_uncore_r3qpi = {
         SNBEP_UNCORE_PCI_COMMON_INIT(),
 };
 
+enum {
+        SNBEP_PCI_UNCORE_HA,
+        SNBEP_PCI_UNCORE_IMC,
+        SNBEP_PCI_UNCORE_QPI,
+        SNBEP_PCI_UNCORE_R2PCIE,
+        SNBEP_PCI_UNCORE_R3QPI,
+};
+
 static struct intel_uncore_type *snbep_pci_uncores[] = {
-        &snbep_uncore_ha,
-        &snbep_uncore_imc,
-        &snbep_uncore_qpi,
-        &snbep_uncore_r2pcie,
-        &snbep_uncore_r3qpi,
+        [SNBEP_PCI_UNCORE_HA]           = &snbep_uncore_ha,
+        [SNBEP_PCI_UNCORE_IMC]          = &snbep_uncore_imc,
+        [SNBEP_PCI_UNCORE_QPI]          = &snbep_uncore_qpi,
+        [SNBEP_PCI_UNCORE_R2PCIE]       = &snbep_uncore_r2pcie,
+        [SNBEP_PCI_UNCORE_R3QPI]        = &snbep_uncore_r3qpi,
         NULL,
 };
 
 static DEFINE_PCI_DEVICE_TABLE(snbep_uncore_pci_ids) = {
         { /* Home Agent */
                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_HA),
-                .driver_data = (unsigned long)&snbep_uncore_ha,
+                .driver_data = SNBEP_PCI_UNCORE_HA,
         },
         { /* MC Channel 0 */
                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC0),
-                .driver_data = (unsigned long)&snbep_uncore_imc,
+                .driver_data = SNBEP_PCI_UNCORE_IMC,
         },
         { /* MC Channel 1 */
                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC1),
-                .driver_data = (unsigned long)&snbep_uncore_imc,
+                .driver_data = SNBEP_PCI_UNCORE_IMC,
         },
         { /* MC Channel 2 */
                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC2),
-                .driver_data = (unsigned long)&snbep_uncore_imc,
+                .driver_data = SNBEP_PCI_UNCORE_IMC,
         },
         { /* MC Channel 3 */
                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC3),
-                .driver_data = (unsigned long)&snbep_uncore_imc,
+                .driver_data = SNBEP_PCI_UNCORE_IMC,
         },
         { /* QPI Port 0 */
                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI0),
-                .driver_data = (unsigned long)&snbep_uncore_qpi,
+                .driver_data = SNBEP_PCI_UNCORE_QPI,
         },
         { /* QPI Port 1 */
                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI1),
-                .driver_data = (unsigned long)&snbep_uncore_qpi,
+                .driver_data = SNBEP_PCI_UNCORE_QPI,
         },
-        { /* P2PCIe */
+        { /* R2PCIe */
                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R2PCIE),
-                .driver_data = (unsigned long)&snbep_uncore_r2pcie,
+                .driver_data = SNBEP_PCI_UNCORE_R2PCIE,
         },
         { /* R3QPI Link 0 */
                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI0),
-                .driver_data = (unsigned long)&snbep_uncore_r3qpi,
+                .driver_data = SNBEP_PCI_UNCORE_R3QPI,
         },
         { /* R3QPI Link 1 */
                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI1),
-                .driver_data = (unsigned long)&snbep_uncore_r3qpi,
+                .driver_data = SNBEP_PCI_UNCORE_R3QPI,
         },
         { /* end: all zeroes */ }
 };
@@ -605,7 +856,7 @@ static struct pci_driver snbep_uncore_pci_driver = {
 /*
  * build pci bus to socket mapping
  */
-static int snbep_pci2phy_map_init(void)
+static int snbep_pci2phy_map_init(int devid)
 {
         struct pci_dev *ubox_dev = NULL;
         int i, bus, nodeid;
@@ -614,9 +865,7 @@ static int snbep_pci2phy_map_init(void)
 
         while (1) {
                 /* find the UBOX device */
-                ubox_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
-                                        PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX,
-                                        ubox_dev);
+                ubox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, ubox_dev);
                 if (!ubox_dev)
                         break;
                 bus = ubox_dev->bus->number;
@@ -639,7 +888,7 @@ static int snbep_pci2phy_map_init(void)
                                 break;
                         }
                 }
-        };
+        }
 
         if (ubox_dev)
                 pci_dev_put(ubox_dev);
@@ -648,6 +897,440 @@ static int snbep_pci2phy_map_init(void)
 }
 /* end of Sandy Bridge-EP uncore support */
 
+/* IvyTown uncore support */
+static void ivt_uncore_msr_init_box(struct intel_uncore_box *box)
+{
+        unsigned msr = uncore_msr_box_ctl(box);
+        if (msr)
+                wrmsrl(msr, IVT_PMON_BOX_CTL_INT);
+}
+
+static void ivt_uncore_pci_init_box(struct intel_uncore_box *box)
+{
+        struct pci_dev *pdev = box->pci_dev;
+
+        pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL, IVT_PMON_BOX_CTL_INT);
+}
+
+#define IVT_UNCORE_MSR_OPS_COMMON_INIT()                        \
+        .init_box       = ivt_uncore_msr_init_box,              \
+        .disable_box    = snbep_uncore_msr_disable_box,         \
+        .enable_box     = snbep_uncore_msr_enable_box,          \
+        .disable_event  = snbep_uncore_msr_disable_event,       \
+        .enable_event   = snbep_uncore_msr_enable_event,        \
+        .read_counter   = uncore_msr_read_counter
+
+static struct intel_uncore_ops ivt_uncore_msr_ops = {
+        IVT_UNCORE_MSR_OPS_COMMON_INIT(),
+};
+
+static struct intel_uncore_ops ivt_uncore_pci_ops = {
+        .init_box       = ivt_uncore_pci_init_box,
+        .disable_box    = snbep_uncore_pci_disable_box,
+        .enable_box     = snbep_uncore_pci_enable_box,
+        .disable_event  = snbep_uncore_pci_disable_event,
+        .enable_event   = snbep_uncore_pci_enable_event,
+        .read_counter   = snbep_uncore_pci_read_counter,
+};
+
+#define IVT_UNCORE_PCI_COMMON_INIT()                            \
+        .perf_ctr       = SNBEP_PCI_PMON_CTR0,                  \
+        .event_ctl      = SNBEP_PCI_PMON_CTL0,                  \
+        .event_mask     = IVT_PMON_RAW_EVENT_MASK,              \
+        .box_ctl        = SNBEP_PCI_PMON_BOX_CTL,               \
+        .ops            = &ivt_uncore_pci_ops,                  \
+        .format_group   = &ivt_uncore_format_group
+
+static struct attribute *ivt_uncore_formats_attr[] = {
+        &format_attr_event.attr,
+        &format_attr_umask.attr,
+        &format_attr_edge.attr,
+        &format_attr_inv.attr,
+        &format_attr_thresh8.attr,
+        NULL,
+};
+
+static struct attribute *ivt_uncore_ubox_formats_attr[] = {
+        &format_attr_event.attr,
+        &format_attr_umask.attr,
+        &format_attr_edge.attr,
+        &format_attr_inv.attr,
+        &format_attr_thresh5.attr,
+        NULL,
+};
+
+static struct attribute *ivt_uncore_cbox_formats_attr[] = {
+        &format_attr_event.attr,
+        &format_attr_umask.attr,
+        &format_attr_edge.attr,
+        &format_attr_tid_en.attr,
+        &format_attr_thresh8.attr,
+        &format_attr_filter_tid.attr,
+        &format_attr_filter_link.attr,
+        &format_attr_filter_state2.attr,
+        &format_attr_filter_nid2.attr,
+        &format_attr_filter_opc2.attr,
+        NULL,
+};
+
+static struct attribute *ivt_uncore_pcu_formats_attr[] = {
+        &format_attr_event_ext.attr,
+        &format_attr_occ_sel.attr,
+        &format_attr_edge.attr,
+        &format_attr_thresh5.attr,
+        &format_attr_occ_invert.attr,
+        &format_attr_occ_edge.attr,
+        &format_attr_filter_band0.attr,
+        &format_attr_filter_band1.attr,
+        &format_attr_filter_band2.attr,
+        &format_attr_filter_band3.attr,
+        NULL,
+};
+
+static struct attribute *ivt_uncore_qpi_formats_attr[] = {
+        &format_attr_event_ext.attr,
+        &format_attr_umask.attr,
+        &format_attr_edge.attr,
+        &format_attr_thresh8.attr,
+        NULL,
+};
+
+static struct attribute_group ivt_uncore_format_group = {
+        .name = "format",
+        .attrs = ivt_uncore_formats_attr,
+};
+
+static struct attribute_group ivt_uncore_ubox_format_group = {
+        .name = "format",
+        .attrs = ivt_uncore_ubox_formats_attr,
+};
+
+static struct attribute_group ivt_uncore_cbox_format_group = {
+        .name = "format",
+        .attrs = ivt_uncore_cbox_formats_attr,
+};
+
+static struct attribute_group ivt_uncore_pcu_format_group = {
+        .name = "format",
+        .attrs = ivt_uncore_pcu_formats_attr,
+};
+
+static struct attribute_group ivt_uncore_qpi_format_group = {
+        .name = "format",
+        .attrs = ivt_uncore_qpi_formats_attr,
+};
+
+static struct intel_uncore_type ivt_uncore_ubox = {
+        .name           = "ubox",
+        .num_counters   = 2,
+        .num_boxes      = 1,
+        .perf_ctr_bits  = 44,
+        .fixed_ctr_bits = 48,
+        .perf_ctr       = SNBEP_U_MSR_PMON_CTR0,
+        .event_ctl      = SNBEP_U_MSR_PMON_CTL0,
+        .event_mask     = IVT_U_MSR_PMON_RAW_EVENT_MASK,
+        .fixed_ctr      = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR,
+        .fixed_ctl      = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL,
+        .ops            = &ivt_uncore_msr_ops,
+        .format_group   = &ivt_uncore_ubox_format_group,
+};
+
+static struct extra_reg ivt_uncore_cbox_extra_regs[] = {
+        SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
+                                  SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x1031, 0x10ff, 0x2),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0xc),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x10),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x2335, 0xffff, 0x10),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0x18),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0x18),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x8),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x8),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x8),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x8),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x8135, 0xffff, 0x10),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x8335, 0xffff, 0x10),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x10),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x10),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0x18),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0x18),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x8),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x8),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x8),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x5036, 0xffff, 0x8),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x8136, 0xffff, 0x10),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x8336, 0xffff, 0x10),
+        SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x8),
+        EVENT_EXTRA_END
+};
+
+static u64 ivt_cbox_filter_mask(int fields)
+{
+        u64 mask = 0;
+
+        if (fields & 0x1)
+                mask |= IVT_CB0_MSR_PMON_BOX_FILTER_TID;
+        if (fields & 0x2)
+                mask |= IVT_CB0_MSR_PMON_BOX_FILTER_LINK;
+        if (fields & 0x4)
+                mask |= IVT_CB0_MSR_PMON_BOX_FILTER_STATE;
+        if (fields & 0x8)
+                mask |= IVT_CB0_MSR_PMON_BOX_FILTER_NID;
+        if (fields & 0x10)
+                mask |= IVT_CB0_MSR_PMON_BOX_FILTER_OPC;
+
+        return mask;
+}
+
+static struct event_constraint *
+ivt_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
+{
+        return __snbep_cbox_get_constraint(box, event, ivt_cbox_filter_mask);
+}
+
+static int ivt_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
+        struct extra_reg *er;
+        int idx = 0;
+
+        for (er = ivt_uncore_cbox_extra_regs; er->msr; er++) {
+                if (er->event != (event->hw.config & er->config_mask))
+                        continue;
+                idx |= er->idx;
+        }
+
+        if (idx) {
+                reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER +
+                        SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
+                reg1->config = event->attr.config1 & ivt_cbox_filter_mask(idx);
+                reg1->idx = idx;
+        }
+        return 0;
+}
+
+static void ivt_cbox_enable_event(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
+
+        if (reg1->idx != EXTRA_REG_NONE) {
+                u64 filter = uncore_shared_reg_config(box, 0);
+                wrmsrl(reg1->reg, filter & 0xffffffff);
+                wrmsrl(reg1->reg + 6, filter >> 32);
+        }
+
+        wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
+}
+
+static struct intel_uncore_ops ivt_uncore_cbox_ops = {
+        .init_box               = ivt_uncore_msr_init_box,
+        .disable_box            = snbep_uncore_msr_disable_box,
+        .enable_box             = snbep_uncore_msr_enable_box,
+        .disable_event          = snbep_uncore_msr_disable_event,
+        .enable_event           = ivt_cbox_enable_event,
+        .read_counter           = uncore_msr_read_counter,
+        .hw_config              = ivt_cbox_hw_config,
+        .get_constraint         = ivt_cbox_get_constraint,
+        .put_constraint         = snbep_cbox_put_constraint,
+};
+
+static struct intel_uncore_type ivt_uncore_cbox = {
+        .name                   = "cbox",
+        .num_counters           = 4,
+        .num_boxes              = 15,
+        .perf_ctr_bits          = 44,
+        .event_ctl              = SNBEP_C0_MSR_PMON_CTL0,
+        .perf_ctr               = SNBEP_C0_MSR_PMON_CTR0,
+        .event_mask             = IVT_CBO_MSR_PMON_RAW_EVENT_MASK,
+        .box_ctl                = SNBEP_C0_MSR_PMON_BOX_CTL,
+        .msr_offset             = SNBEP_CBO_MSR_OFFSET,
+        .num_shared_regs        = 1,
+        .constraints            = snbep_uncore_cbox_constraints,
+        .ops                    = &ivt_uncore_cbox_ops,
+        .format_group           = &ivt_uncore_cbox_format_group,
+};
+
+static struct intel_uncore_ops ivt_uncore_pcu_ops = {
+        IVT_UNCORE_MSR_OPS_COMMON_INIT(),
+        .hw_config              = snbep_pcu_hw_config,
+        .get_constraint         = snbep_pcu_get_constraint,
+        .put_constraint         = snbep_pcu_put_constraint,
+};
+
+static struct intel_uncore_type ivt_uncore_pcu = {
+        .name                   = "pcu",
+        .num_counters           = 4,
+        .num_boxes              = 1,
+        .perf_ctr_bits          = 48,
+        .perf_ctr               = SNBEP_PCU_MSR_PMON_CTR0,
+        .event_ctl              = SNBEP_PCU_MSR_PMON_CTL0,
+        .event_mask             = IVT_PCU_MSR_PMON_RAW_EVENT_MASK,
+        .box_ctl                = SNBEP_PCU_MSR_PMON_BOX_CTL,
+        .num_shared_regs        = 1,
+        .ops                    = &ivt_uncore_pcu_ops,
+        .format_group           = &ivt_uncore_pcu_format_group,
+};
+
+static struct intel_uncore_type *ivt_msr_uncores[] = {
+        &ivt_uncore_ubox,
+        &ivt_uncore_cbox,
+        &ivt_uncore_pcu,
+        NULL,
+};
+
+static struct intel_uncore_type ivt_uncore_ha = {
+        .name           = "ha",
+        .num_counters   = 4,
+        .num_boxes      = 2,
+        .perf_ctr_bits  = 48,
+        IVT_UNCORE_PCI_COMMON_INIT(),
+};
+
+static struct intel_uncore_type ivt_uncore_imc = {
+        .name           = "imc",
+        .num_counters   = 4,
+        .num_boxes      = 8,
+        .perf_ctr_bits  = 48,
+        .fixed_ctr_bits = 48,
+        .fixed_ctr      = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
+        .fixed_ctl      = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
+        IVT_UNCORE_PCI_COMMON_INIT(),
+};
+
+static struct intel_uncore_type ivt_uncore_qpi = {
+        .name           = "qpi",
+        .num_counters   = 4,
+        .num_boxes      = 3,
+        .perf_ctr_bits  = 48,
+        .perf_ctr       = SNBEP_PCI_PMON_CTR0,
+        .event_ctl      = SNBEP_PCI_PMON_CTL0,
+        .event_mask     = IVT_QPI_PCI_PMON_RAW_EVENT_MASK,
+        .box_ctl        = SNBEP_PCI_PMON_BOX_CTL,
+        .ops            = &ivt_uncore_pci_ops,
+        .format_group   = &ivt_uncore_qpi_format_group,
+};
+
+static struct intel_uncore_type ivt_uncore_r2pcie = {
+        .name           = "r2pcie",
+        .num_counters   = 4,
+        .num_boxes      = 1,
+        .perf_ctr_bits  = 44,
+        .constraints    = snbep_uncore_r2pcie_constraints,
+        IVT_UNCORE_PCI_COMMON_INIT(),
+};
+
+static struct intel_uncore_type ivt_uncore_r3qpi = {
+        .name           = "r3qpi",
+        .num_counters   = 3,
+        .num_boxes      = 2,
+        .perf_ctr_bits  = 44,
+        .constraints    = snbep_uncore_r3qpi_constraints,
+        IVT_UNCORE_PCI_COMMON_INIT(),
+};
+
+enum {
+        IVT_PCI_UNCORE_HA,
+        IVT_PCI_UNCORE_IMC,
+        IVT_PCI_UNCORE_QPI,
+        IVT_PCI_UNCORE_R2PCIE,
+        IVT_PCI_UNCORE_R3QPI,
+};
+
+static struct intel_uncore_type *ivt_pci_uncores[] = {
+        [IVT_PCI_UNCORE_HA]     = &ivt_uncore_ha,
+        [IVT_PCI_UNCORE_IMC]    = &ivt_uncore_imc,
+        [IVT_PCI_UNCORE_QPI]    = &ivt_uncore_qpi,
+        [IVT_PCI_UNCORE_R2PCIE] = &ivt_uncore_r2pcie,
+        [IVT_PCI_UNCORE_R3QPI]  = &ivt_uncore_r3qpi,
+        NULL,
+};
+
+static DEFINE_PCI_DEVICE_TABLE(ivt_uncore_pci_ids) = {
+        { /* Home Agent 0 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe30),
+                .driver_data = IVT_PCI_UNCORE_HA,
+        },
+        { /* Home Agent 1 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe38),
+                .driver_data = IVT_PCI_UNCORE_HA,
+        },
+        { /* MC0 Channel 0 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb4),
+                .driver_data = IVT_PCI_UNCORE_IMC,
+        },
+        { /* MC0 Channel 1 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb5),
+                .driver_data = IVT_PCI_UNCORE_IMC,
+        },
+        { /* MC0 Channel 3 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb0),
+                .driver_data = IVT_PCI_UNCORE_IMC,
+        },
+        { /* MC0 Channel 4 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb1),
+                .driver_data = IVT_PCI_UNCORE_IMC,
+        },
+        { /* MC1 Channel 0 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef4),
+                .driver_data = IVT_PCI_UNCORE_IMC,
+        },
+        { /* MC1 Channel 1 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef5),
+                .driver_data = IVT_PCI_UNCORE_IMC,
+        },
+        { /* MC1 Channel 3 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef0),
+                .driver_data = IVT_PCI_UNCORE_IMC,
+        },
+        { /* MC1 Channel 4 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef1),
+                .driver_data = IVT_PCI_UNCORE_IMC,
+        },
+        { /* QPI0 Port 0 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe32),
+                .driver_data = IVT_PCI_UNCORE_QPI,
+        },
+        { /* QPI0 Port 1 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe33),
+                .driver_data = IVT_PCI_UNCORE_QPI,
+        },
+        { /* QPI1 Port 2 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3a),
+                .driver_data = IVT_PCI_UNCORE_QPI,
+        },
+        { /* R2PCIe */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe34),
+                .driver_data = IVT_PCI_UNCORE_R2PCIE,
+        },
+        { /* R3QPI0 Link 0 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe36),
+                .driver_data = IVT_PCI_UNCORE_R3QPI,
+        },
+        { /* R3QPI0 Link 1 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe37),
+                .driver_data = IVT_PCI_UNCORE_R3QPI,
+        },
+        { /* R3QPI1 Link 2 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3e),
+                .driver_data = IVT_PCI_UNCORE_R3QPI,
+        },
+        { /* end: all zeroes */ }
+};
+
+static struct pci_driver ivt_uncore_pci_driver = {
+        .name           = "ivt_uncore",
+        .id_table       = ivt_uncore_pci_ids,
+};
+/* end of IvyTown uncore support */
+
 /* Sandy Bridge uncore support */
 static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
 {
@@ -808,9 +1491,6 @@ static struct intel_uncore_type *nhm_msr_uncores[] = {
 /* end of Nehalem uncore support */
 
 /* Nehalem-EX uncore support */
-#define __BITS_VALUE(x, i, n)  ((typeof(x))(((x) >> ((i) * (n))) & \
-                                ((1ULL << (n)) - 1)))
-
 DEFINE_UNCORE_FORMAT_ATTR(event5, event, "config:1-5");
 DEFINE_UNCORE_FORMAT_ATTR(counter, counter, "config:6-7");
 DEFINE_UNCORE_FORMAT_ATTR(match, match, "config1:0-63");
@@ -1161,7 +1841,7 @@ static struct extra_reg nhmex_uncore_mbox_extra_regs[] = {
 };
 
 /* Nehalem-EX or Westmere-EX ? */
-bool uncore_nhmex;
+static bool uncore_nhmex;
 
 static bool nhmex_mbox_get_shared_reg(struct intel_uncore_box *box, int idx, u64 config)
 {
@@ -1239,7 +1919,7 @@ static void nhmex_mbox_put_shared_reg(struct intel_uncore_box *box, int idx)
         atomic_sub(1 << (idx * 8), &er->ref);
 }
 
-u64 nhmex_mbox_alter_er(struct perf_event *event, int new_idx, bool modify)
+static u64 nhmex_mbox_alter_er(struct perf_event *event, int new_idx, bool modify)
 {
         struct hw_perf_event *hwc = &event->hw;
         struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
@@ -1554,7 +2234,7 @@ static struct intel_uncore_type nhmex_uncore_mbox = {
         .format_group           = &nhmex_uncore_mbox_format_group,
 };
 
-void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event *event)
+static void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event *event)
 {
         struct hw_perf_event *hwc = &event->hw;
         struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
@@ -1724,21 +2404,6 @@ static int nhmex_rbox_hw_config(struct intel_uncore_box *box, struct perf_event
         return 0;
 }
 
-static u64 nhmex_rbox_shared_reg_config(struct intel_uncore_box *box, int idx)
-{
-        struct intel_uncore_extra_reg *er;
-        unsigned long flags;
-        u64 config;
-
-        er = &box->shared_regs[idx];
-
-        raw_spin_lock_irqsave(&er->lock, flags);
-        config = er->config;
-        raw_spin_unlock_irqrestore(&er->lock, flags);
-
-        return config;
-}
-
 static void nhmex_rbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
 {
         struct hw_perf_event *hwc = &event->hw;
@@ -1759,7 +2424,7 @@ static void nhmex_rbox_msr_enable_event(struct intel_uncore_box *box, struct per
         case 2:
         case 3:
                 wrmsrl(NHMEX_R_MSR_PORTN_QLX_CFG(port),
-                        nhmex_rbox_shared_reg_config(box, 2 + (idx / 6) * 5));
+                        uncore_shared_reg_config(box, 2 + (idx / 6) * 5));
                 break;
         case 4:
                 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port),
@@ -2285,7 +2950,7 @@ out:
         return ret;
 }
 
-int uncore_pmu_event_init(struct perf_event *event)
+static int uncore_pmu_event_init(struct perf_event *event)
 {
         struct intel_uncore_pmu *pmu;
         struct intel_uncore_box *box;
@@ -2428,7 +3093,7 @@ static void __init uncore_types_exit(struct intel_uncore_type **types)
 static int __init uncore_type_init(struct intel_uncore_type *type)
 {
         struct intel_uncore_pmu *pmus;
-        struct attribute_group *events_group;
+        struct attribute_group *attr_group;
         struct attribute **attrs;
         int i, j;
 
@@ -2438,7 +3103,7 @@ static int __init uncore_type_init(struct intel_uncore_type *type)
 
         type->unconstrainted = (struct event_constraint)
                 __EVENT_CONSTRAINT(0, (1ULL << type->num_counters) - 1,
-                                0, type->num_counters, 0);
+                                0, type->num_counters, 0, 0);
 
         for (i = 0; i < type->num_boxes; i++) {
                 pmus[i].func_id = -1;
@@ -2455,19 +3120,19 @@ static int __init uncore_type_init(struct intel_uncore_type *type)
                 while (type->event_descs[i].attr.attr.name)
                         i++;
 
-                events_group = kzalloc(sizeof(struct attribute *) * (i + 1) +
-                                        sizeof(*events_group), GFP_KERNEL);
-                if (!events_group)
+                attr_group = kzalloc(sizeof(struct attribute *) * (i + 1) +
+                                        sizeof(*attr_group), GFP_KERNEL);
+                if (!attr_group)
                         goto fail;
 
-                attrs = (struct attribute **)(events_group + 1);
-                events_group->name = "events";
-                events_group->attrs = attrs;
+                attrs = (struct attribute **)(attr_group + 1);
+                attr_group->name = "events";
+                attr_group->attrs = attrs;
 
                 for (j = 0; j < i; j++)
                         attrs[j] = &type->event_descs[j].attr.attr;
 
-                type->events_group = events_group;
+                type->events_group = attr_group;
         }
 
         type->pmu_group = &uncore_pmu_attr_group;
@@ -2556,6 +3221,8 @@ static void uncore_pci_remove(struct pci_dev *pdev)
         if (WARN_ON_ONCE(phys_id != box->phys_id))
                 return;
 
+        pci_set_drvdata(pdev, NULL);
+
         raw_spin_lock(&uncore_box_lock);
         list_del(&box->list);
         raw_spin_unlock(&uncore_box_lock);
@@ -2574,11 +3241,7 @@ static void uncore_pci_remove(struct pci_dev *pdev)
 static int uncore_pci_probe(struct pci_dev *pdev,
                             const struct pci_device_id *id)
 {
-        struct intel_uncore_type *type;
-
-        type = (struct intel_uncore_type *)id->driver_data;
-
-        return uncore_pci_add(type, pdev);
+        return uncore_pci_add(pci_uncores[id->driver_data], pdev);
 }
 
 static int __init uncore_pci_init(void)
@@ -2587,12 +3250,19 @@ static int __init uncore_pci_init(void)
 
         switch (boot_cpu_data.x86_model) {
         case 45: /* Sandy Bridge-EP */
-                ret = snbep_pci2phy_map_init();
+                ret = snbep_pci2phy_map_init(0x3ce0);
                 if (ret)
                         return ret;
                 pci_uncores = snbep_pci_uncores;
                 uncore_pci_driver = &snbep_uncore_pci_driver;
                 break;
+        case 62: /* IvyTown */
+                ret = snbep_pci2phy_map_init(0x0e1e);
+                if (ret)
+                        return ret;
+                pci_uncores = ivt_pci_uncores;
+                uncore_pci_driver = &ivt_uncore_pci_driver;
+                break;
         default:
                 return 0;
         }
@@ -2622,6 +3292,21 @@ static void __init uncore_pci_exit(void)
         }
 }
 
+/* CPU hot plug/unplug are serialized by cpu_add_remove_lock mutex */
+static LIST_HEAD(boxes_to_free);
+
+static void __cpuinit uncore_kfree_boxes(void)
+{
+        struct intel_uncore_box *box;
+
+        while (!list_empty(&boxes_to_free)) {
+                box = list_entry(boxes_to_free.next,
+                                 struct intel_uncore_box, list);
+                list_del(&box->list);
+                kfree(box);
+        }
+}
+
 static void __cpuinit uncore_cpu_dying(int cpu)
 {
         struct intel_uncore_type *type;
@@ -2636,7 +3321,7 @@ static void __cpuinit uncore_cpu_dying(int cpu)
                         box = *per_cpu_ptr(pmu->box, cpu);
                         *per_cpu_ptr(pmu->box, cpu) = NULL;
                         if (box && atomic_dec_and_test(&box->refcnt))
-                                kfree(box);
+                                list_add(&box->list, &boxes_to_free);
                 }
         }
 }
@@ -2666,8 +3351,11 @@ static int __cpuinit uncore_cpu_starting(int cpu)
                                 if (exist && exist->phys_id == phys_id) {
                                         atomic_inc(&exist->refcnt);
                                         *per_cpu_ptr(pmu->box, cpu) = exist;
-                                        kfree(box);
-                                        box = NULL;
+                                        if (box) {
+                                                list_add(&box->list,
+                                                         &boxes_to_free);
+                                                box = NULL;
+                                        }
                                         break;
                                 }
                         }
@@ -2806,6 +3494,10 @@ static int
         case CPU_DYING:
                 uncore_cpu_dying(cpu);
                 break;
+        case CPU_ONLINE:
+        case CPU_DEAD:
+                uncore_kfree_boxes();
+                break;
         default:
                 break;
         }
@@ -2853,11 +3545,12 @@ static int __init uncore_cpu_init(void)
                 msr_uncores = nhm_msr_uncores;
                 break;
         case 42: /* Sandy Bridge */
+        case 58: /* Ivy Bridge */
                 if (snb_uncore_cbox.num_boxes > max_cores)
                         snb_uncore_cbox.num_boxes = max_cores;
                 msr_uncores = snb_msr_uncores;
                 break;
-        case 45: /* Sandy Birdge-EP */
+        case 45: /* Sandy Bridge-EP */
                 if (snbep_uncore_cbox.num_boxes > max_cores)
                         snbep_uncore_cbox.num_boxes = max_cores;
                 msr_uncores = snbep_msr_uncores;
@@ -2871,6 +3564,12 @@ static int __init uncore_cpu_init(void)
                         nhmex_uncore_cbox.num_boxes = max_cores;
                 msr_uncores = nhmex_msr_uncores;
                 break;
+        case 62: /* IvyTown */
+                if (ivt_uncore_cbox.num_boxes > max_cores)
+                        ivt_uncore_cbox.num_boxes = max_cores;
+                msr_uncores = ivt_msr_uncores;
+                break;
+
         default:
                 return 0;
         }
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.h b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
index e68a4550e952..f9528917f6e8 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.h
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
@@ -76,7 +76,7 @@
 #define SNBEP_PMON_CTL_UMASK_MASK       0x0000ff00
 #define SNBEP_PMON_CTL_RST              (1 << 17)
 #define SNBEP_PMON_CTL_EDGE_DET         (1 << 18)
-#define SNBEP_PMON_CTL_EV_SEL_EXT       (1 << 21)       /* only for QPI */
+#define SNBEP_PMON_CTL_EV_SEL_EXT       (1 << 21)
 #define SNBEP_PMON_CTL_EN               (1 << 22)
 #define SNBEP_PMON_CTL_INVERT           (1 << 23)
 #define SNBEP_PMON_CTL_TRESH_MASK       0xff000000
@@ -148,9 +148,20 @@
 #define SNBEP_C0_MSR_PMON_CTL0                  0xd10
 #define SNBEP_C0_MSR_PMON_BOX_CTL               0xd04
 #define SNBEP_C0_MSR_PMON_BOX_FILTER            0xd14
-#define SNBEP_CB0_MSR_PMON_BOX_FILTER_MASK      0xfffffc1f
 #define SNBEP_CBO_MSR_OFFSET                    0x20
 
+#define SNBEP_CB0_MSR_PMON_BOX_FILTER_TID       0x1f
+#define SNBEP_CB0_MSR_PMON_BOX_FILTER_NID       0x3fc00
+#define SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE     0x7c0000
+#define SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC       0xff800000
+
+#define SNBEP_CBO_EVENT_EXTRA_REG(e, m, i) {    \
+        .event = (e),                           \
+        .msr = SNBEP_C0_MSR_PMON_BOX_FILTER,    \
+        .config_mask = (m),                     \
+        .idx = (i)                              \
+}
+
 /* SNB-EP PCU register */
 #define SNBEP_PCU_MSR_PMON_CTR0                 0xc36
 #define SNBEP_PCU_MSR_PMON_CTL0                 0xc30
@@ -160,6 +171,55 @@
 #define SNBEP_PCU_MSR_CORE_C3_CTR               0x3fc
 #define SNBEP_PCU_MSR_CORE_C6_CTR               0x3fd
 
+/* IVT event control */
+#define IVT_PMON_BOX_CTL_INT            (SNBEP_PMON_BOX_CTL_RST_CTRL | \
+                                         SNBEP_PMON_BOX_CTL_RST_CTRS)
+#define IVT_PMON_RAW_EVENT_MASK         (SNBEP_PMON_CTL_EV_SEL_MASK | \
+                                         SNBEP_PMON_CTL_UMASK_MASK | \
+                                         SNBEP_PMON_CTL_EDGE_DET | \
+                                         SNBEP_PMON_CTL_TRESH_MASK)
+/* IVT Ubox */
+#define IVT_U_MSR_PMON_GLOBAL_CTL               0xc00
+#define IVT_U_PMON_GLOBAL_FRZ_ALL               (1 << 31)
+#define IVT_U_PMON_GLOBAL_UNFRZ_ALL             (1 << 29)
+
+#define IVT_U_MSR_PMON_RAW_EVENT_MASK   \
+                                (SNBEP_PMON_CTL_EV_SEL_MASK | \
+                                 SNBEP_PMON_CTL_UMASK_MASK | \
+                                 SNBEP_PMON_CTL_EDGE_DET | \
+                                 SNBEP_U_MSR_PMON_CTL_TRESH_MASK)
+/* IVT Cbo */
+#define IVT_CBO_MSR_PMON_RAW_EVENT_MASK         (IVT_PMON_RAW_EVENT_MASK | \
+                                                 SNBEP_CBO_PMON_CTL_TID_EN)
+
+#define IVT_CB0_MSR_PMON_BOX_FILTER_TID         (0x1fULL << 0)
+#define IVT_CB0_MSR_PMON_BOX_FILTER_LINK        (0xfULL << 5)
+#define IVT_CB0_MSR_PMON_BOX_FILTER_STATE       (0x3fULL << 17)
+#define IVT_CB0_MSR_PMON_BOX_FILTER_NID         (0xffffULL << 32)
+#define IVT_CB0_MSR_PMON_BOX_FILTER_OPC         (0x1ffULL << 52)
+#define IVT_CB0_MSR_PMON_BOX_FILTER_C6          (0x1ULL << 61)
+#define IVT_CB0_MSR_PMON_BOX_FILTER_NC          (0x1ULL << 62)
+#define IVT_CB0_MSR_PMON_BOX_FILTER_IOSC        (0x1ULL << 63)
+
+/* IVT home agent */
+#define IVT_HA_PCI_PMON_CTL_Q_OCC_RST           (1 << 16)
+#define IVT_HA_PCI_PMON_RAW_EVENT_MASK          \
+                                (IVT_PMON_RAW_EVENT_MASK | \
+                                 IVT_HA_PCI_PMON_CTL_Q_OCC_RST)
+/* IVT PCU */
+#define IVT_PCU_MSR_PMON_RAW_EVENT_MASK \
+                                (SNBEP_PMON_CTL_EV_SEL_MASK | \
+                                 SNBEP_PMON_CTL_EV_SEL_EXT | \
+                                 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
+                                 SNBEP_PMON_CTL_EDGE_DET | \
+                                 SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \
+                                 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
+                                 SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)
+/* IVT QPI */
+#define IVT_QPI_PCI_PMON_RAW_EVENT_MASK \
+                                (IVT_PMON_RAW_EVENT_MASK | \
+                                 SNBEP_PMON_CTL_EV_SEL_EXT)
+
 /* NHM-EX event control */
 #define NHMEX_PMON_CTL_EV_SEL_MASK      0x000000ff
 #define NHMEX_PMON_CTL_UMASK_MASK       0x0000ff00
diff --git a/arch/x86/kernel/cpu/perf_event_knc.c b/arch/x86/kernel/cpu/perf_event_knc.c
index 4b7731bf23a8..838fa8772c62 100644
--- a/arch/x86/kernel/cpu/perf_event_knc.c
+++ b/arch/x86/kernel/cpu/perf_event_knc.c
@@ -17,7 +17,7 @@ static const u64 knc_perfmon_event_map[] =
   [PERF_COUNT_HW_BRANCH_MISSES]         = 0x002b,
 };
 
-static __initconst u64 knc_hw_cache_event_ids
+static const u64 __initconst knc_hw_cache_event_ids
                                 [PERF_COUNT_HW_CACHE_MAX]
                                 [PERF_COUNT_HW_CACHE_OP_MAX]
                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
@@ -284,7 +284,7 @@ static struct attribute *intel_knc_formats_attr[] = {
         NULL,
 };
 
-static __initconst struct x86_pmu knc_pmu = {
+static const struct x86_pmu knc_pmu __initconst = {
         .name                   = "knc",
         .handle_irq             = knc_pmu_handle_irq,
         .disable_all            = knc_pmu_disable_all,
diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c
index 92c7e39a079f..3486e6660357 100644
--- a/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@ -895,8 +895,8 @@ static void p4_pmu_disable_pebs(void)
          * So at moment let leave metrics turned on forever -- it's
          * ok for now but need to be revisited!
          *
-         * (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, (u64)0);
-         * (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, (u64)0);
+         * (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, 0);
+         * (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, 0);
          */
 }
 
@@ -910,8 +910,7 @@ static inline void p4_pmu_disable_event(struct perf_event *event)
          * asserted again and again
          */
         (void)wrmsrl_safe(hwc->config_base,
-                (u64)(p4_config_unpack_cccr(hwc->config)) &
-                        ~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED);
+                p4_config_unpack_cccr(hwc->config) & ~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED);
 }
 
 static void p4_pmu_disable_all(void)
@@ -957,7 +956,7 @@ static void p4_pmu_enable_event(struct perf_event *event)
         u64 escr_addr, cccr;
 
         bind = &p4_event_bind_map[idx];
-        escr_addr = (u64)bind->escr_msr[thread];
+        escr_addr = bind->escr_msr[thread];
 
         /*
          * - we dont support cascaded counters yet
diff --git a/arch/x86/kernel/cpu/perf_event_p6.c b/arch/x86/kernel/cpu/perf_event_p6.c
index 4820c232a0b9..b1e2fe115323 100644
--- a/arch/x86/kernel/cpu/perf_event_p6.c
+++ b/arch/x86/kernel/cpu/perf_event_p6.c
@@ -19,7 +19,7 @@ static const u64 p6_perfmon_event_map[] =
 
 };
 
-static u64 p6_hw_cache_event_ids
+static const u64 __initconst p6_hw_cache_event_ids
                                 [PERF_COUNT_HW_CACHE_MAX]
                                 [PERF_COUNT_HW_CACHE_OP_MAX]
                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index e280253f6f94..37a198bd48c8 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -34,9 +34,9 @@ static void show_cpuinfo_misc(struct seq_file *m, struct cpuinfo_x86 *c)
                    "fpu_exception\t: %s\n"
                    "cpuid level\t: %d\n"
                    "wp\t\t: %s\n",
-                   c->fdiv_bug ? "yes" : "no",
-                   c->f00f_bug ? "yes" : "no",
-                   c->coma_bug ? "yes" : "no",
+                   static_cpu_has_bug(X86_BUG_FDIV) ? "yes" : "no",
+                   static_cpu_has_bug(X86_BUG_F00F) ? "yes" : "no",
+                   static_cpu_has_bug(X86_BUG_COMA) ? "yes" : "no",
                    c->hard_math ? "yes" : "no",
                    c->hard_math ? "yes" : "no",
                    c->cpuid_level,
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index ee8e9abc859f..d92b5dad15dd 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -39,8 +39,9 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
                 { X86_FEATURE_APERFMPERF,       CR_ECX, 0, 0x00000006, 0 },
                 { X86_FEATURE_EPB,              CR_ECX, 3, 0x00000006, 0 },
                 { X86_FEATURE_XSAVEOPT,         CR_EAX, 0, 0x0000000d, 1 },
-                { X86_FEATURE_CPB,              CR_EDX, 9, 0x80000007, 0 },
                 { X86_FEATURE_HW_PSTATE,        CR_EDX, 7, 0x80000007, 0 },
+                { X86_FEATURE_CPB,              CR_EDX, 9, 0x80000007, 0 },
+                { X86_FEATURE_PROC_FEEDBACK,    CR_EDX,11, 0x80000007, 0 },
                 { X86_FEATURE_NPT,              CR_EDX, 0, 0x8000000a, 0 },
                 { X86_FEATURE_LBRV,             CR_EDX, 1, 0x8000000a, 0 },
                 { X86_FEATURE_SVML,             CR_EDX, 2, 0x8000000a, 0 },
diff --git a/arch/x86/kernel/doublefault_32.c b/arch/x86/kernel/doublefault_32.c
index 37250fe490b1..155a13f33ed8 100644
--- a/arch/x86/kernel/doublefault_32.c
+++ b/arch/x86/kernel/doublefault_32.c
@@ -20,7 +20,7 @@ static void doublefault_fn(void)
         struct desc_ptr gdt_desc = {0, 0};
         unsigned long gdt, tss;
 
-        store_gdt(&gdt_desc);
+        native_store_gdt(&gdt_desc);
         gdt = gdt_desc.address;
 
         printk(KERN_EMERG "PANIC: double fault, gdt at %08lx [%d bytes]\n", gdt, gdt_desc.size);
diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c
index c8797d55b245..deb6421c9e69 100644
--- a/arch/x86/kernel/dumpstack.c
+++ b/arch/x86/kernel/dumpstack.c
@@ -176,26 +176,20 @@ void show_trace(struct task_struct *task, struct pt_regs *regs,
 
 void show_stack(struct task_struct *task, unsigned long *sp)
 {
-        show_stack_log_lvl(task, NULL, sp, 0, "");
-}
-
-/*
- * The architecture-independent dump_stack generator
- */
-void dump_stack(void)
-{
-        unsigned long bp;
+        unsigned long bp = 0;
         unsigned long stack;
 
-        bp = stack_frame(current, NULL);
-        printk("Pid: %d, comm: %.20s %s %s %.*s\n",
-                current->pid, current->comm, print_tainted(),
-                init_utsname()->release,
-                (int)strcspn(init_utsname()->version, " "),
-                init_utsname()->version);
-        show_trace(NULL, NULL, &stack, bp);
+        /*
+         * Stack frames below this one aren't interesting.  Don't show them
+         * if we're printing for %current.
+         */
+        if (!sp && (!task || task == current)) {
+                sp = &stack;
+                bp = stack_frame(current, NULL);
+        }
+
+        show_stack_log_lvl(task, NULL, sp, bp, "");
 }
-EXPORT_SYMBOL(dump_stack);
 
 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
 static int die_owner = -1;
diff --git a/arch/x86/kernel/dumpstack_32.c b/arch/x86/kernel/dumpstack_32.c
index 1038a417ea53..f2a1770ca176 100644
--- a/arch/x86/kernel/dumpstack_32.c
+++ b/arch/x86/kernel/dumpstack_32.c
@@ -86,11 +86,9 @@ void show_regs(struct pt_regs *regs)
 {
         int i;
 
+        show_regs_print_info(KERN_EMERG);
         __show_regs(regs, !user_mode_vm(regs));
 
-        pr_emerg("Process %.*s (pid: %d, ti=%p task=%p task.ti=%p)\n",
-                 TASK_COMM_LEN, current->comm, task_pid_nr(current),
-                 current_thread_info(), current, task_thread_info(current));
         /*
          * When in-kernel, we also print out the stack and code at the
          * time of the fault..
diff --git a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c
index b653675d5288..addb207dab92 100644
--- a/arch/x86/kernel/dumpstack_64.c
+++ b/arch/x86/kernel/dumpstack_64.c
@@ -249,14 +249,10 @@ void show_regs(struct pt_regs *regs)
 {
         int i;
         unsigned long sp;
-        const int cpu = smp_processor_id();
-        struct task_struct *cur = current;
 
         sp = regs->sp;
-        printk("CPU %d ", cpu);
+        show_regs_print_info(KERN_DEFAULT);
         __show_regs(regs, 1);
-        printk(KERN_DEFAULT "Process %s (pid: %d, threadinfo %p, task %p)\n",
-               cur->comm, cur->pid, task_thread_info(cur), cur);
 
         /*
          * When in-kernel, we also print out the stack and code at the
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 3755ef494390..94ab6b90dd3f 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -18,6 +18,7 @@
 #include <asm/apic.h>
 #include <asm/iommu.h>
 #include <asm/gart.h>
+#include <asm/irq_remapping.h>
 
 static void __init fix_hypertransport_config(int num, int slot, int func)
 {
@@ -192,6 +193,21 @@ static void __init ati_bugs_contd(int num, int slot, int func)
 }
 #endif
 
+static void __init intel_remapping_check(int num, int slot, int func)
+{
+        u8 revision;
+
+        revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID);
+
+        /*
+         * Revision 0x13 of this chipset supports irq remapping
+         * but has an erratum that breaks its behavior, flag it as such
+         */
+        if (revision == 0x13)
+                set_irq_remapping_broken();
+
+}
+
 #define QFLAG_APPLY_ONCE        0x1
 #define QFLAG_APPLIED           0x2
 #define QFLAG_DONE              (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
@@ -221,6 +237,10 @@ static struct chipset early_qrk[] __initdata = {
           PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
           PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
+        { PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST,
+          PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
+        { PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,
+          PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
         {}
 };
 
diff --git a/arch/x86/kernel/early_printk.c b/arch/x86/kernel/early_printk.c
index 9b9f18b49918..d15f575a861b 100644
--- a/arch/x86/kernel/early_printk.c
+++ b/arch/x86/kernel/early_printk.c
@@ -169,25 +169,9 @@ static struct console early_serial_console = {
         .index =        -1,
 };
 
-/* Direct interface for emergencies */
-static struct console *early_console = &early_vga_console;
-static int __initdata early_console_initialized;
-
-asmlinkage void early_printk(const char *fmt, ...)
-{
-        char buf[512];
-        int n;
-        va_list ap;
-
-        va_start(ap, fmt);
-        n = vscnprintf(buf, sizeof(buf), fmt, ap);
-        early_console->write(early_console, buf, n);
-        va_end(ap);
-}
-
 static inline void early_console_register(struct console *con, int keep_early)
 {
-        if (early_console->index != -1) {
+        if (con->index != -1) {
                 printk(KERN_CRIT "ERROR: earlyprintk= %s already used\n",
                        con->name);
                 return;
@@ -207,9 +191,8 @@ static int __init setup_early_printk(char *buf)
         if (!buf)
                 return 0;
 
-        if (early_console_initialized)
+        if (early_console)
                 return 0;
-        early_console_initialized = 1;
 
         keep = (strstr(buf, "keep") != NULL);
 
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index c1d01e6ca790..727208941030 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -1166,6 +1166,11 @@ apicinterrupt LOCAL_TIMER_VECTOR \
 apicinterrupt X86_PLATFORM_IPI_VECTOR \
         x86_platform_ipi smp_x86_platform_ipi
 
+#ifdef CONFIG_HAVE_KVM
+apicinterrupt POSTED_INTR_VECTOR \
+        kvm_posted_intr_ipi smp_kvm_posted_intr_ipi
+#endif
+
 apicinterrupt THRESHOLD_APIC_VECTOR \
         threshold_interrupt smp_threshold_interrupt
 apicinterrupt THERMAL_APIC_VECTOR \
diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
index c5e403f6d869..dab95a85f7f8 100644
--- a/arch/x86/kernel/head64.c
+++ b/arch/x86/kernel/head64.c
@@ -34,6 +34,7 @@
 extern pgd_t early_level4_pgt[PTRS_PER_PGD];
 extern pmd_t early_dynamic_pgts[EARLY_DYNAMIC_PAGE_TABLES][PTRS_PER_PMD];
 static unsigned int __initdata next_early_pgt = 2;
+pmdval_t __initdata early_pmd_flags = __PAGE_KERNEL_LARGE & ~(_PAGE_GLOBAL | _PAGE_NX);
 
 /* Wipe all early page tables except for the kernel symbol map */
 static void __init reset_early_page_tables(void)
@@ -99,7 +100,7 @@ again:
                         pmd_p[i] = 0;
                 *pud_p = (pudval_t)pmd_p - __START_KERNEL_map + phys_base + _KERNPG_TABLE;
         }
-        pmd = (physaddr & PMD_MASK) + (__PAGE_KERNEL_LARGE & ~_PAGE_GLOBAL);
+        pmd = (physaddr & PMD_MASK) + early_pmd_flags;
         pmd_p[pmd_index(address)] = pmd;
 
         return 0;
@@ -144,10 +145,10 @@ void __init x86_64_start_kernel(char * real_mode_data)
          * Build-time sanity checks on the kernel image and module
          * area mappings. (these are purely build-time and produce no code)
          */
-        BUILD_BUG_ON(MODULES_VADDR < KERNEL_IMAGE_START);
-        BUILD_BUG_ON(MODULES_VADDR-KERNEL_IMAGE_START < KERNEL_IMAGE_SIZE);
+        BUILD_BUG_ON(MODULES_VADDR < __START_KERNEL_map);
+        BUILD_BUG_ON(MODULES_VADDR - __START_KERNEL_map < KERNEL_IMAGE_SIZE);
         BUILD_BUG_ON(MODULES_LEN + KERNEL_IMAGE_SIZE > 2*PUD_SIZE);
-        BUILD_BUG_ON((KERNEL_IMAGE_START & ~PMD_MASK) != 0);
+        BUILD_BUG_ON((__START_KERNEL_map & ~PMD_MASK) != 0);
         BUILD_BUG_ON((MODULES_VADDR & ~PMD_MASK) != 0);
         BUILD_BUG_ON(!(MODULES_VADDR > __START_KERNEL));
         BUILD_BUG_ON(!(((MODULES_END - 1) & PGDIR_MASK) ==
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index 6859e9626442..08f7e8039099 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -200,6 +200,7 @@ ENTRY(secondary_startup_64)
         btl     $20,%edi                /* No Execute supported? */
         jnc     1f
         btsl    $_EFER_NX, %eax
+        btsq    $_PAGE_BIT_NX,early_pmd_flags(%rip)
 1:      wrmsr                           /* Make changes effective */
 
         /* Setup cr0 */
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c
index e4595f105910..ac0631d8996f 100644
--- a/arch/x86/kernel/irq.c
+++ b/arch/x86/kernel/irq.c
@@ -165,10 +165,6 @@ u64 arch_irq_stat_cpu(unsigned int cpu)
 u64 arch_irq_stat(void)
 {
         u64 sum = atomic_read(&irq_err_count);
-
-#ifdef CONFIG_X86_IO_APIC
-        sum += atomic_read(&irq_mis_count);
-#endif
         return sum;
 }
 
@@ -228,6 +224,28 @@ void smp_x86_platform_ipi(struct pt_regs *regs)
         set_irq_regs(old_regs);
 }
 
+#ifdef CONFIG_HAVE_KVM
+/*
+ * Handler for POSTED_INTERRUPT_VECTOR.
+ */
+void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
+{
+        struct pt_regs *old_regs = set_irq_regs(regs);
+
+        ack_APIC_irq();
+
+        irq_enter();
+
+        exit_idle();
+
+        inc_irq_stat(kvm_posted_intr_ipis);
+
+        irq_exit();
+
+        set_irq_regs(old_regs);
+}
+#endif
+
 EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
 
 #ifdef CONFIG_HOTPLUG_CPU
diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c
index 7dc4e459c2b3..a2a1fbc594ff 100644
--- a/arch/x86/kernel/irqinit.c
+++ b/arch/x86/kernel/irqinit.c
@@ -172,6 +172,10 @@ static void __init apic_intr_init(void)
 
         /* IPI for X86 platform specific use */
         alloc_intr_gate(X86_PLATFORM_IPI_VECTOR, x86_platform_ipi);
+#ifdef CONFIG_HAVE_KVM
+        /* IPI for KVM to deliver posted interrupt */
+        alloc_intr_gate(POSTED_INTR_VECTOR, kvm_posted_intr_ipi);
+#endif
 
         /* IPI vectors for APIC spurious and error interrupts */
         alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
diff --git a/arch/x86/kernel/kprobes/core.c b/arch/x86/kernel/kprobes/core.c
index 7bfe318d3d8a..9895a9a41380 100644
--- a/arch/x86/kernel/kprobes/core.c
+++ b/arch/x86/kernel/kprobes/core.c
@@ -353,7 +353,11 @@ int __kprobes __copy_instruction(u8 *dest, u8 *src)
                  * have given.
                  */
                 newdisp = (u8 *) src + (s64) insn.displacement.value - (u8 *) dest;
-                BUG_ON((s64) (s32) newdisp != newdisp); /* Sanity check.  */
+                if ((s64) (s32) newdisp != newdisp) {
+                        pr_err("Kprobes error: new displacement does not fit into s32 (%llx)\n", newdisp);
+                        pr_err("\tSrc: %p, Dest: %p, old disp: %x\n", src, dest, insn.displacement.value);
+                        return 0;
+                }
                 disp = (u8 *) dest + insn_offset_displacement(&insn);
                 *(s32 *) disp = (s32) newdisp;
         }
diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
index b686a904d7c3..cd6d9a5a42f6 100644
--- a/arch/x86/kernel/kvm.c
+++ b/arch/x86/kernel/kvm.c
@@ -20,6 +20,7 @@
  *   Authors: Anthony Liguori <aliguori@us.ibm.com>
  */
 
+#include <linux/context_tracking.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/kvm_para.h>
@@ -43,7 +44,6 @@
 #include <asm/apicdef.h>
 #include <asm/hypervisor.h>
 #include <asm/kvm_guest.h>
-#include <asm/context_tracking.h>
 
 static int kvmapf = 1;
 
@@ -254,16 +254,18 @@ EXPORT_SYMBOL_GPL(kvm_read_and_reset_pf_reason);
 dotraplinkage void __kprobes
 do_async_page_fault(struct pt_regs *regs, unsigned long error_code)
 {
+        enum ctx_state prev_state;
+
         switch (kvm_read_and_reset_pf_reason()) {
         default:
                 do_page_fault(regs, error_code);
                 break;
         case KVM_PV_REASON_PAGE_NOT_PRESENT:
                 /* page is swapped out by the host. */
-                exception_enter(regs);
+                prev_state = exception_enter();
                 exit_idle();
                 kvm_async_pf_task_wait((u32)read_cr2());
-                exception_exit(regs);
+                exception_exit(prev_state);
                 break;
         case KVM_PV_REASON_PAGE_READY:
                 rcu_irq_enter();
diff --git a/arch/x86/kernel/kvmclock.c b/arch/x86/kernel/kvmclock.c
index 0732f0089a3d..d2c381280e3c 100644
--- a/arch/x86/kernel/kvmclock.c
+++ b/arch/x86/kernel/kvmclock.c
@@ -160,8 +160,12 @@ int kvm_register_clock(char *txt)
 {
         int cpu = smp_processor_id();
         int low, high, ret;
-        struct pvclock_vcpu_time_info *src = &hv_clock[cpu].pvti;
+        struct pvclock_vcpu_time_info *src;
+
+        if (!hv_clock)
+                return 0;
 
+        src = &hv_clock[cpu].pvti;
         low = (int)slow_virt_to_phys(src) | 1;
         high = ((u64)slow_virt_to_phys(src) >> 32);
         ret = native_write_msr_safe(msr_kvm_system_time, low, high);
@@ -276,6 +280,9 @@ int __init kvm_setup_vsyscall_timeinfo(void)
         struct pvclock_vcpu_time_info *vcpu_time;
         unsigned int size;
 
+        if (!hv_clock)
+                return 0;
+
         size = PAGE_ALIGN(sizeof(struct pvclock_vsyscall_time_info)*NR_CPUS);
 
         preempt_disable();
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index 8bfb335f74bb..cd6de64cc480 100644
--- a/arch/x86/kernel/paravirt.c
+++ b/arch/x86/kernel/paravirt.c
@@ -360,7 +360,6 @@ struct pv_cpu_ops pv_cpu_ops = {
         .set_ldt = native_set_ldt,
         .load_gdt = native_load_gdt,
         .load_idt = native_load_idt,
-        .store_gdt = native_store_gdt,
         .store_idt = native_store_idt,
         .store_tr = native_store_tr,
         .load_tls = native_load_tls,
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 14ae10031ff0..607af0d4d5ef 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -121,30 +121,6 @@ void exit_thread(void)
         drop_fpu(me);
 }
 
-void show_regs_common(void)
-{
-        const char *vendor, *product, *board;
-
-        vendor = dmi_get_system_info(DMI_SYS_VENDOR);
-        if (!vendor)
-                vendor = "";
-        product = dmi_get_system_info(DMI_PRODUCT_NAME);
-        if (!product)
-                product = "";
-
-        /* Board Name is optional */
-        board = dmi_get_system_info(DMI_BOARD_NAME);
-
-        printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s %s %s%s%s\n",
-               current->pid, current->comm, print_tainted(),
-               init_utsname()->release,
-               (int)strcspn(init_utsname()->version, " "),
-               init_utsname()->version,
-               vendor, product,
-               board ? "/" : "",
-               board ? board : "");
-}
-
 void flush_thread(void)
 {
         struct task_struct *tsk = current;
@@ -301,13 +277,7 @@ void exit_idle(void)
 }
 #endif
 
-/*
- * The idle thread. There's no useful work to be
- * done, so just try to conserve power and have a
- * low exit latency (ie sit in a loop waiting for
- * somebody to say that they'd like to reschedule)
- */
-void cpu_idle(void)
+void arch_cpu_idle_prepare(void)
 {
         /*
          * If we're the non-boot CPU, nothing set the stack canary up
@@ -317,71 +287,40 @@ void cpu_idle(void)
          * canaries already on the stack wont ever trigger).
          */
         boot_init_stack_canary();
-        current_thread_info()->status |= TS_POLLING;
-
-        while (1) {
-                tick_nohz_idle_enter();
-
-                while (!need_resched()) {
-                        rmb();
-
-                        if (cpu_is_offline(smp_processor_id()))
-                                play_dead();
-
-                        /*
-                         * Idle routines should keep interrupts disabled
-                         * from here on, until they go to idle.
-                         * Otherwise, idle callbacks can misfire.
-                         */
-                        local_touch_nmi();
-                        local_irq_disable();
-
-                        enter_idle();
-
-                        /* Don't trace irqs off for idle */
-                        stop_critical_timings();
-
-                        /* enter_idle() needs rcu for notifiers */
-                        rcu_idle_enter();
+}
 
-                        if (cpuidle_idle_call())
-                                x86_idle();
+void arch_cpu_idle_enter(void)
+{
+        local_touch_nmi();
+        enter_idle();
+}
 
-                        rcu_idle_exit();
-                        start_critical_timings();
+void arch_cpu_idle_exit(void)
+{
+        __exit_idle();
+}
 
-                        /* In many cases the interrupt that ended idle
-                           has already called exit_idle. But some idle
-                           loops can be woken up without interrupt. */
-                        __exit_idle();
-                }
+void arch_cpu_idle_dead(void)
+{
+        play_dead();
+}
 
-                tick_nohz_idle_exit();
-                preempt_enable_no_resched();
-                schedule();
-                preempt_disable();
-        }
+/*
+ * Called from the generic idle code.
+ */
+void arch_cpu_idle(void)
+{
+        if (cpuidle_idle_call())
+                x86_idle();
 }
 
 /*
- * We use this if we don't have any better
- * idle routine..
+ * We use this if we don't have any better idle routine..
  */
 void default_idle(void)
 {
         trace_cpu_idle_rcuidle(1, smp_processor_id());
-        current_thread_info()->status &= ~TS_POLLING;
-        /*
-         * TS_POLLING-cleared state must be visible before we
-         * test NEED_RESCHED:
-         */
-        smp_mb();
-
-        if (!need_resched())
-                safe_halt();    /* enables interrupts racelessly */
-        else
-                local_irq_enable();
-        current_thread_info()->status |= TS_POLLING;
+        safe_halt();
         trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
 }
 #ifdef CONFIG_APM_MODULE
@@ -411,20 +350,6 @@ void stop_this_cpu(void *dummy)
                 halt();
 }
 
-/*
- * On SMP it's slightly faster (but much more power-consuming!)
- * to poll the ->work.need_resched flag instead of waiting for the
- * cross-CPU IPI to arrive. Use this option with caution.
- */
-static void poll_idle(void)
-{
-        trace_cpu_idle_rcuidle(0, smp_processor_id());
-        local_irq_enable();
-        while (!need_resched())
-                cpu_relax();
-        trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
-}
-
 bool amd_e400_c1e_detected;
 EXPORT_SYMBOL(amd_e400_c1e_detected);
 
@@ -489,13 +414,13 @@ static void amd_e400_idle(void)
 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
 {
 #ifdef CONFIG_SMP
-        if (x86_idle == poll_idle && smp_num_siblings > 1)
+        if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
                 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
 #endif
-        if (x86_idle)
+        if (x86_idle || boot_option_idle_override == IDLE_POLL)
                 return;
 
-        if (cpu_has_amd_erratum(amd_erratum_400)) {
+        if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) {
                 /* E400: APIC timer interrupt does not wake up CPU from C1e */
                 pr_info("using AMD E400 aware idle routine\n");
                 x86_idle = amd_e400_idle;
@@ -517,8 +442,8 @@ static int __init idle_setup(char *str)
 
         if (!strcmp(str, "poll")) {
                 pr_info("using polling idle threads\n");
-                x86_idle = poll_idle;
                 boot_option_idle_override = IDLE_POLL;
+                cpu_idle_poll_ctrl(true);
         } else if (!strcmp(str, "halt")) {
                 /*
                  * When the boot option of idle=halt is added, halt is
diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
index b5a8905785e6..7305f7dfc7ab 100644
--- a/arch/x86/kernel/process_32.c
+++ b/arch/x86/kernel/process_32.c
@@ -84,8 +84,6 @@ void __show_regs(struct pt_regs *regs, int all)
                 savesegment(gs, gs);
         }
 
-        show_regs_common();
-
         printk(KERN_DEFAULT "EIP: %04x:[<%08lx>] EFLAGS: %08lx CPU: %d\n",
                         (u16)regs->cs, regs->ip, regs->flags,
                         smp_processor_id());
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 0f49677da51e..355ae06dbf94 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -62,7 +62,6 @@ void __show_regs(struct pt_regs *regs, int all)
         unsigned int fsindex, gsindex;
         unsigned int ds, cs, es;
 
-        show_regs_common();
         printk(KERN_DEFAULT "RIP: %04lx:[<%016lx>] ", regs->cs & 0xffff, regs->ip);
         printk_address(regs->ip, 1);
         printk(KERN_DEFAULT "RSP: %04lx:%016lx  EFLAGS: %08lx\n", regs->ss,
diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c
index 26ee48a33dc4..04ee1e2e4c02 100644
--- a/arch/x86/kernel/quirks.c
+++ b/arch/x86/kernel/quirks.c
@@ -354,18 +354,22 @@ static void ati_force_hpet_resume(void)
 
 static u32 ati_ixp4x0_rev(struct pci_dev *dev)
 {
-        u32 d;
-        u8  b;
+        int err = 0;
+        u32 d = 0;
+        u8  b = 0;
 
-        pci_read_config_byte(dev, 0xac, &b);
+        err = pci_read_config_byte(dev, 0xac, &b);
         b &= ~(1<<5);
-        pci_write_config_byte(dev, 0xac, b);
-        pci_read_config_dword(dev, 0x70, &d);
+        err |= pci_write_config_byte(dev, 0xac, b);
+        err |= pci_read_config_dword(dev, 0x70, &d);
         d |= 1<<8;
-        pci_write_config_dword(dev, 0x70, d);
-        pci_read_config_dword(dev, 0x8, &d);
+        err |= pci_write_config_dword(dev, 0x70, d);
+        err |= pci_read_config_dword(dev, 0x8, &d);
         d &= 0xff;
         dev_printk(KERN_DEBUG, &dev->dev, "SB4X0 revision 0x%x\n", d);
+
+        WARN_ON_ONCE(err);
+
         return d;
 }
 
diff --git a/arch/x86/kernel/rtc.c b/arch/x86/kernel/rtc.c
index 2e8f3d3b5641..198eb201ed3b 100644
--- a/arch/x86/kernel/rtc.c
+++ b/arch/x86/kernel/rtc.c
@@ -13,6 +13,7 @@
 #include <asm/x86_init.h>
 #include <asm/time.h>
 #include <asm/mrst.h>
+#include <asm/rtc.h>
 
 #ifdef CONFIG_X86_32
 /*
@@ -36,70 +37,24 @@ EXPORT_SYMBOL(rtc_lock);
  * nowtime is written into the registers of the CMOS clock, it will
  * jump to the next second precisely 500 ms later. Check the Motorola
  * MC146818A or Dallas DS12887 data sheet for details.
- *
- * BUG: This routine does not handle hour overflow properly; it just
- *      sets the minutes. Usually you'll only notice that after reboot!
  */
 int mach_set_rtc_mmss(unsigned long nowtime)
 {
-        int real_seconds, real_minutes, cmos_minutes;
-        unsigned char save_control, save_freq_select;
-        unsigned long flags;
+        struct rtc_time tm;
         int retval = 0;
 
-        spin_lock_irqsave(&rtc_lock, flags);
-
-         /* tell the clock it's being set */
-        save_control = CMOS_READ(RTC_CONTROL);
-        CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
-
-        /* stop and reset prescaler */
-        save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
-        CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
-
-        cmos_minutes = CMOS_READ(RTC_MINUTES);
-        if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
-                cmos_minutes = bcd2bin(cmos_minutes);
-
-        /*
-         * since we're only adjusting minutes and seconds,
-         * don't interfere with hour overflow. This avoids
-         * messing with unknown time zones but requires your
-         * RTC not to be off by more than 15 minutes
-         */
-        real_seconds = nowtime % 60;
-        real_minutes = nowtime / 60;
-        /* correct for half hour time zone */
-        if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
-                real_minutes += 30;
-        real_minutes %= 60;
-
-        if (abs(real_minutes - cmos_minutes) < 30) {
-                if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
-                        real_seconds = bin2bcd(real_seconds);
-                        real_minutes = bin2bcd(real_minutes);
-                }
-                CMOS_WRITE(real_seconds, RTC_SECONDS);
-                CMOS_WRITE(real_minutes, RTC_MINUTES);
+        rtc_time_to_tm(nowtime, &tm);
+        if (!rtc_valid_tm(&tm)) {
+                retval = set_rtc_time(&tm);
+                if (retval)
+                        printk(KERN_ERR "%s: RTC write failed with error %d\n",
+                               __FUNCTION__, retval);
         } else {
-                printk_once(KERN_NOTICE
-                       "set_rtc_mmss: can't update from %d to %d\n",
-                       cmos_minutes, real_minutes);
-                retval = -1;
+                printk(KERN_ERR
+                       "%s: Invalid RTC value: write of %lx to RTC failed\n",
+                        __FUNCTION__, nowtime);
+                retval = -EINVAL;
         }
-
-        /* The following flags have to be released exactly in this order,
-         * otherwise the DS12887 (popular MC146818A clone with integrated
-         * battery and quartz) will not reset the oscillator and will not
-         * update precisely 500 ms later. You won't find this mentioned in
-         * the Dallas Semiconductor data sheets, but who believes data
-         * sheets anyway ...                           -- Markus Kuhn
-         */
-        CMOS_WRITE(save_control, RTC_CONTROL);
-        CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
-
-        spin_unlock_irqrestore(&rtc_lock, flags);
-
         return retval;
 }
 
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index fae9134a2de9..56f7fcfe7fa2 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -82,7 +82,6 @@
 #include <asm/timer.h>
 #include <asm/i8259.h>
 #include <asm/sections.h>
-#include <asm/dmi.h>
 #include <asm/io_apic.h>
 #include <asm/ist.h>
 #include <asm/setup_arch.h>
@@ -173,12 +172,10 @@ static struct resource bss_resource = {
 /* cpu data as detected by the assembly code in head.S */
 struct cpuinfo_x86 new_cpu_data __cpuinitdata = {
         .wp_works_ok = -1,
-        .fdiv_bug = -1,
 };
 /* common cpu data for all cpus */
 struct cpuinfo_x86 boot_cpu_data __read_mostly = {
         .wp_works_ok = -1,
-        .fdiv_bug = -1,
 };
 EXPORT_SYMBOL(boot_cpu_data);
 
@@ -999,6 +996,7 @@ void __init setup_arch(char **cmdline_p)
                 efi_init();
 
         dmi_scan_machine();
+        dmi_set_dump_stack_arch_desc();
 
         /*
          * VMware detection requires dmi to be available, so this
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 9f190a2a00e9..9c73b51817e4 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -284,7 +284,7 @@ notrace static void __cpuinit start_secondary(void *unused)
         x86_cpuinit.setup_percpu_clockev();
 
         wmb();
-        cpu_idle();
+        cpu_startup_entry(CPUHP_ONLINE);
 }
 
 void __init smp_store_boot_cpu_info(void)
diff --git a/arch/x86/kernel/tls.c b/arch/x86/kernel/tls.c
index 9d9d2f9e77a5..f7fec09e3e3a 100644
--- a/arch/x86/kernel/tls.c
+++ b/arch/x86/kernel/tls.c
@@ -3,13 +3,13 @@
 #include <linux/sched.h>
 #include <linux/user.h>
 #include <linux/regset.h>
+#include <linux/syscalls.h>
 
 #include <asm/uaccess.h>
 #include <asm/desc.h>
 #include <asm/ldt.h>
 #include <asm/processor.h>
 #include <asm/proto.h>
-#include <asm/syscalls.h>
 
 #include "tls.h"
 
@@ -89,11 +89,9 @@ int do_set_thread_area(struct task_struct *p, int idx,
         return 0;
 }
 
-asmlinkage int sys_set_thread_area(struct user_desc __user *u_info)
+SYSCALL_DEFINE1(set_thread_area, struct user_desc __user *, u_info)
 {
-        int ret = do_set_thread_area(current, -1, u_info, 1);
-        asmlinkage_protect(1, ret, u_info);
-        return ret;
+        return do_set_thread_area(current, -1, u_info, 1);
 }
 
 
@@ -139,11 +137,9 @@ int do_get_thread_area(struct task_struct *p, int idx,
         return 0;
 }
 
-asmlinkage int sys_get_thread_area(struct user_desc __user *u_info)
+SYSCALL_DEFINE1(get_thread_area, struct user_desc __user *, u_info)
 {
-        int ret = do_get_thread_area(current, -1, u_info);
-        asmlinkage_protect(1, ret, u_info);
-        return ret;
+        return do_get_thread_area(current, -1, u_info);
 }
 
 int regset_tls_active(struct task_struct *target,
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 68bda7a84159..772e2a846dec 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -12,6 +12,7 @@
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
+#include <linux/context_tracking.h>
 #include <linux/interrupt.h>
 #include <linux/kallsyms.h>
 #include <linux/spinlock.h>
@@ -55,8 +56,7 @@
 #include <asm/i387.h>
 #include <asm/fpu-internal.h>
 #include <asm/mce.h>
-#include <asm/context_tracking.h>
-
+#include <asm/fixmap.h>
 #include <asm/mach_traps.h>
 
 #ifdef CONFIG_X86_64
@@ -176,34 +176,38 @@ do_trap(int trapnr, int signr, char *str, struct pt_regs *regs,
 #define DO_ERROR(trapnr, signr, str, name)                              \
 dotraplinkage void do_##name(struct pt_regs *regs, long error_code)     \
 {                                                                       \
-        exception_enter(regs);                                          \
+        enum ctx_state prev_state;                                      \
+                                                                        \
+        prev_state = exception_enter();                                 \
         if (notify_die(DIE_TRAP, str, regs, error_code,                 \
                         trapnr, signr) == NOTIFY_STOP) {                \
-                exception_exit(regs);                                   \
+                exception_exit(prev_state);                             \
                 return;                                                 \
         }                                                               \
         conditional_sti(regs);                                          \
         do_trap(trapnr, signr, str, regs, error_code, NULL);            \
-        exception_exit(regs);                                           \
+        exception_exit(prev_state);                                     \
 }
 
 #define DO_ERROR_INFO(trapnr, signr, str, name, sicode, siaddr)         \
 dotraplinkage void do_##name(struct pt_regs *regs, long error_code)     \
 {                                                                       \
         siginfo_t info;                                                 \
+        enum ctx_state prev_state;                                      \
+                                                                        \
         info.si_signo = signr;                                          \
         info.si_errno = 0;                                              \
         info.si_code = sicode;                                          \
         info.si_addr = (void __user *)siaddr;                           \
-        exception_enter(regs);                                          \
+        prev_state = exception_enter();                                 \
         if (notify_die(DIE_TRAP, str, regs, error_code,                 \
                         trapnr, signr) == NOTIFY_STOP) {                \
-                exception_exit(regs);                                   \
+                exception_exit(prev_state);                             \
                 return;                                                 \
         }                                                               \
         conditional_sti(regs);                                          \
         do_trap(trapnr, signr, str, regs, error_code, &info);           \
-        exception_exit(regs);                                           \
+        exception_exit(prev_state);                                     \
 }
 
 DO_ERROR_INFO(X86_TRAP_DE, SIGFPE, "divide error", divide_error, FPE_INTDIV,
@@ -226,14 +230,16 @@ DO_ERROR_INFO(X86_TRAP_AC, SIGBUS, "alignment check", alignment_check,
 /* Runs on IST stack */
 dotraplinkage void do_stack_segment(struct pt_regs *regs, long error_code)
 {
-        exception_enter(regs);
+        enum ctx_state prev_state;
+
+        prev_state = exception_enter();
         if (notify_die(DIE_TRAP, "stack segment", regs, error_code,
                        X86_TRAP_SS, SIGBUS) != NOTIFY_STOP) {
                 preempt_conditional_sti(regs);
                 do_trap(X86_TRAP_SS, SIGBUS, "stack segment", regs, error_code, NULL);
                 preempt_conditional_cli(regs);
         }
-        exception_exit(regs);
+        exception_exit(prev_state);
 }
 
 dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code)
@@ -241,7 +247,7 @@ dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code)
         static const char str[] = "double fault";
         struct task_struct *tsk = current;
 
-        exception_enter(regs);
+        exception_enter();
         /* Return not checked because double check cannot be ignored */
         notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV);
 
@@ -261,8 +267,9 @@ dotraplinkage void __kprobes
 do_general_protection(struct pt_regs *regs, long error_code)
 {
         struct task_struct *tsk;
+        enum ctx_state prev_state;
 
-        exception_enter(regs);
+        prev_state = exception_enter();
         conditional_sti(regs);
 
 #ifdef CONFIG_X86_32
@@ -300,12 +307,14 @@ do_general_protection(struct pt_regs *regs, long error_code)
 
         force_sig(SIGSEGV, tsk);
 exit:
-        exception_exit(regs);
+        exception_exit(prev_state);
 }
 
 /* May run on IST stack. */
 dotraplinkage void __kprobes notrace do_int3(struct pt_regs *regs, long error_code)
 {
+        enum ctx_state prev_state;
+
 #ifdef CONFIG_DYNAMIC_FTRACE
         /*
          * ftrace must be first, everything else may cause a recursive crash.
@@ -315,7 +324,7 @@ dotraplinkage void __kprobes notrace do_int3(struct pt_regs *regs, long error_co
             ftrace_int3_handler(regs))
                 return;
 #endif
-        exception_enter(regs);
+        prev_state = exception_enter();
 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
         if (kgdb_ll_trap(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP,
                                 SIGTRAP) == NOTIFY_STOP)
@@ -336,7 +345,7 @@ dotraplinkage void __kprobes notrace do_int3(struct pt_regs *regs, long error_co
         preempt_conditional_cli(regs);
         debug_stack_usage_dec();
 exit:
-        exception_exit(regs);
+        exception_exit(prev_state);
 }
 
 #ifdef CONFIG_X86_64
@@ -393,11 +402,12 @@ asmlinkage __kprobes struct pt_regs *sync_regs(struct pt_regs *eregs)
 dotraplinkage void __kprobes do_debug(struct pt_regs *regs, long error_code)
 {
         struct task_struct *tsk = current;
+        enum ctx_state prev_state;
         int user_icebp = 0;
         unsigned long dr6;
         int si_code;
 
-        exception_enter(regs);
+        prev_state = exception_enter();
 
         get_debugreg(dr6, 6);
 
@@ -467,7 +477,7 @@ dotraplinkage void __kprobes do_debug(struct pt_regs *regs, long error_code)
         debug_stack_usage_dec();
 
 exit:
-        exception_exit(regs);
+        exception_exit(prev_state);
 }
 
 /*
@@ -561,17 +571,21 @@ void math_error(struct pt_regs *regs, int error_code, int trapnr)
 
 dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code)
 {
-        exception_enter(regs);
+        enum ctx_state prev_state;
+
+        prev_state = exception_enter();
         math_error(regs, error_code, X86_TRAP_MF);
-        exception_exit(regs);
+        exception_exit(prev_state);
 }
 
 dotraplinkage void
 do_simd_coprocessor_error(struct pt_regs *regs, long error_code)
 {
-        exception_enter(regs);
+        enum ctx_state prev_state;
+
+        prev_state = exception_enter();
         math_error(regs, error_code, X86_TRAP_XF);
-        exception_exit(regs);
+        exception_exit(prev_state);
 }
 
 dotraplinkage void
@@ -639,7 +653,9 @@ EXPORT_SYMBOL_GPL(math_state_restore);
 dotraplinkage void __kprobes
 do_device_not_available(struct pt_regs *regs, long error_code)
 {
-        exception_enter(regs);
+        enum ctx_state prev_state;
+
+        prev_state = exception_enter();
         BUG_ON(use_eager_fpu());
 
 #ifdef CONFIG_MATH_EMULATION
@@ -650,7 +666,7 @@ do_device_not_available(struct pt_regs *regs, long error_code)
 
                 info.regs = regs;
                 math_emulate(&info);
-                exception_exit(regs);
+                exception_exit(prev_state);
                 return;
         }
 #endif
@@ -658,15 +674,16 @@ do_device_not_available(struct pt_regs *regs, long error_code)
 #ifdef CONFIG_X86_32
         conditional_sti(regs);
 #endif
-        exception_exit(regs);
+        exception_exit(prev_state);
 }
 
 #ifdef CONFIG_X86_32
 dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code)
 {
         siginfo_t info;
+        enum ctx_state prev_state;
 
-        exception_enter(regs);
+        prev_state = exception_enter();
         local_irq_enable();
 
         info.si_signo = SIGILL;
@@ -678,7 +695,7 @@ dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code)
                 do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, error_code,
                         &info);
         }
-        exception_exit(regs);
+        exception_exit(prev_state);
 }
 #endif
 
@@ -753,6 +770,14 @@ void __init trap_init(void)
 #endif
 
         /*
+         * Set the IDT descriptor to a fixed read-only location, so that the
+         * "sidt" instruction will not leak the location of the kernel, and
+         * to defend the IDT against arbitrary memory write vulnerabilities.
+         * It will be reloaded in cpu_init() */
+        __set_fixmap(FIX_RO_IDT, __pa_symbol(idt_table), PAGE_KERNEL_RO);
+        idt_descr.address = fix_to_virt(FIX_RO_IDT);
+
+        /*
          * Should be a barrier for any external CPU state:
          */
         cpu_init();
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 4b9ea101fe3b..098b3cfda72e 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -768,7 +768,8 @@ static cycle_t read_tsc(struct clocksource *cs)
 
 static void resume_tsc(struct clocksource *cs)
 {
-        clocksource_tsc.cycle_last = 0;
+        if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
+                clocksource_tsc.cycle_last = 0;
 }
 
 static struct clocksource clocksource_tsc = {
@@ -939,6 +940,9 @@ static int __init init_tsc_clocksource(void)
                 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
         }
 
+        if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
+                clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
+
         /*
          * Trust the results of the earlier calibration on systems
          * exporting a reliable TSC.
diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c
index 0ba4cfb4f412..2ed845928b5f 100644
--- a/arch/x86/kernel/uprobes.c
+++ b/arch/x86/kernel/uprobes.c
@@ -697,3 +697,32 @@ bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
                 send_sig(SIGTRAP, current, 0);
         return ret;
 }
+
+unsigned long
+arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs)
+{
+        int rasize, ncopied;
+        unsigned long orig_ret_vaddr = 0; /* clear high bits for 32-bit apps */
+
+        rasize = is_ia32_task() ? 4 : 8;
+        ncopied = copy_from_user(&orig_ret_vaddr, (void __user *)regs->sp, rasize);
+        if (unlikely(ncopied))
+                return -1;
+
+        /* check whether address has been already hijacked */
+        if (orig_ret_vaddr == trampoline_vaddr)
+                return orig_ret_vaddr;
+
+        ncopied = copy_to_user((void __user *)regs->sp, &trampoline_vaddr, rasize);
+        if (likely(!ncopied))
+                return orig_ret_vaddr;
+
+        if (ncopied != rasize) {
+                pr_err("uprobe: return address clobbered: pid=%d, %%sp=%#lx, "
+                        "%%ip=%#lx\n", current->pid, regs->sp, regs->ip);
+
+                force_sig_info(SIGSEGV, SEND_SIG_FORCED, current);
+        }
+
+        return -1;
+}
diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S
index 22a1530146a8..10c4f3006afd 100644
--- a/arch/x86/kernel/vmlinux.lds.S
+++ b/arch/x86/kernel/vmlinux.lds.S
@@ -94,10 +94,6 @@ SECTIONS
                 _text = .;
                 /* bootstrapping code */
                 HEAD_TEXT
-#ifdef CONFIG_X86_32
-                . = ALIGN(PAGE_SIZE);
-                *(.text..page_aligned)
-#endif
                 . = ALIGN(8);
                 _stext = .;
                 TEXT_TEXT
diff --git a/arch/x86/kvm/Kconfig b/arch/x86/kvm/Kconfig
index 586f00059805..a47a3e54b964 100644
--- a/arch/x86/kvm/Kconfig
+++ b/arch/x86/kvm/Kconfig
@@ -21,14 +21,13 @@ config KVM
         tristate "Kernel-based Virtual Machine (KVM) support"
         depends on HAVE_KVM
         depends on HIGH_RES_TIMERS
-        # for device assignment:
-        depends on PCI
         # for TASKSTATS/TASK_DELAY_ACCT:
         depends on NET
         select PREEMPT_NOTIFIERS
         select MMU_NOTIFIER
         select ANON_INODES
         select HAVE_KVM_IRQCHIP
+        select HAVE_KVM_IRQ_ROUTING
         select HAVE_KVM_EVENTFD
         select KVM_APIC_ARCHITECTURE
         select KVM_ASYNC_PF
@@ -82,6 +81,17 @@ config KVM_MMU_AUDIT
          This option adds a R/W kVM module parameter 'mmu_audit', which allows
          audit  KVM MMU at runtime.
 
+config KVM_DEVICE_ASSIGNMENT
+        bool "KVM legacy PCI device assignment support"
+        depends on KVM && PCI && IOMMU_API
+        default y
+        ---help---
+          Provide support for legacy PCI device assignment through KVM.  The
+          kernel now also supports a full featured userspace device driver
+          framework through VFIO, which supersedes much of this support.
+
+          If unsure, say Y.
+
 # OK, it's a little counter-intuitive to do this, but it puts it neatly under
 # the virtualization menu.
 source drivers/vhost/Kconfig
diff --git a/arch/x86/kvm/Makefile b/arch/x86/kvm/Makefile
index 04d30401c5cb..d609e1d84048 100644
--- a/arch/x86/kvm/Makefile
+++ b/arch/x86/kvm/Makefile
@@ -7,8 +7,9 @@ CFLAGS_vmx.o := -I.
 
 kvm-y                   += $(addprefix ../../../virt/kvm/, kvm_main.o ioapic.o \
                                 coalesced_mmio.o irq_comm.o eventfd.o \
-                                assigned-dev.o)
-kvm-$(CONFIG_IOMMU_API) += $(addprefix ../../../virt/kvm/, iommu.o)
+                                irqchip.o)
+kvm-$(CONFIG_KVM_DEVICE_ASSIGNMENT)     += $(addprefix ../../../virt/kvm/, \
+                                assigned-dev.o iommu.o)
 kvm-$(CONFIG_KVM_ASYNC_PF)      += $(addprefix ../../../virt/kvm/, async_pf.o)
 
 kvm-y                   += x86.o mmu.o emulate.o i8259.o irq.o lapic.o \
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index a335cc6cde72..8e517bba6a7c 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -132,8 +132,9 @@
 #define Priv        (1<<27) /* instruction generates #GP if current CPL != 0 */
 #define No64        (1<<28)
 #define PageTable   (1 << 29)   /* instruction used to write page table */
+#define NotImpl     (1 << 30)   /* instruction is not implemented */
 /* Source 2 operand type */
-#define Src2Shift   (30)
+#define Src2Shift   (31)
 #define Src2None    (OpNone << Src2Shift)
 #define Src2CL      (OpCL << Src2Shift)
 #define Src2ImmByte (OpImmByte << Src2Shift)
@@ -1578,12 +1579,21 @@ static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
 
         memset(&seg_desc, 0, sizeof seg_desc);
 
-        if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
-            || ctxt->mode == X86EMUL_MODE_REAL) {
-                /* set real mode segment descriptor */
+        if (ctxt->mode == X86EMUL_MODE_REAL) {
+                /* set real mode segment descriptor (keep limit etc. for
+                 * unreal mode) */
                 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
                 set_desc_base(&seg_desc, selector << 4);
                 goto load;
+        } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
+                /* VM86 needs a clean new segment descriptor */
+                set_desc_base(&seg_desc, selector << 4);
+                set_desc_limit(&seg_desc, 0xffff);
+                seg_desc.type = 3;
+                seg_desc.p = 1;
+                seg_desc.s = 1;
+                seg_desc.dpl = 3;
+                goto load;
         }
 
         rpl = selector & 3;
@@ -3615,7 +3625,7 @@ static int check_perm_out(struct x86_emulate_ctxt *ctxt)
 #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
 #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
                       .check_perm = (_p) }
-#define N    D(0)
+#define N    D(NotImpl)
 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
@@ -3713,7 +3723,7 @@ static const struct opcode group5[] = {
         I(SrcMemFAddr | ImplicitOps | Stack,    em_call_far),
         I(SrcMem | Stack,                       em_grp45),
         I(SrcMemFAddr | ImplicitOps,            em_grp45),
-        I(SrcMem | Stack,                       em_grp45), N,
+        I(SrcMem | Stack,                       em_grp45), D(Undefined),
 };
 
 static const struct opcode group6[] = {
@@ -4162,6 +4172,10 @@ static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
                 break;
         case OpMem8:
                 ctxt->memop.bytes = 1;
+                if (ctxt->memop.type == OP_REG) {
+                        ctxt->memop.addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1);
+                        fetch_register_operand(&ctxt->memop);
+                }
                 goto mem_common;
         case OpMem16:
                 ctxt->memop.bytes = 2;
@@ -4373,7 +4387,7 @@ done_prefixes:
         ctxt->intercept = opcode.intercept;
 
         /* Unrecognised? */
-        if (ctxt->d == 0 || (ctxt->d & Undefined))
+        if (ctxt->d == 0 || (ctxt->d & NotImpl))
                 return EMULATION_FAILED;
 
         if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
@@ -4511,7 +4525,8 @@ int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
 
         ctxt->mem_read.pos = 0;
 
-        if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
+        if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
+                        (ctxt->d & Undefined)) {
                 rc = emulate_ud(ctxt);
                 goto done;
         }
diff --git a/arch/x86/kvm/i8254.c b/arch/x86/kvm/i8254.c
index c1d30b2fc9bb..412a5aa0ef94 100644
--- a/arch/x86/kvm/i8254.c
+++ b/arch/x86/kvm/i8254.c
@@ -290,8 +290,8 @@ static void pit_do_work(struct kthread_work *work)
         }
         spin_unlock(&ps->inject_lock);
         if (inject) {
-                kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1);
-                kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0);
+                kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1, false);
+                kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0, false);
 
                 /*
                  * Provides NMI watchdog support via Virtual Wire mode.
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index f77df1c5de6e..e1adbb4aca75 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -94,6 +94,14 @@ static inline int apic_test_vector(int vec, void *bitmap)
         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 }
 
+bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
+{
+        struct kvm_lapic *apic = vcpu->arch.apic;
+
+        return apic_test_vector(vector, apic->regs + APIC_ISR) ||
+                apic_test_vector(vector, apic->regs + APIC_IRR);
+}
+
 static inline void apic_set_vector(int vec, void *bitmap)
 {
         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
@@ -145,53 +153,6 @@ static inline int kvm_apic_id(struct kvm_lapic *apic)
         return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 }
 
-void kvm_calculate_eoi_exitmap(struct kvm_vcpu *vcpu,
-                                struct kvm_lapic_irq *irq,
-                                u64 *eoi_exit_bitmap)
-{
-        struct kvm_lapic **dst;
-        struct kvm_apic_map *map;
-        unsigned long bitmap = 1;
-        int i;
-
-        rcu_read_lock();
-        map = rcu_dereference(vcpu->kvm->arch.apic_map);
-
-        if (unlikely(!map)) {
-                __set_bit(irq->vector, (unsigned long *)eoi_exit_bitmap);
-                goto out;
-        }
-
-        if (irq->dest_mode == 0) { /* physical mode */
-                if (irq->delivery_mode == APIC_DM_LOWEST ||
-                                irq->dest_id == 0xff) {
-                        __set_bit(irq->vector,
-                                  (unsigned long *)eoi_exit_bitmap);
-                        goto out;
-                }
-                dst = &map->phys_map[irq->dest_id & 0xff];
-        } else {
-                u32 mda = irq->dest_id << (32 - map->ldr_bits);
-
-                dst = map->logical_map[apic_cluster_id(map, mda)];
-
-                bitmap = apic_logical_id(map, mda);
-        }
-
-        for_each_set_bit(i, &bitmap, 16) {
-                if (!dst[i])
-                        continue;
-                if (dst[i]->vcpu == vcpu) {
-                        __set_bit(irq->vector,
-                                  (unsigned long *)eoi_exit_bitmap);
-                        break;
-                }
-        }
-
-out:
-        rcu_read_unlock();
-}
-
 static void recalculate_apic_map(struct kvm *kvm)
 {
         struct kvm_apic_map *new, *old = NULL;
@@ -256,7 +217,7 @@ out:
         if (old)
                 kfree_rcu(old, rcu);
 
-        kvm_ioapic_make_eoibitmap_request(kvm);
+        kvm_vcpu_request_scan_ioapic(kvm);
 }
 
 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
@@ -357,6 +318,19 @@ static u8 count_vectors(void *bitmap)
         return count;
 }
 
+void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
+{
+        u32 i, pir_val;
+        struct kvm_lapic *apic = vcpu->arch.apic;
+
+        for (i = 0; i <= 7; i++) {
+                pir_val = xchg(&pir[i], 0);
+                if (pir_val)
+                        *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
+        }
+}
+EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
+
 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 {
         apic->irr_pending = true;
@@ -379,6 +353,7 @@ static inline int apic_find_highest_irr(struct kvm_lapic *apic)
         if (!apic->irr_pending)
                 return -1;
 
+        kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
         result = apic_search_irr(apic);
         ASSERT(result == -1 || result >= 16);
 
@@ -431,14 +406,16 @@ int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 }
 
 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
-                             int vector, int level, int trig_mode);
+                             int vector, int level, int trig_mode,
+                             unsigned long *dest_map);
 
-int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
+int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
+                unsigned long *dest_map)
 {
         struct kvm_lapic *apic = vcpu->arch.apic;
 
         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
-                        irq->level, irq->trig_mode);
+                        irq->level, irq->trig_mode, dest_map);
 }
 
 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
@@ -505,6 +482,15 @@ static inline int apic_find_highest_isr(struct kvm_lapic *apic)
         return result;
 }
 
+void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
+{
+        struct kvm_lapic *apic = vcpu->arch.apic;
+        int i;
+
+        for (i = 0; i < 8; i++)
+                apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
+}
+
 static void apic_update_ppr(struct kvm_lapic *apic)
 {
         u32 tpr, isrv, ppr, old_ppr;
@@ -611,7 +597,7 @@ int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 }
 
 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
-                struct kvm_lapic_irq *irq, int *r)
+                struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
 {
         struct kvm_apic_map *map;
         unsigned long bitmap = 1;
@@ -622,7 +608,7 @@ bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
         *r = -1;
 
         if (irq->shorthand == APIC_DEST_SELF) {
-                *r = kvm_apic_set_irq(src->vcpu, irq);
+                *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
                 return true;
         }
 
@@ -667,7 +653,7 @@ bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
                         continue;
                 if (*r < 0)
                         *r = 0;
-                *r += kvm_apic_set_irq(dst[i]->vcpu, irq);
+                *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
         }
 
         ret = true;
@@ -681,7 +667,8 @@ out:
  * Return 1 if successfully added and 0 if discarded.
  */
 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
-                             int vector, int level, int trig_mode)
+                             int vector, int level, int trig_mode,
+                             unsigned long *dest_map)
 {
         int result = 0;
         struct kvm_vcpu *vcpu = apic->vcpu;
@@ -694,24 +681,28 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
                 if (unlikely(!apic_enabled(apic)))
                         break;
 
-                if (trig_mode) {
-                        apic_debug("level trig mode for vector %d", vector);
-                        apic_set_vector(vector, apic->regs + APIC_TMR);
-                } else
-                        apic_clear_vector(vector, apic->regs + APIC_TMR);
+                if (dest_map)
+                        __set_bit(vcpu->vcpu_id, dest_map);
 
-                result = !apic_test_and_set_irr(vector, apic);
-                trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
-                                          trig_mode, vector, !result);
-                if (!result) {
-                        if (trig_mode)
-                                apic_debug("level trig mode repeatedly for "
-                                                "vector %d", vector);
-                        break;
-                }
+                if (kvm_x86_ops->deliver_posted_interrupt) {
+                        result = 1;
+                        kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
+                } else {
+                        result = !apic_test_and_set_irr(vector, apic);
 
-                kvm_make_request(KVM_REQ_EVENT, vcpu);
-                kvm_vcpu_kick(vcpu);
+                        if (!result) {
+                                if (trig_mode)
+                                        apic_debug("level trig mode repeatedly "
+                                                "for vector %d", vector);
+                                goto out;
+                        }
+
+                        kvm_make_request(KVM_REQ_EVENT, vcpu);
+                        kvm_vcpu_kick(vcpu);
+                }
+out:
+                trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
+                                trig_mode, vector, !result);
                 break;
 
         case APIC_DM_REMRD:
@@ -731,7 +722,11 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
         case APIC_DM_INIT:
                 if (!trig_mode || level) {
                         result = 1;
-                        vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
+                        /* assumes that there are only KVM_APIC_INIT/SIPI */
+                        apic->pending_events = (1UL << KVM_APIC_INIT);
+                        /* make sure pending_events is visible before sending
+                         * the request */
+                        smp_wmb();
                         kvm_make_request(KVM_REQ_EVENT, vcpu);
                         kvm_vcpu_kick(vcpu);
                 } else {
@@ -743,13 +738,13 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
         case APIC_DM_STARTUP:
                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
                            vcpu->vcpu_id, vector);
-                if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
-                        result = 1;
-                        vcpu->arch.sipi_vector = vector;
-                        vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
-                        kvm_make_request(KVM_REQ_EVENT, vcpu);
-                        kvm_vcpu_kick(vcpu);
-                }
+                result = 1;
+                apic->sipi_vector = vector;
+                /* make sure sipi_vector is visible for the receiver */
+                smp_wmb();
+                set_bit(KVM_APIC_SIPI, &apic->pending_events);
+                kvm_make_request(KVM_REQ_EVENT, vcpu);
+                kvm_vcpu_kick(vcpu);
                 break;
 
         case APIC_DM_EXTINT:
@@ -782,7 +777,7 @@ static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
                         trigger_mode = IOAPIC_LEVEL_TRIG;
                 else
                         trigger_mode = IOAPIC_EDGE_TRIG;
-                kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
+                kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
         }
 }
 
@@ -848,7 +843,7 @@ static void apic_send_ipi(struct kvm_lapic *apic)
                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
                    irq.vector);
 
-        kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
+        kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
 }
 
 static u32 apic_get_tmcct(struct kvm_lapic *apic)
@@ -1484,7 +1479,8 @@ int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
                 vector = reg & APIC_VECTOR_MASK;
                 mode = reg & APIC_MODE_MASK;
                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
-                return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
+                return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
+                                        NULL);
         }
         return 0;
 }
@@ -1654,6 +1650,7 @@ void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
         apic->highest_isr_cache = -1;
         kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic));
         kvm_make_request(KVM_REQ_EVENT, vcpu);
+        kvm_rtc_eoi_tracking_restore_one(vcpu);
 }
 
 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
@@ -1860,6 +1857,34 @@ int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
                                          addr, sizeof(u8));
 }
 
+void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
+{
+        struct kvm_lapic *apic = vcpu->arch.apic;
+        unsigned int sipi_vector;
+
+        if (!kvm_vcpu_has_lapic(vcpu))
+                return;
+
+        if (test_and_clear_bit(KVM_APIC_INIT, &apic->pending_events)) {
+                kvm_lapic_reset(vcpu);
+                kvm_vcpu_reset(vcpu);
+                if (kvm_vcpu_is_bsp(apic->vcpu))
+                        vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
+                else
+                        vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
+        }
+        if (test_and_clear_bit(KVM_APIC_SIPI, &apic->pending_events) &&
+            vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
+                /* evaluate pending_events before reading the vector */
+                smp_rmb();
+                sipi_vector = apic->sipi_vector;
+                pr_debug("vcpu %d received sipi with vector # %x\n",
+                         vcpu->vcpu_id, sipi_vector);
+                kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
+                vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
+        }
+}
+
 void kvm_lapic_init(void)
 {
         /* do not patch jump label more than once per second */
diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
index 1676d34ddb4e..c730ac9fe801 100644
--- a/arch/x86/kvm/lapic.h
+++ b/arch/x86/kvm/lapic.h
@@ -5,6 +5,9 @@
 
 #include <linux/kvm_host.h>
 
+#define KVM_APIC_INIT           0
+#define KVM_APIC_SIPI           1
+
 struct kvm_timer {
         struct hrtimer timer;
         s64 period;                             /* unit: ns */
@@ -32,6 +35,8 @@ struct kvm_lapic {
         void *regs;
         gpa_t vapic_addr;
         struct page *vapic_page;
+        unsigned long pending_events;
+        unsigned int sipi_vector;
 };
 int kvm_create_lapic(struct kvm_vcpu *vcpu);
 void kvm_free_lapic(struct kvm_vcpu *vcpu);
@@ -39,6 +44,7 @@ void kvm_free_lapic(struct kvm_vcpu *vcpu);
 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
+void kvm_apic_accept_events(struct kvm_vcpu *vcpu);
 void kvm_lapic_reset(struct kvm_vcpu *vcpu);
 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
@@ -47,13 +53,16 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
 void kvm_apic_set_version(struct kvm_vcpu *vcpu);
 
+void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr);
+void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir);
 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest);
 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda);
-int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq);
+int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
+                unsigned long *dest_map);
 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
 
 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
-                struct kvm_lapic_irq *irq, int *r);
+                struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map);
 
 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data);
@@ -154,8 +163,11 @@ static inline u16 apic_logical_id(struct kvm_apic_map *map, u32 ldr)
         return ldr & map->lid_mask;
 }
 
-void kvm_calculate_eoi_exitmap(struct kvm_vcpu *vcpu,
-                                struct kvm_lapic_irq *irq,
-                                u64 *eoi_bitmap);
+static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
+{
+        return vcpu->arch.apic->pending_events;
+}
+
+bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
 
 #endif
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 956ca358108a..004cc87b781c 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -199,8 +199,11 @@ EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
 
 static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access)
 {
+        struct kvm_mmu_page *sp =  page_header(__pa(sptep));
+
         access &= ACC_WRITE_MASK | ACC_USER_MASK;
 
+        sp->mmio_cached = true;
         trace_mark_mmio_spte(sptep, gfn, access);
         mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT);
 }
@@ -1502,6 +1505,7 @@ static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
                                                u64 *parent_pte, int direct)
 {
         struct kvm_mmu_page *sp;
+
         sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
         sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
         if (!direct)
@@ -1644,16 +1648,14 @@ static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
                                     struct list_head *invalid_list);
 
-#define for_each_gfn_sp(kvm, sp, gfn)                                   \
-  hlist_for_each_entry(sp,                                              \
-   &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
-        if ((sp)->gfn != (gfn)) {} else
+#define for_each_gfn_sp(_kvm, _sp, _gfn)                                \
+        hlist_for_each_entry(_sp,                                       \
+          &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
+                if ((_sp)->gfn != (_gfn)) {} else
 
-#define for_each_gfn_indirect_valid_sp(kvm, sp, gfn)                    \
-  hlist_for_each_entry(sp,                                              \
-   &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
-                if ((sp)->gfn != (gfn) || (sp)->role.direct ||          \
-                        (sp)->role.invalid) {} else
+#define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn)                 \
+        for_each_gfn_sp(_kvm, _sp, _gfn)                                \
+                if ((_sp)->role.direct || (_sp)->role.invalid) {} else
 
 /* @sp->gfn should be write-protected at the call site */
 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
@@ -2089,7 +2091,7 @@ static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
                                     struct list_head *invalid_list)
 {
-        struct kvm_mmu_page *sp;
+        struct kvm_mmu_page *sp, *nsp;
 
         if (list_empty(invalid_list))
                 return;
@@ -2106,11 +2108,25 @@ static void kvm_mmu_commit_zap_page(struct kvm *kvm,
          */
         kvm_flush_remote_tlbs(kvm);
 
-        do {
-                sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
+        list_for_each_entry_safe(sp, nsp, invalid_list, link) {
                 WARN_ON(!sp->role.invalid || sp->root_count);
                 kvm_mmu_free_page(sp);
-        } while (!list_empty(invalid_list));
+        }
+}
+
+static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
+                                        struct list_head *invalid_list)
+{
+        struct kvm_mmu_page *sp;
+
+        if (list_empty(&kvm->arch.active_mmu_pages))
+                return false;
+
+        sp = list_entry(kvm->arch.active_mmu_pages.prev,
+                        struct kvm_mmu_page, link);
+        kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
+
+        return true;
 }
 
 /*
@@ -2120,23 +2136,15 @@ static void kvm_mmu_commit_zap_page(struct kvm *kvm,
 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
 {
         LIST_HEAD(invalid_list);
-        /*
-         * If we set the number of mmu pages to be smaller be than the
-         * number of actived pages , we must to free some mmu pages before we
-         * change the value
-         */
 
         spin_lock(&kvm->mmu_lock);
 
         if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
-                while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
-                        !list_empty(&kvm->arch.active_mmu_pages)) {
-                        struct kvm_mmu_page *page;
+                /* Need to free some mmu pages to achieve the goal. */
+                while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
+                        if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
+                                break;
 
-                        page = container_of(kvm->arch.active_mmu_pages.prev,
-                                            struct kvm_mmu_page, link);
-                        kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
-                }
                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
                 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
         }
@@ -2794,6 +2802,7 @@ exit:
 
 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
                          gva_t gva, pfn_t *pfn, bool write, bool *writable);
+static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
 
 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
                          gfn_t gfn, bool prefault)
@@ -2835,7 +2844,7 @@ static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
         spin_lock(&vcpu->kvm->mmu_lock);
         if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
                 goto out_unlock;
-        kvm_mmu_free_some_pages(vcpu);
+        make_mmu_pages_available(vcpu);
         if (likely(!force_pt_level))
                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
         r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
@@ -2913,7 +2922,7 @@ static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
 
         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
                 spin_lock(&vcpu->kvm->mmu_lock);
-                kvm_mmu_free_some_pages(vcpu);
+                make_mmu_pages_available(vcpu);
                 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
                                       1, ACC_ALL, NULL);
                 ++sp->root_count;
@@ -2925,7 +2934,7 @@ static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
 
                         ASSERT(!VALID_PAGE(root));
                         spin_lock(&vcpu->kvm->mmu_lock);
-                        kvm_mmu_free_some_pages(vcpu);
+                        make_mmu_pages_available(vcpu);
                         sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
                                               i << 30,
                                               PT32_ROOT_LEVEL, 1, ACC_ALL,
@@ -2964,7 +2973,7 @@ static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
                 ASSERT(!VALID_PAGE(root));
 
                 spin_lock(&vcpu->kvm->mmu_lock);
-                kvm_mmu_free_some_pages(vcpu);
+                make_mmu_pages_available(vcpu);
                 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
                                       0, ACC_ALL, NULL);
                 root = __pa(sp->spt);
@@ -2998,7 +3007,7 @@ static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
                                 return 1;
                 }
                 spin_lock(&vcpu->kvm->mmu_lock);
-                kvm_mmu_free_some_pages(vcpu);
+                make_mmu_pages_available(vcpu);
                 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
                                       PT32_ROOT_LEVEL, 0,
                                       ACC_ALL, NULL);
@@ -3304,7 +3313,7 @@ static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
         spin_lock(&vcpu->kvm->mmu_lock);
         if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
                 goto out_unlock;
-        kvm_mmu_free_some_pages(vcpu);
+        make_mmu_pages_available(vcpu);
         if (likely(!force_pt_level))
                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
         r = __direct_map(vcpu, gpa, write, map_writable,
@@ -4006,17 +4015,17 @@ int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
 }
 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
 
-void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
+static void make_mmu_pages_available(struct kvm_vcpu *vcpu)
 {
         LIST_HEAD(invalid_list);
 
-        while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
-               !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
-                struct kvm_mmu_page *sp;
+        if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
+                return;
+
+        while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
+                if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
+                        break;
 
-                sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
-                                  struct kvm_mmu_page, link);
-                kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
                 ++vcpu->kvm->stat.mmu_recycled;
         }
         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
@@ -4185,17 +4194,22 @@ restart:
         spin_unlock(&kvm->mmu_lock);
 }
 
-static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
-                                                struct list_head *invalid_list)
+void kvm_mmu_zap_mmio_sptes(struct kvm *kvm)
 {
-        struct kvm_mmu_page *page;
+        struct kvm_mmu_page *sp, *node;
+        LIST_HEAD(invalid_list);
 
-        if (list_empty(&kvm->arch.active_mmu_pages))
-                return;
+        spin_lock(&kvm->mmu_lock);
+restart:
+        list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
+                if (!sp->mmio_cached)
+                        continue;
+                if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
+                        goto restart;
+        }
 
-        page = container_of(kvm->arch.active_mmu_pages.prev,
-                            struct kvm_mmu_page, link);
-        kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
+        kvm_mmu_commit_zap_page(kvm, &invalid_list);
+        spin_unlock(&kvm->mmu_lock);
 }
 
 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
@@ -4232,7 +4246,7 @@ static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
                 idx = srcu_read_lock(&kvm->srcu);
                 spin_lock(&kvm->mmu_lock);
 
-                kvm_mmu_remove_some_alloc_mmu_pages(kvm, &invalid_list);
+                prepare_zap_oldest_mmu_page(kvm, &invalid_list);
                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
 
                 spin_unlock(&kvm->mmu_lock);
diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h
index 69871080e866..2adcbc2cac6d 100644
--- a/arch/x86/kvm/mmu.h
+++ b/arch/x86/kvm/mmu.h
@@ -57,14 +57,11 @@ int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context);
 
 static inline unsigned int kvm_mmu_available_pages(struct kvm *kvm)
 {
-        return kvm->arch.n_max_mmu_pages -
-                kvm->arch.n_used_mmu_pages;
-}
+        if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
+                return kvm->arch.n_max_mmu_pages -
+                        kvm->arch.n_used_mmu_pages;
 
-static inline void kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
-{
-        if (unlikely(kvm_mmu_available_pages(vcpu->kvm)< KVM_MIN_FREE_MMU_PAGES))
-                __kvm_mmu_free_some_pages(vcpu);
+        return 0;
 }
 
 static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h
index 105dd5bd550e..da20860b457a 100644
--- a/arch/x86/kvm/paging_tmpl.h
+++ b/arch/x86/kvm/paging_tmpl.h
@@ -627,7 +627,7 @@ static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
                 goto out_unlock;
 
         kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
-        kvm_mmu_free_some_pages(vcpu);
+        make_mmu_pages_available(vcpu);
         if (!force_pt_level)
                 transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
         r = FNAME(fetch)(vcpu, addr, &walker, write_fault,
diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
index cfc258a6bf97..c53e797e7369 100644
--- a/arch/x86/kvm/pmu.c
+++ b/arch/x86/kvm/pmu.c
@@ -360,10 +360,12 @@ int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
         return 1;
 }
 
-int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
+int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 {
         struct kvm_pmu *pmu = &vcpu->arch.pmu;
         struct kvm_pmc *pmc;
+        u32 index = msr_info->index;
+        u64 data = msr_info->data;
 
         switch (index) {
         case MSR_CORE_PERF_FIXED_CTR_CTRL:
@@ -375,6 +377,10 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
                 }
                 break;
         case MSR_CORE_PERF_GLOBAL_STATUS:
+                if (msr_info->host_initiated) {
+                        pmu->global_status = data;
+                        return 0;
+                }
                 break; /* RO MSR */
         case MSR_CORE_PERF_GLOBAL_CTRL:
                 if (pmu->global_ctrl == data)
@@ -386,7 +392,8 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
                 break;
         case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
                 if (!(data & (pmu->global_ctrl_mask & ~(3ull<<62)))) {
-                        pmu->global_status &= ~data;
+                        if (!msr_info->host_initiated)
+                                pmu->global_status &= ~data;
                         pmu->global_ovf_ctrl = data;
                         return 0;
                 }
@@ -394,7 +401,8 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
         default:
                 if ((pmc = get_gp_pmc(pmu, index, MSR_IA32_PERFCTR0)) ||
                                 (pmc = get_fixed_pmc(pmu, index))) {
-                        data = (s64)(s32)data;
+                        if (!msr_info->host_initiated)
+                                data = (s64)(s32)data;
                         pmc->counter += data - read_pmc(pmc);
                         return 0;
                 } else if ((pmc = get_gp_pmc(pmu, index, MSR_P6_EVNTSEL0))) {
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index e1b1ce21bc00..a14a6eaf871d 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -555,7 +555,7 @@ static void svm_init_erratum_383(void)
         int err;
         u64 val;
 
-        if (!cpu_has_amd_erratum(amd_erratum_383))
+        if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
                 return;
 
         /* Use _safe variants to not break nested virtualization */
@@ -1131,17 +1131,11 @@ static void init_vmcb(struct vcpu_svm *svm)
         init_seg(&save->gs);
 
         save->cs.selector = 0xf000;
+        save->cs.base = 0xffff0000;
         /* Executable/Readable Code Segment */
         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
         save->cs.limit = 0xffff;
-        /*
-         * cs.base should really be 0xffff0000, but vmx can't handle that, so
-         * be consistent with it.
-         *
-         * Replace when we have real mode working for vmx.
-         */
-        save->cs.base = 0xf0000;
 
         save->gdtr.limit = 0xffff;
         save->idtr.limit = 0xffff;
@@ -1191,7 +1185,7 @@ static void init_vmcb(struct vcpu_svm *svm)
         enable_gif(svm);
 }
 
-static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
+static void svm_vcpu_reset(struct kvm_vcpu *vcpu)
 {
         struct vcpu_svm *svm = to_svm(vcpu);
         u32 dummy;
@@ -1199,16 +1193,8 @@ static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 
         init_vmcb(svm);
 
-        if (!kvm_vcpu_is_bsp(vcpu)) {
-                kvm_rip_write(vcpu, 0);
-                svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
-                svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
-        }
-
         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
         kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
-
-        return 0;
 }
 
 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
@@ -3487,7 +3473,7 @@ static int handle_exit(struct kvm_vcpu *vcpu)
             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
-                printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
+                printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
                        "exit_code 0x%x\n",
                        __func__, svm->vmcb->control.exit_int_info,
                        exit_code);
@@ -3591,6 +3577,11 @@ static void svm_hwapic_isr_update(struct kvm *kvm, int isr)
         return;
 }
 
+static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
+{
+        return;
+}
+
 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
 {
         struct vcpu_svm *svm = to_svm(vcpu);
@@ -3641,7 +3632,7 @@ static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
         return ret;
 }
 
-static void enable_irq_window(struct kvm_vcpu *vcpu)
+static int enable_irq_window(struct kvm_vcpu *vcpu)
 {
         struct vcpu_svm *svm = to_svm(vcpu);
 
@@ -3655,15 +3646,16 @@ static void enable_irq_window(struct kvm_vcpu *vcpu)
                 svm_set_vintr(svm);
                 svm_inject_irq(svm, 0x0);
         }
+        return 0;
 }
 
-static void enable_nmi_window(struct kvm_vcpu *vcpu)
+static int enable_nmi_window(struct kvm_vcpu *vcpu)
 {
         struct vcpu_svm *svm = to_svm(vcpu);
 
         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
             == HF_NMI_MASK)
-                return; /* IRET will cause a vm exit */
+                return 0; /* IRET will cause a vm exit */
 
         /*
          * Something prevents NMI from been injected. Single step over possible
@@ -3672,6 +3664,7 @@ static void enable_nmi_window(struct kvm_vcpu *vcpu)
         svm->nmi_singlestep = true;
         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
         update_db_bp_intercept(vcpu);
+        return 0;
 }
 
 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
@@ -4247,6 +4240,11 @@ out:
         return ret;
 }
 
+static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
+{
+        local_irq_enable();
+}
+
 static struct kvm_x86_ops svm_x86_ops = {
         .cpu_has_kvm_support = has_svm,
         .disabled_by_bios = is_disabled,
@@ -4314,6 +4312,7 @@ static struct kvm_x86_ops svm_x86_ops = {
         .vm_has_apicv = svm_vm_has_apicv,
         .load_eoi_exitmap = svm_load_eoi_exitmap,
         .hwapic_isr_update = svm_hwapic_isr_update,
+        .sync_pir_to_irr = svm_sync_pir_to_irr,
 
         .set_tss_addr = svm_set_tss_addr,
         .get_tdp_level = get_npt_level,
@@ -4342,6 +4341,7 @@ static struct kvm_x86_ops svm_x86_ops = {
         .set_tdp_cr3 = set_tdp_cr3,
 
         .check_intercept = svm_check_intercept,
+        .handle_external_intr = svm_handle_external_intr,
 };
 
 static int __init svm_init(void)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 6667042714cc..25a791ed21c8 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -84,8 +84,11 @@ module_param(vmm_exclusive, bool, S_IRUGO);
 static bool __read_mostly fasteoi = 1;
 module_param(fasteoi, bool, S_IRUGO);
 
-static bool __read_mostly enable_apicv_reg_vid;
+static bool __read_mostly enable_apicv = 1;
+module_param(enable_apicv, bool, S_IRUGO);
 
+static bool __read_mostly enable_shadow_vmcs = 1;
+module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
 /*
  * If nested=1, nested virtualization is supported, i.e., guests may use
  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
@@ -298,7 +301,8 @@ struct __packed vmcs12 {
         u32 guest_activity_state;
         u32 guest_sysenter_cs;
         u32 host_ia32_sysenter_cs;
-        u32 padding32[8]; /* room for future expansion */
+        u32 vmx_preemption_timer_value;
+        u32 padding32[7]; /* room for future expansion */
         u16 virtual_processor_id;
         u16 guest_es_selector;
         u16 guest_cs_selector;
@@ -351,6 +355,12 @@ struct nested_vmx {
         /* The host-usable pointer to the above */
         struct page *current_vmcs12_page;
         struct vmcs12 *current_vmcs12;
+        struct vmcs *current_shadow_vmcs;
+        /*
+         * Indicates if the shadow vmcs must be updated with the
+         * data hold by vmcs12
+         */
+        bool sync_shadow_vmcs;
 
         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
         struct list_head vmcs02_pool;
@@ -365,6 +375,31 @@ struct nested_vmx {
         struct page *apic_access_page;
 };
 
+#define POSTED_INTR_ON  0
+/* Posted-Interrupt Descriptor */
+struct pi_desc {
+        u32 pir[8];     /* Posted interrupt requested */
+        u32 control;    /* bit 0 of control is outstanding notification bit */
+        u32 rsvd[7];
+} __aligned(64);
+
+static bool pi_test_and_set_on(struct pi_desc *pi_desc)
+{
+        return test_and_set_bit(POSTED_INTR_ON,
+                        (unsigned long *)&pi_desc->control);
+}
+
+static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
+{
+        return test_and_clear_bit(POSTED_INTR_ON,
+                        (unsigned long *)&pi_desc->control);
+}
+
+static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
+{
+        return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
+}
+
 struct vcpu_vmx {
         struct kvm_vcpu       vcpu;
         unsigned long         host_rsp;
@@ -377,6 +412,7 @@ struct vcpu_vmx {
         struct shared_msr_entry *guest_msrs;
         int                   nmsrs;
         int                   save_nmsrs;
+        unsigned long         host_idt_base;
 #ifdef CONFIG_X86_64
         u64                   msr_host_kernel_gs_base;
         u64                   msr_guest_kernel_gs_base;
@@ -428,6 +464,9 @@ struct vcpu_vmx {
 
         bool rdtscp_enabled;
 
+        /* Posted interrupt descriptor */
+        struct pi_desc pi_desc;
+
         /* Support for a guest hypervisor (nested VMX) */
         struct nested_vmx nested;
 };
@@ -451,6 +490,64 @@ static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 
+
+static const unsigned long shadow_read_only_fields[] = {
+        /*
+         * We do NOT shadow fields that are modified when L0
+         * traps and emulates any vmx instruction (e.g. VMPTRLD,
+         * VMXON...) executed by L1.
+         * For example, VM_INSTRUCTION_ERROR is read
+         * by L1 if a vmx instruction fails (part of the error path).
+         * Note the code assumes this logic. If for some reason
+         * we start shadowing these fields then we need to
+         * force a shadow sync when L0 emulates vmx instructions
+         * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
+         * by nested_vmx_failValid)
+         */
+        VM_EXIT_REASON,
+        VM_EXIT_INTR_INFO,
+        VM_EXIT_INSTRUCTION_LEN,
+        IDT_VECTORING_INFO_FIELD,
+        IDT_VECTORING_ERROR_CODE,
+        VM_EXIT_INTR_ERROR_CODE,
+        EXIT_QUALIFICATION,
+        GUEST_LINEAR_ADDRESS,
+        GUEST_PHYSICAL_ADDRESS
+};
+static const int max_shadow_read_only_fields =
+        ARRAY_SIZE(shadow_read_only_fields);
+
+static const unsigned long shadow_read_write_fields[] = {
+        GUEST_RIP,
+        GUEST_RSP,
+        GUEST_CR0,
+        GUEST_CR3,
+        GUEST_CR4,
+        GUEST_INTERRUPTIBILITY_INFO,
+        GUEST_RFLAGS,
+        GUEST_CS_SELECTOR,
+        GUEST_CS_AR_BYTES,
+        GUEST_CS_LIMIT,
+        GUEST_CS_BASE,
+        GUEST_ES_BASE,
+        CR0_GUEST_HOST_MASK,
+        CR0_READ_SHADOW,
+        CR4_READ_SHADOW,
+        TSC_OFFSET,
+        EXCEPTION_BITMAP,
+        CPU_BASED_VM_EXEC_CONTROL,
+        VM_ENTRY_EXCEPTION_ERROR_CODE,
+        VM_ENTRY_INTR_INFO_FIELD,
+        VM_ENTRY_INSTRUCTION_LEN,
+        VM_ENTRY_EXCEPTION_ERROR_CODE,
+        HOST_FS_BASE,
+        HOST_GS_BASE,
+        HOST_FS_SELECTOR,
+        HOST_GS_SELECTOR
+};
+static const int max_shadow_read_write_fields =
+        ARRAY_SIZE(shadow_read_write_fields);
+
 static const unsigned short vmcs_field_to_offset_table[] = {
         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
@@ -537,6 +634,7 @@ static const unsigned short vmcs_field_to_offset_table[] = {
         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
+        FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
@@ -624,6 +722,9 @@ static void vmx_get_segment(struct kvm_vcpu *vcpu,
                             struct kvm_segment *var, int seg);
 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 static u32 vmx_segment_access_rights(struct kvm_segment *var);
+static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
+static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
+static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 
 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
@@ -640,6 +741,8 @@ static unsigned long *vmx_msr_bitmap_legacy;
 static unsigned long *vmx_msr_bitmap_longmode;
 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
+static unsigned long *vmx_vmread_bitmap;
+static unsigned long *vmx_vmwrite_bitmap;
 
 static bool cpu_has_load_ia32_efer;
 static bool cpu_has_load_perf_global_ctrl;
@@ -782,6 +885,18 @@ static inline bool cpu_has_vmx_virtual_intr_delivery(void)
                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
 }
 
+static inline bool cpu_has_vmx_posted_intr(void)
+{
+        return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
+}
+
+static inline bool cpu_has_vmx_apicv(void)
+{
+        return cpu_has_vmx_apic_register_virt() &&
+                cpu_has_vmx_virtual_intr_delivery() &&
+                cpu_has_vmx_posted_intr();
+}
+
 static inline bool cpu_has_vmx_flexpriority(void)
 {
         return cpu_has_vmx_tpr_shadow() &&
@@ -895,6 +1010,18 @@ static inline bool cpu_has_vmx_wbinvd_exit(void)
                 SECONDARY_EXEC_WBINVD_EXITING;
 }
 
+static inline bool cpu_has_vmx_shadow_vmcs(void)
+{
+        u64 vmx_msr;
+        rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
+        /* check if the cpu supports writing r/o exit information fields */
+        if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
+                return false;
+
+        return vmcs_config.cpu_based_2nd_exec_ctrl &
+                SECONDARY_EXEC_SHADOW_VMCS;
+}
+
 static inline bool report_flexpriority(void)
 {
         return flexpriority_enabled;
@@ -1790,7 +1917,7 @@ static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 
         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
-                nested_pf_handled(vcpu))
+            !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
                 return;
 
         if (has_error_code) {
@@ -2022,6 +2149,7 @@ static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
+static u32 nested_vmx_misc_low, nested_vmx_misc_high;
 static __init void nested_vmx_setup_ctls_msrs(void)
 {
         /*
@@ -2040,30 +2168,40 @@ static __init void nested_vmx_setup_ctls_msrs(void)
          */
 
         /* pin-based controls */
+        rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
+              nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
         /*
          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
          */
-        nested_vmx_pinbased_ctls_low = 0x16 ;
-        nested_vmx_pinbased_ctls_high = 0x16 |
-                PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
-                PIN_BASED_VIRTUAL_NMIS;
+        nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
+        nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
+                PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
+                PIN_BASED_VMX_PREEMPTION_TIMER;
+        nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
 
-        /* exit controls */
-        nested_vmx_exit_ctls_low = 0;
+        /*
+         * Exit controls
+         * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
+         * 17 must be 1.
+         */
+        nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
 #ifdef CONFIG_X86_64
         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
 #else
         nested_vmx_exit_ctls_high = 0;
 #endif
+        nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
 
         /* entry controls */
         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
-        nested_vmx_entry_ctls_low = 0;
+        /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
+        nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
         nested_vmx_entry_ctls_high &=
                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
+        nested_vmx_entry_ctls_high |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
 
         /* cpu-based controls */
         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
@@ -2080,6 +2218,7 @@ static __init void nested_vmx_setup_ctls_msrs(void)
                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
                 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
+                CPU_BASED_PAUSE_EXITING |
                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
         /*
          * We can allow some features even when not supported by the
@@ -2094,7 +2233,14 @@ static __init void nested_vmx_setup_ctls_msrs(void)
                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
         nested_vmx_secondary_ctls_low = 0;
         nested_vmx_secondary_ctls_high &=
-                SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
+                SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
+                SECONDARY_EXEC_WBINVD_EXITING;
+
+        /* miscellaneous data */
+        rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
+        nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
+                VMX_MISC_SAVE_EFER_LMA;
+        nested_vmx_misc_high = 0;
 }
 
 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
@@ -2165,7 +2311,8 @@ static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
                                         nested_vmx_entry_ctls_high);
                 break;
         case MSR_IA32_VMX_MISC:
-                *pdata = 0;
+                *pdata = vmx_control_msr(nested_vmx_misc_low,
+                                         nested_vmx_misc_high);
                 break;
         /*
          * These MSRs specify bits which the guest must keep fixed (on or off)
@@ -2459,7 +2606,7 @@ static int hardware_enable(void *garbage)
                 ept_sync_global();
         }
 
-        store_gdt(&__get_cpu_var(host_gdt));
+        native_store_gdt(&__get_cpu_var(host_gdt));
 
         return 0;
 }
@@ -2529,12 +2676,6 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
         u32 _vmexit_control = 0;
         u32 _vmentry_control = 0;
 
-        min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
-        opt = PIN_BASED_VIRTUAL_NMIS;
-        if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
-                                &_pin_based_exec_control) < 0)
-                return -EIO;
-
         min = CPU_BASED_HLT_EXITING |
 #ifdef CONFIG_X86_64
               CPU_BASED_CR8_LOAD_EXITING |
@@ -2573,7 +2714,8 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
                         SECONDARY_EXEC_RDTSCP |
                         SECONDARY_EXEC_ENABLE_INVPCID |
                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
-                        SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
+                        SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
+                        SECONDARY_EXEC_SHADOW_VMCS;
                 if (adjust_vmx_controls(min2, opt2,
                                         MSR_IA32_VMX_PROCBASED_CTLS2,
                                         &_cpu_based_2nd_exec_control) < 0)
@@ -2605,11 +2747,23 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
 #ifdef CONFIG_X86_64
         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
 #endif
-        opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
+        opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
+                VM_EXIT_ACK_INTR_ON_EXIT;
         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
                                 &_vmexit_control) < 0)
                 return -EIO;
 
+        min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
+        opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
+        if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
+                                &_pin_based_exec_control) < 0)
+                return -EIO;
+
+        if (!(_cpu_based_2nd_exec_control &
+                SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
+                !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
+                _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
+
         min = 0;
         opt = VM_ENTRY_LOAD_IA32_PAT;
         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
@@ -2762,6 +2916,8 @@ static __init int hardware_setup(void)
 
         if (!cpu_has_vmx_vpid())
                 enable_vpid = 0;
+        if (!cpu_has_vmx_shadow_vmcs())
+                enable_shadow_vmcs = 0;
 
         if (!cpu_has_vmx_ept() ||
             !cpu_has_vmx_ept_4levels()) {
@@ -2788,14 +2944,16 @@ static __init int hardware_setup(void)
         if (!cpu_has_vmx_ple())
                 ple_gap = 0;
 
-        if (!cpu_has_vmx_apic_register_virt() ||
-                                !cpu_has_vmx_virtual_intr_delivery())
-                enable_apicv_reg_vid = 0;
+        if (!cpu_has_vmx_apicv())
+                enable_apicv = 0;
 
-        if (enable_apicv_reg_vid)
+        if (enable_apicv)
                 kvm_x86_ops->update_cr8_intercept = NULL;
-        else
+        else {
                 kvm_x86_ops->hwapic_irr_update = NULL;
+                kvm_x86_ops->deliver_posted_interrupt = NULL;
+                kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
+        }
 
         if (nested)
                 nested_vmx_setup_ctls_msrs();
@@ -2876,22 +3034,6 @@ static void enter_pmode(struct kvm_vcpu *vcpu)
         vmx->cpl = 0;
 }
 
-static gva_t rmode_tss_base(struct kvm *kvm)
-{
-        if (!kvm->arch.tss_addr) {
-                struct kvm_memslots *slots;
-                struct kvm_memory_slot *slot;
-                gfn_t base_gfn;
-
-                slots = kvm_memslots(kvm);
-                slot = id_to_memslot(slots, 0);
-                base_gfn = slot->base_gfn + slot->npages - 3;
-
-                return base_gfn << PAGE_SHIFT;
-        }
-        return kvm->arch.tss_addr;
-}
-
 static void fix_rmode_seg(int seg, struct kvm_segment *save)
 {
         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
@@ -2942,19 +3084,15 @@ static void enter_rmode(struct kvm_vcpu *vcpu)
 
         /*
          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
-         * vcpu. Call it here with phys address pointing 16M below 4G.
+         * vcpu. Warn the user that an update is overdue.
          */
-        if (!vcpu->kvm->arch.tss_addr) {
+        if (!vcpu->kvm->arch.tss_addr)
                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
                              "called before entering vcpu\n");
-                srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
-                vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
-                vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
-        }
 
         vmx_segment_cache_clear(vmx);
 
-        vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
+        vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
 
@@ -3214,7 +3352,9 @@ static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
                  */
                 if (!nested_vmx_allowed(vcpu))
                         return 1;
-        } else if (to_vmx(vcpu)->nested.vmxon)
+        }
+        if (to_vmx(vcpu)->nested.vmxon &&
+            ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
                 return 1;
 
         vcpu->arch.cr4 = cr4;
@@ -3550,7 +3690,7 @@ static bool guest_state_valid(struct kvm_vcpu *vcpu)
                 return true;
 
         /* real mode guest state checks */
-        if (!is_protmode(vcpu)) {
+        if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
                         return false;
                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
@@ -3599,7 +3739,7 @@ static int init_rmode_tss(struct kvm *kvm)
         int r, idx, ret = 0;
 
         idx = srcu_read_lock(&kvm->srcu);
-        fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
+        fn = kvm->arch.tss_addr >> PAGE_SHIFT;
         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
         if (r < 0)
                 goto out;
@@ -3692,7 +3832,7 @@ static int alloc_apic_access_page(struct kvm *kvm)
         kvm_userspace_mem.flags = 0;
         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
         kvm_userspace_mem.memory_size = PAGE_SIZE;
-        r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, false);
+        r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
         if (r)
                 goto out;
 
@@ -3722,7 +3862,7 @@ static int alloc_identity_pagetable(struct kvm *kvm)
         kvm_userspace_mem.guest_phys_addr =
                 kvm->arch.ept_identity_map_addr;
         kvm_userspace_mem.memory_size = PAGE_SIZE;
-        r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, false);
+        r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
         if (r)
                 goto out;
 
@@ -3869,13 +4009,59 @@ static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
                         msr, MSR_TYPE_W);
 }
 
+static int vmx_vm_has_apicv(struct kvm *kvm)
+{
+        return enable_apicv && irqchip_in_kernel(kvm);
+}
+
+/*
+ * Send interrupt to vcpu via posted interrupt way.
+ * 1. If target vcpu is running(non-root mode), send posted interrupt
+ * notification to vcpu and hardware will sync PIR to vIRR atomically.
+ * 2. If target vcpu isn't running(root mode), kick it to pick up the
+ * interrupt from PIR in next vmentry.
+ */
+static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
+{
+        struct vcpu_vmx *vmx = to_vmx(vcpu);
+        int r;
+
+        if (pi_test_and_set_pir(vector, &vmx->pi_desc))
+                return;
+
+        r = pi_test_and_set_on(&vmx->pi_desc);
+        kvm_make_request(KVM_REQ_EVENT, vcpu);
+#ifdef CONFIG_SMP
+        if (!r && (vcpu->mode == IN_GUEST_MODE))
+                apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
+                                POSTED_INTR_VECTOR);
+        else
+#endif
+                kvm_vcpu_kick(vcpu);
+}
+
+static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
+{
+        struct vcpu_vmx *vmx = to_vmx(vcpu);
+
+        if (!pi_test_and_clear_on(&vmx->pi_desc))
+                return;
+
+        kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
+}
+
+static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
+{
+        return;
+}
+
 /*
  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
  * will not change in the lifetime of the guest.
  * Note that host-state that does change is set elsewhere. E.g., host-state
  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
  */
-static void vmx_set_constant_host_state(void)
+static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
 {
         u32 low32, high32;
         unsigned long tmpl;
@@ -3903,6 +4089,7 @@ static void vmx_set_constant_host_state(void)
 
         native_store_idt(&dt);
         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
+        vmx->host_idt_base = dt.address;
 
         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
 
@@ -3928,6 +4115,15 @@ static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
 }
 
+static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
+{
+        u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
+
+        if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
+                pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
+        return pin_based_exec_ctrl;
+}
+
 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
 {
         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
@@ -3945,11 +4141,6 @@ static u32 vmx_exec_control(struct vcpu_vmx *vmx)
         return exec_control;
 }
 
-static int vmx_vm_has_apicv(struct kvm *kvm)
-{
-        return enable_apicv_reg_vid && irqchip_in_kernel(kvm);
-}
-
 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
 {
         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
@@ -3971,6 +4162,12 @@ static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
+        /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
+           (handle_vmptrld).
+           We can NOT enable shadow_vmcs here because we don't have yet
+           a current VMCS12
+        */
+        exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
         return exec_control;
 }
 
@@ -3999,14 +4196,17 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
 
+        if (enable_shadow_vmcs) {
+                vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
+                vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
+        }
         if (cpu_has_vmx_msr_bitmap())
                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
 
         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
 
         /* Control */
-        vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
-                vmcs_config.pin_based_exec_ctrl);
+        vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
 
         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
 
@@ -4015,13 +4215,16 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
                                 vmx_secondary_exec_control(vmx));
         }
 
-        if (enable_apicv_reg_vid) {
+        if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
 
                 vmcs_write16(GUEST_INTR_STATUS, 0);
+
+                vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
+                vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
         }
 
         if (ple_gap) {
@@ -4035,7 +4238,7 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
 
         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
-        vmx_set_constant_host_state();
+        vmx_set_constant_host_state(vmx);
 #ifdef CONFIG_X86_64
         rdmsrl(MSR_FS_BASE, a);
         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
@@ -4089,11 +4292,10 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
         return 0;
 }
 
-static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
+static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
 {
         struct vcpu_vmx *vmx = to_vmx(vcpu);
         u64 msr;
-        int ret;
 
         vmx->rmode.vm86_active = 0;
 
@@ -4109,12 +4311,8 @@ static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
         vmx_segment_cache_clear(vmx);
 
         seg_setup(VCPU_SREG_CS);
-        if (kvm_vcpu_is_bsp(&vmx->vcpu))
-                vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
-        else {
-                vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
-                vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
-        }
+        vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
+        vmcs_write32(GUEST_CS_BASE, 0xffff0000);
 
         seg_setup(VCPU_SREG_DS);
         seg_setup(VCPU_SREG_ES);
@@ -4137,10 +4335,7 @@ static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
         vmcs_writel(GUEST_SYSENTER_EIP, 0);
 
         vmcs_writel(GUEST_RFLAGS, 0x02);
-        if (kvm_vcpu_is_bsp(&vmx->vcpu))
-                kvm_rip_write(vcpu, 0xfff0);
-        else
-                kvm_rip_write(vcpu, 0);
+        kvm_rip_write(vcpu, 0xfff0);
 
         vmcs_writel(GUEST_GDTR_BASE, 0);
         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
@@ -4171,23 +4366,20 @@ static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
                 vmcs_write64(APIC_ACCESS_ADDR,
                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
 
+        if (vmx_vm_has_apicv(vcpu->kvm))
+                memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
+
         if (vmx->vpid != 0)
                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
 
         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
-        vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
-        srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
         vmx_set_cr4(&vmx->vcpu, 0);
         vmx_set_efer(&vmx->vcpu, 0);
         vmx_fpu_activate(&vmx->vcpu);
         update_exception_bitmap(&vmx->vcpu);
 
         vpid_sync_context(vmx);
-
-        ret = 0;
-
-        return ret;
 }
 
 /*
@@ -4200,40 +4392,45 @@ static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
                 PIN_BASED_EXT_INTR_MASK;
 }
 
-static void enable_irq_window(struct kvm_vcpu *vcpu)
+static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
+{
+        return get_vmcs12(vcpu)->pin_based_vm_exec_control &
+                PIN_BASED_NMI_EXITING;
+}
+
+static int enable_irq_window(struct kvm_vcpu *vcpu)
 {
         u32 cpu_based_vm_exec_control;
-        if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
+
+        if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
                 /*
                  * We get here if vmx_interrupt_allowed() said we can't
-                 * inject to L1 now because L2 must run. Ask L2 to exit
-                 * right after entry, so we can inject to L1 more promptly.
+                 * inject to L1 now because L2 must run. The caller will have
+                 * to make L2 exit right after entry, so we can inject to L1
+                 * more promptly.
                  */
-                kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
-                return;
-        }
+                return -EBUSY;
 
         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
+        return 0;
 }
 
-static void enable_nmi_window(struct kvm_vcpu *vcpu)
+static int enable_nmi_window(struct kvm_vcpu *vcpu)
 {
         u32 cpu_based_vm_exec_control;
 
-        if (!cpu_has_virtual_nmis()) {
-                enable_irq_window(vcpu);
-                return;
-        }
+        if (!cpu_has_virtual_nmis())
+                return enable_irq_window(vcpu);
+
+        if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
+                return enable_irq_window(vcpu);
 
-        if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
-                enable_irq_window(vcpu);
-                return;
-        }
         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
+        return 0;
 }
 
 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
@@ -4294,16 +4491,6 @@ static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
 }
 
-static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
-{
-        if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
-                return 0;
-
-        return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
-                  (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
-                   | GUEST_INTR_STATE_NMI));
-}
-
 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
 {
         if (!cpu_has_virtual_nmis())
@@ -4333,18 +4520,52 @@ static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
         }
 }
 
+static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
+{
+        if (is_guest_mode(vcpu)) {
+                struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
+
+                if (to_vmx(vcpu)->nested.nested_run_pending)
+                        return 0;
+                if (nested_exit_on_nmi(vcpu)) {
+                        nested_vmx_vmexit(vcpu);
+                        vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
+                        vmcs12->vm_exit_intr_info = NMI_VECTOR |
+                                INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
+                        /*
+                         * The NMI-triggered VM exit counts as injection:
+                         * clear this one and block further NMIs.
+                         */
+                        vcpu->arch.nmi_pending = 0;
+                        vmx_set_nmi_mask(vcpu, true);
+                        return 0;
+                }
+        }
+
+        if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
+                return 0;
+
+        return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
+                  (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
+                   | GUEST_INTR_STATE_NMI));
+}
+
 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
 {
-        if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
+        if (is_guest_mode(vcpu)) {
                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
-                if (to_vmx(vcpu)->nested.nested_run_pending ||
-                    (vmcs12->idt_vectoring_info_field &
-                     VECTORING_INFO_VALID_MASK))
+
+                if (to_vmx(vcpu)->nested.nested_run_pending)
                         return 0;
-                nested_vmx_vmexit(vcpu);
-                vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
-                vmcs12->vm_exit_intr_info = 0;
-                /* fall through to normal code, but now in L1, not L2 */
+                if (nested_exit_on_intr(vcpu)) {
+                        nested_vmx_vmexit(vcpu);
+                        vmcs12->vm_exit_reason =
+                                EXIT_REASON_EXTERNAL_INTERRUPT;
+                        vmcs12->vm_exit_intr_info = 0;
+                        /*
+                         * fall through to normal code, but now in L1, not L2
+                         */
+                }
         }
 
         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
@@ -4362,7 +4583,7 @@ static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
                 .flags = 0,
         };
 
-        ret = kvm_set_memory_region(kvm, &tss_mem, false);
+        ret = kvm_set_memory_region(kvm, &tss_mem);
         if (ret)
                 return ret;
         kvm->arch.tss_addr = addr;
@@ -4603,34 +4824,50 @@ vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
 {
-        if (to_vmx(vcpu)->nested.vmxon &&
-            ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
-                return 1;
-
         if (is_guest_mode(vcpu)) {
+                struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
+                unsigned long orig_val = val;
+
                 /*
                  * We get here when L2 changed cr0 in a way that did not change
                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
-                 * but did change L0 shadowed bits. This can currently happen
-                 * with the TS bit: L0 may want to leave TS on (for lazy fpu
-                 * loading) while pretending to allow the guest to change it.
+                 * but did change L0 shadowed bits. So we first calculate the
+                 * effective cr0 value that L1 would like to write into the
+                 * hardware. It consists of the L2-owned bits from the new
+                 * value combined with the L1-owned bits from L1's guest_cr0.
                  */
-                if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
-                         (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
+                val = (val & ~vmcs12->cr0_guest_host_mask) |
+                        (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
+
+                /* TODO: will have to take unrestricted guest mode into
+                 * account */
+                if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
                         return 1;
-                vmcs_writel(CR0_READ_SHADOW, val);
+
+                if (kvm_set_cr0(vcpu, val))
+                        return 1;
+                vmcs_writel(CR0_READ_SHADOW, orig_val);
                 return 0;
-        } else
+        } else {
+                if (to_vmx(vcpu)->nested.vmxon &&
+                    ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
+                        return 1;
                 return kvm_set_cr0(vcpu, val);
+        }
 }
 
 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
 {
         if (is_guest_mode(vcpu)) {
-                if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
-                         (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
+                struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
+                unsigned long orig_val = val;
+
+                /* analogously to handle_set_cr0 */
+                val = (val & ~vmcs12->cr4_guest_host_mask) |
+                        (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
+                if (kvm_set_cr4(vcpu, val))
                         return 1;
-                vmcs_writel(CR4_READ_SHADOW, val);
+                vmcs_writel(CR4_READ_SHADOW, orig_val);
                 return 0;
         } else
                 return kvm_set_cr4(vcpu, val);
@@ -5183,7 +5420,7 @@ static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
                         return 1;
 
-                err = emulate_instruction(vcpu, 0);
+                err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
 
                 if (err == EMULATE_DO_MMIO) {
                         ret = 0;
@@ -5259,8 +5496,7 @@ static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
         }
 
         /* Create a new VMCS */
-        item = (struct vmcs02_list *)
-                kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
+        item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
         if (!item)
                 return NULL;
         item->vmcs02.vmcs = alloc_vmcs();
@@ -5309,6 +5545,9 @@ static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
                 free_loaded_vmcs(&vmx->vmcs01);
 }
 
+static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
+                                 u32 vm_instruction_error);
+
 /*
  * Emulate the VMXON instruction.
  * Currently, we just remember that VMX is active, and do not save or even
@@ -5321,6 +5560,7 @@ static int handle_vmon(struct kvm_vcpu *vcpu)
 {
         struct kvm_segment cs;
         struct vcpu_vmx *vmx = to_vmx(vcpu);
+        struct vmcs *shadow_vmcs;
 
         /* The Intel VMX Instruction Reference lists a bunch of bits that
          * are prerequisite to running VMXON, most notably cr4.VMXE must be
@@ -5344,6 +5584,21 @@ static int handle_vmon(struct kvm_vcpu *vcpu)
                 kvm_inject_gp(vcpu, 0);
                 return 1;
         }
+        if (vmx->nested.vmxon) {
+                nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
+                skip_emulated_instruction(vcpu);
+                return 1;
+        }
+        if (enable_shadow_vmcs) {
+                shadow_vmcs = alloc_vmcs();
+                if (!shadow_vmcs)
+                        return -ENOMEM;
+                /* mark vmcs as shadow */
+                shadow_vmcs->revision_id |= (1u << 31);
+                /* init shadow vmcs */
+                vmcs_clear(shadow_vmcs);
+                vmx->nested.current_shadow_vmcs = shadow_vmcs;
+        }
 
         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
         vmx->nested.vmcs02_num = 0;
@@ -5384,6 +5639,25 @@ static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
         return 1;
 }
 
+static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
+{
+        u32 exec_control;
+        if (enable_shadow_vmcs) {
+                if (vmx->nested.current_vmcs12 != NULL) {
+                        /* copy to memory all shadowed fields in case
+                           they were modified */
+                        copy_shadow_to_vmcs12(vmx);
+                        vmx->nested.sync_shadow_vmcs = false;
+                        exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
+                        exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
+                        vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
+                        vmcs_write64(VMCS_LINK_POINTER, -1ull);
+                }
+        }
+        kunmap(vmx->nested.current_vmcs12_page);
+        nested_release_page(vmx->nested.current_vmcs12_page);
+}
+
 /*
  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
  * just stops using VMX.
@@ -5394,11 +5668,12 @@ static void free_nested(struct vcpu_vmx *vmx)
                 return;
         vmx->nested.vmxon = false;
         if (vmx->nested.current_vmptr != -1ull) {
-                kunmap(vmx->nested.current_vmcs12_page);
-                nested_release_page(vmx->nested.current_vmcs12_page);
+                nested_release_vmcs12(vmx);
                 vmx->nested.current_vmptr = -1ull;
                 vmx->nested.current_vmcs12 = NULL;
         }
+        if (enable_shadow_vmcs)
+                free_vmcs(vmx->nested.current_shadow_vmcs);
         /* Unpin physical memory we referred to in current vmcs02 */
         if (vmx->nested.apic_access_page) {
                 nested_release_page(vmx->nested.apic_access_page);
@@ -5507,6 +5782,10 @@ static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
                             X86_EFLAGS_SF | X86_EFLAGS_OF))
                         | X86_EFLAGS_ZF);
         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
+        /*
+         * We don't need to force a shadow sync because
+         * VM_INSTRUCTION_ERROR is not shadowed
+         */
 }
 
 /* Emulate the VMCLEAR instruction */
@@ -5539,8 +5818,7 @@ static int handle_vmclear(struct kvm_vcpu *vcpu)
         }
 
         if (vmptr == vmx->nested.current_vmptr) {
-                kunmap(vmx->nested.current_vmcs12_page);
-                nested_release_page(vmx->nested.current_vmcs12_page);
+                nested_release_vmcs12(vmx);
                 vmx->nested.current_vmptr = -1ull;
                 vmx->nested.current_vmcs12 = NULL;
         }
@@ -5639,6 +5917,111 @@ static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
         }
 }
 
+
+static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
+                                    unsigned long field, u64 field_value){
+        short offset = vmcs_field_to_offset(field);
+        char *p = ((char *) get_vmcs12(vcpu)) + offset;
+        if (offset < 0)
+                return false;
+
+        switch (vmcs_field_type(field)) {
+        case VMCS_FIELD_TYPE_U16:
+                *(u16 *)p = field_value;
+                return true;
+        case VMCS_FIELD_TYPE_U32:
+                *(u32 *)p = field_value;
+                return true;
+        case VMCS_FIELD_TYPE_U64:
+                *(u64 *)p = field_value;
+                return true;
+        case VMCS_FIELD_TYPE_NATURAL_WIDTH:
+                *(natural_width *)p = field_value;
+                return true;
+        default:
+                return false; /* can never happen. */
+        }
+
+}
+
+static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
+{
+        int i;
+        unsigned long field;
+        u64 field_value;
+        struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
+        unsigned long *fields = (unsigned long *)shadow_read_write_fields;
+        int num_fields = max_shadow_read_write_fields;
+
+        vmcs_load(shadow_vmcs);
+
+        for (i = 0; i < num_fields; i++) {
+                field = fields[i];
+                switch (vmcs_field_type(field)) {
+                case VMCS_FIELD_TYPE_U16:
+                        field_value = vmcs_read16(field);
+                        break;
+                case VMCS_FIELD_TYPE_U32:
+                        field_value = vmcs_read32(field);
+                        break;
+                case VMCS_FIELD_TYPE_U64:
+                        field_value = vmcs_read64(field);
+                        break;
+                case VMCS_FIELD_TYPE_NATURAL_WIDTH:
+                        field_value = vmcs_readl(field);
+                        break;
+                }
+                vmcs12_write_any(&vmx->vcpu, field, field_value);
+        }
+
+        vmcs_clear(shadow_vmcs);
+        vmcs_load(vmx->loaded_vmcs->vmcs);
+}
+
+static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
+{
+        unsigned long *fields[] = {
+                (unsigned long *)shadow_read_write_fields,
+                (unsigned long *)shadow_read_only_fields
+        };
+        int num_lists =  ARRAY_SIZE(fields);
+        int max_fields[] = {
+                max_shadow_read_write_fields,
+                max_shadow_read_only_fields
+        };
+        int i, q;
+        unsigned long field;
+        u64 field_value = 0;
+        struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
+
+        vmcs_load(shadow_vmcs);
+
+        for (q = 0; q < num_lists; q++) {
+                for (i = 0; i < max_fields[q]; i++) {
+                        field = fields[q][i];
+                        vmcs12_read_any(&vmx->vcpu, field, &field_value);
+
+                        switch (vmcs_field_type(field)) {
+                        case VMCS_FIELD_TYPE_U16:
+                                vmcs_write16(field, (u16)field_value);
+                                break;
+                        case VMCS_FIELD_TYPE_U32:
+                                vmcs_write32(field, (u32)field_value);
+                                break;
+                        case VMCS_FIELD_TYPE_U64:
+                                vmcs_write64(field, (u64)field_value);
+                                break;
+                        case VMCS_FIELD_TYPE_NATURAL_WIDTH:
+                                vmcs_writel(field, (long)field_value);
+                                break;
+                        }
+                }
+        }
+
+        vmcs_clear(shadow_vmcs);
+        vmcs_load(vmx->loaded_vmcs->vmcs);
+}
+
 /*
  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
  * used before) all generate the same failure when it is missing.
@@ -5703,8 +6086,6 @@ static int handle_vmwrite(struct kvm_vcpu *vcpu)
         gva_t gva;
         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
-        char *p;
-        short offset;
         /* The value to write might be 32 or 64 bits, depending on L1's long
          * mode, and eventually we need to write that into a field of several
          * possible lengths. The code below first zero-extends the value to 64
@@ -5741,28 +6122,7 @@ static int handle_vmwrite(struct kvm_vcpu *vcpu)
                 return 1;
         }
 
-        offset = vmcs_field_to_offset(field);
-        if (offset < 0) {
-                nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
-                skip_emulated_instruction(vcpu);
-                return 1;
-        }
-        p = ((char *) get_vmcs12(vcpu)) + offset;
-
-        switch (vmcs_field_type(field)) {
-        case VMCS_FIELD_TYPE_U16:
-                *(u16 *)p = field_value;
-                break;
-        case VMCS_FIELD_TYPE_U32:
-                *(u32 *)p = field_value;
-                break;
-        case VMCS_FIELD_TYPE_U64:
-                *(u64 *)p = field_value;
-                break;
-        case VMCS_FIELD_TYPE_NATURAL_WIDTH:
-                *(natural_width *)p = field_value;
-                break;
-        default:
+        if (!vmcs12_write_any(vcpu, field, field_value)) {
                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
                 skip_emulated_instruction(vcpu);
                 return 1;
@@ -5780,6 +6140,7 @@ static int handle_vmptrld(struct kvm_vcpu *vcpu)
         gva_t gva;
         gpa_t vmptr;
         struct x86_exception e;
+        u32 exec_control;
 
         if (!nested_vmx_check_permission(vcpu))
                 return 1;
@@ -5818,14 +6179,20 @@ static int handle_vmptrld(struct kvm_vcpu *vcpu)
                         skip_emulated_instruction(vcpu);
                         return 1;
                 }
-                if (vmx->nested.current_vmptr != -1ull) {
-                        kunmap(vmx->nested.current_vmcs12_page);
-                        nested_release_page(vmx->nested.current_vmcs12_page);
-                }
+                if (vmx->nested.current_vmptr != -1ull)
+                        nested_release_vmcs12(vmx);
 
                 vmx->nested.current_vmptr = vmptr;
                 vmx->nested.current_vmcs12 = new_vmcs12;
                 vmx->nested.current_vmcs12_page = page;
+                if (enable_shadow_vmcs) {
+                        exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
+                        exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
+                        vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
+                        vmcs_write64(VMCS_LINK_POINTER,
+                                     __pa(vmx->nested.current_shadow_vmcs));
+                        vmx->nested.sync_shadow_vmcs = true;
+                }
         }
 
         nested_vmx_succeed(vcpu);
@@ -5908,6 +6275,52 @@ static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
 static const int kvm_vmx_max_exit_handlers =
         ARRAY_SIZE(kvm_vmx_exit_handlers);
 
+static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
+                                       struct vmcs12 *vmcs12)
+{
+        unsigned long exit_qualification;
+        gpa_t bitmap, last_bitmap;
+        unsigned int port;
+        int size;
+        u8 b;
+
+        if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
+                return 1;
+
+        if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
+                return 0;
+
+        exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
+
+        port = exit_qualification >> 16;
+        size = (exit_qualification & 7) + 1;
+
+        last_bitmap = (gpa_t)-1;
+        b = -1;
+
+        while (size > 0) {
+                if (port < 0x8000)
+                        bitmap = vmcs12->io_bitmap_a;
+                else if (port < 0x10000)
+                        bitmap = vmcs12->io_bitmap_b;
+                else
+                        return 1;
+                bitmap += (port & 0x7fff) / 8;
+
+                if (last_bitmap != bitmap)
+                        if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
+                                return 1;
+                if (b & (1 << (port & 7)))
+                        return 1;
+
+                port++;
+                size--;
+                last_bitmap = bitmap;
+        }
+
+        return 0;
+}
+
 /*
  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
@@ -5939,7 +6352,8 @@ static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
         /* Then read the msr_index'th bit from this bitmap: */
         if (msr_index < 1024*8) {
                 unsigned char b;
-                kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
+                if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
+                        return 1;
                 return 1 & (b >> (msr_index & 7));
         } else
                 return 1; /* let L1 handle the wrong parameter */
@@ -6033,10 +6447,10 @@ static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
  */
 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
 {
-        u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
         struct vcpu_vmx *vmx = to_vmx(vcpu);
         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
+        u32 exit_reason = vmx->exit_reason;
 
         if (vmx->nested.nested_run_pending)
                 return 0;
@@ -6060,14 +6474,9 @@ static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
         case EXIT_REASON_TRIPLE_FAULT:
                 return 1;
         case EXIT_REASON_PENDING_INTERRUPT:
+                return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
         case EXIT_REASON_NMI_WINDOW:
-                /*
-                 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
-                 * (aka Interrupt Window Exiting) only when L1 turned it on,
-                 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
-                 * Same for NMI Window Exiting.
-                 */
-                return 1;
+                return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
         case EXIT_REASON_TASK_SWITCH:
                 return 1;
         case EXIT_REASON_CPUID:
@@ -6097,8 +6506,7 @@ static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
         case EXIT_REASON_DR_ACCESS:
                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
         case EXIT_REASON_IO_INSTRUCTION:
-                /* TODO: support IO bitmaps */
-                return 1;
+                return nested_vmx_exit_handled_io(vcpu, vmcs12);
         case EXIT_REASON_MSR_READ:
         case EXIT_REASON_MSR_WRITE:
                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
@@ -6122,6 +6530,9 @@ static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
         case EXIT_REASON_EPT_VIOLATION:
         case EXIT_REASON_EPT_MISCONFIG:
                 return 0;
+        case EXIT_REASON_PREEMPTION_TIMER:
+                return vmcs12->pin_based_vm_exec_control &
+                        PIN_BASED_VMX_PREEMPTION_TIMER;
         case EXIT_REASON_WBINVD:
                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
         case EXIT_REASON_XSETBV:
@@ -6316,6 +6727,9 @@ static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
 
 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
 {
+        if (!vmx_vm_has_apicv(vcpu->kvm))
+                return;
+
         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
@@ -6346,6 +6760,52 @@ static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
         }
 }
 
+static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
+{
+        u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
+
+        /*
+         * If external interrupt exists, IF bit is set in rflags/eflags on the
+         * interrupt stack frame, and interrupt will be enabled on a return
+         * from interrupt handler.
+         */
+        if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
+                        == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
+                unsigned int vector;
+                unsigned long entry;
+                gate_desc *desc;
+                struct vcpu_vmx *vmx = to_vmx(vcpu);
+#ifdef CONFIG_X86_64
+                unsigned long tmp;
+#endif
+
+                vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
+                desc = (gate_desc *)vmx->host_idt_base + vector;
+                entry = gate_offset(*desc);
+                asm volatile(
+#ifdef CONFIG_X86_64
+                        "mov %%" _ASM_SP ", %[sp]\n\t"
+                        "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
+                        "push $%c[ss]\n\t"
+                        "push %[sp]\n\t"
+#endif
+                        "pushf\n\t"
+                        "orl $0x200, (%%" _ASM_SP ")\n\t"
+                        __ASM_SIZE(push) " $%c[cs]\n\t"
+                        "call *%[entry]\n\t"
+                        :
+#ifdef CONFIG_X86_64
+                        [sp]"=&r"(tmp)
+#endif
+                        :
+                        [entry]"r"(entry),
+                        [ss]"i"(__KERNEL_DS),
+                        [cs]"i"(__KERNEL_CS)
+                        );
+        } else
+                local_irq_enable();
+}
+
 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
 {
         u32 exit_intr_info;
@@ -6388,7 +6848,7 @@ static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
 }
 
-static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
+static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
                                       u32 idt_vectoring_info,
                                       int instr_len_field,
                                       int error_code_field)
@@ -6399,46 +6859,43 @@ static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
 
         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
 
-        vmx->vcpu.arch.nmi_injected = false;
-        kvm_clear_exception_queue(&vmx->vcpu);
-        kvm_clear_interrupt_queue(&vmx->vcpu);
+        vcpu->arch.nmi_injected = false;
+        kvm_clear_exception_queue(vcpu);
+        kvm_clear_interrupt_queue(vcpu);
 
         if (!idtv_info_valid)
                 return;
 
-        kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
+        kvm_make_request(KVM_REQ_EVENT, vcpu);
 
         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
 
         switch (type) {
         case INTR_TYPE_NMI_INTR:
-                vmx->vcpu.arch.nmi_injected = true;
+                vcpu->arch.nmi_injected = true;
                 /*
                  * SDM 3: 27.7.1.2 (September 2008)
                  * Clear bit "block by NMI" before VM entry if a NMI
                  * delivery faulted.
                  */
-                vmx_set_nmi_mask(&vmx->vcpu, false);
+                vmx_set_nmi_mask(vcpu, false);
                 break;
         case INTR_TYPE_SOFT_EXCEPTION:
-                vmx->vcpu.arch.event_exit_inst_len =
-                        vmcs_read32(instr_len_field);
+                vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
                 /* fall through */
         case INTR_TYPE_HARD_EXCEPTION:
                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
                         u32 err = vmcs_read32(error_code_field);
-                        kvm_queue_exception_e(&vmx->vcpu, vector, err);
+                        kvm_queue_exception_e(vcpu, vector, err);
                 } else
-                        kvm_queue_exception(&vmx->vcpu, vector);
+                        kvm_queue_exception(vcpu, vector);
                 break;
         case INTR_TYPE_SOFT_INTR:
-                vmx->vcpu.arch.event_exit_inst_len =
-                        vmcs_read32(instr_len_field);
+                vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
                 /* fall through */
         case INTR_TYPE_EXT_INTR:
-                kvm_queue_interrupt(&vmx->vcpu, vector,
-                        type == INTR_TYPE_SOFT_INTR);
+                kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
                 break;
         default:
                 break;
@@ -6447,18 +6904,14 @@ static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
 
 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
 {
-        if (is_guest_mode(&vmx->vcpu))
-                return;
-        __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
+        __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
                                   VM_EXIT_INSTRUCTION_LEN,
                                   IDT_VECTORING_ERROR_CODE);
 }
 
 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
 {
-        if (is_guest_mode(vcpu))
-                return;
-        __vmx_complete_interrupts(to_vmx(vcpu),
+        __vmx_complete_interrupts(vcpu,
                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
                                   VM_ENTRY_INSTRUCTION_LEN,
                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
@@ -6489,21 +6942,6 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
         struct vcpu_vmx *vmx = to_vmx(vcpu);
         unsigned long debugctlmsr;
 
-        if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
-                struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
-                if (vmcs12->idt_vectoring_info_field &
-                                VECTORING_INFO_VALID_MASK) {
-                        vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
-                                vmcs12->idt_vectoring_info_field);
-                        vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
-                                vmcs12->vm_exit_instruction_len);
-                        if (vmcs12->idt_vectoring_info_field &
-                                        VECTORING_INFO_DELIVER_CODE_MASK)
-                                vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
-                                        vmcs12->idt_vectoring_error_code);
-                }
-        }
-
         /* Record the guest's net vcpu time for enforced NMI injections. */
         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
                 vmx->entry_time = ktime_get();
@@ -6513,6 +6951,11 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
         if (vmx->emulation_required)
                 return;
 
+        if (vmx->nested.sync_shadow_vmcs) {
+                copy_vmcs12_to_shadow(vmx);
+                vmx->nested.sync_shadow_vmcs = false;
+        }
+
         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
@@ -6662,17 +7105,6 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
 
         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
 
-        if (is_guest_mode(vcpu)) {
-                struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
-                vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
-                if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
-                        vmcs12->idt_vectoring_error_code =
-                                vmcs_read32(IDT_VECTORING_ERROR_CODE);
-                        vmcs12->vm_exit_instruction_len =
-                                vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
-                }
-        }
-
         vmx->loaded_vmcs->launched = 1;
 
         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
@@ -6734,10 +7166,11 @@ static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
         put_cpu();
         if (err)
                 goto free_vmcs;
-        if (vm_need_virtualize_apic_accesses(kvm))
+        if (vm_need_virtualize_apic_accesses(kvm)) {
                 err = alloc_apic_access_page(kvm);
                 if (err)
                         goto free_vmcs;
+        }
 
         if (enable_ept) {
                 if (!kvm->arch.ept_identity_map_addr)
@@ -6931,9 +7364,8 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
                 vmcs12->vm_entry_instruction_len);
         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
                 vmcs12->guest_interruptibility_info);
-        vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
-        vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
+        kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
                 vmcs12->guest_pending_dbg_exceptions);
@@ -6946,6 +7378,10 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
                 (vmcs_config.pin_based_exec_ctrl |
                  vmcs12->pin_based_vm_exec_control));
 
+        if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
+                vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
+                             vmcs12->vmx_preemption_timer_value);
+
         /*
          * Whether page-faults are trapped is determined by a combination of
          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
@@ -7016,7 +7452,7 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
          * Other fields are different per CPU, and will be set later when
          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
          */
-        vmx_set_constant_host_state();
+        vmx_set_constant_host_state(vmx);
 
         /*
          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
@@ -7082,7 +7518,7 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
 
         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
-        if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
+        else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
         else
                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
@@ -7121,6 +7557,7 @@ static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
         struct vcpu_vmx *vmx = to_vmx(vcpu);
         int cpu;
         struct loaded_vmcs *vmcs02;
+        bool ia32e;
 
         if (!nested_vmx_check_permission(vcpu) ||
             !nested_vmx_check_vmcs12(vcpu))
@@ -7129,6 +7566,9 @@ static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
         skip_emulated_instruction(vcpu);
         vmcs12 = get_vmcs12(vcpu);
 
+        if (enable_shadow_vmcs)
+                copy_shadow_to_vmcs12(vmx);
+
         /*
          * The nested entry process starts with enforcing various prerequisites
          * on vmcs12 as required by the Intel SDM, and act appropriately when
@@ -7146,6 +7586,11 @@ static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
                 return 1;
         }
 
+        if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
+                nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
+                return 1;
+        }
+
         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
                 /*TODO: Also verify bits beyond physical address width are 0*/
@@ -7204,6 +7649,45 @@ static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
         }
 
         /*
+         * If the load IA32_EFER VM-entry control is 1, the following checks
+         * are performed on the field for the IA32_EFER MSR:
+         * - Bits reserved in the IA32_EFER MSR must be 0.
+         * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
+         *   the IA-32e mode guest VM-exit control. It must also be identical
+         *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
+         *   CR0.PG) is 1.
+         */
+        if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
+                ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
+                if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
+                    ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
+                    ((vmcs12->guest_cr0 & X86_CR0_PG) &&
+                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
+                        nested_vmx_entry_failure(vcpu, vmcs12,
+                                EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
+                        return 1;
+                }
+        }
+
+        /*
+         * If the load IA32_EFER VM-exit control is 1, bits reserved in the
+         * IA32_EFER MSR must be 0 in the field for that register. In addition,
+         * the values of the LMA and LME bits in the field must each be that of
+         * the host address-space size VM-exit control.
+         */
+        if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
+                ia32e = (vmcs12->vm_exit_controls &
+                         VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
+                if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
+                    ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
+                    ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
+                        nested_vmx_entry_failure(vcpu, vmcs12,
+                                EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
+                        return 1;
+                }
+        }
+
+        /*
          * We're finally done with prerequisite checking, and can start with
          * the nested entry.
          */
@@ -7223,6 +7707,8 @@ static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
         vcpu->cpu = cpu;
         put_cpu();
 
+        vmx_segment_cache_clear(vmx);
+
         vmcs12->launch_state = 1;
 
         prepare_vmcs02(vcpu, vmcs12);
@@ -7273,6 +7759,48 @@ vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
                         vcpu->arch.cr4_guest_owned_bits));
 }
 
+static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
+                                       struct vmcs12 *vmcs12)
+{
+        u32 idt_vectoring;
+        unsigned int nr;
+
+        if (vcpu->arch.exception.pending) {
+                nr = vcpu->arch.exception.nr;
+                idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
+
+                if (kvm_exception_is_soft(nr)) {
+                        vmcs12->vm_exit_instruction_len =
+                                vcpu->arch.event_exit_inst_len;
+                        idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
+                } else
+                        idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
+
+                if (vcpu->arch.exception.has_error_code) {
+                        idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
+                        vmcs12->idt_vectoring_error_code =
+                                vcpu->arch.exception.error_code;
+                }
+
+                vmcs12->idt_vectoring_info_field = idt_vectoring;
+        } else if (vcpu->arch.nmi_pending) {
+                vmcs12->idt_vectoring_info_field =
+                        INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
+        } else if (vcpu->arch.interrupt.pending) {
+                nr = vcpu->arch.interrupt.nr;
+                idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
+
+                if (vcpu->arch.interrupt.soft) {
+                        idt_vectoring |= INTR_TYPE_SOFT_INTR;
+                        vmcs12->vm_entry_instruction_len =
+                                vcpu->arch.event_exit_inst_len;
+                } else
+                        idt_vectoring |= INTR_TYPE_EXT_INTR;
+
+                vmcs12->idt_vectoring_info_field = idt_vectoring;
+        }
+}
+
 /*
  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
@@ -7284,7 +7812,7 @@ vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
  * which already writes to vmcs12 directly.
  */
-void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
+static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
 {
         /* update guest state fields: */
         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
@@ -7332,16 +7860,19 @@ void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
 
-        vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
         vmcs12->guest_interruptibility_info =
                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
         vmcs12->guest_pending_dbg_exceptions =
                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
 
+        vmcs12->vm_entry_controls =
+                (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
+                (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
+
         /* TODO: These cannot have changed unless we have MSR bitmaps and
          * the relevant bit asks not to trap the change */
         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
-        if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
+        if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
@@ -7349,21 +7880,38 @@ void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
 
         /* update exit information fields: */
 
-        vmcs12->vm_exit_reason  = vmcs_read32(VM_EXIT_REASON);
+        vmcs12->vm_exit_reason  = to_vmx(vcpu)->exit_reason;
         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
 
         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
-        vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
-        vmcs12->idt_vectoring_info_field =
-                vmcs_read32(IDT_VECTORING_INFO_FIELD);
-        vmcs12->idt_vectoring_error_code =
-                vmcs_read32(IDT_VECTORING_ERROR_CODE);
+        if ((vmcs12->vm_exit_intr_info &
+             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
+            (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
+                vmcs12->vm_exit_intr_error_code =
+                        vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
+        vmcs12->idt_vectoring_info_field = 0;
         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
 
-        /* clear vm-entry fields which are to be cleared on exit */
-        if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
+        if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
+                /* vm_entry_intr_info_field is cleared on exit. Emulate this
+                 * instead of reading the real value. */
                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
+
+                /*
+                 * Transfer the event that L0 or L1 may wanted to inject into
+                 * L2 to IDT_VECTORING_INFO_FIELD.
+                 */
+                vmcs12_save_pending_event(vcpu, vmcs12);
+        }
+
+        /*
+         * Drop what we picked up for L2 via vmx_complete_interrupts. It is
+         * preserved above and would only end up incorrectly in L1.
+         */
+        vcpu->arch.nmi_injected = false;
+        kvm_clear_exception_queue(vcpu);
+        kvm_clear_interrupt_queue(vcpu);
 }
 
 /*
@@ -7375,11 +7923,12 @@ void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
  * Failures During or After Loading Guest State").
  * This function should be called when the active VMCS is L1's (vmcs01).
  */
-void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
+static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
+                                   struct vmcs12 *vmcs12)
 {
         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
                 vcpu->arch.efer = vmcs12->host_ia32_efer;
-        if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
+        else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
         else
                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
@@ -7387,6 +7936,7 @@ void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
 
         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
+        vmx_set_rflags(vcpu, X86_EFLAGS_BIT1);
         /*
          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
          * actually changed, because it depends on the current state of
@@ -7445,6 +7995,9 @@ void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
                         vmcs12->host_ia32_perf_global_ctrl);
+
+        kvm_set_dr(vcpu, 7, 0x400);
+        vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
 }
 
 /*
@@ -7458,6 +8011,9 @@ static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
         int cpu;
         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
 
+        /* trying to cancel vmlaunch/vmresume is a bug */
+        WARN_ON_ONCE(vmx->nested.nested_run_pending);
+
         leave_guest_mode(vcpu);
         prepare_vmcs12(vcpu, vmcs12);
 
@@ -7468,6 +8024,8 @@ static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
         vcpu->cpu = cpu;
         put_cpu();
 
+        vmx_segment_cache_clear(vmx);
+
         /* if no vmcs02 cache requested, remove the one we used */
         if (VMCS02_POOL_SIZE == 0)
                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
@@ -7496,6 +8054,8 @@ static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
         } else
                 nested_vmx_succeed(vcpu);
+        if (enable_shadow_vmcs)
+                vmx->nested.sync_shadow_vmcs = true;
 }
 
 /*
@@ -7513,6 +8073,8 @@ static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
         vmcs12->exit_qualification = qualification;
         nested_vmx_succeed(vcpu);
+        if (enable_shadow_vmcs)
+                to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
 }
 
 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
@@ -7590,6 +8152,8 @@ static struct kvm_x86_ops vmx_x86_ops = {
         .load_eoi_exitmap = vmx_load_eoi_exitmap,
         .hwapic_irr_update = vmx_hwapic_irr_update,
         .hwapic_isr_update = vmx_hwapic_isr_update,
+        .sync_pir_to_irr = vmx_sync_pir_to_irr,
+        .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
 
         .set_tss_addr = vmx_set_tss_addr,
         .get_tdp_level = get_ept_level,
@@ -7618,6 +8182,7 @@ static struct kvm_x86_ops vmx_x86_ops = {
         .set_tdp_cr3 = vmx_set_cr3,
 
         .check_intercept = vmx_check_intercept,
+        .handle_external_intr = vmx_handle_external_intr,
 };
 
 static int __init vmx_init(void)
@@ -7656,6 +8221,24 @@ static int __init vmx_init(void)
                                 (unsigned long *)__get_free_page(GFP_KERNEL);
         if (!vmx_msr_bitmap_longmode_x2apic)
                 goto out4;
+        vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
+        if (!vmx_vmread_bitmap)
+                goto out5;
+
+        vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
+        if (!vmx_vmwrite_bitmap)
+                goto out6;
+
+        memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
+        memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
+        /* shadowed read/write fields */
+        for (i = 0; i < max_shadow_read_write_fields; i++) {
+                clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
+                clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
+        }
+        /* shadowed read only fields */
+        for (i = 0; i < max_shadow_read_only_fields; i++)
+                clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
 
         /*
          * Allow direct access to the PC debug port (it is often used for I/O
@@ -7674,7 +8257,7 @@ static int __init vmx_init(void)
         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
                      __alignof__(struct vcpu_vmx), THIS_MODULE);
         if (r)
-                goto out3;
+                goto out7;
 
 #ifdef CONFIG_KEXEC
         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
@@ -7692,7 +8275,7 @@ static int __init vmx_init(void)
         memcpy(vmx_msr_bitmap_longmode_x2apic,
                         vmx_msr_bitmap_longmode, PAGE_SIZE);
 
-        if (enable_apicv_reg_vid) {
+        if (enable_apicv) {
                 for (msr = 0x800; msr <= 0x8ff; msr++)
                         vmx_disable_intercept_msr_read_x2apic(msr);
 
@@ -7722,6 +8305,12 @@ static int __init vmx_init(void)
 
         return 0;
 
+out7:
+        free_page((unsigned long)vmx_vmwrite_bitmap);
+out6:
+        free_page((unsigned long)vmx_vmread_bitmap);
+out5:
+        free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
 out4:
         free_page((unsigned long)vmx_msr_bitmap_longmode);
 out3:
@@ -7743,6 +8332,8 @@ static void __exit vmx_exit(void)
         free_page((unsigned long)vmx_msr_bitmap_longmode);
         free_page((unsigned long)vmx_io_bitmap_b);
         free_page((unsigned long)vmx_io_bitmap_a);
+        free_page((unsigned long)vmx_vmwrite_bitmap);
+        free_page((unsigned long)vmx_vmread_bitmap);
 
 #ifdef CONFIG_KEXEC
         rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index e1721324c271..05a8b1a2300d 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -162,8 +162,6 @@ u64 __read_mostly host_xcr0;
 
 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
 
-static int kvm_vcpu_reset(struct kvm_vcpu *vcpu);
-
 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
 {
         int i;
@@ -263,6 +261,13 @@ void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
 }
 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
 
+asmlinkage void kvm_spurious_fault(void)
+{
+        /* Fault while not rebooting.  We want the trace. */
+        BUG();
+}
+EXPORT_SYMBOL_GPL(kvm_spurious_fault);
+
 #define EXCPT_BENIGN            0
 #define EXCPT_CONTRIBUTORY      1
 #define EXCPT_PF                2
@@ -840,23 +845,17 @@ static const u32 emulated_msrs[] = {
         MSR_IA32_MCG_CTL,
 };
 
-static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
+bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
 {
-        u64 old_efer = vcpu->arch.efer;
-
         if (efer & efer_reserved_bits)
-                return 1;
-
-        if (is_paging(vcpu)
-            && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
-                return 1;
+                return false;
 
         if (efer & EFER_FFXSR) {
                 struct kvm_cpuid_entry2 *feat;
 
                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
                 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
-                        return 1;
+                        return false;
         }
 
         if (efer & EFER_SVME) {
@@ -864,9 +863,24 @@ static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
 
                 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
                 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
-                        return 1;
+                        return false;
         }
 
+        return true;
+}
+EXPORT_SYMBOL_GPL(kvm_valid_efer);
+
+static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
+{
+        u64 old_efer = vcpu->arch.efer;
+
+        if (!kvm_valid_efer(vcpu, efer))
+                return 1;
+
+        if (is_paging(vcpu)
+            && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
+                return 1;
+
         efer &= ~EFER_LMA;
         efer |= vcpu->arch.efer & EFER_LMA;
 
@@ -1079,6 +1093,10 @@ static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
         u32 thresh_lo, thresh_hi;
         int use_scaling = 0;
 
+        /* tsc_khz can be zero if TSC calibration fails */
+        if (this_tsc_khz == 0)
+                return;
+
         /* Compute a scale to convert nanoseconds in TSC cycles */
         kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
                            &vcpu->arch.virtual_tsc_shift,
@@ -1156,20 +1174,23 @@ void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
         ns = get_kernel_ns();
         elapsed = ns - kvm->arch.last_tsc_nsec;
 
-        /* n.b - signed multiplication and division required */
-        usdiff = data - kvm->arch.last_tsc_write;
+        if (vcpu->arch.virtual_tsc_khz) {
+                /* n.b - signed multiplication and division required */
+                usdiff = data - kvm->arch.last_tsc_write;
 #ifdef CONFIG_X86_64
-        usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
+                usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
 #else
-        /* do_div() only does unsigned */
-        asm("idivl %2; xor %%edx, %%edx"
-            : "=A"(usdiff)
-            : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
+                /* do_div() only does unsigned */
+                asm("idivl %2; xor %%edx, %%edx"
+                : "=A"(usdiff)
+                : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
 #endif
-        do_div(elapsed, 1000);
-        usdiff -= elapsed;
-        if (usdiff < 0)
-                usdiff = -usdiff;
+                do_div(elapsed, 1000);
+                usdiff -= elapsed;
+                if (usdiff < 0)
+                        usdiff = -usdiff;
+        } else
+                usdiff = USEC_PER_SEC; /* disable TSC match window below */
 
         /*
          * Special case: TSC write with a small delta (1 second) of virtual
@@ -2034,7 +2055,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
         case MSR_P6_EVNTSEL0:
         case MSR_P6_EVNTSEL1:
                 if (kvm_pmu_msr(vcpu, msr))
-                        return kvm_pmu_set_msr(vcpu, msr, data);
+                        return kvm_pmu_set_msr(vcpu, msr_info);
 
                 if (pr || data != 0)
                         vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
@@ -2080,7 +2101,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
                 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
                         return xen_hvm_config(vcpu, data);
                 if (kvm_pmu_msr(vcpu, msr))
-                        return kvm_pmu_set_msr(vcpu, msr, data);
+                        return kvm_pmu_set_msr(vcpu, msr_info);
                 if (!ignore_msrs) {
                         vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
                                     msr, data);
@@ -2479,7 +2500,6 @@ int kvm_dev_ioctl_check_extension(long ext)
         case KVM_CAP_USER_NMI:
         case KVM_CAP_REINJECT_CONTROL:
         case KVM_CAP_IRQ_INJECT_STATUS:
-        case KVM_CAP_ASSIGN_DEV_IRQ:
         case KVM_CAP_IRQFD:
         case KVM_CAP_IOEVENTFD:
         case KVM_CAP_PIT2:
@@ -2497,10 +2517,12 @@ int kvm_dev_ioctl_check_extension(long ext)
         case KVM_CAP_XSAVE:
         case KVM_CAP_ASYNC_PF:
         case KVM_CAP_GET_TSC_KHZ:
-        case KVM_CAP_PCI_2_3:
         case KVM_CAP_KVMCLOCK_CTRL:
         case KVM_CAP_READONLY_MEM:
-        case KVM_CAP_IRQFD_RESAMPLE:
+#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
+        case KVM_CAP_ASSIGN_DEV_IRQ:
+        case KVM_CAP_PCI_2_3:
+#endif
                 r = 1;
                 break;
         case KVM_CAP_COALESCED_MMIO:
@@ -2521,9 +2543,11 @@ int kvm_dev_ioctl_check_extension(long ext)
         case KVM_CAP_PV_MMU:    /* obsolete */
                 r = 0;
                 break;
+#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
         case KVM_CAP_IOMMU:
                 r = iommu_present(&pci_bus_type);
                 break;
+#endif
         case KVM_CAP_MCE:
                 r = KVM_MAX_MCE_BANKS;
                 break;
@@ -2679,6 +2703,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
                                     struct kvm_lapic_state *s)
 {
+        kvm_x86_ops->sync_pir_to_irr(vcpu);
         memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
 
         return 0;
@@ -2696,7 +2721,7 @@ static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
                                     struct kvm_interrupt *irq)
 {
-        if (irq->irq < 0 || irq->irq >= KVM_NR_INTERRUPTS)
+        if (irq->irq >= KVM_NR_INTERRUPTS)
                 return -EINVAL;
         if (irqchip_in_kernel(vcpu->kvm))
                 return -ENXIO;
@@ -2819,10 +2844,9 @@ static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
         events->nmi.pad = 0;
 
-        events->sipi_vector = vcpu->arch.sipi_vector;
+        events->sipi_vector = 0; /* never valid when reporting to user space */
 
         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
-                         | KVM_VCPUEVENT_VALID_SIPI_VECTOR
                          | KVM_VCPUEVENT_VALID_SHADOW);
         memset(&events->reserved, 0, sizeof(events->reserved));
 }
@@ -2853,8 +2877,9 @@ static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
                 vcpu->arch.nmi_pending = events->nmi.pending;
         kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
 
-        if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
-                vcpu->arch.sipi_vector = events->sipi_vector;
+        if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
+            kvm_vcpu_has_lapic(vcpu))
+                vcpu->arch.apic->sipi_vector = events->sipi_vector;
 
         kvm_make_request(KVM_REQ_EVENT, vcpu);
 
@@ -3478,13 +3503,15 @@ out:
         return r;
 }
 
-int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
+int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
+                        bool line_status)
 {
         if (!irqchip_in_kernel(kvm))
                 return -ENXIO;
 
         irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
-                                        irq_event->irq, irq_event->level);
+                                        irq_event->irq, irq_event->level,
+                                        line_status);
         return 0;
 }
 
@@ -4752,11 +4779,15 @@ static int handle_emulation_failure(struct kvm_vcpu *vcpu)
 }
 
 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
-                                  bool write_fault_to_shadow_pgtable)
+                                  bool write_fault_to_shadow_pgtable,
+                                  int emulation_type)
 {
         gpa_t gpa = cr2;
         pfn_t pfn;
 
+        if (emulation_type & EMULTYPE_NO_REEXECUTE)
+                return false;
+
         if (!vcpu->arch.mmu.direct_map) {
                 /*
                  * Write permission should be allowed since only
@@ -4899,8 +4930,8 @@ int x86_emulate_instruction(struct kvm_vcpu *vcpu,
                 if (r != EMULATION_OK)  {
                         if (emulation_type & EMULTYPE_TRAP_UD)
                                 return EMULATE_FAIL;
-                        if (reexecute_instruction(vcpu, cr2,
-                                                  write_fault_to_spt))
+                        if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
+                                                emulation_type))
                                 return EMULATE_DONE;
                         if (emulation_type & EMULTYPE_SKIP)
                                 return EMULATE_FAIL;
@@ -4930,7 +4961,8 @@ restart:
                 return EMULATE_DONE;
 
         if (r == EMULATION_FAILED) {
-                if (reexecute_instruction(vcpu, cr2, write_fault_to_spt))
+                if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
+                                        emulation_type))
                         return EMULATE_DONE;
 
                 return handle_emulation_failure(vcpu);
@@ -5641,14 +5673,20 @@ static void kvm_gen_update_masterclock(struct kvm *kvm)
 #endif
 }
 
-static void update_eoi_exitmap(struct kvm_vcpu *vcpu)
+static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
 {
         u64 eoi_exit_bitmap[4];
+        u32 tmr[8];
+
+        if (!kvm_apic_hw_enabled(vcpu->arch.apic))
+                return;
 
         memset(eoi_exit_bitmap, 0, 32);
+        memset(tmr, 0, 32);
 
-        kvm_ioapic_calculate_eoi_exitmap(vcpu, eoi_exit_bitmap);
+        kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
         kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
+        kvm_apic_update_tmr(vcpu, tmr);
 }
 
 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
@@ -5656,7 +5694,7 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
         int r;
         bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
                 vcpu->run->request_interrupt_window;
-        bool req_immediate_exit = 0;
+        bool req_immediate_exit = false;
 
         if (vcpu->requests) {
                 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
@@ -5698,24 +5736,30 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
                         record_steal_time(vcpu);
                 if (kvm_check_request(KVM_REQ_NMI, vcpu))
                         process_nmi(vcpu);
-                req_immediate_exit =
-                        kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
                 if (kvm_check_request(KVM_REQ_PMU, vcpu))
                         kvm_handle_pmu_event(vcpu);
                 if (kvm_check_request(KVM_REQ_PMI, vcpu))
                         kvm_deliver_pmi(vcpu);
-                if (kvm_check_request(KVM_REQ_EOIBITMAP, vcpu))
-                        update_eoi_exitmap(vcpu);
+                if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
+                        vcpu_scan_ioapic(vcpu);
         }
 
         if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
+                kvm_apic_accept_events(vcpu);
+                if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
+                        r = 1;
+                        goto out;
+                }
+
                 inject_pending_event(vcpu);
 
                 /* enable NMI/IRQ window open exits if needed */
                 if (vcpu->arch.nmi_pending)
-                        kvm_x86_ops->enable_nmi_window(vcpu);
+                        req_immediate_exit =
+                                kvm_x86_ops->enable_nmi_window(vcpu) != 0;
                 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
-                        kvm_x86_ops->enable_irq_window(vcpu);
+                        req_immediate_exit =
+                                kvm_x86_ops->enable_irq_window(vcpu) != 0;
 
                 if (kvm_lapic_enabled(vcpu)) {
                         /*
@@ -5794,7 +5838,9 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
 
         vcpu->mode = OUTSIDE_GUEST_MODE;
         smp_wmb();
-        local_irq_enable();
+
+        /* Interrupt is enabled by handle_external_intr() */
+        kvm_x86_ops->handle_external_intr(vcpu);
 
         ++vcpu->stat.exits;
 
@@ -5843,16 +5889,6 @@ static int __vcpu_run(struct kvm_vcpu *vcpu)
         int r;
         struct kvm *kvm = vcpu->kvm;
 
-        if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
-                pr_debug("vcpu %d received sipi with vector # %x\n",
-                         vcpu->vcpu_id, vcpu->arch.sipi_vector);
-                kvm_lapic_reset(vcpu);
-                r = kvm_vcpu_reset(vcpu);
-                if (r)
-                        return r;
-                vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
-        }
-
         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
         r = vapic_enter(vcpu);
         if (r) {
@@ -5869,8 +5905,8 @@ static int __vcpu_run(struct kvm_vcpu *vcpu)
                         srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
                         kvm_vcpu_block(vcpu);
                         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
-                        if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
-                        {
+                        if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
+                                kvm_apic_accept_events(vcpu);
                                 switch(vcpu->arch.mp_state) {
                                 case KVM_MP_STATE_HALTED:
                                         vcpu->arch.mp_state =
@@ -5878,7 +5914,8 @@ static int __vcpu_run(struct kvm_vcpu *vcpu)
                                 case KVM_MP_STATE_RUNNABLE:
                                         vcpu->arch.apf.halted = false;
                                         break;
-                                case KVM_MP_STATE_SIPI_RECEIVED:
+                                case KVM_MP_STATE_INIT_RECEIVED:
+                                        break;
                                 default:
                                         r = -EINTR;
                                         break;
@@ -6013,6 +6050,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
 
         if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
                 kvm_vcpu_block(vcpu);
+                kvm_apic_accept_events(vcpu);
                 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
                 r = -EAGAIN;
                 goto out;
@@ -6169,6 +6207,7 @@ int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
                                     struct kvm_mp_state *mp_state)
 {
+        kvm_apic_accept_events(vcpu);
         mp_state->mp_state = vcpu->arch.mp_state;
         return 0;
 }
@@ -6176,7 +6215,15 @@ int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
                                     struct kvm_mp_state *mp_state)
 {
-        vcpu->arch.mp_state = mp_state->mp_state;
+        if (!kvm_vcpu_has_lapic(vcpu) &&
+            mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
+                return -EINVAL;
+
+        if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
+                vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
+                set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
+        } else
+                vcpu->arch.mp_state = mp_state->mp_state;
         kvm_make_request(KVM_REQ_EVENT, vcpu);
         return 0;
 }
@@ -6475,9 +6522,8 @@ int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
         r = vcpu_load(vcpu);
         if (r)
                 return r;
-        r = kvm_vcpu_reset(vcpu);
-        if (r == 0)
-                r = kvm_mmu_setup(vcpu);
+        kvm_vcpu_reset(vcpu);
+        r = kvm_mmu_setup(vcpu);
         vcpu_put(vcpu);
 
         return r;
@@ -6514,7 +6560,7 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
         kvm_x86_ops->vcpu_free(vcpu);
 }
 
-static int kvm_vcpu_reset(struct kvm_vcpu *vcpu)
+void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
 {
         atomic_set(&vcpu->arch.nmi_queued, 0);
         vcpu->arch.nmi_pending = 0;
@@ -6541,7 +6587,18 @@ static int kvm_vcpu_reset(struct kvm_vcpu *vcpu)
         vcpu->arch.regs_avail = ~0;
         vcpu->arch.regs_dirty = ~0;
 
-        return kvm_x86_ops->vcpu_reset(vcpu);
+        kvm_x86_ops->vcpu_reset(vcpu);
+}
+
+void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
+{
+        struct kvm_segment cs;
+
+        kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
+        cs.selector = vector << 8;
+        cs.base = vector << 12;
+        kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
+        kvm_rip_write(vcpu, 0);
 }
 
 int kvm_arch_hardware_enable(void *garbage)
@@ -6706,8 +6763,10 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
         }
         vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
 
-        if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
+        if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
+                r = -ENOMEM;
                 goto fail_free_mce_banks;
+        }
 
         r = fx_init(vcpu);
         if (r)
@@ -6811,6 +6870,23 @@ void kvm_arch_sync_events(struct kvm *kvm)
 
 void kvm_arch_destroy_vm(struct kvm *kvm)
 {
+        if (current->mm == kvm->mm) {
+                /*
+                 * Free memory regions allocated on behalf of userspace,
+                 * unless the the memory map has changed due to process exit
+                 * or fd copying.
+                 */
+                struct kvm_userspace_memory_region mem;
+                memset(&mem, 0, sizeof(mem));
+                mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
+                kvm_set_memory_region(kvm, &mem);
+
+                mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
+                kvm_set_memory_region(kvm, &mem);
+
+                mem.slot = TSS_PRIVATE_MEMSLOT;
+                kvm_set_memory_region(kvm, &mem);
+        }
         kvm_iommu_unmap_guest(kvm);
         kfree(kvm->arch.vpic);
         kfree(kvm->arch.vioapic);
@@ -6903,24 +6979,21 @@ out_free:
 
 int kvm_arch_prepare_memory_region(struct kvm *kvm,
                                 struct kvm_memory_slot *memslot,
-                                struct kvm_memory_slot old,
                                 struct kvm_userspace_memory_region *mem,
-                                bool user_alloc)
+                                enum kvm_mr_change change)
 {
-        int npages = memslot->npages;
-
         /*
          * Only private memory slots need to be mapped here since
          * KVM_SET_MEMORY_REGION ioctl is no longer supported.
          */
-        if ((memslot->id >= KVM_USER_MEM_SLOTS) && npages && !old.npages) {
+        if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
                 unsigned long userspace_addr;
 
                 /*
                  * MAP_SHARED to prevent internal slot pages from being moved
                  * by fork()/COW.
                  */
-                userspace_addr = vm_mmap(NULL, 0, npages * PAGE_SIZE,
+                userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
                                          PROT_READ | PROT_WRITE,
                                          MAP_SHARED | MAP_ANONYMOUS, 0);
 
@@ -6935,17 +7008,17 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
 
 void kvm_arch_commit_memory_region(struct kvm *kvm,
                                 struct kvm_userspace_memory_region *mem,
-                                struct kvm_memory_slot old,
-                                bool user_alloc)
+                                const struct kvm_memory_slot *old,
+                                enum kvm_mr_change change)
 {
 
-        int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
+        int nr_mmu_pages = 0;
 
-        if ((mem->slot >= KVM_USER_MEM_SLOTS) && old.npages && !npages) {
+        if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
                 int ret;
 
-                ret = vm_munmap(old.userspace_addr,
-                                old.npages * PAGE_SIZE);
+                ret = vm_munmap(old->userspace_addr,
+                                old->npages * PAGE_SIZE);
                 if (ret < 0)
                         printk(KERN_WARNING
                                "kvm_vm_ioctl_set_memory_region: "
@@ -6962,14 +7035,14 @@ void kvm_arch_commit_memory_region(struct kvm *kvm,
          * Existing largepage mappings are destroyed here and new ones will
          * not be created until the end of the logging.
          */
-        if (npages && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
+        if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
                 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
         /*
          * If memory slot is created, or moved, we need to clear all
          * mmio sptes.
          */
-        if (npages && old.base_gfn != mem->guest_phys_addr >> PAGE_SHIFT) {
-                kvm_mmu_zap_all(kvm);
+        if ((change == KVM_MR_CREATE) || (change == KVM_MR_MOVE)) {
+                kvm_mmu_zap_mmio_sptes(kvm);
                 kvm_reload_remote_mmus(kvm);
         }
 }
@@ -6991,7 +7064,7 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
         return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
                 !vcpu->arch.apf.halted)
                 || !list_empty_careful(&vcpu->async_pf.done)
-                || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
+                || kvm_apic_has_events(vcpu)
                 || atomic_read(&vcpu->arch.nmi_queued) ||
                 (kvm_arch_interrupt_allowed(vcpu) &&
                  kvm_cpu_has_interrupt(vcpu));
diff --git a/arch/x86/lguest/Kconfig b/arch/x86/lguest/Kconfig
index 29043d2048a0..4a0890f815c4 100644
--- a/arch/x86/lguest/Kconfig
+++ b/arch/x86/lguest/Kconfig
@@ -1,7 +1,6 @@
 config LGUEST_GUEST
         bool "Lguest guest support"
-        select PARAVIRT
-        depends on X86_32
+        depends on X86_32 && PARAVIRT
         select TTY
         select VIRTUALIZATION
         select VIRTIO
diff --git a/arch/x86/lib/checksum_32.S b/arch/x86/lib/checksum_32.S
index 2af5df3ade7c..e78b8eee6615 100644
--- a/arch/x86/lib/checksum_32.S
+++ b/arch/x86/lib/checksum_32.S
@@ -61,7 +61,7 @@ ENTRY(csum_partial)
         testl $3, %esi          # Check alignment.
         jz 2f                   # Jump if alignment is ok.
         testl $1, %esi          # Check alignment.
-        jz 10f                  # Jump if alignment is boundary of 2bytes.
+        jz 10f                  # Jump if alignment is boundary of 2 bytes.
 
         # buf is odd
         dec %ecx
diff --git a/arch/x86/lib/memcpy_32.c b/arch/x86/lib/memcpy_32.c
index b908a59eccf5..e78761d6b7f8 100644
--- a/arch/x86/lib/memcpy_32.c
+++ b/arch/x86/lib/memcpy_32.c
@@ -26,7 +26,7 @@ void *memmove(void *dest, const void *src, size_t n)
         char *ret = dest;
 
         __asm__ __volatile__(
-                /* Handle more 16bytes in loop */
+                /* Handle more 16 bytes in loop */
                 "cmp $0x10, %0\n\t"
                 "jb     1f\n\t"
 
@@ -51,7 +51,7 @@ void *memmove(void *dest, const void *src, size_t n)
                 "sub $0x10, %0\n\t"
 
                 /*
-                 * We gobble 16byts forward in each loop.
+                 * We gobble 16 bytes forward in each loop.
                  */
                 "3:\n\t"
                 "sub $0x10, %0\n\t"
@@ -117,7 +117,7 @@ void *memmove(void *dest, const void *src, size_t n)
                 "sub $0x10, %0\n\t"
 
                 /*
-                 * We gobble 16byts backward in each loop.
+                 * We gobble 16 bytes backward in each loop.
                  */
                 "7:\n\t"
                 "sub $0x10, %0\n\t"
diff --git a/arch/x86/lib/memcpy_64.S b/arch/x86/lib/memcpy_64.S
index 1c273be7c97e..56313a326188 100644
--- a/arch/x86/lib/memcpy_64.S
+++ b/arch/x86/lib/memcpy_64.S
@@ -98,7 +98,7 @@ ENTRY(memcpy)
         subq $0x20,     %rdx
         /*
          * At most 3 ALU operations in one cycle,
-         * so append NOPS in the same 16bytes trunk.
+         * so append NOPS in the same 16 bytes trunk.
          */
         .p2align 4
 .Lcopy_backward_loop:
diff --git a/arch/x86/lib/memmove_64.S b/arch/x86/lib/memmove_64.S
index ee164610ec46..65268a6104f4 100644
--- a/arch/x86/lib/memmove_64.S
+++ b/arch/x86/lib/memmove_64.S
@@ -27,7 +27,7 @@
 ENTRY(memmove)
         CFI_STARTPROC
 
-        /* Handle more 32bytes in loop */
+        /* Handle more 32 bytes in loop */
         mov %rdi, %rax
         cmp $0x20, %rdx
         jb      1f
@@ -56,7 +56,7 @@ ENTRY(memmove)
 3:
         sub $0x20, %rdx
         /*
-         * We gobble 32byts forward in each loop.
+         * We gobble 32 bytes forward in each loop.
          */
 5:
         sub $0x20, %rdx
@@ -122,7 +122,7 @@ ENTRY(memmove)
         addq %rdx, %rdi
         subq $0x20, %rdx
         /*
-         * We gobble 32byts backward in each loop.
+         * We gobble 32 bytes backward in each loop.
          */
 8:
         subq $0x20, %rdx
diff --git a/arch/x86/lib/usercopy_32.c b/arch/x86/lib/usercopy_32.c
index f0312d746402..3eb18acd0e40 100644
--- a/arch/x86/lib/usercopy_32.c
+++ b/arch/x86/lib/usercopy_32.c
@@ -689,9 +689,3 @@ _copy_from_user(void *to, const void __user *from, unsigned long n)
         return n;
 }
 EXPORT_SYMBOL(_copy_from_user);
-
-void copy_from_user_overflow(void)
-{
-        WARN(1, "Buffer overflow detected!\n");
-}
-EXPORT_SYMBOL(copy_from_user_overflow);
diff --git a/arch/x86/mm/amdtopology.c b/arch/x86/mm/amdtopology.c
index 5247d01329ca..2ca15b59fb3f 100644
--- a/arch/x86/mm/amdtopology.c
+++ b/arch/x86/mm/amdtopology.c
@@ -130,9 +130,8 @@ int __init amd_numa_init(void)
                 }
 
                 limit >>= 16;
-                limit <<= 24;
-                limit |= (1<<24)-1;
                 limit++;
+                limit <<= 24;
 
                 if (limit > end)
                         limit = end;
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index 0e883364abb5..654be4ae3047 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -13,12 +13,12 @@
 #include <linux/perf_event.h>           /* perf_sw_event                */
 #include <linux/hugetlb.h>              /* hstate_index_to_shift        */
 #include <linux/prefetch.h>             /* prefetchw                    */
+#include <linux/context_tracking.h>     /* exception_enter(), ...       */
 
 #include <asm/traps.h>                  /* dotraplinkage, ...           */
 #include <asm/pgalloc.h>                /* pgd_*(), ...                 */
 #include <asm/kmemcheck.h>              /* kmemcheck_*(), ...           */
 #include <asm/fixmap.h>                 /* VSYSCALL_START               */
-#include <asm/context_tracking.h>       /* exception_enter(), ...       */
 
 /*
  * Page fault error code bits:
@@ -557,7 +557,7 @@ static int is_f00f_bug(struct pt_regs *regs, unsigned long address)
         /*
          * Pentium F0 0F C7 C8 bug workaround:
          */
-        if (boot_cpu_data.f00f_bug) {
+        if (boot_cpu_has_bug(X86_BUG_F00F)) {
                 nr = (address - idt_descr.address) >> 3;
 
                 if (nr == 6) {
@@ -1224,7 +1224,9 @@ good_area:
 dotraplinkage void __kprobes
 do_page_fault(struct pt_regs *regs, unsigned long error_code)
 {
-        exception_enter(regs);
+        enum ctx_state prev_state;
+
+        prev_state = exception_enter();
         __do_page_fault(regs, error_code);
-        exception_exit(regs);
+        exception_exit(prev_state);
 }
diff --git a/arch/x86/mm/highmem_32.c b/arch/x86/mm/highmem_32.c
index 6f31ee56c008..252b8f5489ba 100644
--- a/arch/x86/mm/highmem_32.c
+++ b/arch/x86/mm/highmem_32.c
@@ -137,5 +137,4 @@ void __init set_highmem_pages_init(void)
                 add_highpages_with_active_regions(nid, zone_start_pfn,
                                  zone_end_pfn);
         }
-        totalram_pages += totalhigh_pages;
 }
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index 59b7fc453277..fdc5dca14fb3 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -515,11 +515,8 @@ void free_init_pages(char *what, unsigned long begin, unsigned long end)
         printk(KERN_INFO "Freeing %s: %luk freed\n", what, (end - begin) >> 10);
 
         for (; addr < end; addr += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(addr));
-                init_page_count(virt_to_page(addr));
                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
-                free_page(addr);
-                totalram_pages++;
+                free_reserved_page(virt_to_page(addr));
         }
 #endif
 }
diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c
index 2d19001151d5..3ac7e319918d 100644
--- a/arch/x86/mm/init_32.c
+++ b/arch/x86/mm/init_32.c
@@ -427,14 +427,6 @@ static void __init permanent_kmaps_init(pgd_t *pgd_base)
         pkmap_page_table = pte;
 }
 
-static void __init add_one_highpage_init(struct page *page)
-{
-        ClearPageReserved(page);
-        init_page_count(page);
-        __free_page(page);
-        totalhigh_pages++;
-}
-
 void __init add_highpages_with_active_regions(int nid,
                          unsigned long start_pfn, unsigned long end_pfn)
 {
@@ -448,7 +440,7 @@ void __init add_highpages_with_active_regions(int nid,
                                               start_pfn, end_pfn);
                 for ( ; pfn < e_pfn; pfn++)
                         if (pfn_valid(pfn))
-                                add_one_highpage_init(pfn_to_page(pfn));
+                                free_highmem_page(pfn_to_page(pfn));
         }
 }
 #else
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index 474e28f10815..bb00c4672ad6 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -32,6 +32,7 @@
 #include <linux/memory_hotplug.h>
 #include <linux/nmi.h>
 #include <linux/gfp.h>
+#include <linux/kcore.h>
 
 #include <asm/processor.h>
 #include <asm/bios_ebda.h>
@@ -1011,14 +1012,12 @@ remove_pagetable(unsigned long start, unsigned long end, bool direct)
         flush_tlb_all();
 }
 
-void __ref vmemmap_free(struct page *memmap, unsigned long nr_pages)
+void __ref vmemmap_free(unsigned long start, unsigned long end)
 {
-        unsigned long start = (unsigned long)memmap;
-        unsigned long end = (unsigned long)(memmap + nr_pages);
-
         remove_pagetable(start, end, false);
 }
 
+#ifdef CONFIG_MEMORY_HOTREMOVE
 static void __meminit
 kernel_physical_mapping_remove(unsigned long start, unsigned long end)
 {
@@ -1028,7 +1027,6 @@ kernel_physical_mapping_remove(unsigned long start, unsigned long end)
         remove_pagetable(start, end, true);
 }
 
-#ifdef CONFIG_MEMORY_HOTREMOVE
 int __ref arch_remove_memory(u64 start, u64 size)
 {
         unsigned long start_pfn = start >> PAGE_SHIFT;
@@ -1067,10 +1065,9 @@ void __init mem_init(void)
 
         /* clear_bss() already clear the empty_zero_page */
 
-        reservedpages = 0;
-
-        /* this will put all low memory onto the freelists */
         register_page_bootmem_info();
+
+        /* this will put all memory onto the freelists */
         totalram_pages = free_all_bootmem();
 
         absent_pages = absent_pages_in_range(0, max_pfn);
@@ -1285,18 +1282,17 @@ static long __meminitdata addr_start, addr_end;
 static void __meminitdata *p_start, *p_end;
 static int __meminitdata node_start;
 
-int __meminit
-vmemmap_populate(struct page *start_page, unsigned long size, int node)
+static int __meminit vmemmap_populate_hugepages(unsigned long start,
+                                                unsigned long end, int node)
 {
-        unsigned long addr = (unsigned long)start_page;
-        unsigned long end = (unsigned long)(start_page + size);
+        unsigned long addr;
         unsigned long next;
         pgd_t *pgd;
         pud_t *pud;
         pmd_t *pmd;
 
-        for (; addr < end; addr = next) {
-                void *p = NULL;
+        for (addr = start; addr < end; addr = next) {
+                next = pmd_addr_end(addr, end);
 
                 pgd = vmemmap_pgd_populate(addr, node);
                 if (!pgd)
@@ -1306,31 +1302,14 @@ vmemmap_populate(struct page *start_page, unsigned long size, int node)
                 if (!pud)
                         return -ENOMEM;
 
-                if (!cpu_has_pse) {
-                        next = (addr + PAGE_SIZE) & PAGE_MASK;
-                        pmd = vmemmap_pmd_populate(pud, addr, node);
-
-                        if (!pmd)
-                                return -ENOMEM;
-
-                        p = vmemmap_pte_populate(pmd, addr, node);
+                pmd = pmd_offset(pud, addr);
+                if (pmd_none(*pmd)) {
+                        void *p;
 
-                        if (!p)
-                                return -ENOMEM;
-
-                        addr_end = addr + PAGE_SIZE;
-                        p_end = p + PAGE_SIZE;
-                } else {
-                        next = pmd_addr_end(addr, end);
-
-                        pmd = pmd_offset(pud, addr);
-                        if (pmd_none(*pmd)) {
+                        p = vmemmap_alloc_block_buf(PMD_SIZE, node);
+                        if (p) {
                                 pte_t entry;
 
-                                p = vmemmap_alloc_block_buf(PMD_SIZE, node);
-                                if (!p)
-                                        return -ENOMEM;
-
                                 entry = pfn_pte(__pa(p) >> PAGE_SHIFT,
                                                 PAGE_KERNEL_LARGE);
                                 set_pmd(pmd, __pmd(pte_val(entry)));
@@ -1347,15 +1326,32 @@ vmemmap_populate(struct page *start_page, unsigned long size, int node)
 
                                 addr_end = addr + PMD_SIZE;
                                 p_end = p + PMD_SIZE;
-                        } else
-                                vmemmap_verify((pte_t *)pmd, node, addr, next);
+                                continue;
+                        }
+                } else if (pmd_large(*pmd)) {
+                        vmemmap_verify((pte_t *)pmd, node, addr, next);
+                        continue;
                 }
-
+                pr_warn_once("vmemmap: falling back to regular page backing\n");
+                if (vmemmap_populate_basepages(addr, next, node))
+                        return -ENOMEM;
         }
-        sync_global_pgds((unsigned long)start_page, end - 1);
         return 0;
 }
 
+int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node)
+{
+        int err;
+
+        if (cpu_has_pse)
+                err = vmemmap_populate_hugepages(start, end, node);
+        else
+                err = vmemmap_populate_basepages(start, end, node);
+        if (!err)
+                sync_global_pgds(start, end - 1);
+        return err;
+}
+
 #if defined(CONFIG_MEMORY_HOTPLUG_SPARSE) && defined(CONFIG_HAVE_BOOTMEM_INFO_NODE)
 void register_page_bootmem_memmap(unsigned long section_nr,
                                   struct page *start_page, unsigned long size)
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index 78fe3f1ac49f..9a1e6583910c 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -282,12 +282,7 @@ void iounmap(volatile void __iomem *addr)
            in parallel. Reuse of the virtual address is prevented by
            leaving it in the global lists until we're done with it.
            cpa takes care of the direct mappings. */
-        read_lock(&vmlist_lock);
-        for (p = vmlist; p; p = p->next) {
-                if (p->addr == (void __force *)addr)
-                        break;
-        }
-        read_unlock(&vmlist_lock);
+        p = find_vm_area((void __force *)addr);
 
         if (!p) {
                 printk(KERN_ERR "iounmap: bad address %p\n", addr);
diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c
index 72fe01e9e414..a71c4e207679 100644
--- a/arch/x86/mm/numa.c
+++ b/arch/x86/mm/numa.c
@@ -114,14 +114,11 @@ void numa_clear_node(int cpu)
  */
 void __init setup_node_to_cpumask_map(void)
 {
-        unsigned int node, num = 0;
+        unsigned int node;
 
         /* setup nr_node_ids if not done yet */
-        if (nr_node_ids == MAX_NUMNODES) {
-                for_each_node_mask(node, node_possible_map)
-                        num = node;
-                nr_node_ids = num + 1;
-        }
+        if (nr_node_ids == MAX_NUMNODES)
+                setup_nr_node_ids();
 
         /* allocate the map */
         for (node = 0; node < nr_node_ids; node++)
diff --git a/arch/x86/mm/pageattr-test.c b/arch/x86/mm/pageattr-test.c
index 0e38951e65eb..d0b1773d9d2e 100644
--- a/arch/x86/mm/pageattr-test.c
+++ b/arch/x86/mm/pageattr-test.c
@@ -130,13 +130,12 @@ static int pageattr_test(void)
         }
 
         failed += print_split(&sa);
-        srandom32(100);
 
         for (i = 0; i < NTEST; i++) {
-                unsigned long pfn = random32() % max_pfn_mapped;
+                unsigned long pfn = prandom_u32() % max_pfn_mapped;
 
                 addr[i] = (unsigned long)__va(pfn << PAGE_SHIFT);
-                len[i] = random32() % 100;
+                len[i] = prandom_u32() % 100;
                 len[i] = min_t(unsigned long, len[i], max_pfn_mapped - pfn - 1);
 
                 if (len[i] == 0)
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index fb4e73ec24d8..bb32480c2d71 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -542,13 +542,14 @@ out_unlock:
         return do_split;
 }
 
-int __split_large_page(pte_t *kpte, unsigned long address, pte_t *pbase)
+static int
+__split_large_page(pte_t *kpte, unsigned long address, struct page *base)
 {
+        pte_t *pbase = (pte_t *)page_address(base);
         unsigned long pfn, pfninc = 1;
         unsigned int i, level;
         pte_t *tmp;
         pgprot_t ref_prot;
-        struct page *base = virt_to_page(pbase);
 
         spin_lock(&pgd_lock);
         /*
@@ -633,7 +634,6 @@ int __split_large_page(pte_t *kpte, unsigned long address, pte_t *pbase)
 
 static int split_large_page(pte_t *kpte, unsigned long address)
 {
-        pte_t *pbase;
         struct page *base;
 
         if (!debug_pagealloc)
@@ -644,8 +644,7 @@ static int split_large_page(pte_t *kpte, unsigned long address)
         if (!base)
                 return -ENOMEM;
 
-        pbase = (pte_t *)page_address(base);
-        if (__split_large_page(kpte, address, pbase))
+        if (__split_large_page(kpte, address, base))
                 __free_page(base);
 
         return 0;
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index 901177d75ff5..305c68b8d538 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -6,6 +6,7 @@
 
 #include <linux/sched.h>
 #include <linux/pci.h>
+#include <linux/pci-acpi.h>
 #include <linux/ioport.h>
 #include <linux/init.h>
 #include <linux/dmi.h>
@@ -170,6 +171,16 @@ void pcibios_fixup_bus(struct pci_bus *b)
                 pcibios_fixup_device_resources(dev);
 }
 
+void pcibios_add_bus(struct pci_bus *bus)
+{
+        acpi_pci_add_bus(bus);
+}
+
+void pcibios_remove_bus(struct pci_bus *bus)
+{
+        acpi_pci_remove_bus(bus);
+}
+
 /*
  * Only use DMI information to set this if nothing was passed
  * on the kernel command line (which was parsed earlier).
diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c
index 94e76620460f..4a9be6ddf054 100644
--- a/arch/x86/pci/xen.c
+++ b/arch/x86/pci/xen.c
@@ -177,7 +177,7 @@ static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
                 goto error;
         i = 0;
         list_for_each_entry(msidesc, &dev->msi_list, list) {
-                irq = xen_bind_pirq_msi_to_irq(dev, msidesc, v[i], 0,
+                irq = xen_bind_pirq_msi_to_irq(dev, msidesc, v[i],
                                                (type == PCI_CAP_ID_MSIX) ?
                                                "pcifront-msi-x" :
                                                "pcifront-msi",
@@ -244,7 +244,7 @@ static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
                         dev_dbg(&dev->dev,
                                 "xen: msi already bound to pirq=%d\n", pirq);
                 }
-                irq = xen_bind_pirq_msi_to_irq(dev, msidesc, pirq, 0,
+                irq = xen_bind_pirq_msi_to_irq(dev, msidesc, pirq,
                                                (type == PCI_CAP_ID_MSIX) ?
                                                "msi-x" : "msi",
                                                DOMID_SELF);
@@ -326,7 +326,7 @@ static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
                 }
 
                 ret = xen_bind_pirq_msi_to_irq(dev, msidesc,
-                                               map_irq.pirq, map_irq.index,
+                                               map_irq.pirq,
                                                (type == PCI_CAP_ID_MSIX) ?
                                                "msi-x" : "msi",
                                                 domid);
diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c
index e4a86a677ce1..55856b2310d3 100644
--- a/arch/x86/platform/efi/efi.c
+++ b/arch/x86/platform/efi/efi.c
@@ -34,6 +34,7 @@
 #include <linux/efi-bgrt.h>
 #include <linux/export.h>
 #include <linux/bootmem.h>
+#include <linux/slab.h>
 #include <linux/memblock.h>
 #include <linux/spinlock.h>
 #include <linux/uaccess.h>
@@ -49,6 +50,7 @@
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
 #include <asm/x86_init.h>
+#include <asm/rtc.h>
 
 #define EFI_DEBUG       1
 
@@ -352,10 +354,10 @@ static efi_status_t __init phys_efi_get_time(efi_time_t *tm,
 
 int efi_set_rtc_mmss(unsigned long nowtime)
 {
-        int real_seconds, real_minutes;
         efi_status_t    status;
         efi_time_t      eft;
         efi_time_cap_t  cap;
+        struct rtc_time tm;
 
         status = efi.get_time(&eft, &cap);
         if (status != EFI_SUCCESS) {
@@ -363,13 +365,20 @@ int efi_set_rtc_mmss(unsigned long nowtime)
                 return -1;
         }
 
-        real_seconds = nowtime % 60;
-        real_minutes = nowtime / 60;
-        if (((abs(real_minutes - eft.minute) + 15)/30) & 1)
-                real_minutes += 30;
-        real_minutes %= 60;
-        eft.minute = real_minutes;
-        eft.second = real_seconds;
+        rtc_time_to_tm(nowtime, &tm);
+        if (!rtc_valid_tm(&tm)) {
+                eft.year = tm.tm_year + 1900;
+                eft.month = tm.tm_mon + 1;
+                eft.day = tm.tm_mday;
+                eft.minute = tm.tm_min;
+                eft.second = tm.tm_sec;
+                eft.nanosecond = 0;
+        } else {
+                printk(KERN_ERR
+                       "%s: Invalid EFI RTC value: write of %lx to EFI RTC failed\n",
+                       __FUNCTION__, nowtime);
+                return -1;
+        }
 
         status = efi.set_time(&eft);
         if (status != EFI_SUCCESS) {
@@ -445,24 +454,25 @@ static void __init do_add_efi_memmap(void)
 
 int __init efi_memblock_x86_reserve_range(void)
 {
+        struct efi_info *e = &boot_params.efi_info;
         unsigned long pmap;
 
 #ifdef CONFIG_X86_32
         /* Can't handle data above 4GB at this time */
-        if (boot_params.efi_info.efi_memmap_hi) {
+        if (e->efi_memmap_hi) {
                 pr_err("Memory map is above 4GB, disabling EFI.\n");
                 return -EINVAL;
         }
-        pmap = boot_params.efi_info.efi_memmap;
+        pmap =  e->efi_memmap;
 #else
-        pmap = (boot_params.efi_info.efi_memmap |
-                ((__u64)boot_params.efi_info.efi_memmap_hi<<32));
+        pmap = (e->efi_memmap | ((__u64)e->efi_memmap_hi << 32));
 #endif
-        memmap.phys_map = (void *)pmap;
-        memmap.nr_map = boot_params.efi_info.efi_memmap_size /
-                boot_params.efi_info.efi_memdesc_size;
-        memmap.desc_version = boot_params.efi_info.efi_memdesc_version;
-        memmap.desc_size = boot_params.efi_info.efi_memdesc_size;
+        memmap.phys_map         = (void *)pmap;
+        memmap.nr_map           = e->efi_memmap_size /
+                                  e->efi_memdesc_size;
+        memmap.desc_size        = e->efi_memdesc_size;
+        memmap.desc_version     = e->efi_memdesc_version;
+
         memblock_reserve(pmap, memmap.nr_map * memmap.desc_size);
 
         return 0;
diff --git a/arch/x86/platform/efi/efi_64.c b/arch/x86/platform/efi/efi_64.c
index 2b2003860615..39a0e7f1f0a3 100644
--- a/arch/x86/platform/efi/efi_64.c
+++ b/arch/x86/platform/efi/efi_64.c
@@ -27,6 +27,7 @@
 #include <linux/uaccess.h>
 #include <linux/io.h>
 #include <linux/reboot.h>
+#include <linux/slab.h>
 
 #include <asm/setup.h>
 #include <asm/page.h>
diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c
index e31bcd8f2eee..a0a0a4389bbd 100644
--- a/arch/x86/platform/mrst/mrst.c
+++ b/arch/x86/platform/mrst/mrst.c
@@ -356,8 +356,7 @@ static int __init sfi_parse_gpio(struct sfi_table_header *table)
         num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
         pentry = (struct sfi_gpio_table_entry *)sb->pentry;
 
-        gpio_table = (struct sfi_gpio_table_entry *)
-                                kmalloc(num * sizeof(*pentry), GFP_KERNEL);
+        gpio_table = kmalloc(num * sizeof(*pentry), GFP_KERNEL);
         if (!gpio_table)
                 return -1;
         memcpy(gpio_table, pentry, num * sizeof(*pentry));
diff --git a/arch/x86/platform/mrst/vrtc.c b/arch/x86/platform/mrst/vrtc.c
index 225bd0f0f675..d62b0a3b5c14 100644
--- a/arch/x86/platform/mrst/vrtc.c
+++ b/arch/x86/platform/mrst/vrtc.c
@@ -85,27 +85,35 @@ unsigned long vrtc_get_time(void)
         return mktime(year, mon, mday, hour, min, sec);
 }
 
-/* Only care about the minutes and seconds */
 int vrtc_set_mmss(unsigned long nowtime)
 {
-        int real_sec, real_min;
         unsigned long flags;
-        int vrtc_min;
-
-        spin_lock_irqsave(&rtc_lock, flags);
-        vrtc_min = vrtc_cmos_read(RTC_MINUTES);
-
-        real_sec = nowtime % 60;
-        real_min = nowtime / 60;
-        if (((abs(real_min - vrtc_min) + 15)/30) & 1)
-                real_min += 30;
-        real_min %= 60;
-
-        vrtc_cmos_write(real_sec, RTC_SECONDS);
-        vrtc_cmos_write(real_min, RTC_MINUTES);
-        spin_unlock_irqrestore(&rtc_lock, flags);
-
-        return 0;
+        struct rtc_time tm;
+        int year;
+        int retval = 0;
+
+        rtc_time_to_tm(nowtime, &tm);
+        if (!rtc_valid_tm(&tm) && tm.tm_year >= 72) {
+                /*
+                 * tm.year is the number of years since 1900, and the
+                 * vrtc need the years since 1972.
+                 */
+                year = tm.tm_year - 72;
+                spin_lock_irqsave(&rtc_lock, flags);
+                vrtc_cmos_write(year, RTC_YEAR);
+                vrtc_cmos_write(tm.tm_mon, RTC_MONTH);
+                vrtc_cmos_write(tm.tm_mday, RTC_DAY_OF_MONTH);
+                vrtc_cmos_write(tm.tm_hour, RTC_HOURS);
+                vrtc_cmos_write(tm.tm_min, RTC_MINUTES);
+                vrtc_cmos_write(tm.tm_sec, RTC_SECONDS);
+                spin_unlock_irqrestore(&rtc_lock, flags);
+        } else {
+                printk(KERN_ERR
+                       "%s: Invalid vRTC value: write of %lx to vRTC failed\n",
+                        __FUNCTION__, nowtime);
+                retval = -EINVAL;
+        }
+        return retval;
 }
 
 void __init mrst_rtc_init(void)
diff --git a/arch/x86/platform/olpc/olpc-xo1-sci.c b/arch/x86/platform/olpc/olpc-xo1-sci.c
index 74704be7b1fe..9a2e590dd202 100644
--- a/arch/x86/platform/olpc/olpc-xo1-sci.c
+++ b/arch/x86/platform/olpc/olpc-xo1-sci.c
@@ -460,7 +460,6 @@ static int setup_power_button(struct platform_device *pdev)
 static void free_power_button(void)
 {
         input_unregister_device(power_button_idev);
-        input_free_device(power_button_idev);
 }
 
 static int setup_ebook_switch(struct platform_device *pdev)
@@ -491,7 +490,6 @@ static int setup_ebook_switch(struct platform_device *pdev)
 static void free_ebook_switch(void)
 {
         input_unregister_device(ebook_switch_idev);
-        input_free_device(ebook_switch_idev);
 }
 
 static int setup_lid_switch(struct platform_device *pdev)
@@ -526,6 +524,7 @@ static int setup_lid_switch(struct platform_device *pdev)
 
 err_create_attr:
         input_unregister_device(lid_switch_idev);
+        lid_switch_idev = NULL;
 err_register:
         input_free_device(lid_switch_idev);
         return r;
@@ -535,7 +534,6 @@ static void free_lid_switch(void)
 {
         device_remove_file(&lid_switch_idev->dev, &dev_attr_lid_wake_mode);
         input_unregister_device(lid_switch_idev);
-        input_free_device(lid_switch_idev);
 }
 
 static int xo1_sci_probe(struct platform_device *pdev)
diff --git a/arch/x86/platform/uv/uv_time.c b/arch/x86/platform/uv/uv_time.c
index 98718f604eb6..5c86786bbfd2 100644
--- a/arch/x86/platform/uv/uv_time.c
+++ b/arch/x86/platform/uv/uv_time.c
@@ -159,10 +159,9 @@ static __init int uv_rtc_allocate_timers(void)
 {
         int cpu;
 
-        blade_info = kmalloc(uv_possible_blades * sizeof(void *), GFP_KERNEL);
+        blade_info = kzalloc(uv_possible_blades * sizeof(void *), GFP_KERNEL);
         if (!blade_info)
                 return -ENOMEM;
-        memset(blade_info, 0, uv_possible_blades * sizeof(void *));
 
         for_each_present_cpu(cpu) {
                 int nid = cpu_to_node(cpu);
diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c
index 3c68768d7a75..1cf5b300305e 100644
--- a/arch/x86/power/cpu.c
+++ b/arch/x86/power/cpu.c
@@ -25,16 +25,12 @@
 #include <asm/cpu.h>
 
 #ifdef CONFIG_X86_32
-static struct saved_context saved_context;
-
 unsigned long saved_context_ebx;
 unsigned long saved_context_esp, saved_context_ebp;
 unsigned long saved_context_esi, saved_context_edi;
 unsigned long saved_context_eflags;
-#else
-/* CONFIG_X86_64 */
-struct saved_context saved_context;
 #endif
+struct saved_context saved_context;
 
 /**
  *      __save_processor_state - save CPU registers before creating a
@@ -62,13 +58,20 @@ static void __save_processor_state(struct saved_context *ctxt)
          * descriptor tables
          */
 #ifdef CONFIG_X86_32
-        store_gdt(&ctxt->gdt);
         store_idt(&ctxt->idt);
 #else
 /* CONFIG_X86_64 */
-        store_gdt((struct desc_ptr *)&ctxt->gdt_limit);
         store_idt((struct desc_ptr *)&ctxt->idt_limit);
 #endif
+        /*
+         * We save it here, but restore it only in the hibernate case.
+         * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
+         * mode in "secondary_startup_64". In 32-bit mode it is done via
+         * 'pmode_gdt' in wakeup_start.
+         */
+        ctxt->gdt_desc.size = GDT_SIZE - 1;
+        ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_table(smp_processor_id());
+
         store_tr(ctxt->tr);
 
         /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
@@ -135,7 +138,10 @@ static void fix_processor_context(void)
 {
         int cpu = smp_processor_id();
         struct tss_struct *t = &per_cpu(init_tss, cpu);
-
+#ifdef CONFIG_X86_64
+        struct desc_struct *desc = get_cpu_gdt_table(cpu);
+        tss_desc tss;
+#endif
         set_tss_desc(cpu, t);   /*
                                  * This just modifies memory; should not be
                                  * necessary. But... This is necessary, because
@@ -144,7 +150,9 @@ static void fix_processor_context(void)
                                  */
 
 #ifdef CONFIG_X86_64
-        get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9;
+        memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
+        tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
+        write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
 
         syscall_init();                         /* This sets MSR_*STAR and related */
 #endif
@@ -183,11 +191,9 @@ static void __restore_processor_state(struct saved_context *ctxt)
          * ltr is done i fix_processor_context().
          */
 #ifdef CONFIG_X86_32
-        load_gdt(&ctxt->gdt);
         load_idt(&ctxt->idt);
 #else
 /* CONFIG_X86_64 */
-        load_gdt((const struct desc_ptr *)&ctxt->gdt_limit);
         load_idt((const struct desc_ptr *)&ctxt->idt_limit);
 #endif
 
diff --git a/arch/x86/power/hibernate_asm_32.S b/arch/x86/power/hibernate_asm_32.S
index ad47daeafa4e..1d0fa0e24070 100644
--- a/arch/x86/power/hibernate_asm_32.S
+++ b/arch/x86/power/hibernate_asm_32.S
@@ -75,6 +75,10 @@ done:
         pushl saved_context_eflags
         popfl
 
+        /* Saved in save_processor_state. */
+        movl $saved_context, %eax
+        lgdt saved_context_gdt_desc(%eax)
+
         xorl    %eax, %eax
 
         ret
diff --git a/arch/x86/power/hibernate_asm_64.S b/arch/x86/power/hibernate_asm_64.S
index 9356547d8c01..3c4469a7a929 100644
--- a/arch/x86/power/hibernate_asm_64.S
+++ b/arch/x86/power/hibernate_asm_64.S
@@ -139,6 +139,9 @@ ENTRY(restore_registers)
         pushq   pt_regs_flags(%rax)
         popfq
 
+        /* Saved in save_processor_state. */
+        lgdt    saved_context_gdt_desc(%rax)
+
         xorq    %rax, %rax
 
         /* tell the hibernation core that we've just restored the memory */
diff --git a/arch/x86/syscalls/syscall_32.tbl b/arch/x86/syscalls/syscall_32.tbl
index e6d55f0064df..d0d59bfbccce 100644
--- a/arch/x86/syscalls/syscall_32.tbl
+++ b/arch/x86/syscalls/syscall_32.tbl
@@ -43,7 +43,7 @@
 34      i386    nice                    sys_nice
 35      i386    ftime
 36      i386    sync                    sys_sync
-37      i386    kill                    sys_kill                        sys32_kill
+37      i386    kill                    sys_kill
 38      i386    rename                  sys_rename
 39      i386    mkdir                   sys_mkdir
 40      i386    rmdir                   sys_rmdir
@@ -123,7 +123,7 @@
 114     i386    wait4                   sys_wait4                       compat_sys_wait4
 115     i386    swapoff                 sys_swapoff
 116     i386    sysinfo                 sys_sysinfo                     compat_sys_sysinfo
-117     i386    ipc                     sys_ipc                         sys32_ipc
+117     i386    ipc                     sys_ipc                         compat_sys_ipc
 118     i386    fsync                   sys_fsync
 119     i386    sigreturn               sys_sigreturn                   stub32_sigreturn
 120     i386    clone                   sys_clone                       stub32_clone
@@ -131,7 +131,7 @@
 122     i386    uname                   sys_newuname
 123     i386    modify_ldt              sys_modify_ldt
 124     i386    adjtimex                sys_adjtimex                    compat_sys_adjtimex
-125     i386    mprotect                sys_mprotect                    sys32_mprotect
+125     i386    mprotect                sys_mprotect
 126     i386    sigprocmask             sys_sigprocmask                 compat_sys_sigprocmask
 127     i386    create_module
 128     i386    init_module             sys_init_module
@@ -193,7 +193,7 @@
 184     i386    capget                  sys_capget
 185     i386    capset                  sys_capset
 186     i386    sigaltstack             sys_sigaltstack                 compat_sys_sigaltstack
-187     i386    sendfile                sys_sendfile                    sys32_sendfile
+187     i386    sendfile                sys_sendfile                    compat_sys_sendfile
 188     i386    getpmsg
 189     i386    putpmsg
 190     i386    vfork                   sys_vfork                       stub32_vfork
@@ -259,7 +259,7 @@
 250     i386    fadvise64               sys_fadvise64                   sys32_fadvise64
 # 251 is available for reuse (was briefly sys_set_zone_reclaim)
 252     i386    exit_group              sys_exit_group
-253     i386    lookup_dcookie          sys_lookup_dcookie              sys32_lookup_dcookie
+253     i386    lookup_dcookie          sys_lookup_dcookie              compat_sys_lookup_dcookie
 254     i386    epoll_create            sys_epoll_create
 255     i386    epoll_ctl               sys_epoll_ctl
 256     i386    epoll_wait              sys_epoll_wait
diff --git a/arch/x86/tools/Makefile b/arch/x86/tools/Makefile
index bae601f900ef..e8120346903b 100644
--- a/arch/x86/tools/Makefile
+++ b/arch/x86/tools/Makefile
@@ -39,4 +39,5 @@ $(obj)/insn_sanity.o: $(srctree)/arch/x86/lib/insn.c $(srctree)/arch/x86/lib/ina
 
 HOST_EXTRACFLAGS += -I$(srctree)/tools/include
 hostprogs-y     += relocs
+relocs-objs     := relocs_32.o relocs_64.o relocs_common.o
 relocs: $(obj)/relocs
diff --git a/arch/x86/tools/relocs.c b/arch/x86/tools/relocs.c
index 79d67bd507fa..590be1090892 100644
--- a/arch/x86/tools/relocs.c
+++ b/arch/x86/tools/relocs.c
@@ -1,43 +1,36 @@
-#include <stdio.h>
-#include <stdarg.h>
-#include <stdlib.h>
-#include <stdint.h>
-#include <string.h>
-#include <errno.h>
-#include <unistd.h>
-#include <elf.h>
-#include <byteswap.h>
-#define USE_BSD
-#include <endian.h>
-#include <regex.h>
-#include <tools/le_byteshift.h>
-
-static void die(char *fmt, ...);
-
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-static Elf32_Ehdr ehdr;
-static unsigned long reloc_count, reloc_idx;
-static unsigned long *relocs;
-static unsigned long reloc16_count, reloc16_idx;
-static unsigned long *relocs16;
+/* This is included from relocs_32/64.c */
+
+#define ElfW(type)              _ElfW(ELF_BITS, type)
+#define _ElfW(bits, type)       __ElfW(bits, type)
+#define __ElfW(bits, type)      Elf##bits##_##type
+
+#define Elf_Addr                ElfW(Addr)
+#define Elf_Ehdr                ElfW(Ehdr)
+#define Elf_Phdr                ElfW(Phdr)
+#define Elf_Shdr                ElfW(Shdr)
+#define Elf_Sym                 ElfW(Sym)
+
+static Elf_Ehdr ehdr;
+
+struct relocs {
+        uint32_t        *offset;
+        unsigned long   count;
+        unsigned long   size;
+};
+
+static struct relocs relocs16;
+static struct relocs relocs32;
+static struct relocs relocs64;
 
 struct section {
-        Elf32_Shdr     shdr;
+        Elf_Shdr       shdr;
         struct section *link;
-        Elf32_Sym      *symtab;
-        Elf32_Rel      *reltab;
+        Elf_Sym        *symtab;
+        Elf_Rel        *reltab;
         char           *strtab;
 };
 static struct section *secs;
 
-enum symtype {
-        S_ABS,
-        S_REL,
-        S_SEG,
-        S_LIN,
-        S_NSYMTYPES
-};
-
 static const char * const sym_regex_kernel[S_NSYMTYPES] = {
 /*
  * Following symbols have been audited. There values are constant and do
@@ -49,6 +42,9 @@ static const char * const sym_regex_kernel[S_NSYMTYPES] = {
         "^(xen_irq_disable_direct_reloc$|"
         "xen_save_fl_direct_reloc$|"
         "VDSO|"
+#if ELF_BITS == 64
+        "__vvar_page|"
+#endif
         "__crc_)",
 
 /*
@@ -72,6 +68,11 @@ static const char * const sym_regex_kernel[S_NSYMTYPES] = {
         "__end_rodata|"
         "__initramfs_start|"
         "(jiffies|jiffies_64)|"
+#if ELF_BITS == 64
+        "__per_cpu_load|"
+        "init_per_cpu__.*|"
+        "__end_rodata_hpage_align|"
+#endif
         "_end)$"
 };
 
@@ -132,15 +133,6 @@ static void regex_init(int use_real_mode)
         }
 }
 
-static void die(char *fmt, ...)
-{
-        va_list ap;
-        va_start(ap, fmt);
-        vfprintf(stderr, fmt, ap);
-        va_end(ap);
-        exit(1);
-}
-
 static const char *sym_type(unsigned type)
 {
         static const char *type_name[] = {
@@ -198,6 +190,24 @@ static const char *rel_type(unsigned type)
 {
         static const char *type_name[] = {
 #define REL_TYPE(X) [X] = #X
+#if ELF_BITS == 64
+                REL_TYPE(R_X86_64_NONE),
+                REL_TYPE(R_X86_64_64),
+                REL_TYPE(R_X86_64_PC32),
+                REL_TYPE(R_X86_64_GOT32),
+                REL_TYPE(R_X86_64_PLT32),
+                REL_TYPE(R_X86_64_COPY),
+                REL_TYPE(R_X86_64_GLOB_DAT),
+                REL_TYPE(R_X86_64_JUMP_SLOT),
+                REL_TYPE(R_X86_64_RELATIVE),
+                REL_TYPE(R_X86_64_GOTPCREL),
+                REL_TYPE(R_X86_64_32),
+                REL_TYPE(R_X86_64_32S),
+                REL_TYPE(R_X86_64_16),
+                REL_TYPE(R_X86_64_PC16),
+                REL_TYPE(R_X86_64_8),
+                REL_TYPE(R_X86_64_PC8),
+#else
                 REL_TYPE(R_386_NONE),
                 REL_TYPE(R_386_32),
                 REL_TYPE(R_386_PC32),
@@ -213,6 +223,7 @@ static const char *rel_type(unsigned type)
                 REL_TYPE(R_386_PC8),
                 REL_TYPE(R_386_16),
                 REL_TYPE(R_386_PC16),
+#endif
 #undef REL_TYPE
         };
         const char *name = "unknown type rel type name";
@@ -240,7 +251,7 @@ static const char *sec_name(unsigned shndx)
         return name;
 }
 
-static const char *sym_name(const char *sym_strtab, Elf32_Sym *sym)
+static const char *sym_name(const char *sym_strtab, Elf_Sym *sym)
 {
         const char *name;
         name = "<noname>";
@@ -253,15 +264,42 @@ static const char *sym_name(const char *sym_strtab, Elf32_Sym *sym)
         return name;
 }
 
+static Elf_Sym *sym_lookup(const char *symname)
+{
+        int i;
+        for (i = 0; i < ehdr.e_shnum; i++) {
+                struct section *sec = &secs[i];
+                long nsyms;
+                char *strtab;
+                Elf_Sym *symtab;
+                Elf_Sym *sym;
+
+                if (sec->shdr.sh_type != SHT_SYMTAB)
+                        continue;
 
+                nsyms = sec->shdr.sh_size/sizeof(Elf_Sym);
+                symtab = sec->symtab;
+                strtab = sec->link->strtab;
+
+                for (sym = symtab; --nsyms >= 0; sym++) {
+                        if (!sym->st_name)
+                                continue;
+                        if (strcmp(symname, strtab + sym->st_name) == 0)
+                                return sym;
+                }
+        }
+        return 0;
+}
 
 #if BYTE_ORDER == LITTLE_ENDIAN
 #define le16_to_cpu(val) (val)
 #define le32_to_cpu(val) (val)
+#define le64_to_cpu(val) (val)
 #endif
 #if BYTE_ORDER == BIG_ENDIAN
 #define le16_to_cpu(val) bswap_16(val)
 #define le32_to_cpu(val) bswap_32(val)
+#define le64_to_cpu(val) bswap_64(val)
 #endif
 
 static uint16_t elf16_to_cpu(uint16_t val)
@@ -274,6 +312,23 @@ static uint32_t elf32_to_cpu(uint32_t val)
         return le32_to_cpu(val);
 }
 
+#define elf_half_to_cpu(x)      elf16_to_cpu(x)
+#define elf_word_to_cpu(x)      elf32_to_cpu(x)
+
+#if ELF_BITS == 64
+static uint64_t elf64_to_cpu(uint64_t val)
+{
+        return le64_to_cpu(val);
+}
+#define elf_addr_to_cpu(x)      elf64_to_cpu(x)
+#define elf_off_to_cpu(x)       elf64_to_cpu(x)
+#define elf_xword_to_cpu(x)     elf64_to_cpu(x)
+#else
+#define elf_addr_to_cpu(x)      elf32_to_cpu(x)
+#define elf_off_to_cpu(x)       elf32_to_cpu(x)
+#define elf_xword_to_cpu(x)     elf32_to_cpu(x)
+#endif
+
 static void read_ehdr(FILE *fp)
 {
         if (fread(&ehdr, sizeof(ehdr), 1, fp) != 1) {
@@ -283,8 +338,8 @@ static void read_ehdr(FILE *fp)
         if (memcmp(ehdr.e_ident, ELFMAG, SELFMAG) != 0) {
                 die("No ELF magic\n");
         }
-        if (ehdr.e_ident[EI_CLASS] != ELFCLASS32) {
-                die("Not a 32 bit executable\n");
+        if (ehdr.e_ident[EI_CLASS] != ELF_CLASS) {
+                die("Not a %d bit executable\n", ELF_BITS);
         }
         if (ehdr.e_ident[EI_DATA] != ELFDATA2LSB) {
                 die("Not a LSB ELF executable\n");
@@ -293,36 +348,36 @@ static void read_ehdr(FILE *fp)
                 die("Unknown ELF version\n");
         }
         /* Convert the fields to native endian */
-        ehdr.e_type      = elf16_to_cpu(ehdr.e_type);
-        ehdr.e_machine   = elf16_to_cpu(ehdr.e_machine);
-        ehdr.e_version   = elf32_to_cpu(ehdr.e_version);
-        ehdr.e_entry     = elf32_to_cpu(ehdr.e_entry);
-        ehdr.e_phoff     = elf32_to_cpu(ehdr.e_phoff);
-        ehdr.e_shoff     = elf32_to_cpu(ehdr.e_shoff);
-        ehdr.e_flags     = elf32_to_cpu(ehdr.e_flags);
-        ehdr.e_ehsize    = elf16_to_cpu(ehdr.e_ehsize);
-        ehdr.e_phentsize = elf16_to_cpu(ehdr.e_phentsize);
-        ehdr.e_phnum     = elf16_to_cpu(ehdr.e_phnum);
-        ehdr.e_shentsize = elf16_to_cpu(ehdr.e_shentsize);
-        ehdr.e_shnum     = elf16_to_cpu(ehdr.e_shnum);
-        ehdr.e_shstrndx  = elf16_to_cpu(ehdr.e_shstrndx);
+        ehdr.e_type      = elf_half_to_cpu(ehdr.e_type);
+        ehdr.e_machine   = elf_half_to_cpu(ehdr.e_machine);
+        ehdr.e_version   = elf_word_to_cpu(ehdr.e_version);
+        ehdr.e_entry     = elf_addr_to_cpu(ehdr.e_entry);
+        ehdr.e_phoff     = elf_off_to_cpu(ehdr.e_phoff);
+        ehdr.e_shoff     = elf_off_to_cpu(ehdr.e_shoff);
+        ehdr.e_flags     = elf_word_to_cpu(ehdr.e_flags);
+        ehdr.e_ehsize    = elf_half_to_cpu(ehdr.e_ehsize);
+        ehdr.e_phentsize = elf_half_to_cpu(ehdr.e_phentsize);
+        ehdr.e_phnum     = elf_half_to_cpu(ehdr.e_phnum);
+        ehdr.e_shentsize = elf_half_to_cpu(ehdr.e_shentsize);
+        ehdr.e_shnum     = elf_half_to_cpu(ehdr.e_shnum);
+        ehdr.e_shstrndx  = elf_half_to_cpu(ehdr.e_shstrndx);
 
         if ((ehdr.e_type != ET_EXEC) && (ehdr.e_type != ET_DYN)) {
                 die("Unsupported ELF header type\n");
         }
-        if (ehdr.e_machine != EM_386) {
-                die("Not for x86\n");
+        if (ehdr.e_machine != ELF_MACHINE) {
+                die("Not for %s\n", ELF_MACHINE_NAME);
         }
         if (ehdr.e_version != EV_CURRENT) {
                 die("Unknown ELF version\n");
         }
-        if (ehdr.e_ehsize != sizeof(Elf32_Ehdr)) {
+        if (ehdr.e_ehsize != sizeof(Elf_Ehdr)) {
                 die("Bad Elf header size\n");
         }
-        if (ehdr.e_phentsize != sizeof(Elf32_Phdr)) {
+        if (ehdr.e_phentsize != sizeof(Elf_Phdr)) {
                 die("Bad program header entry\n");
         }
-        if (ehdr.e_shentsize != sizeof(Elf32_Shdr)) {
+        if (ehdr.e_shentsize != sizeof(Elf_Shdr)) {
                 die("Bad section header entry\n");
         }
         if (ehdr.e_shstrndx >= ehdr.e_shnum) {
@@ -333,7 +388,7 @@ static void read_ehdr(FILE *fp)
 static void read_shdrs(FILE *fp)
 {
         int i;
-        Elf32_Shdr shdr;
+        Elf_Shdr shdr;
 
         secs = calloc(ehdr.e_shnum, sizeof(struct section));
         if (!secs) {
@@ -349,16 +404,16 @@ static void read_shdrs(FILE *fp)
                 if (fread(&shdr, sizeof shdr, 1, fp) != 1)
                         die("Cannot read ELF section headers %d/%d: %s\n",
                             i, ehdr.e_shnum, strerror(errno));
-                sec->shdr.sh_name      = elf32_to_cpu(shdr.sh_name);
-                sec->shdr.sh_type      = elf32_to_cpu(shdr.sh_type);
-                sec->shdr.sh_flags     = elf32_to_cpu(shdr.sh_flags);
-                sec->shdr.sh_addr      = elf32_to_cpu(shdr.sh_addr);
-                sec->shdr.sh_offset    = elf32_to_cpu(shdr.sh_offset);
-                sec->shdr.sh_size      = elf32_to_cpu(shdr.sh_size);
-                sec->shdr.sh_link      = elf32_to_cpu(shdr.sh_link);
-                sec->shdr.sh_info      = elf32_to_cpu(shdr.sh_info);
-                sec->shdr.sh_addralign = elf32_to_cpu(shdr.sh_addralign);
-                sec->shdr.sh_entsize   = elf32_to_cpu(shdr.sh_entsize);
+                sec->shdr.sh_name      = elf_word_to_cpu(shdr.sh_name);
+                sec->shdr.sh_type      = elf_word_to_cpu(shdr.sh_type);
+                sec->shdr.sh_flags     = elf_xword_to_cpu(shdr.sh_flags);
+                sec->shdr.sh_addr      = elf_addr_to_cpu(shdr.sh_addr);
+                sec->shdr.sh_offset    = elf_off_to_cpu(shdr.sh_offset);
+                sec->shdr.sh_size      = elf_xword_to_cpu(shdr.sh_size);
+                sec->shdr.sh_link      = elf_word_to_cpu(shdr.sh_link);
+                sec->shdr.sh_info      = elf_word_to_cpu(shdr.sh_info);
+                sec->shdr.sh_addralign = elf_xword_to_cpu(shdr.sh_addralign);
+                sec->shdr.sh_entsize   = elf_xword_to_cpu(shdr.sh_entsize);
                 if (sec->shdr.sh_link < ehdr.e_shnum)
                         sec->link = &secs[sec->shdr.sh_link];
         }
@@ -412,12 +467,12 @@ static void read_symtabs(FILE *fp)
                         die("Cannot read symbol table: %s\n",
                                 strerror(errno));
                 }
-                for (j = 0; j < sec->shdr.sh_size/sizeof(Elf32_Sym); j++) {
-                        Elf32_Sym *sym = &sec->symtab[j];
-                        sym->st_name  = elf32_to_cpu(sym->st_name);
-                        sym->st_value = elf32_to_cpu(sym->st_value);
-                        sym->st_size  = elf32_to_cpu(sym->st_size);
-                        sym->st_shndx = elf16_to_cpu(sym->st_shndx);
+                for (j = 0; j < sec->shdr.sh_size/sizeof(Elf_Sym); j++) {
+                        Elf_Sym *sym = &sec->symtab[j];
+                        sym->st_name  = elf_word_to_cpu(sym->st_name);
+                        sym->st_value = elf_addr_to_cpu(sym->st_value);
+                        sym->st_size  = elf_xword_to_cpu(sym->st_size);
+                        sym->st_shndx = elf_half_to_cpu(sym->st_shndx);
                 }
         }
 }
@@ -428,7 +483,7 @@ static void read_relocs(FILE *fp)
         int i,j;
         for (i = 0; i < ehdr.e_shnum; i++) {
                 struct section *sec = &secs[i];
-                if (sec->shdr.sh_type != SHT_REL) {
+                if (sec->shdr.sh_type != SHT_REL_TYPE) {
                         continue;
                 }
                 sec->reltab = malloc(sec->shdr.sh_size);
@@ -445,10 +500,13 @@ static void read_relocs(FILE *fp)
                         die("Cannot read symbol table: %s\n",
                                 strerror(errno));
                 }
-                for (j = 0; j < sec->shdr.sh_size/sizeof(Elf32_Rel); j++) {
-                        Elf32_Rel *rel = &sec->reltab[j];
-                        rel->r_offset = elf32_to_cpu(rel->r_offset);
-                        rel->r_info   = elf32_to_cpu(rel->r_info);
+                for (j = 0; j < sec->shdr.sh_size/sizeof(Elf_Rel); j++) {
+                        Elf_Rel *rel = &sec->reltab[j];
+                        rel->r_offset = elf_addr_to_cpu(rel->r_offset);
+                        rel->r_info   = elf_xword_to_cpu(rel->r_info);
+#if (SHT_REL_TYPE == SHT_RELA)
+                        rel->r_addend = elf_xword_to_cpu(rel->r_addend);
+#endif
                 }
         }
 }
@@ -457,6 +515,13 @@ static void read_relocs(FILE *fp)
 static void print_absolute_symbols(void)
 {
         int i;
+        const char *format;
+
+        if (ELF_BITS == 64)
+                format = "%5d %016"PRIx64" %5"PRId64" %10s %10s %12s %s\n";
+        else
+                format = "%5d %08"PRIx32"  %5"PRId32" %10s %10s %12s %s\n";
+
         printf("Absolute symbols\n");
         printf(" Num:    Value Size  Type       Bind        Visibility  Name\n");
         for (i = 0; i < ehdr.e_shnum; i++) {
@@ -468,19 +533,19 @@ static void print_absolute_symbols(void)
                         continue;
                 }
                 sym_strtab = sec->link->strtab;
-                for (j = 0; j < sec->shdr.sh_size/sizeof(Elf32_Sym); j++) {
-                        Elf32_Sym *sym;
+                for (j = 0; j < sec->shdr.sh_size/sizeof(Elf_Sym); j++) {
+                        Elf_Sym *sym;
                         const char *name;
                         sym = &sec->symtab[j];
                         name = sym_name(sym_strtab, sym);
                         if (sym->st_shndx != SHN_ABS) {
                                 continue;
                         }
-                        printf("%5d %08x %5d %10s %10s %12s %s\n",
+                        printf(format,
                                 j, sym->st_value, sym->st_size,
-                                sym_type(ELF32_ST_TYPE(sym->st_info)),
-                                sym_bind(ELF32_ST_BIND(sym->st_info)),
-                                sym_visibility(ELF32_ST_VISIBILITY(sym->st_other)),
+                                sym_type(ELF_ST_TYPE(sym->st_info)),
+                                sym_bind(ELF_ST_BIND(sym->st_info)),
+                                sym_visibility(ELF_ST_VISIBILITY(sym->st_other)),
                                 name);
                 }
         }
@@ -490,14 +555,20 @@ static void print_absolute_symbols(void)
 static void print_absolute_relocs(void)
 {
         int i, printed = 0;
+        const char *format;
+
+        if (ELF_BITS == 64)
+                format = "%016"PRIx64" %016"PRIx64" %10s %016"PRIx64"  %s\n";
+        else
+                format = "%08"PRIx32" %08"PRIx32" %10s %08"PRIx32"  %s\n";
 
         for (i = 0; i < ehdr.e_shnum; i++) {
                 struct section *sec = &secs[i];
                 struct section *sec_applies, *sec_symtab;
                 char *sym_strtab;
-                Elf32_Sym *sh_symtab;
+                Elf_Sym *sh_symtab;
                 int j;
-                if (sec->shdr.sh_type != SHT_REL) {
+                if (sec->shdr.sh_type != SHT_REL_TYPE) {
                         continue;
                 }
                 sec_symtab  = sec->link;
@@ -507,12 +578,12 @@ static void print_absolute_relocs(void)
                 }
                 sh_symtab  = sec_symtab->symtab;
                 sym_strtab = sec_symtab->link->strtab;
-                for (j = 0; j < sec->shdr.sh_size/sizeof(Elf32_Rel); j++) {
-                        Elf32_Rel *rel;
-                        Elf32_Sym *sym;
+                for (j = 0; j < sec->shdr.sh_size/sizeof(Elf_Rel); j++) {
+                        Elf_Rel *rel;
+                        Elf_Sym *sym;
                         const char *name;
                         rel = &sec->reltab[j];
-                        sym = &sh_symtab[ELF32_R_SYM(rel->r_info)];
+                        sym = &sh_symtab[ELF_R_SYM(rel->r_info)];
                         name = sym_name(sym_strtab, sym);
                         if (sym->st_shndx != SHN_ABS) {
                                 continue;
@@ -542,10 +613,10 @@ static void print_absolute_relocs(void)
                                 printed = 1;
                         }
 
-                        printf("%08x %08x %10s %08x  %s\n",
+                        printf(format,
                                 rel->r_offset,
                                 rel->r_info,
-                                rel_type(ELF32_R_TYPE(rel->r_info)),
+                                rel_type(ELF_R_TYPE(rel->r_info)),
                                 sym->st_value,
                                 name);
                 }
@@ -555,19 +626,34 @@ static void print_absolute_relocs(void)
                 printf("\n");
 }
 
-static void walk_relocs(void (*visit)(Elf32_Rel *rel, Elf32_Sym *sym),
-                        int use_real_mode)
+static void add_reloc(struct relocs *r, uint32_t offset)
+{
+        if (r->count == r->size) {
+                unsigned long newsize = r->size + 50000;
+                void *mem = realloc(r->offset, newsize * sizeof(r->offset[0]));
+
+                if (!mem)
+                        die("realloc of %ld entries for relocs failed\n",
+                                newsize);
+                r->offset = mem;
+                r->size = newsize;
+        }
+        r->offset[r->count++] = offset;
+}
+
+static void walk_relocs(int (*process)(struct section *sec, Elf_Rel *rel,
+                        Elf_Sym *sym, const char *symname))
 {
         int i;
         /* Walk through the relocations */
         for (i = 0; i < ehdr.e_shnum; i++) {
                 char *sym_strtab;
-                Elf32_Sym *sh_symtab;
+                Elf_Sym *sh_symtab;
                 struct section *sec_applies, *sec_symtab;
                 int j;
                 struct section *sec = &secs[i];
 
-                if (sec->shdr.sh_type != SHT_REL) {
+                if (sec->shdr.sh_type != SHT_REL_TYPE) {
                         continue;
                 }
                 sec_symtab  = sec->link;
@@ -577,101 +663,281 @@ static void walk_relocs(void (*visit)(Elf32_Rel *rel, Elf32_Sym *sym),
                 }
                 sh_symtab = sec_symtab->symtab;
                 sym_strtab = sec_symtab->link->strtab;
-                for (j = 0; j < sec->shdr.sh_size/sizeof(Elf32_Rel); j++) {
-                        Elf32_Rel *rel;
-                        Elf32_Sym *sym;
-                        unsigned r_type;
-                        const char *symname;
-                        int shn_abs;
+                for (j = 0; j < sec->shdr.sh_size/sizeof(Elf_Rel); j++) {
+                        Elf_Rel *rel = &sec->reltab[j];
+                        Elf_Sym *sym = &sh_symtab[ELF_R_SYM(rel->r_info)];
+                        const char *symname = sym_name(sym_strtab, sym);
 
-                        rel = &sec->reltab[j];
-                        sym = &sh_symtab[ELF32_R_SYM(rel->r_info)];
-                        r_type = ELF32_R_TYPE(rel->r_info);
-
-                        shn_abs = sym->st_shndx == SHN_ABS;
-
-                        switch (r_type) {
-                        case R_386_NONE:
-                        case R_386_PC32:
-                        case R_386_PC16:
-                        case R_386_PC8:
-                                /*
-                                 * NONE can be ignored and and PC relative
-                                 * relocations don't need to be adjusted.
-                                 */
-                                break;
+                        process(sec, rel, sym, symname);
+                }
+        }
+}
 
-                        case R_386_16:
-                                symname = sym_name(sym_strtab, sym);
-                                if (!use_real_mode)
-                                        goto bad;
-                                if (shn_abs) {
-                                        if (is_reloc(S_ABS, symname))
-                                                break;
-                                        else if (!is_reloc(S_SEG, symname))
-                                                goto bad;
-                                } else {
-                                        if (is_reloc(S_LIN, symname))
-                                                goto bad;
-                                        else
-                                                break;
-                                }
-                                visit(rel, sym);
-                                break;
+/*
+ * The .data..percpu section is a special case for x86_64 SMP kernels.
+ * It is used to initialize the actual per_cpu areas and to provide
+ * definitions for the per_cpu variables that correspond to their offsets
+ * within the percpu area. Since the values of all of the symbols need
+ * to be offsets from the start of the per_cpu area the virtual address
+ * (sh_addr) of .data..percpu is 0 in SMP kernels.
+ *
+ * This means that:
+ *
+ *      Relocations that reference symbols in the per_cpu area do not
+ *      need further relocation (since the value is an offset relative
+ *      to the start of the per_cpu area that does not change).
+ *
+ *      Relocations that apply to the per_cpu area need to have their
+ *      offset adjusted by by the value of __per_cpu_load to make them
+ *      point to the correct place in the loaded image (because the
+ *      virtual address of .data..percpu is 0).
+ *
+ * For non SMP kernels .data..percpu is linked as part of the normal
+ * kernel data and does not require special treatment.
+ *
+ */
+static int per_cpu_shndx        = -1;
+Elf_Addr per_cpu_load_addr;
 
-                        case R_386_32:
-                                symname = sym_name(sym_strtab, sym);
-                                if (shn_abs) {
-                                        if (is_reloc(S_ABS, symname))
-                                                break;
-                                        else if (!is_reloc(S_REL, symname))
-                                                goto bad;
-                                } else {
-                                        if (use_real_mode &&
-                                            !is_reloc(S_LIN, symname))
-                                                break;
-                                }
-                                visit(rel, sym);
-                                break;
-                        default:
-                                die("Unsupported relocation type: %s (%d)\n",
-                                    rel_type(r_type), r_type);
+static void percpu_init(void)
+{
+        int i;
+        for (i = 0; i < ehdr.e_shnum; i++) {
+                ElfW(Sym) *sym;
+                if (strcmp(sec_name(i), ".data..percpu"))
+                        continue;
+
+                if (secs[i].shdr.sh_addr != 0)  /* non SMP kernel */
+                        return;
+
+                sym = sym_lookup("__per_cpu_load");
+                if (!sym)
+                        die("can't find __per_cpu_load\n");
+
+                per_cpu_shndx = i;
+                per_cpu_load_addr = sym->st_value;
+                return;
+        }
+}
+
+#if ELF_BITS == 64
+
+/*
+ * Check to see if a symbol lies in the .data..percpu section.
+ * For some as yet not understood reason the "__init_begin"
+ * symbol which immediately preceeds the .data..percpu section
+ * also shows up as it it were part of it so we do an explict
+ * check for that symbol name and ignore it.
+ */
+static int is_percpu_sym(ElfW(Sym) *sym, const char *symname)
+{
+        return (sym->st_shndx == per_cpu_shndx) &&
+                strcmp(symname, "__init_begin");
+}
+
+
+static int do_reloc64(struct section *sec, Elf_Rel *rel, ElfW(Sym) *sym,
+                      const char *symname)
+{
+        unsigned r_type = ELF64_R_TYPE(rel->r_info);
+        ElfW(Addr) offset = rel->r_offset;
+        int shn_abs = (sym->st_shndx == SHN_ABS) && !is_reloc(S_REL, symname);
+
+        if (sym->st_shndx == SHN_UNDEF)
+                return 0;
+
+        /*
+         * Adjust the offset if this reloc applies to the percpu section.
+         */
+        if (sec->shdr.sh_info == per_cpu_shndx)
+                offset += per_cpu_load_addr;
+
+        switch (r_type) {
+        case R_X86_64_NONE:
+        case R_X86_64_PC32:
+                /*
+                 * NONE can be ignored and PC relative relocations don't
+                 * need to be adjusted.
+                 */
+                break;
+
+        case R_X86_64_32:
+        case R_X86_64_32S:
+        case R_X86_64_64:
+                /*
+                 * References to the percpu area don't need to be adjusted.
+                 */
+                if (is_percpu_sym(sym, symname))
+                        break;
+
+                if (shn_abs) {
+                        /*
+                         * Whitelisted absolute symbols do not require
+                         * relocation.
+                         */
+                        if (is_reloc(S_ABS, symname))
                                 break;
-                        bad:
-                                symname = sym_name(sym_strtab, sym);
-                                die("Invalid %s %s relocation: %s\n",
-                                    shn_abs ? "absolute" : "relative",
-                                    rel_type(r_type), symname);
-                        }
+
+                        die("Invalid absolute %s relocation: %s\n",
+                            rel_type(r_type), symname);
+                        break;
                 }
+
+                /*
+                 * Relocation offsets for 64 bit kernels are output
+                 * as 32 bits and sign extended back to 64 bits when
+                 * the relocations are processed.
+                 * Make sure that the offset will fit.
+                 */
+                if ((int32_t)offset != (int64_t)offset)
+                        die("Relocation offset doesn't fit in 32 bits\n");
+
+                if (r_type == R_X86_64_64)
+                        add_reloc(&relocs64, offset);
+                else
+                        add_reloc(&relocs32, offset);
+                break;
+
+        default:
+                die("Unsupported relocation type: %s (%d)\n",
+                    rel_type(r_type), r_type);
+                break;
         }
+
+        return 0;
 }
 
-static void count_reloc(Elf32_Rel *rel, Elf32_Sym *sym)
+#else
+
+static int do_reloc32(struct section *sec, Elf_Rel *rel, Elf_Sym *sym,
+                      const char *symname)
 {
-        if (ELF32_R_TYPE(rel->r_info) == R_386_16)
-                reloc16_count++;
-        else
-                reloc_count++;
+        unsigned r_type = ELF32_R_TYPE(rel->r_info);
+        int shn_abs = (sym->st_shndx == SHN_ABS) && !is_reloc(S_REL, symname);
+
+        switch (r_type) {
+        case R_386_NONE:
+        case R_386_PC32:
+        case R_386_PC16:
+        case R_386_PC8:
+                /*
+                 * NONE can be ignored and PC relative relocations don't
+                 * need to be adjusted.
+                 */
+                break;
+
+        case R_386_32:
+                if (shn_abs) {
+                        /*
+                         * Whitelisted absolute symbols do not require
+                         * relocation.
+                         */
+                        if (is_reloc(S_ABS, symname))
+                                break;
+
+                        die("Invalid absolute %s relocation: %s\n",
+                            rel_type(r_type), symname);
+                        break;
+                }
+
+                add_reloc(&relocs32, rel->r_offset);
+                break;
+
+        default:
+                die("Unsupported relocation type: %s (%d)\n",
+                    rel_type(r_type), r_type);
+                break;
+        }
+
+        return 0;
 }
 
-static void collect_reloc(Elf32_Rel *rel, Elf32_Sym *sym)
+static int do_reloc_real(struct section *sec, Elf_Rel *rel, Elf_Sym *sym,
+                         const char *symname)
 {
-        /* Remember the address that needs to be adjusted. */
-        if (ELF32_R_TYPE(rel->r_info) == R_386_16)
-                relocs16[reloc16_idx++] = rel->r_offset;
-        else
-                relocs[reloc_idx++] = rel->r_offset;
+        unsigned r_type = ELF32_R_TYPE(rel->r_info);
+        int shn_abs = (sym->st_shndx == SHN_ABS) && !is_reloc(S_REL, symname);
+
+        switch (r_type) {
+        case R_386_NONE:
+        case R_386_PC32:
+        case R_386_PC16:
+        case R_386_PC8:
+                /*
+                 * NONE can be ignored and PC relative relocations don't
+                 * need to be adjusted.
+                 */
+                break;
+
+        case R_386_16:
+                if (shn_abs) {
+                        /*
+                         * Whitelisted absolute symbols do not require
+                         * relocation.
+                         */
+                        if (is_reloc(S_ABS, symname))
+                                break;
+
+                        if (is_reloc(S_SEG, symname)) {
+                                add_reloc(&relocs16, rel->r_offset);
+                                break;
+                        }
+                } else {
+                        if (!is_reloc(S_LIN, symname))
+                                break;
+                }
+                die("Invalid %s %s relocation: %s\n",
+                    shn_abs ? "absolute" : "relative",
+                    rel_type(r_type), symname);
+                break;
+
+        case R_386_32:
+                if (shn_abs) {
+                        /*
+                         * Whitelisted absolute symbols do not require
+                         * relocation.
+                         */
+                        if (is_reloc(S_ABS, symname))
+                                break;
+
+                        if (is_reloc(S_REL, symname)) {
+                                add_reloc(&relocs32, rel->r_offset);
+                                break;
+                        }
+                } else {
+                        if (is_reloc(S_LIN, symname))
+                                add_reloc(&relocs32, rel->r_offset);
+                        break;
+                }
+                die("Invalid %s %s relocation: %s\n",
+                    shn_abs ? "absolute" : "relative",
+                    rel_type(r_type), symname);
+                break;
+
+        default:
+                die("Unsupported relocation type: %s (%d)\n",
+                    rel_type(r_type), r_type);
+                break;
+        }
+
+        return 0;
 }
 
+#endif
+
 static int cmp_relocs(const void *va, const void *vb)
 {
-        const unsigned long *a, *b;
+        const uint32_t *a, *b;
         a = va; b = vb;
         return (*a == *b)? 0 : (*a > *b)? 1 : -1;
 }
 
-static int write32(unsigned int v, FILE *f)
+static void sort_relocs(struct relocs *r)
+{
+        qsort(r->offset, r->count, sizeof(r->offset[0]), cmp_relocs);
+}
+
+static int write32(uint32_t v, FILE *f)
 {
         unsigned char buf[4];
 
@@ -679,33 +945,40 @@ static int write32(unsigned int v, FILE *f)
         return fwrite(buf, 1, 4, f) == 4 ? 0 : -1;
 }
 
+static int write32_as_text(uint32_t v, FILE *f)
+{
+        return fprintf(f, "\t.long 0x%08"PRIx32"\n", v) > 0 ? 0 : -1;
+}
+
 static void emit_relocs(int as_text, int use_real_mode)
 {
         int i;
-        /* Count how many relocations I have and allocate space for them. */
-        reloc_count = 0;
-        walk_relocs(count_reloc, use_real_mode);
-        relocs = malloc(reloc_count * sizeof(relocs[0]));
-        if (!relocs) {
-                die("malloc of %d entries for relocs failed\n",
-                        reloc_count);
-        }
+        int (*write_reloc)(uint32_t, FILE *) = write32;
+        int (*do_reloc)(struct section *sec, Elf_Rel *rel, Elf_Sym *sym,
+                        const char *symname);
+
+#if ELF_BITS == 64
+        if (!use_real_mode)
+                do_reloc = do_reloc64;
+        else
+                die("--realmode not valid for a 64-bit ELF file");
+#else
+        if (!use_real_mode)
+                do_reloc = do_reloc32;
+        else
+                do_reloc = do_reloc_real;
+#endif
 
-        relocs16 = malloc(reloc16_count * sizeof(relocs[0]));
-        if (!relocs16) {
-                die("malloc of %d entries for relocs16 failed\n",
-                        reloc16_count);
-        }
         /* Collect up the relocations */
-        reloc_idx = 0;
-        walk_relocs(collect_reloc, use_real_mode);
+        walk_relocs(do_reloc);
 
-        if (reloc16_count && !use_real_mode)
+        if (relocs16.count && !use_real_mode)
                 die("Segment relocations found but --realmode not specified\n");
 
         /* Order the relocations for more efficient processing */
-        qsort(relocs, reloc_count, sizeof(relocs[0]), cmp_relocs);
-        qsort(relocs16, reloc16_count, sizeof(relocs16[0]), cmp_relocs);
+        sort_relocs(&relocs16);
+        sort_relocs(&relocs32);
+        sort_relocs(&relocs64);
 
         /* Print the relocations */
         if (as_text) {
@@ -714,114 +987,60 @@ static void emit_relocs(int as_text, int use_real_mode)
                  */
                 printf(".section \".data.reloc\",\"a\"\n");
                 printf(".balign 4\n");
-                if (use_real_mode) {
-                        printf("\t.long %lu\n", reloc16_count);
-                        for (i = 0; i < reloc16_count; i++)
-                                printf("\t.long 0x%08lx\n", relocs16[i]);
-                        printf("\t.long %lu\n", reloc_count);
-                        for (i = 0; i < reloc_count; i++) {
-                                printf("\t.long 0x%08lx\n", relocs[i]);
-                        }
-                } else {
-                        /* Print a stop */
-                        printf("\t.long 0x%08lx\n", (unsigned long)0);
-                        for (i = 0; i < reloc_count; i++) {
-                                printf("\t.long 0x%08lx\n", relocs[i]);
-                        }
-                }
-
-                printf("\n");
+                write_reloc = write32_as_text;
         }
-        else {
-                if (use_real_mode) {
-                        write32(reloc16_count, stdout);
-                        for (i = 0; i < reloc16_count; i++)
-                                write32(relocs16[i], stdout);
-                        write32(reloc_count, stdout);
 
-                        /* Now print each relocation */
-                        for (i = 0; i < reloc_count; i++)
-                                write32(relocs[i], stdout);
-                } else {
+        if (use_real_mode) {
+                write_reloc(relocs16.count, stdout);
+                for (i = 0; i < relocs16.count; i++)
+                        write_reloc(relocs16.offset[i], stdout);
+
+                write_reloc(relocs32.count, stdout);
+                for (i = 0; i < relocs32.count; i++)
+                        write_reloc(relocs32.offset[i], stdout);
+        } else {
+                if (ELF_BITS == 64) {
                         /* Print a stop */
-                        write32(0, stdout);
+                        write_reloc(0, stdout);
 
                         /* Now print each relocation */
-                        for (i = 0; i < reloc_count; i++) {
-                                write32(relocs[i], stdout);
-                        }
+                        for (i = 0; i < relocs64.count; i++)
+                                write_reloc(relocs64.offset[i], stdout);
                 }
+
+                /* Print a stop */
+                write_reloc(0, stdout);
+
+                /* Now print each relocation */
+                for (i = 0; i < relocs32.count; i++)
+                        write_reloc(relocs32.offset[i], stdout);
         }
 }
 
-static void usage(void)
-{
-        die("relocs [--abs-syms|--abs-relocs|--text|--realmode] vmlinux\n");
-}
+#if ELF_BITS == 64
+# define process process_64
+#else
+# define process process_32
+#endif
 
-int main(int argc, char **argv)
+void process(FILE *fp, int use_real_mode, int as_text,
+             int show_absolute_syms, int show_absolute_relocs)
 {
-        int show_absolute_syms, show_absolute_relocs;
-        int as_text, use_real_mode;
-        const char *fname;
-        FILE *fp;
-        int i;
-
-        show_absolute_syms = 0;
-        show_absolute_relocs = 0;
-        as_text = 0;
-        use_real_mode = 0;
-        fname = NULL;
-        for (i = 1; i < argc; i++) {
-                char *arg = argv[i];
-                if (*arg == '-') {
-                        if (strcmp(arg, "--abs-syms") == 0) {
-                                show_absolute_syms = 1;
-                                continue;
-                        }
-                        if (strcmp(arg, "--abs-relocs") == 0) {
-                                show_absolute_relocs = 1;
-                                continue;
-                        }
-                        if (strcmp(arg, "--text") == 0) {
-                                as_text = 1;
-                                continue;
-                        }
-                        if (strcmp(arg, "--realmode") == 0) {
-                                use_real_mode = 1;
-                                continue;
-                        }
-                }
-                else if (!fname) {
-                        fname = arg;
-                        continue;
-                }
-                usage();
-        }
-        if (!fname) {
-                usage();
-        }
         regex_init(use_real_mode);
-        fp = fopen(fname, "r");
-        if (!fp) {
-                die("Cannot open %s: %s\n",
-                        fname, strerror(errno));
-        }
         read_ehdr(fp);
         read_shdrs(fp);
         read_strtabs(fp);
         read_symtabs(fp);
         read_relocs(fp);
+        if (ELF_BITS == 64)
+                percpu_init();
         if (show_absolute_syms) {
                 print_absolute_symbols();
-                goto out;
+                return;
         }
         if (show_absolute_relocs) {
                 print_absolute_relocs();
-                goto out;
+                return;
         }
         emit_relocs(as_text, use_real_mode);
-out:
-        fclose(fp);
-        return 0;
 }
diff --git a/arch/x86/tools/relocs.h b/arch/x86/tools/relocs.h
new file mode 100644
index 000000000000..07cdb1eca4fa
--- /dev/null
+++ b/arch/x86/tools/relocs.h
@@ -0,0 +1,36 @@
+#ifndef RELOCS_H
+#define RELOCS_H
+
+#include <stdio.h>
+#include <stdarg.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <inttypes.h>
+#include <string.h>
+#include <errno.h>
+#include <unistd.h>
+#include <elf.h>
+#include <byteswap.h>
+#define USE_BSD
+#include <endian.h>
+#include <regex.h>
+#include <tools/le_byteshift.h>
+
+void die(char *fmt, ...);
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+enum symtype {
+        S_ABS,
+        S_REL,
+        S_SEG,
+        S_LIN,
+        S_NSYMTYPES
+};
+
+void process_32(FILE *fp, int use_real_mode, int as_text,
+                int show_absolute_syms, int show_absolute_relocs);
+void process_64(FILE *fp, int use_real_mode, int as_text,
+                int show_absolute_syms, int show_absolute_relocs);
+
+#endif /* RELOCS_H */
diff --git a/arch/x86/tools/relocs_32.c b/arch/x86/tools/relocs_32.c
new file mode 100644
index 000000000000..b2ade2bb4162
--- /dev/null
+++ b/arch/x86/tools/relocs_32.c
@@ -0,0 +1,17 @@
+#include "relocs.h"
+
+#define ELF_BITS 32
+
+#define ELF_MACHINE             EM_386
+#define ELF_MACHINE_NAME        "i386"
+#define SHT_REL_TYPE            SHT_REL
+#define Elf_Rel                 ElfW(Rel)
+
+#define ELF_CLASS               ELFCLASS32
+#define ELF_R_SYM(val)          ELF32_R_SYM(val)
+#define ELF_R_TYPE(val)         ELF32_R_TYPE(val)
+#define ELF_ST_TYPE(o)          ELF32_ST_TYPE(o)
+#define ELF_ST_BIND(o)          ELF32_ST_BIND(o)
+#define ELF_ST_VISIBILITY(o)    ELF32_ST_VISIBILITY(o)
+
+#include "relocs.c"
diff --git a/arch/x86/tools/relocs_64.c b/arch/x86/tools/relocs_64.c
new file mode 100644
index 000000000000..56b61b743c4c
--- /dev/null
+++ b/arch/x86/tools/relocs_64.c
@@ -0,0 +1,17 @@
+#include "relocs.h"
+
+#define ELF_BITS 64
+
+#define ELF_MACHINE             EM_X86_64
+#define ELF_MACHINE_NAME        "x86_64"
+#define SHT_REL_TYPE            SHT_RELA
+#define Elf_Rel                 Elf64_Rela
+
+#define ELF_CLASS               ELFCLASS64
+#define ELF_R_SYM(val)          ELF64_R_SYM(val)
+#define ELF_R_TYPE(val)         ELF64_R_TYPE(val)
+#define ELF_ST_TYPE(o)          ELF64_ST_TYPE(o)
+#define ELF_ST_BIND(o)          ELF64_ST_BIND(o)
+#define ELF_ST_VISIBILITY(o)    ELF64_ST_VISIBILITY(o)
+
+#include "relocs.c"
diff --git a/arch/x86/tools/relocs_common.c b/arch/x86/tools/relocs_common.c
new file mode 100644
index 000000000000..44d396823a53
--- /dev/null
+++ b/arch/x86/tools/relocs_common.c
@@ -0,0 +1,76 @@
+#include "relocs.h"
+
+void die(char *fmt, ...)
+{
+        va_list ap;
+        va_start(ap, fmt);
+        vfprintf(stderr, fmt, ap);
+        va_end(ap);
+        exit(1);
+}
+
+static void usage(void)
+{
+        die("relocs [--abs-syms|--abs-relocs|--text|--realmode] vmlinux\n");
+}
+
+int main(int argc, char **argv)
+{
+        int show_absolute_syms, show_absolute_relocs;
+        int as_text, use_real_mode;
+        const char *fname;
+        FILE *fp;
+        int i;
+        unsigned char e_ident[EI_NIDENT];
+
+        show_absolute_syms = 0;
+        show_absolute_relocs = 0;
+        as_text = 0;
+        use_real_mode = 0;
+        fname = NULL;
+        for (i = 1; i < argc; i++) {
+                char *arg = argv[i];
+                if (*arg == '-') {
+                        if (strcmp(arg, "--abs-syms") == 0) {
+                                show_absolute_syms = 1;
+                                continue;
+                        }
+                        if (strcmp(arg, "--abs-relocs") == 0) {
+                                show_absolute_relocs = 1;
+                                continue;
+                        }
+                        if (strcmp(arg, "--text") == 0) {
+                                as_text = 1;
+                                continue;
+                        }
+                        if (strcmp(arg, "--realmode") == 0) {
+                                use_real_mode = 1;
+                                continue;
+                        }
+                }
+                else if (!fname) {
+                        fname = arg;
+                        continue;
+                }
+                usage();
+        }
+        if (!fname) {
+                usage();
+        }
+        fp = fopen(fname, "r");
+        if (!fp) {
+                die("Cannot open %s: %s\n", fname, strerror(errno));
+        }
+        if (fread(&e_ident, 1, EI_NIDENT, fp) != EI_NIDENT) {
+                die("Cannot read %s: %s", fname, strerror(errno));
+        }
+        rewind(fp);
+        if (e_ident[EI_CLASS] == ELFCLASS64)
+                process_64(fp, use_real_mode, as_text,
+                           show_absolute_syms, show_absolute_relocs);
+        else
+                process_32(fp, use_real_mode, as_text,
+                           show_absolute_syms, show_absolute_relocs);
+        fclose(fp);
+        return 0;
+}
diff --git a/arch/x86/um/tls_32.c b/arch/x86/um/tls_32.c
index 5f5feff3d24c..80ffa5b9982d 100644
--- a/arch/x86/um/tls_32.c
+++ b/arch/x86/um/tls_32.c
@@ -5,6 +5,7 @@
 
 #include <linux/percpu.h>
 #include <linux/sched.h>
+#include <linux/syscalls.h>
 #include <asm/uaccess.h>
 #include <os.h>
 #include <skas.h>
@@ -274,7 +275,7 @@ clear:
         goto out;
 }
 
-int sys_set_thread_area(struct user_desc __user *user_desc)
+SYSCALL_DEFINE1(set_thread_area, struct user_desc __user *, user_desc)
 {
         struct user_desc info;
         int idx, ret;
@@ -322,7 +323,7 @@ int ptrace_set_thread_area(struct task_struct *child, int idx,
         return set_tls_entry(child, &info, idx, 0);
 }
 
-int sys_get_thread_area(struct user_desc __user *user_desc)
+SYSCALL_DEFINE1(get_thread_area, struct user_desc __user *, user_desc)
 {
         struct user_desc info;
         int idx, ret;
diff --git a/arch/x86/xen/Kconfig b/arch/x86/xen/Kconfig
index 131dacd2748a..1a3c76505649 100644
--- a/arch/x86/xen/Kconfig
+++ b/arch/x86/xen/Kconfig
@@ -4,7 +4,7 @@
 
 config XEN
         bool "Xen guest support"
-        select PARAVIRT
+        depends on PARAVIRT
         select PARAVIRT_CLOCK
         select XEN_HAVE_PVMMU
         depends on X86_64 || (X86_32 && X86_PAE && !X86_VISWS)
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index c8e1c7b95c3b..53d4f680c9b5 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -31,6 +31,7 @@
 #include <linux/pci.h>
 #include <linux/gfp.h>
 #include <linux/memblock.h>
+#include <linux/edd.h>
 
 #include <xen/xen.h>
 #include <xen/events.h>
@@ -1220,7 +1221,6 @@ static const struct pv_cpu_ops xen_cpu_ops __initconst = {
         .alloc_ldt = xen_alloc_ldt,
         .free_ldt = xen_free_ldt,
 
-        .store_gdt = native_store_gdt,
         .store_idt = native_store_idt,
         .store_tr = xen_store_tr,
 
@@ -1306,6 +1306,55 @@ static const struct machine_ops xen_machine_ops __initconst = {
         .emergency_restart = xen_emergency_restart,
 };
 
+static void __init xen_boot_params_init_edd(void)
+{
+#if IS_ENABLED(CONFIG_EDD)
+        struct xen_platform_op op;
+        struct edd_info *edd_info;
+        u32 *mbr_signature;
+        unsigned nr;
+        int ret;
+
+        edd_info = boot_params.eddbuf;
+        mbr_signature = boot_params.edd_mbr_sig_buffer;
+
+        op.cmd = XENPF_firmware_info;
+
+        op.u.firmware_info.type = XEN_FW_DISK_INFO;
+        for (nr = 0; nr < EDDMAXNR; nr++) {
+                struct edd_info *info = edd_info + nr;
+
+                op.u.firmware_info.index = nr;
+                info->params.length = sizeof(info->params);
+                set_xen_guest_handle(op.u.firmware_info.u.disk_info.edd_params,
+                                     &info->params);
+                ret = HYPERVISOR_dom0_op(&op);
+                if (ret)
+                        break;
+
+#define C(x) info->x = op.u.firmware_info.u.disk_info.x
+                C(device);
+                C(version);
+                C(interface_support);
+                C(legacy_max_cylinder);
+                C(legacy_max_head);
+                C(legacy_sectors_per_track);
+#undef C
+        }
+        boot_params.eddbuf_entries = nr;
+
+        op.u.firmware_info.type = XEN_FW_DISK_MBR_SIGNATURE;
+        for (nr = 0; nr < EDD_MBR_SIG_MAX; nr++) {
+                op.u.firmware_info.index = nr;
+                ret = HYPERVISOR_dom0_op(&op);
+                if (ret)
+                        break;
+                mbr_signature[nr] = op.u.firmware_info.u.disk_mbr_signature.mbr_signature;
+        }
+        boot_params.edd_mbr_sig_buf_entries = nr;
+#endif
+}
+
 /*
  * Set up the GDT and segment registers for -fstack-protector.  Until
  * we do this, we have to be careful not to call any stack-protected
@@ -1508,6 +1557,8 @@ asmlinkage void __init xen_start_kernel(void)
                 /* Avoid searching for BIOS MP tables */
                 x86_init.mpparse.find_smp_config = x86_init_noop;
                 x86_init.mpparse.get_smp_config = x86_init_uint_noop;
+
+                xen_boot_params_init_edd();
         }
 #ifdef CONFIG_PCI
         /* PCI BIOS service won't work from a PV guest. */
@@ -1589,8 +1640,11 @@ static int __cpuinit xen_hvm_cpu_notify(struct notifier_block *self,
         switch (action) {
         case CPU_UP_PREPARE:
                 xen_vcpu_setup(cpu);
-                if (xen_have_vector_callback)
+                if (xen_have_vector_callback) {
                         xen_init_lock_cpu(cpu);
+                        if (xen_feature(XENFEAT_hvm_safe_pvclock))
+                                xen_setup_timer(cpu);
+                }
                 break;
         default:
                 break;
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index e006c18d288a..fdc3ba28ca38 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -2043,9 +2043,7 @@ static void xen_set_fixmap(unsigned idx, phys_addr_t phys, pgprot_t prot)
 
         switch (idx) {
         case FIX_BTMAP_END ... FIX_BTMAP_BEGIN:
-#ifdef CONFIG_X86_F00F_BUG
-        case FIX_F00F_IDT:
-#endif
+        case FIX_RO_IDT:
 #ifdef CONFIG_X86_32
         case FIX_WP_TEST:
         case FIX_VDSO:
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index 09ea61d2e02f..8ff37995d54e 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -95,7 +95,7 @@ static void __cpuinit cpu_bringup(void)
 static void __cpuinit cpu_bringup_and_idle(void)
 {
         cpu_bringup();
-        cpu_idle();
+        cpu_startup_entry(CPUHP_ONLINE);
 }
 
 static int xen_smp_intr_init(unsigned int cpu)
@@ -144,6 +144,13 @@ static int xen_smp_intr_init(unsigned int cpu)
                 goto fail;
         per_cpu(xen_callfuncsingle_irq, cpu) = rc;
 
+        /*
+         * The IRQ worker on PVHVM goes through the native path and uses the
+         * IPI mechanism.
+         */
+        if (xen_hvm_domain())
+                return 0;
+
         callfunc_name = kasprintf(GFP_KERNEL, "irqwork%d", cpu);
         rc = bind_ipi_to_irqhandler(XEN_IRQ_WORK_VECTOR,
                                     cpu,
@@ -167,6 +174,9 @@ static int xen_smp_intr_init(unsigned int cpu)
         if (per_cpu(xen_callfuncsingle_irq, cpu) >= 0)
                 unbind_from_irqhandler(per_cpu(xen_callfuncsingle_irq, cpu),
                                        NULL);
+        if (xen_hvm_domain())
+                return rc;
+
         if (per_cpu(xen_irq_work, cpu) >= 0)
                 unbind_from_irqhandler(per_cpu(xen_irq_work, cpu), NULL);
 
@@ -418,7 +428,7 @@ static int xen_cpu_disable(void)
 
 static void xen_cpu_die(unsigned int cpu)
 {
-        while (HYPERVISOR_vcpu_op(VCPUOP_is_up, cpu, NULL)) {
+        while (xen_pv_domain() && HYPERVISOR_vcpu_op(VCPUOP_is_up, cpu, NULL)) {
                 current->state = TASK_UNINTERRUPTIBLE;
                 schedule_timeout(HZ/10);
         }
@@ -426,7 +436,8 @@ static void xen_cpu_die(unsigned int cpu)
         unbind_from_irqhandler(per_cpu(xen_callfunc_irq, cpu), NULL);
         unbind_from_irqhandler(per_cpu(xen_debug_irq, cpu), NULL);
         unbind_from_irqhandler(per_cpu(xen_callfuncsingle_irq, cpu), NULL);
-        unbind_from_irqhandler(per_cpu(xen_irq_work, cpu), NULL);
+        if (!xen_hvm_domain())
+                unbind_from_irqhandler(per_cpu(xen_irq_work, cpu), NULL);
         xen_uninit_lock_cpu(cpu);
         xen_teardown_timer(cpu);
 }
@@ -657,11 +668,7 @@ static int __cpuinit xen_hvm_cpu_up(unsigned int cpu, struct task_struct *tidle)
 
 static void xen_hvm_cpu_die(unsigned int cpu)
 {
-        unbind_from_irqhandler(per_cpu(xen_resched_irq, cpu), NULL);
-        unbind_from_irqhandler(per_cpu(xen_callfunc_irq, cpu), NULL);
-        unbind_from_irqhandler(per_cpu(xen_debug_irq, cpu), NULL);
-        unbind_from_irqhandler(per_cpu(xen_callfuncsingle_irq, cpu), NULL);
-        unbind_from_irqhandler(per_cpu(xen_irq_work, cpu), NULL);
+        xen_cpu_die(cpu);
         native_cpu_die(cpu);
 }
 
diff --git a/arch/x86/xen/spinlock.c b/arch/x86/xen/spinlock.c
index f7a080ef0354..8b54603ce816 100644
--- a/arch/x86/xen/spinlock.c
+++ b/arch/x86/xen/spinlock.c
@@ -364,6 +364,16 @@ void __cpuinit xen_init_lock_cpu(int cpu)
         int irq;
         const char *name;
 
+        WARN(per_cpu(lock_kicker_irq, cpu) > 0, "spinlock on CPU%d exists on IRQ%d!\n",
+             cpu, per_cpu(lock_kicker_irq, cpu));
+
+        /*
+         * See git commit f10cd522c5fbfec9ae3cc01967868c9c2401ed23
+         * (xen: disable PV spinlocks on HVM)
+         */
+        if (xen_hvm_domain())
+                return;
+
         name = kasprintf(GFP_KERNEL, "spinlock%d", cpu);
         irq = bind_ipi_to_irqhandler(XEN_SPIN_UNLOCK_VECTOR,
                                      cpu,
@@ -382,11 +392,26 @@ void __cpuinit xen_init_lock_cpu(int cpu)
 
 void xen_uninit_lock_cpu(int cpu)
 {
+        /*
+         * See git commit f10cd522c5fbfec9ae3cc01967868c9c2401ed23
+         * (xen: disable PV spinlocks on HVM)
+         */
+        if (xen_hvm_domain())
+                return;
+
         unbind_from_irqhandler(per_cpu(lock_kicker_irq, cpu), NULL);
+        per_cpu(lock_kicker_irq, cpu) = -1;
 }
 
 void __init xen_init_spinlocks(void)
 {
+        /*
+         * See git commit f10cd522c5fbfec9ae3cc01967868c9c2401ed23
+         * (xen: disable PV spinlocks on HVM)
+         */
+        if (xen_hvm_domain())
+                return;
+
         BUILD_BUG_ON(sizeof(struct xen_spinlock) > sizeof(arch_spinlock_t));
 
         pv_lock_ops.spin_is_locked = xen_spin_is_locked;
diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
index 0296a9522501..3d88bfdf9e1c 100644
--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
@@ -377,7 +377,7 @@ static const struct clock_event_device xen_vcpuop_clockevent = {
 
 static const struct clock_event_device *xen_clockevent =
         &xen_timerop_clockevent;
-static DEFINE_PER_CPU(struct clock_event_device, xen_clock_events);
+static DEFINE_PER_CPU(struct clock_event_device, xen_clock_events) = { .irq = -1 };
 
 static irqreturn_t xen_timer_interrupt(int irq, void *dev_id)
 {
@@ -401,6 +401,9 @@ void xen_setup_timer(int cpu)
         struct clock_event_device *evt;
         int irq;
 
+        evt = &per_cpu(xen_clock_events, cpu);
+        WARN(evt->irq >= 0, "IRQ%d for CPU%d is already allocated\n", evt->irq, cpu);
+
         printk(KERN_INFO "installing Xen timer for CPU %d\n", cpu);
 
         name = kasprintf(GFP_KERNEL, "timer%d", cpu);
@@ -413,7 +416,6 @@ void xen_setup_timer(int cpu)
                                       IRQF_FORCE_RESUME,
                                       name, NULL);
 
-        evt = &per_cpu(xen_clock_events, cpu);
         memcpy(evt, xen_clockevent, sizeof(*evt));
 
         evt->cpumask = cpumask_of(cpu);
@@ -426,6 +428,7 @@ void xen_teardown_timer(int cpu)
         BUG_ON(cpu == 0);
         evt = &per_cpu(xen_clock_events, cpu);
         unbind_from_irqhandler(evt->irq, NULL);
+        evt->irq = -1;
 }
 
 void xen_setup_cpu_clockevents(void)
@@ -497,7 +500,11 @@ static void xen_hvm_setup_cpu_clockevents(void)
 {
         int cpu = smp_processor_id();
         xen_setup_runstate_info(cpu);
-        xen_setup_timer(cpu);
+        /*
+         * xen_setup_timer(cpu) - snprintf is bad in atomic context. Hence
+         * doing it xen_hvm_cpu_notify (which gets called by smp_init during
+         * early bootup and also during CPU hotplug events).
+         */
         xen_setup_cpu_clockevents();
 }
 
diff --git a/arch/xtensa/include/asm/unistd.h b/arch/xtensa/include/asm/unistd.h
index c38834de9ac7..cb4c2ce8d447 100644
--- a/arch/xtensa/include/asm/unistd.h
+++ b/arch/xtensa/include/asm/unistd.h
@@ -4,14 +4,6 @@
 #define __ARCH_WANT_SYS_CLONE
 #include <uapi/asm/unistd.h>
 
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall");
-
 #define __ARCH_WANT_STAT64
 #define __ARCH_WANT_SYS_UTIME
 #define __ARCH_WANT_SYS_LLSEEK
diff --git a/arch/xtensa/kernel/process.c b/arch/xtensa/kernel/process.c
index 5cd82e9f601c..1c85323f01d7 100644
--- a/arch/xtensa/kernel/process.c
+++ b/arch/xtensa/kernel/process.c
@@ -105,19 +105,9 @@ void coprocessor_flush_all(struct thread_info *ti)
 /*
  * Powermanagement idle function, if any is provided by the platform.
  */
-
-void cpu_idle(void)
+void arch_cpu_idle(void)
 {
-        local_irq_enable();
-
-        /* endless idle loop with no priority at all */
-        while (1) {
-                rcu_idle_enter();
-                while (!need_resched())
-                        platform_idle();
-                rcu_idle_exit();
-                schedule_preempt_disabled();
-        }
+        platform_idle();
 }
 
 /*
diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c
index 923db5c15278..458186dab5dc 100644
--- a/arch/xtensa/kernel/traps.c
+++ b/arch/xtensa/kernel/traps.c
@@ -383,6 +383,8 @@ void show_regs(struct pt_regs * regs)
 {
         int i, wmask;
 
+        show_regs_print_info(KERN_DEFAULT);
+
         wmask = regs->wmask & ~1;
 
         for (i = 0; i < 16; i++) {
@@ -481,14 +483,6 @@ void show_stack(struct task_struct *task, unsigned long *sp)
         show_trace(task, stack);
 }
 
-void dump_stack(void)
-{
-        show_stack(current, NULL);
-}
-
-EXPORT_SYMBOL(dump_stack);
-
-
 void show_code(unsigned int *pc)
 {
         long i;
diff --git a/arch/xtensa/mm/init.c b/arch/xtensa/mm/init.c
index 7a5156ffebb6..bba125b4bb06 100644
--- a/arch/xtensa/mm/init.c
+++ b/arch/xtensa/mm/init.c
@@ -208,32 +208,17 @@ void __init mem_init(void)
                highmemsize >> 10);
 }
 
-void
-free_reserved_mem(void *start, void *end)
-{
-        for (; start < end; start += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(start));
-                init_page_count(virt_to_page(start));
-                free_page((unsigned long)start);
-                totalram_pages++;
-        }
-}
-
 #ifdef CONFIG_BLK_DEV_INITRD
 extern int initrd_is_mapped;
 
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        if (initrd_is_mapped) {
-                free_reserved_mem((void*)start, (void*)end);
-                printk ("Freeing initrd memory: %ldk freed\n",(end-start)>>10);
-        }
+        if (initrd_is_mapped)
+                free_reserved_area(start, end, 0, "initrd");
 }
 #endif
 
 void free_initmem(void)
 {
-        free_reserved_mem(__init_begin, __init_end);
-        printk("Freeing unused kernel memory: %zuk freed\n",
-               (__init_end - __init_begin) >> 10);
+        free_initmem_default(0);
 }
diff --git a/arch/xtensa/platforms/iss/simdisk.c b/arch/xtensa/platforms/iss/simdisk.c
index f58ffc3b68a8..88608cc11b8c 100644
--- a/arch/xtensa/platforms/iss/simdisk.c
+++ b/arch/xtensa/platforms/iss/simdisk.c
@@ -214,20 +214,27 @@ static int simdisk_detach(struct simdisk *dev)
         return err;
 }
 
-static int proc_read_simdisk(char *page, char **start, off_t off,
-                int count, int *eof, void *data)
+static ssize_t proc_read_simdisk(struct file *file, char __user *buf,
+                        size_t size, loff_t *ppos)
 {
-        int len;
-        struct simdisk *dev = (struct simdisk *) data;
-        len = sprintf(page, "%s\n", dev->filename ? dev->filename : "");
-        return len;
+        struct simdisk *dev = PDE_DATA(file_inode(file));
+        char *s = dev->filename;
+        if (s) {
+                ssize_t n = simple_read_from_buffer(buf, size, ppos,
+                                                        s, strlen(s));
+                if (n < 0)
+                        return n;
+                buf += n;
+                size -= n;
+        }
+        return simple_read_from_buffer(buf, size, ppos, "\n", 1);
 }
 
-static int proc_write_simdisk(struct file *file, const char *buffer,
-                unsigned long count, void *data)
+static ssize_t proc_write_simdisk(struct file *file, const char __user *buf,
+                        size_t count, loff_t *ppos)
 {
         char *tmp = kmalloc(count + 1, GFP_KERNEL);
-        struct simdisk *dev = (struct simdisk *) data;
+        struct simdisk *dev = PDE_DATA(file_inode(file));
         int err;
 
         if (tmp == NULL)
@@ -256,6 +263,12 @@ out_free:
         return err;
 }
 
+static const struct file_operations fops = {
+        .read = proc_read_simdisk,
+        .write = proc_write_simdisk,
+        .llseek = default_llseek,
+};
+
 static int __init simdisk_setup(struct simdisk *dev, int which,
                 struct proc_dir_entry *procdir)
 {
@@ -289,10 +302,7 @@ static int __init simdisk_setup(struct simdisk *dev, int which,
         set_capacity(dev->gd, 0);
         add_disk(dev->gd);
 
-        dev->procfile = create_proc_entry(tmp, 0644, procdir);
-        dev->procfile->data = dev;
-        dev->procfile->read_proc = proc_read_simdisk;
-        dev->procfile->write_proc = proc_write_simdisk;
+        dev->procfile = proc_create_data(tmp, 0644, procdir, &fops, dev);
         return 0;
 
 out_alloc_disk: