60 files changed, 2218 insertions, 1939 deletions
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 5fc202cdfdb6..995e7cc02bec 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -12,7 +12,8 @@ obj-				:=
 # Core
-obj-$(CONFIG_ARCH_EXYNOS4)      += common.o clock.o
+obj-$(CONFIG_ARCH_EXYNOS)       += common.o
+obj-$(CONFIG_ARCH_EXYNOS4)      += clock-exynos4.o
 obj-$(CONFIG_CPU_EXYNOS4210)    += clock-exynos4210.o
 obj-$(CONFIG_SOC_EXYNOS4212)    += clock-exynos4212.o
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
new file mode 100644
index 000000000000..31b59e65463a
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -0,0 +1,1563 @@
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS4 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/syscore_ops.h>
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+#include <plat/pm.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/sysmmu.h>
+#include "common.h"
+#include "clock-exynos4.h"
+#ifdef CONFIG_PM_SLEEP
+static struct sleep_save exynos4_clock_save[] = {
+        SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
+        SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
+        SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
+        SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
+        SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
+        SAVE_ITEM(EXYNOS4_CLKSRC_TV),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
+        SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
+        SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
+        SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
+        SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
+        SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
+        SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
+        SAVE_ITEM(EXYNOS4_CLKDIV_TV),
+        SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
+        SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
+        SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
+        SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
+        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
+        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
+        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
+        SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
+        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
+        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
+        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
+        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
+        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
+        SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
+        SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
+        SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
+        SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
+        SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
+        SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
+        SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
+        SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
+        SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
+        SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
+        SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
+        SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
+        SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
+        SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
+};
+#endif
+static struct clk exynos4_clk_sclk_hdmi27m = {
+        .name           = "sclk_hdmi27m",
+        .rate           = 27000000,
+};
+static struct clk exynos4_clk_sclk_hdmiphy = {
+        .name           = "sclk_hdmiphy",
+};
+static struct clk exynos4_clk_sclk_usbphy0 = {
+        .name           = "sclk_usbphy0",
+        .rate           = 27000000,
+};
+static struct clk exynos4_clk_sclk_usbphy1 = {
+        .name           = "sclk_usbphy1",
+};
+static struct clk dummy_apb_pclk = {
+        .name           = "apb_pclk",
+        .id             = -1,
+};
+static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
+}
+static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
+}
+static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
+}
+int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
+}
+static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
+}
+static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
+}
+static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
+}
+static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
+}
+static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
+}
+static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
+}
+static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
+}
+static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
+}
+int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
+}
+int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
+}
+static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
+}
+static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
+}
+static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
+}
+static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
+}
+/* Core list of CMU_CPU side */
+static struct clksrc_clk exynos4_clk_mout_apll = {
+        .clk    = {
+                .name           = "mout_apll",
+        },
+        .sources = &clk_src_apll,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
+};
+static struct clksrc_clk exynos4_clk_sclk_apll = {
+        .clk    = {
+                .name           = "sclk_apll",
+                .parent         = &exynos4_clk_mout_apll.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
+};
+static struct clksrc_clk exynos4_clk_mout_epll = {
+        .clk    = {
+                .name           = "mout_epll",
+        },
+        .sources = &clk_src_epll,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
+};
+struct clksrc_clk exynos4_clk_mout_mpll = {
+        .clk    = {
+                .name           = "mout_mpll",
+        },
+        .sources = &clk_src_mpll,
+        /* reg_src will be added in each SoCs' clock */
+};
+static struct clk *exynos4_clkset_moutcore_list[] = {
+        [0] = &exynos4_clk_mout_apll.clk,
+        [1] = &exynos4_clk_mout_mpll.clk,
+};
+static struct clksrc_sources exynos4_clkset_moutcore = {
+        .sources        = exynos4_clkset_moutcore_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_moutcore_list),
+};
+static struct clksrc_clk exynos4_clk_moutcore = {
+        .clk    = {
+                .name           = "moutcore",
+        },
+        .sources = &exynos4_clkset_moutcore,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
+};
+static struct clksrc_clk exynos4_clk_coreclk = {
+        .clk    = {
+                .name           = "core_clk",
+                .parent         = &exynos4_clk_moutcore.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
+};
+static struct clksrc_clk exynos4_clk_armclk = {
+        .clk    = {
+                .name           = "armclk",
+                .parent         = &exynos4_clk_coreclk.clk,
+        },
+};
+static struct clksrc_clk exynos4_clk_aclk_corem0 = {
+        .clk    = {
+                .name           = "aclk_corem0",
+                .parent         = &exynos4_clk_coreclk.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+static struct clksrc_clk exynos4_clk_aclk_cores = {
+        .clk    = {
+                .name           = "aclk_cores",
+                .parent         = &exynos4_clk_coreclk.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+static struct clksrc_clk exynos4_clk_aclk_corem1 = {
+        .clk    = {
+                .name           = "aclk_corem1",
+                .parent         = &exynos4_clk_coreclk.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
+};
+static struct clksrc_clk exynos4_clk_periphclk = {
+        .clk    = {
+                .name           = "periphclk",
+                .parent         = &exynos4_clk_coreclk.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
+};
+/* Core list of CMU_CORE side */
+static struct clk *exynos4_clkset_corebus_list[] = {
+        [0] = &exynos4_clk_mout_mpll.clk,
+        [1] = &exynos4_clk_sclk_apll.clk,
+};
+struct clksrc_sources exynos4_clkset_mout_corebus = {
+        .sources        = exynos4_clkset_corebus_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_corebus_list),
+};
+static struct clksrc_clk exynos4_clk_mout_corebus = {
+        .clk    = {
+                .name           = "mout_corebus",
+        },
+        .sources = &exynos4_clkset_mout_corebus,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
+};
+static struct clksrc_clk exynos4_clk_sclk_dmc = {
+        .clk    = {
+                .name           = "sclk_dmc",
+                .parent         = &exynos4_clk_mout_corebus.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
+};
+static struct clksrc_clk exynos4_clk_aclk_cored = {
+        .clk    = {
+                .name           = "aclk_cored",
+                .parent         = &exynos4_clk_sclk_dmc.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
+};
+static struct clksrc_clk exynos4_clk_aclk_corep = {
+        .clk    = {
+                .name           = "aclk_corep",
+                .parent         = &exynos4_clk_aclk_cored.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
+};
+static struct clksrc_clk exynos4_clk_aclk_acp = {
+        .clk    = {
+                .name           = "aclk_acp",
+                .parent         = &exynos4_clk_mout_corebus.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
+};
+static struct clksrc_clk exynos4_clk_pclk_acp = {
+        .clk    = {
+                .name           = "pclk_acp",
+                .parent         = &exynos4_clk_aclk_acp.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
+};
+/* Core list of CMU_TOP side */
+struct clk *exynos4_clkset_aclk_top_list[] = {
+        [0] = &exynos4_clk_mout_mpll.clk,
+        [1] = &exynos4_clk_sclk_apll.clk,
+};
+static struct clksrc_sources exynos4_clkset_aclk = {
+        .sources        = exynos4_clkset_aclk_top_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
+};
+static struct clksrc_clk exynos4_clk_aclk_200 = {
+        .clk    = {
+                .name           = "aclk_200",
+        },
+        .sources = &exynos4_clkset_aclk,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
+};
+static struct clksrc_clk exynos4_clk_aclk_100 = {
+        .clk    = {
+                .name           = "aclk_100",
+        },
+        .sources = &exynos4_clkset_aclk,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
+};
+static struct clksrc_clk exynos4_clk_aclk_160 = {
+        .clk    = {
+                .name           = "aclk_160",
+        },
+        .sources = &exynos4_clkset_aclk,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
+};
+struct clksrc_clk exynos4_clk_aclk_133 = {
+        .clk    = {
+                .name           = "aclk_133",
+        },
+        .sources = &exynos4_clkset_aclk,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
+};
+static struct clk *exynos4_clkset_vpllsrc_list[] = {
+        [0] = &clk_fin_vpll,
+        [1] = &exynos4_clk_sclk_hdmi27m,
+};
+static struct clksrc_sources exynos4_clkset_vpllsrc = {
+        .sources        = exynos4_clkset_vpllsrc_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
+};
+static struct clksrc_clk exynos4_clk_vpllsrc = {
+        .clk    = {
+                .name           = "vpll_src",
+                .enable         = exynos4_clksrc_mask_top_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .sources = &exynos4_clkset_vpllsrc,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
+};
+static struct clk *exynos4_clkset_sclk_vpll_list[] = {
+        [0] = &exynos4_clk_vpllsrc.clk,
+        [1] = &clk_fout_vpll,
+};
+static struct clksrc_sources exynos4_clkset_sclk_vpll = {
+        .sources        = exynos4_clkset_sclk_vpll_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
+};
+static struct clksrc_clk exynos4_clk_sclk_vpll = {
+        .clk    = {
+                .name           = "sclk_vpll",
+        },
+        .sources = &exynos4_clkset_sclk_vpll,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
+};
+static struct clk exynos4_init_clocks_off[] = {
+        {
+                .name           = "timers",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1<<24),
+        }, {
+                .name           = "csis",
+                .devname        = "s5p-mipi-csis.0",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "csis",
+                .devname        = "s5p-mipi-csis.1",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "fimc",
+                .devname        = "exynos4-fimc.0",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "fimc",
+                .devname        = "exynos4-fimc.1",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "fimc",
+                .devname        = "exynos4-fimc.2",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "fimc",
+                .devname        = "exynos4-fimc.3",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "fimd",
+                .devname        = "exynos4-fb.0",
+                .enable         = exynos4_clk_ip_lcd0_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "hsmmc",
+                .devname        = "s3c-sdhci.0",
+                .parent         = &exynos4_clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "hsmmc",
+                .devname        = "s3c-sdhci.1",
+                .parent         = &exynos4_clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "hsmmc",
+                .devname        = "s3c-sdhci.2",
+                .parent         = &exynos4_clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "hsmmc",
+                .devname        = "s3c-sdhci.3",
+                .parent         = &exynos4_clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "dwmmc",
+                .parent         = &exynos4_clk_aclk_133.clk,
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 9),
+        }, {
+                .name           = "dac",
+                .devname        = "s5p-sdo",
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "mixer",
+                .devname        = "s5p-mixer",
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "vp",
+                .devname        = "s5p-mixer",
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "hdmi",
+                .devname        = "exynos4-hdmi",
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "hdmiphy",
+                .devname        = "exynos4-hdmi",
+                .enable         = exynos4_clk_hdmiphy_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "dacphy",
+                .devname        = "s5p-sdo",
+                .enable         = exynos4_clk_dac_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "adc",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 15),
+        }, {
+                .name           = "keypad",
+                .enable         = exynos4_clk_ip_perir_ctrl,
+                .ctrlbit        = (1 << 16),
+        }, {
+                .name           = "rtc",
+                .enable         = exynos4_clk_ip_perir_ctrl,
+                .ctrlbit        = (1 << 15),
+        }, {
+                .name           = "watchdog",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_perir_ctrl,
+                .ctrlbit        = (1 << 14),
+        }, {
+                .name           = "usbhost",
+                .enable         = exynos4_clk_ip_fsys_ctrl ,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "otg",
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 13),
+        }, {
+                .name           = "spi",
+                .devname        = "s3c64xx-spi.0",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 16),
+        }, {
+                .name           = "spi",
+                .devname        = "s3c64xx-spi.1",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 17),
+        }, {
+                .name           = "spi",
+                .devname        = "s3c64xx-spi.2",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 18),
+        }, {
+                .name           = "iis",
+                .devname        = "samsung-i2s.0",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 19),
+        }, {
+                .name           = "iis",
+                .devname        = "samsung-i2s.1",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 20),
+        }, {
+                .name           = "iis",
+                .devname        = "samsung-i2s.2",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 21),
+        }, {
+                .name           = "ac97",
+                .devname        = "samsung-ac97",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 27),
+        }, {
+                .name           = "fimg2d",
+                .enable         = exynos4_clk_ip_image_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "mfc",
+                .devname        = "s5p-mfc",
+                .enable         = exynos4_clk_ip_mfc_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.0",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.1",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.2",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.3",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 9),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.4",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 10),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.5",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 11),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.6",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-i2c.7",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 13),
+        }, {
+                .name           = "i2c",
+                .devname        = "s3c2440-hdmiphy-i2c",
+                .parent         = &exynos4_clk_aclk_100.clk,
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 14),
+        }, {
+                .name           = "SYSMMU_MDMA",
+                .enable         = exynos4_clk_ip_image_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "SYSMMU_FIMC0",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "SYSMMU_FIMC1",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "SYSMMU_FIMC2",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 9),
+        }, {
+                .name           = "SYSMMU_FIMC3",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 10),
+        }, {
+                .name           = "SYSMMU_JPEG",
+                .enable         = exynos4_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 11),
+        }, {
+                .name           = "SYSMMU_FIMD0",
+                .enable         = exynos4_clk_ip_lcd0_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "SYSMMU_FIMD1",
+                .enable         = exynos4_clk_ip_lcd1_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "SYSMMU_PCIe",
+                .enable         = exynos4_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 18),
+        }, {
+                .name           = "SYSMMU_G2D",
+                .enable         = exynos4_clk_ip_image_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "SYSMMU_ROTATOR",
+                .enable         = exynos4_clk_ip_image_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "SYSMMU_TV",
+                .enable         = exynos4_clk_ip_tv_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "SYSMMU_MFC_L",
+                .enable         = exynos4_clk_ip_mfc_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "SYSMMU_MFC_R",
+                .enable         = exynos4_clk_ip_mfc_ctrl,
+                .ctrlbit        = (1 << 2),
+        }
+};
+static struct clk exynos4_init_clocks_on[] = {
+        {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.0",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.1",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.2",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.3",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.4",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "uart",
+                .devname        = "s5pv210-uart.5",
+                .enable         = exynos4_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 5),
+        }
+};
+static struct clk exynos4_clk_pdma0 = {
+        .name           = "dma",
+        .devname        = "dma-pl330.0",
+        .enable         = exynos4_clk_ip_fsys_ctrl,
+        .ctrlbit        = (1 << 0),
+};
+static struct clk exynos4_clk_pdma1 = {
+        .name           = "dma",
+        .devname        = "dma-pl330.1",
+        .enable         = exynos4_clk_ip_fsys_ctrl,
+        .ctrlbit        = (1 << 1),
+};
+struct clk *exynos4_clkset_group_list[] = {
+        [0] = &clk_ext_xtal_mux,
+        [1] = &clk_xusbxti,
+        [2] = &exynos4_clk_sclk_hdmi27m,
+        [3] = &exynos4_clk_sclk_usbphy0,
+        [4] = &exynos4_clk_sclk_usbphy1,
+        [5] = &exynos4_clk_sclk_hdmiphy,
+        [6] = &exynos4_clk_mout_mpll.clk,
+        [7] = &exynos4_clk_mout_epll.clk,
+        [8] = &exynos4_clk_sclk_vpll.clk,
+};
+struct clksrc_sources exynos4_clkset_group = {
+        .sources        = exynos4_clkset_group_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_group_list),
+};
+static struct clk *exynos4_clkset_mout_g2d0_list[] = {
+        [0] = &exynos4_clk_mout_mpll.clk,
+        [1] = &exynos4_clk_sclk_apll.clk,
+};
+static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
+        .sources        = exynos4_clkset_mout_g2d0_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
+};
+static struct clksrc_clk exynos4_clk_mout_g2d0 = {
+        .clk    = {
+                .name           = "mout_g2d0",
+        },
+        .sources = &exynos4_clkset_mout_g2d0,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
+};
+static struct clk *exynos4_clkset_mout_g2d1_list[] = {
+        [0] = &exynos4_clk_mout_epll.clk,
+        [1] = &exynos4_clk_sclk_vpll.clk,
+};
+static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
+        .sources        = exynos4_clkset_mout_g2d1_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
+};
+static struct clksrc_clk exynos4_clk_mout_g2d1 = {
+        .clk    = {
+                .name           = "mout_g2d1",
+        },
+        .sources = &exynos4_clkset_mout_g2d1,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
+};
+static struct clk *exynos4_clkset_mout_g2d_list[] = {
+        [0] = &exynos4_clk_mout_g2d0.clk,
+        [1] = &exynos4_clk_mout_g2d1.clk,
+};
+static struct clksrc_sources exynos4_clkset_mout_g2d = {
+        .sources        = exynos4_clkset_mout_g2d_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
+};
+static struct clk *exynos4_clkset_mout_mfc0_list[] = {
+        [0] = &exynos4_clk_mout_mpll.clk,
+        [1] = &exynos4_clk_sclk_apll.clk,
+};
+static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
+        .sources        = exynos4_clkset_mout_mfc0_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
+};
+static struct clksrc_clk exynos4_clk_mout_mfc0 = {
+        .clk    = {
+                .name           = "mout_mfc0",
+        },
+        .sources = &exynos4_clkset_mout_mfc0,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
+};
+static struct clk *exynos4_clkset_mout_mfc1_list[] = {
+        [0] = &exynos4_clk_mout_epll.clk,
+        [1] = &exynos4_clk_sclk_vpll.clk,
+};
+static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
+        .sources        = exynos4_clkset_mout_mfc1_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
+};
+static struct clksrc_clk exynos4_clk_mout_mfc1 = {
+        .clk    = {
+                .name           = "mout_mfc1",
+        },
+        .sources = &exynos4_clkset_mout_mfc1,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
+};
+static struct clk *exynos4_clkset_mout_mfc_list[] = {
+        [0] = &exynos4_clk_mout_mfc0.clk,
+        [1] = &exynos4_clk_mout_mfc1.clk,
+};
+static struct clksrc_sources exynos4_clkset_mout_mfc = {
+        .sources        = exynos4_clkset_mout_mfc_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
+};
+static struct clk *exynos4_clkset_sclk_dac_list[] = {
+        [0] = &exynos4_clk_sclk_vpll.clk,
+        [1] = &exynos4_clk_sclk_hdmiphy,
+};
+static struct clksrc_sources exynos4_clkset_sclk_dac = {
+        .sources        = exynos4_clkset_sclk_dac_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
+};
+static struct clksrc_clk exynos4_clk_sclk_dac = {
+        .clk            = {
+                .name           = "sclk_dac",
+                .enable         = exynos4_clksrc_mask_tv_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .sources = &exynos4_clkset_sclk_dac,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
+};
+static struct clksrc_clk exynos4_clk_sclk_pixel = {
+        .clk            = {
+                .name           = "sclk_pixel",
+                .parent         = &exynos4_clk_sclk_vpll.clk,
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
+};
+static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
+        [0] = &exynos4_clk_sclk_pixel.clk,
+        [1] = &exynos4_clk_sclk_hdmiphy,
+};
+static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
+        .sources        = exynos4_clkset_sclk_hdmi_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
+};
+static struct clksrc_clk exynos4_clk_sclk_hdmi = {
+        .clk            = {
+                .name           = "sclk_hdmi",
+                .enable         = exynos4_clksrc_mask_tv_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .sources = &exynos4_clkset_sclk_hdmi,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
+};
+static struct clk *exynos4_clkset_sclk_mixer_list[] = {
+        [0] = &exynos4_clk_sclk_dac.clk,
+        [1] = &exynos4_clk_sclk_hdmi.clk,
+};
+static struct clksrc_sources exynos4_clkset_sclk_mixer = {
+        .sources        = exynos4_clkset_sclk_mixer_list,
+        .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
+};
+static struct clksrc_clk exynos4_clk_sclk_mixer = {
+        .clk    = {
+                .name           = "sclk_mixer",
+                .enable         = exynos4_clksrc_mask_tv_ctrl,
+                .ctrlbit        = (1 << 4),
+        },
+        .sources = &exynos4_clkset_sclk_mixer,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
+};
+static struct clksrc_clk *exynos4_sclk_tv[] = {
+        &exynos4_clk_sclk_dac,
+        &exynos4_clk_sclk_pixel,
+        &exynos4_clk_sclk_hdmi,
+        &exynos4_clk_sclk_mixer,
+};
+static struct clksrc_clk exynos4_clk_dout_mmc0 = {
+        .clk    = {
+                .name           = "dout_mmc0",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+};
+static struct clksrc_clk exynos4_clk_dout_mmc1 = {
+        .clk    = {
+                .name           = "dout_mmc1",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+};
+static struct clksrc_clk exynos4_clk_dout_mmc2 = {
+        .clk    = {
+                .name           = "dout_mmc2",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+};
+static struct clksrc_clk exynos4_clk_dout_mmc3 = {
+        .clk    = {
+                .name           = "dout_mmc3",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+};
+static struct clksrc_clk exynos4_clk_dout_mmc4 = {
+        .clk            = {
+                .name           = "dout_mmc4",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+};
+static struct clksrc_clk exynos4_clksrcs[] = {
+        {
+                .clk    = {
+                        .name           = "sclk_pwm",
+                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                        .ctrlbit        = (1 << 24),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_csis",
+                        .devname        = "s5p-mipi-csis.0",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 24),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_csis",
+                        .devname        = "s5p-mipi-csis.1",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 28),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_cam0",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 16),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_cam1",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 20),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .devname        = "exynos4-fimc.0",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 0),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .devname        = "exynos4-fimc.1",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 4),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .devname        = "exynos4-fimc.2",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 8),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimc",
+                        .devname        = "exynos4-fimc.3",
+                        .enable         = exynos4_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 12),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimd",
+                        .devname        = "exynos4-fb.0",
+                        .enable         = exynos4_clksrc_mask_lcd0_ctrl,
+                        .ctrlbit        = (1 << 0),
+                },
+                .sources = &exynos4_clkset_group,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimg2d",
+                },
+                .sources = &exynos4_clkset_mout_g2d,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_mfc",
+                        .devname        = "s5p-mfc",
+                },
+                .sources = &exynos4_clkset_mout_mfc,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_dwmmc",
+                        .parent         = &exynos4_clk_dout_mmc4.clk,
+                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                        .ctrlbit        = (1 << 16),
+                },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+        }
+};
+static struct clksrc_clk exynos4_clk_sclk_uart0 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.0",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
+};
+static struct clksrc_clk exynos4_clk_sclk_uart1 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.1",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 4),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
+};
+static struct clksrc_clk exynos4_clk_sclk_uart2 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.2",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
+};
+static struct clksrc_clk exynos4_clk_sclk_uart3 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.3",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 12),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
+};
+static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.0",
+                .parent         = &exynos4_clk_dout_mmc0.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+};
+static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.1",
+                .parent         = &exynos4_clk_dout_mmc1.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 4),
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+};
+static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.2",
+                .parent         = &exynos4_clk_dout_mmc2.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+};
+static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.3",
+                .parent         = &exynos4_clk_dout_mmc3.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 12),
+        },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+};
+static struct clksrc_clk exynos4_clk_sclk_spi0 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.0",
+                .enable         = exynos4_clksrc_mask_peril1_ctrl,
+                .ctrlbit        = (1 << 16),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+};
+static struct clksrc_clk exynos4_clk_sclk_spi1 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.1",
+                .enable         = exynos4_clksrc_mask_peril1_ctrl,
+                .ctrlbit        = (1 << 20),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+};
+static struct clksrc_clk exynos4_clk_sclk_spi2 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.2",
+                .enable         = exynos4_clksrc_mask_peril1_ctrl,
+                .ctrlbit        = (1 << 24),
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+};
+/* Clock initialization code */
+static struct clksrc_clk *exynos4_sysclks[] = {
+        &exynos4_clk_mout_apll,
+        &exynos4_clk_sclk_apll,
+        &exynos4_clk_mout_epll,
+        &exynos4_clk_mout_mpll,
+        &exynos4_clk_moutcore,
+        &exynos4_clk_coreclk,
+        &exynos4_clk_armclk,
+        &exynos4_clk_aclk_corem0,
+        &exynos4_clk_aclk_cores,
+        &exynos4_clk_aclk_corem1,
+        &exynos4_clk_periphclk,
+        &exynos4_clk_mout_corebus,
+        &exynos4_clk_sclk_dmc,
+        &exynos4_clk_aclk_cored,
+        &exynos4_clk_aclk_corep,
+        &exynos4_clk_aclk_acp,
+        &exynos4_clk_pclk_acp,
+        &exynos4_clk_vpllsrc,
+        &exynos4_clk_sclk_vpll,
+        &exynos4_clk_aclk_200,
+        &exynos4_clk_aclk_100,
+        &exynos4_clk_aclk_160,
+        &exynos4_clk_aclk_133,
+        &exynos4_clk_dout_mmc0,
+        &exynos4_clk_dout_mmc1,
+        &exynos4_clk_dout_mmc2,
+        &exynos4_clk_dout_mmc3,
+        &exynos4_clk_dout_mmc4,
+        &exynos4_clk_mout_mfc0,
+        &exynos4_clk_mout_mfc1,
+};
+static struct clk *exynos4_clk_cdev[] = {
+        &exynos4_clk_pdma0,
+        &exynos4_clk_pdma1,
+};
+static struct clksrc_clk *exynos4_clksrc_cdev[] = {
+        &exynos4_clk_sclk_uart0,
+        &exynos4_clk_sclk_uart1,
+        &exynos4_clk_sclk_uart2,
+        &exynos4_clk_sclk_uart3,
+        &exynos4_clk_sclk_mmc0,
+        &exynos4_clk_sclk_mmc1,
+        &exynos4_clk_sclk_mmc2,
+        &exynos4_clk_sclk_mmc3,
+        &exynos4_clk_sclk_spi0,
+        &exynos4_clk_sclk_spi1,
+        &exynos4_clk_sclk_spi2,
+};
+static struct clk_lookup exynos4_clk_lookup[] = {
+        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
+        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
+        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
+        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
+        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
+        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
+        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
+        CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
+};
+static int xtal_rate;
+static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
+{
+        if (soc_is_exynos4210())
+                return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
+                                        pll_4508);
+        else if (soc_is_exynos4212() || soc_is_exynos4412())
+                return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
+        else
+                return 0;
+}
+static struct clk_ops exynos4_fout_apll_ops = {
+        .get_rate = exynos4_fout_apll_get_rate,
+};
+static u32 exynos4_vpll_div[][8] = {
+        {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
+        { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
+};
+static unsigned long exynos4_vpll_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int vpll_con0, vpll_con1 = 0;
+        unsigned int i;
+        /* Return if nothing changed */
+        if (clk->rate == rate)
+                return 0;
+        vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
+        vpll_con0 &= ~(0x1 << 27 |                                      \
+                        PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
+                        PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
+                        PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+        vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
+        vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
+                        PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
+                        PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
+        for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
+                if (exynos4_vpll_div[i][0] == rate) {
+                        vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
+                        vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
+                        vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
+                        vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
+                        vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
+                        vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
+                        vpll_con0 |= exynos4_vpll_div[i][7] << 27;
+                        break;
+                }
+        }
+        if (i == ARRAY_SIZE(exynos4_vpll_div)) {
+                printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
+                                __func__);
+                return -EINVAL;
+        }
+        __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
+        __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
+        /* Wait for VPLL lock */
+        while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
+                continue;
+        clk->rate = rate;
+        return 0;
+}
+static struct clk_ops exynos4_vpll_ops = {
+        .get_rate = exynos4_vpll_get_rate,
+        .set_rate = exynos4_vpll_set_rate,
+};
+void __init_or_cpufreq exynos4_setup_clocks(void)
+{
+        struct clk *xtal_clk;
+        unsigned long apll = 0;
+        unsigned long mpll = 0;
+        unsigned long epll = 0;
+        unsigned long vpll = 0;
+        unsigned long vpllsrc;
+        unsigned long xtal;
+        unsigned long armclk;
+        unsigned long sclk_dmc;
+        unsigned long aclk_200;
+        unsigned long aclk_100;
+        unsigned long aclk_160;
+        unsigned long aclk_133;
+        unsigned int ptr;
+        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+        xtal_clk = clk_get(NULL, "xtal");
+        BUG_ON(IS_ERR(xtal_clk));
+        xtal = clk_get_rate(xtal_clk);
+        xtal_rate = xtal;
+        clk_put(xtal_clk);
+        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+        if (soc_is_exynos4210()) {
+                apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
+                                        pll_4508);
+                mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
+                                        pll_4508);
+                epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
+                                        __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
+                vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
+                vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
+                                        __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
+        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+                apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
+                mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
+                epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
+                                        __raw_readl(EXYNOS4_EPLL_CON1));
+                vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
+                vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
+                                        __raw_readl(EXYNOS4_VPLL_CON1));
+        } else {
+                /* nothing */
+        }
+        clk_fout_apll.ops = &exynos4_fout_apll_ops;
+        clk_fout_mpll.rate = mpll;
+        clk_fout_epll.rate = epll;
+        clk_fout_vpll.ops = &exynos4_vpll_ops;
+        clk_fout_vpll.rate = vpll;
+        printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
+                        apll, mpll, epll, vpll);
+        armclk = clk_get_rate(&exynos4_clk_armclk.clk);
+        sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
+        aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
+        aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
+        aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
+        aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
+        printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
+                         "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
+                        armclk, sclk_dmc, aclk_200,
+                        aclk_100, aclk_160, aclk_133);
+        clk_f.rate = armclk;
+        clk_h.rate = sclk_dmc;
+        clk_p.rate = aclk_100;
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
+                s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
+}
+static struct clk *exynos4_clks[] __initdata = {
+        &exynos4_clk_sclk_hdmi27m,
+        &exynos4_clk_sclk_hdmiphy,
+        &exynos4_clk_sclk_usbphy0,
+        &exynos4_clk_sclk_usbphy1,
+};
+#ifdef CONFIG_PM_SLEEP
+static int exynos4_clock_suspend(void)
+{
+        s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+        return 0;
+}
+static void exynos4_clock_resume(void)
+{
+        s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+}
+#else
+#define exynos4_clock_suspend NULL
+#define exynos4_clock_resume NULL
+#endif
+static struct syscore_ops exynos4_clock_syscore_ops = {
+        .suspend        = exynos4_clock_suspend,
+        .resume         = exynos4_clock_resume,
+};
+void __init exynos4_register_clocks(void)
+{
+        int ptr;
+        s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
+                s3c_register_clksrc(exynos4_sysclks[ptr], 1);
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
+                s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
+                s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
+        s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
+        s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
+        s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
+        for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
+                s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
+        s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
+        s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
+        clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
+        register_syscore_ops(&exynos4_clock_syscore_ops);
+        s3c24xx_register_clock(&dummy_apb_pclk);
+        s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
new file mode 100644
index 000000000000..cb71c29c14d1
--- /dev/null
+++ b/arch/arm/mach-exynos/clock-exynos4.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Header file for exynos4 clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H __FILE__
+#include <linux/clk.h>
+extern struct clksrc_clk exynos4_clk_aclk_133;
+extern struct clksrc_clk exynos4_clk_mout_mpll;
+extern struct clksrc_sources exynos4_clkset_mout_corebus;
+extern struct clksrc_sources exynos4_clkset_group;
+extern struct clk *exynos4_clkset_aclk_top_list[];
+extern struct clk *exynos4_clkset_group_list[];
+extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index 54a92efcf5b1..3b131e4b6ef5 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -1,7 +1,5 @@
 /*
- * linux/arch/arm/mach-exynos4/clock-exynos4210.c
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *              http://www.samsung.com
 *
 * EXYNOS4210 - Clock support
@@ -28,20 +26,20 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/exynos4-clock.h>
 #include "common.h"
+#include "clock-exynos4.h"
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos4210_clock_save[] = {
-        SAVE_ITEM(S5P_CLKSRC_IMAGE),
+        SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
-        SAVE_ITEM(S5P_CLKSRC_LCD1),
+        SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
-        SAVE_ITEM(S5P_CLKDIV_IMAGE),
+        SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
-        SAVE_ITEM(S5P_CLKDIV_LCD1),
+        SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
-        SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
+        SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
-        SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
+        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
-        SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
+        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
-        SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
+        SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
 };
 #endif
@@ -51,7 +49,7 @@ static struct clksrc_clk *sysclks[] = {
 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
 {
-        return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
+        return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
 }
 static struct clksrc_clk clksrcs[] = {
@@ -62,9 +60,9 @@ static struct clksrc_clk clksrcs[] = {
                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
                        .ctrlbit        = (1 << 24),
                },
-                .sources = &clkset_mout_corebus,
+                .sources = &exynos4_clkset_mout_corebus,
-                .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
+                .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
-                .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
        }, {
                .clk            = {
                        .name           = "sclk_fimd",
@@ -72,9 +70,9 @@ static struct clksrc_clk clksrcs[] = {
                        .enable         = exynos4_clksrc_mask_lcd1_ctrl,
                        .ctrlbit        = (1 << 0),
                },
-                .sources = &clkset_group,
+                .sources = &exynos4_clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
+                .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
+                .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
        },
 };
@@ -82,13 +80,13 @@ static struct clk init_clocks_off[] = {
        {
                .name           = "sataphy",
                .id             = -1,
-                .parent         = &clk_aclk_133.clk,
+                .parent         = &exynos4_clk_aclk_133.clk,
                .enable         = exynos4_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 3),
        }, {
                .name           = "sata",
                .id             = -1,
-                .parent         = &clk_aclk_133.clk,
+                .parent         = &exynos4_clk_aclk_133.clk,
                .enable         = exynos4_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 10),
        }, {
@@ -126,9 +124,9 @@ void __init exynos4210_register_clocks(void)
 {
        int ptr;
-        clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
+        exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
-        clk_mout_mpll.reg_src.shift = 8;
+        exynos4_clk_mout_mpll.reg_src.shift = 8;
-        clk_mout_mpll.reg_src.size = 1;
+        exynos4_clk_mout_mpll.reg_src.size = 1;
        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
                s3c_register_clksrc(sysclks[ptr], 1);
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 8e07ab13ff19..3ecc01e06f74 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -1,7 +1,5 @@
 /*
- * linux/arch/arm/mach-exynos4/clock-exynos4212.c
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *              http://www.samsung.com
 *
 * EXYNOS4212 - Clock support
@@ -28,22 +26,22 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
-#include <mach/exynos4-clock.h>
 #include "common.h"
+#include "clock-exynos4.h"
 #ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos4212_clock_save[] = {
-        SAVE_ITEM(S5P_CLKSRC_IMAGE),
+        SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
-        SAVE_ITEM(S5P_CLKDIV_IMAGE),
+        SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
-        SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
+        SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
-        SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
+        SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
 };
 #endif
 static struct clk *clk_src_mpll_user_list[] = {
        [0] = &clk_fin_mpll,
-        [1] = &clk_mout_mpll.clk,
+        [1] = &exynos4_clk_mout_mpll.clk,
 };
 static struct clksrc_sources clk_src_mpll_user = {
@@ -56,7 +54,7 @@ static struct clksrc_clk clk_mout_mpll_user = {
                .name           = "mout_mpll_user",
        },
        .sources        = &clk_src_mpll_user,
-        .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
+        .reg_src        = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
 };
 static struct clksrc_clk *sysclks[] = {
@@ -99,15 +97,15 @@ void __init exynos4212_register_clocks(void)
        int ptr;
        /* usbphy1 is removed */
-        clkset_group_list[4] = NULL;
+        exynos4_clkset_group_list[4] = NULL;
        /* mout_mpll_user is used */
-        clkset_group_list[6] = &clk_mout_mpll_user.clk;
+        exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
-        clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
+        exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
-        clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
+        exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
-        clk_mout_mpll.reg_src.shift = 12;
+        exynos4_clk_mout_mpll.reg_src.shift = 12;
-        clk_mout_mpll.reg_src.size = 1;
+        exynos4_clk_mout_mpll.reg_src.size = 1;
        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
                s3c_register_clksrc(sysclks[ptr], 1);
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
deleted file mode 100644
index 200874e82dcd..000000000000
--- a/arch/arm/mach-exynos/clock.c
+++ /dev/null
@@ -1,1564 +0,0 @@
-/* linux/arch/arm/mach-exynos4/clock.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/syscore_ops.h>
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/pm.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/sysmmu.h>
-#include <mach/exynos4-clock.h>
-#include "common.h"
-#ifdef CONFIG_PM_SLEEP
-static struct sleep_save exynos4_clock_save[] = {
-        SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
-        SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
-        SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
-        SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
-        SAVE_ITEM(S5P_CLKSRC_TOP0),
-        SAVE_ITEM(S5P_CLKSRC_TOP1),
-        SAVE_ITEM(S5P_CLKSRC_CAM),
-        SAVE_ITEM(S5P_CLKSRC_TV),
-        SAVE_ITEM(S5P_CLKSRC_MFC),
-        SAVE_ITEM(S5P_CLKSRC_G3D),
-        SAVE_ITEM(S5P_CLKSRC_LCD0),
-        SAVE_ITEM(S5P_CLKSRC_MAUDIO),
-        SAVE_ITEM(S5P_CLKSRC_FSYS),
-        SAVE_ITEM(S5P_CLKSRC_PERIL0),
-        SAVE_ITEM(S5P_CLKSRC_PERIL1),
-        SAVE_ITEM(S5P_CLKDIV_CAM),
-        SAVE_ITEM(S5P_CLKDIV_TV),
-        SAVE_ITEM(S5P_CLKDIV_MFC),
-        SAVE_ITEM(S5P_CLKDIV_G3D),
-        SAVE_ITEM(S5P_CLKDIV_LCD0),
-        SAVE_ITEM(S5P_CLKDIV_MAUDIO),
-        SAVE_ITEM(S5P_CLKDIV_FSYS0),
-        SAVE_ITEM(S5P_CLKDIV_FSYS1),
-        SAVE_ITEM(S5P_CLKDIV_FSYS2),
-        SAVE_ITEM(S5P_CLKDIV_FSYS3),
-        SAVE_ITEM(S5P_CLKDIV_PERIL0),
-        SAVE_ITEM(S5P_CLKDIV_PERIL1),
-        SAVE_ITEM(S5P_CLKDIV_PERIL2),
-        SAVE_ITEM(S5P_CLKDIV_PERIL3),
-        SAVE_ITEM(S5P_CLKDIV_PERIL4),
-        SAVE_ITEM(S5P_CLKDIV_PERIL5),
-        SAVE_ITEM(S5P_CLKDIV_TOP),
-        SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
-        SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
-        SAVE_ITEM(S5P_CLKSRC_MASK_TV),
-        SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
-        SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
-        SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
-        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
-        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
-        SAVE_ITEM(S5P_CLKDIV2_RATIO),
-        SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
-        SAVE_ITEM(S5P_CLKGATE_IP_CAM),
-        SAVE_ITEM(S5P_CLKGATE_IP_TV),
-        SAVE_ITEM(S5P_CLKGATE_IP_MFC),
-        SAVE_ITEM(S5P_CLKGATE_IP_G3D),
-        SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
-        SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
-        SAVE_ITEM(S5P_CLKGATE_IP_GPS),
-        SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
-        SAVE_ITEM(S5P_CLKGATE_BLOCK),
-        SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
-        SAVE_ITEM(S5P_CLKSRC_DMC),
-        SAVE_ITEM(S5P_CLKDIV_DMC0),
-        SAVE_ITEM(S5P_CLKDIV_DMC1),
-        SAVE_ITEM(S5P_CLKGATE_IP_DMC),
-        SAVE_ITEM(S5P_CLKSRC_CPU),
-        SAVE_ITEM(S5P_CLKDIV_CPU),
-        SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
-        SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
-        SAVE_ITEM(S5P_CLKGATE_IP_CPU),
-};
-#endif
-struct clk clk_sclk_hdmi27m = {
-        .name           = "sclk_hdmi27m",
-        .rate           = 27000000,
-};
-struct clk clk_sclk_hdmiphy = {
-        .name           = "sclk_hdmiphy",
-};
-struct clk clk_sclk_usbphy0 = {
-        .name           = "sclk_usbphy0",
-        .rate           = 27000000,
-};
-struct clk clk_sclk_usbphy1 = {
-        .name           = "sclk_usbphy1",
-};
-static struct clk dummy_apb_pclk = {
-        .name           = "apb_pclk",
-        .id             = -1,
-};
-static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
-}
-static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
-}
-static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
-}
-int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
-}
-static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
-}
-static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
-}
-static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
-}
-static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
-}
-static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
-}
-static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
-}
-static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
-}
-static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
-}
-int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
-}
-int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
-}
-static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
-}
-static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
-}
-static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
-}
-static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
-}
-/* Core list of CMU_CPU side */
-static struct clksrc_clk clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-        },
-        .sources        = &clk_src_apll,
-        .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
-};
-struct clksrc_clk clk_sclk_apll = {
-        .clk    = {
-                .name           = "sclk_apll",
-                .parent         = &clk_mout_apll.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
-};
-struct clksrc_clk clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-        },
-        .sources        = &clk_src_epll,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
-};
-struct clksrc_clk clk_mout_mpll = {
-        .clk = {
-                .name           = "mout_mpll",
-        },
-        .sources        = &clk_src_mpll,
-        /* reg_src will be added in each SoCs' clock */
-};
-static struct clk *clkset_moutcore_list[] = {
-        [0] = &clk_mout_apll.clk,
-        [1] = &clk_mout_mpll.clk,
-};
-static struct clksrc_sources clkset_moutcore = {
-        .sources        = clkset_moutcore_list,
-        .nr_sources     = ARRAY_SIZE(clkset_moutcore_list),
-};
-static struct clksrc_clk clk_moutcore = {
-        .clk    = {
-                .name           = "moutcore",
-        },
-        .sources        = &clkset_moutcore,
-        .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
-};
-static struct clksrc_clk clk_coreclk = {
-        .clk    = {
-                .name           = "core_clk",
-                .parent         = &clk_moutcore.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
-};
-static struct clksrc_clk clk_armclk = {
-        .clk    = {
-                .name           = "armclk",
-                .parent         = &clk_coreclk.clk,
-        },
-};
-static struct clksrc_clk clk_aclk_corem0 = {
-        .clk    = {
-                .name           = "aclk_corem0",
-                .parent         = &clk_coreclk.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-static struct clksrc_clk clk_aclk_cores = {
-        .clk    = {
-                .name           = "aclk_cores",
-                .parent         = &clk_coreclk.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
-};
-static struct clksrc_clk clk_aclk_corem1 = {
-        .clk    = {
-                .name           = "aclk_corem1",
-                .parent         = &clk_coreclk.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
-};
-static struct clksrc_clk clk_periphclk = {
-        .clk    = {
-                .name           = "periphclk",
-                .parent         = &clk_coreclk.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
-};
-/* Core list of CMU_CORE side */
-struct clk *clkset_corebus_list[] = {
-        [0] = &clk_mout_mpll.clk,
-        [1] = &clk_sclk_apll.clk,
-};
-struct clksrc_sources clkset_mout_corebus = {
-        .sources        = clkset_corebus_list,
-        .nr_sources     = ARRAY_SIZE(clkset_corebus_list),
-};
-static struct clksrc_clk clk_mout_corebus = {
-        .clk    = {
-                .name           = "mout_corebus",
-        },
-        .sources        = &clkset_mout_corebus,
-        .reg_src        = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
-};
-static struct clksrc_clk clk_sclk_dmc = {
-        .clk    = {
-                .name           = "sclk_dmc",
-                .parent         = &clk_mout_corebus.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
-};
-static struct clksrc_clk clk_aclk_cored = {
-        .clk    = {
-                .name           = "aclk_cored",
-                .parent         = &clk_sclk_dmc.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
-};
-static struct clksrc_clk clk_aclk_corep = {
-        .clk    = {
-                .name           = "aclk_corep",
-                .parent         = &clk_aclk_cored.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
-};
-static struct clksrc_clk clk_aclk_acp = {
-        .clk    = {
-                .name           = "aclk_acp",
-                .parent         = &clk_mout_corebus.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
-};
-static struct clksrc_clk clk_pclk_acp = {
-        .clk    = {
-                .name           = "pclk_acp",
-                .parent         = &clk_aclk_acp.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
-};
-/* Core list of CMU_TOP side */
-struct clk *clkset_aclk_top_list[] = {
-        [0] = &clk_mout_mpll.clk,
-        [1] = &clk_sclk_apll.clk,
-};
-struct clksrc_sources clkset_aclk = {
-        .sources        = clkset_aclk_top_list,
-        .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
-};
-static struct clksrc_clk clk_aclk_200 = {
-        .clk    = {
-                .name           = "aclk_200",
-        },
-        .sources        = &clkset_aclk,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
-        .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
-};
-static struct clksrc_clk clk_aclk_100 = {
-        .clk    = {
-                .name           = "aclk_100",
-        },
-        .sources        = &clkset_aclk,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
-        .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
-};
-static struct clksrc_clk clk_aclk_160 = {
-        .clk    = {
-                .name           = "aclk_160",
-        },
-        .sources        = &clkset_aclk,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
-        .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
-};
-struct clksrc_clk clk_aclk_133 = {
-        .clk    = {
-                .name           = "aclk_133",
-        },
-        .sources        = &clkset_aclk,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
-        .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
-};
-static struct clk *clkset_vpllsrc_list[] = {
-        [0] = &clk_fin_vpll,
-        [1] = &clk_sclk_hdmi27m,
-};
-static struct clksrc_sources clkset_vpllsrc = {
-        .sources        = clkset_vpllsrc_list,
-        .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
-};
-static struct clksrc_clk clk_vpllsrc = {
-        .clk    = {
-                .name           = "vpll_src",
-                .enable         = exynos4_clksrc_mask_top_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources        = &clkset_vpllsrc,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
-};
-static struct clk *clkset_sclk_vpll_list[] = {
-        [0] = &clk_vpllsrc.clk,
-        [1] = &clk_fout_vpll,
-};
-static struct clksrc_sources clkset_sclk_vpll = {
-        .sources        = clkset_sclk_vpll_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
-};
-struct clksrc_clk clk_sclk_vpll = {
-        .clk    = {
-                .name           = "sclk_vpll",
-        },
-        .sources        = &clkset_sclk_vpll,
-        .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
-};
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "timers",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1<<24),
-        }, {
-                .name           = "csis",
-                .devname        = "s5p-mipi-csis.0",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "csis",
-                .devname        = "s5p-mipi-csis.1",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.0",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.1",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.2",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "fimc",
-                .devname        = "exynos4-fimc.3",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "fimd",
-                .devname        = "exynos4-fb.0",
-                .enable         = exynos4_clk_ip_lcd0_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.3",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "dwmmc",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "dac",
-                .devname        = "s5p-sdo",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "mixer",
-                .devname        = "s5p-mixer",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "vp",
-                .devname        = "s5p-mixer",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "hdmi",
-                .devname        = "exynos4-hdmi",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "hdmiphy",
-                .devname        = "exynos4-hdmi",
-                .enable         = exynos4_clk_hdmiphy_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "dacphy",
-                .devname        = "s5p-sdo",
-                .enable         = exynos4_clk_dac_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "adc",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "keypad",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "rtc",
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 15),
-        }, {
-                .name           = "watchdog",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_perir_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "usbhost",
-                .enable         = exynos4_clk_ip_fsys_ctrl ,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "otg",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "spi",
-                .devname        = "s3c64xx-spi.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 16),
-        }, {
-                .name           = "spi",
-                .devname        = "s3c64xx-spi.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 17),
-        }, {
-                .name           = "spi",
-                .devname        = "s3c64xx-spi.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 19),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 20),
-        }, {
-                .name           = "iis",
-                .devname        = "samsung-i2s.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 21),
-        }, {
-                .name           = "ac97",
-                .devname        = "samsung-ac97",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 27),
-        }, {
-                .name           = "fimg2d",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "mfc",
-                .devname        = "s5p-mfc",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.0",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.1",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.2",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.3",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.4",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.5",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.6",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-i2c.7",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 13),
-        }, {
-                .name           = "i2c",
-                .devname        = "s3c2440-hdmiphy-i2c",
-                .parent         = &clk_aclk_100.clk,
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 14),
-        }, {
-                .name           = "SYSMMU_MDMA",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
-                .name           = "SYSMMU_FIMC0",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "SYSMMU_FIMC1",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "SYSMMU_FIMC2",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
-                .name           = "SYSMMU_FIMC3",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
-                .name           = "SYSMMU_JPEG",
-                .enable         = exynos4_clk_ip_cam_ctrl,
-                .ctrlbit        = (1 << 11),
-        }, {
-                .name           = "SYSMMU_FIMD0",
-                .enable         = exynos4_clk_ip_lcd0_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "SYSMMU_FIMD1",
-                .enable         = exynos4_clk_ip_lcd1_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "SYSMMU_PCIe",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 18),
-        }, {
-                .name           = "SYSMMU_G2D",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "SYSMMU_ROTATOR",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "SYSMMU_TV",
-                .enable         = exynos4_clk_ip_tv_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "SYSMMU_MFC_L",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "SYSMMU_MFC_R",
-                .enable         = exynos4_clk_ip_mfc_ctrl,
-                .ctrlbit        = (1 << 2),
-        }
-};
-static struct clk init_clocks[] = {
-        {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.0",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.1",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.2",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 2),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.3",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.4",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 4),
-        }, {
-                .name           = "uart",
-                .devname        = "s5pv210-uart.5",
-                .enable         = exynos4_clk_ip_peril_ctrl,
-                .ctrlbit        = (1 << 5),
-        }
-};
-static struct clk clk_pdma0 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.0",
-        .enable         = exynos4_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 0),
-};
-static struct clk clk_pdma1 = {
-        .name           = "dma",
-        .devname        = "dma-pl330.1",
-        .enable         = exynos4_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 1),
-};
-struct clk *clkset_group_list[] = {
-        [0] = &clk_ext_xtal_mux,
-        [1] = &clk_xusbxti,
-        [2] = &clk_sclk_hdmi27m,
-        [3] = &clk_sclk_usbphy0,
-        [4] = &clk_sclk_usbphy1,
-        [5] = &clk_sclk_hdmiphy,
-        [6] = &clk_mout_mpll.clk,
-        [7] = &clk_mout_epll.clk,
-        [8] = &clk_sclk_vpll.clk,
-};
-struct clksrc_sources clkset_group = {
-        .sources        = clkset_group_list,
-        .nr_sources     = ARRAY_SIZE(clkset_group_list),
-};
-static struct clk *clkset_mout_g2d0_list[] = {
-        [0] = &clk_mout_mpll.clk,
-        [1] = &clk_sclk_apll.clk,
-};
-static struct clksrc_sources clkset_mout_g2d0 = {
-        .sources        = clkset_mout_g2d0_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mout_g2d0_list),
-};
-static struct clksrc_clk clk_mout_g2d0 = {
-        .clk    = {
-                .name           = "mout_g2d0",
-        },
-        .sources        = &clkset_mout_g2d0,
-        .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
-};
-static struct clk *clkset_mout_g2d1_list[] = {
-        [0] = &clk_mout_epll.clk,
-        [1] = &clk_sclk_vpll.clk,
-};
-static struct clksrc_sources clkset_mout_g2d1 = {
-        .sources        = clkset_mout_g2d1_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mout_g2d1_list),
-};
-static struct clksrc_clk clk_mout_g2d1 = {
-        .clk    = {
-                .name           = "mout_g2d1",
-        },
-        .sources        = &clkset_mout_g2d1,
-        .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
-};
-static struct clk *clkset_mout_g2d_list[] = {
-        [0] = &clk_mout_g2d0.clk,
-        [1] = &clk_mout_g2d1.clk,
-};
-static struct clksrc_sources clkset_mout_g2d = {
-        .sources        = clkset_mout_g2d_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mout_g2d_list),
-};
-static struct clk *clkset_mout_mfc0_list[] = {
-        [0] = &clk_mout_mpll.clk,
-        [1] = &clk_sclk_apll.clk,
-};
-static struct clksrc_sources clkset_mout_mfc0 = {
-        .sources        = clkset_mout_mfc0_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mout_mfc0_list),
-};
-static struct clksrc_clk clk_mout_mfc0 = {
-        .clk    = {
-                .name           = "mout_mfc0",
-        },
-        .sources        = &clkset_mout_mfc0,
-        .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
-};
-static struct clk *clkset_mout_mfc1_list[] = {
-        [0] = &clk_mout_epll.clk,
-        [1] = &clk_sclk_vpll.clk,
-};
-static struct clksrc_sources clkset_mout_mfc1 = {
-        .sources        = clkset_mout_mfc1_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mout_mfc1_list),
-};
-static struct clksrc_clk clk_mout_mfc1 = {
-        .clk    = {
-                .name           = "mout_mfc1",
-        },
-        .sources        = &clkset_mout_mfc1,
-        .reg_src        = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
-};
-static struct clk *clkset_mout_mfc_list[] = {
-        [0] = &clk_mout_mfc0.clk,
-        [1] = &clk_mout_mfc1.clk,
-};
-static struct clksrc_sources clkset_mout_mfc = {
-        .sources        = clkset_mout_mfc_list,
-        .nr_sources     = ARRAY_SIZE(clkset_mout_mfc_list),
-};
-static struct clk *clkset_sclk_dac_list[] = {
-        [0] = &clk_sclk_vpll.clk,
-        [1] = &clk_sclk_hdmiphy,
-};
-static struct clksrc_sources clkset_sclk_dac = {
-        .sources        = clkset_sclk_dac_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
-};
-static struct clksrc_clk clk_sclk_dac = {
-        .clk            = {
-                .name           = "sclk_dac",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &clkset_sclk_dac,
-        .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
-};
-static struct clksrc_clk clk_sclk_pixel = {
-        .clk            = {
-                .name           = "sclk_pixel",
-                .parent = &clk_sclk_vpll.clk,
-        },
-        .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
-};
-static struct clk *clkset_sclk_hdmi_list[] = {
-        [0] = &clk_sclk_pixel.clk,
-        [1] = &clk_sclk_hdmiphy,
-};
-static struct clksrc_sources clkset_sclk_hdmi = {
-        .sources        = clkset_sclk_hdmi_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
-};
-static struct clksrc_clk clk_sclk_hdmi = {
-        .clk            = {
-                .name           = "sclk_hdmi",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &clkset_sclk_hdmi,
-        .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
-};
-static struct clk *clkset_sclk_mixer_list[] = {
-        [0] = &clk_sclk_dac.clk,
-        [1] = &clk_sclk_hdmi.clk,
-};
-static struct clksrc_sources clkset_sclk_mixer = {
-        .sources        = clkset_sclk_mixer_list,
-        .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
-};
-static struct clksrc_clk clk_sclk_mixer = {
-        .clk            = {
-                .name           = "sclk_mixer",
-                .enable         = exynos4_clksrc_mask_tv_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &clkset_sclk_mixer,
-        .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
-};
-static struct clksrc_clk *sclk_tv[] = {
-        &clk_sclk_dac,
-        &clk_sclk_pixel,
-        &clk_sclk_hdmi,
-        &clk_sclk_mixer,
-};
-static struct clksrc_clk clk_dout_mmc0 = {
-        .clk            = {
-                .name           = "dout_mmc0",
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
-};
-static struct clksrc_clk clk_dout_mmc1 = {
-        .clk            = {
-                .name           = "dout_mmc1",
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
-};
-static struct clksrc_clk clk_dout_mmc2 = {
-        .clk            = {
-                .name           = "dout_mmc2",
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
-};
-static struct clksrc_clk clk_dout_mmc3 = {
-        .clk            = {
-                .name           = "dout_mmc3",
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
-};
-static struct clksrc_clk clk_dout_mmc4 = {
-        .clk            = {
-                .name           = "dout_mmc4",
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
-};
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk            = {
-                        .name           = "sclk_pwm",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_csis",
-                        .devname        = "s5p-mipi-csis.0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_csis",
-                        .devname        = "s5p-mipi-csis.1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 28),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_cam0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_cam1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 20),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.0",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.1",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 4),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.2",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 8),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimc",
-                        .devname        = "exynos4-fimc.3",
-                        .enable         = exynos4_clksrc_mask_cam_ctrl,
-                        .ctrlbit        = (1 << 12),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimd",
-                        .devname        = "exynos4-fb.0",
-                        .enable         = exynos4_clksrc_mask_lcd0_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_fimg2d",
-                },
-                .sources = &clkset_mout_g2d,
-                .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
-                .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_mfc",
-                        .devname        = "s5p-mfc",
-                },
-                .sources = &clkset_mout_mfc,
-                .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
-                .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_dwmmc",
-                        .parent         = &clk_dout_mmc4.clk,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
-        }
-};
-static struct clksrc_clk clk_sclk_uart0 = {
-        .clk    = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.0",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
-};
-static struct clksrc_clk clk_sclk_uart1 = {
-        .clk            = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.1",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
-};
-static struct clksrc_clk clk_sclk_uart2 = {
-        .clk            = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.2",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
-};
-static struct clksrc_clk clk_sclk_uart3 = {
-        .clk            = {
-                .name           = "uclk1",
-                .devname        = "exynos4210-uart.3",
-                .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
-};
-static struct clksrc_clk clk_sclk_mmc0 = {
-        .clk            = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_dout_mmc0.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
-};
-static struct clksrc_clk clk_sclk_mmc1 = {
-        .clk            = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_dout_mmc1.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 4),
-        },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
-};
-static struct clksrc_clk clk_sclk_mmc2 = {
-        .clk            = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_dout_mmc2.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 8),
-        },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
-};
-static struct clksrc_clk clk_sclk_mmc3 = {
-        .clk            = {
-                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.3",
-                .parent         = &clk_dout_mmc3.clk,
-                .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                .ctrlbit        = (1 << 12),
-        },
-        .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
-};
-static struct clksrc_clk clk_sclk_spi0 = {
-        .clk            = {
-                .name           = "sclk_spi",
-                .devname                = "s3c64xx-spi.0",
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit                = (1 << 16),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
-};
-static struct clksrc_clk clk_sclk_spi1 = {
-        .clk            = {
-                .name           = "sclk_spi",
-                .devname                = "s3c64xx-spi.1",
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit                = (1 << 20),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
-};
-static struct clksrc_clk clk_sclk_spi2 = {
-        .clk            = {
-                .name           = "sclk_spi",
-                .devname                = "s3c64xx-spi.2",
-                .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                .ctrlbit                = (1 << 24),
-        },
-        .sources = &clkset_group,
-        .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
-        .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
-};
-/* Clock initialization code */
-static struct clksrc_clk *sysclks[] = {
-        &clk_mout_apll,
-        &clk_sclk_apll,
-        &clk_mout_epll,
-        &clk_mout_mpll,
-        &clk_moutcore,
-        &clk_coreclk,
-        &clk_armclk,
-        &clk_aclk_corem0,
-        &clk_aclk_cores,
-        &clk_aclk_corem1,
-        &clk_periphclk,
-        &clk_mout_corebus,
-        &clk_sclk_dmc,
-        &clk_aclk_cored,
-        &clk_aclk_corep,
-        &clk_aclk_acp,
-        &clk_pclk_acp,
-        &clk_vpllsrc,
-        &clk_sclk_vpll,
-        &clk_aclk_200,
-        &clk_aclk_100,
-        &clk_aclk_160,
-        &clk_aclk_133,
-        &clk_dout_mmc0,
-        &clk_dout_mmc1,
-        &clk_dout_mmc2,
-        &clk_dout_mmc3,
-        &clk_dout_mmc4,
-        &clk_mout_mfc0,
-        &clk_mout_mfc1,
-};
-static struct clk *clk_cdev[] = {
-        &clk_pdma0,
-        &clk_pdma1,
-};
-static struct clksrc_clk *clksrc_cdev[] = {
-        &clk_sclk_uart0,
-        &clk_sclk_uart1,
-        &clk_sclk_uart2,
-        &clk_sclk_uart3,
-        &clk_sclk_mmc0,
-        &clk_sclk_mmc1,
-        &clk_sclk_mmc2,
-        &clk_sclk_mmc3,
-        &clk_sclk_spi0,
-        &clk_sclk_spi1,
-        &clk_sclk_spi2,
-};
-static struct clk_lookup exynos4_clk_lookup[] = {
-        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
-        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
-        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
-        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
-        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
-        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
-        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
-        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk),
-        CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk),
-};
-static int xtal_rate;
-static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
-{
-        if (soc_is_exynos4210())
-                return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
-                                        pll_4508);
-        else if (soc_is_exynos4212() || soc_is_exynos4412())
-                return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
-        else
-                return 0;
-}
-static struct clk_ops exynos4_fout_apll_ops = {
-        .get_rate = exynos4_fout_apll_get_rate,
-};
-static u32 vpll_div[][8] = {
-        {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
-        { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
-};
-static unsigned long exynos4_vpll_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned int vpll_con0, vpll_con1 = 0;
-        unsigned int i;
-        /* Return if nothing changed */
-        if (clk->rate == rate)
-                return 0;
-        vpll_con0 = __raw_readl(S5P_VPLL_CON0);
-        vpll_con0 &= ~(0x1 << 27 |                                      \
-                        PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
-                        PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
-                        PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
-        vpll_con1 = __raw_readl(S5P_VPLL_CON1);
-        vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
-                        PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
-                        PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
-        for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
-                if (vpll_div[i][0] == rate) {
-                        vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
-                        vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
-                        vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
-                        vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
-                        vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
-                        vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
-                        vpll_con0 |= vpll_div[i][7] << 27;
-                        break;
-                }
-        }
-        if (i == ARRAY_SIZE(vpll_div)) {
-                printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
-                                __func__);
-                return -EINVAL;
-        }
-        __raw_writel(vpll_con0, S5P_VPLL_CON0);
-        __raw_writel(vpll_con1, S5P_VPLL_CON1);
-        /* Wait for VPLL lock */
-        while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
-                continue;
-        clk->rate = rate;
-        return 0;
-}
-static struct clk_ops exynos4_vpll_ops = {
-        .get_rate = exynos4_vpll_get_rate,
-        .set_rate = exynos4_vpll_set_rate,
-};
-void __init_or_cpufreq exynos4_setup_clocks(void)
-{
-        struct clk *xtal_clk;
-        unsigned long apll = 0;
-        unsigned long mpll = 0;
-        unsigned long epll = 0;
-        unsigned long vpll = 0;
-        unsigned long vpllsrc;
-        unsigned long xtal;
-        unsigned long armclk;
-        unsigned long sclk_dmc;
-        unsigned long aclk_200;
-        unsigned long aclk_100;
-        unsigned long aclk_160;
-        unsigned long aclk_133;
-        unsigned int ptr;
-        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-        xtal_clk = clk_get(NULL, "xtal");
-        BUG_ON(IS_ERR(xtal_clk));
-        xtal = clk_get_rate(xtal_clk);
-        xtal_rate = xtal;
-        clk_put(xtal_clk);
-        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-        if (soc_is_exynos4210()) {
-                apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
-                                        pll_4508);
-                mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
-                                        pll_4508);
-                epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
-                                        __raw_readl(S5P_EPLL_CON1), pll_4600);
-                vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
-                vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
-                                        __raw_readl(S5P_VPLL_CON1), pll_4650c);
-        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-                apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
-                mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
-                epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
-                                        __raw_readl(S5P_EPLL_CON1));
-                vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
-                vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
-                                        __raw_readl(S5P_VPLL_CON1));
-        } else {
-                /* nothing */
-        }
-        clk_fout_apll.ops = &exynos4_fout_apll_ops;
-        clk_fout_mpll.rate = mpll;
-        clk_fout_epll.rate = epll;
-        clk_fout_vpll.ops = &exynos4_vpll_ops;
-        clk_fout_vpll.rate = vpll;
-        printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
-                        apll, mpll, epll, vpll);
-        armclk = clk_get_rate(&clk_armclk.clk);
-        sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
-        aclk_200 = clk_get_rate(&clk_aclk_200.clk);
-        aclk_100 = clk_get_rate(&clk_aclk_100.clk);
-        aclk_160 = clk_get_rate(&clk_aclk_160.clk);
-        aclk_133 = clk_get_rate(&clk_aclk_133.clk);
-        printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
-                         "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
-                        armclk, sclk_dmc, aclk_200,
-                        aclk_100, aclk_160, aclk_133);
-        clk_f.rate = armclk;
-        clk_h.rate = sclk_dmc;
-        clk_p.rate = aclk_100;
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-                s3c_set_clksrc(&clksrcs[ptr], true);
-}
-static struct clk *clks[] __initdata = {
-        &clk_sclk_hdmi27m,
-        &clk_sclk_hdmiphy,
-        &clk_sclk_usbphy0,
-        &clk_sclk_usbphy1,
-};
-#ifdef CONFIG_PM_SLEEP
-static int exynos4_clock_suspend(void)
-{
-        s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-        return 0;
-}
-static void exynos4_clock_resume(void)
-{
-        s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
-}
-#else
-#define exynos4_clock_suspend NULL
-#define exynos4_clock_resume NULL
-#endif
-static struct syscore_ops exynos4_clock_syscore_ops = {
-        .suspend        = exynos4_clock_suspend,
-        .resume         = exynos4_clock_resume,
-};
-void __init exynos4_register_clocks(void)
-{
-        int ptr;
-        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-        for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
-                s3c_register_clksrc(sysclks[ptr], 1);
-        for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
-                s3c_register_clksrc(sclk_tv[ptr], 1);
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
-                s3c_register_clksrc(clksrc_cdev[ptr], 1);
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
-        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
-        for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
-                s3c_disable_clocks(clk_cdev[ptr], 1);
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
-        register_syscore_ops(&exynos4_clock_syscore_ops);
-        s3c24xx_register_clock(&dummy_apb_pclk);
-        s3c_pwmclk_init();
-}
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 1ac49de0f398..8c1efe692c20 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -15,12 +15,21 @@
 void exynos_init_io(struct map_desc *mach_desc, int size);
 void exynos4_init_irq(void);
+#ifdef CONFIG_ARCH_EXYNOS4
 void exynos4_register_clocks(void);
 void exynos4_setup_clocks(void);
 void exynos4210_register_clocks(void);
 void exynos4212_register_clocks(void);
+#else
+#define exynos4_register_clocks()
+#define exynos4_setup_clocks()
+#define exynos4210_register_clocks()
+#define exynos4212_register_clocks()
+#endif
 void exynos4_restart(char mode, const char *cmd);
 extern struct sys_timer exynos4_timer;
diff --git a/arch/arm/mach-exynos/include/mach/exynos4-clock.h b/arch/arm/mach-exynos/include/mach/exynos4-clock.h
deleted file mode 100644
index a07fcbf55251..000000000000
--- a/arch/arm/mach-exynos/include/mach/exynos4-clock.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Header file for exynos4 clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H __FILE__
-#include <linux/clk.h>
-extern struct clk clk_sclk_hdmi27m;
-extern struct clk clk_sclk_usbphy0;
-extern struct clk clk_sclk_usbphy1;
-extern struct clk clk_sclk_hdmiphy;
-extern struct clksrc_clk clk_sclk_apll;
-extern struct clksrc_clk clk_mout_mpll;
-extern struct clksrc_clk clk_aclk_133;
-extern struct clksrc_clk clk_mout_epll;
-extern struct clksrc_clk clk_sclk_vpll;
-extern struct clk *clkset_corebus_list[];
-extern struct clksrc_sources clkset_mout_corebus;
-extern struct clk *clkset_aclk_top_list[];
-extern struct clksrc_sources clkset_aclk;
-extern struct clk *clkset_group_list[];
-extern struct clksrc_sources clkset_group;
-extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
-extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
-#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 6c37ebe94829..1e4abd64a547 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -16,195 +16,247 @@
 #include <plat/cpu.h>
 #include <mach/map.h>
-#define S5P_CLKREG(x)                   (S5P_VA_CMU + (x))
+#define EXYNOS_CLKREG(x)                        (S5P_VA_CMU + (x))
-#define S5P_CLKDIV_LEFTBUS              S5P_CLKREG(0x04500)
+#define EXYNOS4_CLKDIV_LEFTBUS                  EXYNOS_CLKREG(0x04500)
-#define S5P_CLKDIV_STAT_LEFTBUS         S5P_CLKREG(0x04600)
+#define EXYNOS4_CLKDIV_STAT_LEFTBUS             EXYNOS_CLKREG(0x04600)
-#define S5P_CLKGATE_IP_LEFTBUS          S5P_CLKREG(0x04800)
+#define EXYNOS4_CLKGATE_IP_LEFTBUS              EXYNOS_CLKREG(0x04800)
-#define S5P_CLKDIV_RIGHTBUS             S5P_CLKREG(0x08500)
+#define EXYNOS4_CLKDIV_RIGHTBUS                 EXYNOS_CLKREG(0x08500)
-#define S5P_CLKDIV_STAT_RIGHTBUS        S5P_CLKREG(0x08600)
+#define EXYNOS4_CLKDIV_STAT_RIGHTBUS            EXYNOS_CLKREG(0x08600)
-#define S5P_CLKGATE_IP_RIGHTBUS         S5P_CLKREG(0x08800)
+#define EXYNOS4_CLKGATE_IP_RIGHTBUS             EXYNOS_CLKREG(0x08800)
-#define S5P_EPLL_LOCK                   S5P_CLKREG(0x0C010)
+#define EXYNOS4_EPLL_LOCK                       EXYNOS_CLKREG(0x0C010)
-#define S5P_VPLL_LOCK                   S5P_CLKREG(0x0C020)
+#define EXYNOS4_VPLL_LOCK                       EXYNOS_CLKREG(0x0C020)
-#define S5P_EPLL_CON0                   S5P_CLKREG(0x0C110)
+#define EXYNOS4_EPLL_CON0                       EXYNOS_CLKREG(0x0C110)
-#define S5P_EPLL_CON1                   S5P_CLKREG(0x0C114)
+#define EXYNOS4_EPLL_CON1                       EXYNOS_CLKREG(0x0C114)
-#define S5P_VPLL_CON0                   S5P_CLKREG(0x0C120)
+#define EXYNOS4_VPLL_CON0                       EXYNOS_CLKREG(0x0C120)
-#define S5P_VPLL_CON1                   S5P_CLKREG(0x0C124)
+#define EXYNOS4_VPLL_CON1                       EXYNOS_CLKREG(0x0C124)
-#define S5P_CLKSRC_TOP0                 S5P_CLKREG(0x0C210)
+#define EXYNOS4_CLKSRC_TOP0                     EXYNOS_CLKREG(0x0C210)
-#define S5P_CLKSRC_TOP1                 S5P_CLKREG(0x0C214)
+#define EXYNOS4_CLKSRC_TOP1                     EXYNOS_CLKREG(0x0C214)
-#define S5P_CLKSRC_CAM                  S5P_CLKREG(0x0C220)
+#define EXYNOS4_CLKSRC_CAM                      EXYNOS_CLKREG(0x0C220)
-#define S5P_CLKSRC_TV                   S5P_CLKREG(0x0C224)
+#define EXYNOS4_CLKSRC_TV                       EXYNOS_CLKREG(0x0C224)
-#define S5P_CLKSRC_MFC                  S5P_CLKREG(0x0C228)
+#define EXYNOS4_CLKSRC_MFC                      EXYNOS_CLKREG(0x0C228)
-#define S5P_CLKSRC_G3D                  S5P_CLKREG(0x0C22C)
+#define EXYNOS4_CLKSRC_G3D                      EXYNOS_CLKREG(0x0C22C)
-#define S5P_CLKSRC_IMAGE                S5P_CLKREG(0x0C230)
+#define EXYNOS4_CLKSRC_IMAGE                    EXYNOS_CLKREG(0x0C230)
-#define S5P_CLKSRC_LCD0                 S5P_CLKREG(0x0C234)
+#define EXYNOS4_CLKSRC_LCD0                     EXYNOS_CLKREG(0x0C234)
-#define S5P_CLKSRC_MAUDIO               S5P_CLKREG(0x0C23C)
+#define EXYNOS4_CLKSRC_MAUDIO                   EXYNOS_CLKREG(0x0C23C)
-#define S5P_CLKSRC_FSYS                 S5P_CLKREG(0x0C240)
+#define EXYNOS4_CLKSRC_FSYS                     EXYNOS_CLKREG(0x0C240)
-#define S5P_CLKSRC_PERIL0               S5P_CLKREG(0x0C250)
+#define EXYNOS4_CLKSRC_PERIL0                   EXYNOS_CLKREG(0x0C250)
-#define S5P_CLKSRC_PERIL1               S5P_CLKREG(0x0C254)
+#define EXYNOS4_CLKSRC_PERIL1                   EXYNOS_CLKREG(0x0C254)
-#define S5P_CLKSRC_MASK_TOP             S5P_CLKREG(0x0C310)
+#define EXYNOS4_CLKSRC_MASK_TOP                 EXYNOS_CLKREG(0x0C310)
-#define S5P_CLKSRC_MASK_CAM             S5P_CLKREG(0x0C320)
+#define EXYNOS4_CLKSRC_MASK_CAM                 EXYNOS_CLKREG(0x0C320)
-#define S5P_CLKSRC_MASK_TV              S5P_CLKREG(0x0C324)
+#define EXYNOS4_CLKSRC_MASK_TV                  EXYNOS_CLKREG(0x0C324)
-#define S5P_CLKSRC_MASK_LCD0            S5P_CLKREG(0x0C334)
+#define EXYNOS4_CLKSRC_MASK_LCD0                EXYNOS_CLKREG(0x0C334)
-#define S5P_CLKSRC_MASK_MAUDIO          S5P_CLKREG(0x0C33C)
+#define EXYNOS4_CLKSRC_MASK_MAUDIO              EXYNOS_CLKREG(0x0C33C)
-#define S5P_CLKSRC_MASK_FSYS            S5P_CLKREG(0x0C340)
+#define EXYNOS4_CLKSRC_MASK_FSYS                EXYNOS_CLKREG(0x0C340)
-#define S5P_CLKSRC_MASK_PERIL0          S5P_CLKREG(0x0C350)
+#define EXYNOS4_CLKSRC_MASK_PERIL0              EXYNOS_CLKREG(0x0C350)
-#define S5P_CLKSRC_MASK_PERIL1          S5P_CLKREG(0x0C354)
+#define EXYNOS4_CLKSRC_MASK_PERIL1              EXYNOS_CLKREG(0x0C354)
-#define S5P_CLKDIV_TOP                  S5P_CLKREG(0x0C510)
+#define EXYNOS4_CLKDIV_TOP                      EXYNOS_CLKREG(0x0C510)
-#define S5P_CLKDIV_CAM                  S5P_CLKREG(0x0C520)
+#define EXYNOS4_CLKDIV_CAM                      EXYNOS_CLKREG(0x0C520)
-#define S5P_CLKDIV_TV                   S5P_CLKREG(0x0C524)
+#define EXYNOS4_CLKDIV_TV                       EXYNOS_CLKREG(0x0C524)
-#define S5P_CLKDIV_MFC                  S5P_CLKREG(0x0C528)
+#define EXYNOS4_CLKDIV_MFC                      EXYNOS_CLKREG(0x0C528)
-#define S5P_CLKDIV_G3D                  S5P_CLKREG(0x0C52C)
+#define EXYNOS4_CLKDIV_G3D                      EXYNOS_CLKREG(0x0C52C)
-#define S5P_CLKDIV_IMAGE                S5P_CLKREG(0x0C530)
+#define EXYNOS4_CLKDIV_IMAGE                    EXYNOS_CLKREG(0x0C530)
-#define S5P_CLKDIV_LCD0                 S5P_CLKREG(0x0C534)
+#define EXYNOS4_CLKDIV_LCD0                     EXYNOS_CLKREG(0x0C534)
-#define S5P_CLKDIV_MAUDIO               S5P_CLKREG(0x0C53C)
+#define EXYNOS4_CLKDIV_MAUDIO                   EXYNOS_CLKREG(0x0C53C)
-#define S5P_CLKDIV_FSYS0                S5P_CLKREG(0x0C540)
+#define EXYNOS4_CLKDIV_FSYS0                    EXYNOS_CLKREG(0x0C540)
-#define S5P_CLKDIV_FSYS1                S5P_CLKREG(0x0C544)
+#define EXYNOS4_CLKDIV_FSYS1                    EXYNOS_CLKREG(0x0C544)
-#define S5P_CLKDIV_FSYS2                S5P_CLKREG(0x0C548)
+#define EXYNOS4_CLKDIV_FSYS2                    EXYNOS_CLKREG(0x0C548)
-#define S5P_CLKDIV_FSYS3                S5P_CLKREG(0x0C54C)
+#define EXYNOS4_CLKDIV_FSYS3                    EXYNOS_CLKREG(0x0C54C)
-#define S5P_CLKDIV_PERIL0               S5P_CLKREG(0x0C550)
+#define EXYNOS4_CLKDIV_PERIL0                   EXYNOS_CLKREG(0x0C550)
-#define S5P_CLKDIV_PERIL1               S5P_CLKREG(0x0C554)
+#define EXYNOS4_CLKDIV_PERIL1                   EXYNOS_CLKREG(0x0C554)
-#define S5P_CLKDIV_PERIL2               S5P_CLKREG(0x0C558)
+#define EXYNOS4_CLKDIV_PERIL2                   EXYNOS_CLKREG(0x0C558)
-#define S5P_CLKDIV_PERIL3               S5P_CLKREG(0x0C55C)
+#define EXYNOS4_CLKDIV_PERIL3                   EXYNOS_CLKREG(0x0C55C)
-#define S5P_CLKDIV_PERIL4               S5P_CLKREG(0x0C560)
+#define EXYNOS4_CLKDIV_PERIL4                   EXYNOS_CLKREG(0x0C560)
-#define S5P_CLKDIV_PERIL5               S5P_CLKREG(0x0C564)
+#define EXYNOS4_CLKDIV_PERIL5                   EXYNOS_CLKREG(0x0C564)
-#define S5P_CLKDIV2_RATIO               S5P_CLKREG(0x0C580)
+#define EXYNOS4_CLKDIV2_RATIO                   EXYNOS_CLKREG(0x0C580)
-#define S5P_CLKDIV_STAT_TOP             S5P_CLKREG(0x0C610)
+#define EXYNOS4_CLKDIV_STAT_TOP                 EXYNOS_CLKREG(0x0C610)
+#define EXYNOS4_CLKDIV_STAT_MFC                 EXYNOS_CLKREG(0x0C628)
-#define S5P_CLKGATE_SCLKCAM             S5P_CLKREG(0x0C820)
-#define S5P_CLKGATE_IP_CAM              S5P_CLKREG(0x0C920)
+#define EXYNOS4_CLKGATE_SCLKCAM                 EXYNOS_CLKREG(0x0C820)
-#define S5P_CLKGATE_IP_TV               S5P_CLKREG(0x0C924)
+#define EXYNOS4_CLKGATE_IP_CAM                  EXYNOS_CLKREG(0x0C920)
-#define S5P_CLKGATE_IP_MFC              S5P_CLKREG(0x0C928)
+#define EXYNOS4_CLKGATE_IP_TV                   EXYNOS_CLKREG(0x0C924)
-#define S5P_CLKGATE_IP_G3D              S5P_CLKREG(0x0C92C)
+#define EXYNOS4_CLKGATE_IP_MFC                  EXYNOS_CLKREG(0x0C928)
-#define S5P_CLKGATE_IP_IMAGE            (soc_is_exynos4210() ? \
+#define EXYNOS4_CLKGATE_IP_G3D                  EXYNOS_CLKREG(0x0C92C)
-                                        S5P_CLKREG(0x0C930) : \
+#define EXYNOS4_CLKGATE_IP_IMAGE                (soc_is_exynos4210() ? \
-                                        S5P_CLKREG(0x04930))
+                                                EXYNOS_CLKREG(0x0C930) : \
-#define S5P_CLKGATE_IP_IMAGE_4210       S5P_CLKREG(0x0C930)
+                                                EXYNOS_CLKREG(0x04930))
-#define S5P_CLKGATE_IP_IMAGE_4212       S5P_CLKREG(0x04930)
+#define EXYNOS4210_CLKGATE_IP_IMAGE             EXYNOS_CLKREG(0x0C930)
-#define S5P_CLKGATE_IP_LCD0             S5P_CLKREG(0x0C934)
+#define EXYNOS4212_CLKGATE_IP_IMAGE             EXYNOS_CLKREG(0x04930)
-#define S5P_CLKGATE_IP_FSYS             S5P_CLKREG(0x0C940)
+#define EXYNOS4_CLKGATE_IP_LCD0                 EXYNOS_CLKREG(0x0C934)
-#define S5P_CLKGATE_IP_GPS              S5P_CLKREG(0x0C94C)
+#define EXYNOS4_CLKGATE_IP_FSYS                 EXYNOS_CLKREG(0x0C940)
-#define S5P_CLKGATE_IP_PERIL            S5P_CLKREG(0x0C950)
+#define EXYNOS4_CLKGATE_IP_GPS                  EXYNOS_CLKREG(0x0C94C)
-#define S5P_CLKGATE_IP_PERIR            (soc_is_exynos4210() ? \
+#define EXYNOS4_CLKGATE_IP_PERIL                EXYNOS_CLKREG(0x0C950)
-                                        S5P_CLKREG(0x0C960) : \
+#define EXYNOS4_CLKGATE_IP_PERIR                (soc_is_exynos4210() ? \
-                                        S5P_CLKREG(0x08960))
+                                                EXYNOS_CLKREG(0x0C960) : \
-#define S5P_CLKGATE_IP_PERIR_4210       S5P_CLKREG(0x0C960)
+                                                EXYNOS_CLKREG(0x08960))
-#define S5P_CLKGATE_IP_PERIR_4212       S5P_CLKREG(0x08960)
+#define EXYNOS4210_CLKGATE_IP_PERIR             EXYNOS_CLKREG(0x0C960)
-#define S5P_CLKGATE_BLOCK               S5P_CLKREG(0x0C970)
+#define EXYNOS4212_CLKGATE_IP_PERIR             EXYNOS_CLKREG(0x08960)
+#define EXYNOS4_CLKGATE_BLOCK                   EXYNOS_CLKREG(0x0C970)
-#define S5P_CLKSRC_MASK_DMC             S5P_CLKREG(0x10300)
-#define S5P_CLKSRC_DMC                  S5P_CLKREG(0x10200)
+#define EXYNOS4_CLKSRC_MASK_DMC                 EXYNOS_CLKREG(0x10300)
-#define S5P_CLKDIV_DMC0                 S5P_CLKREG(0x10500)
+#define EXYNOS4_CLKSRC_DMC                      EXYNOS_CLKREG(0x10200)
-#define S5P_CLKDIV_DMC1                 S5P_CLKREG(0x10504)
+#define EXYNOS4_CLKDIV_DMC0                     EXYNOS_CLKREG(0x10500)
-#define S5P_CLKDIV_STAT_DMC0            S5P_CLKREG(0x10600)
+#define EXYNOS4_CLKDIV_DMC1                     EXYNOS_CLKREG(0x10504)
-#define S5P_CLKGATE_IP_DMC              S5P_CLKREG(0x10900)
+#define EXYNOS4_CLKDIV_STAT_DMC0                EXYNOS_CLKREG(0x10600)
+#define EXYNOS4_CLKDIV_STAT_DMC1                EXYNOS_CLKREG(0x10604)
-#define S5P_APLL_LOCK                   S5P_CLKREG(0x14000)
+#define EXYNOS4_CLKGATE_IP_DMC                  EXYNOS_CLKREG(0x10900)
-#define S5P_MPLL_LOCK                   (soc_is_exynos4210() ? \
-                                        S5P_CLKREG(0x14004) :  \
+#define EXYNOS4_DMC_PAUSE_CTRL                  EXYNOS_CLKREG(0x11094)
-                                        S5P_CLKREG(0x10008))
+#define EXYNOS4_DMC_PAUSE_ENABLE                (1 << 0)
-#define S5P_APLL_CON0                   S5P_CLKREG(0x14100)
-#define S5P_APLL_CON1                   S5P_CLKREG(0x14104)
+#define EXYNOS4_APLL_LOCK                       EXYNOS_CLKREG(0x14000)
-#define S5P_MPLL_CON0                   (soc_is_exynos4210() ? \
+#define EXYNOS4_MPLL_LOCK                       (soc_is_exynos4210() ? \
-                                        S5P_CLKREG(0x14108) : \
+                                                EXYNOS_CLKREG(0x14004) :  \
-                                        S5P_CLKREG(0x10108))
+                                                EXYNOS_CLKREG(0x10008))
-#define S5P_MPLL_CON1                   (soc_is_exynos4210() ? \
+#define EXYNOS4_APLL_CON0                       EXYNOS_CLKREG(0x14100)
-                                        S5P_CLKREG(0x1410C) : \
+#define EXYNOS4_APLL_CON1                       EXYNOS_CLKREG(0x14104)
-                                        S5P_CLKREG(0x1010C))
+#define EXYNOS4_MPLL_CON0                       (soc_is_exynos4210() ? \
+                                                EXYNOS_CLKREG(0x14108) : \
-#define S5P_CLKSRC_CPU                  S5P_CLKREG(0x14200)
+                                                EXYNOS_CLKREG(0x10108))
-#define S5P_CLKMUX_STATCPU              S5P_CLKREG(0x14400)
+#define EXYNOS4_MPLL_CON1                       (soc_is_exynos4210() ? \
+                                                EXYNOS_CLKREG(0x1410C) : \
-#define S5P_CLKDIV_CPU                  S5P_CLKREG(0x14500)
+                                                EXYNOS_CLKREG(0x1010C))
-#define S5P_CLKDIV_CPU1                 S5P_CLKREG(0x14504)
-#define S5P_CLKDIV_STATCPU              S5P_CLKREG(0x14600)
+#define EXYNOS4_CLKSRC_CPU                      EXYNOS_CLKREG(0x14200)
-#define S5P_CLKDIV_STATCPU1             S5P_CLKREG(0x14604)
+#define EXYNOS4_CLKMUX_STATCPU                  EXYNOS_CLKREG(0x14400)
-#define S5P_CLKGATE_SCLKCPU             S5P_CLKREG(0x14800)
+#define EXYNOS4_CLKDIV_CPU                      EXYNOS_CLKREG(0x14500)
-#define S5P_CLKGATE_IP_CPU              S5P_CLKREG(0x14900)
+#define EXYNOS4_CLKDIV_CPU1                     EXYNOS_CLKREG(0x14504)
+#define EXYNOS4_CLKDIV_STATCPU                  EXYNOS_CLKREG(0x14600)
-#define S5P_APLL_LOCKTIME               (0x1C20)        /* 300us */
+#define EXYNOS4_CLKDIV_STATCPU1                 EXYNOS_CLKREG(0x14604)
-#define S5P_APLLCON0_ENABLE_SHIFT       (31)
+#define EXYNOS4_CLKGATE_SCLKCPU                 EXYNOS_CLKREG(0x14800)
-#define S5P_APLLCON0_LOCKED_SHIFT       (29)
+#define EXYNOS4_CLKGATE_IP_CPU                  EXYNOS_CLKREG(0x14900)
-#define S5P_APLL_VAL_1000               ((250 << 16) | (6 << 8) | 1)
-#define S5P_APLL_VAL_800                ((200 << 16) | (6 << 8) | 1)
+#define EXYNOS4_APLL_LOCKTIME                   (0x1C20)        /* 300us */
-#define S5P_EPLLCON0_ENABLE_SHIFT       (31)
+#define EXYNOS4_APLLCON0_ENABLE_SHIFT           (31)
-#define S5P_EPLLCON0_LOCKED_SHIFT       (29)
+#define EXYNOS4_APLLCON0_LOCKED_SHIFT           (29)
+#define EXYNOS4_APLL_VAL_1000                   ((250 << 16) | (6 << 8) | 1)
-#define S5P_VPLLCON0_ENABLE_SHIFT       (31)
+#define EXYNOS4_APLL_VAL_800                    ((200 << 16) | (6 << 8) | 1)
-#define S5P_VPLLCON0_LOCKED_SHIFT       (29)
+#define EXYNOS4_EPLLCON0_ENABLE_SHIFT           (31)
-#define S5P_CLKSRC_CPU_MUXCORE_SHIFT    (16)
+#define EXYNOS4_EPLLCON0_LOCKED_SHIFT           (29)
-#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
+#define EXYNOS4_VPLLCON0_ENABLE_SHIFT           (31)
-#define S5P_CLKDIV_CPU0_CORE_SHIFT      (0)
+#define EXYNOS4_VPLLCON0_LOCKED_SHIFT           (29)
-#define S5P_CLKDIV_CPU0_CORE_MASK       (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
-#define S5P_CLKDIV_CPU0_COREM0_SHIFT    (4)
+#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT        (16)
-#define S5P_CLKDIV_CPU0_COREM0_MASK     (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)
+#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK     (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
-#define S5P_CLKDIV_CPU0_COREM1_SHIFT    (8)
-#define S5P_CLKDIV_CPU0_COREM1_MASK     (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT          (0)
-#define S5P_CLKDIV_CPU0_PERIPH_SHIFT    (12)
+#define EXYNOS4_CLKDIV_CPU0_CORE_MASK           (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)
-#define S5P_CLKDIV_CPU0_PERIPH_MASK     (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT        (4)
-#define S5P_CLKDIV_CPU0_ATB_SHIFT       (16)
+#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK         (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)
-#define S5P_CLKDIV_CPU0_ATB_MASK        (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT        (8)
-#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT   (20)
+#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK         (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)
-#define S5P_CLKDIV_CPU0_PCLKDBG_MASK    (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT        (12)
-#define S5P_CLKDIV_CPU0_APLL_SHIFT      (24)
+#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK         (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)
-#define S5P_CLKDIV_CPU0_APLL_MASK       (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT           (16)
+#define EXYNOS4_CLKDIV_CPU0_ATB_MASK            (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)
-#define S5P_CLKDIV_DMC0_ACP_SHIFT       (0)
+#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT       (20)
-#define S5P_CLKDIV_DMC0_ACP_MASK        (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK        (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)
-#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT   (4)
+#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT          (24)
-#define S5P_CLKDIV_DMC0_ACPPCLK_MASK    (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_APLL_MASK           (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)
-#define S5P_CLKDIV_DMC0_DPHY_SHIFT      (8)
+#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT         28
-#define S5P_CLKDIV_DMC0_DPHY_MASK       (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)
+#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK          (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)
-#define S5P_CLKDIV_DMC0_DMC_SHIFT       (12)
-#define S5P_CLKDIV_DMC0_DMC_MASK        (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)
+#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT          0
-#define S5P_CLKDIV_DMC0_DMCD_SHIFT      (16)
+#define EXYNOS4_CLKDIV_CPU1_COPY_MASK           (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)
-#define S5P_CLKDIV_DMC0_DMCD_MASK       (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)
+#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT           4
-#define S5P_CLKDIV_DMC0_DMCP_SHIFT      (20)
+#define EXYNOS4_CLKDIV_CPU1_HPM_MASK            (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)
-#define S5P_CLKDIV_DMC0_DMCP_MASK       (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)
+#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT         8
-#define S5P_CLKDIV_DMC0_COPY2_SHIFT     (24)
+#define EXYNOS4_CLKDIV_CPU1_CORES_MASK          (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)
-#define S5P_CLKDIV_DMC0_COPY2_MASK      (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)
-#define S5P_CLKDIV_DMC0_CORETI_SHIFT    (28)
+#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT           (0)
-#define S5P_CLKDIV_DMC0_CORETI_MASK     (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_ACP_MASK            (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT       (4)
-#define S5P_CLKDIV_TOP_ACLK200_SHIFT    (0)
+#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK        (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
-#define S5P_CLKDIV_TOP_ACLK200_MASK     (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT          (8)
-#define S5P_CLKDIV_TOP_ACLK100_SHIFT    (4)
+#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK           (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
-#define S5P_CLKDIV_TOP_ACLK100_MASK     (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT           (12)
-#define S5P_CLKDIV_TOP_ACLK160_SHIFT    (8)
+#define EXYNOS4_CLKDIV_DMC0_DMC_MASK            (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
-#define S5P_CLKDIV_TOP_ACLK160_MASK     (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT          (16)
-#define S5P_CLKDIV_TOP_ACLK133_SHIFT    (12)
+#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK           (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
-#define S5P_CLKDIV_TOP_ACLK133_MASK     (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT          (20)
-#define S5P_CLKDIV_TOP_ONENAND_SHIFT    (16)
+#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK           (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
-#define S5P_CLKDIV_TOP_ONENAND_MASK     (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT         (24)
+#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK          (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
-#define S5P_CLKDIV_BUS_GDLR_SHIFT       (0)
+#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT        (28)
-#define S5P_CLKDIV_BUS_GDLR_MASK        (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
+#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK         (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
-#define S5P_CLKDIV_BUS_GPLR_SHIFT       (4)
-#define S5P_CLKDIV_BUS_GPLR_MASK        (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT       (0)
+#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK        (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT           (4)
+#define EXYNOS4_CLKDIV_DMC1_C2C_MASK            (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT           (8)
+#define EXYNOS4_CLKDIV_DMC1_PWI_MASK            (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT       (12)
+#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK        (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT         (16)
+#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK          (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
+#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT           (24)
+#define EXYNOS4_CLKDIV_DMC1_DPM_MASK            (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
+#define EXYNOS4_CLKDIV_MFC_SHIFT                (0)
+#define EXYNOS4_CLKDIV_MFC_MASK                 (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT        (0)
+#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK         (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT        (4)
+#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK         (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT        (8)
+#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK         (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT        (12)
+#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK         (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT        (16)
+#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK         (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT    (20)
+#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK     (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
+#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
+#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK  (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
+#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT           (0)
+#define EXYNOS4_CLKDIV_BUS_GDLR_MASK            (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
+#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT           (4)
+#define EXYNOS4_CLKDIV_BUS_GPLR_MASK            (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
+#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT          (0)
+#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK           (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
+#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT          (4)
+#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK           (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
+#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT          (8)
+#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK           (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
+#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT          (12)
+#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK           (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
 /* Only for EXYNOS4210 */
-#define S5P_CLKSRC_LCD1                 S5P_CLKREG(0x0C238)
+#define EXYNOS4210_CLKSRC_LCD1                  EXYNOS_CLKREG(0x0C238)
-#define S5P_CLKSRC_MASK_LCD1            S5P_CLKREG(0x0C338)
+#define EXYNOS4210_CLKSRC_MASK_LCD1             EXYNOS_CLKREG(0x0C338)
-#define S5P_CLKDIV_LCD1                 S5P_CLKREG(0x0C538)
+#define EXYNOS4210_CLKDIV_LCD1                  EXYNOS_CLKREG(0x0C538)
-#define S5P_CLKGATE_IP_LCD1             S5P_CLKREG(0x0C938)
+#define EXYNOS4210_CLKGATE_IP_LCD1              EXYNOS_CLKREG(0x0C938)
+/* Only for EXYNOS4212 */
+#define EXYNOS4_CLKDIV_CAM1                     EXYNOS_CLKREG(0x0C568)
+#define EXYNOS4_CLKDIV_STAT_CAM1                EXYNOS_CLKREG(0x0C668)
+#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT          (0)
+#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK           (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
 /* Compatibility defines and inclusion */
 #include <mach/regs-pmu.h>
-#define S5P_EPLL_CON                    S5P_EPLL_CON0
+#define S5P_EPLL_CON                            EXYNOS4_EPLL_CON0
 #endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index e19013051772..f105bd2b6765 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -38,29 +38,29 @@
 #include <mach/pmu.h>
 static struct sleep_save exynos4_set_clksrc[] = {
-        { .reg = S5P_CLKSRC_MASK_TOP                    , .val = 0x00000001, },
+        { .reg = EXYNOS4_CLKSRC_MASK_TOP                , .val = 0x00000001, },
-        { .reg = S5P_CLKSRC_MASK_CAM                    , .val = 0x11111111, },
+        { .reg = EXYNOS4_CLKSRC_MASK_CAM                , .val = 0x11111111, },
-        { .reg = S5P_CLKSRC_MASK_TV                     , .val = 0x00000111, },
+        { .reg = EXYNOS4_CLKSRC_MASK_TV                 , .val = 0x00000111, },
-        { .reg = S5P_CLKSRC_MASK_LCD0                   , .val = 0x00001111, },
+        { .reg = EXYNOS4_CLKSRC_MASK_LCD0               , .val = 0x00001111, },
-        { .reg = S5P_CLKSRC_MASK_MAUDIO                 , .val = 0x00000001, },
+        { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO             , .val = 0x00000001, },
-        { .reg = S5P_CLKSRC_MASK_FSYS                   , .val = 0x01011111, },
+        { .reg = EXYNOS4_CLKSRC_MASK_FSYS               , .val = 0x01011111, },
-        { .reg = S5P_CLKSRC_MASK_PERIL0                 , .val = 0x01111111, },
+        { .reg = EXYNOS4_CLKSRC_MASK_PERIL0             , .val = 0x01111111, },
-        { .reg = S5P_CLKSRC_MASK_PERIL1                 , .val = 0x01110111, },
+        { .reg = EXYNOS4_CLKSRC_MASK_PERIL1             , .val = 0x01110111, },
-        { .reg = S5P_CLKSRC_MASK_DMC                    , .val = 0x00010000, },
+        { .reg = EXYNOS4_CLKSRC_MASK_DMC                , .val = 0x00010000, },
 };
 static struct sleep_save exynos4210_set_clksrc[] = {
-        { .reg = S5P_CLKSRC_MASK_LCD1                   , .val = 0x00001111, },
+        { .reg = EXYNOS4210_CLKSRC_MASK_LCD1            , .val = 0x00001111, },
 };
 static struct sleep_save exynos4_epll_save[] = {
-        SAVE_ITEM(S5P_EPLL_CON0),
+        SAVE_ITEM(EXYNOS4_EPLL_CON0),
-        SAVE_ITEM(S5P_EPLL_CON1),
+        SAVE_ITEM(EXYNOS4_EPLL_CON1),
 };
 static struct sleep_save exynos4_vpll_save[] = {
-        SAVE_ITEM(S5P_VPLL_CON0),
+        SAVE_ITEM(EXYNOS4_VPLL_CON0),
-        SAVE_ITEM(S5P_VPLL_CON1),
+        SAVE_ITEM(EXYNOS4_VPLL_CON1),
 };
 static struct sleep_save exynos4_core_save[] = {
@@ -239,7 +239,7 @@ static void exynos4_restore_pll(void)
                locktime = (3000 / pll_in_rate) * p_div;
                lockcnt = locktime * 10000 / (10000 / pll_in_rate);
-                __raw_writel(lockcnt, S5P_EPLL_LOCK);
+                __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
                s3c_pm_do_restore_core(exynos4_epll_save,
                                        ARRAY_SIZE(exynos4_epll_save));
@@ -257,7 +257,7 @@ static void exynos4_restore_pll(void)
                locktime = 750;
                lockcnt = locktime * 10000 / (10000 / pll_in_rate);
-                __raw_writel(lockcnt, S5P_VPLL_LOCK);
+                __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
                s3c_pm_do_restore_core(exynos4_vpll_save,
                                        ARRAY_SIZE(exynos4_vpll_save));
@@ -268,14 +268,14 @@ static void exynos4_restore_pll(void)
        do {
                if (epll_wait) {
-                        pll_con = __raw_readl(S5P_EPLL_CON0);
+                        pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
-                        if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
+                        if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
                                epll_wait = 0;
                }
                if (vpll_wait) {
-                        pll_con = __raw_readl(S5P_VPLL_CON0);
+                        pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
-                        if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
+                        if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
                                vpll_wait = 0;
                }
        } while (epll_wait || vpll_wait);
diff --git a/arch/arm/mach-lpc32xx/include/mach/irqs.h b/arch/arm/mach-lpc32xx/include/mach/irqs.h
index 2667f52e3b04..9e3b90df32e1 100644
--- a/arch/arm/mach-lpc32xx/include/mach/irqs.h
+++ b/arch/arm/mach-lpc32xx/include/mach/irqs.h
@@ -61,7 +61,7 @@
 */
 #define IRQ_LPC32XX_JTAG_COMM_TX        LPC32XX_SIC1_IRQ(1)
 #define IRQ_LPC32XX_JTAG_COMM_RX        LPC32XX_SIC1_IRQ(2)
-#define IRQ_LPC32XX_GPI_11              LPC32XX_SIC1_IRQ(4)
+#define IRQ_LPC32XX_GPI_28              LPC32XX_SIC1_IRQ(4)
 #define IRQ_LPC32XX_TS_P                LPC32XX_SIC1_IRQ(6)
 #define IRQ_LPC32XX_TS_IRQ              LPC32XX_SIC1_IRQ(7)
 #define IRQ_LPC32XX_TS_AUX              LPC32XX_SIC1_IRQ(8)
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index 4eae566dfdc7..c74de01ab5b6 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -118,6 +118,10 @@ static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = {
                .event_group = &lpc32xx_event_pin_regs,
                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT,
        },
+        [IRQ_LPC32XX_GPI_28] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT,
+        },
        [IRQ_LPC32XX_GPIO_00] = {
                .event_group = &lpc32xx_event_int_regs,
                .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
@@ -305,9 +309,18 @@ static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state)
                if (state)
                        eventreg |= lpc32xx_events[d->irq].mask;
-                else
+                else {
                        eventreg &= ~lpc32xx_events[d->irq].mask;
+                        /*
+                         * When disabling the wakeup, clear the latched
+                         * event
+                         */
+                        __raw_writel(lpc32xx_events[d->irq].mask,
+                                lpc32xx_events[d->irq].
+                                event_group->rawstat_reg);
+                }
                __raw_writel(eventreg,
                        lpc32xx_events[d->irq].event_group->enab_reg);
@@ -380,13 +393,15 @@ void __init lpc32xx_init_irq(void)
        /* Setup SIC1 */
        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
-        __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
+        __raw_writel(SIC1_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
-        __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
+        __raw_writel(SIC1_ATR_DEFAULT,
+                                LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
        /* Setup SIC2 */
        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
-        __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
+        __raw_writel(SIC2_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
-        __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
+        __raw_writel(SIC2_ATR_DEFAULT,
+                                LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
        /* Configure supported IRQ's */
        for (i = 0; i < NR_IRQS; i++) {
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
index 429cfdbb2b3d..f2735281616a 100644
--- a/arch/arm/mach-lpc32xx/serial.c
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -88,6 +88,7 @@ struct uartinit {
        char *uart_ck_name;
        u32 ck_mode_mask;
        void __iomem *pdiv_clk_reg;
+        resource_size_t mapbase;
 };
 static struct uartinit uartinit_data[] __initdata = {
@@ -97,6 +98,7 @@ static struct uartinit uartinit_data[] __initdata = {
                .ck_mode_mask =
                        LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
                .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
+                .mapbase = LPC32XX_UART5_BASE,
        },
 #endif
 #ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
@@ -105,6 +107,7 @@ static struct uartinit uartinit_data[] __initdata = {
                .ck_mode_mask =
                        LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
                .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
+                .mapbase = LPC32XX_UART3_BASE,
        },
 #endif
 #ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
@@ -113,6 +116,7 @@ static struct uartinit uartinit_data[] __initdata = {
                .ck_mode_mask =
                        LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
                .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
+                .mapbase = LPC32XX_UART4_BASE,
        },
 #endif
 #ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
@@ -121,6 +125,7 @@ static struct uartinit uartinit_data[] __initdata = {
                .ck_mode_mask =
                        LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
                .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
+                .mapbase = LPC32XX_UART6_BASE,
        },
 #endif
 };
@@ -165,11 +170,24 @@ void __init lpc32xx_serial_init(void)
                /* pre-UART clock divider set to 1 */
                __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
+                /*
+                 * Force a flush of the RX FIFOs to work around a
+                 * HW bug
+                 */
+                puart = uartinit_data[i].mapbase;
+                __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
+                __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
+                j = LPC32XX_SUART_FIFO_SIZE;
+                while (j--)
+                        tmp = __raw_readl(
+                                LPC32XX_UART_DLL_FIFO(puart));
+                __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
        }
        /* This needs to be done after all UART clocks are setup */
        __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
-        for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) {
+        for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
                /* Force a flush of the RX FIFOs to work around a HW bug */
                puart = serial_std_platform_data[i].mapbase;
                __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 17cb76060125..3588a5584153 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -17,7 +17,6 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
 #include <linux/interrupt.h>
-#include <linux/gpio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 7bc17eaa12eb..ada1213982b4 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -24,7 +24,6 @@
 #include <mach/dma.h>
 #include <mach/devices.h>
 #include <mach/mfp.h>
-#include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <mach/pxa168.h>
diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c
index 8e3b5af04a57..bc97170125bf 100644
--- a/arch/arm/mach-mmp/tavorevb.c
+++ b/arch/arm/mach-mmp/tavorevb.c
@@ -12,7 +12,6 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/smc91x.h>
-#include <linux/gpio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 289a6b82c5f7..74de3e39a10d 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -419,13 +419,13 @@ static void __init innovator_init(void)
 #ifdef CONFIG_ARCH_OMAP15XX
        if (cpu_is_omap1510()) {
                omap1_usb_init(&innovator1510_usb_config);
-                innovator_config[1].data = &innovator1510_lcd_config;
+                innovator_config[0].data = &innovator1510_lcd_config;
        }
 #endif
 #ifdef CONFIG_ARCH_OMAP16XX
        if (cpu_is_omap1610()) {
                omap1_usb_init(&h2_usb_config);
-                innovator_config[1].data = &innovator1610_lcd_config;
+                innovator_config[0].data = &innovator1610_lcd_config;
        }
 #endif
        omap_board_config = innovator_config;
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index d965da45160e..e20c8ab80b0e 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -364,8 +364,8 @@ config OMAP3_SDRC_AC_TIMING
          going on could result in system crashes;
 config OMAP4_ERRATA_I688
-        bool "OMAP4 errata: Async Bridge Corruption (BROKEN)"
+        bool "OMAP4 errata: Async Bridge Corruption"
-        depends on ARCH_OMAP4 && BROKEN
+        depends on ARCH_OMAP4
        select ARCH_HAS_BARRIERS
        help
          If a data is stalled inside asynchronous bridge because of back
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 6b77ad95981d..a659e198892b 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -381,7 +381,7 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
        gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "EN_DVI");
        /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
-        gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
+        gpio_leds[0].gpio = gpio + TWL4030_GPIO_MAX + 1;
        platform_device_register(&leds_gpio);
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index f78ec4e6a5c7..4897ec02e798 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -132,6 +132,7 @@ void omap3_map_io(void);
 void am33xx_map_io(void);
 void omap4_map_io(void);
 void ti81xx_map_io(void);
+void omap_barriers_init(void);
 extern void __init omap_init_consistent_dma_size(void);
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index cfdbb86bc84e..72e018b9b260 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -65,7 +65,6 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
        struct timespec ts_preidle, ts_postidle, ts_idle;
        u32 cpu1_state;
        int idle_time;
-        int new_state_idx;
        int cpu_id = smp_processor_id();
        /* Used to keep track of the total time in idle */
@@ -84,8 +83,8 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
         */
        cpu1_state = pwrdm_read_pwrst(cpu1_pd);
        if (cpu1_state != PWRDM_POWER_OFF) {
-                new_state_idx = drv->safe_state_index;
+                index = drv->safe_state_index;
-                cx = cpuidle_get_statedata(&dev->states_usage[new_state_idx]);
+                cx = cpuidle_get_statedata(&dev->states_usage[index]);
        }
        if (index > 0)
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
index 997033129d26..bbb870c04a5e 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -19,6 +19,8 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/smsc911x.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <plat/board.h>
 #include <plat/gpmc.h>
@@ -42,6 +44,50 @@ static struct smsc911x_platform_config gpmc_smsc911x_config = {
        .flags          = SMSC911X_USE_16BIT,
 };
+static struct regulator_consumer_supply gpmc_smsc911x_supply[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
+};
+/* Generic regulator definition to satisfy smsc911x */
+static struct regulator_init_data gpmc_smsc911x_reg_init_data = {
+        .constraints = {
+                .min_uV                 = 3300000,
+                .max_uV                 = 3300000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(gpmc_smsc911x_supply),
+        .consumer_supplies      = gpmc_smsc911x_supply,
+};
+static struct fixed_voltage_config gpmc_smsc911x_fixed_reg_data = {
+        .supply_name            = "gpmc_smsc911x",
+        .microvolts             = 3300000,
+        .gpio                   = -EINVAL,
+        .startup_delay          = 0,
+        .enable_high            = 0,
+        .enabled_at_boot        = 1,
+        .init_data              = &gpmc_smsc911x_reg_init_data,
+};
+/*
+ * Platform device id of 42 is a temporary fix to avoid conflicts
+ * with other reg-fixed-voltage devices. The real fix should
+ * involve the driver core providing a way of dynamically
+ * assigning a unique id on registration for platform devices
+ * in the same name space.
+ */
+static struct platform_device gpmc_smsc911x_regulator = {
+        .name           = "reg-fixed-voltage",
+        .id             = 42,
+        .dev = {
+                .platform_data  = &gpmc_smsc911x_fixed_reg_data,
+        },
+};
 /*
 * Initialize smsc911x device connected to the GPMC. Note that we
 * assume that pin multiplexing is done in the board-*.c file,
@@ -55,6 +101,12 @@ void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
        gpmc_cfg = board_data;
+        ret = platform_device_register(&gpmc_smsc911x_regulator);
+        if (ret < 0) {
+                pr_err("Unable to register smsc911x regulators: %d\n", ret);
+                return;
+        }
        if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
                pr_err("Failed to request GPMC mem region\n");
                return;
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3203128eef7d..0b73d3153604 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -304,6 +304,7 @@ void __init omapam33xx_map_common_io(void)
 void __init omap44xx_map_common_io(void)
 {
        iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
+        omap_barriers_init();
 }
 #endif
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 609ea2ded7e3..2cc1aa004b94 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -281,8 +281,16 @@ static struct omap_mbox mbox_iva_info = {
        .ops    = &omap2_mbox_ops,
        .priv   = &omap2_mbox_iva_priv,
 };
+#endif
-struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
+#ifdef CONFIG_ARCH_OMAP2
+struct omap_mbox *omap2_mboxes[] = {
+        &mbox_dsp_info,
+#ifdef CONFIG_SOC_OMAP2420
+        &mbox_iva_info,
+#endif
+        NULL
+};
 #endif
 #if defined(CONFIG_ARCH_OMAP4)
@@ -412,7 +420,8 @@ static void __exit omap2_mbox_exit(void)
        platform_driver_unregister(&omap2_mbox_driver);
 }
-module_init(omap2_mbox_init);
+/* must be ready before omap3isp is probed */
+subsys_initcall(omap2_mbox_init);
 module_exit(omap2_mbox_exit);
 MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 40a8fbc07e4b..ebc595091312 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -24,6 +24,7 @@
 #include <plat/irqs.h>
 #include <plat/sram.h>
+#include <plat/omap-secure.h>
 #include <mach/hardware.h>
 #include <mach/omap-wakeupgen.h>
@@ -43,6 +44,9 @@ static void __iomem *sar_ram_base;
 void __iomem *dram_sync, *sram_sync;
+static phys_addr_t paddr;
+static u32 size;
 void omap_bus_sync(void)
 {
        if (dram_sync && sram_sync) {
@@ -52,18 +56,20 @@ void omap_bus_sync(void)
        }
 }
-static int __init omap_barriers_init(void)
+/* Steal one page physical memory for barrier implementation */
+int __init omap_barrier_reserve_memblock(void)
 {
-        struct map_desc dram_io_desc[1];
-        phys_addr_t paddr;
-        u32 size;
-        if (!cpu_is_omap44xx())
-                return -ENODEV;
        size = ALIGN(PAGE_SIZE, SZ_1M);
        paddr = arm_memblock_steal(size, SZ_1M);
+        return 0;
+}
+void __init omap_barriers_init(void)
+{
+        struct map_desc dram_io_desc[1];
        dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
        dram_io_desc[0].pfn = __phys_to_pfn(paddr);
        dram_io_desc[0].length = size;
@@ -75,9 +81,10 @@ static int __init omap_barriers_init(void)
        pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
                (long long) paddr, dram_io_desc[0].virtual);
-        return 0;
 }
-core_initcall(omap_barriers_init);
+#else
+void __init omap_barriers_init(void)
+{}
 #endif
 void __init gic_init_irq(void)
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 28706696a341..d383f71b4867 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -189,14 +189,17 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
        freq = clk->rate;
        clk_put(clk);
+        rcu_read_lock();
        opp = opp_find_freq_ceil(dev, &freq);
        if (IS_ERR(opp)) {
+                rcu_read_unlock();
                pr_err("%s: unable to find boot up OPP for vdd_%s\n",
                        __func__, vdd_name);
                goto exit;
        }
        bootup_volt = opp_get_voltage(opp);
+        rcu_read_unlock();
        if (!bootup_volt) {
                pr_err("%s: unable to find voltage corresponding "
                        "to the bootup OPP for vdd_%s\n", __func__, vdd_name);
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index 771dc781b746..f51348dafafd 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -486,7 +486,7 @@ static void setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
 void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
 {
        struct omap_hwmod       *oh[2];
-        struct omap_device      *od;
+        struct platform_device  *pdev;
        int                     bus_id = -1;
        int                     i;
@@ -522,11 +522,11 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
                return;
        }
-        od = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 2,
+        pdev = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 2,
                                (void *)&usbhs_data, sizeof(usbhs_data),
                                omap_uhhtll_latency,
                                ARRAY_SIZE(omap_uhhtll_latency), false);
-        if (IS_ERR(od)) {
+        if (IS_ERR(pdev)) {
                pr_err("Could not build hwmod devices %s,%s\n",
                        USBHS_UHH_HWMODNAME, USBHS_TLL_HWMODNAME);
                return;
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index fb9b62dcf4ca..208eef1c0485 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -45,6 +45,7 @@
 #include <mach/hx4700.h>
 #include <mach/irda.h>
+#include <sound/ak4641.h>
 #include <video/platform_lcd.h>
 #include <video/w100fb.h>
@@ -765,6 +766,28 @@ static struct i2c_board_info __initdata pi2c_board_info[] = {
 };
 /*
+ * Asahi Kasei AK4641 on I2C
+ */
+static struct ak4641_platform_data ak4641_info = {
+        .gpio_power = GPIO27_HX4700_CODEC_ON,
+        .gpio_npdn  = GPIO109_HX4700_CODEC_nPDN,
+};
+static struct i2c_board_info i2c_board_info[] __initdata = {
+        {
+                I2C_BOARD_INFO("ak4641", 0x12),
+                .platform_data = &ak4641_info,
+        },
+};
+static struct platform_device audio = {
+        .name   = "hx4700-audio",
+        .id     = -1,
+};
+/*
 * PCMCIA
 */
@@ -790,6 +813,7 @@ static struct platform_device *devices[] __initdata = {
        &gpio_vbus,
        &power_supply,
        &strataflash,
+        &audio,
        &pcmcia,
 };
@@ -827,6 +851,7 @@ static void __init hx4700_init(void)
        pxa_set_ficp_info(&ficp_info);
        pxa27x_set_i2c_power_info(NULL);
        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(i2c_board_info));
        i2c_register_board_info(1, ARRAY_AND_SIZE(pi2c_board_info));
        pxa2xx_set_spi_info(2, &pxa_ssp2_master_info);
        spi_register_board_info(ARRAY_AND_SIZE(tsc2046_board_info));
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 91e4f6c03766..00d6eacab8e4 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -25,7 +25,6 @@
 #include <linux/suspend.h>
 #include <linux/syscore_ops.h>
 #include <linux/irq.h>
-#include <linux/gpio.h>
 #include <asm/mach/map.h>
 #include <asm/suspend.h>
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index aed6cbcf3866..c1673b3441d4 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -22,7 +22,6 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/i2c/pxa-i2c.h>
-#include <linux/gpio.h>
 #include <asm/mach/map.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c
index febc809ed5a6..5aded5e6148f 100644
--- a/arch/arm/mach-pxa/saarb.c
+++ b/arch/arm/mach-pxa/saarb.c
@@ -15,7 +15,6 @@
 #include <linux/i2c.h>
 #include <linux/i2c/pxa-i2c.h>
 #include <linux/mfd/88pm860x.h>
-#include <linux/gpio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 8d5168d253a9..30989baf7f2a 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -168,6 +168,7 @@ struct battery_thresh sharpsl_battery_levels_noac[] = {
 #define MAXCTRL_SEL_SH   4
 #define MAXCTRL_STR      (1u << 7)
+extern int max1111_read_channel(int);
 /*
 * Read MAX1111 ADC
 */
@@ -177,8 +178,6 @@ int sharpsl_pm_pxa_read_max1111(int channel)
        if (machine_is_tosa())
            return 0;
-        extern int max1111_read_channel(int);
        /* max1111 accepts channels from 0-3, however,
         * it is encoded from 0-7 here in the code.
         */
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 34cbdac51525..438f02fe122a 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -172,10 +172,9 @@ static int spitz_should_wakeup(unsigned int resume_on_alarm)
 static unsigned long spitz_charger_wakeup(void)
 {
        unsigned long ret;
-        ret = (!gpio_get_value(SPITZ_GPIO_KEY_INT)
+        ret = ((!gpio_get_value(SPITZ_GPIO_KEY_INT)
                << GPIO_bit(SPITZ_GPIO_KEY_INT))
-                | (!gpio_get_value(SPITZ_GPIO_SYNC)
+                | gpio_get_value(SPITZ_GPIO_SYNC));
-                << GPIO_bit(SPITZ_GPIO_SYNC));
        return ret;
 }
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 06383b51e655..4de7d1e79e73 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -69,6 +69,7 @@ void __init omap_reserve(void)
        omap_vram_reserve_sdram_memblock();
        omap_dsp_reserve_sdram_memblock();
        omap_secure_ram_reserve_memblock();
+        omap_barrier_reserve_memblock();
 }
 void __init omap_init_consistent_dma_size(void)
diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h
index 3047ff923a63..8c7994ce9869 100644
--- a/arch/arm/plat-omap/include/plat/omap-secure.h
+++ b/arch/arm/plat-omap/include/plat/omap-secure.h
@@ -10,4 +10,10 @@ static inline void omap_secure_ram_reserve_memblock(void)
 { }
 #endif
+#ifdef CONFIG_OMAP4_ERRATA_I688
+extern int omap_barrier_reserve_memblock(void);
+#else
+static inline void omap_barrier_reserve_memblock(void)
+{ }
+#endif
 #endif /* __OMAP_SECURE_H__ */
diff --git a/arch/openrisc/include/asm/ptrace.h b/arch/openrisc/include/asm/ptrace.h
index 054537c5f9c9..e612ce4512c7 100644
--- a/arch/openrisc/include/asm/ptrace.h
+++ b/arch/openrisc/include/asm/ptrace.h
@@ -77,7 +77,6 @@ struct pt_regs {
        long  syscallno;        /* Syscall number (used by strace) */
        long dummy;             /* Cheap alignment fix */
 };
-#endif /* __ASSEMBLY__ */
 /* TODO: Rename this to REDZONE because that's what it is */
 #define STACK_FRAME_OVERHEAD  128  /* size of minimum stack frame */
@@ -87,6 +86,13 @@ struct pt_regs {
 #define user_stack_pointer(regs)        ((unsigned long)(regs)->sp)
 #define profile_pc(regs)                instruction_pointer(regs)
+static inline long regs_return_value(struct pt_regs *regs)
+{
+        return regs->gpr[11];
+}
+#endif /* __ASSEMBLY__ */
 /*
 * Offsets used by 'ptrace' system call interface.
 */
diff --git a/arch/openrisc/kernel/init_task.c b/arch/openrisc/kernel/init_task.c
index 45744a384927..ca534082d5f3 100644
--- a/arch/openrisc/kernel/init_task.c
+++ b/arch/openrisc/kernel/init_task.c
@@ -17,6 +17,7 @@
 #include <linux/init_task.h>
 #include <linux/mqueue.h>
+#include <linux/export.h>
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
diff --git a/arch/openrisc/kernel/irq.c b/arch/openrisc/kernel/irq.c
index 59b302338331..4bfead220956 100644
--- a/arch/openrisc/kernel/irq.c
+++ b/arch/openrisc/kernel/irq.c
@@ -23,6 +23,7 @@
 #include <linux/irq.h>
 #include <linux/seq_file.h>
 #include <linux/kernel_stat.h>
+#include <linux/export.h>
 #include <linux/irqflags.h>
diff --git a/arch/openrisc/kernel/ptrace.c b/arch/openrisc/kernel/ptrace.c
index 656b94beab89..7259047d5f9d 100644
--- a/arch/openrisc/kernel/ptrace.c
+++ b/arch/openrisc/kernel/ptrace.c
@@ -188,11 +188,9 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
                 */
                ret = -1L;
-        /* Are these regs right??? */
+        audit_syscall_entry(audit_arch(), regs->syscallno,
-        if (unlikely(current->audit_context))
+                            regs->gpr[3], regs->gpr[4],
-                audit_syscall_entry(audit_arch(), regs->syscallno,
+                            regs->gpr[5], regs->gpr[6]);
-                                    regs->gpr[3], regs->gpr[4],
-                                    regs->gpr[5], regs->gpr[6]);
        return ret ? : regs->syscallno;
 }
@@ -201,9 +199,7 @@ asmlinkage void do_syscall_trace_leave(struct pt_regs *regs)
 {
        int step;
-        if (unlikely(current->audit_context))
+        audit_syscall_exit(regs);
-                audit_syscall_exit(AUDITSC_RESULT(regs->gpr[11]),
-                                   regs->gpr[11]);
        step = test_thread_flag(TIF_SINGLESTEP);
        if (step || test_thread_flag(TIF_SYSCALL_TRACE))
diff --git a/arch/parisc/Makefile b/arch/parisc/Makefile
index 55cca1dac431..19ab7b2ea1cd 100644
--- a/arch/parisc/Makefile
+++ b/arch/parisc/Makefile
@@ -31,7 +31,11 @@ ifdef CONFIG_64BIT
 UTS_MACHINE     := parisc64
 CHECKFLAGS      += -D__LP64__=1 -m64
 WIDTH           := 64
+# FIXME: if no default set, should really try to locate dynamically
+ifeq ($(CROSS_COMPILE),)
 CROSS_COMPILE   := hppa64-linux-gnu-
+endif
 else # 32-bit
 WIDTH           :=
 endif
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index d1727584230a..6d99a5fcc090 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -227,6 +227,9 @@ config COMPAT
 config SYSVIPC_COMPAT
        def_bool y if COMPAT && SYSVIPC
+config KEYS_COMPAT
+        def_bool y if COMPAT && KEYS
 config AUDIT_ARCH
        def_bool y
diff --git a/arch/s390/include/asm/compat.h b/arch/s390/include/asm/compat.h
index 2e49748b27da..234f1d859cea 100644
--- a/arch/s390/include/asm/compat.h
+++ b/arch/s390/include/asm/compat.h
@@ -172,13 +172,6 @@ static inline int is_compat_task(void)
        return is_32bit_task();
 }
-#else
-static inline int is_compat_task(void)
-{
-        return 0;
-}
 #endif
 static inline void __user *arch_compat_alloc_user_space(long len)
diff --git a/arch/s390/kernel/crash_dump.c b/arch/s390/kernel/crash_dump.c
index 39f8fd4438fc..c383ce440d99 100644
--- a/arch/s390/kernel/crash_dump.c
+++ b/arch/s390/kernel/crash_dump.c
@@ -11,7 +11,6 @@
 #include <linux/module.h>
 #include <linux/gfp.h>
 #include <linux/slab.h>
-#include <linux/crash_dump.h>
 #include <linux/bootmem.h>
 #include <linux/elf.h>
 #include <asm/ipl.h>
diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c
index 4261aa799774..e795933eb2cb 100644
--- a/arch/s390/kernel/process.c
+++ b/arch/s390/kernel/process.c
@@ -29,7 +29,6 @@
 #include <asm/irq.h>
 #include <asm/timer.h>
 #include <asm/nmi.h>
-#include <asm/compat.h>
 #include <asm/smp.h>
 #include "entry.h"
diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c
index 9d82ed4bcb27..61f95489d70c 100644
--- a/arch/s390/kernel/ptrace.c
+++ b/arch/s390/kernel/ptrace.c
@@ -20,8 +20,8 @@
 #include <linux/regset.h>
 #include <linux/tracehook.h>
 #include <linux/seccomp.h>
+#include <linux/compat.h>
 #include <trace/syscall.h>
-#include <asm/compat.h>
 #include <asm/segment.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
index 354de0763eff..3b2efc81f34e 100644
--- a/arch/s390/kernel/setup.c
+++ b/arch/s390/kernel/setup.c
@@ -46,6 +46,7 @@
 #include <linux/kexec.h>
 #include <linux/crash_dump.h>
 #include <linux/memory.h>
+#include <linux/compat.h>
 #include <asm/ipl.h>
 #include <asm/uaccess.h>
@@ -59,7 +60,6 @@
 #include <asm/ptrace.h>
 #include <asm/sections.h>
 #include <asm/ebcdic.h>
-#include <asm/compat.h>
 #include <asm/kvm_virtio.h>
 #include <asm/diag.h>
diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c
index a8ba840294ff..2d421d90fada 100644
--- a/arch/s390/kernel/signal.c
+++ b/arch/s390/kernel/signal.c
@@ -30,7 +30,6 @@
 #include <asm/ucontext.h>
 #include <asm/uaccess.h>
 #include <asm/lowcore.h>
-#include <asm/compat.h>
 #include "entry.h"
 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c
index 354dd39073ef..e8fcd928dc78 100644
--- a/arch/s390/mm/fault.c
+++ b/arch/s390/mm/fault.c
@@ -36,7 +36,6 @@
 #include <asm/pgtable.h>
 #include <asm/irq.h>
 #include <asm/mmu_context.h>
-#include <asm/compat.h>
 #include "../kernel/entry.h"
 #ifndef CONFIG_64BIT
diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c
index 5d633019d8f3..50236610de83 100644
--- a/arch/s390/mm/init.c
+++ b/arch/s390/mm/init.c
@@ -223,16 +223,38 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 #ifdef CONFIG_MEMORY_HOTPLUG
 int arch_add_memory(int nid, u64 start, u64 size)
 {
-        struct pglist_data *pgdat;
+        unsigned long zone_start_pfn, zone_end_pfn, nr_pages;
+        unsigned long start_pfn = PFN_DOWN(start);
+        unsigned long size_pages = PFN_DOWN(size);
        struct zone *zone;
        int rc;
-        pgdat = NODE_DATA(nid);
-        zone = pgdat->node_zones + ZONE_MOVABLE;
        rc = vmem_add_mapping(start, size);
        if (rc)
                return rc;
-        rc = __add_pages(nid, zone, PFN_DOWN(start), PFN_DOWN(size));
+        for_each_zone(zone) {
+                if (zone_idx(zone) != ZONE_MOVABLE) {
+                        /* Add range within existing zone limits */
+                        zone_start_pfn = zone->zone_start_pfn;
+                        zone_end_pfn = zone->zone_start_pfn +
+                                       zone->spanned_pages;
+                } else {
+                        /* Add remaining range to ZONE_MOVABLE */
+                        zone_start_pfn = start_pfn;
+                        zone_end_pfn = start_pfn + size_pages;
+                }
+                if (start_pfn < zone_start_pfn || start_pfn >= zone_end_pfn)
+                        continue;
+                nr_pages = (start_pfn + size_pages > zone_end_pfn) ?
+                           zone_end_pfn - start_pfn : size_pages;
+                rc = __add_pages(nid, zone, start_pfn, nr_pages);
+                if (rc)
+                        break;
+                start_pfn += nr_pages;
+                size_pages -= nr_pages;
+                if (!size_pages)
+                        break;
+        }
        if (rc)
                vmem_remove_mapping(start, size);
        return rc;
diff --git a/arch/s390/mm/mmap.c b/arch/s390/mm/mmap.c
index f09c74881b7e..a0155c02e324 100644
--- a/arch/s390/mm/mmap.c
+++ b/arch/s390/mm/mmap.c
@@ -29,8 +29,8 @@
 #include <linux/mman.h>
 #include <linux/module.h>
 #include <linux/random.h>
+#include <linux/compat.h>
 #include <asm/pgalloc.h>
-#include <asm/compat.h>
 static unsigned long stack_maxrandom_size(void)
 {
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 096c975e099f..461ce432b1c2 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -242,4 +242,12 @@ static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
 static inline void perf_events_lapic_init(void) { }
 #endif
+#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
+ extern void amd_pmu_enable_virt(void);
+ extern void amd_pmu_disable_virt(void);
+#else
+ static inline void amd_pmu_enable_virt(void) { }
+ static inline void amd_pmu_disable_virt(void) { }
+#endif
 #endif /* _ASM_X86_PERF_EVENT_H */
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 6b45e5e7a901..73d08ed98a64 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -326,8 +326,7 @@ static void __cpuinit amd_calc_l3_indices(struct amd_northbridge *nb)
        l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1;
 }
-static void __cpuinit amd_init_l3_cache(struct _cpuid4_info_regs *this_leaf,
+static void __cpuinit amd_init_l3_cache(struct _cpuid4_info_regs *this_leaf, int index)
-                                        int index)
 {
        int node;
@@ -725,14 +724,16 @@ static DEFINE_PER_CPU(struct _cpuid4_info *, ici_cpuid4_info);
 #define CPUID4_INFO_IDX(x, y)   (&((per_cpu(ici_cpuid4_info, x))[y]))
 #ifdef CONFIG_SMP
-static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
+static int __cpuinit cache_shared_amd_cpu_map_setup(unsigned int cpu, int index)
 {
-        struct _cpuid4_info     *this_leaf, *sibling_leaf;
+        struct _cpuid4_info *this_leaf;
-        unsigned long num_threads_sharing;
+        int ret, i, sibling;
-        int index_msb, i, sibling;
        struct cpuinfo_x86 *c = &cpu_data(cpu);
-        if ((index == 3) && (c->x86_vendor == X86_VENDOR_AMD)) {
+        ret = 0;
+        if (index == 3) {
+                ret = 1;
                for_each_cpu(i, cpu_llc_shared_mask(cpu)) {
                        if (!per_cpu(ici_cpuid4_info, i))
                                continue;
@@ -743,8 +744,35 @@ static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
                                set_bit(sibling, this_leaf->shared_cpu_map);
                        }
                }
-                return;
+        } else if ((c->x86 == 0x15) && ((index == 1) || (index == 2))) {
+                ret = 1;
+                for_each_cpu(i, cpu_sibling_mask(cpu)) {
+                        if (!per_cpu(ici_cpuid4_info, i))
+                                continue;
+                        this_leaf = CPUID4_INFO_IDX(i, index);
+                        for_each_cpu(sibling, cpu_sibling_mask(cpu)) {
+                                if (!cpu_online(sibling))
+                                        continue;
+                                set_bit(sibling, this_leaf->shared_cpu_map);
+                        }
+                }
        }
+        return ret;
+}
+static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
+{
+        struct _cpuid4_info *this_leaf, *sibling_leaf;
+        unsigned long num_threads_sharing;
+        int index_msb, i;
+        struct cpuinfo_x86 *c = &cpu_data(cpu);
+        if (c->x86_vendor == X86_VENDOR_AMD) {
+                if (cache_shared_amd_cpu_map_setup(cpu, index))
+                        return;
+        }
        this_leaf = CPUID4_INFO_IDX(cpu, index);
        num_threads_sharing = 1 + this_leaf->base.eax.split.num_threads_sharing;
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 786e76a86322..e4eeaaf58a47 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -528,6 +528,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
        sprintf(name, "threshold_bank%i", bank);
+#ifdef CONFIG_SMP
        if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) {   /* symlink */
                i = cpumask_first(cpu_llc_shared_mask(cpu));
@@ -553,6 +554,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
                goto out;
        }
+#endif
        b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
        if (!b) {
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index 8944062f46e2..c30c807ddc72 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -147,7 +147,9 @@ struct cpu_hw_events {
        /*
         * AMD specific bits
         */
-        struct amd_nb           *amd_nb;
+        struct amd_nb                   *amd_nb;
+        /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
+        u64                             perf_ctr_virt_mask;
        void                            *kfree_on_online;
 };
@@ -417,9 +419,11 @@ void x86_pmu_disable_all(void);
 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
                                          u64 enable_mask)
 {
+        u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
        if (hwc->extra_reg.reg)
                wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
-        wrmsrl(hwc->config_base, hwc->config | enable_mask);
+        wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
 }
 void x86_pmu_enable_all(int added);
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index 0397b23be8e9..67250a52430b 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -1,4 +1,5 @@
 #include <linux/perf_event.h>
+#include <linux/export.h>
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/slab.h>
@@ -357,7 +358,9 @@ static void amd_pmu_cpu_starting(int cpu)
        struct amd_nb *nb;
        int i, nb_id;
-        if (boot_cpu_data.x86_max_cores < 2)
+        cpuc->perf_ctr_virt_mask = AMD_PERFMON_EVENTSEL_HOSTONLY;
+        if (boot_cpu_data.x86_max_cores < 2 || boot_cpu_data.x86 == 0x15)
                return;
        nb_id = amd_get_nb_id(cpu);
@@ -587,9 +590,9 @@ static __initconst const struct x86_pmu amd_pmu_f15h = {
        .put_event_constraints  = amd_put_event_constraints,
        .cpu_prepare            = amd_pmu_cpu_prepare,
-        .cpu_starting           = amd_pmu_cpu_starting,
        .cpu_dead               = amd_pmu_cpu_dead,
 #endif
+        .cpu_starting           = amd_pmu_cpu_starting,
 };
 __init int amd_pmu_init(void)
@@ -621,3 +624,33 @@ __init int amd_pmu_init(void)
        return 0;
 }
+void amd_pmu_enable_virt(void)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        cpuc->perf_ctr_virt_mask = 0;
+        /* Reload all events */
+        x86_pmu_disable_all();
+        x86_pmu_enable_all(0);
+}
+EXPORT_SYMBOL_GPL(amd_pmu_enable_virt);
+void amd_pmu_disable_virt(void)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        /*
+         * We only mask out the Host-only bit so that host-only counting works
+         * when SVM is disabled. If someone sets up a guest-only counter when
+         * SVM is disabled the Guest-only bits still gets set and the counter
+         * will not count anything.
+         */
+        cpuc->perf_ctr_virt_mask = AMD_PERFMON_EVENTSEL_HOSTONLY;
+        /* Reload all events */
+        x86_pmu_disable_all();
+        x86_pmu_enable_all(0);
+}
+EXPORT_SYMBOL_GPL(amd_pmu_disable_virt);
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index 3fe8239fd8fb..1333d9851778 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -1532,10 +1532,17 @@ ENTRY(nmi)
        pushq_cfi %rdx
        /*
+         * If %cs was not the kernel segment, then the NMI triggered in user
+         * space, which means it is definitely not nested.
+         */
+        cmpl $__KERNEL_CS, 16(%rsp)
+        jne first_nmi
+        /*
         * Check the special variable on the stack to see if NMIs are
         * executing.
         */
-        cmp $1, -8(%rsp)
+        cmpl $1, -8(%rsp)
        je nested_nmi
        /*
diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c
index ac0417be9131..73465aab28f8 100644
--- a/arch/x86/kernel/microcode_amd.c
+++ b/arch/x86/kernel/microcode_amd.c
@@ -360,7 +360,6 @@ out:
 static enum ucode_state
 request_microcode_user(int cpu, const void __user *buf, size_t size)
 {
-        pr_info("AMD microcode update via /dev/cpu/microcode not supported\n");
        return UCODE_ERROR;
 }
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 5fa553babe56..e385214711cb 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -29,6 +29,7 @@
 #include <linux/ftrace_event.h>
 #include <linux/slab.h>
+#include <asm/perf_event.h>
 #include <asm/tlbflush.h>
 #include <asm/desc.h>
 #include <asm/kvm_para.h>
@@ -575,6 +576,8 @@ static void svm_hardware_disable(void *garbage)
                wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
        cpu_svm_disable();
+        amd_pmu_disable_virt();
 }
 static int svm_hardware_enable(void *garbage)
@@ -622,6 +625,8 @@ static int svm_hardware_enable(void *garbage)
        svm_init_erratum_383();
+        amd_pmu_enable_virt();
        return 0;
 }
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 12eb07bfb267..4172af8ceeb3 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -1141,7 +1141,9 @@ asmlinkage void __init xen_start_kernel(void)
        /* Prevent unwanted bits from being set in PTEs. */
        __supported_pte_mask &= ~_PAGE_GLOBAL;
+#if 0
        if (!xen_initial_domain())
+#endif
                __supported_pte_mask &= ~(_PAGE_PWT | _PAGE_PCD);
        __supported_pte_mask |= _PAGE_IOMAP;
@@ -1204,10 +1206,6 @@ asmlinkage void __init xen_start_kernel(void)
        pgd = (pgd_t *)xen_start_info->pt_base;
-        if (!xen_initial_domain())
-                __supported_pte_mask &= ~(_PAGE_PWT | _PAGE_PCD);
-        __supported_pte_mask |= _PAGE_IOMAP;
        /* Don't do the full vcpu_info placement stuff until we have a
           possible map and a non-dummy shared_info. */
        per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0];
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index 58a0e46c404d..95c1cf60c669 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -415,13 +415,13 @@ static pteval_t iomap_pte(pteval_t val)
 static pteval_t xen_pte_val(pte_t pte)
 {
        pteval_t pteval = pte.pte;
+#if 0
        /* If this is a WC pte, convert back from Xen WC to Linux WC */
        if ((pteval & (_PAGE_PAT | _PAGE_PCD | _PAGE_PWT)) == _PAGE_PAT) {
                WARN_ON(!pat_enabled);
                pteval = (pteval & ~_PAGE_PAT) | _PAGE_PWT;
        }
+#endif
        if (xen_initial_domain() && (pteval & _PAGE_IOMAP))
                return pteval;
@@ -463,7 +463,7 @@ void xen_set_pat(u64 pat)
 static pte_t xen_make_pte(pteval_t pte)
 {
        phys_addr_t addr = (pte & PTE_PFN_MASK);
+#if 0
        /* If Linux is trying to set a WC pte, then map to the Xen WC.
         * If _PAGE_PAT is set, then it probably means it is really
         * _PAGE_PSE, so avoid fiddling with the PAT mapping and hope
@@ -476,7 +476,7 @@ static pte_t xen_make_pte(pteval_t pte)
                if ((pte & (_PAGE_PCD | _PAGE_PWT)) == _PAGE_PWT)
                        pte = (pte & ~(_PAGE_PCD | _PAGE_PWT)) | _PAGE_PAT;
        }
+#endif
        /*
         * Unprivileged domains are allowed to do IOMAPpings for
         * PCI passthrough, but not map ISA space.  The ISA