65 files changed, 1842 insertions, 148 deletions

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 2498cba723d4..2be254709dcb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -3,6 +3,7 @@ ifeq ($(CONFIG_OF),y)
 # Keep at91 dtb files sorted alphabetically for each SoC
 # rm9200
 dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb
+dtb-$(CONFIG_ARCH_AT91) += mpa1600.dtb
 # sam9260
 dtb-$(CONFIG_ARCH_AT91) += animeo_ip.dtb
 dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb
@@ -26,6 +27,7 @@ dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
 # sam9n12
 dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
 # sam9x5
+dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index e34b280ce6ec..6403acdbb75f 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -94,5 +94,22 @@
                                 spi-max-frequency = <50000000>;
                         };
                 };
+
+                pcie-controller {
+                        status = "okay";
+                        /*
+                         * The two PCIe units are accessible through
+                         * both standard PCIe slots and mini-PCIe
+                         * slots on the board.
+                         */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@2,0 {
+                                /* Port 1, Lane 0 */
+                                status = "okay";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index dd0c57dd9f30..70effc617123 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -33,6 +33,43 @@
                         clock-frequency = <600000000>;
                         status = "okay";
                 };
+
+                pinctrl {
+                        pwr_led_pin: pwr-led-pin {
+                                marvell,pins = "mpp63";
+                                marvell,function = "gpo";
+                        };
+
+                        stat_led_pins: stat-led-pins {
+                                marvell,pins = "mpp64", "mpp65";
+                                marvell,function = "gpio";
+                        };
+                };
+
+                gpio_leds {
+                        compatible = "gpio-leds";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pwr_led_pin &stat_led_pins>;
+
+                        green_pwr_led {
+                                label = "mirabox:green:pwr";
+                                gpios = <&gpio1 31 1>;
+                                linux,default-trigger = "heartbeat";
+                        };
+
+                        blue_stat_led {
+                                label = "mirabox:blue:stat";
+                                gpios = <&gpio2 0 1>;
+                                linux,default-trigger = "cpu0";
+                        };
+
+                        green_stat_led {
+                                label = "mirabox:green:stat";
+                                gpios = <&gpio2 1 1>;
+                                default-state = "off";
+                        };
+                };
+
                 mdio {
                         phy0: ethernet-phy@0 {
                                 reg = <0>;
@@ -70,5 +107,32 @@
                 usb@d0051000 {
                         status = "okay";
                 };
+
+                i2c@d0011000 {
+                        status = "okay";
+                        clock-frequency = <100000>;
+                        pca9505: pca9505@25 {
+                                compatible = "nxp,pca9505";
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                reg = <0x25>;
+                        };
+                };
+
+                pcie-controller {
+                        status = "okay";
+
+                        /* Internal mini-PCIe connector */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+
+                        /* Connected on the PCB to a USB 3.0 XHCI controller */
+                        pcie@2,0 {
+                                /* Port 1, Lane 0 */
+                                status = "okay";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 070bba4f2585..516dec31b469 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -73,4 +73,15 @@
                         status = "okay";
                 };
         };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button@1 {
+                        label = "Software Button";
+                        linux,code = <116>;
+                        gpios = <&gpio0 6 1>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 5b708208b607..758c4ea90344 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -181,6 +181,51 @@
                         clocks = <&coreclk 0>;
                         status = "disabled";
                 };
+
+                devbus-bootcs@d0010400 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <0xd0010400 0x8>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+
+                devbus-cs0@d0010408 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <0xd0010408 0x8>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+
+                devbus-cs1@d0010410 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <0xd0010410 0x8>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+
+                devbus-cs2@d0010418 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <0xd0010418 0x8>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+
+                devbus-cs3@d0010420 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <0xd0010420 0x8>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 8188d138020e..9cf60b2ce864 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -153,5 +153,63 @@
                         clocks = <&coreclk 0>;
                 };
 
+                thermal@d0018300 {
+                        compatible = "marvell,armada370-thermal";
+                        reg = <0xd0018300 0x4
+                               0xd0018304 0x4>;
+                        status = "okay";
+                };
+
+                pcie-controller {
+                        compatible = "marvell,armada-370-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        reg = <0xd0040000 0x2000>, <0xd0080000 0x2000>;
+
+                        reg-names = "pcie0.0", "pcie1.0";
+
+                        ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
+                                  0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */
+                                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 58>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 62>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 9>;
+                                status = "disabled";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index e83505e4c236..54cc5bb705fb 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -121,5 +121,38 @@
                                 spi-max-frequency = <20000000>;
                         };
                 };
+
+                pcie-controller {
+                        status = "okay";
+
+                        /*
+                         * All 6 slots are physically present as
+                         * standard PCIe slots on the board.
+                         */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@2,0 {
+                                /* Port 0, Lane 1 */
+                                status = "okay";
+                        };
+                        pcie@3,0 {
+                                /* Port 0, Lane 2 */
+                                status = "okay";
+                        };
+                        pcie@4,0 {
+                                /* Port 0, Lane 3 */
+                                status = "okay";
+                        };
+                        pcie@9,0 {
+                                /* Port 2, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@10,0 {
+                                /* Port 3, Lane 0 */
+                                status = "okay";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 1c8afe2ffebc..04f28a712b98 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -109,5 +109,55 @@
                                 spi-max-frequency = <108000000>;
                         };
                 };
+
+                devbus-bootcs@d0010400 {
+                        status = "okay";
+                        ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
+
+                        /* Device Bus parameters are required */
+
+                        /* Read parameters */
+                        devbus,bus-width    = <8>;
+                        devbus,turn-off-ps  = <60000>;
+                        devbus,badr-skew-ps = <0>;
+                        devbus,acc-first-ps = <124000>;
+                        devbus,acc-next-ps  = <248000>;
+                        devbus,rd-setup-ps  = <0>;
+                        devbus,rd-hold-ps   = <0>;
+
+                        /* Write parameters */
+                        devbus,sync-enable = <0>;
+                        devbus,wr-high-ps  = <60000>;
+                        devbus,wr-low-ps   = <60000>;
+                        devbus,ale-wr-ps   = <60000>;
+
+                        /* NOR 16 MiB */
+                        nor@0 {
+                                compatible = "cfi-flash";
+                                reg = <0 0x1000000>;
+                                bank-width = <2>;
+                        };
+                };
+
+                pcie-controller {
+                        status = "okay";
+
+                        /*
+                         * The 3 slots are physically present as
+                         * standard PCIe slots on the board.
+                         */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@9,0 {
+                                /* Port 2, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@10,0 {
+                                /* Port 3, Lane 0 */
+                                status = "okay";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index f56c40599f5b..c2c78459a4d4 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -76,5 +76,109 @@
                         #interrupts-cells = <2>;
                         interrupts = <87>, <88>, <89>;
                 };
+
+                /*
+                 * MV78230 has 2 PCIe units Gen2.0: One unit can be
+                 * configured as x4 or quad x1 lanes. One unit is
+                 * x4/x1.
+                 */
+                pcie-controller {
+                        compatible = "marvell,armada-xp-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
+                                  0x82000000 0 0xd0042000 0xd0042000 0 0x00002000   /* Port 2.0 registers */
+                                  0x82000000 0 0xd0044000 0xd0044000 0 0x00002000   /* Port 0.1 registers */
+                                  0x82000000 0 0xd0048000 0xd0048000 0 0x00002000   /* Port 0.2 registers */
+                                  0x82000000 0 0xd004c000 0xd004c000 0 0x00002000   /* Port 0.3 registers */
+                                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 58>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 59>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <1>;
+                                clocks = <&gateclk 6>;
+                                status = "disabled";
+                        };
+
+                        pcie@3,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>;
+                                reg = <0x1800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 60>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <2>;
+                                clocks = <&gateclk 7>;
+                                status = "disabled";
+                        };
+
+                        pcie@4,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>;
+                                reg = <0x2000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 61>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <3>;
+                                clocks = <&gateclk 8>;
+                                status = "disabled";
+                        };
+
+                        pcie@9,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>;
+                                reg = <0x4800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 99>;
+                                marvell,pcie-port = <2>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 26>;
+                                status = "disabled";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index f8f2b787d2b0..885bf229eef7 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -96,5 +96,127 @@
                                 clocks = <&gateclk 1>;
                                 status = "disabled";
                 };
+
+                /*
+                 * MV78260 has 3 PCIe units Gen2.0: Two units can be
+                 * configured as x4 or quad x1 lanes. One unit is
+                 * x4/x1.
+                 */
+                pcie-controller {
+                        compatible = "marvell,armada-xp-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
+                                  0x82000000 0 0xd0042000 0xd0042000 0 0x00002000   /* Port 2.0 registers */
+                                  0x82000000 0 0xd0044000 0xd0044000 0 0x00002000   /* Port 0.1 registers */
+                                  0x82000000 0 0xd0048000 0xd0048000 0 0x00002000   /* Port 0.2 registers */
+                                  0x82000000 0 0xd004c000 0xd004c000 0 0x00002000   /* Port 0.3 registers */
+                                  0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */
+                                  0x82000000 0 0xd0082000 0xd0082000 0 0x00002000   /* Port 3.0 registers */
+                                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 58>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 59>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <1>;
+                                clocks = <&gateclk 6>;
+                                status = "disabled";
+                        };
+
+                        pcie@3,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>;
+                                reg = <0x1800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 60>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <2>;
+                                clocks = <&gateclk 7>;
+                                status = "disabled";
+                        };
+
+                        pcie@4,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>;
+                                reg = <0x2000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 61>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <3>;
+                                clocks = <&gateclk 8>;
+                                status = "disabled";
+                        };
+
+                        pcie@9,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>;
+                                reg = <0x4800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 99>;
+                                marvell,pcie-port = <2>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 26>;
+                                status = "disabled";
+                        };
+
+                        pcie@10,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0082000 0 0x2000>;
+                                reg = <0x5000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 103>;
+                                marvell,pcie-port = <3>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 27>;
+                                status = "disabled";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 936c25dc32b0..23a5ac4490a8 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -111,5 +111,193 @@
                                 clocks = <&gateclk 1>;
                                 status = "disabled";
                 };
+
+                /*
+                 * MV78460 has 4 PCIe units Gen2.0: Two units can be
+                 * configured as x4 or quad x1 lanes. Two units are
+                 * x4/x1.
+                 */
+                pcie-controller {
+                        compatible = "marvell,armada-xp-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
+                                  0x82000000 0 0xd0042000 0xd0042000 0 0x00002000   /* Port 2.0 registers */
+                                  0x82000000 0 0xd0044000 0xd0044000 0 0x00002000   /* Port 0.1 registers */
+                                  0x82000000 0 0xd0048000 0xd0048000 0 0x00002000   /* Port 0.2 registers */
+                                  0x82000000 0 0xd004c000 0xd004c000 0 0x00002000   /* Port 0.3 registers */
+                                  0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */
+                                  0x82000000 0 0xd0082000 0xd0082000 0 0x00002000   /* Port 3.0 registers */
+                                  0x82000000 0 0xd0084000 0xd0084000 0 0x00002000   /* Port 1.1 registers */
+                                  0x82000000 0 0xd0088000 0xd0088000 0 0x00002000   /* Port 1.2 registers */
+                                  0x82000000 0 0xd008c000 0xd008c000 0 0x00002000   /* Port 1.3 registers */
+                                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 58>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 59>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <1>;
+                                clocks = <&gateclk 6>;
+                                status = "disabled";
+                        };
+
+                        pcie@3,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
+                                reg = <0x1800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 60>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <2>;
+                                clocks = <&gateclk 7>;
+                                status = "disabled";
+                        };
+
+                        pcie@4,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
+                                reg = <0x2000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 61>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <3>;
+                                clocks = <&gateclk 8>;
+                                status = "disabled";
+                        };
+
+                        pcie@5,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
+                                reg = <0x2800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 62>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 9>;
+                                status = "disabled";
+                        };
+
+                        pcie@6,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
+                                reg = <0x3000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 63>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <1>;
+                                clocks = <&gateclk 10>;
+                                status = "disabled";
+                        };
+
+                        pcie@7,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
+                                reg = <0x3800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 64>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <2>;
+                                clocks = <&gateclk 11>;
+                                status = "disabled";
+                        };
+
+                        pcie@8,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
+                                reg = <0x4000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 65>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <3>;
+                                clocks = <&gateclk 12>;
+                                status = "disabled";
+                        };
+                        pcie@9,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
+                                reg = <0x4800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 99>;
+                                marvell,pcie-port = <2>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 26>;
+                                status = "disabled";
+                        };
+
+                        pcie@10,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
+                                reg = <0x5000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 103>;
+                                marvell,pcie-port = <3>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 27>;
+                                status = "disabled";
+                        };
+                };
         };
  };
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 3818a82176a2..9d04f04d4e39 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -139,5 +139,43 @@
                 usb@d0051000 {
                         status = "okay";
                 };
+
+                devbus-bootcs@d0010400 {
+                        status = "okay";
+                        ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
+
+                        /* Device Bus parameters are required */
+
+                        /* Read parameters */
+                        devbus,bus-width    = <8>;
+                        devbus,turn-off-ps  = <60000>;
+                        devbus,badr-skew-ps = <0>;
+                        devbus,acc-first-ps = <124000>;
+                        devbus,acc-next-ps  = <248000>;
+                        devbus,rd-setup-ps  = <0>;
+                        devbus,rd-hold-ps   = <0>;
+
+                        /* Write parameters */
+                        devbus,sync-enable = <0>;
+                        devbus,wr-high-ps  = <60000>;
+                        devbus,wr-low-ps   = <60000>;
+                        devbus,ale-wr-ps   = <60000>;
+
+                        /* NOR 128 MiB */
+                        nor@0 {
+                                compatible = "cfi-flash";
+                                reg = <0 0x8000000>;
+                                bank-width = <2>;
+                        };
+                };
+
+                pcie-controller {
+                        status = "okay";
+                        /* Internal mini-PCIe connector */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index ca00d8326c87..29dfeb6d4a26 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -151,5 +151,11 @@
                         status = "disabled";
                 };
 
+                thermal@d00182b0 {
+                        compatible = "marvell,armadaxp-thermal";
+                        reg = <0xd00182b0 0x4
+                               0xd00184d0 0x4>;
+                        status = "okay";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts
new file mode 100644
index 000000000000..c7aebba4e8e7
--- /dev/null
+++ b/arch/arm/boot/dts/at91-ariag25.dts
@@ -0,0 +1,171 @@
+/*
+ * at91-ariag25.dts - Device Tree file for Acme Systems Aria G25 (AT91SAM9G25 based)
+ *
+ * Copyright (C) 2013 Douglas Gilbert <dgilbert@interlog.com>,
+ *                    Robert Nelson <robertcnelson@gmail.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9g25.dtsi"
+
+/ {
+        model = "Acme Systems Aria G25";
+        compatible = "acme,ariag25", "atmel,at91sam9x5ek",
+                     "atmel,at91sam9x5", "atmel,at91sam9";
+
+        aliases {
+                serial0 = &dbgu;
+                serial1 = &usart0;
+                serial2 = &usart1;
+                serial3 = &usart2;
+                serial4 = &usart3;
+                serial5 = &uart0;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait";
+        };
+
+        memory {
+                /* 128 MB, change this for 256 MB revision */
+                reg = <0x20000000 0x8000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        mmc0: mmc@f0008000 {
+                                /* N.B. Aria has no SD card detect (CD), assumed present */
+
+                                pinctrl-0 = <
+                                        &pinctrl_mmc0_slot0_clk_cmd_dat0
+                                        &pinctrl_mmc0_slot0_dat1_3>;
+                                status = "okay";
+                                slot@0 {
+                                        reg = <0>;
+                                        bus-width = <4>;
+                                };
+                        };
+
+                        i2c0: i2c@f8010000 {
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@f8014000 {
+                                status = "okay";
+                        };
+
+                        /* TWD2+TCLK2 hidden behind ethernet, so no i2c2 */
+
+                        usart0: serial@f801c000 {
+                                pinctrl-0 = <&pinctrl_usart0
+                                             &pinctrl_usart0_rts
+                                             &pinctrl_usart0_cts>;
+                                status = "okay";
+                        };
+
+                        usart1: serial@f8020000 {
+                                pinctrl-0 = <&pinctrl_usart1
+                                             /* &pinctrl_usart1_rts */
+                                             /* &pinctrl_usart1_cts */
+                                            >;
+                                status = "okay";
+                        };
+
+                        usart2: serial@f8024000 {
+                                /* cannot activate RTS2+CTS2, clash with
+                                 * ethernet on PB0 and PB1 */
+                                pinctrl-0 = <&pinctrl_usart2>;
+                                status = "okay";
+                        };
+
+                        usart3: serial@f8028000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8028000 0x200>;
+                                interrupts = <8 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usart3
+                                             /* &pinctrl_usart3_rts */
+                                             /* &pinctrl_usart3_cts */
+                                            >;
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@f802c000 {
+                                phy-mode = "rmii";
+                                /*
+                                 * following can be overwritten by bootloader:
+                                 * for example u-boot 'ftd set' command
+                                 */
+                                local-mac-address = [00 00 00 00 00 00];
+                                status = "okay";
+                        };
+
+                        uart0: serial@f8040000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8040000 0x200>;
+                                interrupts = <15 4 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart0>;
+                                status = "okay";
+                        };
+
+                        adc0: adc@f804c000 {
+                                status = "okay";
+                                atmel,adc-channels-used = <0xf>;
+                                atmel,adc-num-channels = <4>;
+                        };
+
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+
+                        pinctrl@fffff400 {
+                                w1_0 {
+                                        pinctrl_w1_0: w1_0-0 {
+                                                atmel,pins = <0 21 0x0 0x1>; /* PA21 PIO, pull-up */
+                                        };
+                                };
+                        };
+                };
+
+                usb0: ohci@00600000 {
+                        status = "okay";
+                        num-ports = <3>;
+                };
+
+                usb1: ehci@00700000 {
+                        status = "okay";
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                /* little green LED in middle of Aria G25 module */
+                aria_led {
+                        label = "aria_led";
+                        gpios = <&pioB 8 0>; /* PB8 */
+                        linux,default-trigger = "heartbeat";
+                };
+
+        };
+
+        onewire@0 {
+                compatible = "w1-gpio";
+                gpios = <&pioA 21 1>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_w1_0>;
+        };
+};
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index b0268a5f4b4e..5d3ed5aafc69 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -29,6 +29,7 @@
                 gpio3 = &pioD;
                 tcb0 = &tcb0;
                 tcb1 = &tcb1;
+                i2c0 = &i2c0;
                 ssc0 = &ssc0;
                 ssc1 = &ssc1;
                 ssc2 = &ssc2;
@@ -91,6 +92,17 @@
                                 interrupts = <20 4 0 21 4 0 22 4 0>;
                         };
 
+                        i2c0: i2c@fffb8000 {
+                                compatible = "atmel,at91rm9200-i2c";
+                                reg = <0xfffb8000 0x4000>;
+                                interrupts = <12 4 6>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_twi>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+
                         mmc0: mmc@fffb4000 {
                                 compatible = "atmel,hsmci";
                                 reg = <0xfffb4000 0x4000>;
@@ -365,6 +377,20 @@
                                         };
                                 };
 
+                                twi {
+                                        pinctrl_twi: twi-0 {
+                                                atmel,pins =
+                                                        <0 25 0x1 0x2   /* PA25 periph A with multi drive */
+                                                         0 26 0x1 0x2>; /* PA26 periph A with multi drive */
+                                        };
+
+                                        pinctrl_twi_gpio: twi_gpio-0 {
+                                                atmel,pins =
+                                                        <0 25 0x0 0x2   /* PA25 GPIO with multi drive */
+                                                         0 26 0x0 0x2>; /* PA26 GPIO with multi drive */
+                                        };
+                                };
+
                                 pioA: gpio@fffff400 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff400 0x200>;
@@ -500,6 +526,8 @@
                 i2c-gpio,sda-open-drain;
                 i2c-gpio,scl-open-drain;
                 i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_twi_gpio>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 status = "disabled";
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index cb7bcc51608d..3e2adfbe3d20 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -158,8 +158,8 @@
                                 usart1 {
                                         pinctrl_usart1: usart1-0 {
                                                 atmel,pins =
-                                                        <2 6 0x1 0x1    /* PB6 periph A with pullup */
-                                                         2 7 0x1 0x0>;  /* PB7 periph A */
+                                                        <1 6 0x1 0x1    /* PB6 periph A with pullup */
+                                                         1 7 0x1 0x0>;  /* PB7 periph A */
                                         };
 
                                         pinctrl_usart1_rts: usart1_rts-0 {
@@ -194,18 +194,18 @@
                                 usart3 {
                                         pinctrl_usart3: usart3-0 {
                                                 atmel,pins =
-                                                        <2 10 0x1 0x1   /* PB10 periph A with pullup */
-                                                         2 11 0x1 0x0>; /* PB11 periph A */
+                                                        <1 10 0x1 0x1   /* PB10 periph A with pullup */
+                                                         1 11 0x1 0x0>; /* PB11 periph A */
                                         };
 
                                         pinctrl_usart3_rts: usart3_rts-0 {
                                                 atmel,pins =
-                                                        <3 8 0x2 0x0>;  /* PB8 periph B */
+                                                        <2 8 0x2 0x0>;  /* PC8 periph B */
                                         };
 
                                         pinctrl_usart3_cts: usart3_cts-0 {
                                                 atmel,pins =
-                                                        <3 10 0x2 0x0>; /* PB10 periph B */
+                                                        <2 10 0x2 0x0>; /* PC10 periph B */
                                         };
                                 };
 
@@ -220,8 +220,8 @@
                                 uart1 {
                                         pinctrl_uart1: uart1-0 {
                                                 atmel,pins =
-                                                        <2 12 0x1 0x1   /* PB12 periph A with pullup */
-                                                         2 13 0x1 0x0>; /* PB13 periph A */
+                                                        <1 12 0x1 0x1   /* PB12 periph A with pullup */
+                                                         1 13 0x1 0x0>; /* PB13 periph A */
                                         };
                                 };
 
@@ -484,6 +484,9 @@
                                 atmel,adc-drdy-mask = <0x10000>;
                                 atmel,adc-status-register = <0x1c>;
                                 atmel,adc-trigger-register = <0x04>;
+                                atmel,adc-res = <8 10>;
+                                atmel,adc-res-names = "lowres", "highres";
+                                atmel,adc-use-res = "highres";
 
                                 trigger@0 {
                                         trigger-name = "timer-counter-0";
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 1eb08728f527..aa0e184336a1 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -155,8 +155,6 @@
 
         gpio_keys {
                 compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
 
                 left_click {
                         label = "left_click";
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi
index fbe7a7089c2a..28467fd6bf96 100644
--- a/arch/arm/boot/dts/at91sam9g15.dtsi
+++ b/arch/arm/boot/dts/at91sam9g15.dtsi
@@ -10,7 +10,7 @@
 
 / {
         model = "Atmel AT91SAM9G15 SoC";
-        compatible = "atmel, at91sam9g15, atmel,at91sam9x5";
+        compatible = "atmel,at91sam9g15", "atmel,at91sam9x5";
 
         ahb {
                 apb {
diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts
index 86dd3f6d938f..5427b2dba87e 100644
--- a/arch/arm/boot/dts/at91sam9g15ek.dts
+++ b/arch/arm/boot/dts/at91sam9g15ek.dts
@@ -11,6 +11,6 @@
 /include/ "at91sam9x5ek.dtsi"
 
 / {
-        model = "Atmel AT91SAM9G25-EK";
+        model = "Atmel AT91SAM9G15-EK";
         compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
 };
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index da15e83e7f17..e041b72216b1 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -167,8 +167,6 @@
 
         gpio_keys {
                 compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
 
                 btn3 {
                         label = "Button 3";
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
index 05a718fb83c4..5fd32df03f25 100644
--- a/arch/arm/boot/dts/at91sam9g25.dtsi
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -10,7 +10,7 @@
 
 / {
         model = "Atmel AT91SAM9G25 SoC";
-        compatible = "atmel, at91sam9g25, atmel,at91sam9x5";
+        compatible = "atmel,at91sam9g25", "atmel,at91sam9x5";
 
         ahb {
                 apb {
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index c5ab16fba059..a1c511fecdc1 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -13,4 +13,13 @@
 / {
         model = "Atmel AT91SAM9G25-EK";
         compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+
+        ahb {
+                apb {
+                        macb0: ethernet@f802c000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
index f9d14a722794..d6fa8af50724 100644
--- a/arch/arm/boot/dts/at91sam9g35.dtsi
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -10,7 +10,7 @@
 
 / {
         model = "Atmel AT91SAM9G35 SoC";
-        compatible = "atmel, at91sam9g35, atmel,at91sam9x5";
+        compatible = "atmel,at91sam9g35", "atmel,at91sam9x5";
 
         ahb {
                 apb {
diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts
index 95944bdd798d..6f58ab8d21f5 100644
--- a/arch/arm/boot/dts/at91sam9g35ek.dts
+++ b/arch/arm/boot/dts/at91sam9g35ek.dts
@@ -13,4 +13,13 @@
 / {
         model = "Atmel AT91SAM9G35-EK";
         compatible = "atmel,at91sam9g35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+
+        ahb {
+                apb {
+                        macb0: ethernet@f802c000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 6b1d4cab24c2..0fa28af229ed 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -484,6 +484,9 @@
                                 atmel,adc-drdy-mask = <0x10000>;
                                 atmel,adc-status-register = <0x1c>;
                                 atmel,adc-trigger-register = <0x08>;
+                                atmel,adc-res = <8 10>;
+                                atmel,adc-res-names = "lowres", "highres";
+                                atmel,adc-use-res = "highres";
 
                                 trigger@0 {
                                         trigger-name = "external-rising";
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 20c31913c270..c795bfbba05d 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -162,8 +162,6 @@
 
         gpio_keys {
                 compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
 
                 left_click {
                         label = "left_click";
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index d400f8de4387..7117c057deb7 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -104,8 +104,6 @@
 
         gpio_keys {
                 compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
 
                 enter {
                         label = "Enter";
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
index 54eb33ba6d22..9ac2bc2b4f07 100644
--- a/arch/arm/boot/dts/at91sam9x25.dtsi
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -10,7 +10,7 @@
 
 / {
         model = "Atmel AT91SAM9X25 SoC";
-        compatible = "atmel, at91sam9x25, atmel,at91sam9x5";
+        compatible = "atmel,at91sam9x25", "atmel,at91sam9x5";
 
         ahb {
                 apb {
diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts
index af907eaa1f25..3b40d11d65e7 100644
--- a/arch/arm/boot/dts/at91sam9x25ek.dts
+++ b/arch/arm/boot/dts/at91sam9x25ek.dts
@@ -13,4 +13,18 @@
 / {
         model = "Atmel AT91SAM9G25-EK";
         compatible = "atmel,at91sam9x25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+
+        ahb {
+                apb {
+                        macb0: ethernet@f802c000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        macb1: ethernet@f8030000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
index fb102d6126ce..ba67d83d17ac 100644
--- a/arch/arm/boot/dts/at91sam9x35.dtsi
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -10,7 +10,7 @@
 
 / {
         model = "Atmel AT91SAM9X35 SoC";
-        compatible = "atmel, at91sam9x35, atmel,at91sam9x5";
+        compatible = "atmel,at91sam9x35", "atmel,at91sam9x5";
 
         ahb {
                 apb {
diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts
index 5ccb607b5414..6ad19a0d5424 100644
--- a/arch/arm/boot/dts/at91sam9x35ek.dts
+++ b/arch/arm/boot/dts/at91sam9x35ek.dts
@@ -13,4 +13,13 @@
 / {
         model = "Atmel AT91SAM9X35-EK";
         compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+
+        ahb {
+                apb {
+                        macb0: ethernet@f802c000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index a98c0d50fbbe..284bf24815bb 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -343,6 +343,54 @@
                                         };
                                 };
 
+                                i2c0 {
+                                        pinctrl_i2c0: i2c0-0 {
+                                                atmel,pins =
+                                                        <0 30 0x1 0x0   /* PA30 periph A I2C0 data */
+                                                         0 31 0x1 0x0>; /* PA31 periph A I2C0 clock */
+                                        };
+                                };
+
+                                i2c1 {
+                                        pinctrl_i2c1: i2c1-0 {
+                                                atmel,pins =
+                                                        <2 0 0x3 0x0    /* PC0 periph C I2C1 data */
+                                                         2 1 0x3 0x0>;  /* PC1 periph C I2C1 clock */
+                                        };
+                                };
+
+                                i2c2 {
+                                        pinctrl_i2c2: i2c2-0 {
+                                                atmel,pins =
+                                                        <1 4 0x2 0x0    /* PB4 periph B I2C2 data */
+                                                         1 5 0x2 0x0>;  /* PB5 periph B I2C2 clock */
+                                        };
+                                };
+
+                                i2c_gpio0 {
+                                        pinctrl_i2c_gpio0: i2c_gpio0-0 {
+                                                atmel,pins =
+                                                        <0 30 0x0 0x2   /* PA30 gpio multidrive I2C0 data */
+                                                         0 31 0x0 0x2>; /* PA31 gpio multidrive I2C0 clock */
+                                        };
+                                };
+
+                                i2c_gpio1 {
+                                        pinctrl_i2c_gpio1: i2c_gpio1-0 {
+                                                atmel,pins =
+                                                        <2 0 0x0 0x2    /* PC0 gpio multidrive I2C1 data */
+                                                         2 1 0x0 0x2>;  /* PC1 gpio multidrive I2C1 clock */
+                                        };
+                                };
+
+                                i2c_gpio2 {
+                                        pinctrl_i2c_gpio2: i2c_gpio2-0 {
+                                                atmel,pins =
+                                                        <1 4 0x0 0x2    /* PB4 gpio multidrive I2C2 data */
+                                                         1 5 0x0 0x2>;  /* PB5 gpio multidrive I2C2 clock */
+                                        };
+                                };
+
                                 pioA: gpio@fffff400 {
                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                         reg = <0xfffff400 0x200>;
@@ -471,6 +519,8 @@
                                 interrupts = <9 4 6>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c0>;
                                 status = "disabled";
                         };
 
@@ -480,6 +530,8 @@
                                 interrupts = <10 4 6>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c1>;
                                 status = "disabled";
                         };
 
@@ -489,6 +541,8 @@
                                 interrupts = <11 4 6>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c2>;
                                 status = "disabled";
                         };
 
@@ -505,6 +559,9 @@
                                 atmel,adc-drdy-mask = <0x1000000>;
                                 atmel,adc-status-register = <0x30>;
                                 atmel,adc-trigger-register = <0xc0>;
+                                atmel,adc-res = <8 10>;
+                                atmel,adc-res-names = "lowres", "highres";
+                                atmel,adc-use-res = "highres";
 
                                 trigger@0 {
                                         trigger-name = "external-rising";
@@ -529,6 +586,13 @@
                                         trigger-value = <0x6>;
                                 };
                         };
+
+                        rtc@fffffeb0 {
+                                compatible = "atmel,at91rm9200-rtc";
+                                reg = <0xfffffeb0 0x40>;
+                                interrupts = <1 4 7>;
+                                status = "disabled";
+                        };
                 };
 
                 nand0: nand@40000000 {
@@ -577,6 +641,8 @@
                 i2c-gpio,delay-us = <2>;        /* ~100 kHz */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_i2c_gpio0>;
                 status = "disabled";
         };
 
@@ -590,6 +656,8 @@
                 i2c-gpio,delay-us = <2>;        /* ~100 kHz */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_i2c_gpio1>;
                 status = "disabled";
         };
 
@@ -603,6 +671,8 @@
                 i2c-gpio,delay-us = <2>;        /* ~100 kHz */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_i2c_gpio2>;
                 status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 4027ac7e4502..347a74a857f6 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -24,6 +24,16 @@
         };
 
         ahb {
+                apb {
+                        pinctrl@fffff400 {
+                                1wire_cm {
+                                        pinctrl_1wire_cm: 1wire_cm-0 {
+                                                atmel,pins = <1 18 0x0 0x2>; /* PB18 multidrive, conflicts with led */
+                                        };
+                                };
+                        };
+                };
+
                 nand0: nand@40000000 {
                         nand-bus-width = <8>;
                         nand-ecc-mode = "hw";
@@ -74,4 +84,14 @@
                         gpios = <&pioD 21 0>;
                 };
         };
+
+        1wire_cm {
+                compatible = "w1-gpio";
+                gpios = <&pioB 18 0>;
+                linux,open-drain;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_1wire_cm>;
+                status = "okay";
+        };
+
 };
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index 8a7cf1d9cf5d..8b5832af6d05 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -13,7 +13,7 @@
         compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
 
         chosen {
-                bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
+                bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
         };
 
         ahb {
@@ -52,23 +52,10 @@
                                 status = "okay";
                         };
 
-                        macb0: ethernet@f802c000 {
-                                phy-mode = "rmii";
-                                status = "okay";
-                        };
-
                         i2c0: i2c@f8010000 {
                                 status = "okay";
                         };
 
-                        i2c1: i2c@f8014000 {
-                                status = "okay";
-                        };
-
-                        i2c2: i2c@f8018000 {
-                                status = "okay";
-                        };
-
                         pinctrl@fffff400 {
                                 mmc0 {
                                         pinctrl_board_mmc0: mmc0-board {
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 7e0481e2441a..f0052dccf9a8 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -34,6 +34,11 @@
                         reg = <0x7e100000 0x28>;
                 };
 
+                rng {
+                        compatible = "brcm,bcm2835-rng";
+                        reg = <0x7e104000 0x10>;
+                };
+
                 uart@20201000 {
                         compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
                         reg = <0x7e201000 0x1000>;
@@ -64,6 +69,16 @@
                         #interrupt-cells = <2>;
                 };
 
+                spi: spi@20204000 {
+                        compatible = "brcm,bcm2835-spi";
+                        reg = <0x7e204000 0x1000>;
+                        interrupts = <2 22>;
+                        clocks = <&clk_spi>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
                 i2c0: i2c@20205000 {
                         compatible = "brcm,bcm2835-i2c";
                         reg = <0x7e205000 0x1000>;
@@ -107,5 +122,12 @@
                         #clock-cells = <0>;
                         clock-frequency = <250000000>;
                 };
+
+                clk_spi: spi {
+                        compatible = "fixed-clock";
+                        reg = <2>;
+                        #clock-cells = <0>;
+                        clock-frequency = <250000000>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index f7509cafc377..6cab46849cdb 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -50,6 +50,11 @@
                         #clock-cells = <1>;
                 };
 
+                thermal: thermal@d001c {
+                        compatible = "marvell,dove-thermal";
+                        reg = <0xd001c 0x0c>, <0xd005c 0x08>;
+                };
+
                 uart0: serial@12000 {
                         compatible = "ns16550a";
                         reg = <0x12000 0x100>;
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index 192cf76fbf93..23991e45bc55 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -49,6 +49,12 @@
                         };
                 };
 
+                thermal@10078 {
+                        compatible = "marvell,kirkwood-thermal";
+                        reg = <0x10078 0x4>;
+                        status = "okay";
+                };
+
                 i2c@11100 {
                         compatible = "marvell,mv64xxx-i2c";
                         reg = <0x11100 0x20>;
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 9555a86297c2..44fd97dfc1f3 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -69,6 +69,10 @@
                         status = "okay";
                         nr-ports = <1>;
                 };
+
+                mvsdio@90000 {
+                        status = "okay";
+                };
         };
 
         gpio-leds {
diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts
new file mode 100644
index 000000000000..317300875f34
--- /dev/null
+++ b/arch/arm/boot/dts/mpa1600.dts
@@ -0,0 +1,69 @@
+/*
+ * mpa1600.dts - Device Tree file for Phontech MPA 1600
+ *
+ *  Copyright (C) 2013 Joachim Eastwood <manabian@gmail.com>
+ *
+ * Licensed under GPLv2 only
+ */
+/dts-v1/;
+/include/ "at91rm9200.dtsi"
+
+/ {
+        model = "Phontech MPA 1600";
+        compatible = "phontech,mpa1600", "atmel,at91rm9200";
+
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <18432000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@fffbc000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        ssc0: ssc@fffd0000 {
+                                status = "okay";
+                        };
+
+                        ssc1: ssc@fffd4000 {
+                                status = "okay";
+                        };
+                };
+
+                usb0: ohci@00300000 {
+                        num-ports = <1>;
+                        status = "okay";
+                };
+        };
+
+        i2c@0 {
+                status = "okay";
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+
+                monitor_mute {
+                        label = "Monitor mute";
+                        gpios = <&pioC 1 1>;
+                        linux,code = <113>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index 8aad00f81ed9..f09133fd8105 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -69,6 +69,20 @@
                         status = "okay";
                 };
 
+                ehci@50000 {
+                        compatible = "marvell,orion-ehci";
+                        reg = <0x50000 0x1000>;
+                        interrupts = <17>;
+                        status = "disabled";
+                };
+
+                ehci@a0000 {
+                        compatible = "marvell,orion-ehci";
+                        reg = <0xa0000 0x1000>;
+                        interrupts = <12>;
+                        status = "disabled";
+                };
+
                 sata@80000 {
                         compatible = "marvell,orion-sata";
                         reg = <0x80000 0x5000>;
@@ -86,6 +100,25 @@
                         status = "disabled";
                 };
 
+                xor@60900 {
+                        compatible = "marvell,orion-xor";
+                        reg = <0x60900 0x100
+                               0x60b00 0x100>;
+                        status = "okay";
+
+                        xor00 {
+                              interrupts = <30>;
+                              dmacap,memcpy;
+                              dmacap,xor;
+                        };
+                        xor01 {
+                              interrupts = <31>;
+                              dmacap,memcpy;
+                              dmacap,xor;
+                              dmacap,memset;
+                        };
+                };
+
                 crypto@90000 {
                         compatible = "marvell,orion-crypto";
                         reg = <0x90000 0x10000>,
diff --git a/arch/arm/boot/dts/skeleton64.dtsi b/arch/arm/boot/dts/skeleton64.dtsi
new file mode 100644
index 000000000000..15994158a998
--- /dev/null
+++ b/arch/arm/boot/dts/skeleton64.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Skeleton device tree in the 64 bits version; the bare minimum
+ * needed to boot; just include and add a compatible value.  The
+ * bootloader will typically populate the memory node.
+ */
+
+/ {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        chosen { };
+        aliases { };
+        memory { device_type = "memory"; reg = <0 0>; };
+};
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 5cab82540437..b70fe0db6bb7 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -26,13 +26,37 @@
                 bootargs = "earlyprintk console=ttyS0,115200";
         };
 
-        soc {
-                uart0: uart@01c28000 {
-                        status = "okay";
+        soc@01c20000 {
+                pinctrl@01c20800 {
+                        led_pins_cubieboard: led_pins@0 {
+                                allwinner,pins = "PH20", "PH21";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <1>;
+                                allwinner,pull = <0>;
+                        };
                 };
 
-                uart1: uart@01c28400 {
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
                         status = "okay";
                 };
         };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_cubieboard>;
+
+                blue {
+                        label = "cubieboard::blue";
+                        gpios = <&pio 7 21 0>; /* LED1 */
+                };
+
+                green {
+                        label = "cubieboard::green";
+                        gpios = <&pio 7 20 0>; /* LED2 */
+                        linux,default-trigger = "heartbeat";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index f84549ad791e..b9efac100c85 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -22,8 +22,10 @@
                 bootargs = "earlyprintk console=ttyS0,115200";
         };
 
-        soc {
-                uart0: uart@01c28000 {
+        soc@01c20000 {
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
                         status = "okay";
                 };
         };
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
new file mode 100644
index 000000000000..4a7c35d6726a
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun4i-a10.dtsi"
+
+/ {
+        model = "PineRiver Mini X-Plus";
+        compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10";
+
+        chosen {
+                bootargs = "earlyprintk console=ttyS0,115200";
+        };
+
+        soc {
+                uart0: uart@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index f99f60dadf5d..5619a213da99 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -10,19 +10,180 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "sunxi.dtsi"
+/include/ "skeleton.dtsi"
 
 / {
+        interrupt-parent = <&intc>;
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a8";
+                };
+        };
+
         memory {
                 reg = <0x40000000 0x80000000>;
         };
 
-        soc {
-                pinctrl@01c20800 {
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                /*
+                 * This is a dummy clock, to be used as placeholder on
+                 * other mux clocks when a specific parent clock is not
+                 * yet implemented. It should be dropped when the driver
+                 * is complete.
+                 */
+                dummy: dummy {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <0>;
+                };
+
+                osc24M_fixed: osc24M_fixed {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+
+                osc24M: osc24M@01c20050 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-osc-clk";
+                        reg = <0x01c20050 0x4>;
+                        clocks = <&osc24M_fixed>;
+                };
+
+                osc32k: osc32k {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+
+                pll1: pll1@01c20000 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20000 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                /* dummy is 200M */
+                cpu: cpu@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-cpu-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
+                };
+
+                axi: axi@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-axi-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&cpu>;
+                };
+
+                axi_gates: axi_gates@01c2005c {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-axi-gates-clk";
+                        reg = <0x01c2005c 0x4>;
+                        clocks = <&axi>;
+                        clock-output-names = "axi_dram";
+                };
+
+                ahb: ahb@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-ahb-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&axi>;
+                };
+
+                ahb_gates: ahb_gates@01c20060 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-ahb-gates-clk";
+                        reg = <0x01c20060 0x8>;
+                        clocks = <&ahb>;
+                        clock-output-names = "ahb_usb0", "ahb_ehci0",
+                                "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
+                                "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+                                "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
+                                "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
+                                "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
+                                "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
+                                "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
+                                "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
+                                "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+                                "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+                };
+
+                apb0: apb0@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb0-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&ahb>;
+                };
+
+                apb0_gates: apb0_gates@01c20068 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-apb0-gates-clk";
+                        reg = <0x01c20068 0x4>;
+                        clocks = <&apb0>;
+                        clock-output-names = "apb0_codec", "apb0_spdif",
+                                "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
+                                "apb0_ir1", "apb0_keypad";
+                };
+
+                /* dummy is pll62 */
+                apb1_mux: apb1_mux@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-mux-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                };
+
+                apb1: apb1@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&apb1_mux>;
+                };
+
+                apb1_gates: apb1_gates@01c2006c {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-apb1-gates-clk";
+                        reg = <0x01c2006c 0x4>;
+                        clocks = <&apb1>;
+                        clock-output-names = "apb1_i2c0", "apb1_i2c1",
+                                "apb1_i2c2", "apb1_can", "apb1_scr",
+                                "apb1_ps20", "apb1_ps21", "apb1_uart0",
+                                "apb1_uart1", "apb1_uart2", "apb1_uart3",
+                                "apb1_uart4", "apb1_uart5", "apb1_uart6",
+                                "apb1_uart7";
+                };
+        };
+
+        soc@01c20000 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x01c20000 0x300000>;
+                ranges;
+
+                intc: interrupt-controller@01c20400 {
+                        compatible = "allwinner,sun4i-ic";
+                        reg = <0x01c20400 0x400>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                pio: pinctrl@01c20800 {
                         compatible = "allwinner,sun4i-a10-pinctrl";
                         reg = <0x01c20800 0x400>;
+                        clocks = <&apb0_gates 5>;
+                        gpio-controller;
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        #gpio-cells = <3>;
 
                         uart0_pins_a: uart0@0 {
                                 allwinner,pins = "PB22", "PB23";
@@ -45,5 +206,97 @@
                                 allwinner,pull = <0>;
                         };
                 };
+
+                timer@01c20c00 {
+                        compatible = "allwinner,sun4i-timer";
+                        reg = <0x01c20c00 0x90>;
+                        interrupts = <22>;
+                        clocks = <&osc24M>;
+                };
+
+                wdt: watchdog@01c20c90 {
+                        compatible = "allwinner,sun4i-wdt";
+                        reg = <0x01c20c90 0x10>;
+                };
+
+                uart0: serial@01c28000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28000 0x400>;
+                        interrupts = <1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 16>;
+                        status = "disabled";
+                };
+
+                uart1: serial@01c28400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28400 0x400>;
+                        interrupts = <2>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 17>;
+                        status = "disabled";
+                };
+
+                uart2: serial@01c28800 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28800 0x400>;
+                        interrupts = <3>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 18>;
+                        status = "disabled";
+                };
+
+                uart3: serial@01c28c00 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28c00 0x400>;
+                        interrupts = <4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 19>;
+                        status = "disabled";
+                };
+
+                uart4: serial@01c29000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c29000 0x400>;
+                        interrupts = <17>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 20>;
+                        status = "disabled";
+                };
+
+                uart5: serial@01c29400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c29400 0x400>;
+                        interrupts = <18>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 21>;
+                        status = "disabled";
+                };
+
+                uart6: serial@01c29800 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c29800 0x400>;
+                        interrupts = <19>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 22>;
+                        status = "disabled";
+                };
+
+                uart7: serial@01c29c00 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c29c00 0x400>;
+                        interrupts = <20>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 23>;
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 4a1e45d4aace..3ca55067f868 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -22,11 +22,31 @@
                 bootargs = "earlyprintk console=ttyS0,115200";
         };
 
-        soc {
-                uart1: uart@01c28400 {
+        soc@01c20000 {
+                pinctrl@01c20800 {
+                        led_pins_olinuxino: led_pins@0 {
+                                allwinner,pins = "PG9";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <1>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                uart1: serial@01c28400 {
                         pinctrl-names = "default";
                         pinctrl-0 = <&uart1_pins_b>;
                         status = "okay";
                 };
         };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_olinuxino>;
+
+                power {
+                        gpios = <&pio 6 9 0>;
+                        default-state = "on";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index e1121890fb29..391bcb70858b 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -11,19 +11,180 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "sunxi.dtsi"
+/include/ "skeleton.dtsi"
 
 / {
+        interrupt-parent = <&intc>;
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a8";
+                };
+        };
+
         memory {
                 reg = <0x40000000 0x20000000>;
         };
 
-        soc {
-                pinctrl@01c20800 {
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                /*
+                 * This is a dummy clock, to be used as placeholder on
+                 * other mux clocks when a specific parent clock is not
+                 * yet implemented. It should be dropped when the driver
+                 * is complete.
+                 */
+                dummy: dummy {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <0>;
+                };
+
+                osc24M_fixed: osc24M_fixed {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+
+                osc24M: osc24M@01c20050 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-osc-clk";
+                        reg = <0x01c20050 0x4>;
+                        clocks = <&osc24M_fixed>;
+                };
+
+                osc32k: osc32k {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+
+                pll1: pll1@01c20000 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20000 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                /* dummy is 200M */
+                cpu: cpu@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-cpu-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
+                };
+
+                axi: axi@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-axi-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&cpu>;
+                };
+
+                axi_gates: axi_gates@01c2005c {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-axi-gates-clk";
+                        reg = <0x01c2005c 0x4>;
+                        clocks = <&axi>;
+                        clock-output-names = "axi_dram";
+                };
+
+                ahb: ahb@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-ahb-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&axi>;
+                };
+
+                ahb_gates: ahb_gates@01c20060 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-ahb-gates-clk";
+                        reg = <0x01c20060 0x8>;
+                        clocks = <&ahb>;
+                        clock-output-names = "ahb_usb0", "ahb_ehci0",
+                                "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
+                                "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+                                "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
+                                "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
+                                "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
+                                "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
+                                "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
+                                "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
+                                "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+                                "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+                };
+
+                apb0: apb0@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb0-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&ahb>;
+                };
+
+                apb0_gates: apb0_gates@01c20068 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-apb0-gates-clk";
+                        reg = <0x01c20068 0x4>;
+                        clocks = <&apb0>;
+                        clock-output-names = "apb0_codec", "apb0_spdif",
+                                "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
+                                "apb0_ir1", "apb0_keypad";
+                };
+
+                /* dummy is pll62 */
+                apb1_mux: apb1_mux@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-mux-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                };
+
+                apb1: apb1@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&apb1_mux>;
+                };
+
+                apb1_gates: apb1_gates@01c2006c {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-apb1-gates-clk";
+                        reg = <0x01c2006c 0x4>;
+                        clocks = <&apb1>;
+                        clock-output-names = "apb1_i2c0", "apb1_i2c1",
+                                "apb1_i2c2", "apb1_can", "apb1_scr",
+                                "apb1_ps20", "apb1_ps21", "apb1_uart0",
+                                "apb1_uart1", "apb1_uart2", "apb1_uart3",
+                                "apb1_uart4", "apb1_uart5", "apb1_uart6",
+                                "apb1_uart7";
+                };
+        };
+
+        soc@01c20000 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x01c20000 0x300000>;
+                ranges;
+
+                intc: interrupt-controller@01c20400 {
+                        compatible = "allwinner,sun4i-ic";
+                        reg = <0x01c20400 0x400>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                pio: pinctrl@01c20800 {
                         compatible = "allwinner,sun5i-a13-pinctrl";
                         reg = <0x01c20800 0x400>;
+                        clocks = <&apb0_gates 5>;
+                        gpio-controller;
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        #gpio-cells = <3>;
 
                         uart1_pins_a: uart1@0 {
                                 allwinner,pins = "PE10", "PE11";
@@ -39,5 +200,37 @@
                                 allwinner,pull = <0>;
                         };
                 };
+
+                timer@01c20c00 {
+                        compatible = "allwinner,sun4i-timer";
+                        reg = <0x01c20c00 0x90>;
+                        interrupts = <22>;
+                        clocks = <&osc24M>;
+                };
+
+                wdt: watchdog@01c20c90 {
+                        compatible = "allwinner,sun4i-wdt";
+                        reg = <0x01c20c90 0x10>;
+                };
+
+                uart1: serial@01c28400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28400 0x400>;
+                        interrupts = <2>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 17>;
+                        status = "disabled";
+                };
+
+                uart3: serial@01c28c00 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28c00 0x400>;
+                        interrupts = <4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 19>;
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/sunxi.dtsi b/arch/arm/boot/dts/sunxi.dtsi
deleted file mode 100644
index 8b36abea9f2e..000000000000
--- a/arch/arm/boot/dts/sunxi.dtsi
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright 2012 Maxime Ripard
- *
- * Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/include/ "skeleton.dtsi"
-
-/ {
-        interrupt-parent = <&intc>;
-
-        cpus {
-                cpu@0 {
-                        compatible = "arm,cortex-a8";
-                };
-        };
-
-        clocks {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                osc: oscillator {
-                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <24000000>;
-                };
-        };
-
-        soc {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                reg = <0x01c20000 0x300000>;
-                ranges;
-
-                timer@01c20c00 {
-                        compatible = "allwinner,sunxi-timer";
-                        reg = <0x01c20c00 0x90>;
-                        interrupts = <22>;
-                        clocks = <&osc>;
-                };
-
-                wdt: watchdog@01c20c90 {
-                        compatible = "allwinner,sunxi-wdt";
-                        reg = <0x01c20c90 0x10>;
-                };
-
-                intc: interrupt-controller@01c20400 {
-                        compatible = "allwinner,sunxi-ic";
-                        reg = <0x01c20400 0x400>;
-                        interrupt-controller;
-                        #interrupt-cells = <1>;
-                };
-
-                uart0: uart@01c28000 {
-                        compatible = "snps,dw-apb-uart";
-                        reg = <0x01c28000 0x400>;
-                        interrupts = <1>;
-                        reg-shift = <2>;
-                        reg-io-width = <4>;
-                        clock-frequency = <24000000>;
-                        status = "disabled";
-                };
-
-                uart1: uart@01c28400 {
-                        compatible = "snps,dw-apb-uart";
-                        reg = <0x01c28400 0x400>;
-                        interrupts = <2>;
-                        reg-shift = <2>;
-                        reg-io-width = <4>;
-                        clock-frequency = <24000000>;
-                        status = "disabled";
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 444162090042..cb73e62d61a9 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -444,7 +444,7 @@
         };
 
         sdhci@c8000600 {
-                cd-gpios = <&gpio 23 0>; /* gpio PC7 */
+                cd-gpios = <&gpio 23 1>; /* gpio PC7 */
         };
 
         sound {
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 61d027f03617..1f79c0debb05 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -437,7 +437,7 @@
 
         sdhci@c8000200 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
                 power-gpios = <&gpio 155 0>; /* gpio PT3 */
                 bus-width = <4>;
@@ -445,7 +445,7 @@
 
         sdhci@c8000600 {
                 status = "okay";
-                cd-gpios = <&gpio 58 0>; /* gpio PH2 */
+                cd-gpios = <&gpio 58 1>; /* gpio PH2 */
                 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
                 power-gpios = <&gpio 70 0>; /* gpio PI6 */
                 bus-width = <8>;
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 54d6fce00a59..9db36da8e023 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -436,7 +436,7 @@
 
         sdhci@c8000000 {
                 status = "okay";
-                cd-gpios = <&gpio 173 0>; /* gpio PV5 */
+                cd-gpios = <&gpio 173 1>; /* gpio PV5 */
                 wp-gpios = <&gpio 57 0>;  /* gpio PH1 */
                 power-gpios = <&gpio 169 0>; /* gpio PV1 */
                 bus-width = <4>;
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 37b3a57ec0f1..715a8b8dd9cd 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -584,7 +584,7 @@
 
         sdhci@c8000400 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
                 power-gpios = <&gpio 70 0>; /* gpio PI6 */
                 bus-width = <4>;
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 4766abae7a72..6e9d91fc6195 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -465,7 +465,7 @@
         };
 
         sdhci@c8000600 {
-                cd-gpios = <&gpio 58 0>; /* gpio PH2 */
+                cd-gpios = <&gpio 58 1>; /* gpio PH2 */
                 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
                 bus-width = <4>;
                 status = "okay";
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 5d79e4fc49a6..98f3e44f2a51 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -325,7 +325,7 @@
 
         sdhci@c8000600 {
                 status = "okay";
-                cd-gpios = <&gpio 121 0>; /* gpio PP1 */
+                cd-gpios = <&gpio 121 1>; /* gpio PP1 */
                 wp-gpios = <&gpio 122 0>; /* gpio PP2 */
                 bus-width = <4>;
         };
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 425c89000c20..4aef56f2d96a 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -520,7 +520,7 @@
 
         sdhci@c8000400 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
                 power-gpios = <&gpio 70 0>; /* gpio PI6 */
                 bus-width = <4>;
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index ea57c0f6dcce..5762188c60ad 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -510,6 +510,7 @@
 
         sdhci@c8000400 {
                 status = "okay";
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 173 0>; /* gpio PV5 */
                 bus-width = <8>;
         };
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 8ff2ff20e4a3..0a2cd24df853 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -257,7 +257,7 @@
 
         sdhci@78000000 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
                 power-gpios = <&gpio 31 0>; /* gpio PD7 */
                 bus-width = <4>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 17499272a4ef..3e2d21018a5b 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -311,7 +311,7 @@
 
         sdhci@78000000 {
                 status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
                 power-gpios = <&gpio 31 0>; /* gpio PD7 */
                 bus-width = <4>;
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
index e74a1c0fb9a2..388f26d0d449 100644
--- a/arch/arm/boot/dts/wm8505.dtsi
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -60,6 +60,19 @@
                                         clock-frequency = <24000000>;
                                 };
 
+                                ref25: ref25M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <25000000>;
+                                };
+
+                                pllb: pllb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x204>;
+                                };
+
                                 clkuart0: uart0 {
                                         #clock-cells = <0>;
                                         compatible = "via,vt8500-device-clock";
@@ -107,6 +120,16 @@
                                         enable-reg = <0x250>;
                                         enable-bit = <23>;
                                 };
+
+                                clksdhc: sdhc {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x328>;
+                                        divisor-mask = <0x3f>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <18>;
+                                };
                         };
                 };
 
@@ -187,5 +210,13 @@
                         reg = <0xd8100000 0x10000>;
                         interrupts = <48>;
                 };
+
+                sdhc@d800a000 {
+                        compatible = "wm,wm8505-sdhc";
+                        reg = <0xd800a000 0x1000>;
+                        interrupts = <20 21>;
+                        clocks = <&clksdhc>;
+                        bus-width = <4>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 5914b5654591..9e1c339c4491 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -15,6 +15,13 @@
 / {
         compatible = "xlnx,zynq-7000";
 
+        pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts = <0 5 4>, <0 6 4>;
+                interrupt-parent = <&intc>;
+                reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
+        };
+
         amba {
                 compatible = "simple-bus";
                 #address-cells = <1>;
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
index 3fe8dae8d32d..4364eff5b01e 100644
--- a/arch/arm/configs/dove_defconfig
+++ b/arch/arm/configs/dove_defconfig
@@ -75,6 +75,8 @@ CONFIG_I2C_MV64XXX=y
 CONFIG_SPI=y
 CONFIG_SPI_ORION=y
 # CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_DOVE_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 13482ea58b09..8f0065bb6f39 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -119,6 +119,8 @@ CONFIG_SPI=y
 CONFIG_SPI_ORION=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_KIRKWOOD_THERMAL=y
 CONFIG_WATCHDOG=y
 CONFIG_ORION_WATCHDOG=y
 CONFIG_HID_DRAGONRISE=y
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 2ec8119cff73..f3e8ae001ff1 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -46,9 +46,16 @@ CONFIG_I2C_MV64XXX=y
 CONFIG_MTD=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_SERIAL_8250_DW=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
+CONFIG_THERMAL=y
+CONFIG_ARMADA_THERMAL=y
 CONFIG_USB_SUPPORT=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
@@ -65,6 +72,8 @@ CONFIG_RTC_DRV_S35390A=y
 CONFIG_RTC_DRV_MV=y
 CONFIG_DMADEVICES=y
 CONFIG_MV_XOR=y
+CONFIG_MEMORY=y
+CONFIG_MVEBU_DEVBUS=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 9706c000f294..36b05fc28816 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -212,6 +212,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
         CLKDEV_CON_DEV_ID("mci_clk", "fffb4000.mmc", &mmc_clk),
         CLKDEV_CON_DEV_ID("emac_clk", "fffbc000.ethernet", &ether_clk),
+        CLKDEV_CON_DEV_ID(NULL, "fffb8000.i2c", &twi_clk),
         CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
         CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
         CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
diff --git a/arch/arm/mach-kirkwood/board-guruplug.c b/arch/arm/mach-kirkwood/board-guruplug.c
index 0a0df4554d8b..a857163954a5 100644
--- a/arch/arm/mach-kirkwood/board-guruplug.c
+++ b/arch/arm/mach-kirkwood/board-guruplug.c
@@ -13,7 +13,6 @@
 #include <linux/init.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
-#include <linux/platform_data/mmc-mvsdio.h>
 #include "common.h"
 
 static struct mv643xx_eth_platform_data guruplug_ge00_data = {
@@ -24,10 +23,6 @@ static struct mv643xx_eth_platform_data guruplug_ge01_data = {
         .phy_addr       = MV643XX_ETH_PHY_ADDR(1),
 };
 
-static struct mvsdio_platform_data guruplug_mvsdio_data = {
-        /* unfortunately the CD signal has not been connected */
-};
-
 void __init guruplug_dt_init(void)
 {
         /*
@@ -35,5 +30,4 @@ void __init guruplug_dt_init(void)
          */
         kirkwood_ge00_init(&guruplug_ge00_data);
         kirkwood_ge01_init(&guruplug_ge01_data);
-        kirkwood_sdio_init(&guruplug_mvsdio_data);
 }