5 files changed, 54 insertions, 40 deletions

diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S
index be6a720dd183..f98763f0bc17 100644
--- a/arch/arm/include/debug/tegra.S
+++ b/arch/arm/include/debug/tegra.S
@@ -46,10 +46,10 @@
 #define TEGRA_APB_MISC_GP_HIDREV        (TEGRA_APB_MISC_BASE + 0x804)
 
 /*
- * Must be 1MB-aligned since a 1MB mapping is used early on.
+ * Must be section-aligned since a section mapping is used early on.
  * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
  */
-#define UART_VIRTUAL_BASE               0xfe100000
+#define UART_VIRTUAL_BASE               0xfe800000
 
 #define checkuart(rp, rv, lhu, bit, uart) \
                 /* Load address of CLK_RST register */ \
@@ -156,28 +156,6 @@
 92:             and     \rv, \rp, #0xffffff     @ offset within 1MB section
                 add     \rv, \rv, #UART_VIRTUAL_BASE
                 str     \rv, [\tmp, #8]         @ Store in tegra_uart_virt
-                movw    \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff
-                movt    \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16
-                ldr     \rv, [\rv, #0]          @ Load HIDREV
-                ubfx    \rv, \rv, #8, #8        @ 15:8 are SoC version
-                cmp     \rv, #0x20              @ Tegra20?
-                moveq   \rv, #0x75              @ Tegra20 divisor
-                movne   \rv, #0xdd              @ Tegra30 divisor
-                str     \rv, [\tmp, #12]        @ Save divisor to scratch
-                /* uart[UART_LCR] = UART_LCR_WLEN8 | UART_LCR_DLAB; */
-                mov     \rv, #UART_LCR_WLEN8 | UART_LCR_DLAB
-                str     \rv, [\rp, #UART_LCR << UART_SHIFT]
-                /* uart[UART_DLL] = div & 0xff; */
-                ldr     \rv, [\tmp, #12]
-                and     \rv, \rv, #0xff
-                str     \rv, [\rp, #UART_DLL << UART_SHIFT]
-                /* uart[UART_DLM] = div >> 8; */
-                ldr     \rv, [\tmp, #12]
-                lsr     \rv, \rv, #8
-                str     \rv, [\rp, #UART_DLM << UART_SHIFT]
-                /* uart[UART_LCR] = UART_LCR_WLEN8; */
-                mov     \rv, #UART_LCR_WLEN8
-                str     \rv, [\rp, #UART_LCR << UART_SHIFT]
                 b       100f
 
                 .align
@@ -205,8 +183,8 @@
                 cmp     \rx, #0
                 beq     1002f
 1001:           ldrb    \rd, [\rx, #UART_LSR << UART_SHIFT]
-                and     \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
-                teq     \rd, #UART_LSR_TEMT | UART_LSR_THRE
+                and     \rd, \rd, #UART_LSR_THRE
+                teq     \rd, #UART_LSR_THRE
                 bne     1001b
 1002:
                 .endm
@@ -225,7 +203,7 @@
 /*
  * Storage for the state maintained by the macros above.
  *
- * In the kernel proper, this data is located in arch/arm/mach-tegra/common.c.
+ * In the kernel proper, this data is located in arch/arm/mach-tegra/tegra.c.
  * That's because this header is included from multiple files, and we only
  * want a single copy of the data. In particular, the UART probing code above
  * assumes it's running using physical addresses. This is true when this file
@@ -247,6 +225,4 @@ tegra_uart_config:
         .word 0
         /* Debug UART virtual address */
         .word 0
-        /* Scratch space for debug macro */
-        .word 0
 #endif
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 15c09294effa..d1a12a496525 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -65,6 +65,7 @@ config ARCH_TEGRA_124_SOC
         bool "Enable support for Tegra124 family"
         select ARM_L1_CACHE_SHIFT_6
         select HAVE_ARM_ARCH_TIMER
+        select PINCTRL_TEGRA124
         help
           Support for NVIDIA Tegra T124 processor family, based on the
           ARM CortexA15MP CPU
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index 3a9c1f1c219d..c9ac23b385be 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/export.h>
 #include <linux/random.h>
+#include <linux/clk.h>
 #include <linux/tegra-soc.h>
 
 #include "fuse.h"
@@ -54,6 +55,7 @@ int tegra_cpu_speedo_id;		/* only exist in Tegra30 and later */
 int tegra_soc_speedo_id;
 enum tegra_revision tegra_revision;
 
+static struct clk *fuse_clk;
 static int tegra_fuse_spare_bit;
 static void (*tegra_init_speedo_data)(void);
 
@@ -77,6 +79,22 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
         [TEGRA_REVISION_A04]     = "A04",
 };
 
+static void tegra_fuse_enable_clk(void)
+{
+        if (IS_ERR(fuse_clk))
+                fuse_clk = clk_get_sys(NULL, "fuse");
+        if (IS_ERR(fuse_clk))
+                return;
+        clk_prepare_enable(fuse_clk);
+}
+
+static void tegra_fuse_disable_clk(void)
+{
+        if (IS_ERR(fuse_clk))
+                return;
+        clk_disable_unprepare(fuse_clk);
+}
+
 u32 tegra_fuse_readl(unsigned long offset)
 {
         return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
@@ -84,7 +102,15 @@ u32 tegra_fuse_readl(unsigned long offset)
 
 bool tegra_spare_fuse(int bit)
 {
-        return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
+        bool ret;
+
+        tegra_fuse_enable_clk();
+
+        ret = tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
+
+        tegra_fuse_disable_clk();
+
+        return ret;
 }
 
 static enum tegra_revision tegra_get_revision(u32 id)
@@ -113,10 +139,14 @@ static void tegra_get_process_id(void)
 {
         u32 reg;
 
+        tegra_fuse_enable_clk();
+
         reg = tegra_fuse_readl(tegra_fuse_spare_bit);
         tegra_cpu_process_id = (reg >> 6) & 3;
         reg = tegra_fuse_readl(tegra_fuse_spare_bit);
         tegra_core_process_id = (reg >> 12) & 3;
+
+        tegra_fuse_disable_clk();
 }
 
 u32 tegra_read_chipid(void)
@@ -159,6 +189,15 @@ void __init tegra_init_fuse(void)
         reg |= 1 << 28;
         writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
 
+        /*
+         * Enable FUSE clock. This needs to be hardcoded because the clock
+         * subsystem is not active during early boot.
+         */
+        reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14));
+        reg |= 1 << 7;
+        writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14));
+        fuse_clk = ERR_PTR(-EINVAL);
+
         reg = tegra_fuse_readl(FUSE_SKU_INFO);
         randomness[0] = reg;
         tegra_sku_id = reg & 0xFF;
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index 26b1c2ad0ceb..ee79808e93a3 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -19,6 +19,7 @@
 #ifndef __MACH_TEGRA_IOMAP_H
 #define __MACH_TEGRA_IOMAP_H
 
+#include <asm/pgtable.h>
 #include <asm/sizes.h>
 
 #define TEGRA_IRAM_BASE                 0x40000000
@@ -115,27 +116,26 @@
  * two 256MB io windows (that actually only use about 64KB
  * at the start of each).
  *
- * We will just map the first 1MB of each window (to minimize
+ * We will just map the first MMU section of each window (to minimize
  * pt entries needed) and provide a macro to transform physical
  * io addresses to an appropriate void __iomem *.
- *
  */
 
 #define IO_IRAM_PHYS    0x40000000
 #define IO_IRAM_VIRT    IOMEM(0xFE400000)
 #define IO_IRAM_SIZE    SZ_256K
 
-#define IO_CPU_PHYS     0x50040000
-#define IO_CPU_VIRT     IOMEM(0xFE000000)
+#define IO_CPU_PHYS     0x50040000
+#define IO_CPU_VIRT     IOMEM(0xFE440000)
 #define IO_CPU_SIZE     SZ_16K
 
 #define IO_PPSB_PHYS    0x60000000
 #define IO_PPSB_VIRT    IOMEM(0xFE200000)
-#define IO_PPSB_SIZE    SZ_1M
+#define IO_PPSB_SIZE    SECTION_SIZE
 
 #define IO_APB_PHYS     0x70000000
-#define IO_APB_VIRT     IOMEM(0xFE300000)
-#define IO_APB_SIZE     SZ_1M
+#define IO_APB_VIRT     IOMEM(0xFE000000)
+#define IO_APB_SIZE     SECTION_SIZE
 
 #define IO_TO_VIRT_BETWEEN(p, st, sz)   ((p) >= (st) && (p) < ((st) + (sz)))
 #define IO_TO_VIRT_XLATE(p, pst, vst)   (((p) - (pst) + (vst)))
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 73368176c6e8..ea14d380fc0c 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -60,15 +60,13 @@
  * kernel is loaded. The data is declared here rather than debug-macro.S so
  * that multiple inclusions of debug-macro.S point at the same data.
  */
-u32 tegra_uart_config[4] = {
+u32 tegra_uart_config[3] = {
         /* Debug UART initialization required */
         1,
         /* Debug UART physical address */
         0,
         /* Debug UART virtual address */
         0,
-        /* Scratch space for debug macro */
-        0,
 };
 
 static void __init tegra_init_cache(void)