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-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/mach-s3c24xx/Kconfig104
-rw-r--r--arch/arm/mach-s3c24xx/Makefile14
-rw-r--r--arch/arm/mach-s3c24xx/clock-dclk.c (renamed from arch/arm/plat-s3c24xx/clock-dclk.c)3
-rw-r--r--arch/arm/mach-s3c24xx/clock-s3c2410.c (renamed from arch/arm/plat-s3c24xx/s3c2410-clock.c)3
-rw-r--r--arch/arm/mach-s3c24xx/cpufreq-debugfs.c (renamed from arch/arm/plat-s3c24xx/cpu-freq-debugfs.c)3
-rw-r--r--arch/arm/mach-s3c24xx/cpufreq-s3c2412.c3
-rw-r--r--arch/arm/mach-s3c24xx/cpufreq-utils.c (renamed from arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c)6
-rw-r--r--arch/arm/mach-s3c24xx/cpufreq.c (renamed from arch/arm/plat-s3c24xx/cpu-freq.c)3
-rw-r--r--arch/arm/mach-s3c24xx/dma-s3c2410.c1
-rw-r--r--arch/arm/mach-s3c24xx/dma-s3c2412.c1
-rw-r--r--arch/arm/mach-s3c24xx/dma-s3c2440.c1
-rw-r--r--arch/arm/mach-s3c24xx/dma-s3c2443.c1
-rw-r--r--arch/arm/mach-s3c24xx/dma.c (renamed from arch/arm/plat-s3c24xx/dma.c)3
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-mem.h202
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-power.h40
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h48
-rw-r--r--arch/arm/mach-s3c24xx/iotiming-s3c2410.c (renamed from arch/arm/plat-s3c24xx/s3c2410-iotiming.c)6
-rw-r--r--arch/arm/mach-s3c24xx/iotiming-s3c2412.c (renamed from arch/arm/plat-s3c24xx/s3c2412-iotiming.c)7
-rw-r--r--arch/arm/mach-s3c24xx/irq-s3c2412.c3
-rw-r--r--arch/arm/mach-s3c24xx/irq.c (renamed from arch/arm/plat-s3c24xx/irq.c)0
-rw-r--r--arch/arm/mach-s3c24xx/mach-anubis.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-at2440evb.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-bast.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-gta02.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-jive.c4
-rw-r--r--arch/arm/mach-s3c24xx/mach-mini2440.c1
-rw-r--r--arch/arm/mach-s3c24xx/mach-osiris.c2
-rw-r--r--arch/arm/mach-s3c24xx/pm-s3c2412.c2
-rw-r--r--arch/arm/mach-s3c24xx/pm-s3c2416.c3
-rw-r--r--arch/arm/mach-s3c24xx/pm.c3
-rw-r--r--arch/arm/mach-s3c24xx/regs-mem.h54
-rw-r--r--arch/arm/mach-s3c24xx/s3c2412-power.h37
-rw-r--r--arch/arm/mach-s3c24xx/s3c2412.c2
-rw-r--r--arch/arm/mach-s3c24xx/s3c2412.h26
-rw-r--r--arch/arm/mach-s3c24xx/simtec-pm.c3
-rw-r--r--arch/arm/mach-s3c24xx/sleep-s3c2410.S3
-rw-r--r--arch/arm/mach-s3c24xx/sleep.S1
-rw-r--r--arch/arm/plat-s3c24xx/Kconfig117
-rw-r--r--arch/arm/plat-s3c24xx/Makefile27
41 files changed, 266 insertions, 478 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 17f49ccb8326..42e263a8d353 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1079,7 +1079,6 @@ source "arch/arm/mach-realview/Kconfig"
1079source "arch/arm/mach-sa1100/Kconfig" 1079source "arch/arm/mach-sa1100/Kconfig"
1080 1080
1081source "arch/arm/plat-samsung/Kconfig" 1081source "arch/arm/plat-samsung/Kconfig"
1082source "arch/arm/plat-s3c24xx/Kconfig"
1083 1082
1084source "arch/arm/mach-socfpga/Kconfig" 1083source "arch/arm/mach-socfpga/Kconfig"
1085 1084
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 0935dac37f62..a554f759c72f 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -204,7 +204,7 @@ plat-$(CONFIG_ARCH_S3C64XX) += samsung
204plat-$(CONFIG_PLAT_IOP) += iop 204plat-$(CONFIG_PLAT_IOP) += iop
205plat-$(CONFIG_PLAT_ORION) += orion 205plat-$(CONFIG_PLAT_ORION) += orion
206plat-$(CONFIG_PLAT_PXA) += pxa 206plat-$(CONFIG_PLAT_PXA) += pxa
207plat-$(CONFIG_PLAT_S3C24XX) += s3c24xx samsung 207plat-$(CONFIG_PLAT_S3C24XX) += samsung
208plat-$(CONFIG_PLAT_S5P) += samsung 208plat-$(CONFIG_PLAT_S5P) += samsung
209plat-$(CONFIG_PLAT_SPEAR) += spear 209plat-$(CONFIG_PLAT_SPEAR) += spear
210plat-$(CONFIG_PLAT_VERSATILE) += versatile 210plat-$(CONFIG_PLAT_VERSATILE) += versatile
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 67df58bdc096..31eacad5b3e9 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -9,6 +9,15 @@
9 9
10if ARCH_S3C24XX 10if ARCH_S3C24XX
11 11
12config PLAT_S3C24XX
13 def_bool y
14 select ARCH_REQUIRE_GPIOLIB
15 select NO_IOPORT
16 select S3C_DEV_NAND
17 select IRQ_DOMAIN
18 help
19 Base platform code for any Samsung S3C24XX device
20
12menu "SAMSUNG S3C24XX SoCs Support" 21menu "SAMSUNG S3C24XX SoCs Support"
13 22
14comment "S3C24XX SoCs" 23comment "S3C24XX SoCs"
@@ -83,6 +92,17 @@ config CPU_S3C2443
83 92
84# common code 93# common code
85 94
95config S3C2410_CLOCK
96 bool
97 help
98 Clock code for the S3C2410, and similar processors which
99 is currently includes the S3C2410, S3C2440, S3C2442.
100
101config S3C24XX_DCLK
102 bool
103 help
104 Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
105
86config S3C24XX_SMDK 106config S3C24XX_SMDK
87 bool 107 bool
88 help 108 help
@@ -111,6 +131,22 @@ config S3C24XX_SETUP_TS
111 help 131 help
112 Compile in platform device definition for Samsung TouchScreen. 132 Compile in platform device definition for Samsung TouchScreen.
113 133
134config S3C24XX_DMA
135 bool "S3C2410 DMA support"
136 depends on ARCH_S3C24XX
137 select S3C_DMA
138 help
139 S3C2410 DMA support. This is needed for drivers like sound which
140 use the S3C2410's DMA system to move data to and from the
141 peripheral blocks.
142
143config S3C2410_DMA_DEBUG
144 bool "S3C2410 DMA support debug"
145 depends on ARCH_S3C24XX && S3C2410_DMA
146 help
147 Enable debugging output for the DMA code. This option sends info
148 to the kernel log, at priority KERN_DEBUG.
149
114config S3C2410_DMA 150config S3C2410_DMA
115 bool 151 bool
116 depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442) 152 depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
@@ -123,6 +159,74 @@ config S3C2410_PM
123 help 159 help
124 Power Management code common to S3C2410 and better 160 Power Management code common to S3C2410 and better
125 161
162# low-level serial option nodes
163
164config CPU_LLSERIAL_S3C2410_ONLY
165 bool
166 default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
167
168config CPU_LLSERIAL_S3C2440_ONLY
169 bool
170 default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
171
172config CPU_LLSERIAL_S3C2410
173 bool
174 help
175 Selected if there is an S3C2410 (or register compatible) serial
176 low-level implementation needed
177
178config CPU_LLSERIAL_S3C2440
179 bool
180 help
181 Selected if there is an S3C2440 (or register compatible) serial
182 low-level implementation needed
183
184# gpio configurations
185
186config S3C24XX_GPIO_EXTRA
187 int
188 default 128 if S3C24XX_GPIO_EXTRA128
189 default 64 if S3C24XX_GPIO_EXTRA64
190 default 16 if ARCH_H1940
191 default 0
192
193config S3C24XX_GPIO_EXTRA64
194 bool
195 help
196 Add an extra 64 gpio numbers to the available GPIO pool. This is
197 available for boards that need extra gpios for external devices.
198
199config S3C24XX_GPIO_EXTRA128
200 bool
201 help
202 Add an extra 128 gpio numbers to the available GPIO pool. This is
203 available for boards that need extra gpios for external devices.
204
205# cpu frequency items common between s3c2410 and s3c2440/s3c2442
206
207config S3C2410_IOTIMING
208 bool
209 depends on CPU_FREQ_S3C24XX
210 help
211 Internal node to select io timing code that is common to the s3c2410
212 and s3c2440/s3c2442 cpu frequency support.
213
214config S3C2410_CPUFREQ_UTILS
215 bool
216 depends on CPU_FREQ_S3C24XX
217 help
218 Internal node to select timing code that is common to the s3c2410
219 and s3c2440/s3c244 cpu frequency support.
220
221# cpu frequency support common to s3c2412, s3c2413 and s3c2442
222
223config S3C2412_IOTIMING
224 bool
225 depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443)
226 help
227 Intel node to select io timing code that is common to the s3c2412
228 and the s3c2443.
229
126# cpu-specific sections 230# cpu-specific sections
127 231
128if CPU_S3C2410 232if CPU_S3C2410
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 1d67582da41a..af53d27d5c36 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -14,7 +14,7 @@ obj- :=
14 14
15# core 15# core
16 16
17obj-y += common.o 17obj-y += common.o irq.o
18 18
19obj-$(CONFIG_CPU_S3C2410) += s3c2410.o 19obj-$(CONFIG_CPU_S3C2410) += s3c2410.o
20obj-$(CONFIG_S3C2410_CPUFREQ) += cpufreq-s3c2410.o 20obj-$(CONFIG_S3C2410_CPUFREQ) += cpufreq-s3c2410.o
@@ -47,9 +47,21 @@ obj-$(CONFIG_PM) += pm.o irq-pm.o sleep.o
47 47
48# common code 48# common code
49 49
50obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o
51obj-$(CONFIG_S3C24XX_DMA) += dma.o
52
53obj-$(CONFIG_S3C2410_CLOCK) += clock-s3c2410.o
54obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o
55
56obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o
57obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o
58
50obj-$(CONFIG_S3C2443_COMMON) += common-s3c2443.o 59obj-$(CONFIG_S3C2443_COMMON) += common-s3c2443.o
51obj-$(CONFIG_S3C2443_DMA) += dma-s3c2443.o 60obj-$(CONFIG_S3C2443_DMA) += dma-s3c2443.o
52 61
62obj-$(CONFIG_CPU_FREQ_S3C24XX) += cpufreq.o
63obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpufreq-debugfs.o
64
53# 65#
54# machine support 66# machine support
55# following is ordered alphabetically by option text. 67# following is ordered alphabetically by option text.
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/mach-s3c24xx/clock-dclk.c
index f95d3268ae1f..1edd9b2369c5 100644
--- a/arch/arm/plat-s3c24xx/clock-dclk.c
+++ b/arch/arm/mach-s3c24xx/clock-dclk.c
@@ -1,5 +1,4 @@
1/* linux/arch/arm/plat-s3c24xx/clock-dclk.c 1/*
2 *
3 * Copyright (c) 2004-2008 Simtec Electronics 2 * Copyright (c) 2004-2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 3 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/ 4 * http://armlinux.simtec.co.uk/
diff --git a/arch/arm/plat-s3c24xx/s3c2410-clock.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c
index 25dc4d4397b1..641266f3d152 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-clock.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2410.c
@@ -1,5 +1,4 @@
1/* linux/arch/arm/mach-s3c2410/clock.c 1/*
2 *
3 * Copyright (c) 2006 Simtec Electronics 2 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 3 * Ben Dooks <ben@simtec.co.uk>
5 * 4 *
diff --git a/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c b/arch/arm/mach-s3c24xx/cpufreq-debugfs.c
index c7adad0e8de0..9b7b4289d66c 100644
--- a/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-debugfs.c
@@ -1,5 +1,4 @@
1/* linux/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c 1/*
2 *
3 * Copyright (c) 2009 Simtec Electronics 2 * Copyright (c) 2009 Simtec Electronics
4 * http://armlinux.simtec.co.uk/ 3 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c
index c8f05f309eee..8bf0f3a77476 100644
--- a/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c
@@ -25,12 +25,13 @@
25#include <asm/mach/map.h> 25#include <asm/mach/map.h>
26 26
27#include <mach/regs-clock.h> 27#include <mach/regs-clock.h>
28#include <mach/regs-s3c2412-mem.h>
29 28
30#include <plat/cpu.h> 29#include <plat/cpu.h>
31#include <plat/clock.h> 30#include <plat/clock.h>
32#include <plat/cpu-freq-core.h> 31#include <plat/cpu-freq-core.h>
33 32
33#include "s3c2412.h"
34
34/* our clock resources. */ 35/* our clock resources. */
35static struct clk *xtal; 36static struct clk *xtal;
36static struct clk *fclk; 37static struct clk *fclk;
diff --git a/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c b/arch/arm/mach-s3c24xx/cpufreq-utils.c
index 43ea80190d87..ddd8280e3875 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c
@@ -1,5 +1,4 @@
1/* linux/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c 1/*
2 *
3 * Copyright (c) 2009 Simtec Electronics 2 * Copyright (c) 2009 Simtec Electronics
4 * http://armlinux.simtec.co.uk/ 3 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
@@ -17,11 +16,12 @@
17#include <linux/io.h> 16#include <linux/io.h>
18 17
19#include <mach/map.h> 18#include <mach/map.h>
20#include <mach/regs-mem.h>
21#include <mach/regs-clock.h> 19#include <mach/regs-clock.h>
22 20
23#include <plat/cpu-freq-core.h> 21#include <plat/cpu-freq-core.h>
24 22
23#include "regs-mem.h"
24
25/** 25/**
26 * s3c2410_cpufreq_setrefresh - set SDRAM refresh value 26 * s3c2410_cpufreq_setrefresh - set SDRAM refresh value
27 * @cfg: The frequency configuration 27 * @cfg: The frequency configuration
diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/mach-s3c24xx/cpufreq.c
index 468079938884..5f181e733eee 100644
--- a/arch/arm/plat-s3c24xx/cpu-freq.c
+++ b/arch/arm/mach-s3c24xx/cpufreq.c
@@ -1,5 +1,4 @@
1/* linux/arch/arm/plat-s3c24xx/cpu-freq.c 1/*
2 *
3 * Copyright (c) 2006-2008 Simtec Electronics 2 * Copyright (c) 2006-2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/ 3 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2410.c b/arch/arm/mach-s3c24xx/dma-s3c2410.c
index 4803338cf56e..25d085adc93c 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2410.c
@@ -27,7 +27,6 @@
27#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
28#include <plat/regs-ac97.h> 28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h> 29#include <plat/regs-dma.h>
30#include <mach/regs-mem.h>
31#include <mach/regs-lcd.h> 30#include <mach/regs-lcd.h>
32#include <mach/regs-sdi.h> 31#include <mach/regs-sdi.h>
33#include <plat/regs-iis.h> 32#include <plat/regs-iis.h>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c
index 38472ac920ff..d2408ba372cb 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c
@@ -27,7 +27,6 @@
27#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
28#include <plat/regs-ac97.h> 28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h> 29#include <plat/regs-dma.h>
30#include <mach/regs-mem.h>
31#include <mach/regs-lcd.h> 30#include <mach/regs-lcd.h>
32#include <mach/regs-sdi.h> 31#include <mach/regs-sdi.h>
33#include <plat/regs-iis.h> 32#include <plat/regs-iis.h>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2440.c b/arch/arm/mach-s3c24xx/dma-s3c2440.c
index 5f0a0c8ef84f..0b86e74d104f 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2440.c
@@ -27,7 +27,6 @@
27#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
28#include <plat/regs-ac97.h> 28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h> 29#include <plat/regs-dma.h>
30#include <mach/regs-mem.h>
31#include <mach/regs-lcd.h> 30#include <mach/regs-lcd.h>
32#include <mach/regs-sdi.h> 31#include <mach/regs-sdi.h>
33#include <plat/regs-iis.h> 32#include <plat/regs-iis.h>
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index 2d94228d2866..05536254a3f8 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -27,7 +27,6 @@
27#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
28#include <plat/regs-ac97.h> 28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h> 29#include <plat/regs-dma.h>
30#include <mach/regs-mem.h>
31#include <mach/regs-lcd.h> 30#include <mach/regs-lcd.h>
32#include <mach/regs-sdi.h> 31#include <mach/regs-sdi.h>
33#include <plat/regs-iis.h> 32#include <plat/regs-iis.h>
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/mach-s3c24xx/dma.c
index ba3e76c95504..aab64909e9a3 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/mach-s3c24xx/dma.c
@@ -1,5 +1,4 @@
1/* linux/arch/arm/plat-s3c24xx/dma.c 1/*
2 *
3 * Copyright 2003-2006 Simtec Electronics 2 * Copyright 2003-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 3 * Ben Dooks <ben@simtec.co.uk>
5 * 4 *
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-mem.h
deleted file mode 100644
index e0c67b0163d8..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-mem.h
+++ /dev/null
@@ -1,202 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-mem.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Memory Control register definitions
11*/
12
13#ifndef __ASM_ARM_MEMREGS_H
14#define __ASM_ARM_MEMREGS_H
15
16#ifndef S3C2410_MEMREG
17#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
18#endif
19
20/* bus width, and wait state control */
21#define S3C2410_BWSCON S3C2410_MEMREG(0x0000)
22
23/* bank zero config - note, pinstrapped from OM pins! */
24#define S3C2410_BWSCON_DW0_16 (1<<1)
25#define S3C2410_BWSCON_DW0_32 (2<<1)
26
27/* bank one configs */
28#define S3C2410_BWSCON_DW1_8 (0<<4)
29#define S3C2410_BWSCON_DW1_16 (1<<4)
30#define S3C2410_BWSCON_DW1_32 (2<<4)
31#define S3C2410_BWSCON_WS1 (1<<6)
32#define S3C2410_BWSCON_ST1 (1<<7)
33
34/* bank 2 configurations */
35#define S3C2410_BWSCON_DW2_8 (0<<8)
36#define S3C2410_BWSCON_DW2_16 (1<<8)
37#define S3C2410_BWSCON_DW2_32 (2<<8)
38#define S3C2410_BWSCON_WS2 (1<<10)
39#define S3C2410_BWSCON_ST2 (1<<11)
40
41/* bank 3 configurations */
42#define S3C2410_BWSCON_DW3_8 (0<<12)
43#define S3C2410_BWSCON_DW3_16 (1<<12)
44#define S3C2410_BWSCON_DW3_32 (2<<12)
45#define S3C2410_BWSCON_WS3 (1<<14)
46#define S3C2410_BWSCON_ST3 (1<<15)
47
48/* bank 4 configurations */
49#define S3C2410_BWSCON_DW4_8 (0<<16)
50#define S3C2410_BWSCON_DW4_16 (1<<16)
51#define S3C2410_BWSCON_DW4_32 (2<<16)
52#define S3C2410_BWSCON_WS4 (1<<18)
53#define S3C2410_BWSCON_ST4 (1<<19)
54
55/* bank 5 configurations */
56#define S3C2410_BWSCON_DW5_8 (0<<20)
57#define S3C2410_BWSCON_DW5_16 (1<<20)
58#define S3C2410_BWSCON_DW5_32 (2<<20)
59#define S3C2410_BWSCON_WS5 (1<<22)
60#define S3C2410_BWSCON_ST5 (1<<23)
61
62/* bank 6 configurations */
63#define S3C2410_BWSCON_DW6_8 (0<<24)
64#define S3C2410_BWSCON_DW6_16 (1<<24)
65#define S3C2410_BWSCON_DW6_32 (2<<24)
66#define S3C2410_BWSCON_WS6 (1<<26)
67#define S3C2410_BWSCON_ST6 (1<<27)
68
69/* bank 7 configurations */
70#define S3C2410_BWSCON_DW7_8 (0<<28)
71#define S3C2410_BWSCON_DW7_16 (1<<28)
72#define S3C2410_BWSCON_DW7_32 (2<<28)
73#define S3C2410_BWSCON_WS7 (1<<30)
74#define S3C2410_BWSCON_ST7 (1<<31)
75
76/* accesor functions for getting BANK(n) configuration. (n != 0) */
77
78#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
79
80#define S3C2410_BWSCON_DW8 (0)
81#define S3C2410_BWSCON_DW16 (1)
82#define S3C2410_BWSCON_DW32 (2)
83#define S3C2410_BWSCON_WS (1 << 2)
84#define S3C2410_BWSCON_ST (1 << 3)
85
86/* memory set (rom, ram) */
87#define S3C2410_BANKCON0 S3C2410_MEMREG(0x0004)
88#define S3C2410_BANKCON1 S3C2410_MEMREG(0x0008)
89#define S3C2410_BANKCON2 S3C2410_MEMREG(0x000C)
90#define S3C2410_BANKCON3 S3C2410_MEMREG(0x0010)
91#define S3C2410_BANKCON4 S3C2410_MEMREG(0x0014)
92#define S3C2410_BANKCON5 S3C2410_MEMREG(0x0018)
93#define S3C2410_BANKCON6 S3C2410_MEMREG(0x001C)
94#define S3C2410_BANKCON7 S3C2410_MEMREG(0x0020)
95
96/* bank configuration registers */
97
98#define S3C2410_BANKCON_PMCnorm (0x00)
99#define S3C2410_BANKCON_PMC4 (0x01)
100#define S3C2410_BANKCON_PMC8 (0x02)
101#define S3C2410_BANKCON_PMC16 (0x03)
102
103/* bank configurations for banks 0..7, note banks
104 * 6 and 7 have different configurations depending on
105 * the memory type bits */
106
107#define S3C2410_BANKCON_Tacp2 (0x0 << 2)
108#define S3C2410_BANKCON_Tacp3 (0x1 << 2)
109#define S3C2410_BANKCON_Tacp4 (0x2 << 2)
110#define S3C2410_BANKCON_Tacp6 (0x3 << 2)
111#define S3C2410_BANKCON_Tacp_SHIFT (2)
112
113#define S3C2410_BANKCON_Tcah0 (0x0 << 4)
114#define S3C2410_BANKCON_Tcah1 (0x1 << 4)
115#define S3C2410_BANKCON_Tcah2 (0x2 << 4)
116#define S3C2410_BANKCON_Tcah4 (0x3 << 4)
117#define S3C2410_BANKCON_Tcah_SHIFT (4)
118
119#define S3C2410_BANKCON_Tcoh0 (0x0 << 6)
120#define S3C2410_BANKCON_Tcoh1 (0x1 << 6)
121#define S3C2410_BANKCON_Tcoh2 (0x2 << 6)
122#define S3C2410_BANKCON_Tcoh4 (0x3 << 6)
123#define S3C2410_BANKCON_Tcoh_SHIFT (6)
124
125#define S3C2410_BANKCON_Tacc1 (0x0 << 8)
126#define S3C2410_BANKCON_Tacc2 (0x1 << 8)
127#define S3C2410_BANKCON_Tacc3 (0x2 << 8)
128#define S3C2410_BANKCON_Tacc4 (0x3 << 8)
129#define S3C2410_BANKCON_Tacc6 (0x4 << 8)
130#define S3C2410_BANKCON_Tacc8 (0x5 << 8)
131#define S3C2410_BANKCON_Tacc10 (0x6 << 8)
132#define S3C2410_BANKCON_Tacc14 (0x7 << 8)
133#define S3C2410_BANKCON_Tacc_SHIFT (8)
134
135#define S3C2410_BANKCON_Tcos0 (0x0 << 11)
136#define S3C2410_BANKCON_Tcos1 (0x1 << 11)
137#define S3C2410_BANKCON_Tcos2 (0x2 << 11)
138#define S3C2410_BANKCON_Tcos4 (0x3 << 11)
139#define S3C2410_BANKCON_Tcos_SHIFT (11)
140
141#define S3C2410_BANKCON_Tacs0 (0x0 << 13)
142#define S3C2410_BANKCON_Tacs1 (0x1 << 13)
143#define S3C2410_BANKCON_Tacs2 (0x2 << 13)
144#define S3C2410_BANKCON_Tacs4 (0x3 << 13)
145#define S3C2410_BANKCON_Tacs_SHIFT (13)
146
147#define S3C2410_BANKCON_SRAM (0x0 << 15)
148#define S3C2410_BANKCON_SDRAM (0x3 << 15)
149
150/* next bits only for SDRAM in 6,7 */
151#define S3C2410_BANKCON_Trcd2 (0x00 << 2)
152#define S3C2410_BANKCON_Trcd3 (0x01 << 2)
153#define S3C2410_BANKCON_Trcd4 (0x02 << 2)
154
155/* control column address select */
156#define S3C2410_BANKCON_SCANb8 (0x00 << 0)
157#define S3C2410_BANKCON_SCANb9 (0x01 << 0)
158#define S3C2410_BANKCON_SCANb10 (0x02 << 0)
159
160#define S3C2410_REFRESH S3C2410_MEMREG(0x0024)
161#define S3C2410_BANKSIZE S3C2410_MEMREG(0x0028)
162#define S3C2410_MRSRB6 S3C2410_MEMREG(0x002C)
163#define S3C2410_MRSRB7 S3C2410_MEMREG(0x0030)
164
165/* refresh control */
166
167#define S3C2410_REFRESH_REFEN (1<<23)
168#define S3C2410_REFRESH_SELF (1<<22)
169#define S3C2410_REFRESH_REFCOUNTER ((1<<11)-1)
170
171#define S3C2410_REFRESH_TRP_MASK (3<<20)
172#define S3C2410_REFRESH_TRP_2clk (0<<20)
173#define S3C2410_REFRESH_TRP_3clk (1<<20)
174#define S3C2410_REFRESH_TRP_4clk (2<<20)
175
176#define S3C2410_REFRESH_TSRC_MASK (3<<18)
177#define S3C2410_REFRESH_TSRC_4clk (0<<18)
178#define S3C2410_REFRESH_TSRC_5clk (1<<18)
179#define S3C2410_REFRESH_TSRC_6clk (2<<18)
180#define S3C2410_REFRESH_TSRC_7clk (3<<18)
181
182
183/* mode select register(s) */
184
185#define S3C2410_MRSRB_CL1 (0x00 << 4)
186#define S3C2410_MRSRB_CL2 (0x02 << 4)
187#define S3C2410_MRSRB_CL3 (0x03 << 4)
188
189/* bank size register */
190#define S3C2410_BANKSIZE_128M (0x2 << 0)
191#define S3C2410_BANKSIZE_64M (0x1 << 0)
192#define S3C2410_BANKSIZE_32M (0x0 << 0)
193#define S3C2410_BANKSIZE_16M (0x7 << 0)
194#define S3C2410_BANKSIZE_8M (0x6 << 0)
195#define S3C2410_BANKSIZE_4M (0x5 << 0)
196#define S3C2410_BANKSIZE_2M (0x4 << 0)
197#define S3C2410_BANKSIZE_MASK (0x7 << 0)
198#define S3C2410_BANKSIZE_SCLK_EN (1<<4)
199#define S3C2410_BANKSIZE_SCKE_EN (1<<5)
200#define S3C2410_BANKSIZE_BURST (1<<7)
201
202#endif /* __ASM_ARM_MEMREGS_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-power.h b/arch/arm/mach-s3c24xx/include/mach/regs-power.h
deleted file mode 100644
index 4932b87bdf3d..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-power.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-power.h
2 *
3 * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
4 * http://armlinux.simtec.co.uk/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C24XX power control register definitions
11*/
12
13#ifndef __ASM_ARM_REGS_PWR
14#define __ASM_ARM_REGS_PWR __FILE__
15
16#define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR)
17
18#define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20)
19#define S3C2412_PWRCFG S3C24XX_PWRREG(0x24)
20
21#define S3C2412_INFORM0 S3C24XX_PWRREG(0x70)
22#define S3C2412_INFORM1 S3C24XX_PWRREG(0x74)
23#define S3C2412_INFORM2 S3C24XX_PWRREG(0x78)
24#define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C)
25
26#define S3C2412_PWRCFG_BATF_IRQ (1<<0)
27#define S3C2412_PWRCFG_BATF_IGNORE (2<<0)
28#define S3C2412_PWRCFG_BATF_SLEEP (3<<0)
29#define S3C2412_PWRCFG_BATF_MASK (3<<0)
30
31#define S3C2412_PWRCFG_STANDBYWFI_IGNORE (0<<6)
32#define S3C2412_PWRCFG_STANDBYWFI_IDLE (1<<6)
33#define S3C2412_PWRCFG_STANDBYWFI_STOP (2<<6)
34#define S3C2412_PWRCFG_STANDBYWFI_SLEEP (3<<6)
35#define S3C2412_PWRCFG_STANDBYWFI_MASK (3<<6)
36
37#define S3C2412_PWRCFG_RTC_MASKIRQ (1<<8)
38#define S3C2412_PWRCFG_NAND_NORST (1<<9)
39
40#endif /* __ASM_ARM_REGS_PWR */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h
deleted file mode 100644
index fb6352515090..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2412-mem.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * S3C2412 memory register definitions
12*/
13
14#ifndef __ASM_ARM_REGS_S3C2412_MEM
15#define __ASM_ARM_REGS_S3C2412_MEM
16
17#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
18#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x))
19
20#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x))
21#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o)))
22
23#define S3C2412_BANKCFG S3C2412_MEMREG(0x00)
24#define S3C2412_BANKCON1 S3C2412_MEMREG(0x04)
25#define S3C2412_BANKCON2 S3C2412_MEMREG(0x08)
26#define S3C2412_BANKCON3 S3C2412_MEMREG(0x0C)
27
28#define S3C2412_REFRESH S3C2412_MEMREG(0x10)
29#define S3C2412_TIMEOUT S3C2412_MEMREG(0x14)
30
31/* EBI control registers */
32
33#define S3C2412_EBI_PR S3C2412_EBIREG(0x00)
34#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x04)
35
36/* SSMC control registers */
37
38#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x00)
39#define S3C2412_SMIDCYR(x) S3C2412_SSMC(x, 0x00)
40#define S3C2412_SMBWSTRD(x) S3C2412_SSMC(x, 0x04)
41#define S3C2412_SMBWSTWRR(x) S3C2412_SSMC(x, 0x08)
42#define S3C2412_SMBWSTOENR(x) S3C2412_SSMC(x, 0x0C)
43#define S3C2412_SMBWSTWENR(x) S3C2412_SSMC(x, 0x10)
44#define S3C2412_SMBCR(x) S3C2412_SSMC(x, 0x14)
45#define S3C2412_SMBSR(x) S3C2412_SSMC(x, 0x18)
46#define S3C2412_SMBWSTBRDR(x) S3C2412_SSMC(x, 0x1C)
47
48#endif /* __ASM_ARM_REGS_S3C2412_MEM */
diff --git a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c b/arch/arm/mach-s3c24xx/iotiming-s3c2410.c
index b1908e56da1b..4cd13ab6496b 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
+++ b/arch/arm/mach-s3c24xx/iotiming-s3c2410.c
@@ -1,5 +1,4 @@
1/* linux/arch/arm/plat-s3c24xx/s3c2410-iotiming.c 1/*
2 *
3 * Copyright (c) 2006-2009 Simtec Electronics 2 * Copyright (c) 2006-2009 Simtec Electronics
4 * http://armlinux.simtec.co.uk/ 3 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
@@ -20,11 +19,12 @@
20#include <linux/slab.h> 19#include <linux/slab.h>
21 20
22#include <mach/map.h> 21#include <mach/map.h>
23#include <mach/regs-mem.h>
24#include <mach/regs-clock.h> 22#include <mach/regs-clock.h>
25 23
26#include <plat/cpu-freq-core.h> 24#include <plat/cpu-freq-core.h>
27 25
26#include "regs-mem.h"
27
28#define print_ns(x) ((x) / 10), ((x) % 10) 28#define print_ns(x) ((x) / 10), ((x) % 10)
29 29
30/** 30/**
diff --git a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
index 48eee39ab369..663436d9db01 100644
--- a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
+++ b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
@@ -1,5 +1,4 @@
1/* linux/arch/arm/plat-s3c24xx/s3c2412-iotiming.c 1/*
2 *
3 * Copyright (c) 2006-2008 Simtec Electronics 2 * Copyright (c) 2006-2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/ 3 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
@@ -28,12 +27,12 @@
28#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
29#include <asm/mach/map.h> 28#include <asm/mach/map.h>
30 29
31#include <mach/regs-s3c2412-mem.h>
32
33#include <plat/cpu.h> 30#include <plat/cpu.h>
34#include <plat/cpu-freq-core.h> 31#include <plat/cpu-freq-core.h>
35#include <plat/clock.h> 32#include <plat/clock.h>
36 33
34#include "s3c2412.h"
35
37#define print_ns(x) ((x) / 10), ((x) % 10) 36#define print_ns(x) ((x) / 10), ((x) % 10)
38 37
39/** 38/**
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2412.c b/arch/arm/mach-s3c24xx/irq-s3c2412.c
index e65619ddbccc..67d763178d3f 100644
--- a/arch/arm/mach-s3c24xx/irq-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/irq-s3c2412.c
@@ -33,12 +33,13 @@
33 33
34#include <mach/regs-irq.h> 34#include <mach/regs-irq.h>
35#include <mach/regs-gpio.h> 35#include <mach/regs-gpio.h>
36#include <mach/regs-power.h>
37 36
38#include <plat/cpu.h> 37#include <plat/cpu.h>
39#include <plat/irq.h> 38#include <plat/irq.h>
40#include <plat/pm.h> 39#include <plat/pm.h>
41 40
41#include "s3c2412-power.h"
42
42#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1) 43#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
43#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0)))) 44#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))
44 45
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c
index cb9f5e011e73..cb9f5e011e73 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/mach-s3c24xx/irq.c
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index 3c4b6e30c742..bb595f15ce36 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -34,7 +34,6 @@
34 34
35#include <plat/regs-serial.h> 35#include <plat/regs-serial.h>
36#include <mach/regs-gpio.h> 36#include <mach/regs-gpio.h>
37#include <mach/regs-mem.h>
38#include <mach/regs-lcd.h> 37#include <mach/regs-lcd.h>
39#include <linux/platform_data/mtd-nand-s3c2410.h> 38#include <linux/platform_data/mtd-nand-s3c2410.h>
40#include <linux/platform_data/i2c-s3c2410.h> 39#include <linux/platform_data/i2c-s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index cdcd784e30c5..b4bc60c78ebb 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -35,7 +35,6 @@
35 35
36#include <plat/regs-serial.h> 36#include <plat/regs-serial.h>
37#include <mach/regs-gpio.h> 37#include <mach/regs-gpio.h>
38#include <mach/regs-mem.h>
39#include <mach/regs-lcd.h> 38#include <mach/regs-lcd.h>
40#include <linux/platform_data/mtd-nand-s3c2410.h> 39#include <linux/platform_data/mtd-nand-s3c2410.h>
41#include <linux/platform_data/i2c-s3c2410.h> 40#include <linux/platform_data/i2c-s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index 5c1e3dfb9ab3..ca6618081041 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -48,7 +48,6 @@
48#include <mach/hardware.h> 48#include <mach/hardware.h>
49#include <mach/regs-gpio.h> 49#include <mach/regs-gpio.h>
50#include <mach/regs-lcd.h> 50#include <mach/regs-lcd.h>
51#include <mach/regs-mem.h>
52 51
53#include <plat/clock.h> 52#include <plat/clock.h>
54#include <plat/cpu.h> 53#include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index b9782ac2237a..a25e8c5a7b4c 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -75,7 +75,6 @@
75#include <mach/hardware.h> 75#include <mach/hardware.h>
76#include <mach/regs-gpio.h> 76#include <mach/regs-gpio.h>
77#include <mach/regs-irq.h> 77#include <mach/regs-irq.h>
78#include <mach/regs-mem.h>
79 78
80#include <plat/cpu.h> 79#include <plat/cpu.h>
81#include <plat/devs.h> 80#include <plat/devs.h>
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index d7a172555238..54e83c1f780c 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -35,9 +35,7 @@
35#include <linux/platform_data/mtd-nand-s3c2410.h> 35#include <linux/platform_data/mtd-nand-s3c2410.h>
36#include <linux/platform_data/i2c-s3c2410.h> 36#include <linux/platform_data/i2c-s3c2410.h>
37 37
38#include <mach/regs-power.h>
39#include <mach/regs-gpio.h> 38#include <mach/regs-gpio.h>
40#include <mach/regs-mem.h>
41#include <mach/regs-lcd.h> 39#include <mach/regs-lcd.h>
42#include <mach/fb.h> 40#include <mach/fb.h>
43 41
@@ -56,6 +54,8 @@
56#include <plat/pm.h> 54#include <plat/pm.h>
57#include <linux/platform_data/usb-s3c2410_udc.h> 55#include <linux/platform_data/usb-s3c2410_udc.h>
58 56
57#include "s3c2412-power.h"
58
59static struct map_desc jive_iodesc[] __initdata = { 59static struct map_desc jive_iodesc[] __initdata = {
60}; 60};
61 61
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 2db09ade9b50..2865e5919f2c 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -40,7 +40,6 @@
40#include <plat/regs-serial.h> 40#include <plat/regs-serial.h>
41#include <mach/regs-gpio.h> 41#include <mach/regs-gpio.h>
42#include <linux/platform_data/leds-s3c24xx.h> 42#include <linux/platform_data/leds-s3c24xx.h>
43#include <mach/regs-mem.h>
44#include <mach/regs-lcd.h> 43#include <mach/regs-lcd.h>
45#include <mach/irqs.h> 44#include <mach/irqs.h>
46#include <linux/platform_data/mtd-nand-s3c2410.h> 45#include <linux/platform_data/mtd-nand-s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index 4b57f9aa0a8f..f60f749d709c 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -47,11 +47,11 @@
47 47
48#include <mach/hardware.h> 48#include <mach/hardware.h>
49#include <mach/regs-gpio.h> 49#include <mach/regs-gpio.h>
50#include <mach/regs-mem.h>
51#include <mach/regs-lcd.h> 50#include <mach/regs-lcd.h>
52 51
53#include "common.h" 52#include "common.h"
54#include "osiris.h" 53#include "osiris.h"
54#include "regs-mem.h"
55 55
56/* onboard perihperal map */ 56/* onboard perihperal map */
57 57
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2412.c b/arch/arm/mach-s3c24xx/pm-s3c2412.c
index 206765cc4092..2ce86a4fa760 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2412.c
@@ -26,13 +26,13 @@
26 26
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/regs-gpio.h> 28#include <mach/regs-gpio.h>
29#include <mach/regs-power.h>
30 29
31#include <plat/cpu.h> 30#include <plat/cpu.h>
32#include <plat/pm.h> 31#include <plat/pm.h>
33#include <plat/s3c2412.h> 32#include <plat/s3c2412.h>
34 33
35#include "regs-dsc.h" 34#include "regs-dsc.h"
35#include "s3c2412-power.h"
36 36
37extern void s3c2412_sleep_enter(void); 37extern void s3c2412_sleep_enter(void);
38 38
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2416.c b/arch/arm/mach-s3c24xx/pm-s3c2416.c
index 1bd4817b8eb8..db7435a9905c 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2416.c
@@ -16,12 +16,13 @@
16 16
17#include <asm/cacheflush.h> 17#include <asm/cacheflush.h>
18 18
19#include <mach/regs-power.h>
20#include <mach/regs-s3c2443-clock.h> 19#include <mach/regs-s3c2443-clock.h>
21 20
22#include <plat/cpu.h> 21#include <plat/cpu.h>
23#include <plat/pm.h> 22#include <plat/pm.h>
24 23
24#include "s3c2412-power.h"
25
25extern void s3c2412_sleep_enter(void); 26extern void s3c2412_sleep_enter(void);
26 27
27static int s3c2416_cpu_suspend(unsigned long arg) 28static int s3c2416_cpu_suspend(unsigned long arg)
diff --git a/arch/arm/mach-s3c24xx/pm.c b/arch/arm/mach-s3c24xx/pm.c
index 724755f0b0f5..caa5b7211380 100644
--- a/arch/arm/mach-s3c24xx/pm.c
+++ b/arch/arm/mach-s3c24xx/pm.c
@@ -38,7 +38,6 @@
38#include <plat/regs-serial.h> 38#include <plat/regs-serial.h>
39#include <mach/regs-clock.h> 39#include <mach/regs-clock.h>
40#include <mach/regs-gpio.h> 40#include <mach/regs-gpio.h>
41#include <mach/regs-mem.h>
42#include <mach/regs-irq.h> 41#include <mach/regs-irq.h>
43 42
44#include <asm/mach/time.h> 43#include <asm/mach/time.h>
@@ -46,6 +45,8 @@
46#include <plat/gpio-cfg.h> 45#include <plat/gpio-cfg.h>
47#include <plat/pm.h> 46#include <plat/pm.h>
48 47
48#include "regs-mem.h"
49
49#define PFX "s3c24xx-pm: " 50#define PFX "s3c24xx-pm: "
50 51
51static struct sleep_save core_save[] = { 52static struct sleep_save core_save[] = {
diff --git a/arch/arm/mach-s3c24xx/regs-mem.h b/arch/arm/mach-s3c24xx/regs-mem.h
new file mode 100644
index 000000000000..86b1258368c2
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/regs-mem.h
@@ -0,0 +1,54 @@
1/*
2 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
3 * http://www.simtec.co.uk/products/SWLINUX/
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * S3C2410 Memory Control register definitions
10 */
11
12#ifndef __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H
13#define __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H __FILE__
14
15#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
16
17#define S3C2410_BWSCON S3C2410_MEMREG(0x00)
18#define S3C2410_BANKCON0 S3C2410_MEMREG(0x04)
19#define S3C2410_BANKCON1 S3C2410_MEMREG(0x08)
20#define S3C2410_BANKCON2 S3C2410_MEMREG(0x0C)
21#define S3C2410_BANKCON3 S3C2410_MEMREG(0x10)
22#define S3C2410_BANKCON4 S3C2410_MEMREG(0x14)
23#define S3C2410_BANKCON5 S3C2410_MEMREG(0x18)
24#define S3C2410_BANKCON6 S3C2410_MEMREG(0x1C)
25#define S3C2410_BANKCON7 S3C2410_MEMREG(0x20)
26#define S3C2410_REFRESH S3C2410_MEMREG(0x24)
27#define S3C2410_BANKSIZE S3C2410_MEMREG(0x28)
28
29#define S3C2410_BWSCON_ST1 (1 << 7)
30#define S3C2410_BWSCON_ST2 (1 << 11)
31#define S3C2410_BWSCON_ST3 (1 << 15)
32#define S3C2410_BWSCON_ST4 (1 << 19)
33#define S3C2410_BWSCON_ST5 (1 << 23)
34
35#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
36
37#define S3C2410_BWSCON_WS (1 << 2)
38
39#define S3C2410_BANKCON_PMC16 (0x3)
40
41#define S3C2410_BANKCON_Tacp_SHIFT (2)
42#define S3C2410_BANKCON_Tcah_SHIFT (4)
43#define S3C2410_BANKCON_Tcoh_SHIFT (6)
44#define S3C2410_BANKCON_Tacc_SHIFT (8)
45#define S3C2410_BANKCON_Tcos_SHIFT (11)
46#define S3C2410_BANKCON_Tacs_SHIFT (13)
47
48#define S3C2410_BANKCON_SDRAM (0x3 << 15)
49
50#define S3C2410_REFRESH_SELF (1 << 22)
51
52#define S3C2410_BANKSIZE_MASK (0x7 << 0)
53
54#endif /* __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H */
diff --git a/arch/arm/mach-s3c24xx/s3c2412-power.h b/arch/arm/mach-s3c24xx/s3c2412-power.h
new file mode 100644
index 000000000000..1b02c5ddb31b
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/s3c2412-power.h
@@ -0,0 +1,37 @@
1/*
2 * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
3 * http://armlinux.simtec.co.uk/
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H
11#define __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H __FILE__
12
13#define S3C24XX_PWRREG(x) ((x) + S3C24XX_VA_CLKPWR)
14
15#define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20)
16#define S3C2412_PWRCFG S3C24XX_PWRREG(0x24)
17
18#define S3C2412_INFORM0 S3C24XX_PWRREG(0x70)
19#define S3C2412_INFORM1 S3C24XX_PWRREG(0x74)
20#define S3C2412_INFORM2 S3C24XX_PWRREG(0x78)
21#define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C)
22
23#define S3C2412_PWRCFG_BATF_IRQ (1 << 0)
24#define S3C2412_PWRCFG_BATF_IGNORE (2 << 0)
25#define S3C2412_PWRCFG_BATF_SLEEP (3 << 0)
26#define S3C2412_PWRCFG_BATF_MASK (3 << 0)
27
28#define S3C2412_PWRCFG_STANDBYWFI_IGNORE (0 << 6)
29#define S3C2412_PWRCFG_STANDBYWFI_IDLE (1 << 6)
30#define S3C2412_PWRCFG_STANDBYWFI_STOP (2 << 6)
31#define S3C2412_PWRCFG_STANDBYWFI_SLEEP (3 << 6)
32#define S3C2412_PWRCFG_STANDBYWFI_MASK (3 << 6)
33
34#define S3C2412_PWRCFG_RTC_MASKIRQ (1 << 8)
35#define S3C2412_PWRCFG_NAND_NORST (1 << 9)
36
37#endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H */
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index ec0b31818c51..0d592159a5c3 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -34,7 +34,6 @@
34#include <mach/hardware.h> 34#include <mach/hardware.h>
35#include <mach/regs-clock.h> 35#include <mach/regs-clock.h>
36#include <mach/regs-gpio.h> 36#include <mach/regs-gpio.h>
37#include <mach/regs-power.h>
38 37
39#include <plat/clock.h> 38#include <plat/clock.h>
40#include <plat/cpu.h> 39#include <plat/cpu.h>
@@ -49,6 +48,7 @@
49 48
50#include "common.h" 49#include "common.h"
51#include "regs-dsc.h" 50#include "regs-dsc.h"
51#include "s3c2412-power.h"
52 52
53#define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30) 53#define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30)
54#define S3C2412_SWRST_RESET (0x533C2412) 54#define S3C2412_SWRST_RESET (0x533C2412)
diff --git a/arch/arm/mach-s3c24xx/s3c2412.h b/arch/arm/mach-s3c24xx/s3c2412.h
new file mode 100644
index 000000000000..548ced42cbb7
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/s3c2412.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright (c) 2008 Simtec Electronics
3 * Ben Dooks <ben@simtec.co.uk>
4 * http://armlinux.simtec.co.uk/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_H
12#define __ARCH_ARM_REGS_S3C24XX_S3C2412_H __FILE__
13
14#define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
15#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x))
16
17#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x))
18#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o)))
19
20#define S3C2412_REFRESH S3C2412_MEMREG(0x10)
21
22#define S3C2412_EBI_BANKCFG S3C2412_EBIREG(0x4)
23
24#define S3C2412_SSMC_BANK(x) S3C2412_SSMC(x, 0x0)
25
26#endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_H */
diff --git a/arch/arm/mach-s3c24xx/simtec-pm.c b/arch/arm/mach-s3c24xx/simtec-pm.c
index 699f93171297..38a2f1fdebab 100644
--- a/arch/arm/mach-s3c24xx/simtec-pm.c
+++ b/arch/arm/mach-s3c24xx/simtec-pm.c
@@ -28,12 +28,13 @@
28 28
29#include <mach/map.h> 29#include <mach/map.h>
30#include <mach/regs-gpio.h> 30#include <mach/regs-gpio.h>
31#include <mach/regs-mem.h>
32 31
33#include <asm/mach-types.h> 32#include <asm/mach-types.h>
34 33
35#include <plat/pm.h> 34#include <plat/pm.h>
36 35
36#include "regs-mem.h"
37
37#define COPYRIGHT ", Copyright 2005 Simtec Electronics" 38#define COPYRIGHT ", Copyright 2005 Simtec Electronics"
38 39
39/* pm_simtec_init 40/* pm_simtec_init
diff --git a/arch/arm/mach-s3c24xx/sleep-s3c2410.S b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
index dd5b6388a5a5..25b212180bf5 100644
--- a/arch/arm/mach-s3c24xx/sleep-s3c2410.S
+++ b/arch/arm/mach-s3c24xx/sleep-s3c2410.S
@@ -31,9 +31,10 @@
31 31
32#include <mach/regs-gpio.h> 32#include <mach/regs-gpio.h>
33#include <mach/regs-clock.h> 33#include <mach/regs-clock.h>
34#include <mach/regs-mem.h>
35#include <plat/regs-serial.h> 34#include <plat/regs-serial.h>
36 35
36#include "regs-mem.h"
37
37 /* s3c2410_cpu_suspend 38 /* s3c2410_cpu_suspend
38 * 39 *
39 * put the cpu into sleep mode 40 * put the cpu into sleep mode
diff --git a/arch/arm/mach-s3c24xx/sleep.S b/arch/arm/mach-s3c24xx/sleep.S
index c56612569b40..7f378b662da6 100644
--- a/arch/arm/mach-s3c24xx/sleep.S
+++ b/arch/arm/mach-s3c24xx/sleep.S
@@ -31,7 +31,6 @@
31 31
32#include <mach/regs-gpio.h> 32#include <mach/regs-gpio.h>
33#include <mach/regs-clock.h> 33#include <mach/regs-clock.h>
34#include <mach/regs-mem.h>
35#include <plat/regs-serial.h> 34#include <plat/regs-serial.h>
36 35
37/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not 36/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
deleted file mode 100644
index 3bb5c8fd34a1..000000000000
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ /dev/null
@@ -1,117 +0,0 @@
1# Copyright 2007 Simtec Electronics
2#
3# Licensed under GPLv2
4
5config PLAT_S3C24XX
6 bool
7 depends on ARCH_S3C24XX
8 default y
9 select ARCH_REQUIRE_GPIOLIB
10 select NO_IOPORT
11 select S3C_DEV_NAND
12 select IRQ_DOMAIN
13 help
14 Base platform code for any Samsung S3C24XX device
15
16if PLAT_S3C24XX
17
18# low-level serial option nodes
19
20config CPU_LLSERIAL_S3C2410_ONLY
21 bool
22 default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
23
24config CPU_LLSERIAL_S3C2440_ONLY
25 bool
26 default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
27
28config CPU_LLSERIAL_S3C2410
29 bool
30 help
31 Selected if there is an S3C2410 (or register compatible) serial
32 low-level implementation needed
33
34config CPU_LLSERIAL_S3C2440
35 bool
36 help
37 Selected if there is an S3C2440 (or register compatible) serial
38 low-level implementation needed
39
40# code that is shared between a number of the s3c24xx implementations
41
42config S3C2410_CLOCK
43 bool
44 help
45 Clock code for the S3C2410, and similar processors which
46 is currently includes the S3C2410, S3C2440, S3C2442.
47
48config S3C24XX_DCLK
49 bool
50 help
51 Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
52
53# gpio configurations
54
55config S3C24XX_GPIO_EXTRA
56 int
57 default 128 if S3C24XX_GPIO_EXTRA128
58 default 64 if S3C24XX_GPIO_EXTRA64
59 default 16 if ARCH_H1940
60 default 0
61
62config S3C24XX_GPIO_EXTRA64
63 bool
64 help
65 Add an extra 64 gpio numbers to the available GPIO pool. This is
66 available for boards that need extra gpios for external devices.
67
68config S3C24XX_GPIO_EXTRA128
69 bool
70 help
71 Add an extra 128 gpio numbers to the available GPIO pool. This is
72 available for boards that need extra gpios for external devices.
73
74config S3C24XX_DMA
75 bool "S3C2410 DMA support"
76 depends on ARCH_S3C24XX
77 select S3C_DMA
78 help
79 S3C2410 DMA support. This is needed for drivers like sound which
80 use the S3C2410's DMA system to move data to and from the
81 peripheral blocks.
82
83config S3C2410_DMA_DEBUG
84 bool "S3C2410 DMA support debug"
85 depends on ARCH_S3C24XX && S3C2410_DMA
86 help
87 Enable debugging output for the DMA code. This option sends info
88 to the kernel log, at priority KERN_DEBUG.
89
90# common code for s3c24xx based machines, such as the SMDKs.
91
92# cpu frequency items common between s3c2410 and s3c2440/s3c2442
93
94config S3C2410_IOTIMING
95 bool
96 depends on CPU_FREQ_S3C24XX
97 help
98 Internal node to select io timing code that is common to the s3c2410
99 and s3c2440/s3c2442 cpu frequency support.
100
101config S3C2410_CPUFREQ_UTILS
102 bool
103 depends on CPU_FREQ_S3C24XX
104 help
105 Internal node to select timing code that is common to the s3c2410
106 and s3c2440/s3c244 cpu frequency support.
107
108# cpu frequency support common to s3c2412, s3c2413 and s3c2442
109
110config S3C2412_IOTIMING
111 bool
112 depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443)
113 help
114 Intel node to select io timing code that is common to the s3c2412
115 and the s3c2443.
116
117endif
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
deleted file mode 100644
index 9f60549c8da1..000000000000
--- a/arch/arm/plat-s3c24xx/Makefile
+++ /dev/null
@@ -1,27 +0,0 @@
1# arch/arm/plat-s3c24xx/Makefile
2#
3# Copyright 2007 Simtec Electronics
4#
5# Licensed under GPLv2
6
7obj-y :=
8obj-m :=
9obj-n :=
10obj- :=
11
12
13# Core files
14
15obj-y += irq.o
16obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o
17
18obj-$(CONFIG_CPU_FREQ_S3C24XX) += cpu-freq.o
19obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o
20
21# Architecture dependent builds
22
23obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o
24obj-$(CONFIG_S3C24XX_DMA) += dma.o
25obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o
26obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o
27obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 14:45:38 -0500