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-rw-r--r--arch/arm/common/edma.c31
-rw-r--r--arch/powerpc/boot/dts/mpc5121.dtsi1
-rw-r--r--arch/sh/drivers/dma/dma-sh.c2
-rw-r--r--arch/sh/include/asm/dma-register.h36
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c24
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c48
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c64
7 files changed, 119 insertions, 87 deletions
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 485be42519b9..88099175fc56 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -1414,6 +1414,34 @@ void edma_clear_event(unsigned channel)
1414} 1414}
1415EXPORT_SYMBOL(edma_clear_event); 1415EXPORT_SYMBOL(edma_clear_event);
1416 1416
1417/*
1418 * edma_assign_channel_eventq - move given channel to desired eventq
1419 * Arguments:
1420 * channel - channel number
1421 * eventq_no - queue to move the channel
1422 *
1423 * Can be used to move a channel to a selected event queue.
1424 */
1425void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no)
1426{
1427 unsigned ctlr;
1428
1429 ctlr = EDMA_CTLR(channel);
1430 channel = EDMA_CHAN_SLOT(channel);
1431
1432 if (channel >= edma_cc[ctlr]->num_channels)
1433 return;
1434
1435 /* default to low priority queue */
1436 if (eventq_no == EVENTQ_DEFAULT)
1437 eventq_no = edma_cc[ctlr]->default_queue;
1438 if (eventq_no >= edma_cc[ctlr]->num_tc)
1439 return;
1440
1441 map_dmach_queue(ctlr, channel, eventq_no);
1442}
1443EXPORT_SYMBOL(edma_assign_channel_eventq);
1444
1417static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, 1445static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
1418 struct edma *edma_cc) 1446 struct edma *edma_cc)
1419{ 1447{
@@ -1470,7 +1498,8 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
1470 queue_priority_map[i][1] = -1; 1498 queue_priority_map[i][1] = -1;
1471 1499
1472 pdata->queue_priority_mapping = queue_priority_map; 1500 pdata->queue_priority_mapping = queue_priority_map;
1473 pdata->default_queue = 0; 1501 /* Default queue has the lowest priority */
1502 pdata->default_queue = i - 1;
1474 1503
1475 return 0; 1504 return 0;
1476} 1505}
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
index 2c0e1552d20b..7f9d14f5c4da 100644
--- a/arch/powerpc/boot/dts/mpc5121.dtsi
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -498,6 +498,7 @@
498 compatible = "fsl,mpc5121-dma"; 498 compatible = "fsl,mpc5121-dma";
499 reg = <0x14000 0x1800>; 499 reg = <0x14000 0x1800>;
500 interrupts = <65 0x8>; 500 interrupts = <65 0x8>;
501 #dma-cells = <1>;
501 }; 502 };
502 }; 503 };
503 504
diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c
index b22565623142..afde2a7d3eb3 100644
--- a/arch/sh/drivers/dma/dma-sh.c
+++ b/arch/sh/drivers/dma/dma-sh.c
@@ -25,7 +25,7 @@
25 * Define the default configuration for dual address memory-memory transfer. 25 * Define the default configuration for dual address memory-memory transfer.
26 * The 0x400 value represents auto-request, external->external. 26 * The 0x400 value represents auto-request, external->external.
27 */ 27 */
28#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_INDEX2VAL(XMIT_SZ_32BIT)) 28#define RS_DUAL (DM_INC | SM_INC | RS_AUTO | TS_INDEX2VAL(XMIT_SZ_32BIT))
29 29
30static unsigned long dma_find_base(unsigned int chan) 30static unsigned long dma_find_base(unsigned int chan)
31{ 31{
diff --git a/arch/sh/include/asm/dma-register.h b/arch/sh/include/asm/dma-register.h
index 51cd78feacff..c757b47e6b64 100644
--- a/arch/sh/include/asm/dma-register.h
+++ b/arch/sh/include/asm/dma-register.h
@@ -13,17 +13,17 @@
13#ifndef DMA_REGISTER_H 13#ifndef DMA_REGISTER_H
14#define DMA_REGISTER_H 14#define DMA_REGISTER_H
15 15
16/* DMA register */ 16/* DMA registers */
17#define SAR 0x00 17#define SAR 0x00 /* Source Address Register */
18#define DAR 0x04 18#define DAR 0x04 /* Destination Address Register */
19#define TCR 0x08 19#define TCR 0x08 /* Transfer Count Register */
20#define CHCR 0x0C 20#define CHCR 0x0C /* Channel Control Register */
21#define DMAOR 0x40 21#define DMAOR 0x40 /* DMA Operation Register */
22 22
23/* DMAOR definitions */ 23/* DMAOR definitions */
24#define DMAOR_AE 0x00000004 24#define DMAOR_AE 0x00000004 /* Address Error Flag */
25#define DMAOR_NMIF 0x00000002 25#define DMAOR_NMIF 0x00000002
26#define DMAOR_DME 0x00000001 26#define DMAOR_DME 0x00000001 /* DMA Master Enable */
27 27
28/* Definitions for the SuperH DMAC */ 28/* Definitions for the SuperH DMAC */
29#define REQ_L 0x00000000 29#define REQ_L 0x00000000
@@ -34,18 +34,20 @@
34#define ACK_W 0x00020000 34#define ACK_W 0x00020000
35#define ACK_H 0x00000000 35#define ACK_H 0x00000000
36#define ACK_L 0x00010000 36#define ACK_L 0x00010000
37#define DM_INC 0x00004000 37#define DM_INC 0x00004000 /* Destination addresses are incremented */
38#define DM_DEC 0x00008000 38#define DM_DEC 0x00008000 /* Destination addresses are decremented */
39#define DM_FIX 0x0000c000 39#define DM_FIX 0x0000c000 /* Destination address is fixed */
40#define SM_INC 0x00001000 40#define SM_INC 0x00001000 /* Source addresses are incremented */
41#define SM_DEC 0x00002000 41#define SM_DEC 0x00002000 /* Source addresses are decremented */
42#define SM_FIX 0x00003000 42#define SM_FIX 0x00003000 /* Source address is fixed */
43#define RS_IN 0x00000200 43#define RS_IN 0x00000200
44#define RS_OUT 0x00000300 44#define RS_OUT 0x00000300
45#define RS_AUTO 0x00000400 /* Auto Request */
46#define RS_ERS 0x00000800 /* DMA extended resource selector */
45#define TS_BLK 0x00000040 47#define TS_BLK 0x00000040
46#define TM_BUR 0x00000020 48#define TM_BUR 0x00000020
47#define CHCR_DE 0x00000001 49#define CHCR_DE 0x00000001 /* DMA Enable */
48#define CHCR_TE 0x00000002 50#define CHCR_TE 0x00000002 /* Transfer End Flag */
49#define CHCR_IE 0x00000004 51#define CHCR_IE 0x00000004 /* Interrupt Enable */
50 52
51#endif 53#endif
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 57f83a92a505..7aa733307afc 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -30,62 +30,62 @@ static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
30 { 30 {
31 .slave_id = SHDMA_SLAVE_SCIF0_TX, 31 .slave_id = SHDMA_SLAVE_SCIF0_TX,
32 .addr = 0xffe0000c, 32 .addr = 0xffe0000c,
33 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 33 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
34 .mid_rid = 0x21, 34 .mid_rid = 0x21,
35 }, { 35 }, {
36 .slave_id = SHDMA_SLAVE_SCIF0_RX, 36 .slave_id = SHDMA_SLAVE_SCIF0_RX,
37 .addr = 0xffe00014, 37 .addr = 0xffe00014,
38 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 38 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
39 .mid_rid = 0x22, 39 .mid_rid = 0x22,
40 }, { 40 }, {
41 .slave_id = SHDMA_SLAVE_SCIF1_TX, 41 .slave_id = SHDMA_SLAVE_SCIF1_TX,
42 .addr = 0xffe1000c, 42 .addr = 0xffe1000c,
43 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 43 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
44 .mid_rid = 0x25, 44 .mid_rid = 0x25,
45 }, { 45 }, {
46 .slave_id = SHDMA_SLAVE_SCIF1_RX, 46 .slave_id = SHDMA_SLAVE_SCIF1_RX,
47 .addr = 0xffe10014, 47 .addr = 0xffe10014,
48 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 48 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
49 .mid_rid = 0x26, 49 .mid_rid = 0x26,
50 }, { 50 }, {
51 .slave_id = SHDMA_SLAVE_SCIF2_TX, 51 .slave_id = SHDMA_SLAVE_SCIF2_TX,
52 .addr = 0xffe2000c, 52 .addr = 0xffe2000c,
53 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 53 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
54 .mid_rid = 0x29, 54 .mid_rid = 0x29,
55 }, { 55 }, {
56 .slave_id = SHDMA_SLAVE_SCIF2_RX, 56 .slave_id = SHDMA_SLAVE_SCIF2_RX,
57 .addr = 0xffe20014, 57 .addr = 0xffe20014,
58 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 58 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
59 .mid_rid = 0x2a, 59 .mid_rid = 0x2a,
60 }, { 60 }, {
61 .slave_id = SHDMA_SLAVE_SIUA_TX, 61 .slave_id = SHDMA_SLAVE_SIUA_TX,
62 .addr = 0xa454c098, 62 .addr = 0xa454c098,
63 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 63 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
64 .mid_rid = 0xb1, 64 .mid_rid = 0xb1,
65 }, { 65 }, {
66 .slave_id = SHDMA_SLAVE_SIUA_RX, 66 .slave_id = SHDMA_SLAVE_SIUA_RX,
67 .addr = 0xa454c090, 67 .addr = 0xa454c090,
68 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 68 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
69 .mid_rid = 0xb2, 69 .mid_rid = 0xb2,
70 }, { 70 }, {
71 .slave_id = SHDMA_SLAVE_SIUB_TX, 71 .slave_id = SHDMA_SLAVE_SIUB_TX,
72 .addr = 0xa454c09c, 72 .addr = 0xa454c09c,
73 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 73 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
74 .mid_rid = 0xb5, 74 .mid_rid = 0xb5,
75 }, { 75 }, {
76 .slave_id = SHDMA_SLAVE_SIUB_RX, 76 .slave_id = SHDMA_SLAVE_SIUB_RX,
77 .addr = 0xa454c094, 77 .addr = 0xa454c094,
78 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 78 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
79 .mid_rid = 0xb6, 79 .mid_rid = 0xb6,
80 }, { 80 }, {
81 .slave_id = SHDMA_SLAVE_SDHI0_TX, 81 .slave_id = SHDMA_SLAVE_SDHI0_TX,
82 .addr = 0x04ce0030, 82 .addr = 0x04ce0030,
83 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 83 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
84 .mid_rid = 0xc1, 84 .mid_rid = 0xc1,
85 }, { 85 }, {
86 .slave_id = SHDMA_SLAVE_SDHI0_RX, 86 .slave_id = SHDMA_SLAVE_SDHI0_RX,
87 .addr = 0x04ce0030, 87 .addr = 0x04ce0030,
88 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 88 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
89 .mid_rid = 0xc2, 89 .mid_rid = 0xc2,
90 }, 90 },
91}; 91};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index b9e84b1d3aa7..ea5780b3c7f6 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -36,122 +36,122 @@ static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = {
36 { 36 {
37 .slave_id = SHDMA_SLAVE_SCIF0_TX, 37 .slave_id = SHDMA_SLAVE_SCIF0_TX,
38 .addr = 0xffe0000c, 38 .addr = 0xffe0000c,
39 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 39 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
40 .mid_rid = 0x21, 40 .mid_rid = 0x21,
41 }, { 41 }, {
42 .slave_id = SHDMA_SLAVE_SCIF0_RX, 42 .slave_id = SHDMA_SLAVE_SCIF0_RX,
43 .addr = 0xffe00014, 43 .addr = 0xffe00014,
44 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 44 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
45 .mid_rid = 0x22, 45 .mid_rid = 0x22,
46 }, { 46 }, {
47 .slave_id = SHDMA_SLAVE_SCIF1_TX, 47 .slave_id = SHDMA_SLAVE_SCIF1_TX,
48 .addr = 0xffe1000c, 48 .addr = 0xffe1000c,
49 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 49 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
50 .mid_rid = 0x25, 50 .mid_rid = 0x25,
51 }, { 51 }, {
52 .slave_id = SHDMA_SLAVE_SCIF1_RX, 52 .slave_id = SHDMA_SLAVE_SCIF1_RX,
53 .addr = 0xffe10014, 53 .addr = 0xffe10014,
54 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 54 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
55 .mid_rid = 0x26, 55 .mid_rid = 0x26,
56 }, { 56 }, {
57 .slave_id = SHDMA_SLAVE_SCIF2_TX, 57 .slave_id = SHDMA_SLAVE_SCIF2_TX,
58 .addr = 0xffe2000c, 58 .addr = 0xffe2000c,
59 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 59 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
60 .mid_rid = 0x29, 60 .mid_rid = 0x29,
61 }, { 61 }, {
62 .slave_id = SHDMA_SLAVE_SCIF2_RX, 62 .slave_id = SHDMA_SLAVE_SCIF2_RX,
63 .addr = 0xffe20014, 63 .addr = 0xffe20014,
64 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 64 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
65 .mid_rid = 0x2a, 65 .mid_rid = 0x2a,
66 }, { 66 }, {
67 .slave_id = SHDMA_SLAVE_SCIF3_TX, 67 .slave_id = SHDMA_SLAVE_SCIF3_TX,
68 .addr = 0xa4e30020, 68 .addr = 0xa4e30020,
69 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 69 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
70 .mid_rid = 0x2d, 70 .mid_rid = 0x2d,
71 }, { 71 }, {
72 .slave_id = SHDMA_SLAVE_SCIF3_RX, 72 .slave_id = SHDMA_SLAVE_SCIF3_RX,
73 .addr = 0xa4e30024, 73 .addr = 0xa4e30024,
74 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 74 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
75 .mid_rid = 0x2e, 75 .mid_rid = 0x2e,
76 }, { 76 }, {
77 .slave_id = SHDMA_SLAVE_SCIF4_TX, 77 .slave_id = SHDMA_SLAVE_SCIF4_TX,
78 .addr = 0xa4e40020, 78 .addr = 0xa4e40020,
79 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 79 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
80 .mid_rid = 0x31, 80 .mid_rid = 0x31,
81 }, { 81 }, {
82 .slave_id = SHDMA_SLAVE_SCIF4_RX, 82 .slave_id = SHDMA_SLAVE_SCIF4_RX,
83 .addr = 0xa4e40024, 83 .addr = 0xa4e40024,
84 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 84 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
85 .mid_rid = 0x32, 85 .mid_rid = 0x32,
86 }, { 86 }, {
87 .slave_id = SHDMA_SLAVE_SCIF5_TX, 87 .slave_id = SHDMA_SLAVE_SCIF5_TX,
88 .addr = 0xa4e50020, 88 .addr = 0xa4e50020,
89 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 89 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
90 .mid_rid = 0x35, 90 .mid_rid = 0x35,
91 }, { 91 }, {
92 .slave_id = SHDMA_SLAVE_SCIF5_RX, 92 .slave_id = SHDMA_SLAVE_SCIF5_RX,
93 .addr = 0xa4e50024, 93 .addr = 0xa4e50024,
94 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 94 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT),
95 .mid_rid = 0x36, 95 .mid_rid = 0x36,
96 }, { 96 }, {
97 .slave_id = SHDMA_SLAVE_USB0D0_TX, 97 .slave_id = SHDMA_SLAVE_USB0D0_TX,
98 .addr = 0xA4D80100, 98 .addr = 0xA4D80100,
99 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 99 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
100 .mid_rid = 0x73, 100 .mid_rid = 0x73,
101 }, { 101 }, {
102 .slave_id = SHDMA_SLAVE_USB0D0_RX, 102 .slave_id = SHDMA_SLAVE_USB0D0_RX,
103 .addr = 0xA4D80100, 103 .addr = 0xA4D80100,
104 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 104 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
105 .mid_rid = 0x73, 105 .mid_rid = 0x73,
106 }, { 106 }, {
107 .slave_id = SHDMA_SLAVE_USB0D1_TX, 107 .slave_id = SHDMA_SLAVE_USB0D1_TX,
108 .addr = 0xA4D80120, 108 .addr = 0xA4D80120,
109 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 109 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
110 .mid_rid = 0x77, 110 .mid_rid = 0x77,
111 }, { 111 }, {
112 .slave_id = SHDMA_SLAVE_USB0D1_RX, 112 .slave_id = SHDMA_SLAVE_USB0D1_RX,
113 .addr = 0xA4D80120, 113 .addr = 0xA4D80120,
114 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 114 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
115 .mid_rid = 0x77, 115 .mid_rid = 0x77,
116 }, { 116 }, {
117 .slave_id = SHDMA_SLAVE_USB1D0_TX, 117 .slave_id = SHDMA_SLAVE_USB1D0_TX,
118 .addr = 0xA4D90100, 118 .addr = 0xA4D90100,
119 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 119 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
120 .mid_rid = 0xab, 120 .mid_rid = 0xab,
121 }, { 121 }, {
122 .slave_id = SHDMA_SLAVE_USB1D0_RX, 122 .slave_id = SHDMA_SLAVE_USB1D0_RX,
123 .addr = 0xA4D90100, 123 .addr = 0xA4D90100,
124 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 124 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
125 .mid_rid = 0xab, 125 .mid_rid = 0xab,
126 }, { 126 }, {
127 .slave_id = SHDMA_SLAVE_USB1D1_TX, 127 .slave_id = SHDMA_SLAVE_USB1D1_TX,
128 .addr = 0xA4D90120, 128 .addr = 0xA4D90120,
129 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 129 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
130 .mid_rid = 0xaf, 130 .mid_rid = 0xaf,
131 }, { 131 }, {
132 .slave_id = SHDMA_SLAVE_USB1D1_RX, 132 .slave_id = SHDMA_SLAVE_USB1D1_RX,
133 .addr = 0xA4D90120, 133 .addr = 0xA4D90120,
134 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 134 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT),
135 .mid_rid = 0xaf, 135 .mid_rid = 0xaf,
136 }, { 136 }, {
137 .slave_id = SHDMA_SLAVE_SDHI0_TX, 137 .slave_id = SHDMA_SLAVE_SDHI0_TX,
138 .addr = 0x04ce0030, 138 .addr = 0x04ce0030,
139 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 139 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
140 .mid_rid = 0xc1, 140 .mid_rid = 0xc1,
141 }, { 141 }, {
142 .slave_id = SHDMA_SLAVE_SDHI0_RX, 142 .slave_id = SHDMA_SLAVE_SDHI0_RX,
143 .addr = 0x04ce0030, 143 .addr = 0x04ce0030,
144 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 144 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
145 .mid_rid = 0xc2, 145 .mid_rid = 0xc2,
146 }, { 146 }, {
147 .slave_id = SHDMA_SLAVE_SDHI1_TX, 147 .slave_id = SHDMA_SLAVE_SDHI1_TX,
148 .addr = 0x04cf0030, 148 .addr = 0x04cf0030,
149 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 149 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
150 .mid_rid = 0xc9, 150 .mid_rid = 0xc9,
151 }, { 151 }, {
152 .slave_id = SHDMA_SLAVE_SDHI1_RX, 152 .slave_id = SHDMA_SLAVE_SDHI1_RX,
153 .addr = 0x04cf0030, 153 .addr = 0x04cf0030,
154 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 154 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT),
155 .mid_rid = 0xca, 155 .mid_rid = 0xca,
156 }, 156 },
157}; 157};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index 7b24ec4b409a..18bcd70cd813 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -123,28 +123,28 @@ static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = {
123 { 123 {
124 .slave_id = SHDMA_SLAVE_SDHI_TX, 124 .slave_id = SHDMA_SLAVE_SDHI_TX,
125 .addr = 0x1fe50030, 125 .addr = 0x1fe50030,
126 .chcr = SM_INC | 0x800 | 0x40000000 | 126 .chcr = SM_INC | RS_ERS | 0x40000000 |
127 TS_INDEX2VAL(XMIT_SZ_16BIT), 127 TS_INDEX2VAL(XMIT_SZ_16BIT),
128 .mid_rid = 0xc5, 128 .mid_rid = 0xc5,
129 }, 129 },
130 { 130 {
131 .slave_id = SHDMA_SLAVE_SDHI_RX, 131 .slave_id = SHDMA_SLAVE_SDHI_RX,
132 .addr = 0x1fe50030, 132 .addr = 0x1fe50030,
133 .chcr = DM_INC | 0x800 | 0x40000000 | 133 .chcr = DM_INC | RS_ERS | 0x40000000 |
134 TS_INDEX2VAL(XMIT_SZ_16BIT), 134 TS_INDEX2VAL(XMIT_SZ_16BIT),
135 .mid_rid = 0xc6, 135 .mid_rid = 0xc6,
136 }, 136 },
137 { 137 {
138 .slave_id = SHDMA_SLAVE_MMCIF_TX, 138 .slave_id = SHDMA_SLAVE_MMCIF_TX,
139 .addr = 0x1fcb0034, 139 .addr = 0x1fcb0034,
140 .chcr = SM_INC | 0x800 | 0x40000000 | 140 .chcr = SM_INC | RS_ERS | 0x40000000 |
141 TS_INDEX2VAL(XMIT_SZ_32BIT), 141 TS_INDEX2VAL(XMIT_SZ_32BIT),
142 .mid_rid = 0xd3, 142 .mid_rid = 0xd3,
143 }, 143 },
144 { 144 {
145 .slave_id = SHDMA_SLAVE_MMCIF_RX, 145 .slave_id = SHDMA_SLAVE_MMCIF_RX,
146 .addr = 0x1fcb0034, 146 .addr = 0x1fcb0034,
147 .chcr = DM_INC | 0x800 | 0x40000000 | 147 .chcr = DM_INC | RS_ERS | 0x40000000 |
148 TS_INDEX2VAL(XMIT_SZ_32BIT), 148 TS_INDEX2VAL(XMIT_SZ_32BIT),
149 .mid_rid = 0xd7, 149 .mid_rid = 0xd7,
150 }, 150 },
@@ -154,56 +154,56 @@ static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = {
154 { 154 {
155 .slave_id = SHDMA_SLAVE_SCIF2_TX, 155 .slave_id = SHDMA_SLAVE_SCIF2_TX,
156 .addr = 0x1f4b000c, 156 .addr = 0x1f4b000c,
157 .chcr = SM_INC | 0x800 | 0x40000000 | 157 .chcr = SM_INC | RS_ERS | 0x40000000 |
158 TS_INDEX2VAL(XMIT_SZ_8BIT), 158 TS_INDEX2VAL(XMIT_SZ_8BIT),
159 .mid_rid = 0x21, 159 .mid_rid = 0x21,
160 }, 160 },
161 { 161 {
162 .slave_id = SHDMA_SLAVE_SCIF2_RX, 162 .slave_id = SHDMA_SLAVE_SCIF2_RX,
163 .addr = 0x1f4b0014, 163 .addr = 0x1f4b0014,
164 .chcr = DM_INC | 0x800 | 0x40000000 | 164 .chcr = DM_INC | RS_ERS | 0x40000000 |
165 TS_INDEX2VAL(XMIT_SZ_8BIT), 165 TS_INDEX2VAL(XMIT_SZ_8BIT),
166 .mid_rid = 0x22, 166 .mid_rid = 0x22,
167 }, 167 },
168 { 168 {
169 .slave_id = SHDMA_SLAVE_SCIF3_TX, 169 .slave_id = SHDMA_SLAVE_SCIF3_TX,
170 .addr = 0x1f4c000c, 170 .addr = 0x1f4c000c,
171 .chcr = SM_INC | 0x800 | 0x40000000 | 171 .chcr = SM_INC | RS_ERS | 0x40000000 |
172 TS_INDEX2VAL(XMIT_SZ_8BIT), 172 TS_INDEX2VAL(XMIT_SZ_8BIT),
173 .mid_rid = 0x29, 173 .mid_rid = 0x29,
174 }, 174 },
175 { 175 {
176 .slave_id = SHDMA_SLAVE_SCIF3_RX, 176 .slave_id = SHDMA_SLAVE_SCIF3_RX,
177 .addr = 0x1f4c0014, 177 .addr = 0x1f4c0014,
178 .chcr = DM_INC | 0x800 | 0x40000000 | 178 .chcr = DM_INC | RS_ERS | 0x40000000 |
179 TS_INDEX2VAL(XMIT_SZ_8BIT), 179 TS_INDEX2VAL(XMIT_SZ_8BIT),
180 .mid_rid = 0x2a, 180 .mid_rid = 0x2a,
181 }, 181 },
182 { 182 {
183 .slave_id = SHDMA_SLAVE_SCIF4_TX, 183 .slave_id = SHDMA_SLAVE_SCIF4_TX,
184 .addr = 0x1f4d000c, 184 .addr = 0x1f4d000c,
185 .chcr = SM_INC | 0x800 | 0x40000000 | 185 .chcr = SM_INC | RS_ERS | 0x40000000 |
186 TS_INDEX2VAL(XMIT_SZ_8BIT), 186 TS_INDEX2VAL(XMIT_SZ_8BIT),
187 .mid_rid = 0x41, 187 .mid_rid = 0x41,
188 }, 188 },
189 { 189 {
190 .slave_id = SHDMA_SLAVE_SCIF4_RX, 190 .slave_id = SHDMA_SLAVE_SCIF4_RX,
191 .addr = 0x1f4d0014, 191 .addr = 0x1f4d0014,
192 .chcr = DM_INC | 0x800 | 0x40000000 | 192 .chcr = DM_INC | RS_ERS | 0x40000000 |
193 TS_INDEX2VAL(XMIT_SZ_8BIT), 193 TS_INDEX2VAL(XMIT_SZ_8BIT),
194 .mid_rid = 0x42, 194 .mid_rid = 0x42,
195 }, 195 },
196 { 196 {
197 .slave_id = SHDMA_SLAVE_RSPI_TX, 197 .slave_id = SHDMA_SLAVE_RSPI_TX,
198 .addr = 0xfe480004, 198 .addr = 0xfe480004,
199 .chcr = SM_INC | 0x800 | 0x40000000 | 199 .chcr = SM_INC | RS_ERS | 0x40000000 |
200 TS_INDEX2VAL(XMIT_SZ_16BIT), 200 TS_INDEX2VAL(XMIT_SZ_16BIT),
201 .mid_rid = 0xc1, 201 .mid_rid = 0xc1,
202 }, 202 },
203 { 203 {
204 .slave_id = SHDMA_SLAVE_RSPI_RX, 204 .slave_id = SHDMA_SLAVE_RSPI_RX,
205 .addr = 0xfe480004, 205 .addr = 0xfe480004,
206 .chcr = DM_INC | 0x800 | 0x40000000 | 206 .chcr = DM_INC | RS_ERS | 0x40000000 |
207 TS_INDEX2VAL(XMIT_SZ_16BIT), 207 TS_INDEX2VAL(XMIT_SZ_16BIT),
208 .mid_rid = 0xc2, 208 .mid_rid = 0xc2,
209 }, 209 },
@@ -213,70 +213,70 @@ static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = {
213 { 213 {
214 .slave_id = SHDMA_SLAVE_RIIC0_TX, 214 .slave_id = SHDMA_SLAVE_RIIC0_TX,
215 .addr = 0x1e500012, 215 .addr = 0x1e500012,
216 .chcr = SM_INC | 0x800 | 0x40000000 | 216 .chcr = SM_INC | RS_ERS | 0x40000000 |
217 TS_INDEX2VAL(XMIT_SZ_8BIT), 217 TS_INDEX2VAL(XMIT_SZ_8BIT),
218 .mid_rid = 0x21, 218 .mid_rid = 0x21,
219 }, 219 },
220 { 220 {
221 .slave_id = SHDMA_SLAVE_RIIC0_RX, 221 .slave_id = SHDMA_SLAVE_RIIC0_RX,
222 .addr = 0x1e500013, 222 .addr = 0x1e500013,
223 .chcr = DM_INC | 0x800 | 0x40000000 | 223 .chcr = DM_INC | RS_ERS | 0x40000000 |
224 TS_INDEX2VAL(XMIT_SZ_8BIT), 224 TS_INDEX2VAL(XMIT_SZ_8BIT),
225 .mid_rid = 0x22, 225 .mid_rid = 0x22,
226 }, 226 },
227 { 227 {
228 .slave_id = SHDMA_SLAVE_RIIC1_TX, 228 .slave_id = SHDMA_SLAVE_RIIC1_TX,
229 .addr = 0x1e510012, 229 .addr = 0x1e510012,
230 .chcr = SM_INC | 0x800 | 0x40000000 | 230 .chcr = SM_INC | RS_ERS | 0x40000000 |
231 TS_INDEX2VAL(XMIT_SZ_8BIT), 231 TS_INDEX2VAL(XMIT_SZ_8BIT),
232 .mid_rid = 0x29, 232 .mid_rid = 0x29,
233 }, 233 },
234 { 234 {
235 .slave_id = SHDMA_SLAVE_RIIC1_RX, 235 .slave_id = SHDMA_SLAVE_RIIC1_RX,
236 .addr = 0x1e510013, 236 .addr = 0x1e510013,
237 .chcr = DM_INC | 0x800 | 0x40000000 | 237 .chcr = DM_INC | RS_ERS | 0x40000000 |
238 TS_INDEX2VAL(XMIT_SZ_8BIT), 238 TS_INDEX2VAL(XMIT_SZ_8BIT),
239 .mid_rid = 0x2a, 239 .mid_rid = 0x2a,
240 }, 240 },
241 { 241 {
242 .slave_id = SHDMA_SLAVE_RIIC2_TX, 242 .slave_id = SHDMA_SLAVE_RIIC2_TX,
243 .addr = 0x1e520012, 243 .addr = 0x1e520012,
244 .chcr = SM_INC | 0x800 | 0x40000000 | 244 .chcr = SM_INC | RS_ERS | 0x40000000 |
245 TS_INDEX2VAL(XMIT_SZ_8BIT), 245 TS_INDEX2VAL(XMIT_SZ_8BIT),
246 .mid_rid = 0xa1, 246 .mid_rid = 0xa1,
247 }, 247 },
248 { 248 {
249 .slave_id = SHDMA_SLAVE_RIIC2_RX, 249 .slave_id = SHDMA_SLAVE_RIIC2_RX,
250 .addr = 0x1e520013, 250 .addr = 0x1e520013,
251 .chcr = DM_INC | 0x800 | 0x40000000 | 251 .chcr = DM_INC | RS_ERS | 0x40000000 |
252 TS_INDEX2VAL(XMIT_SZ_8BIT), 252 TS_INDEX2VAL(XMIT_SZ_8BIT),
253 .mid_rid = 0xa2, 253 .mid_rid = 0xa2,
254 }, 254 },
255 { 255 {
256 .slave_id = SHDMA_SLAVE_RIIC3_TX, 256 .slave_id = SHDMA_SLAVE_RIIC3_TX,
257 .addr = 0x1e530012, 257 .addr = 0x1e530012,
258 .chcr = SM_INC | 0x800 | 0x40000000 | 258 .chcr = SM_INC | RS_ERS | 0x40000000 |
259 TS_INDEX2VAL(XMIT_SZ_8BIT), 259 TS_INDEX2VAL(XMIT_SZ_8BIT),
260 .mid_rid = 0xa9, 260 .mid_rid = 0xa9,
261 }, 261 },
262 { 262 {
263 .slave_id = SHDMA_SLAVE_RIIC3_RX, 263 .slave_id = SHDMA_SLAVE_RIIC3_RX,
264 .addr = 0x1e530013, 264 .addr = 0x1e530013,
265 .chcr = DM_INC | 0x800 | 0x40000000 | 265 .chcr = DM_INC | RS_ERS | 0x40000000 |
266 TS_INDEX2VAL(XMIT_SZ_8BIT), 266 TS_INDEX2VAL(XMIT_SZ_8BIT),
267 .mid_rid = 0xaf, 267 .mid_rid = 0xaf,
268 }, 268 },
269 { 269 {
270 .slave_id = SHDMA_SLAVE_RIIC4_TX, 270 .slave_id = SHDMA_SLAVE_RIIC4_TX,
271 .addr = 0x1e540012, 271 .addr = 0x1e540012,
272 .chcr = SM_INC | 0x800 | 0x40000000 | 272 .chcr = SM_INC | RS_ERS | 0x40000000 |
273 TS_INDEX2VAL(XMIT_SZ_8BIT), 273 TS_INDEX2VAL(XMIT_SZ_8BIT),
274 .mid_rid = 0xc5, 274 .mid_rid = 0xc5,
275 }, 275 },
276 { 276 {
277 .slave_id = SHDMA_SLAVE_RIIC4_RX, 277 .slave_id = SHDMA_SLAVE_RIIC4_RX,
278 .addr = 0x1e540013, 278 .addr = 0x1e540013,
279 .chcr = DM_INC | 0x800 | 0x40000000 | 279 .chcr = DM_INC | RS_ERS | 0x40000000 |
280 TS_INDEX2VAL(XMIT_SZ_8BIT), 280 TS_INDEX2VAL(XMIT_SZ_8BIT),
281 .mid_rid = 0xc6, 281 .mid_rid = 0xc6,
282 }, 282 },
@@ -286,70 +286,70 @@ static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = {
286 { 286 {
287 .slave_id = SHDMA_SLAVE_RIIC5_TX, 287 .slave_id = SHDMA_SLAVE_RIIC5_TX,
288 .addr = 0x1e550012, 288 .addr = 0x1e550012,
289 .chcr = SM_INC | 0x800 | 0x40000000 | 289 .chcr = SM_INC | RS_ERS | 0x40000000 |
290 TS_INDEX2VAL(XMIT_SZ_8BIT), 290 TS_INDEX2VAL(XMIT_SZ_8BIT),
291 .mid_rid = 0x21, 291 .mid_rid = 0x21,
292 }, 292 },
293 { 293 {
294 .slave_id = SHDMA_SLAVE_RIIC5_RX, 294 .slave_id = SHDMA_SLAVE_RIIC5_RX,
295 .addr = 0x1e550013, 295 .addr = 0x1e550013,
296 .chcr = DM_INC | 0x800 | 0x40000000 | 296 .chcr = DM_INC | RS_ERS | 0x40000000 |
297 TS_INDEX2VAL(XMIT_SZ_8BIT), 297 TS_INDEX2VAL(XMIT_SZ_8BIT),
298 .mid_rid = 0x22, 298 .mid_rid = 0x22,
299 }, 299 },
300 { 300 {
301 .slave_id = SHDMA_SLAVE_RIIC6_TX, 301 .slave_id = SHDMA_SLAVE_RIIC6_TX,
302 .addr = 0x1e560012, 302 .addr = 0x1e560012,
303 .chcr = SM_INC | 0x800 | 0x40000000 | 303 .chcr = SM_INC | RS_ERS | 0x40000000 |
304 TS_INDEX2VAL(XMIT_SZ_8BIT), 304 TS_INDEX2VAL(XMIT_SZ_8BIT),
305 .mid_rid = 0x29, 305 .mid_rid = 0x29,
306 }, 306 },
307 { 307 {
308 .slave_id = SHDMA_SLAVE_RIIC6_RX, 308 .slave_id = SHDMA_SLAVE_RIIC6_RX,
309 .addr = 0x1e560013, 309 .addr = 0x1e560013,
310 .chcr = DM_INC | 0x800 | 0x40000000 | 310 .chcr = DM_INC | RS_ERS | 0x40000000 |
311 TS_INDEX2VAL(XMIT_SZ_8BIT), 311 TS_INDEX2VAL(XMIT_SZ_8BIT),
312 .mid_rid = 0x2a, 312 .mid_rid = 0x2a,
313 }, 313 },
314 { 314 {
315 .slave_id = SHDMA_SLAVE_RIIC7_TX, 315 .slave_id = SHDMA_SLAVE_RIIC7_TX,
316 .addr = 0x1e570012, 316 .addr = 0x1e570012,
317 .chcr = SM_INC | 0x800 | 0x40000000 | 317 .chcr = SM_INC | RS_ERS | 0x40000000 |
318 TS_INDEX2VAL(XMIT_SZ_8BIT), 318 TS_INDEX2VAL(XMIT_SZ_8BIT),
319 .mid_rid = 0x41, 319 .mid_rid = 0x41,
320 }, 320 },
321 { 321 {
322 .slave_id = SHDMA_SLAVE_RIIC7_RX, 322 .slave_id = SHDMA_SLAVE_RIIC7_RX,
323 .addr = 0x1e570013, 323 .addr = 0x1e570013,
324 .chcr = DM_INC | 0x800 | 0x40000000 | 324 .chcr = DM_INC | RS_ERS | 0x40000000 |
325 TS_INDEX2VAL(XMIT_SZ_8BIT), 325 TS_INDEX2VAL(XMIT_SZ_8BIT),
326 .mid_rid = 0x42, 326 .mid_rid = 0x42,
327 }, 327 },
328 { 328 {
329 .slave_id = SHDMA_SLAVE_RIIC8_TX, 329 .slave_id = SHDMA_SLAVE_RIIC8_TX,
330 .addr = 0x1e580012, 330 .addr = 0x1e580012,
331 .chcr = SM_INC | 0x800 | 0x40000000 | 331 .chcr = SM_INC | RS_ERS | 0x40000000 |
332 TS_INDEX2VAL(XMIT_SZ_8BIT), 332 TS_INDEX2VAL(XMIT_SZ_8BIT),
333 .mid_rid = 0x45, 333 .mid_rid = 0x45,
334 }, 334 },
335 { 335 {
336 .slave_id = SHDMA_SLAVE_RIIC8_RX, 336 .slave_id = SHDMA_SLAVE_RIIC8_RX,
337 .addr = 0x1e580013, 337 .addr = 0x1e580013,
338 .chcr = DM_INC | 0x800 | 0x40000000 | 338 .chcr = DM_INC | RS_ERS | 0x40000000 |
339 TS_INDEX2VAL(XMIT_SZ_8BIT), 339 TS_INDEX2VAL(XMIT_SZ_8BIT),
340 .mid_rid = 0x46, 340 .mid_rid = 0x46,
341 }, 341 },
342 { 342 {
343 .slave_id = SHDMA_SLAVE_RIIC9_TX, 343 .slave_id = SHDMA_SLAVE_RIIC9_TX,
344 .addr = 0x1e590012, 344 .addr = 0x1e590012,
345 .chcr = SM_INC | 0x800 | 0x40000000 | 345 .chcr = SM_INC | RS_ERS | 0x40000000 |
346 TS_INDEX2VAL(XMIT_SZ_8BIT), 346 TS_INDEX2VAL(XMIT_SZ_8BIT),
347 .mid_rid = 0x51, 347 .mid_rid = 0x51,
348 }, 348 },
349 { 349 {
350 .slave_id = SHDMA_SLAVE_RIIC9_RX, 350 .slave_id = SHDMA_SLAVE_RIIC9_RX,
351 .addr = 0x1e590013, 351 .addr = 0x1e590013,
352 .chcr = DM_INC | 0x800 | 0x40000000 | 352 .chcr = DM_INC | RS_ERS | 0x40000000 |
353 TS_INDEX2VAL(XMIT_SZ_8BIT), 353 TS_INDEX2VAL(XMIT_SZ_8BIT),
354 .mid_rid = 0x52, 354 .mid_rid = 0x52,
355 }, 355 },
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 06:19:14 -0400