61 files changed, 492 insertions, 388 deletions
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 63d7578856c1..a1dd2ee83753 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -29,6 +29,7 @@
                compatible = "arm,cortex-a9-gic";
                #interrupt-cells = <3>;
                interrupt-controller;
+                cpu-offset = <0x8000>;
                reg = <0x10490000 0x1000>, <0x10480000 0x100>;
        };
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 1a1d7023b69b..825d2957da0b 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -46,11 +46,11 @@
        };
        serial@70006200 {
-                status = "disable";
+                clock-frequency = <216000000>;
        };
        serial@70006300 {
-                clock-frequency = <216000000>;
+                status = "disable";
        };
        serial@70006400 {
@@ -60,7 +60,7 @@
        sdhci@c8000000 {
                cd-gpios = <&gpio 173 0>; /* gpio PV5 */
                wp-gpios = <&gpio 57 0>;  /* gpio PH1 */
-                power-gpios = <&gpio 155 0>; /* gpio PT3 */
+                power-gpios = <&gpio 169 0>; /* gpio PV1 */
        };
        sdhci@c8000200 {
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 18bacec2b094..97676bdae998 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -83,7 +83,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
 *  USB Device (Gadget)
 * -------------------------------------------------------------------- */
-#ifdef CONFIG_USB_AT91
+#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
 static struct at91_udc_data udc_data;
 static struct resource udc_resources[] = {
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 642ccb6d26b2..5a24f0b4554d 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -84,7 +84,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
 *  USB Device (Gadget)
 * -------------------------------------------------------------------- */
-#ifdef CONFIG_USB_AT91
+#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
 static struct at91_udc_data udc_data;
 static struct resource udc_resources[] = {
@@ -1215,8 +1215,7 @@ void __init at91_add_device_serial(void) {}
 *  CF/IDE
 * -------------------------------------------------------------------- */
-#if defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) || \
+#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
-        defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
        defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
 static struct at91_cf_data cf0_data;
@@ -1313,10 +1312,8 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
        if (data->flags & AT91_CF_TRUE_IDE)
 #if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE)
                pdev->name = "pata_at91";
-#elif defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE)
-                pdev->name = "at91_ide";
 #else
-#warning "board requires AT91_CF_TRUE_IDE: enable either at91_ide or pata_at91"
+#warning "board requires AT91_CF_TRUE_IDE: enable pata_at91"
 #endif
        else
                pdev->name = "at91_cf";
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index fc59cbdb0e3c..1e28bed8f425 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -87,7 +87,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
 *  USB Device (Gadget)
 * -------------------------------------------------------------------- */
-#ifdef CONFIG_USB_AT91
+#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
 static struct at91_udc_data udc_data;
 static struct resource udc_resources[] = {
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 7b46b2787022..366a7765635b 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -92,7 +92,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
 *  USB Device (Gadget)
 * -------------------------------------------------------------------- */
-#ifdef CONFIG_USB_AT91
+#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
 static struct at91_udc_data udc_data;
 static struct resource udc_resources[] = {
@@ -355,8 +355,8 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
 *  Compact Flash (PCMCIA or IDE)
 * -------------------------------------------------------------------- */
-#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) || \
+#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
-    defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE)
+        defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
 static struct at91_cf_data cf0_data;
@@ -450,7 +450,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
        at91_set_A_periph(AT91_PIN_PD9, 0);  /* CFCE2 */
        at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */
-        pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "at91_ide" : "at91_cf";
+        pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "pata_at91" : "at91_cf";
        platform_device_register(pdev);
 }
 #else
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
index eb18a70fa647..175e1fdd9fe8 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
@@ -18,6 +18,35 @@
 #include <mach/cpu.h>
+#ifndef __ASSEMBLY__
+struct sam9_smc_config {
+        /* Setup register */
+        u8 ncs_read_setup;
+        u8 nrd_setup;
+        u8 ncs_write_setup;
+        u8 nwe_setup;
+        /* Pulse register */
+        u8 ncs_read_pulse;
+        u8 nrd_pulse;
+        u8 ncs_write_pulse;
+        u8 nwe_pulse;
+        /* Cycle register */
+        u16 read_cycle;
+        u16 write_cycle;
+        /* Mode register */
+        u32 mode;
+        u8 tdf_cycles:4;
+};
+extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
+extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config);
+extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config);
+extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
+#endif
 #define AT91_SMC_SETUP          0x00                            /* Setup Register for CS n */
 #define         AT91_SMC_NWESETUP       (0x3f << 0)                     /* NWE Setup Length */
 #define                 AT91_SMC_NWESETUP_(x)   ((x) << 0)
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index 8294783b679d..99a0a1d2b7dc 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -2,6 +2,7 @@
 * linux/arch/arm/mach-at91/sam9_smc.c
 *
 * Copyright (C) 2008 Andrew Victor
+ * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
@@ -22,7 +23,22 @@
 static void __iomem *smc_base_addr[2];
-static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_config* config)
+static void sam9_smc_cs_write_mode(void __iomem *base,
+                                        struct sam9_smc_config *config)
+{
+        __raw_writel(config->mode
+                   | AT91_SMC_TDF_(config->tdf_cycles),
+                   base + AT91_SMC_MODE);
+}
+void sam9_smc_write_mode(int id, int cs,
+                                        struct sam9_smc_config *config)
+{
+        sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config);
+}
+static void sam9_smc_cs_configure(void __iomem *base,
+                                        struct sam9_smc_config *config)
 {
        /* Setup register */
@@ -45,16 +61,66 @@ static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_con
                   base + AT91_SMC_CYCLE);
        /* Mode register */
-        __raw_writel(config->mode
+        sam9_smc_cs_write_mode(base, config);
-                   | AT91_SMC_TDF_(config->tdf_cycles),
-                   base + AT91_SMC_MODE);
 }
-void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config)
+void sam9_smc_configure(int id, int cs,
+                                        struct sam9_smc_config *config)
 {
        sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config);
 }
+static void sam9_smc_cs_read_mode(void __iomem *base,
+                                        struct sam9_smc_config *config)
+{
+        u32 val = __raw_readl(base + AT91_SMC_MODE);
+        config->mode = (val & ~AT91_SMC_NWECYCLE);
+        config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ;
+}
+void sam9_smc_read_mode(int id, int cs,
+                                        struct sam9_smc_config *config)
+{
+        sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config);
+}
+static void sam9_smc_cs_read(void __iomem *base,
+                                        struct sam9_smc_config *config)
+{
+        u32 val;
+        /* Setup register */
+        val = __raw_readl(base + AT91_SMC_SETUP);
+        config->nwe_setup = val & AT91_SMC_NWESETUP;
+        config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8;
+        config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16;
+        config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24;
+        /* Pulse register */
+        val = __raw_readl(base + AT91_SMC_PULSE);
+        config->nwe_setup = val & AT91_SMC_NWEPULSE;
+        config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8;
+        config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16;
+        config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24;
+        /* Cycle register */
+        val = __raw_readl(base + AT91_SMC_CYCLE);
+        config->write_cycle = val & AT91_SMC_NWECYCLE;
+        config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16;
+        /* Mode register */
+        sam9_smc_cs_read_mode(base, config);
+}
+void sam9_smc_read(int id, int cs, struct sam9_smc_config *config)
+{
+        sam9_smc_cs_read(AT91_SMC_CS(id, cs), config);
+}
 void __init at91sam9_ioremap_smc(int id, u32 addr)
 {
        if (id > 1) {
diff --git a/arch/arm/mach-at91/sam9_smc.h b/arch/arm/mach-at91/sam9_smc.h
index 039c5ce17aec..3e52dcd4a59f 100644
--- a/arch/arm/mach-at91/sam9_smc.h
+++ b/arch/arm/mach-at91/sam9_smc.h
@@ -8,27 +8,4 @@
 * published by the Free Software Foundation.
 */
-struct sam9_smc_config {
-        /* Setup register */
-        u8 ncs_read_setup;
-        u8 nrd_setup;
-        u8 ncs_write_setup;
-        u8 nwe_setup;
-        /* Pulse register */
-        u8 ncs_read_pulse;
-        u8 nrd_pulse;
-        u8 ncs_write_pulse;
-        u8 nwe_pulse;
-        /* Cycle register */
-        u16 read_cycle;
-        u16 write_cycle;
-        /* Mode register */
-        u32 mode;
-        u8 tdf_cycles:4;
-};
-extern void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config);
 extern void __init at91sam9_ioremap_smc(int id, u32 addr);
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index dd1429ae6405..bda7aca04ca0 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -28,6 +28,7 @@
 #include <asm/mach/arch.h>
 #include <linux/irq.h>
 #include <plat/time.h>
+#include <plat/ehci-orion.h>
 #include <plat/common.h>
 #include <plat/addr-map.h>
 #include "common.h"
@@ -71,7 +72,7 @@ void __init dove_map_io(void)
 ****************************************************************************/
 void __init dove_ehci0_init(void)
 {
-        orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
+        orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
 }
 /*****************************************************************************
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
index 03dd4012043e..d5fb44f16d31 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -32,6 +32,7 @@
 #include <mach/hardware.h>
 #include <mach/fb.h>
 #include <mach/ep93xx_spi.h>
+#include <mach/gpio-ep93xx.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
@@ -153,7 +154,6 @@ static struct i2c_board_info vision_i2c_info[] __initdata = {
        }, {
                I2C_BOARD_INFO("pca9539", 0x74),
                .platform_data  = &pca953x_74_gpio_data,
-                .irq            = gpio_to_irq(EP93XX_GPIO_LINE_F(7)),
        }, {
                I2C_BOARD_INFO("pca9539", 0x75),
                .platform_data  = &pca953x_75_gpio_data,
@@ -348,6 +348,8 @@ static void __init vision_init_machine(void)
                                "pca9539:74"))
                pr_warn("cannot request interrupt gpio for pca9539:74\n");
+        vision_i2c_info[1].irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7));
        ep93xx_register_i2c(&vision_i2c_gpio_data, vision_i2c_info,
                                ARRAY_SIZE(vision_i2c_info));
        ep93xx_register_spi(&vision_spi_master, vision_spi_board_info,
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index a5823a7f249e..13312ccb2d93 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -32,6 +32,7 @@
 #include "common.h"
+#ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos4210_clock_save[] = {
        SAVE_ITEM(S5P_CLKSRC_IMAGE),
        SAVE_ITEM(S5P_CLKSRC_LCD1),
@@ -42,6 +43,7 @@ static struct sleep_save exynos4210_clock_save[] = {
        SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
        SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
 };
+#endif
 static struct clksrc_clk *sysclks[] = {
        /* nothing here yet */
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 26a668b0d101..48af28566fa1 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -32,12 +32,14 @@
 #include "common.h"
+#ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos4212_clock_save[] = {
        SAVE_ITEM(S5P_CLKSRC_IMAGE),
        SAVE_ITEM(S5P_CLKDIV_IMAGE),
        SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
        SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
 };
+#endif
 static struct clk *clk_src_mpll_user_list[] = {
        [0] = &clk_fin_mpll,
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 5a8c42e90005..187287aa57ab 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -30,6 +30,7 @@
 #include "common.h"
+#ifdef CONFIG_PM_SLEEP
 static struct sleep_save exynos4_clock_save[] = {
        SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
        SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
@@ -93,6 +94,7 @@ static struct sleep_save exynos4_clock_save[] = {
        SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
        SAVE_ITEM(S5P_CLKGATE_IP_CPU),
 };
+#endif
 struct clk clk_sclk_hdmi27m = {
        .name           = "sclk_hdmi27m",
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index 85fa02767d67..e6b02fdf1b09 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -15,11 +15,13 @@
 #include <linux/serial_core.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <mach/map.h>
 #include <plat/cpu.h>
 #include <plat/regs-serial.h>
-#include <plat/exynos4.h>
+#include "common.h"
 /*
 * The following lookup table is used to override device names when devices
@@ -60,7 +62,7 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
 static void __init exynos4210_dt_map_io(void)
 {
-        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        exynos_init_io(NULL, 0);
        s3c24xx_init_clocks(24000000);
 }
@@ -79,7 +81,9 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
        /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
        .init_irq       = exynos4_init_irq,
        .map_io         = exynos4210_dt_map_io,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = exynos4210_dt_machine_init,
        .timer          = &exynos4_timer,
        .dt_compat      = exynos4210_dt_compat,
+        .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index b895ec031105..435261f83f46 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -220,14 +220,14 @@ static struct s3c_fb_pd_win nuri_fb_win0 = {
                .lower_margin   = 1,
                .hsync_len      = 48,
                .vsync_len      = 3,
-                .xres           = 1280,
+                .xres           = 1024,
-                .yres           = 800,
+                .yres           = 600,
                .refresh        = 60,
        },
        .max_bpp        = 24,
        .default_bpp    = 16,
-        .virtual_x      = 1280,
+        .virtual_x      = 1024,
-        .virtual_y      = 800,
+        .virtual_y      = 2 * 600,
 };
 static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 37ac93e8d6d9..0fc65ffde8ff 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -910,7 +910,7 @@ static struct s5p_fimc_isp_info universal_camera_sensors[] = {
                .bus_type       = FIMC_MIPI_CSI2,
                .board_info     = &m5mols_board_info,
                .i2c_bus_num    = 0,
-                .clk_frequency  = 21600000UL,
+                .clk_frequency  = 24000000UL,
                .csi_data_align = 32,
        },
 };
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index a4f61a43c7ba..e19013051772 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -206,7 +206,7 @@ static void exynos4_pm_prepare(void)
 }
-static int exynos4_pm_add(struct device *dev)
+static int exynos4_pm_add(struct device *dev, struct subsys_interface *sif)
 {
        pm_cpu_prep = exynos4_pm_prepare;
        pm_cpu_sleep = exynos4_cpu_suspend;
@@ -384,7 +384,9 @@ static void exynos4_pm_resume(void)
        exynos4_restore_pll();
+#ifdef CONFIG_SMP
        scu_enable(S5P_VA_SCU);
+#endif
 #ifdef CONFIG_CACHE_L2X0
        s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index cc15426787b1..77d4852e19f2 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -27,6 +27,7 @@
 #include <plat/cache-feroceon-l2.h>
 #include <plat/mvsdio.h>
 #include <plat/orion_nand.h>
+#include <plat/ehci-orion.h>
 #include <plat/common.h>
 #include <plat/time.h>
 #include <plat/addr-map.h>
@@ -73,7 +74,7 @@ unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
 void __init kirkwood_ehci_init(void)
 {
        kirkwood_clk_ctrl |= CGC_USB0;
-        orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
+        orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
 }
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index e8fda45c0736..d5a0d1da2e0e 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -31,314 +31,314 @@
 #define MPP_F6282_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP0_GPIO               MPP(  0, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP0_NF_IO2             MPP(  0, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP0_NF_IO2             MPP(  0, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP0_SPI_SCn            MPP(  0, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP0_SPI_SCn            MPP(  0, 0x2, 0, 0, 1,   1,   1,   1,   1 )
 #define MPP1_GPO                MPP(  1, 0x0, 0, 1, 1,   1,   1,   1,   1 )
-#define MPP1_NF_IO3             MPP(  1, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP1_NF_IO3             MPP(  1, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP1_SPI_MOSI           MPP(  1, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP1_SPI_MOSI           MPP(  1, 0x2, 0, 0, 1,   1,   1,   1,   1 )
 #define MPP2_GPO                MPP(  2, 0x0, 0, 1, 1,   1,   1,   1,   1 )
-#define MPP2_NF_IO4             MPP(  2, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP2_NF_IO4             MPP(  2, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP2_SPI_SCK            MPP(  2, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP2_SPI_SCK            MPP(  2, 0x2, 0, 0, 1,   1,   1,   1,   1 )
 #define MPP3_GPO                MPP(  3, 0x0, 0, 1, 1,   1,   1,   1,   1 )
-#define MPP3_NF_IO5             MPP(  3, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP3_NF_IO5             MPP(  3, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP3_SPI_MISO           MPP(  3, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP3_SPI_MISO           MPP(  3, 0x2, 0, 0, 1,   1,   1,   1,   1 )
 #define MPP4_GPIO               MPP(  4, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP4_NF_IO6             MPP(  4, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP4_NF_IO6             MPP(  4, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP4_UART0_RXD          MPP(  4, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP4_UART0_RXD          MPP(  4, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP4_SATA1_ACTn         MPP(  4, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP4_SATA1_ACTn         MPP(  4, 0x5, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP4_LCD_VGA_HSYNC      MPP(  4, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP4_PTP_CLK            MPP(  4, 0xd, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP4_PTP_CLK            MPP(  4, 0xd, 0, 0, 1,   1,   1,   1,   0 )
 #define MPP5_GPO                MPP(  5, 0x0, 0, 1, 1,   1,   1,   1,   1 )
-#define MPP5_NF_IO7             MPP(  5, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP5_NF_IO7             MPP(  5, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP5_UART0_TXD          MPP(  5, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP5_UART0_TXD          MPP(  5, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP5_PTP_TRIG_GEN       MPP(  5, 0x4, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP5_PTP_TRIG_GEN       MPP(  5, 0x4, 0, 0, 1,   1,   1,   1,   0 )
-#define MPP5_SATA0_ACTn         MPP(  5, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP5_SATA0_ACTn         MPP(  5, 0x5, 0, 0, 0,   1,   1,   1,   1 )
 #define MPP5_LCD_VGA_VSYNC      MPP(  5, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP6_SYSRST_OUTn        MPP(  6, 0x1, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP6_SYSRST_OUTn        MPP(  6, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP6_SPI_MOSI           MPP(  6, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP6_SPI_MOSI           MPP(  6, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP6_PTP_TRIG_GEN       MPP(  6, 0x3, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP6_PTP_TRIG_GEN       MPP(  6, 0x3, 0, 0, 1,   1,   1,   1,   0 )
 #define MPP7_GPO                MPP(  7, 0x0, 0, 1, 1,   1,   1,   1,   1 )
-#define MPP7_PEX_RST_OUTn       MPP(  7, 0x1, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP7_PEX_RST_OUTn       MPP(  7, 0x1, 0, 0, 1,   1,   1,   1,   0 )
-#define MPP7_SPI_SCn            MPP(  7, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP7_SPI_SCn            MPP(  7, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP7_PTP_TRIG_GEN       MPP(  7, 0x3, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP7_PTP_TRIG_GEN       MPP(  7, 0x3, 0, 0, 1,   1,   1,   1,   0 )
-#define MPP7_LCD_PWM            MPP(  7, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP7_LCD_PWM            MPP(  7, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP8_GPIO               MPP(  8, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP8_TW0_SDA            MPP(  8, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP8_TW0_SDA            MPP(  8, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP8_UART0_RTS          MPP(  8, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP8_UART0_RTS          MPP(  8, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP8_UART1_RTS          MPP(  8, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP8_UART1_RTS          MPP(  8, 0x3, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP8_MII0_RXERR         MPP(  8, 0x4, 1, 0, 0,   1,   1,   1,   1 )
+#define MPP8_MII0_RXERR         MPP(  8, 0x4, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP8_SATA1_PRESENTn     MPP(  8, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP8_SATA1_PRESENTn     MPP(  8, 0x5, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP8_PTP_CLK            MPP(  8, 0xc, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP8_PTP_CLK            MPP(  8, 0xc, 0, 0, 1,   1,   1,   1,   0 )
-#define MPP8_MII0_COL           MPP(  8, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP8_MII0_COL           MPP(  8, 0xd, 0, 0, 1,   1,   1,   1,   1 )
 #define MPP9_GPIO               MPP(  9, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP9_TW0_SCK            MPP(  9, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP9_TW0_SCK            MPP(  9, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP9_UART0_CTS          MPP(  9, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP9_UART0_CTS          MPP(  9, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP9_UART1_CTS          MPP(  9, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP9_UART1_CTS          MPP(  9, 0x3, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP9_SATA0_PRESENTn     MPP(  9, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP9_SATA0_PRESENTn     MPP(  9, 0x5, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP9_PTP_EVENT_REQ      MPP(  9, 0xc, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP9_PTP_EVENT_REQ      MPP(  9, 0xc, 0, 0, 1,   1,   1,   1,   0 )
-#define MPP9_MII0_CRS           MPP(  9, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP9_MII0_CRS           MPP(  9, 0xd, 0, 0, 1,   1,   1,   1,   1 )
 #define MPP10_GPO               MPP( 10, 0x0, 0, 1, 1,   1,   1,   1,   1 )
-#define MPP10_SPI_SCK           MPP( 10, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP10_SPI_SCK           MPP( 10, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP10_UART0_TXD         MPP( 10, 0X3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP10_UART0_TXD         MPP( 10, 0X3, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP10_SATA1_ACTn        MPP( 10, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP10_SATA1_ACTn        MPP( 10, 0x5, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP10_PTP_TRIG_GEN      MPP( 10, 0xc, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP10_PTP_TRIG_GEN      MPP( 10, 0xc, 0, 0, 1,   1,   1,   1,   0 )
 #define MPP11_GPIO              MPP( 11, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP11_SPI_MISO          MPP( 11, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP11_SPI_MISO          MPP( 11, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP11_UART0_RXD         MPP( 11, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP11_UART0_RXD         MPP( 11, 0x3, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP11_PTP_EVENT_REQ     MPP( 11, 0x4, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP11_PTP_EVENT_REQ     MPP( 11, 0x4, 0, 0, 1,   1,   1,   1,   0 )
-#define MPP11_PTP_TRIG_GEN      MPP( 11, 0xc, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP11_PTP_TRIG_GEN      MPP( 11, 0xc, 0, 0, 1,   1,   1,   1,   0 )
-#define MPP11_PTP_CLK           MPP( 11, 0xd, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP11_PTP_CLK           MPP( 11, 0xd, 0, 0, 1,   1,   1,   1,   0 )
-#define MPP11_SATA0_ACTn        MPP( 11, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP11_SATA0_ACTn        MPP( 11, 0x5, 0, 0, 0,   1,   1,   1,   1 )
 #define MPP12_GPO               MPP( 12, 0x0, 0, 1, 1,   1,   1,   1,   1 )
 #define MPP12_GPIO              MPP( 12, 0x0, 1, 1, 0,   0,   0,   1,   0 )
-#define MPP12_SD_CLK            MPP( 12, 0x1, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP12_SD_CLK            MPP( 12, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP12_AU_SPDIF0         MPP( 12, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP12_AU_SPDIF0         MPP( 12, 0xa, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP12_SPI_MOSI          MPP( 12, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP12_SPI_MOSI          MPP( 12, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP12_TW1_SDA           MPP( 12, 0xd, 1, 0, 0,   0,   0,   0,   1 )
+#define MPP12_TW1_SDA           MPP( 12, 0xd, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP13_GPIO              MPP( 13, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP13_SD_CMD            MPP( 13, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP13_SD_CMD            MPP( 13, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP13_UART1_TXD         MPP( 13, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP13_UART1_TXD         MPP( 13, 0x3, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP13_AU_SPDIFRMCLK     MPP( 13, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP13_AU_SPDIFRMCLK     MPP( 13, 0xa, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP13_LCDPWM            MPP( 13, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP13_LCDPWM            MPP( 13, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP14_GPIO              MPP( 14, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP14_SD_D0             MPP( 14, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP14_SD_D0             MPP( 14, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP14_UART1_RXD         MPP( 14, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP14_UART1_RXD         MPP( 14, 0x3, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP14_SATA1_PRESENTn    MPP( 14, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP14_SATA1_PRESENTn    MPP( 14, 0x4, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP14_AU_SPDIFI         MPP( 14, 0xa, 1, 0, 0,   0,   0,   0,   1 )
+#define MPP14_AU_SPDIFI         MPP( 14, 0xa, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP14_AU_I2SDI          MPP( 14, 0xb, 1, 0, 0,   0,   0,   0,   1 )
+#define MPP14_AU_I2SDI          MPP( 14, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP14_MII0_COL          MPP( 14, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP14_MII0_COL          MPP( 14, 0xd, 0, 0, 1,   1,   1,   1,   1 )
 #define MPP15_GPIO              MPP( 15, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP15_SD_D1             MPP( 15, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP15_SD_D1             MPP( 15, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP15_UART0_RTS         MPP( 15, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP15_UART0_RTS         MPP( 15, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP15_UART1_TXD         MPP( 15, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP15_UART1_TXD         MPP( 15, 0x3, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP15_SATA0_ACTn        MPP( 15, 0x4, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP15_SATA0_ACTn        MPP( 15, 0x4, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP15_SPI_CSn           MPP( 15, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP15_SPI_CSn           MPP( 15, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP16_GPIO              MPP( 16, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP16_SD_D2             MPP( 16, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP16_SD_D2             MPP( 16, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP16_UART0_CTS         MPP( 16, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP16_UART0_CTS         MPP( 16, 0x2, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP16_UART1_RXD         MPP( 16, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP16_UART1_RXD         MPP( 16, 0x3, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP16_SATA1_ACTn        MPP( 16, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP16_SATA1_ACTn        MPP( 16, 0x4, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP16_LCD_EXT_REF_CLK   MPP( 16, 0xb, 1, 0, 0,   0,   0,   0,   1 )
+#define MPP16_LCD_EXT_REF_CLK   MPP( 16, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP16_MII0_CRS          MPP( 16, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP16_MII0_CRS          MPP( 16, 0xd, 0, 0, 1,   1,   1,   1,   1 )
 #define MPP17_GPIO              MPP( 17, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP17_SD_D3             MPP( 17, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP17_SD_D3             MPP( 17, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP17_SATA0_PRESENTn    MPP( 17, 0x4, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP17_SATA0_PRESENTn    MPP( 17, 0x4, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP17_SATA1_ACTn        MPP( 17, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP17_SATA1_ACTn        MPP( 17, 0xa, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP17_TW1_SCK           MPP( 17, 0xd, 1, 1, 0,   0,   0,   0,   1 )
+#define MPP17_TW1_SCK           MPP( 17, 0xd, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP18_GPO               MPP( 18, 0x0, 0, 1, 1,   1,   1,   1,   1 )
-#define MPP18_NF_IO0            MPP( 18, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP18_NF_IO0            MPP( 18, 0x1, 0, 0, 1,   1,   1,   1,   1 )
-#define MPP18_PEX0_CLKREQ       MPP( 18, 0x2, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP18_PEX0_CLKREQ       MPP( 18, 0x2, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP19_GPO               MPP( 19, 0x0, 0, 1, 1,   1,   1,   1,   1 )
-#define MPP19_NF_IO1            MPP( 19, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP19_NF_IO1            MPP( 19, 0x1, 0, 0, 1,   1,   1,   1,   1 )
 #define MPP20_GPIO              MPP( 20, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP20_TSMP0             MPP( 20, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP20_TSMP0             MPP( 20, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP20_TDM_CH0_TX_QL     MPP( 20, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP20_TDM_CH0_TX_QL     MPP( 20, 0x2, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP20_GE1_TXD0          MPP( 20, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP20_AU_SPDIFI         MPP( 20, 0x4, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP20_AU_SPDIFI         MPP( 20, 0x4, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP20_SATA1_ACTn        MPP( 20, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP20_SATA1_ACTn        MPP( 20, 0x5, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP20_LCD_D0            MPP( 20, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP21_GPIO              MPP( 21, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP21_TSMP1             MPP( 21, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP21_TSMP1             MPP( 21, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP21_TDM_CH0_RX_QL     MPP( 21, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP21_TDM_CH0_RX_QL     MPP( 21, 0x2, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP21_GE1_TXD1          MPP( 21, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP21_AU_SPDIFO         MPP( 21, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP21_AU_SPDIFO         MPP( 21, 0x4, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP21_SATA0_ACTn        MPP( 21, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP21_SATA0_ACTn        MPP( 21, 0x5, 0, 0, 0,   1,   1,   1,   1 )
 #define MPP21_LCD_D1            MPP( 21, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP22_GPIO              MPP( 22, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP22_TSMP2             MPP( 22, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP22_TSMP2             MPP( 22, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP22_TDM_CH2_TX_QL     MPP( 22, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP22_TDM_CH2_TX_QL     MPP( 22, 0x2, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP22_GE1_TXD2          MPP( 22, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP22_AU_SPDIFRMKCLK    MPP( 22, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP22_AU_SPDIFRMKCLK    MPP( 22, 0x4, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP22_SATA1_PRESENTn    MPP( 22, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP22_SATA1_PRESENTn    MPP( 22, 0x5, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP22_LCD_D2            MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP23_GPIO              MPP( 23, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP23_TSMP3             MPP( 23, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP23_TSMP3             MPP( 23, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP23_TDM_CH2_RX_QL     MPP( 23, 0x2, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP23_TDM_CH2_RX_QL     MPP( 23, 0x2, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP23_GE1_TXD3          MPP( 23, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP23_AU_I2SBCLK        MPP( 23, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP23_AU_I2SBCLK        MPP( 23, 0x4, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP23_SATA0_PRESENTn    MPP( 23, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP23_SATA0_PRESENTn    MPP( 23, 0x5, 0, 0, 0,   1,   1,   1,   1 )
 #define MPP23_LCD_D3            MPP( 23, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP24_GPIO              MPP( 24, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP24_TSMP4             MPP( 24, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP24_TSMP4             MPP( 24, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP24_TDM_SPI_CS0       MPP( 24, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP24_TDM_SPI_CS0       MPP( 24, 0x2, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP24_GE1_RXD0          MPP( 24, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP24_AU_I2SDO          MPP( 24, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP24_AU_I2SDO          MPP( 24, 0x4, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP24_LCD_D4            MPP( 24, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP25_GPIO              MPP( 25, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP25_TSMP5             MPP( 25, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP25_TSMP5             MPP( 25, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP25_TDM_SPI_SCK       MPP( 25, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP25_TDM_SPI_SCK       MPP( 25, 0x2, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP25_GE1_RXD1          MPP( 25, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP25_AU_I2SLRCLK       MPP( 25, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP25_AU_I2SLRCLK       MPP( 25, 0x4, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP25_LCD_D5            MPP( 25, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP26_GPIO              MPP( 26, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP26_TSMP6             MPP( 26, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP26_TSMP6             MPP( 26, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP26_TDM_SPI_MISO      MPP( 26, 0x2, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP26_TDM_SPI_MISO      MPP( 26, 0x2, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP26_GE1_RXD2          MPP( 26, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP26_AU_I2SMCLK        MPP( 26, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP26_AU_I2SMCLK        MPP( 26, 0x4, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP26_LCD_D6            MPP( 26, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP27_GPIO              MPP( 27, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP27_TSMP7             MPP( 27, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP27_TSMP7             MPP( 27, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP27_TDM_SPI_MOSI      MPP( 27, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP27_TDM_SPI_MOSI      MPP( 27, 0x2, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP27_GE1_RXD3          MPP( 27, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP27_AU_I2SDI          MPP( 27, 0x4, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP27_AU_I2SDI          MPP( 27, 0x4, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP27_LCD_D7            MPP( 27, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP28_GPIO              MPP( 28, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP28_TSMP8             MPP( 28, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP28_TSMP8             MPP( 28, 0x1, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP28_TDM_CODEC_INTn    MPP( 28, 0x2, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP28_GE1_COL           MPP( 28, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP28_AU_EXTCLK         MPP( 28, 0x4, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP28_AU_EXTCLK         MPP( 28, 0x4, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP28_LCD_D8            MPP( 28, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP29_GPIO              MPP( 29, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP29_TSMP9             MPP( 29, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP29_TSMP9             MPP( 29, 0x1, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP29_TDM_CODEC_RSTn    MPP( 29, 0x2, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP29_GE1_TCLK          MPP( 29, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 #define MPP29_LCD_D9            MPP( 29, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP30_GPIO              MPP( 30, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP30_TSMP10            MPP( 30, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP30_TSMP10            MPP( 30, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP30_TDM_PCLK          MPP( 30, 0x2, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP30_TDM_PCLK          MPP( 30, 0x2, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP30_GE1_RXCTL         MPP( 30, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 #define MPP30_LCD_D10           MPP( 30, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP31_GPIO              MPP( 31, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP31_TSMP11            MPP( 31, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP31_TSMP11            MPP( 31, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP31_TDM_FS            MPP( 31, 0x2, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP31_TDM_FS            MPP( 31, 0x2, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP31_GE1_RXCLK         MPP( 31, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 #define MPP31_LCD_D11           MPP( 31, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP32_GPIO              MPP( 32, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP32_TSMP12            MPP( 32, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP32_TSMP12            MPP( 32, 0x1, 0, 0, 0,   0,   1,   1,   1 )
-#define MPP32_TDM_DRX           MPP( 32, 0x2, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP32_TDM_DRX           MPP( 32, 0x2, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP32_GE1_TCLKOUT       MPP( 32, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 #define MPP32_LCD_D12           MPP( 32, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP33_GPO               MPP( 33, 0x0, 0, 1, 0,   1,   1,   1,   1 )
-#define MPP33_TDM_DTX           MPP( 33, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP33_TDM_DTX           MPP( 33, 0x2, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP33_GE1_TXCTL         MPP( 33, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 #define MPP33_LCD_D13           MPP( 33, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP34_GPIO              MPP( 34, 0x0, 1, 1, 0,   1,   1,   1,   1 )
-#define MPP34_TDM_SPI_CS1       MPP( 34, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP34_TDM_SPI_CS1       MPP( 34, 0x2, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP34_GE1_TXEN          MPP( 34, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP34_SATA1_ACTn        MPP( 34, 0x5, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP34_SATA1_ACTn        MPP( 34, 0x5, 0, 0, 0,   0,   0,   1,   1 )
 #define MPP34_LCD_D14           MPP( 34, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP35_GPIO              MPP( 35, 0x0, 1, 1, 1,   1,   1,   1,   1 )
-#define MPP35_TDM_CH0_TX_QL     MPP( 35, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP35_TDM_CH0_TX_QL     MPP( 35, 0x2, 0, 0, 0,   0,   1,   1,   1 )
 #define MPP35_GE1_RXERR         MPP( 35, 0x3, 0, 0, 0,   1,   1,   1,   1 )
-#define MPP35_SATA0_ACTn        MPP( 35, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP35_SATA0_ACTn        MPP( 35, 0x5, 0, 0, 0,   1,   1,   1,   1 )
 #define MPP35_LCD_D15           MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
-#define MPP35_MII0_RXERR        MPP( 35, 0xc, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP35_MII0_RXERR        MPP( 35, 0xc, 0, 0, 1,   1,   1,   1,   1 )
 #define MPP36_GPIO              MPP( 36, 0x0, 1, 1, 1,   0,   0,   1,   1 )
-#define MPP36_TSMP0             MPP( 36, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP36_TSMP0             MPP( 36, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP36_TDM_SPI_CS1       MPP( 36, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP36_TDM_SPI_CS1       MPP( 36, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP36_AU_SPDIFI         MPP( 36, 0x4, 1, 0, 1,   0,   0,   1,   1 )
+#define MPP36_AU_SPDIFI         MPP( 36, 0x4, 0, 0, 1,   0,   0,   1,   1 )
-#define MPP36_TW1_SDA           MPP( 36, 0xb, 1, 1, 0,   0,   0,   0,   1 )
+#define MPP36_TW1_SDA           MPP( 36, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP37_GPIO              MPP( 37, 0x0, 1, 1, 1,   0,   0,   1,   1 )
-#define MPP37_TSMP1             MPP( 37, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP37_TSMP1             MPP( 37, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP37_TDM_CH2_TX_QL     MPP( 37, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP37_TDM_CH2_TX_QL     MPP( 37, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP37_AU_SPDIFO         MPP( 37, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP37_AU_SPDIFO         MPP( 37, 0x4, 0, 0, 1,   0,   0,   1,   1 )
-#define MPP37_TW1_SCK           MPP( 37, 0xb, 1, 1, 0,   0,   0,   0,   1 )
+#define MPP37_TW1_SCK           MPP( 37, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP38_GPIO              MPP( 38, 0x0, 1, 1, 1,   0,   0,   1,   1 )
-#define MPP38_TSMP2             MPP( 38, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP38_TSMP2             MPP( 38, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP38_TDM_CH2_RX_QL     MPP( 38, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP38_TDM_CH2_RX_QL     MPP( 38, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP38_AU_SPDIFRMLCLK    MPP( 38, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP38_AU_SPDIFRMLCLK    MPP( 38, 0x4, 0, 0, 1,   0,   0,   1,   1 )
 #define MPP38_LCD_D18           MPP( 38, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP39_GPIO              MPP( 39, 0x0, 1, 1, 1,   0,   0,   1,   1 )
-#define MPP39_TSMP3             MPP( 39, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP39_TSMP3             MPP( 39, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP39_TDM_SPI_CS0       MPP( 39, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP39_TDM_SPI_CS0       MPP( 39, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP39_AU_I2SBCLK        MPP( 39, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP39_AU_I2SBCLK        MPP( 39, 0x4, 0, 0, 1,   0,   0,   1,   1 )
 #define MPP39_LCD_D19           MPP( 39, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP40_GPIO              MPP( 40, 0x0, 1, 1, 1,   0,   0,   1,   1 )
-#define MPP40_TSMP4             MPP( 40, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP40_TSMP4             MPP( 40, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP40_TDM_SPI_SCK       MPP( 40, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP40_TDM_SPI_SCK       MPP( 40, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP40_AU_I2SDO          MPP( 40, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP40_AU_I2SDO          MPP( 40, 0x4, 0, 0, 1,   0,   0,   1,   1 )
 #define MPP40_LCD_D20           MPP( 40, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP41_GPIO              MPP( 41, 0x0, 1, 1, 1,   0,   0,   1,   1 )
-#define MPP41_TSMP5             MPP( 41, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP41_TSMP5             MPP( 41, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP41_TDM_SPI_MISO      MPP( 41, 0x2, 1, 0, 0,   0,   0,   1,   1 )
+#define MPP41_TDM_SPI_MISO      MPP( 41, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP41_AU_I2SLRCLK       MPP( 41, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP41_AU_I2SLRCLK       MPP( 41, 0x4, 0, 0, 1,   0,   0,   1,   1 )
 #define MPP41_LCD_D21           MPP( 41, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP42_GPIO              MPP( 42, 0x0, 1, 1, 1,   0,   0,   1,   1 )
-#define MPP42_TSMP6             MPP( 42, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP42_TSMP6             MPP( 42, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP42_TDM_SPI_MOSI      MPP( 42, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP42_TDM_SPI_MOSI      MPP( 42, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP42_AU_I2SMCLK        MPP( 42, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP42_AU_I2SMCLK        MPP( 42, 0x4, 0, 0, 1,   0,   0,   1,   1 )
 #define MPP42_LCD_D22           MPP( 42, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP43_GPIO              MPP( 43, 0x0, 1, 1, 1,   0,   0,   1,   1 )
-#define MPP43_TSMP7             MPP( 43, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP43_TSMP7             MPP( 43, 0x1, 0, 0, 0,   0,   0,   1,   1 )
 #define MPP43_TDM_CODEC_INTn    MPP( 43, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP43_AU_I2SDI          MPP( 43, 0x4, 1, 0, 1,   0,   0,   1,   1 )
+#define MPP43_AU_I2SDI          MPP( 43, 0x4, 0, 0, 1,   0,   0,   1,   1 )
 #define MPP43_LCD_D23           MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP44_GPIO              MPP( 44, 0x0, 1, 1, 1,   0,   0,   1,   1 )
-#define MPP44_TSMP8             MPP( 44, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP44_TSMP8             MPP( 44, 0x1, 0, 0, 0,   0,   0,   1,   1 )
 #define MPP44_TDM_CODEC_RSTn    MPP( 44, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP44_AU_EXTCLK         MPP( 44, 0x4, 1, 0, 1,   0,   0,   1,   1 )
+#define MPP44_AU_EXTCLK         MPP( 44, 0x4, 0, 0, 1,   0,   0,   1,   1 )
 #define MPP44_LCD_CLK           MPP( 44, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP45_GPIO              MPP( 45, 0x0, 1, 1, 0,   0,   0,   1,   1 )
-#define MPP45_TSMP9             MPP( 45, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP45_TSMP9             MPP( 45, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP45_TDM_PCLK          MPP( 45, 0x2, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP45_TDM_PCLK          MPP( 45, 0x2, 0, 0, 0,   0,   0,   1,   1 )
 #define MPP245_LCD_E            MPP( 45, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP46_GPIO              MPP( 46, 0x0, 1, 1, 0,   0,   0,   1,   1 )
-#define MPP46_TSMP10            MPP( 46, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP46_TSMP10            MPP( 46, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP46_TDM_FS            MPP( 46, 0x2, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP46_TDM_FS            MPP( 46, 0x2, 0, 0, 0,   0,   0,   1,   1 )
 #define MPP46_LCD_HSYNC         MPP( 46, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP47_GPIO              MPP( 47, 0x0, 1, 1, 0,   0,   0,   1,   1 )
-#define MPP47_TSMP11            MPP( 47, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP47_TSMP11            MPP( 47, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP47_TDM_DRX           MPP( 47, 0x2, 1, 0, 0,   0,   0,   1,   1 )
+#define MPP47_TDM_DRX           MPP( 47, 0x2, 0, 0, 0,   0,   0,   1,   1 )
 #define MPP47_LCD_VSYNC         MPP( 47, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP48_GPIO              MPP( 48, 0x0, 1, 1, 0,   0,   0,   1,   1 )
-#define MPP48_TSMP12            MPP( 48, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP48_TSMP12            MPP( 48, 0x1, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP48_TDM_DTX           MPP( 48, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP48_TDM_DTX           MPP( 48, 0x2, 0, 0, 0,   0,   0,   1,   1 )
 #define MPP48_LCD_D16           MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP49_GPIO              MPP( 49, 0x0, 1, 1, 0,   0,   0,   1,   0 )
 #define MPP49_GPO               MPP( 49, 0x0, 0, 1, 0,   0,   0,   0,   1 )
-#define MPP49_TSMP9             MPP( 49, 0x1, 1, 1, 0,   0,   0,   1,   0 )
+#define MPP49_TSMP9             MPP( 49, 0x1, 0, 0, 0,   0,   0,   1,   0 )
-#define MPP49_TDM_CH0_RX_QL     MPP( 49, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP49_TDM_CH0_RX_QL     MPP( 49, 0x2, 0, 0, 0,   0,   0,   1,   1 )
-#define MPP49_PTP_CLK           MPP( 49, 0x5, 1, 0, 0,   0,   0,   1,   0 )
+#define MPP49_PTP_CLK           MPP( 49, 0x5, 0, 0, 0,   0,   0,   1,   0 )
-#define MPP49_PEX0_CLKREQ       MPP( 49, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP49_PEX0_CLKREQ       MPP( 49, 0xa, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP49_LCD_D17           MPP( 49, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 #define MPP_MAX                 49
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 0cdd41004ad0..a5dcf766a3f9 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -19,6 +19,7 @@
 #include <mach/mv78xx0.h>
 #include <mach/bridge-regs.h>
 #include <plat/cache-feroceon-l2.h>
+#include <plat/ehci-orion.h>
 #include <plat/orion_nand.h>
 #include <plat/time.h>
 #include <plat/common.h>
@@ -169,7 +170,7 @@ void __init mv78xx0_map_io(void)
 ****************************************************************************/
 void __init mv78xx0_ehci0_init(void)
 {
-        orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
+        orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
 }
diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h
index b61b50927123..3752302ae2ee 100644
--- a/arch/arm/mach-mv78xx0/mpp.h
+++ b/arch/arm/mach-mv78xx0/mpp.h
@@ -24,296 +24,296 @@
 #define MPP_78100_A0_MASK    MPP(0, 0x0, 0, 0, 1)
 #define MPP0_GPIO        MPP(0, 0x0, 1, 1, 1)
-#define MPP0_GE0_COL        MPP(0, 0x1, 1, 0, 1)
+#define MPP0_GE0_COL        MPP(0, 0x1, 0, 0, 1)
-#define MPP0_GE1_TXCLK        MPP(0, 0x2, 0, 1, 1)
+#define MPP0_GE1_TXCLK        MPP(0, 0x2, 0, 0, 1)
 #define MPP0_UNUSED        MPP(0, 0x3, 0, 0, 1)
 #define MPP1_GPIO        MPP(1, 0x0, 1, 1, 1)
-#define MPP1_GE0_RXERR        MPP(1, 0x1, 1, 0, 1)
+#define MPP1_GE0_RXERR        MPP(1, 0x1, 0, 0, 1)
-#define MPP1_GE1_TXCTL        MPP(1, 0x2, 0, 1, 1)
+#define MPP1_GE1_TXCTL        MPP(1, 0x2, 0, 0, 1)
 #define MPP1_UNUSED        MPP(1, 0x3, 0, 0, 1)
 #define MPP2_GPIO        MPP(2, 0x0, 1, 1, 1)
-#define MPP2_GE0_CRS        MPP(2, 0x1, 1, 0, 1)
+#define MPP2_GE0_CRS        MPP(2, 0x1, 0, 0, 1)
-#define MPP2_GE1_RXCTL        MPP(2, 0x2, 1, 0, 1)
+#define MPP2_GE1_RXCTL        MPP(2, 0x2, 0, 0, 1)
 #define MPP2_UNUSED        MPP(2, 0x3, 0, 0, 1)
 #define MPP3_GPIO        MPP(3, 0x0, 1, 1, 1)
-#define MPP3_GE0_TXERR        MPP(3, 0x1, 0, 1, 1)
+#define MPP3_GE0_TXERR        MPP(3, 0x1, 0, 0, 1)
-#define MPP3_GE1_RXCLK        MPP(3, 0x2, 1, 0, 1)
+#define MPP3_GE1_RXCLK        MPP(3, 0x2, 0, 0, 1)
 #define MPP3_UNUSED        MPP(3, 0x3, 0, 0, 1)
 #define MPP4_GPIO        MPP(4, 0x0, 1, 1, 1)
-#define MPP4_GE0_TXD4        MPP(4, 0x1, 0, 1, 1)
+#define MPP4_GE0_TXD4        MPP(4, 0x1, 0, 0, 1)
-#define MPP4_GE1_TXD0        MPP(4, 0x2, 0, 1, 1)
+#define MPP4_GE1_TXD0        MPP(4, 0x2, 0, 0, 1)
 #define MPP4_UNUSED        MPP(4, 0x3, 0, 0, 1)
 #define MPP5_GPIO        MPP(5, 0x0, 1, 1, 1)
-#define MPP5_GE0_TXD5        MPP(5, 0x1, 0, 1, 1)
+#define MPP5_GE0_TXD5        MPP(5, 0x1, 0, 0, 1)
-#define MPP5_GE1_TXD1        MPP(5, 0x2, 0, 1, 1)
+#define MPP5_GE1_TXD1        MPP(5, 0x2, 0, 0, 1)
 #define MPP5_UNUSED        MPP(5, 0x3, 0, 0, 1)
 #define MPP6_GPIO        MPP(6, 0x0, 1, 1, 1)
-#define MPP6_GE0_TXD6        MPP(6, 0x1, 0, 1, 1)
+#define MPP6_GE0_TXD6        MPP(6, 0x1, 0, 0, 1)
-#define MPP6_GE1_TXD2        MPP(6, 0x2, 0, 1, 1)
+#define MPP6_GE1_TXD2        MPP(6, 0x2, 0, 0, 1)
 #define MPP6_UNUSED        MPP(6, 0x3, 0, 0, 1)
 #define MPP7_GPIO        MPP(7, 0x0, 1, 1, 1)
-#define MPP7_GE0_TXD7        MPP(7, 0x1, 0, 1, 1)
+#define MPP7_GE0_TXD7        MPP(7, 0x1, 0, 0, 1)
-#define MPP7_GE1_TXD3        MPP(7, 0x2, 0, 1, 1)
+#define MPP7_GE1_TXD3        MPP(7, 0x2, 0, 0, 1)
 #define MPP7_UNUSED        MPP(7, 0x3, 0, 0, 1)
 #define MPP8_GPIO        MPP(8, 0x0, 1, 1, 1)
-#define MPP8_GE0_RXD4        MPP(8, 0x1, 1, 0, 1)
+#define MPP8_GE0_RXD4        MPP(8, 0x1, 0, 0, 1)
-#define MPP8_GE1_RXD0        MPP(8, 0x2, 1, 0, 1)
+#define MPP8_GE1_RXD0        MPP(8, 0x2, 0, 0, 1)
 #define MPP8_UNUSED        MPP(8, 0x3, 0, 0, 1)
 #define MPP9_GPIO        MPP(9, 0x0, 1, 1, 1)
-#define MPP9_GE0_RXD5        MPP(9, 0x1, 1, 0, 1)
+#define MPP9_GE0_RXD5        MPP(9, 0x1, 0, 0, 1)
-#define MPP9_GE1_RXD1        MPP(9, 0x2, 1, 0, 1)
+#define MPP9_GE1_RXD1        MPP(9, 0x2, 0, 0, 1)
 #define MPP9_UNUSED        MPP(9, 0x3, 0, 0, 1)
 #define MPP10_GPIO        MPP(10, 0x0, 1, 1, 1)
-#define MPP10_GE0_RXD6        MPP(10, 0x1, 1, 0, 1)
+#define MPP10_GE0_RXD6        MPP(10, 0x1, 0, 0, 1)
-#define MPP10_GE1_RXD2        MPP(10, 0x2, 1, 0, 1)
+#define MPP10_GE1_RXD2        MPP(10, 0x2, 0, 0, 1)
 #define MPP10_UNUSED        MPP(10, 0x3, 0, 0, 1)
 #define MPP11_GPIO        MPP(11, 0x0, 1, 1, 1)
-#define MPP11_GE0_RXD7        MPP(11, 0x1, 1, 0, 1)
+#define MPP11_GE0_RXD7        MPP(11, 0x1, 0, 0, 1)
-#define MPP11_GE1_RXD3        MPP(11, 0x2, 1, 0, 1)
+#define MPP11_GE1_RXD3        MPP(11, 0x2, 0, 0, 1)
 #define MPP11_UNUSED        MPP(11, 0x3, 0, 0, 1)
 #define MPP12_GPIO        MPP(12, 0x0, 1, 1, 1)
-#define MPP12_M_BB        MPP(12, 0x3, 1, 0, 1)
+#define MPP12_M_BB        MPP(12, 0x3, 0, 0, 1)
-#define MPP12_UA0_CTSn        MPP(12, 0x4, 1, 0, 1)
+#define MPP12_UA0_CTSn        MPP(12, 0x4, 0, 0, 1)
-#define MPP12_NAND_FLASH_REn0    MPP(12, 0x5, 0, 1, 1)
+#define MPP12_NAND_FLASH_REn0    MPP(12, 0x5, 0, 0, 1)
-#define MPP12_TDM0_SCSn        MPP(12, 0X6, 0, 1, 1)
+#define MPP12_TDM0_SCSn        MPP(12, 0X6, 0, 0, 1)
 #define MPP12_UNUSED        MPP(12, 0x1, 0, 0, 1)
 #define MPP13_GPIO        MPP(13, 0x0, 1, 1, 1)
-#define MPP13_SYSRST_OUTn    MPP(13, 0x3, 0, 1, 1)
+#define MPP13_SYSRST_OUTn    MPP(13, 0x3, 0, 0, 1)
-#define MPP13_UA0_RTSn        MPP(13, 0x4, 0, 1, 1)
+#define MPP13_UA0_RTSn        MPP(13, 0x4, 0, 0, 1)
-#define MPP13_NAN_FLASH_WEn0    MPP(13, 0x5, 0, 1, 1)
+#define MPP13_NAN_FLASH_WEn0    MPP(13, 0x5, 0, 0, 1)
-#define MPP13_TDM_SCLK        MPP(13, 0x6, 0, 1, 1)
+#define MPP13_TDM_SCLK        MPP(13, 0x6, 0, 0, 1)
 #define MPP13_UNUSED        MPP(13, 0x1, 0, 0, 1)
 #define MPP14_GPIO        MPP(14, 0x0, 1, 1, 1)
-#define MPP14_SATA1_ACTn    MPP(14, 0x3, 0, 1, 1)
+#define MPP14_SATA1_ACTn    MPP(14, 0x3, 0, 0, 1)
-#define MPP14_UA1_CTSn        MPP(14, 0x4, 1, 0, 1)
+#define MPP14_UA1_CTSn        MPP(14, 0x4, 0, 0, 1)
-#define MPP14_NAND_FLASH_REn1    MPP(14, 0x5, 0, 1, 1)
+#define MPP14_NAND_FLASH_REn1    MPP(14, 0x5, 0, 0, 1)
-#define MPP14_TDM_SMOSI        MPP(14, 0x6, 0, 1, 1)
+#define MPP14_TDM_SMOSI        MPP(14, 0x6, 0, 0, 1)
 #define MPP14_UNUSED        MPP(14, 0x1, 0, 0, 1)
 #define MPP15_GPIO        MPP(15, 0x0, 1, 1, 1)
-#define MPP15_SATA0_ACTn    MPP(15, 0x3, 0, 1, 1)
+#define MPP15_SATA0_ACTn    MPP(15, 0x3, 0, 0, 1)
-#define MPP15_UA1_RTSn        MPP(15, 0x4, 0, 1, 1)
+#define MPP15_UA1_RTSn        MPP(15, 0x4, 0, 0, 1)
-#define MPP15_NAND_FLASH_WEn1    MPP(15, 0x5, 0, 1, 1)
+#define MPP15_NAND_FLASH_WEn1    MPP(15, 0x5, 0, 0, 1)
-#define MPP15_TDM_SMISO        MPP(15, 0x6, 1, 0, 1)
+#define MPP15_TDM_SMISO        MPP(15, 0x6, 0, 0, 1)
 #define MPP15_UNUSED        MPP(15, 0x1, 0, 0, 1)
 #define MPP16_GPIO        MPP(16, 0x0, 1, 1, 1)
-#define MPP16_SATA1_PRESENTn    MPP(16, 0x3, 0, 1, 1)
+#define MPP16_SATA1_PRESENTn    MPP(16, 0x3, 0, 0, 1)
-#define MPP16_UA2_TXD        MPP(16, 0x4, 0, 1, 1)
+#define MPP16_UA2_TXD        MPP(16, 0x4, 0, 0, 1)
-#define MPP16_NAND_FLASH_REn3    MPP(16, 0x5, 0, 1, 1)
+#define MPP16_NAND_FLASH_REn3    MPP(16, 0x5, 0, 0, 1)
-#define MPP16_TDM_INTn        MPP(16, 0x6, 1, 0, 1)
+#define MPP16_TDM_INTn        MPP(16, 0x6, 0, 0, 1)
 #define MPP16_UNUSED        MPP(16, 0x1, 0, 0, 1)
 #define MPP17_GPIO        MPP(17, 0x0, 1, 1, 1)
-#define MPP17_SATA0_PRESENTn    MPP(17, 0x3, 0, 1, 1)
+#define MPP17_SATA0_PRESENTn    MPP(17, 0x3, 0, 0, 1)
-#define MPP17_UA2_RXD        MPP(17, 0x4, 1, 0, 1)
+#define MPP17_UA2_RXD        MPP(17, 0x4, 0, 0, 1)
-#define MPP17_NAND_FLASH_WEn3    MPP(17, 0x5, 0, 1, 1)
+#define MPP17_NAND_FLASH_WEn3    MPP(17, 0x5, 0, 0, 1)
-#define MPP17_TDM_RSTn        MPP(17, 0x6, 0, 1, 1)
+#define MPP17_TDM_RSTn        MPP(17, 0x6, 0, 0, 1)
 #define MPP17_UNUSED        MPP(17, 0x1, 0, 0, 1)
 #define MPP18_GPIO        MPP(18, 0x0, 1, 1, 1)
-#define MPP18_UA0_CTSn        MPP(18, 0x4, 1, 0, 1)
+#define MPP18_UA0_CTSn        MPP(18, 0x4, 0, 0, 1)
-#define MPP18_BOOT_FLASH_REn    MPP(18, 0x5, 0, 1, 1)
+#define MPP18_BOOT_FLASH_REn    MPP(18, 0x5, 0, 0, 1)
 #define MPP18_UNUSED        MPP(18, 0x1, 0, 0, 1)
 #define MPP19_GPIO        MPP(19, 0x0, 1, 1, 1)
-#define MPP19_UA0_CTSn        MPP(19, 0x4, 0, 1, 1)
+#define MPP19_UA0_CTSn        MPP(19, 0x4, 0, 0, 1)
-#define MPP19_BOOT_FLASH_WEn    MPP(19, 0x5, 0, 1, 1)
+#define MPP19_BOOT_FLASH_WEn    MPP(19, 0x5, 0, 0, 1)
 #define MPP19_UNUSED        MPP(19, 0x1, 0, 0, 1)
 #define MPP20_GPIO        MPP(20, 0x0, 1, 1, 1)
-#define MPP20_UA1_CTSs        MPP(20, 0x4, 1, 0, 1)
+#define MPP20_UA1_CTSs        MPP(20, 0x4, 0, 0, 1)
-#define MPP20_TDM_PCLK        MPP(20, 0x6, 1, 1, 0)
+#define MPP20_TDM_PCLK        MPP(20, 0x6, 0, 0, 0)
 #define MPP20_UNUSED        MPP(20, 0x1, 0, 0, 1)
 #define MPP21_GPIO        MPP(21, 0x0, 1, 1, 1)
-#define MPP21_UA1_CTSs        MPP(21, 0x4, 0, 1, 1)
+#define MPP21_UA1_CTSs        MPP(21, 0x4, 0, 0, 1)
-#define MPP21_TDM_FSYNC        MPP(21, 0x6, 1, 1, 0)
+#define MPP21_TDM_FSYNC        MPP(21, 0x6, 0, 0, 0)
 #define MPP21_UNUSED        MPP(21, 0x1, 0, 0, 1)
 #define MPP22_GPIO        MPP(22, 0x0, 1, 1, 1)
-#define MPP22_UA3_TDX        MPP(22, 0x4, 0, 1, 1)
+#define MPP22_UA3_TDX        MPP(22, 0x4, 0, 0, 1)
-#define MPP22_NAND_FLASH_REn2    MPP(22, 0x5, 0, 1, 1)
+#define MPP22_NAND_FLASH_REn2    MPP(22, 0x5, 0, 0, 1)
-#define MPP22_TDM_DRX        MPP(22, 0x6, 1, 0, 1)
+#define MPP22_TDM_DRX        MPP(22, 0x6, 0, 0, 1)
 #define MPP22_UNUSED        MPP(22, 0x1, 0, 0, 1)
 #define MPP23_GPIO        MPP(23, 0x0, 1, 1, 1)
-#define MPP23_UA3_RDX        MPP(23, 0x4, 1, 0, 1)
+#define MPP23_UA3_RDX        MPP(23, 0x4, 0, 0, 1)
-#define MPP23_NAND_FLASH_WEn2    MPP(23, 0x5, 0, 1, 1)
+#define MPP23_NAND_FLASH_WEn2    MPP(23, 0x5, 0, 0, 1)
-#define MPP23_TDM_DTX        MPP(23, 0x6, 0, 1, 1)
+#define MPP23_TDM_DTX        MPP(23, 0x6, 0, 0, 1)
 #define MPP23_UNUSED        MPP(23, 0x1, 0, 0, 1)
 #define MPP24_GPIO        MPP(24, 0x0, 1, 1, 1)
-#define MPP24_UA2_TXD        MPP(24, 0x4, 0, 1, 1)
+#define MPP24_UA2_TXD        MPP(24, 0x4, 0, 0, 1)
-#define MPP24_TDM_INTn        MPP(24, 0x6, 1, 0, 1)
+#define MPP24_TDM_INTn        MPP(24, 0x6, 0, 0, 1)
 #define MPP24_UNUSED        MPP(24, 0x1, 0, 0, 1)
 #define MPP25_GPIO        MPP(25, 0x0, 1, 1, 1)
-#define MPP25_UA2_RXD        MPP(25, 0x4, 1, 0, 1)
+#define MPP25_UA2_RXD        MPP(25, 0x4, 0, 0, 1)
-#define MPP25_TDM_RSTn        MPP(25, 0x6, 0, 1, 1)
+#define MPP25_TDM_RSTn        MPP(25, 0x6, 0, 0, 1)
 #define MPP25_UNUSED        MPP(25, 0x1, 0, 0, 1)
 #define MPP26_GPIO        MPP(26, 0x0, 1, 1, 1)
-#define MPP26_UA2_CTSn        MPP(26, 0x4, 1, 0, 1)
+#define MPP26_UA2_CTSn        MPP(26, 0x4, 0, 0, 1)
-#define MPP26_TDM_PCLK        MPP(26, 0x6, 1, 1, 1)
+#define MPP26_TDM_PCLK        MPP(26, 0x6, 0, 0, 1)
 #define MPP26_UNUSED        MPP(26, 0x1, 0, 0, 1)
 #define MPP27_GPIO        MPP(27, 0x0, 1, 1, 1)
-#define MPP27_UA2_RTSn        MPP(27, 0x4, 0, 1, 1)
+#define MPP27_UA2_RTSn        MPP(27, 0x4, 0, 0, 1)
-#define MPP27_TDM_FSYNC        MPP(27, 0x6, 1, 1, 1)
+#define MPP27_TDM_FSYNC        MPP(27, 0x6, 0, 0, 1)
 #define MPP27_UNUSED        MPP(27, 0x1, 0, 0, 1)
 #define MPP28_GPIO        MPP(28, 0x0, 1, 1, 1)
-#define MPP28_UA3_TXD        MPP(28, 0x4, 0, 1, 1)
+#define MPP28_UA3_TXD        MPP(28, 0x4, 0, 0, 1)
-#define MPP28_TDM_DRX        MPP(28, 0x6, 1, 0, 1)
+#define MPP28_TDM_DRX        MPP(28, 0x6, 0, 0, 1)
 #define MPP28_UNUSED        MPP(28, 0x1, 0, 0, 1)
 #define MPP29_GPIO        MPP(29, 0x0, 1, 1, 1)
-#define MPP29_UA3_RXD        MPP(29, 0x4, 1, 0, 1)
+#define MPP29_UA3_RXD        MPP(29, 0x4, 0, 0, 1)
-#define MPP29_SYSRST_OUTn    MPP(29, 0x5, 0, 1, 1)
+#define MPP29_SYSRST_OUTn    MPP(29, 0x5, 0, 0, 1)
-#define MPP29_TDM_DTX        MPP(29, 0x6, 0, 1, 1)
+#define MPP29_TDM_DTX        MPP(29, 0x6, 0, 0, 1)
 #define MPP29_UNUSED        MPP(29, 0x1, 0, 0, 1)
 #define MPP30_GPIO        MPP(30, 0x0, 1, 1, 1)
-#define MPP30_UA3_CTSn        MPP(30, 0x4, 1, 0, 1)
+#define MPP30_UA3_CTSn        MPP(30, 0x4, 0, 0, 1)
 #define MPP30_UNUSED        MPP(30, 0x1, 0, 0, 1)
 #define MPP31_GPIO        MPP(31, 0x0, 1, 1, 1)
-#define MPP31_UA3_RTSn        MPP(31, 0x4, 0, 1, 1)
+#define MPP31_UA3_RTSn        MPP(31, 0x4, 0, 0, 1)
-#define MPP31_TDM1_SCSn        MPP(31, 0x6, 0, 1, 1)
+#define MPP31_TDM1_SCSn        MPP(31, 0x6, 0, 0, 1)
 #define MPP31_UNUSED        MPP(31, 0x1, 0, 0, 1)
 #define MPP32_GPIO        MPP(32, 0x1, 1, 1, 1)
-#define MPP32_UA3_TDX        MPP(32, 0x4, 0, 1, 1)
+#define MPP32_UA3_TDX        MPP(32, 0x4, 0, 0, 1)
-#define MPP32_SYSRST_OUTn    MPP(32, 0x5, 0, 1, 1)
+#define MPP32_SYSRST_OUTn    MPP(32, 0x5, 0, 0, 1)
-#define MPP32_TDM0_RXQ        MPP(32, 0x6, 0, 1, 1)
+#define MPP32_TDM0_RXQ        MPP(32, 0x6, 0, 0, 1)
 #define MPP32_UNUSED        MPP(32, 0x3, 0, 0, 1)
 #define MPP33_GPIO        MPP(33, 0x1, 1, 1, 1)
-#define MPP33_UA3_RDX        MPP(33, 0x4, 1, 0, 1)
+#define MPP33_UA3_RDX        MPP(33, 0x4, 0, 0, 1)
-#define MPP33_TDM0_TXQ        MPP(33, 0x6, 0, 1, 1)
+#define MPP33_TDM0_TXQ        MPP(33, 0x6, 0, 0, 1)
 #define MPP33_UNUSED        MPP(33, 0x3, 0, 0, 1)
 #define MPP34_GPIO        MPP(34, 0x1, 1, 1, 1)
-#define MPP34_UA2_TDX        MPP(34, 0x4, 0, 1, 1)
+#define MPP34_UA2_TDX        MPP(34, 0x4, 0, 0, 1)
-#define MPP34_TDM1_RXQ        MPP(34, 0x6, 0, 1, 1)
+#define MPP34_TDM1_RXQ        MPP(34, 0x6, 0, 0, 1)
 #define MPP34_UNUSED        MPP(34, 0x3, 0, 0, 1)
 #define MPP35_GPIO        MPP(35, 0x1, 1, 1, 1)
-#define MPP35_UA2_RDX        MPP(35, 0x4, 1, 0, 1)
+#define MPP35_UA2_RDX        MPP(35, 0x4, 0, 0, 1)
-#define MPP35_TDM1_TXQ        MPP(35, 0x6, 0, 1, 1)
+#define MPP35_TDM1_TXQ        MPP(35, 0x6, 0, 0, 1)
 #define MPP35_UNUSED        MPP(35, 0x3, 0, 0, 1)
 #define MPP36_GPIO        MPP(36, 0x1, 1, 1, 1)
-#define MPP36_UA0_CTSn        MPP(36, 0x2, 1, 0, 1)
+#define MPP36_UA0_CTSn        MPP(36, 0x2, 0, 0, 1)
-#define MPP36_UA2_TDX        MPP(36, 0x4, 0, 1, 1)
+#define MPP36_UA2_TDX        MPP(36, 0x4, 0, 0, 1)
-#define MPP36_TDM0_SCSn        MPP(36, 0x6, 0, 1, 1)
+#define MPP36_TDM0_SCSn        MPP(36, 0x6, 0, 0, 1)
 #define MPP36_UNUSED        MPP(36, 0x3, 0, 0, 1)
 #define MPP37_GPIO        MPP(37, 0x1, 1, 1, 1)
-#define MPP37_UA0_RTSn        MPP(37, 0x2, 0, 1, 1)
+#define MPP37_UA0_RTSn        MPP(37, 0x2, 0, 0, 1)
-#define MPP37_UA2_RXD        MPP(37, 0x4, 1, 0, 1)
+#define MPP37_UA2_RXD        MPP(37, 0x4, 0, 0, 1)
-#define MPP37_SYSRST_OUTn    MPP(37, 0x5, 0, 1, 1)
+#define MPP37_SYSRST_OUTn    MPP(37, 0x5, 0, 0, 1)
-#define MPP37_TDM_SCLK        MPP(37, 0x6, 0, 1, 1)
+#define MPP37_TDM_SCLK        MPP(37, 0x6, 0, 0, 1)
 #define MPP37_UNUSED        MPP(37, 0x3, 0, 0, 1)
 #define MPP38_GPIO        MPP(38, 0x1, 1, 1, 1)
-#define MPP38_UA1_CTSn        MPP(38, 0x2, 1, 0, 1)
+#define MPP38_UA1_CTSn        MPP(38, 0x2, 0, 0, 1)
-#define MPP38_UA3_TXD        MPP(38, 0x4, 0, 1, 1)
+#define MPP38_UA3_TXD        MPP(38, 0x4, 0, 0, 1)
-#define MPP38_SYSRST_OUTn    MPP(38, 0x5, 0, 1, 1)
+#define MPP38_SYSRST_OUTn    MPP(38, 0x5, 0, 0, 1)
-#define MPP38_TDM_SMOSI        MPP(38, 0x6, 0, 1, 1)
+#define MPP38_TDM_SMOSI        MPP(38, 0x6, 0, 0, 1)
 #define MPP38_UNUSED        MPP(38, 0x3, 0, 0, 1)
 #define MPP39_GPIO        MPP(39, 0x1, 1, 1, 1)
-#define MPP39_UA1_RTSn        MPP(39, 0x2, 0, 1, 1)
+#define MPP39_UA1_RTSn        MPP(39, 0x2, 0, 0, 1)
-#define MPP39_UA3_RXD        MPP(39, 0x4, 1, 0, 1)
+#define MPP39_UA3_RXD        MPP(39, 0x4, 0, 0, 1)
-#define MPP39_SYSRST_OUTn    MPP(39, 0x5, 0, 1, 1)
+#define MPP39_SYSRST_OUTn    MPP(39, 0x5, 0, 0, 1)
-#define MPP39_TDM_SMISO        MPP(39, 0x6, 1, 0, 1)
+#define MPP39_TDM_SMISO        MPP(39, 0x6, 0, 0, 1)
 #define MPP39_UNUSED        MPP(39, 0x3, 0, 0, 1)
 #define MPP40_GPIO        MPP(40, 0x1, 1, 1, 1)
-#define MPP40_TDM_INTn        MPP(40, 0x6, 1, 0, 1)
+#define MPP40_TDM_INTn        MPP(40, 0x6, 0, 0, 1)
 #define MPP40_UNUSED        MPP(40, 0x0, 0, 0, 1)
 #define MPP41_GPIO        MPP(41, 0x1, 1, 1, 1)
-#define MPP41_TDM_RSTn        MPP(41, 0x6, 0, 1, 1)
+#define MPP41_TDM_RSTn        MPP(41, 0x6, 0, 0, 1)
 #define MPP41_UNUSED        MPP(41, 0x0, 0, 0, 1)
 #define MPP42_GPIO        MPP(42, 0x1, 1, 1, 1)
-#define MPP42_TDM_PCLK        MPP(42, 0x6, 1, 1, 1)
+#define MPP42_TDM_PCLK        MPP(42, 0x6, 0, 0, 1)
 #define MPP42_UNUSED        MPP(42, 0x0, 0, 0, 1)
 #define MPP43_GPIO        MPP(43, 0x1, 1, 1, 1)
-#define MPP43_TDM_FSYNC        MPP(43, 0x6, 1, 1, 1)
+#define MPP43_TDM_FSYNC        MPP(43, 0x6, 0, 0, 1)
 #define MPP43_UNUSED        MPP(43, 0x0, 0, 0, 1)
 #define MPP44_GPIO        MPP(44, 0x1, 1, 1, 1)
-#define MPP44_TDM_DRX        MPP(44, 0x6, 1, 0, 1)
+#define MPP44_TDM_DRX        MPP(44, 0x6, 0, 0, 1)
 #define MPP44_UNUSED        MPP(44, 0x0, 0, 0, 1)
 #define MPP45_GPIO        MPP(45, 0x1, 1, 1, 1)
-#define MPP45_SATA0_ACTn    MPP(45, 0x3, 0, 1, 1)
+#define MPP45_SATA0_ACTn    MPP(45, 0x3, 0, 0, 1)
-#define MPP45_TDM_DRX        MPP(45, 0x6, 0, 1, 1)
+#define MPP45_TDM_DRX        MPP(45, 0x6, 0, 0, 1)
 #define MPP45_UNUSED        MPP(45, 0x0, 0, 0, 1)
 #define MPP46_GPIO        MPP(46, 0x1, 1, 1, 1)
-#define MPP46_TDM_SCSn        MPP(46, 0x6, 0, 1, 1)
+#define MPP46_TDM_SCSn        MPP(46, 0x6, 0, 0, 1)
 #define MPP46_UNUSED        MPP(46, 0x0, 0, 0, 1)
@@ -323,14 +323,14 @@
 #define MPP48_GPIO        MPP(48, 0x1, 1, 1, 1)
-#define MPP48_SATA1_ACTn    MPP(48, 0x3, 0, 1, 1)
+#define MPP48_SATA1_ACTn    MPP(48, 0x3, 0, 0, 1)
 #define MPP48_UNUSED        MPP(48, 0x2, 0, 0, 1)
 #define MPP49_GPIO        MPP(49, 0x1, 1, 1, 1)
-#define MPP49_SATA0_ACTn    MPP(49, 0x3, 0, 1, 1)
+#define MPP49_SATA0_ACTn    MPP(49, 0x3, 0, 0, 1)
-#define MPP49_M_BB        MPP(49, 0x4, 1, 0, 1)
+#define MPP49_M_BB        MPP(49, 0x4, 0, 0, 1)
 #define MPP49_UNUSED        MPP(49, 0x2, 0, 0, 1)
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index fc9b238cbc19..bd76394ccaf8 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -11,9 +11,9 @@ hwmod-common				= omap_hwmod.o \
                                          omap_hwmod_common_data.o
 clock-common                            = clock.o clock_common_data.o \
                                          clkt_dpll.o clkt_clksel.o
-secure-common                          = omap-smc.o omap-secure.o
+secure-common                           = omap-smc.o omap-secure.o
-obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
+obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
 obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index e921e3be24a4..d73316ed4207 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -437,7 +437,7 @@ static struct usbhs_omap_board_data usbhs_bdata __initdata = {
        .reset_gpio_port[2]  = -EINVAL
 };
-static void cm_t35_init_usbh(void)
+static void  __init cm_t35_init_usbh(void)
 {
        int err;
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index d58756060483..ad497620539b 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -17,6 +17,7 @@
 #include <linux/i2c/twl.h>
 #include <mach/hardware.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <plat/board.h>
@@ -102,6 +103,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
        .map_io         = omap242x_map_io,
        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
+        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = omap_generic_init,
        .timer          = &omap2_timer,
        .dt_compat      = omap242x_boards_compat,
@@ -141,6 +143,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
        .map_io         = omap3_map_io,
        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3_init,
        .timer          = &omap3_timer,
        .dt_compat      = omap3_boards_compat,
@@ -160,6 +163,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
        .map_io         = omap4_map_io,
        .init_early     = omap4430_init_early,
        .init_irq       = gic_init_irq,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = omap4_init,
        .timer          = &omap4_timer,
        .dt_compat      = omap4_boards_compat,
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index b8822f8b2891..23de98d03841 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -82,13 +82,7 @@ static int omap2_fclks_active(void)
        f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
        f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
-        /* Ignore UART clocks.  These are handled by UART core (serial.c) */
+        return (f1 | f2) ? 1 : 0;
-        f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
-        f2 &= ~OMAP24XX_EN_UART3_MASK;
-        if (f1 | f2)
-                return 1;
-        return 0;
 }
 static void omap2_enter_full_retention(void)
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 0e28bae20bd4..5dad38ec00ea 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -29,6 +29,7 @@
 #include <mach/hardware.h>
 #include <mach/orion5x.h>
 #include <plat/orion_nand.h>
+#include <plat/ehci-orion.h>
 #include <plat/time.h>
 #include <plat/common.h>
 #include <plat/addr-map.h>
@@ -72,7 +73,8 @@ void __init orion5x_map_io(void)
 ****************************************************************************/
 void __init orion5x_ehci0_init(void)
 {
-        orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
+        orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
+                        EHCI_PHY_ORION);
 }
diff --git a/arch/arm/mach-s3c2410/cpu-freq.c b/arch/arm/mach-s3c2410/cpu-freq.c
index 7dc6c46b5e2b..5404535da1a5 100644
--- a/arch/arm/mach-s3c2410/cpu-freq.c
+++ b/arch/arm/mach-s3c2410/cpu-freq.c
@@ -115,7 +115,8 @@ static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
 };
-static int s3c2410_cpufreq_add(struct device *dev)
+static int s3c2410_cpufreq_add(struct device *dev,
+                               struct subsys_interface *sif)
 {
        return s3c_cpufreq_register(&s3c2410_cpufreq_info);
 }
@@ -133,7 +134,8 @@ static int __init s3c2410_cpufreq_init(void)
 arch_initcall(s3c2410_cpufreq_init);
-static int s3c2410a_cpufreq_add(struct device *dev)
+static int s3c2410a_cpufreq_add(struct device *dev,
+                                struct subsys_interface *sif)
 {
        /* alter the maximum freq settings for S3C2410A. If a board knows
         * it only has a maximum of 200, then it should register its own
@@ -144,7 +146,7 @@ static int s3c2410a_cpufreq_add(struct device *dev)
        s3c2410_cpufreq_info.max.pclk =  66500000;
        s3c2410_cpufreq_info.name = "s3c2410a";
-        return s3c2410_cpufreq_add(dev);
+        return s3c2410_cpufreq_add(dev, sif);
 }
 static struct subsys_interface s3c2410a_cpufreq_interface = {
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 2afd00014a77..4803338cf56e 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -132,7 +132,8 @@ static struct s3c24xx_dma_order __initdata s3c2410_dma_order = {
        },
 };
-static int __init s3c2410_dma_add(struct device *dev)
+static int __init s3c2410_dma_add(struct device *dev,
+                                  struct subsys_interface *sif)
 {
        s3c2410_dma_init();
        s3c24xx_dma_order_set(&s3c2410_dma_order);
@@ -148,7 +149,7 @@ static struct subsys_interface s3c2410_dma_interface = {
 static int __init s3c2410_dma_drvinit(void)
 {
-        return subsys_interface_register(&s3c2410_interface);
+        return subsys_interface_register(&s3c2410_dma_interface);
 }
 arch_initcall(s3c2410_dma_drvinit);
diff --git a/arch/arm/mach-s3c2410/pll.c b/arch/arm/mach-s3c2410/pll.c
index c07438bfc99f..e0b3b347da82 100644
--- a/arch/arm/mach-s3c2410/pll.c
+++ b/arch/arm/mach-s3c2410/pll.c
@@ -66,7 +66,7 @@ static struct cpufreq_frequency_table pll_vals_12MHz[] = {
    { .frequency = 270000000, .index = PLLVAL(127, 1, 1),  },
 };
-static int s3c2410_plls_add(struct device *dev)
+static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif)
 {
        return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz));
 }
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index fda5385deff6..03f706dd6009 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -111,7 +111,7 @@ struct syscore_ops s3c2410_pm_syscore_ops = {
        .resume         = s3c2410_pm_resume,
 };
-static int s3c2410_pm_add(struct device *dev)
+static int s3c2410_pm_add(struct device *dev, struct subsys_interface *sif)
 {
        pm_cpu_prep = s3c2410_pm_prepare;
        pm_cpu_sleep = s3c2410_cpu_suspend;
diff --git a/arch/arm/mach-s3c2412/cpu-freq.c b/arch/arm/mach-s3c2412/cpu-freq.c
index d8664b7652ce..125be7d5fa60 100644
--- a/arch/arm/mach-s3c2412/cpu-freq.c
+++ b/arch/arm/mach-s3c2412/cpu-freq.c
@@ -194,7 +194,8 @@ static struct s3c_cpufreq_info s3c2412_cpufreq_info = {
        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),
 };
-static int s3c2412_cpufreq_add(struct device *dev)
+static int s3c2412_cpufreq_add(struct device *dev,
+                               struct subsys_interface *sif)
 {
        unsigned long fclk_rate;
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index 142acd3b5e15..38472ac920ff 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -159,7 +159,8 @@ static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
        .map_size       = ARRAY_SIZE(s3c2412_dma_mappings),
 };
-static int __init s3c2412_dma_add(struct device *dev)
+static int __init s3c2412_dma_add(struct device *dev,
+                                  struct subsys_interface *sif)
 {
        s3c2410_dma_init();
        return s3c24xx_dma_init_map(&s3c2412_dma_sel);
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c
index a8a46c1644f4..e65619ddbccc 100644
--- a/arch/arm/mach-s3c2412/irq.c
+++ b/arch/arm/mach-s3c2412/irq.c
@@ -170,7 +170,7 @@ static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)
 static struct irq_chip s3c2412_irq_rtc_chip;
-static int s3c2412_irq_add(struct device *dev)
+static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif)
 {
        unsigned int irqno;
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c
index d1adfa65f66d..d04588506ec4 100644
--- a/arch/arm/mach-s3c2412/pm.c
+++ b/arch/arm/mach-s3c2412/pm.c
@@ -56,7 +56,7 @@ static void s3c2412_pm_prepare(void)
 {
 }
-static int s3c2412_pm_add(struct device *dev)
+static int s3c2412_pm_add(struct device *dev, struct subsys_interface *sif)
 {
        pm_cpu_prep = s3c2412_pm_prepare;
        pm_cpu_sleep = s3c2412_cpu_suspend;
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c
index 36df761061de..fd49f35e448e 100644
--- a/arch/arm/mach-s3c2416/irq.c
+++ b/arch/arm/mach-s3c2416/irq.c
@@ -213,7 +213,8 @@ static int __init s3c2416_add_sub(unsigned int base,
        return 0;
 }
-static int __init s3c2416_irq_add(struct device *dev)
+static int __init s3c2416_irq_add(struct device *dev,
+                                  struct subsys_interface *sif)
 {
        printk(KERN_INFO "S3C2416: IRQ Support\n");
diff --git a/arch/arm/mach-s3c2416/pm.c b/arch/arm/mach-s3c2416/pm.c
index 3bdb15a0d419..1bd4817b8eb8 100644
--- a/arch/arm/mach-s3c2416/pm.c
+++ b/arch/arm/mach-s3c2416/pm.c
@@ -48,7 +48,7 @@ static void s3c2416_pm_prepare(void)
        __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
 }
-static int s3c2416_pm_add(struct device *dev)
+static int s3c2416_pm_add(struct device *dev, struct subsys_interface *sif)
 {
        pm_cpu_prep = s3c2416_pm_prepare;
        pm_cpu_sleep = s3c2416_cpu_suspend;
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index bedbc87a3426..414364eb426c 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -149,7 +149,7 @@ static struct clk_lookup s3c2440_clk_lookup[] = {
        CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
 };
-static int s3c2440_clk_add(struct device *dev)
+static int s3c2440_clk_add(struct device *dev, struct subsys_interface *sif)
 {
        struct clk *clock_upll;
        struct clk *clock_h;
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index 15b1ddf8f626..5f0a0c8ef84f 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -174,7 +174,8 @@ static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
        },
 };
-static int __init s3c2440_dma_add(struct device *dev)
+static int __init s3c2440_dma_add(struct device *dev,
+                                  struct subsys_interface *sif)
 {
        s3c2410_dma_init();
        s3c24xx_dma_order_set(&s3c2440_dma_order);
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c
index 4fee9bc6bcb5..4a18cde439cc 100644
--- a/arch/arm/mach-s3c2440/irq.c
+++ b/arch/arm/mach-s3c2440/irq.c
@@ -92,7 +92,7 @@ static struct irq_chip s3c_irq_wdtac97 = {
        .irq_ack        = s3c_irq_wdtac97_ack,
 };
-static int s3c2440_irq_add(struct device *dev)
+static int s3c2440_irq_add(struct device *dev, struct subsys_interface *sif)
 {
        unsigned int irqno;
diff --git a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c b/arch/arm/mach-s3c2440/s3c2440-cpufreq.c
index cf7596694efe..61776764d9f4 100644
--- a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c
+++ b/arch/arm/mach-s3c2440/s3c2440-cpufreq.c
@@ -270,7 +270,8 @@ struct s3c_cpufreq_info s3c2440_cpufreq_info = {
        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
 };
-static int s3c2440_cpufreq_add(struct device *dev)
+static int s3c2440_cpufreq_add(struct device *dev,
+                               struct subsys_interface *sif)
 {
        xtal = s3c_cpufreq_clk_get(NULL, "xtal");
        hclk = s3c_cpufreq_clk_get(NULL, "hclk");
diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c b/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
index b5368ae8d7fe..551fb433be87 100644
--- a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
+++ b/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
@@ -51,7 +51,7 @@ static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = {
        { .frequency = 400000000,       .index = PLLVAL(0x5c, 1, 1),  },        /* FVco 800.000000 */
 };
-static int s3c2440_plls12_add(struct device *dev)
+static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif)
 {
        struct clk *xtal_clk;
        unsigned long xtal;
diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c b/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
index 42f2b5cd2399..3f15bcf64290 100644
--- a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
+++ b/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
@@ -79,7 +79,8 @@ static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = {
        { .frequency = 402192000,       .index = PLLVAL(87, 2, 1),      },      /* FVco 804.384000 */
 };
-static int s3c2440_plls169344_add(struct device *dev)
+static int s3c2440_plls169344_add(struct device *dev,
+                                  struct subsys_interface *sif)
 {
        struct clk *xtal_clk;
        unsigned long xtal;
diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c2440/s3c2442.c
index 8004e0497bf4..22cb7c94a8c8 100644
--- a/arch/arm/mach-s3c2440/s3c2442.c
+++ b/arch/arm/mach-s3c2440/s3c2442.c
@@ -122,7 +122,7 @@ static struct clk s3c2442_clk_cam_upll = {
        },
 };
-static int s3c2442_clk_add(struct device *dev)
+static int s3c2442_clk_add(struct device *dev, struct subsys_interface *sif)
 {
        struct clk *clock_upll;
        struct clk *clock_h;
diff --git a/arch/arm/mach-s3c2440/s3c244x-clock.c b/arch/arm/mach-s3c2440/s3c244x-clock.c
index b3fdbdda3d5f..6d9b688c442b 100644
--- a/arch/arm/mach-s3c2440/s3c244x-clock.c
+++ b/arch/arm/mach-s3c2440/s3c244x-clock.c
@@ -72,7 +72,7 @@ static struct clk clk_arm = {
        },
 };
-static int s3c244x_clk_add(struct device *dev)
+static int s3c244x_clk_add(struct device *dev, struct subsys_interface *sif)
 {
        unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
        unsigned long clkdivn;
diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c
index 74d3dcf46a48..5fe8e58d3afd 100644
--- a/arch/arm/mach-s3c2440/s3c244x-irq.c
+++ b/arch/arm/mach-s3c2440/s3c244x-irq.c
@@ -91,7 +91,7 @@ static struct irq_chip s3c_irq_cam = {
        .irq_ack        = s3c_irq_cam_ack,
 };
-static int s3c244x_irq_add(struct device *dev)
+static int s3c244x_irq_add(struct device *dev, struct subsys_interface *sif)
 {
        unsigned int irqno;
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index de6b4a23c9ed..14224517e621 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -135,7 +135,8 @@ static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = {
        .map_size       = ARRAY_SIZE(s3c2443_dma_mappings),
 };
-static int __init s3c2443_dma_add(struct device *dev)
+static int __init s3c2443_dma_add(struct device *dev,
+                                  struct subsys_interface *sif)
 {
        s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100);
        return s3c24xx_dma_init_map(&s3c2443_dma_sel);
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c
index 35e4ff24fb43..ac2829f56d12 100644
--- a/arch/arm/mach-s3c2443/irq.c
+++ b/arch/arm/mach-s3c2443/irq.c
@@ -241,7 +241,8 @@ static int __init s3c2443_add_sub(unsigned int base,
        return 0;
 }
-static int __init s3c2443_irq_add(struct device *dev)
+static int __init s3c2443_irq_add(struct device *dev,
+                                  struct subsys_interface *sif)
 {
        printk("S3C2443: IRQ Support\n");
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 31bb27dc4aeb..aebbcc291b4e 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -138,6 +138,11 @@ static struct clk init_clocks_off[] = {
                .ctrlbit        = S3C_CLKCON_PCLK_TSADC,
        }, {
                .name           = "i2c",
+#ifdef CONFIG_S3C_DEV_I2C1
+                .devname        = "s3c2440-i2c.0",
+#else
+                .devname        = "s3c2440-i2c",
+#endif
                .parent         = &clk_p,
                .enable         = s3c64xx_pclk_ctrl,
                .ctrlbit        = S3C_CLKCON_PCLK_IIC,
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 4a7394d4bd9e..bee7dcd4df7c 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -49,7 +49,7 @@
 /* uart registration process */
-void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
        s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
 }
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
index 23f9b22439c9..9cba18bfe47b 100644
--- a/arch/arm/mach-s5p64x0/pm.c
+++ b/arch/arm/mach-s5p64x0/pm.c
@@ -160,7 +160,7 @@ static void s5p64x0_pm_prepare(void)
 }
-static int s5p64x0_pm_add(struct device *dev)
+static int s5p64x0_pm_add(struct device *dev, struct subsys_interface *sif)
 {
        pm_cpu_prep = s5p64x0_pm_prepare;
        pm_cpu_sleep = s5p64x0_cpu_suspend;
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index c78dfddd77fd..b9ec0c35379f 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -175,7 +175,7 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
        return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
 }
-static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+static int s5pv210_clk_hdmiphy_ctrl(struct clk *clk, int enable)
 {
        return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
 }
@@ -372,7 +372,7 @@ static struct clk init_clocks_off[] = {
        }, {
                .name           = "hdmiphy",
                .devname        = "s5pv210-hdmi",
-                .enable         = exynos4_clk_hdmiphy_ctrl,
+                .enable         = s5pv210_clk_hdmiphy_ctrl,
                .ctrlbit        = (1 << 0),
        }, {
                .name           = "dacphy",
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 677c71c41e50..736bfb103cbc 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -133,7 +133,7 @@ static void s5pv210_pm_prepare(void)
        s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
 }
-static int s5pv210_pm_add(struct device *dev)
+static int s5pv210_pm_add(struct device *dev, struct subsys_interface *sif)
 {
        pm_cpu_prep = s5pv210_pm_prepare;
        pm_cpu_sleep = s5pv210_cpu_suspend;
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index fcf4f377b1dc..330afdfa2475 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -60,9 +60,9 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
                .uartclk        = 216000000,
        }, {
                /* serial port on mini-pcie */
-                .membase        = IO_ADDRESS(TEGRA_UARTD_BASE),
+                .membase        = IO_ADDRESS(TEGRA_UARTC_BASE),
-                .mapbase        = TEGRA_UARTD_BASE,
+                .mapbase        = TEGRA_UARTC_BASE,
-                .irq            = INT_UARTD,
+                .irq            = INT_UARTC,
                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
                .type           = PORT_TEGRA,
                .iotype         = UPIO_MEM,
@@ -174,7 +174,7 @@ static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline,
 static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
        /* name         parent          rate            enabled */
        { "uarta",      "pll_p",        216000000,      true },
-        { "uartd",      "pll_p",        216000000,      true },
+        { "uartc",      "pll_p",        216000000,      true },
        { "pll_p_out4", "pll_p",        24000000,       true },
        { "usbd",       "clk_m",        12000000,       false },
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h
index ffa83f580db6..3c9f8da37ea3 100644
--- a/arch/arm/mach-tegra/board-paz00.h
+++ b/arch/arm/mach-tegra/board-paz00.h
@@ -22,7 +22,7 @@
 /* SDCARD */
 #define TEGRA_GPIO_SD1_CD               TEGRA_GPIO_PV5
 #define TEGRA_GPIO_SD1_WP               TEGRA_GPIO_PH1
-#define TEGRA_GPIO_SD1_POWER            TEGRA_GPIO_PT3
+#define TEGRA_GPIO_SD1_POWER            TEGRA_GPIO_PV1
 /* ULPI */
 #define TEGRA_ULPI_RST                  TEGRA_GPIO_PV0
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
index d0132e8031a1..3c9339058bec 100644
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -23,11 +23,6 @@
 #include <linux/list.h>
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-struct tegra_dma_req;
-struct tegra_dma_channel;
 #define TEGRA_DMA_REQ_SEL_CNTR                  0
 #define TEGRA_DMA_REQ_SEL_I2S_2                 1
 #define TEGRA_DMA_REQ_SEL_I2S_1                 2
@@ -56,6 +51,11 @@ struct tegra_dma_channel;
 #define TEGRA_DMA_REQ_SEL_OWR                   25
 #define TEGRA_DMA_REQ_SEL_INVALID               31
+#if defined(CONFIG_TEGRA_SYSTEM_DMA)
+struct tegra_dma_req;
+struct tegra_dma_channel;
 enum tegra_dma_mode {
        TEGRA_DMA_SHARED = 1,
        TEGRA_DMA_MODE_CONTINOUS = 2,
diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h
index 64f9d1c7f1bb..3047ff923a63 100644
--- a/arch/arm/plat-omap/include/plat/omap-secure.h
+++ b/arch/arm/plat-omap/include/plat/omap-secure.h
@@ -3,7 +3,7 @@
 #include <linux/types.h>
-#ifdef CONFIG_ARCH_OMAP2PLUS
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 extern int omap_secure_ram_reserve_memblock(void);
 #else
 static inline void omap_secure_ram_reserve_memblock(void)
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index e5a2fde29b19..089899a7db72 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -789,10 +789,7 @@ void __init orion_xor1_init(unsigned long mapbase_low,
 /*****************************************************************************
 * EHCI
 ****************************************************************************/
-static struct orion_ehci_data orion_ehci_data = {
+static struct orion_ehci_data orion_ehci_data;
-        .phy_version    = EHCI_PHY_NA,
-};
 static u64 ehci_dmamask = DMA_BIT_MASK(32);
@@ -812,8 +809,10 @@ static struct platform_device orion_ehci = {
 };
 void __init orion_ehci_init(unsigned long mapbase,
-                            unsigned long irq)
+                            unsigned long irq,
+                            enum orion_ehci_phy_ver phy_version)
 {
+        orion_ehci_data.phy_version = phy_version;
        fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
                       irq);
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
index 0fe08d77e835..a7fa005a5a0e 100644
--- a/arch/arm/plat-orion/include/plat/common.h
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -89,7 +89,8 @@ void __init orion_xor1_init(unsigned long mapbase_low,
                            unsigned long irq_1);
 void __init orion_ehci_init(unsigned long mapbase,
-                            unsigned long irq);
+                            unsigned long irq,
+                            enum orion_ehci_phy_ver phy_version);
 void __init orion_ehci_1_init(unsigned long mapbase,
                              unsigned long irq);
diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c
index 91553432711d..3b1e17bd3d17 100644
--- a/arch/arm/plat-orion/mpp.c
+++ b/arch/arm/plat-orion/mpp.c
@@ -64,8 +64,7 @@ void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
                        gpio_mode |= GPIO_INPUT_OK;
                if (*mpp_list & MPP_OUTPUT_MASK)
                        gpio_mode |= GPIO_OUTPUT_OK;
-                if (sel != 0)
-                        gpio_mode = 0;
                orion_gpio_set_valid(num, gpio_mode);
        }
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 32a6e394db24..f10768e988d4 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -468,8 +468,10 @@ void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
 {
        struct s3c2410_platform_i2c *npd;
-        if (!pd)
+        if (!pd) {
                pd = &default_i2c_data;
+                pd->bus_num = 0;
+        }
        npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
                               &s3c_device_i2c0);