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-rw-r--r--arch/powerpc/boot/dts/mpc5121ads.dts122
1 files changed, 122 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
new file mode 100644
index 000000000000..94ad7b2b241e
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -0,0 +1,122 @@
1/*
2 * MPC5121E MDS Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "mpc5121ads";
16 compatible = "fsl,mpc5121ads";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 PowerPC,5121@0 {
25 device_type = "cpu";
26 reg = <0>;
27 d-cache-line-size = <0x20>; // 32 bytes
28 i-cache-line-size = <0x20>; // 32 bytes
29 d-cache-size = <0x8000>; // L1, 32K
30 i-cache-size = <0x8000>; // L1, 32K
31 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
32 bus-frequency = <198000000>; // 198 MHz csb bus
33 clock-frequency = <396000000>; // 396 MHz ppc core
34 };
35 };
36
37 memory {
38 device_type = "memory";
39 reg = <0x00000000 0x10000000>; // 256MB at 0
40 };
41
42 localbus@80000020 {
43 compatible = "fsl,mpc5121ads-localbus";
44 #address-cells = <2>;
45 #size-cells = <1>;
46 reg = <0x80000020 0x40>;
47
48 ranges = <0x0 0x0 0xfc000000 0x04000000
49 0x2 0x0 0x82000000 0x00008000>;
50
51 flash@0,0 {
52 compatible = "cfi-flash";
53 reg = <0 0x0 0x4000000>;
54 bank-width = <4>;
55 device-width = <1>;
56 };
57
58 board-control@2,0 {
59 compatible = "fsl,mpc5121ads-cpld";
60 reg = <0x2 0x0 0x8000>;
61 };
62 };
63
64 soc@80000000 {
65 compatible = "fsl,mpc5121-immr";
66 #address-cells = <1>;
67 #size-cells = <1>;
68 #interrupt-cells = <2>;
69 ranges = <0x0 0x80000000 0x400000>;
70 reg = <0x80000000 0x400000>;
71 bus-frequency = <66000000>; // 66 MHz ips bus
72
73
74 // IPIC
75 // interrupts cell = <intr #, sense>
76 // sense values match linux IORESOURCE_IRQ_* defines:
77 // sense == 8: Level, low assertion
78 // sense == 2: Edge, high-to-low change
79 //
80 ipic: interrupt-controller@c00 {
81 compatible = "fsl,mpc5121-ipic", "fsl,ipic";
82 interrupt-controller;
83 #address-cells = <0>;
84 #interrupt-cells = <2>;
85 reg = <0xc00 0x100>;
86 };
87
88 // 512x PSCs are not 52xx PSCs compatible
89 // PSC3 serial port A aka ttyPSC0
90 serial@11300 {
91 device_type = "serial";
92 compatible = "fsl,mpc5121-psc-uart";
93 // Logical port assignment needed until driver
94 // learns to use aliases
95 port-number = <0>;
96 cell-index = <3>;
97 reg = <0x11300 0x100>;
98 interrupts = <0x28 0x8>; // actually the fifo irq
99 interrupt-parent = < &ipic >;
100 };
101
102 // PSC4 serial port B aka ttyPSC1
103 serial@11400 {
104 device_type = "serial";
105 compatible = "fsl,mpc5121-psc-uart";
106 // Logical port assignment needed until driver
107 // learns to use aliases
108 port-number = <1>;
109 cell-index = <4>;
110 reg = <0x11400 0x100>;
111 interrupts = <0x28 0x8>; // actually the fifo irq
112 interrupt-parent = < &ipic >;
113 };
114
115 pscsfifo@11f00 {
116 compatible = "fsl,mpc5121-psc-fifo";
117 reg = <0x11f00 0x100>;
118 interrupts = <0x28 0x8>;
119 interrupt-parent = < &ipic >;
120 };
121 };
122};