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-rw-r--r--arch/alpha/kernel/pci.c40
-rw-r--r--arch/arm/common/it8152.c9
-rw-r--r--arch/arm/common/via82c505.c3
-rw-r--r--arch/arm/configs/bonito_defconfig72
-rw-r--r--arch/arm/configs/kota2_defconfig122
-rw-r--r--arch/arm/configs/marzen_defconfig87
-rw-r--r--arch/arm/include/asm/mach/pci.h2
-rw-r--r--arch/arm/include/asm/pci.h12
-rw-r--r--arch/arm/kernel/bios32.c34
-rw-r--r--arch/arm/mach-cns3xxx/pcie.c8
-rw-r--r--arch/arm/mach-dove/pcie.c9
-rw-r--r--arch/arm/mach-exynos/include/mach/cpufreq.h34
-rw-r--r--arch/arm/mach-footbridge/dc21285.c8
-rw-r--r--arch/arm/mach-integrator/pci_v3.c19
-rw-r--r--arch/arm/mach-iop13xx/pci.c17
-rw-r--r--arch/arm/mach-ixp2000/enp2611.c3
-rw-r--r--arch/arm/mach-ixp2000/pci.c8
-rw-r--r--arch/arm/mach-ixp23xx/pci.c8
-rw-r--r--arch/arm/mach-ixp4xx/common-pci.c8
-rw-r--r--arch/arm/mach-kirkwood/pcie.c8
-rw-r--r--arch/arm/mach-ks8695/pci.c8
-rw-r--r--arch/arm/mach-mv78xx0/pcie.c8
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c3
-rw-r--r--arch/arm/mach-omap2/mcbsp.c3
-rw-r--r--arch/arm/mach-orion5x/pci.c16
-rw-r--r--arch/arm/mach-pxa/corgi.c9
-rw-r--r--arch/arm/mach-pxa/eseries.c18
-rw-r--r--arch/arm/mach-pxa/poodle.c6
-rw-r--r--arch/arm/mach-pxa/stargate2.c6
-rw-r--r--arch/arm/mach-pxa/tosa.c6
-rw-r--r--arch/arm/mach-s3c64xx/mach-crag6410.c6
-rw-r--r--arch/arm/mach-sa1100/pci-nanoengine.c13
-rw-r--r--arch/arm/mach-shmobile/Kconfig27
-rw-r--r--arch/arm/mach-shmobile/Makefile9
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c15
-rw-r--r--arch/arm/mach-shmobile/board-bonito.c522
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c14
-rw-r--r--arch/arm/mach-shmobile/board-marzen.c157
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7740.c382
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7779.c176
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c6
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c140
-rw-r--r--arch/arm/mach-shmobile/headsmp.S2
-rw-r--r--arch/arm/mach-shmobile/hotplug.c32
-rw-r--r--arch/arm/mach-shmobile/include/mach/common.h22
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7740.h584
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7779.h363
-rw-r--r--arch/arm/mach-shmobile/intc-r8a7740.c631
-rw-r--r--arch/arm/mach-shmobile/intc-r8a7779.c58
-rw-r--r--arch/arm/mach-shmobile/pfc-r8a7740.c2562
-rw-r--r--arch/arm/mach-shmobile/pfc-r8a7779.c2645
-rw-r--r--arch/arm/mach-shmobile/platsmp.c21
-rw-r--r--arch/arm/mach-shmobile/pm-r8a7779.c249
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c352
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c239
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c6
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c2
-rw-r--r--arch/arm/mach-shmobile/smp-r8a7779.c153
-rw-r--r--arch/arm/mach-tegra/board-harmony.c8
-rw-r--r--arch/arm/mach-tegra/board-seaboard.c8
-rw-r--r--arch/arm/mach-tegra/pcie.c9
-rw-r--r--arch/arm/mach-versatile/pci.c19
-rw-r--r--arch/arm/plat-iop/pci.c8
-rw-r--r--arch/arm/plat-omap/cpu-omap.c171
-rw-r--r--arch/blackfin/include/asm/pci.h4
-rw-r--r--arch/frv/Kconfig1
-rw-r--r--arch/frv/mb93090-mb00/pci-frv.c20
-rw-r--r--arch/frv/mb93090-mb00/pci-frv.h2
-rw-r--r--arch/frv/mb93090-mb00/pci-vdk.c11
-rw-r--r--arch/h8300/Kconfig1
-rw-r--r--arch/h8300/include/asm/pci.h5
-rw-r--r--arch/ia64/include/asm/pci.h6
-rw-r--r--arch/ia64/pci/pci.c43
-rw-r--r--arch/m68k/Kconfig1
-rw-r--r--arch/microblaze/Kconfig1
-rw-r--r--arch/microblaze/include/asm/pci-bridge.h1
-rw-r--r--arch/microblaze/include/asm/pci.h5
-rw-r--r--arch/microblaze/pci/pci-common.c43
-rw-r--r--arch/mips/pci/pci.c38
-rw-r--r--arch/mn10300/unit-asb2305/pci-asb2305.c22
-rw-r--r--arch/mn10300/unit-asb2305/pci-asb2305.h2
-rw-r--r--arch/mn10300/unit-asb2305/pci.c12
-rw-r--r--arch/openrisc/Kconfig1
-rw-r--r--arch/powerpc/include/asm/pci-bridge.h1
-rw-r--r--arch/powerpc/include/asm/pci.h5
-rw-r--r--arch/powerpc/kernel/pci-common.c30
-rw-r--r--arch/powerpc/kernel/pci_64.c40
-rw-r--r--arch/score/Kconfig1
-rw-r--r--arch/sh/boards/board-magicpanelr2.c34
-rw-r--r--arch/sh/boards/board-sh7757lcr.c39
-rw-r--r--arch/sh/boards/mach-ap325rxa/setup.c12
-rw-r--r--arch/sh/boards/mach-ecovec24/setup.c36
-rw-r--r--arch/sh/boards/mach-kfr2r09/setup.c12
-rw-r--r--arch/sh/boards/mach-migor/setup.c12
-rw-r--r--arch/sh/boards/mach-rsk/setup.c43
-rw-r--r--arch/sh/boards/mach-se/7722/setup.c3
-rw-r--r--arch/sh/boards/mach-se/7724/setup.c44
-rw-r--r--arch/sh/drivers/pci/pci.c41
-rw-r--r--arch/sh/include/asm/device.h10
-rw-r--r--arch/sh/include/asm/hwblk.h70
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7722.h13
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7723.h3
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7724.h4
-rw-r--r--arch/sh/kernel/cpu/Makefile2
-rw-r--r--arch/sh/kernel/cpu/hwblk.c159
-rw-r--r--arch/sh/kernel/cpu/sh4/sq.c8
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile6
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c77
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7723.c209
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7724.c201
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7757.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c106
-rw-r--r--arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c117
-rw-r--r--arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c121
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c38
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c39
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c64
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c7
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c2
-rw-r--r--arch/sh/kernel/cpu/shmobile/Makefile1
-rw-r--r--arch/sh/kernel/cpu/shmobile/cpuidle.c3
-rw-r--r--arch/sh/kernel/cpu/shmobile/pm_runtime.c319
-rw-r--r--arch/sh/kernel/entry-common.S1
-rw-r--r--arch/sh/kernel/signal_32.c4
-rw-r--r--arch/sh/kernel/signal_64.c4
-rw-r--r--arch/sh/kernel/time.c2
-rw-r--r--arch/sh/mm/cache-sh2a.c123
-rw-r--r--arch/sparc/include/asm/pci_32.h5
-rw-r--r--arch/sparc/include/asm/pci_64.h5
-rw-r--r--arch/sparc/kernel/leon_pci.c25
-rw-r--r--arch/sparc/kernel/pci.c22
-rw-r--r--arch/tile/include/asm/pci.h7
-rw-r--r--arch/tile/kernel/pci.c5
-rw-r--r--arch/um/Kconfig.common1
-rw-r--r--arch/unicore32/include/asm/pci.h5
-rw-r--r--arch/unicore32/kernel/pci.c5
-rw-r--r--arch/x86/Kconfig38
-rw-r--r--arch/x86/Kconfig.debug25
-rw-r--r--arch/x86/boot/compressed/Makefile10
-rw-r--r--arch/x86/boot/compressed/eboot.c1022
-rw-r--r--arch/x86/boot/compressed/eboot.h61
-rw-r--r--arch/x86/boot/compressed/efi_stub_32.S86
-rw-r--r--arch/x86/boot/compressed/efi_stub_64.S1
-rw-r--r--arch/x86/boot/compressed/head_32.S22
-rw-r--r--arch/x86/boot/compressed/head_64.S20
-rw-r--r--arch/x86/boot/compressed/string.c9
-rw-r--r--arch/x86/boot/header.S158
-rw-r--r--arch/x86/boot/string.c35
-rw-r--r--arch/x86/boot/tools/build.c39
-rw-r--r--arch/x86/crypto/Makefile4
-rw-r--r--arch/x86/crypto/serpent-sse2-i586-asm_32.S638
-rw-r--r--arch/x86/crypto/serpent-sse2-x86_64-asm_64.S761
-rw-r--r--arch/x86/crypto/serpent_sse2_glue.c1070
-rw-r--r--arch/x86/crypto/twofish_glue_3way.c218
-rw-r--r--arch/x86/include/asm/amd_nb.h2
-rw-r--r--arch/x86/include/asm/bootparam.h2
-rw-r--r--arch/x86/include/asm/efi.h4
-rw-r--r--arch/x86/include/asm/fixmap.h2
-rw-r--r--arch/x86/include/asm/init.h2
-rw-r--r--arch/x86/include/asm/pci.h9
-rw-r--r--arch/x86/include/asm/pci_x86.h2
-rw-r--r--arch/x86/include/asm/serpent.h63
-rw-r--r--arch/x86/include/asm/setup.h2
-rw-r--r--arch/x86/include/asm/smp.h6
-rw-r--r--arch/x86/include/asm/thread_info.h4
-rw-r--r--arch/x86/include/asm/topology.h2
-rw-r--r--arch/x86/include/asm/x86_init.h1
-rw-r--r--arch/x86/kernel/Makefile1
-rw-r--r--arch/x86/kernel/amd_nb.c31
-rw-r--r--arch/x86/kernel/asm-offsets.c2
-rw-r--r--arch/x86/kernel/e820.c59
-rw-r--r--arch/x86/kernel/early_printk.c2
-rw-r--r--arch/x86/kernel/irq_32.c5
-rw-r--r--arch/x86/kernel/irq_64.c35
-rw-r--r--arch/x86/kernel/nmi_selftest.c180
-rw-r--r--arch/x86/kernel/setup.c7
-rw-r--r--arch/x86/kernel/smp.c72
-rw-r--r--arch/x86/kernel/smpboot.c17
-rw-r--r--arch/x86/kernel/tsc.c20
-rw-r--r--arch/x86/kernel/x86_init.c1
-rw-r--r--arch/x86/mm/init.c23
-rw-r--r--arch/x86/mm/init_32.c29
-rw-r--r--arch/x86/mm/init_64.c11
-rw-r--r--arch/x86/mm/mmap.c4
-rw-r--r--arch/x86/mm/numa.c10
-rw-r--r--arch/x86/mm/pageattr.c6
-rw-r--r--arch/x86/pci/Makefile5
-rw-r--r--arch/x86/pci/acpi.c75
-rw-r--r--arch/x86/pci/amd_bus.c43
-rw-r--r--arch/x86/pci/broadcom_bus.c62
-rw-r--r--arch/x86/pci/bus_numa.c31
-rw-r--r--arch/x86/pci/common.c19
-rw-r--r--arch/x86/pci/i386.c20
-rw-r--r--arch/x86/pci/legacy.c3
-rw-r--r--arch/x86/pci/numaq_32.c2
-rw-r--r--arch/x86/platform/mrst/Makefile6
-rw-r--r--arch/x86/platform/mrst/mrst.c4
-rw-r--r--arch/xtensa/Kconfig1
-rw-r--r--arch/xtensa/include/asm/pci.h5
-rw-r--r--arch/xtensa/kernel/pci.c90
202 files changed, 15313 insertions, 2462 deletions
diff --git a/arch/alpha/kernel/pci.c b/arch/alpha/kernel/pci.c
index f3cae275d3f5..8c723c1b086a 100644
--- a/arch/alpha/kernel/pci.c
+++ b/arch/alpha/kernel/pci.c
@@ -281,27 +281,9 @@ pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus)
281void __devinit 281void __devinit
282pcibios_fixup_bus(struct pci_bus *bus) 282pcibios_fixup_bus(struct pci_bus *bus)
283{ 283{
284 /* Propagate hose info into the subordinate devices. */
285
286 struct pci_controller *hose = bus->sysdata;
287 struct pci_dev *dev = bus->self; 284 struct pci_dev *dev = bus->self;
288 285
289 if (!dev) { 286 if (pci_probe_only && dev &&
290 /* Root bus. */
291 u32 pci_mem_end;
292 u32 sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
293 unsigned long end;
294
295 bus->resource[0] = hose->io_space;
296 bus->resource[1] = hose->mem_space;
297
298 /* Adjust hose mem_space limit to prevent PCI allocations
299 in the iommu windows. */
300 pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
301 end = hose->mem_space->start + pci_mem_end;
302 if (hose->mem_space->end > end)
303 hose->mem_space->end = end;
304 } else if (pci_probe_only &&
305 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 287 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
306 pci_read_bridge_bases(bus); 288 pci_read_bridge_bases(bus);
307 pcibios_fixup_device_resources(dev, bus); 289 pcibios_fixup_device_resources(dev, bus);
@@ -414,13 +396,31 @@ void __init
414common_init_pci(void) 396common_init_pci(void)
415{ 397{
416 struct pci_controller *hose; 398 struct pci_controller *hose;
399 struct list_head resources;
417 struct pci_bus *bus; 400 struct pci_bus *bus;
418 int next_busno; 401 int next_busno;
419 int need_domain_info = 0; 402 int need_domain_info = 0;
403 u32 pci_mem_end;
404 u32 sg_base;
405 unsigned long end;
420 406
421 /* Scan all of the recorded PCI controllers. */ 407 /* Scan all of the recorded PCI controllers. */
422 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) { 408 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
423 bus = pci_scan_bus(next_busno, alpha_mv.pci_ops, hose); 409 sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
410
411 /* Adjust hose mem_space limit to prevent PCI allocations
412 in the iommu windows. */
413 pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
414 end = hose->mem_space->start + pci_mem_end;
415 if (hose->mem_space->end > end)
416 hose->mem_space->end = end;
417
418 INIT_LIST_HEAD(&resources);
419 pci_add_resource(&resources, hose->io_space);
420 pci_add_resource(&resources, hose->mem_space);
421
422 bus = pci_scan_root_bus(NULL, next_busno, alpha_mv.pci_ops,
423 hose, &resources);
424 hose->bus = bus; 424 hose->bus = bus;
425 hose->need_domain_info = need_domain_info; 425 hose->need_domain_info = need_domain_info;
426 next_busno = bus->subordinate + 1; 426 next_busno = bus->subordinate + 1;
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index b539ec855e1a..d1bcd7b13ebc 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -299,8 +299,8 @@ int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
299 goto err1; 299 goto err1;
300 } 300 }
301 301
302 sys->resource[0] = &it8152_io; 302 pci_add_resource(&sys->resources, &it8152_io);
303 sys->resource[1] = &it8152_mem; 303 pci_add_resource(&sys->resources, &it8152_mem);
304 304
305 if (platform_notify || platform_notify_remove) { 305 if (platform_notify || platform_notify_remove) {
306 printk(KERN_ERR "PCI: Can't use platform_notify\n"); 306 printk(KERN_ERR "PCI: Can't use platform_notify\n");
@@ -327,6 +327,9 @@ err0:
327 */ 327 */
328unsigned int pcibios_max_latency = 255; 328unsigned int pcibios_max_latency = 255;
329 329
330/* ITE bridge requires setting latency timer to avoid early bus access
331 termination by PCI bus master devices
332*/
330void pcibios_set_master(struct pci_dev *dev) 333void pcibios_set_master(struct pci_dev *dev)
331{ 334{
332 u8 lat; 335 u8 lat;
@@ -352,7 +355,7 @@ void pcibios_set_master(struct pci_dev *dev)
352 355
353struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys) 356struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
354{ 357{
355 return pci_scan_bus(nr, &it8152_ops, sys); 358 return pci_scan_root_bus(NULL, nr, &it8152_ops, sys, &sys->resources);
356} 359}
357 360
358EXPORT_SYMBOL(dma_set_coherent_mask); 361EXPORT_SYMBOL(dma_set_coherent_mask);
diff --git a/arch/arm/common/via82c505.c b/arch/arm/common/via82c505.c
index 8421d39109b3..67dd2affc57a 100644
--- a/arch/arm/common/via82c505.c
+++ b/arch/arm/common/via82c505.c
@@ -86,7 +86,8 @@ int __init via82c505_setup(int nr, struct pci_sys_data *sys)
86struct pci_bus * __init via82c505_scan_bus(int nr, struct pci_sys_data *sysdata) 86struct pci_bus * __init via82c505_scan_bus(int nr, struct pci_sys_data *sysdata)
87{ 87{
88 if (nr == 0) 88 if (nr == 0)
89 return pci_scan_bus(0, &via82c505_ops, sysdata); 89 return pci_scan_root_bus(NULL, 0, &via82c505_ops, sysdata,
90 &sysdata->resources);
90 91
91 return NULL; 92 return NULL;
92} 93}
diff --git a/arch/arm/configs/bonito_defconfig b/arch/arm/configs/bonito_defconfig
new file mode 100644
index 000000000000..54571082d920
--- /dev/null
+++ b/arch/arm/configs/bonito_defconfig
@@ -0,0 +1,72 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=16
6# CONFIG_UTS_NS is not set
7# CONFIG_IPC_NS is not set
8# CONFIG_USER_NS is not set
9# CONFIG_PID_NS is not set
10CONFIG_BLK_DEV_INITRD=y
11CONFIG_INITRAMFS_SOURCE=""
12CONFIG_CC_OPTIMIZE_FOR_SIZE=y
13CONFIG_SLAB=y
14CONFIG_MODULES=y
15CONFIG_MODULE_UNLOAD=y
16CONFIG_MODULE_FORCE_UNLOAD=y
17# CONFIG_BLK_DEV_BSG is not set
18# CONFIG_IOSCHED_DEADLINE is not set
19# CONFIG_IOSCHED_CFQ is not set
20CONFIG_ARCH_SHMOBILE=y
21CONFIG_ARCH_R8A7740=y
22CONFIG_MACH_BONITO=y
23# CONFIG_SH_TIMER_TMU is not set
24CONFIG_AEABI=y
25# CONFIG_OABI_COMPAT is not set
26CONFIG_FORCE_MAX_ZONEORDER=12
27CONFIG_ZBOOT_ROM_TEXT=0x0
28CONFIG_ZBOOT_ROM_BSS=0x0
29CONFIG_CMDLINE="console=ttySC5,115200 earlyprintk=sh-sci.5,115200 ignore_loglevel"
30CONFIG_KEXEC=y
31# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
32# CONFIG_SUSPEND is not set
33CONFIG_PM_RUNTIME=y
34CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
35# CONFIG_FIRMWARE_IN_KERNEL is not set
36CONFIG_MTD=y
37CONFIG_MTD_CHAR=y
38CONFIG_MTD_BLOCK=y
39CONFIG_MTD_CFI=y
40CONFIG_MTD_CFI_ADV_OPTIONS=y
41CONFIG_MTD_CFI_INTELEXT=y
42CONFIG_MTD_PHYSMAP=y
43CONFIG_MTD_ARM_INTEGRATOR=y
44CONFIG_MTD_BLOCK2MTD=y
45CONFIG_SCSI=y
46CONFIG_BLK_DEV_SD=y
47# CONFIG_SCSI_LOWLEVEL is not set
48# CONFIG_INPUT_KEYBOARD is not set
49# CONFIG_INPUT_MOUSE is not set
50# CONFIG_LEGACY_PTYS is not set
51CONFIG_SERIAL_SH_SCI=y
52CONFIG_SERIAL_SH_SCI_NR_UARTS=9
53CONFIG_SERIAL_SH_SCI_CONSOLE=y
54# CONFIG_HW_RANDOM is not set
55CONFIG_I2C=y
56CONFIG_I2C_CHARDEV=y
57CONFIG_I2C_SH_MOBILE=y
58CONFIG_GPIO_SYSFS=y
59# CONFIG_HWMON is not set
60# CONFIG_MFD_SUPPORT is not set
61# CONFIG_HID_SUPPORT is not set
62# CONFIG_USB_SUPPORT is not set
63CONFIG_UIO=y
64CONFIG_UIO_PDRV=y
65CONFIG_UIO_PDRV_GENIRQ=y
66# CONFIG_DNOTIFY is not set
67# CONFIG_INOTIFY_USER is not set
68CONFIG_TMPFS=y
69# CONFIG_MISC_FILESYSTEMS is not set
70# CONFIG_ENABLE_WARN_DEPRECATED is not set
71# CONFIG_ENABLE_MUST_CHECK is not set
72# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/configs/kota2_defconfig b/arch/arm/configs/kota2_defconfig
new file mode 100644
index 000000000000..b7735d6347ac
--- /dev/null
+++ b/arch/arm/configs/kota2_defconfig
@@ -0,0 +1,122 @@
1# CONFIG_ARM_PATCH_PHYS_VIRT is not set
2CONFIG_EXPERIMENTAL=y
3CONFIG_SYSVIPC=y
4CONFIG_IKCONFIG=y
5CONFIG_IKCONFIG_PROC=y
6CONFIG_LOG_BUF_SHIFT=16
7CONFIG_CGROUPS=y
8CONFIG_CPUSETS=y
9CONFIG_NAMESPACES=y
10# CONFIG_UTS_NS is not set
11# CONFIG_IPC_NS is not set
12# CONFIG_USER_NS is not set
13# CONFIG_PID_NS is not set
14CONFIG_SYSCTL_SYSCALL=y
15CONFIG_EMBEDDED=y
16CONFIG_SLAB=y
17# CONFIG_BLK_DEV_BSG is not set
18# CONFIG_IOSCHED_DEADLINE is not set
19# CONFIG_IOSCHED_CFQ is not set
20CONFIG_ARCH_SHMOBILE=y
21CONFIG_KEYBOARD_GPIO_POLLED=y
22CONFIG_ARCH_SH73A0=y
23CONFIG_MACH_KOTA2=y
24CONFIG_MEMORY_SIZE=0x1e0000000
25# CONFIG_SH_TIMER_TMU is not set
26# CONFIG_SWP_EMULATE is not set
27CONFIG_CPU_BPREDICT_DISABLE=y
28CONFIG_ARM_ERRATA_460075=y
29CONFIG_ARM_ERRATA_742230=y
30CONFIG_ARM_ERRATA_742231=y
31CONFIG_PL310_ERRATA_588369=y
32CONFIG_ARM_ERRATA_720789=y
33CONFIG_PL310_ERRATA_727915=y
34CONFIG_ARM_ERRATA_743622=y
35CONFIG_ARM_ERRATA_751472=y
36CONFIG_PL310_ERRATA_753970=y
37CONFIG_ARM_ERRATA_754322=y
38CONFIG_PL310_ERRATA_769419=y
39CONFIG_NO_HZ=y
40CONFIG_SMP=y
41CONFIG_AEABI=y
42# CONFIG_OABI_COMPAT is not set
43CONFIG_HIGHMEM=y
44CONFIG_ZBOOT_ROM_TEXT=0x0
45CONFIG_ZBOOT_ROM_BSS=0x0
46CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
47CONFIG_CMDLINE_FORCE=y
48CONFIG_KEXEC=y
49CONFIG_CPU_IDLE=y
50# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
51CONFIG_PM_RUNTIME=y
52CONFIG_NET=y
53CONFIG_PACKET=y
54CONFIG_UNIX=y
55CONFIG_INET=y
56CONFIG_IP_PNP=y
57CONFIG_IP_PNP_DHCP=y
58# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
59# CONFIG_INET_XFRM_MODE_TUNNEL is not set
60# CONFIG_INET_XFRM_MODE_BEET is not set
61# CONFIG_INET_LRO is not set
62# CONFIG_INET_DIAG is not set
63# CONFIG_IPV6 is not set
64CONFIG_CFG80211=y
65CONFIG_WIRELESS_EXT_SYSFS=y
66CONFIG_MAC80211=y
67CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
68# CONFIG_BLK_DEV is not set
69CONFIG_NETDEVICES=y
70# CONFIG_NET_VENDOR_BROADCOM is not set
71# CONFIG_NET_VENDOR_CHELSIO is not set
72# CONFIG_NET_VENDOR_FARADAY is not set
73# CONFIG_NET_VENDOR_INTEL is not set
74# CONFIG_NET_VENDOR_MARVELL is not set
75# CONFIG_NET_VENDOR_MICREL is not set
76# CONFIG_NET_VENDOR_NATSEMI is not set
77# CONFIG_NET_VENDOR_SEEQ is not set
78CONFIG_SMSC911X=y
79# CONFIG_NET_VENDOR_STMICRO is not set
80CONFIG_B43=y
81CONFIG_B43_PHY_N=y
82CONFIG_B43_DEBUG=y
83CONFIG_INPUT_SPARSEKMAP=y
84# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
85CONFIG_INPUT_EVDEV=y
86# CONFIG_KEYBOARD_ATKBD is not set
87CONFIG_KEYBOARD_GPIO=y
88CONFIG_KEYBOARD_SH_KEYSC=y
89# CONFIG_INPUT_MOUSE is not set
90# CONFIG_LEGACY_PTYS is not set
91CONFIG_SERIAL_SH_SCI=y
92CONFIG_SERIAL_SH_SCI_NR_UARTS=9
93CONFIG_SERIAL_SH_SCI_CONSOLE=y
94# CONFIG_HW_RANDOM is not set
95CONFIG_I2C_SH_MOBILE=y
96# CONFIG_HWMON is not set
97CONFIG_BCMA=y
98CONFIG_BCMA_DEBUG=y
99CONFIG_FB=y
100CONFIG_FB_SH_MOBILE_LCDC=y
101CONFIG_LCD_PLATFORM=y
102CONFIG_FRAMEBUFFER_CONSOLE=y
103CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
104# CONFIG_HID_SUPPORT is not set
105# CONFIG_USB_SUPPORT is not set
106CONFIG_MMC=y
107CONFIG_MMC_SDHI=y
108CONFIG_MMC_SH_MMCIF=y
109CONFIG_NEW_LEDS=y
110CONFIG_LEDS_CLASS=y
111CONFIG_LEDS_GPIO=y
112CONFIG_LEDS_RENESAS_TPU=y
113CONFIG_LEDS_TRIGGERS=y
114# CONFIG_DNOTIFY is not set
115# CONFIG_INOTIFY_USER is not set
116CONFIG_TMPFS=y
117# CONFIG_MISC_FILESYSTEMS is not set
118CONFIG_MAGIC_SYSRQ=y
119CONFIG_DEBUG_INFO=y
120CONFIG_DEBUG_INFO_REDUCED=y
121# CONFIG_FTRACE is not set
122CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
new file mode 100644
index 000000000000..864f9a5c39dd
--- /dev/null
+++ b/arch/arm/configs/marzen_defconfig
@@ -0,0 +1,87 @@
1# CONFIG_ARM_PATCH_PHYS_VIRT is not set
2CONFIG_EXPERIMENTAL=y
3CONFIG_KERNEL_LZMA=y
4CONFIG_IKCONFIG=y
5CONFIG_IKCONFIG_PROC=y
6CONFIG_LOG_BUF_SHIFT=16
7CONFIG_SYSCTL_SYSCALL=y
8CONFIG_EMBEDDED=y
9CONFIG_SLAB=y
10# CONFIG_BLOCK is not set
11CONFIG_ARCH_SHMOBILE=y
12CONFIG_ARCH_R8A7779=y
13CONFIG_MACH_MARZEN=y
14CONFIG_MEMORY_START=0x60000000
15CONFIG_MEMORY_SIZE=0x10000000
16CONFIG_SHMOBILE_TIMER_HZ=1024
17# CONFIG_SH_TIMER_CMT is not set
18# CONFIG_SWP_EMULATE is not set
19CONFIG_ARM_ERRATA_430973=y
20CONFIG_ARM_ERRATA_458693=y
21CONFIG_ARM_ERRATA_460075=y
22CONFIG_ARM_ERRATA_743622=y
23CONFIG_ARM_ERRATA_754322=y
24CONFIG_NO_HZ=y
25CONFIG_SMP=y
26# CONFIG_ARM_CPU_TOPOLOGY is not set
27CONFIG_AEABI=y
28# CONFIG_OABI_COMPAT is not set
29CONFIG_HIGHMEM=y
30CONFIG_ZBOOT_ROM_TEXT=0x0
31CONFIG_ZBOOT_ROM_BSS=0x0
32CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
33CONFIG_CMDLINE_FORCE=y
34CONFIG_KEXEC=y
35# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
36CONFIG_PM_RUNTIME=y
37CONFIG_NET=y
38CONFIG_INET=y
39# CONFIG_IPV6 is not set
40# CONFIG_WIRELESS is not set
41CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
42CONFIG_DEVTMPFS=y
43CONFIG_DEVTMPFS_MOUNT=y
44# CONFIG_STANDALONE is not set
45# CONFIG_PREVENT_FIRMWARE_BUILD is not set
46# CONFIG_FW_LOADER is not set
47CONFIG_NETDEVICES=y
48# CONFIG_NET_VENDOR_BROADCOM is not set
49# CONFIG_NET_VENDOR_FARADAY is not set
50# CONFIG_NET_VENDOR_INTEL is not set
51# CONFIG_NET_VENDOR_MICREL is not set
52# CONFIG_NET_VENDOR_NATSEMI is not set
53# CONFIG_NET_VENDOR_SEEQ is not set
54CONFIG_SMC911X=y
55CONFIG_SMSC911X=y
56# CONFIG_NET_VENDOR_STMICRO is not set
57# CONFIG_WLAN is not set
58# CONFIG_INPUT_MOUSEDEV is not set
59# CONFIG_INPUT_KEYBOARD is not set
60# CONFIG_INPUT_MOUSE is not set
61# CONFIG_SERIO is not set
62# CONFIG_VT is not set
63# CONFIG_LEGACY_PTYS is not set
64# CONFIG_DEVKMEM is not set
65CONFIG_SERIAL_SH_SCI=y
66CONFIG_SERIAL_SH_SCI_NR_UARTS=6
67CONFIG_SERIAL_SH_SCI_CONSOLE=y
68# CONFIG_HW_RANDOM is not set
69CONFIG_GPIO_SYSFS=y
70# CONFIG_HWMON is not set
71CONFIG_SSB=y
72# CONFIG_HID_SUPPORT is not set
73# CONFIG_USB_SUPPORT is not set
74CONFIG_UIO=y
75CONFIG_UIO_PDRV_GENIRQ=y
76# CONFIG_IOMMU_SUPPORT is not set
77# CONFIG_FILE_LOCKING is not set
78# CONFIG_DNOTIFY is not set
79# CONFIG_INOTIFY_USER is not set
80CONFIG_TMPFS=y
81# CONFIG_MISC_FILESYSTEMS is not set
82CONFIG_MAGIC_SYSRQ=y
83CONFIG_DEBUG_INFO=y
84CONFIG_DEBUG_INFO_REDUCED=y
85# CONFIG_FTRACE is not set
86CONFIG_DEBUG_USER=y
87CONFIG_AVERAGE=y
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 186efd4e05c9..d943b7d20f11 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -40,7 +40,7 @@ struct pci_sys_data {
40 u64 mem_offset; /* bus->cpu memory mapping offset */ 40 u64 mem_offset; /* bus->cpu memory mapping offset */
41 unsigned long io_offset; /* bus->cpu IO mapping offset */ 41 unsigned long io_offset; /* bus->cpu IO mapping offset */
42 struct pci_bus *bus; /* PCI bus */ 42 struct pci_bus *bus; /* PCI bus */
43 struct resource *resource[3]; /* Primary PCI bus resources */ 43 struct list_head resources; /* root bus resources (apertures) */
44 /* Bridge swizzling */ 44 /* Bridge swizzling */
45 u8 (*swizzle)(struct pci_dev *, u8 *); 45 u8 (*swizzle)(struct pci_dev *, u8 *);
46 /* IRQ mapping */ 46 /* IRQ mapping */
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index 2b1f245db0c6..da337ba57ffd 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -31,18 +31,6 @@ static inline int pci_proc_domain(struct pci_bus *bus)
31} 31}
32#endif /* CONFIG_PCI_DOMAINS */ 32#endif /* CONFIG_PCI_DOMAINS */
33 33
34#ifdef CONFIG_PCI_HOST_ITE8152
35/* ITE bridge requires setting latency timer to avoid early bus access
36 termination by PIC bus mater devices
37*/
38extern void pcibios_set_master(struct pci_dev *dev);
39#else
40static inline void pcibios_set_master(struct pci_dev *dev)
41{
42 /* No special bus mastering setup handling */
43}
44#endif
45
46static inline void pcibios_penalize_isa_irq(int irq, int active) 34static inline void pcibios_penalize_isa_irq(int irq, int active)
47{ 35{
48 /* We don't do dynamic PCI IRQ allocation */ 36 /* We don't do dynamic PCI IRQ allocation */
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index b530e9116a0c..f58ba3589908 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -316,21 +316,6 @@ pdev_fixup_device_resources(struct pci_sys_data *root, struct pci_dev *dev)
316 } 316 }
317} 317}
318 318
319static void __devinit
320pbus_assign_bus_resources(struct pci_bus *bus, struct pci_sys_data *root)
321{
322 struct pci_dev *dev = bus->self;
323 int i;
324
325 if (!dev) {
326 /*
327 * Assign root bus resources.
328 */
329 for (i = 0; i < 3; i++)
330 bus->resource[i] = root->resource[i];
331 }
332}
333
334/* 319/*
335 * pcibios_fixup_bus - Called after each bus is probed, 320 * pcibios_fixup_bus - Called after each bus is probed,
336 * but before its children are examined. 321 * but before its children are examined.
@@ -341,8 +326,6 @@ void pcibios_fixup_bus(struct pci_bus *bus)
341 struct pci_dev *dev; 326 struct pci_dev *dev;
342 u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK; 327 u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
343 328
344 pbus_assign_bus_resources(bus, root);
345
346 /* 329 /*
347 * Walk the devices on this bus, working out what we can 330 * Walk the devices on this bus, working out what we can
348 * and can't support. 331 * and can't support.
@@ -508,12 +491,18 @@ static void __init pcibios_init_hw(struct hw_pci *hw)
508 sys->busnr = busnr; 491 sys->busnr = busnr;
509 sys->swizzle = hw->swizzle; 492 sys->swizzle = hw->swizzle;
510 sys->map_irq = hw->map_irq; 493 sys->map_irq = hw->map_irq;
511 sys->resource[0] = &ioport_resource; 494 INIT_LIST_HEAD(&sys->resources);
512 sys->resource[1] = &iomem_resource;
513 495
514 ret = hw->setup(nr, sys); 496 ret = hw->setup(nr, sys);
515 497
516 if (ret > 0) { 498 if (ret > 0) {
499 if (list_empty(&sys->resources)) {
500 pci_add_resource(&sys->resources,
501 &ioport_resource);
502 pci_add_resource(&sys->resources,
503 &iomem_resource);
504 }
505
517 sys->bus = hw->scan(nr, sys); 506 sys->bus = hw->scan(nr, sys);
518 507
519 if (!sys->bus) 508 if (!sys->bus)
@@ -571,6 +560,13 @@ void __init pci_common_init(struct hw_pci *hw)
571 } 560 }
572} 561}
573 562
563#ifndef CONFIG_PCI_HOST_ITE8152
564void pcibios_set_master(struct pci_dev *dev)
565{
566 /* No special bus mastering setup handling */
567}
568#endif
569
574char * __init pcibios_setup(char *str) 570char * __init pcibios_setup(char *str)
575{ 571{
576 if (!strcmp(str, "debug")) { 572 if (!strcmp(str, "debug")) {
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index 0f8fca48a5ed..e159d69967c9 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -151,13 +151,12 @@ static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
151 struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys); 151 struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
152 struct resource *res_io = &cnspci->res_io; 152 struct resource *res_io = &cnspci->res_io;
153 struct resource *res_mem = &cnspci->res_mem; 153 struct resource *res_mem = &cnspci->res_mem;
154 struct resource **sysres = sys->resource;
155 154
156 BUG_ON(request_resource(&iomem_resource, res_io) || 155 BUG_ON(request_resource(&iomem_resource, res_io) ||
157 request_resource(&iomem_resource, res_mem)); 156 request_resource(&iomem_resource, res_mem));
158 157
159 sysres[0] = res_io; 158 pci_add_resource(&sys->resources, res_io);
160 sysres[1] = res_mem; 159 pci_add_resource(&sys->resources, res_mem);
161 160
162 return 1; 161 return 1;
163} 162}
@@ -169,7 +168,8 @@ static struct pci_ops cns3xxx_pcie_ops = {
169 168
170static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys) 169static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys)
171{ 170{
172 return pci_scan_bus(sys->busnr, &cns3xxx_pcie_ops, sys); 171 return pci_scan_root_bus(NULL, sys->busnr, &cns3xxx_pcie_ops, sys,
172 &sys->resources);
173} 173}
174 174
175static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 175static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index 6c11a4df7178..52e96d397ba8 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -69,7 +69,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
69 pp->res[0].flags = IORESOURCE_IO; 69 pp->res[0].flags = IORESOURCE_IO;
70 if (request_resource(&ioport_resource, &pp->res[0])) 70 if (request_resource(&ioport_resource, &pp->res[0]))
71 panic("Request PCIe IO resource failed\n"); 71 panic("Request PCIe IO resource failed\n");
72 sys->resource[0] = &pp->res[0]; 72 pci_add_resource(&sys->resources, &pp->res[0]);
73 73
74 /* 74 /*
75 * IORESOURCE_MEM 75 * IORESOURCE_MEM
@@ -88,9 +88,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
88 pp->res[1].flags = IORESOURCE_MEM; 88 pp->res[1].flags = IORESOURCE_MEM;
89 if (request_resource(&iomem_resource, &pp->res[1])) 89 if (request_resource(&iomem_resource, &pp->res[1]))
90 panic("Request PCIe Memory resource failed\n"); 90 panic("Request PCIe Memory resource failed\n");
91 sys->resource[1] = &pp->res[1]; 91 pci_add_resource(&sys->resources, &pp->res[1]);
92
93 sys->resource[2] = NULL;
94 92
95 return 1; 93 return 1;
96} 94}
@@ -184,7 +182,8 @@ dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
184 struct pci_bus *bus; 182 struct pci_bus *bus;
185 183
186 if (nr < num_pcie_ports) { 184 if (nr < num_pcie_ports) {
187 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); 185 bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
186 &sys->resources);
188 } else { 187 } else {
189 bus = NULL; 188 bus = NULL;
190 BUG(); 189 BUG();
diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h
new file mode 100644
index 000000000000..3df27f2d5034
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/cpufreq.h
@@ -0,0 +1,34 @@
1/* linux/arch/arm/mach-exynos/include/mach/cpufreq.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS - CPUFreq support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13enum cpufreq_level_index {
14 L0, L1, L2, L3, L4,
15 L5, L6, L7, L8, L9,
16 L10, L11, L12, L13, L14,
17 L15, L16, L17, L18, L19,
18 L20,
19};
20
21struct exynos_dvfs_info {
22 unsigned long mpll_freq_khz;
23 unsigned int pll_safe_idx;
24 unsigned int pm_lock_idx;
25 unsigned int max_support_idx;
26 unsigned int min_support_idx;
27 struct clk *cpu_clk;
28 unsigned int *volt_table;
29 struct cpufreq_frequency_table *freq_table;
30 void (*set_freq)(unsigned int, unsigned int);
31 bool (*need_apll_change)(unsigned int, unsigned int);
32};
33
34extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 18c32a5541d9..f685650c25d7 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -275,9 +275,9 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
275 allocate_resource(&iomem_resource, &res[0], 0x40000000, 275 allocate_resource(&iomem_resource, &res[0], 0x40000000,
276 0x80000000, 0xffffffff, 0x40000000, NULL, NULL); 276 0x80000000, 0xffffffff, 0x40000000, NULL, NULL);
277 277
278 sys->resource[0] = &ioport_resource; 278 pci_add_resource(&sys->resources, &ioport_resource);
279 sys->resource[1] = &res[0]; 279 pci_add_resource(&sys->resources, &res[0]);
280 sys->resource[2] = &res[1]; 280 pci_add_resource(&sys->resources, &res[1]);
281 sys->mem_offset = DC21285_PCI_MEM; 281 sys->mem_offset = DC21285_PCI_MEM;
282 282
283 return 1; 283 return 1;
@@ -285,7 +285,7 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
285 285
286struct pci_bus * __init dc21285_scan_bus(int nr, struct pci_sys_data *sys) 286struct pci_bus * __init dc21285_scan_bus(int nr, struct pci_sys_data *sys)
287{ 287{
288 return pci_scan_bus(0, &dc21285_ops, sys); 288 return pci_scan_root_bus(NULL, 0, &dc21285_ops, sys, &sys->resources);
289} 289}
290 290
291#define dc21285_request_irq(_a, _b, _c, _d, _e) \ 291#define dc21285_request_irq(_a, _b, _c, _d, _e) \
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index b4d8f8b8a085..3c82566acece 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -359,7 +359,7 @@ static struct resource pre_mem = {
359 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, 359 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
360}; 360};
361 361
362static int __init pci_v3_setup_resources(struct resource **resource) 362static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
363{ 363{
364 if (request_resource(&iomem_resource, &non_mem)) { 364 if (request_resource(&iomem_resource, &non_mem)) {
365 printk(KERN_ERR "PCI: unable to allocate non-prefetchable " 365 printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
@@ -374,13 +374,13 @@ static int __init pci_v3_setup_resources(struct resource **resource)
374 } 374 }
375 375
376 /* 376 /*
377 * bus->resource[0] is the IO resource for this bus 377 * the IO resource for this bus
378 * bus->resource[1] is the mem resource for this bus 378 * the mem resource for this bus
379 * bus->resource[2] is the prefetch mem resource for this bus 379 * the prefetch mem resource for this bus
380 */ 380 */
381 resource[0] = &ioport_resource; 381 pci_add_resource(&sys->resources, &ioport_resource);
382 resource[1] = &non_mem; 382 pci_add_resource(&sys->resources, &non_mem);
383 resource[2] = &pre_mem; 383 pci_add_resource(&sys->resources, &pre_mem);
384 384
385 return 1; 385 return 1;
386} 386}
@@ -481,7 +481,7 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
481 481
482 if (nr == 0) { 482 if (nr == 0) {
483 sys->mem_offset = PHYS_PCI_MEM_BASE; 483 sys->mem_offset = PHYS_PCI_MEM_BASE;
484 ret = pci_v3_setup_resources(sys->resource); 484 ret = pci_v3_setup_resources(sys);
485 } 485 }
486 486
487 return ret; 487 return ret;
@@ -489,7 +489,8 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
489 489
490struct pci_bus * __init pci_v3_scan_bus(int nr, struct pci_sys_data *sys) 490struct pci_bus * __init pci_v3_scan_bus(int nr, struct pci_sys_data *sys)
491{ 491{
492 return pci_scan_bus(sys->busnr, &pci_v3_ops, sys); 492 return pci_scan_root_bus(NULL, sys->busnr, &pci_v3_ops, sys,
493 &sys->resources);
493} 494}
494 495
495/* 496/*
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index db012fadf88c..b8f5a8736511 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -537,14 +537,14 @@ struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys)
537 while(time_before(jiffies, atux_trhfa_timeout)) 537 while(time_before(jiffies, atux_trhfa_timeout))
538 udelay(100); 538 udelay(100);
539 539
540 bus = pci_bus_atux = pci_scan_bus(sys->busnr, 540 bus = pci_bus_atux = pci_scan_root_bus(NULL, sys->busnr,
541 &iop13xx_atux_ops, 541 &iop13xx_atux_ops,
542 sys); 542 sys, &sys->resources);
543 break; 543 break;
544 case IOP13XX_INIT_ATU_ATUE: 544 case IOP13XX_INIT_ATU_ATUE:
545 bus = pci_bus_atue = pci_scan_bus(sys->busnr, 545 bus = pci_bus_atue = pci_scan_root_bus(NULL, sys->busnr,
546 &iop13xx_atue_ops, 546 &iop13xx_atue_ops,
547 sys); 547 sys, &sys->resources);
548 break; 548 break;
549 } 549 }
550 550
@@ -1084,9 +1084,8 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
1084 request_resource(&ioport_resource, &res[0]); 1084 request_resource(&ioport_resource, &res[0]);
1085 request_resource(&iomem_resource, &res[1]); 1085 request_resource(&iomem_resource, &res[1]);
1086 1086
1087 sys->resource[0] = &res[0]; 1087 pci_add_resource(&sys->resources, &res[0]);
1088 sys->resource[1] = &res[1]; 1088 pci_add_resource(&sys->resources, &res[1]);
1089 sys->resource[2] = NULL;
1090 1089
1091 return 1; 1090 return 1;
1092} 1091}
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
index ee525416f0d2..e872d238cd0f 100644
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ b/arch/arm/mach-ixp2000/enp2611.c
@@ -145,7 +145,8 @@ static struct pci_ops enp2611_pci_ops = {
145static struct pci_bus * __init enp2611_pci_scan_bus(int nr, 145static struct pci_bus * __init enp2611_pci_scan_bus(int nr,
146 struct pci_sys_data *sys) 146 struct pci_sys_data *sys)
147{ 147{
148 return pci_scan_bus(sys->busnr, &enp2611_pci_ops, sys); 148 return pci_scan_root_bus(NULL, sys->busnr, &enp2611_pci_ops, sys,
149 &sys->resources);
149} 150}
150 151
151static int __init enp2611_pci_map_irq(const struct pci_dev *dev, u8 slot, 152static int __init enp2611_pci_map_irq(const struct pci_dev *dev, u8 slot,
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index f5098b306fd3..626fda435aa9 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -132,7 +132,8 @@ static struct pci_ops ixp2000_pci_ops = {
132 132
133struct pci_bus *ixp2000_pci_scan_bus(int nr, struct pci_sys_data *sysdata) 133struct pci_bus *ixp2000_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
134{ 134{
135 return pci_scan_bus(sysdata->busnr, &ixp2000_pci_ops, sysdata); 135 return pci_scan_root_bus(NULL, sysdata->busnr, &ixp2000_pci_ops,
136 sysdata, &sysdata->resources);
136} 137}
137 138
138 139
@@ -242,9 +243,8 @@ int ixp2000_pci_setup(int nr, struct pci_sys_data *sys)
242 if (nr >= 1) 243 if (nr >= 1)
243 return 0; 244 return 0;
244 245
245 sys->resource[0] = &ixp2000_pci_io_space; 246 pci_add_resource(&sys->resources, &ixp2000_pci_io_space);
246 sys->resource[1] = &ixp2000_pci_mem_space; 247 pci_add_resource(&sys->resources, &ixp2000_pci_mem_space);
247 sys->resource[2] = NULL;
248 248
249 return 1; 249 return 1;
250} 250}
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
index e6be5711c700..25b5c462cea2 100644
--- a/arch/arm/mach-ixp23xx/pci.c
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -143,7 +143,8 @@ struct pci_ops ixp23xx_pci_ops = {
143 143
144struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata) 144struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
145{ 145{
146 return pci_scan_bus(sysdata->busnr, &ixp23xx_pci_ops, sysdata); 146 return pci_scan_root_bus(NULL, sysdata->busnr, &ixp23xx_pci_ops,
147 sysdata, &sysdata->resources);
147} 148}
148 149
149int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) 150int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
@@ -280,9 +281,8 @@ int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys)
280 if (nr >= 1) 281 if (nr >= 1)
281 return 0; 282 return 0;
282 283
283 sys->resource[0] = &ixp23xx_pci_io_space; 284 pci_add_resource(&sys->resources, &ixp23xx_pci_io_space);
284 sys->resource[1] = &ixp23xx_pci_mem_space; 285 pci_add_resource(&sys->resources, &ixp23xx_pci_mem_space);
285 sys->resource[2] = NULL;
286 286
287 return 1; 287 return 1;
288} 288}
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 8325058ef871..5eff15f24bc2 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -472,9 +472,8 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
472 request_resource(&ioport_resource, &res[0]); 472 request_resource(&ioport_resource, &res[0]);
473 request_resource(&iomem_resource, &res[1]); 473 request_resource(&iomem_resource, &res[1]);
474 474
475 sys->resource[0] = &res[0]; 475 pci_add_resource(&sys->resources, &res[0]);
476 sys->resource[1] = &res[1]; 476 pci_add_resource(&sys->resources, &res[1]);
477 sys->resource[2] = NULL;
478 477
479 platform_notify = ixp4xx_pci_platform_notify; 478 platform_notify = ixp4xx_pci_platform_notify;
480 platform_notify_remove = ixp4xx_pci_platform_notify_remove; 479 platform_notify_remove = ixp4xx_pci_platform_notify_remove;
@@ -484,7 +483,8 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
484 483
485struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys) 484struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
486{ 485{
487 return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys); 486 return pci_scan_root_bus(NULL, sys->busnr, &ixp4xx_ops, sys,
487 &sys->resources);
488} 488}
489 489
490int dma_set_coherent_mask(struct device *dev, u64 mask) 490int dma_set_coherent_mask(struct device *dev, u64 mask)
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index fb451bfe478b..a066a6d8d9d2 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -198,9 +198,8 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
198 if (request_resource(&iomem_resource, &pp->res[1])) 198 if (request_resource(&iomem_resource, &pp->res[1]))
199 panic("Request PCIe%d Memory resource failed\n", index); 199 panic("Request PCIe%d Memory resource failed\n", index);
200 200
201 sys->resource[0] = &pp->res[0]; 201 pci_add_resource(&sys->resources, &pp->res[0]);
202 sys->resource[1] = &pp->res[1]; 202 pci_add_resource(&sys->resources, &pp->res[1]);
203 sys->resource[2] = NULL;
204 sys->io_offset = 0; 203 sys->io_offset = 0;
205 204
206 /* 205 /*
@@ -236,7 +235,8 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
236 struct pci_bus *bus; 235 struct pci_bus *bus;
237 236
238 if (nr < num_pcie_ports) { 237 if (nr < num_pcie_ports) {
239 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); 238 bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
239 &sys->resources);
240 } else { 240 } else {
241 bus = NULL; 241 bus = NULL;
242 BUG(); 242 BUG();
diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c
index c7c9a188d105..b26f992071df 100644
--- a/arch/arm/mach-ks8695/pci.c
+++ b/arch/arm/mach-ks8695/pci.c
@@ -143,7 +143,8 @@ static struct pci_ops ks8695_pci_ops = {
143 143
144static struct pci_bus* __init ks8695_pci_scan_bus(int nr, struct pci_sys_data *sys) 144static struct pci_bus* __init ks8695_pci_scan_bus(int nr, struct pci_sys_data *sys)
145{ 145{
146 return pci_scan_bus(sys->busnr, &ks8695_pci_ops, sys); 146 return pci_scan_root_bus(NULL, sys->busnr, &ks8695_pci_ops, sys,
147 &sys->resources);
147} 148}
148 149
149static struct resource pci_mem = { 150static struct resource pci_mem = {
@@ -168,9 +169,8 @@ static int __init ks8695_pci_setup(int nr, struct pci_sys_data *sys)
168 request_resource(&iomem_resource, &pci_mem); 169 request_resource(&iomem_resource, &pci_mem);
169 request_resource(&ioport_resource, &pci_io); 170 request_resource(&ioport_resource, &pci_io);
170 171
171 sys->resource[0] = &pci_io; 172 pci_add_resource(&sys->resources, &pci_io);
172 sys->resource[1] = &pci_mem; 173 pci_add_resource(&sys->resources, &pci_mem);
173 sys->resource[2] = NULL;
174 174
175 /* Assign and enable processor bridge */ 175 /* Assign and enable processor bridge */
176 ks8695_local_writeconfig(PCI_BASE_ADDRESS_0, KS8695_PCIMEM_PA); 176 ks8695_local_writeconfig(PCI_BASE_ADDRESS_0, KS8695_PCIMEM_PA);
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index 12fcb108b0e1..8459f6d7d8ca 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -155,9 +155,8 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
155 orion_pcie_set_local_bus_nr(pp->base, sys->busnr); 155 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
156 orion_pcie_setup(pp->base); 156 orion_pcie_setup(pp->base);
157 157
158 sys->resource[0] = &pp->res[0]; 158 pci_add_resource(&sys->resources, &pp->res[0]);
159 sys->resource[1] = &pp->res[1]; 159 pci_add_resource(&sys->resources, &pp->res[1]);
160 sys->resource[2] = NULL;
161 160
162 return 1; 161 return 1;
163} 162}
@@ -251,7 +250,8 @@ mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys)
251 struct pci_bus *bus; 250 struct pci_bus *bus;
252 251
253 if (nr < num_pcie_ports) { 252 if (nr < num_pcie_ports) {
254 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); 253 bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
254 &sys->resources);
255 } else { 255 } else {
256 bus = NULL; 256 bus = NULL;
257 BUG(); 257 BUG();
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index d67bcdf724d7..acb4e77b39ef 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -945,6 +945,9 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = {
945 }, 945 },
946#endif 946#endif
947 { 947 {
948 I2C_BOARD_INFO("bq27200", 0x55),
949 },
950 {
948 I2C_BOARD_INFO("tpa6130a2", 0x60), 951 I2C_BOARD_INFO("tpa6130a2", 0x60),
949 .platform_data = &rx51_tpa6130a2_data, 952 .platform_data = &rx51_tpa6130a2_data,
950 } 953 }
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 28fcb27005d2..fb4bcf81a183 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -156,6 +156,9 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
156 else 156 else
157 /* The FIFO has 128 locations */ 157 /* The FIFO has 128 locations */
158 pdata->buffer_size = 0x80; 158 pdata->buffer_size = 0x80;
159 } else if (oh->class->rev == MCBSP_CONFIG_TYPE4) {
160 /* The FIFO has 128 locations for all instances */
161 pdata->buffer_size = 0x80;
159 } 162 }
160 163
161 if (oh->class->rev >= MCBSP_CONFIG_TYPE3) 164 if (oh->class->rev >= MCBSP_CONFIG_TYPE3)
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index a494c470e3e4..09a045f0c406 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -177,7 +177,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
177 res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1; 177 res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
178 if (request_resource(&ioport_resource, &res[0])) 178 if (request_resource(&ioport_resource, &res[0]))
179 panic("Request PCIe IO resource failed\n"); 179 panic("Request PCIe IO resource failed\n");
180 sys->resource[0] = &res[0]; 180 pci_add_resource(&sys->resources, &res[0]);
181 181
182 /* 182 /*
183 * IORESOURCE_MEM 183 * IORESOURCE_MEM
@@ -188,9 +188,8 @@ static int __init pcie_setup(struct pci_sys_data *sys)
188 res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1; 188 res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
189 if (request_resource(&iomem_resource, &res[1])) 189 if (request_resource(&iomem_resource, &res[1]))
190 panic("Request PCIe Memory resource failed\n"); 190 panic("Request PCIe Memory resource failed\n");
191 sys->resource[1] = &res[1]; 191 pci_add_resource(&sys->resources, &res[1]);
192 192
193 sys->resource[2] = NULL;
194 sys->io_offset = 0; 193 sys->io_offset = 0;
195 194
196 return 1; 195 return 1;
@@ -506,7 +505,7 @@ static int __init pci_setup(struct pci_sys_data *sys)
506 res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1; 505 res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
507 if (request_resource(&ioport_resource, &res[0])) 506 if (request_resource(&ioport_resource, &res[0]))
508 panic("Request PCI IO resource failed\n"); 507 panic("Request PCI IO resource failed\n");
509 sys->resource[0] = &res[0]; 508 pci_add_resource(&sys->resources, &res[0]);
510 509
511 /* 510 /*
512 * IORESOURCE_MEM 511 * IORESOURCE_MEM
@@ -517,9 +516,8 @@ static int __init pci_setup(struct pci_sys_data *sys)
517 res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1; 516 res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
518 if (request_resource(&iomem_resource, &res[1])) 517 if (request_resource(&iomem_resource, &res[1]))
519 panic("Request PCI Memory resource failed\n"); 518 panic("Request PCI Memory resource failed\n");
520 sys->resource[1] = &res[1]; 519 pci_add_resource(&sys->resources, &res[1]);
521 520
522 sys->resource[2] = NULL;
523 sys->io_offset = 0; 521 sys->io_offset = 0;
524 522
525 return 1; 523 return 1;
@@ -580,9 +578,11 @@ struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys
580 struct pci_bus *bus; 578 struct pci_bus *bus;
581 579
582 if (nr == 0) { 580 if (nr == 0) {
583 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); 581 bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
582 &sys->resources);
584 } else if (nr == 1 && !orion5x_pci_disabled) { 583 } else if (nr == 1 && !orion5x_pci_disabled) {
585 bus = pci_scan_bus(sys->busnr, &pci_ops, sys); 584 bus = pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys,
585 &sys->resources);
586 } else { 586 } else {
587 bus = NULL; 587 bus = NULL;
588 BUG(); 588 BUG();
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 66600f05e436..11f1e735966e 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -436,6 +436,14 @@ static struct platform_device corgiled_device = {
436}; 436};
437 437
438/* 438/*
439 * Corgi Audio
440 */
441static struct platform_device corgi_audio_device = {
442 .name = "corgi-audio",
443 .id = -1,
444};
445
446/*
439 * MMC/SD Device 447 * MMC/SD Device
440 * 448 *
441 * The card detect interrupt isn't debounced so we delay it by 250ms 449 * The card detect interrupt isn't debounced so we delay it by 250ms
@@ -641,6 +649,7 @@ static struct platform_device *devices[] __initdata = {
641 &corgifb_device, 649 &corgifb_device,
642 &corgikbd_device, 650 &corgikbd_device,
643 &corgiled_device, 651 &corgiled_device,
652 &corgi_audio_device,
644 &sharpsl_nand_device, 653 &sharpsl_nand_device,
645 &sharpsl_rom_device, 654 &sharpsl_rom_device,
646}; 655};
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index f79a610c62fc..4cb2391a782e 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -528,12 +528,18 @@ static struct platform_device e740_t7l66xb_device = {
528 .resource = eseries_tmio_resources, 528 .resource = eseries_tmio_resources,
529}; 529};
530 530
531static struct platform_device e740_audio_device = {
532 .name = "e740-audio",
533 .id = -1,
534};
535
531/* ----------------------------------------------------------------------- */ 536/* ----------------------------------------------------------------------- */
532 537
533static struct platform_device *e740_devices[] __initdata = { 538static struct platform_device *e740_devices[] __initdata = {
534 &e740_fb_device, 539 &e740_fb_device,
535 &e740_t7l66xb_device, 540 &e740_t7l66xb_device,
536 &e7xx_gpio_vbus, 541 &e7xx_gpio_vbus,
542 &e740_audio_device,
537}; 543};
538 544
539static void __init e740_init(void) 545static void __init e740_init(void)
@@ -722,12 +728,18 @@ static struct platform_device e750_tc6393xb_device = {
722 .resource = eseries_tmio_resources, 728 .resource = eseries_tmio_resources,
723}; 729};
724 730
731static struct platform_device e750_audio_device = {
732 .name = "e750-audio",
733 .id = -1,
734};
735
725/* ------------------------------------------------------------- */ 736/* ------------------------------------------------------------- */
726 737
727static struct platform_device *e750_devices[] __initdata = { 738static struct platform_device *e750_devices[] __initdata = {
728 &e750_fb_device, 739 &e750_fb_device,
729 &e750_tc6393xb_device, 740 &e750_tc6393xb_device,
730 &e7xx_gpio_vbus, 741 &e7xx_gpio_vbus,
742 &e750_audio_device,
731}; 743};
732 744
733static void __init e750_init(void) 745static void __init e750_init(void)
@@ -929,12 +941,18 @@ static struct platform_device e800_tc6393xb_device = {
929 .resource = eseries_tmio_resources, 941 .resource = eseries_tmio_resources,
930}; 942};
931 943
944static struct platform_device e800_audio_device = {
945 .name = "e800-audio",
946 .id = -1,
947};
948
932/* ----------------------------------------------------------------------- */ 949/* ----------------------------------------------------------------------- */
933 950
934static struct platform_device *e800_devices[] __initdata = { 951static struct platform_device *e800_devices[] __initdata = {
935 &e800_fb_device, 952 &e800_fb_device,
936 &e800_tc6393xb_device, 953 &e800_tc6393xb_device,
937 &e800_gpio_vbus, 954 &e800_gpio_vbus,
955 &e800_audio_device,
938}; 956};
939 957
940static void __init e800_init(void) 958static void __init e800_init(void)
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 69036e42ca31..744baee12c0c 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -158,6 +158,11 @@ static struct scoop_pcmcia_config poodle_pcmcia_config = {
158EXPORT_SYMBOL(poodle_scoop_device); 158EXPORT_SYMBOL(poodle_scoop_device);
159 159
160 160
161static struct platform_device poodle_audio_device = {
162 .name = "poodle-audio",
163 .id = -1,
164};
165
161/* LoCoMo device */ 166/* LoCoMo device */
162static struct resource locomo_resources[] = { 167static struct resource locomo_resources[] = {
163 [0] = { 168 [0] = {
@@ -407,6 +412,7 @@ static struct platform_device sharpsl_rom_device = {
407static struct platform_device *devices[] __initdata = { 412static struct platform_device *devices[] __initdata = {
408 &poodle_locomo_device, 413 &poodle_locomo_device,
409 &poodle_scoop_device, 414 &poodle_scoop_device,
415 &poodle_audio_device,
410 &sharpsl_nand_device, 416 &sharpsl_nand_device,
411 &sharpsl_rom_device, 417 &sharpsl_rom_device,
412}; 418};
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index d8a2467de92e..b0656e158d90 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -593,10 +593,16 @@ static struct pxa2xx_udc_mach_info imote2_udc_info __initdata = {
593 .udc_command = sg2_udc_command, 593 .udc_command = sg2_udc_command,
594}; 594};
595 595
596static struct platform_device imote2_audio_device = {
597 .name = "imote2-audio",
598 .id = -1,
599};
600
596static struct platform_device *imote2_devices[] = { 601static struct platform_device *imote2_devices[] = {
597 &stargate2_flash_device, 602 &stargate2_flash_device,
598 &imote2_leds, 603 &imote2_leds,
599 &sht15, 604 &sht15,
605 &imote2_audio_device,
600}; 606};
601 607
602static void __init imote2_init(void) 608static void __init imote2_init(void)
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 7ce5c436cc4e..4d4eb60bad1e 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -889,6 +889,11 @@ static struct platform_device wm9712_device = {
889 .id = -1, 889 .id = -1,
890}; 890};
891 891
892static struct platform_device tosa_audio_device = {
893 .name = "tosa-audio",
894 .id = -1,
895};
896
892static struct platform_device *devices[] __initdata = { 897static struct platform_device *devices[] __initdata = {
893 &tosascoop_device, 898 &tosascoop_device,
894 &tosascoop_jc_device, 899 &tosascoop_jc_device,
@@ -901,6 +906,7 @@ static struct platform_device *devices[] __initdata = {
901 &sharpsl_rom_device, 906 &sharpsl_rom_device,
902 &wm9712_device, 907 &wm9712_device,
903 &tosa_gpio_vbus, 908 &tosa_gpio_vbus,
909 &tosa_audio_device,
904}; 910};
905 911
906static void tosa_poweroff(void) 912static void tosa_poweroff(void)
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 680fd758ff2d..1cc91d794c97 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -286,8 +286,8 @@ static struct platform_device lowland_device = {
286 .id = -1, 286 .id = -1,
287}; 287};
288 288
289static struct platform_device speyside_wm8962_device = { 289static struct platform_device tobermory_device = {
290 .name = "speyside-wm8962", 290 .name = "tobermory",
291 .id = -1, 291 .id = -1,
292}; 292};
293 293
@@ -347,7 +347,7 @@ static struct platform_device *crag6410_devices[] __initdata = {
347 &crag6410_lcd_powerdev, 347 &crag6410_lcd_powerdev,
348 &crag6410_backlight_device, 348 &crag6410_backlight_device,
349 &speyside_device, 349 &speyside_device,
350 &speyside_wm8962_device, 350 &tobermory_device,
351 &littlemill_device, 351 &littlemill_device,
352 &lowland_device, 352 &lowland_device,
353 &wallvdd_device, 353 &wallvdd_device,
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c
index dd39fee59549..0d01ca788922 100644
--- a/arch/arm/mach-sa1100/pci-nanoengine.c
+++ b/arch/arm/mach-sa1100/pci-nanoengine.c
@@ -131,7 +131,8 @@ static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot,
131 131
132struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys) 132struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys)
133{ 133{
134 return pci_scan_bus(sys->busnr, &pci_nano_ops, sys); 134 return pci_scan_root_bus(NULL, sys->busnr, &pci_nano_ops, sys,
135 &sys->resources);
135} 136}
136 137
137static struct resource pci_io_ports = { 138static struct resource pci_io_ports = {
@@ -226,7 +227,7 @@ static struct resource pci_prefetchable_memory = {
226 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, 227 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
227}; 228};
228 229
229static int __init pci_nanoengine_setup_resources(struct resource **resource) 230static int __init pci_nanoengine_setup_resources(struct pci_sys_data *sys)
230{ 231{
231 if (request_resource(&ioport_resource, &pci_io_ports)) { 232 if (request_resource(&ioport_resource, &pci_io_ports)) {
232 printk(KERN_ERR "PCI: unable to allocate io port region\n"); 233 printk(KERN_ERR "PCI: unable to allocate io port region\n");
@@ -243,9 +244,9 @@ static int __init pci_nanoengine_setup_resources(struct resource **resource)
243 printk(KERN_ERR "PCI: unable to allocate prefetchable\n"); 244 printk(KERN_ERR "PCI: unable to allocate prefetchable\n");
244 return -EBUSY; 245 return -EBUSY;
245 } 246 }
246 resource[0] = &pci_io_ports; 247 pci_add_resource(&sys->resources, &pci_io_ports);
247 resource[1] = &pci_non_prefetchable_memory; 248 pci_add_resource(&sys->resources, &pci_non_prefetchable_memory);
248 resource[2] = &pci_prefetchable_memory; 249 pci_add_resource(&sys->resources, &pci_prefetchable_memory);
249 250
250 return 1; 251 return 1;
251} 252}
@@ -260,7 +261,7 @@ int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys)
260 if (nr == 0) { 261 if (nr == 0) {
261 sys->mem_offset = NANO_PCI_MEM_RW_PHYS; 262 sys->mem_offset = NANO_PCI_MEM_RW_PHYS;
262 sys->io_offset = 0x400; 263 sys->io_offset = 0x400;
263 ret = pci_nanoengine_setup_resources(sys->resource); 264 ret = pci_nanoengine_setup_resources(sys);
264 /* Enable alternate memory bus master mode, see 265 /* Enable alternate memory bus master mode, see
265 * "Intel StrongARM SA1110 Developer's Manual", 266 * "Intel StrongARM SA1110 Developer's Manual",
266 * section 10.8, "Alternate Memory Bus Master Mode". */ 267 * section 10.8, "Alternate Memory Bus Master Mode". */
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 0828fab2b65c..060e5644c49c 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -28,6 +28,19 @@ config ARCH_SH73A0
28 select ARM_GIC 28 select ARM_GIC
29 select I2C 29 select I2C
30 30
31config ARCH_R8A7740
32 bool "R-Mobile A1 (R8A77400)"
33 select CPU_V7
34 select SH_CLK_CPG
35 select ARCH_WANT_OPTIONAL_GPIOLIB
36
37config ARCH_R8A7779
38 bool "R-Car H1 (R8A77790)"
39 select CPU_V7
40 select SH_CLK_CPG
41 select ARM_GIC
42 select ARCH_WANT_OPTIONAL_GPIOLIB
43
31comment "SH-Mobile Board Type" 44comment "SH-Mobile Board Type"
32 45
33config MACH_G3EVM 46config MACH_G3EVM
@@ -75,6 +88,16 @@ config MACH_KOTA2
75 select ARCH_REQUIRE_GPIOLIB 88 select ARCH_REQUIRE_GPIOLIB
76 depends on ARCH_SH73A0 89 depends on ARCH_SH73A0
77 90
91config MACH_BONITO
92 bool "bonito board"
93 select ARCH_REQUIRE_GPIOLIB
94 depends on ARCH_R8A7740
95
96config MACH_MARZEN
97 bool "MARZEN board"
98 depends on ARCH_R8A7779
99 select ARCH_REQUIRE_GPIOLIB
100
78comment "SH-Mobile System Configuration" 101comment "SH-Mobile System Configuration"
79 102
80menu "Memory configuration" 103menu "Memory configuration"
@@ -83,7 +106,7 @@ config MEMORY_START
83 hex "Physical memory start address" 106 hex "Physical memory start address"
84 default "0x50000000" if MACH_G3EVM 107 default "0x50000000" if MACH_G3EVM
85 default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \ 108 default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \
86 MACH_MACKEREL 109 MACH_MACKEREL || MACH_BONITO
87 default "0x41000000" if MACH_KOTA2 110 default "0x41000000" if MACH_KOTA2
88 default "0x00000000" 111 default "0x00000000"
89 ---help--- 112 ---help---
@@ -95,7 +118,7 @@ config MEMORY_SIZE
95 hex "Physical memory size" 118 hex "Physical memory size"
96 default "0x08000000" if MACH_G3EVM 119 default "0x08000000" if MACH_G3EVM
97 default "0x08000000" if MACH_G4EVM 120 default "0x08000000" if MACH_G4EVM
98 default "0x20000000" if MACH_AG5EVM 121 default "0x20000000" if MACH_AG5EVM || MACH_BONITO
99 default "0x1e000000" if MACH_KOTA2 122 default "0x1e000000" if MACH_KOTA2
100 default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL 123 default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL
101 default "0x04000000" 124 default "0x04000000"
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 5ca1f9d66995..7ad6954c46cd 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -10,12 +10,15 @@ obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o
10obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o 10obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o
11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o 11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
12obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o 12obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
13obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
14obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o
13 15
14# SMP objects 16# SMP objects
15smp-y := platsmp.o headsmp.o 17smp-y := platsmp.o headsmp.o
16smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o 18smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o
17smp-$(CONFIG_LOCAL_TIMERS) += localtimer.o 19smp-$(CONFIG_LOCAL_TIMERS) += localtimer.o
18smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o 20smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o
21smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o
19 22
20# Pinmux setup 23# Pinmux setup
21pfc-y := 24pfc-y :=
@@ -23,16 +26,20 @@ pfc-$(CONFIG_ARCH_SH7367) += pfc-sh7367.o
23pfc-$(CONFIG_ARCH_SH7377) += pfc-sh7377.o 26pfc-$(CONFIG_ARCH_SH7377) += pfc-sh7377.o
24pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o 27pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o
25pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o 28pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o
29pfc-$(CONFIG_ARCH_R8A7740) += pfc-r8a7740.o
30pfc-$(CONFIG_ARCH_R8A7779) += pfc-r8a7779.o
26 31
27# IRQ objects 32# IRQ objects
28obj-$(CONFIG_ARCH_SH7367) += entry-intc.o 33obj-$(CONFIG_ARCH_SH7367) += entry-intc.o
29obj-$(CONFIG_ARCH_SH7377) += entry-intc.o 34obj-$(CONFIG_ARCH_SH7377) += entry-intc.o
30obj-$(CONFIG_ARCH_SH7372) += entry-intc.o 35obj-$(CONFIG_ARCH_SH7372) += entry-intc.o
36obj-$(CONFIG_ARCH_R8A7740) += entry-intc.o
31 37
32# PM objects 38# PM objects
33obj-$(CONFIG_SUSPEND) += suspend.o 39obj-$(CONFIG_SUSPEND) += suspend.o
34obj-$(CONFIG_CPU_IDLE) += cpuidle.o 40obj-$(CONFIG_CPU_IDLE) += cpuidle.o
35obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o 41obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o
42obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o
36 43
37# Board objects 44# Board objects
38obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o 45obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o
@@ -41,6 +48,8 @@ obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o
41obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o 48obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o
42obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o 49obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
43obj-$(CONFIG_MACH_KOTA2) += board-kota2.o 50obj-$(CONFIG_MACH_KOTA2) += board-kota2.o
51obj-$(CONFIG_MACH_BONITO) += board-bonito.o
52obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
44 53
45# Framework support 54# Framework support
46obj-$(CONFIG_SMP) += $(smp-y) 55obj-$(CONFIG_SMP) += $(smp-y)
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 6a6f9f7568c2..d2e7b73aa9b6 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -762,9 +762,22 @@ static struct platform_device fsi_device = {
762 }, 762 },
763}; 763};
764 764
765static struct fsi_ak4642_info fsi2_ak4643_info = {
766 .name = "AK4643",
767 .card = "FSI2A-AK4643",
768 .cpu_dai = "fsia-dai",
769 .codec = "ak4642-codec.0-0013",
770 .platform = "sh_fsi2",
771 .id = FSI_PORT_A,
772};
773
765static struct platform_device fsi_ak4643_device = { 774static struct platform_device fsi_ak4643_device = {
766 .name = "sh_fsi2_a_ak4643", 775 .name = "fsi-ak4642-audio",
776 .dev = {
777 .platform_data = &fsi_info,
778 },
767}; 779};
780
768static struct sh_mobile_meram_cfg hdmi_meram_cfg = { 781static struct sh_mobile_meram_cfg hdmi_meram_cfg = {
769 .icb[0] = { 782 .icb[0] = {
770 .marker_icb = 30, 783 .marker_icb = 30,
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
new file mode 100644
index 000000000000..4d2201622323
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -0,0 +1,522 @@
1/*
2 * bonito board support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 */
21
22#include <linux/kernel.h>
23#include <linux/i2c.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/platform_device.h>
28#include <linux/gpio.h>
29#include <linux/smsc911x.h>
30#include <mach/common.h>
31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/map.h>
34#include <asm/mach/time.h>
35#include <asm/hardware/cache-l2x0.h>
36#include <mach/r8a7740.h>
37#include <video/sh_mobile_lcdc.h>
38
39/*
40 * CS Address device note
41 *----------------------------------------------------------------
42 * 0 0x0000_0000 NOR Flash (64MB) SW12 : bit3 = OFF
43 * 2 0x0800_0000 ExtNOR (64MB) SW12 : bit3 = OFF
44 * 4 -
45 * 5A -
46 * 5B 0x1600_0000 SRAM (8MB)
47 * 6 0x1800_0000 FPGA (64K)
48 * 0x1801_0000 Ether (4KB)
49 * 0x1801_1000 USB (4KB)
50 */
51
52/*
53 * SW12
54 *
55 * bit1 bit2 bit3
56 *----------------------------------------------------------------------------
57 * ON NOR WriteProtect NAND WriteProtect CS0 ExtNOR / CS2 NOR
58 * OFF NOR Not WriteProtect NAND Not WriteProtect CS0 NOR / CS2 ExtNOR
59 */
60
61/*
62 * SCIFA5 (CN42)
63 *
64 * S38.3 = ON
65 * S39.6 = ON
66 * S43.1 = ON
67 */
68
69/*
70 * LCDC0 (CN3/CN4/CN7)
71 *
72 * S38.1 = OFF
73 * S38.2 = OFF
74 */
75
76/*
77 * FPGA
78 */
79#define IRQSR0 0x0020
80#define IRQSR1 0x0022
81#define IRQMR0 0x0030
82#define IRQMR1 0x0032
83#define BUSSWMR1 0x0070
84#define BUSSWMR2 0x0072
85#define BUSSWMR3 0x0074
86#define BUSSWMR4 0x0076
87
88#define LCDCR 0x10B4
89#define DEVRSTCR1 0x10D0
90#define DEVRSTCR2 0x10D2
91#define A1MDSR 0x10E0
92#define BVERR 0x1100
93
94/* FPGA IRQ */
95#define FPGA_IRQ_BASE (512)
96#define FPGA_IRQ0 (FPGA_IRQ_BASE)
97#define FPGA_IRQ1 (FPGA_IRQ_BASE + 16)
98#define FPGA_ETH_IRQ (FPGA_IRQ0 + 15)
99static u16 bonito_fpga_read(u32 offset)
100{
101 return __raw_readw(0xf0003000 + offset);
102}
103
104static void bonito_fpga_write(u32 offset, u16 val)
105{
106 __raw_writew(val, 0xf0003000 + offset);
107}
108
109static void bonito_fpga_irq_disable(struct irq_data *data)
110{
111 unsigned int irq = data->irq;
112 u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
113 int shift = irq % 16;
114
115 bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift));
116}
117
118static void bonito_fpga_irq_enable(struct irq_data *data)
119{
120 unsigned int irq = data->irq;
121 u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
122 int shift = irq % 16;
123
124 bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
125}
126
127static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
128 .name = "bonito FPGA",
129 .irq_mask = bonito_fpga_irq_disable,
130 .irq_unmask = bonito_fpga_irq_enable,
131};
132
133static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
134{
135 u32 val = bonito_fpga_read(IRQSR1) << 16 |
136 bonito_fpga_read(IRQSR0);
137 u32 mask = bonito_fpga_read(IRQMR1) << 16 |
138 bonito_fpga_read(IRQMR0);
139
140 int i;
141
142 val &= ~mask;
143
144 for (i = 0; i < 32; i++) {
145 if (!(val & (1 << i)))
146 continue;
147
148 generic_handle_irq(FPGA_IRQ_BASE + i);
149 }
150}
151
152static void bonito_fpga_init(void)
153{
154 int i;
155
156 bonito_fpga_write(IRQMR0, 0xffff); /* mask all */
157 bonito_fpga_write(IRQMR1, 0xffff); /* mask all */
158
159 /* Device reset */
160 bonito_fpga_write(DEVRSTCR1,
161 (1 << 2)); /* Eth */
162
163 /* FPGA irq require special handling */
164 for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
165 irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
166 handle_level_irq, "level");
167 set_irq_flags(i, IRQF_VALID); /* yuck */
168 }
169
170 irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);
171 irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW);
172}
173
174/*
175* PMIC settings
176*
177* FIXME
178*
179* bonito board needs some settings by pmic which use i2c access.
180* pmic settings use device_initcall() here for use it.
181*/
182static __u8 *pmic_settings = NULL;
183static __u8 pmic_do_2A[] = {
184 0x1C, 0x09,
185 0x1A, 0x80,
186 0xff, 0xff,
187};
188
189static int __init pmic_init(void)
190{
191 struct i2c_adapter *a = i2c_get_adapter(0);
192 struct i2c_msg msg;
193 __u8 buf[2];
194 int i, ret;
195
196 if (!pmic_settings)
197 return 0;
198 if (!a)
199 return 0;
200
201 msg.addr = 0x46;
202 msg.buf = buf;
203 msg.len = 2;
204 msg.flags = 0;
205
206 for (i = 0; ; i += 2) {
207 buf[0] = pmic_settings[i + 0];
208 buf[1] = pmic_settings[i + 1];
209
210 if ((0xff == buf[0]) && (0xff == buf[1]))
211 break;
212
213 ret = i2c_transfer(a, &msg, 1);
214 if (ret < 0) {
215 pr_err("i2c transfer fail\n");
216 break;
217 }
218 }
219
220 return 0;
221}
222device_initcall(pmic_init);
223
224/*
225 * LCDC0
226 */
227static const struct fb_videomode lcdc0_mode = {
228 .name = "WVGA Panel",
229 .xres = 800,
230 .yres = 480,
231 .left_margin = 88,
232 .right_margin = 40,
233 .hsync_len = 128,
234 .upper_margin = 20,
235 .lower_margin = 5,
236 .vsync_len = 5,
237 .sync = 0,
238};
239
240static struct sh_mobile_lcdc_info lcdc0_info = {
241 .clock_source = LCDC_CLK_BUS,
242 .ch[0] = {
243 .chan = LCDC_CHAN_MAINLCD,
244 .bpp = 16,
245 .interface_type = RGB24,
246 .clock_divider = 5,
247 .flags = 0,
248 .lcd_cfg = &lcdc0_mode,
249 .num_cfg = 1,
250 .lcd_size_cfg = {
251 .width = 152,
252 .height = 91,
253 },
254 },
255};
256
257static struct resource lcdc0_resources[] = {
258 [0] = {
259 .name = "LCDC0",
260 .start = 0xfe940000,
261 .end = 0xfe943fff,
262 .flags = IORESOURCE_MEM,
263 },
264 [1] = {
265 .start = intcs_evt2irq(0x0580),
266 .flags = IORESOURCE_IRQ,
267 },
268};
269
270static struct platform_device lcdc0_device = {
271 .name = "sh_mobile_lcdc_fb",
272 .id = 0,
273 .resource = lcdc0_resources,
274 .num_resources = ARRAY_SIZE(lcdc0_resources),
275 .dev = {
276 .platform_data = &lcdc0_info,
277 .coherent_dma_mask = ~0,
278 },
279};
280
281/*
282 * SMSC 9221
283 */
284static struct resource smsc_resources[] = {
285 [0] = {
286 .start = 0x18010000,
287 .end = 0x18011000 - 1,
288 .flags = IORESOURCE_MEM,
289 },
290 [1] = {
291 .start = FPGA_ETH_IRQ,
292 .flags = IORESOURCE_IRQ,
293 },
294};
295
296static struct smsc911x_platform_config smsc_platdata = {
297 .flags = SMSC911X_USE_16BIT,
298 .phy_interface = PHY_INTERFACE_MODE_MII,
299 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
300 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
301};
302
303static struct platform_device smsc_device = {
304 .name = "smsc911x",
305 .dev = {
306 .platform_data = &smsc_platdata,
307 },
308 .resource = smsc_resources,
309 .num_resources = ARRAY_SIZE(smsc_resources),
310};
311
312/*
313 * core board devices
314 */
315static struct platform_device *bonito_core_devices[] __initdata = {
316};
317
318/*
319 * base board devices
320 */
321static struct platform_device *bonito_base_devices[] __initdata = {
322 &lcdc0_device,
323 &smsc_device,
324};
325
326/*
327 * map I/O
328 */
329static struct map_desc bonito_io_desc[] __initdata = {
330 /*
331 * for CPGA/INTC/PFC
332 * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
333 */
334 {
335 .virtual = 0xe6000000,
336 .pfn = __phys_to_pfn(0xe6000000),
337 .length = 160 << 20,
338 .type = MT_DEVICE_NONSHARED
339 },
340#ifdef CONFIG_CACHE_L2X0
341 /*
342 * for l2x0_init()
343 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
344 */
345 {
346 .virtual = 0xf0002000,
347 .pfn = __phys_to_pfn(0xf0100000),
348 .length = PAGE_SIZE,
349 .type = MT_DEVICE_NONSHARED
350 },
351#endif
352 /*
353 * for FPGA (0x1800000-0x19ffffff)
354 * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
355 */
356 {
357 .virtual = 0xf0003000,
358 .pfn = __phys_to_pfn(0x18000000),
359 .length = PAGE_SIZE * 2,
360 .type = MT_DEVICE_NONSHARED
361 }
362};
363
364static void __init bonito_map_io(void)
365{
366 iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
367
368 /* setup early devices and console here as well */
369 r8a7740_add_early_devices();
370 shmobile_setup_console();
371}
372
373/*
374 * board init
375 */
376#define BIT_ON(sw, bit) (sw & (1 << bit))
377#define BIT_OFF(sw, bit) (!(sw & (1 << bit)))
378
379#define VCCQ1CR 0xE6058140
380#define VCCQ1LCDCR 0xE6058186
381
382static void __init bonito_init(void)
383{
384 u16 val;
385
386 r8a7740_pinmux_init();
387 bonito_fpga_init();
388
389 pmic_settings = pmic_do_2A;
390
391 /*
392 * core board settings
393 */
394
395#ifdef CONFIG_CACHE_L2X0
396 /* Early BRESP enable, Shared attribute override enable, 32K*8way */
397 l2x0_init(__io(0xf0002000), 0x40440000, 0x82000fff);
398#endif
399
400 r8a7740_add_standard_devices();
401
402 platform_add_devices(bonito_core_devices,
403 ARRAY_SIZE(bonito_core_devices));
404
405 /*
406 * base board settings
407 */
408 gpio_request(GPIO_PORT176, NULL);
409 gpio_direction_input(GPIO_PORT176);
410 if (!gpio_get_value(GPIO_PORT176)) {
411 u16 bsw2;
412 u16 bsw3;
413 u16 bsw4;
414
415 /*
416 * FPGA
417 */
418 gpio_request(GPIO_FN_CS5B, NULL);
419 gpio_request(GPIO_FN_CS6A, NULL);
420 gpio_request(GPIO_FN_CS5A_PORT105, NULL);
421 gpio_request(GPIO_FN_IRQ10, NULL);
422
423 val = bonito_fpga_read(BVERR);
424 pr_info("bonito version: cpu %02x, base %02x\n",
425 ((val >> 8) & 0xFF),
426 ((val >> 0) & 0xFF));
427
428 bsw2 = bonito_fpga_read(BUSSWMR2);
429 bsw3 = bonito_fpga_read(BUSSWMR3);
430 bsw4 = bonito_fpga_read(BUSSWMR4);
431
432 /*
433 * SCIFA5 (CN42)
434 */
435 if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
436 BIT_OFF(bsw3, 9) && /* S39.6 = ON */
437 BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
438 gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
439 gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
440 }
441
442 /*
443 * LCDC0 (CN3)
444 */
445 if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
446 BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
447 gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
448 gpio_request(GPIO_FN_LCD0_D0, NULL);
449 gpio_request(GPIO_FN_LCD0_D1, NULL);
450 gpio_request(GPIO_FN_LCD0_D2, NULL);
451 gpio_request(GPIO_FN_LCD0_D3, NULL);
452 gpio_request(GPIO_FN_LCD0_D4, NULL);
453 gpio_request(GPIO_FN_LCD0_D5, NULL);
454 gpio_request(GPIO_FN_LCD0_D6, NULL);
455 gpio_request(GPIO_FN_LCD0_D7, NULL);
456 gpio_request(GPIO_FN_LCD0_D8, NULL);
457 gpio_request(GPIO_FN_LCD0_D9, NULL);
458 gpio_request(GPIO_FN_LCD0_D10, NULL);
459 gpio_request(GPIO_FN_LCD0_D11, NULL);
460 gpio_request(GPIO_FN_LCD0_D12, NULL);
461 gpio_request(GPIO_FN_LCD0_D13, NULL);
462 gpio_request(GPIO_FN_LCD0_D14, NULL);
463 gpio_request(GPIO_FN_LCD0_D15, NULL);
464 gpio_request(GPIO_FN_LCD0_D16, NULL);
465 gpio_request(GPIO_FN_LCD0_D17, NULL);
466 gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL);
467 gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL);
468 gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL);
469 gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL);
470 gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL);
471 gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL);
472 gpio_request(GPIO_FN_LCD0_DCK, NULL);
473 gpio_request(GPIO_FN_LCD0_VSYN, NULL);
474 gpio_request(GPIO_FN_LCD0_HSYN, NULL);
475 gpio_request(GPIO_FN_LCD0_DISP, NULL);
476 gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
477
478 gpio_request(GPIO_PORT61, NULL); /* LCDDON */
479 gpio_direction_output(GPIO_PORT61, 1);
480
481 /* backlight on */
482 bonito_fpga_write(LCDCR, 1);
483
484 /* drivability Max */
485 __raw_writew(0x00FF , VCCQ1LCDCR);
486 __raw_writew(0xFFFF , VCCQ1CR);
487 }
488
489 platform_add_devices(bonito_base_devices,
490 ARRAY_SIZE(bonito_base_devices));
491 }
492}
493
494static void __init bonito_timer_init(void)
495{
496 u16 val;
497 u8 md_ck = 0;
498
499 /* read MD_CK value */
500 val = bonito_fpga_read(A1MDSR);
501 if (val & (1 << 10))
502 md_ck |= MD_CK2;
503 if (val & (1 << 9))
504 md_ck |= MD_CK1;
505 if (val & (1 << 8))
506 md_ck |= MD_CK0;
507
508 r8a7740_clock_init(md_ck);
509 shmobile_timer.init();
510}
511
512struct sys_timer bonito_timer = {
513 .init = bonito_timer_init,
514};
515
516MACHINE_START(BONITO, "bonito")
517 .map_io = bonito_map_io,
518 .init_irq = r8a7740_init_irq,
519 .handle_irq = shmobile_handle_irq_intc,
520 .init_machine = bonito_init,
521 .timer = &bonito_timer,
522MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index ed5256687397..cbc5934ae03f 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -990,8 +990,20 @@ static struct platform_device fsi_device = {
990 }, 990 },
991}; 991};
992 992
993static struct fsi_ak4642_info fsi2_ak4643_info = {
994 .name = "AK4643",
995 .card = "FSI2A-AK4643",
996 .cpu_dai = "fsia-dai",
997 .codec = "ak4642-codec.0-0013",
998 .platform = "sh_fsi2",
999 .id = FSI_PORT_A,
1000};
1001
993static struct platform_device fsi_ak4643_device = { 1002static struct platform_device fsi_ak4643_device = {
994 .name = "sh_fsi2_a_ak4643", 1003 .name = "fsi-ak4642-audio",
1004 .dev = {
1005 .platform_data = &fsi2_ak4643_info,
1006 },
995}; 1007};
996 1008
997/* 1009/*
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
new file mode 100644
index 000000000000..f0e02c0ce99f
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -0,0 +1,157 @@
1/*
2 * marzen board support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/platform_device.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28#include <linux/gpio.h>
29#include <linux/dma-mapping.h>
30#include <linux/smsc911x.h>
31#include <mach/hardware.h>
32#include <mach/r8a7779.h>
33#include <mach/common.h>
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37#include <asm/mach/time.h>
38#include <asm/hardware/gic.h>
39#include <asm/traps.h>
40
41/* SMSC LAN89218 */
42static struct resource smsc911x_resources[] = {
43 [0] = {
44 .start = 0x18000000, /* ExCS0 */
45 .end = 0x180000ff, /* A1->A7 */
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
49 .start = gic_spi(28), /* IRQ 1 */
50 .flags = IORESOURCE_IRQ,
51 },
52};
53
54static struct smsc911x_platform_config smsc911x_platdata = {
55 .flags = SMSC911X_USE_32BIT, /* 32-bit SW on 16-bit HW bus */
56 .phy_interface = PHY_INTERFACE_MODE_MII,
57 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
58 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
59};
60
61static struct platform_device eth_device = {
62 .name = "smsc911x",
63 .id = 0,
64 .dev = {
65 .platform_data = &smsc911x_platdata,
66 },
67 .resource = smsc911x_resources,
68 .num_resources = ARRAY_SIZE(smsc911x_resources),
69};
70
71static struct platform_device *marzen_devices[] __initdata = {
72 &eth_device,
73};
74
75static struct map_desc marzen_io_desc[] __initdata = {
76 /* 2M entity map for 0xf0000000 (MPCORE) */
77 {
78 .virtual = 0xf0000000,
79 .pfn = __phys_to_pfn(0xf0000000),
80 .length = SZ_2M,
81 .type = MT_DEVICE_NONSHARED
82 },
83 /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
84 {
85 .virtual = 0xfe000000,
86 .pfn = __phys_to_pfn(0xfe000000),
87 .length = SZ_16M,
88 .type = MT_DEVICE_NONSHARED
89 },
90};
91
92static void __init marzen_map_io(void)
93{
94 iotable_init(marzen_io_desc, ARRAY_SIZE(marzen_io_desc));
95}
96
97static void __init marzen_init_early(void)
98{
99 r8a7779_add_early_devices();
100
101 /* Early serial console setup is not included here due to
102 * memory map collisions. The SCIF serial ports in r8a7779
103 * are difficult to entity map 1:1 due to collision with the
104 * virtual memory range used by the coherent DMA code on ARM.
105 *
106 * Anyone wanting to debug early can remove UPF_IOREMAP from
107 * the sh-sci serial console platform data, adjust mapbase
108 * to a static M:N virt:phys mapping that needs to be added to
109 * the mappings passed with iotable_init() above.
110 *
111 * Then add a call to shmobile_setup_console() from this function.
112 *
113 * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
114 * command line.
115 */
116}
117
118static void __init marzen_init(void)
119{
120 r8a7779_pinmux_init();
121
122 /* SCIF2 (CN18: DEBUG0) */
123 gpio_request(GPIO_FN_TX2_C, NULL);
124 gpio_request(GPIO_FN_RX2_C, NULL);
125
126 /* SCIF4 (CN19: DEBUG1) */
127 gpio_request(GPIO_FN_TX4, NULL);
128 gpio_request(GPIO_FN_RX4, NULL);
129
130 /* LAN89218 */
131 gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
132 gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
133
134 r8a7779_add_standard_devices();
135 platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
136}
137
138static void __init marzen_timer_init(void)
139{
140 r8a7779_clock_init();
141 shmobile_timer.init();
142 return;
143}
144
145struct sys_timer marzen_timer = {
146 .init = marzen_timer_init,
147};
148
149MACHINE_START(MARZEN, "marzen")
150 .map_io = marzen_map_io,
151 .init_early = marzen_init_early,
152 .nr_irqs = NR_IRQS_LEGACY,
153 .init_irq = r8a7779_init_irq,
154 .handle_irq = gic_handle_irq,
155 .init_machine = marzen_init,
156 .timer = &marzen_timer,
157MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
new file mode 100644
index 000000000000..3b35b9afc001
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -0,0 +1,382 @@
1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/io.h>
23#include <linux/sh_clk.h>
24#include <linux/clkdev.h>
25#include <mach/common.h>
26#include <mach/r8a7740.h>
27
28/*
29 * | MDx | XTAL1/EXTAL1 | System | EXTALR |
30 * Clock |-------+-----------------+ clock | 32.768 | RCLK
31 * Mode | 2/1/0 | src MHz | source | KHz | source
32 * -------+-------+-----------------+-----------+--------+----------
33 * 0 | 0 0 0 | External 20~50 | XTAL1 | O | EXTALR
34 * 1 | 0 0 1 | Crystal 20~30 | XTAL1 | O | EXTALR
35 * 2 | 0 1 0 | External 40~50 | XTAL1 / 2 | O | EXTALR
36 * 3 | 0 1 1 | Crystal 40~50 | XTAL1 / 2 | O | EXTALR
37 * 4 | 1 0 0 | External 20~50 | XTAL1 | x | XTAL1 / 1024
38 * 5 | 1 0 1 | Crystal 20~30 | XTAL1 | x | XTAL1 / 1024
39 * 6 | 1 1 0 | External 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
40 * 7 | 1 1 1 | Crystal 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
41 */
42
43/* CPG registers */
44#define FRQCRA 0xe6150000
45#define FRQCRB 0xe6150004
46#define FRQCRC 0xe61500e0
47#define PLLC01CR 0xe6150028
48
49#define SUBCKCR 0xe6150080
50
51#define MSTPSR0 0xe6150030
52#define MSTPSR1 0xe6150038
53#define MSTPSR2 0xe6150040
54#define MSTPSR3 0xe6150048
55#define MSTPSR4 0xe615004c
56#define SMSTPCR0 0xe6150130
57#define SMSTPCR1 0xe6150134
58#define SMSTPCR2 0xe6150138
59#define SMSTPCR3 0xe615013c
60#define SMSTPCR4 0xe6150140
61
62/* Fixed 32 KHz root clock from EXTALR pin */
63static struct clk extalr_clk = {
64 .rate = 32768,
65};
66
67/*
68 * 25MHz default rate for the EXTAL1 root input clock.
69 * If needed, reset this with clk_set_rate() from the platform code.
70 */
71static struct clk extal1_clk = {
72 .rate = 25000000,
73};
74
75/*
76 * 48MHz default rate for the EXTAL2 root input clock.
77 * If needed, reset this with clk_set_rate() from the platform code.
78 */
79static struct clk extal2_clk = {
80 .rate = 48000000,
81};
82
83/*
84 * 27MHz default rate for the DV_CLKI root input clock.
85 * If needed, reset this with clk_set_rate() from the platform code.
86 */
87static struct clk dv_clk = {
88 .rate = 27000000,
89};
90
91static unsigned long div_recalc(struct clk *clk)
92{
93 return clk->parent->rate / (int)(clk->priv);
94}
95
96static struct clk_ops div_clk_ops = {
97 .recalc = div_recalc,
98};
99
100/* extal1 / 2 */
101static struct clk extal1_div2_clk = {
102 .ops = &div_clk_ops,
103 .priv = (void *)2,
104 .parent = &extal1_clk,
105};
106
107/* extal1 / 1024 */
108static struct clk extal1_div1024_clk = {
109 .ops = &div_clk_ops,
110 .priv = (void *)1024,
111 .parent = &extal1_clk,
112};
113
114/* extal1 / 2 / 1024 */
115static struct clk extal1_div2048_clk = {
116 .ops = &div_clk_ops,
117 .priv = (void *)1024,
118 .parent = &extal1_div2_clk,
119};
120
121/* extal2 / 2 */
122static struct clk extal2_div2_clk = {
123 .ops = &div_clk_ops,
124 .priv = (void *)2,
125 .parent = &extal2_clk,
126};
127
128static struct clk_ops followparent_clk_ops = {
129 .recalc = followparent_recalc,
130};
131
132/* Main clock */
133static struct clk system_clk = {
134 .ops = &followparent_clk_ops,
135};
136
137static struct clk system_div2_clk = {
138 .ops = &div_clk_ops,
139 .priv = (void *)2,
140 .parent = &system_clk,
141};
142
143/* r_clk */
144static struct clk r_clk = {
145 .ops = &followparent_clk_ops,
146};
147
148/* PLLC0/PLLC1 */
149static unsigned long pllc01_recalc(struct clk *clk)
150{
151 unsigned long mult = 1;
152
153 if (__raw_readl(PLLC01CR) & (1 << 14))
154 mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1;
155
156 return clk->parent->rate * mult;
157}
158
159static struct clk_ops pllc01_clk_ops = {
160 .recalc = pllc01_recalc,
161};
162
163static struct clk pllc0_clk = {
164 .ops = &pllc01_clk_ops,
165 .flags = CLK_ENABLE_ON_INIT,
166 .parent = &system_clk,
167 .enable_reg = (void __iomem *)FRQCRC,
168};
169
170static struct clk pllc1_clk = {
171 .ops = &pllc01_clk_ops,
172 .flags = CLK_ENABLE_ON_INIT,
173 .parent = &system_div2_clk,
174 .enable_reg = (void __iomem *)FRQCRA,
175};
176
177/* PLLC1 / 2 */
178static struct clk pllc1_div2_clk = {
179 .ops = &div_clk_ops,
180 .priv = (void *)2,
181 .parent = &pllc1_clk,
182};
183
184struct clk *main_clks[] = {
185 &extalr_clk,
186 &extal1_clk,
187 &extal2_clk,
188 &extal1_div2_clk,
189 &extal1_div1024_clk,
190 &extal1_div2048_clk,
191 &extal2_div2_clk,
192 &dv_clk,
193 &system_clk,
194 &system_div2_clk,
195 &r_clk,
196 &pllc0_clk,
197 &pllc1_clk,
198 &pllc1_div2_clk,
199};
200
201static void div4_kick(struct clk *clk)
202{
203 unsigned long value;
204
205 /* set KICK bit in FRQCRB to update hardware setting */
206 value = __raw_readl(FRQCRB);
207 value |= (1 << 31);
208 __raw_writel(value, FRQCRB);
209}
210
211static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
212 24, 32, 36, 48, 0, 72, 96, 0 };
213
214static struct clk_div_mult_table div4_div_mult_table = {
215 .divisors = divisors,
216 .nr_divisors = ARRAY_SIZE(divisors),
217};
218
219static struct clk_div4_table div4_table = {
220 .div_mult_table = &div4_div_mult_table,
221 .kick = div4_kick,
222};
223
224enum {
225 DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
226 DIV4_HPP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
227 DIV4_NR
228};
229
230struct clk div4_clks[DIV4_NR] = {
231 [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
232 [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
233 [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
234 [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
235 [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
236 [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
237 [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
238 [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
239 [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
240 [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
241};
242
243enum {
244 DIV6_SUB,
245 DIV6_NR
246};
247
248static struct clk div6_clks[DIV6_NR] = {
249 [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
250};
251
252enum {
253 MSTP125,
254 MSTP116, MSTP111, MSTP100, MSTP117,
255
256 MSTP230,
257 MSTP222,
258 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
259
260 MSTP329, MSTP323,
261
262 MSTP_NR
263};
264
265static struct clk mstp_clks[MSTP_NR] = {
266 [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
267 [MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
268 [MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
269 [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */
270 [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
271
272 [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
273 [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
274 [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
275 [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
276 [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
277 [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
278 [MSTP202] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
279 [MSTP201] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
280 [MSTP200] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
281
282 [MSTP329] = SH_CLK_MSTP32(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
283 [MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
284};
285
286static struct clk_lookup lookups[] = {
287 /* main clocks */
288 CLKDEV_CON_ID("extalr", &extalr_clk),
289 CLKDEV_CON_ID("extal1", &extal1_clk),
290 CLKDEV_CON_ID("extal2", &extal2_clk),
291 CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk),
292 CLKDEV_CON_ID("extal1_div1024", &extal1_div1024_clk),
293 CLKDEV_CON_ID("extal1_div2048", &extal1_div2048_clk),
294 CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk),
295 CLKDEV_CON_ID("dv_clk", &dv_clk),
296 CLKDEV_CON_ID("system_clk", &system_clk),
297 CLKDEV_CON_ID("system_div2_clk", &system_div2_clk),
298 CLKDEV_CON_ID("r_clk", &r_clk),
299 CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
300 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
301 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
302
303 /* DIV4 clocks */
304 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
305 CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
306 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
307 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
308 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
309 CLKDEV_CON_ID("hpp_clk", &div4_clks[DIV4_HPP]),
310 CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
311 CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
312 CLKDEV_CON_ID("m3_clk", &div4_clks[DIV4_M3]),
313 CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
314
315 /* DIV6 clocks */
316 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
317
318 /* MSTP32 clocks */
319 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]),
320 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP111]),
321 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]),
322 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]),
323 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]),
324
325 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]),
326 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]),
327 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]),
328 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
329 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
330 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]),
331 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]),
332
333 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
334 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
335
336 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
337 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
338};
339
340void __init r8a7740_clock_init(u8 md_ck)
341{
342 int k, ret = 0;
343
344 /* detect system clock parent */
345 if (md_ck & MD_CK1)
346 system_clk.parent = &extal1_div2_clk;
347 else
348 system_clk.parent = &extal1_clk;
349
350 /* detect RCLK parent */
351 switch (md_ck & (MD_CK2 | MD_CK1)) {
352 case MD_CK2 | MD_CK1:
353 r_clk.parent = &extal1_div2048_clk;
354 break;
355 case MD_CK2:
356 r_clk.parent = &extal1_div1024_clk;
357 break;
358 case MD_CK1:
359 default:
360 r_clk.parent = &extalr_clk;
361 break;
362 }
363
364 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
365 ret = clk_register(main_clks[k]);
366
367 if (!ret)
368 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
369
370 if (!ret)
371 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
372
373 if (!ret)
374 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
375
376 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
377
378 if (!ret)
379 clk_init();
380 else
381 panic("failed to setup r8a7740 clocks\n");
382}
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
new file mode 100644
index 000000000000..b4b0e8cd096d
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -0,0 +1,176 @@
1/*
2 * r8a7779 clock framework support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/io.h>
23#include <linux/sh_clk.h>
24#include <linux/clkdev.h>
25#include <mach/common.h>
26
27#define FRQMR 0xffc80014
28#define MSTPCR0 0xffc80030
29#define MSTPCR1 0xffc80034
30#define MSTPCR3 0xffc8003c
31#define MSTPSR1 0xffc80044
32#define MSTPSR4 0xffc80048
33#define MSTPSR6 0xffc8004c
34#define MSTPCR4 0xffc80050
35#define MSTPCR5 0xffc80054
36#define MSTPCR6 0xffc80058
37#define MSTPCR7 0xffc80040
38
39/* ioremap() through clock mapping mandatory to avoid
40 * collision with ARM coherent DMA virtual memory range.
41 */
42
43static struct clk_mapping cpg_mapping = {
44 .phys = 0xffc80000,
45 .len = 0x80,
46};
47
48/*
49 * Default rate for the root input clock, reset this with clk_set_rate()
50 * from the platform code.
51 */
52static struct clk plla_clk = {
53 .rate = 1500000000,
54 .mapping = &cpg_mapping,
55};
56
57static struct clk *main_clks[] = {
58 &plla_clk,
59};
60
61static int divisors[] = { 0, 0, 0, 6, 8, 12, 16, 0, 24, 32, 36, 0, 0, 0, 0, 0 };
62
63static struct clk_div_mult_table div4_div_mult_table = {
64 .divisors = divisors,
65 .nr_divisors = ARRAY_SIZE(divisors),
66};
67
68static struct clk_div4_table div4_table = {
69 .div_mult_table = &div4_div_mult_table,
70};
71
72enum { DIV4_S, DIV4_OUT, DIV4_S4, DIV4_S3, DIV4_S1, DIV4_P, DIV4_NR };
73
74static struct clk div4_clks[DIV4_NR] = {
75 [DIV4_S] = SH_CLK_DIV4(&plla_clk, FRQMR, 20,
76 0x0018, CLK_ENABLE_ON_INIT),
77 [DIV4_OUT] = SH_CLK_DIV4(&plla_clk, FRQMR, 16,
78 0x0700, CLK_ENABLE_ON_INIT),
79 [DIV4_S4] = SH_CLK_DIV4(&plla_clk, FRQMR, 12,
80 0x0040, CLK_ENABLE_ON_INIT),
81 [DIV4_S3] = SH_CLK_DIV4(&plla_clk, FRQMR, 8,
82 0x0010, CLK_ENABLE_ON_INIT),
83 [DIV4_S1] = SH_CLK_DIV4(&plla_clk, FRQMR, 4,
84 0x0060, CLK_ENABLE_ON_INIT),
85 [DIV4_P] = SH_CLK_DIV4(&plla_clk, FRQMR, 0,
86 0x0300, CLK_ENABLE_ON_INIT),
87};
88
89enum { MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
90 MSTP016, MSTP015, MSTP014,
91 MSTP_NR };
92
93static struct clk mstp_clks[MSTP_NR] = {
94 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
95 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
96 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
97 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), /* SCIF3 */
98 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), /* SCIF4 */
99 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), /* SCIF5 */
100 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */
101 [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */
102 [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */
103};
104
105static unsigned long mul4_recalc(struct clk *clk)
106{
107 return clk->parent->rate * 4;
108}
109
110static struct clk_ops mul4_clk_ops = {
111 .recalc = mul4_recalc,
112};
113
114struct clk clkz_clk = {
115 .ops = &mul4_clk_ops,
116 .parent = &div4_clks[DIV4_S],
117};
118
119struct clk clkzs_clk = {
120 /* clks x 4 / 4 = clks */
121 .parent = &div4_clks[DIV4_S],
122};
123
124static struct clk *late_main_clks[] = {
125 &clkz_clk,
126 &clkzs_clk,
127};
128
129static struct clk_lookup lookups[] = {
130 /* main clocks */
131 CLKDEV_CON_ID("plla_clk", &plla_clk),
132 CLKDEV_CON_ID("clkz_clk", &clkz_clk),
133 CLKDEV_CON_ID("clkzs_clk", &clkzs_clk),
134
135 /* DIV4 clocks */
136 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]),
137 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_OUT]),
138 CLKDEV_CON_ID("shyway4_clk", &div4_clks[DIV4_S4]),
139 CLKDEV_CON_ID("shyway3_clk", &div4_clks[DIV4_S3]),
140 CLKDEV_CON_ID("shyway1_clk", &div4_clks[DIV4_S1]),
141 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
142
143 /* MSTP32 clocks */
144 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
145 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
146 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
147 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
148 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
149 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
150 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
151 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
152};
153
154void __init r8a7779_clock_init(void)
155{
156 int k, ret = 0;
157
158 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
159 ret = clk_register(main_clks[k]);
160
161 if (!ret)
162 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
163
164 if (!ret)
165 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
166
167 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
168 ret = clk_register(late_main_clks[k]);
169
170 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
171
172 if (!ret)
173 clk_init();
174 else
175 panic("failed to setup r8a7779 clocks\n");
176}
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 995a9c3aec8f..e349c22a0d71 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -411,11 +411,11 @@ static struct clk *fsibckcr_parent[] = {
411}; 411};
412 412
413static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { 413static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
414 [DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0, 414 [DIV6_HDMI] = SH_CLK_DIV6_EXT(HDMICKCR, 0,
415 hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2), 415 hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
416 [DIV6_FSIA] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIACKCR, 0, 416 [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
417 fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2), 417 fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2),
418 [DIV6_FSIB] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIBCKCR, 0, 418 [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
419 fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2), 419 fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
420}; 420};
421 421
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 1370a89ca358..34944d01bf1e 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -92,6 +92,24 @@ static struct clk_ops div2_clk_ops = {
92 .recalc = div2_recalc, 92 .recalc = div2_recalc,
93}; 93};
94 94
95static unsigned long div7_recalc(struct clk *clk)
96{
97 return clk->parent->rate / 7;
98}
99
100static struct clk_ops div7_clk_ops = {
101 .recalc = div7_recalc,
102};
103
104static unsigned long div13_recalc(struct clk *clk)
105{
106 return clk->parent->rate / 13;
107}
108
109static struct clk_ops div13_clk_ops = {
110 .recalc = div13_recalc,
111};
112
95/* Divide extal1 by two */ 113/* Divide extal1 by two */
96static struct clk extal1_div2_clk = { 114static struct clk extal1_div2_clk = {
97 .ops = &div2_clk_ops, 115 .ops = &div2_clk_ops,
@@ -174,12 +192,29 @@ static struct clk pll3_clk = {
174 .enable_bit = 3, 192 .enable_bit = 3,
175}; 193};
176 194
177/* Divide PLL1 by two */ 195/* Divide PLL */
178static struct clk pll1_div2_clk = { 196static struct clk pll1_div2_clk = {
179 .ops = &div2_clk_ops, 197 .ops = &div2_clk_ops,
180 .parent = &pll1_clk, 198 .parent = &pll1_clk,
181}; 199};
182 200
201static struct clk pll1_div7_clk = {
202 .ops = &div7_clk_ops,
203 .parent = &pll1_clk,
204};
205
206static struct clk pll1_div13_clk = {
207 .ops = &div13_clk_ops,
208 .parent = &pll1_clk,
209};
210
211/* External input clock */
212struct clk sh73a0_extcki_clk = {
213};
214
215struct clk sh73a0_extalr_clk = {
216};
217
183static struct clk *main_clks[] = { 218static struct clk *main_clks[] = {
184 &r_clk, 219 &r_clk,
185 &sh73a0_extal1_clk, 220 &sh73a0_extal1_clk,
@@ -193,6 +228,10 @@ static struct clk *main_clks[] = {
193 &pll2_clk, 228 &pll2_clk,
194 &pll3_clk, 229 &pll3_clk,
195 &pll1_div2_clk, 230 &pll1_div2_clk,
231 &pll1_div7_clk,
232 &pll1_div13_clk,
233 &sh73a0_extcki_clk,
234 &sh73a0_extalr_clk,
196}; 235};
197 236
198static void div4_kick(struct clk *clk) 237static void div4_kick(struct clk *clk)
@@ -246,27 +285,84 @@ enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
246 DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P, 285 DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
247 DIV6_NR }; 286 DIV6_NR };
248 287
288static struct clk *vck_parent[8] = {
289 [0] = &pll1_div2_clk,
290 [1] = &pll2_clk,
291 [2] = &sh73a0_extcki_clk,
292 [3] = &sh73a0_extal2_clk,
293 [4] = &main_div2_clk,
294 [5] = &sh73a0_extalr_clk,
295 [6] = &main_clk,
296};
297
298static struct clk *pll_parent[4] = {
299 [0] = &pll1_div2_clk,
300 [1] = &pll2_clk,
301 [2] = &pll1_div13_clk,
302};
303
304static struct clk *hsi_parent[4] = {
305 [0] = &pll1_div2_clk,
306 [1] = &pll2_clk,
307 [2] = &pll1_div7_clk,
308};
309
310static struct clk *pll_extal2_parent[] = {
311 [0] = &pll1_div2_clk,
312 [1] = &pll2_clk,
313 [2] = &sh73a0_extal2_clk,
314 [3] = &sh73a0_extal2_clk,
315};
316
317static struct clk *dsi_parent[8] = {
318 [0] = &pll1_div2_clk,
319 [1] = &pll2_clk,
320 [2] = &main_clk,
321 [3] = &sh73a0_extal2_clk,
322 [4] = &sh73a0_extcki_clk,
323};
324
249static struct clk div6_clks[DIV6_NR] = { 325static struct clk div6_clks[DIV6_NR] = {
250 [DIV6_VCK1] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR1, 0), 326 [DIV6_VCK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0,
251 [DIV6_VCK2] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR2, 0), 327 vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
252 [DIV6_VCK3] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR3, 0), 328 [DIV6_VCK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0,
253 [DIV6_ZB1] = SH_CLK_DIV6(&pll1_div2_clk, ZBCKCR, CLK_ENABLE_ON_INIT), 329 vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
254 [DIV6_FLCTL] = SH_CLK_DIV6(&pll1_div2_clk, FLCKCR, 0), 330 [DIV6_VCK3] = SH_CLK_DIV6_EXT(VCLKCR3, 0,
255 [DIV6_SDHI0] = SH_CLK_DIV6(&pll1_div2_clk, SD0CKCR, 0), 331 vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
256 [DIV6_SDHI1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0), 332 [DIV6_ZB1] = SH_CLK_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
257 [DIV6_SDHI2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0), 333 pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
258 [DIV6_FSIA] = SH_CLK_DIV6(&pll1_div2_clk, FSIACKCR, 0), 334 [DIV6_FLCTL] = SH_CLK_DIV6_EXT(FLCKCR, 0,
259 [DIV6_FSIB] = SH_CLK_DIV6(&pll1_div2_clk, FSIBCKCR, 0), 335 pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
260 [DIV6_SUB] = SH_CLK_DIV6(&sh73a0_extal2_clk, SUBCKCR, 0), 336 [DIV6_SDHI0] = SH_CLK_DIV6_EXT(SD0CKCR, 0,
261 [DIV6_SPUA] = SH_CLK_DIV6(&pll1_div2_clk, SPUACKCR, 0), 337 pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
262 [DIV6_SPUV] = SH_CLK_DIV6(&pll1_div2_clk, SPUVCKCR, 0), 338 [DIV6_SDHI1] = SH_CLK_DIV6_EXT(SD1CKCR, 0,
263 [DIV6_MSU] = SH_CLK_DIV6(&pll1_div2_clk, MSUCKCR, 0), 339 pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
264 [DIV6_HSI] = SH_CLK_DIV6(&pll1_div2_clk, HSICKCR, 0), 340 [DIV6_SDHI2] = SH_CLK_DIV6_EXT(SD2CKCR, 0,
265 [DIV6_MFG1] = SH_CLK_DIV6(&pll1_div2_clk, MFCK1CR, 0), 341 pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
266 [DIV6_MFG2] = SH_CLK_DIV6(&pll1_div2_clk, MFCK2CR, 0), 342 [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
267 [DIV6_DSIT] = SH_CLK_DIV6(&pll1_div2_clk, DSITCKCR, 0), 343 pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
268 [DIV6_DSI0P] = SH_CLK_DIV6(&pll1_div2_clk, DSI0PCKCR, 0), 344 [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
269 [DIV6_DSI1P] = SH_CLK_DIV6(&pll1_div2_clk, DSI1PCKCR, 0), 345 pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
346 [DIV6_SUB] = SH_CLK_DIV6_EXT(SUBCKCR, 0,
347 pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
348 [DIV6_SPUA] = SH_CLK_DIV6_EXT(SPUACKCR, 0,
349 pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
350 [DIV6_SPUV] = SH_CLK_DIV6_EXT(SPUVCKCR, 0,
351 pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
352 [DIV6_MSU] = SH_CLK_DIV6_EXT(MSUCKCR, 0,
353 pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
354 [DIV6_HSI] = SH_CLK_DIV6_EXT(HSICKCR, 0,
355 hsi_parent, ARRAY_SIZE(hsi_parent), 6, 2),
356 [DIV6_MFG1] = SH_CLK_DIV6_EXT(MFCK1CR, 0,
357 pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
358 [DIV6_MFG2] = SH_CLK_DIV6_EXT(MFCK2CR, 0,
359 pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
360 [DIV6_DSIT] = SH_CLK_DIV6_EXT(DSITCKCR, 0,
361 pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
362 [DIV6_DSI0P] = SH_CLK_DIV6_EXT(DSI0PCKCR, 0,
363 dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
364 [DIV6_DSI1P] = SH_CLK_DIV6_EXT(DSI1PCKCR, 0,
365 dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
270}; 366};
271 367
272enum { MSTP001, 368enum { MSTP001,
@@ -403,7 +499,7 @@ void __init sh73a0_clock_init(void)
403 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 499 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
404 500
405 if (!ret) 501 if (!ret)
406 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 502 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
407 503
408 if (!ret) 504 if (!ret)
409 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); 505 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index 26079d933d91..6ac015c89206 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -14,7 +14,7 @@
14#include <linux/init.h> 14#include <linux/init.h>
15#include <asm/memory.h> 15#include <asm/memory.h>
16 16
17 __INIT 17 __CPUINIT
18 18
19/* 19/*
20 * Reset vector for secondary CPUs. 20 * Reset vector for secondary CPUs.
diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c
index 238a0d97d2d5..828d22f3af57 100644
--- a/arch/arm/mach-shmobile/hotplug.c
+++ b/arch/arm/mach-shmobile/hotplug.c
@@ -12,14 +12,43 @@
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/errno.h> 13#include <linux/errno.h>
14#include <linux/smp.h> 14#include <linux/smp.h>
15#include <linux/cpumask.h>
16#include <linux/delay.h>
17#include <mach/common.h>
18#include <asm/cacheflush.h>
19
20static cpumask_t dead_cpus;
15 21
16int platform_cpu_kill(unsigned int cpu) 22int platform_cpu_kill(unsigned int cpu)
17{ 23{
18 return 1; 24 int k;
25
26 /* this function is running on another CPU than the offline target,
27 * here we need wait for shutdown code in platform_cpu_die() to
28 * finish before asking SoC-specific code to power off the CPU core.
29 */
30 for (k = 0; k < 1000; k++) {
31 if (cpumask_test_cpu(cpu, &dead_cpus))
32 return shmobile_platform_cpu_kill(cpu);
33
34 mdelay(1);
35 }
36
37 return 0;
19} 38}
20 39
21void platform_cpu_die(unsigned int cpu) 40void platform_cpu_die(unsigned int cpu)
22{ 41{
42 /* hardware shutdown code running on the CPU that is being offlined */
43 flush_cache_all();
44 dsb();
45
46 /* notify platform_cpu_kill() that hardware shutdown is finished */
47 cpumask_set_cpu(cpu, &dead_cpus);
48
49 /* wait for SoC code in platform_cpu_kill() to shut off CPU core
50 * power. CPU bring up starts from the reset vector.
51 */
23 while (1) { 52 while (1) {
24 /* 53 /*
25 * here's the WFI 54 * here's the WFI
@@ -33,6 +62,7 @@ void platform_cpu_die(unsigned int cpu)
33 62
34int platform_cpu_disable(unsigned int cpu) 63int platform_cpu_disable(unsigned int cpu)
35{ 64{
65 cpumask_clear_cpu(cpu, &dead_cpus);
36 /* 66 /*
37 * we don't allow CPU 0 to be shutdown (it is still too special 67 * we don't allow CPU 0 to be shutdown (it is still too special
38 * e.g. clock tick interrupts) 68 * e.g. clock tick interrupts)
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index be78a2c73db4..e4b945e271e7 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -4,6 +4,7 @@
4extern struct sys_timer shmobile_timer; 4extern struct sys_timer shmobile_timer;
5extern void shmobile_setup_console(void); 5extern void shmobile_setup_console(void);
6extern void shmobile_secondary_vector(void); 6extern void shmobile_secondary_vector(void);
7extern int shmobile_platform_cpu_kill(unsigned int cpu);
7struct clk; 8struct clk;
8extern int clk_init(void); 9extern int clk_init(void);
9extern void shmobile_handle_irq_intc(struct pt_regs *); 10extern void shmobile_handle_irq_intc(struct pt_regs *);
@@ -46,10 +47,31 @@ extern void sh73a0_clock_init(void);
46extern void sh73a0_pinmux_init(void); 47extern void sh73a0_pinmux_init(void);
47extern struct clk sh73a0_extal1_clk; 48extern struct clk sh73a0_extal1_clk;
48extern struct clk sh73a0_extal2_clk; 49extern struct clk sh73a0_extal2_clk;
50extern struct clk sh73a0_extcki_clk;
51extern struct clk sh73a0_extalr_clk;
49 52
50extern unsigned int sh73a0_get_core_count(void); 53extern unsigned int sh73a0_get_core_count(void);
51extern void sh73a0_secondary_init(unsigned int cpu); 54extern void sh73a0_secondary_init(unsigned int cpu);
52extern int sh73a0_boot_secondary(unsigned int cpu); 55extern int sh73a0_boot_secondary(unsigned int cpu);
53extern void sh73a0_smp_prepare_cpus(void); 56extern void sh73a0_smp_prepare_cpus(void);
54 57
58extern void r8a7740_init_irq(void);
59extern void r8a7740_add_early_devices(void);
60extern void r8a7740_add_standard_devices(void);
61extern void r8a7740_clock_init(u8 md_ck);
62extern void r8a7740_pinmux_init(void);
63
64extern void r8a7779_init_irq(void);
65extern void r8a7779_add_early_devices(void);
66extern void r8a7779_add_standard_devices(void);
67extern void r8a7779_clock_init(void);
68extern void r8a7779_pinmux_init(void);
69extern void r8a7779_pm_init(void);
70
71extern unsigned int r8a7779_get_core_count(void);
72extern int r8a7779_platform_cpu_kill(unsigned int cpu);
73extern void r8a7779_secondary_init(unsigned int cpu);
74extern int r8a7779_boot_secondary(unsigned int cpu);
75extern void r8a7779_smp_prepare_cpus(void);
76
55#endif /* __ARCH_MACH_COMMON_H */ 77#endif /* __ARCH_MACH_COMMON_H */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
new file mode 100644
index 000000000000..9d447abb969c
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -0,0 +1,584 @@
1/*
2 * Copyright (C) 2011 Renesas Solutions Corp.
3 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef __ASM_R8A7740_H__
20#define __ASM_R8A7740_H__
21
22/*
23 * MD_CKx pin
24 */
25#define MD_CK2 (1 << 2)
26#define MD_CK1 (1 << 1)
27#define MD_CK0 (1 << 0)
28
29/*
30 * Pin Function Controller:
31 * GPIO_FN_xx - GPIO used to select pin function
32 * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
33 */
34enum {
35 /* PORT */
36 GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
37 GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
38
39 GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
40 GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
41
42 GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
43 GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
44
45 GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
46 GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
47
48 GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
49 GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
50
51 GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
52 GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
53
54 GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
55 GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
56
57 GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
58 GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
59
60 GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
61 GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
62
63 GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
64 GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
65
66 GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
67 GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
68
69 GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
70 GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
71
72 GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
73 GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
74
75 GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
76 GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
77
78 GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
79 GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
80
81 GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
82 GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
83
84 GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
85 GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
86
87 GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
88 GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
89
90 GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
91 GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
92
93 GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
94 GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
95
96 GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
97 GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
98
99 GPIO_PORT210, GPIO_PORT211,
100
101 /* IRQ */
102 GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13,
103 GPIO_FN_IRQ1,
104 GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12,
105 GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14,
106 GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172,
107 GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1,
108 GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173,
109 GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209,
110 GPIO_FN_IRQ8,
111 GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210,
112 GPIO_FN_IRQ10,
113 GPIO_FN_IRQ11,
114 GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97,
115 GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98,
116 GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99,
117 GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100,
118 GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211,
119 GPIO_FN_IRQ17,
120 GPIO_FN_IRQ18,
121 GPIO_FN_IRQ19,
122 GPIO_FN_IRQ20,
123 GPIO_FN_IRQ21,
124 GPIO_FN_IRQ22,
125 GPIO_FN_IRQ23,
126 GPIO_FN_IRQ24,
127 GPIO_FN_IRQ25,
128 GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81,
129 GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168,
130 GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169,
131 GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170,
132 GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171,
133 GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167,
134
135 /* Function */
136
137 /* DBGT */
138 GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0,
139 GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20,
140 GPIO_FN_DBGMD21,
141
142 /* FSI */
143 GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */
144 GPIO_FN_FSIAISLD_PORT5,
145 GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */
146 GPIO_FN_FSIASPDIF_PORT18,
147 GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2,
148 GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT,
149 GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC,
150 GPIO_FN_FSIACK, GPIO_FN_FSIAILR,
151 GPIO_FN_FSIAIBT,
152
153 /* FMSI */
154 GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
155 GPIO_FN_FMSISLD_PORT6,
156 GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT,
157 GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT,
158 GPIO_FN_FMSICK, GPIO_FN_FMSOILR,
159 GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR,
160 GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD,
161 GPIO_FN_FMSOCK,
162
163 /* SCIFA0 */
164 GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS,
165 GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD,
166 GPIO_FN_SCIFA0_TXD,
167
168 /* SCIFA1 */
169 GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK,
170 GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD,
171 GPIO_FN_SCIFA1_RTS,
172
173 /* SCIFA2 */
174 GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
175 GPIO_FN_SCIFA2_SCK_PORT199,
176 GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD,
177 GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS,
178
179 /* SCIFA3 */
180 GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
181 GPIO_FN_SCIFA3_SCK_PORT116,
182 GPIO_FN_SCIFA3_CTS_PORT117,
183 GPIO_FN_SCIFA3_RXD_PORT174,
184 GPIO_FN_SCIFA3_TXD_PORT175,
185
186 GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
187 GPIO_FN_SCIFA3_SCK_PORT158,
188 GPIO_FN_SCIFA3_CTS_PORT162,
189 GPIO_FN_SCIFA3_RXD_PORT159,
190 GPIO_FN_SCIFA3_TXD_PORT160,
191
192 /* SCIFA4 */
193 GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
194 GPIO_FN_SCIFA4_TXD_PORT13,
195
196 GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
197 GPIO_FN_SCIFA4_TXD_PORT203,
198
199 GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
200 GPIO_FN_SCIFA4_TXD_PORT93,
201
202 GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
203 GPIO_FN_SCIFA4_SCK_PORT205,
204
205 /* SCIFA5 */
206 GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
207 GPIO_FN_SCIFA5_RXD_PORT10,
208
209 GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
210 GPIO_FN_SCIFA5_TXD_PORT208,
211
212 GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
213 GPIO_FN_SCIFA5_RXD_PORT92,
214
215 GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
216 GPIO_FN_SCIFA5_SCK_PORT206,
217
218 /* SCIFA6 */
219 GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD,
220
221 /* SCIFA7 */
222 GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD,
223
224 /* SCIFAB */
225 GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
226 GPIO_FN_SCIFB_RXD_PORT191,
227 GPIO_FN_SCIFB_TXD_PORT192,
228 GPIO_FN_SCIFB_RTS_PORT186,
229 GPIO_FN_SCIFB_CTS_PORT187,
230
231 GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
232 GPIO_FN_SCIFB_RXD_PORT3,
233 GPIO_FN_SCIFB_TXD_PORT4,
234 GPIO_FN_SCIFB_RTS_PORT172,
235 GPIO_FN_SCIFB_CTS_PORT173,
236
237 /* LCD0 */
238 GPIO_FN_LCDC0_SELECT,
239 GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2,
240 GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5,
241 GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8,
242 GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11,
243 GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14,
244 GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17,
245 GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC,
246
247 GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */
248 GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */
249
250 GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */
251 GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */
252
253 GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162,
254 GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158,
255 GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159,
256 GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */
257
258 GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4,
259 GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2,
260 GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1,
261 GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */
262
263 /* LCD1 */
264 GPIO_FN_LCDC1_SELECT,
265 GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2,
266 GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5,
267 GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8,
268 GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11,
269 GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14,
270 GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17,
271 GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20,
272 GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23,
273 GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC,
274 GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC,
275
276 GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */
277 GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */
278
279 GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */
280 GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */
281
282 /* RSPI */
283 GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A,
284 GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A,
285 GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A,
286 GPIO_FN_RSPI_CK_A,
287
288 /* VIO CKO */
289 GPIO_FN_VIO_CKO1,
290 GPIO_FN_VIO_CKO2,
291 GPIO_FN_VIO_CKO_1,
292 GPIO_FN_VIO_CKO,
293
294 /* VIO0 */
295 GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2,
296 GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5,
297 GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8,
298 GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11,
299 GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD,
300 GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD,
301
302 GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
303 GPIO_FN_VIO0_D14_PORT25,
304 GPIO_FN_VIO0_D15_PORT24,
305
306 GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
307 GPIO_FN_VIO0_D14_PORT95,
308 GPIO_FN_VIO0_D15_PORT96,
309
310 /* VIO1 */
311 GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2,
312 GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5,
313 GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD,
314 GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD,
315
316 /* TPU0 */
317 GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1,
318 GPIO_FN_TPU0TO3,
319 GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
320 GPIO_FN_TPU0TO2_PORT202,
321
322 /* SSP1 0 */
323 GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2,
324 GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5,
325 GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN,
326 GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC,
327
328 /* SSP1 1 */
329 GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3,
330 GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6,
331 GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC,
332
333 GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
334 GPIO_FN_STP1_IPEN_PORT187,
335
336 GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
337 GPIO_FN_STP1_IPEN_PORT193,
338
339 /* SIM */
340 GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK,
341 GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */
342 GPIO_FN_SIM_D_PORT199,
343
344 /* SDHI0 */
345 GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2,
346 GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP,
347 GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK,
348
349 /* SDHI1 */
350 GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2,
351 GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP,
352 GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK,
353
354 /* SDHI2 */
355 GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2,
356 GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD,
357
358 GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
359 GPIO_FN_SDHI2_WP_PORT25,
360
361 GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
362 GPIO_FN_SDHI2_CD_PORT202,
363
364 /* MSIOF2 */
365 GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK,
366 GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1,
367 GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC,
368 GPIO_FN_MSIOF2_RSCK,
369
370 /* KEYSC */
371 GPIO_FN_KEYIN4, GPIO_FN_KEYIN5,
372 GPIO_FN_KEYIN6, GPIO_FN_KEYIN7,
373 GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2,
374 GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5,
375 GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7,
376
377 GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
378 GPIO_FN_KEYIN1_PORT44,
379 GPIO_FN_KEYIN2_PORT45,
380 GPIO_FN_KEYIN3_PORT46,
381
382 GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
383 GPIO_FN_KEYIN1_PORT57,
384 GPIO_FN_KEYIN2_PORT56,
385 GPIO_FN_KEYIN3_PORT55,
386
387 /* VOU */
388 GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3,
389 GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7,
390 GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11,
391 GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15,
392 GPIO_FN_DV_CLK,
393 GPIO_FN_DV_VSYNC,
394 GPIO_FN_DV_HSYNC,
395
396 /* MEMC */
397 GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2,
398 GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5,
399 GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8,
400 GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11,
401 GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14,
402 GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT,
403 GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE,
404
405 GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
406 GPIO_FN_MEMC_ADV,
407 GPIO_FN_MEMC_WAIT,
408 GPIO_FN_MEMC_BUSCLK,
409
410 GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
411 GPIO_FN_MEMC_DREQ0,
412 GPIO_FN_MEMC_DREQ1,
413 GPIO_FN_MEMC_A0,
414
415 /* MMC */
416 GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69,
417 GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71,
418 GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73,
419 GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75,
420 GPIO_FN_MMC0_CLK_PORT66,
421 GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */
422
423 GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148,
424 GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146,
425 GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144,
426 GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142,
427 GPIO_FN_MMC1_CLK_PORT103,
428 GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */
429
430 /* MSIOF0 */
431 GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
432 GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
433 GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1,
434 GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK,
435 GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC,
436
437 /* MSIOF1 */
438 GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC,
439 GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1,
440
441 GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117,
442 GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119,
443 GPIO_FN_MSIOF1_TSYNC_PORT120,
444 GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */
445
446 GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72,
447 GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74,
448 GPIO_FN_MSIOF1_RXD_PORT75,
449 GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */
450
451 /* GPIO */
452 GPIO_FN_GPO0, GPIO_FN_GPI0,
453 GPIO_FN_GPO1, GPIO_FN_GPI1,
454
455 /* USB0 */
456 GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS,
457
458 /* USB1 */
459 GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON,
460
461 /* BBIF1 */
462 GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC,
463 GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC,
464 GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N,
465
466 /* BBIF2 */
467 GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
468 GPIO_FN_BBIF2_RXD2_PORT60,
469 GPIO_FN_BBIF2_TSYNC2_PORT6,
470 GPIO_FN_BBIF2_TSCK2_PORT59,
471
472 GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
473 GPIO_FN_BBIF2_TXD2_PORT183,
474 GPIO_FN_BBIF2_TSCK2_PORT89,
475 GPIO_FN_BBIF2_TSYNC2_PORT184,
476
477 /* BSC / FLCTL / PCMCIA */
478 GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4,
479 GPIO_FN_CS5B, GPIO_FN_CS6A,
480 GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
481 GPIO_FN_CS5A_PORT19,
482 GPIO_FN_IOIS16, /* ? */
483
484 GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3,
485 GPIO_FN_A4_FOE, /* share with FLCTL */
486 GPIO_FN_A5_FCDE, /* share with FLCTL */
487 GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9,
488 GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13,
489 GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17,
490 GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21,
491 GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25,
492 GPIO_FN_A26,
493
494 GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */
495 GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */
496 GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */
497 GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */
498 GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */
499 GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */
500 GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */
501 GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */
502
503 GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19,
504 GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23,
505 GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27,
506 GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31,
507
508 GPIO_FN_WE0_FWE, /* share with FLCTL */
509 GPIO_FN_WE1,
510 GPIO_FN_WE2_ICIORD, /* share with PCMCIA */
511 GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */
512 GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR,
513 GPIO_FN_RD_FSC, /* share with FLCTL */
514 GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */
515 GPIO_FN_WAIT_PORT90,
516
517 GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */
518
519 /* IRDA */
520 GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT,
521
522 /* ATAPI */
523 GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2,
524 GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5,
525 GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8,
526 GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11,
527 GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14,
528 GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1,
529 GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1,
530 GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY,
531 GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION,
532 GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ,
533
534 /* RMII */
535 GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0,
536 GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0,
537 GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO,
538 GPIO_FN_RMII_REF50CK, /* for RMII */
539 GPIO_FN_RMII_REF125CK, /* for GMII */
540
541 /* GEther */
542 GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0,
543 GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3,
544 GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */
545 GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */
546 GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER,
547 GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV,
548 GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1,
549 GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3,
550 GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */
551 GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */
552 GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS,
553 GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO,
554 GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT,
555 GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK,
556
557 /* DMA0 */
558 GPIO_FN_DREQ0, GPIO_FN_DACK0,
559
560 /* DMA1 */
561 GPIO_FN_DREQ1, GPIO_FN_DACK1,
562
563 /* SYSC */
564 GPIO_FN_RESETOUTS,
565 GPIO_FN_RESETP_PULLUP,
566 GPIO_FN_RESETP_PLAIN,
567
568 /* SDENC */
569 GPIO_FN_SDENC_CPG,
570 GPIO_FN_SDENC_DV_CLKI,
571
572 /* IRREM */
573 GPIO_FN_IROUT,
574
575 /* DEBUG */
576 GPIO_FN_EDEBGREQ_PULLDOWN,
577 GPIO_FN_EDEBGREQ_PULLUP,
578
579 GPIO_FN_TRACEAUD_FROM_VIO,
580 GPIO_FN_TRACEAUD_FROM_LCDC0,
581 GPIO_FN_TRACEAUD_FROM_MEMC,
582};
583
584#endif /* __ASM_R8A7740_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
new file mode 100644
index 000000000000..b07ad318eb2e
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -0,0 +1,363 @@
1#ifndef __ASM_R8A7779_H__
2#define __ASM_R8A7779_H__
3
4#include <linux/sh_clk.h>
5#include <linux/pm_domain.h>
6
7/* Pin Function Controller:
8 * GPIO_FN_xx - GPIO used to select pin function
9 * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
10 */
11enum {
12 GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
13 GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
14 GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
15 GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
16 GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
17 GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
18 GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
19 GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
20
21 GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
22 GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
23 GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
24 GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
25 GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
26 GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
27 GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
28 GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31,
29
30 GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
31 GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
32 GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
33 GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
34 GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
35 GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
36 GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
37 GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
38
39 GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
40 GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
41 GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
42 GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
43 GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
44 GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
45 GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
46 GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
47
48 GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
49 GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
50 GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
51 GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
52 GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
53 GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
54 GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
55 GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
56
57 GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
58 GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
59 GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
60 GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
61 GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
62 GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
63 GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
64 GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
65
66 GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
67 GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
68 GPIO_GP_6_8,
69
70 GPIO_FN_AVS1, GPIO_FN_AVS2, GPIO_FN_A17, GPIO_FN_A18,
71 GPIO_FN_A19,
72
73 /* IPSR0 */
74 GPIO_FN_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
75 GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
76 GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
77 GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
78 GPIO_FN_MMC0_D3, GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D,
79 GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_SCK5_D, GPIO_FN_HSPI_CLK2_B,
80 GPIO_FN_A22, GPIO_FN_RX5_D, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0,
81 GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1,
82 GPIO_FN_A24, GPIO_FN_SD1_CD, GPIO_FN_MMC0_D4, GPIO_FN_FD4,
83 GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
84 GPIO_FN_SD1_WP, GPIO_FN_MMC0_D5, GPIO_FN_FD5, GPIO_FN_HSPI_RX2,
85 GPIO_FN_VI1_R3, GPIO_FN_TX5_B, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CTS0_B,
86 GPIO_FN_CLKOUT, GPIO_FN_TX3C_IRDA_TX_C, GPIO_FN_PWM0_B, GPIO_FN_CS0,
87 GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2,
88 GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
89 GPIO_FN_VI1_R7, GPIO_FN_HRTS1, GPIO_FN_RX4_C,
90
91 /* IPSR1 */
92 GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C, GPIO_FN_MMC0_D6,
93 GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_MMC0_D7, GPIO_FN_FD7,
94 GPIO_FN_EX_CS2, GPIO_FN_SD1_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_FALE,
95 GPIO_FN_ATACS00, GPIO_FN_EX_CS3, GPIO_FN_SD1_CMD, GPIO_FN_MMC0_CMD,
96 GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_RX5_B,
97 GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_RTS0_B_TANS_B,
98 GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, GPIO_FN_SD1_DAT0, GPIO_FN_MMC0_D0,
99 GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_SCK5_B,
100 GPIO_FN_HTX1, GPIO_FN_TX2_E, GPIO_FN_TX0_B, GPIO_FN_SSI_SCK9,
101 GPIO_FN_EX_CS5, GPIO_FN_SD1_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FD1,
102 GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_RX2_E,
103 GPIO_FN_RX0_B, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
104 GPIO_FN_SCK4, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, GPIO_FN_TX4,
105 GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_RX4, GPIO_FN_HTX0,
106 GPIO_FN_TX1, GPIO_FN_SDATA, GPIO_FN_CTS0_C, GPIO_FN_SUB_TCK,
107 GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18,
108 GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34,
109
110 /* IPSR2 */
111 GPIO_FN_HRX0, GPIO_FN_RX1, GPIO_FN_SCKZ, GPIO_FN_RTS0_C_TANS_C,
112 GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11,
113 GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35,
114 GPIO_FN_HSCK0, GPIO_FN_SCK1, GPIO_FN_MTS, GPIO_FN_PWM5,
115 GPIO_FN_SCK0_C, GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
116 GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16,
117 GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0, GPIO_FN_CTS1,
118 GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_RX0_C, GPIO_FN_SCIF_CLK_C,
119 GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0,
120 GPIO_FN_RTS1_TANS, GPIO_FN_MDATA, GPIO_FN_TX0_C, GPIO_FN_SUB_TMS,
121 GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17,
122 GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, GPIO_FN_DU0_DR0,
123 GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0,
124 GPIO_FN_TX5_C, GPIO_FN_DU0_DR1, GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
125 GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_RX5_C,
126 GPIO_FN_DU0_DR2, GPIO_FN_LCDOUT2, GPIO_FN_DU0_DR3, GPIO_FN_LCDOUT3,
127 GPIO_FN_DU0_DR4, GPIO_FN_LCDOUT4, GPIO_FN_DU0_DR5, GPIO_FN_LCDOUT5,
128 GPIO_FN_DU0_DR6, GPIO_FN_LCDOUT6, GPIO_FN_DU0_DR7, GPIO_FN_LCDOUT7,
129 GPIO_FN_DU0_DG0, GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
130 GPIO_FN_AUDATA2,
131
132 /* IPSR3 */
133 GPIO_FN_DU0_DG1, GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
134 GPIO_FN_AUDATA3, GPIO_FN_DU0_DG2, GPIO_FN_LCDOUT10, GPIO_FN_DU0_DG3,
135 GPIO_FN_LCDOUT11, GPIO_FN_DU0_DG4, GPIO_FN_LCDOUT12, GPIO_FN_DU0_DG5,
136 GPIO_FN_LCDOUT13, GPIO_FN_DU0_DG6, GPIO_FN_LCDOUT14, GPIO_FN_DU0_DG7,
137 GPIO_FN_LCDOUT15, GPIO_FN_DU0_DB0, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
138 GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, GPIO_FN_DU0_DB1,
139 GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B,
140 GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_DU0_DB2, GPIO_FN_LCDOUT18,
141 GPIO_FN_DU0_DB3, GPIO_FN_LCDOUT19, GPIO_FN_DU0_DB4, GPIO_FN_LCDOUT20,
142 GPIO_FN_DU0_DB5, GPIO_FN_LCDOUT21, GPIO_FN_DU0_DB6, GPIO_FN_LCDOUT22,
143 GPIO_FN_DU0_DB7, GPIO_FN_LCDOUT23, GPIO_FN_DU0_DOTCLKIN,
144 GPIO_FN_QSTVA_QVS, GPIO_FN_TX3_D_IRDA_TX_D, GPIO_FN_SCL3_B,
145 GPIO_FN_DU0_DOTCLKOUT0, GPIO_FN_QCLK, GPIO_FN_DU0_DOTCLKOUT1,
146 GPIO_FN_QSTVB_QVE, GPIO_FN_RX3_D_IRDA_RX_D, GPIO_FN_SDA3_B,
147 GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B,
148 GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_QSTH_QHS,
149 GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE,
150 GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
151 GPIO_FN_CAN1_TX, GPIO_FN_TX2_C, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
152
153 /* IPSR4 */
154 GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C,
155 GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C,
156 GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, GPIO_FN_DU1_DR0,
157 GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_SD3_CLK,
158 GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
159 GPIO_FN_DU1_DR1, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
160 GPIO_FN_SD3_CMD, GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC,
161 GPIO_FN_CTS0_D, GPIO_FN_DU1_DR2, GPIO_FN_VI2_G0, GPIO_FN_DU1_DR3,
162 GPIO_FN_VI2_G1, GPIO_FN_DU1_DR4, GPIO_FN_VI2_G2, GPIO_FN_DU1_DR5,
163 GPIO_FN_VI2_G3, GPIO_FN_DU1_DR6, GPIO_FN_VI2_G4, GPIO_FN_DU1_DR7,
164 GPIO_FN_VI2_G5, GPIO_FN_DU1_DG0, GPIO_FN_VI2_DATA2_VI2_B2,
165 GPIO_FN_SCL1_B, GPIO_FN_SD3_DAT2, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6,
166 GPIO_FN_TX0_D, GPIO_FN_DU1_DG1, GPIO_FN_VI2_DATA3_VI2_B3,
167 GPIO_FN_SDA1_B, GPIO_FN_SD3_DAT3, GPIO_FN_SCK5, GPIO_FN_AUDATA7,
168 GPIO_FN_RX0_D, GPIO_FN_DU1_DG2, GPIO_FN_VI2_G6, GPIO_FN_DU1_DG3,
169 GPIO_FN_VI2_G7, GPIO_FN_DU1_DG4, GPIO_FN_VI2_R0, GPIO_FN_DU1_DG5,
170 GPIO_FN_VI2_R1, GPIO_FN_DU1_DG6, GPIO_FN_VI2_R2, GPIO_FN_DU1_DG7,
171 GPIO_FN_VI2_R3, GPIO_FN_DU1_DB0, GPIO_FN_VI2_DATA4_VI2_B4,
172 GPIO_FN_SCL2_B, GPIO_FN_SD3_DAT0, GPIO_FN_TX5, GPIO_FN_SCK0_D,
173
174 /* IPSR5 */
175 GPIO_FN_DU1_DB1, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
176 GPIO_FN_SD3_DAT1, GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D,
177 GPIO_FN_DU1_DB2, GPIO_FN_VI2_R4, GPIO_FN_DU1_DB3, GPIO_FN_VI2_R5,
178 GPIO_FN_DU1_DB4, GPIO_FN_VI2_R6, GPIO_FN_DU1_DB5, GPIO_FN_VI2_R7,
179 GPIO_FN_DU1_DB6, GPIO_FN_SCL2_D, GPIO_FN_DU1_DB7, GPIO_FN_SDA2_D,
180 GPIO_FN_DU1_DOTCLKIN, GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1,
181 GPIO_FN_SCL1_D, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_VI2_FIELD,
182 GPIO_FN_SDA1_D, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_VI2_HSYNC,
183 GPIO_FN_VI3_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_VI2_VSYNC,
184 GPIO_FN_VI3_VSYNC, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
185 GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_SD3_CD,
186 GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
187 GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN,
188 GPIO_FN_GPS_SIGN_D, GPIO_FN_DU1_DISP, GPIO_FN_VI2_DATA6_VI2_B6,
189 GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1,
190 GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
191 GPIO_FN_DU1_CDE, GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B,
192 GPIO_FN_SD3_WP, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
193 GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C,
194 GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
195 GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0,
196 GPIO_FN_MOUT0,
197
198 /* IPSR6 */
199 GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_MOUT1,
200 GPIO_FN_SSI_WS0129, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_MOUT2,
201 GPIO_FN_SSI_SDATA0, GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_MOUT5,
202 GPIO_FN_SSI_SDATA1, GPIO_FN_CAN_DEBUGOUT4, GPIO_FN_MOUT6,
203 GPIO_FN_SSI_SDATA2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK34,
204 GPIO_FN_CAN_DEBUGOUT6, GPIO_FN_CAN0_TX_B, GPIO_FN_IERX,
205 GPIO_FN_SSI_SCK9_C, GPIO_FN_SSI_WS34, GPIO_FN_CAN_DEBUGOUT7,
206 GPIO_FN_CAN0_RX_B, GPIO_FN_IETX, GPIO_FN_SSI_WS9_C,
207 GPIO_FN_SSI_SDATA3, GPIO_FN_PWM0_C, GPIO_FN_CAN_DEBUGOUT8,
208 GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B,
209 GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C,
210 GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10,
211 GPIO_FN_SCK3, GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
212 GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_TX3_IRDA_TX, GPIO_FN_SSI_SDATA5,
213 GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_RX3_IRDA_RX,
214 GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B,
215
216 /* IPSR7 */
217 GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B,
218 GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B,
219 GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_IRQ0_B,
220 GPIO_FN_SSI_SCK9_B, GPIO_FN_HSPI_CLK1_C, GPIO_FN_SSI_WS78,
221 GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_IRQ1_B, GPIO_FN_SSI_WS9_B,
222 GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
223 GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C,
224 GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C,
225 GPIO_FN_SD0_CLK, GPIO_FN_ATACS01, GPIO_FN_SCK1_B, GPIO_FN_SD0_CMD,
226 GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO, GPIO_FN_SD0_DAT0,
227 GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST, GPIO_FN_SD0_DAT1,
228 GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS, GPIO_FN_SD0_DAT2,
229 GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK, GPIO_FN_SD0_DAT3,
230 GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI, GPIO_FN_SD0_CD,
231 GPIO_FN_DREQ2, GPIO_FN_RTS1_B_TANS_B, GPIO_FN_SD0_WP, GPIO_FN_DACK2,
232 GPIO_FN_CTS1_B,
233
234 /* IPSR8 */
235 GPIO_FN_HSPI_CLK0, GPIO_FN_CTS0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK,
236 GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
237 GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_HSPI_CS0,
238 GPIO_FN_RTS0_TANS, GPIO_FN_USB_OVC1, GPIO_FN_AD_DI,
239 GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
240 GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_HSPI_TX0,
241 GPIO_FN_TX0, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
242 GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22,
243 GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_HSPI_RX0,
244 GPIO_FN_RX0, GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
245 GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
246 GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
247 GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA,
248 GPIO_FN_VI0_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C,
249 GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_RX1_C,
250 GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B,
251 GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_MMC1_CMD, GPIO_FN_HSCK1_B,
252 GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B,
253 GPIO_FN_RTS1_C_TANS_C, GPIO_FN_RX4_D, GPIO_FN_PWMFSW0_C,
254
255 /* IPSR9 */
256 GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO,
257 GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM,
258 GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_MMC1_D0, GPIO_FN_VI0_DATA3_VI0_B3,
259 GPIO_FN_MMC1_D1, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_MMC1_D2,
260 GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_MMC1_D3, GPIO_FN_VI0_DATA6_VI0_B6,
261 GPIO_FN_MMC1_D4, GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
262 GPIO_FN_MMC1_D5, GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
263 GPIO_FN_SSI_SCK78_C, GPIO_FN_IRQ0, GPIO_FN_ARM_TRACEDATA_2,
264 GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_IRQ1,
265 GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1,
266 GPIO_FN_MMC1_D6, GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
267 GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, GPIO_FN_MMC1_D7,
268 GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4,
269 GPIO_FN_ETH_TX_EN, GPIO_FN_SD2_DAT0_B, GPIO_FN_ARM_TRACEDATA_6,
270 GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER, GPIO_FN_SD2_DAT1_B,
271 GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0,
272 GPIO_FN_SD2_DAT2_B, GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
273 GPIO_FN_ETH_RXD1, GPIO_FN_SD2_DAT3_B, GPIO_FN_ARM_TRACEDATA_9,
274
275 /* IPSR10 */
276 GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_SCK1_C, GPIO_FN_DREQ1_B,
277 GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
278 GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
279 GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
280 GPIO_FN_SD2_CLK_B, GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12,
281 GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_SD2_CMD_B, GPIO_FN_IRQ3,
282 GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
283 GPIO_FN_SD2_CD_B, GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14,
284 GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
285 GPIO_FN_SD2_WP_B, GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15,
286 GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC,
287 GPIO_FN_DREQ2_C, GPIO_FN_HSPI_TX1_B, GPIO_FN_TRACECLK,
288 GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO,
289 GPIO_FN_DACK2_C, GPIO_FN_HSPI_RX1_B, GPIO_FN_SCIF_CLK_D,
290 GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D,
291 GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4,
292 GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC,
293 GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_SSI_WS4, GPIO_FN_SIM_CLK,
294 GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3,
295
296 /* IPSR11 */
297 GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SD2_DAT0, GPIO_FN_SIM_RST,
298 GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1,
299 GPIO_FN_SD2_DAT1, GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
300 GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SD2_DAT2,
301 GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B,
302 GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SD2_DAT3, GPIO_FN_MT0_BEN,
303 GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4,
304 GPIO_FN_SD2_CLK, GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
305 GPIO_FN_HSPI_CLK1_D, GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
306 GPIO_FN_SD2_CMD, GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
307 GPIO_FN_HSPI_CS1_D, GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
308 GPIO_FN_SD2_CD, GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D,
309 GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_SD2_WP, GPIO_FN_MT0_PWM,
310 GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
311 GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2,
312 GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
313 GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_RX2,
314 GPIO_FN_HRTS0_B,
315
316 /* IPSR12 */
317 GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1,
318 GPIO_FN_SCK2, GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
319 GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B,
320 GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C,
321 GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5,
322 GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_TX4_B, GPIO_FN_SIM_D_B,
323 GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB,
324 GPIO_FN_RX4_B, GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
325 GPIO_FN_GPS_MAG, GPIO_FN_FCE, GPIO_FN_SCK4_B,
326};
327
328struct platform_device;
329
330struct r8a7779_pm_ch {
331 unsigned long chan_offs;
332 unsigned int chan_bit;
333 unsigned int isr_bit;
334};
335
336struct r8a7779_pm_domain {
337 struct generic_pm_domain genpd;
338 struct r8a7779_pm_ch ch;
339};
340
341static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d)
342{
343 return &container_of(d, struct r8a7779_pm_domain, genpd)->ch;
344}
345
346extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch);
347extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch);
348
349#ifdef CONFIG_PM
350extern struct r8a7779_pm_domain r8a7779_sh4a;
351extern struct r8a7779_pm_domain r8a7779_sgx;
352extern struct r8a7779_pm_domain r8a7779_vdp1;
353extern struct r8a7779_pm_domain r8a7779_impx3;
354
355extern void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd);
356extern void r8a7779_add_device_to_domain(struct r8a7779_pm_domain *r8a7779_pd,
357 struct platform_device *pdev);
358#else
359#define r8a7779_init_pm_domain(pd) do { } while (0)
360#define r8a7779_add_device_to_domain(pd, pdev) do { } while (0)
361#endif /* CONFIG_PM */
362
363#endif /* __ASM_R8A7779_H__ */
diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
new file mode 100644
index 000000000000..272c84c20c83
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-r8a7740.c
@@ -0,0 +1,631 @@
1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26#include <linux/sh_intc.h>
27#include <mach/intc.h>
28#include <asm/mach-types.h>
29#include <asm/mach/arch.h>
30
31/*
32 * INTCA
33 */
34enum {
35 UNUSED_INTCA = 0,
36
37 /* interrupt sources INTCA */
38 DIRC,
39 ATAPI,
40 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI,
41 AP_ARM_COMMTX, AP_ARM_COMMRX,
42 MFI, MFIS,
43 BBIF1, BBIF2,
44 USBHSDMAC,
45 USBF_OUL_SOF, USBF_IXL_INT,
46 SGX540,
47 CMT1_0, CMT1_1, CMT1_2, CMT1_3,
48 CMT2,
49 CMT3,
50 KEYSC,
51 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
52 MSIOF2, MSIOF1,
53 SCIFA4, SCIFA5, SCIFB,
54 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
55 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3,
56 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3,
57 AP_ARM_L2CINT,
58 IRDA,
59 TPU0,
60 SCIFA6, SCIFA7,
61 GbEther,
62 ICBS0,
63 DDM,
64 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3,
65 RWDT0,
66 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
67 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
68 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
69 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
70 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
71 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
72 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
73 USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND,
74 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF,
75 SPU2_0, SPU2_1,
76 FSI, FMSI,
77 IPMMU,
78 AP_ARM_CTIIRQ, AP_ARM_PMURQ,
79 MFIS2,
80 CPORTR2S,
81 CMT14, CMT15,
82 MMCIF_0, MMCIF_1, MMCIF_2,
83 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
84 STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4,
85
86 /* interrupt groups INTCA */
87 DMAC1_1, DMAC1_2,
88 DMAC2_1, DMAC2_2,
89 DMAC3_1, DMAC3_2,
90 AP_ARM1, AP_ARM2,
91 SDHI0, SDHI1, SDHI2,
92 SHWYSTAT,
93 USBF, USBH1, USBH2,
94 RSPI, SPU2, FLCTL, IIC1,
95};
96
97static struct intc_vect intca_vectors[] __initdata = {
98 INTC_VECT(DIRC, 0x0560),
99 INTC_VECT(ATAPI, 0x05E0),
100 INTC_VECT(IIC1_ALI, 0x0780),
101 INTC_VECT(IIC1_TACKI, 0x07A0),
102 INTC_VECT(IIC1_WAITI, 0x07C0),
103 INTC_VECT(IIC1_DTEI, 0x07E0),
104 INTC_VECT(AP_ARM_COMMTX, 0x0840),
105 INTC_VECT(AP_ARM_COMMRX, 0x0860),
106 INTC_VECT(MFI, 0x0900),
107 INTC_VECT(MFIS, 0x0920),
108 INTC_VECT(BBIF1, 0x0940),
109 INTC_VECT(BBIF2, 0x0960),
110 INTC_VECT(USBHSDMAC, 0x0A00),
111 INTC_VECT(USBF_OUL_SOF, 0x0A20),
112 INTC_VECT(USBF_IXL_INT, 0x0A40),
113 INTC_VECT(SGX540, 0x0A60),
114 INTC_VECT(CMT1_0, 0x0B00),
115 INTC_VECT(CMT1_1, 0x0B20),
116 INTC_VECT(CMT1_2, 0x0B40),
117 INTC_VECT(CMT1_3, 0x0B60),
118 INTC_VECT(CMT2, 0x0B80),
119 INTC_VECT(CMT3, 0x0BA0),
120 INTC_VECT(KEYSC, 0x0BE0),
121 INTC_VECT(SCIFA0, 0x0C00),
122 INTC_VECT(SCIFA1, 0x0C20),
123 INTC_VECT(SCIFA2, 0x0C40),
124 INTC_VECT(SCIFA3, 0x0C60),
125 INTC_VECT(MSIOF2, 0x0C80),
126 INTC_VECT(MSIOF1, 0x0D00),
127 INTC_VECT(SCIFA4, 0x0D20),
128 INTC_VECT(SCIFA5, 0x0D40),
129 INTC_VECT(SCIFB, 0x0D60),
130 INTC_VECT(FLCTL_FLSTEI, 0x0D80),
131 INTC_VECT(FLCTL_FLTENDI, 0x0DA0),
132 INTC_VECT(FLCTL_FLTREQ0I, 0x0DC0),
133 INTC_VECT(FLCTL_FLTREQ1I, 0x0DE0),
134 INTC_VECT(SDHI0_0, 0x0E00),
135 INTC_VECT(SDHI0_1, 0x0E20),
136 INTC_VECT(SDHI0_2, 0x0E40),
137 INTC_VECT(SDHI0_3, 0x0E60),
138 INTC_VECT(SDHI1_0, 0x0E80),
139 INTC_VECT(SDHI1_1, 0x0EA0),
140 INTC_VECT(SDHI1_2, 0x0EC0),
141 INTC_VECT(SDHI1_3, 0x0EE0),
142 INTC_VECT(AP_ARM_L2CINT, 0x0FA0),
143 INTC_VECT(IRDA, 0x0480),
144 INTC_VECT(TPU0, 0x04A0),
145 INTC_VECT(SCIFA6, 0x04C0),
146 INTC_VECT(SCIFA7, 0x04E0),
147 INTC_VECT(GbEther, 0x0500),
148 INTC_VECT(ICBS0, 0x0540),
149 INTC_VECT(DDM, 0x1140),
150 INTC_VECT(SDHI2_0, 0x1200),
151 INTC_VECT(SDHI2_1, 0x1220),
152 INTC_VECT(SDHI2_2, 0x1240),
153 INTC_VECT(SDHI2_3, 0x1260),
154 INTC_VECT(RWDT0, 0x1280),
155 INTC_VECT(DMAC1_1_DEI0, 0x2000),
156 INTC_VECT(DMAC1_1_DEI1, 0x2020),
157 INTC_VECT(DMAC1_1_DEI2, 0x2040),
158 INTC_VECT(DMAC1_1_DEI3, 0x2060),
159 INTC_VECT(DMAC1_2_DEI4, 0x2080),
160 INTC_VECT(DMAC1_2_DEI5, 0x20A0),
161 INTC_VECT(DMAC1_2_DADERR, 0x20C0),
162 INTC_VECT(DMAC2_1_DEI0, 0x2100),
163 INTC_VECT(DMAC2_1_DEI1, 0x2120),
164 INTC_VECT(DMAC2_1_DEI2, 0x2140),
165 INTC_VECT(DMAC2_1_DEI3, 0x2160),
166 INTC_VECT(DMAC2_2_DEI4, 0x2180),
167 INTC_VECT(DMAC2_2_DEI5, 0x21A0),
168 INTC_VECT(DMAC2_2_DADERR, 0x21C0),
169 INTC_VECT(DMAC3_1_DEI0, 0x2200),
170 INTC_VECT(DMAC3_1_DEI1, 0x2220),
171 INTC_VECT(DMAC3_1_DEI2, 0x2240),
172 INTC_VECT(DMAC3_1_DEI3, 0x2260),
173 INTC_VECT(DMAC3_2_DEI4, 0x2280),
174 INTC_VECT(DMAC3_2_DEI5, 0x22A0),
175 INTC_VECT(DMAC3_2_DADERR, 0x22C0),
176 INTC_VECT(SHWYSTAT_RT, 0x1300),
177 INTC_VECT(SHWYSTAT_HS, 0x1320),
178 INTC_VECT(SHWYSTAT_COM, 0x1340),
179 INTC_VECT(USBH_INT, 0x1540),
180 INTC_VECT(USBH_OHCI, 0x1560),
181 INTC_VECT(USBH_EHCI, 0x1580),
182 INTC_VECT(USBH_PME, 0x15A0),
183 INTC_VECT(USBH_BIND, 0x15C0),
184 INTC_VECT(RSPI_OVRF, 0x1780),
185 INTC_VECT(RSPI_SPTEF, 0x17A0),
186 INTC_VECT(RSPI_SPRF, 0x17C0),
187 INTC_VECT(SPU2_0, 0x1800),
188 INTC_VECT(SPU2_1, 0x1820),
189 INTC_VECT(FSI, 0x1840),
190 INTC_VECT(FMSI, 0x1860),
191 INTC_VECT(IPMMU, 0x1920),
192 INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
193 INTC_VECT(AP_ARM_PMURQ, 0x19A0),
194 INTC_VECT(MFIS2, 0x1A00),
195 INTC_VECT(CPORTR2S, 0x1A20),
196 INTC_VECT(CMT14, 0x1A40),
197 INTC_VECT(CMT15, 0x1A60),
198 INTC_VECT(MMCIF_0, 0x1AA0),
199 INTC_VECT(MMCIF_1, 0x1AC0),
200 INTC_VECT(MMCIF_2, 0x1AE0),
201 INTC_VECT(SIM_ERI, 0x1C00),
202 INTC_VECT(SIM_RXI, 0x1C20),
203 INTC_VECT(SIM_TXI, 0x1C40),
204 INTC_VECT(SIM_TEI, 0x1C60),
205 INTC_VECT(STPRO_0, 0x1C80),
206 INTC_VECT(STPRO_1, 0x1CA0),
207 INTC_VECT(STPRO_2, 0x1CC0),
208 INTC_VECT(STPRO_3, 0x1CE0),
209 INTC_VECT(STPRO_4, 0x1D00),
210};
211
212static struct intc_group intca_groups[] __initdata = {
213 INTC_GROUP(DMAC1_1,
214 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
215 INTC_GROUP(DMAC1_2,
216 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR),
217 INTC_GROUP(DMAC2_1,
218 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
219 INTC_GROUP(DMAC2_2,
220 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR),
221 INTC_GROUP(DMAC3_1,
222 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
223 INTC_GROUP(DMAC3_2,
224 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR),
225 INTC_GROUP(AP_ARM1,
226 AP_ARM_COMMTX, AP_ARM_COMMRX),
227 INTC_GROUP(AP_ARM2,
228 AP_ARM_CTIIRQ, AP_ARM_PMURQ),
229 INTC_GROUP(USBF,
230 USBF_OUL_SOF, USBF_IXL_INT),
231 INTC_GROUP(SDHI0,
232 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3),
233 INTC_GROUP(SDHI1,
234 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3),
235 INTC_GROUP(SDHI2,
236 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3),
237 INTC_GROUP(SHWYSTAT,
238 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
239 INTC_GROUP(USBH1, /* FIXME */
240 USBH_INT, USBH_OHCI),
241 INTC_GROUP(USBH2, /* FIXME */
242 USBH_EHCI,
243 USBH_PME, USBH_BIND),
244 INTC_GROUP(RSPI,
245 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF),
246 INTC_GROUP(SPU2,
247 SPU2_0, SPU2_1),
248 INTC_GROUP(FLCTL,
249 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
250 INTC_GROUP(IIC1,
251 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI),
252};
253
254static struct intc_mask_reg intca_mask_registers[] __initdata = {
255 { /* IMR0A / IMCR0A */ 0xe6940080, 0xe69400c0, 8,
256 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
257 0, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
258 { /* IMR1A / IMCR1A */ 0xe6940084, 0xe69400c4, 8,
259 { ATAPI, 0, DIRC, 0,
260 DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
261 { /* IMR2A / IMCR2A */ 0xe6940088, 0xe69400c8, 8,
262 { 0, 0, 0, 0,
263 BBIF1, BBIF2, MFIS, MFI } },
264 { /* IMR3A / IMCR3A */ 0xe694008c, 0xe69400cc, 8,
265 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
266 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
267 { /* IMR4A / IMCR4A */ 0xe6940090, 0xe69400d0, 8,
268 { DDM, 0, 0, 0,
269 0, 0, 0, 0 } },
270 { /* IMR5A / IMCR5A */ 0xe6940094, 0xe69400d4, 8,
271 { KEYSC, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
272 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
273 { /* IMR6A / IMCR6A */ 0xe6940098, 0xe69400d8, 8,
274 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
275 0, 0, MSIOF2, 0 } },
276 { /* IMR7A / IMCR7A */ 0xe694009c, 0xe69400dc, 8,
277 { SDHI0_3, SDHI0_2, SDHI0_1, SDHI0_0,
278 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
279 { /* IMR8A / IMCR8A */ 0xe69400a0, 0xe69400e0, 8,
280 { SDHI1_3, SDHI1_2, SDHI1_1, SDHI1_0,
281 0, USBHSDMAC, 0, AP_ARM_L2CINT } },
282 { /* IMR9A / IMCR9A */ 0xe69400a4, 0xe69400e4, 8,
283 { CMT1_3, CMT1_2, CMT1_1, CMT1_0,
284 CMT2, USBF_IXL_INT, USBF_OUL_SOF, SGX540 } },
285 { /* IMR10A / IMCR10A */ 0xe69400a8, 0xe69400e8, 8,
286 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
287 0, 0, 0, 0 } },
288 { /* IMR11A / IMCR11A */ 0xe69400ac, 0xe69400ec, 8,
289 { IIC1_DTEI, IIC1_WAITI, IIC1_TACKI, IIC1_ALI,
290 ICBS0, 0, 0, 0 } },
291 { /* IMR12A / IMCR12A */ 0xe69400b0, 0xe69400f0, 8,
292 { 0, 0, TPU0, SCIFA6,
293 SCIFA7, GbEther, 0, 0 } },
294 { /* IMR13A / IMCR13A */ 0xe69400b4, 0xe69400f4, 8,
295 { SDHI2_3, SDHI2_2, SDHI2_1, SDHI2_0,
296 0, CMT3, 0, RWDT0 } },
297 { /* IMR0A3 / IMCR0A3 */ 0xe6950080, 0xe69500c0, 8,
298 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
299 0, 0, 0, 0 } },
300 /* IMR1A3 / IMCR1A3 */
301 { /* IMR2A3 / IMCR2A3 */ 0xe6950088, 0xe69500c8, 8,
302 { 0, 0, USBH_INT, USBH_OHCI,
303 USBH_EHCI, USBH_PME, USBH_BIND, 0 } },
304 /* IMR3A3 / IMCR3A3 */
305 { /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8,
306 { 0, 0, 0, 0,
307 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } },
308 { /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8,
309 { SPU2_0, SPU2_1, FSI, FMSI,
310 0, 0, 0, 0 } },
311 { /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8,
312 { 0, IPMMU, 0, 0,
313 AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } },
314 { /* IMR7A3 / IMCR7A3 */ 0xe695009c, 0xe69500dc, 8,
315 { MFIS2, CPORTR2S, CMT14, CMT15,
316 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
317 /* IMR8A3 / IMCR8A3 */
318 { /* IMR9A3 / IMCR9A3 */ 0xe69500a4, 0xe69500e4, 8,
319 { SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
320 STPRO_0, STPRO_1, STPRO_2, STPRO_3 } },
321 { /* IMR10A3 / IMCR10A3 */ 0xe69500a8, 0xe69500e8, 8,
322 { STPRO_4, 0, 0, 0,
323 0, 0, 0, 0 } },
324};
325
326static struct intc_prio_reg intca_prio_registers[] __initdata = {
327 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, ICBS0 } },
328 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
329 { 0xe6940008, 0, 16, 4, /* IPRCA */ { ATAPI, 0, CMT1_1, AP_ARM1 } },
330 { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_2, 0 } },
331 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFIS, MFI, USBF } },
332 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC, DMAC1_2,
333 SGX540, CMT1_0 } },
334 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
335 SCIFA2, SCIFA3 } },
336 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC,
337 FLCTL, SDHI0 } },
338 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } },
339 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
340 AP_ARM_L2CINT, 0 } },
341 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_3, 0, SDHI1 } },
342 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, SCIFA6,
343 SCIFA7, GbEther } },
344 { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
345 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
346 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
347 { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
348 /* IPRBA3 */
349 /* IPRCA3 */
350 /* IPRDA3 */
351 { 0xe6950010, 0, 16, 4, /* IPREA3 */ { USBH1, 0, 0, 0 } },
352 { 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } },
353 /* IPRGA3 */
354 /* IPRHA3 */
355 /* IPRIA3 */
356 { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } },
357 { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
358 /* IPRLA3 */
359 { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } },
360 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
361 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
362 CMT14, CMT15 } },
363 { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
364 /* IPRQA3 */
365 /* IPRRA3 */
366 { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { SIM_ERI, SIM_RXI,
367 SIM_TXI, SIM_TEI } },
368 { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { STPRO_0, STPRO_1,
369 STPRO_2, STPRO_3 } },
370 { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { STPRO_4, 0, 0, 0 } },
371};
372
373static DECLARE_INTC_DESC(intca_desc, "r8a7740-intca",
374 intca_vectors, intca_groups,
375 intca_mask_registers, intca_prio_registers,
376 NULL);
377
378INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
379 INTC_VECT, "r8a7740-intca-irq-pins");
380
381
382/*
383 * INTCS
384 */
385enum {
386 UNUSED_INTCS = 0,
387
388 INTCS,
389
390 /* interrupt sources INTCS */
391
392 /* HUDI */
393 /* STPRO */
394 /* RTDMAC(1) */
395 VPU5HA2,
396 _2DG_TRAP, _2DG_GPM_INT, _2DG_CER_INT,
397 /* MFI */
398 /* BBIF2 */
399 VPU5F,
400 _2DG_BRK_INT,
401 /* SGX540 */
402 /* 2DDMAC */
403 /* IPMMU */
404 /* RTDMAC 2 */
405 /* KEYSC */
406 /* MSIOF */
407 IIC0_ALI, IIC0_TACKI, IIC0_WAITI, IIC0_DTEI,
408 TMU0_0, TMU0_1, TMU0_2,
409 CMT0,
410 /* CMT2 */
411 LMB,
412 CTI,
413 VOU,
414 /* RWDT0 */
415 ICB,
416 VIO6C,
417 CEU20, CEU21,
418 JPU,
419 LCDC0,
420 LCRC,
421 /* RTDMAC2(1) */
422 /* RTDMAC2(2) */
423 LCDC1,
424 /* SPU2 */
425 /* FSI */
426 /* FMSI */
427 TMU1_0, TMU1_1, TMU1_2,
428 CMT4,
429 DISP,
430 DSRV,
431 /* MFIS2 */
432 CPORTS2R,
433
434 /* interrupt groups INTCS */
435 _2DG1,
436 IIC0, TMU1,
437};
438
439static struct intc_vect intcs_vectors[] = {
440 /* HUDI */
441 /* STPRO */
442 /* RTDMAC(1) */
443 INTCS_VECT(VPU5HA2, 0x0880),
444 INTCS_VECT(_2DG_TRAP, 0x08A0),
445 INTCS_VECT(_2DG_GPM_INT, 0x08C0),
446 INTCS_VECT(_2DG_CER_INT, 0x08E0),
447 /* MFI */
448 /* BBIF2 */
449 INTCS_VECT(VPU5F, 0x0980),
450 INTCS_VECT(_2DG_BRK_INT, 0x09A0),
451 /* SGX540 */
452 /* 2DDMAC */
453 /* IPMMU */
454 /* RTDMAC(2) */
455 /* KEYSC */
456 /* MSIOF */
457 INTCS_VECT(IIC0_ALI, 0x0E00),
458 INTCS_VECT(IIC0_TACKI, 0x0E20),
459 INTCS_VECT(IIC0_WAITI, 0x0E40),
460 INTCS_VECT(IIC0_DTEI, 0x0E60),
461 INTCS_VECT(TMU0_0, 0x0E80),
462 INTCS_VECT(TMU0_1, 0x0EA0),
463 INTCS_VECT(TMU0_2, 0x0EC0),
464 INTCS_VECT(CMT0, 0x0F00),
465 /* CMT2 */
466 INTCS_VECT(LMB, 0x0F60),
467 INTCS_VECT(CTI, 0x0400),
468 INTCS_VECT(VOU, 0x0420),
469 /* RWDT0 */
470 INTCS_VECT(ICB, 0x0480),
471 INTCS_VECT(VIO6C, 0x04E0),
472 INTCS_VECT(CEU20, 0x0500),
473 INTCS_VECT(CEU21, 0x0520),
474 INTCS_VECT(JPU, 0x0560),
475 INTCS_VECT(LCDC0, 0x0580),
476 INTCS_VECT(LCRC, 0x05A0),
477 /* RTDMAC2(1) */
478 /* RTDMAC2(2) */
479 INTCS_VECT(LCDC1, 0x1780),
480 /* SPU2 */
481 /* FSI */
482 /* FMSI */
483 INTCS_VECT(TMU1_0, 0x1900),
484 INTCS_VECT(TMU1_1, 0x1920),
485 INTCS_VECT(TMU1_2, 0x1940),
486 INTCS_VECT(CMT4, 0x1980),
487 INTCS_VECT(DISP, 0x19A0),
488 INTCS_VECT(DSRV, 0x19C0),
489 /* MFIS2 */
490 INTCS_VECT(CPORTS2R, 0x1A20),
491
492 INTC_VECT(INTCS, 0xf80),
493};
494
495static struct intc_group intcs_groups[] __initdata = {
496 INTC_GROUP(_2DG1, /*FIXME*/
497 _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP),
498 INTC_GROUP(IIC0,
499 IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI),
500 INTC_GROUP(TMU1,
501 TMU1_0, TMU1_1, TMU1_2),
502};
503
504static struct intc_mask_reg intcs_mask_registers[] = {
505 /* IMR0SA / IMCR0SA */ /* all 0 */
506 { /* IMR1SA / IMCR1SA */ 0xffd20184, 0xffd201c4, 8,
507 { _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP, VPU5HA2,
508 0, 0, 0, 0 /*STPRO*/ } },
509 { /* IMR2SA / IMCR2SA */ 0xffd20188, 0xffd201c8, 8,
510 { 0/*STPRO*/, 0, CEU21, VPU5F,
511 0/*BBIF2*/, 0, 0, 0/*MFI*/ } },
512 { /* IMR3SA / IMCR3SA */ 0xffd2018c, 0xffd201cc, 8,
513 { 0, 0, 0, 0, /*2DDMAC*/
514 VIO6C, 0, 0, ICB } },
515 { /* IMR4SA / IMCR4SA */ 0xffd20190, 0xffd201d0, 8,
516 { 0, 0, VOU, CTI,
517 JPU, 0, LCRC, LCDC0 } },
518 /* IMR5SA / IMCR5SA */ /*KEYSC/RTDMAC2/RTDMAC1*/
519 /* IMR6SA / IMCR6SA */ /*MSIOF/SGX540*/
520 { /* IMR7SA / IMCR7SA */ 0xffd2019c, 0xffd201dc, 8,
521 { 0, TMU0_2, TMU0_1, TMU0_0,
522 0, 0, 0, 0 } },
523 { /* IMR8SA / IMCR8SA */ 0xffd201a0, 0xffd201e0, 8,
524 { 0, 0, 0, 0,
525 CEU20, 0, 0, 0 } },
526 { /* IMR9SA / IMCR9SA */ 0xffd201a4, 0xffd201e4, 8,
527 { 0, 0/*RWDT0*/, 0/*CMT2*/, CMT0,
528 0, 0, 0, 0 } },
529 /* IMR10SA / IMCR10SA */ /*IPMMU*/
530 { /* IMR11SA / IMCR11SA */ 0xffd201ac, 0xffd201ec, 8,
531 { IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI,
532 0, _2DG_BRK_INT, LMB, 0 } },
533 /* IMR12SA / IMCR12SA */
534 /* IMR13SA / IMCR13SA */
535 /* IMR0SA3 / IMCR0SA3 */ /*RTDMAC2(1)/RTDMAC2(2)*/
536 /* IMR1SA3 / IMCR1SA3 */
537 /* IMR2SA3 / IMCR2SA3 */
538 /* IMR3SA3 / IMCR3SA3 */
539 { /* IMR4SA3 / IMCR4SA3 */ 0xffd50190, 0xffd501d0, 8,
540 { 0, 0, 0, 0,
541 LCDC1, 0, 0, 0 } },
542 /* IMR5SA3 / IMCR5SA3 */ /* SPU2/FSI/FMSI */
543 { /* IMR6SA3 / IMCR6SA3 */ 0xffd50198, 0xffd501d8, 8,
544 { TMU1_0, TMU1_1, TMU1_2, 0,
545 CMT4, DISP, DSRV, 0 } },
546 { /* IMR7SA3 / IMCR7SA3 */ 0xffd5019c, 0xffd501dc, 8,
547 { 0/*MFIS2*/, CPORTS2R, 0, 0,
548 0, 0, 0, 0 } },
549 { /* INTAMASK */ 0xffd20104, 0, 16,
550 { 0, 0, 0, 0, 0, 0, 0, 0,
551 0, 0, 0, 0, 0, 0, 0, INTCS } },
552};
553
554/* Priority is needed for INTCA to receive the INTCS interrupt */
555static struct intc_prio_reg intcs_prio_registers[] = {
556 { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, VOU, 0/*2DDMAC*/, ICB } },
557 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU, LCDC0, 0, LCRC } },
558 /* IPRCS */ /*BBIF2*/
559 /* IPRDS */
560 { 0xffd20010, 0, 16, 4, /* IPRES */ { 0/*RTDMAC(1)*/, VPU5HA2,
561 0/*MFI*/, VPU5F } },
562 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0/*KEYSC*/, 0/*RTDMAC(2)*/,
563 0/*CMT2*/, CMT0 } },
564 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_0, TMU0_1,
565 TMU0_2, _2DG1 } },
566 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0/*STPRO*/, 0/*STPRO*/,
567 _2DG_BRK_INT/*FIXME*/ } },
568 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, 0/*MSIOF*/, 0, IIC0 } },
569 { 0xffd20024, 0, 16, 4, /* IPRJS */ { CEU20, 0/*SGX540*/, 0, 0 } },
570 { 0xffd20028, 0, 16, 4, /* IPRKS */ { VIO6C, 0, LMB, 0 } },
571 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { 0/*IPMMU*/, 0, CEU21, 0 } },
572 /* IPRMS */ /*RWDT0*/
573 /* IPRAS3 */ /*RTDMAC2(1)*/
574 /* IPRBS3 */ /*RTDMAC2(2)*/
575 /* IPRCS3 */
576 /* IPRDS3 */
577 /* IPRES3 */
578 /* IPRFS3 */
579 /* IPRGS3 */
580 /* IPRHS3 */
581 /* IPRIS3 */
582 { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, 0, 0, 0 } },
583 /* IPRKS3 */ /*SPU2/FSI/FMSi*/
584 /* IPRLS3 */
585 { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
586 { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DISP, DSRV, 0 } },
587 { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0/*MFIS2*/, CPORTS2R, 0, 0 } },
588 /* IPRPS3 */
589};
590
591static struct resource intcs_resources[] __initdata = {
592 [0] = {
593 .start = 0xffd20000,
594 .end = 0xffd201ff,
595 .flags = IORESOURCE_MEM,
596 },
597 [1] = {
598 .start = 0xffd50000,
599 .end = 0xffd501ff,
600 .flags = IORESOURCE_MEM,
601 }
602};
603
604static struct intc_desc intcs_desc __initdata = {
605 .name = "r8a7740-intcs",
606 .resource = intcs_resources,
607 .num_resources = ARRAY_SIZE(intcs_resources),
608 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
609 intcs_prio_registers, NULL, NULL),
610};
611
612static void intcs_demux(unsigned int irq, struct irq_desc *desc)
613{
614 void __iomem *reg = (void *)irq_get_handler_data(irq);
615 unsigned int evtcodeas = ioread32(reg);
616
617 generic_handle_irq(intcs_evt2irq(evtcodeas));
618}
619
620void __init r8a7740_init_irq(void)
621{
622 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
623
624 register_intc_controller(&intca_desc);
625 register_intc_controller(&intca_irq_pins_desc);
626 register_intc_controller(&intcs_desc);
627
628 /* demux using INTEVTSA */
629 irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
630 irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
631}
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
new file mode 100644
index 000000000000..5d92fcde2bc3
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -0,0 +1,58 @@
1/*
2 * r8a7779 processor support - INTC hardware block
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/io.h>
25#include <mach/common.h>
26#include <mach/intc.h>
27#include <mach/r8a7779.h>
28#include <asm/hardware/gic.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31
32#define INT2SMSKCR0 0xfe7822a0
33#define INT2SMSKCR1 0xfe7822a4
34#define INT2SMSKCR2 0xfe7822a8
35#define INT2SMSKCR3 0xfe7822ac
36#define INT2SMSKCR4 0xfe7822b0
37
38static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
39{
40 return 0; /* always allow wakeup */
41}
42
43void __init r8a7779_init_irq(void)
44{
45 void __iomem *gic_dist_base = __io(0xf0001000);
46 void __iomem *gic_cpu_base = __io(0xf0000100);
47
48 /* use GIC to handle interrupts */
49 gic_init(0, 29, gic_dist_base, gic_cpu_base);
50 gic_arch_extn.irq_set_wake = r8a7779_set_wake;
51
52 /* unmask all known interrupts in INTCS2 */
53 __raw_writel(0xfffffff0, INT2SMSKCR0);
54 __raw_writel(0xfff7ffff, INT2SMSKCR1);
55 __raw_writel(0xfffbffdf, INT2SMSKCR2);
56 __raw_writel(0xbffffffc, INT2SMSKCR3);
57 __raw_writel(0x003fee3f, INT2SMSKCR4);
58}
diff --git a/arch/arm/mach-shmobile/pfc-r8a7740.c b/arch/arm/mach-shmobile/pfc-r8a7740.c
new file mode 100644
index 000000000000..a4fff6950b03
--- /dev/null
+++ b/arch/arm/mach-shmobile/pfc-r8a7740.c
@@ -0,0 +1,2562 @@
1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/gpio.h>
24#include <mach/r8a7740.h>
25
26#define CPU_ALL_PORT(fn, pfx, sfx) \
27 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
28 PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
29 PORT_10(fn, pfx##20, sfx), \
30 PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx)
31
32enum {
33 PINMUX_RESERVED = 0,
34
35 /* PORT0_DATA -> PORT211_DATA */
36 PINMUX_DATA_BEGIN,
37 PORT_ALL(DATA),
38 PINMUX_DATA_END,
39
40 /* PORT0_IN -> PORT211_IN */
41 PINMUX_INPUT_BEGIN,
42 PORT_ALL(IN),
43 PINMUX_INPUT_END,
44
45 /* PORT0_IN_PU -> PORT211_IN_PU */
46 PINMUX_INPUT_PULLUP_BEGIN,
47 PORT_ALL(IN_PU),
48 PINMUX_INPUT_PULLUP_END,
49
50 /* PORT0_IN_PD -> PORT211_IN_PD */
51 PINMUX_INPUT_PULLDOWN_BEGIN,
52 PORT_ALL(IN_PD),
53 PINMUX_INPUT_PULLDOWN_END,
54
55 /* PORT0_OUT -> PORT211_OUT */
56 PINMUX_OUTPUT_BEGIN,
57 PORT_ALL(OUT),
58 PINMUX_OUTPUT_END,
59
60 PINMUX_FUNCTION_BEGIN,
61 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
62 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
63 PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
64 PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
65 PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
66 PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
67 PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
68 PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
69 PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
70 PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
71
72 MSEL1CR_31_0, MSEL1CR_31_1,
73 MSEL1CR_30_0, MSEL1CR_30_1,
74 MSEL1CR_29_0, MSEL1CR_29_1,
75 MSEL1CR_28_0, MSEL1CR_28_1,
76 MSEL1CR_27_0, MSEL1CR_27_1,
77 MSEL1CR_26_0, MSEL1CR_26_1,
78 MSEL1CR_16_0, MSEL1CR_16_1,
79 MSEL1CR_15_0, MSEL1CR_15_1,
80 MSEL1CR_14_0, MSEL1CR_14_1,
81 MSEL1CR_13_0, MSEL1CR_13_1,
82 MSEL1CR_12_0, MSEL1CR_12_1,
83 MSEL1CR_9_0, MSEL1CR_9_1,
84 MSEL1CR_7_0, MSEL1CR_7_1,
85 MSEL1CR_6_0, MSEL1CR_6_1,
86 MSEL1CR_5_0, MSEL1CR_5_1,
87 MSEL1CR_4_0, MSEL1CR_4_1,
88 MSEL1CR_3_0, MSEL1CR_3_1,
89 MSEL1CR_2_0, MSEL1CR_2_1,
90 MSEL1CR_0_0, MSEL1CR_0_1,
91
92 MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
93 MSEL3CR_6_0, MSEL3CR_6_1,
94
95 MSEL4CR_19_0, MSEL4CR_19_1,
96 MSEL4CR_18_0, MSEL4CR_18_1,
97 MSEL4CR_15_0, MSEL4CR_15_1,
98 MSEL4CR_10_0, MSEL4CR_10_1,
99 MSEL4CR_6_0, MSEL4CR_6_1,
100 MSEL4CR_4_0, MSEL4CR_4_1,
101 MSEL4CR_1_0, MSEL4CR_1_1,
102
103 MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
104 MSEL5CR_30_0, MSEL5CR_30_1,
105 MSEL5CR_29_0, MSEL5CR_29_1,
106 MSEL5CR_27_0, MSEL5CR_27_1,
107 MSEL5CR_25_0, MSEL5CR_25_1,
108 MSEL5CR_23_0, MSEL5CR_23_1,
109 MSEL5CR_21_0, MSEL5CR_21_1,
110 MSEL5CR_19_0, MSEL5CR_19_1,
111 MSEL5CR_17_0, MSEL5CR_17_1,
112 MSEL5CR_15_0, MSEL5CR_15_1,
113 MSEL5CR_14_0, MSEL5CR_14_1,
114 MSEL5CR_13_0, MSEL5CR_13_1,
115 MSEL5CR_12_0, MSEL5CR_12_1,
116 MSEL5CR_11_0, MSEL5CR_11_1,
117 MSEL5CR_10_0, MSEL5CR_10_1,
118 MSEL5CR_8_0, MSEL5CR_8_1,
119 MSEL5CR_7_0, MSEL5CR_7_1,
120 MSEL5CR_6_0, MSEL5CR_6_1,
121 MSEL5CR_5_0, MSEL5CR_5_1,
122 MSEL5CR_4_0, MSEL5CR_4_1,
123 MSEL5CR_3_0, MSEL5CR_3_1,
124 MSEL5CR_2_0, MSEL5CR_2_1,
125 MSEL5CR_0_0, MSEL5CR_0_1,
126 PINMUX_FUNCTION_END,
127
128 PINMUX_MARK_BEGIN,
129
130 /* IRQ */
131 IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
132 IRQ1_MARK,
133 IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
134 IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
135 IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
136 IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
137 IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
138 IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
139 IRQ8_MARK,
140 IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
141 IRQ10_MARK,
142 IRQ11_MARK,
143 IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
144 IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
145 IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
146 IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
147 IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
148 IRQ17_MARK,
149 IRQ18_MARK,
150 IRQ19_MARK,
151 IRQ20_MARK,
152 IRQ21_MARK,
153 IRQ22_MARK,
154 IRQ23_MARK,
155 IRQ24_MARK,
156 IRQ25_MARK,
157 IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
158 IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
159 IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
160 IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
161 IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
162 IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
163
164 /* Function */
165
166 /* DBGT */
167 DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
168 DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
169 DBGMD21_MARK,
170
171 /* FSI */
172 FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
173 FSIAISLD_PORT5_MARK,
174 FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
175 FSIASPDIF_PORT18_MARK,
176 FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
177 FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
178 FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
179
180 /* FMSI */
181 FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
182 FMSISLD_PORT6_MARK,
183 FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
184 FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
185 FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
186
187 /* SCIFA0 */
188 SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
189 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
190
191 /* SCIFA1 */
192 SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
193 SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
194
195 /* SCIFA2 */
196 SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
197 SCIFA2_SCK_PORT199_MARK,
198 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
199 SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
200
201 /* SCIFA3 */
202 SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
203 SCIFA3_SCK_PORT116_MARK,
204 SCIFA3_CTS_PORT117_MARK,
205 SCIFA3_RXD_PORT174_MARK,
206 SCIFA3_TXD_PORT175_MARK,
207
208 SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
209 SCIFA3_SCK_PORT158_MARK,
210 SCIFA3_CTS_PORT162_MARK,
211 SCIFA3_RXD_PORT159_MARK,
212 SCIFA3_TXD_PORT160_MARK,
213
214 /* SCIFA4 */
215 SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
216 SCIFA4_TXD_PORT13_MARK,
217
218 SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
219 SCIFA4_TXD_PORT203_MARK,
220
221 SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
222 SCIFA4_TXD_PORT93_MARK,
223
224 SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
225 SCIFA4_SCK_PORT205_MARK,
226
227 /* SCIFA5 */
228 SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
229 SCIFA5_RXD_PORT10_MARK,
230
231 SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
232 SCIFA5_TXD_PORT208_MARK,
233
234 SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
235 SCIFA5_RXD_PORT92_MARK,
236
237 SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
238 SCIFA5_SCK_PORT206_MARK,
239
240 /* SCIFA6 */
241 SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
242
243 /* SCIFA7 */
244 SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
245
246 /* SCIFAB */
247 SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
248 SCIFB_RXD_PORT191_MARK,
249 SCIFB_TXD_PORT192_MARK,
250 SCIFB_RTS_PORT186_MARK,
251 SCIFB_CTS_PORT187_MARK,
252
253 SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
254 SCIFB_RXD_PORT3_MARK,
255 SCIFB_TXD_PORT4_MARK,
256 SCIFB_RTS_PORT172_MARK,
257 SCIFB_CTS_PORT173_MARK,
258
259 /* LCD0 */
260 LCDC0_SELECT_MARK,
261
262 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
263 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
264 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
265 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
266 LCD0_D16_MARK, LCD0_D17_MARK,
267 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
268 LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
269 LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
270 LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
271 LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
272
273 LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
274 LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
275 LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
276 LCD0_LCLK_PORT165_MARK,
277
278 LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
279 LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
280 LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
281 LCD0_LCLK_PORT102_MARK,
282
283 /* LCD1 */
284 LCDC1_SELECT_MARK,
285
286 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
287 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
288 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
289 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
290 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
291 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
292 LCD1_DON_MARK, LCD1_VCPWC_MARK,
293 LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
294
295 LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
296 LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
297 LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
298 LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
299
300 /* RSPI */
301 RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
302 RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
303 RSPI_MISO_A_MARK,
304
305 /* VIO CKO */
306 VIO_CKO1_MARK, /* needs fixup */
307 VIO_CKO2_MARK,
308 VIO_CKO_1_MARK,
309 VIO_CKO_MARK,
310
311 /* VIO0 */
312 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
313 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
314 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
315 VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
316 VIO0_FIELD_MARK,
317
318 VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
319 VIO0_D14_PORT25_MARK,
320 VIO0_D15_PORT24_MARK,
321
322 VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
323 VIO0_D14_PORT95_MARK,
324 VIO0_D15_PORT96_MARK,
325
326 /* VIO1 */
327 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
328 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
329 VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
330
331 /* TPU0 */
332 TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
333 TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
334 TPU0TO2_PORT202_MARK,
335
336 /* SSP1 0 */
337 STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
338 STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
339 STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
340
341 /* SSP1 1 */
342 STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
343 STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
344 STP1_IPSYNC_MARK,
345
346 STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
347 STP1_IPEN_PORT187_MARK,
348
349 STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
350 STP1_IPEN_PORT193_MARK,
351
352 /* SIM */
353 SIM_RST_MARK, SIM_CLK_MARK,
354 SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
355 SIM_D_PORT199_MARK,
356
357 /* SDHI0 */
358 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
359 SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
360
361 /* SDHI1 */
362 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
363 SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
364
365 /* SDHI2 */
366 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
367 SDHI2_CLK_MARK, SDHI2_CMD_MARK,
368
369 SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
370 SDHI2_WP_PORT25_MARK,
371
372 SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
373 SDHI2_CD_PORT202_MARK,
374
375 /* MSIOF2 */
376 MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
377 MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
378 MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
379 MSIOF2_RSCK_MARK,
380
381 /* KEYSC */
382 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
383 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
384 KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
385
386 KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
387 KEYIN1_PORT44_MARK,
388 KEYIN2_PORT45_MARK,
389 KEYIN3_PORT46_MARK,
390
391 KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
392 KEYIN1_PORT57_MARK,
393 KEYIN2_PORT56_MARK,
394 KEYIN3_PORT55_MARK,
395
396 /* VOU */
397 DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
398 DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
399 DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
400 DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
401 DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
402
403 /* MEMC */
404 MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
405 MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
406 MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
407 MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
408 MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
409
410 MEMC_CS1_MARK, /* MSEL4CR_6_0 */
411 MEMC_ADV_MARK,
412 MEMC_WAIT_MARK,
413 MEMC_BUSCLK_MARK,
414
415 MEMC_A1_MARK, /* MSEL4CR_6_1 */
416 MEMC_DREQ0_MARK,
417 MEMC_DREQ1_MARK,
418 MEMC_A0_MARK,
419
420 /* MMC */
421 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
422 MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
423 MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
424 MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
425
426 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
427 MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
428 MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
429 MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
430
431 /* MSIOF0 */
432 MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
433 MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
434 MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
435 MSIOF0_TSYNC_MARK,
436
437 /* MSIOF1 */
438 MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
439 MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
440
441 MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
442 MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
443 MSIOF1_TSYNC_PORT120_MARK,
444 MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
445
446 MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
447 MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
448 MSIOF1_RXD_PORT75_MARK,
449 MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
450
451 /* GPIO */
452 GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
453
454 /* USB0 */
455 USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
456
457 /* USB1 */
458 USB1_OCI_MARK, USB1_PPON_MARK,
459
460 /* BBIF1 */
461 BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
462 BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
463 BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
464
465 /* BBIF2 */
466 BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
467 BBIF2_RXD2_PORT60_MARK,
468 BBIF2_TSYNC2_PORT6_MARK,
469 BBIF2_TSCK2_PORT59_MARK,
470
471 BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
472 BBIF2_TXD2_PORT183_MARK,
473 BBIF2_TSCK2_PORT89_MARK,
474 BBIF2_TSYNC2_PORT184_MARK,
475
476 /* BSC / FLCTL / PCMCIA */
477 CS0_MARK, CS2_MARK, CS4_MARK,
478 CS5B_MARK, CS6A_MARK,
479 CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
480 CS5A_PORT19_MARK,
481 IOIS16_MARK, /* ? */
482
483 A0_MARK, A1_MARK, A2_MARK, A3_MARK,
484 A4_FOE_MARK, /* share with FLCTL */
485 A5_FCDE_MARK, /* share with FLCTL */
486 A6_MARK, A7_MARK, A8_MARK, A9_MARK,
487 A10_MARK, A11_MARK, A12_MARK, A13_MARK,
488 A14_MARK, A15_MARK, A16_MARK, A17_MARK,
489 A18_MARK, A19_MARK, A20_MARK, A21_MARK,
490 A22_MARK, A23_MARK, A24_MARK, A25_MARK,
491 A26_MARK,
492
493 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
494 D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
495 D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
496 D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
497 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
498 D15_NAF15_MARK, /* share with FLCTL */
499 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
500 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
501 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
502 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
503
504 WE0_FWE_MARK, /* share with FLCTL */
505 WE1_MARK,
506 WE2_ICIORD_MARK, /* share with PCMCIA */
507 WE3_ICIOWR_MARK, /* share with PCMCIA */
508 CKO_MARK, BS_MARK, RDWR_MARK,
509 RD_FSC_MARK, /* share with FLCTL */
510 WAIT_PORT177_MARK, /* WAIT Port 90/177 */
511 WAIT_PORT90_MARK,
512
513 FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
514
515 /* IRDA */
516 IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
517
518 /* ATAPI */
519 IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
520 IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
521 IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
522 IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
523 IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
524 IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
525 IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
526 IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
527
528 /* RMII */
529 RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
530 RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
531 RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
532 RMII_REF50CK_MARK, /* for RMII */
533 RMII_REF125CK_MARK, /* for GMII */
534
535 /* GEther */
536 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
537 ET_ETXD2_MARK, ET_ETXD3_MARK,
538 ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
539 ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
540 ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
541 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
542 ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
543 ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
544 ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
545 ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
546
547 /* DMA0 */
548 DREQ0_MARK, DACK0_MARK,
549
550 /* DMA1 */
551 DREQ1_MARK, DACK1_MARK,
552
553 /* SYSC */
554 RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
555
556 /* IRREM */
557 IROUT_MARK,
558
559 /* SDENC */
560 SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
561
562 /* DEBUG */
563 EDEBGREQ_PULLUP_MARK, /* for JTAG */
564 EDEBGREQ_PULLDOWN_MARK,
565
566 TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
567 TRACEAUD_FROM_LCDC0_MARK,
568 TRACEAUD_FROM_MEMC_MARK,
569
570 PINMUX_MARK_END,
571};
572
573static pinmux_enum_t pinmux_data[] = {
574 /* specify valid pin states for each pin in GPIO mode */
575
576 /* I/O and Pull U/D */
577 PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
578 PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3),
579 PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5),
580 PORT_DATA_IO_PD(6), PORT_DATA_IO(7),
581 PORT_DATA_IO(8), PORT_DATA_IO(9),
582
583 PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11),
584 PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13),
585 PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15),
586 PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17),
587 PORT_DATA_IO(18), PORT_DATA_IO_PU(19),
588
589 PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21),
590 PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23),
591 PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25),
592 PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27),
593 PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29),
594
595 PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31),
596 PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33),
597 PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35),
598 PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37),
599 PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39),
600
601 PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41),
602 PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43),
603 PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45),
604 PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47),
605 PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49),
606
607 PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51),
608 PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53),
609 PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55),
610 PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57),
611 PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59),
612
613 PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61),
614 PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
615 PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
616 PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
617 PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
618
619 PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
620 PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
621 PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75),
622 PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
623 PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
624
625 PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
626 PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83),
627 PORT_DATA_IO(84), PORT_DATA_IO_PD(85),
628 PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87),
629 PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89),
630
631 PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91),
632 PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93),
633 PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95),
634 PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
635 PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),
636
637 PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101),
638 PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103),
639 PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105),
640 PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107),
641 PORT_DATA_IO(108), PORT_DATA_IO(109),
642
643 PORT_DATA_IO(110), PORT_DATA_IO(111),
644 PORT_DATA_IO(112), PORT_DATA_IO(113),
645 PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115),
646 PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117),
647 PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119),
648
649 PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121),
650 PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123),
651 PORT_DATA_IO_PD(124), PORT_DATA_IO(125),
652 PORT_DATA_IO(126), PORT_DATA_IO(127),
653 PORT_DATA_IO(128), PORT_DATA_IO(129),
654
655 PORT_DATA_IO(130), PORT_DATA_IO(131),
656 PORT_DATA_IO(132), PORT_DATA_IO(133),
657 PORT_DATA_IO(134), PORT_DATA_IO(135),
658 PORT_DATA_IO(136), PORT_DATA_IO(137),
659 PORT_DATA_IO(138), PORT_DATA_IO(139),
660
661 PORT_DATA_IO(140), PORT_DATA_IO(141),
662 PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143),
663 PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145),
664 PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147),
665 PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149),
666
667 PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151),
668 PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153),
669 PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155),
670 PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157),
671 PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159),
672
673 PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161),
674 PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163),
675 PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165),
676 PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167),
677 PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169),
678
679 PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171),
680 PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
681 PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175),
682 PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177),
683 PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179),
684
685 PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181),
686 PORT_DATA_IO_PU(182), PORT_DATA_IO(183),
687 PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185),
688 PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187),
689 PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
690
691 PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191),
692 PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193),
693 PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195),
694 PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197),
695 PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),
696
697 PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201),
698 PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203),
699 PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
700 PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
701 PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209),
702
703 PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
704
705 /* Port0 */
706 PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
707 PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
708 PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
709 PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
710 PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
711 PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
712 PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
713
714 /* Port1 */
715 PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
716 PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
717 PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
718 PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
719 PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
720 PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
721 PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
722
723 /* Port2 */
724 PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
725 PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
726 PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
727 PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
728 PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
729
730 /* Port3 */
731 PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
732 PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
733 PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
734 PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
735
736 /* Port4 */
737 PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
738 PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
739 PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
740 PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
741
742 /* Port5 */
743 PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
744 PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
745 PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
746 PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
747 PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
748
749 /* Port6 */
750 PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
751 PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
752 PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
753 PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
754 PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
755
756 /* Port7 */
757 PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
758
759 /* Port8 */
760 PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
761
762 /* Port9 */
763 PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
764 PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
765
766 /* Port10 */
767 PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
768 PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, MSEL5CR_15_0),
769 PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
770
771 /* Port11 */
772 PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
773 PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
774
775 /* Port12 */
776 PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
777 PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
778 PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
779 PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
780 PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
781
782 /* Port13 */
783 PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
784 PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
785 PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
786 PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
787
788 /* Port14 */
789 PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
790 PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
791 PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
792 PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
793 PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
794
795 /* Port15 */
796 PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
797 PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
798 PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
799 PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
800 PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
801
802 /* Port16 */
803 PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
804 PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
805
806 /* Port17 */
807 PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
808 PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
809
810 /* Port18 */
811 PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
812 PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
813
814 /* Port19 */
815 PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
816 PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
817 PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
818
819 /* Port20 */
820 PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
821 PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, MSEL5CR_14_0),
822 PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
823
824 /* Port21 */
825 PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
826 PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
827 PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
828 PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
829 PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
830 PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
831
832 /* Port22 */
833 PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
834 PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
835 PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
836
837 /* Port23 */
838 PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
839 PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
840 PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
841 PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
842 PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
843 PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
844
845 /* Port24 */
846 PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
847 PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
848 PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
849 PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
850
851 /* Port25 */
852 PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
853 PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
854 PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
855 PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
856
857 /* Port26 */
858 PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
859 PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
860 PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
861
862 /* Port27 - Port39 Function */
863 PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
864 PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
865 PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
866 PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
867 PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
868 PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
869 PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
870 PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
871 PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
872 PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
873 PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
874 PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
875 PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
876
877 /* Port38 IRQ */
878 PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
879
880 /* Port40 */
881 PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
882 PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
883 PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
884
885 /* Port41 */
886 PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
887 PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
888 PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
889
890 /* Port42 */
891 PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
892 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
893 PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
894
895 /* Port43 */
896 PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
897 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
898 PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
899 PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
900
901 /* Port44 */
902 PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
903 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
904 PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
905 PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
906
907 /* Port45 */
908 PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
909 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
910 PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
911 PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
912
913 /* Port46 */
914 PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
915 PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
916 PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
917
918 /* Port47 */
919 PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
920 PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
921 PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
922
923 /* Port48 */
924 PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
925 PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
926 PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
927
928 /* Port49 */
929 PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
930 PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
931 PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
932 PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
933
934 /* Port50 */
935 PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
936 PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
937 PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
938 PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
939
940 /* Port51 */
941 PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
942 PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
943 PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
944
945 /* Port52 */
946 PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
947 PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
948 PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
949
950 /* Port53 */
951 PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
952 PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
953 PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
954
955 /* Port54 */
956 PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
957 PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
958 PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
959
960 /* Port55 */
961 PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
962 PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
963 PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
964 PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
965
966 /* Port56 */
967 PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
968 PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
969 PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
970 PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
971 PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
972
973 /* Port57 */
974 PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
975 PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
976 PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
977 PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
978 PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
979
980 /* Port58 */
981 PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1),
982 PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
983 PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
984 PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
985 PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
986
987 /* Port59 */
988 PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
989 PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
990 PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
991
992 /* Port60 */
993 PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
994 PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
995 PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
996
997 /* Port61 */
998 PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
999 PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
1000
1001 /* Port62 */
1002 PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
1003 PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
1004 PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
1005 PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
1006
1007 /* Port63 */
1008 PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
1009 PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
1010 PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
1011
1012 /* Port64 */
1013 PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
1014 PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
1015 PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
1016 PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
1017
1018 /* Port65 */
1019 PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
1020 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
1021 PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
1022
1023 /* Port66 */
1024 PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
1025 PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
1026 PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
1027 PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
1028
1029 /* Port67 - Port73 Function1 */
1030 PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
1031 PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
1032 PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
1033 PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
1034 PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
1035 PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
1036 PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
1037
1038 /* Port67 - Port73 Function2 */
1039 PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
1040 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
1041 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
1042 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
1043 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
1044 PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
1045 PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
1046
1047 /* Port67 - Port73 Function4 */
1048 PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
1049 PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
1050 PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
1051 PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
1052 PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
1053 PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
1054 PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
1055
1056 /* Port67 - Port73 Function6 */
1057 PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
1058 PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
1059 PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
1060 PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
1061 PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
1062 PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
1063 PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
1064
1065 /* Port67 - Port71 IRQ */
1066 PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
1067 PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
1068 PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
1069 PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
1070 PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
1071
1072 /* Port74 */
1073 PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
1074 PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
1075 PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
1076 PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
1077 PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
1078
1079 /* Port75 */
1080 PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
1081 PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
1082 PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
1083 PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
1084 PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
1085
1086 /* Port76 - Port80 Function */
1087 PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
1088 PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
1089 PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
1090 PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
1091 PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
1092
1093 /* Port81 */
1094 PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
1095 PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
1096
1097 /* Port82 - Port88 Function */
1098 PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
1099 PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
1100 PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
1101 PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
1102 PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
1103 PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
1104 PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
1105
1106 /* Port89 */
1107 PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
1108 PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
1109 PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
1110
1111 /* Port90 */
1112 PINMUX_DATA(DACK0_MARK, PORT90_FN1),
1113 PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
1114 PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
1115 PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
1116
1117 /* Port91 */
1118 PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
1119 PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
1120 PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1121 PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
1122
1123 /* Port92 */
1124 PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
1125 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
1126 PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1127 PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
1128 PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
1129
1130 /* Port93 */
1131 PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
1132 PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
1133 PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1134 PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
1135 PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
1136
1137 /* Port94 */
1138 PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
1139 PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
1140 PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1141 PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
1142 PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
1143
1144 /* Port95 */
1145 PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
1146 PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
1147
1148 PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
1149 PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
1150 PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
1151 PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
1152
1153 /* Port96 */
1154 PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
1155 PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
1156
1157 PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
1158 PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
1159 PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
1160 PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
1161
1162 /* Port97 */
1163 PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
1164 PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
1165 PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
1166 PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
1167 PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
1168
1169 /* Port98 */
1170 PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
1171 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
1172 PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
1173 PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
1174
1175 /* Port99 */
1176 PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
1177 PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
1178 PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
1179 PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
1180 PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
1181
1182 /* Port100 */
1183 PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
1184 PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
1185 PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
1186 PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
1187
1188 /* Port101 */
1189 PINMUX_DATA(FCE0_MARK, PORT101_FN1),
1190
1191 /* Port102 */
1192 PINMUX_DATA(FRB_MARK, PORT102_FN1),
1193 PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
1194
1195 /* Port103 */
1196 PINMUX_DATA(CS5B_MARK, PORT103_FN1),
1197 PINMUX_DATA(FCE1_MARK, PORT103_FN2),
1198 PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
1199
1200 /* Port104 */
1201 PINMUX_DATA(CS6A_MARK, PORT104_FN1),
1202 PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
1203 PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
1204
1205 /* Port105 */
1206 PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
1207 PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
1208
1209 /* Port106 */
1210 PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
1211 PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
1212
1213 /* Port107 - Port115 Function */
1214 PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
1215 PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
1216 PINMUX_DATA(CS0_MARK, PORT109_FN1),
1217 PINMUX_DATA(CS2_MARK, PORT110_FN1),
1218 PINMUX_DATA(CS4_MARK, PORT111_FN1),
1219 PINMUX_DATA(WE1_MARK, PORT112_FN1),
1220 PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
1221 PINMUX_DATA(RDWR_MARK, PORT114_FN1),
1222 PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
1223
1224 /* Port116 */
1225 PINMUX_DATA(A25_MARK, PORT116_FN1),
1226 PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
1227 PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
1228 PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
1229 PINMUX_DATA(GPO1_MARK, PORT116_FN5),
1230
1231 /* Port117 */
1232 PINMUX_DATA(A24_MARK, PORT117_FN1),
1233 PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
1234 PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
1235 PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
1236 PINMUX_DATA(GPO0_MARK, PORT117_FN5),
1237
1238 /* Port118 */
1239 PINMUX_DATA(A23_MARK, PORT118_FN1),
1240 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
1241 PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
1242 PINMUX_DATA(GPI1_MARK, PORT118_FN5),
1243 PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
1244
1245 /* Port119 */
1246 PINMUX_DATA(A22_MARK, PORT119_FN1),
1247 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
1248 PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
1249 PINMUX_DATA(GPI0_MARK, PORT119_FN5),
1250 PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
1251
1252 /* Port120 */
1253 PINMUX_DATA(A21_MARK, PORT120_FN1),
1254 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
1255 PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
1256 PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_0),
1257
1258 /* Port121 */
1259 PINMUX_DATA(A20_MARK, PORT121_FN1),
1260 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
1261 PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
1262 PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
1263
1264 /* Port122 */
1265 PINMUX_DATA(A19_MARK, PORT122_FN1),
1266 PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
1267
1268 /* Port123 */
1269 PINMUX_DATA(A18_MARK, PORT123_FN1),
1270 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
1271
1272 /* Port124 */
1273 PINMUX_DATA(A17_MARK, PORT124_FN1),
1274 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
1275
1276 /* Port125 - Port141 Function */
1277 PINMUX_DATA(A16_MARK, PORT125_FN1),
1278 PINMUX_DATA(A15_MARK, PORT126_FN1),
1279 PINMUX_DATA(A14_MARK, PORT127_FN1),
1280 PINMUX_DATA(A13_MARK, PORT128_FN1),
1281 PINMUX_DATA(A12_MARK, PORT129_FN1),
1282 PINMUX_DATA(A11_MARK, PORT130_FN1),
1283 PINMUX_DATA(A10_MARK, PORT131_FN1),
1284 PINMUX_DATA(A9_MARK, PORT132_FN1),
1285 PINMUX_DATA(A8_MARK, PORT133_FN1),
1286 PINMUX_DATA(A7_MARK, PORT134_FN1),
1287 PINMUX_DATA(A6_MARK, PORT135_FN1),
1288 PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
1289 PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
1290 PINMUX_DATA(A3_MARK, PORT138_FN1),
1291 PINMUX_DATA(A2_MARK, PORT139_FN1),
1292 PINMUX_DATA(A1_MARK, PORT140_FN1),
1293 PINMUX_DATA(CKO_MARK, PORT141_FN1),
1294
1295 /* Port142 - Port157 Function1 */
1296 PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
1297 PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
1298 PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
1299 PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
1300 PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
1301 PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
1302 PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
1303 PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
1304 PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
1305 PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
1306 PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
1307 PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
1308 PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
1309 PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
1310 PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
1311 PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
1312
1313 /* Port142 - Port149 Function3 */
1314 PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
1315 PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
1316 PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
1317 PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
1318 PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
1319 PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
1320 PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
1321 PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
1322
1323 /* Port158 */
1324 PINMUX_DATA(D31_MARK, PORT158_FN1),
1325 PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
1326 PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
1327 PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
1328 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
1329 PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
1330
1331 /* Port159 */
1332 PINMUX_DATA(D30_MARK, PORT159_FN1),
1333 PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
1334 PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
1335 PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
1336 PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
1337
1338 /* Port160 */
1339 PINMUX_DATA(D29_MARK, PORT160_FN1),
1340 PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
1341 PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
1342 PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
1343 PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
1344
1345 /* Port161 */
1346 PINMUX_DATA(D28_MARK, PORT161_FN1),
1347 PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
1348 PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
1349 PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
1350 PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
1351 PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
1352
1353 /* Port162 */
1354 PINMUX_DATA(D27_MARK, PORT162_FN1),
1355 PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
1356 PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
1357 PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
1358 PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
1359
1360 /* Port163 */
1361 PINMUX_DATA(D26_MARK, PORT163_FN1),
1362 PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
1363 PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
1364 PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
1365 PINMUX_DATA(IROUT_MARK, PORT163_FN5),
1366 PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
1367
1368 /* Port164 */
1369 PINMUX_DATA(D25_MARK, PORT164_FN1),
1370 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
1371 PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
1372 PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
1373 PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
1374
1375 /* Port165 */
1376 PINMUX_DATA(D24_MARK, PORT165_FN1),
1377 PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
1378 PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
1379 PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
1380
1381 /* Port166 - Port171 Function1 */
1382 PINMUX_DATA(D21_MARK, PORT166_FN1),
1383 PINMUX_DATA(D20_MARK, PORT167_FN1),
1384 PINMUX_DATA(D19_MARK, PORT168_FN1),
1385 PINMUX_DATA(D18_MARK, PORT169_FN1),
1386 PINMUX_DATA(D17_MARK, PORT170_FN1),
1387 PINMUX_DATA(D16_MARK, PORT171_FN1),
1388
1389 /* Port166 - Port171 Function3 */
1390 PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
1391 PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
1392 PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
1393 PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
1394 PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
1395 PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
1396
1397 /* Port166 - Port171 Function6 */
1398 PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
1399 PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
1400 PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
1401 PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
1402 PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
1403 PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
1404
1405 /* Port167 - Port171 IRQ */
1406 PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
1407 PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
1408 PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
1409 PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
1410 PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
1411
1412 /* Port172 */
1413 PINMUX_DATA(D23_MARK, PORT172_FN1),
1414 PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
1415 PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
1416 PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
1417 PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
1418
1419 /* Port173 */
1420 PINMUX_DATA(D22_MARK, PORT173_FN1),
1421 PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
1422 PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
1423 PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
1424 PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
1425
1426 /* Port174 */
1427 PINMUX_DATA(A26_MARK, PORT174_FN1),
1428 PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
1429 PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
1430 PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
1431
1432 /* Port175 */
1433 PINMUX_DATA(A0_MARK, PORT175_FN1),
1434 PINMUX_DATA(BS_MARK, PORT175_FN2),
1435 PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
1436 PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
1437
1438 /* Port176 */
1439 PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
1440
1441 /* Port177 */
1442 PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
1443 PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
1444 PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
1445 PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
1446
1447 /* Port178 */
1448 PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
1449 PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
1450 PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
1451
1452 /* Port179 */
1453 PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
1454 PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
1455 PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
1456
1457 /* Port180 */
1458 PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
1459 PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
1460 PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
1461 PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
1462 PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
1463
1464 /* Port181 */
1465 PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
1466 PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
1467 PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
1468
1469 /* Port182 */
1470 PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
1471 PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
1472 PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
1473
1474 /* Port183 */
1475 PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
1476 PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
1477 PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
1478
1479 /* Port184 */
1480 PINMUX_DATA(DACK1_MARK, PORT184_FN1),
1481 PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
1482 PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
1483
1484 /* Port185 - Port192 Function1 */
1485 PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
1486 PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
1487 PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
1488 PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
1489 PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
1490 PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
1491 PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
1492
1493 /* Port185 - Port192 Function3 */
1494 PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
1495 PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
1496 PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
1497 PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
1498 PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
1499 PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
1500 PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
1501 PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
1502
1503 /* Port185 - Port192 Function6 */
1504 PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
1505 PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
1506 PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
1507 PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
1508 PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
1509 PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
1510 PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
1511 PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
1512
1513 /* Port193 */
1514 PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
1515 PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
1516 PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), /* ? */
1517 PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
1518
1519 /* Port194 */
1520 PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
1521 PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
1522 PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), /* ? */
1523 PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
1524
1525 /* Port195 */
1526 PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
1527 PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
1528 PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
1529 PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
1530
1531 /* Port196 */
1532 PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
1533 PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
1534 PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
1535 PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
1536
1537 /* Port197 */
1538 PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
1539 PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
1540 PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
1541 PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
1542
1543 /* Port198 */
1544 PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
1545 PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
1546 PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
1547 PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
1548
1549 /* Port199 */
1550 PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
1551 PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
1552 PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
1553 PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
1554 PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
1555 PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
1556
1557 /* Port200 */
1558 PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
1559 PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
1560 PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
1561 PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
1562 PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
1563
1564 /* Port201 */
1565 PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
1566 PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
1567
1568 PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
1569 PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
1570 PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
1571 PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
1572
1573 /* Port202 */
1574 PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
1575 PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
1576
1577 PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
1578 PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
1579 PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
1580 PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
1581 PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
1582 PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
1583
1584 /* Port203 - Port208 Function1 */
1585 PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
1586 PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
1587 PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
1588 PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
1589 PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
1590 PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
1591
1592 /* Port203 - Port208 Function3 */
1593 PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
1594 PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
1595 PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
1596 PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
1597 PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
1598 PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
1599
1600 /* Port203 - Port208 Function6 */
1601 PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
1602 PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
1603 PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
1604 PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
1605 PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
1606 PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
1607
1608 /* Port203 - Port208 Function7 */
1609 PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1610 PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1611 PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
1612 PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
1613 PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1614 PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1615
1616 /* Port209 */
1617 PINMUX_DATA(VBUS_MARK, PORT209_FN1),
1618 PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_1),
1619
1620 /* Port210 */
1621 PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
1622
1623 /* Port211 */
1624 PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
1625
1626 /* LCDC select */
1627 PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0),
1628 PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1),
1629
1630 /* SDENC */
1631 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
1632 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
1633
1634 /* SYSC */
1635 PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
1636 PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
1637
1638 /* DEBUG */
1639 PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
1640 PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
1641
1642 PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
1643 PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
1644 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
1645};
1646
1647static struct pinmux_gpio pinmux_gpios[] = {
1648
1649 /* PORT */
1650 GPIO_PORT_ALL(),
1651
1652 /* IRQ */
1653 GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13),
1654 GPIO_FN(IRQ1),
1655 GPIO_FN(IRQ2_PORT11), GPIO_FN(IRQ2_PORT12),
1656 GPIO_FN(IRQ3_PORT10), GPIO_FN(IRQ3_PORT14),
1657 GPIO_FN(IRQ4_PORT15), GPIO_FN(IRQ4_PORT172),
1658 GPIO_FN(IRQ5_PORT0), GPIO_FN(IRQ5_PORT1),
1659 GPIO_FN(IRQ6_PORT121), GPIO_FN(IRQ6_PORT173),
1660 GPIO_FN(IRQ7_PORT120), GPIO_FN(IRQ7_PORT209),
1661 GPIO_FN(IRQ8),
1662 GPIO_FN(IRQ9_PORT118), GPIO_FN(IRQ9_PORT210),
1663 GPIO_FN(IRQ10),
1664 GPIO_FN(IRQ11),
1665 GPIO_FN(IRQ12_PORT42), GPIO_FN(IRQ12_PORT97),
1666 GPIO_FN(IRQ13_PORT64), GPIO_FN(IRQ13_PORT98),
1667 GPIO_FN(IRQ14_PORT63), GPIO_FN(IRQ14_PORT99),
1668 GPIO_FN(IRQ15_PORT62), GPIO_FN(IRQ15_PORT100),
1669 GPIO_FN(IRQ16_PORT68), GPIO_FN(IRQ16_PORT211),
1670 GPIO_FN(IRQ17),
1671 GPIO_FN(IRQ18),
1672 GPIO_FN(IRQ19),
1673 GPIO_FN(IRQ20),
1674 GPIO_FN(IRQ21),
1675 GPIO_FN(IRQ22),
1676 GPIO_FN(IRQ23),
1677 GPIO_FN(IRQ24),
1678 GPIO_FN(IRQ25),
1679 GPIO_FN(IRQ26_PORT58), GPIO_FN(IRQ26_PORT81),
1680 GPIO_FN(IRQ27_PORT57), GPIO_FN(IRQ27_PORT168),
1681 GPIO_FN(IRQ28_PORT56), GPIO_FN(IRQ28_PORT169),
1682 GPIO_FN(IRQ29_PORT50), GPIO_FN(IRQ29_PORT170),
1683 GPIO_FN(IRQ30_PORT49), GPIO_FN(IRQ30_PORT171),
1684 GPIO_FN(IRQ31_PORT41), GPIO_FN(IRQ31_PORT167),
1685
1686 /* Function */
1687
1688 /* DBGT */
1689 GPIO_FN(DBGMDT2), GPIO_FN(DBGMDT1), GPIO_FN(DBGMDT0),
1690 GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20),
1691 GPIO_FN(DBGMD21),
1692
1693 /* FSI */
1694 GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */
1695 GPIO_FN(FSIAISLD_PORT5),
1696 GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */
1697 GPIO_FN(FSIASPDIF_PORT18),
1698 GPIO_FN(FSIAOSLD1), GPIO_FN(FSIAOSLD2), GPIO_FN(FSIAOLR),
1699 GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC),
1700 GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT),
1701
1702 /* FMSI */
1703 GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
1704 GPIO_FN(FMSISLD_PORT6),
1705 GPIO_FN(FMSIILR), GPIO_FN(FMSIIBT), GPIO_FN(FMSIOLR),
1706 GPIO_FN(FMSIOBT), GPIO_FN(FMSICK), GPIO_FN(FMSOILR),
1707 GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT),
1708 GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK),
1709
1710 /* SCIFA0 */
1711 GPIO_FN(SCIFA0_SCK), GPIO_FN(SCIFA0_CTS), GPIO_FN(SCIFA0_RTS),
1712 GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_TXD),
1713
1714 /* SCIFA1 */
1715 GPIO_FN(SCIFA1_CTS), GPIO_FN(SCIFA1_SCK),
1716 GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RTS),
1717
1718 /* SCIFA2 */
1719 GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */
1720 GPIO_FN(SCIFA2_SCK_PORT199),
1721 GPIO_FN(SCIFA2_RXD), GPIO_FN(SCIFA2_TXD),
1722 GPIO_FN(SCIFA2_CTS), GPIO_FN(SCIFA2_RTS),
1723
1724 /* SCIFA3 */
1725 GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */
1726 GPIO_FN(SCIFA3_SCK_PORT116),
1727 GPIO_FN(SCIFA3_CTS_PORT117),
1728 GPIO_FN(SCIFA3_RXD_PORT174),
1729 GPIO_FN(SCIFA3_TXD_PORT175),
1730
1731 GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */
1732 GPIO_FN(SCIFA3_SCK_PORT158),
1733 GPIO_FN(SCIFA3_CTS_PORT162),
1734 GPIO_FN(SCIFA3_RXD_PORT159),
1735 GPIO_FN(SCIFA3_TXD_PORT160),
1736
1737 /* SCIFA4 */
1738 GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */
1739 GPIO_FN(SCIFA4_TXD_PORT13),
1740
1741 GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */
1742 GPIO_FN(SCIFA4_TXD_PORT203),
1743
1744 GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */
1745 GPIO_FN(SCIFA4_TXD_PORT93),
1746
1747 GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */
1748 GPIO_FN(SCIFA4_SCK_PORT205),
1749
1750 /* SCIFA5 */
1751 GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */
1752 GPIO_FN(SCIFA5_RXD_PORT10),
1753
1754 GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */
1755 GPIO_FN(SCIFA5_TXD_PORT208),
1756
1757 GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */
1758 GPIO_FN(SCIFA5_RXD_PORT92),
1759
1760 GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */
1761 GPIO_FN(SCIFA5_SCK_PORT206),
1762
1763 /* SCIFA6 */
1764 GPIO_FN(SCIFA6_SCK), GPIO_FN(SCIFA6_RXD), GPIO_FN(SCIFA6_TXD),
1765
1766 /* SCIFA7 */
1767 GPIO_FN(SCIFA7_TXD), GPIO_FN(SCIFA7_RXD),
1768
1769 /* SCIFAB */
1770 GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */
1771 GPIO_FN(SCIFB_RXD_PORT191),
1772 GPIO_FN(SCIFB_TXD_PORT192),
1773 GPIO_FN(SCIFB_RTS_PORT186),
1774 GPIO_FN(SCIFB_CTS_PORT187),
1775
1776 GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */
1777 GPIO_FN(SCIFB_RXD_PORT3),
1778 GPIO_FN(SCIFB_TXD_PORT4),
1779 GPIO_FN(SCIFB_RTS_PORT172),
1780 GPIO_FN(SCIFB_CTS_PORT173),
1781
1782 /* LCD0 */
1783 GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2),
1784 GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5),
1785 GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8),
1786 GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11),
1787 GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14),
1788 GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17),
1789 GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC),
1790 GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN),
1791 GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP),
1792 GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD),
1793 GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS),
1794
1795 GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162),
1796 GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158),
1797 GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159),
1798 GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */
1799
1800 GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4),
1801 GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2),
1802 GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1),
1803 GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */
1804
1805 /* LCD1 */
1806 GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2),
1807 GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5),
1808 GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8),
1809 GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11),
1810 GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14),
1811 GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17),
1812 GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20),
1813 GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23),
1814 GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS),
1815 GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON),
1816 GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN),
1817 GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP),
1818
1819 /* RSPI */
1820 GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A),
1821 GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A),
1822 GPIO_FN(RSPI_MISO_A),
1823
1824 /* VIO CKO */
1825 GPIO_FN(VIO_CKO1),
1826 GPIO_FN(VIO_CKO2),
1827 GPIO_FN(VIO_CKO_1),
1828 GPIO_FN(VIO_CKO),
1829
1830 /* VIO0 */
1831 GPIO_FN(VIO0_D0), GPIO_FN(VIO0_D1), GPIO_FN(VIO0_D2),
1832 GPIO_FN(VIO0_D3), GPIO_FN(VIO0_D4), GPIO_FN(VIO0_D5),
1833 GPIO_FN(VIO0_D6), GPIO_FN(VIO0_D7), GPIO_FN(VIO0_D8),
1834 GPIO_FN(VIO0_D9), GPIO_FN(VIO0_D10), GPIO_FN(VIO0_D11),
1835 GPIO_FN(VIO0_D12), GPIO_FN(VIO0_VD), GPIO_FN(VIO0_HD),
1836 GPIO_FN(VIO0_CLK), GPIO_FN(VIO0_FIELD),
1837
1838 GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
1839 GPIO_FN(VIO0_D14_PORT25),
1840 GPIO_FN(VIO0_D15_PORT24),
1841
1842 GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
1843 GPIO_FN(VIO0_D14_PORT95),
1844 GPIO_FN(VIO0_D15_PORT96),
1845
1846 /* VIO1 */
1847 GPIO_FN(VIO1_D0), GPIO_FN(VIO1_D1), GPIO_FN(VIO1_D2),
1848 GPIO_FN(VIO1_D3), GPIO_FN(VIO1_D4), GPIO_FN(VIO1_D5),
1849 GPIO_FN(VIO1_D6), GPIO_FN(VIO1_D7), GPIO_FN(VIO1_VD),
1850 GPIO_FN(VIO1_HD), GPIO_FN(VIO1_CLK), GPIO_FN(VIO1_FIELD),
1851
1852 /* TPU0 */
1853 GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3),
1854 GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
1855 GPIO_FN(TPU0TO2_PORT202),
1856
1857 /* SSP1 0 */
1858 GPIO_FN(STP0_IPD0), GPIO_FN(STP0_IPD1), GPIO_FN(STP0_IPD2),
1859 GPIO_FN(STP0_IPD3), GPIO_FN(STP0_IPD4), GPIO_FN(STP0_IPD5),
1860 GPIO_FN(STP0_IPD6), GPIO_FN(STP0_IPD7), GPIO_FN(STP0_IPEN),
1861 GPIO_FN(STP0_IPCLK), GPIO_FN(STP0_IPSYNC),
1862
1863 /* SSP1 1 */
1864 GPIO_FN(STP1_IPD1), GPIO_FN(STP1_IPD2), GPIO_FN(STP1_IPD3),
1865 GPIO_FN(STP1_IPD4), GPIO_FN(STP1_IPD5), GPIO_FN(STP1_IPD6),
1866 GPIO_FN(STP1_IPD7), GPIO_FN(STP1_IPCLK), GPIO_FN(STP1_IPSYNC),
1867
1868 GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
1869 GPIO_FN(STP1_IPEN_PORT187),
1870
1871 GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
1872 GPIO_FN(STP1_IPEN_PORT193),
1873
1874 /* SIM */
1875 GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK),
1876 GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */
1877 GPIO_FN(SIM_D_PORT199),
1878
1879 /* SDHI0 */
1880 GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2),
1881 GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP),
1882 GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK),
1883
1884 /* SDHI1 */
1885 GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2),
1886 GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP),
1887 GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK),
1888
1889 /* SDHI2 */
1890 GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2),
1891 GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD),
1892
1893 GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */
1894 GPIO_FN(SDHI2_WP_PORT25),
1895
1896 GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */
1897 GPIO_FN(SDHI2_CD_PORT202),
1898
1899 /* MSIOF2 */
1900 GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK),
1901 GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1),
1902 GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_MCK0), GPIO_FN(MSIOF2_RSYNC),
1903 GPIO_FN(MSIOF2_RSCK),
1904
1905 /* KEYSC */
1906 GPIO_FN(KEYIN4), GPIO_FN(KEYIN5),
1907 GPIO_FN(KEYIN6), GPIO_FN(KEYIN7),
1908 GPIO_FN(KEYOUT0), GPIO_FN(KEYOUT1), GPIO_FN(KEYOUT2),
1909 GPIO_FN(KEYOUT3), GPIO_FN(KEYOUT4), GPIO_FN(KEYOUT5),
1910 GPIO_FN(KEYOUT6), GPIO_FN(KEYOUT7),
1911
1912 GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
1913 GPIO_FN(KEYIN1_PORT44),
1914 GPIO_FN(KEYIN2_PORT45),
1915 GPIO_FN(KEYIN3_PORT46),
1916
1917 GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
1918 GPIO_FN(KEYIN1_PORT57),
1919 GPIO_FN(KEYIN2_PORT56),
1920 GPIO_FN(KEYIN3_PORT55),
1921
1922 /* VOU */
1923 GPIO_FN(DV_D0), GPIO_FN(DV_D1), GPIO_FN(DV_D2),
1924 GPIO_FN(DV_D3), GPIO_FN(DV_D4), GPIO_FN(DV_D5),
1925 GPIO_FN(DV_D6), GPIO_FN(DV_D7), GPIO_FN(DV_D8),
1926 GPIO_FN(DV_D9), GPIO_FN(DV_D10), GPIO_FN(DV_D11),
1927 GPIO_FN(DV_D12), GPIO_FN(DV_D13), GPIO_FN(DV_D14),
1928 GPIO_FN(DV_D15), GPIO_FN(DV_CLK),
1929 GPIO_FN(DV_VSYNC), GPIO_FN(DV_HSYNC),
1930
1931 /* MEMC */
1932 GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2),
1933 GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5),
1934 GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8),
1935 GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11),
1936 GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14),
1937 GPIO_FN(MEMC_AD15), GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_INT),
1938 GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_NOE), GPIO_FN(MEMC_CS1),
1939 GPIO_FN(MEMC_A1), GPIO_FN(MEMC_ADV), GPIO_FN(MEMC_DREQ0),
1940 GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK),
1941 GPIO_FN(MEMC_A0),
1942
1943 /* MMC */
1944 GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69),
1945 GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71),
1946 GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73),
1947 GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75),
1948 GPIO_FN(MMC0_CLK_PORT66),
1949 GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */
1950
1951 GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148),
1952 GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146),
1953 GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144),
1954 GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142),
1955 GPIO_FN(MMC1_CLK_PORT103),
1956 GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */
1957
1958 /* MSIOF0 */
1959 GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD),
1960 GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1),
1961 GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_TSCK),
1962 GPIO_FN(MSIOF0_TSYNC),
1963
1964 /* MSIOF1 */
1965 GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC),
1966 GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
1967
1968 GPIO_FN(MSIOF1_SS2_PORT116), GPIO_FN(MSIOF1_SS1_PORT117),
1969 GPIO_FN(MSIOF1_RXD_PORT118), GPIO_FN(MSIOF1_TXD_PORT119),
1970 GPIO_FN(MSIOF1_TSYNC_PORT120),
1971 GPIO_FN(MSIOF1_TSCK_PORT121), /* MSEL4CR_10_0 */
1972
1973 GPIO_FN(MSIOF1_SS1_PORT67), GPIO_FN(MSIOF1_TSCK_PORT72),
1974 GPIO_FN(MSIOF1_TSYNC_PORT73), GPIO_FN(MSIOF1_TXD_PORT74),
1975 GPIO_FN(MSIOF1_RXD_PORT75),
1976 GPIO_FN(MSIOF1_SS2_PORT202), /* MSEL4CR_10_1 */
1977
1978 /* GPIO */
1979 GPIO_FN(GPO0), GPIO_FN(GPI0),
1980 GPIO_FN(GPO1), GPIO_FN(GPI1),
1981
1982 /* USB0 */
1983 GPIO_FN(USB0_OCI), GPIO_FN(USB0_PPON), GPIO_FN(VBUS),
1984
1985 /* USB1 */
1986 GPIO_FN(USB1_OCI), GPIO_FN(USB1_PPON),
1987
1988 /* BBIF1 */
1989 GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_TSYNC),
1990 GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC),
1991 GPIO_FN(BBIF1_FLOW), GPIO_FN(BBIF1_RX_FLOW_N),
1992
1993 /* BBIF2 */
1994 GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
1995 GPIO_FN(BBIF2_RXD2_PORT60),
1996 GPIO_FN(BBIF2_TSYNC2_PORT6),
1997 GPIO_FN(BBIF2_TSCK2_PORT59),
1998
1999 GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
2000 GPIO_FN(BBIF2_TXD2_PORT183),
2001 GPIO_FN(BBIF2_TSCK2_PORT89),
2002 GPIO_FN(BBIF2_TSYNC2_PORT184),
2003
2004 /* BSC / FLCTL / PCMCIA */
2005 GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4),
2006 GPIO_FN(CS5B), GPIO_FN(CS6A),
2007 GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */
2008 GPIO_FN(CS5A_PORT19),
2009 GPIO_FN(IOIS16), /* ? */
2010
2011 GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3),
2012 GPIO_FN(A4_FOE), GPIO_FN(A5_FCDE), /* share with FLCTL */
2013 GPIO_FN(A6), GPIO_FN(A7), GPIO_FN(A8), GPIO_FN(A9),
2014 GPIO_FN(A10), GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13),
2015 GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), GPIO_FN(A17),
2016 GPIO_FN(A18), GPIO_FN(A19), GPIO_FN(A20), GPIO_FN(A21),
2017 GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25),
2018 GPIO_FN(A26),
2019
2020 GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), /* share with FLCTL */
2021 GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), /* share with FLCTL */
2022 GPIO_FN(D4_NAF4), GPIO_FN(D5_NAF5), /* share with FLCTL */
2023 GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), /* share with FLCTL */
2024 GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), /* share with FLCTL */
2025 GPIO_FN(D10_NAF10), GPIO_FN(D11_NAF11), /* share with FLCTL */
2026 GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), /* share with FLCTL */
2027 GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), /* share with FLCTL */
2028 GPIO_FN(D16), GPIO_FN(D17), GPIO_FN(D18), GPIO_FN(D19),
2029 GPIO_FN(D20), GPIO_FN(D21), GPIO_FN(D22), GPIO_FN(D23),
2030 GPIO_FN(D24), GPIO_FN(D25), GPIO_FN(D26), GPIO_FN(D27),
2031 GPIO_FN(D28), GPIO_FN(D29), GPIO_FN(D30), GPIO_FN(D31),
2032
2033 GPIO_FN(WE0_FWE), /* share with FLCTL */
2034 GPIO_FN(WE1),
2035 GPIO_FN(WE2_ICIORD), /* share with PCMCIA */
2036 GPIO_FN(WE3_ICIOWR), /* share with PCMCIA */
2037 GPIO_FN(CKO), GPIO_FN(BS), GPIO_FN(RDWR),
2038 GPIO_FN(RD_FSC), /* share with FLCTL */
2039 GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
2040 GPIO_FN(WAIT_PORT90),
2041
2042 GPIO_FN(FCE0), GPIO_FN(FCE1), GPIO_FN(FRB), /* FLCTL */
2043
2044 /* IRDA */
2045 GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_OUT),
2046
2047 /* ATAPI */
2048 GPIO_FN(IDE_D0), GPIO_FN(IDE_D1), GPIO_FN(IDE_D2),
2049 GPIO_FN(IDE_D3), GPIO_FN(IDE_D4), GPIO_FN(IDE_D5),
2050 GPIO_FN(IDE_D6), GPIO_FN(IDE_D7), GPIO_FN(IDE_D8),
2051 GPIO_FN(IDE_D9), GPIO_FN(IDE_D10), GPIO_FN(IDE_D11),
2052 GPIO_FN(IDE_D12), GPIO_FN(IDE_D13), GPIO_FN(IDE_D14),
2053 GPIO_FN(IDE_D15), GPIO_FN(IDE_A0), GPIO_FN(IDE_A1),
2054 GPIO_FN(IDE_A2), GPIO_FN(IDE_CS0), GPIO_FN(IDE_CS1),
2055 GPIO_FN(IDE_IOWR), GPIO_FN(IDE_IORD), GPIO_FN(IDE_IORDY),
2056 GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION),
2057 GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ),
2058
2059 /* RMII */
2060 GPIO_FN(RMII_CRS_DV), GPIO_FN(RMII_RX_ER), GPIO_FN(RMII_RXD0),
2061 GPIO_FN(RMII_RXD1), GPIO_FN(RMII_TX_EN), GPIO_FN(RMII_TXD0),
2062 GPIO_FN(RMII_MDC), GPIO_FN(RMII_TXD1), GPIO_FN(RMII_MDIO),
2063 GPIO_FN(RMII_REF50CK), GPIO_FN(RMII_REF125CK), /* for GMII */
2064
2065 /* GEther */
2066 GPIO_FN(ET_TX_CLK), GPIO_FN(ET_TX_EN), GPIO_FN(ET_ETXD0),
2067 GPIO_FN(ET_ETXD1), GPIO_FN(ET_ETXD2), GPIO_FN(ET_ETXD3),
2068 GPIO_FN(ET_ETXD4), GPIO_FN(ET_ETXD5), /* for GEther */
2069 GPIO_FN(ET_ETXD6), GPIO_FN(ET_ETXD7), /* for GEther */
2070 GPIO_FN(ET_COL), GPIO_FN(ET_TX_ER), GPIO_FN(ET_RX_CLK),
2071 GPIO_FN(ET_RX_DV), GPIO_FN(ET_ERXD0), GPIO_FN(ET_ERXD1),
2072 GPIO_FN(ET_ERXD2), GPIO_FN(ET_ERXD3),
2073 GPIO_FN(ET_ERXD4), GPIO_FN(ET_ERXD5), /* for GEther */
2074 GPIO_FN(ET_ERXD6), GPIO_FN(ET_ERXD7), /* for GEther */
2075 GPIO_FN(ET_RX_ER), GPIO_FN(ET_CRS), GPIO_FN(ET_MDC),
2076 GPIO_FN(ET_MDIO), GPIO_FN(ET_LINK), GPIO_FN(ET_PHY_INT),
2077 GPIO_FN(ET_WOL), GPIO_FN(ET_GTX_CLK),
2078
2079 /* DMA0 */
2080 GPIO_FN(DREQ0), GPIO_FN(DACK0),
2081
2082 /* DMA1 */
2083 GPIO_FN(DREQ1), GPIO_FN(DACK1),
2084
2085 /* SYSC */
2086 GPIO_FN(RESETOUTS),
2087
2088 /* IRREM */
2089 GPIO_FN(IROUT),
2090
2091 /* LCDC */
2092 GPIO_FN(LCDC0_SELECT),
2093 GPIO_FN(LCDC1_SELECT),
2094
2095 /* SDENC */
2096 GPIO_FN(SDENC_CPG),
2097 GPIO_FN(SDENC_DV_CLKI),
2098
2099 /* SYSC */
2100 GPIO_FN(RESETP_PULLUP),
2101 GPIO_FN(RESETP_PLAIN),
2102
2103 /* DEBUG */
2104 GPIO_FN(EDEBGREQ_PULLDOWN),
2105 GPIO_FN(EDEBGREQ_PULLUP),
2106
2107 GPIO_FN(TRACEAUD_FROM_VIO),
2108 GPIO_FN(TRACEAUD_FROM_LCDC0),
2109 GPIO_FN(TRACEAUD_FROM_MEMC),
2110};
2111
2112static struct pinmux_cfg_reg pinmux_config_regs[] = {
2113 PORTCR(0, 0xe6050000), /* PORT0CR */
2114 PORTCR(1, 0xe6050001), /* PORT1CR */
2115 PORTCR(2, 0xe6050002), /* PORT2CR */
2116 PORTCR(3, 0xe6050003), /* PORT3CR */
2117 PORTCR(4, 0xe6050004), /* PORT4CR */
2118 PORTCR(5, 0xe6050005), /* PORT5CR */
2119 PORTCR(6, 0xe6050006), /* PORT6CR */
2120 PORTCR(7, 0xe6050007), /* PORT7CR */
2121 PORTCR(8, 0xe6050008), /* PORT8CR */
2122 PORTCR(9, 0xe6050009), /* PORT9CR */
2123 PORTCR(10, 0xe605000a), /* PORT10CR */
2124 PORTCR(11, 0xe605000b), /* PORT11CR */
2125 PORTCR(12, 0xe605000c), /* PORT12CR */
2126 PORTCR(13, 0xe605000d), /* PORT13CR */
2127 PORTCR(14, 0xe605000e), /* PORT14CR */
2128 PORTCR(15, 0xe605000f), /* PORT15CR */
2129 PORTCR(16, 0xe6050010), /* PORT16CR */
2130 PORTCR(17, 0xe6050011), /* PORT17CR */
2131 PORTCR(18, 0xe6050012), /* PORT18CR */
2132 PORTCR(19, 0xe6050013), /* PORT19CR */
2133 PORTCR(20, 0xe6050014), /* PORT20CR */
2134 PORTCR(21, 0xe6050015), /* PORT21CR */
2135 PORTCR(22, 0xe6050016), /* PORT22CR */
2136 PORTCR(23, 0xe6050017), /* PORT23CR */
2137 PORTCR(24, 0xe6050018), /* PORT24CR */
2138 PORTCR(25, 0xe6050019), /* PORT25CR */
2139 PORTCR(26, 0xe605001a), /* PORT26CR */
2140 PORTCR(27, 0xe605001b), /* PORT27CR */
2141 PORTCR(28, 0xe605001c), /* PORT28CR */
2142 PORTCR(29, 0xe605001d), /* PORT29CR */
2143 PORTCR(30, 0xe605001e), /* PORT30CR */
2144 PORTCR(31, 0xe605001f), /* PORT31CR */
2145 PORTCR(32, 0xe6050020), /* PORT32CR */
2146 PORTCR(33, 0xe6050021), /* PORT33CR */
2147 PORTCR(34, 0xe6050022), /* PORT34CR */
2148 PORTCR(35, 0xe6050023), /* PORT35CR */
2149 PORTCR(36, 0xe6050024), /* PORT36CR */
2150 PORTCR(37, 0xe6050025), /* PORT37CR */
2151 PORTCR(38, 0xe6050026), /* PORT38CR */
2152 PORTCR(39, 0xe6050027), /* PORT39CR */
2153 PORTCR(40, 0xe6050028), /* PORT40CR */
2154 PORTCR(41, 0xe6050029), /* PORT41CR */
2155 PORTCR(42, 0xe605002a), /* PORT42CR */
2156 PORTCR(43, 0xe605002b), /* PORT43CR */
2157 PORTCR(44, 0xe605002c), /* PORT44CR */
2158 PORTCR(45, 0xe605002d), /* PORT45CR */
2159 PORTCR(46, 0xe605002e), /* PORT46CR */
2160 PORTCR(47, 0xe605002f), /* PORT47CR */
2161 PORTCR(48, 0xe6050030), /* PORT48CR */
2162 PORTCR(49, 0xe6050031), /* PORT49CR */
2163 PORTCR(50, 0xe6050032), /* PORT50CR */
2164 PORTCR(51, 0xe6050033), /* PORT51CR */
2165 PORTCR(52, 0xe6050034), /* PORT52CR */
2166 PORTCR(53, 0xe6050035), /* PORT53CR */
2167 PORTCR(54, 0xe6050036), /* PORT54CR */
2168 PORTCR(55, 0xe6050037), /* PORT55CR */
2169 PORTCR(56, 0xe6050038), /* PORT56CR */
2170 PORTCR(57, 0xe6050039), /* PORT57CR */
2171 PORTCR(58, 0xe605003a), /* PORT58CR */
2172 PORTCR(59, 0xe605003b), /* PORT59CR */
2173 PORTCR(60, 0xe605003c), /* PORT60CR */
2174 PORTCR(61, 0xe605003d), /* PORT61CR */
2175 PORTCR(62, 0xe605003e), /* PORT62CR */
2176 PORTCR(63, 0xe605003f), /* PORT63CR */
2177 PORTCR(64, 0xe6050040), /* PORT64CR */
2178 PORTCR(65, 0xe6050041), /* PORT65CR */
2179 PORTCR(66, 0xe6050042), /* PORT66CR */
2180 PORTCR(67, 0xe6050043), /* PORT67CR */
2181 PORTCR(68, 0xe6050044), /* PORT68CR */
2182 PORTCR(69, 0xe6050045), /* PORT69CR */
2183 PORTCR(70, 0xe6050046), /* PORT70CR */
2184 PORTCR(71, 0xe6050047), /* PORT71CR */
2185 PORTCR(72, 0xe6050048), /* PORT72CR */
2186 PORTCR(73, 0xe6050049), /* PORT73CR */
2187 PORTCR(74, 0xe605004a), /* PORT74CR */
2188 PORTCR(75, 0xe605004b), /* PORT75CR */
2189 PORTCR(76, 0xe605004c), /* PORT76CR */
2190 PORTCR(77, 0xe605004d), /* PORT77CR */
2191 PORTCR(78, 0xe605004e), /* PORT78CR */
2192 PORTCR(79, 0xe605004f), /* PORT79CR */
2193 PORTCR(80, 0xe6050050), /* PORT80CR */
2194 PORTCR(81, 0xe6050051), /* PORT81CR */
2195 PORTCR(82, 0xe6050052), /* PORT82CR */
2196 PORTCR(83, 0xe6050053), /* PORT83CR */
2197
2198 PORTCR(84, 0xe6051054), /* PORT84CR */
2199 PORTCR(85, 0xe6051055), /* PORT85CR */
2200 PORTCR(86, 0xe6051056), /* PORT86CR */
2201 PORTCR(87, 0xe6051057), /* PORT87CR */
2202 PORTCR(88, 0xe6051058), /* PORT88CR */
2203 PORTCR(89, 0xe6051059), /* PORT89CR */
2204 PORTCR(90, 0xe605105a), /* PORT90CR */
2205 PORTCR(91, 0xe605105b), /* PORT91CR */
2206 PORTCR(92, 0xe605105c), /* PORT92CR */
2207 PORTCR(93, 0xe605105d), /* PORT93CR */
2208 PORTCR(94, 0xe605105e), /* PORT94CR */
2209 PORTCR(95, 0xe605105f), /* PORT95CR */
2210 PORTCR(96, 0xe6051060), /* PORT96CR */
2211 PORTCR(97, 0xe6051061), /* PORT97CR */
2212 PORTCR(98, 0xe6051062), /* PORT98CR */
2213 PORTCR(99, 0xe6051063), /* PORT99CR */
2214 PORTCR(100, 0xe6051064), /* PORT100CR */
2215 PORTCR(101, 0xe6051065), /* PORT101CR */
2216 PORTCR(102, 0xe6051066), /* PORT102CR */
2217 PORTCR(103, 0xe6051067), /* PORT103CR */
2218 PORTCR(104, 0xe6051068), /* PORT104CR */
2219 PORTCR(105, 0xe6051069), /* PORT105CR */
2220 PORTCR(106, 0xe605106a), /* PORT106CR */
2221 PORTCR(107, 0xe605106b), /* PORT107CR */
2222 PORTCR(108, 0xe605106c), /* PORT108CR */
2223 PORTCR(109, 0xe605106d), /* PORT109CR */
2224 PORTCR(110, 0xe605106e), /* PORT110CR */
2225 PORTCR(111, 0xe605106f), /* PORT111CR */
2226 PORTCR(112, 0xe6051070), /* PORT112CR */
2227 PORTCR(113, 0xe6051071), /* PORT113CR */
2228 PORTCR(114, 0xe6051072), /* PORT114CR */
2229
2230 PORTCR(115, 0xe6052073), /* PORT115CR */
2231 PORTCR(116, 0xe6052074), /* PORT116CR */
2232 PORTCR(117, 0xe6052075), /* PORT117CR */
2233 PORTCR(118, 0xe6052076), /* PORT118CR */
2234 PORTCR(119, 0xe6052077), /* PORT119CR */
2235 PORTCR(120, 0xe6052078), /* PORT120CR */
2236 PORTCR(121, 0xe6052079), /* PORT121CR */
2237 PORTCR(122, 0xe605207a), /* PORT122CR */
2238 PORTCR(123, 0xe605207b), /* PORT123CR */
2239 PORTCR(124, 0xe605207c), /* PORT124CR */
2240 PORTCR(125, 0xe605207d), /* PORT125CR */
2241 PORTCR(126, 0xe605207e), /* PORT126CR */
2242 PORTCR(127, 0xe605207f), /* PORT127CR */
2243 PORTCR(128, 0xe6052080), /* PORT128CR */
2244 PORTCR(129, 0xe6052081), /* PORT129CR */
2245 PORTCR(130, 0xe6052082), /* PORT130CR */
2246 PORTCR(131, 0xe6052083), /* PORT131CR */
2247 PORTCR(132, 0xe6052084), /* PORT132CR */
2248 PORTCR(133, 0xe6052085), /* PORT133CR */
2249 PORTCR(134, 0xe6052086), /* PORT134CR */
2250 PORTCR(135, 0xe6052087), /* PORT135CR */
2251 PORTCR(136, 0xe6052088), /* PORT136CR */
2252 PORTCR(137, 0xe6052089), /* PORT137CR */
2253 PORTCR(138, 0xe605208a), /* PORT138CR */
2254 PORTCR(139, 0xe605208b), /* PORT139CR */
2255 PORTCR(140, 0xe605208c), /* PORT140CR */
2256 PORTCR(141, 0xe605208d), /* PORT141CR */
2257 PORTCR(142, 0xe605208e), /* PORT142CR */
2258 PORTCR(143, 0xe605208f), /* PORT143CR */
2259 PORTCR(144, 0xe6052090), /* PORT144CR */
2260 PORTCR(145, 0xe6052091), /* PORT145CR */
2261 PORTCR(146, 0xe6052092), /* PORT146CR */
2262 PORTCR(147, 0xe6052093), /* PORT147CR */
2263 PORTCR(148, 0xe6052094), /* PORT148CR */
2264 PORTCR(149, 0xe6052095), /* PORT149CR */
2265 PORTCR(150, 0xe6052096), /* PORT150CR */
2266 PORTCR(151, 0xe6052097), /* PORT151CR */
2267 PORTCR(152, 0xe6052098), /* PORT152CR */
2268 PORTCR(153, 0xe6052099), /* PORT153CR */
2269 PORTCR(154, 0xe605209a), /* PORT154CR */
2270 PORTCR(155, 0xe605209b), /* PORT155CR */
2271 PORTCR(156, 0xe605209c), /* PORT156CR */
2272 PORTCR(157, 0xe605209d), /* PORT157CR */
2273 PORTCR(158, 0xe605209e), /* PORT158CR */
2274 PORTCR(159, 0xe605209f), /* PORT159CR */
2275 PORTCR(160, 0xe60520a0), /* PORT160CR */
2276 PORTCR(161, 0xe60520a1), /* PORT161CR */
2277 PORTCR(162, 0xe60520a2), /* PORT162CR */
2278 PORTCR(163, 0xe60520a3), /* PORT163CR */
2279 PORTCR(164, 0xe60520a4), /* PORT164CR */
2280 PORTCR(165, 0xe60520a5), /* PORT165CR */
2281 PORTCR(166, 0xe60520a6), /* PORT166CR */
2282 PORTCR(167, 0xe60520a7), /* PORT167CR */
2283 PORTCR(168, 0xe60520a8), /* PORT168CR */
2284 PORTCR(169, 0xe60520a9), /* PORT169CR */
2285 PORTCR(170, 0xe60520aa), /* PORT170CR */
2286 PORTCR(171, 0xe60520ab), /* PORT171CR */
2287 PORTCR(172, 0xe60520ac), /* PORT172CR */
2288 PORTCR(173, 0xe60520ad), /* PORT173CR */
2289 PORTCR(174, 0xe60520ae), /* PORT174CR */
2290 PORTCR(175, 0xe60520af), /* PORT175CR */
2291 PORTCR(176, 0xe60520b0), /* PORT176CR */
2292 PORTCR(177, 0xe60520b1), /* PORT177CR */
2293 PORTCR(178, 0xe60520b2), /* PORT178CR */
2294 PORTCR(179, 0xe60520b3), /* PORT179CR */
2295 PORTCR(180, 0xe60520b4), /* PORT180CR */
2296 PORTCR(181, 0xe60520b5), /* PORT181CR */
2297 PORTCR(182, 0xe60520b6), /* PORT182CR */
2298 PORTCR(183, 0xe60520b7), /* PORT183CR */
2299 PORTCR(184, 0xe60520b8), /* PORT184CR */
2300 PORTCR(185, 0xe60520b9), /* PORT185CR */
2301 PORTCR(186, 0xe60520ba), /* PORT186CR */
2302 PORTCR(187, 0xe60520bb), /* PORT187CR */
2303 PORTCR(188, 0xe60520bc), /* PORT188CR */
2304 PORTCR(189, 0xe60520bd), /* PORT189CR */
2305 PORTCR(190, 0xe60520be), /* PORT190CR */
2306 PORTCR(191, 0xe60520bf), /* PORT191CR */
2307 PORTCR(192, 0xe60520c0), /* PORT192CR */
2308 PORTCR(193, 0xe60520c1), /* PORT193CR */
2309 PORTCR(194, 0xe60520c2), /* PORT194CR */
2310 PORTCR(195, 0xe60520c3), /* PORT195CR */
2311 PORTCR(196, 0xe60520c4), /* PORT196CR */
2312 PORTCR(197, 0xe60520c5), /* PORT197CR */
2313 PORTCR(198, 0xe60520c6), /* PORT198CR */
2314 PORTCR(199, 0xe60520c7), /* PORT199CR */
2315 PORTCR(200, 0xe60520c8), /* PORT200CR */
2316 PORTCR(201, 0xe60520c9), /* PORT201CR */
2317 PORTCR(202, 0xe60520ca), /* PORT202CR */
2318 PORTCR(203, 0xe60520cb), /* PORT203CR */
2319 PORTCR(204, 0xe60520cc), /* PORT204CR */
2320 PORTCR(205, 0xe60520cd), /* PORT205CR */
2321 PORTCR(206, 0xe60520ce), /* PORT206CR */
2322 PORTCR(207, 0xe60520cf), /* PORT207CR */
2323 PORTCR(208, 0xe60520d0), /* PORT208CR */
2324 PORTCR(209, 0xe60520d1), /* PORT209CR */
2325
2326 PORTCR(210, 0xe60530d2), /* PORT210CR */
2327 PORTCR(211, 0xe60530d3), /* PORT211CR */
2328
2329 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
2330 MSEL1CR_31_0, MSEL1CR_31_1,
2331 MSEL1CR_30_0, MSEL1CR_30_1,
2332 MSEL1CR_29_0, MSEL1CR_29_1,
2333 MSEL1CR_28_0, MSEL1CR_28_1,
2334 MSEL1CR_27_0, MSEL1CR_27_1,
2335 MSEL1CR_26_0, MSEL1CR_26_1,
2336 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2337 0, 0, 0, 0, 0, 0, 0, 0,
2338 MSEL1CR_16_0, MSEL1CR_16_1,
2339 MSEL1CR_15_0, MSEL1CR_15_1,
2340 MSEL1CR_14_0, MSEL1CR_14_1,
2341 MSEL1CR_13_0, MSEL1CR_13_1,
2342 MSEL1CR_12_0, MSEL1CR_12_1,
2343 0, 0, 0, 0,
2344 MSEL1CR_9_0, MSEL1CR_9_1,
2345 0, 0,
2346 MSEL1CR_7_0, MSEL1CR_7_1,
2347 MSEL1CR_6_0, MSEL1CR_6_1,
2348 MSEL1CR_5_0, MSEL1CR_5_1,
2349 MSEL1CR_4_0, MSEL1CR_4_1,
2350 MSEL1CR_3_0, MSEL1CR_3_1,
2351 MSEL1CR_2_0, MSEL1CR_2_1,
2352 0, 0,
2353 MSEL1CR_0_0, MSEL1CR_0_1,
2354 }
2355 },
2356 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
2357 0, 0, 0, 0, 0, 0, 0, 0,
2358 0, 0, 0, 0, 0, 0, 0, 0,
2359 0, 0, 0, 0, 0, 0, 0, 0,
2360 0, 0, 0, 0, 0, 0, 0, 0,
2361 MSEL3CR_15_0, MSEL3CR_15_1,
2362 0, 0, 0, 0, 0, 0, 0, 0,
2363 0, 0, 0, 0, 0, 0, 0, 0,
2364 MSEL3CR_6_0, MSEL3CR_6_1,
2365 0, 0, 0, 0, 0, 0, 0, 0,
2366 0, 0, 0, 0,
2367 }
2368 },
2369 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
2370 0, 0, 0, 0, 0, 0, 0, 0,
2371 0, 0, 0, 0, 0, 0, 0, 0,
2372 0, 0, 0, 0, 0, 0, 0, 0,
2373 MSEL4CR_19_0, MSEL4CR_19_1,
2374 MSEL4CR_18_0, MSEL4CR_18_1,
2375 0, 0, 0, 0,
2376 MSEL4CR_15_0, MSEL4CR_15_1,
2377 0, 0, 0, 0, 0, 0, 0, 0,
2378 MSEL4CR_10_0, MSEL4CR_10_1,
2379 0, 0, 0, 0, 0, 0,
2380 MSEL4CR_6_0, MSEL4CR_6_1,
2381 0, 0,
2382 MSEL4CR_4_0, MSEL4CR_4_1,
2383 0, 0, 0, 0,
2384 MSEL4CR_1_0, MSEL4CR_1_1,
2385 0, 0,
2386 }
2387 },
2388 { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
2389 MSEL5CR_31_0, MSEL5CR_31_1,
2390 MSEL5CR_30_0, MSEL5CR_30_1,
2391 MSEL5CR_29_0, MSEL5CR_29_1,
2392 0, 0,
2393 MSEL5CR_27_0, MSEL5CR_27_1,
2394 0, 0,
2395 MSEL5CR_25_0, MSEL5CR_25_1,
2396 0, 0,
2397 MSEL5CR_23_0, MSEL5CR_23_1,
2398 0, 0,
2399 MSEL5CR_21_0, MSEL5CR_21_1,
2400 0, 0,
2401 MSEL5CR_19_0, MSEL5CR_19_1,
2402 0, 0,
2403 MSEL5CR_17_0, MSEL5CR_17_1,
2404 0, 0,
2405 MSEL5CR_15_0, MSEL5CR_15_1,
2406 MSEL5CR_14_0, MSEL5CR_14_1,
2407 MSEL5CR_13_0, MSEL5CR_13_1,
2408 MSEL5CR_12_0, MSEL5CR_12_1,
2409 MSEL5CR_11_0, MSEL5CR_11_1,
2410 MSEL5CR_10_0, MSEL5CR_10_1,
2411 0, 0,
2412 MSEL5CR_8_0, MSEL5CR_8_1,
2413 MSEL5CR_7_0, MSEL5CR_7_1,
2414 MSEL5CR_6_0, MSEL5CR_6_1,
2415 MSEL5CR_5_0, MSEL5CR_5_1,
2416 MSEL5CR_4_0, MSEL5CR_4_1,
2417 MSEL5CR_3_0, MSEL5CR_3_1,
2418 MSEL5CR_2_0, MSEL5CR_2_1,
2419 0, 0,
2420 MSEL5CR_0_0, MSEL5CR_0_1,
2421 }
2422 },
2423 { },
2424};
2425
2426static struct pinmux_data_reg pinmux_data_regs[] = {
2427 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
2428 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2429 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2430 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2431 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2432 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2433 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2434 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2435 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
2436 },
2437 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
2438 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
2439 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
2440 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
2441 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
2442 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
2443 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
2444 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2445 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
2446 },
2447 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
2448 0, 0, 0, 0,
2449 0, 0, 0, 0,
2450 0, 0, 0, 0,
2451 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2452 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2453 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2454 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2455 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
2456 },
2457 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
2458 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
2459 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
2460 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
2461 0, 0, 0, 0,
2462 0, 0, 0, 0,
2463 0, 0, 0, 0,
2464 0, 0, 0, 0,
2465 0, 0, 0, 0 }
2466 },
2467 { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
2468 0, 0, 0, 0,
2469 0, 0, 0, 0,
2470 0, 0, 0, 0,
2471 0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2472 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2473 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2474 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2475 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
2476 },
2477 { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
2478 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2479 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
2480 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2481 PORT115_DATA, 0, 0, 0,
2482 0, 0, 0, 0,
2483 0, 0, 0, 0,
2484 0, 0, 0, 0,
2485 0, 0, 0, 0 }
2486 },
2487 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
2488 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
2489 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
2490 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
2491 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
2492 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
2493 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
2494 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2495 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
2496 },
2497 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
2498 PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
2499 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
2500 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
2501 PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2502 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2503 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2504 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2505 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
2506 },
2507 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
2508 0, 0, 0, 0,
2509 0, 0, 0, 0,
2510 0, 0, 0, 0,
2511 0, 0, PORT209_DATA, PORT208_DATA,
2512 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
2513 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
2514 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
2515 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
2516 },
2517 { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
2518 0, 0, 0, 0,
2519 0, 0, 0, 0,
2520 0, 0, 0, 0,
2521 PORT211_DATA, PORT210_DATA, 0, 0,
2522 0, 0, 0, 0,
2523 0, 0, 0, 0,
2524 0, 0, 0, 0,
2525 0, 0, 0, 0 }
2526 },
2527 { },
2528};
2529
2530static struct pinmux_info r8a7740_pinmux_info = {
2531 .name = "r8a7740_pfc",
2532 .reserved_id = PINMUX_RESERVED,
2533 .data = { PINMUX_DATA_BEGIN,
2534 PINMUX_DATA_END },
2535 .input = { PINMUX_INPUT_BEGIN,
2536 PINMUX_INPUT_END },
2537 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
2538 PINMUX_INPUT_PULLUP_END },
2539 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN,
2540 PINMUX_INPUT_PULLDOWN_END },
2541 .output = { PINMUX_OUTPUT_BEGIN,
2542 PINMUX_OUTPUT_END },
2543 .mark = { PINMUX_MARK_BEGIN,
2544 PINMUX_MARK_END },
2545 .function = { PINMUX_FUNCTION_BEGIN,
2546 PINMUX_FUNCTION_END },
2547
2548 .first_gpio = GPIO_PORT0,
2549 .last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC,
2550
2551 .gpios = pinmux_gpios,
2552 .cfg_regs = pinmux_config_regs,
2553 .data_regs = pinmux_data_regs,
2554
2555 .gpio_data = pinmux_data,
2556 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2557};
2558
2559void r8a7740_pinmux_init(void)
2560{
2561 register_pinmux(&r8a7740_pinmux_info);
2562}
diff --git a/arch/arm/mach-shmobile/pfc-r8a7779.c b/arch/arm/mach-shmobile/pfc-r8a7779.c
new file mode 100644
index 000000000000..963532f2b2c4
--- /dev/null
+++ b/arch/arm/mach-shmobile/pfc-r8a7779.c
@@ -0,0 +1,2645 @@
1/*
2 * r8a7779 processor support - PFC hardware block
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/gpio.h>
23#include <linux/ioport.h>
24#include <mach/r8a7779.h>
25
26#define CPU_32_PORT(fn, pfx, sfx) \
27 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
28 PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
29 PORT_1(fn, pfx##31, sfx)
30
31#define CPU_32_PORT6(fn, pfx, sfx) \
32 PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
33 PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
34 PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
35 PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
36 PORT_1(fn, pfx##8, sfx)
37
38#define CPU_ALL_PORT(fn, pfx, sfx) \
39 CPU_32_PORT(fn, pfx##_0_, sfx), \
40 CPU_32_PORT(fn, pfx##_1_, sfx), \
41 CPU_32_PORT(fn, pfx##_2_, sfx), \
42 CPU_32_PORT(fn, pfx##_3_, sfx), \
43 CPU_32_PORT(fn, pfx##_4_, sfx), \
44 CPU_32_PORT(fn, pfx##_5_, sfx), \
45 CPU_32_PORT6(fn, pfx##_6_, sfx)
46
47#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
48#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
49 GP##pfx##_IN, GP##pfx##_OUT)
50
51#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
52#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
53
54#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
55#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
56#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
57
58
59#define PORT_10_REV(fn, pfx, sfx) \
60 PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
61 PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
62 PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
63 PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
64 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
65
66#define CPU_32_PORT_REV(fn, pfx, sfx) \
67 PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
68 PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
69 PORT_10_REV(fn, pfx, sfx)
70
71#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
72#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
73
74#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
75#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
76 FN_##ipsr, FN_##fn)
77
78enum {
79 PINMUX_RESERVED = 0,
80
81 PINMUX_DATA_BEGIN,
82 GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
83 PINMUX_DATA_END,
84
85 PINMUX_INPUT_BEGIN,
86 GP_ALL(IN), /* GP_0_0_IN -> GP_6_8_IN */
87 PINMUX_INPUT_END,
88
89 PINMUX_OUTPUT_BEGIN,
90 GP_ALL(OUT), /* GP_0_0_OUT -> GP_6_8_OUT */
91 PINMUX_OUTPUT_END,
92
93 PINMUX_FUNCTION_BEGIN,
94 GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
95
96 /* GPSR0 */
97 FN_AVS1, FN_AVS2, FN_IP0_7_6, FN_A17,
98 FN_A18, FN_A19, FN_IP0_9_8, FN_IP0_11_10,
99 FN_IP0_13_12, FN_IP0_15_14, FN_IP0_18_16, FN_IP0_22_19,
100 FN_IP0_24_23, FN_IP0_25, FN_IP0_27_26, FN_IP1_1_0,
101 FN_IP1_3_2, FN_IP1_6_4, FN_IP1_10_7, FN_IP1_14_11,
102 FN_IP1_18_15, FN_IP0_5_3, FN_IP0_30_28, FN_IP2_18_16,
103 FN_IP2_21_19, FN_IP2_30_28, FN_IP3_2_0, FN_IP3_11_9,
104 FN_IP3_14_12, FN_IP3_22_21, FN_IP3_26_24, FN_IP3_31_29,
105
106 /* GPSR1 */
107 FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, FN_IP4_10_8,
108 FN_IP4_11, FN_IP4_12, FN_IP4_13, FN_IP4_14,
109 FN_IP4_15, FN_IP4_16, FN_IP4_19_17, FN_IP4_22_20,
110 FN_IP4_23, FN_IP4_24, FN_IP4_25, FN_IP4_26,
111 FN_IP4_27, FN_IP4_28, FN_IP4_31_29, FN_IP5_2_0,
112 FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6,
113 FN_IP5_7, FN_IP5_8, FN_IP5_10_9, FN_IP5_12_11,
114 FN_IP5_14_13, FN_IP5_16_15, FN_IP5_20_17, FN_IP5_23_21,
115
116 /* GPSR2 */
117 FN_IP5_27_24, FN_IP8_20, FN_IP8_22_21, FN_IP8_24_23,
118 FN_IP8_27_25, FN_IP8_30_28, FN_IP9_1_0, FN_IP9_3_2,
119 FN_IP9_4, FN_IP9_5, FN_IP9_6, FN_IP9_7,
120 FN_IP9_9_8, FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14,
121 FN_IP9_18_16, FN_IP9_21_19, FN_IP9_23_22, FN_IP9_25_24,
122 FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
123 FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
124 FN_IP10_20_18, FN_IP10_23_21, FN_IP10_25_24, FN_IP10_28_26,
125
126 /* GPSR3 */
127 FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
128 FN_IP11_11_9, FN_IP11_14_12, FN_IP11_17_15, FN_IP11_20_18,
129 FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
130 FN_IP12_5_3, FN_IP12_8_6, FN_IP12_11_9, FN_IP12_14_12,
131 FN_IP12_17_15, FN_IP7_16_15, FN_IP7_18_17, FN_IP7_28_27,
132 FN_IP7_30_29, FN_IP7_20_19, FN_IP7_22_21, FN_IP7_24_23,
133 FN_IP7_26_25, FN_IP1_20_19, FN_IP1_22_21, FN_IP1_24_23,
134 FN_IP5_28, FN_IP5_30_29, FN_IP6_1_0, FN_IP6_3_2,
135
136 /* GPSR4 */
137 FN_IP6_5_4, FN_IP6_7_6, FN_IP6_8, FN_IP6_11_9,
138 FN_IP6_14_12, FN_IP6_17_15, FN_IP6_19_18, FN_IP6_22_20,
139 FN_IP6_24_23, FN_IP6_26_25, FN_IP6_30_29, FN_IP7_1_0,
140 FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
141 FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
142 FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
143 FN_IP8_11_8, FN_IP8_15_12, FN_PENC0, FN_PENC1,
144 FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
145
146 /* GPSR5 */
147 FN_A1, FN_A2, FN_A3, FN_A4,
148 FN_A5, FN_A6, FN_A7, FN_A8,
149 FN_A9, FN_A10, FN_A11, FN_A12,
150 FN_A13, FN_A14, FN_A15, FN_A16,
151 FN_RD, FN_WE0, FN_WE1, FN_EX_WAIT0,
152 FN_IP3_23, FN_IP3_27, FN_IP3_28, FN_IP2_22,
153 FN_IP2_23, FN_IP2_24, FN_IP2_25, FN_IP2_26,
154 FN_IP2_27, FN_IP3_3, FN_IP3_4, FN_IP3_5,
155
156 /* GPSR6 */
157 FN_IP3_6, FN_IP3_7, FN_IP3_8, FN_IP3_15,
158 FN_IP3_16, FN_IP3_17, FN_IP3_18, FN_IP3_19,
159 FN_IP3_20,
160
161 /* IPSR0 */
162 FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
163 FN_HRTS1, FN_RX4_C,
164 FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B,
165 FN_CS0, FN_HSPI_CS2_B,
166 FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B,
167 FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
168 FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
169 FN_CTS0_B,
170 FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
171 FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B,
172 FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
173 FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
174 FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B,
175 FN_A20, FN_TX5_D, FN_HSPI_TX2_B,
176 FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
177 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
178 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
179 FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
180 FN_SCIF_CLK, FN_TCLK0_C,
181
182 /* IPSR1 */
183 FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6,
184 FN_FD6, FN_EX_CS1, FN_MMC0_D7, FN_FD7,
185 FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
186 FN_ATACS00, FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD,
187 FN_FRE, FN_ATACS10, FN_VI1_R4, FN_RX5_B,
188 FN_HSCK1, FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9,
189 FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
190 FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
191 FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, FN_EX_CS5,
192 FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, FN_ATAWR0,
193 FN_VI1_R6, FN_HRX1, FN_RX2_E, FN_RX0_B,
194 FN_SSI_WS9, FN_MLB_CLK, FN_PWM2, FN_SCK4,
195 FN_MLB_SIG, FN_PWM3, FN_TX4, FN_MLB_DAT,
196 FN_PWM4, FN_RX4, FN_HTX0, FN_TX1,
197 FN_SDATA, FN_CTS0_C, FN_SUB_TCK, FN_CC5_STATE2,
198 FN_CC5_STATE10, FN_CC5_STATE18, FN_CC5_STATE26, FN_CC5_STATE34,
199
200 /* IPSR2 */
201 FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
202 FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
203 FN_CC5_STATE27, FN_CC5_STATE35, FN_HSCK0, FN_SCK1,
204 FN_MTS, FN_PWM5, FN_SCK0_C, FN_SSI_SDATA9_B,
205 FN_SUB_TDO, FN_CC5_STATE0, FN_CC5_STATE8, FN_CC5_STATE16,
206 FN_CC5_STATE24, FN_CC5_STATE32, FN_HCTS0, FN_CTS1,
207 FN_STM, FN_PWM0_D, FN_RX0_C, FN_SCIF_CLK_C,
208 FN_SUB_TRST, FN_TCLK1_B, FN_CC5_OSCOUT, FN_HRTS0,
209 FN_RTS1_TANS, FN_MDATA, FN_TX0_C, FN_SUB_TMS,
210 FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, FN_CC5_STATE25,
211 FN_CC5_STATE33, FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0,
212 FN_GPS_CLK_B, FN_AUDATA0, FN_TX5_C, FN_DU0_DR1,
213 FN_LCDOUT1, FN_DACK0, FN_DRACK0, FN_GPS_SIGN_B,
214 FN_AUDATA1, FN_RX5_C, FN_DU0_DR2, FN_LCDOUT2,
215 FN_DU0_DR3, FN_LCDOUT3, FN_DU0_DR4, FN_LCDOUT4,
216 FN_DU0_DR5, FN_LCDOUT5, FN_DU0_DR6, FN_LCDOUT6,
217 FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8,
218 FN_DREQ1, FN_SCL2, FN_AUDATA2,
219
220 /* IPSR3 */
221 FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
222 FN_AUDATA3, FN_DU0_DG2, FN_LCDOUT10, FN_DU0_DG3,
223 FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, FN_DU0_DG5,
224 FN_LCDOUT13, FN_DU0_DG6, FN_LCDOUT14, FN_DU0_DG7,
225 FN_LCDOUT15, FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1,
226 FN_SCL1, FN_TCLK1, FN_AUDATA4, FN_DU0_DB1,
227 FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, FN_GPS_MAG_B,
228 FN_AUDATA5, FN_SCK5_C, FN_DU0_DB2, FN_LCDOUT18,
229 FN_DU0_DB3, FN_LCDOUT19, FN_DU0_DB4, FN_LCDOUT20,
230 FN_DU0_DB5, FN_LCDOUT21, FN_DU0_DB6, FN_LCDOUT22,
231 FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
232 FN_TX3_D_IRDA_TX_D, FN_SCL3_B, FN_DU0_DOTCLKOUT0, FN_QCLK,
233 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
234 FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, FN_DU0_EXHSYNC_DU0_HSYNC,
235 FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
236 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX,
237 FN_TX2_C, FN_SCL2_C, FN_REMOCON,
238
239 /* IPSR4 */
240 FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C,
241 FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
242 FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, FN_DU1_DR0,
243 FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, FN_TX3_E_IRDA_TX_E,
244 FN_AUDCK, FN_PWMFSW0_B, FN_DU1_DR1, FN_VI2_DATA1_VI2_B1,
245 FN_PWM0, FN_SD3_CMD, FN_RX3_E_IRDA_RX_E, FN_AUDSYNC,
246 FN_CTS0_D, FN_DU1_DR2, FN_VI2_G0, FN_DU1_DR3,
247 FN_VI2_G1, FN_DU1_DR4, FN_VI2_G2, FN_DU1_DR5,
248 FN_VI2_G3, FN_DU1_DR6, FN_VI2_G4, FN_DU1_DR7,
249 FN_VI2_G5, FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B,
250 FN_SD3_DAT2, FN_SCK3_E, FN_AUDATA6, FN_TX0_D,
251 FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
252 FN_SCK5, FN_AUDATA7, FN_RX0_D, FN_DU1_DG2,
253 FN_VI2_G6, FN_DU1_DG3, FN_VI2_G7, FN_DU1_DG4,
254 FN_VI2_R0, FN_DU1_DG5, FN_VI2_R1, FN_DU1_DG6,
255 FN_VI2_R2, FN_DU1_DG7, FN_VI2_R3, FN_DU1_DB0,
256 FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, FN_TX5,
257 FN_SCK0_D,
258
259 /* IPSR5 */
260 FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
261 FN_RX5, FN_RTS0_D_TANS_D, FN_DU1_DB2, FN_VI2_R4,
262 FN_DU1_DB3, FN_VI2_R5, FN_DU1_DB4, FN_VI2_R6,
263 FN_DU1_DB5, FN_VI2_R7, FN_DU1_DB6, FN_SCL2_D,
264 FN_DU1_DB7, FN_SDA2_D, FN_DU1_DOTCLKIN, FN_VI2_CLKENB,
265 FN_HSPI_CS1, FN_SCL1_D, FN_DU1_DOTCLKOUT, FN_VI2_FIELD,
266 FN_SDA1_D, FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC,
267 FN_VI3_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC,
268 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
269 FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
270 FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D,
271 FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
272 FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
273 FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B,
274 FN_SD3_WP, FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD,
275 FN_AUDIO_CLKOUT, FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D,
276 FN_AUDIO_CLKA, FN_CAN_TXCLK, FN_AUDIO_CLKB, FN_USB_OVC2,
277 FN_CAN_DEBUGOUT0, FN_MOUT0,
278
279 /* IPSR6 */
280 FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, FN_SSI_WS0129,
281 FN_CAN_DEBUGOUT2, FN_MOUT2, FN_SSI_SDATA0, FN_CAN_DEBUGOUT3,
282 FN_MOUT5, FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6,
283 FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, FN_SSI_SCK34, FN_CAN_DEBUGOUT6,
284 FN_CAN0_TX_B, FN_IERX, FN_SSI_SCK9_C, FN_SSI_WS34,
285 FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, FN_SSI_WS9_C,
286 FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
287 FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, FN_SSI_SDATA4,
288 FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, FN_SSI_SCK5, FN_ADICLK,
289 FN_CAN_DEBUGOUT10, FN_SCK3, FN_TCLK0_D, FN_SSI_WS5,
290 FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, FN_SSI_SDATA5,
291 FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, FN_SSI_SCK6,
292 FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
293
294 /* IPSR7 */
295 FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B,
296 FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
297 FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
298 FN_HSPI_CLK1_C, FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B,
299 FN_SSI_WS9_B, FN_HSPI_CS1_C, FN_SSI_SDATA7, FN_CAN_DEBUGOUT15,
300 FN_IRQ2_B, FN_TCLK1_C, FN_HSPI_TX1_C, FN_SSI_SDATA8,
301 FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, FN_SD0_CLK,
302 FN_ATACS01, FN_SCK1_B, FN_SD0_CMD, FN_ATACS11,
303 FN_TX1_B, FN_CC5_TDO, FN_SD0_DAT0, FN_ATADIR1,
304 FN_RX1_B, FN_CC5_TRST, FN_SD0_DAT1, FN_ATAG1,
305 FN_SCK2_B, FN_CC5_TMS, FN_SD0_DAT2, FN_ATARD1,
306 FN_TX2_B, FN_CC5_TCK, FN_SD0_DAT3, FN_ATAWR1,
307 FN_RX2_B, FN_CC5_TDI, FN_SD0_CD, FN_DREQ2,
308 FN_RTS1_B_TANS_B, FN_SD0_WP, FN_DACK2, FN_CTS1_B,
309
310 /* IPSR8 */
311 FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
312 FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
313 FN_CC5_STATE36, FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1,
314 FN_AD_DI, FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21,
315 FN_CC5_STATE29, FN_CC5_STATE37, FN_HSPI_TX0, FN_TX0,
316 FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, FN_CC5_STATE6, FN_CC5_STATE14,
317 FN_CC5_STATE22, FN_CC5_STATE30, FN_CC5_STATE38, FN_HSPI_RX0,
318 FN_RX0, FN_CAN_STEP0, FN_AD_NCS, FN_CC5_STATE7,
319 FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, FN_CC5_STATE39,
320 FN_FMCLK, FN_RDS_CLK, FN_PCMOE, FN_BPFCLK,
321 FN_PCMWE, FN_FMIN, FN_RDS_DATA, FN_VI0_CLK,
322 FN_MMC1_CLK, FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B,
323 FN_MT1_SYNC, FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B,
324 FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
325 FN_MMC1_CMD, FN_HSCK1_B, FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B,
326 FN_RTS1_C_TANS_C, FN_RX4_D, FN_PWMFSW0_C,
327
328 /* IPSR9 */
329 FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, FN_VI0_DATA1_VI0_B1,
330 FN_HCTS1_B, FN_MT1_PWM, FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
331 FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
332 FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, FN_VI0_DATA6_VI0_B6, FN_MMC1_D4,
333 FN_ARM_TRACEDATA_0, FN_VI0_DATA7_VI0_B7, FN_MMC1_D5,
334 FN_ARM_TRACEDATA_1, FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0,
335 FN_ARM_TRACEDATA_2, FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1,
336 FN_ARM_TRACEDATA_3, FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6,
337 FN_ARM_TRACEDATA_4, FN_TS_SPSYNC0, FN_VI0_G3, FN_ETH_CRS_DV,
338 FN_MMC1_D7, FN_ARM_TRACEDATA_5, FN_TS_SDAT0, FN_VI0_G4,
339 FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, FN_VI0_G5,
340 FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, FN_VI0_G6,
341 FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, FN_VI0_G7,
342 FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
343
344 /* IPSR10 */
345 FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
346 FN_ARM_TRACEDATA_10, FN_DREQ0_C, FN_VI0_R1, FN_SSI_SDATA8_C,
347 FN_DACK1_B, FN_ARM_TRACEDATA_11, FN_DACK0_C, FN_DRACK0_C,
348 FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
349 FN_ARM_TRACEDATA_12, FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B,
350 FN_IRQ3, FN_ARM_TRACEDATA_13, FN_VI0_R4, FN_ETH_REFCLK,
351 FN_SD2_CD_B, FN_HSPI_CLK1_B, FN_ARM_TRACEDATA_14, FN_MT1_CLK,
352 FN_TS_SCK0, FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
353 FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, FN_VI0_R6,
354 FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, FN_TRACECLK,
355 FN_MT1_BEN, FN_PWMFSW0_D, FN_VI0_R7, FN_ETH_MDIO,
356 FN_DACK2_C, FN_HSPI_RX1_B, FN_SCIF_CLK_D, FN_TRACECTL,
357 FN_MT1_PEN, FN_VI1_CLK, FN_SIM_D, FN_SDA3,
358 FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
359 FN_PWMFSW0_E, FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4,
360 FN_SIM_CLK, FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3,
361
362 /* IPSR11 */
363 FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
364 FN_ADICLK_B, FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK,
365 FN_SPV_TMS, FN_ADICS_B_SAMP_B, FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2,
366 FN_MT0_D, FN_SPVTDI, FN_ADIDATA_B, FN_VI1_DATA3_VI1_B3,
367 FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, FN_ADICHS0_B,
368 FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
369 FN_HSPI_CLK1_D, FN_ADICHS1_B, FN_VI1_DATA5_VI1_B5, FN_SD2_CMD,
370 FN_MT0_SYNC, FN_SPA_TCK, FN_HSPI_CS1_D, FN_ADICHS2_B,
371 FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
372 FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM,
373 FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0,
374 FN_DU1_DOTCLKOUT1, FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
375 FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1,
376 FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B,
377
378 /* IPSR12 */
379 FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
380 FN_SCK2, FN_HSCK0_B, FN_VI1_G3, FN_VI3_DATA3,
381 FN_SSI_SCK2, FN_TS_SDAT1, FN_SCL1_C, FN_HTX0_B,
382 FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
383 FN_SIM_RST_B, FN_HRX0_B, FN_VI1_G5, FN_VI3_DATA5,
384 FN_GPS_CLK, FN_FSE, FN_TX4_B, FN_SIM_D_B,
385 FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
386 FN_RX4_B, FN_SIM_CLK_B, FN_VI1_G7, FN_VI3_DATA7,
387 FN_GPS_MAG, FN_FCE, FN_SCK4_B,
388
389 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
390 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
391 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
392 FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
393 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
394 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
395 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
396 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
397 FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2,
398 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
399 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
400 FN_SEL_VI0_0, FN_SEL_VI0_1,
401 FN_SEL_SD2_0, FN_SEL_SD2_1,
402 FN_SEL_INT3_0, FN_SEL_INT3_1,
403 FN_SEL_INT2_0, FN_SEL_INT2_1,
404 FN_SEL_INT1_0, FN_SEL_INT1_1,
405 FN_SEL_INT0_0, FN_SEL_INT0_1,
406 FN_SEL_IE_0, FN_SEL_IE_1,
407 FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2,
408 FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
409 FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2,
410
411 FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2,
412 FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
413 FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
414 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
415 FN_SEL_CAN0_0, FN_SEL_CAN0_1,
416 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
417 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
418 FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
419 FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4,
420 FN_SEL_ADI_0, FN_SEL_ADI_1,
421 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
422 FN_SEL_SIM_0, FN_SEL_SIM_1,
423 FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
424 FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
425 FN_SEL_I2C3_0, FN_SEL_I2C3_1,
426 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
427 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
428 PINMUX_FUNCTION_END,
429
430 PINMUX_MARK_BEGIN,
431 AVS1_MARK, AVS2_MARK, A17_MARK, A18_MARK,
432 A19_MARK,
433
434 RD_WR_MARK, FWE_MARK, ATAG0_MARK, VI1_R7_MARK,
435 HRTS1_MARK, RX4_C_MARK,
436 CS1_A26_MARK, HSPI_TX2_MARK, SDSELF_B_MARK,
437 CS0_MARK, HSPI_CS2_B_MARK,
438 CLKOUT_MARK, TX3C_IRDA_TX_C_MARK, PWM0_B_MARK,
439 A25_MARK, SD1_WP_MARK, MMC0_D5_MARK, FD5_MARK,
440 HSPI_RX2_MARK, VI1_R3_MARK, TX5_B_MARK, SSI_SDATA7_B_MARK, CTS0_B_MARK,
441 A24_MARK, SD1_CD_MARK, MMC0_D4_MARK, FD4_MARK,
442 HSPI_CS2_MARK, VI1_R2_MARK, SSI_WS78_B_MARK,
443 A23_MARK, FCLE_MARK, HSPI_CLK2_MARK, VI1_R1_MARK,
444 A22_MARK, RX5_D_MARK, HSPI_RX2_B_MARK, VI1_R0_MARK,
445 A21_MARK, SCK5_D_MARK, HSPI_CLK2_B_MARK,
446 A20_MARK, TX5_D_MARK, HSPI_TX2_B_MARK,
447 A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
448 BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
449 ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
450 PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
451 SCIF_CLK_MARK, TCLK0_C_MARK,
452
453 EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
454 FD6_MARK, EX_CS1_MARK, MMC0_D7_MARK, FD7_MARK,
455 EX_CS2_MARK, SD1_CLK_MARK, MMC0_CLK_MARK, FALE_MARK,
456 ATACS00_MARK, EX_CS3_MARK, SD1_CMD_MARK, MMC0_CMD_MARK,
457 FRE_MARK, ATACS10_MARK, VI1_R4_MARK, RX5_B_MARK,
458 HSCK1_MARK, SSI_SDATA8_B_MARK, RTS0_B_TANS_B_MARK, SSI_SDATA9_MARK,
459 EX_CS4_MARK, SD1_DAT0_MARK, MMC0_D0_MARK, FD0_MARK,
460 ATARD0_MARK, VI1_R5_MARK, SCK5_B_MARK, HTX1_MARK,
461 TX2_E_MARK, TX0_B_MARK, SSI_SCK9_MARK, EX_CS5_MARK,
462 SD1_DAT1_MARK, MMC0_D1_MARK, FD1_MARK, ATAWR0_MARK,
463 VI1_R6_MARK, HRX1_MARK, RX2_E_MARK, RX0_B_MARK,
464 SSI_WS9_MARK, MLB_CLK_MARK, PWM2_MARK, SCK4_MARK,
465 MLB_SIG_MARK, PWM3_MARK, TX4_MARK, MLB_DAT_MARK,
466 PWM4_MARK, RX4_MARK, HTX0_MARK, TX1_MARK,
467 SDATA_MARK, CTS0_C_MARK, SUB_TCK_MARK, CC5_STATE2_MARK,
468 CC5_STATE10_MARK, CC5_STATE18_MARK, CC5_STATE26_MARK, CC5_STATE34_MARK,
469
470 HRX0_MARK, RX1_MARK, SCKZ_MARK, RTS0_C_TANS_C_MARK,
471 SUB_TDI_MARK, CC5_STATE3_MARK, CC5_STATE11_MARK, CC5_STATE19_MARK,
472 CC5_STATE27_MARK, CC5_STATE35_MARK, HSCK0_MARK, SCK1_MARK,
473 MTS_MARK, PWM5_MARK, SCK0_C_MARK, SSI_SDATA9_B_MARK,
474 SUB_TDO_MARK, CC5_STATE0_MARK, CC5_STATE8_MARK, CC5_STATE16_MARK,
475 CC5_STATE24_MARK, CC5_STATE32_MARK, HCTS0_MARK, CTS1_MARK,
476 STM_MARK, PWM0_D_MARK, RX0_C_MARK, SCIF_CLK_C_MARK,
477 SUB_TRST_MARK, TCLK1_B_MARK, CC5_OSCOUT_MARK, HRTS0_MARK,
478 RTS1_TANS_MARK, MDATA_MARK, TX0_C_MARK, SUB_TMS_MARK,
479 CC5_STATE1_MARK, CC5_STATE9_MARK, CC5_STATE17_MARK, CC5_STATE25_MARK,
480 CC5_STATE33_MARK, DU0_DR0_MARK, LCDOUT0_MARK, DREQ0_MARK,
481 GPS_CLK_B_MARK, AUDATA0_MARK, TX5_C_MARK, DU0_DR1_MARK,
482 LCDOUT1_MARK, DACK0_MARK, DRACK0_MARK, GPS_SIGN_B_MARK,
483 AUDATA1_MARK, RX5_C_MARK, DU0_DR2_MARK, LCDOUT2_MARK,
484 DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK,
485 DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK,
486 DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK,
487 DREQ1_MARK, SCL2_MARK, AUDATA2_MARK,
488
489 DU0_DG1_MARK, LCDOUT9_MARK, DACK1_MARK, SDA2_MARK,
490 AUDATA3_MARK, DU0_DG2_MARK, LCDOUT10_MARK, DU0_DG3_MARK,
491 LCDOUT11_MARK, DU0_DG4_MARK, LCDOUT12_MARK, DU0_DG5_MARK,
492 LCDOUT13_MARK, DU0_DG6_MARK, LCDOUT14_MARK, DU0_DG7_MARK,
493 LCDOUT15_MARK, DU0_DB0_MARK, LCDOUT16_MARK, EX_WAIT1_MARK,
494 SCL1_MARK, TCLK1_MARK, AUDATA4_MARK, DU0_DB1_MARK,
495 LCDOUT17_MARK, EX_WAIT2_MARK, SDA1_MARK, GPS_MAG_B_MARK,
496 AUDATA5_MARK, SCK5_C_MARK, DU0_DB2_MARK, LCDOUT18_MARK,
497 DU0_DB3_MARK, LCDOUT19_MARK, DU0_DB4_MARK, LCDOUT20_MARK,
498 DU0_DB5_MARK, LCDOUT21_MARK, DU0_DB6_MARK, LCDOUT22_MARK,
499 DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
500 TX3_D_IRDA_TX_D_MARK, SCL3_B_MARK, DU0_DOTCLKOUT0_MARK, QCLK_MARK,
501 DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, RX3_D_IRDA_RX_D_MARK, SDA3_B_MARK,
502 SDA2_C_MARK, DACK0_B_MARK, DRACK0_B_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
503 QSTH_QHS_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
504 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CAN1_TX_MARK,
505 TX2_C_MARK, SCL2_C_MARK, REMOCON_MARK,
506
507 DU0_DISP_MARK, QPOLA_MARK, CAN_CLK_C_MARK, SCK2_C_MARK,
508 DU0_CDE_MARK, QPOLB_MARK, CAN1_RX_MARK, RX2_C_MARK,
509 DREQ0_B_MARK, SSI_SCK78_B_MARK, SCK0_B_MARK, DU1_DR0_MARK,
510 VI2_DATA0_VI2_B0_MARK, PWM6_MARK, SD3_CLK_MARK, TX3_E_IRDA_TX_E_MARK,
511 AUDCK_MARK, PWMFSW0_B_MARK, DU1_DR1_MARK, VI2_DATA1_VI2_B1_MARK,
512 PWM0_MARK, SD3_CMD_MARK, RX3_E_IRDA_RX_E_MARK, AUDSYNC_MARK,
513 CTS0_D_MARK, DU1_DR2_MARK, VI2_G0_MARK, DU1_DR3_MARK,
514 VI2_G1_MARK, DU1_DR4_MARK, VI2_G2_MARK, DU1_DR5_MARK,
515 VI2_G3_MARK, DU1_DR6_MARK, VI2_G4_MARK, DU1_DR7_MARK,
516 VI2_G5_MARK, DU1_DG0_MARK, VI2_DATA2_VI2_B2_MARK, SCL1_B_MARK,
517 SD3_DAT2_MARK, SCK3_E_MARK, AUDATA6_MARK, TX0_D_MARK,
518 DU1_DG1_MARK, VI2_DATA3_VI2_B3_MARK, SDA1_B_MARK, SD3_DAT3_MARK,
519 SCK5_MARK, AUDATA7_MARK, RX0_D_MARK, DU1_DG2_MARK,
520 VI2_G6_MARK, DU1_DG3_MARK, VI2_G7_MARK, DU1_DG4_MARK,
521 VI2_R0_MARK, DU1_DG5_MARK, VI2_R1_MARK, DU1_DG6_MARK,
522 VI2_R2_MARK, DU1_DG7_MARK, VI2_R3_MARK, DU1_DB0_MARK,
523 VI2_DATA4_VI2_B4_MARK, SCL2_B_MARK, SD3_DAT0_MARK, TX5_MARK,
524 SCK0_D_MARK,
525
526 DU1_DB1_MARK, VI2_DATA5_VI2_B5_MARK, SDA2_B_MARK, SD3_DAT1_MARK,
527 RX5_MARK, RTS0_D_TANS_D_MARK, DU1_DB2_MARK, VI2_R4_MARK,
528 DU1_DB3_MARK, VI2_R5_MARK, DU1_DB4_MARK, VI2_R6_MARK,
529 DU1_DB5_MARK, VI2_R7_MARK, DU1_DB6_MARK, SCL2_D_MARK,
530 DU1_DB7_MARK, SDA2_D_MARK, DU1_DOTCLKIN_MARK, VI2_CLKENB_MARK,
531 HSPI_CS1_MARK, SCL1_D_MARK, DU1_DOTCLKOUT_MARK, VI2_FIELD_MARK,
532 SDA1_D_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, VI2_HSYNC_MARK,
533 VI3_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, VI2_VSYNC_MARK,
534 VI3_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, VI2_CLK_MARK,
535 TX3_B_IRDA_TX_B_MARK, SD3_CD_MARK, HSPI_TX1_MARK, VI1_CLKENB_MARK,
536 VI3_CLKENB_MARK, AUDIO_CLKC_MARK, TX2_D_MARK, SPEEDIN_MARK,
537 GPS_SIGN_D_MARK, DU1_DISP_MARK, VI2_DATA6_VI2_B6_MARK, TCLK0_MARK,
538 QSTVA_B_QVS_B_MARK, HSPI_CLK1_MARK, SCK2_D_MARK, AUDIO_CLKOUT_B_MARK,
539 GPS_MAG_D_MARK, DU1_CDE_MARK, VI2_DATA7_VI2_B7_MARK,
540 RX3_B_IRDA_RX_B_MARK, SD3_WP_MARK, HSPI_RX1_MARK, VI1_FIELD_MARK,
541 VI3_FIELD_MARK, AUDIO_CLKOUT_MARK, RX2_D_MARK, GPS_CLK_C_MARK,
542 GPS_CLK_D_MARK, AUDIO_CLKA_MARK, CAN_TXCLK_MARK, AUDIO_CLKB_MARK,
543 USB_OVC2_MARK, CAN_DEBUGOUT0_MARK, MOUT0_MARK,
544
545 SSI_SCK0129_MARK, CAN_DEBUGOUT1_MARK, MOUT1_MARK, SSI_WS0129_MARK,
546 CAN_DEBUGOUT2_MARK, MOUT2_MARK, SSI_SDATA0_MARK, CAN_DEBUGOUT3_MARK,
547 MOUT5_MARK, SSI_SDATA1_MARK, CAN_DEBUGOUT4_MARK, MOUT6_MARK,
548 SSI_SDATA2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK34_MARK,
549 CAN_DEBUGOUT6_MARK, CAN0_TX_B_MARK, IERX_MARK, SSI_SCK9_C_MARK,
550 SSI_WS34_MARK, CAN_DEBUGOUT7_MARK, CAN0_RX_B_MARK, IETX_MARK,
551 SSI_WS9_C_MARK, SSI_SDATA3_MARK, PWM0_C_MARK, CAN_DEBUGOUT8_MARK,
552 CAN_CLK_B_MARK, IECLK_MARK, SCIF_CLK_B_MARK, TCLK0_B_MARK,
553 SSI_SDATA4_MARK, CAN_DEBUGOUT9_MARK, SSI_SDATA9_C_MARK, SSI_SCK5_MARK,
554 ADICLK_MARK, CAN_DEBUGOUT10_MARK, SCK3_MARK, TCLK0_D_MARK,
555 SSI_WS5_MARK, ADICS_SAMP_MARK, CAN_DEBUGOUT11_MARK, TX3_IRDA_TX_MARK,
556 SSI_SDATA5_MARK, ADIDATA_MARK, CAN_DEBUGOUT12_MARK, RX3_IRDA_RX_MARK,
557 SSI_SCK6_MARK, ADICHS0_MARK, CAN0_TX_MARK, IERX_B_MARK,
558
559 SSI_WS6_MARK, ADICHS1_MARK, CAN0_RX_MARK, IETX_B_MARK,
560 SSI_SDATA6_MARK, ADICHS2_MARK, CAN_CLK_MARK, IECLK_B_MARK,
561 SSI_SCK78_MARK, CAN_DEBUGOUT13_MARK, IRQ0_B_MARK, SSI_SCK9_B_MARK,
562 HSPI_CLK1_C_MARK, SSI_WS78_MARK, CAN_DEBUGOUT14_MARK, IRQ1_B_MARK,
563 SSI_WS9_B_MARK, HSPI_CS1_C_MARK, SSI_SDATA7_MARK, CAN_DEBUGOUT15_MARK,
564 IRQ2_B_MARK, TCLK1_C_MARK, HSPI_TX1_C_MARK, SSI_SDATA8_MARK,
565 VSP_MARK, IRQ3_B_MARK, HSPI_RX1_C_MARK, SD0_CLK_MARK,
566 ATACS01_MARK, SCK1_B_MARK, SD0_CMD_MARK, ATACS11_MARK,
567 TX1_B_MARK, CC5_TDO_MARK, SD0_DAT0_MARK, ATADIR1_MARK,
568 RX1_B_MARK, CC5_TRST_MARK, SD0_DAT1_MARK, ATAG1_MARK,
569 SCK2_B_MARK, CC5_TMS_MARK, SD0_DAT2_MARK, ATARD1_MARK,
570 TX2_B_MARK, CC5_TCK_MARK, SD0_DAT3_MARK, ATAWR1_MARK,
571 RX2_B_MARK, CC5_TDI_MARK, SD0_CD_MARK, DREQ2_MARK,
572 RTS1_B_TANS_B_MARK, SD0_WP_MARK, DACK2_MARK, CTS1_B_MARK,
573
574 HSPI_CLK0_MARK, CTS0_MARK, USB_OVC0_MARK, AD_CLK_MARK,
575 CC5_STATE4_MARK, CC5_STATE12_MARK, CC5_STATE20_MARK, CC5_STATE28_MARK,
576 CC5_STATE36_MARK, HSPI_CS0_MARK, RTS0_TANS_MARK, USB_OVC1_MARK,
577 AD_DI_MARK, CC5_STATE5_MARK, CC5_STATE13_MARK, CC5_STATE21_MARK,
578 CC5_STATE29_MARK, CC5_STATE37_MARK, HSPI_TX0_MARK, TX0_MARK,
579 CAN_DEBUG_HW_TRIGGER_MARK, AD_DO_MARK, CC5_STATE6_MARK,
580 CC5_STATE14_MARK, CC5_STATE22_MARK, CC5_STATE30_MARK,
581 CC5_STATE38_MARK, HSPI_RX0_MARK, RX0_MARK, CAN_STEP0_MARK,
582 AD_NCS_MARK, CC5_STATE7_MARK, CC5_STATE15_MARK, CC5_STATE23_MARK,
583 CC5_STATE31_MARK, CC5_STATE39_MARK, FMCLK_MARK, RDS_CLK_MARK,
584 PCMOE_MARK, BPFCLK_MARK, PCMWE_MARK, FMIN_MARK, RDS_DATA_MARK,
585 VI0_CLK_MARK, MMC1_CLK_MARK, VI0_CLKENB_MARK, TX1_C_MARK, HTX1_B_MARK,
586 MT1_SYNC_MARK, VI0_FIELD_MARK, RX1_C_MARK, HRX1_B_MARK,
587 VI0_HSYNC_MARK, VI0_DATA0_B_VI0_B0_B_MARK, CTS1_C_MARK, TX4_D_MARK,
588 MMC1_CMD_MARK, HSCK1_B_MARK, VI0_VSYNC_MARK, VI0_DATA1_B_VI0_B1_B_MARK,
589 RTS1_C_TANS_C_MARK, RX4_D_MARK, PWMFSW0_C_MARK,
590
591 VI0_DATA0_VI0_B0_MARK, HRTS1_B_MARK, MT1_VCXO_MARK,
592 VI0_DATA1_VI0_B1_MARK, HCTS1_B_MARK, MT1_PWM_MARK,
593 VI0_DATA2_VI0_B2_MARK, MMC1_D0_MARK, VI0_DATA3_VI0_B3_MARK,
594 MMC1_D1_MARK, VI0_DATA4_VI0_B4_MARK, MMC1_D2_MARK,
595 VI0_DATA5_VI0_B5_MARK, MMC1_D3_MARK, VI0_DATA6_VI0_B6_MARK,
596 MMC1_D4_MARK, ARM_TRACEDATA_0_MARK, VI0_DATA7_VI0_B7_MARK,
597 MMC1_D5_MARK, ARM_TRACEDATA_1_MARK, VI0_G0_MARK, SSI_SCK78_C_MARK,
598 IRQ0_MARK, ARM_TRACEDATA_2_MARK, VI0_G1_MARK, SSI_WS78_C_MARK,
599 IRQ1_MARK, ARM_TRACEDATA_3_MARK, VI0_G2_MARK, ETH_TXD1_MARK,
600 MMC1_D6_MARK, ARM_TRACEDATA_4_MARK, TS_SPSYNC0_MARK, VI0_G3_MARK,
601 ETH_CRS_DV_MARK, MMC1_D7_MARK, ARM_TRACEDATA_5_MARK, TS_SDAT0_MARK,
602 VI0_G4_MARK, ETH_TX_EN_MARK, SD2_DAT0_B_MARK, ARM_TRACEDATA_6_MARK,
603 VI0_G5_MARK, ETH_RX_ER_MARK, SD2_DAT1_B_MARK, ARM_TRACEDATA_7_MARK,
604 VI0_G6_MARK, ETH_RXD0_MARK, SD2_DAT2_B_MARK, ARM_TRACEDATA_8_MARK,
605 VI0_G7_MARK, ETH_RXD1_MARK, SD2_DAT3_B_MARK, ARM_TRACEDATA_9_MARK,
606
607 VI0_R0_MARK, SSI_SDATA7_C_MARK, SCK1_C_MARK, DREQ1_B_MARK,
608 ARM_TRACEDATA_10_MARK, DREQ0_C_MARK, VI0_R1_MARK, SSI_SDATA8_C_MARK,
609 DACK1_B_MARK, ARM_TRACEDATA_11_MARK, DACK0_C_MARK, DRACK0_C_MARK,
610 VI0_R2_MARK, ETH_LINK_MARK, SD2_CLK_B_MARK, IRQ2_MARK,
611 ARM_TRACEDATA_12_MARK, VI0_R3_MARK, ETH_MAGIC_MARK, SD2_CMD_B_MARK,
612 IRQ3_MARK, ARM_TRACEDATA_13_MARK, VI0_R4_MARK, ETH_REFCLK_MARK,
613 SD2_CD_B_MARK, HSPI_CLK1_B_MARK, ARM_TRACEDATA_14_MARK, MT1_CLK_MARK,
614 TS_SCK0_MARK, VI0_R5_MARK, ETH_TXD0_MARK, SD2_WP_B_MARK,
615 HSPI_CS1_B_MARK, ARM_TRACEDATA_15_MARK, MT1_D_MARK, TS_SDEN0_MARK,
616 VI0_R6_MARK, ETH_MDC_MARK, DREQ2_C_MARK, HSPI_TX1_B_MARK,
617 TRACECLK_MARK, MT1_BEN_MARK, PWMFSW0_D_MARK, VI0_R7_MARK,
618 ETH_MDIO_MARK, DACK2_C_MARK, HSPI_RX1_B_MARK, SCIF_CLK_D_MARK,
619 TRACECTL_MARK, MT1_PEN_MARK, VI1_CLK_MARK, SIM_D_MARK, SDA3_MARK,
620 VI1_HSYNC_MARK, VI3_CLK_MARK, SSI_SCK4_MARK, GPS_SIGN_C_MARK,
621 PWMFSW0_E_MARK, VI1_VSYNC_MARK, AUDIO_CLKOUT_C_MARK, SSI_WS4_MARK,
622 SIM_CLK_MARK, GPS_MAG_C_MARK, SPV_TRST_MARK, SCL3_MARK,
623
624 VI1_DATA0_VI1_B0_MARK, SD2_DAT0_MARK, SIM_RST_MARK, SPV_TCK_MARK,
625 ADICLK_B_MARK, VI1_DATA1_VI1_B1_MARK, SD2_DAT1_MARK, MT0_CLK_MARK,
626 SPV_TMS_MARK, ADICS_B_SAMP_B_MARK, VI1_DATA2_VI1_B2_MARK,
627 SD2_DAT2_MARK, MT0_D_MARK, SPVTDI_MARK, ADIDATA_B_MARK,
628 VI1_DATA3_VI1_B3_MARK, SD2_DAT3_MARK, MT0_BEN_MARK, SPV_TDO_MARK,
629 ADICHS0_B_MARK, VI1_DATA4_VI1_B4_MARK, SD2_CLK_MARK, MT0_PEN_MARK,
630 SPA_TRST_MARK, HSPI_CLK1_D_MARK, ADICHS1_B_MARK,
631 VI1_DATA5_VI1_B5_MARK, SD2_CMD_MARK, MT0_SYNC_MARK, SPA_TCK_MARK,
632 HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK,
633 MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK,
634 SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK,
635 VI1_G0_MARK, VI3_DATA0_MARK, DU1_DOTCLKOUT1_MARK, TS_SCK1_MARK,
636 DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK,
637 VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK,
638 DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK,
639
640 VI1_G2_MARK, VI3_DATA2_MARK, SSI_WS1_MARK, TS_SPSYNC1_MARK,
641 SCK2_MARK, HSCK0_B_MARK, VI1_G3_MARK, VI3_DATA3_MARK,
642 SSI_SCK2_MARK, TS_SDAT1_MARK, SCL1_C_MARK, HTX0_B_MARK,
643 VI1_G4_MARK, VI3_DATA4_MARK, SSI_WS2_MARK, SDA1_C_MARK,
644 SIM_RST_B_MARK, HRX0_B_MARK, VI1_G5_MARK, VI3_DATA5_MARK,
645 GPS_CLK_MARK, FSE_MARK, TX4_B_MARK, SIM_D_B_MARK,
646 VI1_G6_MARK, VI3_DATA6_MARK, GPS_SIGN_MARK, FRB_MARK,
647 RX4_B_MARK, SIM_CLK_B_MARK, VI1_G7_MARK, VI3_DATA7_MARK,
648 GPS_MAG_MARK, FCE_MARK, SCK4_B_MARK,
649 PINMUX_MARK_END,
650};
651
652static pinmux_enum_t pinmux_data[] = {
653 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
654
655 PINMUX_DATA(AVS1_MARK, FN_AVS1),
656 PINMUX_DATA(AVS1_MARK, FN_AVS1),
657 PINMUX_DATA(A17_MARK, FN_A17),
658 PINMUX_DATA(A18_MARK, FN_A18),
659 PINMUX_DATA(A19_MARK, FN_A19),
660
661 PINMUX_IPSR_DATA(IP0_2_0, PENC2),
662 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
663 PINMUX_IPSR_DATA(IP0_2_0, PWM1),
664 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
665 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
666 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, TCLK0_C, SEL_TMU0_2),
667 PINMUX_IPSR_DATA(IP0_5_3, BS),
668 PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2),
669 PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2),
670 PINMUX_IPSR_DATA(IP0_5_3, FD2),
671 PINMUX_IPSR_DATA(IP0_5_3, ATADIR0),
672 PINMUX_IPSR_DATA(IP0_5_3, SDSELF),
673 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, HCTS1, SEL_HSCIF1_0),
674 PINMUX_IPSR_DATA(IP0_5_3, TX4_C),
675 PINMUX_IPSR_DATA(IP0_7_6, A0),
676 PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3),
677 PINMUX_IPSR_DATA(IP0_7_6, MMC0_D3),
678 PINMUX_IPSR_DATA(IP0_7_6, FD3),
679 PINMUX_IPSR_DATA(IP0_9_8, A20),
680 PINMUX_IPSR_DATA(IP0_9_8, TX5_D),
681 PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B),
682 PINMUX_IPSR_DATA(IP0_11_10, A21),
683 PINMUX_IPSR_MODSEL_DATA(IP0_11_10, SCK5_D, SEL_SCIF5_3),
684 PINMUX_IPSR_MODSEL_DATA(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
685 PINMUX_IPSR_DATA(IP0_13_12, A22),
686 PINMUX_IPSR_MODSEL_DATA(IP0_13_12, RX5_D, SEL_SCIF5_3),
687 PINMUX_IPSR_MODSEL_DATA(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
688 PINMUX_IPSR_DATA(IP0_13_12, VI1_R0),
689 PINMUX_IPSR_DATA(IP0_15_14, A23),
690 PINMUX_IPSR_DATA(IP0_15_14, FCLE),
691 PINMUX_IPSR_MODSEL_DATA(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
692 PINMUX_IPSR_DATA(IP0_15_14, VI1_R1),
693 PINMUX_IPSR_DATA(IP0_18_16, A24),
694 PINMUX_IPSR_DATA(IP0_18_16, SD1_CD),
695 PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4),
696 PINMUX_IPSR_DATA(IP0_18_16, FD4),
697 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
698 PINMUX_IPSR_DATA(IP0_18_16, VI1_R2),
699 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
700 PINMUX_IPSR_DATA(IP0_22_19, A25),
701 PINMUX_IPSR_DATA(IP0_22_19, SD1_WP),
702 PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5),
703 PINMUX_IPSR_DATA(IP0_22_19, FD5),
704 PINMUX_IPSR_MODSEL_DATA(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
705 PINMUX_IPSR_DATA(IP0_22_19, VI1_R3),
706 PINMUX_IPSR_DATA(IP0_22_19, TX5_B),
707 PINMUX_IPSR_MODSEL_DATA(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
708 PINMUX_IPSR_MODSEL_DATA(IP0_22_19, CTS0_B, SEL_SCIF0_1),
709 PINMUX_IPSR_DATA(IP0_24_23, CLKOUT),
710 PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C),
711 PINMUX_IPSR_DATA(IP0_24_23, PWM0_B),
712 PINMUX_IPSR_DATA(IP0_25, CS0),
713 PINMUX_IPSR_MODSEL_DATA(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
714 PINMUX_IPSR_DATA(IP0_27_26, CS1_A26),
715 PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2),
716 PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B),
717 PINMUX_IPSR_DATA(IP0_30_28, RD_WR),
718 PINMUX_IPSR_DATA(IP0_30_28, FWE),
719 PINMUX_IPSR_DATA(IP0_30_28, ATAG0),
720 PINMUX_IPSR_DATA(IP0_30_28, VI1_R7),
721 PINMUX_IPSR_MODSEL_DATA(IP0_30_28, HRTS1, SEL_HSCIF1_0),
722 PINMUX_IPSR_MODSEL_DATA(IP0_30_28, RX4_C, SEL_SCIF4_2),
723
724 PINMUX_IPSR_DATA(IP1_1_0, EX_CS0),
725 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
726 PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6),
727 PINMUX_IPSR_DATA(IP1_1_0, FD6),
728 PINMUX_IPSR_DATA(IP1_3_2, EX_CS1),
729 PINMUX_IPSR_DATA(IP1_3_2, MMC0_D7),
730 PINMUX_IPSR_DATA(IP1_3_2, FD7),
731 PINMUX_IPSR_DATA(IP1_6_4, EX_CS2),
732 PINMUX_IPSR_DATA(IP1_6_4, SD1_CLK),
733 PINMUX_IPSR_DATA(IP1_6_4, MMC0_CLK),
734 PINMUX_IPSR_DATA(IP1_6_4, FALE),
735 PINMUX_IPSR_DATA(IP1_6_4, ATACS00),
736 PINMUX_IPSR_DATA(IP1_10_7, EX_CS3),
737 PINMUX_IPSR_DATA(IP1_10_7, SD1_CMD),
738 PINMUX_IPSR_DATA(IP1_10_7, MMC0_CMD),
739 PINMUX_IPSR_DATA(IP1_10_7, FRE),
740 PINMUX_IPSR_DATA(IP1_10_7, ATACS10),
741 PINMUX_IPSR_DATA(IP1_10_7, VI1_R4),
742 PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RX5_B, SEL_SCIF5_1),
743 PINMUX_IPSR_MODSEL_DATA(IP1_10_7, HSCK1, SEL_HSCIF1_0),
744 PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
745 PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
746 PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
747 PINMUX_IPSR_DATA(IP1_14_11, EX_CS4),
748 PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0),
749 PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0),
750 PINMUX_IPSR_DATA(IP1_14_11, FD0),
751 PINMUX_IPSR_DATA(IP1_14_11, ATARD0),
752 PINMUX_IPSR_DATA(IP1_14_11, VI1_R5),
753 PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SCK5_B, SEL_SCIF5_1),
754 PINMUX_IPSR_DATA(IP1_14_11, HTX1),
755 PINMUX_IPSR_DATA(IP1_14_11, TX2_E),
756 PINMUX_IPSR_DATA(IP1_14_11, TX0_B),
757 PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
758 PINMUX_IPSR_DATA(IP1_18_15, EX_CS5),
759 PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1),
760 PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1),
761 PINMUX_IPSR_DATA(IP1_18_15, FD1),
762 PINMUX_IPSR_DATA(IP1_18_15, ATAWR0),
763 PINMUX_IPSR_DATA(IP1_18_15, VI1_R6),
764 PINMUX_IPSR_MODSEL_DATA(IP1_18_15, HRX1, SEL_HSCIF1_0),
765 PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX2_E, SEL_SCIF2_4),
766 PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX0_B, SEL_SCIF0_1),
767 PINMUX_IPSR_MODSEL_DATA(IP1_18_15, SSI_WS9, SEL_SSI9_0),
768 PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK),
769 PINMUX_IPSR_DATA(IP1_20_19, PWM2),
770 PINMUX_IPSR_MODSEL_DATA(IP1_20_19, SCK4, SEL_SCIF4_0),
771 PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG),
772 PINMUX_IPSR_DATA(IP1_22_21, PWM3),
773 PINMUX_IPSR_DATA(IP1_22_21, TX4),
774 PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT),
775 PINMUX_IPSR_DATA(IP1_24_23, PWM4),
776 PINMUX_IPSR_MODSEL_DATA(IP1_24_23, RX4, SEL_SCIF4_0),
777 PINMUX_IPSR_DATA(IP1_28_25, HTX0),
778 PINMUX_IPSR_DATA(IP1_28_25, TX1),
779 PINMUX_IPSR_DATA(IP1_28_25, SDATA),
780 PINMUX_IPSR_MODSEL_DATA(IP1_28_25, CTS0_C, SEL_SCIF0_2),
781 PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK),
782 PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2),
783 PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10),
784 PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE18),
785 PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26),
786 PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34),
787
788 PINMUX_IPSR_MODSEL_DATA(IP2_3_0, HRX0, SEL_HSCIF0_0),
789 PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RX1, SEL_SCIF1_0),
790 PINMUX_IPSR_DATA(IP2_3_0, SCKZ),
791 PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
792 PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI),
793 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3),
794 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11),
795 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19),
796 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27),
797 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35),
798 PINMUX_IPSR_MODSEL_DATA(IP2_7_4, HSCK0, SEL_HSCIF0_0),
799 PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK1, SEL_SCIF1_0),
800 PINMUX_IPSR_DATA(IP2_7_4, MTS),
801 PINMUX_IPSR_DATA(IP2_7_4, PWM5),
802 PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK0_C, SEL_SCIF0_2),
803 PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
804 PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO),
805 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0),
806 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8),
807 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16),
808 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24),
809 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32),
810 PINMUX_IPSR_MODSEL_DATA(IP2_11_8, HCTS0, SEL_HSCIF0_0),
811 PINMUX_IPSR_MODSEL_DATA(IP2_11_8, CTS1, SEL_SCIF1_0),
812 PINMUX_IPSR_DATA(IP2_11_8, STM),
813 PINMUX_IPSR_DATA(IP2_11_8, PWM0_D),
814 PINMUX_IPSR_MODSEL_DATA(IP2_11_8, RX0_C, SEL_SCIF0_2),
815 PINMUX_IPSR_MODSEL_DATA(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
816 PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST),
817 PINMUX_IPSR_MODSEL_DATA(IP2_11_8, TCLK1_B, SEL_TMU1_1),
818 PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT),
819 PINMUX_IPSR_MODSEL_DATA(IP2_15_12, HRTS0, SEL_HSCIF0_0),
820 PINMUX_IPSR_MODSEL_DATA(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
821 PINMUX_IPSR_DATA(IP2_15_12, MDATA),
822 PINMUX_IPSR_DATA(IP2_15_12, TX0_C),
823 PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS),
824 PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE1),
825 PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE9),
826 PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE17),
827 PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE25),
828 PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33),
829 PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0),
830 PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0),
831 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ0, SEL_EXBUS0_0),
832 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
833 PINMUX_IPSR_DATA(IP2_18_16, AUDATA0),
834 PINMUX_IPSR_DATA(IP2_18_16, TX5_C),
835 PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1),
836 PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1),
837 PINMUX_IPSR_DATA(IP2_21_19, DACK0),
838 PINMUX_IPSR_DATA(IP2_21_19, DRACK0),
839 PINMUX_IPSR_MODSEL_DATA(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
840 PINMUX_IPSR_DATA(IP2_21_19, AUDATA1),
841 PINMUX_IPSR_MODSEL_DATA(IP2_21_19, RX5_C, SEL_SCIF5_2),
842 PINMUX_IPSR_DATA(IP2_22, DU0_DR2),
843 PINMUX_IPSR_DATA(IP2_22, LCDOUT2),
844 PINMUX_IPSR_DATA(IP2_23, DU0_DR3),
845 PINMUX_IPSR_DATA(IP2_23, LCDOUT3),
846 PINMUX_IPSR_DATA(IP2_24, DU0_DR4),
847 PINMUX_IPSR_DATA(IP2_24, LCDOUT4),
848 PINMUX_IPSR_DATA(IP2_25, DU0_DR5),
849 PINMUX_IPSR_DATA(IP2_25, LCDOUT5),
850 PINMUX_IPSR_DATA(IP2_26, DU0_DR6),
851 PINMUX_IPSR_DATA(IP2_26, LCDOUT6),
852 PINMUX_IPSR_DATA(IP2_27, DU0_DR7),
853 PINMUX_IPSR_DATA(IP2_27, LCDOUT7),
854 PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0),
855 PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8),
856 PINMUX_IPSR_MODSEL_DATA(IP2_30_28, DREQ1, SEL_EXBUS1_0),
857 PINMUX_IPSR_MODSEL_DATA(IP2_30_28, SCL2, SEL_I2C2_0),
858 PINMUX_IPSR_DATA(IP2_30_28, AUDATA2),
859
860 PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1),
861 PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9),
862 PINMUX_IPSR_DATA(IP3_2_0, DACK1),
863 PINMUX_IPSR_MODSEL_DATA(IP3_2_0, SDA2, SEL_I2C2_0),
864 PINMUX_IPSR_DATA(IP3_2_0, AUDATA3),
865 PINMUX_IPSR_DATA(IP3_3, DU0_DG2),
866 PINMUX_IPSR_DATA(IP3_3, LCDOUT10),
867 PINMUX_IPSR_DATA(IP3_4, DU0_DG3),
868 PINMUX_IPSR_DATA(IP3_4, LCDOUT11),
869 PINMUX_IPSR_DATA(IP3_5, DU0_DG4),
870 PINMUX_IPSR_DATA(IP3_5, LCDOUT12),
871 PINMUX_IPSR_DATA(IP3_6, DU0_DG5),
872 PINMUX_IPSR_DATA(IP3_6, LCDOUT13),
873 PINMUX_IPSR_DATA(IP3_7, DU0_DG6),
874 PINMUX_IPSR_DATA(IP3_7, LCDOUT14),
875 PINMUX_IPSR_DATA(IP3_8, DU0_DG7),
876 PINMUX_IPSR_DATA(IP3_8, LCDOUT15),
877 PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0),
878 PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16),
879 PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1),
880 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCL1, SEL_I2C1_0),
881 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, TCLK1, SEL_TMU1_0),
882 PINMUX_IPSR_DATA(IP3_11_9, AUDATA4),
883 PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1),
884 PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17),
885 PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2),
886 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SDA1, SEL_I2C1_0),
887 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
888 PINMUX_IPSR_DATA(IP3_14_12, AUDATA5),
889 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCK5_C, SEL_SCIF5_2),
890 PINMUX_IPSR_DATA(IP3_15, DU0_DB2),
891 PINMUX_IPSR_DATA(IP3_15, LCDOUT18),
892 PINMUX_IPSR_DATA(IP3_16, DU0_DB3),
893 PINMUX_IPSR_DATA(IP3_16, LCDOUT19),
894 PINMUX_IPSR_DATA(IP3_17, DU0_DB4),
895 PINMUX_IPSR_DATA(IP3_17, LCDOUT20),
896 PINMUX_IPSR_DATA(IP3_18, DU0_DB5),
897 PINMUX_IPSR_DATA(IP3_18, LCDOUT21),
898 PINMUX_IPSR_DATA(IP3_19, DU0_DB6),
899 PINMUX_IPSR_DATA(IP3_19, LCDOUT22),
900 PINMUX_IPSR_DATA(IP3_20, DU0_DB7),
901 PINMUX_IPSR_DATA(IP3_20, LCDOUT23),
902 PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN),
903 PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS),
904 PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D),
905 PINMUX_IPSR_MODSEL_DATA(IP3_22_21, SCL3_B, SEL_I2C3_1),
906 PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0),
907 PINMUX_IPSR_DATA(IP3_23, QCLK),
908 PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1),
909 PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE),
910 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
911 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA3_B, SEL_I2C3_1),
912 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA2_C, SEL_I2C2_2),
913 PINMUX_IPSR_DATA(IP3_26_24, DACK0_B),
914 PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B),
915 PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
916 PINMUX_IPSR_DATA(IP3_27, QSTH_QHS),
917 PINMUX_IPSR_DATA(IP3_28, DU0_EXVSYNC_DU0_VSYNC),
918 PINMUX_IPSR_DATA(IP3_28, QSTB_QHE),
919 PINMUX_IPSR_DATA(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE),
920 PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE),
921 PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX),
922 PINMUX_IPSR_DATA(IP3_31_29, TX2_C),
923 PINMUX_IPSR_MODSEL_DATA(IP3_31_29, SCL2_C, SEL_I2C2_2),
924 PINMUX_IPSR_DATA(IP3_31_29, REMOCON),
925
926 PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP),
927 PINMUX_IPSR_DATA(IP4_1_0, QPOLA),
928 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
929 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCK2_C, SEL_SCIF2_2),
930 PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE),
931 PINMUX_IPSR_DATA(IP4_4_2, QPOLB),
932 PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX),
933 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, RX2_C, SEL_SCIF2_2),
934 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
935 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
936 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCK0_B, SEL_SCIF0_1),
937 PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0),
938 PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0),
939 PINMUX_IPSR_DATA(IP4_7_5, PWM6),
940 PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK),
941 PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E),
942 PINMUX_IPSR_DATA(IP4_7_5, AUDCK),
943 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
944 PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1),
945 PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1),
946 PINMUX_IPSR_DATA(IP4_10_8, PWM0),
947 PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD),
948 PINMUX_IPSR_MODSEL_DATA(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
949 PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC),
950 PINMUX_IPSR_MODSEL_DATA(IP4_10_8, CTS0_D, SEL_SCIF0_3),
951 PINMUX_IPSR_DATA(IP4_11, DU1_DR2),
952 PINMUX_IPSR_DATA(IP4_11, VI2_G0),
953 PINMUX_IPSR_DATA(IP4_12, DU1_DR3),
954 PINMUX_IPSR_DATA(IP4_12, VI2_G1),
955 PINMUX_IPSR_DATA(IP4_13, DU1_DR4),
956 PINMUX_IPSR_DATA(IP4_13, VI2_G2),
957 PINMUX_IPSR_DATA(IP4_14, DU1_DR5),
958 PINMUX_IPSR_DATA(IP4_14, VI2_G3),
959 PINMUX_IPSR_DATA(IP4_15, DU1_DR6),
960 PINMUX_IPSR_DATA(IP4_15, VI2_G4),
961 PINMUX_IPSR_DATA(IP4_16, DU1_DR7),
962 PINMUX_IPSR_DATA(IP4_16, VI2_G5),
963 PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0),
964 PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2),
965 PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCL1_B, SEL_I2C1_1),
966 PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2),
967 PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCK3_E, SEL_SCIF3_4),
968 PINMUX_IPSR_DATA(IP4_19_17, AUDATA6),
969 PINMUX_IPSR_DATA(IP4_19_17, TX0_D),
970 PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1),
971 PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3),
972 PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SDA1_B, SEL_I2C1_1),
973 PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3),
974 PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCK5, SEL_SCIF5_0),
975 PINMUX_IPSR_DATA(IP4_22_20, AUDATA7),
976 PINMUX_IPSR_MODSEL_DATA(IP4_22_20, RX0_D, SEL_SCIF0_3),
977 PINMUX_IPSR_DATA(IP4_23, DU1_DG2),
978 PINMUX_IPSR_DATA(IP4_23, VI2_G6),
979 PINMUX_IPSR_DATA(IP4_24, DU1_DG3),
980 PINMUX_IPSR_DATA(IP4_24, VI2_G7),
981 PINMUX_IPSR_DATA(IP4_25, DU1_DG4),
982 PINMUX_IPSR_DATA(IP4_25, VI2_R0),
983 PINMUX_IPSR_DATA(IP4_26, DU1_DG5),
984 PINMUX_IPSR_DATA(IP4_26, VI2_R1),
985 PINMUX_IPSR_DATA(IP4_27, DU1_DG6),
986 PINMUX_IPSR_DATA(IP4_27, VI2_R2),
987 PINMUX_IPSR_DATA(IP4_28, DU1_DG7),
988 PINMUX_IPSR_DATA(IP4_28, VI2_R3),
989 PINMUX_IPSR_DATA(IP4_31_29, DU1_DB0),
990 PINMUX_IPSR_DATA(IP4_31_29, VI2_DATA4_VI2_B4),
991 PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCL2_B, SEL_I2C2_1),
992 PINMUX_IPSR_DATA(IP4_31_29, SD3_DAT0),
993 PINMUX_IPSR_DATA(IP4_31_29, TX5),
994 PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCK0_D, SEL_SCIF0_3),
995
996 PINMUX_IPSR_DATA(IP5_2_0, DU1_DB1),
997 PINMUX_IPSR_DATA(IP5_2_0, VI2_DATA5_VI2_B5),
998 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SDA2_B, SEL_I2C2_1),
999 PINMUX_IPSR_DATA(IP5_2_0, SD3_DAT1),
1000 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX5, SEL_SCIF5_0),
1001 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
1002 PINMUX_IPSR_DATA(IP5_3, DU1_DB2),
1003 PINMUX_IPSR_DATA(IP5_3, VI2_R4),
1004 PINMUX_IPSR_DATA(IP5_4, DU1_DB3),
1005 PINMUX_IPSR_DATA(IP5_4, VI2_R5),
1006 PINMUX_IPSR_DATA(IP5_5, DU1_DB4),
1007 PINMUX_IPSR_DATA(IP5_5, VI2_R6),
1008 PINMUX_IPSR_DATA(IP5_6, DU1_DB5),
1009 PINMUX_IPSR_DATA(IP5_6, VI2_R7),
1010 PINMUX_IPSR_DATA(IP5_7, DU1_DB6),
1011 PINMUX_IPSR_MODSEL_DATA(IP5_7, SCL2_D, SEL_I2C2_3),
1012 PINMUX_IPSR_DATA(IP5_8, DU1_DB7),
1013 PINMUX_IPSR_MODSEL_DATA(IP5_8, SDA2_D, SEL_I2C2_3),
1014 PINMUX_IPSR_DATA(IP5_10_9, DU1_DOTCLKIN),
1015 PINMUX_IPSR_DATA(IP5_10_9, VI2_CLKENB),
1016 PINMUX_IPSR_MODSEL_DATA(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
1017 PINMUX_IPSR_MODSEL_DATA(IP5_10_9, SCL1_D, SEL_I2C1_3),
1018 PINMUX_IPSR_DATA(IP5_12_11, DU1_DOTCLKOUT),
1019 PINMUX_IPSR_DATA(IP5_12_11, VI2_FIELD),
1020 PINMUX_IPSR_MODSEL_DATA(IP5_12_11, SDA1_D, SEL_I2C1_3),
1021 PINMUX_IPSR_DATA(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
1022 PINMUX_IPSR_DATA(IP5_14_13, VI2_HSYNC),
1023 PINMUX_IPSR_DATA(IP5_14_13, VI3_HSYNC),
1024 PINMUX_IPSR_DATA(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC),
1025 PINMUX_IPSR_DATA(IP5_16_15, VI2_VSYNC),
1026 PINMUX_IPSR_DATA(IP5_16_15, VI3_VSYNC),
1027 PINMUX_IPSR_DATA(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1028 PINMUX_IPSR_DATA(IP5_20_17, VI2_CLK),
1029 PINMUX_IPSR_DATA(IP5_20_17, TX3_B_IRDA_TX_B),
1030 PINMUX_IPSR_DATA(IP5_20_17, SD3_CD),
1031 PINMUX_IPSR_DATA(IP5_20_17, HSPI_TX1),
1032 PINMUX_IPSR_DATA(IP5_20_17, VI1_CLKENB),
1033 PINMUX_IPSR_DATA(IP5_20_17, VI3_CLKENB),
1034 PINMUX_IPSR_DATA(IP5_20_17, AUDIO_CLKC),
1035 PINMUX_IPSR_DATA(IP5_20_17, TX2_D),
1036 PINMUX_IPSR_DATA(IP5_20_17, SPEEDIN),
1037 PINMUX_IPSR_MODSEL_DATA(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
1038 PINMUX_IPSR_DATA(IP5_23_21, DU1_DISP),
1039 PINMUX_IPSR_DATA(IP5_23_21, VI2_DATA6_VI2_B6),
1040 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, TCLK0, SEL_TMU0_0),
1041 PINMUX_IPSR_DATA(IP5_23_21, QSTVA_B_QVS_B),
1042 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
1043 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCK2_D, SEL_SCIF2_3),
1044 PINMUX_IPSR_DATA(IP5_23_21, AUDIO_CLKOUT_B),
1045 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
1046 PINMUX_IPSR_DATA(IP5_27_24, DU1_CDE),
1047 PINMUX_IPSR_DATA(IP5_27_24, VI2_DATA7_VI2_B7),
1048 PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
1049 PINMUX_IPSR_DATA(IP5_27_24, SD3_WP),
1050 PINMUX_IPSR_MODSEL_DATA(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
1051 PINMUX_IPSR_DATA(IP5_27_24, VI1_FIELD),
1052 PINMUX_IPSR_DATA(IP5_27_24, VI3_FIELD),
1053 PINMUX_IPSR_DATA(IP5_27_24, AUDIO_CLKOUT),
1054 PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX2_D, SEL_SCIF2_3),
1055 PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
1056 PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
1057 PINMUX_IPSR_DATA(IP5_28, AUDIO_CLKA),
1058 PINMUX_IPSR_DATA(IP5_28, CAN_TXCLK),
1059 PINMUX_IPSR_DATA(IP5_30_29, AUDIO_CLKB),
1060 PINMUX_IPSR_DATA(IP5_30_29, USB_OVC2),
1061 PINMUX_IPSR_DATA(IP5_30_29, CAN_DEBUGOUT0),
1062 PINMUX_IPSR_DATA(IP5_30_29, MOUT0),
1063
1064 PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK0129),
1065 PINMUX_IPSR_DATA(IP6_1_0, CAN_DEBUGOUT1),
1066 PINMUX_IPSR_DATA(IP6_1_0, MOUT1),
1067 PINMUX_IPSR_DATA(IP6_3_2, SSI_WS0129),
1068 PINMUX_IPSR_DATA(IP6_3_2, CAN_DEBUGOUT2),
1069 PINMUX_IPSR_DATA(IP6_3_2, MOUT2),
1070 PINMUX_IPSR_DATA(IP6_5_4, SSI_SDATA0),
1071 PINMUX_IPSR_DATA(IP6_5_4, CAN_DEBUGOUT3),
1072 PINMUX_IPSR_DATA(IP6_5_4, MOUT5),
1073 PINMUX_IPSR_DATA(IP6_7_6, SSI_SDATA1),
1074 PINMUX_IPSR_DATA(IP6_7_6, CAN_DEBUGOUT4),
1075 PINMUX_IPSR_DATA(IP6_7_6, MOUT6),
1076 PINMUX_IPSR_DATA(IP6_8, SSI_SDATA2),
1077 PINMUX_IPSR_DATA(IP6_8, CAN_DEBUGOUT5),
1078 PINMUX_IPSR_DATA(IP6_11_9, SSI_SCK34),
1079 PINMUX_IPSR_DATA(IP6_11_9, CAN_DEBUGOUT6),
1080 PINMUX_IPSR_DATA(IP6_11_9, CAN0_TX_B),
1081 PINMUX_IPSR_MODSEL_DATA(IP6_11_9, IERX, SEL_IE_0),
1082 PINMUX_IPSR_MODSEL_DATA(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
1083 PINMUX_IPSR_DATA(IP6_14_12, SSI_WS34),
1084 PINMUX_IPSR_DATA(IP6_14_12, CAN_DEBUGOUT7),
1085 PINMUX_IPSR_MODSEL_DATA(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
1086 PINMUX_IPSR_DATA(IP6_14_12, IETX),
1087 PINMUX_IPSR_MODSEL_DATA(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
1088 PINMUX_IPSR_DATA(IP6_17_15, SSI_SDATA3),
1089 PINMUX_IPSR_DATA(IP6_17_15, PWM0_C),
1090 PINMUX_IPSR_DATA(IP6_17_15, CAN_DEBUGOUT8),
1091 PINMUX_IPSR_MODSEL_DATA(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
1092 PINMUX_IPSR_MODSEL_DATA(IP6_17_15, IECLK, SEL_IE_0),
1093 PINMUX_IPSR_MODSEL_DATA(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
1094 PINMUX_IPSR_MODSEL_DATA(IP6_17_15, TCLK0_B, SEL_TMU0_1),
1095 PINMUX_IPSR_DATA(IP6_19_18, SSI_SDATA4),
1096 PINMUX_IPSR_DATA(IP6_19_18, CAN_DEBUGOUT9),
1097 PINMUX_IPSR_MODSEL_DATA(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
1098 PINMUX_IPSR_DATA(IP6_22_20, SSI_SCK5),
1099 PINMUX_IPSR_DATA(IP6_22_20, ADICLK),
1100 PINMUX_IPSR_DATA(IP6_22_20, CAN_DEBUGOUT10),
1101 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK3, SEL_SCIF3_0),
1102 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TCLK0_D, SEL_TMU0_3),
1103 PINMUX_IPSR_DATA(IP6_24_23, SSI_WS5),
1104 PINMUX_IPSR_MODSEL_DATA(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
1105 PINMUX_IPSR_DATA(IP6_24_23, CAN_DEBUGOUT11),
1106 PINMUX_IPSR_DATA(IP6_24_23, TX3_IRDA_TX),
1107 PINMUX_IPSR_DATA(IP6_26_25, SSI_SDATA5),
1108 PINMUX_IPSR_MODSEL_DATA(IP6_26_25, ADIDATA, SEL_ADI_0),
1109 PINMUX_IPSR_DATA(IP6_26_25, CAN_DEBUGOUT12),
1110 PINMUX_IPSR_MODSEL_DATA(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
1111 PINMUX_IPSR_DATA(IP6_30_29, SSI_SCK6),
1112 PINMUX_IPSR_DATA(IP6_30_29, ADICHS0),
1113 PINMUX_IPSR_DATA(IP6_30_29, CAN0_TX),
1114 PINMUX_IPSR_MODSEL_DATA(IP6_30_29, IERX_B, SEL_IE_1),
1115
1116 PINMUX_IPSR_DATA(IP7_1_0, SSI_WS6),
1117 PINMUX_IPSR_DATA(IP7_1_0, ADICHS1),
1118 PINMUX_IPSR_MODSEL_DATA(IP7_1_0, CAN0_RX, SEL_CAN0_0),
1119 PINMUX_IPSR_DATA(IP7_1_0, IETX_B),
1120 PINMUX_IPSR_DATA(IP7_3_2, SSI_SDATA6),
1121 PINMUX_IPSR_DATA(IP7_3_2, ADICHS2),
1122 PINMUX_IPSR_MODSEL_DATA(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
1123 PINMUX_IPSR_MODSEL_DATA(IP7_3_2, IECLK_B, SEL_IE_1),
1124 PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
1125 PINMUX_IPSR_DATA(IP7_6_4, CAN_DEBUGOUT13),
1126 PINMUX_IPSR_MODSEL_DATA(IP7_6_4, IRQ0_B, SEL_INT0_1),
1127 PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
1128 PINMUX_IPSR_MODSEL_DATA(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
1129 PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS78, SEL_SSI7_0),
1130 PINMUX_IPSR_DATA(IP7_9_7, CAN_DEBUGOUT14),
1131 PINMUX_IPSR_MODSEL_DATA(IP7_9_7, IRQ1_B, SEL_INT1_1),
1132 PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
1133 PINMUX_IPSR_MODSEL_DATA(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
1134 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
1135 PINMUX_IPSR_DATA(IP7_12_10, CAN_DEBUGOUT15),
1136 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, IRQ2_B, SEL_INT2_1),
1137 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TCLK1_C, SEL_TMU1_2),
1138 PINMUX_IPSR_DATA(IP7_12_10, HSPI_TX1_C),
1139 PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
1140 PINMUX_IPSR_DATA(IP7_14_13, VSP),
1141 PINMUX_IPSR_MODSEL_DATA(IP7_14_13, IRQ3_B, SEL_INT3_1),
1142 PINMUX_IPSR_MODSEL_DATA(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
1143 PINMUX_IPSR_DATA(IP7_16_15, SD0_CLK),
1144 PINMUX_IPSR_DATA(IP7_16_15, ATACS01),
1145 PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SCK1_B, SEL_SCIF1_1),
1146 PINMUX_IPSR_DATA(IP7_18_17, SD0_CMD),
1147 PINMUX_IPSR_DATA(IP7_18_17, ATACS11),
1148 PINMUX_IPSR_DATA(IP7_18_17, TX1_B),
1149 PINMUX_IPSR_DATA(IP7_18_17, CC5_TDO),
1150 PINMUX_IPSR_DATA(IP7_20_19, SD0_DAT0),
1151 PINMUX_IPSR_DATA(IP7_20_19, ATADIR1),
1152 PINMUX_IPSR_MODSEL_DATA(IP7_20_19, RX1_B, SEL_SCIF1_1),
1153 PINMUX_IPSR_DATA(IP7_20_19, CC5_TRST),
1154 PINMUX_IPSR_DATA(IP7_22_21, SD0_DAT1),
1155 PINMUX_IPSR_DATA(IP7_22_21, ATAG1),
1156 PINMUX_IPSR_MODSEL_DATA(IP7_22_21, SCK2_B, SEL_SCIF2_1),
1157 PINMUX_IPSR_DATA(IP7_22_21, CC5_TMS),
1158 PINMUX_IPSR_DATA(IP7_24_23, SD0_DAT2),
1159 PINMUX_IPSR_DATA(IP7_24_23, ATARD1),
1160 PINMUX_IPSR_DATA(IP7_24_23, TX2_B),
1161 PINMUX_IPSR_DATA(IP7_24_23, CC5_TCK),
1162 PINMUX_IPSR_DATA(IP7_26_25, SD0_DAT3),
1163 PINMUX_IPSR_DATA(IP7_26_25, ATAWR1),
1164 PINMUX_IPSR_MODSEL_DATA(IP7_26_25, RX2_B, SEL_SCIF2_1),
1165 PINMUX_IPSR_DATA(IP7_26_25, CC5_TDI),
1166 PINMUX_IPSR_DATA(IP7_28_27, SD0_CD),
1167 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, DREQ2, SEL_EXBUS2_0),
1168 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
1169 PINMUX_IPSR_DATA(IP7_30_29, SD0_WP),
1170 PINMUX_IPSR_DATA(IP7_30_29, DACK2),
1171 PINMUX_IPSR_MODSEL_DATA(IP7_30_29, CTS1_B, SEL_SCIF1_1),
1172
1173 PINMUX_IPSR_DATA(IP8_3_0, HSPI_CLK0),
1174 PINMUX_IPSR_MODSEL_DATA(IP8_3_0, CTS0, SEL_SCIF0_0),
1175 PINMUX_IPSR_DATA(IP8_3_0, USB_OVC0),
1176 PINMUX_IPSR_DATA(IP8_3_0, AD_CLK),
1177 PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE4),
1178 PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE12),
1179 PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE20),
1180 PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE28),
1181 PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE36),
1182 PINMUX_IPSR_DATA(IP8_7_4, HSPI_CS0),
1183 PINMUX_IPSR_MODSEL_DATA(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
1184 PINMUX_IPSR_DATA(IP8_7_4, USB_OVC1),
1185 PINMUX_IPSR_DATA(IP8_7_4, AD_DI),
1186 PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE5),
1187 PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE13),
1188 PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE21),
1189 PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE29),
1190 PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE37),
1191 PINMUX_IPSR_DATA(IP8_11_8, HSPI_TX0),
1192 PINMUX_IPSR_DATA(IP8_11_8, TX0),
1193 PINMUX_IPSR_DATA(IP8_11_8, CAN_DEBUG_HW_TRIGGER),
1194 PINMUX_IPSR_DATA(IP8_11_8, AD_DO),
1195 PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE6),
1196 PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE14),
1197 PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE22),
1198 PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE30),
1199 PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE38),
1200 PINMUX_IPSR_DATA(IP8_15_12, HSPI_RX0),
1201 PINMUX_IPSR_MODSEL_DATA(IP8_15_12, RX0, SEL_SCIF0_0),
1202 PINMUX_IPSR_DATA(IP8_15_12, CAN_STEP0),
1203 PINMUX_IPSR_DATA(IP8_15_12, AD_NCS),
1204 PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE7),
1205 PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE15),
1206 PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE23),
1207 PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE31),
1208 PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE39),
1209 PINMUX_IPSR_DATA(IP8_17_16, FMCLK),
1210 PINMUX_IPSR_DATA(IP8_17_16, RDS_CLK),
1211 PINMUX_IPSR_DATA(IP8_17_16, PCMOE),
1212 PINMUX_IPSR_DATA(IP8_18, BPFCLK),
1213 PINMUX_IPSR_DATA(IP8_18, PCMWE),
1214 PINMUX_IPSR_DATA(IP8_19, FMIN),
1215 PINMUX_IPSR_DATA(IP8_19, RDS_DATA),
1216 PINMUX_IPSR_DATA(IP8_20, VI0_CLK),
1217 PINMUX_IPSR_DATA(IP8_20, MMC1_CLK),
1218 PINMUX_IPSR_DATA(IP8_22_21, VI0_CLKENB),
1219 PINMUX_IPSR_DATA(IP8_22_21, TX1_C),
1220 PINMUX_IPSR_DATA(IP8_22_21, HTX1_B),
1221 PINMUX_IPSR_DATA(IP8_22_21, MT1_SYNC),
1222 PINMUX_IPSR_DATA(IP8_24_23, VI0_FIELD),
1223 PINMUX_IPSR_MODSEL_DATA(IP8_24_23, RX1_C, SEL_SCIF1_2),
1224 PINMUX_IPSR_MODSEL_DATA(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
1225 PINMUX_IPSR_DATA(IP8_27_25, VI0_HSYNC),
1226 PINMUX_IPSR_MODSEL_DATA(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
1227 PINMUX_IPSR_MODSEL_DATA(IP8_27_25, CTS1_C, SEL_SCIF1_2),
1228 PINMUX_IPSR_DATA(IP8_27_25, TX4_D),
1229 PINMUX_IPSR_DATA(IP8_27_25, MMC1_CMD),
1230 PINMUX_IPSR_MODSEL_DATA(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
1231 PINMUX_IPSR_DATA(IP8_30_28, VI0_VSYNC),
1232 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
1233 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
1234 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RX4_D, SEL_SCIF4_3),
1235 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2),
1236
1237 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
1238 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
1239 PINMUX_IPSR_DATA(IP9_1_0, MT1_VCXO),
1240 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
1241 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
1242 PINMUX_IPSR_DATA(IP9_3_2, MT1_PWM),
1243 PINMUX_IPSR_DATA(IP9_4, VI0_DATA2_VI0_B2),
1244 PINMUX_IPSR_DATA(IP9_4, MMC1_D0),
1245 PINMUX_IPSR_DATA(IP9_5, VI0_DATA3_VI0_B3),
1246 PINMUX_IPSR_DATA(IP9_5, MMC1_D1),
1247 PINMUX_IPSR_DATA(IP9_6, VI0_DATA4_VI0_B4),
1248 PINMUX_IPSR_DATA(IP9_6, MMC1_D2),
1249 PINMUX_IPSR_DATA(IP9_7, VI0_DATA5_VI0_B5),
1250 PINMUX_IPSR_DATA(IP9_7, MMC1_D3),
1251 PINMUX_IPSR_DATA(IP9_9_8, VI0_DATA6_VI0_B6),
1252 PINMUX_IPSR_DATA(IP9_9_8, MMC1_D4),
1253 PINMUX_IPSR_DATA(IP9_9_8, ARM_TRACEDATA_0),
1254 PINMUX_IPSR_DATA(IP9_11_10, VI0_DATA7_VI0_B7),
1255 PINMUX_IPSR_DATA(IP9_11_10, MMC1_D5),
1256 PINMUX_IPSR_DATA(IP9_11_10, ARM_TRACEDATA_1),
1257 PINMUX_IPSR_DATA(IP9_13_12, VI0_G0),
1258 PINMUX_IPSR_MODSEL_DATA(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
1259 PINMUX_IPSR_MODSEL_DATA(IP9_13_12, IRQ0, SEL_INT0_0),
1260 PINMUX_IPSR_DATA(IP9_13_12, ARM_TRACEDATA_2),
1261 PINMUX_IPSR_DATA(IP9_15_14, VI0_G1),
1262 PINMUX_IPSR_MODSEL_DATA(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
1263 PINMUX_IPSR_MODSEL_DATA(IP9_15_14, IRQ1, SEL_INT1_0),
1264 PINMUX_IPSR_DATA(IP9_15_14, ARM_TRACEDATA_3),
1265 PINMUX_IPSR_DATA(IP9_18_16, VI0_G2),
1266 PINMUX_IPSR_DATA(IP9_18_16, ETH_TXD1),
1267 PINMUX_IPSR_DATA(IP9_18_16, MMC1_D6),
1268 PINMUX_IPSR_DATA(IP9_18_16, ARM_TRACEDATA_4),
1269 PINMUX_IPSR_DATA(IP9_18_16, TS_SPSYNC0),
1270 PINMUX_IPSR_DATA(IP9_21_19, VI0_G3),
1271 PINMUX_IPSR_DATA(IP9_21_19, ETH_CRS_DV),
1272 PINMUX_IPSR_DATA(IP9_21_19, MMC1_D7),
1273 PINMUX_IPSR_DATA(IP9_21_19, ARM_TRACEDATA_5),
1274 PINMUX_IPSR_DATA(IP9_21_19, TS_SDAT0),
1275 PINMUX_IPSR_DATA(IP9_23_22, VI0_G4),
1276 PINMUX_IPSR_DATA(IP9_23_22, ETH_TX_EN),
1277 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
1278 PINMUX_IPSR_DATA(IP9_23_22, ARM_TRACEDATA_6),
1279 PINMUX_IPSR_DATA(IP9_25_24, VI0_G5),
1280 PINMUX_IPSR_DATA(IP9_25_24, ETH_RX_ER),
1281 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
1282 PINMUX_IPSR_DATA(IP9_25_24, ARM_TRACEDATA_7),
1283 PINMUX_IPSR_DATA(IP9_27_26, VI0_G6),
1284 PINMUX_IPSR_DATA(IP9_27_26, ETH_RXD0),
1285 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
1286 PINMUX_IPSR_DATA(IP9_27_26, ARM_TRACEDATA_8),
1287 PINMUX_IPSR_DATA(IP9_29_28, VI0_G7),
1288 PINMUX_IPSR_DATA(IP9_29_28, ETH_RXD1),
1289 PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
1290 PINMUX_IPSR_DATA(IP9_29_28, ARM_TRACEDATA_9),
1291
1292 PINMUX_IPSR_DATA(IP10_2_0, VI0_R0),
1293 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
1294 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCK1_C, SEL_SCIF1_2),
1295 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
1296 PINMUX_IPSR_DATA(IP10_2_0, ARM_TRACEDATA_10),
1297 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
1298 PINMUX_IPSR_DATA(IP10_5_3, VI0_R1),
1299 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
1300 PINMUX_IPSR_DATA(IP10_5_3, DACK1_B),
1301 PINMUX_IPSR_DATA(IP10_5_3, ARM_TRACEDATA_11),
1302 PINMUX_IPSR_DATA(IP10_5_3, DACK0_C),
1303 PINMUX_IPSR_DATA(IP10_5_3, DRACK0_C),
1304 PINMUX_IPSR_DATA(IP10_8_6, VI0_R2),
1305 PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
1306 PINMUX_IPSR_DATA(IP10_8_6, SD2_CLK_B),
1307 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IRQ2, SEL_INT2_0),
1308 PINMUX_IPSR_DATA(IP10_8_6, ARM_TRACEDATA_12),
1309 PINMUX_IPSR_DATA(IP10_11_9, VI0_R3),
1310 PINMUX_IPSR_DATA(IP10_11_9, ETH_MAGIC),
1311 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
1312 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IRQ3, SEL_INT3_0),
1313 PINMUX_IPSR_DATA(IP10_11_9, ARM_TRACEDATA_13),
1314 PINMUX_IPSR_DATA(IP10_14_12, VI0_R4),
1315 PINMUX_IPSR_DATA(IP10_14_12, ETH_REFCLK),
1316 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SD2_CD_B, SEL_SD2_1),
1317 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
1318 PINMUX_IPSR_DATA(IP10_14_12, ARM_TRACEDATA_14),
1319 PINMUX_IPSR_DATA(IP10_14_12, MT1_CLK),
1320 PINMUX_IPSR_DATA(IP10_14_12, TS_SCK0),
1321 PINMUX_IPSR_DATA(IP10_17_15, VI0_R5),
1322 PINMUX_IPSR_DATA(IP10_17_15, ETH_TXD0),
1323 PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SD2_WP_B, SEL_SD2_1),
1324 PINMUX_IPSR_MODSEL_DATA(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
1325 PINMUX_IPSR_DATA(IP10_17_15, ARM_TRACEDATA_15),
1326 PINMUX_IPSR_DATA(IP10_17_15, MT1_D),
1327 PINMUX_IPSR_DATA(IP10_17_15, TS_SDEN0),
1328 PINMUX_IPSR_DATA(IP10_20_18, VI0_R6),
1329 PINMUX_IPSR_DATA(IP10_20_18, ETH_MDC),
1330 PINMUX_IPSR_MODSEL_DATA(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
1331 PINMUX_IPSR_DATA(IP10_20_18, HSPI_TX1_B),
1332 PINMUX_IPSR_DATA(IP10_20_18, TRACECLK),
1333 PINMUX_IPSR_DATA(IP10_20_18, MT1_BEN),
1334 PINMUX_IPSR_MODSEL_DATA(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
1335 PINMUX_IPSR_DATA(IP10_23_21, VI0_R7),
1336 PINMUX_IPSR_DATA(IP10_23_21, ETH_MDIO),
1337 PINMUX_IPSR_DATA(IP10_23_21, DACK2_C),
1338 PINMUX_IPSR_MODSEL_DATA(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
1339 PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
1340 PINMUX_IPSR_DATA(IP10_23_21, TRACECTL),
1341 PINMUX_IPSR_DATA(IP10_23_21, MT1_PEN),
1342 PINMUX_IPSR_DATA(IP10_25_24, VI1_CLK),
1343 PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SIM_D, SEL_SIM_0),
1344 PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SDA3, SEL_I2C3_0),
1345 PINMUX_IPSR_DATA(IP10_28_26, VI1_HSYNC),
1346 PINMUX_IPSR_DATA(IP10_28_26, VI3_CLK),
1347 PINMUX_IPSR_DATA(IP10_28_26, SSI_SCK4),
1348 PINMUX_IPSR_MODSEL_DATA(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
1349 PINMUX_IPSR_MODSEL_DATA(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
1350 PINMUX_IPSR_DATA(IP10_31_29, VI1_VSYNC),
1351 PINMUX_IPSR_DATA(IP10_31_29, AUDIO_CLKOUT_C),
1352 PINMUX_IPSR_DATA(IP10_31_29, SSI_WS4),
1353 PINMUX_IPSR_DATA(IP10_31_29, SIM_CLK),
1354 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
1355 PINMUX_IPSR_DATA(IP10_31_29, SPV_TRST),
1356 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL3, SEL_I2C3_0),
1357
1358 PINMUX_IPSR_DATA(IP11_2_0, VI1_DATA0_VI1_B0),
1359 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SD2_DAT0, SEL_SD2_0),
1360 PINMUX_IPSR_DATA(IP11_2_0, SIM_RST),
1361 PINMUX_IPSR_DATA(IP11_2_0, SPV_TCK),
1362 PINMUX_IPSR_DATA(IP11_2_0, ADICLK_B),
1363 PINMUX_IPSR_DATA(IP11_5_3, VI1_DATA1_VI1_B1),
1364 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SD2_DAT1, SEL_SD2_0),
1365 PINMUX_IPSR_DATA(IP11_5_3, MT0_CLK),
1366 PINMUX_IPSR_DATA(IP11_5_3, SPV_TMS),
1367 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
1368 PINMUX_IPSR_DATA(IP11_8_6, VI1_DATA2_VI1_B2),
1369 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SD2_DAT2, SEL_SD2_0),
1370 PINMUX_IPSR_DATA(IP11_8_6, MT0_D),
1371 PINMUX_IPSR_DATA(IP11_8_6, SPVTDI),
1372 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, ADIDATA_B, SEL_ADI_1),
1373 PINMUX_IPSR_DATA(IP11_11_9, VI1_DATA3_VI1_B3),
1374 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SD2_DAT3, SEL_SD2_0),
1375 PINMUX_IPSR_DATA(IP11_11_9, MT0_BEN),
1376 PINMUX_IPSR_DATA(IP11_11_9, SPV_TDO),
1377 PINMUX_IPSR_DATA(IP11_11_9, ADICHS0_B),
1378 PINMUX_IPSR_DATA(IP11_14_12, VI1_DATA4_VI1_B4),
1379 PINMUX_IPSR_DATA(IP11_14_12, SD2_CLK),
1380 PINMUX_IPSR_DATA(IP11_14_12, MT0_PEN),
1381 PINMUX_IPSR_DATA(IP11_14_12, SPA_TRST),
1382 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
1383 PINMUX_IPSR_DATA(IP11_14_12, ADICHS1_B),
1384 PINMUX_IPSR_DATA(IP11_17_15, VI1_DATA5_VI1_B5),
1385 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SD2_CMD, SEL_SD2_0),
1386 PINMUX_IPSR_DATA(IP11_17_15, MT0_SYNC),
1387 PINMUX_IPSR_DATA(IP11_17_15, SPA_TCK),
1388 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
1389 PINMUX_IPSR_DATA(IP11_17_15, ADICHS2_B),
1390 PINMUX_IPSR_DATA(IP11_20_18, VI1_DATA6_VI1_B6),
1391 PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SD2_CD, SEL_SD2_0),
1392 PINMUX_IPSR_DATA(IP11_20_18, MT0_VCXO),
1393 PINMUX_IPSR_DATA(IP11_20_18, SPA_TMS),
1394 PINMUX_IPSR_DATA(IP11_20_18, HSPI_TX1_D),
1395 PINMUX_IPSR_DATA(IP11_23_21, VI1_DATA7_VI1_B7),
1396 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SD2_WP, SEL_SD2_0),
1397 PINMUX_IPSR_DATA(IP11_23_21, MT0_PWM),
1398 PINMUX_IPSR_DATA(IP11_23_21, SPA_TDI),
1399 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
1400 PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
1401 PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
1402 PINMUX_IPSR_DATA(IP11_26_24, DU1_DOTCLKOUT1),
1403 PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
1404 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
1405 PINMUX_IPSR_DATA(IP11_26_24, TX2),
1406 PINMUX_IPSR_DATA(IP11_26_24, SPA_TDO),
1407 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
1408 PINMUX_IPSR_DATA(IP11_29_27, VI1_G1),
1409 PINMUX_IPSR_DATA(IP11_29_27, VI3_DATA1),
1410 PINMUX_IPSR_DATA(IP11_29_27, SSI_SCK1),
1411 PINMUX_IPSR_DATA(IP11_29_27, TS_SDEN1),
1412 PINMUX_IPSR_DATA(IP11_29_27, DACK2_B),
1413 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RX2, SEL_SCIF2_0),
1414 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
1415
1416 PINMUX_IPSR_DATA(IP12_2_0, VI1_G2),
1417 PINMUX_IPSR_DATA(IP12_2_0, VI3_DATA2),
1418 PINMUX_IPSR_DATA(IP12_2_0, SSI_WS1),
1419 PINMUX_IPSR_DATA(IP12_2_0, TS_SPSYNC1),
1420 PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCK2, SEL_SCIF2_0),
1421 PINMUX_IPSR_MODSEL_DATA(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
1422 PINMUX_IPSR_DATA(IP12_5_3, VI1_G3),
1423 PINMUX_IPSR_DATA(IP12_5_3, VI3_DATA3),
1424 PINMUX_IPSR_DATA(IP12_5_3, SSI_SCK2),
1425 PINMUX_IPSR_DATA(IP12_5_3, TS_SDAT1),
1426 PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCL1_C, SEL_I2C1_2),
1427 PINMUX_IPSR_DATA(IP12_5_3, HTX0_B),
1428 PINMUX_IPSR_DATA(IP12_8_6, VI1_G4),
1429 PINMUX_IPSR_DATA(IP12_8_6, VI3_DATA4),
1430 PINMUX_IPSR_DATA(IP12_8_6, SSI_WS2),
1431 PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SDA1_C, SEL_I2C1_2),
1432 PINMUX_IPSR_DATA(IP12_8_6, SIM_RST_B),
1433 PINMUX_IPSR_MODSEL_DATA(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
1434 PINMUX_IPSR_DATA(IP12_11_9, VI1_G5),
1435 PINMUX_IPSR_DATA(IP12_11_9, VI3_DATA5),
1436 PINMUX_IPSR_MODSEL_DATA(IP12_11_9, GPS_CLK, SEL_GPS_0),
1437 PINMUX_IPSR_DATA(IP12_11_9, FSE),
1438 PINMUX_IPSR_DATA(IP12_11_9, TX4_B),
1439 PINMUX_IPSR_MODSEL_DATA(IP12_11_9, SIM_D_B, SEL_SIM_1),
1440 PINMUX_IPSR_DATA(IP12_14_12, VI1_G6),
1441 PINMUX_IPSR_DATA(IP12_14_12, VI3_DATA6),
1442 PINMUX_IPSR_MODSEL_DATA(IP12_14_12, GPS_SIGN, SEL_GPS_0),
1443 PINMUX_IPSR_DATA(IP12_14_12, FRB),
1444 PINMUX_IPSR_MODSEL_DATA(IP12_14_12, RX4_B, SEL_SCIF4_1),
1445 PINMUX_IPSR_DATA(IP12_14_12, SIM_CLK_B),
1446 PINMUX_IPSR_DATA(IP12_17_15, VI1_G7),
1447 PINMUX_IPSR_DATA(IP12_17_15, VI3_DATA7),
1448 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, GPS_MAG, SEL_GPS_0),
1449 PINMUX_IPSR_DATA(IP12_17_15, FCE),
1450 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
1451};
1452
1453static struct pinmux_gpio pinmux_gpios[] = {
1454 PINMUX_GPIO_GP_ALL(),
1455 GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18),
1456 GPIO_FN(A19),
1457
1458 /* IPSR0 */
1459 GPIO_FN(PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
1460 GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2),
1461 GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
1462 GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3),
1463 GPIO_FN(MMC0_D3), GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D),
1464 GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), GPIO_FN(SCK5_D),
1465 GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), GPIO_FN(RX5_D),
1466 GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE),
1467 GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24), GPIO_FN(SD1_CD),
1468 GPIO_FN(MMC0_D4), GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2),
1469 GPIO_FN(SSI_WS78_B), GPIO_FN(A25), GPIO_FN(SD1_WP), GPIO_FN(MMC0_D5),
1470 GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), GPIO_FN(TX5_B),
1471 GPIO_FN(SSI_SDATA7_B), GPIO_FN(CTS0_B), GPIO_FN(CLKOUT),
1472 GPIO_FN(TX3C_IRDA_TX_C), GPIO_FN(PWM0_B), GPIO_FN(CS0),
1473 GPIO_FN(HSPI_CS2_B), GPIO_FN(CS1_A26), GPIO_FN(HSPI_TX2),
1474 GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0),
1475 GPIO_FN(VI1_R7), GPIO_FN(HRTS1), GPIO_FN(RX4_C),
1476
1477 /* IPSR1 */
1478 GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C), GPIO_FN(MMC0_D6),
1479 GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(MMC0_D7), GPIO_FN(FD7),
1480 GPIO_FN(EX_CS2), GPIO_FN(SD1_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(FALE),
1481 GPIO_FN(ATACS00), GPIO_FN(EX_CS3), GPIO_FN(SD1_CMD), GPIO_FN(MMC0_CMD),
1482 GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), GPIO_FN(RX5_B),
1483 GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), GPIO_FN(RTS0_B_TANS_B),
1484 GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4), GPIO_FN(SD1_DAT0),
1485 GPIO_FN(MMC0_D0), GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5),
1486 GPIO_FN(SCK5_B), GPIO_FN(HTX1), GPIO_FN(TX2_E), GPIO_FN(TX0_B),
1487 GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5), GPIO_FN(SD1_DAT1),
1488 GPIO_FN(MMC0_D1), GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6),
1489 GPIO_FN(HRX1), GPIO_FN(RX2_E), GPIO_FN(RX0_B), GPIO_FN(SSI_WS9),
1490 GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(SCK4), GPIO_FN(MLB_SIG),
1491 GPIO_FN(PWM3), GPIO_FN(TX4), GPIO_FN(MLB_DAT), GPIO_FN(PWM4),
1492 GPIO_FN(RX4), GPIO_FN(HTX0), GPIO_FN(TX1), GPIO_FN(SDATA),
1493 GPIO_FN(CTS0_C), GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2),
1494 GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26),
1495 GPIO_FN(CC5_STATE34),
1496
1497 /* IPSR2 */
1498 GPIO_FN(HRX0), GPIO_FN(RX1), GPIO_FN(SCKZ), GPIO_FN(RTS0_C_TANS_C),
1499 GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11),
1500 GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35),
1501 GPIO_FN(HSCK0), GPIO_FN(SCK1), GPIO_FN(MTS), GPIO_FN(PWM5),
1502 GPIO_FN(SCK0_C), GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO),
1503 GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16),
1504 GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0),
1505 GPIO_FN(CTS1), GPIO_FN(STM), GPIO_FN(PWM0_D), GPIO_FN(RX0_C),
1506 GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B),
1507 GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), GPIO_FN(RTS1_TANS),
1508 GPIO_FN(MDATA), GPIO_FN(TX0_C), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1),
1509 GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25),
1510 GPIO_FN(CC5_STATE33), GPIO_FN(DU0_DR0), GPIO_FN(LCDOUT0),
1511 GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0),
1512 GPIO_FN(TX5_C), GPIO_FN(DU0_DR1), GPIO_FN(LCDOUT1), GPIO_FN(DACK0),
1513 GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), GPIO_FN(RX5_C),
1514 GPIO_FN(DU0_DR2), GPIO_FN(LCDOUT2), GPIO_FN(DU0_DR3), GPIO_FN(LCDOUT3),
1515 GPIO_FN(DU0_DR4), GPIO_FN(LCDOUT4), GPIO_FN(DU0_DR5), GPIO_FN(LCDOUT5),
1516 GPIO_FN(DU0_DR6), GPIO_FN(LCDOUT6), GPIO_FN(DU0_DR7), GPIO_FN(LCDOUT7),
1517 GPIO_FN(DU0_DG0), GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2),
1518 GPIO_FN(AUDATA2),
1519
1520 /* IPSR3 */
1521 GPIO_FN(DU0_DG1), GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2),
1522 GPIO_FN(AUDATA3), GPIO_FN(DU0_DG2), GPIO_FN(LCDOUT10),
1523 GPIO_FN(DU0_DG3), GPIO_FN(LCDOUT11), GPIO_FN(DU0_DG4),
1524 GPIO_FN(LCDOUT12), GPIO_FN(DU0_DG5), GPIO_FN(LCDOUT13),
1525 GPIO_FN(DU0_DG6), GPIO_FN(LCDOUT14), GPIO_FN(DU0_DG7),
1526 GPIO_FN(LCDOUT15), GPIO_FN(DU0_DB0), GPIO_FN(LCDOUT16),
1527 GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4),
1528 GPIO_FN(DU0_DB1), GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1),
1529 GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), GPIO_FN(SCK5_C),
1530 GPIO_FN(DU0_DB2), GPIO_FN(LCDOUT18), GPIO_FN(DU0_DB3),
1531 GPIO_FN(LCDOUT19), GPIO_FN(DU0_DB4), GPIO_FN(LCDOUT20),
1532 GPIO_FN(DU0_DB5), GPIO_FN(LCDOUT21), GPIO_FN(DU0_DB6),
1533 GPIO_FN(LCDOUT22), GPIO_FN(DU0_DB7), GPIO_FN(LCDOUT23),
1534 GPIO_FN(DU0_DOTCLKIN), GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D),
1535 GPIO_FN(SCL3_B), GPIO_FN(DU0_DOTCLKOUT0), GPIO_FN(QCLK),
1536 GPIO_FN(DU0_DOTCLKOUT1), GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D),
1537 GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B),
1538 GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(QSTH_QHS),
1539 GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE),
1540 GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), GPIO_FN(QCPV_QDE),
1541 GPIO_FN(CAN1_TX), GPIO_FN(TX2_C), GPIO_FN(SCL2_C), GPIO_FN(REMOCON),
1542
1543 /* IPSR4 */
1544 GPIO_FN(DU0_DISP), GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C),
1545 GPIO_FN(DU0_CDE), GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C),
1546 GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B),
1547 GPIO_FN(DU1_DR0), GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6),
1548 GPIO_FN(SD3_CLK), GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK),
1549 GPIO_FN(PWMFSW0_B), GPIO_FN(DU1_DR1), GPIO_FN(VI2_DATA1_VI2_B1),
1550 GPIO_FN(PWM0), GPIO_FN(SD3_CMD), GPIO_FN(RX3_E_IRDA_RX_E),
1551 GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(DU1_DR2), GPIO_FN(VI2_G0),
1552 GPIO_FN(DU1_DR3), GPIO_FN(VI2_G1), GPIO_FN(DU1_DR4), GPIO_FN(VI2_G2),
1553 GPIO_FN(DU1_DR5), GPIO_FN(VI2_G3), GPIO_FN(DU1_DR6), GPIO_FN(VI2_G4),
1554 GPIO_FN(DU1_DR7), GPIO_FN(VI2_G5), GPIO_FN(DU1_DG0),
1555 GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), GPIO_FN(SD3_DAT2),
1556 GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D), GPIO_FN(DU1_DG1),
1557 GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), GPIO_FN(SD3_DAT3),
1558 GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D), GPIO_FN(DU1_DG2),
1559 GPIO_FN(VI2_G6), GPIO_FN(DU1_DG3), GPIO_FN(VI2_G7), GPIO_FN(DU1_DG4),
1560 GPIO_FN(VI2_R0), GPIO_FN(DU1_DG5), GPIO_FN(VI2_R1), GPIO_FN(DU1_DG6),
1561 GPIO_FN(VI2_R2), GPIO_FN(DU1_DG7), GPIO_FN(VI2_R3), GPIO_FN(DU1_DB0),
1562 GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), GPIO_FN(SD3_DAT0),
1563 GPIO_FN(TX5), GPIO_FN(SCK0_D),
1564
1565 /* IPSR5 */
1566 GPIO_FN(DU1_DB1), GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B),
1567 GPIO_FN(SD3_DAT1), GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D),
1568 GPIO_FN(DU1_DB2), GPIO_FN(VI2_R4), GPIO_FN(DU1_DB3), GPIO_FN(VI2_R5),
1569 GPIO_FN(DU1_DB4), GPIO_FN(VI2_R6), GPIO_FN(DU1_DB5), GPIO_FN(VI2_R7),
1570 GPIO_FN(DU1_DB6), GPIO_FN(SCL2_D), GPIO_FN(DU1_DB7), GPIO_FN(SDA2_D),
1571 GPIO_FN(DU1_DOTCLKIN), GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1),
1572 GPIO_FN(SCL1_D), GPIO_FN(DU1_DOTCLKOUT), GPIO_FN(VI2_FIELD),
1573 GPIO_FN(SDA1_D), GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(VI2_HSYNC),
1574 GPIO_FN(VI3_HSYNC), GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(VI2_VSYNC),
1575 GPIO_FN(VI3_VSYNC), GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE),
1576 GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), GPIO_FN(SD3_CD),
1577 GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
1578 GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN),
1579 GPIO_FN(GPS_SIGN_D), GPIO_FN(DU1_DISP), GPIO_FN(VI2_DATA6_VI2_B6),
1580 GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1),
1581 GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
1582 GPIO_FN(DU1_CDE), GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B),
1583 GPIO_FN(SD3_WP), GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD),
1584 GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D),
1585 GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA),
1586 GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2),
1587 GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0),
1588
1589 /* IPSR6 */
1590 GPIO_FN(SSI_SCK0129), GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(MOUT1),
1591 GPIO_FN(SSI_WS0129), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(MOUT2),
1592 GPIO_FN(SSI_SDATA0), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(MOUT5),
1593 GPIO_FN(SSI_SDATA1), GPIO_FN(CAN_DEBUGOUT4), GPIO_FN(MOUT6),
1594 GPIO_FN(SSI_SDATA2), GPIO_FN(CAN_DEBUGOUT5), GPIO_FN(SSI_SCK34),
1595 GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(CAN0_TX_B), GPIO_FN(IERX),
1596 GPIO_FN(SSI_SCK9_C), GPIO_FN(SSI_WS34), GPIO_FN(CAN_DEBUGOUT7),
1597 GPIO_FN(CAN0_RX_B), GPIO_FN(IETX), GPIO_FN(SSI_WS9_C),
1598 GPIO_FN(SSI_SDATA3), GPIO_FN(PWM0_C), GPIO_FN(CAN_DEBUGOUT8),
1599 GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B),
1600 GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9),
1601 GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK),
1602 GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SCK3), GPIO_FN(TCLK0_D),
1603 GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11),
1604 GPIO_FN(TX3_IRDA_TX), GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA),
1605 GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(RX3_IRDA_RX), GPIO_FN(SSI_SCK6),
1606 GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B),
1607
1608 /* IPSR7 */
1609 GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B),
1610 GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK),
1611 GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13),
1612 GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B), GPIO_FN(HSPI_CLK1_C),
1613 GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), GPIO_FN(IRQ1_B),
1614 GPIO_FN(SSI_WS9_B), GPIO_FN(HSPI_CS1_C), GPIO_FN(SSI_SDATA7),
1615 GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C),
1616 GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
1617 GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C), GPIO_FN(SD0_CLK),
1618 GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(SD0_CMD), GPIO_FN(ATACS11),
1619 GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(SD0_DAT0), GPIO_FN(ATADIR1),
1620 GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(SD0_DAT1), GPIO_FN(ATAG1),
1621 GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(SD0_DAT2), GPIO_FN(ATARD1),
1622 GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(SD0_DAT3), GPIO_FN(ATAWR1),
1623 GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(SD0_CD), GPIO_FN(DREQ2),
1624 GPIO_FN(RTS1_B_TANS_B), GPIO_FN(SD0_WP), GPIO_FN(DACK2),
1625 GPIO_FN(CTS1_B),
1626
1627 /* IPSR8 */
1628 GPIO_FN(HSPI_CLK0), GPIO_FN(CTS0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK),
1629 GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20),
1630 GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), GPIO_FN(HSPI_CS0),
1631 GPIO_FN(RTS0_TANS), GPIO_FN(USB_OVC1), GPIO_FN(AD_DI),
1632 GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21),
1633 GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(HSPI_TX0),
1634 GPIO_FN(TX0), GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO),
1635 GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22),
1636 GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), GPIO_FN(HSPI_RX0),
1637 GPIO_FN(RX0), GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7),
1638 GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31),
1639 GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE),
1640 GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA),
1641 GPIO_FN(VI0_CLK), GPIO_FN(MMC1_CLK), GPIO_FN(VI0_CLKENB),
1642 GPIO_FN(TX1_C), GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC),
1643 GPIO_FN(VI0_FIELD), GPIO_FN(RX1_C), GPIO_FN(HRX1_B),
1644 GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), GPIO_FN(CTS1_C),
1645 GPIO_FN(TX4_D), GPIO_FN(MMC1_CMD), GPIO_FN(HSCK1_B),
1646 GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B),
1647 GPIO_FN(RTS1_C_TANS_C), GPIO_FN(RX4_D), GPIO_FN(PWMFSW0_C),
1648
1649 /* IPSR9 */
1650 GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO),
1651 GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM),
1652 GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(MMC1_D0), GPIO_FN(VI0_DATA3_VI0_B3),
1653 GPIO_FN(MMC1_D1), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(MMC1_D2),
1654 GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(MMC1_D3), GPIO_FN(VI0_DATA6_VI0_B6),
1655 GPIO_FN(MMC1_D4), GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7),
1656 GPIO_FN(MMC1_D5), GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0),
1657 GPIO_FN(SSI_SCK78_C), GPIO_FN(IRQ0), GPIO_FN(ARM_TRACEDATA_2),
1658 GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), GPIO_FN(IRQ1),
1659 GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1),
1660 GPIO_FN(MMC1_D6), GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0),
1661 GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV), GPIO_FN(MMC1_D7),
1662 GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4),
1663 GPIO_FN(ETH_TX_EN), GPIO_FN(SD2_DAT0_B), GPIO_FN(ARM_TRACEDATA_6),
1664 GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER), GPIO_FN(SD2_DAT1_B),
1665 GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0),
1666 GPIO_FN(SD2_DAT2_B), GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7),
1667 GPIO_FN(ETH_RXD1), GPIO_FN(SD2_DAT3_B), GPIO_FN(ARM_TRACEDATA_9),
1668
1669 /* IPSR10 */
1670 GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SCK1_C),
1671 GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C),
1672 GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B),
1673 GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C),
1674 GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(SD2_CLK_B), GPIO_FN(IRQ2),
1675 GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC),
1676 GPIO_FN(SD2_CMD_B), GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13),
1677 GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), GPIO_FN(SD2_CD_B),
1678 GPIO_FN(HSPI_CLK1_B), GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK),
1679 GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0),
1680 GPIO_FN(SD2_WP_B), GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15),
1681 GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC),
1682 GPIO_FN(DREQ2_C), GPIO_FN(HSPI_TX1_B), GPIO_FN(TRACECLK),
1683 GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7),
1684 GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C), GPIO_FN(HSPI_RX1_B),
1685 GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN),
1686 GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC),
1687 GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C),
1688 GPIO_FN(PWMFSW0_E), GPIO_FN(VI1_VSYNC), GPIO_FN(AUDIO_CLKOUT_C),
1689 GPIO_FN(SSI_WS4), GPIO_FN(SIM_CLK), GPIO_FN(GPS_MAG_C),
1690 GPIO_FN(SPV_TRST), GPIO_FN(SCL3),
1691
1692 /* IPSR11 */
1693 GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SD2_DAT0), GPIO_FN(SIM_RST),
1694 GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1),
1695 GPIO_FN(SD2_DAT1), GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS),
1696 GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SD2_DAT2),
1697 GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B),
1698 GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SD2_DAT3), GPIO_FN(MT0_BEN),
1699 GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4),
1700 GPIO_FN(SD2_CLK), GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST),
1701 GPIO_FN(HSPI_CLK1_D), GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5),
1702 GPIO_FN(SD2_CMD), GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK),
1703 GPIO_FN(HSPI_CS1_D), GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6),
1704 GPIO_FN(SD2_CD), GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS),
1705 GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(SD2_WP),
1706 GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D),
1707 GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), GPIO_FN(DU1_DOTCLKOUT1),
1708 GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO),
1709 GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1),
1710 GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), GPIO_FN(RX2),
1711 GPIO_FN(HRTS0_B),
1712
1713 /* IPSR12 */
1714 GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1),
1715 GPIO_FN(TS_SPSYNC1), GPIO_FN(SCK2), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3),
1716 GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1),
1717 GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4),
1718 GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B),
1719 GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5),
1720 GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(TX4_B), GPIO_FN(SIM_D_B),
1721 GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB),
1722 GPIO_FN(RX4_B), GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7),
1723 GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), GPIO_FN(SCK4_B),
1724};
1725
1726static struct pinmux_cfg_reg pinmux_config_regs[] = {
1727 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
1728 GP_0_31_FN, FN_IP3_31_29,
1729 GP_0_30_FN, FN_IP3_26_24,
1730 GP_0_29_FN, FN_IP3_22_21,
1731 GP_0_28_FN, FN_IP3_14_12,
1732 GP_0_27_FN, FN_IP3_11_9,
1733 GP_0_26_FN, FN_IP3_2_0,
1734 GP_0_25_FN, FN_IP2_30_28,
1735 GP_0_24_FN, FN_IP2_21_19,
1736 GP_0_23_FN, FN_IP2_18_16,
1737 GP_0_22_FN, FN_IP0_30_28,
1738 GP_0_21_FN, FN_IP0_5_3,
1739 GP_0_20_FN, FN_IP1_18_15,
1740 GP_0_19_FN, FN_IP1_14_11,
1741 GP_0_18_FN, FN_IP1_10_7,
1742 GP_0_17_FN, FN_IP1_6_4,
1743 GP_0_16_FN, FN_IP1_3_2,
1744 GP_0_15_FN, FN_IP1_1_0,
1745 GP_0_14_FN, FN_IP0_27_26,
1746 GP_0_13_FN, FN_IP0_25,
1747 GP_0_12_FN, FN_IP0_24_23,
1748 GP_0_11_FN, FN_IP0_22_19,
1749 GP_0_10_FN, FN_IP0_18_16,
1750 GP_0_9_FN, FN_IP0_15_14,
1751 GP_0_8_FN, FN_IP0_13_12,
1752 GP_0_7_FN, FN_IP0_11_10,
1753 GP_0_6_FN, FN_IP0_9_8,
1754 GP_0_5_FN, FN_A19,
1755 GP_0_4_FN, FN_A18,
1756 GP_0_3_FN, FN_A17,
1757 GP_0_2_FN, FN_IP0_7_6,
1758 GP_0_1_FN, FN_AVS2,
1759 GP_0_0_FN, FN_AVS1 }
1760 },
1761 { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
1762 GP_1_31_FN, FN_IP5_23_21,
1763 GP_1_30_FN, FN_IP5_20_17,
1764 GP_1_29_FN, FN_IP5_16_15,
1765 GP_1_28_FN, FN_IP5_14_13,
1766 GP_1_27_FN, FN_IP5_12_11,
1767 GP_1_26_FN, FN_IP5_10_9,
1768 GP_1_25_FN, FN_IP5_8,
1769 GP_1_24_FN, FN_IP5_7,
1770 GP_1_23_FN, FN_IP5_6,
1771 GP_1_22_FN, FN_IP5_5,
1772 GP_1_21_FN, FN_IP5_4,
1773 GP_1_20_FN, FN_IP5_3,
1774 GP_1_19_FN, FN_IP5_2_0,
1775 GP_1_18_FN, FN_IP4_31_29,
1776 GP_1_17_FN, FN_IP4_28,
1777 GP_1_16_FN, FN_IP4_27,
1778 GP_1_15_FN, FN_IP4_26,
1779 GP_1_14_FN, FN_IP4_25,
1780 GP_1_13_FN, FN_IP4_24,
1781 GP_1_12_FN, FN_IP4_23,
1782 GP_1_11_FN, FN_IP4_22_20,
1783 GP_1_10_FN, FN_IP4_19_17,
1784 GP_1_9_FN, FN_IP4_16,
1785 GP_1_8_FN, FN_IP4_15,
1786 GP_1_7_FN, FN_IP4_14,
1787 GP_1_6_FN, FN_IP4_13,
1788 GP_1_5_FN, FN_IP4_12,
1789 GP_1_4_FN, FN_IP4_11,
1790 GP_1_3_FN, FN_IP4_10_8,
1791 GP_1_2_FN, FN_IP4_7_5,
1792 GP_1_1_FN, FN_IP4_4_2,
1793 GP_1_0_FN, FN_IP4_1_0 }
1794 },
1795 { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
1796 GP_2_31_FN, FN_IP10_28_26,
1797 GP_2_30_FN, FN_IP10_25_24,
1798 GP_2_29_FN, FN_IP10_23_21,
1799 GP_2_28_FN, FN_IP10_20_18,
1800 GP_2_27_FN, FN_IP10_17_15,
1801 GP_2_26_FN, FN_IP10_14_12,
1802 GP_2_25_FN, FN_IP10_11_9,
1803 GP_2_24_FN, FN_IP10_8_6,
1804 GP_2_23_FN, FN_IP10_5_3,
1805 GP_2_22_FN, FN_IP10_2_0,
1806 GP_2_21_FN, FN_IP9_29_28,
1807 GP_2_20_FN, FN_IP9_27_26,
1808 GP_2_19_FN, FN_IP9_25_24,
1809 GP_2_18_FN, FN_IP9_23_22,
1810 GP_2_17_FN, FN_IP9_21_19,
1811 GP_2_16_FN, FN_IP9_18_16,
1812 GP_2_15_FN, FN_IP9_15_14,
1813 GP_2_14_FN, FN_IP9_13_12,
1814 GP_2_13_FN, FN_IP9_11_10,
1815 GP_2_12_FN, FN_IP9_9_8,
1816 GP_2_11_FN, FN_IP9_7,
1817 GP_2_10_FN, FN_IP9_6,
1818 GP_2_9_FN, FN_IP9_5,
1819 GP_2_8_FN, FN_IP9_4,
1820 GP_2_7_FN, FN_IP9_3_2,
1821 GP_2_6_FN, FN_IP9_1_0,
1822 GP_2_5_FN, FN_IP8_30_28,
1823 GP_2_4_FN, FN_IP8_27_25,
1824 GP_2_3_FN, FN_IP8_24_23,
1825 GP_2_2_FN, FN_IP8_22_21,
1826 GP_2_1_FN, FN_IP8_20,
1827 GP_2_0_FN, FN_IP5_27_24 }
1828 },
1829 { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
1830 GP_3_31_FN, FN_IP6_3_2,
1831 GP_3_30_FN, FN_IP6_1_0,
1832 GP_3_29_FN, FN_IP5_30_29,
1833 GP_3_28_FN, FN_IP5_28,
1834 GP_3_27_FN, FN_IP1_24_23,
1835 GP_3_26_FN, FN_IP1_22_21,
1836 GP_3_25_FN, FN_IP1_20_19,
1837 GP_3_24_FN, FN_IP7_26_25,
1838 GP_3_23_FN, FN_IP7_24_23,
1839 GP_3_22_FN, FN_IP7_22_21,
1840 GP_3_21_FN, FN_IP7_20_19,
1841 GP_3_20_FN, FN_IP7_30_29,
1842 GP_3_19_FN, FN_IP7_28_27,
1843 GP_3_18_FN, FN_IP7_18_17,
1844 GP_3_17_FN, FN_IP7_16_15,
1845 GP_3_16_FN, FN_IP12_17_15,
1846 GP_3_15_FN, FN_IP12_14_12,
1847 GP_3_14_FN, FN_IP12_11_9,
1848 GP_3_13_FN, FN_IP12_8_6,
1849 GP_3_12_FN, FN_IP12_5_3,
1850 GP_3_11_FN, FN_IP12_2_0,
1851 GP_3_10_FN, FN_IP11_29_27,
1852 GP_3_9_FN, FN_IP11_26_24,
1853 GP_3_8_FN, FN_IP11_23_21,
1854 GP_3_7_FN, FN_IP11_20_18,
1855 GP_3_6_FN, FN_IP11_17_15,
1856 GP_3_5_FN, FN_IP11_14_12,
1857 GP_3_4_FN, FN_IP11_11_9,
1858 GP_3_3_FN, FN_IP11_8_6,
1859 GP_3_2_FN, FN_IP11_5_3,
1860 GP_3_1_FN, FN_IP11_2_0,
1861 GP_3_0_FN, FN_IP10_31_29 }
1862 },
1863 { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
1864 GP_4_31_FN, FN_IP8_19,
1865 GP_4_30_FN, FN_IP8_18,
1866 GP_4_29_FN, FN_IP8_17_16,
1867 GP_4_28_FN, FN_IP0_2_0,
1868 GP_4_27_FN, FN_PENC1,
1869 GP_4_26_FN, FN_PENC0,
1870 GP_4_25_FN, FN_IP8_15_12,
1871 GP_4_24_FN, FN_IP8_11_8,
1872 GP_4_23_FN, FN_IP8_7_4,
1873 GP_4_22_FN, FN_IP8_3_0,
1874 GP_4_21_FN, FN_IP2_3_0,
1875 GP_4_20_FN, FN_IP1_28_25,
1876 GP_4_19_FN, FN_IP2_15_12,
1877 GP_4_18_FN, FN_IP2_11_8,
1878 GP_4_17_FN, FN_IP2_7_4,
1879 GP_4_16_FN, FN_IP7_14_13,
1880 GP_4_15_FN, FN_IP7_12_10,
1881 GP_4_14_FN, FN_IP7_9_7,
1882 GP_4_13_FN, FN_IP7_6_4,
1883 GP_4_12_FN, FN_IP7_3_2,
1884 GP_4_11_FN, FN_IP7_1_0,
1885 GP_4_10_FN, FN_IP6_30_29,
1886 GP_4_9_FN, FN_IP6_26_25,
1887 GP_4_8_FN, FN_IP6_24_23,
1888 GP_4_7_FN, FN_IP6_22_20,
1889 GP_4_6_FN, FN_IP6_19_18,
1890 GP_4_5_FN, FN_IP6_17_15,
1891 GP_4_4_FN, FN_IP6_14_12,
1892 GP_4_3_FN, FN_IP6_11_9,
1893 GP_4_2_FN, FN_IP6_8,
1894 GP_4_1_FN, FN_IP6_7_6,
1895 GP_4_0_FN, FN_IP6_5_4 }
1896 },
1897 { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1) {
1898 GP_5_31_FN, FN_IP3_5,
1899 GP_5_30_FN, FN_IP3_4,
1900 GP_5_29_FN, FN_IP3_3,
1901 GP_5_28_FN, FN_IP2_27,
1902 GP_5_27_FN, FN_IP2_26,
1903 GP_5_26_FN, FN_IP2_25,
1904 GP_5_25_FN, FN_IP2_24,
1905 GP_5_24_FN, FN_IP2_23,
1906 GP_5_23_FN, FN_IP2_22,
1907 GP_5_22_FN, FN_IP3_28,
1908 GP_5_21_FN, FN_IP3_27,
1909 GP_5_20_FN, FN_IP3_23,
1910 GP_5_19_FN, FN_EX_WAIT0,
1911 GP_5_18_FN, FN_WE1,
1912 GP_5_17_FN, FN_WE0,
1913 GP_5_16_FN, FN_RD,
1914 GP_5_15_FN, FN_A16,
1915 GP_5_14_FN, FN_A15,
1916 GP_5_13_FN, FN_A14,
1917 GP_5_12_FN, FN_A13,
1918 GP_5_11_FN, FN_A12,
1919 GP_5_10_FN, FN_A11,
1920 GP_5_9_FN, FN_A10,
1921 GP_5_8_FN, FN_A9,
1922 GP_5_7_FN, FN_A8,
1923 GP_5_6_FN, FN_A7,
1924 GP_5_5_FN, FN_A6,
1925 GP_5_4_FN, FN_A5,
1926 GP_5_3_FN, FN_A4,
1927 GP_5_2_FN, FN_A3,
1928 GP_5_1_FN, FN_A2,
1929 GP_5_0_FN, FN_A1 }
1930 },
1931 { PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1) {
1932 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1933 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1934 0, 0, 0, 0, 0, 0, 0, 0,
1935 0, 0,
1936 0, 0,
1937 0, 0,
1938 GP_6_8_FN, FN_IP3_20,
1939 GP_6_7_FN, FN_IP3_19,
1940 GP_6_6_FN, FN_IP3_18,
1941 GP_6_5_FN, FN_IP3_17,
1942 GP_6_4_FN, FN_IP3_16,
1943 GP_6_3_FN, FN_IP3_15,
1944 GP_6_2_FN, FN_IP3_8,
1945 GP_6_1_FN, FN_IP3_7,
1946 GP_6_0_FN, FN_IP3_6 }
1947 },
1948
1949 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
1950 1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3) {
1951 /* IP0_31 [1] */
1952 0, 0,
1953 /* IP0_30_28 [3] */
1954 FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
1955 FN_HRTS1, FN_RX4_C, 0, 0,
1956 /* IP0_27_26 [2] */
1957 FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, 0,
1958 /* IP0_25 [1] */
1959 FN_CS0, FN_HSPI_CS2_B,
1960 /* IP0_24_23 [2] */
1961 FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, 0,
1962 /* IP0_22_19 [4] */
1963 FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
1964 FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
1965 FN_CTS0_B, 0, 0, 0,
1966 0, 0, 0, 0,
1967 /* IP0_18_16 [3] */
1968 FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
1969 FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, 0,
1970 /* IP0_15_14 [2] */
1971 FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
1972 /* IP0_13_12 [2] */
1973 FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
1974 /* IP0_11_10 [2] */
1975 FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, 0,
1976 /* IP0_9_8 [2] */
1977 FN_A20, FN_TX5_D, FN_HSPI_TX2_B, 0,
1978 /* IP0_7_6 [2] */
1979 FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
1980 /* IP0_5_3 [3] */
1981 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
1982 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
1983 /* IP0_2_0 [3] */
1984 FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
1985 FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
1986 },
1987 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
1988 3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2) {
1989 /* IP1_31_29 [3] */
1990 0, 0, 0, 0, 0, 0, 0, 0,
1991 /* IP1_28_25 [4] */
1992 FN_HTX0, FN_TX1, FN_SDATA, FN_CTS0_C,
1993 FN_SUB_TCK, FN_CC5_STATE2, FN_CC5_STATE10, FN_CC5_STATE18,
1994 FN_CC5_STATE26, FN_CC5_STATE34, 0, 0,
1995 0, 0, 0, 0,
1996 /* IP1_24_23 [2] */
1997 FN_MLB_DAT, FN_PWM4, FN_RX4, 0,
1998 /* IP1_22_21 [2] */
1999 FN_MLB_SIG, FN_PWM3, FN_TX4, 0,
2000 /* IP1_20_19 [2] */
2001 FN_MLB_CLK, FN_PWM2, FN_SCK4, 0,
2002 /* IP1_18_15 [4] */
2003 FN_EX_CS5, FN_SD1_DAT1, FN_MMC0_D1, FN_FD1,
2004 FN_ATAWR0, FN_VI1_R6, FN_HRX1, FN_RX2_E,
2005 FN_RX0_B, FN_SSI_WS9, 0, 0,
2006 0, 0, 0, 0,
2007 /* IP1_14_11 [4] */
2008 FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
2009 FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
2010 FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, 0,
2011 0, 0, 0, 0,
2012 /* IP1_10_7 [4] */
2013 FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, FN_FRE,
2014 FN_ATACS10, FN_VI1_R4, FN_RX5_B, FN_HSCK1,
2015 FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, 0,
2016 0, 0, 0, 0,
2017 /* IP1_6_4 [3] */
2018 FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
2019 FN_ATACS00, 0, 0, 0,
2020 /* IP1_3_2 [2] */
2021 FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0,
2022 /* IP1_1_0 [2] */
2023 FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 }
2024 },
2025 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
2026 1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4) {
2027 /* IP2_31 [1] */
2028 0, 0,
2029 /* IP2_30_28 [3] */
2030 FN_DU0_DG0, FN_LCDOUT8, FN_DREQ1, FN_SCL2,
2031 FN_AUDATA2, 0, 0, 0,
2032 /* IP2_27 [1] */
2033 FN_DU0_DR7, FN_LCDOUT7,
2034 /* IP2_26 [1] */
2035 FN_DU0_DR6, FN_LCDOUT6,
2036 /* IP2_25 [1] */
2037 FN_DU0_DR5, FN_LCDOUT5,
2038 /* IP2_24 [1] */
2039 FN_DU0_DR4, FN_LCDOUT4,
2040 /* IP2_23 [1] */
2041 FN_DU0_DR3, FN_LCDOUT3,
2042 /* IP2_22 [1] */
2043 FN_DU0_DR2, FN_LCDOUT2,
2044 /* IP2_21_19 [3] */
2045 FN_DU0_DR1, FN_LCDOUT1, FN_DACK0, FN_DRACK0,
2046 FN_GPS_SIGN_B, FN_AUDATA1, FN_RX5_C, 0,
2047 /* IP2_18_16 [3] */
2048 FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, FN_GPS_CLK_B,
2049 FN_AUDATA0, FN_TX5_C, 0, 0,
2050 /* IP2_15_12 [4] */
2051 FN_HRTS0, FN_RTS1_TANS, FN_MDATA, FN_TX0_C,
2052 FN_SUB_TMS, FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17,
2053 FN_CC5_STATE25, FN_CC5_STATE33, 0, 0,
2054 0, 0, 0, 0,
2055 /* IP2_11_8 [4] */
2056 FN_HCTS0, FN_CTS1, FN_STM, FN_PWM0_D,
2057 FN_RX0_C, FN_SCIF_CLK_C, FN_SUB_TRST, FN_TCLK1_B,
2058 FN_CC5_OSCOUT, 0, 0, 0,
2059 0, 0, 0, 0,
2060 /* IP2_7_4 [4] */
2061 FN_HSCK0, FN_SCK1, FN_MTS, FN_PWM5,
2062 FN_SCK0_C, FN_SSI_SDATA9_B, FN_SUB_TDO, FN_CC5_STATE0,
2063 FN_CC5_STATE8, FN_CC5_STATE16, FN_CC5_STATE24, FN_CC5_STATE32,
2064 0, 0, 0, 0,
2065 /* IP2_3_0 [4] */
2066 FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
2067 FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
2068 FN_CC5_STATE27, FN_CC5_STATE35, 0, 0,
2069 0, 0, 0, 0 }
2070 },
2071 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
2072 3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1,
2073 1, 3, 3, 1, 1, 1, 1, 1, 1, 3) {
2074 /* IP3_31_29 [3] */
2075 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C,
2076 FN_SCL2_C, FN_REMOCON, 0, 0,
2077 /* IP3_28 [1] */
2078 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
2079 /* IP3_27 [1] */
2080 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
2081 /* IP3_26_24 [3] */
2082 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
2083 FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, 0,
2084 /* IP3_23 [1] */
2085 FN_DU0_DOTCLKOUT0, FN_QCLK,
2086 /* IP3_22_21 [2] */
2087 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_TX3_D_IRDA_TX_D, FN_SCL3_B,
2088 /* IP3_20 [1] */
2089 FN_DU0_DB7, FN_LCDOUT23,
2090 /* IP3_19 [1] */
2091 FN_DU0_DB6, FN_LCDOUT22,
2092 /* IP3_18 [1] */
2093 FN_DU0_DB5, FN_LCDOUT21,
2094 /* IP3_17 [1] */
2095 FN_DU0_DB4, FN_LCDOUT20,
2096 /* IP3_16 [1] */
2097 FN_DU0_DB3, FN_LCDOUT19,
2098 /* IP3_15 [1] */
2099 FN_DU0_DB2, FN_LCDOUT18,
2100 /* IP3_14_12 [3] */
2101 FN_DU0_DB1, FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1,
2102 FN_GPS_MAG_B, FN_AUDATA5, FN_SCK5_C, 0,
2103 /* IP3_11_9 [3] */
2104 FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, FN_SCL1,
2105 FN_TCLK1, FN_AUDATA4, 0, 0,
2106 /* IP3_8 [1] */
2107 FN_DU0_DG7, FN_LCDOUT15,
2108 /* IP3_7 [1] */
2109 FN_DU0_DG6, FN_LCDOUT14,
2110 /* IP3_6 [1] */
2111 FN_DU0_DG5, FN_LCDOUT13,
2112 /* IP3_5 [1] */
2113 FN_DU0_DG4, FN_LCDOUT12,
2114 /* IP3_4 [1] */
2115 FN_DU0_DG3, FN_LCDOUT11,
2116 /* IP3_3 [1] */
2117 FN_DU0_DG2, FN_LCDOUT10,
2118 /* IP3_2_0 [3] */
2119 FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
2120 FN_AUDATA3, 0, 0, 0 }
2121 },
2122 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
2123 3, 1, 1, 1, 1, 1, 1, 3, 3, 1,
2124 1, 1, 1, 1, 1, 1, 3, 3, 3, 2) {
2125 /* IP4_31_29 [3] */
2126 FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0,
2127 FN_TX5, FN_SCK0_D, 0, 0,
2128 /* IP4_28 [1] */
2129 FN_DU1_DG7, FN_VI2_R3,
2130 /* IP4_27 [1] */
2131 FN_DU1_DG6, FN_VI2_R2,
2132 /* IP4_26 [1] */
2133 FN_DU1_DG5, FN_VI2_R1,
2134 /* IP4_25 [1] */
2135 FN_DU1_DG4, FN_VI2_R0,
2136 /* IP4_24 [1] */
2137 FN_DU1_DG3, FN_VI2_G7,
2138 /* IP4_23 [1] */
2139 FN_DU1_DG2, FN_VI2_G6,
2140 /* IP4_22_20 [3] */
2141 FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
2142 FN_SCK5, FN_AUDATA7, FN_RX0_D, 0,
2143 /* IP4_19_17 [3] */
2144 FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, FN_SD3_DAT2,
2145 FN_SCK3_E, FN_AUDATA6, FN_TX0_D, 0,
2146 /* IP4_16 [1] */
2147 FN_DU1_DR7, FN_VI2_G5,
2148 /* IP4_15 [1] */
2149 FN_DU1_DR6, FN_VI2_G4,
2150 /* IP4_14 [1] */
2151 FN_DU1_DR5, FN_VI2_G3,
2152 /* IP4_13 [1] */
2153 FN_DU1_DR4, FN_VI2_G2,
2154 /* IP4_12 [1] */
2155 FN_DU1_DR3, FN_VI2_G1,
2156 /* IP4_11 [1] */
2157 FN_DU1_DR2, FN_VI2_G0,
2158 /* IP4_10_8 [3] */
2159 FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, FN_PWM0, FN_SD3_CMD,
2160 FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, FN_CTS0_D, 0,
2161 /* IP4_7_5 [3] */
2162 FN_DU1_DR0, FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK,
2163 FN_TX3_E_IRDA_TX_E, FN_AUDCK, FN_PWMFSW0_B, 0,
2164 /* IP4_4_2 [3] */
2165 FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
2166 FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0,
2167 /* IP4_1_0 [2] */
2168 FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C }
2169 },
2170 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
2171 1, 2, 1, 4, 3, 4, 2, 2,
2172 2, 2, 1, 1, 1, 1, 1, 1, 3) {
2173 /* IP5_31 [1] */
2174 0, 0,
2175 /* IP5_30_29 [2] */
2176 FN_AUDIO_CLKB, FN_USB_OVC2, FN_CAN_DEBUGOUT0, FN_MOUT0,
2177 /* IP5_28 [1] */
2178 FN_AUDIO_CLKA, FN_CAN_TXCLK,
2179 /* IP5_27_24 [4] */
2180 FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, FN_SD3_WP,
2181 FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, FN_AUDIO_CLKOUT,
2182 FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, 0,
2183 0, 0, 0, 0,
2184 /* IP5_23_21 [3] */
2185 FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
2186 FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
2187 /* IP5_20_17 [4] */
2188 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
2189 FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
2190 FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, 0,
2191 0, 0, 0, 0,
2192 /* IP5_16_15 [2] */
2193 FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, 0,
2194 /* IP5_14_13 [2] */
2195 FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, FN_VI3_HSYNC, 0,
2196 /* IP5_12_11 [2] */
2197 FN_DU1_DOTCLKOUT, FN_VI2_FIELD, FN_SDA1_D, 0,
2198 /* IP5_10_9 [2] */
2199 FN_DU1_DOTCLKIN, FN_VI2_CLKENB, FN_HSPI_CS1, FN_SCL1_D,
2200 /* IP5_8 [1] */
2201 FN_DU1_DB7, FN_SDA2_D,
2202 /* IP5_7 [1] */
2203 FN_DU1_DB6, FN_SCL2_D,
2204 /* IP5_6 [1] */
2205 FN_DU1_DB5, FN_VI2_R7,
2206 /* IP5_5 [1] */
2207 FN_DU1_DB4, FN_VI2_R6,
2208 /* IP5_4 [1] */
2209 FN_DU1_DB3, FN_VI2_R5,
2210 /* IP5_3 [1] */
2211 FN_DU1_DB2, FN_VI2_R4,
2212 /* IP5_2_0 [3] */
2213 FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
2214 FN_RX5, FN_RTS0_D_TANS_D, 0, 0 }
2215 },
2216 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
2217 1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2, 2, 2, 2) {
2218 /* IP6_31 [1] */
2219 0, 0,
2220 /* IP6_30_29 [2] */
2221 FN_SSI_SCK6, FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
2222 /* IP_28_27 [2] */
2223 0, 0, 0, 0,
2224 /* IP6_26_25 [2] */
2225 FN_SSI_SDATA5, FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX,
2226 /* IP6_24_23 [2] */
2227 FN_SSI_WS5, FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX,
2228 /* IP6_22_20 [3] */
2229 FN_SSI_SCK5, FN_ADICLK, FN_CAN_DEBUGOUT10, FN_SCK3,
2230 FN_TCLK0_D, 0, 0, 0,
2231 /* IP6_19_18 [2] */
2232 FN_SSI_SDATA4, FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, 0,
2233 /* IP6_17_15 [3] */
2234 FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
2235 FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, 0,
2236 /* IP6_14_12 [3] */
2237 FN_SSI_WS34, FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX,
2238 FN_SSI_WS9_C, 0, 0, 0,
2239 /* IP6_11_9 [3] */
2240 FN_SSI_SCK34, FN_CAN_DEBUGOUT6, FN_CAN0_TX_B, FN_IERX,
2241 FN_SSI_SCK9_C, 0, 0, 0,
2242 /* IP6_8 [1] */
2243 FN_SSI_SDATA2, FN_CAN_DEBUGOUT5,
2244 /* IP6_7_6 [2] */
2245 FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, 0,
2246 /* IP6_5_4 [2] */
2247 FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, FN_MOUT5, 0,
2248 /* IP6_3_2 [2] */
2249 FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0,
2250 /* IP6_1_0 [2] */
2251 FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 }
2252 },
2253 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
2254 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 2, 2) {
2255 /* IP7_31 [1] */
2256 0, 0,
2257 /* IP7_30_29 [2] */
2258 FN_SD0_WP, FN_DACK2, FN_CTS1_B, 0,
2259 /* IP7_28_27 [2] */
2260 FN_SD0_CD, FN_DREQ2, FN_RTS1_B_TANS_B, 0,
2261 /* IP7_26_25 [2] */
2262 FN_SD0_DAT3, FN_ATAWR1, FN_RX2_B, FN_CC5_TDI,
2263 /* IP7_24_23 [2] */
2264 FN_SD0_DAT2, FN_ATARD1, FN_TX2_B, FN_CC5_TCK,
2265 /* IP7_22_21 [2] */
2266 FN_SD0_DAT1, FN_ATAG1, FN_SCK2_B, FN_CC5_TMS,
2267 /* IP7_20_19 [2] */
2268 FN_SD0_DAT0, FN_ATADIR1, FN_RX1_B, FN_CC5_TRST,
2269 /* IP7_18_17 [2] */
2270 FN_SD0_CMD, FN_ATACS11, FN_TX1_B, FN_CC5_TDO,
2271 /* IP7_16_15 [2] */
2272 FN_SD0_CLK, FN_ATACS01, FN_SCK1_B, 0,
2273 /* IP7_14_13 [2] */
2274 FN_SSI_SDATA8, FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C,
2275 /* IP7_12_10 [3] */
2276 FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, FN_IRQ2_B, FN_TCLK1_C,
2277 FN_HSPI_TX1_C, 0, 0, 0,
2278 /* IP7_9_7 [3] */
2279 FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, FN_SSI_WS9_B,
2280 FN_HSPI_CS1_C, 0, 0, 0,
2281 /* IP7_6_4 [3] */
2282 FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
2283 FN_HSPI_CLK1_C, 0, 0, 0,
2284 /* IP7_3_2 [2] */
2285 FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
2286 /* IP7_1_0 [2] */
2287 FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B }
2288 },
2289 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
2290 1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4) {
2291 /* IP8_31 [1] */
2292 0, 0,
2293 /* IP8_30_28 [3] */
2294 FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, FN_RTS1_C_TANS_C, FN_RX4_D,
2295 FN_PWMFSW0_C, 0, 0, 0,
2296 /* IP8_27_25 [3] */
2297 FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
2298 FN_MMC1_CMD, FN_HSCK1_B, 0, 0,
2299 /* IP8_24_23 [2] */
2300 FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, 0,
2301 /* IP8_22_21 [2] */
2302 FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, FN_MT1_SYNC,
2303 /* IP8_20 [1] */
2304 FN_VI0_CLK, FN_MMC1_CLK,
2305 /* IP8_19 [1] */
2306 FN_FMIN, FN_RDS_DATA,
2307 /* IP8_18 [1] */
2308 FN_BPFCLK, FN_PCMWE,
2309 /* IP8_17_16 [2] */
2310 FN_FMCLK, FN_RDS_CLK, FN_PCMOE, 0,
2311 /* IP8_15_12 [4] */
2312 FN_HSPI_RX0, FN_RX0, FN_CAN_STEP0, FN_AD_NCS,
2313 FN_CC5_STATE7, FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31,
2314 FN_CC5_STATE39, 0, 0, 0,
2315 0, 0, 0, 0,
2316 /* IP8_11_8 [4] */
2317 FN_HSPI_TX0, FN_TX0, FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO,
2318 FN_CC5_STATE6, FN_CC5_STATE14, FN_CC5_STATE22, FN_CC5_STATE30,
2319 FN_CC5_STATE38, 0, 0, 0,
2320 0, 0, 0, 0,
2321 /* IP8_7_4 [4] */
2322 FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, FN_AD_DI,
2323 FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, FN_CC5_STATE29,
2324 FN_CC5_STATE37, 0, 0, 0,
2325 0, 0, 0, 0,
2326 /* IP8_3_0 [4] */
2327 FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
2328 FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
2329 FN_CC5_STATE36, 0, 0, 0,
2330 0, 0, 0, 0 }
2331 },
2332 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
2333 2, 2, 2, 2, 2, 3, 3, 2, 2,
2334 2, 2, 1, 1, 1, 1, 2, 2) {
2335 /* IP9_31_30 [2] */
2336 0, 0, 0, 0,
2337 /* IP9_29_28 [2] */
2338 FN_VI0_G7, FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
2339 /* IP9_27_26 [2] */
2340 FN_VI0_G6, FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8,
2341 /* IP9_25_24 [2] */
2342 FN_VI0_G5, FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7,
2343 /* IP9_23_22 [2] */
2344 FN_VI0_G4, FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6,
2345 /* IP9_21_19 [3] */
2346 FN_VI0_G3, FN_ETH_CRS_DV, FN_MMC1_D7, FN_ARM_TRACEDATA_5,
2347 FN_TS_SDAT0, 0, 0, 0,
2348 /* IP9_18_16 [3] */
2349 FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, FN_ARM_TRACEDATA_4,
2350 FN_TS_SPSYNC0, 0, 0, 0,
2351 /* IP9_15_14 [2] */
2352 FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, FN_ARM_TRACEDATA_3,
2353 /* IP9_13_12 [2] */
2354 FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, FN_ARM_TRACEDATA_2,
2355 /* IP9_11_10 [2] */
2356 FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, FN_ARM_TRACEDATA_1, 0,
2357 /* IP9_9_8 [2] */
2358 FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, FN_ARM_TRACEDATA_0, 0,
2359 /* IP9_7 [1] */
2360 FN_VI0_DATA5_VI0_B5, FN_MMC1_D3,
2361 /* IP9_6 [1] */
2362 FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
2363 /* IP9_5 [1] */
2364 FN_VI0_DATA3_VI0_B3, FN_MMC1_D1,
2365 /* IP9_4 [1] */
2366 FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
2367 /* IP9_3_2 [2] */
2368 FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0,
2369 /* IP9_1_0 [2] */
2370 FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 }
2371 },
2372 { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
2373 3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
2374 /* IP10_31_29 [3] */
2375 FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK,
2376 FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0,
2377 /* IP10_28_26 [3] */
2378 FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
2379 FN_PWMFSW0_E, 0, 0, 0,
2380 /* IP10_25_24 [2] */
2381 FN_VI1_CLK, FN_SIM_D, FN_SDA3, 0,
2382 /* IP10_23_21 [3] */
2383 FN_VI0_R7, FN_ETH_MDIO, FN_DACK2_C, FN_HSPI_RX1_B,
2384 FN_SCIF_CLK_D, FN_TRACECTL, FN_MT1_PEN, 0,
2385 /* IP10_20_18 [3] */
2386 FN_VI0_R6, FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B,
2387 FN_TRACECLK, FN_MT1_BEN, FN_PWMFSW0_D, 0,
2388 /* IP10_17_15 [3] */
2389 FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
2390 FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, 0,
2391 /* IP10_14_12 [3] */
2392 FN_VI0_R4, FN_ETH_REFCLK, FN_SD2_CD_B, FN_HSPI_CLK1_B,
2393 FN_ARM_TRACEDATA_14, FN_MT1_CLK, FN_TS_SCK0, 0,
2394 /* IP10_11_9 [3] */
2395 FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, FN_IRQ3,
2396 FN_ARM_TRACEDATA_13, 0, 0, 0,
2397 /* IP10_8_6 [3] */
2398 FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
2399 FN_ARM_TRACEDATA_12, 0, 0, 0,
2400 /* IP10_5_3 [3] */
2401 FN_VI0_R1, FN_SSI_SDATA8_C, FN_DACK1_B, FN_ARM_TRACEDATA_11,
2402 FN_DACK0_C, FN_DRACK0_C, 0, 0,
2403 /* IP10_2_0 [3] */
2404 FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
2405 FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 }
2406 },
2407 { PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32,
2408 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
2409 /* IP11_31_30 [2] */
2410 0, 0, 0, 0,
2411 /* IP11_29_27 [3] */
2412 FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
2413 FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
2414 /* IP11_26_24 [3] */
2415 FN_VI1_G0, FN_VI3_DATA0, FN_DU1_DOTCLKOUT1, FN_TS_SCK1,
2416 FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B,
2417 /* IP11_23_21 [3] */
2418 FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI,
2419 FN_HSPI_RX1_D, 0, 0, 0,
2420 /* IP11_20_18 [3] */
2421 FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
2422 FN_HSPI_TX1_D, 0, 0, 0,
2423 /* IP11_17_15 [3] */
2424 FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, FN_MT0_SYNC, FN_SPA_TCK,
2425 FN_HSPI_CS1_D, FN_ADICHS2_B, 0, 0,
2426 /* IP11_14_12 [3] */
2427 FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
2428 FN_HSPI_CLK1_D, FN_ADICHS1_B, 0, 0,
2429 /* IP11_11_9 [3] */
2430 FN_VI1_DATA3_VI1_B3, FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO,
2431 FN_ADICHS0_B, 0, 0, 0,
2432 /* IP11_8_6 [3] */
2433 FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, FN_MT0_D, FN_SPVTDI,
2434 FN_ADIDATA_B, 0, 0, 0,
2435 /* IP11_5_3 [3] */
2436 FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, FN_SPV_TMS,
2437 FN_ADICS_B_SAMP_B, 0, 0, 0,
2438 /* IP11_2_0 [3] */
2439 FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
2440 FN_ADICLK_B, 0, 0, 0 }
2441 },
2442 { PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32,
2443 4, 4, 4, 2, 3, 3, 3, 3, 3, 3) {
2444 /* IP12_31_28 [4] */
2445 0, 0, 0, 0, 0, 0, 0, 0,
2446 0, 0, 0, 0, 0, 0, 0, 0,
2447 /* IP12_27_24 [4] */
2448 0, 0, 0, 0, 0, 0, 0, 0,
2449 0, 0, 0, 0, 0, 0, 0, 0,
2450 /* IP12_23_20 [4] */
2451 0, 0, 0, 0, 0, 0, 0, 0,
2452 0, 0, 0, 0, 0, 0, 0, 0,
2453 /* IP12_19_18 [2] */
2454 0, 0, 0, 0,
2455 /* IP12_17_15 [3] */
2456 FN_VI1_G7, FN_VI3_DATA7, FN_GPS_MAG, FN_FCE,
2457 FN_SCK4_B, 0, 0, 0,
2458 /* IP12_14_12 [3] */
2459 FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
2460 FN_RX4_B, FN_SIM_CLK_B, 0, 0,
2461 /* IP12_11_9 [3] */
2462 FN_VI1_G5, FN_VI3_DATA5, FN_GPS_CLK, FN_FSE,
2463 FN_TX4_B, FN_SIM_D_B, 0, 0,
2464 /* IP12_8_6 [3] */
2465 FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
2466 FN_SIM_RST_B, FN_HRX0_B, 0, 0,
2467 /* IP12_5_3 [3] */
2468 FN_VI1_G3, FN_VI3_DATA3, FN_SSI_SCK2, FN_TS_SDAT1,
2469 FN_SCL1_C, FN_HTX0_B, 0, 0,
2470 /* IP12_2_0 [3] */
2471 FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
2472 FN_SCK2, FN_HSCK0_B, 0, 0 }
2473 },
2474 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xfffc0090, 32,
2475 2, 2, 3, 3, 2, 2, 2, 2, 2,
2476 1, 1, 1, 1, 1, 1, 1, 2, 1, 2) {
2477 /* SEL_SCIF5 [2] */
2478 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
2479 /* SEL_SCIF4 [2] */
2480 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
2481 /* SEL_SCIF3 [3] */
2482 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
2483 FN_SEL_SCIF3_4, 0, 0, 0,
2484 /* SEL_SCIF2 [3] */
2485 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
2486 FN_SEL_SCIF2_4, 0, 0, 0,
2487 /* SEL_SCIF1 [2] */
2488 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
2489 /* SEL_SCIF0 [2] */
2490 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
2491 /* SEL_SSI9 [2] */
2492 FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2, 0,
2493 /* SEL_SSI8 [2] */
2494 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0,
2495 /* SEL_SSI7 [2] */
2496 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
2497 /* SEL_VI0 [1] */
2498 FN_SEL_VI0_0, FN_SEL_VI0_1,
2499 /* SEL_SD2 [1] */
2500 FN_SEL_SD2_0, FN_SEL_SD2_1,
2501 /* SEL_INT3 [1] */
2502 FN_SEL_INT3_0, FN_SEL_INT3_1,
2503 /* SEL_INT2 [1] */
2504 FN_SEL_INT2_0, FN_SEL_INT2_1,
2505 /* SEL_INT1 [1] */
2506 FN_SEL_INT1_0, FN_SEL_INT1_1,
2507 /* SEL_INT0 [1] */
2508 FN_SEL_INT0_0, FN_SEL_INT0_1,
2509 /* SEL_IE [1] */
2510 FN_SEL_IE_0, FN_SEL_IE_1,
2511 /* SEL_EXBUS2 [2] */
2512 FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2, 0,
2513 /* SEL_EXBUS1 [1] */
2514 FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
2515 /* SEL_EXBUS0 [2] */
2516 FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 }
2517 },
2518 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32,
2519 2, 2, 2, 2, 1, 1, 1, 3, 1,
2520 2, 2, 2, 2, 1, 1, 2, 1, 2, 2) {
2521 /* SEL_TMU1 [2] */
2522 FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 0,
2523 /* SEL_TMU0 [2] */
2524 FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
2525 /* SEL_SCIF [2] */
2526 FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
2527 /* SEL_CANCLK [2] */
2528 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
2529 /* SEL_CAN0 [1] */
2530 FN_SEL_CAN0_0, FN_SEL_CAN0_1,
2531 /* SEL_HSCIF1 [1] */
2532 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
2533 /* SEL_HSCIF0 [1] */
2534 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
2535 /* SEL_PWMFSW [3] */
2536 FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
2537 FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, 0, 0, 0,
2538 /* SEL_ADI [1] */
2539 FN_SEL_ADI_0, FN_SEL_ADI_1,
2540 /* [2] */
2541 0, 0, 0, 0,
2542 /* [2] */
2543 0, 0, 0, 0,
2544 /* [2] */
2545 0, 0, 0, 0,
2546 /* SEL_GPS [2] */
2547 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
2548 /* SEL_SIM [1] */
2549 FN_SEL_SIM_0, FN_SEL_SIM_1,
2550 /* SEL_HSPI2 [1] */
2551 FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
2552 /* SEL_HSPI1 [2] */
2553 FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
2554 /* SEL_I2C3 [1] */
2555 FN_SEL_I2C3_0, FN_SEL_I2C3_1,
2556 /* SEL_I2C2 [2] */
2557 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
2558 /* SEL_I2C1 [2] */
2559 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 }
2560 },
2561 { PINMUX_CFG_REG("INOUTSEL0", 0xffc40004, 32, 1) { GP_INOUTSEL(0) } },
2562 { PINMUX_CFG_REG("INOUTSEL1", 0xffc41004, 32, 1) { GP_INOUTSEL(1) } },
2563 { PINMUX_CFG_REG("INOUTSEL2", 0xffc42004, 32, 1) { GP_INOUTSEL(2) } },
2564 { PINMUX_CFG_REG("INOUTSEL3", 0xffc43004, 32, 1) { GP_INOUTSEL(3) } },
2565 { PINMUX_CFG_REG("INOUTSEL4", 0xffc44004, 32, 1) { GP_INOUTSEL(4) } },
2566 { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) { GP_INOUTSEL(5) } },
2567 { PINMUX_CFG_REG("INOUTSEL6", 0xffc46004, 32, 1) {
2568 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2569 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2570 0, 0, 0, 0, 0, 0, 0, 0,
2571 0, 0,
2572 0, 0,
2573 0, 0,
2574 GP_6_8_IN, GP_6_8_OUT,
2575 GP_6_7_IN, GP_6_7_OUT,
2576 GP_6_6_IN, GP_6_6_OUT,
2577 GP_6_5_IN, GP_6_5_OUT,
2578 GP_6_4_IN, GP_6_4_OUT,
2579 GP_6_3_IN, GP_6_3_OUT,
2580 GP_6_2_IN, GP_6_2_OUT,
2581 GP_6_1_IN, GP_6_1_OUT,
2582 GP_6_0_IN, GP_6_0_OUT, }
2583 },
2584 { },
2585};
2586
2587static struct pinmux_data_reg pinmux_data_regs[] = {
2588 { PINMUX_DATA_REG("INDT0", 0xffc40008, 32) { GP_INDT(0) } },
2589 { PINMUX_DATA_REG("INDT1", 0xffc41008, 32) { GP_INDT(1) } },
2590 { PINMUX_DATA_REG("INDT2", 0xffc42008, 32) { GP_INDT(2) } },
2591 { PINMUX_DATA_REG("INDT3", 0xffc43008, 32) { GP_INDT(3) } },
2592 { PINMUX_DATA_REG("INDT4", 0xffc44008, 32) { GP_INDT(4) } },
2593 { PINMUX_DATA_REG("INDT5", 0xffc45008, 32) { GP_INDT(5) } },
2594 { PINMUX_DATA_REG("INDT6", 0xffc46008, 32) {
2595 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2596 0, 0, 0, 0, 0, 0, 0, GP_6_8_DATA,
2597 GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
2598 GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
2599 },
2600 { },
2601};
2602
2603static struct resource r8a7779_pfc_resources[] = {
2604 [0] = {
2605 .start = 0xfffc0000,
2606 .end = 0xfffc023b,
2607 .flags = IORESOURCE_MEM,
2608 },
2609 [1] = {
2610 .start = 0xffc40000,
2611 .end = 0xffc46fff,
2612 .flags = IORESOURCE_MEM,
2613 }
2614};
2615
2616static struct pinmux_info r8a7779_pinmux_info = {
2617 .name = "r8a7779_pfc",
2618
2619 .resource = r8a7779_pfc_resources,
2620 .num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
2621
2622 .unlock_reg = 0xfffc0000, /* PMMR */
2623
2624 .reserved_id = PINMUX_RESERVED,
2625 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2626 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2627 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2628 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2629 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2630
2631 .first_gpio = GPIO_GP_0_0,
2632 .last_gpio = GPIO_FN_SCK4_B,
2633
2634 .gpios = pinmux_gpios,
2635 .cfg_regs = pinmux_config_regs,
2636 .data_regs = pinmux_data_regs,
2637
2638 .gpio_data = pinmux_data,
2639 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2640};
2641
2642void r8a7779_pinmux_init(void)
2643{
2644 register_pinmux(&r8a7779_pinmux_info);
2645}
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
index c49a833bf9bb..993381257f69 100644
--- a/arch/arm/mach-shmobile/platsmp.c
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -22,12 +22,16 @@
22#include <mach/common.h> 22#include <mach/common.h>
23 23
24#define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2()) 24#define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2())
25#define is_r8a7779() machine_is_marzen()
25 26
26static unsigned int __init shmobile_smp_get_core_count(void) 27static unsigned int __init shmobile_smp_get_core_count(void)
27{ 28{
28 if (is_sh73a0()) 29 if (is_sh73a0())
29 return sh73a0_get_core_count(); 30 return sh73a0_get_core_count();
30 31
32 if (is_r8a7779())
33 return r8a7779_get_core_count();
34
31 return 1; 35 return 1;
32} 36}
33 37
@@ -35,6 +39,17 @@ static void __init shmobile_smp_prepare_cpus(void)
35{ 39{
36 if (is_sh73a0()) 40 if (is_sh73a0())
37 sh73a0_smp_prepare_cpus(); 41 sh73a0_smp_prepare_cpus();
42
43 if (is_r8a7779())
44 r8a7779_smp_prepare_cpus();
45}
46
47int shmobile_platform_cpu_kill(unsigned int cpu)
48{
49 if (is_r8a7779())
50 return r8a7779_platform_cpu_kill(cpu);
51
52 return 1;
38} 53}
39 54
40void __cpuinit platform_secondary_init(unsigned int cpu) 55void __cpuinit platform_secondary_init(unsigned int cpu)
@@ -43,6 +58,9 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
43 58
44 if (is_sh73a0()) 59 if (is_sh73a0())
45 sh73a0_secondary_init(cpu); 60 sh73a0_secondary_init(cpu);
61
62 if (is_r8a7779())
63 r8a7779_secondary_init(cpu);
46} 64}
47 65
48int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) 66int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
@@ -50,6 +68,9 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
50 if (is_sh73a0()) 68 if (is_sh73a0())
51 return sh73a0_boot_secondary(cpu); 69 return sh73a0_boot_secondary(cpu);
52 70
71 if (is_r8a7779())
72 return r8a7779_boot_secondary(cpu);
73
53 return -ENOSYS; 74 return -ENOSYS;
54} 75}
55 76
diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c
new file mode 100644
index 000000000000..c38ba7b43ef8
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm-r8a7779.c
@@ -0,0 +1,249 @@
1/*
2 * r8a7779 Power management support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12#include <linux/pm.h>
13#include <linux/suspend.h>
14#include <linux/err.h>
15#include <linux/pm_clock.h>
16#include <linux/platform_device.h>
17#include <linux/delay.h>
18#include <linux/irq.h>
19#include <linux/interrupt.h>
20#include <linux/console.h>
21#include <asm/system.h>
22#include <asm/io.h>
23#include <mach/common.h>
24#include <mach/r8a7779.h>
25
26static void __iomem *r8a7779_sysc_base;
27
28/* SYSC */
29#define SYSCSR 0x00
30#define SYSCISR 0x04
31#define SYSCISCR 0x08
32#define SYSCIER 0x0c
33#define SYSCIMR 0x10
34#define PWRSR0 0x40
35#define PWRSR1 0x80
36#define PWRSR2 0xc0
37#define PWRSR3 0x100
38#define PWRSR4 0x140
39
40#define PWRSR_OFFS 0x00
41#define PWROFFCR_OFFS 0x04
42#define PWRONCR_OFFS 0x0c
43#define PWRER_OFFS 0x14
44
45#define SYSCSR_RETRIES 100
46#define SYSCSR_DELAY_US 1
47
48#define SYSCISR_RETRIES 1000
49#define SYSCISR_DELAY_US 1
50
51#if defined(CONFIG_PM) || defined(CONFIG_SMP)
52
53static DEFINE_SPINLOCK(r8a7779_sysc_lock); /* SMP CPUs + I/O devices */
54
55static int r8a7779_sysc_pwr_on_off(struct r8a7779_pm_ch *r8a7779_ch,
56 int sr_bit, int reg_offs)
57{
58 int k;
59
60 for (k = 0; k < SYSCSR_RETRIES; k++) {
61 if (ioread32(r8a7779_sysc_base + SYSCSR) & (1 << sr_bit))
62 break;
63 udelay(SYSCSR_DELAY_US);
64 }
65
66 if (k == SYSCSR_RETRIES)
67 return -EAGAIN;
68
69 iowrite32(1 << r8a7779_ch->chan_bit,
70 r8a7779_sysc_base + r8a7779_ch->chan_offs + reg_offs);
71
72 return 0;
73}
74
75static int r8a7779_sysc_pwr_off(struct r8a7779_pm_ch *r8a7779_ch)
76{
77 return r8a7779_sysc_pwr_on_off(r8a7779_ch, 0, PWROFFCR_OFFS);
78}
79
80static int r8a7779_sysc_pwr_on(struct r8a7779_pm_ch *r8a7779_ch)
81{
82 return r8a7779_sysc_pwr_on_off(r8a7779_ch, 1, PWRONCR_OFFS);
83}
84
85static int r8a7779_sysc_update(struct r8a7779_pm_ch *r8a7779_ch,
86 int (*on_off_fn)(struct r8a7779_pm_ch *))
87{
88 unsigned int isr_mask = 1 << r8a7779_ch->isr_bit;
89 unsigned int chan_mask = 1 << r8a7779_ch->chan_bit;
90 unsigned int status;
91 unsigned long flags;
92 int ret = 0;
93 int k;
94
95 spin_lock_irqsave(&r8a7779_sysc_lock, flags);
96
97 iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
98
99 do {
100 ret = on_off_fn(r8a7779_ch);
101 if (ret)
102 goto out;
103
104 status = ioread32(r8a7779_sysc_base +
105 r8a7779_ch->chan_offs + PWRER_OFFS);
106 } while (status & chan_mask);
107
108 for (k = 0; k < SYSCISR_RETRIES; k++) {
109 if (ioread32(r8a7779_sysc_base + SYSCISR) & isr_mask)
110 break;
111 udelay(SYSCISR_DELAY_US);
112 }
113
114 if (k == SYSCISR_RETRIES)
115 ret = -EIO;
116
117 iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
118
119 out:
120 spin_unlock_irqrestore(&r8a7779_sysc_lock, flags);
121
122 pr_debug("r8a7779 power domain %d: %02x %02x %02x %02x %02x -> %d\n",
123 r8a7779_ch->isr_bit, ioread32(r8a7779_sysc_base + PWRSR0),
124 ioread32(r8a7779_sysc_base + PWRSR1),
125 ioread32(r8a7779_sysc_base + PWRSR2),
126 ioread32(r8a7779_sysc_base + PWRSR3),
127 ioread32(r8a7779_sysc_base + PWRSR4), ret);
128 return ret;
129}
130
131int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch)
132{
133 return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_off);
134}
135
136int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch)
137{
138 return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_on);
139}
140
141static void __init r8a7779_sysc_init(void)
142{
143 r8a7779_sysc_base = ioremap_nocache(0xffd85000, PAGE_SIZE);
144 if (!r8a7779_sysc_base)
145 panic("unable to ioremap r8a7779 SYSC hardware block\n");
146
147 /* enable all interrupt sources, but do not use interrupt handler */
148 iowrite32(0x0131000e, r8a7779_sysc_base + SYSCIER);
149 iowrite32(0, r8a7779_sysc_base + SYSCIMR);
150}
151
152#else /* CONFIG_PM || CONFIG_SMP */
153
154static inline void r8a7779_sysc_init(void) {}
155
156#endif /* CONFIG_PM || CONFIG_SMP */
157
158#ifdef CONFIG_PM
159
160static int pd_power_down(struct generic_pm_domain *genpd)
161{
162 return r8a7779_sysc_power_down(to_r8a7779_ch(genpd));
163}
164
165static int pd_power_up(struct generic_pm_domain *genpd)
166{
167 return r8a7779_sysc_power_up(to_r8a7779_ch(genpd));
168}
169
170static bool pd_is_off(struct generic_pm_domain *genpd)
171{
172 struct r8a7779_pm_ch *r8a7779_ch = to_r8a7779_ch(genpd);
173 unsigned int st;
174
175 st = ioread32(r8a7779_sysc_base + r8a7779_ch->chan_offs + PWRSR_OFFS);
176 if (st & (1 << r8a7779_ch->chan_bit))
177 return true;
178
179 return false;
180}
181
182static bool pd_active_wakeup(struct device *dev)
183{
184 return true;
185}
186
187void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd)
188{
189 struct generic_pm_domain *genpd = &r8a7779_pd->genpd;
190
191 pm_genpd_init(genpd, NULL, false);
192 genpd->dev_ops.stop = pm_clk_suspend;
193 genpd->dev_ops.start = pm_clk_resume;
194 genpd->dev_ops.active_wakeup = pd_active_wakeup;
195 genpd->dev_irq_safe = true;
196 genpd->power_off = pd_power_down;
197 genpd->power_on = pd_power_up;
198
199 if (pd_is_off(&r8a7779_pd->genpd))
200 pd_power_up(&r8a7779_pd->genpd);
201}
202
203void r8a7779_add_device_to_domain(struct r8a7779_pm_domain *r8a7779_pd,
204 struct platform_device *pdev)
205{
206 struct device *dev = &pdev->dev;
207
208 pm_genpd_add_device(&r8a7779_pd->genpd, dev);
209 if (pm_clk_no_clocks(dev))
210 pm_clk_add(dev, NULL);
211}
212
213struct r8a7779_pm_domain r8a7779_sh4a = {
214 .ch = {
215 .chan_offs = 0x80, /* PWRSR1 .. PWRER1 */
216 .isr_bit = 16, /* SH4A */
217 }
218};
219
220struct r8a7779_pm_domain r8a7779_sgx = {
221 .ch = {
222 .chan_offs = 0xc0, /* PWRSR2 .. PWRER2 */
223 .isr_bit = 20, /* SGX */
224 }
225};
226
227struct r8a7779_pm_domain r8a7779_vdp1 = {
228 .ch = {
229 .chan_offs = 0x100, /* PWRSR3 .. PWRER3 */
230 .isr_bit = 21, /* VDP */
231 }
232};
233
234struct r8a7779_pm_domain r8a7779_impx3 = {
235 .ch = {
236 .chan_offs = 0x140, /* PWRSR4 .. PWRER4 */
237 .isr_bit = 24, /* IMP */
238 }
239};
240
241#endif /* CONFIG_PM */
242
243void __init r8a7779_pm_init(void)
244{
245 static int once;
246
247 if (!once++)
248 r8a7779_sysc_init();
249}
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
new file mode 100644
index 000000000000..986dca6b3fad
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -0,0 +1,352 @@
1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/delay.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/platform_device.h>
25#include <linux/serial_sci.h>
26#include <linux/sh_timer.h>
27#include <mach/r8a7740.h>
28#include <asm/mach-types.h>
29#include <asm/mach/arch.h>
30
31/* SCIFA0 */
32static struct plat_sci_port scif0_platform_data = {
33 .mapbase = 0xe6c40000,
34 .flags = UPF_BOOT_AUTOCONF,
35 .scscr = SCSCR_RE | SCSCR_TE,
36 .scbrr_algo_id = SCBRR_ALGO_4,
37 .type = PORT_SCIFA,
38 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)),
39};
40
41static struct platform_device scif0_device = {
42 .name = "sh-sci",
43 .id = 0,
44 .dev = {
45 .platform_data = &scif0_platform_data,
46 },
47};
48
49/* SCIFA1 */
50static struct plat_sci_port scif1_platform_data = {
51 .mapbase = 0xe6c50000,
52 .flags = UPF_BOOT_AUTOCONF,
53 .scscr = SCSCR_RE | SCSCR_TE,
54 .scbrr_algo_id = SCBRR_ALGO_4,
55 .type = PORT_SCIFA,
56 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)),
57};
58
59static struct platform_device scif1_device = {
60 .name = "sh-sci",
61 .id = 1,
62 .dev = {
63 .platform_data = &scif1_platform_data,
64 },
65};
66
67/* SCIFA2 */
68static struct plat_sci_port scif2_platform_data = {
69 .mapbase = 0xe6c60000,
70 .flags = UPF_BOOT_AUTOCONF,
71 .scscr = SCSCR_RE | SCSCR_TE,
72 .scbrr_algo_id = SCBRR_ALGO_4,
73 .type = PORT_SCIFA,
74 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)),
75};
76
77static struct platform_device scif2_device = {
78 .name = "sh-sci",
79 .id = 2,
80 .dev = {
81 .platform_data = &scif2_platform_data,
82 },
83};
84
85/* SCIFA3 */
86static struct plat_sci_port scif3_platform_data = {
87 .mapbase = 0xe6c70000,
88 .flags = UPF_BOOT_AUTOCONF,
89 .scscr = SCSCR_RE | SCSCR_TE,
90 .scbrr_algo_id = SCBRR_ALGO_4,
91 .type = PORT_SCIFA,
92 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)),
93};
94
95static struct platform_device scif3_device = {
96 .name = "sh-sci",
97 .id = 3,
98 .dev = {
99 .platform_data = &scif3_platform_data,
100 },
101};
102
103/* SCIFA4 */
104static struct plat_sci_port scif4_platform_data = {
105 .mapbase = 0xe6c80000,
106 .flags = UPF_BOOT_AUTOCONF,
107 .scscr = SCSCR_RE | SCSCR_TE,
108 .scbrr_algo_id = SCBRR_ALGO_4,
109 .type = PORT_SCIFA,
110 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)),
111};
112
113static struct platform_device scif4_device = {
114 .name = "sh-sci",
115 .id = 4,
116 .dev = {
117 .platform_data = &scif4_platform_data,
118 },
119};
120
121/* SCIFA5 */
122static struct plat_sci_port scif5_platform_data = {
123 .mapbase = 0xe6cb0000,
124 .flags = UPF_BOOT_AUTOCONF,
125 .scscr = SCSCR_RE | SCSCR_TE,
126 .scbrr_algo_id = SCBRR_ALGO_4,
127 .type = PORT_SCIFA,
128 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)),
129};
130
131static struct platform_device scif5_device = {
132 .name = "sh-sci",
133 .id = 5,
134 .dev = {
135 .platform_data = &scif5_platform_data,
136 },
137};
138
139/* SCIFA6 */
140static struct plat_sci_port scif6_platform_data = {
141 .mapbase = 0xe6cc0000,
142 .flags = UPF_BOOT_AUTOCONF,
143 .scscr = SCSCR_RE | SCSCR_TE,
144 .scbrr_algo_id = SCBRR_ALGO_4,
145 .type = PORT_SCIFA,
146 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)),
147};
148
149static struct platform_device scif6_device = {
150 .name = "sh-sci",
151 .id = 6,
152 .dev = {
153 .platform_data = &scif6_platform_data,
154 },
155};
156
157/* SCIFA7 */
158static struct plat_sci_port scif7_platform_data = {
159 .mapbase = 0xe6cd0000,
160 .flags = UPF_BOOT_AUTOCONF,
161 .scscr = SCSCR_RE | SCSCR_TE,
162 .scbrr_algo_id = SCBRR_ALGO_4,
163 .type = PORT_SCIFA,
164 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)),
165};
166
167static struct platform_device scif7_device = {
168 .name = "sh-sci",
169 .id = 7,
170 .dev = {
171 .platform_data = &scif7_platform_data,
172 },
173};
174
175/* SCIFB */
176static struct plat_sci_port scifb_platform_data = {
177 .mapbase = 0xe6c30000,
178 .flags = UPF_BOOT_AUTOCONF,
179 .scscr = SCSCR_RE | SCSCR_TE,
180 .scbrr_algo_id = SCBRR_ALGO_4,
181 .type = PORT_SCIFB,
182 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)),
183};
184
185static struct platform_device scifb_device = {
186 .name = "sh-sci",
187 .id = 8,
188 .dev = {
189 .platform_data = &scifb_platform_data,
190 },
191};
192
193/* CMT */
194static struct sh_timer_config cmt10_platform_data = {
195 .name = "CMT10",
196 .channel_offset = 0x10,
197 .timer_bit = 0,
198 .clockevent_rating = 125,
199 .clocksource_rating = 125,
200};
201
202static struct resource cmt10_resources[] = {
203 [0] = {
204 .name = "CMT10",
205 .start = 0xe6138010,
206 .end = 0xe613801b,
207 .flags = IORESOURCE_MEM,
208 },
209 [1] = {
210 .start = evt2irq(0x0b00),
211 .flags = IORESOURCE_IRQ,
212 },
213};
214
215static struct platform_device cmt10_device = {
216 .name = "sh_cmt",
217 .id = 10,
218 .dev = {
219 .platform_data = &cmt10_platform_data,
220 },
221 .resource = cmt10_resources,
222 .num_resources = ARRAY_SIZE(cmt10_resources),
223};
224
225static struct platform_device *r8a7740_early_devices[] __initdata = {
226 &scif0_device,
227 &scif1_device,
228 &scif2_device,
229 &scif3_device,
230 &scif4_device,
231 &scif5_device,
232 &scif6_device,
233 &scif7_device,
234 &scifb_device,
235 &cmt10_device,
236};
237
238/* I2C */
239static struct resource i2c0_resources[] = {
240 [0] = {
241 .name = "IIC0",
242 .start = 0xfff20000,
243 .end = 0xfff20425 - 1,
244 .flags = IORESOURCE_MEM,
245 },
246 [1] = {
247 .start = intcs_evt2irq(0xe00),
248 .end = intcs_evt2irq(0xe60),
249 .flags = IORESOURCE_IRQ,
250 },
251};
252
253static struct resource i2c1_resources[] = {
254 [0] = {
255 .name = "IIC1",
256 .start = 0xe6c20000,
257 .end = 0xe6c20425 - 1,
258 .flags = IORESOURCE_MEM,
259 },
260 [1] = {
261 .start = evt2irq(0x780), /* IIC1_ALI1 */
262 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
263 .flags = IORESOURCE_IRQ,
264 },
265};
266
267static struct platform_device i2c0_device = {
268 .name = "i2c-sh_mobile",
269 .id = 0,
270 .resource = i2c0_resources,
271 .num_resources = ARRAY_SIZE(i2c0_resources),
272};
273
274static struct platform_device i2c1_device = {
275 .name = "i2c-sh_mobile",
276 .id = 1,
277 .resource = i2c1_resources,
278 .num_resources = ARRAY_SIZE(i2c1_resources),
279};
280
281static struct platform_device *r8a7740_late_devices[] __initdata = {
282 &i2c0_device,
283 &i2c1_device,
284};
285
286#define ICCR 0x0004
287#define ICSTART 0x0070
288
289#define i2c_read(reg, offset) ioread8(reg + offset)
290#define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
291
292/*
293 * r8a7740 chip has lasting errata on I2C I/O pad reset.
294 * this is work-around for it.
295 */
296static void r8a7740_i2c_workaround(struct platform_device *pdev)
297{
298 struct resource *res;
299 void __iomem *reg;
300
301 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
302 if (unlikely(!res)) {
303 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
304 return;
305 }
306
307 reg = ioremap(res->start, resource_size(res));
308 if (unlikely(!reg)) {
309 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
310 return;
311 }
312
313 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
314 i2c_read(reg, ICCR); /* dummy read */
315
316 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
317 i2c_read(reg, ICSTART); /* dummy read */
318
319 mdelay(100);
320
321 i2c_write(reg, ICCR, 0x01);
322 i2c_read(reg, ICCR);
323 i2c_write(reg, ICSTART, 0x00);
324 i2c_read(reg, ICSTART);
325
326 i2c_write(reg, ICCR, 0x10);
327 mdelay(100);
328 i2c_write(reg, ICCR, 0x00);
329 mdelay(100);
330 i2c_write(reg, ICCR, 0x10);
331 mdelay(100);
332
333 iounmap(reg);
334}
335
336void __init r8a7740_add_standard_devices(void)
337{
338 /* I2C work-around */
339 r8a7740_i2c_workaround(&i2c0_device);
340 r8a7740_i2c_workaround(&i2c1_device);
341
342 platform_add_devices(r8a7740_early_devices,
343 ARRAY_SIZE(r8a7740_early_devices));
344 platform_add_devices(r8a7740_late_devices,
345 ARRAY_SIZE(r8a7740_late_devices));
346}
347
348void __init r8a7740_add_early_devices(void)
349{
350 early_platform_add_devices(r8a7740_early_devices,
351 ARRAY_SIZE(r8a7740_early_devices));
352}
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
new file mode 100644
index 000000000000..4725663bd032
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -0,0 +1,239 @@
1/*
2 * r8a7779 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/delay.h>
26#include <linux/input.h>
27#include <linux/io.h>
28#include <linux/serial_sci.h>
29#include <linux/sh_intc.h>
30#include <linux/sh_timer.h>
31#include <mach/hardware.h>
32#include <mach/r8a7779.h>
33#include <mach/common.h>
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36
37static struct plat_sci_port scif0_platform_data = {
38 .mapbase = 0xffe40000,
39 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
41 .scbrr_algo_id = SCBRR_ALGO_2,
42 .type = PORT_SCIF,
43 .irqs = { gic_spi(88), gic_spi(88),
44 gic_spi(88), gic_spi(88) },
45};
46
47static struct platform_device scif0_device = {
48 .name = "sh-sci",
49 .id = 0,
50 .dev = {
51 .platform_data = &scif0_platform_data,
52 },
53};
54
55static struct plat_sci_port scif1_platform_data = {
56 .mapbase = 0xffe41000,
57 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
58 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
59 .scbrr_algo_id = SCBRR_ALGO_2,
60 .type = PORT_SCIF,
61 .irqs = { gic_spi(89), gic_spi(89),
62 gic_spi(89), gic_spi(89) },
63};
64
65static struct platform_device scif1_device = {
66 .name = "sh-sci",
67 .id = 1,
68 .dev = {
69 .platform_data = &scif1_platform_data,
70 },
71};
72
73static struct plat_sci_port scif2_platform_data = {
74 .mapbase = 0xffe42000,
75 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
76 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
77 .scbrr_algo_id = SCBRR_ALGO_2,
78 .type = PORT_SCIF,
79 .irqs = { gic_spi(90), gic_spi(90),
80 gic_spi(90), gic_spi(90) },
81};
82
83static struct platform_device scif2_device = {
84 .name = "sh-sci",
85 .id = 2,
86 .dev = {
87 .platform_data = &scif2_platform_data,
88 },
89};
90
91static struct plat_sci_port scif3_platform_data = {
92 .mapbase = 0xffe43000,
93 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
94 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
95 .scbrr_algo_id = SCBRR_ALGO_2,
96 .type = PORT_SCIF,
97 .irqs = { gic_spi(91), gic_spi(91),
98 gic_spi(91), gic_spi(91) },
99};
100
101static struct platform_device scif3_device = {
102 .name = "sh-sci",
103 .id = 3,
104 .dev = {
105 .platform_data = &scif3_platform_data,
106 },
107};
108
109static struct plat_sci_port scif4_platform_data = {
110 .mapbase = 0xffe44000,
111 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
112 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
113 .scbrr_algo_id = SCBRR_ALGO_2,
114 .type = PORT_SCIF,
115 .irqs = { gic_spi(92), gic_spi(92),
116 gic_spi(92), gic_spi(92) },
117};
118
119static struct platform_device scif4_device = {
120 .name = "sh-sci",
121 .id = 4,
122 .dev = {
123 .platform_data = &scif4_platform_data,
124 },
125};
126
127static struct plat_sci_port scif5_platform_data = {
128 .mapbase = 0xffe45000,
129 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
130 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
131 .scbrr_algo_id = SCBRR_ALGO_2,
132 .type = PORT_SCIF,
133 .irqs = { gic_spi(93), gic_spi(93),
134 gic_spi(93), gic_spi(93) },
135};
136
137static struct platform_device scif5_device = {
138 .name = "sh-sci",
139 .id = 5,
140 .dev = {
141 .platform_data = &scif5_platform_data,
142 },
143};
144
145/* TMU */
146static struct sh_timer_config tmu00_platform_data = {
147 .name = "TMU00",
148 .channel_offset = 0x4,
149 .timer_bit = 0,
150 .clockevent_rating = 200,
151};
152
153static struct resource tmu00_resources[] = {
154 [0] = {
155 .name = "TMU00",
156 .start = 0xffd80008,
157 .end = 0xffd80013,
158 .flags = IORESOURCE_MEM,
159 },
160 [1] = {
161 .start = gic_spi(32),
162 .flags = IORESOURCE_IRQ,
163 },
164};
165
166static struct platform_device tmu00_device = {
167 .name = "sh_tmu",
168 .id = 0,
169 .dev = {
170 .platform_data = &tmu00_platform_data,
171 },
172 .resource = tmu00_resources,
173 .num_resources = ARRAY_SIZE(tmu00_resources),
174};
175
176static struct sh_timer_config tmu01_platform_data = {
177 .name = "TMU01",
178 .channel_offset = 0x10,
179 .timer_bit = 1,
180 .clocksource_rating = 200,
181};
182
183static struct resource tmu01_resources[] = {
184 [0] = {
185 .name = "TMU01",
186 .start = 0xffd80014,
187 .end = 0xffd8001f,
188 .flags = IORESOURCE_MEM,
189 },
190 [1] = {
191 .start = gic_spi(33),
192 .flags = IORESOURCE_IRQ,
193 },
194};
195
196static struct platform_device tmu01_device = {
197 .name = "sh_tmu",
198 .id = 1,
199 .dev = {
200 .platform_data = &tmu01_platform_data,
201 },
202 .resource = tmu01_resources,
203 .num_resources = ARRAY_SIZE(tmu01_resources),
204};
205
206static struct platform_device *r8a7779_early_devices[] __initdata = {
207 &scif0_device,
208 &scif1_device,
209 &scif2_device,
210 &scif3_device,
211 &scif4_device,
212 &scif5_device,
213 &tmu00_device,
214 &tmu01_device,
215};
216
217static struct platform_device *r8a7779_late_devices[] __initdata = {
218};
219
220void __init r8a7779_add_standard_devices(void)
221{
222 r8a7779_pm_init();
223
224 r8a7779_init_pm_domain(&r8a7779_sh4a);
225 r8a7779_init_pm_domain(&r8a7779_sgx);
226 r8a7779_init_pm_domain(&r8a7779_vdp1);
227 r8a7779_init_pm_domain(&r8a7779_impx3);
228
229 platform_add_devices(r8a7779_early_devices,
230 ARRAY_SIZE(r8a7779_early_devices));
231 platform_add_devices(r8a7779_late_devices,
232 ARRAY_SIZE(r8a7779_late_devices));
233}
234
235void __init r8a7779_add_early_devices(void)
236{
237 early_platform_add_devices(r8a7779_early_devices,
238 ARRAY_SIZE(r8a7779_early_devices));
239}
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index c197f9d29d04..1ea89be63e29 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -504,7 +504,7 @@ static struct resource sh7372_dmae0_resources[] = {
504 .flags = IORESOURCE_MEM, 504 .flags = IORESOURCE_MEM,
505 }, 505 },
506 { 506 {
507 /* DMA error IRQ */ 507 .name = "error_irq",
508 .start = evt2irq(0x20c0), 508 .start = evt2irq(0x20c0),
509 .end = evt2irq(0x20c0), 509 .end = evt2irq(0x20c0),
510 .flags = IORESOURCE_IRQ, 510 .flags = IORESOURCE_IRQ,
@@ -532,7 +532,7 @@ static struct resource sh7372_dmae1_resources[] = {
532 .flags = IORESOURCE_MEM, 532 .flags = IORESOURCE_MEM,
533 }, 533 },
534 { 534 {
535 /* DMA error IRQ */ 535 .name = "error_irq",
536 .start = evt2irq(0x21c0), 536 .start = evt2irq(0x21c0),
537 .end = evt2irq(0x21c0), 537 .end = evt2irq(0x21c0),
538 .flags = IORESOURCE_IRQ, 538 .flags = IORESOURCE_IRQ,
@@ -560,7 +560,7 @@ static struct resource sh7372_dmae2_resources[] = {
560 .flags = IORESOURCE_MEM, 560 .flags = IORESOURCE_MEM,
561 }, 561 },
562 { 562 {
563 /* DMA error IRQ */ 563 .name = "error_irq",
564 .start = evt2irq(0x22c0), 564 .start = evt2irq(0x22c0),
565 .end = evt2irq(0x22c0), 565 .end = evt2irq(0x22c0),
566 .flags = IORESOURCE_IRQ, 566 .flags = IORESOURCE_IRQ,
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index e46821c0a62e..20e71e5cace4 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -607,7 +607,7 @@ static struct resource sh73a0_dmae_resources[] = {
607 .flags = IORESOURCE_MEM, 607 .flags = IORESOURCE_MEM,
608 }, 608 },
609 { 609 {
610 /* DMA error IRQ */ 610 .name = "error_irq",
611 .start = gic_spi(129), 611 .start = gic_spi(129),
612 .end = gic_spi(129), 612 .end = gic_spi(129),
613 .flags = IORESOURCE_IRQ, 613 .flags = IORESOURCE_IRQ,
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
new file mode 100644
index 000000000000..cc97ef892d1b
--- /dev/null
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -0,0 +1,153 @@
1/*
2 * SMP support for R-Mobile / SH-Mobile - r8a7779 portion
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/smp.h>
23#include <linux/spinlock.h>
24#include <linux/io.h>
25#include <linux/delay.h>
26#include <mach/common.h>
27#include <mach/r8a7779.h>
28#include <asm/smp_scu.h>
29#include <asm/smp_twd.h>
30#include <asm/hardware/gic.h>
31
32#define AVECR 0xfe700040
33
34static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
35 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
36 .chan_bit = 1, /* ARM1 */
37 .isr_bit = 1, /* ARM1 */
38};
39
40static struct r8a7779_pm_ch r8a7779_ch_cpu2 = {
41 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
42 .chan_bit = 2, /* ARM2 */
43 .isr_bit = 2, /* ARM2 */
44};
45
46static struct r8a7779_pm_ch r8a7779_ch_cpu3 = {
47 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
48 .chan_bit = 3, /* ARM3 */
49 .isr_bit = 3, /* ARM3 */
50};
51
52static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = {
53 [1] = &r8a7779_ch_cpu1,
54 [2] = &r8a7779_ch_cpu2,
55 [3] = &r8a7779_ch_cpu3,
56};
57
58static void __iomem *scu_base_addr(void)
59{
60 return (void __iomem *)0xf0000000;
61}
62
63static DEFINE_SPINLOCK(scu_lock);
64static unsigned long tmp;
65
66static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
67{
68 void __iomem *scu_base = scu_base_addr();
69
70 spin_lock(&scu_lock);
71 tmp = __raw_readl(scu_base + 8);
72 tmp &= ~clr;
73 tmp |= set;
74 spin_unlock(&scu_lock);
75
76 /* disable cache coherency after releasing the lock */
77 __raw_writel(tmp, scu_base + 8);
78}
79
80unsigned int __init r8a7779_get_core_count(void)
81{
82 void __iomem *scu_base = scu_base_addr();
83
84#ifdef CONFIG_HAVE_ARM_TWD
85 /* twd_base needs to be initialized before percpu_timer_setup() */
86 twd_base = (void __iomem *)0xf0000600;
87#endif
88
89 return scu_get_core_count(scu_base);
90}
91
92int r8a7779_platform_cpu_kill(unsigned int cpu)
93{
94 struct r8a7779_pm_ch *ch = NULL;
95 int ret = -EIO;
96
97 cpu = cpu_logical_map(cpu);
98
99 /* disable cache coherency */
100 modify_scu_cpu_psr(3 << (cpu * 8), 0);
101
102 if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
103 ch = r8a7779_ch_cpu[cpu];
104
105 if (ch)
106 ret = r8a7779_sysc_power_down(ch);
107
108 return ret ? ret : 1;
109}
110
111void __cpuinit r8a7779_secondary_init(unsigned int cpu)
112{
113 gic_secondary_init(0);
114}
115
116int __cpuinit r8a7779_boot_secondary(unsigned int cpu)
117{
118 struct r8a7779_pm_ch *ch = NULL;
119 int ret = -EIO;
120
121 cpu = cpu_logical_map(cpu);
122
123 /* enable cache coherency */
124 modify_scu_cpu_psr(0, 3 << (cpu * 8));
125
126 if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
127 ch = r8a7779_ch_cpu[cpu];
128
129 if (ch)
130 ret = r8a7779_sysc_power_up(ch);
131
132 return ret;
133}
134
135void __init r8a7779_smp_prepare_cpus(void)
136{
137 int cpu = cpu_logical_map(0);
138
139 scu_enable(scu_base_addr());
140
141 /* Map the reset vector (in headsmp.S) */
142 __raw_writel(__pa(shmobile_secondary_vector), __io(AVECR));
143
144 /* enable cache coherency on CPU0 */
145 modify_scu_cpu_psr(0, 3 << (cpu * 8));
146
147 r8a7779_pm_init();
148
149 /* power off secondary CPUs */
150 r8a7779_platform_cpu_kill(1);
151 r8a7779_platform_cpu_kill(2);
152 r8a7779_platform_cpu_kill(3);
153}
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index a0f9634f6727..789bdc9e8f91 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -90,11 +90,11 @@ static struct wm8903_platform_data harmony_wm8903_pdata = {
90 .micdet_delay = 100, 90 .micdet_delay = 100,
91 .gpio_base = HARMONY_GPIO_WM8903(0), 91 .gpio_base = HARMONY_GPIO_WM8903(0),
92 .gpio_cfg = { 92 .gpio_cfg = {
93 WM8903_GPIO_NO_CONFIG,
94 WM8903_GPIO_NO_CONFIG,
95 0, 93 0,
96 WM8903_GPIO_NO_CONFIG, 94 0,
97 WM8903_GPIO_NO_CONFIG, 95 WM8903_GPIO_CONFIG_ZERO,
96 0,
97 0,
98 }, 98 },
99}; 99};
100 100
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index cfc74d46a09e..ebac65f52510 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -172,11 +172,11 @@ static struct wm8903_platform_data wm8903_pdata = {
172 .micdet_delay = 100, 172 .micdet_delay = 100,
173 .gpio_base = SEABOARD_GPIO_WM8903(0), 173 .gpio_base = SEABOARD_GPIO_WM8903(0),
174 .gpio_cfg = { 174 .gpio_cfg = {
175 WM8903_GPIO_NO_CONFIG,
176 WM8903_GPIO_NO_CONFIG,
177 0, 175 0,
178 WM8903_GPIO_NO_CONFIG, 176 0,
179 WM8903_GPIO_NO_CONFIG, 177 WM8903_GPIO_CONFIG_ZERO,
178 0,
179 0,
180 }, 180 },
181}; 181};
182 182
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index ec63c6b2b6b5..af8b63435727 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -408,7 +408,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
408 pp->res[0].flags = IORESOURCE_IO; 408 pp->res[0].flags = IORESOURCE_IO;
409 if (request_resource(&ioport_resource, &pp->res[0])) 409 if (request_resource(&ioport_resource, &pp->res[0]))
410 panic("Request PCIe IO resource failed\n"); 410 panic("Request PCIe IO resource failed\n");
411 sys->resource[0] = &pp->res[0]; 411 pci_add_resource(&sys->resources, &pp->res[0]);
412 412
413 /* 413 /*
414 * IORESOURCE_MEM 414 * IORESOURCE_MEM
@@ -427,7 +427,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
427 pp->res[1].flags = IORESOURCE_MEM; 427 pp->res[1].flags = IORESOURCE_MEM;
428 if (request_resource(&iomem_resource, &pp->res[1])) 428 if (request_resource(&iomem_resource, &pp->res[1]))
429 panic("Request PCIe Memory resource failed\n"); 429 panic("Request PCIe Memory resource failed\n");
430 sys->resource[1] = &pp->res[1]; 430 pci_add_resource(&sys->resources, &pp->res[1]);
431 431
432 /* 432 /*
433 * IORESOURCE_MEM | IORESOURCE_PREFETCH 433 * IORESOURCE_MEM | IORESOURCE_PREFETCH
@@ -446,7 +446,7 @@ static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
446 pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; 446 pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
447 if (request_resource(&iomem_resource, &pp->res[2])) 447 if (request_resource(&iomem_resource, &pp->res[2]))
448 panic("Request PCIe Prefetch Memory resource failed\n"); 448 panic("Request PCIe Prefetch Memory resource failed\n");
449 sys->resource[2] = &pp->res[2]; 449 pci_add_resource(&sys->resources, &pp->res[2]);
450 450
451 return 1; 451 return 1;
452} 452}
@@ -467,7 +467,8 @@ static struct pci_bus __init *tegra_pcie_scan_bus(int nr,
467 pp = tegra_pcie.port + nr; 467 pp = tegra_pcie.port + nr;
468 pp->root_bus_nr = sys->busnr; 468 pp->root_bus_nr = sys->busnr;
469 469
470 return pci_scan_bus(sys->busnr, &tegra_pcie_ops, sys); 470 return pci_scan_root_bus(NULL, sys->busnr, &tegra_pcie_ops, sys,
471 &sys->resources);
471} 472}
472 473
473static struct hw_pci tegra_pcie_hw __initdata = { 474static struct hw_pci tegra_pcie_hw __initdata = {
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index c898deb3ada0..90069bce23bc 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -191,7 +191,7 @@ static struct resource pre_mem = {
191 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, 191 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
192}; 192};
193 193
194static int __init pci_versatile_setup_resources(struct resource **resource) 194static int __init pci_versatile_setup_resources(struct list_head *resources)
195{ 195{
196 int ret = 0; 196 int ret = 0;
197 197
@@ -215,13 +215,13 @@ static int __init pci_versatile_setup_resources(struct resource **resource)
215 } 215 }
216 216
217 /* 217 /*
218 * bus->resource[0] is the IO resource for this bus 218 * the IO resource for this bus
219 * bus->resource[1] is the mem resource for this bus 219 * the mem resource for this bus
220 * bus->resource[2] is the prefetch mem resource for this bus 220 * the prefetch mem resource for this bus
221 */ 221 */
222 resource[0] = &io_mem; 222 pci_add_resource(resources, &io_mem);
223 resource[1] = &non_mem; 223 pci_add_resource(resources, &non_mem);
224 resource[2] = &pre_mem; 224 pci_add_resource(resources, &pre_mem);
225 225
226 goto out; 226 goto out;
227 227
@@ -250,7 +250,7 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
250 250
251 if (nr == 0) { 251 if (nr == 0) {
252 sys->mem_offset = 0; 252 sys->mem_offset = 0;
253 ret = pci_versatile_setup_resources(sys->resource); 253 ret = pci_versatile_setup_resources(&sys->resources);
254 if (ret < 0) { 254 if (ret < 0) {
255 printk("pci_versatile_setup: resources... oops?\n"); 255 printk("pci_versatile_setup: resources... oops?\n");
256 goto out; 256 goto out;
@@ -306,7 +306,8 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
306 306
307struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys) 307struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
308{ 308{
309 return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys); 309 return pci_scan_root_bus(NULL, sys->busnr, &pci_versatile_ops, sys,
310 &sys->resources);
310} 311}
311 312
312void __init pci_versatile_preinit(void) 313void __init pci_versatile_preinit(void)
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index 845549cbbb27..f4d40a27111e 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -215,16 +215,16 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
215 sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0; 215 sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0;
216 sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR; 216 sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR;
217 217
218 sys->resource[0] = &res[0]; 218 pci_add_resource(&sys->resources, &res[0]);
219 sys->resource[1] = &res[1]; 219 pci_add_resource(&sys->resources, &res[1]);
220 sys->resource[2] = NULL;
221 220
222 return 1; 221 return 1;
223} 222}
224 223
225struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys) 224struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys)
226{ 225{
227 return pci_scan_bus(sys->busnr, &iop3xx_ops, sys); 226 return pci_scan_root_bus(NULL, sys->busnr, &iop3xx_ops, sys,
227 &sys->resources);
228} 228}
229 229
230void __init iop3xx_atu_setup(void) 230void __init iop3xx_atu_setup(void)
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
deleted file mode 100644
index da4f68dbba1d..000000000000
--- a/arch/arm/plat-omap/cpu-omap.c
+++ /dev/null
@@ -1,171 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/cpu-omap.c
3 *
4 * CPU frequency scaling for OMAP
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
8 *
9 * Based on cpu-sa1110.c, Copyright (C) 2001 Russell King
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15#include <linux/types.h>
16#include <linux/kernel.h>
17#include <linux/sched.h>
18#include <linux/cpufreq.h>
19#include <linux/delay.h>
20#include <linux/init.h>
21#include <linux/err.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24
25#include <mach/hardware.h>
26#include <plat/clock.h>
27#include <asm/system.h>
28
29#define VERY_HI_RATE 900000000
30
31static struct cpufreq_frequency_table *freq_table;
32
33#ifdef CONFIG_ARCH_OMAP1
34#define MPU_CLK "mpu"
35#else
36#define MPU_CLK "virt_prcm_set"
37#endif
38
39static struct clk *mpu_clk;
40
41/* TODO: Add support for SDRAM timing changes */
42
43static int omap_verify_speed(struct cpufreq_policy *policy)
44{
45 if (freq_table)
46 return cpufreq_frequency_table_verify(policy, freq_table);
47
48 if (policy->cpu)
49 return -EINVAL;
50
51 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
52 policy->cpuinfo.max_freq);
53
54 policy->min = clk_round_rate(mpu_clk, policy->min * 1000) / 1000;
55 policy->max = clk_round_rate(mpu_clk, policy->max * 1000) / 1000;
56 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
57 policy->cpuinfo.max_freq);
58 return 0;
59}
60
61static unsigned int omap_getspeed(unsigned int cpu)
62{
63 unsigned long rate;
64
65 if (cpu)
66 return 0;
67
68 rate = clk_get_rate(mpu_clk) / 1000;
69 return rate;
70}
71
72static int omap_target(struct cpufreq_policy *policy,
73 unsigned int target_freq,
74 unsigned int relation)
75{
76 struct cpufreq_freqs freqs;
77 int ret = 0;
78
79 /* Ensure desired rate is within allowed range. Some govenors
80 * (ondemand) will just pass target_freq=0 to get the minimum. */
81 if (target_freq < policy->min)
82 target_freq = policy->min;
83 if (target_freq > policy->max)
84 target_freq = policy->max;
85
86 freqs.old = omap_getspeed(0);
87 freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000;
88 freqs.cpu = 0;
89
90 if (freqs.old == freqs.new)
91 return ret;
92
93 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
94#ifdef CONFIG_CPU_FREQ_DEBUG
95 printk(KERN_DEBUG "cpufreq-omap: transition: %u --> %u\n",
96 freqs.old, freqs.new);
97#endif
98 ret = clk_set_rate(mpu_clk, freqs.new * 1000);
99 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
100
101 return ret;
102}
103
104static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
105{
106 int result = 0;
107
108 mpu_clk = clk_get(NULL, MPU_CLK);
109 if (IS_ERR(mpu_clk))
110 return PTR_ERR(mpu_clk);
111
112 if (policy->cpu != 0)
113 return -EINVAL;
114
115 policy->cur = policy->min = policy->max = omap_getspeed(0);
116
117 clk_init_cpufreq_table(&freq_table);
118 if (freq_table) {
119 result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
120 if (!result)
121 cpufreq_frequency_table_get_attr(freq_table,
122 policy->cpu);
123 } else {
124 policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000;
125 policy->cpuinfo.max_freq = clk_round_rate(mpu_clk,
126 VERY_HI_RATE) / 1000;
127 }
128
129 /* FIXME: what's the actual transition time? */
130 policy->cpuinfo.transition_latency = 300 * 1000;
131
132 return 0;
133}
134
135static int omap_cpu_exit(struct cpufreq_policy *policy)
136{
137 clk_exit_cpufreq_table(&freq_table);
138 clk_put(mpu_clk);
139 return 0;
140}
141
142static struct freq_attr *omap_cpufreq_attr[] = {
143 &cpufreq_freq_attr_scaling_available_freqs,
144 NULL,
145};
146
147static struct cpufreq_driver omap_driver = {
148 .flags = CPUFREQ_STICKY,
149 .verify = omap_verify_speed,
150 .target = omap_target,
151 .get = omap_getspeed,
152 .init = omap_cpu_init,
153 .exit = omap_cpu_exit,
154 .name = "omap",
155 .attr = omap_cpufreq_attr,
156};
157
158static int __init omap_cpufreq_init(void)
159{
160 return cpufreq_register_driver(&omap_driver);
161}
162
163arch_initcall(omap_cpufreq_init);
164
165/*
166 * if ever we want to remove this, upon cleanup call:
167 *
168 * cpufreq_unregister_driver()
169 * cpufreq_frequency_table_put_attr()
170 */
171
diff --git a/arch/blackfin/include/asm/pci.h b/arch/blackfin/include/asm/pci.h
index 99cae2e3bac7..74352c4597d9 100644
--- a/arch/blackfin/include/asm/pci.h
+++ b/arch/blackfin/include/asm/pci.h
@@ -10,10 +10,6 @@
10#define PCIBIOS_MIN_IO 0x00001000 10#define PCIBIOS_MIN_IO 0x00001000
11#define PCIBIOS_MIN_MEM 0x10000000 11#define PCIBIOS_MIN_MEM 0x10000000
12 12
13static inline void pcibios_set_master(struct pci_dev *dev)
14{
15 /* No special bus mastering setup handling */
16}
17static inline void pcibios_penalize_isa_irq(int irq) 13static inline void pcibios_penalize_isa_irq(int irq)
18{ 14{
19 /* We don't do dynamic PCI IRQ allocation */ 15 /* We don't do dynamic PCI IRQ allocation */
diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig
index bbbf7927f238..a685910d2d5c 100644
--- a/arch/frv/Kconfig
+++ b/arch/frv/Kconfig
@@ -8,6 +8,7 @@ config FRV
8 select HAVE_GENERIC_HARDIRQS 8 select HAVE_GENERIC_HARDIRQS
9 select GENERIC_IRQ_SHOW 9 select GENERIC_IRQ_SHOW
10 select ARCH_HAVE_NMI_SAFE_CMPXCHG 10 select ARCH_HAVE_NMI_SAFE_CMPXCHG
11 select GENERIC_CPU_DEVICES
11 12
12config ZONE_DMA 13config ZONE_DMA
13 bool 14 bool
diff --git a/arch/frv/mb93090-mb00/pci-frv.c b/arch/frv/mb93090-mb00/pci-frv.c
index 6b4fb28e9f99..c28121765448 100644
--- a/arch/frv/mb93090-mb00/pci-frv.c
+++ b/arch/frv/mb93090-mb00/pci-frv.c
@@ -194,23 +194,3 @@ void __init pcibios_resource_survey(void)
194 pcibios_allocate_resources(1); 194 pcibios_allocate_resources(1);
195 pcibios_assign_resources(); 195 pcibios_assign_resources();
196} 196}
197
198/*
199 * If we set up a device for bus mastering, we need to check the latency
200 * timer as certain crappy BIOSes forget to set it properly.
201 */
202unsigned int pcibios_max_latency = 255;
203
204void pcibios_set_master(struct pci_dev *dev)
205{
206 u8 lat;
207 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
208 if (lat < 16)
209 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
210 else if (lat > pcibios_max_latency)
211 lat = pcibios_max_latency;
212 else
213 return;
214 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
215 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
216}
diff --git a/arch/frv/mb93090-mb00/pci-frv.h b/arch/frv/mb93090-mb00/pci-frv.h
index f3fe55914793..089eeba4f3bc 100644
--- a/arch/frv/mb93090-mb00/pci-frv.h
+++ b/arch/frv/mb93090-mb00/pci-frv.h
@@ -26,8 +26,6 @@ extern unsigned int __nongpreldata pci_probe;
26 26
27/* pci-frv.c */ 27/* pci-frv.c */
28 28
29extern unsigned int pcibios_max_latency;
30
31void pcibios_resource_survey(void); 29void pcibios_resource_survey(void);
32 30
33/* pci-vdk.c */ 31/* pci-vdk.c */
diff --git a/arch/frv/mb93090-mb00/pci-vdk.c b/arch/frv/mb93090-mb00/pci-vdk.c
index f8dd37e49535..6b0b82ff4419 100644
--- a/arch/frv/mb93090-mb00/pci-vdk.c
+++ b/arch/frv/mb93090-mb00/pci-vdk.c
@@ -327,11 +327,6 @@ void __init pcibios_fixup_bus(struct pci_bus *bus)
327 printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number); 327 printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number);
328#endif 328#endif
329 329
330 if (bus->number == 0) {
331 bus->resource[0] = &pci_ioport_resource;
332 bus->resource[1] = &pci_iomem_resource;
333 }
334
335 pci_read_bridge_bases(bus); 330 pci_read_bridge_bases(bus);
336 331
337 if (bus->number == 0) { 332 if (bus->number == 0) {
@@ -357,6 +352,7 @@ void __init pcibios_fixup_bus(struct pci_bus *bus)
357int __init pcibios_init(void) 352int __init pcibios_init(void)
358{ 353{
359 struct pci_ops *dir = NULL; 354 struct pci_ops *dir = NULL;
355 LIST_HEAD(resources);
360 356
361 if (!mb93090_mb00_detected) 357 if (!mb93090_mb00_detected)
362 return -ENXIO; 358 return -ENXIO;
@@ -420,7 +416,10 @@ int __init pcibios_init(void)
420 } 416 }
421 417
422 printk("PCI: Probing PCI hardware\n"); 418 printk("PCI: Probing PCI hardware\n");
423 pci_root_bus = pci_scan_bus(0, pci_root_ops, NULL); 419 pci_add_resource(&resources, &pci_ioport_resource);
420 pci_add_resource(&resources, &pci_iomem_resource);
421 pci_root_bus = pci_scan_root_bus(NULL, 0, pci_root_ops, NULL,
422 &resources);
424 423
425 pcibios_irq_init(); 424 pcibios_irq_init();
426 pcibios_fixup_peer_bridges(); 425 pcibios_fixup_peer_bridges();
diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig
index d1f377f5d3b6..56e890df5053 100644
--- a/arch/h8300/Kconfig
+++ b/arch/h8300/Kconfig
@@ -4,6 +4,7 @@ config H8300
4 select HAVE_IDE 4 select HAVE_IDE
5 select HAVE_GENERIC_HARDIRQS 5 select HAVE_GENERIC_HARDIRQS
6 select GENERIC_IRQ_SHOW 6 select GENERIC_IRQ_SHOW
7 select GENERIC_CPU_DEVICES
7 8
8config SYMBOL_PREFIX 9config SYMBOL_PREFIX
9 string 10 string
diff --git a/arch/h8300/include/asm/pci.h b/arch/h8300/include/asm/pci.h
index cc9762091c0a..0b2acaa3dd84 100644
--- a/arch/h8300/include/asm/pci.h
+++ b/arch/h8300/include/asm/pci.h
@@ -9,11 +9,6 @@
9 9
10#define pcibios_assign_all_busses() 0 10#define pcibios_assign_all_busses() 0
11 11
12static inline void pcibios_set_master(struct pci_dev *dev)
13{
14 /* No special bus mastering setup handling */
15}
16
17static inline void pcibios_penalize_isa_irq(int irq, int active) 12static inline void pcibios_penalize_isa_irq(int irq, int active)
18{ 13{
19 /* We don't do dynamic PCI IRQ allocation */ 14 /* We don't do dynamic PCI IRQ allocation */
diff --git a/arch/ia64/include/asm/pci.h b/arch/ia64/include/asm/pci.h
index 127dd7be346a..279b38ae74aa 100644
--- a/arch/ia64/include/asm/pci.h
+++ b/arch/ia64/include/asm/pci.h
@@ -43,12 +43,6 @@ extern unsigned long ia64_max_iommu_merge_mask;
43#define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL) 43#define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL)
44 44
45static inline void 45static inline void
46pcibios_set_master (struct pci_dev *dev)
47{
48 /* No special bus mastering setup handling */
49}
50
51static inline void
52pcibios_penalize_isa_irq (int irq, int active) 46pcibios_penalize_isa_irq (int irq, int active)
53{ 47{
54 /* We don't do dynamic PCI IRQ allocation */ 48 /* We don't do dynamic PCI IRQ allocation */
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index 2c27714d7b78..f82f5d4b65fd 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -134,6 +134,7 @@ alloc_pci_controller (int seg)
134struct pci_root_info { 134struct pci_root_info {
135 struct acpi_device *bridge; 135 struct acpi_device *bridge;
136 struct pci_controller *controller; 136 struct pci_controller *controller;
137 struct list_head resources;
137 char *name; 138 char *name;
138}; 139};
139 140
@@ -315,24 +316,13 @@ static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
315 &window->resource); 316 &window->resource);
316 } 317 }
317 318
318 return AE_OK; 319 /* HP's firmware has a hack to work around a Windows bug.
319} 320 * Ignore these tiny memory ranges */
320 321 if (!((window->resource.flags & IORESOURCE_MEM) &&
321static void __devinit 322 (window->resource.end - window->resource.start < 16)))
322pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl) 323 pci_add_resource(&info->resources, &window->resource);
323{
324 int i;
325 324
326 pci_bus_remove_resources(bus); 325 return AE_OK;
327 for (i = 0; i < ctrl->windows; i++) {
328 struct resource *res = &ctrl->window[i].resource;
329 /* HP's firmware has a hack to work around a Windows bug.
330 * Ignore these tiny memory ranges */
331 if ((res->flags & IORESOURCE_MEM) &&
332 (res->end - res->start < 16))
333 continue;
334 pci_bus_add_resource(bus, res, 0);
335 }
336} 326}
337 327
338struct pci_bus * __devinit 328struct pci_bus * __devinit
@@ -343,6 +333,7 @@ pci_acpi_scan_root(struct acpi_pci_root *root)
343 int bus = root->secondary.start; 333 int bus = root->secondary.start;
344 struct pci_controller *controller; 334 struct pci_controller *controller;
345 unsigned int windows = 0; 335 unsigned int windows = 0;
336 struct pci_root_info info;
346 struct pci_bus *pbus; 337 struct pci_bus *pbus;
347 char *name; 338 char *name;
348 int pxm; 339 int pxm;
@@ -359,11 +350,10 @@ pci_acpi_scan_root(struct acpi_pci_root *root)
359 controller->node = pxm_to_node(pxm); 350 controller->node = pxm_to_node(pxm);
360#endif 351#endif
361 352
353 INIT_LIST_HEAD(&info.resources);
362 acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, 354 acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
363 &windows); 355 &windows);
364 if (windows) { 356 if (windows) {
365 struct pci_root_info info;
366
367 controller->window = 357 controller->window =
368 kmalloc_node(sizeof(*controller->window) * windows, 358 kmalloc_node(sizeof(*controller->window) * windows,
369 GFP_KERNEL, controller->node); 359 GFP_KERNEL, controller->node);
@@ -387,8 +377,14 @@ pci_acpi_scan_root(struct acpi_pci_root *root)
387 * should handle the case here, but it appears that IA64 hasn't 377 * should handle the case here, but it appears that IA64 hasn't
388 * such quirk. So we just ignore the case now. 378 * such quirk. So we just ignore the case now.
389 */ 379 */
390 pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller); 380 pbus = pci_create_root_bus(NULL, bus, &pci_root_ops, controller,
381 &info.resources);
382 if (!pbus) {
383 pci_free_resource_list(&info.resources);
384 return NULL;
385 }
391 386
387 pbus->subordinate = pci_scan_child_bus(pbus);
392 return pbus; 388 return pbus;
393 389
394out3: 390out3:
@@ -504,14 +500,15 @@ pcibios_fixup_bus (struct pci_bus *b)
504 if (b->self) { 500 if (b->self) {
505 pci_read_bridge_bases(b); 501 pci_read_bridge_bases(b);
506 pcibios_fixup_bridge_resources(b->self); 502 pcibios_fixup_bridge_resources(b->self);
507 } else {
508 pcibios_setup_root_windows(b, b->sysdata);
509 } 503 }
510 list_for_each_entry(dev, &b->devices, bus_list) 504 list_for_each_entry(dev, &b->devices, bus_list)
511 pcibios_fixup_device_resources(dev); 505 pcibios_fixup_device_resources(dev);
512 platform_pci_fixup_bus(b); 506 platform_pci_fixup_bus(b);
507}
513 508
514 return; 509void pcibios_set_master (struct pci_dev *dev)
510{
511 /* No special bus mastering setup handling */
515} 512}
516 513
517void __devinit 514void __devinit
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 99c363617f27..ae413d4a8bb7 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -6,6 +6,7 @@ config M68K
6 select HAVE_GENERIC_HARDIRQS 6 select HAVE_GENERIC_HARDIRQS
7 select GENERIC_IRQ_SHOW 7 select GENERIC_IRQ_SHOW
8 select ARCH_HAVE_NMI_SAFE_CMPXCHG if RMW_INSNS 8 select ARCH_HAVE_NMI_SAFE_CMPXCHG if RMW_INSNS
9 select GENERIC_CPU_DEVICES
9 10
10config RWSEM_GENERIC_SPINLOCK 11config RWSEM_GENERIC_SPINLOCK
11 bool 12 bool
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index f0eead74fff6..74f23a460ba2 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -18,6 +18,7 @@ config MICROBLAZE
18 select GENERIC_IRQ_PROBE 18 select GENERIC_IRQ_PROBE
19 select GENERIC_IRQ_SHOW 19 select GENERIC_IRQ_SHOW
20 select GENERIC_PCI_IOMAP 20 select GENERIC_PCI_IOMAP
21 select GENERIC_CPU_DEVICES
21 22
22config SWAP 23config SWAP
23 def_bool n 24 def_bool n
diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h
index 32764cd077c6..e9834b2991d0 100644
--- a/arch/microblaze/include/asm/pci-bridge.h
+++ b/arch/microblaze/include/asm/pci-bridge.h
@@ -140,7 +140,6 @@ extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
140/* Allocate & free a PCI host bridge structure */ 140/* Allocate & free a PCI host bridge structure */
141extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); 141extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
142extern void pcibios_free_controller(struct pci_controller *phb); 142extern void pcibios_free_controller(struct pci_controller *phb);
143extern void pcibios_setup_phb_resources(struct pci_controller *hose);
144 143
145#endif /* __KERNEL__ */ 144#endif /* __KERNEL__ */
146#endif /* _ASM_MICROBLAZE_PCI_BRIDGE_H */ 145#endif /* _ASM_MICROBLAZE_PCI_BRIDGE_H */
diff --git a/arch/microblaze/include/asm/pci.h b/arch/microblaze/include/asm/pci.h
index 1dd9d6b1e275..033137628e8a 100644
--- a/arch/microblaze/include/asm/pci.h
+++ b/arch/microblaze/include/asm/pci.h
@@ -42,11 +42,6 @@ struct pci_dev;
42 */ 42 */
43#define pcibios_assign_all_busses() 0 43#define pcibios_assign_all_busses() 0
44 44
45static inline void pcibios_set_master(struct pci_dev *dev)
46{
47 /* No special bus mastering setup handling */
48}
49
50static inline void pcibios_penalize_isa_irq(int irq, int active) 45static inline void pcibios_penalize_isa_irq(int irq, int active)
51{ 46{
52 /* We don't do dynamic PCI IRQ allocation */ 47 /* We don't do dynamic PCI IRQ allocation */
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index 0d71b2ed8107..85f2ac1230a8 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -190,6 +190,11 @@ int pcibios_add_platform_entries(struct pci_dev *pdev)
190 return device_create_file(&pdev->dev, &dev_attr_devspec); 190 return device_create_file(&pdev->dev, &dev_attr_devspec);
191} 191}
192 192
193void pcibios_set_master(struct pci_dev *dev)
194{
195 /* No special bus mastering setup handling */
196}
197
193char __devinit *pcibios_setup(char *str) 198char __devinit *pcibios_setup(char *str)
194{ 199{
195 return str; 200 return str;
@@ -1019,7 +1024,6 @@ static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
1019 struct pci_dev *dev = bus->self; 1024 struct pci_dev *dev = bus->self;
1020 1025
1021 pci_bus_for_each_resource(bus, res, i) { 1026 pci_bus_for_each_resource(bus, res, i) {
1022 res = bus->resource[i];
1023 if (!res) 1027 if (!res)
1024 continue; 1028 continue;
1025 if (!res->flags) 1029 if (!res->flags)
@@ -1219,7 +1223,6 @@ void pcibios_allocate_bus_resources(struct pci_bus *bus)
1219 pci_domain_nr(bus), bus->number); 1223 pci_domain_nr(bus), bus->number);
1220 1224
1221 pci_bus_for_each_resource(bus, res, i) { 1225 pci_bus_for_each_resource(bus, res, i) {
1222 res = bus->resource[i];
1223 if (!res || !res->flags 1226 if (!res || !res->flags
1224 || res->start > res->end || res->parent) 1227 || res->start > res->end || res->parent)
1225 continue; 1228 continue;
@@ -1510,14 +1513,18 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
1510 return pci_enable_resources(dev, mask); 1513 return pci_enable_resources(dev, mask);
1511} 1514}
1512 1515
1513void __devinit pcibios_setup_phb_resources(struct pci_controller *hose) 1516static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, struct list_head *resources)
1514{ 1517{
1515 struct pci_bus *bus = hose->bus;
1516 struct resource *res; 1518 struct resource *res;
1517 int i; 1519 int i;
1518 1520
1519 /* Hookup PHB IO resource */ 1521 /* Hookup PHB IO resource */
1520 bus->resource[0] = res = &hose->io_resource; 1522 res = &hose->io_resource;
1523
1524 /* Fixup IO space offset */
1525 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1526 res->start = (res->start + io_offset) & 0xffffffffu;
1527 res->end = (res->end + io_offset) & 0xffffffffu;
1521 1528
1522 if (!res->flags) { 1529 if (!res->flags) {
1523 printk(KERN_WARNING "PCI: I/O resource not set for host" 1530 printk(KERN_WARNING "PCI: I/O resource not set for host"
@@ -1528,6 +1535,7 @@ void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
1528 res->end = res->start + IO_SPACE_LIMIT; 1535 res->end = res->start + IO_SPACE_LIMIT;
1529 res->flags = IORESOURCE_IO; 1536 res->flags = IORESOURCE_IO;
1530 } 1537 }
1538 pci_add_resource(resources, res);
1531 1539
1532 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", 1540 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1533 (unsigned long long)res->start, 1541 (unsigned long long)res->start,
@@ -1550,7 +1558,7 @@ void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
1550 res->flags = IORESOURCE_MEM; 1558 res->flags = IORESOURCE_MEM;
1551 1559
1552 } 1560 }
1553 bus->resource[i+1] = res; 1561 pci_add_resource(resources, res);
1554 1562
1555 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", 1563 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1556 i, (unsigned long long)res->start, 1564 i, (unsigned long long)res->start,
@@ -1573,34 +1581,27 @@ struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1573 1581
1574static void __devinit pcibios_scan_phb(struct pci_controller *hose) 1582static void __devinit pcibios_scan_phb(struct pci_controller *hose)
1575{ 1583{
1584 LIST_HEAD(resources);
1576 struct pci_bus *bus; 1585 struct pci_bus *bus;
1577 struct device_node *node = hose->dn; 1586 struct device_node *node = hose->dn;
1578 unsigned long io_offset;
1579 struct resource *res = &hose->io_resource;
1580 1587
1581 pr_debug("PCI: Scanning PHB %s\n", 1588 pr_debug("PCI: Scanning PHB %s\n",
1582 node ? node->full_name : "<NO NAME>"); 1589 node ? node->full_name : "<NO NAME>");
1583 1590
1584 /* Create an empty bus for the toplevel */ 1591 pcibios_setup_phb_resources(hose, &resources);
1585 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose); 1592
1593 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
1594 hose->ops, hose, &resources);
1586 if (bus == NULL) { 1595 if (bus == NULL) {
1587 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n", 1596 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
1588 hose->global_number); 1597 hose->global_number);
1598 pci_free_resource_list(&resources);
1589 return; 1599 return;
1590 } 1600 }
1591 bus->secondary = hose->first_busno; 1601 bus->secondary = hose->first_busno;
1592 hose->bus = bus; 1602 hose->bus = bus;
1593 1603
1594 /* Fixup IO space offset */ 1604 hose->last_busno = bus->subordinate;
1595 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1596 res->start = (res->start + io_offset) & 0xffffffffu;
1597 res->end = (res->end + io_offset) & 0xffffffffu;
1598
1599 /* Wire up PHB bus resources */
1600 pcibios_setup_phb_resources(hose);
1601
1602 /* Scan children */
1603 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
1604} 1605}
1605 1606
1606static int __init pcibios_init(void) 1607static int __init pcibios_init(void)
@@ -1614,8 +1615,6 @@ static int __init pcibios_init(void)
1614 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { 1615 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1615 hose->last_busno = 0xff; 1616 hose->last_busno = 0xff;
1616 pcibios_scan_phb(hose); 1617 pcibios_scan_phb(hose);
1617 printk(KERN_INFO "calling pci_bus_add_devices()\n");
1618 pci_bus_add_devices(hose->bus);
1619 if (next_busno <= hose->last_busno) 1618 if (next_busno <= hose->last_busno)
1620 next_busno = hose->last_busno + 1; 1619 next_busno = hose->last_busno + 1;
1621 } 1620 }
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 41af7fa2887b..fa8e378413b1 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -81,6 +81,7 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose)
81{ 81{
82 static int next_busno; 82 static int next_busno;
83 static int need_domain_info; 83 static int need_domain_info;
84 LIST_HEAD(resources);
84 struct pci_bus *bus; 85 struct pci_bus *bus;
85 86
86 if (!hose->iommu) 87 if (!hose->iommu)
@@ -89,7 +90,13 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose)
89 if (hose->get_busno && pci_probe_only) 90 if (hose->get_busno && pci_probe_only)
90 next_busno = (*hose->get_busno)(); 91 next_busno = (*hose->get_busno)();
91 92
92 bus = pci_scan_bus(next_busno, hose->pci_ops, hose); 93 pci_add_resource(&resources, hose->mem_resource);
94 pci_add_resource(&resources, hose->io_resource);
95 bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
96 &resources);
97 if (!bus)
98 pci_free_resource_list(&resources);
99
93 hose->bus = bus; 100 hose->bus = bus;
94 101
95 need_domain_info = need_domain_info || hose->index; 102 need_domain_info = need_domain_info || hose->index;
@@ -205,27 +212,6 @@ static int pcibios_enable_resources(struct pci_dev *dev, int mask)
205 return 0; 212 return 0;
206} 213}
207 214
208/*
209 * If we set up a device for bus mastering, we need to check the latency
210 * timer as certain crappy BIOSes forget to set it properly.
211 */
212static unsigned int pcibios_max_latency = 255;
213
214void pcibios_set_master(struct pci_dev *dev)
215{
216 u8 lat;
217 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
218 if (lat < 16)
219 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
220 else if (lat > pcibios_max_latency)
221 lat = pcibios_max_latency;
222 else
223 return;
224 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
225 pci_name(dev), lat);
226 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
227}
228
229unsigned int pcibios_assign_all_busses(void) 215unsigned int pcibios_assign_all_busses(void)
230{ 216{
231 return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0; 217 return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
@@ -266,15 +252,11 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
266{ 252{
267 /* Propagate hose info into the subordinate devices. */ 253 /* Propagate hose info into the subordinate devices. */
268 254
269 struct pci_controller *hose = bus->sysdata;
270 struct list_head *ln; 255 struct list_head *ln;
271 struct pci_dev *dev = bus->self; 256 struct pci_dev *dev = bus->self;
272 257
273 if (!dev) { 258 if (pci_probe_only && dev &&
274 bus->resource[0] = hose->io_resource; 259 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
275 bus->resource[1] = hose->mem_resource;
276 } else if (pci_probe_only &&
277 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
278 pci_read_bridge_bases(bus); 260 pci_read_bridge_bases(bus);
279 pcibios_fixup_device_resources(dev, bus); 261 pcibios_fixup_device_resources(dev, bus);
280 } 262 }
diff --git a/arch/mn10300/unit-asb2305/pci-asb2305.c b/arch/mn10300/unit-asb2305/pci-asb2305.c
index 8e6763e6f250..c4e2e79281e8 100644
--- a/arch/mn10300/unit-asb2305/pci-asb2305.c
+++ b/arch/mn10300/unit-asb2305/pci-asb2305.c
@@ -213,28 +213,6 @@ void __init pcibios_resource_survey(void)
213 pcibios_allocate_resources(1); 213 pcibios_allocate_resources(1);
214} 214}
215 215
216/*
217 * If we set up a device for bus mastering, we need to check the latency
218 * timer as certain crappy BIOSes forget to set it properly.
219 */
220unsigned int pcibios_max_latency = 255;
221
222void pcibios_set_master(struct pci_dev *dev)
223{
224 u8 lat;
225
226 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
227
228 if (lat < 16)
229 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
230 else if (lat > pcibios_max_latency)
231 lat = pcibios_max_latency;
232 else
233 return;
234
235 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
236}
237
238int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 216int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
239 enum pci_mmap_state mmap_state, int write_combine) 217 enum pci_mmap_state mmap_state, int write_combine)
240{ 218{
diff --git a/arch/mn10300/unit-asb2305/pci-asb2305.h b/arch/mn10300/unit-asb2305/pci-asb2305.h
index c3fa294b6e28..1194fe486b01 100644
--- a/arch/mn10300/unit-asb2305/pci-asb2305.h
+++ b/arch/mn10300/unit-asb2305/pci-asb2305.h
@@ -31,8 +31,6 @@ extern unsigned int pci_probe;
31 31
32/* pci-asb2305.c */ 32/* pci-asb2305.c */
33 33
34extern unsigned int pcibios_max_latency;
35
36extern void pcibios_resource_survey(void); 34extern void pcibios_resource_survey(void);
37 35
38/* pci.c */ 36/* pci.c */
diff --git a/arch/mn10300/unit-asb2305/pci.c b/arch/mn10300/unit-asb2305/pci.c
index a4954fe82094..a7c5f08ca9f5 100644
--- a/arch/mn10300/unit-asb2305/pci.c
+++ b/arch/mn10300/unit-asb2305/pci.c
@@ -380,11 +380,6 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
380{ 380{
381 struct pci_dev *dev; 381 struct pci_dev *dev;
382 382
383 if (bus->number == 0) {
384 bus->resource[0] = &pci_ioport_resource;
385 bus->resource[1] = &pci_iomem_resource;
386 }
387
388 if (bus->self) { 383 if (bus->self) {
389 pci_read_bridge_bases(bus); 384 pci_read_bridge_bases(bus);
390 pcibios_fixup_device_resources(bus->self); 385 pcibios_fixup_device_resources(bus->self);
@@ -402,6 +397,8 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
402 */ 397 */
403static int __init pcibios_init(void) 398static int __init pcibios_init(void)
404{ 399{
400 LIST_HEAD(resources);
401
405 ioport_resource.start = 0xA0000000; 402 ioport_resource.start = 0xA0000000;
406 ioport_resource.end = 0xDFFFFFFF; 403 ioport_resource.end = 0xDFFFFFFF;
407 iomem_resource.start = 0xA0000000; 404 iomem_resource.start = 0xA0000000;
@@ -423,7 +420,10 @@ static int __init pcibios_init(void)
423 printk(KERN_INFO "PCI: Probing PCI hardware [mempage %08x]\n", 420 printk(KERN_INFO "PCI: Probing PCI hardware [mempage %08x]\n",
424 MEM_PAGING_REG); 421 MEM_PAGING_REG);
425 422
426 pci_root_bus = pci_scan_bus(0, &pci_direct_ampci, NULL); 423 pci_add_resource(&resources, &pci_ioport_resource);
424 pci_add_resource(&resources, &pci_iomem_resource);
425 pci_root_bus = pci_scan_root_bus(NULL, 0, &pci_direct_ampci, NULL,
426 &resources);
427 427
428 pcibios_irq_init(); 428 pcibios_irq_init();
429 pcibios_fixup_irqs(); 429 pcibios_fixup_irqs();
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 081a54f1a93d..bc428b5f126c 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -15,6 +15,7 @@ config OPENRISC
15 select GENERIC_IRQ_PROBE 15 select GENERIC_IRQ_PROBE
16 select GENERIC_IRQ_SHOW 16 select GENERIC_IRQ_SHOW
17 select GENERIC_IOMAP 17 select GENERIC_IOMAP
18 select GENERIC_CPU_DEVICES
18 19
19config MMU 20config MMU
20 def_bool y 21 def_bool y
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index 882b6aa6c857..5d487657322e 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -226,7 +226,6 @@ extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
226/* Allocate & free a PCI host bridge structure */ 226/* Allocate & free a PCI host bridge structure */
227extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); 227extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
228extern void pcibios_free_controller(struct pci_controller *phb); 228extern void pcibios_free_controller(struct pci_controller *phb);
229extern void pcibios_setup_phb_resources(struct pci_controller *hose);
230 229
231#ifdef CONFIG_PCI 230#ifdef CONFIG_PCI
232extern int pcibios_vaddr_is_ioport(void __iomem *address); 231extern int pcibios_vaddr_is_ioport(void __iomem *address);
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
index 1c92013466e3..f54b3d26ce9d 100644
--- a/arch/powerpc/include/asm/pci.h
+++ b/arch/powerpc/include/asm/pci.h
@@ -46,11 +46,6 @@ struct pci_dev;
46#define pcibios_assign_all_busses() \ 46#define pcibios_assign_all_busses() \
47 (pci_has_flag(PCI_REASSIGN_ALL_BUS)) 47 (pci_has_flag(PCI_REASSIGN_ALL_BUS))
48 48
49static inline void pcibios_set_master(struct pci_dev *dev)
50{
51 /* No special bus mastering setup handling */
52}
53
54static inline void pcibios_penalize_isa_irq(int irq, int active) 49static inline void pcibios_penalize_isa_irq(int irq, int active)
55{ 50{
56 /* We don't do dynamic PCI IRQ allocation */ 51 /* We don't do dynamic PCI IRQ allocation */
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index fa4a573d6716..cce98d76e905 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -1131,6 +1131,11 @@ void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
1131 } 1131 }
1132} 1132}
1133 1133
1134void pcibios_set_master(struct pci_dev *dev)
1135{
1136 /* No special bus mastering setup handling */
1137}
1138
1134void __devinit pcibios_fixup_bus(struct pci_bus *bus) 1139void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1135{ 1140{
1136 /* When called from the generic PCI probe, read PCI<->PCI bridge 1141 /* When called from the generic PCI probe, read PCI<->PCI bridge
@@ -1560,14 +1565,13 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
1560 return pci_enable_resources(dev, mask); 1565 return pci_enable_resources(dev, mask);
1561} 1566}
1562 1567
1563void __devinit pcibios_setup_phb_resources(struct pci_controller *hose) 1568static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, struct list_head *resources)
1564{ 1569{
1565 struct pci_bus *bus = hose->bus;
1566 struct resource *res; 1570 struct resource *res;
1567 int i; 1571 int i;
1568 1572
1569 /* Hookup PHB IO resource */ 1573 /* Hookup PHB IO resource */
1570 bus->resource[0] = res = &hose->io_resource; 1574 res = &hose->io_resource;
1571 1575
1572 if (!res->flags) { 1576 if (!res->flags) {
1573 printk(KERN_WARNING "PCI: I/O resource not set for host" 1577 printk(KERN_WARNING "PCI: I/O resource not set for host"
@@ -1585,6 +1589,7 @@ void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
1585 (unsigned long long)res->start, 1589 (unsigned long long)res->start,
1586 (unsigned long long)res->end, 1590 (unsigned long long)res->end,
1587 (unsigned long)res->flags); 1591 (unsigned long)res->flags);
1592 pci_add_resource(resources, res);
1588 1593
1589 /* Hookup PHB Memory resources */ 1594 /* Hookup PHB Memory resources */
1590 for (i = 0; i < 3; ++i) { 1595 for (i = 0; i < 3; ++i) {
@@ -1602,12 +1607,12 @@ void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
1602 res->flags = IORESOURCE_MEM; 1607 res->flags = IORESOURCE_MEM;
1603#endif /* CONFIG_PPC32 */ 1608#endif /* CONFIG_PPC32 */
1604 } 1609 }
1605 bus->resource[i+1] = res;
1606 1610
1607 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i, 1611 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i,
1608 (unsigned long long)res->start, 1612 (unsigned long long)res->start,
1609 (unsigned long long)res->end, 1613 (unsigned long long)res->end,
1610 (unsigned long)res->flags); 1614 (unsigned long)res->flags);
1615 pci_add_resource(resources, res);
1611 } 1616 }
1612 1617
1613 pr_debug("PCI: PHB MEM offset = %016llx\n", 1618 pr_debug("PCI: PHB MEM offset = %016llx\n",
@@ -1701,6 +1706,7 @@ struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1701 */ 1706 */
1702void __devinit pcibios_scan_phb(struct pci_controller *hose) 1707void __devinit pcibios_scan_phb(struct pci_controller *hose)
1703{ 1708{
1709 LIST_HEAD(resources);
1704 struct pci_bus *bus; 1710 struct pci_bus *bus;
1705 struct device_node *node = hose->dn; 1711 struct device_node *node = hose->dn;
1706 int mode; 1712 int mode;
@@ -1708,22 +1714,24 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose)
1708 pr_debug("PCI: Scanning PHB %s\n", 1714 pr_debug("PCI: Scanning PHB %s\n",
1709 node ? node->full_name : "<NO NAME>"); 1715 node ? node->full_name : "<NO NAME>");
1710 1716
1717 /* Get some IO space for the new PHB */
1718 pcibios_setup_phb_io_space(hose);
1719
1720 /* Wire up PHB bus resources */
1721 pcibios_setup_phb_resources(hose, &resources);
1722
1711 /* Create an empty bus for the toplevel */ 1723 /* Create an empty bus for the toplevel */
1712 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose); 1724 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1725 hose->ops, hose, &resources);
1713 if (bus == NULL) { 1726 if (bus == NULL) {
1714 pr_err("Failed to create bus for PCI domain %04x\n", 1727 pr_err("Failed to create bus for PCI domain %04x\n",
1715 hose->global_number); 1728 hose->global_number);
1729 pci_free_resource_list(&resources);
1716 return; 1730 return;
1717 } 1731 }
1718 bus->secondary = hose->first_busno; 1732 bus->secondary = hose->first_busno;
1719 hose->bus = bus; 1733 hose->bus = bus;
1720 1734
1721 /* Get some IO space for the new PHB */
1722 pcibios_setup_phb_io_space(hose);
1723
1724 /* Wire up PHB bus resources */
1725 pcibios_setup_phb_resources(hose);
1726
1727 /* Get probe mode and perform scan */ 1735 /* Get probe mode and perform scan */
1728 mode = PCI_PROBE_NORMAL; 1736 mode = PCI_PROBE_NORMAL;
1729 if (node && ppc_md.pci_probe_mode) 1737 if (node && ppc_md.pci_probe_mode)
diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c
index bcf4bf9e72d9..3318d39b7d4c 100644
--- a/arch/powerpc/kernel/pci_64.c
+++ b/arch/powerpc/kernel/pci_64.c
@@ -131,30 +131,13 @@ EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
131 131
132#endif /* CONFIG_HOTPLUG */ 132#endif /* CONFIG_HOTPLUG */
133 133
134int __devinit pcibios_map_io_space(struct pci_bus *bus) 134static int __devinit pcibios_map_phb_io_space(struct pci_controller *hose)
135{ 135{
136 struct vm_struct *area; 136 struct vm_struct *area;
137 unsigned long phys_page; 137 unsigned long phys_page;
138 unsigned long size_page; 138 unsigned long size_page;
139 unsigned long io_virt_offset; 139 unsigned long io_virt_offset;
140 struct pci_controller *hose;
141
142 WARN_ON(bus == NULL);
143
144 /* If this not a PHB, nothing to do, page tables still exist and
145 * thus HPTEs will be faulted in when needed
146 */
147 if (bus->self) {
148 pr_debug("IO mapping for PCI-PCI bridge %s\n",
149 pci_name(bus->self));
150 pr_debug(" virt=0x%016llx...0x%016llx\n",
151 bus->resource[0]->start + _IO_BASE,
152 bus->resource[0]->end + _IO_BASE);
153 return 0;
154 }
155 140
156 /* Get the host bridge */
157 hose = pci_bus_to_host(bus);
158 phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE); 141 phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
159 size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE); 142 size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);
160 143
@@ -198,11 +181,30 @@ int __devinit pcibios_map_io_space(struct pci_bus *bus)
198 181
199 return 0; 182 return 0;
200} 183}
184
185int __devinit pcibios_map_io_space(struct pci_bus *bus)
186{
187 WARN_ON(bus == NULL);
188
189 /* If this not a PHB, nothing to do, page tables still exist and
190 * thus HPTEs will be faulted in when needed
191 */
192 if (bus->self) {
193 pr_debug("IO mapping for PCI-PCI bridge %s\n",
194 pci_name(bus->self));
195 pr_debug(" virt=0x%016llx...0x%016llx\n",
196 bus->resource[0]->start + _IO_BASE,
197 bus->resource[0]->end + _IO_BASE);
198 return 0;
199 }
200
201 return pcibios_map_phb_io_space(pci_bus_to_host(bus));
202}
201EXPORT_SYMBOL_GPL(pcibios_map_io_space); 203EXPORT_SYMBOL_GPL(pcibios_map_io_space);
202 204
203void __devinit pcibios_setup_phb_io_space(struct pci_controller *hose) 205void __devinit pcibios_setup_phb_io_space(struct pci_controller *hose)
204{ 206{
205 pcibios_map_io_space(hose->bus); 207 pcibios_map_phb_io_space(hose);
206} 208}
207 209
208#define IOBASE_BRIDGE_NUMBER 0 210#define IOBASE_BRIDGE_NUMBER 0
diff --git a/arch/score/Kconfig b/arch/score/Kconfig
index 3df65d39abc1..4b285779ac05 100644
--- a/arch/score/Kconfig
+++ b/arch/score/Kconfig
@@ -8,6 +8,7 @@ config SCORE
8 select HAVE_MEMBLOCK 8 select HAVE_MEMBLOCK
9 select HAVE_MEMBLOCK_NODE_MAP 9 select HAVE_MEMBLOCK_NODE_MAP
10 select ARCH_DISCARD_MEMBLOCK 10 select ARCH_DISCARD_MEMBLOCK
11 select GENERIC_CPU_DEVICES
11 12
12choice 13choice
13 prompt "System type" 14 prompt "System type"
diff --git a/arch/sh/boards/board-magicpanelr2.c b/arch/sh/boards/board-magicpanelr2.c
index 93f5039099b7..b2ca1d9948fb 100644
--- a/arch/sh/boards/board-magicpanelr2.c
+++ b/arch/sh/boards/board-magicpanelr2.c
@@ -25,9 +25,6 @@
25 25
26#define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL) 26#define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL)
27 27
28/* Prefer cmdline over RedBoot */
29static const char *probes[] = { "cmdlinepart", "RedBoot", NULL };
30
31/* Wait until reset finished. Timeout is 100ms. */ 28/* Wait until reset finished. Timeout is 100ms. */
32static int __init ethernet_reset_finished(void) 29static int __init ethernet_reset_finished(void)
33{ 30{
@@ -293,8 +290,6 @@ static struct platform_device heartbeat_device = {
293 .resource = heartbeat_resources, 290 .resource = heartbeat_resources,
294}; 291};
295 292
296static struct mtd_partition *parsed_partitions;
297
298static struct mtd_partition mpr2_partitions[] = { 293static struct mtd_partition mpr2_partitions[] = {
299 /* Reserved for bootloader, read-only */ 294 /* Reserved for bootloader, read-only */
300 { 295 {
@@ -318,6 +313,8 @@ static struct mtd_partition mpr2_partitions[] = {
318}; 313};
319 314
320static struct physmap_flash_data flash_data = { 315static struct physmap_flash_data flash_data = {
316 .parts = mpr2_partitions,
317 .nr_parts = ARRAY_SIZE(mpr2_partitions),
321 .width = 2, 318 .width = 2,
322}; 319};
323 320
@@ -337,32 +334,6 @@ static struct platform_device flash_device = {
337 }, 334 },
338}; 335};
339 336
340static struct mtd_info *flash_mtd;
341
342static struct map_info mpr2_flash_map = {
343 .name = "Magic Panel R2 Flash",
344 .size = 0x2000000UL,
345 .bankwidth = 2,
346};
347
348static void __init set_mtd_partitions(void)
349{
350 int nr_parts = 0;
351
352 simple_map_init(&mpr2_flash_map);
353 flash_mtd = do_map_probe("cfi_probe", &mpr2_flash_map);
354 nr_parts = parse_mtd_partitions(flash_mtd, probes,
355 &parsed_partitions, 0);
356 /* If there is no partition table, used the hard coded table */
357 if (nr_parts <= 0) {
358 flash_data.parts = mpr2_partitions;
359 flash_data.nr_parts = ARRAY_SIZE(mpr2_partitions);
360 } else {
361 flash_data.nr_parts = nr_parts;
362 flash_data.parts = parsed_partitions;
363 }
364}
365
366/* 337/*
367 * Add all resources to the platform_device 338 * Add all resources to the platform_device
368 */ 339 */
@@ -376,7 +347,6 @@ static struct platform_device *mpr2_devices[] __initdata = {
376 347
377static int __init mpr2_devices_setup(void) 348static int __init mpr2_devices_setup(void)
378{ 349{
379 set_mtd_partitions();
380 return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices)); 350 return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices));
381} 351}
382device_initcall(mpr2_devices_setup); 352device_initcall(mpr2_devices_setup);
diff --git a/arch/sh/boards/board-sh7757lcr.c b/arch/sh/boards/board-sh7757lcr.c
index 895e337c79b6..0838154dd216 100644
--- a/arch/sh/boards/board-sh7757lcr.c
+++ b/arch/sh/boards/board-sh7757lcr.c
@@ -19,6 +19,7 @@
19#include <linux/mmc/sh_mmcif.h> 19#include <linux/mmc/sh_mmcif.h>
20#include <linux/mmc/sh_mobile_sdhi.h> 20#include <linux/mmc/sh_mobile_sdhi.h>
21#include <linux/sh_eth.h> 21#include <linux/sh_eth.h>
22#include <linux/usb/renesas_usbhs.h>
22#include <cpu/sh7757.h> 23#include <cpu/sh7757.h>
23#include <asm/heartbeat.h> 24#include <asm/heartbeat.h>
24 25
@@ -264,6 +265,43 @@ static struct platform_device sdhi_device = {
264 }, 265 },
265}; 266};
266 267
268static int usbhs0_get_id(struct platform_device *pdev)
269{
270 return USBHS_GADGET;
271}
272
273static struct renesas_usbhs_platform_info usb0_data = {
274 .platform_callback = {
275 .get_id = usbhs0_get_id,
276 },
277 .driver_param = {
278 .buswait_bwait = 5,
279 }
280};
281
282static struct resource usb0_resources[] = {
283 [0] = {
284 .start = 0xfe450000,
285 .end = 0xfe4501ff,
286 .flags = IORESOURCE_MEM,
287 },
288 [1] = {
289 .start = 50,
290 .end = 50,
291 .flags = IORESOURCE_IRQ,
292 },
293};
294
295static struct platform_device usb0_device = {
296 .name = "renesas_usbhs",
297 .id = 0,
298 .dev = {
299 .platform_data = &usb0_data,
300 },
301 .num_resources = ARRAY_SIZE(usb0_resources),
302 .resource = usb0_resources,
303};
304
267static struct platform_device *sh7757lcr_devices[] __initdata = { 305static struct platform_device *sh7757lcr_devices[] __initdata = {
268 &heartbeat_device, 306 &heartbeat_device,
269 &sh7757_eth0_device, 307 &sh7757_eth0_device,
@@ -272,6 +310,7 @@ static struct platform_device *sh7757lcr_devices[] __initdata = {
272 &sh7757_eth_giga1_device, 310 &sh7757_eth_giga1_device,
273 &sh_mmcif_device, 311 &sh_mmcif_device,
274 &sdhi_device, 312 &sdhi_device,
313 &usb0_device,
275}; 314};
276 315
277static struct flash_platform_data spi_flash_data = { 316static struct flash_platform_data spi_flash_data = {
diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c
index 7030f4c8cf11..74d49c01783b 100644
--- a/arch/sh/boards/mach-ap325rxa/setup.c
+++ b/arch/sh/boards/mach-ap325rxa/setup.c
@@ -249,9 +249,6 @@ static struct platform_device lcdc_device = {
249 .dev = { 249 .dev = {
250 .platform_data = &lcdc_info, 250 .platform_data = &lcdc_info,
251 }, 251 },
252 .archdata = {
253 .hwblk_id = HWBLK_LCDC,
254 },
255}; 252};
256 253
257static void camera_power(int val) 254static void camera_power(int val)
@@ -424,9 +421,6 @@ static struct platform_device ceu_device = {
424 .dev = { 421 .dev = {
425 .platform_data = &sh_mobile_ceu_info, 422 .platform_data = &sh_mobile_ceu_info,
426 }, 423 },
427 .archdata = {
428 .hwblk_id = HWBLK_CEU,
429 },
430}; 424};
431 425
432static struct resource sdhi0_cn3_resources[] = { 426static struct resource sdhi0_cn3_resources[] = {
@@ -454,9 +448,6 @@ static struct platform_device sdhi0_cn3_device = {
454 .dev = { 448 .dev = {
455 .platform_data = &sdhi0_cn3_data, 449 .platform_data = &sdhi0_cn3_data,
456 }, 450 },
457 .archdata = {
458 .hwblk_id = HWBLK_SDHI0,
459 },
460}; 451};
461 452
462static struct resource sdhi1_cn7_resources[] = { 453static struct resource sdhi1_cn7_resources[] = {
@@ -484,9 +475,6 @@ static struct platform_device sdhi1_cn7_device = {
484 .dev = { 475 .dev = {
485 .platform_data = &sdhi1_cn7_data, 476 .platform_data = &sdhi1_cn7_data,
486 }, 477 },
487 .archdata = {
488 .hwblk_id = HWBLK_SDHI1,
489 },
490}; 478};
491 479
492static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = { 480static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index 92ddce4b3456..9a19fb07276c 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -156,9 +156,6 @@ static struct platform_device sh_eth_device = {
156 }, 156 },
157 .num_resources = ARRAY_SIZE(sh_eth_resources), 157 .num_resources = ARRAY_SIZE(sh_eth_resources),
158 .resource = sh_eth_resources, 158 .resource = sh_eth_resources,
159 .archdata = {
160 .hwblk_id = HWBLK_ETHER,
161 },
162}; 159};
163 160
164/* USB0 host */ 161/* USB0 host */
@@ -278,9 +275,6 @@ static struct platform_device usbhs_device = {
278 }, 275 },
279 .num_resources = ARRAY_SIZE(usbhs_resources), 276 .num_resources = ARRAY_SIZE(usbhs_resources),
280 .resource = usbhs_resources, 277 .resource = usbhs_resources,
281 .archdata = {
282 .hwblk_id = HWBLK_USB1,
283 },
284}; 278};
285 279
286/* LCDC */ 280/* LCDC */
@@ -366,9 +360,6 @@ static struct platform_device lcdc_device = {
366 .dev = { 360 .dev = {
367 .platform_data = &lcdc_info, 361 .platform_data = &lcdc_info,
368 }, 362 },
369 .archdata = {
370 .hwblk_id = HWBLK_LCDC,
371 },
372}; 363};
373 364
374/* CEU0 */ 365/* CEU0 */
@@ -400,9 +391,6 @@ static struct platform_device ceu0_device = {
400 .dev = { 391 .dev = {
401 .platform_data = &sh_mobile_ceu0_info, 392 .platform_data = &sh_mobile_ceu0_info,
402 }, 393 },
403 .archdata = {
404 .hwblk_id = HWBLK_CEU0,
405 },
406}; 394};
407 395
408/* CEU1 */ 396/* CEU1 */
@@ -434,9 +422,6 @@ static struct platform_device ceu1_device = {
434 .dev = { 422 .dev = {
435 .platform_data = &sh_mobile_ceu1_info, 423 .platform_data = &sh_mobile_ceu1_info,
436 }, 424 },
437 .archdata = {
438 .hwblk_id = HWBLK_CEU1,
439 },
440}; 425};
441 426
442/* I2C device */ 427/* I2C device */
@@ -491,9 +476,6 @@ static struct platform_device keysc_device = {
491 .dev = { 476 .dev = {
492 .platform_data = &keysc_info, 477 .platform_data = &keysc_info,
493 }, 478 },
494 .archdata = {
495 .hwblk_id = HWBLK_KEYSC,
496 },
497}; 479};
498 480
499/* TouchScreen */ 481/* TouchScreen */
@@ -568,9 +550,6 @@ static struct platform_device sdhi0_device = {
568 .dev = { 550 .dev = {
569 .platform_data = &sdhi0_info, 551 .platform_data = &sdhi0_info,
570 }, 552 },
571 .archdata = {
572 .hwblk_id = HWBLK_SDHI0,
573 },
574}; 553};
575 554
576#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) 555#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
@@ -608,9 +587,6 @@ static struct platform_device sdhi1_device = {
608 .dev = { 587 .dev = {
609 .platform_data = &sdhi1_info, 588 .platform_data = &sdhi1_info,
610 }, 589 },
611 .archdata = {
612 .hwblk_id = HWBLK_SDHI1,
613 },
614}; 590};
615#endif /* CONFIG_MMC_SH_MMCIF */ 591#endif /* CONFIG_MMC_SH_MMCIF */
616 592
@@ -676,9 +652,6 @@ static struct platform_device msiof0_device = {
676 }, 652 },
677 .num_resources = ARRAY_SIZE(msiof0_resources), 653 .num_resources = ARRAY_SIZE(msiof0_resources),
678 .resource = msiof0_resources, 654 .resource = msiof0_resources,
679 .archdata = {
680 .hwblk_id = HWBLK_MSIOF0,
681 },
682}; 655};
683 656
684#endif 657#endif
@@ -818,9 +791,6 @@ static struct platform_device fsi_device = {
818 .dev = { 791 .dev = {
819 .platform_data = &fsi_info, 792 .platform_data = &fsi_info,
820 }, 793 },
821 .archdata = {
822 .hwblk_id = HWBLK_SPU, /* FSI needs SPU hwblk */
823 },
824}; 794};
825 795
826/* IrDA */ 796/* IrDA */
@@ -882,9 +852,6 @@ static struct platform_device vou_device = {
882 .dev = { 852 .dev = {
883 .platform_data = &sh_vou_pdata, 853 .platform_data = &sh_vou_pdata,
884 }, 854 },
885 .archdata = {
886 .hwblk_id = HWBLK_VOU,
887 },
888}; 855};
889 856
890#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE) 857#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE)
@@ -936,9 +903,6 @@ static struct platform_device sh_mmcif_device = {
936 }, 903 },
937 .num_resources = ARRAY_SIZE(sh_mmcif_resources), 904 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
938 .resource = sh_mmcif_resources, 905 .resource = sh_mmcif_resources,
939 .archdata = {
940 .hwblk_id = HWBLK_MMC,
941 },
942}; 906};
943#endif 907#endif
944 908
diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c
index f65271a8d075..5c3c71366848 100644
--- a/arch/sh/boards/mach-kfr2r09/setup.c
+++ b/arch/sh/boards/mach-kfr2r09/setup.c
@@ -122,9 +122,6 @@ static struct platform_device kfr2r09_sh_keysc_device = {
122 .dev = { 122 .dev = {
123 .platform_data = &kfr2r09_sh_keysc_info, 123 .platform_data = &kfr2r09_sh_keysc_info,
124 }, 124 },
125 .archdata = {
126 .hwblk_id = HWBLK_KEYSC,
127 },
128}; 125};
129 126
130static const struct fb_videomode kfr2r09_lcdc_modes[] = { 127static const struct fb_videomode kfr2r09_lcdc_modes[] = {
@@ -191,9 +188,6 @@ static struct platform_device kfr2r09_sh_lcdc_device = {
191 .dev = { 188 .dev = {
192 .platform_data = &kfr2r09_sh_lcdc_info, 189 .platform_data = &kfr2r09_sh_lcdc_info,
193 }, 190 },
194 .archdata = {
195 .hwblk_id = HWBLK_LCDC,
196 },
197}; 191};
198 192
199static struct r8a66597_platdata kfr2r09_usb0_gadget_data = { 193static struct r8a66597_platdata kfr2r09_usb0_gadget_data = {
@@ -254,9 +248,6 @@ static struct platform_device kfr2r09_ceu_device = {
254 .dev = { 248 .dev = {
255 .platform_data = &sh_mobile_ceu_info, 249 .platform_data = &sh_mobile_ceu_info,
256 }, 250 },
257 .archdata = {
258 .hwblk_id = HWBLK_CEU0,
259 },
260}; 251};
261 252
262static struct i2c_board_info kfr2r09_i2c_camera = { 253static struct i2c_board_info kfr2r09_i2c_camera = {
@@ -377,9 +368,6 @@ static struct platform_device kfr2r09_sh_sdhi0_device = {
377 .dev = { 368 .dev = {
378 .platform_data = &sh7724_sdhi0_data, 369 .platform_data = &sh7724_sdhi0_data,
379 }, 370 },
380 .archdata = {
381 .hwblk_id = HWBLK_SDHI0,
382 },
383}; 371};
384 372
385static struct platform_device *kfr2r09_devices[] __initdata = { 373static struct platform_device *kfr2r09_devices[] __initdata = {
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c
index e4c81195929c..f8f9377d5684 100644
--- a/arch/sh/boards/mach-migor/setup.c
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -99,9 +99,6 @@ static struct platform_device sh_keysc_device = {
99 .dev = { 99 .dev = {
100 .platform_data = &sh_keysc_info, 100 .platform_data = &sh_keysc_info,
101 }, 101 },
102 .archdata = {
103 .hwblk_id = HWBLK_KEYSC,
104 },
105}; 102};
106 103
107static struct mtd_partition migor_nor_flash_partitions[] = 104static struct mtd_partition migor_nor_flash_partitions[] =
@@ -300,9 +297,6 @@ static struct platform_device migor_lcdc_device = {
300 .dev = { 297 .dev = {
301 .platform_data = &sh_mobile_lcdc_info, 298 .platform_data = &sh_mobile_lcdc_info,
302 }, 299 },
303 .archdata = {
304 .hwblk_id = HWBLK_LCDC,
305 },
306}; 300};
307 301
308static struct clk *camera_clk; 302static struct clk *camera_clk;
@@ -390,9 +384,6 @@ static struct platform_device migor_ceu_device = {
390 .dev = { 384 .dev = {
391 .platform_data = &sh_mobile_ceu_info, 385 .platform_data = &sh_mobile_ceu_info,
392 }, 386 },
393 .archdata = {
394 .hwblk_id = HWBLK_CEU,
395 },
396}; 387};
397 388
398static struct resource sdhi_cn9_resources[] = { 389static struct resource sdhi_cn9_resources[] = {
@@ -421,9 +412,6 @@ static struct platform_device sdhi_cn9_device = {
421 .dev = { 412 .dev = {
422 .platform_data = &sh7724_sdhi_data, 413 .platform_data = &sh7724_sdhi_data,
423 }, 414 },
424 .archdata = {
425 .hwblk_id = HWBLK_SDHI,
426 },
427}; 415};
428 416
429static struct i2c_board_info migor_i2c_devices[] = { 417static struct i2c_board_info migor_i2c_devices[] = {
diff --git a/arch/sh/boards/mach-rsk/setup.c b/arch/sh/boards/mach-rsk/setup.c
index a5c0df785bfe..895f030070d3 100644
--- a/arch/sh/boards/mach-rsk/setup.c
+++ b/arch/sh/boards/mach-rsk/setup.c
@@ -15,12 +15,12 @@
15#include <linux/mtd/mtd.h> 15#include <linux/mtd/mtd.h>
16#include <linux/mtd/partitions.h> 16#include <linux/mtd/partitions.h>
17#include <linux/mtd/physmap.h> 17#include <linux/mtd/physmap.h>
18#ifdef CONFIG_MTD
19#include <linux/mtd/map.h> 18#include <linux/mtd/map.h>
20#endif
21#include <asm/machvec.h> 19#include <asm/machvec.h>
22#include <asm/io.h> 20#include <asm/io.h>
23 21
22static const char *part_probes[] = { "cmdlinepart", NULL };
23
24static struct mtd_partition rsk_partitions[] = { 24static struct mtd_partition rsk_partitions[] = {
25 { 25 {
26 .name = "Bootloader", 26 .name = "Bootloader",
@@ -39,9 +39,10 @@ static struct mtd_partition rsk_partitions[] = {
39}; 39};
40 40
41static struct physmap_flash_data flash_data = { 41static struct physmap_flash_data flash_data = {
42 .parts = rsk_partitions, 42 .parts = rsk_partitions,
43 .nr_parts = ARRAY_SIZE(rsk_partitions), 43 .nr_parts = ARRAY_SIZE(rsk_partitions),
44 .width = 2, 44 .width = 2,
45 .part_probe_types = part_probes,
45}; 46};
46 47
47static struct resource flash_resource = { 48static struct resource flash_resource = {
@@ -60,44 +61,12 @@ static struct platform_device flash_device = {
60 }, 61 },
61}; 62};
62 63
63#ifdef CONFIG_MTD
64static const char *probes[] = { "cmdlinepart", NULL };
65
66static struct map_info rsk_flash_map = {
67 .name = "RSK+ Flash",
68 .size = 0x400000,
69 .bankwidth = 2,
70};
71
72static struct mtd_info *flash_mtd;
73
74static struct mtd_partition *parsed_partitions;
75
76static void __init set_mtd_partitions(void)
77{
78 int nr_parts = 0;
79
80 simple_map_init(&rsk_flash_map);
81 flash_mtd = do_map_probe("cfi_probe", &rsk_flash_map);
82 nr_parts = parse_mtd_partitions(flash_mtd, probes,
83 &parsed_partitions, 0);
84 /* If there is no partition table, used the hard coded table */
85 if (nr_parts > 0) {
86 flash_data.nr_parts = nr_parts;
87 flash_data.parts = parsed_partitions;
88 }
89}
90#else
91static inline void set_mtd_partitions(void) {}
92#endif
93
94static struct platform_device *rsk_devices[] __initdata = { 64static struct platform_device *rsk_devices[] __initdata = {
95 &flash_device, 65 &flash_device,
96}; 66};
97 67
98static int __init rsk_devices_setup(void) 68static int __init rsk_devices_setup(void)
99{ 69{
100 set_mtd_partitions();
101 return platform_add_devices(rsk_devices, 70 return platform_add_devices(rsk_devices,
102 ARRAY_SIZE(rsk_devices)); 71 ARRAY_SIZE(rsk_devices));
103} 72}
diff --git a/arch/sh/boards/mach-se/7722/setup.c b/arch/sh/boards/mach-se/7722/setup.c
index 80a4e571b310..e1963fecd761 100644
--- a/arch/sh/boards/mach-se/7722/setup.c
+++ b/arch/sh/boards/mach-se/7722/setup.c
@@ -127,9 +127,6 @@ static struct platform_device sh_keysc_device = {
127 .dev = { 127 .dev = {
128 .platform_data = &sh_keysc_info, 128 .platform_data = &sh_keysc_info,
129 }, 129 },
130 .archdata = {
131 .hwblk_id = HWBLK_KEYSC,
132 },
133}; 130};
134 131
135static struct platform_device *se7722_devices[] __initdata = { 132static struct platform_device *se7722_devices[] __initdata = {
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
index b747c0ab9264..2585733e9bce 100644
--- a/arch/sh/boards/mach-se/7724/setup.c
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -210,9 +210,6 @@ static struct platform_device lcdc_device = {
210 .dev = { 210 .dev = {
211 .platform_data = &lcdc_info, 211 .platform_data = &lcdc_info,
212 }, 212 },
213 .archdata = {
214 .hwblk_id = HWBLK_LCDC,
215 },
216}; 213};
217 214
218/* CEU0 */ 215/* CEU0 */
@@ -244,9 +241,6 @@ static struct platform_device ceu0_device = {
244 .dev = { 241 .dev = {
245 .platform_data = &sh_mobile_ceu0_info, 242 .platform_data = &sh_mobile_ceu0_info,
246 }, 243 },
247 .archdata = {
248 .hwblk_id = HWBLK_CEU0,
249 },
250}; 244};
251 245
252/* CEU1 */ 246/* CEU1 */
@@ -278,9 +272,6 @@ static struct platform_device ceu1_device = {
278 .dev = { 272 .dev = {
279 .platform_data = &sh_mobile_ceu1_info, 273 .platform_data = &sh_mobile_ceu1_info,
280 }, 274 },
281 .archdata = {
282 .hwblk_id = HWBLK_CEU1,
283 },
284}; 275};
285 276
286/* FSI */ 277/* FSI */
@@ -310,13 +301,22 @@ static struct platform_device fsi_device = {
310 .dev = { 301 .dev = {
311 .platform_data = &fsi_info, 302 .platform_data = &fsi_info,
312 }, 303 },
313 .archdata = { 304};
314 .hwblk_id = HWBLK_SPU, /* FSI needs SPU hwblk */ 305
315 }, 306static struct fsi_ak4642_info fsi_ak4642_info = {
307 .name = "AK4642",
308 .card = "FSIA-AK4642",
309 .cpu_dai = "fsia-dai",
310 .codec = "ak4642-codec.0-0012",
311 .platform = "sh_fsi.0",
312 .id = FSI_PORT_A,
316}; 313};
317 314
318static struct platform_device fsi_ak4642_device = { 315static struct platform_device fsi_ak4642_device = {
319 .name = "sh_fsi_a_ak4642", 316 .name = "fsi-ak4642-audio",
317 .dev = {
318 .platform_data = &fsi_ak4642_info,
319 },
320}; 320};
321 321
322/* KEYSC in SoC (Needs SW33-2 set to ON) */ 322/* KEYSC in SoC (Needs SW33-2 set to ON) */
@@ -355,9 +355,6 @@ static struct platform_device keysc_device = {
355 .dev = { 355 .dev = {
356 .platform_data = &keysc_info, 356 .platform_data = &keysc_info,
357 }, 357 },
358 .archdata = {
359 .hwblk_id = HWBLK_KEYSC,
360 },
361}; 358};
362 359
363/* SH Eth */ 360/* SH Eth */
@@ -386,9 +383,6 @@ static struct platform_device sh_eth_device = {
386 }, 383 },
387 .num_resources = ARRAY_SIZE(sh_eth_resources), 384 .num_resources = ARRAY_SIZE(sh_eth_resources),
388 .resource = sh_eth_resources, 385 .resource = sh_eth_resources,
389 .archdata = {
390 .hwblk_id = HWBLK_ETHER,
391 },
392}; 386};
393 387
394static struct r8a66597_platdata sh7724_usb0_host_data = { 388static struct r8a66597_platdata sh7724_usb0_host_data = {
@@ -418,9 +412,6 @@ static struct platform_device sh7724_usb0_host_device = {
418 }, 412 },
419 .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources), 413 .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources),
420 .resource = sh7724_usb0_host_resources, 414 .resource = sh7724_usb0_host_resources,
421 .archdata = {
422 .hwblk_id = HWBLK_USB0,
423 },
424}; 415};
425 416
426static struct r8a66597_platdata sh7724_usb1_gadget_data = { 417static struct r8a66597_platdata sh7724_usb1_gadget_data = {
@@ -479,9 +470,6 @@ static struct platform_device sdhi0_cn7_device = {
479 .dev = { 470 .dev = {
480 .platform_data = &sh7724_sdhi0_data, 471 .platform_data = &sh7724_sdhi0_data,
481 }, 472 },
482 .archdata = {
483 .hwblk_id = HWBLK_SDHI0,
484 },
485}; 473};
486 474
487static struct resource sdhi1_cn8_resources[] = { 475static struct resource sdhi1_cn8_resources[] = {
@@ -511,9 +499,6 @@ static struct platform_device sdhi1_cn8_device = {
511 .dev = { 499 .dev = {
512 .platform_data = &sh7724_sdhi1_data, 500 .platform_data = &sh7724_sdhi1_data,
513 }, 501 },
514 .archdata = {
515 .hwblk_id = HWBLK_SDHI1,
516 },
517}; 502};
518 503
519/* IrDA */ 504/* IrDA */
@@ -576,9 +561,6 @@ static struct platform_device vou_device = {
576 .dev = { 561 .dev = {
577 .platform_data = &sh_vou_pdata, 562 .platform_data = &sh_vou_pdata,
578 }, 563 },
579 .archdata = {
580 .hwblk_id = HWBLK_VOU,
581 },
582}; 564};
583 565
584static struct platform_device *ms7724se_devices[] __initdata = { 566static struct platform_device *ms7724se_devices[] __initdata = {
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index 11aaf2fdec84..8f18dd090a66 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -36,9 +36,15 @@ static void __devinit pcibios_scanbus(struct pci_channel *hose)
36{ 36{
37 static int next_busno; 37 static int next_busno;
38 static int need_domain_info; 38 static int need_domain_info;
39 LIST_HEAD(resources);
40 int i;
39 struct pci_bus *bus; 41 struct pci_bus *bus;
40 42
41 bus = pci_scan_bus(next_busno, hose->pci_ops, hose); 43 for (i = 0; i < hose->nr_resources; i++)
44 pci_add_resource(&resources, hose->resources + i);
45
46 bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
47 &resources);
42 hose->bus = bus; 48 hose->bus = bus;
43 49
44 need_domain_info = need_domain_info || hose->index; 50 need_domain_info = need_domain_info || hose->index;
@@ -55,6 +61,8 @@ static void __devinit pcibios_scanbus(struct pci_channel *hose)
55 pci_bus_size_bridges(bus); 61 pci_bus_size_bridges(bus);
56 pci_bus_assign_resources(bus); 62 pci_bus_assign_resources(bus);
57 pci_enable_bridges(bus); 63 pci_enable_bridges(bus);
64 } else {
65 pci_free_resource_list(&resources);
58 } 66 }
59} 67}
60 68
@@ -162,16 +170,8 @@ static void pcibios_fixup_device_resources(struct pci_dev *dev,
162 */ 170 */
163void __devinit pcibios_fixup_bus(struct pci_bus *bus) 171void __devinit pcibios_fixup_bus(struct pci_bus *bus)
164{ 172{
165 struct pci_dev *dev = bus->self; 173 struct pci_dev *dev;
166 struct list_head *ln; 174 struct list_head *ln;
167 struct pci_channel *hose = bus->sysdata;
168
169 if (!dev) {
170 int i;
171
172 for (i = 0; i < hose->nr_resources; i++)
173 bus->resource[i] = hose->resources + i;
174 }
175 175
176 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { 176 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
177 dev = pci_dev_b(ln); 177 dev = pci_dev_b(ln);
@@ -243,27 +243,6 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
243 return pci_enable_resources(dev, mask); 243 return pci_enable_resources(dev, mask);
244} 244}
245 245
246/*
247 * If we set up a device for bus mastering, we need to check and set
248 * the latency timer as it may not be properly set.
249 */
250static unsigned int pcibios_max_latency = 255;
251
252void pcibios_set_master(struct pci_dev *dev)
253{
254 u8 lat;
255 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
256 if (lat < 16)
257 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
258 else if (lat > pcibios_max_latency)
259 lat = pcibios_max_latency;
260 else
261 return;
262 printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n",
263 pci_name(dev), lat);
264 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
265}
266
267void __init pcibios_update_irq(struct pci_dev *dev, int irq) 246void __init pcibios_update_irq(struct pci_dev *dev, int irq)
268{ 247{
269 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 248 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
diff --git a/arch/sh/include/asm/device.h b/arch/sh/include/asm/device.h
index b16debfe8c1e..a1c9c0daec10 100644
--- a/arch/sh/include/asm/device.h
+++ b/arch/sh/include/asm/device.h
@@ -14,15 +14,5 @@ int platform_resource_setup_memory(struct platform_device *pdev,
14 14
15void plat_early_device_setup(void); 15void plat_early_device_setup(void);
16 16
17#define PDEV_ARCHDATA_FLAG_INIT 0
18#define PDEV_ARCHDATA_FLAG_IDLE 1
19#define PDEV_ARCHDATA_FLAG_SUSP 2
20
21struct pdev_archdata { 17struct pdev_archdata {
22 int hwblk_id;
23#ifdef CONFIG_PM_RUNTIME
24 unsigned long flags;
25 struct list_head entry;
26 struct mutex mutex;
27#endif
28}; 18};
diff --git a/arch/sh/include/asm/hwblk.h b/arch/sh/include/asm/hwblk.h
deleted file mode 100644
index 855e945c6199..000000000000
--- a/arch/sh/include/asm/hwblk.h
+++ /dev/null
@@ -1,70 +0,0 @@
1#ifndef __ASM_SH_HWBLK_H
2#define __ASM_SH_HWBLK_H
3
4#include <asm/clock.h>
5#include <asm/io.h>
6
7#define HWBLK_CNT_USAGE 0
8#define HWBLK_CNT_IDLE 1
9#define HWBLK_CNT_DEVICES 2
10#define HWBLK_CNT_NR 3
11
12#define HWBLK_AREA_FLAG_PARENT (1 << 0) /* valid parent */
13
14#define HWBLK_AREA(_flags, _parent) \
15{ \
16 .flags = _flags, \
17 .parent = _parent, \
18}
19
20struct hwblk_area {
21 int cnt[HWBLK_CNT_NR];
22 unsigned char parent;
23 unsigned char flags;
24};
25
26#define HWBLK(_mstp, _bit, _area) \
27{ \
28 .mstp = (void __iomem *)_mstp, \
29 .bit = _bit, \
30 .area = _area, \
31}
32
33struct hwblk {
34 void __iomem *mstp;
35 unsigned char bit;
36 unsigned char area;
37 int cnt[HWBLK_CNT_NR];
38};
39
40struct hwblk_info {
41 struct hwblk_area *areas;
42 int nr_areas;
43 struct hwblk *hwblks;
44 int nr_hwblks;
45};
46
47/* Should be defined by processor-specific code */
48int arch_hwblk_init(void);
49int arch_hwblk_sleep_mode(void);
50
51int hwblk_register(struct hwblk_info *info);
52int hwblk_init(void);
53
54void hwblk_enable(struct hwblk_info *info, int hwblk);
55void hwblk_disable(struct hwblk_info *info, int hwblk);
56
57void hwblk_cnt_inc(struct hwblk_info *info, int hwblk, int cnt);
58void hwblk_cnt_dec(struct hwblk_info *info, int hwblk, int cnt);
59
60/* allow clocks to enable and disable hardware blocks */
61#define SH_HWBLK_CLK(_hwblk, _parent, _flags) \
62[_hwblk] = { \
63 .parent = _parent, \
64 .arch_flags = _hwblk, \
65 .flags = _flags, \
66}
67
68int sh_hwblk_clk_register(struct clk *clks, int nr);
69
70#endif /* __ASM_SH_HWBLK_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7722.h b/arch/sh/include/cpu-sh4/cpu/sh7722.h
index bd0622788d64..3bb74e534d0f 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7722.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7722.h
@@ -222,14 +222,11 @@ enum {
222}; 222};
223 223
224enum { 224enum {
225 HWBLK_UNKNOWN = 0, 225 HWBLK_URAM, HWBLK_XYMEM,
226 HWBLK_TLB, HWBLK_IC, HWBLK_OC, HWBLK_URAM, HWBLK_XYMEM, 226 HWBLK_TMU, HWBLK_CMT, HWBLK_RWDT, HWBLK_FLCTL,
227 HWBLK_INTC, HWBLK_DMAC, HWBLK_SHYWAY, HWBLK_HUDI, 227 HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2, HWBLK_IIC, HWBLK_RTC,
228 HWBLK_UBC, HWBLK_TMU, HWBLK_CMT, HWBLK_RWDT, HWBLK_FLCTL, 228 HWBLK_SDHI, HWBLK_KEYSC,
229 HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2, HWBLK_SIO, 229 HWBLK_USBF, HWBLK_2DG, HWBLK_SIU, HWBLK_VOU,
230 HWBLK_SIOF0, HWBLK_SIOF1, HWBLK_IIC, HWBLK_RTC,
231 HWBLK_TPU, HWBLK_IRDA, HWBLK_SDHI, HWBLK_SIM, HWBLK_KEYSC,
232 HWBLK_TSIF, HWBLK_USBF, HWBLK_2DG, HWBLK_SIU, HWBLK_VOU,
233 HWBLK_JPU, HWBLK_BEU, HWBLK_CEU, HWBLK_VEU, HWBLK_VPU, 230 HWBLK_JPU, HWBLK_BEU, HWBLK_CEU, HWBLK_VEU, HWBLK_VPU,
234 HWBLK_LCDC, 231 HWBLK_LCDC,
235 HWBLK_NR, 232 HWBLK_NR,
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7723.h b/arch/sh/include/cpu-sh4/cpu/sh7723.h
index 9b36fae72324..6fae50cb1e94 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7723.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7723.h
@@ -266,10 +266,9 @@ enum {
266}; 266};
267 267
268enum { 268enum {
269 HWBLK_UNKNOWN = 0,
270 HWBLK_TLB, HWBLK_IC, HWBLK_OC, HWBLK_L2C, HWBLK_ILMEM, HWBLK_FPU, 269 HWBLK_TLB, HWBLK_IC, HWBLK_OC, HWBLK_L2C, HWBLK_ILMEM, HWBLK_FPU,
271 HWBLK_INTC, HWBLK_DMAC0, HWBLK_SHYWAY, 270 HWBLK_INTC, HWBLK_DMAC0, HWBLK_SHYWAY,
272 HWBLK_HUDI, HWBLK_DBG, HWBLK_UBC, HWBLK_SUBC, 271 HWBLK_HUDI, HWBLK_UBC,
273 HWBLK_TMU0, HWBLK_CMT, HWBLK_RWDT, HWBLK_DMAC1, HWBLK_TMU1, 272 HWBLK_TMU0, HWBLK_CMT, HWBLK_RWDT, HWBLK_DMAC1, HWBLK_TMU1,
274 HWBLK_FLCTL, 273 HWBLK_FLCTL,
275 HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2, 274 HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2,
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7724.h b/arch/sh/include/cpu-sh4/cpu/sh7724.h
index cbc47e6bcab5..38859f96d4e5 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7724.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7724.h
@@ -268,10 +268,9 @@ enum {
268}; 268};
269 269
270enum { 270enum {
271 HWBLK_UNKNOWN = 0,
272 HWBLK_TLB, HWBLK_IC, HWBLK_OC, HWBLK_RSMEM, HWBLK_ILMEM, HWBLK_L2C, 271 HWBLK_TLB, HWBLK_IC, HWBLK_OC, HWBLK_RSMEM, HWBLK_ILMEM, HWBLK_L2C,
273 HWBLK_FPU, HWBLK_INTC, HWBLK_DMAC0, HWBLK_SHYWAY, 272 HWBLK_FPU, HWBLK_INTC, HWBLK_DMAC0, HWBLK_SHYWAY,
274 HWBLK_HUDI, HWBLK_DBG, HWBLK_UBC, 273 HWBLK_HUDI, HWBLK_UBC,
275 HWBLK_TMU0, HWBLK_CMT, HWBLK_RWDT, HWBLK_DMAC1, HWBLK_TMU1, 274 HWBLK_TMU0, HWBLK_CMT, HWBLK_RWDT, HWBLK_DMAC1, HWBLK_TMU1,
276 HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2, HWBLK_SCIF3, 275 HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2, HWBLK_SCIF3,
277 HWBLK_SCIF4, HWBLK_SCIF5, HWBLK_MSIOF0, HWBLK_MSIOF1, 276 HWBLK_SCIF4, HWBLK_SCIF5, HWBLK_MSIOF0, HWBLK_MSIOF1,
@@ -314,5 +313,6 @@ enum {
314 313
315extern struct clk sh7724_fsimcka_clk; 314extern struct clk sh7724_fsimcka_clk;
316extern struct clk sh7724_fsimckb_clk; 315extern struct clk sh7724_fsimckb_clk;
316extern struct clk sh7724_dv_clki;
317 317
318#endif /* __ASM_SH7724_H__ */ 318#endif /* __ASM_SH7724_H__ */
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index ae95935d93cd..fa58bfd30d82 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -18,4 +18,4 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/
18obj-$(CONFIG_SH_ADC) += adc.o 18obj-$(CONFIG_SH_ADC) += adc.o
19obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o 19obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o
20 20
21obj-y += irq/ init.o clock.o fpu.o hwblk.o proc.o 21obj-y += irq/ init.o clock.o fpu.o proc.o
diff --git a/arch/sh/kernel/cpu/hwblk.c b/arch/sh/kernel/cpu/hwblk.c
deleted file mode 100644
index 3e985aae5d91..000000000000
--- a/arch/sh/kernel/cpu/hwblk.c
+++ /dev/null
@@ -1,159 +0,0 @@
1#include <linux/clk.h>
2#include <linux/compiler.h>
3#include <linux/io.h>
4#include <linux/spinlock.h>
5#include <asm/suspend.h>
6#include <asm/hwblk.h>
7#include <asm/clock.h>
8
9static DEFINE_SPINLOCK(hwblk_lock);
10
11static void hwblk_area_mod_cnt(struct hwblk_info *info,
12 int area, int counter, int value, int goal)
13{
14 struct hwblk_area *hap = info->areas + area;
15
16 hap->cnt[counter] += value;
17
18 if (hap->cnt[counter] != goal)
19 return;
20
21 if (hap->flags & HWBLK_AREA_FLAG_PARENT)
22 hwblk_area_mod_cnt(info, hap->parent, counter, value, goal);
23}
24
25
26static int __hwblk_mod_cnt(struct hwblk_info *info, int hwblk,
27 int counter, int value, int goal)
28{
29 struct hwblk *hp = info->hwblks + hwblk;
30
31 hp->cnt[counter] += value;
32 if (hp->cnt[counter] == goal)
33 hwblk_area_mod_cnt(info, hp->area, counter, value, goal);
34
35 return hp->cnt[counter];
36}
37
38static void hwblk_mod_cnt(struct hwblk_info *info, int hwblk,
39 int counter, int value, int goal)
40{
41 unsigned long flags;
42
43 spin_lock_irqsave(&hwblk_lock, flags);
44 __hwblk_mod_cnt(info, hwblk, counter, value, goal);
45 spin_unlock_irqrestore(&hwblk_lock, flags);
46}
47
48void hwblk_cnt_inc(struct hwblk_info *info, int hwblk, int counter)
49{
50 hwblk_mod_cnt(info, hwblk, counter, 1, 1);
51}
52
53void hwblk_cnt_dec(struct hwblk_info *info, int hwblk, int counter)
54{
55 hwblk_mod_cnt(info, hwblk, counter, -1, 0);
56}
57
58void hwblk_enable(struct hwblk_info *info, int hwblk)
59{
60 struct hwblk *hp = info->hwblks + hwblk;
61 unsigned long tmp;
62 unsigned long flags;
63 int ret;
64
65 spin_lock_irqsave(&hwblk_lock, flags);
66
67 ret = __hwblk_mod_cnt(info, hwblk, HWBLK_CNT_USAGE, 1, 1);
68 if (ret == 1) {
69 tmp = __raw_readl(hp->mstp);
70 tmp &= ~(1 << hp->bit);
71 __raw_writel(tmp, hp->mstp);
72 }
73
74 spin_unlock_irqrestore(&hwblk_lock, flags);
75}
76
77void hwblk_disable(struct hwblk_info *info, int hwblk)
78{
79 struct hwblk *hp = info->hwblks + hwblk;
80 unsigned long tmp;
81 unsigned long flags;
82 int ret;
83
84 spin_lock_irqsave(&hwblk_lock, flags);
85
86 ret = __hwblk_mod_cnt(info, hwblk, HWBLK_CNT_USAGE, -1, 0);
87 if (ret == 0) {
88 tmp = __raw_readl(hp->mstp);
89 tmp |= 1 << hp->bit;
90 __raw_writel(tmp, hp->mstp);
91 }
92
93 spin_unlock_irqrestore(&hwblk_lock, flags);
94}
95
96struct hwblk_info *hwblk_info;
97
98int __init hwblk_register(struct hwblk_info *info)
99{
100 hwblk_info = info;
101 return 0;
102}
103
104int __init __weak arch_hwblk_init(void)
105{
106 return 0;
107}
108
109int __weak arch_hwblk_sleep_mode(void)
110{
111 return SUSP_SH_SLEEP;
112}
113
114int __init hwblk_init(void)
115{
116 return arch_hwblk_init();
117}
118
119/* allow clocks to enable and disable hardware blocks */
120static int sh_hwblk_clk_enable(struct clk *clk)
121{
122 if (!hwblk_info)
123 return -ENOENT;
124
125 hwblk_enable(hwblk_info, clk->arch_flags);
126 return 0;
127}
128
129static void sh_hwblk_clk_disable(struct clk *clk)
130{
131 if (hwblk_info)
132 hwblk_disable(hwblk_info, clk->arch_flags);
133}
134
135static struct clk_ops sh_hwblk_clk_ops = {
136 .enable = sh_hwblk_clk_enable,
137 .disable = sh_hwblk_clk_disable,
138 .recalc = followparent_recalc,
139};
140
141int __init sh_hwblk_clk_register(struct clk *clks, int nr)
142{
143 struct clk *clkp;
144 int ret = 0;
145 int k;
146
147 for (k = 0; !ret && (k < nr); k++) {
148 clkp = clks + k;
149
150 /* skip over clocks using hwblk 0 (HWBLK_UNKNOWN) */
151 if (!clkp->arch_flags)
152 continue;
153
154 clkp->ops = &sh_hwblk_clk_ops;
155 ret |= clk_register(clkp);
156 }
157
158 return ret;
159}
diff --git a/arch/sh/kernel/cpu/sh4/sq.c b/arch/sh/kernel/cpu/sh4/sq.c
index a8140f0bbf6c..0a47bd3e7bee 100644
--- a/arch/sh/kernel/cpu/sh4/sq.c
+++ b/arch/sh/kernel/cpu/sh4/sq.c
@@ -337,7 +337,7 @@ static struct kobj_type ktype_percpu_entry = {
337 .default_attrs = sq_sysfs_attrs, 337 .default_attrs = sq_sysfs_attrs,
338}; 338};
339 339
340static int __devinit sq_dev_add(struct device *dev) 340static int sq_dev_add(struct device *dev, struct subsys_interface *sif)
341{ 341{
342 unsigned int cpu = dev->id; 342 unsigned int cpu = dev->id;
343 struct kobject *kobj; 343 struct kobject *kobj;
@@ -355,7 +355,7 @@ static int __devinit sq_dev_add(struct device *dev)
355 return error; 355 return error;
356} 356}
357 357
358static int __devexit sq_dev_remove(struct device *dev) 358static int sq_dev_remove(struct device *dev, struct subsys_interface *sif)
359{ 359{
360 unsigned int cpu = dev->id; 360 unsigned int cpu = dev->id;
361 struct kobject *kobj = sq_kobject[cpu]; 361 struct kobject *kobj = sq_kobject[cpu];
@@ -365,10 +365,10 @@ static int __devexit sq_dev_remove(struct device *dev)
365} 365}
366 366
367static struct subsys_interface sq_interface = { 367static struct subsys_interface sq_interface = {
368 .name = "sq" 368 .name = "sq",
369 .subsys = &cpu_subsys, 369 .subsys = &cpu_subsys,
370 .add_dev = sq_dev_add, 370 .add_dev = sq_dev_add,
371 .remove_dev = __devexit_p(sq_dev_remove), 371 .remove_dev = sq_dev_remove,
372}; 372};
373 373
374static int __init sq_api_init(void) 374static int __init sq_api_init(void)
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index c57fb287011e..0b22d108f4c5 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -27,9 +27,9 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
27clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o 27clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
28clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o 28clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o
29clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o 29clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
30clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o hwblk-sh7722.o 30clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
31clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o hwblk-sh7723.o 31clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o
32clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o hwblk-sh7724.o 32clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o
33clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o 33clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o
34clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o 34clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
35 35
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index c9a48088ad47..212c72ef959c 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -22,8 +22,8 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clkdev.h> 24#include <linux/clkdev.h>
25#include <linux/sh_clk.h>
25#include <asm/clock.h> 26#include <asm/clock.h>
26#include <asm/hwblk.h>
27#include <cpu/sh7722.h> 27#include <cpu/sh7722.h>
28 28
29/* SH7722 registers */ 29/* SH7722 registers */
@@ -33,6 +33,9 @@
33#define SCLKBCR 0xa415000c 33#define SCLKBCR 0xa415000c
34#define IRDACLKCR 0xa4150018 34#define IRDACLKCR 0xa4150018
35#define PLLCR 0xa4150024 35#define PLLCR 0xa4150024
36#define MSTPCR0 0xa4150030
37#define MSTPCR1 0xa4150034
38#define MSTPCR2 0xa4150038
36#define DLLFRQ 0xa4150050 39#define DLLFRQ 0xa4150050
37 40
38/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 41/* Fixed 32 KHz root clock for RTC and Power Management purposes */
@@ -148,31 +151,31 @@ struct clk div6_clks[DIV6_NR] = {
148}; 151};
149 152
150static struct clk mstp_clks[HWBLK_NR] = { 153static struct clk mstp_clks[HWBLK_NR] = {
151 SH_HWBLK_CLK(HWBLK_URAM, &div4_clks[DIV4_U], CLK_ENABLE_ON_INIT), 154 [HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
152 SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 155 [HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
153 SH_HWBLK_CLK(HWBLK_TMU, &div4_clks[DIV4_P], 0), 156 [HWBLK_TMU] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
154 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0), 157 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
155 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0), 158 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
156 SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0), 159 [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
157 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0), 160 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
158 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0), 161 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
159 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0), 162 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
160 163
161 SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0), 164 [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
162 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0), 165 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
163 166
164 SH_HWBLK_CLK(HWBLK_SDHI, &div4_clks[DIV4_P], 0), 167 [HWBLK_SDHI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
165 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0), 168 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
166 SH_HWBLK_CLK(HWBLK_USBF, &div4_clks[DIV4_P], 0), 169 [HWBLK_USBF] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
167 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0), 170 [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),
168 SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0), 171 [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
169 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0), 172 [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
170 SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0), 173 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
171 SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0), 174 [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
172 SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0), 175 [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
173 SH_HWBLK_CLK(HWBLK_VEU, &div4_clks[DIV4_B], 0), 176 [HWBLK_VEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
174 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0), 177 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
175 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_P], 0), 178 [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 0, 0),
176}; 179};
177 180
178static struct clk_lookup lookups[] = { 181static struct clk_lookup lookups[] = {
@@ -205,27 +208,27 @@ static struct clk_lookup lookups[] = {
205 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU]), 208 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU]),
206 209
207 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), 210 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
208 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]), 211 CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
209 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]), 212 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
210 213
211 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]), 214 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
212 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]), 215 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
213 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]), 216 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
214 217
215 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]), 218 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]),
216 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 219 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
217 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]), 220 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI]),
218 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]), 221 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]),
219 CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]), 222 CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
220 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), 223 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
221 CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]), 224 CLKDEV_DEV_ID("siu-pcm-audio", &mstp_clks[HWBLK_SIU]),
222 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]), 225 CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
223 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]), 226 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
224 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]), 227 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
225 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]), 228 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU]),
226 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]), 229 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
227 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), 230 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
228 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]), 231 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]),
229}; 232};
230 233
231int __init arch_clk_init(void) 234int __init arch_clk_init(void)
@@ -258,7 +261,7 @@ int __init arch_clk_init(void)
258 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 261 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
259 262
260 if (!ret) 263 if (!ret)
261 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); 264 ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR);
262 265
263 return ret; 266 return ret;
264} 267}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index 3cc3827380e3..2f8c9179da47 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -23,8 +23,8 @@
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h> 24#include <linux/clk.h>
25#include <linux/clkdev.h> 25#include <linux/clkdev.h>
26#include <linux/sh_clk.h>
26#include <asm/clock.h> 27#include <asm/clock.h>
27#include <asm/hwblk.h>
28#include <cpu/sh7723.h> 28#include <cpu/sh7723.h>
29 29
30/* SH7723 registers */ 30/* SH7723 registers */
@@ -34,6 +34,9 @@
34#define SCLKBCR 0xa415000c 34#define SCLKBCR 0xa415000c
35#define IRDACLKCR 0xa4150018 35#define IRDACLKCR 0xa4150018
36#define PLLCR 0xa4150024 36#define PLLCR 0xa4150024
37#define MSTPCR0 0xa4150030
38#define MSTPCR1 0xa4150034
39#define MSTPCR2 0xa4150038
37#define DLLFRQ 0xa4150050 40#define DLLFRQ 0xa4150050
38 41
39/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 42/* Fixed 32 KHz root clock for RTC and Power Management purposes */
@@ -149,55 +152,55 @@ struct clk div6_clks[DIV6_NR] = {
149 152
150static struct clk mstp_clks[] = { 153static struct clk mstp_clks[] = {
151 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */ 154 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
152 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 155 [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
153 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 156 [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
154 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 157 [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
155 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 158 [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
156 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 159 [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),
157 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 160 [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),
158 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 161 [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 22, CLK_ENABLE_ON_INIT),
159 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0), 162 [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0),
160 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 163 [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
161 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0), 164 [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
162 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0), 165 [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0),
163 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0), 166 [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
164 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0), 167 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
165 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0), 168 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
166 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0), 169 [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0),
167 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0), 170 [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
168 SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0), 171 [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
169 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0), 172 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
170 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0), 173 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
171 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0), 174 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
172 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0), 175 [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0),
173 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0), 176 [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0),
174 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0), 177 [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0),
175 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0), 178 [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0),
176 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0), 179 [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0),
177 SH_HWBLK_CLK(HWBLK_MERAM, &div4_clks[DIV4_SH], 0), 180 [HWBLK_MERAM] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 0, 0),
178 181
179 SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0), 182 [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
180 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0), 183 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0),
181 184
182 SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_SH], 0), 185 [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 28, 0),
183 SH_HWBLK_CLK(HWBLK_ADC, &div4_clks[DIV4_P], 0), 186 [HWBLK_ADC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
184 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0), 187 [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0),
185 SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0), 188 [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
186 SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0), 189 [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0),
187 SH_HWBLK_CLK(HWBLK_ICB, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 190 [HWBLK_ICB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, CLK_ENABLE_ON_INIT),
188 SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0), 191 [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0),
189 SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0), 192 [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0),
190 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0), 193 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0),
191 SH_HWBLK_CLK(HWBLK_USB, &div4_clks[DIV4_B], 0), 194 [HWBLK_USB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 11, 0),
192 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0), 195 [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 10, 0),
193 SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0), 196 [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
194 SH_HWBLK_CLK(HWBLK_VEU2H1, &div4_clks[DIV4_B], 0), 197 [HWBLK_VEU2H1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
195 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0), 198 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
196 SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0), 199 [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
197 SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0), 200 [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
198 SH_HWBLK_CLK(HWBLK_VEU2H0, &div4_clks[DIV4_B], 0), 201 [HWBLK_VEU2H0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
199 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0), 202 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
200 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0), 203 [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
201}; 204};
202 205
203static struct clk_lookup lookups[] = { 206static struct clk_lookup lookups[] = {
@@ -229,80 +232,17 @@ static struct clk_lookup lookups[] = {
229 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]), 232 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
230 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]), 233 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
231 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]), 234 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
232 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]), 235 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]),
233 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]), 236 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
234 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]), 237 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
235 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]), 238 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
236 {
237 /* TMU0 */
238 .dev_id = "sh_tmu.0",
239 .con_id = "tmu_fck",
240 .clk = &mstp_clks[HWBLK_TMU0],
241 }, {
242 /* TMU1 */
243 .dev_id = "sh_tmu.1",
244 .con_id = "tmu_fck",
245 .clk = &mstp_clks[HWBLK_TMU0],
246 }, {
247 /* TMU2 */
248 .dev_id = "sh_tmu.2",
249 .con_id = "tmu_fck",
250 .clk = &mstp_clks[HWBLK_TMU0],
251 },
252 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), 239 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
253 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]), 240 CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
254 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]), 241 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[HWBLK_DMAC1]),
255 {
256 /* TMU3 */
257 .dev_id = "sh_tmu.3",
258 .con_id = "tmu_fck",
259 .clk = &mstp_clks[HWBLK_TMU1],
260 }, {
261 /* TMU4 */
262 .dev_id = "sh_tmu.4",
263 .con_id = "tmu_fck",
264 .clk = &mstp_clks[HWBLK_TMU1],
265 }, {
266 /* TMU5 */
267 .dev_id = "sh_tmu.5",
268 .con_id = "tmu_fck",
269 .clk = &mstp_clks[HWBLK_TMU1],
270 },
271 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]), 242 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
272 { 243 CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[HWBLK_MSIOF0]),
273 /* SCIF0 */ 244 CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[HWBLK_MSIOF1]),
274 .dev_id = "sh-sci.0", 245 CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[HWBLK_MERAM]),
275 .con_id = "sci_fck",
276 .clk = &mstp_clks[HWBLK_SCIF0],
277 }, {
278 /* SCIF1 */
279 .dev_id = "sh-sci.1",
280 .con_id = "sci_fck",
281 .clk = &mstp_clks[HWBLK_SCIF1],
282 }, {
283 /* SCIF2 */
284 .dev_id = "sh-sci.2",
285 .con_id = "sci_fck",
286 .clk = &mstp_clks[HWBLK_SCIF2],
287 }, {
288 /* SCIF3 */
289 .dev_id = "sh-sci.3",
290 .con_id = "sci_fck",
291 .clk = &mstp_clks[HWBLK_SCIF3],
292 }, {
293 /* SCIF4 */
294 .dev_id = "sh-sci.4",
295 .con_id = "sci_fck",
296 .clk = &mstp_clks[HWBLK_SCIF4],
297 }, {
298 /* SCIF5 */
299 .dev_id = "sh-sci.5",
300 .con_id = "sci_fck",
301 .clk = &mstp_clks[HWBLK_SCIF5],
302 },
303 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
304 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
305 CLKDEV_CON_ID("meram0", &mstp_clks[HWBLK_MERAM]),
306 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]), 246 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]),
307 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 247 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
308 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), 248 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
@@ -311,19 +251,34 @@ static struct clk_lookup lookups[] = {
311 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]), 251 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
312 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]), 252 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
313 CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]), 253 CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]),
314 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]), 254 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI0]),
315 CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]), 255 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[HWBLK_SDHI1]),
316 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]), 256 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]),
317 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]), 257 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]),
318 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), 258 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
319 CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]), 259 CLKDEV_DEV_ID("siu-pcm-audio", &mstp_clks[HWBLK_SIU]),
320 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]), 260 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]),
321 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]), 261 CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
322 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]), 262 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
323 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]), 263 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU]),
324 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]), 264 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]),
325 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), 265 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
326 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]), 266
267 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[HWBLK_TMU0]),
268 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[HWBLK_TMU0]),
269 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU0]),
270 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[HWBLK_TMU1]),
271 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[HWBLK_TMU1]),
272 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[HWBLK_TMU1]),
273
274 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
275 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
276 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
277 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[HWBLK_SCIF3]),
278 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[HWBLK_SCIF4]),
279 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[HWBLK_SCIF5]),
280
281 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]),
327}; 282};
328 283
329int __init arch_clk_init(void) 284int __init arch_clk_init(void)
@@ -356,7 +311,7 @@ int __init arch_clk_init(void)
356 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 311 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
357 312
358 if (!ret) 313 if (!ret)
359 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); 314 ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR);
360 315
361 return ret; 316 return ret;
362} 317}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 8668f557e0ac..b3c039a5064a 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -23,8 +23,8 @@
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h> 24#include <linux/clk.h>
25#include <linux/clkdev.h> 25#include <linux/clkdev.h>
26#include <linux/sh_clk.h>
26#include <asm/clock.h> 27#include <asm/clock.h>
27#include <asm/hwblk.h>
28#include <cpu/sh7724.h> 28#include <cpu/sh7724.h>
29 29
30/* SH7724 registers */ 30/* SH7724 registers */
@@ -35,6 +35,9 @@
35#define FCLKBCR 0xa415000c 35#define FCLKBCR 0xa415000c
36#define IRDACLKCR 0xa4150018 36#define IRDACLKCR 0xa4150018
37#define PLLCR 0xa4150024 37#define PLLCR 0xa4150024
38#define MSTPCR0 0xa4150030
39#define MSTPCR1 0xa4150034
40#define MSTPCR2 0xa4150038
38#define SPUCLKCR 0xa415003c 41#define SPUCLKCR 0xa415003c
39#define FLLFRQ 0xa4150050 42#define FLLFRQ 0xa4150050
40#define LSTATS 0xa4150060 43#define LSTATS 0xa4150060
@@ -111,13 +114,16 @@ static struct clk div3_clk = {
111 .parent = &pll_clk, 114 .parent = &pll_clk,
112}; 115};
113 116
114/* External input clock (pin name: FSIMCKA/FSIMCKB ) */ 117/* External input clock (pin name: FSIMCKA/FSIMCKB/DV_CLKI ) */
115struct clk sh7724_fsimcka_clk = { 118struct clk sh7724_fsimcka_clk = {
116}; 119};
117 120
118struct clk sh7724_fsimckb_clk = { 121struct clk sh7724_fsimckb_clk = {
119}; 122};
120 123
124struct clk sh7724_dv_clki = {
125};
126
121static struct clk *main_clks[] = { 127static struct clk *main_clks[] = {
122 &r_clk, 128 &r_clk,
123 &extal_clk, 129 &extal_clk,
@@ -126,6 +132,7 @@ static struct clk *main_clks[] = {
126 &div3_clk, 132 &div3_clk,
127 &sh7724_fsimcka_clk, 133 &sh7724_fsimcka_clk,
128 &sh7724_fsimckb_clk, 134 &sh7724_fsimckb_clk,
135 &sh7724_dv_clki,
129}; 136};
130 137
131static void div4_kick(struct clk *clk) 138static void div4_kick(struct clk *clk)
@@ -163,17 +170,20 @@ struct clk div4_clks[DIV4_NR] = {
163 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), 170 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
164}; 171};
165 172
166enum { DIV6_V, DIV6_I, DIV6_S, DIV6_NR }; 173enum { DIV6_V, DIV6_I, DIV6_S, DIV6_FA, DIV6_FB, DIV6_NR };
167 174
168static struct clk div6_clks[DIV6_NR] = { 175/* Indices are important - they are the actual src selecting values */
169 [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0), 176static struct clk *common_parent[] = {
170 [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0), 177 [0] = &div3_clk,
171 [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT), 178 [1] = NULL,
172}; 179};
173 180
174enum { DIV6_FA, DIV6_FB, DIV6_REPARENT_NR }; 181static struct clk *vclkcr_parent[8] = {
182 [0] = &div3_clk,
183 [2] = &sh7724_dv_clki,
184 [4] = &extal_clk,
185};
175 186
176/* Indices are important - they are the actual src selecting values */
177static struct clk *fclkacr_parent[] = { 187static struct clk *fclkacr_parent[] = {
178 [0] = &div3_clk, 188 [0] = &div3_clk,
179 [1] = NULL, 189 [1] = NULL,
@@ -188,68 +198,74 @@ static struct clk *fclkbcr_parent[] = {
188 [3] = NULL, 198 [3] = NULL,
189}; 199};
190 200
191static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { 201static struct clk div6_clks[DIV6_NR] = {
192 [DIV6_FA] = SH_CLK_DIV6_EXT(&div3_clk, FCLKACR, 0, 202 [DIV6_V] = SH_CLK_DIV6_EXT(VCLKCR, 0,
203 vclkcr_parent, ARRAY_SIZE(vclkcr_parent), 12, 3),
204 [DIV6_I] = SH_CLK_DIV6_EXT(IRDACLKCR, 0,
205 common_parent, ARRAY_SIZE(common_parent), 6, 1),
206 [DIV6_S] = SH_CLK_DIV6_EXT(SPUCLKCR, CLK_ENABLE_ON_INIT,
207 common_parent, ARRAY_SIZE(common_parent), 6, 1),
208 [DIV6_FA] = SH_CLK_DIV6_EXT(FCLKACR, 0,
193 fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2), 209 fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2),
194 [DIV6_FB] = SH_CLK_DIV6_EXT(&div3_clk, FCLKBCR, 0, 210 [DIV6_FB] = SH_CLK_DIV6_EXT(FCLKBCR, 0,
195 fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2), 211 fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2),
196}; 212};
197 213
198static struct clk mstp_clks[HWBLK_NR] = { 214static struct clk mstp_clks[HWBLK_NR] = {
199 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 215 [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
200 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 216 [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
201 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 217 [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
202 SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 218 [HWBLK_RSMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
203 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 219 [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),
204 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 220 [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
205 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), 221 [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),
206 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT), 222 [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, CLK_ENABLE_ON_INIT),
207 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0), 223 [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0),
208 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT), 224 [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
209 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0), 225 [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
210 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0), 226 [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0),
211 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0), 227 [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
212 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0), 228 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0),
213 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0), 229 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0),
214 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0), 230 [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0),
215 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0), 231 [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
216 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0), 232 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
217 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0), 233 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
218 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0), 234 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
219 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0), 235 [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0),
220 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0), 236 [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0),
221 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0), 237 [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0),
222 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0), 238 [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0),
223 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0), 239 [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0),
224 240
225 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0), 241 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 12, 0),
226 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0), 242 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 11, 0),
227 SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P], 0), 243 [HWBLK_IIC0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
228 SH_HWBLK_CLK(HWBLK_IIC1, &div4_clks[DIV4_P], 0), 244 [HWBLK_IIC1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
229 245
230 SH_HWBLK_CLK(HWBLK_MMC, &div4_clks[DIV4_B], 0), 246 [HWBLK_MMC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 29, 0),
231 SH_HWBLK_CLK(HWBLK_ETHER, &div4_clks[DIV4_B], 0), 247 [HWBLK_ETHER] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 28, 0),
232 SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_B], 0), 248 [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 26, 0),
233 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0), 249 [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0),
234 SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0), 250 [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
235 SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0), 251 [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0),
236 SH_HWBLK_CLK(HWBLK_USB1, &div4_clks[DIV4_B], 0), 252 [HWBLK_USB1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, 0),
237 SH_HWBLK_CLK(HWBLK_USB0, &div4_clks[DIV4_B], 0), 253 [HWBLK_USB0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 20, 0),
238 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0), 254 [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 19, 0),
239 SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0), 255 [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0),
240 SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0), 256 [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0),
241 SH_HWBLK_CLK(HWBLK_VEU1, &div4_clks[DIV4_B], 0), 257 [HWBLK_VEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 15, 0),
242 SH_HWBLK_CLK(HWBLK_CEU1, &div4_clks[DIV4_B], 0), 258 [HWBLK_CEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 13, 0),
243 SH_HWBLK_CLK(HWBLK_BEU1, &div4_clks[DIV4_B], 0), 259 [HWBLK_BEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 12, 0),
244 SH_HWBLK_CLK(HWBLK_2DDMAC, &div4_clks[DIV4_SH], 0), 260 [HWBLK_2DDMAC] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 10, 0),
245 SH_HWBLK_CLK(HWBLK_SPU, &div4_clks[DIV4_B], 0), 261 [HWBLK_SPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0),
246 SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0), 262 [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0),
247 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0), 263 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
248 SH_HWBLK_CLK(HWBLK_BEU0, &div4_clks[DIV4_B], 0), 264 [HWBLK_BEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
249 SH_HWBLK_CLK(HWBLK_CEU0, &div4_clks[DIV4_B], 0), 265 [HWBLK_CEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
250 SH_HWBLK_CLK(HWBLK_VEU0, &div4_clks[DIV4_B], 0), 266 [HWBLK_VEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0),
251 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0), 267 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0),
252 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0), 268 [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
253}; 269};
254 270
255static struct clk_lookup lookups[] = { 271static struct clk_lookup lookups[] = {
@@ -269,8 +285,8 @@ static struct clk_lookup lookups[] = {
269 285
270 /* DIV6 clocks */ 286 /* DIV6 clocks */
271 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), 287 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
272 CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FA]), 288 CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]),
273 CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FB]), 289 CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]),
274 CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]), 290 CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
275 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]), 291 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
276 292
@@ -283,7 +299,7 @@ static struct clk_lookup lookups[] = {
283 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]), 299 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
284 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]), 300 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
285 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]), 301 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
286 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]), 302 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]),
287 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]), 303 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
288 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]), 304 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
289 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]), 305 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
@@ -294,26 +310,26 @@ static struct clk_lookup lookups[] = {
294 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[HWBLK_TMU1]), 310 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[HWBLK_TMU1]),
295 311
296 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), 312 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
297 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]), 313 CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
298 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]), 314 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[HWBLK_DMAC1]),
299 315
300 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[HWBLK_TMU1]), 316 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[HWBLK_TMU1]),
301 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[HWBLK_TMU1]), 317 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[HWBLK_TMU1]),
302 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[HWBLK_SCIF0]), 318 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
303 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[HWBLK_SCIF1]), 319 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
304 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[HWBLK_SCIF2]), 320 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
305 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[HWBLK_SCIF3]), 321 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[HWBLK_SCIF3]),
306 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[HWBLK_SCIF4]), 322 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[HWBLK_SCIF4]),
307 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[HWBLK_SCIF5]), 323 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[HWBLK_SCIF5]),
308 324
309 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]), 325 CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[HWBLK_MSIOF0]),
310 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]), 326 CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[HWBLK_MSIOF1]),
311 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]), 327 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]),
312 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 328 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
313 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC0]), 329 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC0]),
314 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[HWBLK_IIC1]), 330 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[HWBLK_IIC1]),
315 CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]), 331 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[HWBLK_MMC]),
316 CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]), 332 CLKDEV_DEV_ID("sh-eth.0", &mstp_clks[HWBLK_ETHER]),
317 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), 333 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
318 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]), 334 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
319 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]), 335 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
@@ -321,20 +337,20 @@ static struct clk_lookup lookups[] = {
321 CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]), 337 CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]),
322 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]), 338 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]),
323 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), 339 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
324 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]), 340 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI0]),
325 CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]), 341 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[HWBLK_SDHI1]),
326 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]), 342 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]),
327 CLKDEV_CON_ID("ceu1", &mstp_clks[HWBLK_CEU1]), 343 CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[HWBLK_CEU1]),
328 CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]), 344 CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]),
329 CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]), 345 CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]),
330 CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]), 346 CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]),
331 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]), 347 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
332 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]), 348 CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
333 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]), 349 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]),
334 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU0]), 350 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU0]),
335 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]), 351 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]),
336 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), 352 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
337 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]), 353 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]),
338}; 354};
339 355
340int __init arch_clk_init(void) 356int __init arch_clk_init(void)
@@ -356,13 +372,10 @@ int __init arch_clk_init(void)
356 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 372 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
357 373
358 if (!ret) 374 if (!ret)
359 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 375 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
360
361 if (!ret)
362 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
363 376
364 if (!ret) 377 if (!ret)
365 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); 378 ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR);
366 379
367 return ret; 380 return ret;
368} 381}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index 19222dae8233..0fbff1422f54 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -129,7 +129,7 @@ static struct clk_lookup lookups[] = {
129 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP110]), 129 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP110]),
130 130
131 CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP103]), 131 CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP103]),
132 CLKDEV_CON_ID("usb0", &mstp_clks[MSTP102]), 132 CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP102]),
133 CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]), 133 CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]),
134}; 134};
135 135
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
deleted file mode 100644
index a288b5d92341..000000000000
--- a/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
3 *
4 * SH7722 hardware block support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/suspend.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7722.h>
27
28/* SH7722 registers */
29#define MSTPCR0 0xa4150030
30#define MSTPCR1 0xa4150034
31#define MSTPCR2 0xa4150038
32
33/* SH7722 Power Domains */
34enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35static struct hwblk_area sh7722_hwblk_area[] = {
36 [CORE_AREA] = HWBLK_AREA(0, 0),
37 [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38 [SUB_AREA] = HWBLK_AREA(0, 0),
39};
40
41/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42static struct hwblk sh7722_hwblk[HWBLK_NR] = {
43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46 [HWBLK_URAM] = HWBLK(MSTPCR0, 28, CORE_AREA),
47 [HWBLK_XYMEM] = HWBLK(MSTPCR0, 26, CORE_AREA),
48 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
49 [HWBLK_DMAC] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
50 [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
51 [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
52 [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
53 [HWBLK_TMU] = HWBLK(MSTPCR0, 15, CORE_AREA),
54 [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
55 [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
56 [HWBLK_FLCTL] = HWBLK(MSTPCR0, 10, CORE_AREA),
57 [HWBLK_SCIF0] = HWBLK(MSTPCR0, 7, CORE_AREA),
58 [HWBLK_SCIF1] = HWBLK(MSTPCR0, 6, CORE_AREA),
59 [HWBLK_SCIF2] = HWBLK(MSTPCR0, 5, CORE_AREA),
60 [HWBLK_SIO] = HWBLK(MSTPCR0, 3, CORE_AREA),
61 [HWBLK_SIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
62 [HWBLK_SIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
63
64 [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA),
65 [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA),
66
67 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
68 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
69 [HWBLK_SDHI] = HWBLK(MSTPCR2, 18, CORE_AREA),
70 [HWBLK_SIM] = HWBLK(MSTPCR2, 16, CORE_AREA),
71 [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA),
72 [HWBLK_TSIF] = HWBLK(MSTPCR2, 13, SUB_AREA),
73 [HWBLK_USBF] = HWBLK(MSTPCR2, 11, CORE_AREA),
74 [HWBLK_2DG] = HWBLK(MSTPCR2, 9, CORE_AREA_BM),
75 [HWBLK_SIU] = HWBLK(MSTPCR2, 8, CORE_AREA),
76 [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
77 [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
78 [HWBLK_BEU] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
79 [HWBLK_CEU] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
80 [HWBLK_VEU] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
81 [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
82 [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
83};
84
85static struct hwblk_info sh7722_hwblk_info = {
86 .areas = sh7722_hwblk_area,
87 .nr_areas = ARRAY_SIZE(sh7722_hwblk_area),
88 .hwblks = sh7722_hwblk,
89 .nr_hwblks = ARRAY_SIZE(sh7722_hwblk),
90};
91
92int arch_hwblk_sleep_mode(void)
93{
94 if (!sh7722_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
95 return SUSP_SH_STANDBY | SUSP_SH_SF;
96
97 if (!sh7722_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
98 return SUSP_SH_SLEEP | SUSP_SH_SF;
99
100 return SUSP_SH_SLEEP;
101}
102
103int __init arch_hwblk_init(void)
104{
105 return hwblk_register(&sh7722_hwblk_info);
106}
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
deleted file mode 100644
index a7f4684d2032..000000000000
--- a/arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/hwblk-sh7723.c
3 *
4 * SH7723 hardware block support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/suspend.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7723.h>
27
28/* SH7723 registers */
29#define MSTPCR0 0xa4150030
30#define MSTPCR1 0xa4150034
31#define MSTPCR2 0xa4150038
32
33/* SH7723 Power Domains */
34enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35static struct hwblk_area sh7723_hwblk_area[] = {
36 [CORE_AREA] = HWBLK_AREA(0, 0),
37 [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38 [SUB_AREA] = HWBLK_AREA(0, 0),
39};
40
41/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42static struct hwblk sh7723_hwblk[HWBLK_NR] = {
43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46 [HWBLK_L2C] = HWBLK(MSTPCR0, 28, CORE_AREA),
47 [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA),
48 [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA),
49 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
50 [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
51 [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
52 [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
53 [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA),
54 [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
55 [HWBLK_SUBC] = HWBLK(MSTPCR0, 16, CORE_AREA),
56 [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA),
57 [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
58 [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
59 [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM),
60 [HWBLK_TMU1] = HWBLK(MSTPCR0, 11, CORE_AREA),
61 [HWBLK_FLCTL] = HWBLK(MSTPCR0, 10, CORE_AREA),
62 [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA),
63 [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA),
64 [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA),
65 [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA),
66 [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA),
67 [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA),
68 [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
69 [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
70 [HWBLK_MERAM] = HWBLK(MSTPCR0, 0, CORE_AREA),
71
72 [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA),
73 [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA),
74
75 [HWBLK_ATAPI] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
76 [HWBLK_ADC] = HWBLK(MSTPCR2, 27, CORE_AREA),
77 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
78 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
79 [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
80 [HWBLK_ICB] = HWBLK(MSTPCR2, 21, CORE_AREA_BM),
81 [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA),
82 [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA),
83 [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA),
84 [HWBLK_USB] = HWBLK(MSTPCR2, 11, CORE_AREA),
85 [HWBLK_2DG] = HWBLK(MSTPCR2, 10, CORE_AREA_BM),
86 [HWBLK_SIU] = HWBLK(MSTPCR2, 8, CORE_AREA),
87 [HWBLK_VEU2H1] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
88 [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
89 [HWBLK_BEU] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
90 [HWBLK_CEU] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
91 [HWBLK_VEU2H0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
92 [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
93 [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
94};
95
96static struct hwblk_info sh7723_hwblk_info = {
97 .areas = sh7723_hwblk_area,
98 .nr_areas = ARRAY_SIZE(sh7723_hwblk_area),
99 .hwblks = sh7723_hwblk,
100 .nr_hwblks = ARRAY_SIZE(sh7723_hwblk),
101};
102
103int arch_hwblk_sleep_mode(void)
104{
105 if (!sh7723_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
106 return SUSP_SH_STANDBY | SUSP_SH_SF;
107
108 if (!sh7723_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
109 return SUSP_SH_SLEEP | SUSP_SH_SF;
110
111 return SUSP_SH_SLEEP;
112}
113
114int __init arch_hwblk_init(void)
115{
116 return hwblk_register(&sh7723_hwblk_info);
117}
diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
deleted file mode 100644
index 1613ad6013c3..000000000000
--- a/arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/hwblk-sh7724.c
3 *
4 * SH7724 hardware block support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/suspend.h>
25#include <asm/hwblk.h>
26#include <cpu/sh7724.h>
27
28/* SH7724 registers */
29#define MSTPCR0 0xa4150030
30#define MSTPCR1 0xa4150034
31#define MSTPCR2 0xa4150038
32
33/* SH7724 Power Domains */
34enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
35static struct hwblk_area sh7724_hwblk_area[] = {
36 [CORE_AREA] = HWBLK_AREA(0, 0),
37 [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
38 [SUB_AREA] = HWBLK_AREA(0, 0),
39};
40
41/* Table mapping HWBLK to Module Stop Bit and Power Domain */
42static struct hwblk sh7724_hwblk[HWBLK_NR] = {
43 [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
44 [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
45 [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
46 [HWBLK_RSMEM] = HWBLK(MSTPCR0, 28, CORE_AREA),
47 [HWBLK_ILMEM] = HWBLK(MSTPCR0, 27, CORE_AREA),
48 [HWBLK_L2C] = HWBLK(MSTPCR0, 26, CORE_AREA),
49 [HWBLK_FPU] = HWBLK(MSTPCR0, 24, CORE_AREA),
50 [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
51 [HWBLK_DMAC0] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
52 [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
53 [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
54 [HWBLK_DBG] = HWBLK(MSTPCR0, 18, CORE_AREA),
55 [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
56 [HWBLK_TMU0] = HWBLK(MSTPCR0, 15, CORE_AREA),
57 [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
58 [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
59 [HWBLK_DMAC1] = HWBLK(MSTPCR0, 12, CORE_AREA_BM),
60 [HWBLK_TMU1] = HWBLK(MSTPCR0, 10, CORE_AREA),
61 [HWBLK_SCIF0] = HWBLK(MSTPCR0, 9, CORE_AREA),
62 [HWBLK_SCIF1] = HWBLK(MSTPCR0, 8, CORE_AREA),
63 [HWBLK_SCIF2] = HWBLK(MSTPCR0, 7, CORE_AREA),
64 [HWBLK_SCIF3] = HWBLK(MSTPCR0, 6, CORE_AREA),
65 [HWBLK_SCIF4] = HWBLK(MSTPCR0, 5, CORE_AREA),
66 [HWBLK_SCIF5] = HWBLK(MSTPCR0, 4, CORE_AREA),
67 [HWBLK_MSIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
68 [HWBLK_MSIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
69
70 [HWBLK_KEYSC] = HWBLK(MSTPCR1, 12, SUB_AREA),
71 [HWBLK_RTC] = HWBLK(MSTPCR1, 11, SUB_AREA),
72 [HWBLK_IIC0] = HWBLK(MSTPCR1, 9, CORE_AREA),
73 [HWBLK_IIC1] = HWBLK(MSTPCR1, 8, CORE_AREA),
74
75 [HWBLK_MMC] = HWBLK(MSTPCR2, 29, CORE_AREA),
76 [HWBLK_ETHER] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
77 [HWBLK_ATAPI] = HWBLK(MSTPCR2, 26, CORE_AREA_BM),
78 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
79 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
80 [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
81 [HWBLK_USB1] = HWBLK(MSTPCR2, 21, CORE_AREA),
82 [HWBLK_USB0] = HWBLK(MSTPCR2, 20, CORE_AREA),
83 [HWBLK_2DG] = HWBLK(MSTPCR2, 19, CORE_AREA_BM),
84 [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA),
85 [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA),
86 [HWBLK_VEU1] = HWBLK(MSTPCR2, 15, CORE_AREA_BM),
87 [HWBLK_CEU1] = HWBLK(MSTPCR2, 13, CORE_AREA_BM),
88 [HWBLK_BEU1] = HWBLK(MSTPCR2, 12, CORE_AREA_BM),
89 [HWBLK_2DDMAC] = HWBLK(MSTPCR2, 10, CORE_AREA_BM),
90 [HWBLK_SPU] = HWBLK(MSTPCR2, 9, CORE_AREA_BM),
91 [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
92 [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
93 [HWBLK_BEU0] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
94 [HWBLK_CEU0] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
95 [HWBLK_VEU0] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
96 [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
97 [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
98};
99
100static struct hwblk_info sh7724_hwblk_info = {
101 .areas = sh7724_hwblk_area,
102 .nr_areas = ARRAY_SIZE(sh7724_hwblk_area),
103 .hwblks = sh7724_hwblk,
104 .nr_hwblks = ARRAY_SIZE(sh7724_hwblk),
105};
106
107int arch_hwblk_sleep_mode(void)
108{
109 if (!sh7724_hwblk_area[CORE_AREA].cnt[HWBLK_CNT_USAGE])
110 return SUSP_SH_STANDBY | SUSP_SH_SF;
111
112 if (!sh7724_hwblk_area[CORE_AREA_BM].cnt[HWBLK_CNT_USAGE])
113 return SUSP_SH_SLEEP | SUSP_SH_SF;
114
115 return SUSP_SH_SLEEP;
116}
117
118int __init arch_hwblk_init(void)
119{
120 return hwblk_register(&sh7724_hwblk_info);
121}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 278a0e572158..8420d4bc8bfc 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -146,7 +146,7 @@ static struct resource sh7722_dmae_resources[] = {
146 .flags = IORESOURCE_MEM, 146 .flags = IORESOURCE_MEM,
147 }, 147 },
148 { 148 {
149 /* DMA error IRQ */ 149 .name = "error_irq",
150 .start = 78, 150 .start = 78,
151 .end = 78, 151 .end = 78,
152 .flags = IORESOURCE_IRQ, 152 .flags = IORESOURCE_IRQ,
@@ -173,9 +173,6 @@ struct platform_device dma_device = {
173 .dev = { 173 .dev = {
174 .platform_data = &dma_platform_data, 174 .platform_data = &dma_platform_data,
175 }, 175 },
176 .archdata = {
177 .hwblk_id = HWBLK_DMAC,
178 },
179}; 176};
180 177
181/* Serial */ 178/* Serial */
@@ -264,9 +261,6 @@ static struct platform_device rtc_device = {
264 .id = -1, 261 .id = -1,
265 .num_resources = ARRAY_SIZE(rtc_resources), 262 .num_resources = ARRAY_SIZE(rtc_resources),
266 .resource = rtc_resources, 263 .resource = rtc_resources,
267 .archdata = {
268 .hwblk_id = HWBLK_RTC,
269 },
270}; 264};
271 265
272static struct m66592_platdata usbf_platdata = { 266static struct m66592_platdata usbf_platdata = {
@@ -297,9 +291,6 @@ static struct platform_device usbf_device = {
297 }, 291 },
298 .num_resources = ARRAY_SIZE(usbf_resources), 292 .num_resources = ARRAY_SIZE(usbf_resources),
299 .resource = usbf_resources, 293 .resource = usbf_resources,
300 .archdata = {
301 .hwblk_id = HWBLK_USBF,
302 },
303}; 294};
304 295
305static struct resource iic_resources[] = { 296static struct resource iic_resources[] = {
@@ -321,9 +312,6 @@ static struct platform_device iic_device = {
321 .id = 0, /* "i2c0" clock */ 312 .id = 0, /* "i2c0" clock */
322 .num_resources = ARRAY_SIZE(iic_resources), 313 .num_resources = ARRAY_SIZE(iic_resources),
323 .resource = iic_resources, 314 .resource = iic_resources,
324 .archdata = {
325 .hwblk_id = HWBLK_IIC,
326 },
327}; 315};
328 316
329static struct uio_info vpu_platform_data = { 317static struct uio_info vpu_platform_data = {
@@ -352,9 +340,6 @@ static struct platform_device vpu_device = {
352 }, 340 },
353 .resource = vpu_resources, 341 .resource = vpu_resources,
354 .num_resources = ARRAY_SIZE(vpu_resources), 342 .num_resources = ARRAY_SIZE(vpu_resources),
355 .archdata = {
356 .hwblk_id = HWBLK_VPU,
357 },
358}; 343};
359 344
360static struct uio_info veu_platform_data = { 345static struct uio_info veu_platform_data = {
@@ -383,9 +368,6 @@ static struct platform_device veu_device = {
383 }, 368 },
384 .resource = veu_resources, 369 .resource = veu_resources,
385 .num_resources = ARRAY_SIZE(veu_resources), 370 .num_resources = ARRAY_SIZE(veu_resources),
386 .archdata = {
387 .hwblk_id = HWBLK_VEU,
388 },
389}; 371};
390 372
391static struct uio_info jpu_platform_data = { 373static struct uio_info jpu_platform_data = {
@@ -414,9 +396,6 @@ static struct platform_device jpu_device = {
414 }, 396 },
415 .resource = jpu_resources, 397 .resource = jpu_resources,
416 .num_resources = ARRAY_SIZE(jpu_resources), 398 .num_resources = ARRAY_SIZE(jpu_resources),
417 .archdata = {
418 .hwblk_id = HWBLK_JPU,
419 },
420}; 399};
421 400
422static struct sh_timer_config cmt_platform_data = { 401static struct sh_timer_config cmt_platform_data = {
@@ -446,9 +425,6 @@ static struct platform_device cmt_device = {
446 }, 425 },
447 .resource = cmt_resources, 426 .resource = cmt_resources,
448 .num_resources = ARRAY_SIZE(cmt_resources), 427 .num_resources = ARRAY_SIZE(cmt_resources),
449 .archdata = {
450 .hwblk_id = HWBLK_CMT,
451 },
452}; 428};
453 429
454static struct sh_timer_config tmu0_platform_data = { 430static struct sh_timer_config tmu0_platform_data = {
@@ -477,9 +453,6 @@ static struct platform_device tmu0_device = {
477 }, 453 },
478 .resource = tmu0_resources, 454 .resource = tmu0_resources,
479 .num_resources = ARRAY_SIZE(tmu0_resources), 455 .num_resources = ARRAY_SIZE(tmu0_resources),
480 .archdata = {
481 .hwblk_id = HWBLK_TMU,
482 },
483}; 456};
484 457
485static struct sh_timer_config tmu1_platform_data = { 458static struct sh_timer_config tmu1_platform_data = {
@@ -508,9 +481,6 @@ static struct platform_device tmu1_device = {
508 }, 481 },
509 .resource = tmu1_resources, 482 .resource = tmu1_resources,
510 .num_resources = ARRAY_SIZE(tmu1_resources), 483 .num_resources = ARRAY_SIZE(tmu1_resources),
511 .archdata = {
512 .hwblk_id = HWBLK_TMU,
513 },
514}; 484};
515 485
516static struct sh_timer_config tmu2_platform_data = { 486static struct sh_timer_config tmu2_platform_data = {
@@ -538,9 +508,6 @@ static struct platform_device tmu2_device = {
538 }, 508 },
539 .resource = tmu2_resources, 509 .resource = tmu2_resources,
540 .num_resources = ARRAY_SIZE(tmu2_resources), 510 .num_resources = ARRAY_SIZE(tmu2_resources),
541 .archdata = {
542 .hwblk_id = HWBLK_TMU,
543 },
544}; 511};
545 512
546static struct siu_platform siu_platform_data = { 513static struct siu_platform siu_platform_data = {
@@ -571,9 +538,6 @@ static struct platform_device siu_device = {
571 }, 538 },
572 .resource = siu_resources, 539 .resource = siu_resources,
573 .num_resources = ARRAY_SIZE(siu_resources), 540 .num_resources = ARRAY_SIZE(siu_resources),
574 .archdata = {
575 .hwblk_id = HWBLK_SIU,
576 },
577}; 541};
578 542
579static struct platform_device *sh7722_devices[] __initdata = { 543static struct platform_device *sh7722_devices[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 3c2810d8f72e..a188c9ea4393 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -158,9 +158,6 @@ static struct platform_device vpu_device = {
158 }, 158 },
159 .resource = vpu_resources, 159 .resource = vpu_resources,
160 .num_resources = ARRAY_SIZE(vpu_resources), 160 .num_resources = ARRAY_SIZE(vpu_resources),
161 .archdata = {
162 .hwblk_id = HWBLK_VPU,
163 },
164}; 161};
165 162
166static struct uio_info veu0_platform_data = { 163static struct uio_info veu0_platform_data = {
@@ -189,9 +186,6 @@ static struct platform_device veu0_device = {
189 }, 186 },
190 .resource = veu0_resources, 187 .resource = veu0_resources,
191 .num_resources = ARRAY_SIZE(veu0_resources), 188 .num_resources = ARRAY_SIZE(veu0_resources),
192 .archdata = {
193 .hwblk_id = HWBLK_VEU2H0,
194 },
195}; 189};
196 190
197static struct uio_info veu1_platform_data = { 191static struct uio_info veu1_platform_data = {
@@ -220,9 +214,6 @@ static struct platform_device veu1_device = {
220 }, 214 },
221 .resource = veu1_resources, 215 .resource = veu1_resources,
222 .num_resources = ARRAY_SIZE(veu1_resources), 216 .num_resources = ARRAY_SIZE(veu1_resources),
223 .archdata = {
224 .hwblk_id = HWBLK_VEU2H1,
225 },
226}; 217};
227 218
228static struct sh_timer_config cmt_platform_data = { 219static struct sh_timer_config cmt_platform_data = {
@@ -252,9 +243,6 @@ static struct platform_device cmt_device = {
252 }, 243 },
253 .resource = cmt_resources, 244 .resource = cmt_resources,
254 .num_resources = ARRAY_SIZE(cmt_resources), 245 .num_resources = ARRAY_SIZE(cmt_resources),
255 .archdata = {
256 .hwblk_id = HWBLK_CMT,
257 },
258}; 246};
259 247
260static struct sh_timer_config tmu0_platform_data = { 248static struct sh_timer_config tmu0_platform_data = {
@@ -283,9 +271,6 @@ static struct platform_device tmu0_device = {
283 }, 271 },
284 .resource = tmu0_resources, 272 .resource = tmu0_resources,
285 .num_resources = ARRAY_SIZE(tmu0_resources), 273 .num_resources = ARRAY_SIZE(tmu0_resources),
286 .archdata = {
287 .hwblk_id = HWBLK_TMU0,
288 },
289}; 274};
290 275
291static struct sh_timer_config tmu1_platform_data = { 276static struct sh_timer_config tmu1_platform_data = {
@@ -314,9 +299,6 @@ static struct platform_device tmu1_device = {
314 }, 299 },
315 .resource = tmu1_resources, 300 .resource = tmu1_resources,
316 .num_resources = ARRAY_SIZE(tmu1_resources), 301 .num_resources = ARRAY_SIZE(tmu1_resources),
317 .archdata = {
318 .hwblk_id = HWBLK_TMU0,
319 },
320}; 302};
321 303
322static struct sh_timer_config tmu2_platform_data = { 304static struct sh_timer_config tmu2_platform_data = {
@@ -344,9 +326,6 @@ static struct platform_device tmu2_device = {
344 }, 326 },
345 .resource = tmu2_resources, 327 .resource = tmu2_resources,
346 .num_resources = ARRAY_SIZE(tmu2_resources), 328 .num_resources = ARRAY_SIZE(tmu2_resources),
347 .archdata = {
348 .hwblk_id = HWBLK_TMU0,
349 },
350}; 329};
351 330
352static struct sh_timer_config tmu3_platform_data = { 331static struct sh_timer_config tmu3_platform_data = {
@@ -374,9 +353,6 @@ static struct platform_device tmu3_device = {
374 }, 353 },
375 .resource = tmu3_resources, 354 .resource = tmu3_resources,
376 .num_resources = ARRAY_SIZE(tmu3_resources), 355 .num_resources = ARRAY_SIZE(tmu3_resources),
377 .archdata = {
378 .hwblk_id = HWBLK_TMU1,
379 },
380}; 356};
381 357
382static struct sh_timer_config tmu4_platform_data = { 358static struct sh_timer_config tmu4_platform_data = {
@@ -404,9 +380,6 @@ static struct platform_device tmu4_device = {
404 }, 380 },
405 .resource = tmu4_resources, 381 .resource = tmu4_resources,
406 .num_resources = ARRAY_SIZE(tmu4_resources), 382 .num_resources = ARRAY_SIZE(tmu4_resources),
407 .archdata = {
408 .hwblk_id = HWBLK_TMU1,
409 },
410}; 383};
411 384
412static struct sh_timer_config tmu5_platform_data = { 385static struct sh_timer_config tmu5_platform_data = {
@@ -434,9 +407,6 @@ static struct platform_device tmu5_device = {
434 }, 407 },
435 .resource = tmu5_resources, 408 .resource = tmu5_resources,
436 .num_resources = ARRAY_SIZE(tmu5_resources), 409 .num_resources = ARRAY_SIZE(tmu5_resources),
437 .archdata = {
438 .hwblk_id = HWBLK_TMU1,
439 },
440}; 410};
441 411
442static struct resource rtc_resources[] = { 412static struct resource rtc_resources[] = {
@@ -467,9 +437,6 @@ static struct platform_device rtc_device = {
467 .id = -1, 437 .id = -1,
468 .num_resources = ARRAY_SIZE(rtc_resources), 438 .num_resources = ARRAY_SIZE(rtc_resources),
469 .resource = rtc_resources, 439 .resource = rtc_resources,
470 .archdata = {
471 .hwblk_id = HWBLK_RTC,
472 },
473}; 440};
474 441
475static struct r8a66597_platdata r8a66597_data = { 442static struct r8a66597_platdata r8a66597_data = {
@@ -499,9 +466,6 @@ static struct platform_device sh7723_usb_host_device = {
499 }, 466 },
500 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources), 467 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources),
501 .resource = sh7723_usb_host_resources, 468 .resource = sh7723_usb_host_resources,
502 .archdata = {
503 .hwblk_id = HWBLK_USB,
504 },
505}; 469};
506 470
507static struct resource iic_resources[] = { 471static struct resource iic_resources[] = {
@@ -523,9 +487,6 @@ static struct platform_device iic_device = {
523 .id = 0, /* "i2c0" clock */ 487 .id = 0, /* "i2c0" clock */
524 .num_resources = ARRAY_SIZE(iic_resources), 488 .num_resources = ARRAY_SIZE(iic_resources),
525 .resource = iic_resources, 489 .resource = iic_resources,
526 .archdata = {
527 .hwblk_id = HWBLK_IIC,
528 },
529}; 490};
530 491
531static struct platform_device *sh7723_devices[] __initdata = { 492static struct platform_device *sh7723_devices[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index a37dd72c3671..4c671cfe68aa 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -214,7 +214,7 @@ static struct resource sh7724_dmae0_resources[] = {
214 .flags = IORESOURCE_MEM, 214 .flags = IORESOURCE_MEM,
215 }, 215 },
216 { 216 {
217 /* DMA error IRQ */ 217 .name = "error_irq",
218 .start = 78, 218 .start = 78,
219 .end = 78, 219 .end = 78,
220 .flags = IORESOURCE_IRQ, 220 .flags = IORESOURCE_IRQ,
@@ -248,7 +248,7 @@ static struct resource sh7724_dmae1_resources[] = {
248 .flags = IORESOURCE_MEM, 248 .flags = IORESOURCE_MEM,
249 }, 249 },
250 { 250 {
251 /* DMA error IRQ */ 251 .name = "error_irq",
252 .start = 74, 252 .start = 74,
253 .end = 74, 253 .end = 74,
254 .flags = IORESOURCE_IRQ, 254 .flags = IORESOURCE_IRQ,
@@ -275,9 +275,6 @@ static struct platform_device dma0_device = {
275 .dev = { 275 .dev = {
276 .platform_data = &dma_platform_data, 276 .platform_data = &dma_platform_data,
277 }, 277 },
278 .archdata = {
279 .hwblk_id = HWBLK_DMAC0,
280 },
281}; 278};
282 279
283static struct platform_device dma1_device = { 280static struct platform_device dma1_device = {
@@ -288,9 +285,6 @@ static struct platform_device dma1_device = {
288 .dev = { 285 .dev = {
289 .platform_data = &dma_platform_data, 286 .platform_data = &dma_platform_data,
290 }, 287 },
291 .archdata = {
292 .hwblk_id = HWBLK_DMAC1,
293 },
294}; 288};
295 289
296/* Serial */ 290/* Serial */
@@ -434,9 +428,6 @@ static struct platform_device rtc_device = {
434 .id = -1, 428 .id = -1,
435 .num_resources = ARRAY_SIZE(rtc_resources), 429 .num_resources = ARRAY_SIZE(rtc_resources),
436 .resource = rtc_resources, 430 .resource = rtc_resources,
437 .archdata = {
438 .hwblk_id = HWBLK_RTC,
439 },
440}; 431};
441 432
442/* I2C0 */ 433/* I2C0 */
@@ -459,9 +450,6 @@ static struct platform_device iic0_device = {
459 .id = 0, /* "i2c0" clock */ 450 .id = 0, /* "i2c0" clock */
460 .num_resources = ARRAY_SIZE(iic0_resources), 451 .num_resources = ARRAY_SIZE(iic0_resources),
461 .resource = iic0_resources, 452 .resource = iic0_resources,
462 .archdata = {
463 .hwblk_id = HWBLK_IIC0,
464 },
465}; 453};
466 454
467/* I2C1 */ 455/* I2C1 */
@@ -484,9 +472,6 @@ static struct platform_device iic1_device = {
484 .id = 1, /* "i2c1" clock */ 472 .id = 1, /* "i2c1" clock */
485 .num_resources = ARRAY_SIZE(iic1_resources), 473 .num_resources = ARRAY_SIZE(iic1_resources),
486 .resource = iic1_resources, 474 .resource = iic1_resources,
487 .archdata = {
488 .hwblk_id = HWBLK_IIC1,
489 },
490}; 475};
491 476
492/* VPU */ 477/* VPU */
@@ -516,9 +501,6 @@ static struct platform_device vpu_device = {
516 }, 501 },
517 .resource = vpu_resources, 502 .resource = vpu_resources,
518 .num_resources = ARRAY_SIZE(vpu_resources), 503 .num_resources = ARRAY_SIZE(vpu_resources),
519 .archdata = {
520 .hwblk_id = HWBLK_VPU,
521 },
522}; 504};
523 505
524/* VEU0 */ 506/* VEU0 */
@@ -548,9 +530,6 @@ static struct platform_device veu0_device = {
548 }, 530 },
549 .resource = veu0_resources, 531 .resource = veu0_resources,
550 .num_resources = ARRAY_SIZE(veu0_resources), 532 .num_resources = ARRAY_SIZE(veu0_resources),
551 .archdata = {
552 .hwblk_id = HWBLK_VEU0,
553 },
554}; 533};
555 534
556/* VEU1 */ 535/* VEU1 */
@@ -580,9 +559,6 @@ static struct platform_device veu1_device = {
580 }, 559 },
581 .resource = veu1_resources, 560 .resource = veu1_resources,
582 .num_resources = ARRAY_SIZE(veu1_resources), 561 .num_resources = ARRAY_SIZE(veu1_resources),
583 .archdata = {
584 .hwblk_id = HWBLK_VEU1,
585 },
586}; 562};
587 563
588/* BEU0 */ 564/* BEU0 */
@@ -612,9 +588,6 @@ static struct platform_device beu0_device = {
612 }, 588 },
613 .resource = beu0_resources, 589 .resource = beu0_resources,
614 .num_resources = ARRAY_SIZE(beu0_resources), 590 .num_resources = ARRAY_SIZE(beu0_resources),
615 .archdata = {
616 .hwblk_id = HWBLK_BEU0,
617 },
618}; 591};
619 592
620/* BEU1 */ 593/* BEU1 */
@@ -644,9 +617,6 @@ static struct platform_device beu1_device = {
644 }, 617 },
645 .resource = beu1_resources, 618 .resource = beu1_resources,
646 .num_resources = ARRAY_SIZE(beu1_resources), 619 .num_resources = ARRAY_SIZE(beu1_resources),
647 .archdata = {
648 .hwblk_id = HWBLK_BEU1,
649 },
650}; 620};
651 621
652static struct sh_timer_config cmt_platform_data = { 622static struct sh_timer_config cmt_platform_data = {
@@ -676,9 +646,6 @@ static struct platform_device cmt_device = {
676 }, 646 },
677 .resource = cmt_resources, 647 .resource = cmt_resources,
678 .num_resources = ARRAY_SIZE(cmt_resources), 648 .num_resources = ARRAY_SIZE(cmt_resources),
679 .archdata = {
680 .hwblk_id = HWBLK_CMT,
681 },
682}; 649};
683 650
684static struct sh_timer_config tmu0_platform_data = { 651static struct sh_timer_config tmu0_platform_data = {
@@ -707,9 +674,6 @@ static struct platform_device tmu0_device = {
707 }, 674 },
708 .resource = tmu0_resources, 675 .resource = tmu0_resources,
709 .num_resources = ARRAY_SIZE(tmu0_resources), 676 .num_resources = ARRAY_SIZE(tmu0_resources),
710 .archdata = {
711 .hwblk_id = HWBLK_TMU0,
712 },
713}; 677};
714 678
715static struct sh_timer_config tmu1_platform_data = { 679static struct sh_timer_config tmu1_platform_data = {
@@ -738,9 +702,6 @@ static struct platform_device tmu1_device = {
738 }, 702 },
739 .resource = tmu1_resources, 703 .resource = tmu1_resources,
740 .num_resources = ARRAY_SIZE(tmu1_resources), 704 .num_resources = ARRAY_SIZE(tmu1_resources),
741 .archdata = {
742 .hwblk_id = HWBLK_TMU0,
743 },
744}; 705};
745 706
746static struct sh_timer_config tmu2_platform_data = { 707static struct sh_timer_config tmu2_platform_data = {
@@ -768,9 +729,6 @@ static struct platform_device tmu2_device = {
768 }, 729 },
769 .resource = tmu2_resources, 730 .resource = tmu2_resources,
770 .num_resources = ARRAY_SIZE(tmu2_resources), 731 .num_resources = ARRAY_SIZE(tmu2_resources),
771 .archdata = {
772 .hwblk_id = HWBLK_TMU0,
773 },
774}; 732};
775 733
776 734
@@ -799,9 +757,6 @@ static struct platform_device tmu3_device = {
799 }, 757 },
800 .resource = tmu3_resources, 758 .resource = tmu3_resources,
801 .num_resources = ARRAY_SIZE(tmu3_resources), 759 .num_resources = ARRAY_SIZE(tmu3_resources),
802 .archdata = {
803 .hwblk_id = HWBLK_TMU1,
804 },
805}; 760};
806 761
807static struct sh_timer_config tmu4_platform_data = { 762static struct sh_timer_config tmu4_platform_data = {
@@ -829,9 +784,6 @@ static struct platform_device tmu4_device = {
829 }, 784 },
830 .resource = tmu4_resources, 785 .resource = tmu4_resources,
831 .num_resources = ARRAY_SIZE(tmu4_resources), 786 .num_resources = ARRAY_SIZE(tmu4_resources),
832 .archdata = {
833 .hwblk_id = HWBLK_TMU1,
834 },
835}; 787};
836 788
837static struct sh_timer_config tmu5_platform_data = { 789static struct sh_timer_config tmu5_platform_data = {
@@ -859,9 +811,6 @@ static struct platform_device tmu5_device = {
859 }, 811 },
860 .resource = tmu5_resources, 812 .resource = tmu5_resources,
861 .num_resources = ARRAY_SIZE(tmu5_resources), 813 .num_resources = ARRAY_SIZE(tmu5_resources),
862 .archdata = {
863 .hwblk_id = HWBLK_TMU1,
864 },
865}; 814};
866 815
867/* JPU */ 816/* JPU */
@@ -891,9 +840,6 @@ static struct platform_device jpu_device = {
891 }, 840 },
892 .resource = jpu_resources, 841 .resource = jpu_resources,
893 .num_resources = ARRAY_SIZE(jpu_resources), 842 .num_resources = ARRAY_SIZE(jpu_resources),
894 .archdata = {
895 .hwblk_id = HWBLK_JPU,
896 },
897}; 843};
898 844
899/* SPU2DSP0 */ 845/* SPU2DSP0 */
@@ -923,9 +869,6 @@ static struct platform_device spu0_device = {
923 }, 869 },
924 .resource = spu0_resources, 870 .resource = spu0_resources,
925 .num_resources = ARRAY_SIZE(spu0_resources), 871 .num_resources = ARRAY_SIZE(spu0_resources),
926 .archdata = {
927 .hwblk_id = HWBLK_SPU,
928 },
929}; 872};
930 873
931/* SPU2DSP1 */ 874/* SPU2DSP1 */
@@ -955,9 +898,6 @@ static struct platform_device spu1_device = {
955 }, 898 },
956 .resource = spu1_resources, 899 .resource = spu1_resources,
957 .num_resources = ARRAY_SIZE(spu1_resources), 900 .num_resources = ARRAY_SIZE(spu1_resources),
958 .archdata = {
959 .hwblk_id = HWBLK_SPU,
960 },
961}; 901};
962 902
963static struct platform_device *sh7724_devices[] __initdata = { 903static struct platform_device *sh7724_devices[] __initdata = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index 05559295d2ca..a7b2da6b3a1a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -465,6 +465,7 @@ static struct resource sh7757_dmae0_resources[] = {
465 .flags = IORESOURCE_MEM, 465 .flags = IORESOURCE_MEM,
466 }, 466 },
467 { 467 {
468 .name = "error_irq",
468 .start = 34, 469 .start = 34,
469 .end = 34, 470 .end = 34,
470 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 471 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
@@ -486,7 +487,7 @@ static struct resource sh7757_dmae1_resources[] = {
486 .flags = IORESOURCE_MEM, 487 .flags = IORESOURCE_MEM,
487 }, 488 },
488 { 489 {
489 /* DMA error */ 490 .name = "error_irq",
490 .start = 34, 491 .start = 34,
491 .end = 34, 492 .end = 34,
492 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 493 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
@@ -556,7 +557,7 @@ static struct resource sh7757_dmae2_resources[] = {
556 .flags = IORESOURCE_MEM, 557 .flags = IORESOURCE_MEM,
557 }, 558 },
558 { 559 {
559 /* DMA error */ 560 .name = "error_irq",
560 .start = 323, 561 .start = 323,
561 .end = 323, 562 .end = 323,
562 .flags = IORESOURCE_IRQ, 563 .flags = IORESOURCE_IRQ,
@@ -590,7 +591,7 @@ static struct resource sh7757_dmae3_resources[] = {
590 .flags = IORESOURCE_MEM, 591 .flags = IORESOURCE_MEM,
591 }, 592 },
592 { 593 {
593 /* DMA error */ 594 .name = "error_irq",
594 .start = 324, 595 .start = 324,
595 .end = 324, 596 .end = 324,
596 .flags = IORESOURCE_IRQ, 597 .flags = IORESOURCE_IRQ,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index 3d4d2075c19a..d431b0052d0c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -322,6 +322,7 @@ static struct resource sh7780_dmae0_resources[] = {
322 }, 322 },
323 { 323 {
324 /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */ 324 /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */
325 .name = "error_irq",
325 .start = 34, 326 .start = 34,
326 .end = 34, 327 .end = 34,
327 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 328 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
@@ -338,6 +339,7 @@ static struct resource sh7780_dmae1_resources[] = {
338 /* DMAC1 has no DMARS */ 339 /* DMAC1 has no DMARS */
339 { 340 {
340 /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */ 341 /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */
342 .name = "error_irq",
341 .start = 46, 343 .start = 46,
342 .end = 46, 344 .end = 46,
343 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 345 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index b29e6340414a..81588ef15a6c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -376,6 +376,7 @@ static struct resource sh7785_dmae0_resources[] = {
376 }, 376 },
377 { 377 {
378 /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */ 378 /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */
379 .name = "error_irq",
379 .start = 33, 380 .start = 33,
380 .end = 33, 381 .end = 33,
381 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 382 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
@@ -392,6 +393,7 @@ static struct resource sh7785_dmae1_resources[] = {
392 /* DMAC1 has no DMARS */ 393 /* DMAC1 has no DMARS */
393 { 394 {
394 /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */ 395 /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */
396 .name = "error_irq",
395 .start = 52, 397 .start = 52,
396 .end = 52, 398 .end = 52,
397 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 399 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index dd5e709f9821..599022d73b28 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -518,7 +518,7 @@ static struct resource dmac0_resources[] = {
518 .end = 0xfe00900b, 518 .end = 0xfe00900b,
519 .flags = IORESOURCE_MEM, 519 .flags = IORESOURCE_MEM,
520 }, { 520 }, {
521 /* DMA error IRQ */ 521 .name = "error_irq",
522 .start = evt2irq(0x5c0), 522 .start = evt2irq(0x5c0),
523 .end = evt2irq(0x5c0), 523 .end = evt2irq(0x5c0),
524 .flags = IORESOURCE_IRQ, 524 .flags = IORESOURCE_IRQ,
diff --git a/arch/sh/kernel/cpu/shmobile/Makefile b/arch/sh/kernel/cpu/shmobile/Makefile
index a39f88ea1a85..e8a5111e848a 100644
--- a/arch/sh/kernel/cpu/shmobile/Makefile
+++ b/arch/sh/kernel/cpu/shmobile/Makefile
@@ -5,4 +5,3 @@
5# Power Management & Sleep mode 5# Power Management & Sleep mode
6obj-$(CONFIG_PM) += pm.o sleep.o 6obj-$(CONFIG_PM) += pm.o sleep.o
7obj-$(CONFIG_CPU_IDLE) += cpuidle.o 7obj-$(CONFIG_CPU_IDLE) += cpuidle.o
8obj-$(CONFIG_PM_RUNTIME) += pm_runtime.o
diff --git a/arch/sh/kernel/cpu/shmobile/cpuidle.c b/arch/sh/kernel/cpu/shmobile/cpuidle.c
index 1cc257c9b1e3..6d62eb40e750 100644
--- a/arch/sh/kernel/cpu/shmobile/cpuidle.c
+++ b/arch/sh/kernel/cpu/shmobile/cpuidle.c
@@ -17,7 +17,6 @@
17#include <linux/export.h> 17#include <linux/export.h>
18#include <asm/suspend.h> 18#include <asm/suspend.h>
19#include <asm/uaccess.h> 19#include <asm/uaccess.h>
20#include <asm/hwblk.h>
21 20
22static unsigned long cpuidle_mode[] = { 21static unsigned long cpuidle_mode[] = {
23 SUSP_SH_SLEEP, /* regular sleep mode */ 22 SUSP_SH_SLEEP, /* regular sleep mode */
@@ -29,7 +28,7 @@ static int cpuidle_sleep_enter(struct cpuidle_device *dev,
29 struct cpuidle_driver *drv, 28 struct cpuidle_driver *drv,
30 int index) 29 int index)
31{ 30{
32 unsigned long allowed_mode = arch_hwblk_sleep_mode(); 31 unsigned long allowed_mode = SUSP_SH_SLEEP;
33 ktime_t before, after; 32 ktime_t before, after;
34 int requested_state = index; 33 int requested_state = index;
35 int allowed_state; 34 int allowed_state;
diff --git a/arch/sh/kernel/cpu/shmobile/pm_runtime.c b/arch/sh/kernel/cpu/shmobile/pm_runtime.c
deleted file mode 100644
index bf280c812d2f..000000000000
--- a/arch/sh/kernel/cpu/shmobile/pm_runtime.c
+++ /dev/null
@@ -1,319 +0,0 @@
1/*
2 * arch/sh/kernel/cpu/shmobile/pm_runtime.c
3 *
4 * Runtime PM support code for SuperH Mobile
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <linux/pm_runtime.h>
16#include <linux/platform_device.h>
17#include <linux/mutex.h>
18#include <asm/hwblk.h>
19
20static DEFINE_SPINLOCK(hwblk_lock);
21static LIST_HEAD(hwblk_idle_list);
22static struct work_struct hwblk_work;
23
24extern struct hwblk_info *hwblk_info;
25
26static void platform_pm_runtime_not_idle(struct platform_device *pdev)
27{
28 unsigned long flags;
29
30 /* remove device from idle list */
31 spin_lock_irqsave(&hwblk_lock, flags);
32 if (test_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags)) {
33 list_del(&pdev->archdata.entry);
34 __clear_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags);
35 }
36 spin_unlock_irqrestore(&hwblk_lock, flags);
37}
38
39static int __platform_pm_runtime_resume(struct platform_device *pdev)
40{
41 struct device *d = &pdev->dev;
42 struct pdev_archdata *ad = &pdev->archdata;
43 int hwblk = ad->hwblk_id;
44 int ret = -ENOSYS;
45
46 dev_dbg(d, "__platform_pm_runtime_resume() [%d]\n", hwblk);
47
48 if (d->driver) {
49 hwblk_enable(hwblk_info, hwblk);
50 ret = 0;
51
52 if (test_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags)) {
53 if (d->driver->pm && d->driver->pm->runtime_resume)
54 ret = d->driver->pm->runtime_resume(d);
55
56 if (!ret)
57 clear_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags);
58 else
59 hwblk_disable(hwblk_info, hwblk);
60 }
61 }
62
63 dev_dbg(d, "__platform_pm_runtime_resume() [%d] - returns %d\n",
64 hwblk, ret);
65
66 return ret;
67}
68
69static int __platform_pm_runtime_suspend(struct platform_device *pdev)
70{
71 struct device *d = &pdev->dev;
72 struct pdev_archdata *ad = &pdev->archdata;
73 int hwblk = ad->hwblk_id;
74 int ret = -ENOSYS;
75
76 dev_dbg(d, "__platform_pm_runtime_suspend() [%d]\n", hwblk);
77
78 if (d->driver) {
79 BUG_ON(!test_bit(PDEV_ARCHDATA_FLAG_IDLE, &ad->flags));
80 ret = 0;
81
82 if (d->driver->pm && d->driver->pm->runtime_suspend) {
83 hwblk_enable(hwblk_info, hwblk);
84 ret = d->driver->pm->runtime_suspend(d);
85 hwblk_disable(hwblk_info, hwblk);
86 }
87
88 if (!ret) {
89 set_bit(PDEV_ARCHDATA_FLAG_SUSP, &ad->flags);
90 platform_pm_runtime_not_idle(pdev);
91 hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_IDLE);
92 }
93 }
94
95 dev_dbg(d, "__platform_pm_runtime_suspend() [%d] - returns %d\n",
96 hwblk, ret);
97
98 return ret;
99}
100
101static void platform_pm_runtime_work(struct work_struct *work)
102{
103 struct platform_device *pdev;
104 unsigned long flags;
105 int ret;
106
107 /* go through the idle list and suspend one device at a time */
108 do {
109 spin_lock_irqsave(&hwblk_lock, flags);
110 if (list_empty(&hwblk_idle_list))
111 pdev = NULL;
112 else
113 pdev = list_first_entry(&hwblk_idle_list,
114 struct platform_device,
115 archdata.entry);
116 spin_unlock_irqrestore(&hwblk_lock, flags);
117
118 if (pdev) {
119 mutex_lock(&pdev->archdata.mutex);
120 ret = __platform_pm_runtime_suspend(pdev);
121
122 /* at this point the platform device may be:
123 * suspended: ret = 0, FLAG_SUSP set, clock stopped
124 * failed: ret < 0, FLAG_IDLE set, clock stopped
125 */
126 mutex_unlock(&pdev->archdata.mutex);
127 } else {
128 ret = -ENODEV;
129 }
130 } while (!ret);
131}
132
133/* this function gets called from cpuidle context when all devices in the
134 * main power domain are unused but some are counted as idle, ie the hwblk
135 * counter values are (HWBLK_CNT_USAGE == 0) && (HWBLK_CNT_IDLE != 0)
136 */
137void platform_pm_runtime_suspend_idle(void)
138{
139 queue_work(pm_wq, &hwblk_work);
140}
141
142static int default_platform_runtime_suspend(struct device *dev)
143{
144 struct platform_device *pdev = to_platform_device(dev);
145 struct pdev_archdata *ad = &pdev->archdata;
146 unsigned long flags;
147 int hwblk = ad->hwblk_id;
148 int ret = 0;
149
150 dev_dbg(dev, "%s() [%d]\n", __func__, hwblk);
151
152 /* ignore off-chip platform devices */
153 if (!hwblk)
154 goto out;
155
156 /* interrupt context not allowed */
157 might_sleep();
158
159 /* catch misconfigured drivers not starting with resume */
160 if (test_bit(PDEV_ARCHDATA_FLAG_INIT, &ad->flags)) {
161 ret = -EINVAL;
162 goto out;
163 }
164
165 /* serialize */
166 mutex_lock(&ad->mutex);
167
168 /* disable clock */
169 hwblk_disable(hwblk_info, hwblk);
170
171 /* put device on idle list */
172 spin_lock_irqsave(&hwblk_lock, flags);
173 list_add_tail(&ad->entry, &hwblk_idle_list);
174 __set_bit(PDEV_ARCHDATA_FLAG_IDLE, &ad->flags);
175 spin_unlock_irqrestore(&hwblk_lock, flags);
176
177 /* increase idle count */
178 hwblk_cnt_inc(hwblk_info, hwblk, HWBLK_CNT_IDLE);
179
180 /* at this point the platform device is:
181 * idle: ret = 0, FLAG_IDLE set, clock stopped
182 */
183 mutex_unlock(&ad->mutex);
184
185out:
186 dev_dbg(dev, "%s() [%d] returns %d\n",
187 __func__, hwblk, ret);
188
189 return ret;
190}
191
192static int default_platform_runtime_resume(struct device *dev)
193{
194 struct platform_device *pdev = to_platform_device(dev);
195 struct pdev_archdata *ad = &pdev->archdata;
196 int hwblk = ad->hwblk_id;
197 int ret = 0;
198
199 dev_dbg(dev, "%s() [%d]\n", __func__, hwblk);
200
201 /* ignore off-chip platform devices */
202 if (!hwblk)
203 goto out;
204
205 /* interrupt context not allowed */
206 might_sleep();
207
208 /* serialize */
209 mutex_lock(&ad->mutex);
210
211 /* make sure device is removed from idle list */
212 platform_pm_runtime_not_idle(pdev);
213
214 /* decrease idle count */
215 if (!test_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags) &&
216 !test_bit(PDEV_ARCHDATA_FLAG_SUSP, &pdev->archdata.flags))
217 hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_IDLE);
218
219 /* resume the device if needed */
220 ret = __platform_pm_runtime_resume(pdev);
221
222 /* the driver has been initialized now, so clear the init flag */
223 clear_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
224
225 /* at this point the platform device may be:
226 * resumed: ret = 0, flags = 0, clock started
227 * failed: ret < 0, FLAG_SUSP set, clock stopped
228 */
229 mutex_unlock(&ad->mutex);
230out:
231 dev_dbg(dev, "%s() [%d] returns %d\n",
232 __func__, hwblk, ret);
233
234 return ret;
235}
236
237static int default_platform_runtime_idle(struct device *dev)
238{
239 struct platform_device *pdev = to_platform_device(dev);
240 int hwblk = pdev->archdata.hwblk_id;
241 int ret = 0;
242
243 dev_dbg(dev, "%s() [%d]\n", __func__, hwblk);
244
245 /* ignore off-chip platform devices */
246 if (!hwblk)
247 goto out;
248
249 /* interrupt context not allowed, use pm_runtime_put()! */
250 might_sleep();
251
252 /* suspend synchronously to disable clocks immediately */
253 ret = pm_runtime_suspend(dev);
254out:
255 dev_dbg(dev, "%s() [%d] done!\n", __func__, hwblk);
256 return ret;
257}
258
259static struct dev_pm_domain default_pm_domain = {
260 .ops = {
261 .runtime_suspend = default_platform_runtime_suspend,
262 .runtime_resume = default_platform_runtime_resume,
263 .runtime_idle = default_platform_runtime_idle,
264 USE_PLATFORM_PM_SLEEP_OPS
265 },
266};
267
268static int platform_bus_notify(struct notifier_block *nb,
269 unsigned long action, void *data)
270{
271 struct device *dev = data;
272 struct platform_device *pdev = to_platform_device(dev);
273 int hwblk = pdev->archdata.hwblk_id;
274
275 /* ignore off-chip platform devices */
276 if (!hwblk)
277 return 0;
278
279 switch (action) {
280 case BUS_NOTIFY_ADD_DEVICE:
281 INIT_LIST_HEAD(&pdev->archdata.entry);
282 mutex_init(&pdev->archdata.mutex);
283 /* platform devices without drivers should be disabled */
284 hwblk_enable(hwblk_info, hwblk);
285 hwblk_disable(hwblk_info, hwblk);
286 /* make sure driver re-inits itself once */
287 __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
288 dev->pm_domain = &default_pm_domain;
289 break;
290 /* TODO: add BUS_NOTIFY_BIND_DRIVER and increase idle count */
291 case BUS_NOTIFY_BOUND_DRIVER:
292 /* keep track of number of devices in use per hwblk */
293 hwblk_cnt_inc(hwblk_info, hwblk, HWBLK_CNT_DEVICES);
294 break;
295 case BUS_NOTIFY_UNBOUND_DRIVER:
296 /* keep track of number of devices in use per hwblk */
297 hwblk_cnt_dec(hwblk_info, hwblk, HWBLK_CNT_DEVICES);
298 /* make sure driver re-inits itself once */
299 __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
300 break;
301 case BUS_NOTIFY_DEL_DEVICE:
302 dev->pm_domain = NULL;
303 break;
304 }
305 return 0;
306}
307
308static struct notifier_block platform_bus_notifier = {
309 .notifier_call = platform_bus_notify
310};
311
312static int __init sh_pm_runtime_init(void)
313{
314 INIT_WORK(&hwblk_work, platform_pm_runtime_work);
315
316 bus_register_notifier(&platform_bus_type, &platform_bus_notifier);
317 return 0;
318}
319core_initcall(sh_pm_runtime_init);
diff --git a/arch/sh/kernel/entry-common.S b/arch/sh/kernel/entry-common.S
index 2b15ae60c3a0..f67601cb3f1f 100644
--- a/arch/sh/kernel/entry-common.S
+++ b/arch/sh/kernel/entry-common.S
@@ -145,6 +145,7 @@ work_notifysig:
145 mov r15, r4 145 mov r15, r4
146 mov r12, r5 ! set arg1(save_r0) 146 mov r12, r5 ! set arg1(save_r0)
147 mov r0, r6 147 mov r0, r6
148 sti
148 mov.l 2f, r1 149 mov.l 2f, r1
149 mov.l 3f, r0 150 mov.l 3f, r0
150 jmp @r1 151 jmp @r1
diff --git a/arch/sh/kernel/signal_32.c b/arch/sh/kernel/signal_32.c
index 579cd2ca358d..a7a55ed43a59 100644
--- a/arch/sh/kernel/signal_32.c
+++ b/arch/sh/kernel/signal_32.c
@@ -588,9 +588,6 @@ static void do_signal(struct pt_regs *regs, unsigned int save_r0)
588 if (!user_mode(regs)) 588 if (!user_mode(regs))
589 return; 589 return;
590 590
591 if (try_to_freeze())
592 goto no_signal;
593
594 if (current_thread_info()->status & TS_RESTORE_SIGMASK) 591 if (current_thread_info()->status & TS_RESTORE_SIGMASK)
595 oldset = &current->saved_sigmask; 592 oldset = &current->saved_sigmask;
596 else 593 else
@@ -618,7 +615,6 @@ static void do_signal(struct pt_regs *regs, unsigned int save_r0)
618 return; 615 return;
619 } 616 }
620 617
621no_signal:
622 /* Did we come from a system call? */ 618 /* Did we come from a system call? */
623 if (regs->tra >= 0) { 619 if (regs->tra >= 0) {
624 /* Restart the system call - no handlers present */ 620 /* Restart the system call - no handlers present */
diff --git a/arch/sh/kernel/signal_64.c b/arch/sh/kernel/signal_64.c
index 5a9f1f10ebf4..6b5603fe274b 100644
--- a/arch/sh/kernel/signal_64.c
+++ b/arch/sh/kernel/signal_64.c
@@ -98,9 +98,6 @@ static int do_signal(struct pt_regs *regs, sigset_t *oldset)
98 if (!user_mode(regs)) 98 if (!user_mode(regs))
99 return 1; 99 return 1;
100 100
101 if (try_to_freeze())
102 goto no_signal;
103
104 if (current_thread_info()->status & TS_RESTORE_SIGMASK) 101 if (current_thread_info()->status & TS_RESTORE_SIGMASK)
105 oldset = &current->saved_sigmask; 102 oldset = &current->saved_sigmask;
106 else if (!oldset) 103 else if (!oldset)
@@ -125,7 +122,6 @@ static int do_signal(struct pt_regs *regs, sigset_t *oldset)
125 } 122 }
126 } 123 }
127 124
128no_signal:
129 /* Did we come from a system call? */ 125 /* Did we come from a system call? */
130 if (regs->syscall_nr >= 0) { 126 if (regs->syscall_nr >= 0) {
131 /* Restart the system call - no handlers present */ 127 /* Restart the system call - no handlers present */
diff --git a/arch/sh/kernel/time.c b/arch/sh/kernel/time.c
index 8a0072de2bcc..552c8fcf9416 100644
--- a/arch/sh/kernel/time.c
+++ b/arch/sh/kernel/time.c
@@ -21,7 +21,6 @@
21#include <linux/smp.h> 21#include <linux/smp.h>
22#include <linux/rtc.h> 22#include <linux/rtc.h>
23#include <asm/clock.h> 23#include <asm/clock.h>
24#include <asm/hwblk.h>
25#include <asm/rtc.h> 24#include <asm/rtc.h>
26 25
27/* Dummy RTC ops */ 26/* Dummy RTC ops */
@@ -110,7 +109,6 @@ void __init time_init(void)
110 if (board_time_init) 109 if (board_time_init)
111 board_time_init(); 110 board_time_init();
112 111
113 hwblk_init();
114 clk_init(); 112 clk_init();
115 113
116 late_time_init = sh_late_time_init; 114 late_time_init = sh_late_time_init;
diff --git a/arch/sh/mm/cache-sh2a.c b/arch/sh/mm/cache-sh2a.c
index 1f51225426a2..ae08cbbfa569 100644
--- a/arch/sh/mm/cache-sh2a.c
+++ b/arch/sh/mm/cache-sh2a.c
@@ -15,35 +15,78 @@
15#include <asm/cacheflush.h> 15#include <asm/cacheflush.h>
16#include <asm/io.h> 16#include <asm/io.h>
17 17
18/*
19 * The maximum number of pages we support up to when doing ranged dcache
20 * flushing. Anything exceeding this will simply flush the dcache in its
21 * entirety.
22 */
23#define MAX_OCACHE_PAGES 32
24#define MAX_ICACHE_PAGES 32
25
26static void sh2a_flush_oc_line(unsigned long v, int way)
27{
28 unsigned long addr = (v & 0x000007f0) | (way << 11);
29 unsigned long data;
30
31 data = __raw_readl(CACHE_OC_ADDRESS_ARRAY | addr);
32 if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
33 data &= ~SH_CACHE_UPDATED;
34 __raw_writel(data, CACHE_OC_ADDRESS_ARRAY | addr);
35 }
36}
37
38static void sh2a_invalidate_line(unsigned long cache_addr, unsigned long v)
39{
40 /* Set associative bit to hit all ways */
41 unsigned long addr = (v & 0x000007f0) | SH_CACHE_ASSOC;
42 __raw_writel((addr & CACHE_PHYSADDR_MASK), cache_addr | addr);
43}
44
45/*
46 * Write back the dirty D-caches, but not invalidate them.
47 */
18static void sh2a__flush_wback_region(void *start, int size) 48static void sh2a__flush_wback_region(void *start, int size)
19{ 49{
50#ifdef CONFIG_CACHE_WRITEBACK
20 unsigned long v; 51 unsigned long v;
21 unsigned long begin, end; 52 unsigned long begin, end;
22 unsigned long flags; 53 unsigned long flags;
54 int nr_ways;
23 55
24 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); 56 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
25 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) 57 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
26 & ~(L1_CACHE_BYTES-1); 58 & ~(L1_CACHE_BYTES-1);
59 nr_ways = current_cpu_data.dcache.ways;
27 60
28 local_irq_save(flags); 61 local_irq_save(flags);
29 jump_to_uncached(); 62 jump_to_uncached();
30 63
31 for (v = begin; v < end; v+=L1_CACHE_BYTES) { 64 /* If there are too many pages then flush the entire cache */
32 unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0); 65 if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) {
66 begin = CACHE_OC_ADDRESS_ARRAY;
67 end = begin + (nr_ways * current_cpu_data.dcache.way_size);
68
69 for (v = begin; v < end; v += L1_CACHE_BYTES) {
70 unsigned long data = __raw_readl(v);
71 if (data & SH_CACHE_UPDATED)
72 __raw_writel(data & ~SH_CACHE_UPDATED, v);
73 }
74 } else {
33 int way; 75 int way;
34 for (way = 0; way < 4; way++) { 76 for (way = 0; way < nr_ways; way++) {
35 unsigned long data = __raw_readl(addr | (way << 11)); 77 for (v = begin; v < end; v += L1_CACHE_BYTES)
36 if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) { 78 sh2a_flush_oc_line(v, way);
37 data &= ~SH_CACHE_UPDATED;
38 __raw_writel(data, addr | (way << 11));
39 }
40 } 79 }
41 } 80 }
42 81
43 back_to_cached(); 82 back_to_cached();
44 local_irq_restore(flags); 83 local_irq_restore(flags);
84#endif
45} 85}
46 86
87/*
88 * Write back the dirty D-caches and invalidate them.
89 */
47static void sh2a__flush_purge_region(void *start, int size) 90static void sh2a__flush_purge_region(void *start, int size)
48{ 91{
49 unsigned long v; 92 unsigned long v;
@@ -58,13 +101,22 @@ static void sh2a__flush_purge_region(void *start, int size)
58 jump_to_uncached(); 101 jump_to_uncached();
59 102
60 for (v = begin; v < end; v+=L1_CACHE_BYTES) { 103 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
61 __raw_writel((v & CACHE_PHYSADDR_MASK), 104#ifdef CONFIG_CACHE_WRITEBACK
62 CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); 105 int way;
106 int nr_ways = current_cpu_data.dcache.ways;
107 for (way = 0; way < nr_ways; way++)
108 sh2a_flush_oc_line(v, way);
109#endif
110 sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
63 } 111 }
112
64 back_to_cached(); 113 back_to_cached();
65 local_irq_restore(flags); 114 local_irq_restore(flags);
66} 115}
67 116
117/*
118 * Invalidate the D-caches, but no write back please
119 */
68static void sh2a__flush_invalidate_region(void *start, int size) 120static void sh2a__flush_invalidate_region(void *start, int size)
69{ 121{
70 unsigned long v; 122 unsigned long v;
@@ -74,29 +126,25 @@ static void sh2a__flush_invalidate_region(void *start, int size)
74 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); 126 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
75 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) 127 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
76 & ~(L1_CACHE_BYTES-1); 128 & ~(L1_CACHE_BYTES-1);
129
77 local_irq_save(flags); 130 local_irq_save(flags);
78 jump_to_uncached(); 131 jump_to_uncached();
79 132
80#ifdef CONFIG_CACHE_WRITEBACK 133 /* If there are too many pages then just blow the cache */
81 __raw_writel(__raw_readl(CCR) | CCR_OCACHE_INVALIDATE, CCR); 134 if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) {
82 /* I-cache invalidate */ 135 __raw_writel(__raw_readl(CCR) | CCR_OCACHE_INVALIDATE, CCR);
83 for (v = begin; v < end; v+=L1_CACHE_BYTES) { 136 } else {
84 __raw_writel((v & CACHE_PHYSADDR_MASK), 137 for (v = begin; v < end; v += L1_CACHE_BYTES)
85 CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); 138 sh2a_invalidate_line(CACHE_OC_ADDRESS_ARRAY, v);
86 }
87#else
88 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
89 __raw_writel((v & CACHE_PHYSADDR_MASK),
90 CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
91 __raw_writel((v & CACHE_PHYSADDR_MASK),
92 CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
93 } 139 }
94#endif 140
95 back_to_cached(); 141 back_to_cached();
96 local_irq_restore(flags); 142 local_irq_restore(flags);
97} 143}
98 144
99/* WBack O-Cache and flush I-Cache */ 145/*
146 * Write back the range of D-cache, and purge the I-cache.
147 */
100static void sh2a_flush_icache_range(void *args) 148static void sh2a_flush_icache_range(void *args)
101{ 149{
102 struct flusher_data *data = args; 150 struct flusher_data *data = args;
@@ -107,23 +155,20 @@ static void sh2a_flush_icache_range(void *args)
107 start = data->addr1 & ~(L1_CACHE_BYTES-1); 155 start = data->addr1 & ~(L1_CACHE_BYTES-1);
108 end = (data->addr2 + L1_CACHE_BYTES-1) & ~(L1_CACHE_BYTES-1); 156 end = (data->addr2 + L1_CACHE_BYTES-1) & ~(L1_CACHE_BYTES-1);
109 157
158#ifdef CONFIG_CACHE_WRITEBACK
159 sh2a__flush_wback_region((void *)start, end-start);
160#endif
161
110 local_irq_save(flags); 162 local_irq_save(flags);
111 jump_to_uncached(); 163 jump_to_uncached();
112 164
113 for (v = start; v < end; v+=L1_CACHE_BYTES) { 165 /* I-Cache invalidate */
114 unsigned long addr = (v & 0x000007f0); 166 /* If there are too many pages then just blow the cache */
115 int way; 167 if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) {
116 /* O-Cache writeback */ 168 __raw_writel(__raw_readl(CCR) | CCR_ICACHE_INVALIDATE, CCR);
117 for (way = 0; way < 4; way++) { 169 } else {
118 unsigned long data = __raw_readl(CACHE_OC_ADDRESS_ARRAY | addr | (way << 11)); 170 for (v = start; v < end; v += L1_CACHE_BYTES)
119 if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) { 171 sh2a_invalidate_line(CACHE_IC_ADDRESS_ARRAY, v);
120 data &= ~SH_CACHE_UPDATED;
121 __raw_writel(data, CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
122 }
123 }
124 /* I-Cache invalidate */
125 __raw_writel(addr,
126 CACHE_IC_ADDRESS_ARRAY | addr | 0x00000008);
127 } 172 }
128 173
129 back_to_cached(); 174 back_to_cached();
diff --git a/arch/sparc/include/asm/pci_32.h b/arch/sparc/include/asm/pci_32.h
index 02939abd356c..6de7f7bf956a 100644
--- a/arch/sparc/include/asm/pci_32.h
+++ b/arch/sparc/include/asm/pci_32.h
@@ -16,11 +16,6 @@
16 16
17#define PCI_IRQ_NONE 0xffffffff 17#define PCI_IRQ_NONE 0xffffffff
18 18
19static inline void pcibios_set_master(struct pci_dev *dev)
20{
21 /* No special bus mastering setup handling */
22}
23
24static inline void pcibios_penalize_isa_irq(int irq, int active) 19static inline void pcibios_penalize_isa_irq(int irq, int active)
25{ 20{
26 /* We don't do dynamic PCI IRQ allocation */ 21 /* We don't do dynamic PCI IRQ allocation */
diff --git a/arch/sparc/include/asm/pci_64.h b/arch/sparc/include/asm/pci_64.h
index 2614d96141c9..755a4bb6bcd3 100644
--- a/arch/sparc/include/asm/pci_64.h
+++ b/arch/sparc/include/asm/pci_64.h
@@ -16,11 +16,6 @@
16 16
17#define PCI_IRQ_NONE 0xffffffff 17#define PCI_IRQ_NONE 0xffffffff
18 18
19static inline void pcibios_set_master(struct pci_dev *dev)
20{
21 /* No special bus mastering setup handling */
22}
23
24static inline void pcibios_penalize_isa_irq(int irq, int active) 19static inline void pcibios_penalize_isa_irq(int irq, int active)
25{ 20{
26 /* We don't do dynamic PCI IRQ allocation */ 21 /* We don't do dynamic PCI IRQ allocation */
diff --git a/arch/sparc/kernel/leon_pci.c b/arch/sparc/kernel/leon_pci.c
index f1cf6ef011a7..c7bec25fdb1c 100644
--- a/arch/sparc/kernel/leon_pci.c
+++ b/arch/sparc/kernel/leon_pci.c
@@ -19,22 +19,22 @@
19 */ 19 */
20void leon_pci_init(struct platform_device *ofdev, struct leon_pci_info *info) 20void leon_pci_init(struct platform_device *ofdev, struct leon_pci_info *info)
21{ 21{
22 LIST_HEAD(resources);
22 struct pci_bus *root_bus; 23 struct pci_bus *root_bus;
23 24
24 root_bus = pci_scan_bus_parented(&ofdev->dev, 0, info->ops, info); 25 pci_add_resource(&resources, &info->io_space);
25 if (root_bus) { 26 pci_add_resource(&resources, &info->mem_space);
26 root_bus->resource[0] = &info->io_space;
27 root_bus->resource[1] = &info->mem_space;
28 root_bus->resource[2] = NULL;
29
30 /* Init all PCI devices into PCI tree */
31 pci_bus_add_devices(root_bus);
32 27
28 root_bus = pci_scan_root_bus(&ofdev->dev, 0, info->ops, info,
29 &resources);
30 if (root_bus) {
33 /* Setup IRQs of all devices using custom routines */ 31 /* Setup IRQs of all devices using custom routines */
34 pci_fixup_irqs(pci_common_swizzle, info->map_irq); 32 pci_fixup_irqs(pci_common_swizzle, info->map_irq);
35 33
36 /* Assign devices with resources */ 34 /* Assign devices with resources */
37 pci_assign_unassigned_resources(); 35 pci_assign_unassigned_resources();
36 } else {
37 pci_free_resource_list(&resources);
38 } 38 }
39} 39}
40 40
@@ -83,15 +83,6 @@ void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
83 int i, has_io, has_mem; 83 int i, has_io, has_mem;
84 u16 cmd; 84 u16 cmd;
85 85
86 /* Generic PCI bus probing sets these to point at
87 * &io{port,mem}_resouce which is wrong for us.
88 */
89 if (pbus->self == NULL) {
90 pbus->resource[0] = &info->io_space;
91 pbus->resource[1] = &info->mem_space;
92 pbus->resource[2] = NULL;
93 }
94
95 list_for_each_entry(dev, &pbus->devices, bus_list) { 86 list_for_each_entry(dev, &pbus->devices, bus_list) {
96 /* 87 /*
97 * We can not rely on that the bootloader has enabled I/O 88 * We can not rely on that the bootloader has enabled I/O
diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c
index 31111e35281e..bb8bc2e519ac 100644
--- a/arch/sparc/kernel/pci.c
+++ b/arch/sparc/kernel/pci.c
@@ -685,23 +685,25 @@ static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
685struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm, 685struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm,
686 struct device *parent) 686 struct device *parent)
687{ 687{
688 LIST_HEAD(resources);
688 struct device_node *node = pbm->op->dev.of_node; 689 struct device_node *node = pbm->op->dev.of_node;
689 struct pci_bus *bus; 690 struct pci_bus *bus;
690 691
691 printk("PCI: Scanning PBM %s\n", node->full_name); 692 printk("PCI: Scanning PBM %s\n", node->full_name);
692 693
693 bus = pci_create_bus(parent, pbm->pci_first_busno, pbm->pci_ops, pbm); 694 pci_add_resource(&resources, &pbm->io_space);
695 pci_add_resource(&resources, &pbm->mem_space);
696 bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
697 pbm, &resources);
694 if (!bus) { 698 if (!bus) {
695 printk(KERN_ERR "Failed to create bus for %s\n", 699 printk(KERN_ERR "Failed to create bus for %s\n",
696 node->full_name); 700 node->full_name);
701 pci_free_resource_list(&resources);
697 return NULL; 702 return NULL;
698 } 703 }
699 bus->secondary = pbm->pci_first_busno; 704 bus->secondary = pbm->pci_first_busno;
700 bus->subordinate = pbm->pci_last_busno; 705 bus->subordinate = pbm->pci_last_busno;
701 706
702 bus->resource[0] = &pbm->io_space;
703 bus->resource[1] = &pbm->mem_space;
704
705 pci_of_scan_bus(pbm, node, bus); 707 pci_of_scan_bus(pbm, node, bus);
706 pci_bus_add_devices(bus); 708 pci_bus_add_devices(bus);
707 pci_bus_register_of_sysfs(bus); 709 pci_bus_register_of_sysfs(bus);
@@ -711,13 +713,6 @@ struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm,
711 713
712void __devinit pcibios_fixup_bus(struct pci_bus *pbus) 714void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
713{ 715{
714 struct pci_pbm_info *pbm = pbus->sysdata;
715
716 /* Generic PCI bus probing sets these to point at
717 * &io{port,mem}_resouce which is wrong for us.
718 */
719 pbus->resource[0] = &pbm->io_space;
720 pbus->resource[1] = &pbm->mem_space;
721} 716}
722 717
723void pcibios_update_irq(struct pci_dev *pdev, int irq) 718void pcibios_update_irq(struct pci_dev *pdev, int irq)
@@ -1083,6 +1078,11 @@ void pci_resource_to_user(const struct pci_dev *pdev, int bar,
1083 *end = rp->end - offset; 1078 *end = rp->end - offset;
1084} 1079}
1085 1080
1081void pcibios_set_master(struct pci_dev *dev)
1082{
1083 /* No special bus mastering setup handling */
1084}
1085
1086static int __init pcibios_init(void) 1086static int __init pcibios_init(void)
1087{ 1087{
1088 pci_dfl_cache_line_size = 64 >> 2; 1088 pci_dfl_cache_line_size = 64 >> 2;
diff --git a/arch/tile/include/asm/pci.h b/arch/tile/include/asm/pci.h
index 1d25fea42e54..5d5a635530bd 100644
--- a/arch/tile/include/asm/pci.h
+++ b/arch/tile/include/asm/pci.h
@@ -76,13 +76,6 @@ static inline int pcibios_assign_all_busses(void)
76 return 1; 76 return 1;
77} 77}
78 78
79/*
80 * No special bus mastering setup handling.
81 */
82static inline void pcibios_set_master(struct pci_dev *dev)
83{
84}
85
86#define PCIBIOS_MIN_MEM 0 79#define PCIBIOS_MIN_MEM 0
87#define PCIBIOS_MIN_IO 0 80#define PCIBIOS_MIN_IO 0
88 81
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
index 25567934a21e..a1bb59eecc18 100644
--- a/arch/tile/kernel/pci.c
+++ b/arch/tile/kernel/pci.c
@@ -395,6 +395,11 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
395 /* Nothing needs to be done. */ 395 /* Nothing needs to be done. */
396} 396}
397 397
398void pcibios_set_master(struct pci_dev *dev)
399{
400 /* No special bus mastering setup handling. */
401}
402
398/* 403/*
399 * This can be called from the generic PCI layer, but doesn't need to 404 * This can be called from the generic PCI layer, but doesn't need to
400 * do anything. 405 * do anything.
diff --git a/arch/um/Kconfig.common b/arch/um/Kconfig.common
index a9234838e8a2..b37ae706af3e 100644
--- a/arch/um/Kconfig.common
+++ b/arch/um/Kconfig.common
@@ -8,6 +8,7 @@ config UML
8 default y 8 default y
9 select HAVE_GENERIC_HARDIRQS 9 select HAVE_GENERIC_HARDIRQS
10 select GENERIC_IRQ_SHOW 10 select GENERIC_IRQ_SHOW
11 select GENERIC_CPU_DEVICES
11 12
12config MMU 13config MMU
13 bool 14 bool
diff --git a/arch/unicore32/include/asm/pci.h b/arch/unicore32/include/asm/pci.h
index c5b28b459535..dd3867727c35 100644
--- a/arch/unicore32/include/asm/pci.h
+++ b/arch/unicore32/include/asm/pci.h
@@ -17,11 +17,6 @@
17#include <asm-generic/pci.h> 17#include <asm-generic/pci.h>
18#include <mach/hardware.h> /* for PCIBIOS_MIN_* */ 18#include <mach/hardware.h> /* for PCIBIOS_MIN_* */
19 19
20static inline void pcibios_set_master(struct pci_dev *dev)
21{
22 /* No special bus mastering setup handling */
23}
24
25static inline void pcibios_penalize_isa_irq(int irq, int active) 20static inline void pcibios_penalize_isa_irq(int irq, int active)
26{ 21{
27 /* We don't do dynamic PCI IRQ allocation */ 22 /* We don't do dynamic PCI IRQ allocation */
diff --git a/arch/unicore32/kernel/pci.c b/arch/unicore32/kernel/pci.c
index 4892fbb54ebf..a8f07fe10cad 100644
--- a/arch/unicore32/kernel/pci.c
+++ b/arch/unicore32/kernel/pci.c
@@ -309,6 +309,11 @@ char * __devinit pcibios_setup(char *str)
309 return str; 309 return str;
310} 310}
311 311
312void pcibios_set_master(struct pci_dev *dev)
313{
314 /* No special bus mastering setup handling */
315}
316
312/* 317/*
313 * From arch/i386/kernel/pci-i386.c: 318 * From arch/i386/kernel/pci-i386.c:
314 * 319 *
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 1a31254ceb83..a150f4c35e94 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -420,12 +420,14 @@ config X86_MRST
420 depends on PCI 420 depends on PCI
421 depends on PCI_GOANY 421 depends on PCI_GOANY
422 depends on X86_IO_APIC 422 depends on X86_IO_APIC
423 select X86_INTEL_MID
424 select SFI
425 select DW_APB_TIMER
423 select APB_TIMER 426 select APB_TIMER
424 select I2C 427 select I2C
425 select SPI 428 select SPI
426 select INTEL_SCU_IPC 429 select INTEL_SCU_IPC
427 select X86_PLATFORM_DEVICES 430 select X86_PLATFORM_DEVICES
428 select X86_INTEL_MID
429 ---help--- 431 ---help---
430 Moorestown is Intel's Low Power Intel Architecture (LPIA) based Moblin 432 Moorestown is Intel's Low Power Intel Architecture (LPIA) based Moblin
431 Internet Device(MID) platform. Moorestown consists of two chips: 433 Internet Device(MID) platform. Moorestown consists of two chips:
@@ -434,6 +436,26 @@ config X86_MRST
434 nor standard legacy replacement devices/features. e.g. Moorestown does 436 nor standard legacy replacement devices/features. e.g. Moorestown does
435 not contain i8259, i8254, HPET, legacy BIOS, most of the io ports. 437 not contain i8259, i8254, HPET, legacy BIOS, most of the io ports.
436 438
439config X86_MDFLD
440 bool "Medfield MID platform"
441 depends on PCI
442 depends on PCI_GOANY
443 depends on X86_IO_APIC
444 select X86_INTEL_MID
445 select SFI
446 select DW_APB_TIMER
447 select APB_TIMER
448 select I2C
449 select SPI
450 select INTEL_SCU_IPC
451 select X86_PLATFORM_DEVICES
452 ---help---
453 Medfield is Intel's Low Power Intel Architecture (LPIA) based Moblin
454 Internet Device(MID) platform.
455 Unlike standard x86 PCs, Medfield does not have many legacy devices
456 nor standard legacy replacement devices/features. e.g. Medfield does
457 not contain i8259, i8254, HPET, legacy BIOS, most of the io ports.
458
437endif 459endif
438 460
439config X86_RDC321X 461config X86_RDC321X
@@ -631,7 +653,7 @@ config X86_SUMMIT_NUMA
631 653
632config X86_CYCLONE_TIMER 654config X86_CYCLONE_TIMER
633 def_bool y 655 def_bool y
634 depends on X86_32_NON_STANDARD 656 depends on X86_SUMMIT
635 657
636source "arch/x86/Kconfig.cpu" 658source "arch/x86/Kconfig.cpu"
637 659
@@ -659,9 +681,10 @@ config HPET_EMULATE_RTC
659 depends on HPET_TIMER && (RTC=y || RTC=m || RTC_DRV_CMOS=m || RTC_DRV_CMOS=y) 681 depends on HPET_TIMER && (RTC=y || RTC=m || RTC_DRV_CMOS=m || RTC_DRV_CMOS=y)
660 682
661config APB_TIMER 683config APB_TIMER
662 def_bool y if MRST 684 def_bool y if X86_INTEL_MID
663 prompt "Langwell APB Timer Support" if X86_MRST 685 prompt "Intel MID APB Timer Support" if X86_INTEL_MID
664 select DW_APB_TIMER 686 select DW_APB_TIMER
687 depends on X86_INTEL_MID && SFI
665 help 688 help
666 APB timer is the replacement for 8254, HPET on X86 MID platforms. 689 APB timer is the replacement for 8254, HPET on X86 MID platforms.
667 The APBT provides a stable time base on SMP 690 The APBT provides a stable time base on SMP
@@ -1489,6 +1512,13 @@ config EFI
1489 resultant kernel should continue to boot on existing non-EFI 1512 resultant kernel should continue to boot on existing non-EFI
1490 platforms. 1513 platforms.
1491 1514
1515config EFI_STUB
1516 bool "EFI stub support"
1517 depends on EFI
1518 ---help---
1519 This kernel feature allows a bzImage to be loaded directly
1520 by EFI firmware without the use of a bootloader.
1521
1492config SECCOMP 1522config SECCOMP
1493 def_bool y 1523 def_bool y
1494 prompt "Enable seccomp to safely compute untrusted bytecode" 1524 prompt "Enable seccomp to safely compute untrusted bytecode"
diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug
index bf56e1793272..e46c2147397f 100644
--- a/arch/x86/Kconfig.debug
+++ b/arch/x86/Kconfig.debug
@@ -43,9 +43,9 @@ config EARLY_PRINTK
43 with klogd/syslogd or the X server. You should normally N here, 43 with klogd/syslogd or the X server. You should normally N here,
44 unless you want to debug such a crash. 44 unless you want to debug such a crash.
45 45
46config EARLY_PRINTK_MRST 46config EARLY_PRINTK_INTEL_MID
47 bool "Early printk for MRST platform support" 47 bool "Early printk for Intel MID platform support"
48 depends on EARLY_PRINTK && X86_MRST 48 depends on EARLY_PRINTK && X86_INTEL_MID
49 49
50config EARLY_PRINTK_DBGP 50config EARLY_PRINTK_DBGP
51 bool "Early printk via EHCI debug port" 51 bool "Early printk via EHCI debug port"
@@ -63,8 +63,11 @@ config DEBUG_STACKOVERFLOW
63 bool "Check for stack overflows" 63 bool "Check for stack overflows"
64 depends on DEBUG_KERNEL 64 depends on DEBUG_KERNEL
65 ---help--- 65 ---help---
66 This option will cause messages to be printed if free stack space 66 Say Y here if you want to check the overflows of kernel, IRQ
67 drops below a certain limit. 67 and exception stacks. This option will cause messages of the
68 stacks in detail when free stack space drops below a certain
69 limit.
70 If in doubt, say "N".
68 71
69config X86_PTDUMP 72config X86_PTDUMP
70 bool "Export kernel pagetable layout to userspace via debugfs" 73 bool "Export kernel pagetable layout to userspace via debugfs"
@@ -284,4 +287,16 @@ config DEBUG_STRICT_USER_COPY_CHECKS
284 287
285 If unsure, or if you run an older (pre 4.4) gcc, say N. 288 If unsure, or if you run an older (pre 4.4) gcc, say N.
286 289
290config DEBUG_NMI_SELFTEST
291 bool "NMI Selftest"
292 depends on DEBUG_KERNEL && X86_LOCAL_APIC
293 ---help---
294 Enabling this option turns on a quick NMI selftest to verify
295 that the NMI behaves correctly.
296
297 This might help diagnose strange hangs that rely on NMI to
298 function properly.
299
300 If unsure, say N.
301
287endmenu 302endmenu
diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile
index 09664efb9cee..b123b9a8f5b3 100644
--- a/arch/x86/boot/compressed/Makefile
+++ b/arch/x86/boot/compressed/Makefile
@@ -23,7 +23,15 @@ LDFLAGS_vmlinux := -T
23 23
24hostprogs-y := mkpiggy 24hostprogs-y := mkpiggy
25 25
26$(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/head_$(BITS).o $(obj)/misc.o $(obj)/string.o $(obj)/cmdline.o $(obj)/early_serial_console.o $(obj)/piggy.o FORCE 26VMLINUX_OBJS = $(obj)/vmlinux.lds $(obj)/head_$(BITS).o $(obj)/misc.o \
27 $(obj)/string.o $(obj)/cmdline.o $(obj)/early_serial_console.o \
28 $(obj)/piggy.o
29
30ifeq ($(CONFIG_EFI_STUB), y)
31 VMLINUX_OBJS += $(obj)/eboot.o $(obj)/efi_stub_$(BITS).o
32endif
33
34$(obj)/vmlinux: $(VMLINUX_OBJS) FORCE
27 $(call if_changed,ld) 35 $(call if_changed,ld)
28 @: 36 @:
29 37
diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c
new file mode 100644
index 000000000000..fec216f4fbc3
--- /dev/null
+++ b/arch/x86/boot/compressed/eboot.c
@@ -0,0 +1,1022 @@
1/* -----------------------------------------------------------------------
2 *
3 * Copyright 2011 Intel Corporation; author Matt Fleming
4 *
5 * This file is part of the Linux kernel, and is made available under
6 * the terms of the GNU General Public License version 2.
7 *
8 * ----------------------------------------------------------------------- */
9
10#include <linux/efi.h>
11#include <asm/efi.h>
12#include <asm/setup.h>
13#include <asm/desc.h>
14
15#include "eboot.h"
16
17static efi_system_table_t *sys_table;
18
19static efi_status_t __get_map(efi_memory_desc_t **map, unsigned long *map_size,
20 unsigned long *desc_size)
21{
22 efi_memory_desc_t *m = NULL;
23 efi_status_t status;
24 unsigned long key;
25 u32 desc_version;
26
27 *map_size = sizeof(*m) * 32;
28again:
29 /*
30 * Add an additional efi_memory_desc_t because we're doing an
31 * allocation which may be in a new descriptor region.
32 */
33 *map_size += sizeof(*m);
34 status = efi_call_phys3(sys_table->boottime->allocate_pool,
35 EFI_LOADER_DATA, *map_size, (void **)&m);
36 if (status != EFI_SUCCESS)
37 goto fail;
38
39 status = efi_call_phys5(sys_table->boottime->get_memory_map, map_size,
40 m, &key, desc_size, &desc_version);
41 if (status == EFI_BUFFER_TOO_SMALL) {
42 efi_call_phys1(sys_table->boottime->free_pool, m);
43 goto again;
44 }
45
46 if (status != EFI_SUCCESS)
47 efi_call_phys1(sys_table->boottime->free_pool, m);
48
49fail:
50 *map = m;
51 return status;
52}
53
54/*
55 * Allocate at the highest possible address that is not above 'max'.
56 */
57static efi_status_t high_alloc(unsigned long size, unsigned long align,
58 unsigned long *addr, unsigned long max)
59{
60 unsigned long map_size, desc_size;
61 efi_memory_desc_t *map;
62 efi_status_t status;
63 unsigned long nr_pages;
64 u64 max_addr = 0;
65 int i;
66
67 status = __get_map(&map, &map_size, &desc_size);
68 if (status != EFI_SUCCESS)
69 goto fail;
70
71 nr_pages = round_up(size, EFI_PAGE_SIZE) / EFI_PAGE_SIZE;
72again:
73 for (i = 0; i < map_size / desc_size; i++) {
74 efi_memory_desc_t *desc;
75 unsigned long m = (unsigned long)map;
76 u64 start, end;
77
78 desc = (efi_memory_desc_t *)(m + (i * desc_size));
79 if (desc->type != EFI_CONVENTIONAL_MEMORY)
80 continue;
81
82 if (desc->num_pages < nr_pages)
83 continue;
84
85 start = desc->phys_addr;
86 end = start + desc->num_pages * (1UL << EFI_PAGE_SHIFT);
87
88 if ((start + size) > end || (start + size) > max)
89 continue;
90
91 if (end - size > max)
92 end = max;
93
94 if (round_down(end - size, align) < start)
95 continue;
96
97 start = round_down(end - size, align);
98
99 /*
100 * Don't allocate at 0x0. It will confuse code that
101 * checks pointers against NULL.
102 */
103 if (start == 0x0)
104 continue;
105
106 if (start > max_addr)
107 max_addr = start;
108 }
109
110 if (!max_addr)
111 status = EFI_NOT_FOUND;
112 else {
113 status = efi_call_phys4(sys_table->boottime->allocate_pages,
114 EFI_ALLOCATE_ADDRESS, EFI_LOADER_DATA,
115 nr_pages, &max_addr);
116 if (status != EFI_SUCCESS) {
117 max = max_addr;
118 max_addr = 0;
119 goto again;
120 }
121
122 *addr = max_addr;
123 }
124
125free_pool:
126 efi_call_phys1(sys_table->boottime->free_pool, map);
127
128fail:
129 return status;
130}
131
132/*
133 * Allocate at the lowest possible address.
134 */
135static efi_status_t low_alloc(unsigned long size, unsigned long align,
136 unsigned long *addr)
137{
138 unsigned long map_size, desc_size;
139 efi_memory_desc_t *map;
140 efi_status_t status;
141 unsigned long nr_pages;
142 int i;
143
144 status = __get_map(&map, &map_size, &desc_size);
145 if (status != EFI_SUCCESS)
146 goto fail;
147
148 nr_pages = round_up(size, EFI_PAGE_SIZE) / EFI_PAGE_SIZE;
149 for (i = 0; i < map_size / desc_size; i++) {
150 efi_memory_desc_t *desc;
151 unsigned long m = (unsigned long)map;
152 u64 start, end;
153
154 desc = (efi_memory_desc_t *)(m + (i * desc_size));
155
156 if (desc->type != EFI_CONVENTIONAL_MEMORY)
157 continue;
158
159 if (desc->num_pages < nr_pages)
160 continue;
161
162 start = desc->phys_addr;
163 end = start + desc->num_pages * (1UL << EFI_PAGE_SHIFT);
164
165 /*
166 * Don't allocate at 0x0. It will confuse code that
167 * checks pointers against NULL. Skip the first 8
168 * bytes so we start at a nice even number.
169 */
170 if (start == 0x0)
171 start += 8;
172
173 start = round_up(start, align);
174 if ((start + size) > end)
175 continue;
176
177 status = efi_call_phys4(sys_table->boottime->allocate_pages,
178 EFI_ALLOCATE_ADDRESS, EFI_LOADER_DATA,
179 nr_pages, &start);
180 if (status == EFI_SUCCESS) {
181 *addr = start;
182 break;
183 }
184 }
185
186 if (i == map_size / desc_size)
187 status = EFI_NOT_FOUND;
188
189free_pool:
190 efi_call_phys1(sys_table->boottime->free_pool, map);
191fail:
192 return status;
193}
194
195static void low_free(unsigned long size, unsigned long addr)
196{
197 unsigned long nr_pages;
198
199 nr_pages = round_up(size, EFI_PAGE_SIZE) / EFI_PAGE_SIZE;
200 efi_call_phys2(sys_table->boottime->free_pages, addr, size);
201}
202
203static void find_bits(unsigned long mask, u8 *pos, u8 *size)
204{
205 u8 first, len;
206
207 first = 0;
208 len = 0;
209
210 if (mask) {
211 while (!(mask & 0x1)) {
212 mask = mask >> 1;
213 first++;
214 }
215
216 while (mask & 0x1) {
217 mask = mask >> 1;
218 len++;
219 }
220 }
221
222 *pos = first;
223 *size = len;
224}
225
226/*
227 * See if we have Graphics Output Protocol
228 */
229static efi_status_t setup_gop(struct screen_info *si, efi_guid_t *proto,
230 unsigned long size)
231{
232 struct efi_graphics_output_protocol *gop, *first_gop;
233 struct efi_pixel_bitmask pixel_info;
234 unsigned long nr_gops;
235 efi_status_t status;
236 void **gop_handle;
237 u16 width, height;
238 u32 fb_base, fb_size;
239 u32 pixels_per_scan_line;
240 int pixel_format;
241 int i;
242
243 status = efi_call_phys3(sys_table->boottime->allocate_pool,
244 EFI_LOADER_DATA, size, &gop_handle);
245 if (status != EFI_SUCCESS)
246 return status;
247
248 status = efi_call_phys5(sys_table->boottime->locate_handle,
249 EFI_LOCATE_BY_PROTOCOL, proto,
250 NULL, &size, gop_handle);
251 if (status != EFI_SUCCESS)
252 goto free_handle;
253
254 first_gop = NULL;
255
256 nr_gops = size / sizeof(void *);
257 for (i = 0; i < nr_gops; i++) {
258 struct efi_graphics_output_mode_info *info;
259 efi_guid_t pciio_proto = EFI_PCI_IO_PROTOCOL_GUID;
260 void *pciio;
261 void *h = gop_handle[i];
262
263 status = efi_call_phys3(sys_table->boottime->handle_protocol,
264 h, proto, &gop);
265 if (status != EFI_SUCCESS)
266 continue;
267
268 efi_call_phys3(sys_table->boottime->handle_protocol,
269 h, &pciio_proto, &pciio);
270
271 status = efi_call_phys4(gop->query_mode, gop,
272 gop->mode->mode, &size, &info);
273 if (status == EFI_SUCCESS && (!first_gop || pciio)) {
274 /*
275 * Apple provide GOPs that are not backed by
276 * real hardware (they're used to handle
277 * multiple displays). The workaround is to
278 * search for a GOP implementing the PCIIO
279 * protocol, and if one isn't found, to just
280 * fallback to the first GOP.
281 */
282 width = info->horizontal_resolution;
283 height = info->vertical_resolution;
284 fb_base = gop->mode->frame_buffer_base;
285 fb_size = gop->mode->frame_buffer_size;
286 pixel_format = info->pixel_format;
287 pixel_info = info->pixel_information;
288 pixels_per_scan_line = info->pixels_per_scan_line;
289
290 /*
291 * Once we've found a GOP supporting PCIIO,
292 * don't bother looking any further.
293 */
294 if (pciio)
295 break;
296
297 first_gop = gop;
298 }
299 }
300
301 /* Did we find any GOPs? */
302 if (!first_gop)
303 goto free_handle;
304
305 /* EFI framebuffer */
306 si->orig_video_isVGA = VIDEO_TYPE_EFI;
307
308 si->lfb_width = width;
309 si->lfb_height = height;
310 si->lfb_base = fb_base;
311 si->lfb_size = fb_size;
312 si->pages = 1;
313
314 if (pixel_format == PIXEL_RGB_RESERVED_8BIT_PER_COLOR) {
315 si->lfb_depth = 32;
316 si->lfb_linelength = pixels_per_scan_line * 4;
317 si->red_size = 8;
318 si->red_pos = 0;
319 si->green_size = 8;
320 si->green_pos = 8;
321 si->blue_size = 8;
322 si->blue_pos = 16;
323 si->rsvd_size = 8;
324 si->rsvd_pos = 24;
325 } else if (pixel_format == PIXEL_BGR_RESERVED_8BIT_PER_COLOR) {
326 si->lfb_depth = 32;
327 si->lfb_linelength = pixels_per_scan_line * 4;
328 si->red_size = 8;
329 si->red_pos = 16;
330 si->green_size = 8;
331 si->green_pos = 8;
332 si->blue_size = 8;
333 si->blue_pos = 0;
334 si->rsvd_size = 8;
335 si->rsvd_pos = 24;
336 } else if (pixel_format == PIXEL_BIT_MASK) {
337 find_bits(pixel_info.red_mask, &si->red_pos, &si->red_size);
338 find_bits(pixel_info.green_mask, &si->green_pos,
339 &si->green_size);
340 find_bits(pixel_info.blue_mask, &si->blue_pos, &si->blue_size);
341 find_bits(pixel_info.reserved_mask, &si->rsvd_pos,
342 &si->rsvd_size);
343 si->lfb_depth = si->red_size + si->green_size +
344 si->blue_size + si->rsvd_size;
345 si->lfb_linelength = (pixels_per_scan_line * si->lfb_depth) / 8;
346 } else {
347 si->lfb_depth = 4;
348 si->lfb_linelength = si->lfb_width / 2;
349 si->red_size = 0;
350 si->red_pos = 0;
351 si->green_size = 0;
352 si->green_pos = 0;
353 si->blue_size = 0;
354 si->blue_pos = 0;
355 si->rsvd_size = 0;
356 si->rsvd_pos = 0;
357 }
358
359free_handle:
360 efi_call_phys1(sys_table->boottime->free_pool, gop_handle);
361 return status;
362}
363
364/*
365 * See if we have Universal Graphics Adapter (UGA) protocol
366 */
367static efi_status_t setup_uga(struct screen_info *si, efi_guid_t *uga_proto,
368 unsigned long size)
369{
370 struct efi_uga_draw_protocol *uga, *first_uga;
371 unsigned long nr_ugas;
372 efi_status_t status;
373 u32 width, height;
374 void **uga_handle = NULL;
375 int i;
376
377 status = efi_call_phys3(sys_table->boottime->allocate_pool,
378 EFI_LOADER_DATA, size, &uga_handle);
379 if (status != EFI_SUCCESS)
380 return status;
381
382 status = efi_call_phys5(sys_table->boottime->locate_handle,
383 EFI_LOCATE_BY_PROTOCOL, uga_proto,
384 NULL, &size, uga_handle);
385 if (status != EFI_SUCCESS)
386 goto free_handle;
387
388 first_uga = NULL;
389
390 nr_ugas = size / sizeof(void *);
391 for (i = 0; i < nr_ugas; i++) {
392 efi_guid_t pciio_proto = EFI_PCI_IO_PROTOCOL_GUID;
393 void *handle = uga_handle[i];
394 u32 w, h, depth, refresh;
395 void *pciio;
396
397 status = efi_call_phys3(sys_table->boottime->handle_protocol,
398 handle, uga_proto, &uga);
399 if (status != EFI_SUCCESS)
400 continue;
401
402 efi_call_phys3(sys_table->boottime->handle_protocol,
403 handle, &pciio_proto, &pciio);
404
405 status = efi_call_phys5(uga->get_mode, uga, &w, &h,
406 &depth, &refresh);
407 if (status == EFI_SUCCESS && (!first_uga || pciio)) {
408 width = w;
409 height = h;
410
411 /*
412 * Once we've found a UGA supporting PCIIO,
413 * don't bother looking any further.
414 */
415 if (pciio)
416 break;
417
418 first_uga = uga;
419 }
420 }
421
422 if (!first_uga)
423 goto free_handle;
424
425 /* EFI framebuffer */
426 si->orig_video_isVGA = VIDEO_TYPE_EFI;
427
428 si->lfb_depth = 32;
429 si->lfb_width = width;
430 si->lfb_height = height;
431
432 si->red_size = 8;
433 si->red_pos = 16;
434 si->green_size = 8;
435 si->green_pos = 8;
436 si->blue_size = 8;
437 si->blue_pos = 0;
438 si->rsvd_size = 8;
439 si->rsvd_pos = 24;
440
441
442free_handle:
443 efi_call_phys1(sys_table->boottime->free_pool, uga_handle);
444 return status;
445}
446
447void setup_graphics(struct boot_params *boot_params)
448{
449 efi_guid_t graphics_proto = EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID;
450 struct screen_info *si;
451 efi_guid_t uga_proto = EFI_UGA_PROTOCOL_GUID;
452 efi_status_t status;
453 unsigned long size;
454 void **gop_handle = NULL;
455 void **uga_handle = NULL;
456
457 si = &boot_params->screen_info;
458 memset(si, 0, sizeof(*si));
459
460 size = 0;
461 status = efi_call_phys5(sys_table->boottime->locate_handle,
462 EFI_LOCATE_BY_PROTOCOL, &graphics_proto,
463 NULL, &size, gop_handle);
464 if (status == EFI_BUFFER_TOO_SMALL)
465 status = setup_gop(si, &graphics_proto, size);
466
467 if (status != EFI_SUCCESS) {
468 size = 0;
469 status = efi_call_phys5(sys_table->boottime->locate_handle,
470 EFI_LOCATE_BY_PROTOCOL, &uga_proto,
471 NULL, &size, uga_handle);
472 if (status == EFI_BUFFER_TOO_SMALL)
473 setup_uga(si, &uga_proto, size);
474 }
475}
476
477struct initrd {
478 efi_file_handle_t *handle;
479 u64 size;
480};
481
482/*
483 * Check the cmdline for a LILO-style initrd= arguments.
484 *
485 * We only support loading an initrd from the same filesystem as the
486 * kernel image.
487 */
488static efi_status_t handle_ramdisks(efi_loaded_image_t *image,
489 struct setup_header *hdr)
490{
491 struct initrd *initrds;
492 unsigned long initrd_addr;
493 efi_guid_t fs_proto = EFI_FILE_SYSTEM_GUID;
494 u64 initrd_total;
495 efi_file_io_interface_t *io;
496 efi_file_handle_t *fh;
497 efi_status_t status;
498 int nr_initrds;
499 char *str;
500 int i, j, k;
501
502 initrd_addr = 0;
503 initrd_total = 0;
504
505 str = (char *)(unsigned long)hdr->cmd_line_ptr;
506
507 j = 0; /* See close_handles */
508
509 if (!str || !*str)
510 return EFI_SUCCESS;
511
512 for (nr_initrds = 0; *str; nr_initrds++) {
513 str = strstr(str, "initrd=");
514 if (!str)
515 break;
516
517 str += 7;
518
519 /* Skip any leading slashes */
520 while (*str == '/' || *str == '\\')
521 str++;
522
523 while (*str && *str != ' ' && *str != '\n')
524 str++;
525 }
526
527 if (!nr_initrds)
528 return EFI_SUCCESS;
529
530 status = efi_call_phys3(sys_table->boottime->allocate_pool,
531 EFI_LOADER_DATA,
532 nr_initrds * sizeof(*initrds),
533 &initrds);
534 if (status != EFI_SUCCESS)
535 goto fail;
536
537 str = (char *)(unsigned long)hdr->cmd_line_ptr;
538 for (i = 0; i < nr_initrds; i++) {
539 struct initrd *initrd;
540 efi_file_handle_t *h;
541 efi_file_info_t *info;
542 efi_char16_t filename[256];
543 unsigned long info_sz;
544 efi_guid_t info_guid = EFI_FILE_INFO_ID;
545 efi_char16_t *p;
546 u64 file_sz;
547
548 str = strstr(str, "initrd=");
549 if (!str)
550 break;
551
552 str += 7;
553
554 initrd = &initrds[i];
555 p = filename;
556
557 /* Skip any leading slashes */
558 while (*str == '/' || *str == '\\')
559 str++;
560
561 while (*str && *str != ' ' && *str != '\n') {
562 if (p >= filename + sizeof(filename))
563 break;
564
565 *p++ = *str++;
566 }
567
568 *p = '\0';
569
570 /* Only open the volume once. */
571 if (!i) {
572 efi_boot_services_t *boottime;
573
574 boottime = sys_table->boottime;
575
576 status = efi_call_phys3(boottime->handle_protocol,
577 image->device_handle, &fs_proto, &io);
578 if (status != EFI_SUCCESS)
579 goto free_initrds;
580
581 status = efi_call_phys2(io->open_volume, io, &fh);
582 if (status != EFI_SUCCESS)
583 goto free_initrds;
584 }
585
586 status = efi_call_phys5(fh->open, fh, &h, filename,
587 EFI_FILE_MODE_READ, (u64)0);
588 if (status != EFI_SUCCESS)
589 goto close_handles;
590
591 initrd->handle = h;
592
593 info_sz = 0;
594 status = efi_call_phys4(h->get_info, h, &info_guid,
595 &info_sz, NULL);
596 if (status != EFI_BUFFER_TOO_SMALL)
597 goto close_handles;
598
599grow:
600 status = efi_call_phys3(sys_table->boottime->allocate_pool,
601 EFI_LOADER_DATA, info_sz, &info);
602 if (status != EFI_SUCCESS)
603 goto close_handles;
604
605 status = efi_call_phys4(h->get_info, h, &info_guid,
606 &info_sz, info);
607 if (status == EFI_BUFFER_TOO_SMALL) {
608 efi_call_phys1(sys_table->boottime->free_pool, info);
609 goto grow;
610 }
611
612 file_sz = info->file_size;
613 efi_call_phys1(sys_table->boottime->free_pool, info);
614
615 if (status != EFI_SUCCESS)
616 goto close_handles;
617
618 initrd->size = file_sz;
619 initrd_total += file_sz;
620 }
621
622 if (initrd_total) {
623 unsigned long addr;
624
625 /*
626 * Multiple initrd's need to be at consecutive
627 * addresses in memory, so allocate enough memory for
628 * all the initrd's.
629 */
630 status = high_alloc(initrd_total, 0x1000,
631 &initrd_addr, hdr->initrd_addr_max);
632 if (status != EFI_SUCCESS)
633 goto close_handles;
634
635 /* We've run out of free low memory. */
636 if (initrd_addr > hdr->initrd_addr_max) {
637 status = EFI_INVALID_PARAMETER;
638 goto free_initrd_total;
639 }
640
641 addr = initrd_addr;
642 for (j = 0; j < nr_initrds; j++) {
643 u64 size;
644
645 size = initrds[j].size;
646 while (size) {
647 u64 chunksize;
648 if (size > EFI_READ_CHUNK_SIZE)
649 chunksize = EFI_READ_CHUNK_SIZE;
650 else
651 chunksize = size;
652 status = efi_call_phys3(fh->read,
653 initrds[j].handle,
654 &chunksize, addr);
655 if (status != EFI_SUCCESS)
656 goto free_initrd_total;
657 addr += chunksize;
658 size -= chunksize;
659 }
660
661 efi_call_phys1(fh->close, initrds[j].handle);
662 }
663
664 }
665
666 efi_call_phys1(sys_table->boottime->free_pool, initrds);
667
668 hdr->ramdisk_image = initrd_addr;
669 hdr->ramdisk_size = initrd_total;
670
671 return status;
672
673free_initrd_total:
674 low_free(initrd_total, initrd_addr);
675
676close_handles:
677 for (k = j; k < nr_initrds; k++)
678 efi_call_phys1(fh->close, initrds[k].handle);
679free_initrds:
680 efi_call_phys1(sys_table->boottime->free_pool, initrds);
681fail:
682 hdr->ramdisk_image = 0;
683 hdr->ramdisk_size = 0;
684
685 return status;
686}
687
688/*
689 * Because the x86 boot code expects to be passed a boot_params we
690 * need to create one ourselves (usually the bootloader would create
691 * one for us).
692 */
693static efi_status_t make_boot_params(struct boot_params *boot_params,
694 efi_loaded_image_t *image,
695 void *handle)
696{
697 struct efi_info *efi = &boot_params->efi_info;
698 struct apm_bios_info *bi = &boot_params->apm_bios_info;
699 struct sys_desc_table *sdt = &boot_params->sys_desc_table;
700 struct e820entry *e820_map = &boot_params->e820_map[0];
701 struct e820entry *prev = NULL;
702 struct setup_header *hdr = &boot_params->hdr;
703 unsigned long size, key, desc_size, _size;
704 efi_memory_desc_t *mem_map;
705 void *options = image->load_options;
706 u32 load_options_size = image->load_options_size / 2; /* ASCII */
707 int options_size = 0;
708 efi_status_t status;
709 __u32 desc_version;
710 unsigned long cmdline;
711 u8 nr_entries;
712 u16 *s2;
713 u8 *s1;
714 int i;
715
716 hdr->type_of_loader = 0x21;
717
718 /* Convert unicode cmdline to ascii */
719 cmdline = 0;
720 s2 = (u16 *)options;
721
722 if (s2) {
723 while (*s2 && *s2 != '\n' && options_size < load_options_size) {
724 s2++;
725 options_size++;
726 }
727
728 if (options_size) {
729 if (options_size > hdr->cmdline_size)
730 options_size = hdr->cmdline_size;
731
732 options_size++; /* NUL termination */
733
734 status = low_alloc(options_size, 1, &cmdline);
735 if (status != EFI_SUCCESS)
736 goto fail;
737
738 s1 = (u8 *)(unsigned long)cmdline;
739 s2 = (u16 *)options;
740
741 for (i = 0; i < options_size - 1; i++)
742 *s1++ = *s2++;
743
744 *s1 = '\0';
745 }
746 }
747
748 hdr->cmd_line_ptr = cmdline;
749
750 hdr->ramdisk_image = 0;
751 hdr->ramdisk_size = 0;
752
753 status = handle_ramdisks(image, hdr);
754 if (status != EFI_SUCCESS)
755 goto free_cmdline;
756
757 setup_graphics(boot_params);
758
759 /* Clear APM BIOS info */
760 memset(bi, 0, sizeof(*bi));
761
762 memset(sdt, 0, sizeof(*sdt));
763
764 memcpy(&efi->efi_loader_signature, EFI_LOADER_SIGNATURE, sizeof(__u32));
765
766 size = sizeof(*mem_map) * 32;
767
768again:
769 size += sizeof(*mem_map);
770 _size = size;
771 status = low_alloc(size, 1, (unsigned long *)&mem_map);
772 if (status != EFI_SUCCESS)
773 goto free_cmdline;
774
775 status = efi_call_phys5(sys_table->boottime->get_memory_map, &size,
776 mem_map, &key, &desc_size, &desc_version);
777 if (status == EFI_BUFFER_TOO_SMALL) {
778 low_free(_size, (unsigned long)mem_map);
779 goto again;
780 }
781
782 if (status != EFI_SUCCESS)
783 goto free_mem_map;
784
785 efi->efi_systab = (unsigned long)sys_table;
786 efi->efi_memdesc_size = desc_size;
787 efi->efi_memdesc_version = desc_version;
788 efi->efi_memmap = (unsigned long)mem_map;
789 efi->efi_memmap_size = size;
790
791#ifdef CONFIG_X86_64
792 efi->efi_systab_hi = (unsigned long)sys_table >> 32;
793 efi->efi_memmap_hi = (unsigned long)mem_map >> 32;
794#endif
795
796 /* Might as well exit boot services now */
797 status = efi_call_phys2(sys_table->boottime->exit_boot_services,
798 handle, key);
799 if (status != EFI_SUCCESS)
800 goto free_mem_map;
801
802 /* Historic? */
803 boot_params->alt_mem_k = 32 * 1024;
804
805 /*
806 * Convert the EFI memory map to E820.
807 */
808 nr_entries = 0;
809 for (i = 0; i < size / desc_size; i++) {
810 efi_memory_desc_t *d;
811 unsigned int e820_type = 0;
812 unsigned long m = (unsigned long)mem_map;
813
814 d = (efi_memory_desc_t *)(m + (i * desc_size));
815 switch (d->type) {
816 case EFI_RESERVED_TYPE:
817 case EFI_RUNTIME_SERVICES_CODE:
818 case EFI_RUNTIME_SERVICES_DATA:
819 case EFI_MEMORY_MAPPED_IO:
820 case EFI_MEMORY_MAPPED_IO_PORT_SPACE:
821 case EFI_PAL_CODE:
822 e820_type = E820_RESERVED;
823 break;
824
825 case EFI_UNUSABLE_MEMORY:
826 e820_type = E820_UNUSABLE;
827 break;
828
829 case EFI_ACPI_RECLAIM_MEMORY:
830 e820_type = E820_ACPI;
831 break;
832
833 case EFI_LOADER_CODE:
834 case EFI_LOADER_DATA:
835 case EFI_BOOT_SERVICES_CODE:
836 case EFI_BOOT_SERVICES_DATA:
837 case EFI_CONVENTIONAL_MEMORY:
838 e820_type = E820_RAM;
839 break;
840
841 case EFI_ACPI_MEMORY_NVS:
842 e820_type = E820_NVS;
843 break;
844
845 default:
846 continue;
847 }
848
849 /* Merge adjacent mappings */
850 if (prev && prev->type == e820_type &&
851 (prev->addr + prev->size) == d->phys_addr)
852 prev->size += d->num_pages << 12;
853 else {
854 e820_map->addr = d->phys_addr;
855 e820_map->size = d->num_pages << 12;
856 e820_map->type = e820_type;
857 prev = e820_map++;
858 nr_entries++;
859 }
860 }
861
862 boot_params->e820_entries = nr_entries;
863
864 return EFI_SUCCESS;
865
866free_mem_map:
867 low_free(_size, (unsigned long)mem_map);
868free_cmdline:
869 if (options_size)
870 low_free(options_size, hdr->cmd_line_ptr);
871fail:
872 return status;
873}
874
875/*
876 * On success we return a pointer to a boot_params structure, and NULL
877 * on failure.
878 */
879struct boot_params *efi_main(void *handle, efi_system_table_t *_table)
880{
881 struct boot_params *boot_params;
882 unsigned long start, nr_pages;
883 struct desc_ptr *gdt, *idt;
884 efi_loaded_image_t *image;
885 struct setup_header *hdr;
886 efi_status_t status;
887 efi_guid_t proto = LOADED_IMAGE_PROTOCOL_GUID;
888 struct desc_struct *desc;
889
890 sys_table = _table;
891
892 /* Check if we were booted by the EFI firmware */
893 if (sys_table->hdr.signature != EFI_SYSTEM_TABLE_SIGNATURE)
894 goto fail;
895
896 status = efi_call_phys3(sys_table->boottime->handle_protocol,
897 handle, &proto, (void *)&image);
898 if (status != EFI_SUCCESS)
899 goto fail;
900
901 status = low_alloc(0x4000, 1, (unsigned long *)&boot_params);
902 if (status != EFI_SUCCESS)
903 goto fail;
904
905 memset(boot_params, 0x0, 0x4000);
906
907 /* Copy first two sectors to boot_params */
908 memcpy(boot_params, image->image_base, 1024);
909
910 hdr = &boot_params->hdr;
911
912 /*
913 * The EFI firmware loader could have placed the kernel image
914 * anywhere in memory, but the kernel has various restrictions
915 * on the max physical address it can run at. Attempt to move
916 * the kernel to boot_params.pref_address, or as low as
917 * possible.
918 */
919 start = hdr->pref_address;
920 nr_pages = round_up(hdr->init_size, EFI_PAGE_SIZE) / EFI_PAGE_SIZE;
921
922 status = efi_call_phys4(sys_table->boottime->allocate_pages,
923 EFI_ALLOCATE_ADDRESS, EFI_LOADER_DATA,
924 nr_pages, &start);
925 if (status != EFI_SUCCESS) {
926 status = low_alloc(hdr->init_size, hdr->kernel_alignment,
927 &start);
928 if (status != EFI_SUCCESS)
929 goto fail;
930 }
931
932 hdr->code32_start = (__u32)start;
933 hdr->pref_address = (__u64)(unsigned long)image->image_base;
934
935 memcpy((void *)start, image->image_base, image->image_size);
936
937 status = efi_call_phys3(sys_table->boottime->allocate_pool,
938 EFI_LOADER_DATA, sizeof(*gdt),
939 (void **)&gdt);
940 if (status != EFI_SUCCESS)
941 goto fail;
942
943 gdt->size = 0x800;
944 status = low_alloc(gdt->size, 8, (unsigned long *)&gdt->address);
945 if (status != EFI_SUCCESS)
946 goto fail;
947
948 status = efi_call_phys3(sys_table->boottime->allocate_pool,
949 EFI_LOADER_DATA, sizeof(*idt),
950 (void **)&idt);
951 if (status != EFI_SUCCESS)
952 goto fail;
953
954 idt->size = 0;
955 idt->address = 0;
956
957 status = make_boot_params(boot_params, image, handle);
958 if (status != EFI_SUCCESS)
959 goto fail;
960
961 memset((char *)gdt->address, 0x0, gdt->size);
962 desc = (struct desc_struct *)gdt->address;
963
964 /* The first GDT is a dummy and the second is unused. */
965 desc += 2;
966
967 desc->limit0 = 0xffff;
968 desc->base0 = 0x0000;
969 desc->base1 = 0x0000;
970 desc->type = SEG_TYPE_CODE | SEG_TYPE_EXEC_READ;
971 desc->s = DESC_TYPE_CODE_DATA;
972 desc->dpl = 0;
973 desc->p = 1;
974 desc->limit = 0xf;
975 desc->avl = 0;
976 desc->l = 0;
977 desc->d = SEG_OP_SIZE_32BIT;
978 desc->g = SEG_GRANULARITY_4KB;
979 desc->base2 = 0x00;
980
981 desc++;
982 desc->limit0 = 0xffff;
983 desc->base0 = 0x0000;
984 desc->base1 = 0x0000;
985 desc->type = SEG_TYPE_DATA | SEG_TYPE_READ_WRITE;
986 desc->s = DESC_TYPE_CODE_DATA;
987 desc->dpl = 0;
988 desc->p = 1;
989 desc->limit = 0xf;
990 desc->avl = 0;
991 desc->l = 0;
992 desc->d = SEG_OP_SIZE_32BIT;
993 desc->g = SEG_GRANULARITY_4KB;
994 desc->base2 = 0x00;
995
996#ifdef CONFIG_X86_64
997 /* Task segment value */
998 desc++;
999 desc->limit0 = 0x0000;
1000 desc->base0 = 0x0000;
1001 desc->base1 = 0x0000;
1002 desc->type = SEG_TYPE_TSS;
1003 desc->s = 0;
1004 desc->dpl = 0;
1005 desc->p = 1;
1006 desc->limit = 0x0;
1007 desc->avl = 0;
1008 desc->l = 0;
1009 desc->d = 0;
1010 desc->g = SEG_GRANULARITY_4KB;
1011 desc->base2 = 0x00;
1012#endif /* CONFIG_X86_64 */
1013
1014 asm volatile ("lidt %0" : : "m" (*idt));
1015 asm volatile ("lgdt %0" : : "m" (*gdt));
1016
1017 asm volatile("cli");
1018
1019 return boot_params;
1020fail:
1021 return NULL;
1022}
diff --git a/arch/x86/boot/compressed/eboot.h b/arch/x86/boot/compressed/eboot.h
new file mode 100644
index 000000000000..39251663e65b
--- /dev/null
+++ b/arch/x86/boot/compressed/eboot.h
@@ -0,0 +1,61 @@
1#ifndef BOOT_COMPRESSED_EBOOT_H
2#define BOOT_COMPRESSED_EBOOT_H
3
4#define SEG_TYPE_DATA (0 << 3)
5#define SEG_TYPE_READ_WRITE (1 << 1)
6#define SEG_TYPE_CODE (1 << 3)
7#define SEG_TYPE_EXEC_READ (1 << 1)
8#define SEG_TYPE_TSS ((1 << 3) | (1 << 0))
9#define SEG_OP_SIZE_32BIT (1 << 0)
10#define SEG_GRANULARITY_4KB (1 << 0)
11
12#define DESC_TYPE_CODE_DATA (1 << 0)
13
14#define EFI_PAGE_SIZE (1UL << EFI_PAGE_SHIFT)
15#define EFI_READ_CHUNK_SIZE (1024 * 1024)
16
17#define PIXEL_RGB_RESERVED_8BIT_PER_COLOR 0
18#define PIXEL_BGR_RESERVED_8BIT_PER_COLOR 1
19#define PIXEL_BIT_MASK 2
20#define PIXEL_BLT_ONLY 3
21#define PIXEL_FORMAT_MAX 4
22
23struct efi_pixel_bitmask {
24 u32 red_mask;
25 u32 green_mask;
26 u32 blue_mask;
27 u32 reserved_mask;
28};
29
30struct efi_graphics_output_mode_info {
31 u32 version;
32 u32 horizontal_resolution;
33 u32 vertical_resolution;
34 int pixel_format;
35 struct efi_pixel_bitmask pixel_information;
36 u32 pixels_per_scan_line;
37} __packed;
38
39struct efi_graphics_output_protocol_mode {
40 u32 max_mode;
41 u32 mode;
42 unsigned long info;
43 unsigned long size_of_info;
44 u64 frame_buffer_base;
45 unsigned long frame_buffer_size;
46} __packed;
47
48struct efi_graphics_output_protocol {
49 void *query_mode;
50 unsigned long set_mode;
51 unsigned long blt;
52 struct efi_graphics_output_protocol_mode *mode;
53};
54
55struct efi_uga_draw_protocol {
56 void *get_mode;
57 void *set_mode;
58 void *blt;
59};
60
61#endif /* BOOT_COMPRESSED_EBOOT_H */
diff --git a/arch/x86/boot/compressed/efi_stub_32.S b/arch/x86/boot/compressed/efi_stub_32.S
new file mode 100644
index 000000000000..a53440e81d52
--- /dev/null
+++ b/arch/x86/boot/compressed/efi_stub_32.S
@@ -0,0 +1,86 @@
1/*
2 * EFI call stub for IA32.
3 *
4 * This stub allows us to make EFI calls in physical mode with interrupts
5 * turned off. Note that this implementation is different from the one in
6 * arch/x86/platform/efi/efi_stub_32.S because we're _already_ in physical
7 * mode at this point.
8 */
9
10#include <linux/linkage.h>
11#include <asm/page_types.h>
12
13/*
14 * efi_call_phys(void *, ...) is a function with variable parameters.
15 * All the callers of this function assure that all the parameters are 4-bytes.
16 */
17
18/*
19 * In gcc calling convention, EBX, ESP, EBP, ESI and EDI are all callee save.
20 * So we'd better save all of them at the beginning of this function and restore
21 * at the end no matter how many we use, because we can not assure EFI runtime
22 * service functions will comply with gcc calling convention, too.
23 */
24
25.text
26ENTRY(efi_call_phys)
27 /*
28 * 0. The function can only be called in Linux kernel. So CS has been
29 * set to 0x0010, DS and SS have been set to 0x0018. In EFI, I found
30 * the values of these registers are the same. And, the corresponding
31 * GDT entries are identical. So I will do nothing about segment reg
32 * and GDT, but change GDT base register in prelog and epilog.
33 */
34
35 /*
36 * 1. Because we haven't been relocated by this point we need to
37 * use relative addressing.
38 */
39 call 1f
401: popl %edx
41 subl $1b, %edx
42
43 /*
44 * 2. Now on the top of stack is the return
45 * address in the caller of efi_call_phys(), then parameter 1,
46 * parameter 2, ..., param n. To make things easy, we save the return
47 * address of efi_call_phys in a global variable.
48 */
49 popl %ecx
50 movl %ecx, saved_return_addr(%edx)
51 /* get the function pointer into ECX*/
52 popl %ecx
53 movl %ecx, efi_rt_function_ptr(%edx)
54
55 /*
56 * 3. Call the physical function.
57 */
58 call *%ecx
59
60 /*
61 * 4. Balance the stack. And because EAX contain the return value,
62 * we'd better not clobber it. We need to calculate our address
63 * again because %ecx and %edx are not preserved across EFI function
64 * calls.
65 */
66 call 1f
671: popl %edx
68 subl $1b, %edx
69
70 movl efi_rt_function_ptr(%edx), %ecx
71 pushl %ecx
72
73 /*
74 * 10. Push the saved return address onto the stack and return.
75 */
76 movl saved_return_addr(%edx), %ecx
77 pushl %ecx
78 ret
79ENDPROC(efi_call_phys)
80.previous
81
82.data
83saved_return_addr:
84 .long 0
85efi_rt_function_ptr:
86 .long 0
diff --git a/arch/x86/boot/compressed/efi_stub_64.S b/arch/x86/boot/compressed/efi_stub_64.S
new file mode 100644
index 000000000000..cedc60de86eb
--- /dev/null
+++ b/arch/x86/boot/compressed/efi_stub_64.S
@@ -0,0 +1 @@
#include "../../platform/efi/efi_stub_64.S"
diff --git a/arch/x86/boot/compressed/head_32.S b/arch/x86/boot/compressed/head_32.S
index 67a655a39ce4..a0559930a180 100644
--- a/arch/x86/boot/compressed/head_32.S
+++ b/arch/x86/boot/compressed/head_32.S
@@ -32,6 +32,28 @@
32 32
33 __HEAD 33 __HEAD
34ENTRY(startup_32) 34ENTRY(startup_32)
35#ifdef CONFIG_EFI_STUB
36 /*
37 * We don't need the return address, so set up the stack so
38 * efi_main() can find its arugments.
39 */
40 add $0x4, %esp
41
42 call efi_main
43 cmpl $0, %eax
44 je preferred_addr
45 movl %eax, %esi
46 call 1f
471:
48 popl %eax
49 subl $1b, %eax
50 subl BP_pref_address(%esi), %eax
51 add BP_code32_start(%esi), %eax
52 leal preferred_addr(%eax), %eax
53 jmp *%eax
54
55preferred_addr:
56#endif
35 cld 57 cld
36 /* 58 /*
37 * Test KEEP_SEGMENTS flag to see if the bootloader is asking 59 * Test KEEP_SEGMENTS flag to see if the bootloader is asking
diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
index 35af09d13dc1..558d76ce23bc 100644
--- a/arch/x86/boot/compressed/head_64.S
+++ b/arch/x86/boot/compressed/head_64.S
@@ -199,6 +199,26 @@ ENTRY(startup_64)
199 * an identity mapped page table being provied that maps our 199 * an identity mapped page table being provied that maps our
200 * entire text+data+bss and hopefully all of memory. 200 * entire text+data+bss and hopefully all of memory.
201 */ 201 */
202#ifdef CONFIG_EFI_STUB
203 pushq %rsi
204 mov %rcx, %rdi
205 mov %rdx, %rsi
206 call efi_main
207 popq %rsi
208 cmpq $0,%rax
209 je preferred_addr
210 movq %rax,%rsi
211 call 1f
2121:
213 popq %rax
214 subq $1b, %rax
215 subq BP_pref_address(%rsi), %rax
216 add BP_code32_start(%esi), %eax
217 leaq preferred_addr(%rax), %rax
218 jmp *%rax
219
220preferred_addr:
221#endif
202 222
203 /* Setup data segments. */ 223 /* Setup data segments. */
204 xorl %eax, %eax 224 xorl %eax, %eax
diff --git a/arch/x86/boot/compressed/string.c b/arch/x86/boot/compressed/string.c
index 19b3e693cd72..ffb9c5c9d748 100644
--- a/arch/x86/boot/compressed/string.c
+++ b/arch/x86/boot/compressed/string.c
@@ -1,2 +1,11 @@
1#include "misc.h" 1#include "misc.h"
2
3int memcmp(const void *s1, const void *s2, size_t len)
4{
5 u8 diff;
6 asm("repe; cmpsb; setnz %0"
7 : "=qm" (diff), "+D" (s1), "+S" (s2), "+c" (len));
8 return diff;
9}
10
2#include "../string.c" 11#include "../string.c"
diff --git a/arch/x86/boot/header.S b/arch/x86/boot/header.S
index bdb4d458ec8c..f1bbeeb09148 100644
--- a/arch/x86/boot/header.S
+++ b/arch/x86/boot/header.S
@@ -45,6 +45,11 @@ SYSSEG = 0x1000 /* historical load address >> 4 */
45 45
46 .global bootsect_start 46 .global bootsect_start
47bootsect_start: 47bootsect_start:
48#ifdef CONFIG_EFI_STUB
49 # "MZ", MS-DOS header
50 .byte 0x4d
51 .byte 0x5a
52#endif
48 53
49 # Normalize the start address 54 # Normalize the start address
50 ljmp $BOOTSEG, $start2 55 ljmp $BOOTSEG, $start2
@@ -79,6 +84,14 @@ bs_die:
79 # invoke the BIOS reset code... 84 # invoke the BIOS reset code...
80 ljmp $0xf000,$0xfff0 85 ljmp $0xf000,$0xfff0
81 86
87#ifdef CONFIG_EFI_STUB
88 .org 0x3c
89 #
90 # Offset to the PE header.
91 #
92 .long pe_header
93#endif /* CONFIG_EFI_STUB */
94
82 .section ".bsdata", "a" 95 .section ".bsdata", "a"
83bugger_off_msg: 96bugger_off_msg:
84 .ascii "Direct booting from floppy is no longer supported.\r\n" 97 .ascii "Direct booting from floppy is no longer supported.\r\n"
@@ -87,6 +100,141 @@ bugger_off_msg:
87 .ascii "Remove disk and press any key to reboot . . .\r\n" 100 .ascii "Remove disk and press any key to reboot . . .\r\n"
88 .byte 0 101 .byte 0
89 102
103#ifdef CONFIG_EFI_STUB
104pe_header:
105 .ascii "PE"
106 .word 0
107
108coff_header:
109#ifdef CONFIG_X86_32
110 .word 0x14c # i386
111#else
112 .word 0x8664 # x86-64
113#endif
114 .word 2 # nr_sections
115 .long 0 # TimeDateStamp
116 .long 0 # PointerToSymbolTable
117 .long 1 # NumberOfSymbols
118 .word section_table - optional_header # SizeOfOptionalHeader
119#ifdef CONFIG_X86_32
120 .word 0x306 # Characteristics.
121 # IMAGE_FILE_32BIT_MACHINE |
122 # IMAGE_FILE_DEBUG_STRIPPED |
123 # IMAGE_FILE_EXECUTABLE_IMAGE |
124 # IMAGE_FILE_LINE_NUMS_STRIPPED
125#else
126 .word 0x206 # Characteristics
127 # IMAGE_FILE_DEBUG_STRIPPED |
128 # IMAGE_FILE_EXECUTABLE_IMAGE |
129 # IMAGE_FILE_LINE_NUMS_STRIPPED
130#endif
131
132optional_header:
133#ifdef CONFIG_X86_32
134 .word 0x10b # PE32 format
135#else
136 .word 0x20b # PE32+ format
137#endif
138 .byte 0x02 # MajorLinkerVersion
139 .byte 0x14 # MinorLinkerVersion
140
141 # Filled in by build.c
142 .long 0 # SizeOfCode
143
144 .long 0 # SizeOfInitializedData
145 .long 0 # SizeOfUninitializedData
146
147 # Filled in by build.c
148 .long 0x0000 # AddressOfEntryPoint
149
150 .long 0x0000 # BaseOfCode
151#ifdef CONFIG_X86_32
152 .long 0 # data
153#endif
154
155extra_header_fields:
156#ifdef CONFIG_X86_32
157 .long 0 # ImageBase
158#else
159 .quad 0 # ImageBase
160#endif
161 .long 0x1000 # SectionAlignment
162 .long 0x200 # FileAlignment
163 .word 0 # MajorOperatingSystemVersion
164 .word 0 # MinorOperatingSystemVersion
165 .word 0 # MajorImageVersion
166 .word 0 # MinorImageVersion
167 .word 0 # MajorSubsystemVersion
168 .word 0 # MinorSubsystemVersion
169 .long 0 # Win32VersionValue
170
171 #
172 # The size of the bzImage is written in tools/build.c
173 #
174 .long 0 # SizeOfImage
175
176 .long 0x200 # SizeOfHeaders
177 .long 0 # CheckSum
178 .word 0xa # Subsystem (EFI application)
179 .word 0 # DllCharacteristics
180#ifdef CONFIG_X86_32
181 .long 0 # SizeOfStackReserve
182 .long 0 # SizeOfStackCommit
183 .long 0 # SizeOfHeapReserve
184 .long 0 # SizeOfHeapCommit
185#else
186 .quad 0 # SizeOfStackReserve
187 .quad 0 # SizeOfStackCommit
188 .quad 0 # SizeOfHeapReserve
189 .quad 0 # SizeOfHeapCommit
190#endif
191 .long 0 # LoaderFlags
192 .long 0x1 # NumberOfRvaAndSizes
193
194 .quad 0 # ExportTable
195 .quad 0 # ImportTable
196 .quad 0 # ResourceTable
197 .quad 0 # ExceptionTable
198 .quad 0 # CertificationTable
199 .quad 0 # BaseRelocationTable
200
201 # Section table
202section_table:
203 .ascii ".text"
204 .byte 0
205 .byte 0
206 .byte 0
207 .long 0
208 .long 0x0 # startup_{32,64}
209 .long 0 # Size of initialized data
210 # on disk
211 .long 0x0 # startup_{32,64}
212 .long 0 # PointerToRelocations
213 .long 0 # PointerToLineNumbers
214 .word 0 # NumberOfRelocations
215 .word 0 # NumberOfLineNumbers
216 .long 0x60500020 # Characteristics (section flags)
217
218 #
219 # The EFI application loader requires a relocation section
220 # because EFI applications are relocatable and not having
221 # this section seems to confuse it. But since we don't need
222 # the loader to fixup any relocs for us just fill it with a
223 # single dummy reloc.
224 #
225 .ascii ".reloc"
226 .byte 0
227 .byte 0
228 .long reloc_end - reloc_start
229 .long reloc_start
230 .long reloc_end - reloc_start # SizeOfRawData
231 .long reloc_start # PointerToRawData
232 .long 0 # PointerToRelocations
233 .long 0 # PointerToLineNumbers
234 .word 0 # NumberOfRelocations
235 .word 0 # NumberOfLineNumbers
236 .long 0x42100040 # Characteristics (section flags)
237#endif /* CONFIG_EFI_STUB */
90 238
91 # Kernel attributes; used by setup. This is part 1 of the 239 # Kernel attributes; used by setup. This is part 1 of the
92 # header, from the old boot sector. 240 # header, from the old boot sector.
@@ -318,3 +466,13 @@ die:
318setup_corrupt: 466setup_corrupt:
319 .byte 7 467 .byte 7
320 .string "No setup signature found...\n" 468 .string "No setup signature found...\n"
469
470 .data
471dummy: .long 0
472
473 .section .reloc
474reloc_start:
475 .long dummy - reloc_start
476 .long 10
477 .word 0
478reloc_end:
diff --git a/arch/x86/boot/string.c b/arch/x86/boot/string.c
index 3cbc4058dd26..574dedfe2890 100644
--- a/arch/x86/boot/string.c
+++ b/arch/x86/boot/string.c
@@ -111,3 +111,38 @@ unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int bas
111 111
112 return result; 112 return result;
113} 113}
114
115/**
116 * strlen - Find the length of a string
117 * @s: The string to be sized
118 */
119size_t strlen(const char *s)
120{
121 const char *sc;
122
123 for (sc = s; *sc != '\0'; ++sc)
124 /* nothing */;
125 return sc - s;
126}
127
128/**
129 * strstr - Find the first substring in a %NUL terminated string
130 * @s1: The string to be searched
131 * @s2: The string to search for
132 */
133char *strstr(const char *s1, const char *s2)
134{
135 size_t l1, l2;
136
137 l2 = strlen(s2);
138 if (!l2)
139 return (char *)s1;
140 l1 = strlen(s1);
141 while (l1 >= l2) {
142 l1--;
143 if (!memcmp(s1, s2, l2))
144 return (char *)s1;
145 s1++;
146 }
147 return NULL;
148}
diff --git a/arch/x86/boot/tools/build.c b/arch/x86/boot/tools/build.c
index fdc60a0b3c20..4e9bd6bcafa6 100644
--- a/arch/x86/boot/tools/build.c
+++ b/arch/x86/boot/tools/build.c
@@ -135,6 +135,9 @@ static void usage(void)
135 135
136int main(int argc, char ** argv) 136int main(int argc, char ** argv)
137{ 137{
138#ifdef CONFIG_EFI_STUB
139 unsigned int file_sz, pe_header;
140#endif
138 unsigned int i, sz, setup_sectors; 141 unsigned int i, sz, setup_sectors;
139 int c; 142 int c;
140 u32 sys_size; 143 u32 sys_size;
@@ -194,6 +197,42 @@ int main(int argc, char ** argv)
194 buf[0x1f6] = sys_size >> 16; 197 buf[0x1f6] = sys_size >> 16;
195 buf[0x1f7] = sys_size >> 24; 198 buf[0x1f7] = sys_size >> 24;
196 199
200#ifdef CONFIG_EFI_STUB
201 file_sz = sz + i + ((sys_size * 16) - sz);
202
203 pe_header = *(unsigned int *)&buf[0x3c];
204
205 /* Size of code */
206 *(unsigned int *)&buf[pe_header + 0x1c] = file_sz;
207
208 /* Size of image */
209 *(unsigned int *)&buf[pe_header + 0x50] = file_sz;
210
211#ifdef CONFIG_X86_32
212 /* Address of entry point */
213 *(unsigned int *)&buf[pe_header + 0x28] = i;
214
215 /* .text size */
216 *(unsigned int *)&buf[pe_header + 0xb0] = file_sz;
217
218 /* .text size of initialised data */
219 *(unsigned int *)&buf[pe_header + 0xb8] = file_sz;
220#else
221 /*
222 * Address of entry point. startup_32 is at the beginning and
223 * the 64-bit entry point (startup_64) is always 512 bytes
224 * after.
225 */
226 *(unsigned int *)&buf[pe_header + 0x28] = i + 512;
227
228 /* .text size */
229 *(unsigned int *)&buf[pe_header + 0xc0] = file_sz;
230
231 /* .text size of initialised data */
232 *(unsigned int *)&buf[pe_header + 0xc8] = file_sz;
233#endif /* CONFIG_X86_32 */
234#endif /* CONFIG_EFI_STUB */
235
197 crc = partial_crc32(buf, i, crc); 236 crc = partial_crc32(buf, i, crc);
198 if (fwrite(buf, 1, i, stdout) != i) 237 if (fwrite(buf, 1, i, stdout) != i)
199 die("Writing setup failed"); 238 die("Writing setup failed");
diff --git a/arch/x86/crypto/Makefile b/arch/x86/crypto/Makefile
index 3537d4b91f74..2b0b9631474b 100644
--- a/arch/x86/crypto/Makefile
+++ b/arch/x86/crypto/Makefile
@@ -5,12 +5,14 @@
5obj-$(CONFIG_CRYPTO_AES_586) += aes-i586.o 5obj-$(CONFIG_CRYPTO_AES_586) += aes-i586.o
6obj-$(CONFIG_CRYPTO_TWOFISH_586) += twofish-i586.o 6obj-$(CONFIG_CRYPTO_TWOFISH_586) += twofish-i586.o
7obj-$(CONFIG_CRYPTO_SALSA20_586) += salsa20-i586.o 7obj-$(CONFIG_CRYPTO_SALSA20_586) += salsa20-i586.o
8obj-$(CONFIG_CRYPTO_SERPENT_SSE2_586) += serpent-sse2-i586.o
8 9
9obj-$(CONFIG_CRYPTO_AES_X86_64) += aes-x86_64.o 10obj-$(CONFIG_CRYPTO_AES_X86_64) += aes-x86_64.o
10obj-$(CONFIG_CRYPTO_BLOWFISH_X86_64) += blowfish-x86_64.o 11obj-$(CONFIG_CRYPTO_BLOWFISH_X86_64) += blowfish-x86_64.o
11obj-$(CONFIG_CRYPTO_TWOFISH_X86_64) += twofish-x86_64.o 12obj-$(CONFIG_CRYPTO_TWOFISH_X86_64) += twofish-x86_64.o
12obj-$(CONFIG_CRYPTO_TWOFISH_X86_64_3WAY) += twofish-x86_64-3way.o 13obj-$(CONFIG_CRYPTO_TWOFISH_X86_64_3WAY) += twofish-x86_64-3way.o
13obj-$(CONFIG_CRYPTO_SALSA20_X86_64) += salsa20-x86_64.o 14obj-$(CONFIG_CRYPTO_SALSA20_X86_64) += salsa20-x86_64.o
15obj-$(CONFIG_CRYPTO_SERPENT_SSE2_X86_64) += serpent-sse2-x86_64.o
14obj-$(CONFIG_CRYPTO_AES_NI_INTEL) += aesni-intel.o 16obj-$(CONFIG_CRYPTO_AES_NI_INTEL) += aesni-intel.o
15obj-$(CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL) += ghash-clmulni-intel.o 17obj-$(CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL) += ghash-clmulni-intel.o
16 18
@@ -20,12 +22,14 @@ obj-$(CONFIG_CRYPTO_SHA1_SSSE3) += sha1-ssse3.o
20aes-i586-y := aes-i586-asm_32.o aes_glue.o 22aes-i586-y := aes-i586-asm_32.o aes_glue.o
21twofish-i586-y := twofish-i586-asm_32.o twofish_glue.o 23twofish-i586-y := twofish-i586-asm_32.o twofish_glue.o
22salsa20-i586-y := salsa20-i586-asm_32.o salsa20_glue.o 24salsa20-i586-y := salsa20-i586-asm_32.o salsa20_glue.o
25serpent-sse2-i586-y := serpent-sse2-i586-asm_32.o serpent_sse2_glue.o
23 26
24aes-x86_64-y := aes-x86_64-asm_64.o aes_glue.o 27aes-x86_64-y := aes-x86_64-asm_64.o aes_glue.o
25blowfish-x86_64-y := blowfish-x86_64-asm_64.o blowfish_glue.o 28blowfish-x86_64-y := blowfish-x86_64-asm_64.o blowfish_glue.o
26twofish-x86_64-y := twofish-x86_64-asm_64.o twofish_glue.o 29twofish-x86_64-y := twofish-x86_64-asm_64.o twofish_glue.o
27twofish-x86_64-3way-y := twofish-x86_64-asm_64-3way.o twofish_glue_3way.o 30twofish-x86_64-3way-y := twofish-x86_64-asm_64-3way.o twofish_glue_3way.o
28salsa20-x86_64-y := salsa20-x86_64-asm_64.o salsa20_glue.o 31salsa20-x86_64-y := salsa20-x86_64-asm_64.o salsa20_glue.o
32serpent-sse2-x86_64-y := serpent-sse2-x86_64-asm_64.o serpent_sse2_glue.o
29 33
30aesni-intel-y := aesni-intel_asm.o aesni-intel_glue.o fpu.o 34aesni-intel-y := aesni-intel_asm.o aesni-intel_glue.o fpu.o
31 35
diff --git a/arch/x86/crypto/serpent-sse2-i586-asm_32.S b/arch/x86/crypto/serpent-sse2-i586-asm_32.S
new file mode 100644
index 000000000000..4e37677ca851
--- /dev/null
+++ b/arch/x86/crypto/serpent-sse2-i586-asm_32.S
@@ -0,0 +1,638 @@
1/*
2 * Serpent Cipher 4-way parallel algorithm (i586/SSE2)
3 *
4 * Copyright (C) 2011 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
5 *
6 * Based on crypto/serpent.c by
7 * Copyright (C) 2002 Dag Arne Osvik <osvik@ii.uib.no>
8 * 2003 Herbert Valerio Riedel <hvr@gnu.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
23 * USA
24 *
25 */
26
27.file "serpent-sse2-i586-asm_32.S"
28.text
29
30#define arg_ctx 4
31#define arg_dst 8
32#define arg_src 12
33#define arg_xor 16
34
35/**********************************************************************
36 4-way SSE2 serpent
37 **********************************************************************/
38#define CTX %edx
39
40#define RA %xmm0
41#define RB %xmm1
42#define RC %xmm2
43#define RD %xmm3
44#define RE %xmm4
45
46#define RT0 %xmm5
47#define RT1 %xmm6
48
49#define RNOT %xmm7
50
51#define get_key(i, j, t) \
52 movd (4*(i)+(j))*4(CTX), t; \
53 pshufd $0, t, t;
54
55#define K(x0, x1, x2, x3, x4, i) \
56 get_key(i, 0, x4); \
57 get_key(i, 1, RT0); \
58 get_key(i, 2, RT1); \
59 pxor x4, x0; \
60 pxor RT0, x1; \
61 pxor RT1, x2; \
62 get_key(i, 3, x4); \
63 pxor x4, x3;
64
65#define LK(x0, x1, x2, x3, x4, i) \
66 movdqa x0, x4; \
67 pslld $13, x0; \
68 psrld $(32 - 13), x4; \
69 por x4, x0; \
70 pxor x0, x1; \
71 movdqa x2, x4; \
72 pslld $3, x2; \
73 psrld $(32 - 3), x4; \
74 por x4, x2; \
75 pxor x2, x1; \
76 movdqa x1, x4; \
77 pslld $1, x1; \
78 psrld $(32 - 1), x4; \
79 por x4, x1; \
80 movdqa x0, x4; \
81 pslld $3, x4; \
82 pxor x2, x3; \
83 pxor x4, x3; \
84 movdqa x3, x4; \
85 pslld $7, x3; \
86 psrld $(32 - 7), x4; \
87 por x4, x3; \
88 movdqa x1, x4; \
89 pslld $7, x4; \
90 pxor x1, x0; \
91 pxor x3, x0; \
92 pxor x3, x2; \
93 pxor x4, x2; \
94 movdqa x0, x4; \
95 get_key(i, 1, RT0); \
96 pxor RT0, x1; \
97 get_key(i, 3, RT0); \
98 pxor RT0, x3; \
99 pslld $5, x0; \
100 psrld $(32 - 5), x4; \
101 por x4, x0; \
102 movdqa x2, x4; \
103 pslld $22, x2; \
104 psrld $(32 - 22), x4; \
105 por x4, x2; \
106 get_key(i, 0, RT0); \
107 pxor RT0, x0; \
108 get_key(i, 2, RT0); \
109 pxor RT0, x2;
110
111#define KL(x0, x1, x2, x3, x4, i) \
112 K(x0, x1, x2, x3, x4, i); \
113 movdqa x0, x4; \
114 psrld $5, x0; \
115 pslld $(32 - 5), x4; \
116 por x4, x0; \
117 movdqa x2, x4; \
118 psrld $22, x2; \
119 pslld $(32 - 22), x4; \
120 por x4, x2; \
121 pxor x3, x2; \
122 pxor x3, x0; \
123 movdqa x1, x4; \
124 pslld $7, x4; \
125 pxor x1, x0; \
126 pxor x4, x2; \
127 movdqa x1, x4; \
128 psrld $1, x1; \
129 pslld $(32 - 1), x4; \
130 por x4, x1; \
131 movdqa x3, x4; \
132 psrld $7, x3; \
133 pslld $(32 - 7), x4; \
134 por x4, x3; \
135 pxor x0, x1; \
136 movdqa x0, x4; \
137 pslld $3, x4; \
138 pxor x4, x3; \
139 movdqa x0, x4; \
140 psrld $13, x0; \
141 pslld $(32 - 13), x4; \
142 por x4, x0; \
143 pxor x2, x1; \
144 pxor x2, x3; \
145 movdqa x2, x4; \
146 psrld $3, x2; \
147 pslld $(32 - 3), x4; \
148 por x4, x2;
149
150#define S0(x0, x1, x2, x3, x4) \
151 movdqa x3, x4; \
152 por x0, x3; \
153 pxor x4, x0; \
154 pxor x2, x4; \
155 pxor RNOT, x4; \
156 pxor x1, x3; \
157 pand x0, x1; \
158 pxor x4, x1; \
159 pxor x0, x2; \
160 pxor x3, x0; \
161 por x0, x4; \
162 pxor x2, x0; \
163 pand x1, x2; \
164 pxor x2, x3; \
165 pxor RNOT, x1; \
166 pxor x4, x2; \
167 pxor x2, x1;
168
169#define S1(x0, x1, x2, x3, x4) \
170 movdqa x1, x4; \
171 pxor x0, x1; \
172 pxor x3, x0; \
173 pxor RNOT, x3; \
174 pand x1, x4; \
175 por x1, x0; \
176 pxor x2, x3; \
177 pxor x3, x0; \
178 pxor x3, x1; \
179 pxor x4, x3; \
180 por x4, x1; \
181 pxor x2, x4; \
182 pand x0, x2; \
183 pxor x1, x2; \
184 por x0, x1; \
185 pxor RNOT, x0; \
186 pxor x2, x0; \
187 pxor x1, x4;
188
189#define S2(x0, x1, x2, x3, x4) \
190 pxor RNOT, x3; \
191 pxor x0, x1; \
192 movdqa x0, x4; \
193 pand x2, x0; \
194 pxor x3, x0; \
195 por x4, x3; \
196 pxor x1, x2; \
197 pxor x1, x3; \
198 pand x0, x1; \
199 pxor x2, x0; \
200 pand x3, x2; \
201 por x1, x3; \
202 pxor RNOT, x0; \
203 pxor x0, x3; \
204 pxor x0, x4; \
205 pxor x2, x0; \
206 por x2, x1;
207
208#define S3(x0, x1, x2, x3, x4) \
209 movdqa x1, x4; \
210 pxor x3, x1; \
211 por x0, x3; \
212 pand x0, x4; \
213 pxor x2, x0; \
214 pxor x1, x2; \
215 pand x3, x1; \
216 pxor x3, x2; \
217 por x4, x0; \
218 pxor x3, x4; \
219 pxor x0, x1; \
220 pand x3, x0; \
221 pand x4, x3; \
222 pxor x2, x3; \
223 por x1, x4; \
224 pand x1, x2; \
225 pxor x3, x4; \
226 pxor x3, x0; \
227 pxor x2, x3;
228
229#define S4(x0, x1, x2, x3, x4) \
230 movdqa x3, x4; \
231 pand x0, x3; \
232 pxor x4, x0; \
233 pxor x2, x3; \
234 por x4, x2; \
235 pxor x1, x0; \
236 pxor x3, x4; \
237 por x0, x2; \
238 pxor x1, x2; \
239 pand x0, x1; \
240 pxor x4, x1; \
241 pand x2, x4; \
242 pxor x3, x2; \
243 pxor x0, x4; \
244 por x1, x3; \
245 pxor RNOT, x1; \
246 pxor x0, x3;
247
248#define S5(x0, x1, x2, x3, x4) \
249 movdqa x1, x4; \
250 por x0, x1; \
251 pxor x1, x2; \
252 pxor RNOT, x3; \
253 pxor x0, x4; \
254 pxor x2, x0; \
255 pand x4, x1; \
256 por x3, x4; \
257 pxor x0, x4; \
258 pand x3, x0; \
259 pxor x3, x1; \
260 pxor x2, x3; \
261 pxor x1, x0; \
262 pand x4, x2; \
263 pxor x2, x1; \
264 pand x0, x2; \
265 pxor x2, x3;
266
267#define S6(x0, x1, x2, x3, x4) \
268 movdqa x1, x4; \
269 pxor x0, x3; \
270 pxor x2, x1; \
271 pxor x0, x2; \
272 pand x3, x0; \
273 por x3, x1; \
274 pxor RNOT, x4; \
275 pxor x1, x0; \
276 pxor x2, x1; \
277 pxor x4, x3; \
278 pxor x0, x4; \
279 pand x0, x2; \
280 pxor x1, x4; \
281 pxor x3, x2; \
282 pand x1, x3; \
283 pxor x0, x3; \
284 pxor x2, x1;
285
286#define S7(x0, x1, x2, x3, x4) \
287 pxor RNOT, x1; \
288 movdqa x1, x4; \
289 pxor RNOT, x0; \
290 pand x2, x1; \
291 pxor x3, x1; \
292 por x4, x3; \
293 pxor x2, x4; \
294 pxor x3, x2; \
295 pxor x0, x3; \
296 por x1, x0; \
297 pand x0, x2; \
298 pxor x4, x0; \
299 pxor x3, x4; \
300 pand x0, x3; \
301 pxor x1, x4; \
302 pxor x4, x2; \
303 pxor x1, x3; \
304 por x0, x4; \
305 pxor x1, x4;
306
307#define SI0(x0, x1, x2, x3, x4) \
308 movdqa x3, x4; \
309 pxor x0, x1; \
310 por x1, x3; \
311 pxor x1, x4; \
312 pxor RNOT, x0; \
313 pxor x3, x2; \
314 pxor x0, x3; \
315 pand x1, x0; \
316 pxor x2, x0; \
317 pand x3, x2; \
318 pxor x4, x3; \
319 pxor x3, x2; \
320 pxor x3, x1; \
321 pand x0, x3; \
322 pxor x0, x1; \
323 pxor x2, x0; \
324 pxor x3, x4;
325
326#define SI1(x0, x1, x2, x3, x4) \
327 pxor x3, x1; \
328 movdqa x0, x4; \
329 pxor x2, x0; \
330 pxor RNOT, x2; \
331 por x1, x4; \
332 pxor x3, x4; \
333 pand x1, x3; \
334 pxor x2, x1; \
335 pand x4, x2; \
336 pxor x1, x4; \
337 por x3, x1; \
338 pxor x0, x3; \
339 pxor x0, x2; \
340 por x4, x0; \
341 pxor x4, x2; \
342 pxor x0, x1; \
343 pxor x1, x4;
344
345#define SI2(x0, x1, x2, x3, x4) \
346 pxor x1, x2; \
347 movdqa x3, x4; \
348 pxor RNOT, x3; \
349 por x2, x3; \
350 pxor x4, x2; \
351 pxor x0, x4; \
352 pxor x1, x3; \
353 por x2, x1; \
354 pxor x0, x2; \
355 pxor x4, x1; \
356 por x3, x4; \
357 pxor x3, x2; \
358 pxor x2, x4; \
359 pand x1, x2; \
360 pxor x3, x2; \
361 pxor x4, x3; \
362 pxor x0, x4;
363
364#define SI3(x0, x1, x2, x3, x4) \
365 pxor x1, x2; \
366 movdqa x1, x4; \
367 pand x2, x1; \
368 pxor x0, x1; \
369 por x4, x0; \
370 pxor x3, x4; \
371 pxor x3, x0; \
372 por x1, x3; \
373 pxor x2, x1; \
374 pxor x3, x1; \
375 pxor x2, x0; \
376 pxor x3, x2; \
377 pand x1, x3; \
378 pxor x0, x1; \
379 pand x2, x0; \
380 pxor x3, x4; \
381 pxor x0, x3; \
382 pxor x1, x0;
383
384#define SI4(x0, x1, x2, x3, x4) \
385 pxor x3, x2; \
386 movdqa x0, x4; \
387 pand x1, x0; \
388 pxor x2, x0; \
389 por x3, x2; \
390 pxor RNOT, x4; \
391 pxor x0, x1; \
392 pxor x2, x0; \
393 pand x4, x2; \
394 pxor x0, x2; \
395 por x4, x0; \
396 pxor x3, x0; \
397 pand x2, x3; \
398 pxor x3, x4; \
399 pxor x1, x3; \
400 pand x0, x1; \
401 pxor x1, x4; \
402 pxor x3, x0;
403
404#define SI5(x0, x1, x2, x3, x4) \
405 movdqa x1, x4; \
406 por x2, x1; \
407 pxor x4, x2; \
408 pxor x3, x1; \
409 pand x4, x3; \
410 pxor x3, x2; \
411 por x0, x3; \
412 pxor RNOT, x0; \
413 pxor x2, x3; \
414 por x0, x2; \
415 pxor x1, x4; \
416 pxor x4, x2; \
417 pand x0, x4; \
418 pxor x1, x0; \
419 pxor x3, x1; \
420 pand x2, x0; \
421 pxor x3, x2; \
422 pxor x2, x0; \
423 pxor x4, x2; \
424 pxor x3, x4;
425
426#define SI6(x0, x1, x2, x3, x4) \
427 pxor x2, x0; \
428 movdqa x0, x4; \
429 pand x3, x0; \
430 pxor x3, x2; \
431 pxor x2, x0; \
432 pxor x1, x3; \
433 por x4, x2; \
434 pxor x3, x2; \
435 pand x0, x3; \
436 pxor RNOT, x0; \
437 pxor x1, x3; \
438 pand x2, x1; \
439 pxor x0, x4; \
440 pxor x4, x3; \
441 pxor x2, x4; \
442 pxor x1, x0; \
443 pxor x0, x2;
444
445#define SI7(x0, x1, x2, x3, x4) \
446 movdqa x3, x4; \
447 pand x0, x3; \
448 pxor x2, x0; \
449 por x4, x2; \
450 pxor x1, x4; \
451 pxor RNOT, x0; \
452 por x3, x1; \
453 pxor x0, x4; \
454 pand x2, x0; \
455 pxor x1, x0; \
456 pand x2, x1; \
457 pxor x2, x3; \
458 pxor x3, x4; \
459 pand x3, x2; \
460 por x0, x3; \
461 pxor x4, x1; \
462 pxor x4, x3; \
463 pand x0, x4; \
464 pxor x2, x4;
465
466#define transpose_4x4(x0, x1, x2, x3, t1, t2, t3) \
467 movdqa x2, t3; \
468 movdqa x0, t1; \
469 unpcklps x3, t3; \
470 movdqa x0, t2; \
471 unpcklps x1, t1; \
472 unpckhps x1, t2; \
473 movdqa t3, x1; \
474 unpckhps x3, x2; \
475 movdqa t1, x0; \
476 movhlps t1, x1; \
477 movdqa t2, t1; \
478 movlhps t3, x0; \
479 movlhps x2, t1; \
480 movhlps t2, x2; \
481 movdqa x2, x3; \
482 movdqa t1, x2;
483
484#define read_blocks(in, x0, x1, x2, x3, t0, t1, t2) \
485 movdqu (0*4*4)(in), x0; \
486 movdqu (1*4*4)(in), x1; \
487 movdqu (2*4*4)(in), x2; \
488 movdqu (3*4*4)(in), x3; \
489 \
490 transpose_4x4(x0, x1, x2, x3, t0, t1, t2)
491
492#define write_blocks(out, x0, x1, x2, x3, t0, t1, t2) \
493 transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
494 \
495 movdqu x0, (0*4*4)(out); \
496 movdqu x1, (1*4*4)(out); \
497 movdqu x2, (2*4*4)(out); \
498 movdqu x3, (3*4*4)(out);
499
500#define xor_blocks(out, x0, x1, x2, x3, t0, t1, t2) \
501 transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
502 \
503 movdqu (0*4*4)(out), t0; \
504 pxor t0, x0; \
505 movdqu x0, (0*4*4)(out); \
506 movdqu (1*4*4)(out), t0; \
507 pxor t0, x1; \
508 movdqu x1, (1*4*4)(out); \
509 movdqu (2*4*4)(out), t0; \
510 pxor t0, x2; \
511 movdqu x2, (2*4*4)(out); \
512 movdqu (3*4*4)(out), t0; \
513 pxor t0, x3; \
514 movdqu x3, (3*4*4)(out);
515
516.align 8
517.global __serpent_enc_blk_4way
518.type __serpent_enc_blk_4way,@function;
519
520__serpent_enc_blk_4way:
521 /* input:
522 * arg_ctx(%esp): ctx, CTX
523 * arg_dst(%esp): dst
524 * arg_src(%esp): src
525 * arg_xor(%esp): bool, if true: xor output
526 */
527
528 pcmpeqd RNOT, RNOT;
529
530 movl arg_ctx(%esp), CTX;
531
532 movl arg_src(%esp), %eax;
533 read_blocks(%eax, RA, RB, RC, RD, RT0, RT1, RE);
534
535 K(RA, RB, RC, RD, RE, 0);
536 S0(RA, RB, RC, RD, RE); LK(RC, RB, RD, RA, RE, 1);
537 S1(RC, RB, RD, RA, RE); LK(RE, RD, RA, RC, RB, 2);
538 S2(RE, RD, RA, RC, RB); LK(RB, RD, RE, RC, RA, 3);
539 S3(RB, RD, RE, RC, RA); LK(RC, RA, RD, RB, RE, 4);
540 S4(RC, RA, RD, RB, RE); LK(RA, RD, RB, RE, RC, 5);
541 S5(RA, RD, RB, RE, RC); LK(RC, RA, RD, RE, RB, 6);
542 S6(RC, RA, RD, RE, RB); LK(RD, RB, RA, RE, RC, 7);
543 S7(RD, RB, RA, RE, RC); LK(RC, RA, RE, RD, RB, 8);
544 S0(RC, RA, RE, RD, RB); LK(RE, RA, RD, RC, RB, 9);
545 S1(RE, RA, RD, RC, RB); LK(RB, RD, RC, RE, RA, 10);
546 S2(RB, RD, RC, RE, RA); LK(RA, RD, RB, RE, RC, 11);
547 S3(RA, RD, RB, RE, RC); LK(RE, RC, RD, RA, RB, 12);
548 S4(RE, RC, RD, RA, RB); LK(RC, RD, RA, RB, RE, 13);
549 S5(RC, RD, RA, RB, RE); LK(RE, RC, RD, RB, RA, 14);
550 S6(RE, RC, RD, RB, RA); LK(RD, RA, RC, RB, RE, 15);
551 S7(RD, RA, RC, RB, RE); LK(RE, RC, RB, RD, RA, 16);
552 S0(RE, RC, RB, RD, RA); LK(RB, RC, RD, RE, RA, 17);
553 S1(RB, RC, RD, RE, RA); LK(RA, RD, RE, RB, RC, 18);
554 S2(RA, RD, RE, RB, RC); LK(RC, RD, RA, RB, RE, 19);
555 S3(RC, RD, RA, RB, RE); LK(RB, RE, RD, RC, RA, 20);
556 S4(RB, RE, RD, RC, RA); LK(RE, RD, RC, RA, RB, 21);
557 S5(RE, RD, RC, RA, RB); LK(RB, RE, RD, RA, RC, 22);
558 S6(RB, RE, RD, RA, RC); LK(RD, RC, RE, RA, RB, 23);
559 S7(RD, RC, RE, RA, RB); LK(RB, RE, RA, RD, RC, 24);
560 S0(RB, RE, RA, RD, RC); LK(RA, RE, RD, RB, RC, 25);
561 S1(RA, RE, RD, RB, RC); LK(RC, RD, RB, RA, RE, 26);
562 S2(RC, RD, RB, RA, RE); LK(RE, RD, RC, RA, RB, 27);
563 S3(RE, RD, RC, RA, RB); LK(RA, RB, RD, RE, RC, 28);
564 S4(RA, RB, RD, RE, RC); LK(RB, RD, RE, RC, RA, 29);
565 S5(RB, RD, RE, RC, RA); LK(RA, RB, RD, RC, RE, 30);
566 S6(RA, RB, RD, RC, RE); LK(RD, RE, RB, RC, RA, 31);
567 S7(RD, RE, RB, RC, RA); K(RA, RB, RC, RD, RE, 32);
568
569 movl arg_dst(%esp), %eax;
570
571 cmpb $0, arg_xor(%esp);
572 jnz __enc_xor4;
573
574 write_blocks(%eax, RA, RB, RC, RD, RT0, RT1, RE);
575
576 ret;
577
578__enc_xor4:
579 xor_blocks(%eax, RA, RB, RC, RD, RT0, RT1, RE);
580
581 ret;
582
583.align 8
584.global serpent_dec_blk_4way
585.type serpent_dec_blk_4way,@function;
586
587serpent_dec_blk_4way:
588 /* input:
589 * arg_ctx(%esp): ctx, CTX
590 * arg_dst(%esp): dst
591 * arg_src(%esp): src
592 */
593
594 pcmpeqd RNOT, RNOT;
595
596 movl arg_ctx(%esp), CTX;
597
598 movl arg_src(%esp), %eax;
599 read_blocks(%eax, RA, RB, RC, RD, RT0, RT1, RE);
600
601 K(RA, RB, RC, RD, RE, 32);
602 SI7(RA, RB, RC, RD, RE); KL(RB, RD, RA, RE, RC, 31);
603 SI6(RB, RD, RA, RE, RC); KL(RA, RC, RE, RB, RD, 30);
604 SI5(RA, RC, RE, RB, RD); KL(RC, RD, RA, RE, RB, 29);
605 SI4(RC, RD, RA, RE, RB); KL(RC, RA, RB, RE, RD, 28);
606 SI3(RC, RA, RB, RE, RD); KL(RB, RC, RD, RE, RA, 27);
607 SI2(RB, RC, RD, RE, RA); KL(RC, RA, RE, RD, RB, 26);
608 SI1(RC, RA, RE, RD, RB); KL(RB, RA, RE, RD, RC, 25);
609 SI0(RB, RA, RE, RD, RC); KL(RE, RC, RA, RB, RD, 24);
610 SI7(RE, RC, RA, RB, RD); KL(RC, RB, RE, RD, RA, 23);
611 SI6(RC, RB, RE, RD, RA); KL(RE, RA, RD, RC, RB, 22);
612 SI5(RE, RA, RD, RC, RB); KL(RA, RB, RE, RD, RC, 21);
613 SI4(RA, RB, RE, RD, RC); KL(RA, RE, RC, RD, RB, 20);
614 SI3(RA, RE, RC, RD, RB); KL(RC, RA, RB, RD, RE, 19);
615 SI2(RC, RA, RB, RD, RE); KL(RA, RE, RD, RB, RC, 18);
616 SI1(RA, RE, RD, RB, RC); KL(RC, RE, RD, RB, RA, 17);
617 SI0(RC, RE, RD, RB, RA); KL(RD, RA, RE, RC, RB, 16);
618 SI7(RD, RA, RE, RC, RB); KL(RA, RC, RD, RB, RE, 15);
619 SI6(RA, RC, RD, RB, RE); KL(RD, RE, RB, RA, RC, 14);
620 SI5(RD, RE, RB, RA, RC); KL(RE, RC, RD, RB, RA, 13);
621 SI4(RE, RC, RD, RB, RA); KL(RE, RD, RA, RB, RC, 12);
622 SI3(RE, RD, RA, RB, RC); KL(RA, RE, RC, RB, RD, 11);
623 SI2(RA, RE, RC, RB, RD); KL(RE, RD, RB, RC, RA, 10);
624 SI1(RE, RD, RB, RC, RA); KL(RA, RD, RB, RC, RE, 9);
625 SI0(RA, RD, RB, RC, RE); KL(RB, RE, RD, RA, RC, 8);
626 SI7(RB, RE, RD, RA, RC); KL(RE, RA, RB, RC, RD, 7);
627 SI6(RE, RA, RB, RC, RD); KL(RB, RD, RC, RE, RA, 6);
628 SI5(RB, RD, RC, RE, RA); KL(RD, RA, RB, RC, RE, 5);
629 SI4(RD, RA, RB, RC, RE); KL(RD, RB, RE, RC, RA, 4);
630 SI3(RD, RB, RE, RC, RA); KL(RE, RD, RA, RC, RB, 3);
631 SI2(RE, RD, RA, RC, RB); KL(RD, RB, RC, RA, RE, 2);
632 SI1(RD, RB, RC, RA, RE); KL(RE, RB, RC, RA, RD, 1);
633 SI0(RE, RB, RC, RA, RD); K(RC, RD, RB, RE, RA, 0);
634
635 movl arg_dst(%esp), %eax;
636 write_blocks(%eax, RC, RD, RB, RE, RT0, RT1, RA);
637
638 ret;
diff --git a/arch/x86/crypto/serpent-sse2-x86_64-asm_64.S b/arch/x86/crypto/serpent-sse2-x86_64-asm_64.S
new file mode 100644
index 000000000000..7f24a1540821
--- /dev/null
+++ b/arch/x86/crypto/serpent-sse2-x86_64-asm_64.S
@@ -0,0 +1,761 @@
1/*
2 * Serpent Cipher 8-way parallel algorithm (x86_64/SSE2)
3 *
4 * Copyright (C) 2011 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
5 *
6 * Based on crypto/serpent.c by
7 * Copyright (C) 2002 Dag Arne Osvik <osvik@ii.uib.no>
8 * 2003 Herbert Valerio Riedel <hvr@gnu.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
23 * USA
24 *
25 */
26
27.file "serpent-sse2-x86_64-asm_64.S"
28.text
29
30#define CTX %rdi
31
32/**********************************************************************
33 8-way SSE2 serpent
34 **********************************************************************/
35#define RA1 %xmm0
36#define RB1 %xmm1
37#define RC1 %xmm2
38#define RD1 %xmm3
39#define RE1 %xmm4
40
41#define RA2 %xmm5
42#define RB2 %xmm6
43#define RC2 %xmm7
44#define RD2 %xmm8
45#define RE2 %xmm9
46
47#define RNOT %xmm10
48
49#define RK0 %xmm11
50#define RK1 %xmm12
51#define RK2 %xmm13
52#define RK3 %xmm14
53
54#define S0_1(x0, x1, x2, x3, x4) \
55 movdqa x3, x4; \
56 por x0, x3; \
57 pxor x4, x0; \
58 pxor x2, x4; \
59 pxor RNOT, x4; \
60 pxor x1, x3; \
61 pand x0, x1; \
62 pxor x4, x1; \
63 pxor x0, x2;
64#define S0_2(x0, x1, x2, x3, x4) \
65 pxor x3, x0; \
66 por x0, x4; \
67 pxor x2, x0; \
68 pand x1, x2; \
69 pxor x2, x3; \
70 pxor RNOT, x1; \
71 pxor x4, x2; \
72 pxor x2, x1;
73
74#define S1_1(x0, x1, x2, x3, x4) \
75 movdqa x1, x4; \
76 pxor x0, x1; \
77 pxor x3, x0; \
78 pxor RNOT, x3; \
79 pand x1, x4; \
80 por x1, x0; \
81 pxor x2, x3; \
82 pxor x3, x0; \
83 pxor x3, x1;
84#define S1_2(x0, x1, x2, x3, x4) \
85 pxor x4, x3; \
86 por x4, x1; \
87 pxor x2, x4; \
88 pand x0, x2; \
89 pxor x1, x2; \
90 por x0, x1; \
91 pxor RNOT, x0; \
92 pxor x2, x0; \
93 pxor x1, x4;
94
95#define S2_1(x0, x1, x2, x3, x4) \
96 pxor RNOT, x3; \
97 pxor x0, x1; \
98 movdqa x0, x4; \
99 pand x2, x0; \
100 pxor x3, x0; \
101 por x4, x3; \
102 pxor x1, x2; \
103 pxor x1, x3; \
104 pand x0, x1;
105#define S2_2(x0, x1, x2, x3, x4) \
106 pxor x2, x0; \
107 pand x3, x2; \
108 por x1, x3; \
109 pxor RNOT, x0; \
110 pxor x0, x3; \
111 pxor x0, x4; \
112 pxor x2, x0; \
113 por x2, x1;
114
115#define S3_1(x0, x1, x2, x3, x4) \
116 movdqa x1, x4; \
117 pxor x3, x1; \
118 por x0, x3; \
119 pand x0, x4; \
120 pxor x2, x0; \
121 pxor x1, x2; \
122 pand x3, x1; \
123 pxor x3, x2; \
124 por x4, x0; \
125 pxor x3, x4;
126#define S3_2(x0, x1, x2, x3, x4) \
127 pxor x0, x1; \
128 pand x3, x0; \
129 pand x4, x3; \
130 pxor x2, x3; \
131 por x1, x4; \
132 pand x1, x2; \
133 pxor x3, x4; \
134 pxor x3, x0; \
135 pxor x2, x3;
136
137#define S4_1(x0, x1, x2, x3, x4) \
138 movdqa x3, x4; \
139 pand x0, x3; \
140 pxor x4, x0; \
141 pxor x2, x3; \
142 por x4, x2; \
143 pxor x1, x0; \
144 pxor x3, x4; \
145 por x0, x2; \
146 pxor x1, x2;
147#define S4_2(x0, x1, x2, x3, x4) \
148 pand x0, x1; \
149 pxor x4, x1; \
150 pand x2, x4; \
151 pxor x3, x2; \
152 pxor x0, x4; \
153 por x1, x3; \
154 pxor RNOT, x1; \
155 pxor x0, x3;
156
157#define S5_1(x0, x1, x2, x3, x4) \
158 movdqa x1, x4; \
159 por x0, x1; \
160 pxor x1, x2; \
161 pxor RNOT, x3; \
162 pxor x0, x4; \
163 pxor x2, x0; \
164 pand x4, x1; \
165 por x3, x4; \
166 pxor x0, x4;
167#define S5_2(x0, x1, x2, x3, x4) \
168 pand x3, x0; \
169 pxor x3, x1; \
170 pxor x2, x3; \
171 pxor x1, x0; \
172 pand x4, x2; \
173 pxor x2, x1; \
174 pand x0, x2; \
175 pxor x2, x3;
176
177#define S6_1(x0, x1, x2, x3, x4) \
178 movdqa x1, x4; \
179 pxor x0, x3; \
180 pxor x2, x1; \
181 pxor x0, x2; \
182 pand x3, x0; \
183 por x3, x1; \
184 pxor RNOT, x4; \
185 pxor x1, x0; \
186 pxor x2, x1;
187#define S6_2(x0, x1, x2, x3, x4) \
188 pxor x4, x3; \
189 pxor x0, x4; \
190 pand x0, x2; \
191 pxor x1, x4; \
192 pxor x3, x2; \
193 pand x1, x3; \
194 pxor x0, x3; \
195 pxor x2, x1;
196
197#define S7_1(x0, x1, x2, x3, x4) \
198 pxor RNOT, x1; \
199 movdqa x1, x4; \
200 pxor RNOT, x0; \
201 pand x2, x1; \
202 pxor x3, x1; \
203 por x4, x3; \
204 pxor x2, x4; \
205 pxor x3, x2; \
206 pxor x0, x3; \
207 por x1, x0;
208#define S7_2(x0, x1, x2, x3, x4) \
209 pand x0, x2; \
210 pxor x4, x0; \
211 pxor x3, x4; \
212 pand x0, x3; \
213 pxor x1, x4; \
214 pxor x4, x2; \
215 pxor x1, x3; \
216 por x0, x4; \
217 pxor x1, x4;
218
219#define SI0_1(x0, x1, x2, x3, x4) \
220 movdqa x3, x4; \
221 pxor x0, x1; \
222 por x1, x3; \
223 pxor x1, x4; \
224 pxor RNOT, x0; \
225 pxor x3, x2; \
226 pxor x0, x3; \
227 pand x1, x0; \
228 pxor x2, x0;
229#define SI0_2(x0, x1, x2, x3, x4) \
230 pand x3, x2; \
231 pxor x4, x3; \
232 pxor x3, x2; \
233 pxor x3, x1; \
234 pand x0, x3; \
235 pxor x0, x1; \
236 pxor x2, x0; \
237 pxor x3, x4;
238
239#define SI1_1(x0, x1, x2, x3, x4) \
240 pxor x3, x1; \
241 movdqa x0, x4; \
242 pxor x2, x0; \
243 pxor RNOT, x2; \
244 por x1, x4; \
245 pxor x3, x4; \
246 pand x1, x3; \
247 pxor x2, x1; \
248 pand x4, x2;
249#define SI1_2(x0, x1, x2, x3, x4) \
250 pxor x1, x4; \
251 por x3, x1; \
252 pxor x0, x3; \
253 pxor x0, x2; \
254 por x4, x0; \
255 pxor x4, x2; \
256 pxor x0, x1; \
257 pxor x1, x4;
258
259#define SI2_1(x0, x1, x2, x3, x4) \
260 pxor x1, x2; \
261 movdqa x3, x4; \
262 pxor RNOT, x3; \
263 por x2, x3; \
264 pxor x4, x2; \
265 pxor x0, x4; \
266 pxor x1, x3; \
267 por x2, x1; \
268 pxor x0, x2;
269#define SI2_2(x0, x1, x2, x3, x4) \
270 pxor x4, x1; \
271 por x3, x4; \
272 pxor x3, x2; \
273 pxor x2, x4; \
274 pand x1, x2; \
275 pxor x3, x2; \
276 pxor x4, x3; \
277 pxor x0, x4;
278
279#define SI3_1(x0, x1, x2, x3, x4) \
280 pxor x1, x2; \
281 movdqa x1, x4; \
282 pand x2, x1; \
283 pxor x0, x1; \
284 por x4, x0; \
285 pxor x3, x4; \
286 pxor x3, x0; \
287 por x1, x3; \
288 pxor x2, x1;
289#define SI3_2(x0, x1, x2, x3, x4) \
290 pxor x3, x1; \
291 pxor x2, x0; \
292 pxor x3, x2; \
293 pand x1, x3; \
294 pxor x0, x1; \
295 pand x2, x0; \
296 pxor x3, x4; \
297 pxor x0, x3; \
298 pxor x1, x0;
299
300#define SI4_1(x0, x1, x2, x3, x4) \
301 pxor x3, x2; \
302 movdqa x0, x4; \
303 pand x1, x0; \
304 pxor x2, x0; \
305 por x3, x2; \
306 pxor RNOT, x4; \
307 pxor x0, x1; \
308 pxor x2, x0; \
309 pand x4, x2;
310#define SI4_2(x0, x1, x2, x3, x4) \
311 pxor x0, x2; \
312 por x4, x0; \
313 pxor x3, x0; \
314 pand x2, x3; \
315 pxor x3, x4; \
316 pxor x1, x3; \
317 pand x0, x1; \
318 pxor x1, x4; \
319 pxor x3, x0;
320
321#define SI5_1(x0, x1, x2, x3, x4) \
322 movdqa x1, x4; \
323 por x2, x1; \
324 pxor x4, x2; \
325 pxor x3, x1; \
326 pand x4, x3; \
327 pxor x3, x2; \
328 por x0, x3; \
329 pxor RNOT, x0; \
330 pxor x2, x3; \
331 por x0, x2;
332#define SI5_2(x0, x1, x2, x3, x4) \
333 pxor x1, x4; \
334 pxor x4, x2; \
335 pand x0, x4; \
336 pxor x1, x0; \
337 pxor x3, x1; \
338 pand x2, x0; \
339 pxor x3, x2; \
340 pxor x2, x0; \
341 pxor x4, x2; \
342 pxor x3, x4;
343
344#define SI6_1(x0, x1, x2, x3, x4) \
345 pxor x2, x0; \
346 movdqa x0, x4; \
347 pand x3, x0; \
348 pxor x3, x2; \
349 pxor x2, x0; \
350 pxor x1, x3; \
351 por x4, x2; \
352 pxor x3, x2; \
353 pand x0, x3;
354#define SI6_2(x0, x1, x2, x3, x4) \
355 pxor RNOT, x0; \
356 pxor x1, x3; \
357 pand x2, x1; \
358 pxor x0, x4; \
359 pxor x4, x3; \
360 pxor x2, x4; \
361 pxor x1, x0; \
362 pxor x0, x2;
363
364#define SI7_1(x0, x1, x2, x3, x4) \
365 movdqa x3, x4; \
366 pand x0, x3; \
367 pxor x2, x0; \
368 por x4, x2; \
369 pxor x1, x4; \
370 pxor RNOT, x0; \
371 por x3, x1; \
372 pxor x0, x4; \
373 pand x2, x0; \
374 pxor x1, x0;
375#define SI7_2(x0, x1, x2, x3, x4) \
376 pand x2, x1; \
377 pxor x2, x3; \
378 pxor x3, x4; \
379 pand x3, x2; \
380 por x0, x3; \
381 pxor x4, x1; \
382 pxor x4, x3; \
383 pand x0, x4; \
384 pxor x2, x4;
385
386#define get_key(i, j, t) \
387 movd (4*(i)+(j))*4(CTX), t; \
388 pshufd $0, t, t;
389
390#define K2(x0, x1, x2, x3, x4, i) \
391 get_key(i, 0, RK0); \
392 get_key(i, 1, RK1); \
393 get_key(i, 2, RK2); \
394 get_key(i, 3, RK3); \
395 pxor RK0, x0 ## 1; \
396 pxor RK1, x1 ## 1; \
397 pxor RK2, x2 ## 1; \
398 pxor RK3, x3 ## 1; \
399 pxor RK0, x0 ## 2; \
400 pxor RK1, x1 ## 2; \
401 pxor RK2, x2 ## 2; \
402 pxor RK3, x3 ## 2;
403
404#define LK2(x0, x1, x2, x3, x4, i) \
405 movdqa x0 ## 1, x4 ## 1; \
406 pslld $13, x0 ## 1; \
407 psrld $(32 - 13), x4 ## 1; \
408 por x4 ## 1, x0 ## 1; \
409 pxor x0 ## 1, x1 ## 1; \
410 movdqa x2 ## 1, x4 ## 1; \
411 pslld $3, x2 ## 1; \
412 psrld $(32 - 3), x4 ## 1; \
413 por x4 ## 1, x2 ## 1; \
414 pxor x2 ## 1, x1 ## 1; \
415 movdqa x0 ## 2, x4 ## 2; \
416 pslld $13, x0 ## 2; \
417 psrld $(32 - 13), x4 ## 2; \
418 por x4 ## 2, x0 ## 2; \
419 pxor x0 ## 2, x1 ## 2; \
420 movdqa x2 ## 2, x4 ## 2; \
421 pslld $3, x2 ## 2; \
422 psrld $(32 - 3), x4 ## 2; \
423 por x4 ## 2, x2 ## 2; \
424 pxor x2 ## 2, x1 ## 2; \
425 movdqa x1 ## 1, x4 ## 1; \
426 pslld $1, x1 ## 1; \
427 psrld $(32 - 1), x4 ## 1; \
428 por x4 ## 1, x1 ## 1; \
429 movdqa x0 ## 1, x4 ## 1; \
430 pslld $3, x4 ## 1; \
431 pxor x2 ## 1, x3 ## 1; \
432 pxor x4 ## 1, x3 ## 1; \
433 movdqa x3 ## 1, x4 ## 1; \
434 get_key(i, 1, RK1); \
435 movdqa x1 ## 2, x4 ## 2; \
436 pslld $1, x1 ## 2; \
437 psrld $(32 - 1), x4 ## 2; \
438 por x4 ## 2, x1 ## 2; \
439 movdqa x0 ## 2, x4 ## 2; \
440 pslld $3, x4 ## 2; \
441 pxor x2 ## 2, x3 ## 2; \
442 pxor x4 ## 2, x3 ## 2; \
443 movdqa x3 ## 2, x4 ## 2; \
444 get_key(i, 3, RK3); \
445 pslld $7, x3 ## 1; \
446 psrld $(32 - 7), x4 ## 1; \
447 por x4 ## 1, x3 ## 1; \
448 movdqa x1 ## 1, x4 ## 1; \
449 pslld $7, x4 ## 1; \
450 pxor x1 ## 1, x0 ## 1; \
451 pxor x3 ## 1, x0 ## 1; \
452 pxor x3 ## 1, x2 ## 1; \
453 pxor x4 ## 1, x2 ## 1; \
454 get_key(i, 0, RK0); \
455 pslld $7, x3 ## 2; \
456 psrld $(32 - 7), x4 ## 2; \
457 por x4 ## 2, x3 ## 2; \
458 movdqa x1 ## 2, x4 ## 2; \
459 pslld $7, x4 ## 2; \
460 pxor x1 ## 2, x0 ## 2; \
461 pxor x3 ## 2, x0 ## 2; \
462 pxor x3 ## 2, x2 ## 2; \
463 pxor x4 ## 2, x2 ## 2; \
464 get_key(i, 2, RK2); \
465 pxor RK1, x1 ## 1; \
466 pxor RK3, x3 ## 1; \
467 movdqa x0 ## 1, x4 ## 1; \
468 pslld $5, x0 ## 1; \
469 psrld $(32 - 5), x4 ## 1; \
470 por x4 ## 1, x0 ## 1; \
471 movdqa x2 ## 1, x4 ## 1; \
472 pslld $22, x2 ## 1; \
473 psrld $(32 - 22), x4 ## 1; \
474 por x4 ## 1, x2 ## 1; \
475 pxor RK0, x0 ## 1; \
476 pxor RK2, x2 ## 1; \
477 pxor RK1, x1 ## 2; \
478 pxor RK3, x3 ## 2; \
479 movdqa x0 ## 2, x4 ## 2; \
480 pslld $5, x0 ## 2; \
481 psrld $(32 - 5), x4 ## 2; \
482 por x4 ## 2, x0 ## 2; \
483 movdqa x2 ## 2, x4 ## 2; \
484 pslld $22, x2 ## 2; \
485 psrld $(32 - 22), x4 ## 2; \
486 por x4 ## 2, x2 ## 2; \
487 pxor RK0, x0 ## 2; \
488 pxor RK2, x2 ## 2;
489
490#define KL2(x0, x1, x2, x3, x4, i) \
491 pxor RK0, x0 ## 1; \
492 pxor RK2, x2 ## 1; \
493 movdqa x0 ## 1, x4 ## 1; \
494 psrld $5, x0 ## 1; \
495 pslld $(32 - 5), x4 ## 1; \
496 por x4 ## 1, x0 ## 1; \
497 pxor RK3, x3 ## 1; \
498 pxor RK1, x1 ## 1; \
499 movdqa x2 ## 1, x4 ## 1; \
500 psrld $22, x2 ## 1; \
501 pslld $(32 - 22), x4 ## 1; \
502 por x4 ## 1, x2 ## 1; \
503 pxor x3 ## 1, x2 ## 1; \
504 pxor RK0, x0 ## 2; \
505 pxor RK2, x2 ## 2; \
506 movdqa x0 ## 2, x4 ## 2; \
507 psrld $5, x0 ## 2; \
508 pslld $(32 - 5), x4 ## 2; \
509 por x4 ## 2, x0 ## 2; \
510 pxor RK3, x3 ## 2; \
511 pxor RK1, x1 ## 2; \
512 movdqa x2 ## 2, x4 ## 2; \
513 psrld $22, x2 ## 2; \
514 pslld $(32 - 22), x4 ## 2; \
515 por x4 ## 2, x2 ## 2; \
516 pxor x3 ## 2, x2 ## 2; \
517 pxor x3 ## 1, x0 ## 1; \
518 movdqa x1 ## 1, x4 ## 1; \
519 pslld $7, x4 ## 1; \
520 pxor x1 ## 1, x0 ## 1; \
521 pxor x4 ## 1, x2 ## 1; \
522 movdqa x1 ## 1, x4 ## 1; \
523 psrld $1, x1 ## 1; \
524 pslld $(32 - 1), x4 ## 1; \
525 por x4 ## 1, x1 ## 1; \
526 pxor x3 ## 2, x0 ## 2; \
527 movdqa x1 ## 2, x4 ## 2; \
528 pslld $7, x4 ## 2; \
529 pxor x1 ## 2, x0 ## 2; \
530 pxor x4 ## 2, x2 ## 2; \
531 movdqa x1 ## 2, x4 ## 2; \
532 psrld $1, x1 ## 2; \
533 pslld $(32 - 1), x4 ## 2; \
534 por x4 ## 2, x1 ## 2; \
535 movdqa x3 ## 1, x4 ## 1; \
536 psrld $7, x3 ## 1; \
537 pslld $(32 - 7), x4 ## 1; \
538 por x4 ## 1, x3 ## 1; \
539 pxor x0 ## 1, x1 ## 1; \
540 movdqa x0 ## 1, x4 ## 1; \
541 pslld $3, x4 ## 1; \
542 pxor x4 ## 1, x3 ## 1; \
543 movdqa x0 ## 1, x4 ## 1; \
544 movdqa x3 ## 2, x4 ## 2; \
545 psrld $7, x3 ## 2; \
546 pslld $(32 - 7), x4 ## 2; \
547 por x4 ## 2, x3 ## 2; \
548 pxor x0 ## 2, x1 ## 2; \
549 movdqa x0 ## 2, x4 ## 2; \
550 pslld $3, x4 ## 2; \
551 pxor x4 ## 2, x3 ## 2; \
552 movdqa x0 ## 2, x4 ## 2; \
553 psrld $13, x0 ## 1; \
554 pslld $(32 - 13), x4 ## 1; \
555 por x4 ## 1, x0 ## 1; \
556 pxor x2 ## 1, x1 ## 1; \
557 pxor x2 ## 1, x3 ## 1; \
558 movdqa x2 ## 1, x4 ## 1; \
559 psrld $3, x2 ## 1; \
560 pslld $(32 - 3), x4 ## 1; \
561 por x4 ## 1, x2 ## 1; \
562 psrld $13, x0 ## 2; \
563 pslld $(32 - 13), x4 ## 2; \
564 por x4 ## 2, x0 ## 2; \
565 pxor x2 ## 2, x1 ## 2; \
566 pxor x2 ## 2, x3 ## 2; \
567 movdqa x2 ## 2, x4 ## 2; \
568 psrld $3, x2 ## 2; \
569 pslld $(32 - 3), x4 ## 2; \
570 por x4 ## 2, x2 ## 2;
571
572#define S(SBOX, x0, x1, x2, x3, x4) \
573 SBOX ## _1(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
574 SBOX ## _2(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
575 SBOX ## _1(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2); \
576 SBOX ## _2(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2);
577
578#define SP(SBOX, x0, x1, x2, x3, x4, i) \
579 get_key(i, 0, RK0); \
580 SBOX ## _1(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
581 get_key(i, 2, RK2); \
582 SBOX ## _1(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2); \
583 get_key(i, 3, RK3); \
584 SBOX ## _2(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
585 get_key(i, 1, RK1); \
586 SBOX ## _2(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2); \
587
588#define transpose_4x4(x0, x1, x2, x3, t1, t2, t3) \
589 movdqa x2, t3; \
590 movdqa x0, t1; \
591 unpcklps x3, t3; \
592 movdqa x0, t2; \
593 unpcklps x1, t1; \
594 unpckhps x1, t2; \
595 movdqa t3, x1; \
596 unpckhps x3, x2; \
597 movdqa t1, x0; \
598 movhlps t1, x1; \
599 movdqa t2, t1; \
600 movlhps t3, x0; \
601 movlhps x2, t1; \
602 movhlps t2, x2; \
603 movdqa x2, x3; \
604 movdqa t1, x2;
605
606#define read_blocks(in, x0, x1, x2, x3, t0, t1, t2) \
607 movdqu (0*4*4)(in), x0; \
608 movdqu (1*4*4)(in), x1; \
609 movdqu (2*4*4)(in), x2; \
610 movdqu (3*4*4)(in), x3; \
611 \
612 transpose_4x4(x0, x1, x2, x3, t0, t1, t2)
613
614#define write_blocks(out, x0, x1, x2, x3, t0, t1, t2) \
615 transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
616 \
617 movdqu x0, (0*4*4)(out); \
618 movdqu x1, (1*4*4)(out); \
619 movdqu x2, (2*4*4)(out); \
620 movdqu x3, (3*4*4)(out);
621
622#define xor_blocks(out, x0, x1, x2, x3, t0, t1, t2) \
623 transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
624 \
625 movdqu (0*4*4)(out), t0; \
626 pxor t0, x0; \
627 movdqu x0, (0*4*4)(out); \
628 movdqu (1*4*4)(out), t0; \
629 pxor t0, x1; \
630 movdqu x1, (1*4*4)(out); \
631 movdqu (2*4*4)(out), t0; \
632 pxor t0, x2; \
633 movdqu x2, (2*4*4)(out); \
634 movdqu (3*4*4)(out), t0; \
635 pxor t0, x3; \
636 movdqu x3, (3*4*4)(out);
637
638.align 8
639.global __serpent_enc_blk_8way
640.type __serpent_enc_blk_8way,@function;
641
642__serpent_enc_blk_8way:
643 /* input:
644 * %rdi: ctx, CTX
645 * %rsi: dst
646 * %rdx: src
647 * %rcx: bool, if true: xor output
648 */
649
650 pcmpeqd RNOT, RNOT;
651
652 leaq (4*4*4)(%rdx), %rax;
653 read_blocks(%rdx, RA1, RB1, RC1, RD1, RK0, RK1, RK2);
654 read_blocks(%rax, RA2, RB2, RC2, RD2, RK0, RK1, RK2);
655
656 K2(RA, RB, RC, RD, RE, 0);
657 S(S0, RA, RB, RC, RD, RE); LK2(RC, RB, RD, RA, RE, 1);
658 S(S1, RC, RB, RD, RA, RE); LK2(RE, RD, RA, RC, RB, 2);
659 S(S2, RE, RD, RA, RC, RB); LK2(RB, RD, RE, RC, RA, 3);
660 S(S3, RB, RD, RE, RC, RA); LK2(RC, RA, RD, RB, RE, 4);
661 S(S4, RC, RA, RD, RB, RE); LK2(RA, RD, RB, RE, RC, 5);
662 S(S5, RA, RD, RB, RE, RC); LK2(RC, RA, RD, RE, RB, 6);
663 S(S6, RC, RA, RD, RE, RB); LK2(RD, RB, RA, RE, RC, 7);
664 S(S7, RD, RB, RA, RE, RC); LK2(RC, RA, RE, RD, RB, 8);
665 S(S0, RC, RA, RE, RD, RB); LK2(RE, RA, RD, RC, RB, 9);
666 S(S1, RE, RA, RD, RC, RB); LK2(RB, RD, RC, RE, RA, 10);
667 S(S2, RB, RD, RC, RE, RA); LK2(RA, RD, RB, RE, RC, 11);
668 S(S3, RA, RD, RB, RE, RC); LK2(RE, RC, RD, RA, RB, 12);
669 S(S4, RE, RC, RD, RA, RB); LK2(RC, RD, RA, RB, RE, 13);
670 S(S5, RC, RD, RA, RB, RE); LK2(RE, RC, RD, RB, RA, 14);
671 S(S6, RE, RC, RD, RB, RA); LK2(RD, RA, RC, RB, RE, 15);
672 S(S7, RD, RA, RC, RB, RE); LK2(RE, RC, RB, RD, RA, 16);
673 S(S0, RE, RC, RB, RD, RA); LK2(RB, RC, RD, RE, RA, 17);
674 S(S1, RB, RC, RD, RE, RA); LK2(RA, RD, RE, RB, RC, 18);
675 S(S2, RA, RD, RE, RB, RC); LK2(RC, RD, RA, RB, RE, 19);
676 S(S3, RC, RD, RA, RB, RE); LK2(RB, RE, RD, RC, RA, 20);
677 S(S4, RB, RE, RD, RC, RA); LK2(RE, RD, RC, RA, RB, 21);
678 S(S5, RE, RD, RC, RA, RB); LK2(RB, RE, RD, RA, RC, 22);
679 S(S6, RB, RE, RD, RA, RC); LK2(RD, RC, RE, RA, RB, 23);
680 S(S7, RD, RC, RE, RA, RB); LK2(RB, RE, RA, RD, RC, 24);
681 S(S0, RB, RE, RA, RD, RC); LK2(RA, RE, RD, RB, RC, 25);
682 S(S1, RA, RE, RD, RB, RC); LK2(RC, RD, RB, RA, RE, 26);
683 S(S2, RC, RD, RB, RA, RE); LK2(RE, RD, RC, RA, RB, 27);
684 S(S3, RE, RD, RC, RA, RB); LK2(RA, RB, RD, RE, RC, 28);
685 S(S4, RA, RB, RD, RE, RC); LK2(RB, RD, RE, RC, RA, 29);
686 S(S5, RB, RD, RE, RC, RA); LK2(RA, RB, RD, RC, RE, 30);
687 S(S6, RA, RB, RD, RC, RE); LK2(RD, RE, RB, RC, RA, 31);
688 S(S7, RD, RE, RB, RC, RA); K2(RA, RB, RC, RD, RE, 32);
689
690 leaq (4*4*4)(%rsi), %rax;
691
692 testb %cl, %cl;
693 jnz __enc_xor8;
694
695 write_blocks(%rsi, RA1, RB1, RC1, RD1, RK0, RK1, RK2);
696 write_blocks(%rax, RA2, RB2, RC2, RD2, RK0, RK1, RK2);
697
698 ret;
699
700__enc_xor8:
701 xor_blocks(%rsi, RA1, RB1, RC1, RD1, RK0, RK1, RK2);
702 xor_blocks(%rax, RA2, RB2, RC2, RD2, RK0, RK1, RK2);
703
704 ret;
705
706.align 8
707.global serpent_dec_blk_8way
708.type serpent_dec_blk_8way,@function;
709
710serpent_dec_blk_8way:
711 /* input:
712 * %rdi: ctx, CTX
713 * %rsi: dst
714 * %rdx: src
715 */
716
717 pcmpeqd RNOT, RNOT;
718
719 leaq (4*4*4)(%rdx), %rax;
720 read_blocks(%rdx, RA1, RB1, RC1, RD1, RK0, RK1, RK2);
721 read_blocks(%rax, RA2, RB2, RC2, RD2, RK0, RK1, RK2);
722
723 K2(RA, RB, RC, RD, RE, 32);
724 SP(SI7, RA, RB, RC, RD, RE, 31); KL2(RB, RD, RA, RE, RC, 31);
725 SP(SI6, RB, RD, RA, RE, RC, 30); KL2(RA, RC, RE, RB, RD, 30);
726 SP(SI5, RA, RC, RE, RB, RD, 29); KL2(RC, RD, RA, RE, RB, 29);
727 SP(SI4, RC, RD, RA, RE, RB, 28); KL2(RC, RA, RB, RE, RD, 28);
728 SP(SI3, RC, RA, RB, RE, RD, 27); KL2(RB, RC, RD, RE, RA, 27);
729 SP(SI2, RB, RC, RD, RE, RA, 26); KL2(RC, RA, RE, RD, RB, 26);
730 SP(SI1, RC, RA, RE, RD, RB, 25); KL2(RB, RA, RE, RD, RC, 25);
731 SP(SI0, RB, RA, RE, RD, RC, 24); KL2(RE, RC, RA, RB, RD, 24);
732 SP(SI7, RE, RC, RA, RB, RD, 23); KL2(RC, RB, RE, RD, RA, 23);
733 SP(SI6, RC, RB, RE, RD, RA, 22); KL2(RE, RA, RD, RC, RB, 22);
734 SP(SI5, RE, RA, RD, RC, RB, 21); KL2(RA, RB, RE, RD, RC, 21);
735 SP(SI4, RA, RB, RE, RD, RC, 20); KL2(RA, RE, RC, RD, RB, 20);
736 SP(SI3, RA, RE, RC, RD, RB, 19); KL2(RC, RA, RB, RD, RE, 19);
737 SP(SI2, RC, RA, RB, RD, RE, 18); KL2(RA, RE, RD, RB, RC, 18);
738 SP(SI1, RA, RE, RD, RB, RC, 17); KL2(RC, RE, RD, RB, RA, 17);
739 SP(SI0, RC, RE, RD, RB, RA, 16); KL2(RD, RA, RE, RC, RB, 16);
740 SP(SI7, RD, RA, RE, RC, RB, 15); KL2(RA, RC, RD, RB, RE, 15);
741 SP(SI6, RA, RC, RD, RB, RE, 14); KL2(RD, RE, RB, RA, RC, 14);
742 SP(SI5, RD, RE, RB, RA, RC, 13); KL2(RE, RC, RD, RB, RA, 13);
743 SP(SI4, RE, RC, RD, RB, RA, 12); KL2(RE, RD, RA, RB, RC, 12);
744 SP(SI3, RE, RD, RA, RB, RC, 11); KL2(RA, RE, RC, RB, RD, 11);
745 SP(SI2, RA, RE, RC, RB, RD, 10); KL2(RE, RD, RB, RC, RA, 10);
746 SP(SI1, RE, RD, RB, RC, RA, 9); KL2(RA, RD, RB, RC, RE, 9);
747 SP(SI0, RA, RD, RB, RC, RE, 8); KL2(RB, RE, RD, RA, RC, 8);
748 SP(SI7, RB, RE, RD, RA, RC, 7); KL2(RE, RA, RB, RC, RD, 7);
749 SP(SI6, RE, RA, RB, RC, RD, 6); KL2(RB, RD, RC, RE, RA, 6);
750 SP(SI5, RB, RD, RC, RE, RA, 5); KL2(RD, RA, RB, RC, RE, 5);
751 SP(SI4, RD, RA, RB, RC, RE, 4); KL2(RD, RB, RE, RC, RA, 4);
752 SP(SI3, RD, RB, RE, RC, RA, 3); KL2(RE, RD, RA, RC, RB, 3);
753 SP(SI2, RE, RD, RA, RC, RB, 2); KL2(RD, RB, RC, RA, RE, 2);
754 SP(SI1, RD, RB, RC, RA, RE, 1); KL2(RE, RB, RC, RA, RD, 1);
755 S(SI0, RE, RB, RC, RA, RD); K2(RC, RD, RB, RE, RA, 0);
756
757 leaq (4*4*4)(%rsi), %rax;
758 write_blocks(%rsi, RC1, RD1, RB1, RE1, RK0, RK1, RK2);
759 write_blocks(%rax, RC2, RD2, RB2, RE2, RK0, RK1, RK2);
760
761 ret;
diff --git a/arch/x86/crypto/serpent_sse2_glue.c b/arch/x86/crypto/serpent_sse2_glue.c
new file mode 100644
index 000000000000..7955a9b76b91
--- /dev/null
+++ b/arch/x86/crypto/serpent_sse2_glue.c
@@ -0,0 +1,1070 @@
1/*
2 * Glue Code for SSE2 assembler versions of Serpent Cipher
3 *
4 * Copyright (c) 2011 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
5 *
6 * Glue code based on aesni-intel_glue.c by:
7 * Copyright (C) 2008, Intel Corp.
8 * Author: Huang Ying <ying.huang@intel.com>
9 *
10 * CBC & ECB parts based on code (crypto/cbc.c,ecb.c) by:
11 * Copyright (c) 2006 Herbert Xu <herbert@gondor.apana.org.au>
12 * CTR part based on code (crypto/ctr.c) by:
13 * (C) Copyright IBM Corp. 2007 - Joy Latten <latten@us.ibm.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
28 * USA
29 *
30 */
31
32#include <linux/module.h>
33#include <linux/hardirq.h>
34#include <linux/types.h>
35#include <linux/crypto.h>
36#include <linux/err.h>
37#include <crypto/algapi.h>
38#include <crypto/serpent.h>
39#include <crypto/cryptd.h>
40#include <crypto/b128ops.h>
41#include <crypto/ctr.h>
42#include <crypto/lrw.h>
43#include <crypto/xts.h>
44#include <asm/i387.h>
45#include <asm/serpent.h>
46#include <crypto/scatterwalk.h>
47#include <linux/workqueue.h>
48#include <linux/spinlock.h>
49
50struct async_serpent_ctx {
51 struct cryptd_ablkcipher *cryptd_tfm;
52};
53
54static inline bool serpent_fpu_begin(bool fpu_enabled, unsigned int nbytes)
55{
56 if (fpu_enabled)
57 return true;
58
59 /* SSE2 is only used when chunk to be processed is large enough, so
60 * do not enable FPU until it is necessary.
61 */
62 if (nbytes < SERPENT_BLOCK_SIZE * SERPENT_PARALLEL_BLOCKS)
63 return false;
64
65 kernel_fpu_begin();
66 return true;
67}
68
69static inline void serpent_fpu_end(bool fpu_enabled)
70{
71 if (fpu_enabled)
72 kernel_fpu_end();
73}
74
75static int ecb_crypt(struct blkcipher_desc *desc, struct blkcipher_walk *walk,
76 bool enc)
77{
78 bool fpu_enabled = false;
79 struct serpent_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
80 const unsigned int bsize = SERPENT_BLOCK_SIZE;
81 unsigned int nbytes;
82 int err;
83
84 err = blkcipher_walk_virt(desc, walk);
85 desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
86
87 while ((nbytes = walk->nbytes)) {
88 u8 *wsrc = walk->src.virt.addr;
89 u8 *wdst = walk->dst.virt.addr;
90
91 fpu_enabled = serpent_fpu_begin(fpu_enabled, nbytes);
92
93 /* Process multi-block batch */
94 if (nbytes >= bsize * SERPENT_PARALLEL_BLOCKS) {
95 do {
96 if (enc)
97 serpent_enc_blk_xway(ctx, wdst, wsrc);
98 else
99 serpent_dec_blk_xway(ctx, wdst, wsrc);
100
101 wsrc += bsize * SERPENT_PARALLEL_BLOCKS;
102 wdst += bsize * SERPENT_PARALLEL_BLOCKS;
103 nbytes -= bsize * SERPENT_PARALLEL_BLOCKS;
104 } while (nbytes >= bsize * SERPENT_PARALLEL_BLOCKS);
105
106 if (nbytes < bsize)
107 goto done;
108 }
109
110 /* Handle leftovers */
111 do {
112 if (enc)
113 __serpent_encrypt(ctx, wdst, wsrc);
114 else
115 __serpent_decrypt(ctx, wdst, wsrc);
116
117 wsrc += bsize;
118 wdst += bsize;
119 nbytes -= bsize;
120 } while (nbytes >= bsize);
121
122done:
123 err = blkcipher_walk_done(desc, walk, nbytes);
124 }
125
126 serpent_fpu_end(fpu_enabled);
127 return err;
128}
129
130static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
131 struct scatterlist *src, unsigned int nbytes)
132{
133 struct blkcipher_walk walk;
134
135 blkcipher_walk_init(&walk, dst, src, nbytes);
136 return ecb_crypt(desc, &walk, true);
137}
138
139static int ecb_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
140 struct scatterlist *src, unsigned int nbytes)
141{
142 struct blkcipher_walk walk;
143
144 blkcipher_walk_init(&walk, dst, src, nbytes);
145 return ecb_crypt(desc, &walk, false);
146}
147
148static struct crypto_alg blk_ecb_alg = {
149 .cra_name = "__ecb-serpent-sse2",
150 .cra_driver_name = "__driver-ecb-serpent-sse2",
151 .cra_priority = 0,
152 .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
153 .cra_blocksize = SERPENT_BLOCK_SIZE,
154 .cra_ctxsize = sizeof(struct serpent_ctx),
155 .cra_alignmask = 0,
156 .cra_type = &crypto_blkcipher_type,
157 .cra_module = THIS_MODULE,
158 .cra_list = LIST_HEAD_INIT(blk_ecb_alg.cra_list),
159 .cra_u = {
160 .blkcipher = {
161 .min_keysize = SERPENT_MIN_KEY_SIZE,
162 .max_keysize = SERPENT_MAX_KEY_SIZE,
163 .setkey = serpent_setkey,
164 .encrypt = ecb_encrypt,
165 .decrypt = ecb_decrypt,
166 },
167 },
168};
169
170static unsigned int __cbc_encrypt(struct blkcipher_desc *desc,
171 struct blkcipher_walk *walk)
172{
173 struct serpent_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
174 const unsigned int bsize = SERPENT_BLOCK_SIZE;
175 unsigned int nbytes = walk->nbytes;
176 u128 *src = (u128 *)walk->src.virt.addr;
177 u128 *dst = (u128 *)walk->dst.virt.addr;
178 u128 *iv = (u128 *)walk->iv;
179
180 do {
181 u128_xor(dst, src, iv);
182 __serpent_encrypt(ctx, (u8 *)dst, (u8 *)dst);
183 iv = dst;
184
185 src += 1;
186 dst += 1;
187 nbytes -= bsize;
188 } while (nbytes >= bsize);
189
190 u128_xor((u128 *)walk->iv, (u128 *)walk->iv, iv);
191 return nbytes;
192}
193
194static int cbc_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
195 struct scatterlist *src, unsigned int nbytes)
196{
197 struct blkcipher_walk walk;
198 int err;
199
200 blkcipher_walk_init(&walk, dst, src, nbytes);
201 err = blkcipher_walk_virt(desc, &walk);
202
203 while ((nbytes = walk.nbytes)) {
204 nbytes = __cbc_encrypt(desc, &walk);
205 err = blkcipher_walk_done(desc, &walk, nbytes);
206 }
207
208 return err;
209}
210
211static unsigned int __cbc_decrypt(struct blkcipher_desc *desc,
212 struct blkcipher_walk *walk)
213{
214 struct serpent_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
215 const unsigned int bsize = SERPENT_BLOCK_SIZE;
216 unsigned int nbytes = walk->nbytes;
217 u128 *src = (u128 *)walk->src.virt.addr;
218 u128 *dst = (u128 *)walk->dst.virt.addr;
219 u128 ivs[SERPENT_PARALLEL_BLOCKS - 1];
220 u128 last_iv;
221 int i;
222
223 /* Start of the last block. */
224 src += nbytes / bsize - 1;
225 dst += nbytes / bsize - 1;
226
227 last_iv = *src;
228
229 /* Process multi-block batch */
230 if (nbytes >= bsize * SERPENT_PARALLEL_BLOCKS) {
231 do {
232 nbytes -= bsize * (SERPENT_PARALLEL_BLOCKS - 1);
233 src -= SERPENT_PARALLEL_BLOCKS - 1;
234 dst -= SERPENT_PARALLEL_BLOCKS - 1;
235
236 for (i = 0; i < SERPENT_PARALLEL_BLOCKS - 1; i++)
237 ivs[i] = src[i];
238
239 serpent_dec_blk_xway(ctx, (u8 *)dst, (u8 *)src);
240
241 for (i = 0; i < SERPENT_PARALLEL_BLOCKS - 1; i++)
242 u128_xor(dst + (i + 1), dst + (i + 1), ivs + i);
243
244 nbytes -= bsize;
245 if (nbytes < bsize)
246 goto done;
247
248 u128_xor(dst, dst, src - 1);
249 src -= 1;
250 dst -= 1;
251 } while (nbytes >= bsize * SERPENT_PARALLEL_BLOCKS);
252
253 if (nbytes < bsize)
254 goto done;
255 }
256
257 /* Handle leftovers */
258 for (;;) {
259 __serpent_decrypt(ctx, (u8 *)dst, (u8 *)src);
260
261 nbytes -= bsize;
262 if (nbytes < bsize)
263 break;
264
265 u128_xor(dst, dst, src - 1);
266 src -= 1;
267 dst -= 1;
268 }
269
270done:
271 u128_xor(dst, dst, (u128 *)walk->iv);
272 *(u128 *)walk->iv = last_iv;
273
274 return nbytes;
275}
276
277static int cbc_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
278 struct scatterlist *src, unsigned int nbytes)
279{
280 bool fpu_enabled = false;
281 struct blkcipher_walk walk;
282 int err;
283
284 blkcipher_walk_init(&walk, dst, src, nbytes);
285 err = blkcipher_walk_virt(desc, &walk);
286 desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
287
288 while ((nbytes = walk.nbytes)) {
289 fpu_enabled = serpent_fpu_begin(fpu_enabled, nbytes);
290 nbytes = __cbc_decrypt(desc, &walk);
291 err = blkcipher_walk_done(desc, &walk, nbytes);
292 }
293
294 serpent_fpu_end(fpu_enabled);
295 return err;
296}
297
298static struct crypto_alg blk_cbc_alg = {
299 .cra_name = "__cbc-serpent-sse2",
300 .cra_driver_name = "__driver-cbc-serpent-sse2",
301 .cra_priority = 0,
302 .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
303 .cra_blocksize = SERPENT_BLOCK_SIZE,
304 .cra_ctxsize = sizeof(struct serpent_ctx),
305 .cra_alignmask = 0,
306 .cra_type = &crypto_blkcipher_type,
307 .cra_module = THIS_MODULE,
308 .cra_list = LIST_HEAD_INIT(blk_cbc_alg.cra_list),
309 .cra_u = {
310 .blkcipher = {
311 .min_keysize = SERPENT_MIN_KEY_SIZE,
312 .max_keysize = SERPENT_MAX_KEY_SIZE,
313 .setkey = serpent_setkey,
314 .encrypt = cbc_encrypt,
315 .decrypt = cbc_decrypt,
316 },
317 },
318};
319
320static inline void u128_to_be128(be128 *dst, const u128 *src)
321{
322 dst->a = cpu_to_be64(src->a);
323 dst->b = cpu_to_be64(src->b);
324}
325
326static inline void be128_to_u128(u128 *dst, const be128 *src)
327{
328 dst->a = be64_to_cpu(src->a);
329 dst->b = be64_to_cpu(src->b);
330}
331
332static inline void u128_inc(u128 *i)
333{
334 i->b++;
335 if (!i->b)
336 i->a++;
337}
338
339static void ctr_crypt_final(struct blkcipher_desc *desc,
340 struct blkcipher_walk *walk)
341{
342 struct serpent_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
343 u8 *ctrblk = walk->iv;
344 u8 keystream[SERPENT_BLOCK_SIZE];
345 u8 *src = walk->src.virt.addr;
346 u8 *dst = walk->dst.virt.addr;
347 unsigned int nbytes = walk->nbytes;
348
349 __serpent_encrypt(ctx, keystream, ctrblk);
350 crypto_xor(keystream, src, nbytes);
351 memcpy(dst, keystream, nbytes);
352
353 crypto_inc(ctrblk, SERPENT_BLOCK_SIZE);
354}
355
356static unsigned int __ctr_crypt(struct blkcipher_desc *desc,
357 struct blkcipher_walk *walk)
358{
359 struct serpent_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
360 const unsigned int bsize = SERPENT_BLOCK_SIZE;
361 unsigned int nbytes = walk->nbytes;
362 u128 *src = (u128 *)walk->src.virt.addr;
363 u128 *dst = (u128 *)walk->dst.virt.addr;
364 u128 ctrblk;
365 be128 ctrblocks[SERPENT_PARALLEL_BLOCKS];
366 int i;
367
368 be128_to_u128(&ctrblk, (be128 *)walk->iv);
369
370 /* Process multi-block batch */
371 if (nbytes >= bsize * SERPENT_PARALLEL_BLOCKS) {
372 do {
373 /* create ctrblks for parallel encrypt */
374 for (i = 0; i < SERPENT_PARALLEL_BLOCKS; i++) {
375 if (dst != src)
376 dst[i] = src[i];
377
378 u128_to_be128(&ctrblocks[i], &ctrblk);
379 u128_inc(&ctrblk);
380 }
381
382 serpent_enc_blk_xway_xor(ctx, (u8 *)dst,
383 (u8 *)ctrblocks);
384
385 src += SERPENT_PARALLEL_BLOCKS;
386 dst += SERPENT_PARALLEL_BLOCKS;
387 nbytes -= bsize * SERPENT_PARALLEL_BLOCKS;
388 } while (nbytes >= bsize * SERPENT_PARALLEL_BLOCKS);
389
390 if (nbytes < bsize)
391 goto done;
392 }
393
394 /* Handle leftovers */
395 do {
396 if (dst != src)
397 *dst = *src;
398
399 u128_to_be128(&ctrblocks[0], &ctrblk);
400 u128_inc(&ctrblk);
401
402 __serpent_encrypt(ctx, (u8 *)ctrblocks, (u8 *)ctrblocks);
403 u128_xor(dst, dst, (u128 *)ctrblocks);
404
405 src += 1;
406 dst += 1;
407 nbytes -= bsize;
408 } while (nbytes >= bsize);
409
410done:
411 u128_to_be128((be128 *)walk->iv, &ctrblk);
412 return nbytes;
413}
414
415static int ctr_crypt(struct blkcipher_desc *desc, struct scatterlist *dst,
416 struct scatterlist *src, unsigned int nbytes)
417{
418 bool fpu_enabled = false;
419 struct blkcipher_walk walk;
420 int err;
421
422 blkcipher_walk_init(&walk, dst, src, nbytes);
423 err = blkcipher_walk_virt_block(desc, &walk, SERPENT_BLOCK_SIZE);
424 desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
425
426 while ((nbytes = walk.nbytes) >= SERPENT_BLOCK_SIZE) {
427 fpu_enabled = serpent_fpu_begin(fpu_enabled, nbytes);
428 nbytes = __ctr_crypt(desc, &walk);
429 err = blkcipher_walk_done(desc, &walk, nbytes);
430 }
431
432 serpent_fpu_end(fpu_enabled);
433
434 if (walk.nbytes) {
435 ctr_crypt_final(desc, &walk);
436 err = blkcipher_walk_done(desc, &walk, 0);
437 }
438
439 return err;
440}
441
442static struct crypto_alg blk_ctr_alg = {
443 .cra_name = "__ctr-serpent-sse2",
444 .cra_driver_name = "__driver-ctr-serpent-sse2",
445 .cra_priority = 0,
446 .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
447 .cra_blocksize = 1,
448 .cra_ctxsize = sizeof(struct serpent_ctx),
449 .cra_alignmask = 0,
450 .cra_type = &crypto_blkcipher_type,
451 .cra_module = THIS_MODULE,
452 .cra_list = LIST_HEAD_INIT(blk_ctr_alg.cra_list),
453 .cra_u = {
454 .blkcipher = {
455 .min_keysize = SERPENT_MIN_KEY_SIZE,
456 .max_keysize = SERPENT_MAX_KEY_SIZE,
457 .ivsize = SERPENT_BLOCK_SIZE,
458 .setkey = serpent_setkey,
459 .encrypt = ctr_crypt,
460 .decrypt = ctr_crypt,
461 },
462 },
463};
464
465struct crypt_priv {
466 struct serpent_ctx *ctx;
467 bool fpu_enabled;
468};
469
470static void encrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
471{
472 const unsigned int bsize = SERPENT_BLOCK_SIZE;
473 struct crypt_priv *ctx = priv;
474 int i;
475
476 ctx->fpu_enabled = serpent_fpu_begin(ctx->fpu_enabled, nbytes);
477
478 if (nbytes == bsize * SERPENT_PARALLEL_BLOCKS) {
479 serpent_enc_blk_xway(ctx->ctx, srcdst, srcdst);
480 return;
481 }
482
483 for (i = 0; i < nbytes / bsize; i++, srcdst += bsize)
484 __serpent_encrypt(ctx->ctx, srcdst, srcdst);
485}
486
487static void decrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
488{
489 const unsigned int bsize = SERPENT_BLOCK_SIZE;
490 struct crypt_priv *ctx = priv;
491 int i;
492
493 ctx->fpu_enabled = serpent_fpu_begin(ctx->fpu_enabled, nbytes);
494
495 if (nbytes == bsize * SERPENT_PARALLEL_BLOCKS) {
496 serpent_dec_blk_xway(ctx->ctx, srcdst, srcdst);
497 return;
498 }
499
500 for (i = 0; i < nbytes / bsize; i++, srcdst += bsize)
501 __serpent_decrypt(ctx->ctx, srcdst, srcdst);
502}
503
504struct serpent_lrw_ctx {
505 struct lrw_table_ctx lrw_table;
506 struct serpent_ctx serpent_ctx;
507};
508
509static int lrw_serpent_setkey(struct crypto_tfm *tfm, const u8 *key,
510 unsigned int keylen)
511{
512 struct serpent_lrw_ctx *ctx = crypto_tfm_ctx(tfm);
513 int err;
514
515 err = __serpent_setkey(&ctx->serpent_ctx, key, keylen -
516 SERPENT_BLOCK_SIZE);
517 if (err)
518 return err;
519
520 return lrw_init_table(&ctx->lrw_table, key + keylen -
521 SERPENT_BLOCK_SIZE);
522}
523
524static int lrw_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
525 struct scatterlist *src, unsigned int nbytes)
526{
527 struct serpent_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
528 be128 buf[SERPENT_PARALLEL_BLOCKS];
529 struct crypt_priv crypt_ctx = {
530 .ctx = &ctx->serpent_ctx,
531 .fpu_enabled = false,
532 };
533 struct lrw_crypt_req req = {
534 .tbuf = buf,
535 .tbuflen = sizeof(buf),
536
537 .table_ctx = &ctx->lrw_table,
538 .crypt_ctx = &crypt_ctx,
539 .crypt_fn = encrypt_callback,
540 };
541 int ret;
542
543 desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
544 ret = lrw_crypt(desc, dst, src, nbytes, &req);
545 serpent_fpu_end(crypt_ctx.fpu_enabled);
546
547 return ret;
548}
549
550static int lrw_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
551 struct scatterlist *src, unsigned int nbytes)
552{
553 struct serpent_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
554 be128 buf[SERPENT_PARALLEL_BLOCKS];
555 struct crypt_priv crypt_ctx = {
556 .ctx = &ctx->serpent_ctx,
557 .fpu_enabled = false,
558 };
559 struct lrw_crypt_req req = {
560 .tbuf = buf,
561 .tbuflen = sizeof(buf),
562
563 .table_ctx = &ctx->lrw_table,
564 .crypt_ctx = &crypt_ctx,
565 .crypt_fn = decrypt_callback,
566 };
567 int ret;
568
569 desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
570 ret = lrw_crypt(desc, dst, src, nbytes, &req);
571 serpent_fpu_end(crypt_ctx.fpu_enabled);
572
573 return ret;
574}
575
576static void lrw_exit_tfm(struct crypto_tfm *tfm)
577{
578 struct serpent_lrw_ctx *ctx = crypto_tfm_ctx(tfm);
579
580 lrw_free_table(&ctx->lrw_table);
581}
582
583static struct crypto_alg blk_lrw_alg = {
584 .cra_name = "__lrw-serpent-sse2",
585 .cra_driver_name = "__driver-lrw-serpent-sse2",
586 .cra_priority = 0,
587 .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
588 .cra_blocksize = SERPENT_BLOCK_SIZE,
589 .cra_ctxsize = sizeof(struct serpent_lrw_ctx),
590 .cra_alignmask = 0,
591 .cra_type = &crypto_blkcipher_type,
592 .cra_module = THIS_MODULE,
593 .cra_list = LIST_HEAD_INIT(blk_lrw_alg.cra_list),
594 .cra_exit = lrw_exit_tfm,
595 .cra_u = {
596 .blkcipher = {
597 .min_keysize = SERPENT_MIN_KEY_SIZE +
598 SERPENT_BLOCK_SIZE,
599 .max_keysize = SERPENT_MAX_KEY_SIZE +
600 SERPENT_BLOCK_SIZE,
601 .ivsize = SERPENT_BLOCK_SIZE,
602 .setkey = lrw_serpent_setkey,
603 .encrypt = lrw_encrypt,
604 .decrypt = lrw_decrypt,
605 },
606 },
607};
608
609struct serpent_xts_ctx {
610 struct serpent_ctx tweak_ctx;
611 struct serpent_ctx crypt_ctx;
612};
613
614static int xts_serpent_setkey(struct crypto_tfm *tfm, const u8 *key,
615 unsigned int keylen)
616{
617 struct serpent_xts_ctx *ctx = crypto_tfm_ctx(tfm);
618 u32 *flags = &tfm->crt_flags;
619 int err;
620
621 /* key consists of keys of equal size concatenated, therefore
622 * the length must be even
623 */
624 if (keylen % 2) {
625 *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
626 return -EINVAL;
627 }
628
629 /* first half of xts-key is for crypt */
630 err = __serpent_setkey(&ctx->crypt_ctx, key, keylen / 2);
631 if (err)
632 return err;
633
634 /* second half of xts-key is for tweak */
635 return __serpent_setkey(&ctx->tweak_ctx, key + keylen / 2, keylen / 2);
636}
637
638static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
639 struct scatterlist *src, unsigned int nbytes)
640{
641 struct serpent_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
642 be128 buf[SERPENT_PARALLEL_BLOCKS];
643 struct crypt_priv crypt_ctx = {
644 .ctx = &ctx->crypt_ctx,
645 .fpu_enabled = false,
646 };
647 struct xts_crypt_req req = {
648 .tbuf = buf,
649 .tbuflen = sizeof(buf),
650
651 .tweak_ctx = &ctx->tweak_ctx,
652 .tweak_fn = XTS_TWEAK_CAST(__serpent_encrypt),
653 .crypt_ctx = &crypt_ctx,
654 .crypt_fn = encrypt_callback,
655 };
656 int ret;
657
658 desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
659 ret = xts_crypt(desc, dst, src, nbytes, &req);
660 serpent_fpu_end(crypt_ctx.fpu_enabled);
661
662 return ret;
663}
664
665static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
666 struct scatterlist *src, unsigned int nbytes)
667{
668 struct serpent_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
669 be128 buf[SERPENT_PARALLEL_BLOCKS];
670 struct crypt_priv crypt_ctx = {
671 .ctx = &ctx->crypt_ctx,
672 .fpu_enabled = false,
673 };
674 struct xts_crypt_req req = {
675 .tbuf = buf,
676 .tbuflen = sizeof(buf),
677
678 .tweak_ctx = &ctx->tweak_ctx,
679 .tweak_fn = XTS_TWEAK_CAST(__serpent_encrypt),
680 .crypt_ctx = &crypt_ctx,
681 .crypt_fn = decrypt_callback,
682 };
683 int ret;
684
685 desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
686 ret = xts_crypt(desc, dst, src, nbytes, &req);
687 serpent_fpu_end(crypt_ctx.fpu_enabled);
688
689 return ret;
690}
691
692static struct crypto_alg blk_xts_alg = {
693 .cra_name = "__xts-serpent-sse2",
694 .cra_driver_name = "__driver-xts-serpent-sse2",
695 .cra_priority = 0,
696 .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
697 .cra_blocksize = SERPENT_BLOCK_SIZE,
698 .cra_ctxsize = sizeof(struct serpent_xts_ctx),
699 .cra_alignmask = 0,
700 .cra_type = &crypto_blkcipher_type,
701 .cra_module = THIS_MODULE,
702 .cra_list = LIST_HEAD_INIT(blk_xts_alg.cra_list),
703 .cra_u = {
704 .blkcipher = {
705 .min_keysize = SERPENT_MIN_KEY_SIZE * 2,
706 .max_keysize = SERPENT_MAX_KEY_SIZE * 2,
707 .ivsize = SERPENT_BLOCK_SIZE,
708 .setkey = xts_serpent_setkey,
709 .encrypt = xts_encrypt,
710 .decrypt = xts_decrypt,
711 },
712 },
713};
714
715static int ablk_set_key(struct crypto_ablkcipher *tfm, const u8 *key,
716 unsigned int key_len)
717{
718 struct async_serpent_ctx *ctx = crypto_ablkcipher_ctx(tfm);
719 struct crypto_ablkcipher *child = &ctx->cryptd_tfm->base;
720 int err;
721
722 crypto_ablkcipher_clear_flags(child, CRYPTO_TFM_REQ_MASK);
723 crypto_ablkcipher_set_flags(child, crypto_ablkcipher_get_flags(tfm)
724 & CRYPTO_TFM_REQ_MASK);
725 err = crypto_ablkcipher_setkey(child, key, key_len);
726 crypto_ablkcipher_set_flags(tfm, crypto_ablkcipher_get_flags(child)
727 & CRYPTO_TFM_RES_MASK);
728 return err;
729}
730
731static int __ablk_encrypt(struct ablkcipher_request *req)
732{
733 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
734 struct async_serpent_ctx *ctx = crypto_ablkcipher_ctx(tfm);
735 struct blkcipher_desc desc;
736
737 desc.tfm = cryptd_ablkcipher_child(ctx->cryptd_tfm);
738 desc.info = req->info;
739 desc.flags = 0;
740
741 return crypto_blkcipher_crt(desc.tfm)->encrypt(
742 &desc, req->dst, req->src, req->nbytes);
743}
744
745static int ablk_encrypt(struct ablkcipher_request *req)
746{
747 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
748 struct async_serpent_ctx *ctx = crypto_ablkcipher_ctx(tfm);
749
750 if (!irq_fpu_usable()) {
751 struct ablkcipher_request *cryptd_req =
752 ablkcipher_request_ctx(req);
753
754 memcpy(cryptd_req, req, sizeof(*req));
755 ablkcipher_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base);
756
757 return crypto_ablkcipher_encrypt(cryptd_req);
758 } else {
759 return __ablk_encrypt(req);
760 }
761}
762
763static int ablk_decrypt(struct ablkcipher_request *req)
764{
765 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
766 struct async_serpent_ctx *ctx = crypto_ablkcipher_ctx(tfm);
767
768 if (!irq_fpu_usable()) {
769 struct ablkcipher_request *cryptd_req =
770 ablkcipher_request_ctx(req);
771
772 memcpy(cryptd_req, req, sizeof(*req));
773 ablkcipher_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base);
774
775 return crypto_ablkcipher_decrypt(cryptd_req);
776 } else {
777 struct blkcipher_desc desc;
778
779 desc.tfm = cryptd_ablkcipher_child(ctx->cryptd_tfm);
780 desc.info = req->info;
781 desc.flags = 0;
782
783 return crypto_blkcipher_crt(desc.tfm)->decrypt(
784 &desc, req->dst, req->src, req->nbytes);
785 }
786}
787
788static void ablk_exit(struct crypto_tfm *tfm)
789{
790 struct async_serpent_ctx *ctx = crypto_tfm_ctx(tfm);
791
792 cryptd_free_ablkcipher(ctx->cryptd_tfm);
793}
794
795static void ablk_init_common(struct crypto_tfm *tfm,
796 struct cryptd_ablkcipher *cryptd_tfm)
797{
798 struct async_serpent_ctx *ctx = crypto_tfm_ctx(tfm);
799
800 ctx->cryptd_tfm = cryptd_tfm;
801 tfm->crt_ablkcipher.reqsize = sizeof(struct ablkcipher_request) +
802 crypto_ablkcipher_reqsize(&cryptd_tfm->base);
803}
804
805static int ablk_ecb_init(struct crypto_tfm *tfm)
806{
807 struct cryptd_ablkcipher *cryptd_tfm;
808
809 cryptd_tfm = cryptd_alloc_ablkcipher("__driver-ecb-serpent-sse2", 0, 0);
810 if (IS_ERR(cryptd_tfm))
811 return PTR_ERR(cryptd_tfm);
812 ablk_init_common(tfm, cryptd_tfm);
813 return 0;
814}
815
816static struct crypto_alg ablk_ecb_alg = {
817 .cra_name = "ecb(serpent)",
818 .cra_driver_name = "ecb-serpent-sse2",
819 .cra_priority = 400,
820 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
821 .cra_blocksize = SERPENT_BLOCK_SIZE,
822 .cra_ctxsize = sizeof(struct async_serpent_ctx),
823 .cra_alignmask = 0,
824 .cra_type = &crypto_ablkcipher_type,
825 .cra_module = THIS_MODULE,
826 .cra_list = LIST_HEAD_INIT(ablk_ecb_alg.cra_list),
827 .cra_init = ablk_ecb_init,
828 .cra_exit = ablk_exit,
829 .cra_u = {
830 .ablkcipher = {
831 .min_keysize = SERPENT_MIN_KEY_SIZE,
832 .max_keysize = SERPENT_MAX_KEY_SIZE,
833 .setkey = ablk_set_key,
834 .encrypt = ablk_encrypt,
835 .decrypt = ablk_decrypt,
836 },
837 },
838};
839
840static int ablk_cbc_init(struct crypto_tfm *tfm)
841{
842 struct cryptd_ablkcipher *cryptd_tfm;
843
844 cryptd_tfm = cryptd_alloc_ablkcipher("__driver-cbc-serpent-sse2", 0, 0);
845 if (IS_ERR(cryptd_tfm))
846 return PTR_ERR(cryptd_tfm);
847 ablk_init_common(tfm, cryptd_tfm);
848 return 0;
849}
850
851static struct crypto_alg ablk_cbc_alg = {
852 .cra_name = "cbc(serpent)",
853 .cra_driver_name = "cbc-serpent-sse2",
854 .cra_priority = 400,
855 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
856 .cra_blocksize = SERPENT_BLOCK_SIZE,
857 .cra_ctxsize = sizeof(struct async_serpent_ctx),
858 .cra_alignmask = 0,
859 .cra_type = &crypto_ablkcipher_type,
860 .cra_module = THIS_MODULE,
861 .cra_list = LIST_HEAD_INIT(ablk_cbc_alg.cra_list),
862 .cra_init = ablk_cbc_init,
863 .cra_exit = ablk_exit,
864 .cra_u = {
865 .ablkcipher = {
866 .min_keysize = SERPENT_MIN_KEY_SIZE,
867 .max_keysize = SERPENT_MAX_KEY_SIZE,
868 .ivsize = SERPENT_BLOCK_SIZE,
869 .setkey = ablk_set_key,
870 .encrypt = __ablk_encrypt,
871 .decrypt = ablk_decrypt,
872 },
873 },
874};
875
876static int ablk_ctr_init(struct crypto_tfm *tfm)
877{
878 struct cryptd_ablkcipher *cryptd_tfm;
879
880 cryptd_tfm = cryptd_alloc_ablkcipher("__driver-ctr-serpent-sse2", 0, 0);
881 if (IS_ERR(cryptd_tfm))
882 return PTR_ERR(cryptd_tfm);
883 ablk_init_common(tfm, cryptd_tfm);
884 return 0;
885}
886
887static struct crypto_alg ablk_ctr_alg = {
888 .cra_name = "ctr(serpent)",
889 .cra_driver_name = "ctr-serpent-sse2",
890 .cra_priority = 400,
891 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
892 .cra_blocksize = 1,
893 .cra_ctxsize = sizeof(struct async_serpent_ctx),
894 .cra_alignmask = 0,
895 .cra_type = &crypto_ablkcipher_type,
896 .cra_module = THIS_MODULE,
897 .cra_list = LIST_HEAD_INIT(ablk_ctr_alg.cra_list),
898 .cra_init = ablk_ctr_init,
899 .cra_exit = ablk_exit,
900 .cra_u = {
901 .ablkcipher = {
902 .min_keysize = SERPENT_MIN_KEY_SIZE,
903 .max_keysize = SERPENT_MAX_KEY_SIZE,
904 .ivsize = SERPENT_BLOCK_SIZE,
905 .setkey = ablk_set_key,
906 .encrypt = ablk_encrypt,
907 .decrypt = ablk_encrypt,
908 .geniv = "chainiv",
909 },
910 },
911};
912
913static int ablk_lrw_init(struct crypto_tfm *tfm)
914{
915 struct cryptd_ablkcipher *cryptd_tfm;
916
917 cryptd_tfm = cryptd_alloc_ablkcipher("__driver-lrw-serpent-sse2", 0, 0);
918 if (IS_ERR(cryptd_tfm))
919 return PTR_ERR(cryptd_tfm);
920 ablk_init_common(tfm, cryptd_tfm);
921 return 0;
922}
923
924static struct crypto_alg ablk_lrw_alg = {
925 .cra_name = "lrw(serpent)",
926 .cra_driver_name = "lrw-serpent-sse2",
927 .cra_priority = 400,
928 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
929 .cra_blocksize = SERPENT_BLOCK_SIZE,
930 .cra_ctxsize = sizeof(struct async_serpent_ctx),
931 .cra_alignmask = 0,
932 .cra_type = &crypto_ablkcipher_type,
933 .cra_module = THIS_MODULE,
934 .cra_list = LIST_HEAD_INIT(ablk_lrw_alg.cra_list),
935 .cra_init = ablk_lrw_init,
936 .cra_exit = ablk_exit,
937 .cra_u = {
938 .ablkcipher = {
939 .min_keysize = SERPENT_MIN_KEY_SIZE +
940 SERPENT_BLOCK_SIZE,
941 .max_keysize = SERPENT_MAX_KEY_SIZE +
942 SERPENT_BLOCK_SIZE,
943 .ivsize = SERPENT_BLOCK_SIZE,
944 .setkey = ablk_set_key,
945 .encrypt = ablk_encrypt,
946 .decrypt = ablk_decrypt,
947 },
948 },
949};
950
951static int ablk_xts_init(struct crypto_tfm *tfm)
952{
953 struct cryptd_ablkcipher *cryptd_tfm;
954
955 cryptd_tfm = cryptd_alloc_ablkcipher("__driver-xts-serpent-sse2", 0, 0);
956 if (IS_ERR(cryptd_tfm))
957 return PTR_ERR(cryptd_tfm);
958 ablk_init_common(tfm, cryptd_tfm);
959 return 0;
960}
961
962static struct crypto_alg ablk_xts_alg = {
963 .cra_name = "xts(serpent)",
964 .cra_driver_name = "xts-serpent-sse2",
965 .cra_priority = 400,
966 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
967 .cra_blocksize = SERPENT_BLOCK_SIZE,
968 .cra_ctxsize = sizeof(struct async_serpent_ctx),
969 .cra_alignmask = 0,
970 .cra_type = &crypto_ablkcipher_type,
971 .cra_module = THIS_MODULE,
972 .cra_list = LIST_HEAD_INIT(ablk_xts_alg.cra_list),
973 .cra_init = ablk_xts_init,
974 .cra_exit = ablk_exit,
975 .cra_u = {
976 .ablkcipher = {
977 .min_keysize = SERPENT_MIN_KEY_SIZE * 2,
978 .max_keysize = SERPENT_MAX_KEY_SIZE * 2,
979 .ivsize = SERPENT_BLOCK_SIZE,
980 .setkey = ablk_set_key,
981 .encrypt = ablk_encrypt,
982 .decrypt = ablk_decrypt,
983 },
984 },
985};
986
987static int __init serpent_sse2_init(void)
988{
989 int err;
990
991 if (!cpu_has_xmm2) {
992 printk(KERN_INFO "SSE2 instructions are not detected.\n");
993 return -ENODEV;
994 }
995
996 err = crypto_register_alg(&blk_ecb_alg);
997 if (err)
998 goto blk_ecb_err;
999 err = crypto_register_alg(&blk_cbc_alg);
1000 if (err)
1001 goto blk_cbc_err;
1002 err = crypto_register_alg(&blk_ctr_alg);
1003 if (err)
1004 goto blk_ctr_err;
1005 err = crypto_register_alg(&ablk_ecb_alg);
1006 if (err)
1007 goto ablk_ecb_err;
1008 err = crypto_register_alg(&ablk_cbc_alg);
1009 if (err)
1010 goto ablk_cbc_err;
1011 err = crypto_register_alg(&ablk_ctr_alg);
1012 if (err)
1013 goto ablk_ctr_err;
1014 err = crypto_register_alg(&blk_lrw_alg);
1015 if (err)
1016 goto blk_lrw_err;
1017 err = crypto_register_alg(&ablk_lrw_alg);
1018 if (err)
1019 goto ablk_lrw_err;
1020 err = crypto_register_alg(&blk_xts_alg);
1021 if (err)
1022 goto blk_xts_err;
1023 err = crypto_register_alg(&ablk_xts_alg);
1024 if (err)
1025 goto ablk_xts_err;
1026 return err;
1027
1028 crypto_unregister_alg(&ablk_xts_alg);
1029ablk_xts_err:
1030 crypto_unregister_alg(&blk_xts_alg);
1031blk_xts_err:
1032 crypto_unregister_alg(&ablk_lrw_alg);
1033ablk_lrw_err:
1034 crypto_unregister_alg(&blk_lrw_alg);
1035blk_lrw_err:
1036 crypto_unregister_alg(&ablk_ctr_alg);
1037ablk_ctr_err:
1038 crypto_unregister_alg(&ablk_cbc_alg);
1039ablk_cbc_err:
1040 crypto_unregister_alg(&ablk_ecb_alg);
1041ablk_ecb_err:
1042 crypto_unregister_alg(&blk_ctr_alg);
1043blk_ctr_err:
1044 crypto_unregister_alg(&blk_cbc_alg);
1045blk_cbc_err:
1046 crypto_unregister_alg(&blk_ecb_alg);
1047blk_ecb_err:
1048 return err;
1049}
1050
1051static void __exit serpent_sse2_exit(void)
1052{
1053 crypto_unregister_alg(&ablk_xts_alg);
1054 crypto_unregister_alg(&blk_xts_alg);
1055 crypto_unregister_alg(&ablk_lrw_alg);
1056 crypto_unregister_alg(&blk_lrw_alg);
1057 crypto_unregister_alg(&ablk_ctr_alg);
1058 crypto_unregister_alg(&ablk_cbc_alg);
1059 crypto_unregister_alg(&ablk_ecb_alg);
1060 crypto_unregister_alg(&blk_ctr_alg);
1061 crypto_unregister_alg(&blk_cbc_alg);
1062 crypto_unregister_alg(&blk_ecb_alg);
1063}
1064
1065module_init(serpent_sse2_init);
1066module_exit(serpent_sse2_exit);
1067
1068MODULE_DESCRIPTION("Serpent Cipher Algorithm, SSE2 optimized");
1069MODULE_LICENSE("GPL");
1070MODULE_ALIAS("serpent");
diff --git a/arch/x86/crypto/twofish_glue_3way.c b/arch/x86/crypto/twofish_glue_3way.c
index 5ede9c444c3e..7fee8c152f93 100644
--- a/arch/x86/crypto/twofish_glue_3way.c
+++ b/arch/x86/crypto/twofish_glue_3way.c
@@ -32,6 +32,8 @@
32#include <crypto/algapi.h> 32#include <crypto/algapi.h>
33#include <crypto/twofish.h> 33#include <crypto/twofish.h>
34#include <crypto/b128ops.h> 34#include <crypto/b128ops.h>
35#include <crypto/lrw.h>
36#include <crypto/xts.h>
35 37
36/* regular block cipher functions from twofish_x86_64 module */ 38/* regular block cipher functions from twofish_x86_64 module */
37asmlinkage void twofish_enc_blk(struct twofish_ctx *ctx, u8 *dst, 39asmlinkage void twofish_enc_blk(struct twofish_ctx *ctx, u8 *dst,
@@ -432,6 +434,209 @@ static struct crypto_alg blk_ctr_alg = {
432 }, 434 },
433}; 435};
434 436
437static void encrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
438{
439 const unsigned int bsize = TF_BLOCK_SIZE;
440 struct twofish_ctx *ctx = priv;
441 int i;
442
443 if (nbytes == 3 * bsize) {
444 twofish_enc_blk_3way(ctx, srcdst, srcdst);
445 return;
446 }
447
448 for (i = 0; i < nbytes / bsize; i++, srcdst += bsize)
449 twofish_enc_blk(ctx, srcdst, srcdst);
450}
451
452static void decrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
453{
454 const unsigned int bsize = TF_BLOCK_SIZE;
455 struct twofish_ctx *ctx = priv;
456 int i;
457
458 if (nbytes == 3 * bsize) {
459 twofish_dec_blk_3way(ctx, srcdst, srcdst);
460 return;
461 }
462
463 for (i = 0; i < nbytes / bsize; i++, srcdst += bsize)
464 twofish_dec_blk(ctx, srcdst, srcdst);
465}
466
467struct twofish_lrw_ctx {
468 struct lrw_table_ctx lrw_table;
469 struct twofish_ctx twofish_ctx;
470};
471
472static int lrw_twofish_setkey(struct crypto_tfm *tfm, const u8 *key,
473 unsigned int keylen)
474{
475 struct twofish_lrw_ctx *ctx = crypto_tfm_ctx(tfm);
476 int err;
477
478 err = __twofish_setkey(&ctx->twofish_ctx, key, keylen - TF_BLOCK_SIZE,
479 &tfm->crt_flags);
480 if (err)
481 return err;
482
483 return lrw_init_table(&ctx->lrw_table, key + keylen - TF_BLOCK_SIZE);
484}
485
486static int lrw_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
487 struct scatterlist *src, unsigned int nbytes)
488{
489 struct twofish_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
490 be128 buf[3];
491 struct lrw_crypt_req req = {
492 .tbuf = buf,
493 .tbuflen = sizeof(buf),
494
495 .table_ctx = &ctx->lrw_table,
496 .crypt_ctx = &ctx->twofish_ctx,
497 .crypt_fn = encrypt_callback,
498 };
499
500 return lrw_crypt(desc, dst, src, nbytes, &req);
501}
502
503static int lrw_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
504 struct scatterlist *src, unsigned int nbytes)
505{
506 struct twofish_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
507 be128 buf[3];
508 struct lrw_crypt_req req = {
509 .tbuf = buf,
510 .tbuflen = sizeof(buf),
511
512 .table_ctx = &ctx->lrw_table,
513 .crypt_ctx = &ctx->twofish_ctx,
514 .crypt_fn = decrypt_callback,
515 };
516
517 return lrw_crypt(desc, dst, src, nbytes, &req);
518}
519
520static void lrw_exit_tfm(struct crypto_tfm *tfm)
521{
522 struct twofish_lrw_ctx *ctx = crypto_tfm_ctx(tfm);
523
524 lrw_free_table(&ctx->lrw_table);
525}
526
527static struct crypto_alg blk_lrw_alg = {
528 .cra_name = "lrw(twofish)",
529 .cra_driver_name = "lrw-twofish-3way",
530 .cra_priority = 300,
531 .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
532 .cra_blocksize = TF_BLOCK_SIZE,
533 .cra_ctxsize = sizeof(struct twofish_lrw_ctx),
534 .cra_alignmask = 0,
535 .cra_type = &crypto_blkcipher_type,
536 .cra_module = THIS_MODULE,
537 .cra_list = LIST_HEAD_INIT(blk_lrw_alg.cra_list),
538 .cra_exit = lrw_exit_tfm,
539 .cra_u = {
540 .blkcipher = {
541 .min_keysize = TF_MIN_KEY_SIZE + TF_BLOCK_SIZE,
542 .max_keysize = TF_MAX_KEY_SIZE + TF_BLOCK_SIZE,
543 .ivsize = TF_BLOCK_SIZE,
544 .setkey = lrw_twofish_setkey,
545 .encrypt = lrw_encrypt,
546 .decrypt = lrw_decrypt,
547 },
548 },
549};
550
551struct twofish_xts_ctx {
552 struct twofish_ctx tweak_ctx;
553 struct twofish_ctx crypt_ctx;
554};
555
556static int xts_twofish_setkey(struct crypto_tfm *tfm, const u8 *key,
557 unsigned int keylen)
558{
559 struct twofish_xts_ctx *ctx = crypto_tfm_ctx(tfm);
560 u32 *flags = &tfm->crt_flags;
561 int err;
562
563 /* key consists of keys of equal size concatenated, therefore
564 * the length must be even
565 */
566 if (keylen % 2) {
567 *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
568 return -EINVAL;
569 }
570
571 /* first half of xts-key is for crypt */
572 err = __twofish_setkey(&ctx->crypt_ctx, key, keylen / 2, flags);
573 if (err)
574 return err;
575
576 /* second half of xts-key is for tweak */
577 return __twofish_setkey(&ctx->tweak_ctx, key + keylen / 2, keylen / 2,
578 flags);
579}
580
581static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
582 struct scatterlist *src, unsigned int nbytes)
583{
584 struct twofish_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
585 be128 buf[3];
586 struct xts_crypt_req req = {
587 .tbuf = buf,
588 .tbuflen = sizeof(buf),
589
590 .tweak_ctx = &ctx->tweak_ctx,
591 .tweak_fn = XTS_TWEAK_CAST(twofish_enc_blk),
592 .crypt_ctx = &ctx->crypt_ctx,
593 .crypt_fn = encrypt_callback,
594 };
595
596 return xts_crypt(desc, dst, src, nbytes, &req);
597}
598
599static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
600 struct scatterlist *src, unsigned int nbytes)
601{
602 struct twofish_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
603 be128 buf[3];
604 struct xts_crypt_req req = {
605 .tbuf = buf,
606 .tbuflen = sizeof(buf),
607
608 .tweak_ctx = &ctx->tweak_ctx,
609 .tweak_fn = XTS_TWEAK_CAST(twofish_enc_blk),
610 .crypt_ctx = &ctx->crypt_ctx,
611 .crypt_fn = decrypt_callback,
612 };
613
614 return xts_crypt(desc, dst, src, nbytes, &req);
615}
616
617static struct crypto_alg blk_xts_alg = {
618 .cra_name = "xts(twofish)",
619 .cra_driver_name = "xts-twofish-3way",
620 .cra_priority = 300,
621 .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
622 .cra_blocksize = TF_BLOCK_SIZE,
623 .cra_ctxsize = sizeof(struct twofish_xts_ctx),
624 .cra_alignmask = 0,
625 .cra_type = &crypto_blkcipher_type,
626 .cra_module = THIS_MODULE,
627 .cra_list = LIST_HEAD_INIT(blk_xts_alg.cra_list),
628 .cra_u = {
629 .blkcipher = {
630 .min_keysize = TF_MIN_KEY_SIZE * 2,
631 .max_keysize = TF_MAX_KEY_SIZE * 2,
632 .ivsize = TF_BLOCK_SIZE,
633 .setkey = xts_twofish_setkey,
634 .encrypt = xts_encrypt,
635 .decrypt = xts_decrypt,
636 },
637 },
638};
639
435int __init init(void) 640int __init init(void)
436{ 641{
437 int err; 642 int err;
@@ -445,9 +650,20 @@ int __init init(void)
445 err = crypto_register_alg(&blk_ctr_alg); 650 err = crypto_register_alg(&blk_ctr_alg);
446 if (err) 651 if (err)
447 goto ctr_err; 652 goto ctr_err;
653 err = crypto_register_alg(&blk_lrw_alg);
654 if (err)
655 goto blk_lrw_err;
656 err = crypto_register_alg(&blk_xts_alg);
657 if (err)
658 goto blk_xts_err;
448 659
449 return 0; 660 return 0;
450 661
662 crypto_unregister_alg(&blk_xts_alg);
663blk_xts_err:
664 crypto_unregister_alg(&blk_lrw_alg);
665blk_lrw_err:
666 crypto_unregister_alg(&blk_ctr_alg);
451ctr_err: 667ctr_err:
452 crypto_unregister_alg(&blk_cbc_alg); 668 crypto_unregister_alg(&blk_cbc_alg);
453cbc_err: 669cbc_err:
@@ -458,6 +674,8 @@ ecb_err:
458 674
459void __exit fini(void) 675void __exit fini(void)
460{ 676{
677 crypto_unregister_alg(&blk_xts_alg);
678 crypto_unregister_alg(&blk_lrw_alg);
461 crypto_unregister_alg(&blk_ctr_alg); 679 crypto_unregister_alg(&blk_ctr_alg);
462 crypto_unregister_alg(&blk_cbc_alg); 680 crypto_unregister_alg(&blk_cbc_alg);
463 crypto_unregister_alg(&blk_ecb_alg); 681 crypto_unregister_alg(&blk_ecb_alg);
diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index 8e41071704a5..49ad773f4b9f 100644
--- a/arch/x86/include/asm/amd_nb.h
+++ b/arch/x86/include/asm/amd_nb.h
@@ -1,6 +1,7 @@
1#ifndef _ASM_X86_AMD_NB_H 1#ifndef _ASM_X86_AMD_NB_H
2#define _ASM_X86_AMD_NB_H 2#define _ASM_X86_AMD_NB_H
3 3
4#include <linux/ioport.h>
4#include <linux/pci.h> 5#include <linux/pci.h>
5 6
6struct amd_nb_bus_dev_range { 7struct amd_nb_bus_dev_range {
@@ -13,6 +14,7 @@ extern const struct pci_device_id amd_nb_misc_ids[];
13extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[]; 14extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
14 15
15extern bool early_is_amd_nb(u32 value); 16extern bool early_is_amd_nb(u32 value);
17extern struct resource *amd_get_mmconfig_range(struct resource *res);
16extern int amd_cache_northbridges(void); 18extern int amd_cache_northbridges(void);
17extern void amd_flush_garts(void); 19extern void amd_flush_garts(void);
18extern int amd_numa_init(void); 20extern int amd_numa_init(void);
diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h
index e020d88ec02d..2f90c51cc49d 100644
--- a/arch/x86/include/asm/bootparam.h
+++ b/arch/x86/include/asm/bootparam.h
@@ -64,6 +64,8 @@ struct setup_header {
64 __u32 payload_offset; 64 __u32 payload_offset;
65 __u32 payload_length; 65 __u32 payload_length;
66 __u64 setup_data; 66 __u64 setup_data;
67 __u64 pref_address;
68 __u32 init_size;
67} __attribute__((packed)); 69} __attribute__((packed));
68 70
69struct sys_desc_table { 71struct sys_desc_table {
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
index 7093e4a6a0bc..844f735fd63a 100644
--- a/arch/x86/include/asm/efi.h
+++ b/arch/x86/include/asm/efi.h
@@ -3,6 +3,8 @@
3 3
4#ifdef CONFIG_X86_32 4#ifdef CONFIG_X86_32
5 5
6#define EFI_LOADER_SIGNATURE "EL32"
7
6extern unsigned long asmlinkage efi_call_phys(void *, ...); 8extern unsigned long asmlinkage efi_call_phys(void *, ...);
7 9
8#define efi_call_phys0(f) efi_call_phys(f) 10#define efi_call_phys0(f) efi_call_phys(f)
@@ -37,6 +39,8 @@ extern unsigned long asmlinkage efi_call_phys(void *, ...);
37 39
38#else /* !CONFIG_X86_32 */ 40#else /* !CONFIG_X86_32 */
39 41
42#define EFI_LOADER_SIGNATURE "EL64"
43
40extern u64 efi_call0(void *fp); 44extern u64 efi_call0(void *fp);
41extern u64 efi_call1(void *fp, u64 arg1); 45extern u64 efi_call1(void *fp, u64 arg1);
42extern u64 efi_call2(void *fp, u64 arg1, u64 arg2); 46extern u64 efi_call2(void *fp, u64 arg1, u64 arg2);
diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h
index 460c74e4852c..4da3c0c4c974 100644
--- a/arch/x86/include/asm/fixmap.h
+++ b/arch/x86/include/asm/fixmap.h
@@ -117,7 +117,7 @@ enum fixed_addresses {
117#endif 117#endif
118 FIX_TEXT_POKE1, /* reserve 2 pages for text_poke() */ 118 FIX_TEXT_POKE1, /* reserve 2 pages for text_poke() */
119 FIX_TEXT_POKE0, /* first page is last, because allocation is backward */ 119 FIX_TEXT_POKE0, /* first page is last, because allocation is backward */
120#ifdef CONFIG_X86_MRST 120#ifdef CONFIG_X86_INTEL_MID
121 FIX_LNW_VRTC, 121 FIX_LNW_VRTC,
122#endif 122#endif
123 __end_of_permanent_fixed_addresses, 123 __end_of_permanent_fixed_addresses,
diff --git a/arch/x86/include/asm/init.h b/arch/x86/include/asm/init.h
index 8dbe353e41e1..adcc0ae73d09 100644
--- a/arch/x86/include/asm/init.h
+++ b/arch/x86/include/asm/init.h
@@ -5,6 +5,8 @@
5extern void __init early_ioremap_page_table_range_init(void); 5extern void __init early_ioremap_page_table_range_init(void);
6#endif 6#endif
7 7
8extern void __init zone_sizes_init(void);
9
8extern unsigned long __init 10extern unsigned long __init
9kernel_physical_mapping_init(unsigned long start, 11kernel_physical_mapping_init(unsigned long start,
10 unsigned long end, 12 unsigned long end,
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index d498943b906c..df75d07571ce 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -112,19 +112,28 @@ static inline void x86_teardown_msi_irq(unsigned int irq)
112{ 112{
113 x86_msi.teardown_msi_irq(irq); 113 x86_msi.teardown_msi_irq(irq);
114} 114}
115static inline void x86_restore_msi_irqs(struct pci_dev *dev, int irq)
116{
117 x86_msi.restore_msi_irqs(dev, irq);
118}
115#define arch_setup_msi_irqs x86_setup_msi_irqs 119#define arch_setup_msi_irqs x86_setup_msi_irqs
116#define arch_teardown_msi_irqs x86_teardown_msi_irqs 120#define arch_teardown_msi_irqs x86_teardown_msi_irqs
117#define arch_teardown_msi_irq x86_teardown_msi_irq 121#define arch_teardown_msi_irq x86_teardown_msi_irq
122#define arch_restore_msi_irqs x86_restore_msi_irqs
118/* implemented in arch/x86/kernel/apic/io_apic. */ 123/* implemented in arch/x86/kernel/apic/io_apic. */
119int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); 124int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
120void native_teardown_msi_irq(unsigned int irq); 125void native_teardown_msi_irq(unsigned int irq);
126void native_restore_msi_irqs(struct pci_dev *dev, int irq);
121/* default to the implementation in drivers/lib/msi.c */ 127/* default to the implementation in drivers/lib/msi.c */
122#define HAVE_DEFAULT_MSI_TEARDOWN_IRQS 128#define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
129#define HAVE_DEFAULT_MSI_RESTORE_IRQS
123void default_teardown_msi_irqs(struct pci_dev *dev); 130void default_teardown_msi_irqs(struct pci_dev *dev);
131void default_restore_msi_irqs(struct pci_dev *dev, int irq);
124#else 132#else
125#define native_setup_msi_irqs NULL 133#define native_setup_msi_irqs NULL
126#define native_teardown_msi_irq NULL 134#define native_teardown_msi_irq NULL
127#define default_teardown_msi_irqs NULL 135#define default_teardown_msi_irqs NULL
136#define default_restore_msi_irqs NULL
128#endif 137#endif
129 138
130#define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys) 139#define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h
index e38197806853..b3a531746026 100644
--- a/arch/x86/include/asm/pci_x86.h
+++ b/arch/x86/include/asm/pci_x86.h
@@ -44,8 +44,6 @@ enum pci_bf_sort_state {
44 44
45/* pci-i386.c */ 45/* pci-i386.c */
46 46
47extern unsigned int pcibios_max_latency;
48
49void pcibios_resource_survey(void); 47void pcibios_resource_survey(void);
50void pcibios_set_cache_line_size(void); 48void pcibios_set_cache_line_size(void);
51 49
diff --git a/arch/x86/include/asm/serpent.h b/arch/x86/include/asm/serpent.h
new file mode 100644
index 000000000000..d3ef63fe0c81
--- /dev/null
+++ b/arch/x86/include/asm/serpent.h
@@ -0,0 +1,63 @@
1#ifndef ASM_X86_SERPENT_H
2#define ASM_X86_SERPENT_H
3
4#include <linux/crypto.h>
5#include <crypto/serpent.h>
6
7#ifdef CONFIG_X86_32
8
9#define SERPENT_PARALLEL_BLOCKS 4
10
11asmlinkage void __serpent_enc_blk_4way(struct serpent_ctx *ctx, u8 *dst,
12 const u8 *src, bool xor);
13asmlinkage void serpent_dec_blk_4way(struct serpent_ctx *ctx, u8 *dst,
14 const u8 *src);
15
16static inline void serpent_enc_blk_xway(struct serpent_ctx *ctx, u8 *dst,
17 const u8 *src)
18{
19 __serpent_enc_blk_4way(ctx, dst, src, false);
20}
21
22static inline void serpent_enc_blk_xway_xor(struct serpent_ctx *ctx, u8 *dst,
23 const u8 *src)
24{
25 __serpent_enc_blk_4way(ctx, dst, src, true);
26}
27
28static inline void serpent_dec_blk_xway(struct serpent_ctx *ctx, u8 *dst,
29 const u8 *src)
30{
31 serpent_dec_blk_4way(ctx, dst, src);
32}
33
34#else
35
36#define SERPENT_PARALLEL_BLOCKS 8
37
38asmlinkage void __serpent_enc_blk_8way(struct serpent_ctx *ctx, u8 *dst,
39 const u8 *src, bool xor);
40asmlinkage void serpent_dec_blk_8way(struct serpent_ctx *ctx, u8 *dst,
41 const u8 *src);
42
43static inline void serpent_enc_blk_xway(struct serpent_ctx *ctx, u8 *dst,
44 const u8 *src)
45{
46 __serpent_enc_blk_8way(ctx, dst, src, false);
47}
48
49static inline void serpent_enc_blk_xway_xor(struct serpent_ctx *ctx, u8 *dst,
50 const u8 *src)
51{
52 __serpent_enc_blk_8way(ctx, dst, src, true);
53}
54
55static inline void serpent_dec_blk_xway(struct serpent_ctx *ctx, u8 *dst,
56 const u8 *src)
57{
58 serpent_dec_blk_8way(ctx, dst, src);
59}
60
61#endif
62
63#endif
diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h
index 9756551ec760..d0f19f9fb846 100644
--- a/arch/x86/include/asm/setup.h
+++ b/arch/x86/include/asm/setup.h
@@ -47,7 +47,7 @@ extern void reserve_standard_io_resources(void);
47extern void i386_reserve_resources(void); 47extern void i386_reserve_resources(void);
48extern void setup_default_timer_irq(void); 48extern void setup_default_timer_irq(void);
49 49
50#ifdef CONFIG_X86_MRST 50#ifdef CONFIG_X86_INTEL_MID
51extern void x86_mrst_early_setup(void); 51extern void x86_mrst_early_setup(void);
52#else 52#else
53static inline void x86_mrst_early_setup(void) { } 53static inline void x86_mrst_early_setup(void) { }
diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h
index 73b11bc0ae6f..0434c400287c 100644
--- a/arch/x86/include/asm/smp.h
+++ b/arch/x86/include/asm/smp.h
@@ -225,5 +225,11 @@ extern int hard_smp_processor_id(void);
225 225
226#endif /* CONFIG_X86_LOCAL_APIC */ 226#endif /* CONFIG_X86_LOCAL_APIC */
227 227
228#ifdef CONFIG_DEBUG_NMI_SELFTEST
229extern void nmi_selftest(void);
230#else
231#define nmi_selftest() do { } while (0)
232#endif
233
228#endif /* __ASSEMBLY__ */ 234#endif /* __ASSEMBLY__ */
229#endif /* _ASM_X86_SMP_H */ 235#endif /* _ASM_X86_SMP_H */
diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
index 74047159d0ab..bc817cd8b443 100644
--- a/arch/x86/include/asm/thread_info.h
+++ b/arch/x86/include/asm/thread_info.h
@@ -40,8 +40,8 @@ struct thread_info {
40 */ 40 */
41 __u8 supervisor_stack[0]; 41 __u8 supervisor_stack[0];
42#endif 42#endif
43 int sig_on_uaccess_error:1; 43 unsigned int sig_on_uaccess_error:1;
44 int uaccess_err:1; /* uaccess failed */ 44 unsigned int uaccess_err:1; /* uaccess failed */
45}; 45};
46 46
47#define INIT_THREAD_INFO(tsk) \ 47#define INIT_THREAD_INFO(tsk) \
diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h
index 800f77c60051..b9676ae37ada 100644
--- a/arch/x86/include/asm/topology.h
+++ b/arch/x86/include/asm/topology.h
@@ -172,7 +172,7 @@ static inline void arch_fix_phys_package_id(int num, u32 slot)
172} 172}
173 173
174struct pci_bus; 174struct pci_bus;
175void x86_pci_root_bus_res_quirks(struct pci_bus *b); 175void x86_pci_root_bus_resources(int bus, struct list_head *resources);
176 176
177#ifdef CONFIG_SMP 177#ifdef CONFIG_SMP
178#define mc_capable() ((boot_cpu_data.x86_max_cores > 1) && \ 178#define mc_capable() ((boot_cpu_data.x86_max_cores > 1) && \
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index 1ac860a09849..517d4767ffdd 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -179,6 +179,7 @@ struct x86_msi_ops {
179 int (*setup_msi_irqs)(struct pci_dev *dev, int nvec, int type); 179 int (*setup_msi_irqs)(struct pci_dev *dev, int nvec, int type);
180 void (*teardown_msi_irq)(unsigned int irq); 180 void (*teardown_msi_irq)(unsigned int irq);
181 void (*teardown_msi_irqs)(struct pci_dev *dev); 181 void (*teardown_msi_irqs)(struct pci_dev *dev);
182 void (*restore_msi_irqs)(struct pci_dev *dev, int irq);
182}; 183};
183 184
184extern struct x86_init_ops x86_init; 185extern struct x86_init_ops x86_init;
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 8baca3c4871c..02b2f05b371e 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -80,6 +80,7 @@ obj-$(CONFIG_APB_TIMER) += apb_timer.o
80obj-$(CONFIG_AMD_NB) += amd_nb.o 80obj-$(CONFIG_AMD_NB) += amd_nb.o
81obj-$(CONFIG_DEBUG_RODATA_TEST) += test_rodata.o 81obj-$(CONFIG_DEBUG_RODATA_TEST) += test_rodata.o
82obj-$(CONFIG_DEBUG_NX_TEST) += test_nx.o 82obj-$(CONFIG_DEBUG_NX_TEST) += test_nx.o
83obj-$(CONFIG_DEBUG_NMI_SELFTEST) += nmi_selftest.o
83 84
84obj-$(CONFIG_KVM_GUEST) += kvm.o 85obj-$(CONFIG_KVM_GUEST) += kvm.o
85obj-$(CONFIG_KVM_CLOCK) += kvmclock.o 86obj-$(CONFIG_KVM_CLOCK) += kvmclock.o
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 013c1810ce72..be16854591cc 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -119,6 +119,37 @@ bool __init early_is_amd_nb(u32 device)
119 return false; 119 return false;
120} 120}
121 121
122struct resource *amd_get_mmconfig_range(struct resource *res)
123{
124 u32 address;
125 u64 base, msr;
126 unsigned segn_busn_bits;
127
128 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
129 return NULL;
130
131 /* assume all cpus from fam10h have mmconfig */
132 if (boot_cpu_data.x86 < 0x10)
133 return NULL;
134
135 address = MSR_FAM10H_MMIO_CONF_BASE;
136 rdmsrl(address, msr);
137
138 /* mmconfig is not enabled */
139 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
140 return NULL;
141
142 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
143
144 segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
145 FAM10H_MMIO_CONF_BUSRANGE_MASK;
146
147 res->flags = IORESOURCE_MEM;
148 res->start = base;
149 res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
150 return res;
151}
152
122int amd_get_subcaches(int cpu) 153int amd_get_subcaches(int cpu)
123{ 154{
124 struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link; 155 struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link;
diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c
index 4f13fafc5264..68de2dc962ec 100644
--- a/arch/x86/kernel/asm-offsets.c
+++ b/arch/x86/kernel/asm-offsets.c
@@ -67,4 +67,6 @@ void common(void) {
67 OFFSET(BP_hardware_subarch, boot_params, hdr.hardware_subarch); 67 OFFSET(BP_hardware_subarch, boot_params, hdr.hardware_subarch);
68 OFFSET(BP_version, boot_params, hdr.version); 68 OFFSET(BP_version, boot_params, hdr.version);
69 OFFSET(BP_kernel_alignment, boot_params, hdr.kernel_alignment); 69 OFFSET(BP_kernel_alignment, boot_params, hdr.kernel_alignment);
70 OFFSET(BP_pref_address, boot_params, hdr.pref_address);
71 OFFSET(BP_code32_start, boot_params, hdr.code32_start);
70} 72}
diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c
index 8071e2f3d6eb..174d938d576b 100644
--- a/arch/x86/kernel/e820.c
+++ b/arch/x86/kernel/e820.c
@@ -19,6 +19,7 @@
19#include <linux/acpi.h> 19#include <linux/acpi.h>
20#include <linux/firmware-map.h> 20#include <linux/firmware-map.h>
21#include <linux/memblock.h> 21#include <linux/memblock.h>
22#include <linux/sort.h>
22 23
23#include <asm/e820.h> 24#include <asm/e820.h>
24#include <asm/proto.h> 25#include <asm/proto.h>
@@ -227,22 +228,38 @@ void __init e820_print_map(char *who)
227 * ____________________33__ 228 * ____________________33__
228 * ______________________4_ 229 * ______________________4_
229 */ 230 */
231struct change_member {
232 struct e820entry *pbios; /* pointer to original bios entry */
233 unsigned long long addr; /* address for this change point */
234};
235
236static int __init cpcompare(const void *a, const void *b)
237{
238 struct change_member * const *app = a, * const *bpp = b;
239 const struct change_member *ap = *app, *bp = *bpp;
240
241 /*
242 * Inputs are pointers to two elements of change_point[]. If their
243 * addresses are unequal, their difference dominates. If the addresses
244 * are equal, then consider one that represents the end of its region
245 * to be greater than one that does not.
246 */
247 if (ap->addr != bp->addr)
248 return ap->addr > bp->addr ? 1 : -1;
249
250 return (ap->addr != ap->pbios->addr) - (bp->addr != bp->pbios->addr);
251}
230 252
231int __init sanitize_e820_map(struct e820entry *biosmap, int max_nr_map, 253int __init sanitize_e820_map(struct e820entry *biosmap, int max_nr_map,
232 u32 *pnr_map) 254 u32 *pnr_map)
233{ 255{
234 struct change_member {
235 struct e820entry *pbios; /* pointer to original bios entry */
236 unsigned long long addr; /* address for this change point */
237 };
238 static struct change_member change_point_list[2*E820_X_MAX] __initdata; 256 static struct change_member change_point_list[2*E820_X_MAX] __initdata;
239 static struct change_member *change_point[2*E820_X_MAX] __initdata; 257 static struct change_member *change_point[2*E820_X_MAX] __initdata;
240 static struct e820entry *overlap_list[E820_X_MAX] __initdata; 258 static struct e820entry *overlap_list[E820_X_MAX] __initdata;
241 static struct e820entry new_bios[E820_X_MAX] __initdata; 259 static struct e820entry new_bios[E820_X_MAX] __initdata;
242 struct change_member *change_tmp;
243 unsigned long current_type, last_type; 260 unsigned long current_type, last_type;
244 unsigned long long last_addr; 261 unsigned long long last_addr;
245 int chgidx, still_changing; 262 int chgidx;
246 int overlap_entries; 263 int overlap_entries;
247 int new_bios_entry; 264 int new_bios_entry;
248 int old_nr, new_nr, chg_nr; 265 int old_nr, new_nr, chg_nr;
@@ -279,35 +296,7 @@ int __init sanitize_e820_map(struct e820entry *biosmap, int max_nr_map,
279 chg_nr = chgidx; 296 chg_nr = chgidx;
280 297
281 /* sort change-point list by memory addresses (low -> high) */ 298 /* sort change-point list by memory addresses (low -> high) */
282 still_changing = 1; 299 sort(change_point, chg_nr, sizeof *change_point, cpcompare, NULL);
283 while (still_changing) {
284 still_changing = 0;
285 for (i = 1; i < chg_nr; i++) {
286 unsigned long long curaddr, lastaddr;
287 unsigned long long curpbaddr, lastpbaddr;
288
289 curaddr = change_point[i]->addr;
290 lastaddr = change_point[i - 1]->addr;
291 curpbaddr = change_point[i]->pbios->addr;
292 lastpbaddr = change_point[i - 1]->pbios->addr;
293
294 /*
295 * swap entries, when:
296 *
297 * curaddr > lastaddr or
298 * curaddr == lastaddr and curaddr == curpbaddr and
299 * lastaddr != lastpbaddr
300 */
301 if (curaddr < lastaddr ||
302 (curaddr == lastaddr && curaddr == curpbaddr &&
303 lastaddr != lastpbaddr)) {
304 change_tmp = change_point[i];
305 change_point[i] = change_point[i-1];
306 change_point[i-1] = change_tmp;
307 still_changing = 1;
308 }
309 }
310 }
311 300
312 /* create a new bios memory map, removing overlaps */ 301 /* create a new bios memory map, removing overlaps */
313 overlap_entries = 0; /* number of entries in the overlap table */ 302 overlap_entries = 0; /* number of entries in the overlap table */
diff --git a/arch/x86/kernel/early_printk.c b/arch/x86/kernel/early_printk.c
index 9d42a52d2331..9b9f18b49918 100644
--- a/arch/x86/kernel/early_printk.c
+++ b/arch/x86/kernel/early_printk.c
@@ -240,7 +240,7 @@ static int __init setup_early_printk(char *buf)
240 if (!strncmp(buf, "xen", 3)) 240 if (!strncmp(buf, "xen", 3))
241 early_console_register(&xenboot_console, keep); 241 early_console_register(&xenboot_console, keep);
242#endif 242#endif
243#ifdef CONFIG_EARLY_PRINTK_MRST 243#ifdef CONFIG_EARLY_PRINTK_INTEL_MID
244 if (!strncmp(buf, "mrst", 4)) { 244 if (!strncmp(buf, "mrst", 4)) {
245 mrst_early_console_init(); 245 mrst_early_console_init();
246 early_console_register(&early_mrst_console, keep); 246 early_console_register(&early_mrst_console, keep);
diff --git a/arch/x86/kernel/irq_32.c b/arch/x86/kernel/irq_32.c
index 72090705a656..40fc86161d92 100644
--- a/arch/x86/kernel/irq_32.c
+++ b/arch/x86/kernel/irq_32.c
@@ -28,6 +28,9 @@ DEFINE_PER_CPU(struct pt_regs *, irq_regs);
28EXPORT_PER_CPU_SYMBOL(irq_regs); 28EXPORT_PER_CPU_SYMBOL(irq_regs);
29 29
30#ifdef CONFIG_DEBUG_STACKOVERFLOW 30#ifdef CONFIG_DEBUG_STACKOVERFLOW
31
32int sysctl_panic_on_stackoverflow __read_mostly;
33
31/* Debugging check for stack overflow: is there less than 1KB free? */ 34/* Debugging check for stack overflow: is there less than 1KB free? */
32static int check_stack_overflow(void) 35static int check_stack_overflow(void)
33{ 36{
@@ -43,6 +46,8 @@ static void print_stack_overflow(void)
43{ 46{
44 printk(KERN_WARNING "low stack detected by irq handler\n"); 47 printk(KERN_WARNING "low stack detected by irq handler\n");
45 dump_stack(); 48 dump_stack();
49 if (sysctl_panic_on_stackoverflow)
50 panic("low stack detected by irq handler - check messages\n");
46} 51}
47 52
48#else 53#else
diff --git a/arch/x86/kernel/irq_64.c b/arch/x86/kernel/irq_64.c
index 69bca468c47a..d04d3ecded62 100644
--- a/arch/x86/kernel/irq_64.c
+++ b/arch/x86/kernel/irq_64.c
@@ -26,6 +26,8 @@ EXPORT_PER_CPU_SYMBOL(irq_stat);
26DEFINE_PER_CPU(struct pt_regs *, irq_regs); 26DEFINE_PER_CPU(struct pt_regs *, irq_regs);
27EXPORT_PER_CPU_SYMBOL(irq_regs); 27EXPORT_PER_CPU_SYMBOL(irq_regs);
28 28
29int sysctl_panic_on_stackoverflow;
30
29/* 31/*
30 * Probabilistic stack overflow check: 32 * Probabilistic stack overflow check:
31 * 33 *
@@ -36,18 +38,39 @@ EXPORT_PER_CPU_SYMBOL(irq_regs);
36static inline void stack_overflow_check(struct pt_regs *regs) 38static inline void stack_overflow_check(struct pt_regs *regs)
37{ 39{
38#ifdef CONFIG_DEBUG_STACKOVERFLOW 40#ifdef CONFIG_DEBUG_STACKOVERFLOW
41#define STACK_TOP_MARGIN 128
42 struct orig_ist *oist;
43 u64 irq_stack_top, irq_stack_bottom;
44 u64 estack_top, estack_bottom;
39 u64 curbase = (u64)task_stack_page(current); 45 u64 curbase = (u64)task_stack_page(current);
40 46
41 if (user_mode_vm(regs)) 47 if (user_mode_vm(regs))
42 return; 48 return;
43 49
44 WARN_ONCE(regs->sp >= curbase && 50 if (regs->sp >= curbase + sizeof(struct thread_info) +
45 regs->sp <= curbase + THREAD_SIZE && 51 sizeof(struct pt_regs) + STACK_TOP_MARGIN &&
46 regs->sp < curbase + sizeof(struct thread_info) + 52 regs->sp <= curbase + THREAD_SIZE)
47 sizeof(struct pt_regs) + 128, 53 return;
54
55 irq_stack_top = (u64)__get_cpu_var(irq_stack_union.irq_stack) +
56 STACK_TOP_MARGIN;
57 irq_stack_bottom = (u64)__get_cpu_var(irq_stack_ptr);
58 if (regs->sp >= irq_stack_top && regs->sp <= irq_stack_bottom)
59 return;
60
61 oist = &__get_cpu_var(orig_ist);
62 estack_top = (u64)oist->ist[0] - EXCEPTION_STKSZ + STACK_TOP_MARGIN;
63 estack_bottom = (u64)oist->ist[N_EXCEPTION_STACKS - 1];
64 if (regs->sp >= estack_top && regs->sp <= estack_bottom)
65 return;
66
67 WARN_ONCE(1, "do_IRQ(): %s has overflown the kernel stack (cur:%Lx,sp:%lx,irq stk top-bottom:%Lx-%Lx,exception stk top-bottom:%Lx-%Lx)\n",
68 current->comm, curbase, regs->sp,
69 irq_stack_top, irq_stack_bottom,
70 estack_top, estack_bottom);
48 71
49 "do_IRQ: %s near stack overflow (cur:%Lx,sp:%lx)\n", 72 if (sysctl_panic_on_stackoverflow)
50 current->comm, curbase, regs->sp); 73 panic("low stack detected by irq handler - check messages\n");
51#endif 74#endif
52} 75}
53 76
diff --git a/arch/x86/kernel/nmi_selftest.c b/arch/x86/kernel/nmi_selftest.c
new file mode 100644
index 000000000000..0d01a8ea4e11
--- /dev/null
+++ b/arch/x86/kernel/nmi_selftest.c
@@ -0,0 +1,180 @@
1/*
2 * arch/x86/kernel/nmi-selftest.c
3 *
4 * Testsuite for NMI: IPIs
5 *
6 * Started by Don Zickus:
7 * (using lib/locking-selftest.c as a guide)
8 *
9 * Copyright (C) 2011 Red Hat, Inc., Don Zickus <dzickus@redhat.com>
10 */
11
12#include <linux/smp.h>
13#include <linux/cpumask.h>
14#include <linux/delay.h>
15
16#include <asm/apic.h>
17#include <asm/nmi.h>
18
19#define SUCCESS 0
20#define FAILURE 1
21#define TIMEOUT 2
22
23static int nmi_fail;
24
25/* check to see if NMI IPIs work on this machine */
26static DECLARE_BITMAP(nmi_ipi_mask, NR_CPUS) __read_mostly;
27
28static int testcase_total;
29static int testcase_successes;
30static int expected_testcase_failures;
31static int unexpected_testcase_failures;
32static int unexpected_testcase_unknowns;
33
34static int nmi_unk_cb(unsigned int val, struct pt_regs *regs)
35{
36 unexpected_testcase_unknowns++;
37 return NMI_HANDLED;
38}
39
40static void init_nmi_testsuite(void)
41{
42 /* trap all the unknown NMIs we may generate */
43 register_nmi_handler(NMI_UNKNOWN, nmi_unk_cb, 0, "nmi_selftest_unk");
44}
45
46static void cleanup_nmi_testsuite(void)
47{
48 unregister_nmi_handler(NMI_UNKNOWN, "nmi_selftest_unk");
49}
50
51static int test_nmi_ipi_callback(unsigned int val, struct pt_regs *regs)
52{
53 int cpu = raw_smp_processor_id();
54
55 if (cpumask_test_and_clear_cpu(cpu, to_cpumask(nmi_ipi_mask)))
56 return NMI_HANDLED;
57
58 return NMI_DONE;
59}
60
61static void test_nmi_ipi(struct cpumask *mask)
62{
63 unsigned long timeout;
64
65 if (register_nmi_handler(NMI_LOCAL, test_nmi_ipi_callback,
66 NMI_FLAG_FIRST, "nmi_selftest")) {
67 nmi_fail = FAILURE;
68 return;
69 }
70
71 /* sync above data before sending NMI */
72 wmb();
73
74 apic->send_IPI_mask(mask, NMI_VECTOR);
75
76 /* Don't wait longer than a second */
77 timeout = USEC_PER_SEC;
78 while (!cpumask_empty(mask) && timeout--)
79 udelay(1);
80
81 /* What happens if we timeout, do we still unregister?? */
82 unregister_nmi_handler(NMI_LOCAL, "nmi_selftest");
83
84 if (!timeout)
85 nmi_fail = TIMEOUT;
86 return;
87}
88
89static void remote_ipi(void)
90{
91 cpumask_copy(to_cpumask(nmi_ipi_mask), cpu_online_mask);
92 cpumask_clear_cpu(smp_processor_id(), to_cpumask(nmi_ipi_mask));
93 if (!cpumask_empty(to_cpumask(nmi_ipi_mask)))
94 test_nmi_ipi(to_cpumask(nmi_ipi_mask));
95}
96
97static void local_ipi(void)
98{
99 cpumask_clear(to_cpumask(nmi_ipi_mask));
100 cpumask_set_cpu(smp_processor_id(), to_cpumask(nmi_ipi_mask));
101 test_nmi_ipi(to_cpumask(nmi_ipi_mask));
102}
103
104static void reset_nmi(void)
105{
106 nmi_fail = 0;
107}
108
109static void dotest(void (*testcase_fn)(void), int expected)
110{
111 testcase_fn();
112 /*
113 * Filter out expected failures:
114 */
115 if (nmi_fail != expected) {
116 unexpected_testcase_failures++;
117
118 if (nmi_fail == FAILURE)
119 printk("FAILED |");
120 else if (nmi_fail == TIMEOUT)
121 printk("TIMEOUT|");
122 else
123 printk("ERROR |");
124 dump_stack();
125 } else {
126 testcase_successes++;
127 printk(" ok |");
128 }
129 testcase_total++;
130
131 reset_nmi();
132}
133
134static inline void print_testname(const char *testname)
135{
136 printk("%12s:", testname);
137}
138
139void nmi_selftest(void)
140{
141 init_nmi_testsuite();
142
143 /*
144 * Run the testsuite:
145 */
146 printk("----------------\n");
147 printk("| NMI testsuite:\n");
148 printk("--------------------\n");
149
150 print_testname("remote IPI");
151 dotest(remote_ipi, SUCCESS);
152 printk("\n");
153 print_testname("local IPI");
154 dotest(local_ipi, SUCCESS);
155 printk("\n");
156
157 cleanup_nmi_testsuite();
158
159 if (unexpected_testcase_failures) {
160 printk("--------------------\n");
161 printk("BUG: %3d unexpected failures (out of %3d) - debugging disabled! |\n",
162 unexpected_testcase_failures, testcase_total);
163 printk("-----------------------------------------------------------------\n");
164 } else if (expected_testcase_failures && testcase_successes) {
165 printk("--------------------\n");
166 printk("%3d out of %3d testcases failed, as expected. |\n",
167 expected_testcase_failures, testcase_total);
168 printk("----------------------------------------------------\n");
169 } else if (expected_testcase_failures && !testcase_successes) {
170 printk("--------------------\n");
171 printk("All %3d testcases failed, as expected. |\n",
172 expected_testcase_failures);
173 printk("----------------------------------------\n");
174 } else {
175 printk("--------------------\n");
176 printk("Good, all %3d testcases passed! |\n",
177 testcase_successes);
178 printk("---------------------------------\n");
179 }
180}
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index d05444ac2aea..d7d5099fe874 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -749,12 +749,7 @@ void __init setup_arch(char **cmdline_p)
749#endif 749#endif
750#ifdef CONFIG_EFI 750#ifdef CONFIG_EFI
751 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature, 751 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
752#ifdef CONFIG_X86_32 752 EFI_LOADER_SIGNATURE, 4)) {
753 "EL32",
754#else
755 "EL64",
756#endif
757 4)) {
758 efi_enabled = 1; 753 efi_enabled = 1;
759 efi_memblock_x86_reserve_range(); 754 efi_memblock_x86_reserve_range();
760 } 755 }
diff --git a/arch/x86/kernel/smp.c b/arch/x86/kernel/smp.c
index 16204dc15484..66c74f481cab 100644
--- a/arch/x86/kernel/smp.c
+++ b/arch/x86/kernel/smp.c
@@ -29,6 +29,7 @@
29#include <asm/mmu_context.h> 29#include <asm/mmu_context.h>
30#include <asm/proto.h> 30#include <asm/proto.h>
31#include <asm/apic.h> 31#include <asm/apic.h>
32#include <asm/nmi.h>
32/* 33/*
33 * Some notes on x86 processor bugs affecting SMP operation: 34 * Some notes on x86 processor bugs affecting SMP operation:
34 * 35 *
@@ -148,6 +149,60 @@ void native_send_call_func_ipi(const struct cpumask *mask)
148 free_cpumask_var(allbutself); 149 free_cpumask_var(allbutself);
149} 150}
150 151
152static atomic_t stopping_cpu = ATOMIC_INIT(-1);
153
154static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs)
155{
156 /* We are registered on stopping cpu too, avoid spurious NMI */
157 if (raw_smp_processor_id() == atomic_read(&stopping_cpu))
158 return NMI_HANDLED;
159
160 stop_this_cpu(NULL);
161
162 return NMI_HANDLED;
163}
164
165static void native_nmi_stop_other_cpus(int wait)
166{
167 unsigned long flags;
168 unsigned long timeout;
169
170 if (reboot_force)
171 return;
172
173 /*
174 * Use an own vector here because smp_call_function
175 * does lots of things not suitable in a panic situation.
176 */
177 if (num_online_cpus() > 1) {
178 /* did someone beat us here? */
179 if (atomic_cmpxchg(&stopping_cpu, -1, safe_smp_processor_id()) != -1)
180 return;
181
182 if (register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback,
183 NMI_FLAG_FIRST, "smp_stop"))
184 /* Note: we ignore failures here */
185 return;
186
187 /* sync above data before sending NMI */
188 wmb();
189
190 apic->send_IPI_allbutself(NMI_VECTOR);
191
192 /*
193 * Don't wait longer than a second if the caller
194 * didn't ask us to wait.
195 */
196 timeout = USEC_PER_SEC;
197 while (num_online_cpus() > 1 && (wait || timeout--))
198 udelay(1);
199 }
200
201 local_irq_save(flags);
202 disable_local_APIC();
203 local_irq_restore(flags);
204}
205
151/* 206/*
152 * this function calls the 'stop' function on all other CPUs in the system. 207 * this function calls the 'stop' function on all other CPUs in the system.
153 */ 208 */
@@ -160,7 +215,7 @@ asmlinkage void smp_reboot_interrupt(void)
160 irq_exit(); 215 irq_exit();
161} 216}
162 217
163static void native_stop_other_cpus(int wait) 218static void native_irq_stop_other_cpus(int wait)
164{ 219{
165 unsigned long flags; 220 unsigned long flags;
166 unsigned long timeout; 221 unsigned long timeout;
@@ -194,6 +249,11 @@ static void native_stop_other_cpus(int wait)
194 local_irq_restore(flags); 249 local_irq_restore(flags);
195} 250}
196 251
252static void native_smp_disable_nmi_ipi(void)
253{
254 smp_ops.stop_other_cpus = native_irq_stop_other_cpus;
255}
256
197/* 257/*
198 * Reschedule call back. 258 * Reschedule call back.
199 */ 259 */
@@ -225,12 +285,20 @@ void smp_call_function_single_interrupt(struct pt_regs *regs)
225 irq_exit(); 285 irq_exit();
226} 286}
227 287
288static int __init nonmi_ipi_setup(char *str)
289{
290 native_smp_disable_nmi_ipi();
291 return 1;
292}
293
294__setup("nonmi_ipi", nonmi_ipi_setup);
295
228struct smp_ops smp_ops = { 296struct smp_ops smp_ops = {
229 .smp_prepare_boot_cpu = native_smp_prepare_boot_cpu, 297 .smp_prepare_boot_cpu = native_smp_prepare_boot_cpu,
230 .smp_prepare_cpus = native_smp_prepare_cpus, 298 .smp_prepare_cpus = native_smp_prepare_cpus,
231 .smp_cpus_done = native_smp_cpus_done, 299 .smp_cpus_done = native_smp_cpus_done,
232 300
233 .stop_other_cpus = native_stop_other_cpus, 301 .stop_other_cpus = native_nmi_stop_other_cpus,
234 .smp_send_reschedule = native_smp_send_reschedule, 302 .smp_send_reschedule = native_smp_send_reschedule,
235 303
236 .cpu_up = native_cpu_up, 304 .cpu_up = native_cpu_up,
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index e38e21754eea..66d250c00d11 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -207,23 +207,29 @@ static void __cpuinit smp_callin(void)
207 * Need to setup vector mappings before we enable interrupts. 207 * Need to setup vector mappings before we enable interrupts.
208 */ 208 */
209 setup_vector_irq(smp_processor_id()); 209 setup_vector_irq(smp_processor_id());
210
211 /*
212 * Save our processor parameters. Note: this information
213 * is needed for clock calibration.
214 */
215 smp_store_cpu_info(cpuid);
216
210 /* 217 /*
211 * Get our bogomips. 218 * Get our bogomips.
219 * Update loops_per_jiffy in cpu_data. Previous call to
220 * smp_store_cpu_info() stored a value that is close but not as
221 * accurate as the value just calculated.
212 * 222 *
213 * Need to enable IRQs because it can take longer and then 223 * Need to enable IRQs because it can take longer and then
214 * the NMI watchdog might kill us. 224 * the NMI watchdog might kill us.
215 */ 225 */
216 local_irq_enable(); 226 local_irq_enable();
217 calibrate_delay(); 227 calibrate_delay();
228 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
218 local_irq_disable(); 229 local_irq_disable();
219 pr_debug("Stack at about %p\n", &cpuid); 230 pr_debug("Stack at about %p\n", &cpuid);
220 231
221 /* 232 /*
222 * Save our processor parameters
223 */
224 smp_store_cpu_info(cpuid);
225
226 /*
227 * This must be done before setting cpu_online_mask 233 * This must be done before setting cpu_online_mask
228 * or calling notify_cpu_starting. 234 * or calling notify_cpu_starting.
229 */ 235 */
@@ -1143,6 +1149,7 @@ void __init native_smp_cpus_done(unsigned int max_cpus)
1143{ 1149{
1144 pr_debug("Boot done.\n"); 1150 pr_debug("Boot done.\n");
1145 1151
1152 nmi_selftest();
1146 impress_friends(); 1153 impress_friends();
1147#ifdef CONFIG_X86_IO_APIC 1154#ifdef CONFIG_X86_IO_APIC
1148 setup_ioapic_dest(); 1155 setup_ioapic_dest();
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 2c9cf0fd78f5..c0dd5b603749 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -995,3 +995,23 @@ void __init tsc_init(void)
995 check_system_tsc_reliable(); 995 check_system_tsc_reliable();
996} 996}
997 997
998#ifdef CONFIG_SMP
999/*
1000 * If we have a constant TSC and are using the TSC for the delay loop,
1001 * we can skip clock calibration if another cpu in the same socket has already
1002 * been calibrated. This assumes that CONSTANT_TSC applies to all
1003 * cpus in the socket - this should be a safe assumption.
1004 */
1005unsigned long __cpuinit calibrate_delay_is_known(void)
1006{
1007 int i, cpu = smp_processor_id();
1008
1009 if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
1010 return 0;
1011
1012 for_each_online_cpu(i)
1013 if (cpu_data(i).phys_proc_id == cpu_data(cpu).phys_proc_id)
1014 return cpu_data(i).loops_per_jiffy;
1015 return 0;
1016}
1017#endif
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index 91f83e21b989..947a06ccc673 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -115,4 +115,5 @@ struct x86_msi_ops x86_msi = {
115 .setup_msi_irqs = native_setup_msi_irqs, 115 .setup_msi_irqs = native_setup_msi_irqs,
116 .teardown_msi_irq = native_teardown_msi_irq, 116 .teardown_msi_irq = native_teardown_msi_irq,
117 .teardown_msi_irqs = default_teardown_msi_irqs, 117 .teardown_msi_irqs = default_teardown_msi_irqs,
118 .restore_msi_irqs = default_restore_msi_irqs,
118}; 119};
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index a298914058f9..6cabf6570d64 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -3,6 +3,7 @@
3#include <linux/ioport.h> 3#include <linux/ioport.h>
4#include <linux/swap.h> 4#include <linux/swap.h>
5#include <linux/memblock.h> 5#include <linux/memblock.h>
6#include <linux/bootmem.h> /* for max_low_pfn */
6 7
7#include <asm/cacheflush.h> 8#include <asm/cacheflush.h>
8#include <asm/e820.h> 9#include <asm/e820.h>
@@ -15,6 +16,7 @@
15#include <asm/tlbflush.h> 16#include <asm/tlbflush.h>
16#include <asm/tlb.h> 17#include <asm/tlb.h>
17#include <asm/proto.h> 18#include <asm/proto.h>
19#include <asm/dma.h> /* for MAX_DMA_PFN */
18 20
19unsigned long __initdata pgt_buf_start; 21unsigned long __initdata pgt_buf_start;
20unsigned long __meminitdata pgt_buf_end; 22unsigned long __meminitdata pgt_buf_end;
@@ -392,3 +394,24 @@ void free_initrd_mem(unsigned long start, unsigned long end)
392 free_init_pages("initrd memory", start, PAGE_ALIGN(end)); 394 free_init_pages("initrd memory", start, PAGE_ALIGN(end));
393} 395}
394#endif 396#endif
397
398void __init zone_sizes_init(void)
399{
400 unsigned long max_zone_pfns[MAX_NR_ZONES];
401
402 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
403
404#ifdef CONFIG_ZONE_DMA
405 max_zone_pfns[ZONE_DMA] = MAX_DMA_PFN;
406#endif
407#ifdef CONFIG_ZONE_DMA32
408 max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
409#endif
410 max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
411#ifdef CONFIG_HIGHMEM
412 max_zone_pfns[ZONE_HIGHMEM] = max_pfn;
413#endif
414
415 free_area_init_nodes(max_zone_pfns);
416}
417
diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c
index 0c1da394a634..8663f6c47ccb 100644
--- a/arch/x86/mm/init_32.c
+++ b/arch/x86/mm/init_32.c
@@ -668,22 +668,6 @@ void __init initmem_init(void)
668} 668}
669#endif /* !CONFIG_NEED_MULTIPLE_NODES */ 669#endif /* !CONFIG_NEED_MULTIPLE_NODES */
670 670
671static void __init zone_sizes_init(void)
672{
673 unsigned long max_zone_pfns[MAX_NR_ZONES];
674 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
675#ifdef CONFIG_ZONE_DMA
676 max_zone_pfns[ZONE_DMA] =
677 virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
678#endif
679 max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
680#ifdef CONFIG_HIGHMEM
681 max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
682#endif
683
684 free_area_init_nodes(max_zone_pfns);
685}
686
687void __init setup_bootmem_allocator(void) 671void __init setup_bootmem_allocator(void)
688{ 672{
689 printk(KERN_INFO " mapped low ram: 0 - %08lx\n", 673 printk(KERN_INFO " mapped low ram: 0 - %08lx\n",
@@ -754,6 +738,17 @@ void __init mem_init(void)
754#ifdef CONFIG_FLATMEM 738#ifdef CONFIG_FLATMEM
755 BUG_ON(!mem_map); 739 BUG_ON(!mem_map);
756#endif 740#endif
741 /*
742 * With CONFIG_DEBUG_PAGEALLOC initialization of highmem pages has to
743 * be done before free_all_bootmem(). Memblock use free low memory for
744 * temporary data (see find_range_array()) and for this purpose can use
745 * pages that was already passed to the buddy allocator, hence marked as
746 * not accessible in the page tables when compiled with
747 * CONFIG_DEBUG_PAGEALLOC. Otherwise order of initialization is not
748 * important here.
749 */
750 set_highmem_pages_init();
751
757 /* this will put all low memory onto the freelists */ 752 /* this will put all low memory onto the freelists */
758 totalram_pages += free_all_bootmem(); 753 totalram_pages += free_all_bootmem();
759 754
@@ -765,8 +760,6 @@ void __init mem_init(void)
765 if (page_is_ram(tmp) && PageReserved(pfn_to_page(tmp))) 760 if (page_is_ram(tmp) && PageReserved(pfn_to_page(tmp)))
766 reservedpages++; 761 reservedpages++;
767 762
768 set_highmem_pages_init();
769
770 codesize = (unsigned long) &_etext - (unsigned long) &_text; 763 codesize = (unsigned long) &_etext - (unsigned long) &_text;
771 datasize = (unsigned long) &_edata - (unsigned long) &_etext; 764 datasize = (unsigned long) &_edata - (unsigned long) &_etext;
772 initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin; 765 initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index a8a56ce3a962..436a0309db33 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -614,15 +614,6 @@ void __init initmem_init(void)
614 614
615void __init paging_init(void) 615void __init paging_init(void)
616{ 616{
617 unsigned long max_zone_pfns[MAX_NR_ZONES];
618
619 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
620#ifdef CONFIG_ZONE_DMA
621 max_zone_pfns[ZONE_DMA] = MAX_DMA_PFN;
622#endif
623 max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
624 max_zone_pfns[ZONE_NORMAL] = max_pfn;
625
626 sparse_memory_present_with_active_regions(MAX_NUMNODES); 617 sparse_memory_present_with_active_regions(MAX_NUMNODES);
627 sparse_init(); 618 sparse_init();
628 619
@@ -634,7 +625,7 @@ void __init paging_init(void)
634 */ 625 */
635 node_clear_state(0, N_NORMAL_MEMORY); 626 node_clear_state(0, N_NORMAL_MEMORY);
636 627
637 free_area_init_nodes(max_zone_pfns); 628 zone_sizes_init();
638} 629}
639 630
640/* 631/*
diff --git a/arch/x86/mm/mmap.c b/arch/x86/mm/mmap.c
index 4b5ba85eb5c9..845df6835f9f 100644
--- a/arch/x86/mm/mmap.c
+++ b/arch/x86/mm/mmap.c
@@ -75,9 +75,9 @@ static unsigned long mmap_rnd(void)
75 */ 75 */
76 if (current->flags & PF_RANDOMIZE) { 76 if (current->flags & PF_RANDOMIZE) {
77 if (mmap_is_ia32()) 77 if (mmap_is_ia32())
78 rnd = (long)get_random_int() % (1<<8); 78 rnd = get_random_int() % (1<<8);
79 else 79 else
80 rnd = (long)(get_random_int() % (1<<28)); 80 rnd = get_random_int() % (1<<28);
81 } 81 }
82 return rnd << PAGE_SHIFT; 82 return rnd << PAGE_SHIFT;
83} 83}
diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c
index 496f494593bf..020cd2e80873 100644
--- a/arch/x86/mm/numa.c
+++ b/arch/x86/mm/numa.c
@@ -422,8 +422,9 @@ static int __init numa_alloc_distance(void)
422 * calls are ignored until the distance table is reset with 422 * calls are ignored until the distance table is reset with
423 * numa_reset_distance(). 423 * numa_reset_distance().
424 * 424 *
425 * If @from or @to is higher than the highest known node at the time of 425 * If @from or @to is higher than the highest known node or lower than zero
426 * table creation or @distance doesn't make sense, the call is ignored. 426 * at the time of table creation or @distance doesn't make sense, the call
427 * is ignored.
427 * This is to allow simplification of specific NUMA config implementations. 428 * This is to allow simplification of specific NUMA config implementations.
428 */ 429 */
429void __init numa_set_distance(int from, int to, int distance) 430void __init numa_set_distance(int from, int to, int distance)
@@ -431,8 +432,9 @@ void __init numa_set_distance(int from, int to, int distance)
431 if (!numa_distance && numa_alloc_distance() < 0) 432 if (!numa_distance && numa_alloc_distance() < 0)
432 return; 433 return;
433 434
434 if (from >= numa_distance_cnt || to >= numa_distance_cnt) { 435 if (from >= numa_distance_cnt || to >= numa_distance_cnt ||
435 printk_once(KERN_DEBUG "NUMA: Debug: distance out of bound, from=%d to=%d distance=%d\n", 436 from < 0 || to < 0) {
437 pr_warn_once("NUMA: Warning: node ids are out of bound, from=%d to=%d distance=%d\n",
436 from, to, distance); 438 from, to, distance);
437 return; 439 return;
438 } 440 }
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index eda2acbb6e81..e1ebde315210 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -1334,12 +1334,6 @@ void kernel_map_pages(struct page *page, int numpages, int enable)
1334 } 1334 }
1335 1335
1336 /* 1336 /*
1337 * If page allocator is not up yet then do not call c_p_a():
1338 */
1339 if (!debug_pagealloc_enabled)
1340 return;
1341
1342 /*
1343 * The return value is ignored as the calls cannot fail. 1337 * The return value is ignored as the calls cannot fail.
1344 * Large pages for identity mappings are not used at boot time 1338 * Large pages for identity mappings are not used at boot time
1345 * and hence no memory allocations during large page split. 1339 * and hence no memory allocations during large page split.
diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile
index 6b8759f7634e..e76e18c94a3c 100644
--- a/arch/x86/pci/Makefile
+++ b/arch/x86/pci/Makefile
@@ -15,11 +15,12 @@ obj-$(CONFIG_X86_VISWS) += visws.o
15 15
16obj-$(CONFIG_X86_NUMAQ) += numaq_32.o 16obj-$(CONFIG_X86_NUMAQ) += numaq_32.o
17 17
18obj-$(CONFIG_X86_MRST) += mrst.o 18obj-$(CONFIG_X86_INTEL_MID) += mrst.o
19 19
20obj-y += common.o early.o 20obj-y += common.o early.o
21obj-y += amd_bus.o bus_numa.o 21obj-y += bus_numa.o
22 22
23obj-$(CONFIG_AMD_NB) += amd_bus.o
23obj-$(CONFIG_PCI_CNB20LE_QUIRK) += broadcom_bus.o 24obj-$(CONFIG_PCI_CNB20LE_QUIRK) += broadcom_bus.o
24 25
25ifeq ($(CONFIG_PCI_DEBUG),y) 26ifeq ($(CONFIG_PCI_DEBUG),y)
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index 404f21a3ff9e..a312e76063a7 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -12,7 +12,7 @@ struct pci_root_info {
12 char *name; 12 char *name;
13 unsigned int res_num; 13 unsigned int res_num;
14 struct resource *res; 14 struct resource *res;
15 struct pci_bus *bus; 15 struct list_head *resources;
16 int busnum; 16 int busnum;
17}; 17};
18 18
@@ -24,6 +24,12 @@ static int __init set_use_crs(const struct dmi_system_id *id)
24 return 0; 24 return 0;
25} 25}
26 26
27static int __init set_nouse_crs(const struct dmi_system_id *id)
28{
29 pci_use_crs = false;
30 return 0;
31}
32
27static const struct dmi_system_id pci_use_crs_table[] __initconst = { 33static const struct dmi_system_id pci_use_crs_table[] __initconst = {
28 /* http://bugzilla.kernel.org/show_bug.cgi?id=14183 */ 34 /* http://bugzilla.kernel.org/show_bug.cgi?id=14183 */
29 { 35 {
@@ -54,6 +60,29 @@ static const struct dmi_system_id pci_use_crs_table[] __initconst = {
54 DMI_MATCH(DMI_BIOS_VENDOR, "American Megatrends Inc."), 60 DMI_MATCH(DMI_BIOS_VENDOR, "American Megatrends Inc."),
55 }, 61 },
56 }, 62 },
63
64 /* Now for the blacklist.. */
65
66 /* https://bugzilla.redhat.com/show_bug.cgi?id=769657 */
67 {
68 .callback = set_nouse_crs,
69 .ident = "Dell Studio 1557",
70 .matches = {
71 DMI_MATCH(DMI_BOARD_VENDOR, "Dell Inc."),
72 DMI_MATCH(DMI_PRODUCT_NAME, "Studio 1557"),
73 DMI_MATCH(DMI_BIOS_VERSION, "A09"),
74 },
75 },
76 /* https://bugzilla.redhat.com/show_bug.cgi?id=769657 */
77 {
78 .callback = set_nouse_crs,
79 .ident = "Thinkpad SL510",
80 .matches = {
81 DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
82 DMI_MATCH(DMI_BOARD_NAME, "2847DFG"),
83 DMI_MATCH(DMI_BIOS_VERSION, "6JET85WW (1.43 )"),
84 },
85 },
57 {} 86 {}
58}; 87};
59 88
@@ -149,7 +178,7 @@ setup_resource(struct acpi_resource *acpi_res, void *data)
149 struct acpi_resource_address64 addr; 178 struct acpi_resource_address64 addr;
150 acpi_status status; 179 acpi_status status;
151 unsigned long flags; 180 unsigned long flags;
152 u64 start, end; 181 u64 start, orig_end, end;
153 182
154 status = resource_to_addr(acpi_res, &addr); 183 status = resource_to_addr(acpi_res, &addr);
155 if (!ACPI_SUCCESS(status)) 184 if (!ACPI_SUCCESS(status))
@@ -165,7 +194,21 @@ setup_resource(struct acpi_resource *acpi_res, void *data)
165 return AE_OK; 194 return AE_OK;
166 195
167 start = addr.minimum + addr.translation_offset; 196 start = addr.minimum + addr.translation_offset;
168 end = addr.maximum + addr.translation_offset; 197 orig_end = end = addr.maximum + addr.translation_offset;
198
199 /* Exclude non-addressable range or non-addressable portion of range */
200 end = min(end, (u64)iomem_resource.end);
201 if (end <= start) {
202 dev_info(&info->bridge->dev,
203 "host bridge window [%#llx-%#llx] "
204 "(ignored, not CPU addressable)\n", start, orig_end);
205 return AE_OK;
206 } else if (orig_end != end) {
207 dev_info(&info->bridge->dev,
208 "host bridge window [%#llx-%#llx] "
209 "([%#llx-%#llx] ignored, not CPU addressable)\n",
210 start, orig_end, end + 1, orig_end);
211 }
169 212
170 res = &info->res[info->res_num]; 213 res = &info->res[info->res_num];
171 res->name = info->name; 214 res->name = info->name;
@@ -261,23 +304,20 @@ static void add_resources(struct pci_root_info *info)
261 "ignoring host bridge window %pR (conflicts with %s %pR)\n", 304 "ignoring host bridge window %pR (conflicts with %s %pR)\n",
262 res, conflict->name, conflict); 305 res, conflict->name, conflict);
263 else 306 else
264 pci_bus_add_resource(info->bus, res, 0); 307 pci_add_resource(info->resources, res);
265 } 308 }
266} 309}
267 310
268static void 311static void
269get_current_resources(struct acpi_device *device, int busnum, 312get_current_resources(struct acpi_device *device, int busnum,
270 int domain, struct pci_bus *bus) 313 int domain, struct list_head *resources)
271{ 314{
272 struct pci_root_info info; 315 struct pci_root_info info;
273 size_t size; 316 size_t size;
274 317
275 if (pci_use_crs)
276 pci_bus_remove_resources(bus);
277
278 info.bridge = device; 318 info.bridge = device;
279 info.bus = bus;
280 info.res_num = 0; 319 info.res_num = 0;
320 info.resources = resources;
281 acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_resource, 321 acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_resource,
282 &info); 322 &info);
283 if (!info.res_num) 323 if (!info.res_num)
@@ -286,7 +326,7 @@ get_current_resources(struct acpi_device *device, int busnum,
286 size = sizeof(*info.res) * info.res_num; 326 size = sizeof(*info.res) * info.res_num;
287 info.res = kmalloc(size, GFP_KERNEL); 327 info.res = kmalloc(size, GFP_KERNEL);
288 if (!info.res) 328 if (!info.res)
289 goto res_alloc_fail; 329 return;
290 330
291 info.name = kasprintf(GFP_KERNEL, "PCI Bus %04x:%02x", domain, busnum); 331 info.name = kasprintf(GFP_KERNEL, "PCI Bus %04x:%02x", domain, busnum);
292 if (!info.name) 332 if (!info.name)
@@ -301,8 +341,6 @@ get_current_resources(struct acpi_device *device, int busnum,
301 341
302name_alloc_fail: 342name_alloc_fail:
303 kfree(info.res); 343 kfree(info.res);
304res_alloc_fail:
305 return;
306} 344}
307 345
308struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root) 346struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
@@ -310,6 +348,7 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
310 struct acpi_device *device = root->device; 348 struct acpi_device *device = root->device;
311 int domain = root->segment; 349 int domain = root->segment;
312 int busnum = root->secondary.start; 350 int busnum = root->secondary.start;
351 LIST_HEAD(resources);
313 struct pci_bus *bus; 352 struct pci_bus *bus;
314 struct pci_sysdata *sd; 353 struct pci_sysdata *sd;
315 int node; 354 int node;
@@ -364,11 +403,15 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
364 memcpy(bus->sysdata, sd, sizeof(*sd)); 403 memcpy(bus->sysdata, sd, sizeof(*sd));
365 kfree(sd); 404 kfree(sd);
366 } else { 405 } else {
367 bus = pci_create_bus(NULL, busnum, &pci_root_ops, sd); 406 get_current_resources(device, busnum, domain, &resources);
368 if (bus) { 407 if (list_empty(&resources))
369 get_current_resources(device, busnum, domain, bus); 408 x86_pci_root_bus_resources(busnum, &resources);
409 bus = pci_create_root_bus(NULL, busnum, &pci_root_ops, sd,
410 &resources);
411 if (bus)
370 bus->subordinate = pci_scan_child_bus(bus); 412 bus->subordinate = pci_scan_child_bus(bus);
371 } 413 else
414 pci_free_resource_list(&resources);
372 } 415 }
373 416
374 /* After the PCI-E bus has been walked and all devices discovered, 417 /* After the PCI-E bus has been walked and all devices discovered,
diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c
index 026e4931d162..0567df3890e1 100644
--- a/arch/x86/pci/amd_bus.c
+++ b/arch/x86/pci/amd_bus.c
@@ -30,34 +30,6 @@ static struct pci_hostbridge_probe pci_probes[] __initdata = {
30 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 }, 30 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
31}; 31};
32 32
33static u64 __initdata fam10h_mmconf_start;
34static u64 __initdata fam10h_mmconf_end;
35static void __init get_pci_mmcfg_amd_fam10h_range(void)
36{
37 u32 address;
38 u64 base, msr;
39 unsigned segn_busn_bits;
40
41 /* assume all cpus from fam10h have mmconf */
42 if (boot_cpu_data.x86 < 0x10)
43 return;
44
45 address = MSR_FAM10H_MMIO_CONF_BASE;
46 rdmsrl(address, msr);
47
48 /* mmconfig is not enable */
49 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
50 return;
51
52 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
53
54 segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
55 FAM10H_MMIO_CONF_BUSRANGE_MASK;
56
57 fam10h_mmconf_start = base;
58 fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
59}
60
61#define RANGE_NUM 16 33#define RANGE_NUM 16
62 34
63/** 35/**
@@ -85,6 +57,9 @@ static int __init early_fill_mp_bus_info(void)
85 u64 val; 57 u64 val;
86 u32 address; 58 u32 address;
87 bool found; 59 bool found;
60 struct resource fam10h_mmconf_res, *fam10h_mmconf;
61 u64 fam10h_mmconf_start;
62 u64 fam10h_mmconf_end;
88 63
89 if (!early_pci_allowed()) 64 if (!early_pci_allowed())
90 return -1; 65 return -1;
@@ -211,12 +186,17 @@ static int __init early_fill_mp_bus_info(void)
211 subtract_range(range, RANGE_NUM, 0, end); 186 subtract_range(range, RANGE_NUM, 0, end);
212 187
213 /* get mmconfig */ 188 /* get mmconfig */
214 get_pci_mmcfg_amd_fam10h_range(); 189 fam10h_mmconf = amd_get_mmconfig_range(&fam10h_mmconf_res);
215 /* need to take out mmconf range */ 190 /* need to take out mmconf range */
216 if (fam10h_mmconf_end) { 191 if (fam10h_mmconf) {
217 printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end); 192 printk(KERN_DEBUG "Fam 10h mmconf %pR\n", fam10h_mmconf);
193 fam10h_mmconf_start = fam10h_mmconf->start;
194 fam10h_mmconf_end = fam10h_mmconf->end;
218 subtract_range(range, RANGE_NUM, fam10h_mmconf_start, 195 subtract_range(range, RANGE_NUM, fam10h_mmconf_start,
219 fam10h_mmconf_end + 1); 196 fam10h_mmconf_end + 1);
197 } else {
198 fam10h_mmconf_start = 0;
199 fam10h_mmconf_end = 0;
220 } 200 }
221 201
222 /* mmio resource */ 202 /* mmio resource */
@@ -403,7 +383,6 @@ static void __init pci_enable_pci_io_ecs(void)
403 ++n; 383 ++n;
404 } 384 }
405 } 385 }
406 pr_info("Extended Config Space enabled on %u nodes\n", n);
407#endif 386#endif
408} 387}
409 388
diff --git a/arch/x86/pci/broadcom_bus.c b/arch/x86/pci/broadcom_bus.c
index ab8269b0da29..f3a7c569a403 100644
--- a/arch/x86/pci/broadcom_bus.c
+++ b/arch/x86/pci/broadcom_bus.c
@@ -15,10 +15,11 @@
15#include <linux/pci.h> 15#include <linux/pci.h>
16#include <linux/init.h> 16#include <linux/init.h>
17#include <asm/pci_x86.h> 17#include <asm/pci_x86.h>
18#include <asm/pci-direct.h>
18 19
19#include "bus_numa.h" 20#include "bus_numa.h"
20 21
21static void __devinit cnb20le_res(struct pci_dev *dev) 22static void __init cnb20le_res(u8 bus, u8 slot, u8 func)
22{ 23{
23 struct pci_root_info *info; 24 struct pci_root_info *info;
24 struct resource res; 25 struct resource res;
@@ -26,21 +27,12 @@ static void __devinit cnb20le_res(struct pci_dev *dev)
26 u8 fbus, lbus; 27 u8 fbus, lbus;
27 int i; 28 int i;
28 29
29#ifdef CONFIG_ACPI
30 /*
31 * We should get host bridge information from ACPI unless the BIOS
32 * doesn't support it.
33 */
34 if (acpi_os_get_root_pointer())
35 return;
36#endif
37
38 info = &pci_root_info[pci_root_num]; 30 info = &pci_root_info[pci_root_num];
39 pci_root_num++; 31 pci_root_num++;
40 32
41 /* read the PCI bus numbers */ 33 /* read the PCI bus numbers */
42 pci_read_config_byte(dev, 0x44, &fbus); 34 fbus = read_pci_config_byte(bus, slot, func, 0x44);
43 pci_read_config_byte(dev, 0x45, &lbus); 35 lbus = read_pci_config_byte(bus, slot, func, 0x45);
44 info->bus_min = fbus; 36 info->bus_min = fbus;
45 info->bus_max = lbus; 37 info->bus_max = lbus;
46 38
@@ -59,8 +51,8 @@ static void __devinit cnb20le_res(struct pci_dev *dev)
59 } 51 }
60 52
61 /* read the non-prefetchable memory window */ 53 /* read the non-prefetchable memory window */
62 pci_read_config_word(dev, 0xc0, &word1); 54 word1 = read_pci_config_16(bus, slot, func, 0xc0);
63 pci_read_config_word(dev, 0xc2, &word2); 55 word2 = read_pci_config_16(bus, slot, func, 0xc2);
64 if (word1 != word2) { 56 if (word1 != word2) {
65 res.start = (word1 << 16) | 0x0000; 57 res.start = (word1 << 16) | 0x0000;
66 res.end = (word2 << 16) | 0xffff; 58 res.end = (word2 << 16) | 0xffff;
@@ -69,8 +61,8 @@ static void __devinit cnb20le_res(struct pci_dev *dev)
69 } 61 }
70 62
71 /* read the prefetchable memory window */ 63 /* read the prefetchable memory window */
72 pci_read_config_word(dev, 0xc4, &word1); 64 word1 = read_pci_config_16(bus, slot, func, 0xc4);
73 pci_read_config_word(dev, 0xc6, &word2); 65 word2 = read_pci_config_16(bus, slot, func, 0xc6);
74 if (word1 != word2) { 66 if (word1 != word2) {
75 res.start = (word1 << 16) | 0x0000; 67 res.start = (word1 << 16) | 0x0000;
76 res.end = (word2 << 16) | 0xffff; 68 res.end = (word2 << 16) | 0xffff;
@@ -79,8 +71,8 @@ static void __devinit cnb20le_res(struct pci_dev *dev)
79 } 71 }
80 72
81 /* read the IO port window */ 73 /* read the IO port window */
82 pci_read_config_word(dev, 0xd0, &word1); 74 word1 = read_pci_config_16(bus, slot, func, 0xd0);
83 pci_read_config_word(dev, 0xd2, &word2); 75 word2 = read_pci_config_16(bus, slot, func, 0xd2);
84 if (word1 != word2) { 76 if (word1 != word2) {
85 res.start = word1; 77 res.start = word1;
86 res.end = word2; 78 res.end = word2;
@@ -92,13 +84,37 @@ static void __devinit cnb20le_res(struct pci_dev *dev)
92 res.start = fbus; 84 res.start = fbus;
93 res.end = lbus; 85 res.end = lbus;
94 res.flags = IORESOURCE_BUS; 86 res.flags = IORESOURCE_BUS;
95 dev_info(&dev->dev, "CNB20LE PCI Host Bridge (domain %04x %pR)\n", 87 printk(KERN_INFO "CNB20LE PCI Host Bridge (domain 0000 %pR)\n", &res);
96 pci_domain_nr(dev->bus), &res);
97 88
98 for (i = 0; i < info->res_num; i++) 89 for (i = 0; i < info->res_num; i++)
99 dev_info(&dev->dev, "host bridge window %pR\n", &info->res[i]); 90 printk(KERN_INFO "host bridge window %pR\n", &info->res[i]);
100} 91}
101 92
102DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE, 93static int __init broadcom_postcore_init(void)
103 cnb20le_res); 94{
95 u8 bus = 0, slot = 0;
96 u32 id;
97 u16 vendor, device;
98
99#ifdef CONFIG_ACPI
100 /*
101 * We should get host bridge information from ACPI unless the BIOS
102 * doesn't support it.
103 */
104 if (acpi_os_get_root_pointer())
105 return 0;
106#endif
107
108 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
109 vendor = id & 0xffff;
110 device = (id >> 16) & 0xffff;
111
112 if (vendor == PCI_VENDOR_ID_SERVERWORKS &&
113 device == PCI_DEVICE_ID_SERVERWORKS_LE) {
114 cnb20le_res(bus, slot, 0);
115 cnb20le_res(bus, slot, 1);
116 }
117 return 0;
118}
104 119
120postcore_initcall(broadcom_postcore_init);
diff --git a/arch/x86/pci/bus_numa.c b/arch/x86/pci/bus_numa.c
index 64a122883896..fd3f65510e9d 100644
--- a/arch/x86/pci/bus_numa.c
+++ b/arch/x86/pci/bus_numa.c
@@ -7,45 +7,50 @@
7int pci_root_num; 7int pci_root_num;
8struct pci_root_info pci_root_info[PCI_ROOT_NR]; 8struct pci_root_info pci_root_info[PCI_ROOT_NR];
9 9
10void x86_pci_root_bus_res_quirks(struct pci_bus *b) 10void x86_pci_root_bus_resources(int bus, struct list_head *resources)
11{ 11{
12 int i; 12 int i;
13 int j; 13 int j;
14 struct pci_root_info *info; 14 struct pci_root_info *info;
15 15
16 /* don't go for it if _CRS is used already */
17 if (b->resource[0] != &ioport_resource ||
18 b->resource[1] != &iomem_resource)
19 return;
20
21 if (!pci_root_num) 16 if (!pci_root_num)
22 return; 17 goto default_resources;
23 18
24 for (i = 0; i < pci_root_num; i++) { 19 for (i = 0; i < pci_root_num; i++) {
25 if (pci_root_info[i].bus_min == b->number) 20 if (pci_root_info[i].bus_min == bus)
26 break; 21 break;
27 } 22 }
28 23
29 if (i == pci_root_num) 24 if (i == pci_root_num)
30 return; 25 goto default_resources;
31 26
32 printk(KERN_DEBUG "PCI: peer root bus %02x res updated from pci conf\n", 27 printk(KERN_DEBUG "PCI: root bus %02x: hardware-probed resources\n",
33 b->number); 28 bus);
34 29
35 pci_bus_remove_resources(b);
36 info = &pci_root_info[i]; 30 info = &pci_root_info[i];
37 for (j = 0; j < info->res_num; j++) { 31 for (j = 0; j < info->res_num; j++) {
38 struct resource *res; 32 struct resource *res;
39 struct resource *root; 33 struct resource *root;
40 34
41 res = &info->res[j]; 35 res = &info->res[j];
42 pci_bus_add_resource(b, res, 0); 36 pci_add_resource(resources, res);
43 if (res->flags & IORESOURCE_IO) 37 if (res->flags & IORESOURCE_IO)
44 root = &ioport_resource; 38 root = &ioport_resource;
45 else 39 else
46 root = &iomem_resource; 40 root = &iomem_resource;
47 insert_resource(root, res); 41 insert_resource(root, res);
48 } 42 }
43 return;
44
45default_resources:
46 /*
47 * We don't have any host bridge aperture information from the
48 * "native host bridge drivers," e.g., amd_bus or broadcom_bus,
49 * so fall back to the defaults historically used by pci_create_bus().
50 */
51 printk(KERN_DEBUG "PCI: root bus %02x: using default resources\n", bus);
52 pci_add_resource(resources, &ioport_resource);
53 pci_add_resource(resources, &iomem_resource);
49} 54}
50 55
51void __devinit update_res(struct pci_root_info *info, resource_size_t start, 56void __devinit update_res(struct pci_root_info *info, resource_size_t start,
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index 7962ccb4d9b2..323481e06ef8 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -164,9 +164,6 @@ void __devinit pcibios_fixup_bus(struct pci_bus *b)
164{ 164{
165 struct pci_dev *dev; 165 struct pci_dev *dev;
166 166
167 /* root bus? */
168 if (!b->parent)
169 x86_pci_root_bus_res_quirks(b);
170 pci_read_bridge_bases(b); 167 pci_read_bridge_bases(b);
171 list_for_each_entry(dev, &b->devices, bus_list) 168 list_for_each_entry(dev, &b->devices, bus_list)
172 pcibios_fixup_device_resources(dev); 169 pcibios_fixup_device_resources(dev);
@@ -433,6 +430,7 @@ void __init dmi_check_pciprobe(void)
433 430
434struct pci_bus * __devinit pcibios_scan_root(int busnum) 431struct pci_bus * __devinit pcibios_scan_root(int busnum)
435{ 432{
433 LIST_HEAD(resources);
436 struct pci_bus *bus = NULL; 434 struct pci_bus *bus = NULL;
437 struct pci_sysdata *sd; 435 struct pci_sysdata *sd;
438 436
@@ -456,9 +454,12 @@ struct pci_bus * __devinit pcibios_scan_root(int busnum)
456 sd->node = get_mp_bus_to_node(busnum); 454 sd->node = get_mp_bus_to_node(busnum);
457 455
458 printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum); 456 printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum);
459 bus = pci_scan_bus_parented(NULL, busnum, &pci_root_ops, sd); 457 x86_pci_root_bus_resources(busnum, &resources);
460 if (!bus) 458 bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, sd, &resources);
459 if (!bus) {
460 pci_free_resource_list(&resources);
461 kfree(sd); 461 kfree(sd);
462 }
462 463
463 return bus; 464 return bus;
464} 465}
@@ -639,6 +640,7 @@ int pci_ext_cfg_avail(struct pci_dev *dev)
639 640
640struct pci_bus * __devinit pci_scan_bus_on_node(int busno, struct pci_ops *ops, int node) 641struct pci_bus * __devinit pci_scan_bus_on_node(int busno, struct pci_ops *ops, int node)
641{ 642{
643 LIST_HEAD(resources);
642 struct pci_bus *bus = NULL; 644 struct pci_bus *bus = NULL;
643 struct pci_sysdata *sd; 645 struct pci_sysdata *sd;
644 646
@@ -653,9 +655,12 @@ struct pci_bus * __devinit pci_scan_bus_on_node(int busno, struct pci_ops *ops,
653 return NULL; 655 return NULL;
654 } 656 }
655 sd->node = node; 657 sd->node = node;
656 bus = pci_scan_bus(busno, ops, sd); 658 x86_pci_root_bus_resources(busno, &resources);
657 if (!bus) 659 bus = pci_scan_root_bus(NULL, busno, ops, sd, &resources);
660 if (!bus) {
661 pci_free_resource_list(&resources);
658 kfree(sd); 662 kfree(sd);
663 }
659 664
660 return bus; 665 return bus;
661} 666}
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index 794b092d01ae..91821a1a0c3a 100644
--- a/arch/x86/pci/i386.c
+++ b/arch/x86/pci/i386.c
@@ -254,26 +254,6 @@ void __init pcibios_resource_survey(void)
254 */ 254 */
255fs_initcall(pcibios_assign_resources); 255fs_initcall(pcibios_assign_resources);
256 256
257/*
258 * If we set up a device for bus mastering, we need to check the latency
259 * timer as certain crappy BIOSes forget to set it properly.
260 */
261unsigned int pcibios_max_latency = 255;
262
263void pcibios_set_master(struct pci_dev *dev)
264{
265 u8 lat;
266 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
267 if (lat < 16)
268 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
269 else if (lat > pcibios_max_latency)
270 lat = pcibios_max_latency;
271 else
272 return;
273 dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
274 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
275}
276
277static const struct vm_operations_struct pci_mmap_ops = { 257static const struct vm_operations_struct pci_mmap_ops = {
278 .access = generic_access_phys, 258 .access = generic_access_phys,
279}; 259};
diff --git a/arch/x86/pci/legacy.c b/arch/x86/pci/legacy.c
index 2c2aeabc2609..a1df191129d3 100644
--- a/arch/x86/pci/legacy.c
+++ b/arch/x86/pci/legacy.c
@@ -31,9 +31,6 @@ int __init pci_legacy_init(void)
31 31
32 printk("PCI: Probing PCI hardware\n"); 32 printk("PCI: Probing PCI hardware\n");
33 pci_root_bus = pcibios_scan_root(0); 33 pci_root_bus = pcibios_scan_root(0);
34 if (pci_root_bus)
35 pci_bus_add_devices(pci_root_bus);
36
37 return 0; 34 return 0;
38} 35}
39 36
diff --git a/arch/x86/pci/numaq_32.c b/arch/x86/pci/numaq_32.c
index 51abf02f9226..83e125b95ca6 100644
--- a/arch/x86/pci/numaq_32.c
+++ b/arch/x86/pci/numaq_32.c
@@ -153,8 +153,6 @@ int __init pci_numaq_init(void)
153 raw_pci_ops = &pci_direct_conf1_mq; 153 raw_pci_ops = &pci_direct_conf1_mq;
154 154
155 pci_root_bus = pcibios_scan_root(0); 155 pci_root_bus = pcibios_scan_root(0);
156 if (pci_root_bus)
157 pci_bus_add_devices(pci_root_bus);
158 if (num_online_nodes() > 1) 156 if (num_online_nodes() > 1)
159 for_each_online_node(quad) { 157 for_each_online_node(quad) {
160 if (quad == 0) 158 if (quad == 0)
diff --git a/arch/x86/platform/mrst/Makefile b/arch/x86/platform/mrst/Makefile
index 1ea38775a6d3..7baed5135e0f 100644
--- a/arch/x86/platform/mrst/Makefile
+++ b/arch/x86/platform/mrst/Makefile
@@ -1,4 +1,4 @@
1obj-$(CONFIG_X86_MRST) += mrst.o 1obj-$(CONFIG_X86_INTEL_MID) += mrst.o
2obj-$(CONFIG_X86_MRST) += vrtc.o 2obj-$(CONFIG_X86_INTEL_MID) += vrtc.o
3obj-$(CONFIG_EARLY_PRINTK_MRST) += early_printk_mrst.o 3obj-$(CONFIG_EARLY_PRINTK_INTEL_MID) += early_printk_mrst.o
4obj-$(CONFIG_X86_MRST) += pmu.o 4obj-$(CONFIG_X86_MRST) += pmu.o
diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c
index ad4ec1cb097e..475e2cd0f3c3 100644
--- a/arch/x86/platform/mrst/mrst.c
+++ b/arch/x86/platform/mrst/mrst.c
@@ -848,8 +848,7 @@ static void __init sfi_handle_ipc_dev(struct sfi_device_table_entry *entry)
848 if (mrst_has_msic()) 848 if (mrst_has_msic())
849 return; 849 return;
850 850
851 /* ID as IRQ is a hack that will go away */ 851 pdev = platform_device_alloc(entry->name, 0);
852 pdev = platform_device_alloc(entry->name, entry->irq);
853 if (pdev == NULL) { 852 if (pdev == NULL) {
854 pr_err("out of memory for SFI platform device '%s'.\n", 853 pr_err("out of memory for SFI platform device '%s'.\n",
855 entry->name); 854 entry->name);
@@ -1030,6 +1029,7 @@ static int __init pb_keys_init(void)
1030 num = sizeof(gpio_button) / sizeof(struct gpio_keys_button); 1029 num = sizeof(gpio_button) / sizeof(struct gpio_keys_button);
1031 for (i = 0; i < num; i++) { 1030 for (i = 0; i < num; i++) {
1032 gb[i].gpio = get_gpio_by_name(gb[i].desc); 1031 gb[i].gpio = get_gpio_by_name(gb[i].desc);
1032 pr_debug("info[%2d]: name = %s, gpio = %d\n", i, gb[i].desc, gb[i].gpio);
1033 if (gb[i].gpio == -1) 1033 if (gb[i].gpio == -1)
1034 continue; 1034 continue;
1035 1035
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index c346ccdce0df..8a3f8351f438 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -9,6 +9,7 @@ config XTENSA
9 select HAVE_IDE 9 select HAVE_IDE
10 select HAVE_GENERIC_HARDIRQS 10 select HAVE_GENERIC_HARDIRQS
11 select GENERIC_IRQ_SHOW 11 select GENERIC_IRQ_SHOW
12 select GENERIC_CPU_DEVICES
12 help 13 help
13 Xtensa processors are 32-bit RISC machines designed by Tensilica 14 Xtensa processors are 32-bit RISC machines designed by Tensilica
14 primarily for embedded systems. These processors are both 15 primarily for embedded systems. These processors are both
diff --git a/arch/xtensa/include/asm/pci.h b/arch/xtensa/include/asm/pci.h
index 4609b0f15f1f..05244f07dd31 100644
--- a/arch/xtensa/include/asm/pci.h
+++ b/arch/xtensa/include/asm/pci.h
@@ -22,11 +22,6 @@
22 22
23extern struct pci_controller* pcibios_alloc_controller(void); 23extern struct pci_controller* pcibios_alloc_controller(void);
24 24
25static inline void pcibios_set_master(struct pci_dev *dev)
26{
27 /* No special bus mastering setup handling */
28}
29
30static inline void pcibios_penalize_isa_irq(int irq) 25static inline void pcibios_penalize_isa_irq(int irq)
31{ 26{
32 /* We don't do dynamic PCI IRQ allocation */ 27 /* We don't do dynamic PCI IRQ allocation */
diff --git a/arch/xtensa/kernel/pci.c b/arch/xtensa/kernel/pci.c
index cd1026931203..61045c192e88 100644
--- a/arch/xtensa/kernel/pci.c
+++ b/arch/xtensa/kernel/pci.c
@@ -134,9 +134,46 @@ struct pci_controller * __init pcibios_alloc_controller(void)
134 return pci_ctrl; 134 return pci_ctrl;
135} 135}
136 136
137static void __init pci_controller_apertures(struct pci_controller *pci_ctrl,
138 struct list_head *resources)
139{
140 struct resource *res;
141 unsigned long io_offset;
142 int i;
143
144 io_offset = (unsigned long)pci_ctrl->io_space.base;
145 res = &pci_ctrl->io_resource;
146 if (!res->flags) {
147 if (io_offset)
148 printk (KERN_ERR "I/O resource not set for host"
149 " bridge %d\n", pci_ctrl->index);
150 res->start = 0;
151 res->end = IO_SPACE_LIMIT;
152 res->flags = IORESOURCE_IO;
153 }
154 res->start += io_offset;
155 res->end += io_offset;
156 pci_add_resource(resources, res);
157
158 for (i = 0; i < 3; i++) {
159 res = &pci_ctrl->mem_resources[i];
160 if (!res->flags) {
161 if (i > 0)
162 continue;
163 printk(KERN_ERR "Memory resource not set for "
164 "host bridge %d\n", pci_ctrl->index);
165 res->start = 0;
166 res->end = ~0U;
167 res->flags = IORESOURCE_MEM;
168 }
169 pci_add_resource(resources, res);
170 }
171}
172
137static int __init pcibios_init(void) 173static int __init pcibios_init(void)
138{ 174{
139 struct pci_controller *pci_ctrl; 175 struct pci_controller *pci_ctrl;
176 struct list_head resources;
140 struct pci_bus *bus; 177 struct pci_bus *bus;
141 int next_busno = 0, i; 178 int next_busno = 0, i;
142 179
@@ -145,19 +182,10 @@ static int __init pcibios_init(void)
145 /* Scan all of the recorded PCI controllers. */ 182 /* Scan all of the recorded PCI controllers. */
146 for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) { 183 for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) {
147 pci_ctrl->last_busno = 0xff; 184 pci_ctrl->last_busno = 0xff;
148 bus = pci_scan_bus(pci_ctrl->first_busno, pci_ctrl->ops, 185 INIT_LIST_HEAD(&resources);
149 pci_ctrl); 186 pci_controller_apertures(pci_ctrl, &resources);
150 if (pci_ctrl->io_resource.flags) { 187 bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno,
151 unsigned long offs; 188 pci_ctrl->ops, pci_ctrl, &resources);
152
153 offs = (unsigned long)pci_ctrl->io_space.base;
154 pci_ctrl->io_resource.start += offs;
155 pci_ctrl->io_resource.end += offs;
156 bus->resource[0] = &pci_ctrl->io_resource;
157 }
158 for (i = 0; i < 3; ++i)
159 if (pci_ctrl->mem_resources[i].flags)
160 bus->resource[i+1] =&pci_ctrl->mem_resources[i];
161 pci_ctrl->bus = bus; 189 pci_ctrl->bus = bus;
162 pci_ctrl->last_busno = bus->subordinate; 190 pci_ctrl->last_busno = bus->subordinate;
163 if (next_busno <= pci_ctrl->last_busno) 191 if (next_busno <= pci_ctrl->last_busno)
@@ -178,36 +206,7 @@ void __init pcibios_fixup_bus(struct pci_bus *bus)
178 int i; 206 int i;
179 207
180 io_offset = (unsigned long)pci_ctrl->io_space.base; 208 io_offset = (unsigned long)pci_ctrl->io_space.base;
181 if (bus->parent == NULL) { 209 if (bus->parent) {
182 /* this is a host bridge - fill in its resources */
183 pci_ctrl->bus = bus;
184
185 bus->resource[0] = res = &pci_ctrl->io_resource;
186 if (!res->flags) {
187 if (io_offset)
188 printk (KERN_ERR "I/O resource not set for host"
189 " bridge %d\n", pci_ctrl->index);
190 res->start = 0;
191 res->end = IO_SPACE_LIMIT;
192 res->flags = IORESOURCE_IO;
193 }
194 res->start += io_offset;
195 res->end += io_offset;
196
197 for (i = 0; i < 3; i++) {
198 res = &pci_ctrl->mem_resources[i];
199 if (!res->flags) {
200 if (i > 0)
201 continue;
202 printk(KERN_ERR "Memory resource not set for "
203 "host bridge %d\n", pci_ctrl->index);
204 res->start = 0;
205 res->end = ~0U;
206 res->flags = IORESOURCE_MEM;
207 }
208 bus->resource[i+1] = res;
209 }
210 } else {
211 /* This is a subordinate bridge */ 210 /* This is a subordinate bridge */
212 pci_read_bridge_bases(bus); 211 pci_read_bridge_bases(bus);
213 212
@@ -227,6 +226,11 @@ char __init *pcibios_setup(char *str)
227 return str; 226 return str;
228} 227}
229 228
229void pcibios_set_master(struct pci_dev *dev)
230{
231 /* No special bus mastering setup handling */
232}
233
230/* the next one is stolen from the alpha port... */ 234/* the next one is stolen from the alpha port... */
231 235
232void __init 236void __init
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-15 20:15:48 -0500