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-rw-r--r--arch/arc/Kconfig6
-rw-r--r--arch/arc/Makefile17
-rw-r--r--arch/arc/boot/dts/angel4.dts5
-rw-r--r--arch/arc/boot/dts/nsimosci.dts7
-rw-r--r--arch/arc/configs/fpga_defconfig1
-rw-r--r--arch/arc/configs/fpga_noramfs_defconfig1
-rw-r--r--arch/arc/configs/nsimosci_defconfig1
-rw-r--r--arch/arc/include/asm/arcregs.h89
-rw-r--r--arch/arc/include/asm/atomic.h4
-rw-r--r--arch/arc/include/asm/bitops.h4
-rw-r--r--arch/arc/include/asm/bug.h7
-rw-r--r--arch/arc/include/asm/cache.h2
-rw-r--r--arch/arc/include/asm/current.h4
-rw-r--r--arch/arc/include/asm/irqflags.h4
-rw-r--r--arch/arc/include/asm/kgdb.h32
-rw-r--r--arch/arc/include/asm/processor.h13
-rw-r--r--arch/arc/include/asm/setup.h1
-rw-r--r--arch/arc/include/asm/smp.h10
-rw-r--r--arch/arc/include/asm/string.h3
-rw-r--r--arch/arc/include/asm/syscalls.h4
-rw-r--r--arch/arc/include/asm/thread_info.h4
-rw-r--r--arch/arc/include/asm/unaligned.h2
-rw-r--r--arch/arc/kernel/Makefile2
-rw-r--r--arch/arc/kernel/disasm.c4
-rw-r--r--arch/arc/kernel/head.S10
-rw-r--r--arch/arc/kernel/kgdb.c5
-rw-r--r--arch/arc/kernel/perf_event.c22
-rw-r--r--arch/arc/kernel/setup.c272
-rw-r--r--arch/arc/kernel/smp.c2
-rw-r--r--arch/arc/mm/cache_arc700.c14
-rw-r--r--arch/arc/mm/tlb.c8
-rw-r--r--arch/arc/plat-arcfpga/Kconfig13
-rw-r--r--arch/arc/plat-arcfpga/include/plat/irq.h27
-rw-r--r--arch/arc/plat-arcfpga/include/plat/memmap.h29
-rw-r--r--arch/arc/plat-arcfpga/platform.c61
-rw-r--r--arch/arc/plat-arcfpga/smp.c3
-rw-r--r--arch/arc/plat-tb10x/Kconfig1
-rw-r--r--arch/arc/plat-tb10x/tb10x.c13
-rw-r--r--arch/arm/boot/dts/Makefile41
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts4
-rw-r--r--arch/arm/boot/dts/am335x-igep0033.dtsi4
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi7
-rw-r--r--arch/arm/boot/dts/am4372.dtsi1
-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts4
-rw-r--r--arch/arm/boot/dts/am57xx-beagle-x15.dts405
-rw-r--r--arch/arm/boot/dts/arm-realview-pb1176.dts412
-rw-r--r--arch/arm/boot/dts/armada-370-netgear-rn102.dts17
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi1
-rw-r--r--arch/arm/boot/dts/armada-375.dtsi12
-rw-r--r--arch/arm/boot/dts/armada-xp-axpwifiap.dts58
-rw-r--r--arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts73
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi15
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi15
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi15
-rw-r--r--arch/arm/boot/dts/armada-xp-netgear-rn2120.dts166
-rw-r--r--arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts14
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi38
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi24
-rw-r--r--arch/arm/boot/dts/at91sam9x25.dtsi1
-rw-r--r--arch/arm/boot/dts/at91sam9x35.dtsi1
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi12
-rw-r--r--arch/arm/boot/dts/at91sam9x5_can.dtsi50
-rw-r--r--arch/arm/boot/dts/at91sam9x5_usart3.dtsi3
-rw-r--r--arch/arm/boot/dts/bcm-cygnus-clock.dtsi91
-rw-r--r--arch/arm/boot/dts/bcm-cygnus.dtsi140
-rw-r--r--arch/arm/boot/dts/bcm2835-rpi-b-plus.dts30
-rw-r--r--arch/arm/boot/dts/bcm2835-rpi-b.dts46
-rw-r--r--arch/arm/boot/dts/bcm2835-rpi.dtsi51
-rw-r--r--arch/arm/boot/dts/bcm911360_entphn.dts53
-rw-r--r--arch/arm/boot/dts/bcm911360k.dts53
-rw-r--r--arch/arm/boot/dts/bcm958300k.dts53
-rw-r--r--arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts16
-rw-r--r--arch/arm/boot/dts/berlin2.dtsi110
-rw-r--r--arch/arm/boot/dts/berlin2cd-google-chromecast.dts30
-rw-r--r--arch/arm/boot/dts/berlin2cd.dtsi82
-rw-r--r--arch/arm/boot/dts/berlin2q-marvell-dmp.dts61
-rw-r--r--arch/arm/boot/dts/berlin2q.dtsi96
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts111
-rw-r--r--arch/arm/boot/dts/dra7.dtsi167
-rw-r--r--arch/arm/boot/dts/dra72-evm.dts296
-rw-r--r--arch/arm/boot/dts/dra74x.dtsi22
-rw-r--r--arch/arm/boot/dts/emev2-kzm9d.dts63
-rw-r--r--arch/arm/boot/dts/emev2.dtsi12
-rw-r--r--arch/arm/boot/dts/hisi-x5hd2-dkb.dts33
-rw-r--r--arch/arm/boot/dts/hisi-x5hd2.dtsi390
-rw-r--r--arch/arm/boot/dts/imx28-evk.dts1
-rw-r--r--arch/arm/boot/dts/k2e-evm.dts12
-rw-r--r--arch/arm/boot/dts/k2e.dtsi45
-rw-r--r--arch/arm/boot/dts/k2l-evm.dts12
-rw-r--r--arch/arm/boot/dts/keystone.dtsi45
-rw-r--r--arch/arm/boot/dts/kirkwood-dir665.dts278
-rw-r--r--arch/arm/boot/dts/meson.dtsi37
-rw-r--r--arch/arm/boot/dts/meson6-atv1200.dts2
-rw-r--r--arch/arm/boot/dts/meson6.dtsi2
-rw-r--r--arch/arm/boot/dts/meson8.dtsi92
-rw-r--r--arch/arm/boot/dts/mt6592-evb.dts26
-rw-r--r--arch/arm/boot/dts/mt6592.dtsi98
-rw-r--r--arch/arm/boot/dts/mt8127-moose.dts25
-rw-r--r--arch/arm/boot/dts/mt8127.dtsi94
-rw-r--r--arch/arm/boot/dts/mt8135-evbp1.dts25
-rw-r--r--arch/arm/boot/dts/mt8135.dtsi116
-rw-r--r--arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi41
-rw-r--r--arch/arm/boot/dts/omap-zoom-common.dtsi62
-rw-r--r--arch/arm/boot/dts/omap2420-n8x0-common.dtsi4
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi1
-rw-r--r--arch/arm/boot/dts/omap2430-sdp.dts28
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi1
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3517.dts11
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3530.dts11
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3730.dts24
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3x.dtsi39
-rw-r--r--arch/arm/boot/dts/omap3-devkit8000.dts4
-rw-r--r--arch/arm/boot/dts/omap3-evm-37xx.dts5
-rw-r--r--arch/arm/boot/dts/omap3-gta04.dtsi86
-rw-r--r--arch/arm/boot/dts/omap3-igep.dtsi103
-rw-r--r--arch/arm/boot/dts/omap3-igep0020-common.dtsi246
-rw-r--r--arch/arm/boot/dts/omap3-igep0020-rev-f.dts45
-rw-r--r--arch/arm/boot/dts/omap3-igep0020.dts285
-rw-r--r--arch/arm/boot/dts/omap3-igep0030-common.dtsi60
-rw-r--r--arch/arm/boot/dts/omap3-igep0030-rev-g.dts67
-rw-r--r--arch/arm/boot/dts/omap3-igep0030.dts123
-rw-r--r--arch/arm/boot/dts/omap3-ldp.dts3
-rw-r--r--arch/arm/boot/dts/omap3-lilly-a83x.dtsi2
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts37
-rw-r--r--arch/arm/boot/dts/omap3-n950-n9.dtsi4
-rw-r--r--arch/arm/boot/dts/omap3-sb-t35.dtsi90
-rw-r--r--arch/arm/boot/dts/omap3-sbc-t3517.dts14
-rw-r--r--arch/arm/boot/dts/omap3-sbc-t3530.dts14
-rw-r--r--arch/arm/boot/dts/omap3-sbc-t3730.dts14
-rw-r--r--arch/arm/boot/dts/omap3-tao3530.dtsi2
-rw-r--r--arch/arm/boot/dts/omap3.dtsi1
-rw-r--r--arch/arm/boot/dts/omap3430-sdp.dts8
-rw-r--r--arch/arm/boot/dts/omap4.dtsi1
-rw-r--r--arch/arm/boot/dts/omap5.dtsi1
-rw-r--r--arch/arm/boot/dts/r7s72100-genmai.dts3
-rw-r--r--arch/arm/boot/dts/r7s72100.dtsi202
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts7
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi263
-rw-r--r--arch/arm/boot/dts/r8a7740-armadillo800eva.dts7
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi44
-rw-r--r--arch/arm/boot/dts/r8a7778-bockw-reference.dts7
-rw-r--r--arch/arm/boot/dts/r8a7778.dtsi42
-rw-r--r--arch/arm/boot/dts/r8a7779-marzen.dts84
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi34
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts185
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi279
-rw-r--r--arch/arm/boot/dts/r8a7791-henninger.dts12
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts116
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi255
-rw-r--r--arch/arm/boot/dts/r8a7794-alt.dts3
-rw-r--r--arch/arm/boot/dts/r8a7794.dtsi29
-rw-r--r--arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi41
-rw-r--r--arch/arm/boot/dts/rk3066a-bqcurie2.dts4
-rw-r--r--arch/arm/boot/dts/rk3066a-marsboard.dts192
-rw-r--r--arch/arm/boot/dts/rk3066a.dtsi115
-rw-r--r--arch/arm/boot/dts/rk3188-radxarock.dts18
-rw-r--r--arch/arm/boot/dts/rk3188.dtsi45
-rw-r--r--arch/arm/boot/dts/rk3288-evb-rk808.dts6
-rw-r--r--arch/arm/boot/dts/rk3288.dtsi70
-rw-r--r--arch/arm/boot/dts/rk3xxx.dtsi8
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g-reference.dts9
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi10
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi39
-rw-r--r--arch/arm/boot/dts/socfpga_arria10.dtsi374
-rwxr-xr-xarch/arm/boot/dts/socfpga_arria10_socdk.dts48
-rw-r--r--arch/arm/boot/dts/socfpga_arria5.dtsi2
-rw-r--r--arch/arm/boot/dts/socfpga_arria5_socdk.dts12
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5.dtsi4
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_socdk.dts15
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_sockit.dts12
-rw-r--r--arch/arm/boot/dts/ste-nomadik-nhk15.dts151
-rw-r--r--arch/arm/boot/dts/ste-nomadik-s8815.dts56
-rw-r--r--arch/arm/boot/dts/ste-nomadik-stn8815.dtsi45
-rw-r--r--arch/arm/boot/dts/stih407-b2120.dts55
-rw-r--r--arch/arm/boot/dts/stih407-clock.dtsi293
-rw-r--r--arch/arm/boot/dts/stih407-family.dtsi (renamed from arch/arm/boot/dts/stih407.dtsi)35
-rw-r--r--arch/arm/boot/dts/stih410-b2120.dts29
-rw-r--r--arch/arm/boot/dts/stih410-clock.dtsi338
-rw-r--r--arch/arm/boot/dts/stih410-pinctrl.dtsi34
-rw-r--r--arch/arm/boot/dts/stih410.dtsi14
-rw-r--r--arch/arm/boot/dts/stih415-pinctrl.dtsi361
-rw-r--r--arch/arm/boot/dts/stih415.dtsi12
-rw-r--r--arch/arm/boot/dts/stih416-b2020.dts22
-rw-r--r--arch/arm/boot/dts/stih416-b2020e.dts26
-rw-r--r--arch/arm/boot/dts/stih416-pinctrl.dtsi415
-rw-r--r--arch/arm/boot/dts/stih416.dtsi209
-rw-r--r--arch/arm/boot/dts/stih41x-b2000.dtsi6
-rw-r--r--arch/arm/boot/dts/stih41x-b2020.dtsi10
-rw-r--r--arch/arm/boot/dts/stih41x-b2020x.dtsi4
-rw-r--r--arch/arm/boot/dts/stihxxx-b2120.dtsi59
-rw-r--r--arch/arm/boot/dts/sun4i-a10-a1000.dts46
-rw-r--r--arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts46
-rw-r--r--arch/arm/boot/dts/sun4i-a10-cubieboard.dts46
-rw-r--r--arch/arm/boot/dts/sun4i-a10-hackberry.dts46
-rw-r--r--arch/arm/boot/dts/sun4i-a10-inet97fv2.dts46
-rw-r--r--arch/arm/boot/dts/sun4i-a10-mini-xplus.dts46
-rw-r--r--arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts46
-rw-r--r--arch/arm/boot/dts/sun4i-a10-pcduino.dts46
-rw-r--r--arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts46
-rw-r--r--arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts46
-rw-r--r--arch/arm/boot/dts/sun5i-a13-hsg-h702.dts6
-rw-r--r--arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts48
-rw-r--r--arch/arm/boot/dts/sun5i-a13-olinuxino.dts46
-rw-r--r--arch/arm/boot/dts/sun6i-a31-app4-evb1.dts46
-rw-r--r--arch/arm/boot/dts/sun6i-a31-colombus.dts46
-rw-r--r--arch/arm/boot/dts/sun6i-a31-hummingbird.dts46
-rw-r--r--arch/arm/boot/dts/sun6i-a31-m9.dts103
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi36
-rw-r--r--arch/arm/boot/dts/sun7i-a20-bananapi.dts214
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubietruck.dts14
-rw-r--r--arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts46
-rw-r--r--arch/arm/boot/dts/sun7i-a20-m3.dts168
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts46
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts228
-rw-r--r--arch/arm/boot/dts/sun7i-a20-pcduino3.dts46
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi31
-rw-r--r--arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts46
-rw-r--r--arch/arm/boot/dts/sun8i-a23.dtsi6
-rw-r--r--arch/arm/boot/dts/sun9i-a80-optimus.dts119
-rw-r--r--arch/arm/boot/dts/sun9i-a80.dtsi514
-rw-r--r--arch/arm/boot/dts/sunxi-common-regulators.dtsi66
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi2
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi24
-rw-r--r--arch/arm/configs/multi_v7_defconfig2
-rw-r--r--arch/arm/configs/nhk8815_defconfig11
-rw-r--r--arch/arm/configs/sunxi_defconfig1
-rw-r--r--arch/arm/include/uapi/asm/unistd.h1
-rw-r--r--arch/arm/kernel/asm-offsets.c12
-rw-r--r--arch/arm/kernel/calls.S1
-rw-r--r--arch/arm/mach-highbank/highbank.c2
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c14
-rw-r--r--arch/arm/mach-mediatek/mediatek.c3
-rw-r--r--arch/arm/mach-nomadik/cpu-8815.c1
-rw-r--r--arch/arm/mach-omap2/pdata-quirks.c39
-rw-r--r--arch/arm/mach-realview/Kconfig13
-rw-r--r--arch/arm/mach-realview/Makefile1
-rw-r--r--arch/arm/mach-realview/realview-dt.c32
-rw-r--r--arch/arm/mach-shmobile/board-ape6evm-reference.c5
-rw-r--r--arch/arm/mach-shmobile/board-ape6evm.c4
-rw-r--r--arch/arm/mach-shmobile/board-armadillo800eva.c5
-rw-r--r--arch/arm/mach-shmobile/board-bockw-reference.c4
-rw-r--r--arch/arm/mach-shmobile/board-bockw.c4
-rw-r--r--arch/arm/mach-shmobile/board-koelsch-reference.c77
-rw-r--r--arch/arm/mach-shmobile/board-koelsch.c4
-rw-r--r--arch/arm/mach-shmobile/board-kzm9g-reference.c4
-rw-r--r--arch/arm/mach-shmobile/board-kzm9g.c4
-rw-r--r--arch/arm/mach-shmobile/board-lager-reference.c84
-rw-r--r--arch/arm/mach-shmobile/board-lager.c4
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c4
-rw-r--r--arch/arm/mach-shmobile/board-marzen-reference.c4
-rw-r--r--arch/arm/mach-shmobile/board-marzen.c4
-rw-r--r--arch/arm/mach-shmobile/clock-r8a73a4.c4
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7740.c4
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7778.c4
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7779.c4
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c4
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7791.c4
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c4
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c4
-rw-r--r--arch/arm/mach-shmobile/clock.c4
-rw-r--r--arch/arm/mach-shmobile/console.c4
-rw-r--r--arch/arm/mach-shmobile/headsmp-scu.S5
-rw-r--r--arch/arm/mach-shmobile/intc-sh7372.c4
-rw-r--r--arch/arm/mach-shmobile/intc-sh73a0.c4
-rw-r--r--arch/arm/mach-shmobile/r8a73a4.h1
-rw-r--r--arch/arm/mach-shmobile/r8a7740.h4
-rw-r--r--arch/arm/mach-shmobile/r8a7778.h4
-rw-r--r--arch/arm/mach-shmobile/setup-emev2.c4
-rw-r--r--arch/arm/mach-shmobile/setup-r7s72100.c4
-rw-r--r--arch/arm/mach-shmobile/setup-r8a73a4.c13
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c4
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7778.c7
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c4
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7790.c4
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7791.c4
-rw-r--r--arch/arm/mach-shmobile/setup-rcar-gen2.c4
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c4
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c4
-rw-r--r--arch/arm/mach-shmobile/sleep-sh7372.S5
-rw-r--r--arch/arm/mach-shmobile/smp-emev2.c4
-rw-r--r--arch/arm/mach-shmobile/smp-r8a7779.c4
-rw-r--r--arch/arm/mach-shmobile/smp-sh73a0.c4
-rw-r--r--arch/arm/mach-shmobile/timer.c5
-rw-r--r--arch/arm/mach-socfpga/core.h2
-rw-r--r--arch/arm/mach-socfpga/headsmp.S25
-rw-r--r--arch/arm/mach-socfpga/platsmp.c4
-rw-r--r--arch/arm/mach-socfpga/socfpga.c4
-rw-r--r--arch/arm/mach-sti/Kconfig10
-rw-r--r--arch/arm/mm/cache-l2x0.c26
-rw-r--r--arch/arm/mm/dma-mapping.c1
-rw-r--r--arch/arm/mm/highmem.c3
-rw-r--r--arch/arm/mm/init.c8
-rw-r--r--arch/arm64/Kconfig3
-rw-r--r--arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi35
-rw-r--r--arch/arm64/configs/defconfig2
-rw-r--r--arch/arm64/include/asm/compat.h4
-rw-r--r--arch/arm64/include/asm/elf.h4
-rw-r--r--arch/arm64/include/asm/irq_work.h11
-rw-r--r--arch/arm64/kernel/efi.c44
-rw-r--r--arch/arm64/kernel/process.c5
-rw-r--r--arch/arm64/mm/ioremap.c4
-rw-r--r--arch/arm64/mm/mmu.c12
-rw-r--r--arch/arm64/mm/pgd.c18
-rw-r--r--arch/arm64/net/bpf_jit.h8
-rw-r--r--arch/arm64/net/bpf_jit_comp.c84
-rw-r--r--arch/ia64/kernel/efi.c6
-rw-r--r--arch/microblaze/Kconfig4
-rw-r--r--arch/microblaze/include/asm/unistd.h2
-rw-r--r--arch/microblaze/include/uapi/asm/unistd.h1
-rw-r--r--arch/microblaze/kernel/syscall_table.S1
-rw-r--r--arch/microblaze/pci/pci-common.c9
-rw-r--r--arch/mips/Kconfig1
-rw-r--r--arch/mips/ath79/mach-db120.c2
-rw-r--r--arch/mips/cavium-octeon/setup.c9
-rw-r--r--arch/mips/include/asm/cop2.h8
-rw-r--r--arch/mips/include/asm/ftrace.h4
-rw-r--r--arch/mips/include/asm/idle.h7
-rw-r--r--arch/mips/include/uapi/asm/ptrace.h2
-rw-r--r--arch/mips/kernel/idle.c3
-rw-r--r--arch/mips/lasat/Kconfig2
-rw-r--r--arch/mips/loongson/lemote-2f/clock.c5
-rw-r--r--arch/mips/math-emu/cp1emu.c4
-rw-r--r--arch/mips/mm/tlbex.c6
-rw-r--r--arch/mips/mti-malta/Makefile3
-rw-r--r--arch/mips/mti-sead3/Makefile1
-rw-r--r--arch/mips/mti-sead3/sead3-i2c.c8
-rw-r--r--arch/mips/mti-sead3/sead3-pic32-bus.c102
-rw-r--r--arch/mips/mti-sead3/sead3-pic32-i2c-drv.c423
-rw-r--r--arch/mips/pci/pci-lantiq.c7
-rw-r--r--arch/mips/pmcs-msp71xx/msp_irq.c1
-rw-r--r--arch/mips/pmcs-msp71xx/msp_irq_cic.c4
-rw-r--r--arch/mips/sibyte/Makefile1
-rw-r--r--arch/powerpc/configs/pseries_le_defconfig7
-rw-r--r--arch/powerpc/include/asm/eeh.h3
-rw-r--r--arch/powerpc/include/asm/hugetlb.h2
-rw-r--r--arch/powerpc/include/asm/perf_event.h2
-rw-r--r--arch/powerpc/include/asm/reg.h3
-rw-r--r--arch/powerpc/include/asm/syscall.h2
-rw-r--r--arch/powerpc/include/asm/systbl.h1
-rw-r--r--arch/powerpc/include/asm/unistd.h2
-rw-r--r--arch/powerpc/include/uapi/asm/unistd.h1
-rw-r--r--arch/powerpc/kernel/dma.c8
-rw-r--r--arch/powerpc/kernel/eeh.c19
-rw-r--r--arch/powerpc/kernel/eeh_driver.c12
-rw-r--r--arch/powerpc/kernel/eeh_pe.c10
-rw-r--r--arch/powerpc/kernel/exceptions-64s.S5
-rw-r--r--arch/powerpc/kernel/irq.c2
-rw-r--r--arch/powerpc/kernel/misc.S4
-rw-r--r--arch/powerpc/kernel/ppc_ksyms.c2
-rw-r--r--arch/powerpc/kernel/process.c2
-rw-r--r--arch/powerpc/kernel/rtas_pci.c30
-rw-r--r--arch/powerpc/kernel/setup_64.c32
-rw-r--r--arch/powerpc/kernel/stacktrace.c2
-rw-r--r--arch/powerpc/mm/copro_fault.c3
-rw-r--r--arch/powerpc/mm/numa.c48
-rw-r--r--arch/powerpc/mm/slice.c3
-rw-r--r--arch/powerpc/perf/hv-24x7.c6
-rw-r--r--arch/powerpc/perf/hv-gpci.c6
-rw-r--r--arch/powerpc/platforms/powernv/eeh-ioda.c2
-rw-r--r--arch/powerpc/platforms/powernv/eeh-powernv.c57
-rw-r--r--arch/powerpc/platforms/powernv/opal-lpc.c4
-rw-r--r--arch/powerpc/platforms/powernv/opal-wrappers.S2
-rw-r--r--arch/powerpc/platforms/powernv/opal.c21
-rw-r--r--arch/powerpc/platforms/powernv/pci.c2
-rw-r--r--arch/powerpc/platforms/pseries/dlpar.c22
-rw-r--r--arch/powerpc/platforms/pseries/hotplug-cpu.c4
-rw-r--r--arch/powerpc/platforms/pseries/iommu.c11
-rw-r--r--arch/powerpc/platforms/pseries/pseries.h3
-rw-r--r--arch/powerpc/sysdev/msi_bitmap.c66
-rw-r--r--arch/s390/include/uapi/asm/unistd.h3
-rw-r--r--arch/s390/kernel/compat_wrapper.c1
-rw-r--r--arch/s390/kernel/perf_cpum_sf.c6
-rw-r--r--arch/s390/kernel/syscalls.S1
-rw-r--r--arch/s390/kernel/uprobes.c2
-rw-r--r--arch/s390/lib/probes.c2
-rw-r--r--arch/s390/mm/pgtable.c6
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c6
-rw-r--r--arch/sparc/include/asm/oplib_64.h3
-rw-r--r--arch/sparc/include/asm/setup.h2
-rw-r--r--arch/sparc/include/uapi/asm/unistd.h3
-rw-r--r--arch/sparc/kernel/entry.h3
-rw-r--r--arch/sparc/kernel/head_64.S40
-rw-r--r--arch/sparc/kernel/hvtramp.S1
-rw-r--r--arch/sparc/kernel/setup_64.c28
-rw-r--r--arch/sparc/kernel/systbls_32.S2
-rw-r--r--arch/sparc/kernel/systbls_64.S4
-rw-r--r--arch/sparc/kernel/trampoline_64.S12
-rw-r--r--arch/sparc/mm/gup.c30
-rw-r--r--arch/sparc/prom/cif.S5
-rw-r--r--arch/sparc/prom/init_64.c6
-rw-r--r--arch/sparc/prom/p1275.c2
-rw-r--r--arch/x86/Kconfig4
-rw-r--r--arch/x86/boot/compressed/eboot.c32
-rw-r--r--arch/x86/ia32/ia32entry.S2
-rw-r--r--arch/x86/include/asm/efi.h31
-rw-r--r--arch/x86/include/asm/kvm_host.h16
-rw-r--r--arch/x86/include/asm/preempt.h1
-rw-r--r--arch/x86/include/uapi/asm/vmx.h2
-rw-r--r--arch/x86/kernel/acpi/boot.c16
-rw-r--r--arch/x86/kernel/apb_timer.c2
-rw-r--r--arch/x86/kernel/apic/apic.c4
-rw-r--r--arch/x86/kernel/cpu/Makefile7
-rw-r--r--arch/x86/kernel/cpu/intel.c5
-rw-r--r--arch/x86/kernel/cpu/perf_event.c14
-rw-r--r--arch/x86/kernel/cpu/perf_event.h1
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel.c173
-rw-r--r--arch/x86/kernel/entry_32.S15
-rw-r--r--arch/x86/kernel/i8259.c3
-rw-r--r--arch/x86/kernel/irqinit.c3
-rw-r--r--arch/x86/kernel/setup.c2
-rw-r--r--arch/x86/kernel/smpboot.c4
-rw-r--r--arch/x86/kernel/tsc.c5
-rw-r--r--arch/x86/kvm/emulate.c299
-rw-r--r--arch/x86/kvm/i8254.c2
-rw-r--r--arch/x86/kvm/paging_tmpl.h2
-rw-r--r--arch/x86/kvm/svm.c8
-rw-r--r--arch/x86/kvm/vmx.c30
-rw-r--r--arch/x86/kvm/x86.c38
-rw-r--r--arch/x86/mm/pageattr.c2
-rw-r--r--arch/x86/platform/efi/efi-bgrt.c36
-rw-r--r--arch/x86/platform/efi/efi.c52
-rw-r--r--arch/x86/platform/efi/efi_32.c12
-rw-r--r--arch/x86/platform/efi/efi_64.c6
-rw-r--r--arch/x86/platform/efi/efi_stub_32.S4
-rw-r--r--arch/x86/platform/intel-mid/intel_mid_weak_decls.h7
-rw-r--r--arch/x86/platform/intel-mid/sfi.c2
-rw-r--r--arch/x86/xen/enlighten.c3
-rw-r--r--arch/x86/xen/mmu.c5
-rw-r--r--arch/x86/xen/p2m.c83
-rw-r--r--arch/x86/xen/setup.c1
-rw-r--r--arch/x86/xen/time.c2
431 files changed, 12670 insertions, 3902 deletions
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 9596b0ab108d..fe44b2494609 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -9,6 +9,7 @@
9config ARC 9config ARC
10 def_bool y 10 def_bool y
11 select BUILDTIME_EXTABLE_SORT 11 select BUILDTIME_EXTABLE_SORT
12 select COMMON_CLK
12 select CLONE_BACKWARDS 13 select CLONE_BACKWARDS
13 # ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev 14 # ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev
14 select DEVTMPFS if !INITRAMFS_SOURCE="" 15 select DEVTMPFS if !INITRAMFS_SOURCE=""
@@ -73,9 +74,6 @@ config STACKTRACE_SUPPORT
73config HAVE_LATENCYTOP_SUPPORT 74config HAVE_LATENCYTOP_SUPPORT
74 def_bool y 75 def_bool y
75 76
76config NO_DMA
77 def_bool n
78
79source "init/Kconfig" 77source "init/Kconfig"
80source "kernel/Kconfig.freezer" 78source "kernel/Kconfig.freezer"
81 79
@@ -354,7 +352,7 @@ config ARC_CURR_IN_REG
354 kernel mode. This saves memory access for each such access 352 kernel mode. This saves memory access for each such access
355 353
356 354
357config ARC_MISALIGN_ACCESS 355config ARC_EMUL_UNALIGNED
358 bool "Emulate unaligned memory access (userspace only)" 356 bool "Emulate unaligned memory access (userspace only)"
359 select SYSCTL_ARCH_UNALIGN_NO_WARN 357 select SYSCTL_ARCH_UNALIGN_NO_WARN
360 select SYSCTL_ARCH_UNALIGN_ALLOW 358 select SYSCTL_ARCH_UNALIGN_ALLOW
diff --git a/arch/arc/Makefile b/arch/arc/Makefile
index 8c0b1aa56f7e..10bc3d4e8a44 100644
--- a/arch/arc/Makefile
+++ b/arch/arc/Makefile
@@ -25,7 +25,6 @@ ifdef CONFIG_ARC_CURR_IN_REG
25LINUXINCLUDE += -include ${src}/arch/arc/include/asm/current.h 25LINUXINCLUDE += -include ${src}/arch/arc/include/asm/current.h
26endif 26endif
27 27
28upto_gcc42 := $(call cc-ifversion, -le, 0402, y)
29upto_gcc44 := $(call cc-ifversion, -le, 0404, y) 28upto_gcc44 := $(call cc-ifversion, -le, 0404, y)
30atleast_gcc44 := $(call cc-ifversion, -ge, 0404, y) 29atleast_gcc44 := $(call cc-ifversion, -ge, 0404, y)
31atleast_gcc48 := $(call cc-ifversion, -ge, 0408, y) 30atleast_gcc48 := $(call cc-ifversion, -ge, 0408, y)
@@ -60,25 +59,11 @@ ldflags-$(CONFIG_CPU_BIG_ENDIAN) += -EB
60# --build-id w/o "-marclinux". Default arc-elf32-ld is OK 59# --build-id w/o "-marclinux". Default arc-elf32-ld is OK
61ldflags-$(upto_gcc44) += -marclinux 60ldflags-$(upto_gcc44) += -marclinux
62 61
63ARC_LIBGCC := -mA7
64cflags-$(CONFIG_ARC_HAS_HW_MPY) += -multcost=16
65
66ifndef CONFIG_ARC_HAS_HW_MPY 62ifndef CONFIG_ARC_HAS_HW_MPY
67 cflags-y += -mno-mpy 63 cflags-y += -mno-mpy
68
69# newlib for ARC700 assumes MPY to be always present, which is generally true
70# However, if someone really doesn't want MPY, we need to use the 600 ver
71# which coupled with -mno-mpy will use mpy emulation
72# With gcc 4.4.7, -mno-mpy is enough to make any other related adjustments,
73# e.g. increased cost of MPY. With gcc 4.2.1 this had to be explicitly hinted
74
75 ifeq ($(upto_gcc42),y)
76 ARC_LIBGCC := -marc600
77 cflags-y += -multcost=30
78 endif
79endif 64endif
80 65
81LIBGCC := $(shell $(CC) $(ARC_LIBGCC) $(cflags-y) --print-libgcc-file-name) 66LIBGCC := $(shell $(CC) $(cflags-y) --print-libgcc-file-name)
82 67
83# Modules with short calls might break for calls into builtin-kernel 68# Modules with short calls might break for calls into builtin-kernel
84KBUILD_CFLAGS_MODULE += -mlong-calls 69KBUILD_CFLAGS_MODULE += -mlong-calls
diff --git a/arch/arc/boot/dts/angel4.dts b/arch/arc/boot/dts/angel4.dts
index 6b57475967a6..757e0c62c4f9 100644
--- a/arch/arc/boot/dts/angel4.dts
+++ b/arch/arc/boot/dts/angel4.dts
@@ -24,11 +24,6 @@
24 serial0 = &arcuart0; 24 serial0 = &arcuart0;
25 }; 25 };
26 26
27 memory {
28 device_type = "memory";
29 reg = <0x00000000 0x10000000>; /* 256M */
30 };
31
32 fpga { 27 fpga {
33 compatible = "simple-bus"; 28 compatible = "simple-bus";
34 #address-cells = <1>; 29 #address-cells = <1>;
diff --git a/arch/arc/boot/dts/nsimosci.dts b/arch/arc/boot/dts/nsimosci.dts
index 4f31b2eb5cdf..cfaedd9c61c9 100644
--- a/arch/arc/boot/dts/nsimosci.dts
+++ b/arch/arc/boot/dts/nsimosci.dts
@@ -20,18 +20,13 @@
20 /* this is for console on PGU */ 20 /* this is for console on PGU */
21 /* bootargs = "console=tty0 consoleblank=0"; */ 21 /* bootargs = "console=tty0 consoleblank=0"; */
22 /* this is for console on serial */ 22 /* this is for console on serial */
23 bootargs = "earlycon=uart8250,mmio32,0xc0000000,115200n8 console=ttyS0,115200n8 consoleblank=0 debug"; 23 bootargs = "earlycon=uart8250,mmio32,0xc0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug";
24 }; 24 };
25 25
26 aliases { 26 aliases {
27 serial0 = &uart0; 27 serial0 = &uart0;
28 }; 28 };
29 29
30 memory {
31 device_type = "memory";
32 reg = <0x80000000 0x10000000>; /* 256M */
33 };
34
35 fpga { 30 fpga {
36 compatible = "simple-bus"; 31 compatible = "simple-bus";
37 #address-cells = <1>; 32 #address-cells = <1>;
diff --git a/arch/arc/configs/fpga_defconfig b/arch/arc/configs/fpga_defconfig
index e283aa586934..ef4d3bc7b6c0 100644
--- a/arch/arc/configs/fpga_defconfig
+++ b/arch/arc/configs/fpga_defconfig
@@ -23,7 +23,6 @@ CONFIG_MODULES=y
23# CONFIG_IOSCHED_DEADLINE is not set 23# CONFIG_IOSCHED_DEADLINE is not set
24# CONFIG_IOSCHED_CFQ is not set 24# CONFIG_IOSCHED_CFQ is not set
25CONFIG_ARC_PLAT_FPGA_LEGACY=y 25CONFIG_ARC_PLAT_FPGA_LEGACY=y
26CONFIG_ARC_BOARD_ML509=y
27# CONFIG_ARC_HAS_RTSC is not set 26# CONFIG_ARC_HAS_RTSC is not set
28CONFIG_ARC_BUILTIN_DTB_NAME="angel4" 27CONFIG_ARC_BUILTIN_DTB_NAME="angel4"
29CONFIG_PREEMPT=y 28CONFIG_PREEMPT=y
diff --git a/arch/arc/configs/fpga_noramfs_defconfig b/arch/arc/configs/fpga_noramfs_defconfig
index 5276a52f6a2f..49c93011ab96 100644
--- a/arch/arc/configs/fpga_noramfs_defconfig
+++ b/arch/arc/configs/fpga_noramfs_defconfig
@@ -20,7 +20,6 @@ CONFIG_MODULES=y
20# CONFIG_IOSCHED_DEADLINE is not set 20# CONFIG_IOSCHED_DEADLINE is not set
21# CONFIG_IOSCHED_CFQ is not set 21# CONFIG_IOSCHED_CFQ is not set
22CONFIG_ARC_PLAT_FPGA_LEGACY=y 22CONFIG_ARC_PLAT_FPGA_LEGACY=y
23CONFIG_ARC_BOARD_ML509=y
24# CONFIG_ARC_HAS_RTSC is not set 23# CONFIG_ARC_HAS_RTSC is not set
25CONFIG_ARC_BUILTIN_DTB_NAME="angel4" 24CONFIG_ARC_BUILTIN_DTB_NAME="angel4"
26CONFIG_PREEMPT=y 25CONFIG_PREEMPT=y
diff --git a/arch/arc/configs/nsimosci_defconfig b/arch/arc/configs/nsimosci_defconfig
index c01ba35a4eff..278dacf2a3f9 100644
--- a/arch/arc/configs/nsimosci_defconfig
+++ b/arch/arc/configs/nsimosci_defconfig
@@ -21,7 +21,6 @@ CONFIG_MODULES=y
21# CONFIG_IOSCHED_DEADLINE is not set 21# CONFIG_IOSCHED_DEADLINE is not set
22# CONFIG_IOSCHED_CFQ is not set 22# CONFIG_IOSCHED_CFQ is not set
23CONFIG_ARC_PLAT_FPGA_LEGACY=y 23CONFIG_ARC_PLAT_FPGA_LEGACY=y
24CONFIG_ARC_BOARD_ML509=y
25# CONFIG_ARC_IDE is not set 24# CONFIG_ARC_IDE is not set
26# CONFIG_ARCTANGENT_EMAC is not set 25# CONFIG_ARCTANGENT_EMAC is not set
27# CONFIG_ARC_HAS_RTSC is not set 26# CONFIG_ARC_HAS_RTSC is not set
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 372466b371bf..be33db8a2ee3 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -9,19 +9,16 @@
9#ifndef _ASM_ARC_ARCREGS_H 9#ifndef _ASM_ARC_ARCREGS_H
10#define _ASM_ARC_ARCREGS_H 10#define _ASM_ARC_ARCREGS_H
11 11
12#ifdef __KERNEL__
13
14/* Build Configuration Registers */ 12/* Build Configuration Registers */
15#define ARC_REG_DCCMBASE_BCR 0x61 /* DCCM Base Addr */ 13#define ARC_REG_DCCMBASE_BCR 0x61 /* DCCM Base Addr */
16#define ARC_REG_CRC_BCR 0x62 14#define ARC_REG_CRC_BCR 0x62
17#define ARC_REG_DVFB_BCR 0x64
18#define ARC_REG_EXTARITH_BCR 0x65
19#define ARC_REG_VECBASE_BCR 0x68 15#define ARC_REG_VECBASE_BCR 0x68
20#define ARC_REG_PERIBASE_BCR 0x69 16#define ARC_REG_PERIBASE_BCR 0x69
21#define ARC_REG_FP_BCR 0x6B /* Single-Precision FPU */ 17#define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
22#define ARC_REG_DPFP_BCR 0x6C /* Dbl Precision FPU */ 18#define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */
23#define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */ 19#define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */
24#define ARC_REG_TIMERS_BCR 0x75 20#define ARC_REG_TIMERS_BCR 0x75
21#define ARC_REG_AP_BCR 0x76
25#define ARC_REG_ICCM_BCR 0x78 22#define ARC_REG_ICCM_BCR 0x78
26#define ARC_REG_XY_MEM_BCR 0x79 23#define ARC_REG_XY_MEM_BCR 0x79
27#define ARC_REG_MAC_BCR 0x7a 24#define ARC_REG_MAC_BCR 0x7a
@@ -31,6 +28,9 @@
31#define ARC_REG_MIXMAX_BCR 0x7e 28#define ARC_REG_MIXMAX_BCR 0x7e
32#define ARC_REG_BARREL_BCR 0x7f 29#define ARC_REG_BARREL_BCR 0x7f
33#define ARC_REG_D_UNCACH_BCR 0x6A 30#define ARC_REG_D_UNCACH_BCR 0x6A
31#define ARC_REG_BPU_BCR 0xc0
32#define ARC_REG_ISA_CFG_BCR 0xc1
33#define ARC_REG_SMART_BCR 0xFF
34 34
35/* status32 Bits Positions */ 35/* status32 Bits Positions */
36#define STATUS_AE_BIT 5 /* Exception active */ 36#define STATUS_AE_BIT 5 /* Exception active */
@@ -191,14 +191,6 @@
191#define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10)) 191#define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10))
192#define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10) 192#define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10)
193 193
194#ifdef CONFIG_ARC_FPU_SAVE_RESTORE
195/* These DPFP regs need to be saved/restored across ctx-sw */
196struct arc_fpu {
197 struct {
198 unsigned int l, h;
199 } aux_dpfp[2];
200};
201#endif
202 194
203/* 195/*
204 *************************************************************** 196 ***************************************************************
@@ -212,27 +204,19 @@ struct bcr_identity {
212#endif 204#endif
213}; 205};
214 206
215#define EXTN_SWAP_VALID 0x1 207struct bcr_isa {
216#define EXTN_NORM_VALID 0x2
217#define EXTN_MINMAX_VALID 0x2
218#define EXTN_BARREL_VALID 0x2
219
220struct bcr_extn {
221#ifdef CONFIG_CPU_BIG_ENDIAN 208#ifdef CONFIG_CPU_BIG_ENDIAN
222 unsigned int pad:20, crc:1, ext_arith:2, mul:2, barrel:2, minmax:2, 209 unsigned int pad1:23, atomic1:1, ver:8;
223 norm:2, swap:1;
224#else 210#else
225 unsigned int swap:1, norm:2, minmax:2, barrel:2, mul:2, ext_arith:2, 211 unsigned int ver:8, atomic1:1, pad1:23;
226 crc:1, pad:20;
227#endif 212#endif
228}; 213};
229 214
230/* DSP Options Ref Manual */ 215struct bcr_mpy {
231struct bcr_extn_mac_mul {
232#ifdef CONFIG_CPU_BIG_ENDIAN 216#ifdef CONFIG_CPU_BIG_ENDIAN
233 unsigned int pad:16, type:8, ver:8; 217 unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
234#else 218#else
235 unsigned int ver:8, type:8, pad:16; 219 unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8;
236#endif 220#endif
237}; 221};
238 222
@@ -251,6 +235,7 @@ struct bcr_perip {
251 unsigned int pad:8, sz:8, pad2:8, start:8; 235 unsigned int pad:8, sz:8, pad2:8, start:8;
252#endif 236#endif
253}; 237};
238
254struct bcr_iccm { 239struct bcr_iccm {
255#ifdef CONFIG_CPU_BIG_ENDIAN 240#ifdef CONFIG_CPU_BIG_ENDIAN
256 unsigned int base:16, pad:5, sz:3, ver:8; 241 unsigned int base:16, pad:5, sz:3, ver:8;
@@ -277,8 +262,8 @@ struct bcr_dccm {
277#endif 262#endif
278}; 263};
279 264
280/* Both SP and DP FPU BCRs have same format */ 265/* ARCompact: Both SP and DP FPU BCRs have same format */
281struct bcr_fp { 266struct bcr_fp_arcompact {
282#ifdef CONFIG_CPU_BIG_ENDIAN 267#ifdef CONFIG_CPU_BIG_ENDIAN
283 unsigned int fast:1, ver:8; 268 unsigned int fast:1, ver:8;
284#else 269#else
@@ -286,6 +271,30 @@ struct bcr_fp {
286#endif 271#endif
287}; 272};
288 273
274struct bcr_timer {
275#ifdef CONFIG_CPU_BIG_ENDIAN
276 unsigned int pad2:15, rtsc:1, pad1:6, t1:1, t0:1, ver:8;
277#else
278 unsigned int ver:8, t0:1, t1:1, pad1:6, rtsc:1, pad2:15;
279#endif
280};
281
282struct bcr_bpu_arcompact {
283#ifdef CONFIG_CPU_BIG_ENDIAN
284 unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8;
285#else
286 unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19;
287#endif
288};
289
290struct bcr_generic {
291#ifdef CONFIG_CPU_BIG_ENDIAN
292 unsigned int pad:24, ver:8;
293#else
294 unsigned int ver:8, pad:24;
295#endif
296};
297
289/* 298/*
290 ******************************************************************* 299 *******************************************************************
291 * Generic structures to hold build configuration used at runtime 300 * Generic structures to hold build configuration used at runtime
@@ -299,6 +308,10 @@ struct cpuinfo_arc_cache {
299 unsigned int sz_k:8, line_len:8, assoc:4, ver:4, alias:1, vipt:1, pad:6; 308 unsigned int sz_k:8, line_len:8, assoc:4, ver:4, alias:1, vipt:1, pad:6;
300}; 309};
301 310
311struct cpuinfo_arc_bpu {
312 unsigned int ver, full, num_cache, num_pred;
313};
314
302struct cpuinfo_arc_ccm { 315struct cpuinfo_arc_ccm {
303 unsigned int base_addr, sz; 316 unsigned int base_addr, sz;
304}; 317};
@@ -306,21 +319,25 @@ struct cpuinfo_arc_ccm {
306struct cpuinfo_arc { 319struct cpuinfo_arc {
307 struct cpuinfo_arc_cache icache, dcache; 320 struct cpuinfo_arc_cache icache, dcache;
308 struct cpuinfo_arc_mmu mmu; 321 struct cpuinfo_arc_mmu mmu;
322 struct cpuinfo_arc_bpu bpu;
309 struct bcr_identity core; 323 struct bcr_identity core;
310 unsigned int timers; 324 struct bcr_isa isa;
325 struct bcr_timer timers;
311 unsigned int vec_base; 326 unsigned int vec_base;
312 unsigned int uncached_base; 327 unsigned int uncached_base;
313 struct cpuinfo_arc_ccm iccm, dccm; 328 struct cpuinfo_arc_ccm iccm, dccm;
314 struct bcr_extn extn; 329 struct {
330 unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, pad1:3,
331 fpu_sp:1, fpu_dp:1, pad2:6,
332 debug:1, ap:1, smart:1, rtt:1, pad3:4,
333 pad4:8;
334 } extn;
335 struct bcr_mpy extn_mpy;
315 struct bcr_extn_xymem extn_xymem; 336 struct bcr_extn_xymem extn_xymem;
316 struct bcr_extn_mac_mul extn_mac_mul;
317 struct bcr_fp fp, dpfp;
318}; 337};
319 338
320extern struct cpuinfo_arc cpuinfo_arc700[]; 339extern struct cpuinfo_arc cpuinfo_arc700[];
321 340
322#endif /* __ASEMBLY__ */ 341#endif /* __ASEMBLY__ */
323 342
324#endif /* __KERNEL__ */
325
326#endif /* _ASM_ARC_ARCREGS_H */ 343#endif /* _ASM_ARC_ARCREGS_H */
diff --git a/arch/arc/include/asm/atomic.h b/arch/arc/include/asm/atomic.h
index 173f303a868f..067551b6920a 100644
--- a/arch/arc/include/asm/atomic.h
+++ b/arch/arc/include/asm/atomic.h
@@ -9,8 +9,6 @@
9#ifndef _ASM_ARC_ATOMIC_H 9#ifndef _ASM_ARC_ATOMIC_H
10#define _ASM_ARC_ATOMIC_H 10#define _ASM_ARC_ATOMIC_H
11 11
12#ifdef __KERNEL__
13
14#ifndef __ASSEMBLY__ 12#ifndef __ASSEMBLY__
15 13
16#include <linux/types.h> 14#include <linux/types.h>
@@ -170,5 +168,3 @@ ATOMIC_OP(and, &=, and)
170#endif 168#endif
171 169
172#endif 170#endif
173
174#endif
diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h
index ebc0cf3164dc..1a5bf07eefe2 100644
--- a/arch/arc/include/asm/bitops.h
+++ b/arch/arc/include/asm/bitops.h
@@ -13,8 +13,6 @@
13#error only <linux/bitops.h> can be included directly 13#error only <linux/bitops.h> can be included directly
14#endif 14#endif
15 15
16#ifdef __KERNEL__
17
18#ifndef __ASSEMBLY__ 16#ifndef __ASSEMBLY__
19 17
20#include <linux/types.h> 18#include <linux/types.h>
@@ -508,6 +506,4 @@ static inline __attribute__ ((const)) int __ffs(unsigned long word)
508 506
509#endif /* !__ASSEMBLY__ */ 507#endif /* !__ASSEMBLY__ */
510 508
511#endif /* __KERNEL__ */
512
513#endif 509#endif
diff --git a/arch/arc/include/asm/bug.h b/arch/arc/include/asm/bug.h
index 5b18e94c6678..ea022d47896c 100644
--- a/arch/arc/include/asm/bug.h
+++ b/arch/arc/include/asm/bug.h
@@ -21,10 +21,9 @@ void show_kernel_fault_diag(const char *str, struct pt_regs *regs,
21 unsigned long address); 21 unsigned long address);
22void die(const char *str, struct pt_regs *regs, unsigned long address); 22void die(const char *str, struct pt_regs *regs, unsigned long address);
23 23
24#define BUG() do { \ 24#define BUG() do { \
25 dump_stack(); \ 25 pr_warn("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
26 pr_warn("Kernel BUG in %s: %s: %d!\n", \ 26 dump_stack(); \
27 __FILE__, __func__, __LINE__); \
28} while (0) 27} while (0)
29 28
30#define HAVE_ARCH_BUG 29#define HAVE_ARCH_BUG
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index b3c750979aa1..7861255da32d 100644
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -20,7 +20,7 @@
20#define CACHE_LINE_MASK (~(L1_CACHE_BYTES - 1)) 20#define CACHE_LINE_MASK (~(L1_CACHE_BYTES - 1))
21 21
22/* 22/*
23 * ARC700 doesn't cache any access in top 256M. 23 * ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF)
24 * Ideal for wiring memory mapped peripherals as we don't need to do 24 * Ideal for wiring memory mapped peripherals as we don't need to do
25 * explicit uncached accesses (LD.di/ST.di) hence more portable drivers 25 * explicit uncached accesses (LD.di/ST.di) hence more portable drivers
26 */ 26 */
diff --git a/arch/arc/include/asm/current.h b/arch/arc/include/asm/current.h
index 87b918585c4a..c2453ee62801 100644
--- a/arch/arc/include/asm/current.h
+++ b/arch/arc/include/asm/current.h
@@ -12,8 +12,6 @@
12#ifndef _ASM_ARC_CURRENT_H 12#ifndef _ASM_ARC_CURRENT_H
13#define _ASM_ARC_CURRENT_H 13#define _ASM_ARC_CURRENT_H
14 14
15#ifdef __KERNEL__
16
17#ifndef __ASSEMBLY__ 15#ifndef __ASSEMBLY__
18 16
19#ifdef CONFIG_ARC_CURR_IN_REG 17#ifdef CONFIG_ARC_CURR_IN_REG
@@ -27,6 +25,4 @@ register struct task_struct *curr_arc asm("r25");
27 25
28#endif /* ! __ASSEMBLY__ */ 26#endif /* ! __ASSEMBLY__ */
29 27
30#endif /* __KERNEL__ */
31
32#endif /* _ASM_ARC_CURRENT_H */ 28#endif /* _ASM_ARC_CURRENT_H */
diff --git a/arch/arc/include/asm/irqflags.h b/arch/arc/include/asm/irqflags.h
index 587df8236e8b..742816f1b210 100644
--- a/arch/arc/include/asm/irqflags.h
+++ b/arch/arc/include/asm/irqflags.h
@@ -15,8 +15,6 @@
15 * -Conditionally disable interrupts (if they are not enabled, don't disable) 15 * -Conditionally disable interrupts (if they are not enabled, don't disable)
16*/ 16*/
17 17
18#ifdef __KERNEL__
19
20#include <asm/arcregs.h> 18#include <asm/arcregs.h>
21 19
22/* status32 Reg bits related to Interrupt Handling */ 20/* status32 Reg bits related to Interrupt Handling */
@@ -169,6 +167,4 @@ static inline int arch_irqs_disabled(void)
169 167
170#endif /* __ASSEMBLY__ */ 168#endif /* __ASSEMBLY__ */
171 169
172#endif /* KERNEL */
173
174#endif 170#endif
diff --git a/arch/arc/include/asm/kgdb.h b/arch/arc/include/asm/kgdb.h
index b65fca7ffeb5..fea931634136 100644
--- a/arch/arc/include/asm/kgdb.h
+++ b/arch/arc/include/asm/kgdb.h
@@ -19,7 +19,7 @@
19 * register API yet */ 19 * register API yet */
20#undef DBG_MAX_REG_NUM 20#undef DBG_MAX_REG_NUM
21 21
22#define GDB_MAX_REGS 39 22#define GDB_MAX_REGS 87
23 23
24#define BREAK_INSTR_SIZE 2 24#define BREAK_INSTR_SIZE 2
25#define CACHE_FLUSH_IS_SAFE 1 25#define CACHE_FLUSH_IS_SAFE 1
@@ -33,23 +33,27 @@ static inline void arch_kgdb_breakpoint(void)
33 33
34extern void kgdb_trap(struct pt_regs *regs); 34extern void kgdb_trap(struct pt_regs *regs);
35 35
36enum arc700_linux_regnums { 36/* This is the numbering of registers according to the GDB. See GDB's
37 * arc-tdep.h for details.
38 *
39 * Registers are ordered for GDB 7.5. It is incompatible with GDB 6.8. */
40enum arc_linux_regnums {
37 _R0 = 0, 41 _R0 = 0,
38 _R1, _R2, _R3, _R4, _R5, _R6, _R7, _R8, _R9, _R10, _R11, _R12, _R13, 42 _R1, _R2, _R3, _R4, _R5, _R6, _R7, _R8, _R9, _R10, _R11, _R12, _R13,
39 _R14, _R15, _R16, _R17, _R18, _R19, _R20, _R21, _R22, _R23, _R24, 43 _R14, _R15, _R16, _R17, _R18, _R19, _R20, _R21, _R22, _R23, _R24,
40 _R25, _R26, 44 _R25, _R26,
41 _BTA = 27, 45 _FP = 27,
42 _LP_START = 28, 46 __SP = 28,
43 _LP_END = 29, 47 _R30 = 30,
44 _LP_COUNT = 30, 48 _BLINK = 31,
45 _STATUS32 = 31, 49 _LP_COUNT = 60,
46 _BLINK = 32, 50 _STOP_PC = 64,
47 _FP = 33, 51 _RET = 64,
48 __SP = 34, 52 _LP_START = 65,
49 _EFA = 35, 53 _LP_END = 66,
50 _RET = 36, 54 _STATUS32 = 67,
51 _ORIG_R8 = 37, 55 _ECR = 76,
52 _STOP_PC = 38 56 _BTA = 82,
53}; 57};
54 58
55#else 59#else
diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
index 82588f3ba77f..210fe97464c3 100644
--- a/arch/arc/include/asm/processor.h
+++ b/arch/arc/include/asm/processor.h
@@ -14,12 +14,19 @@
14#ifndef __ASM_ARC_PROCESSOR_H 14#ifndef __ASM_ARC_PROCESSOR_H
15#define __ASM_ARC_PROCESSOR_H 15#define __ASM_ARC_PROCESSOR_H
16 16
17#ifdef __KERNEL__
18
19#ifndef __ASSEMBLY__ 17#ifndef __ASSEMBLY__
20 18
21#include <asm/ptrace.h> 19#include <asm/ptrace.h>
22 20
21#ifdef CONFIG_ARC_FPU_SAVE_RESTORE
22/* These DPFP regs need to be saved/restored across ctx-sw */
23struct arc_fpu {
24 struct {
25 unsigned int l, h;
26 } aux_dpfp[2];
27};
28#endif
29
23/* Arch specific stuff which needs to be saved per task. 30/* Arch specific stuff which needs to be saved per task.
24 * However these items are not so important so as to earn a place in 31 * However these items are not so important so as to earn a place in
25 * struct thread_info 32 * struct thread_info
@@ -128,6 +135,4 @@ extern unsigned int get_wchan(struct task_struct *p);
128 */ 135 */
129#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) 136#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
130 137
131#endif /* __KERNEL__ */
132
133#endif /* __ASM_ARC_PROCESSOR_H */ 138#endif /* __ASM_ARC_PROCESSOR_H */
diff --git a/arch/arc/include/asm/setup.h b/arch/arc/include/asm/setup.h
index e10f8cef56a8..6e3ef5ba4f74 100644
--- a/arch/arc/include/asm/setup.h
+++ b/arch/arc/include/asm/setup.h
@@ -29,7 +29,6 @@ struct cpuinfo_data {
29}; 29};
30 30
31extern int root_mountflags, end_mem; 31extern int root_mountflags, end_mem;
32extern int running_on_hw;
33 32
34void setup_processor(void); 33void setup_processor(void);
35void __init setup_arch_memory(void); 34void __init setup_arch_memory(void);
diff --git a/arch/arc/include/asm/smp.h b/arch/arc/include/asm/smp.h
index 5d06eee43ea9..3845b9e94f69 100644
--- a/arch/arc/include/asm/smp.h
+++ b/arch/arc/include/asm/smp.h
@@ -59,7 +59,15 @@ struct plat_smp_ops {
59/* TBD: stop exporting it for direct population by platform */ 59/* TBD: stop exporting it for direct population by platform */
60extern struct plat_smp_ops plat_smp_ops; 60extern struct plat_smp_ops plat_smp_ops;
61 61
62#endif /* CONFIG_SMP */ 62#else /* CONFIG_SMP */
63
64static inline void smp_init_cpus(void) {}
65static inline const char *arc_platform_smp_cpuinfo(void)
66{
67 return "";
68}
69
70#endif /* !CONFIG_SMP */
63 71
64/* 72/*
65 * ARC700 doesn't support atomic Read-Modify-Write ops. 73 * ARC700 doesn't support atomic Read-Modify-Write ops.
diff --git a/arch/arc/include/asm/string.h b/arch/arc/include/asm/string.h
index 87676c8f1412..95822b550a18 100644
--- a/arch/arc/include/asm/string.h
+++ b/arch/arc/include/asm/string.h
@@ -17,8 +17,6 @@
17 17
18#include <linux/types.h> 18#include <linux/types.h>
19 19
20#ifdef __KERNEL__
21
22#define __HAVE_ARCH_MEMSET 20#define __HAVE_ARCH_MEMSET
23#define __HAVE_ARCH_MEMCPY 21#define __HAVE_ARCH_MEMCPY
24#define __HAVE_ARCH_MEMCMP 22#define __HAVE_ARCH_MEMCMP
@@ -36,5 +34,4 @@ extern char *strcpy(char *dest, const char *src);
36extern int strcmp(const char *cs, const char *ct); 34extern int strcmp(const char *cs, const char *ct);
37extern __kernel_size_t strlen(const char *); 35extern __kernel_size_t strlen(const char *);
38 36
39#endif /* __KERNEL__ */
40#endif /* _ASM_ARC_STRING_H */ 37#endif /* _ASM_ARC_STRING_H */
diff --git a/arch/arc/include/asm/syscalls.h b/arch/arc/include/asm/syscalls.h
index dd785befe7fd..e56f9fcc5581 100644
--- a/arch/arc/include/asm/syscalls.h
+++ b/arch/arc/include/asm/syscalls.h
@@ -9,8 +9,6 @@
9#ifndef _ASM_ARC_SYSCALLS_H 9#ifndef _ASM_ARC_SYSCALLS_H
10#define _ASM_ARC_SYSCALLS_H 1 10#define _ASM_ARC_SYSCALLS_H 1
11 11
12#ifdef __KERNEL__
13
14#include <linux/compiler.h> 12#include <linux/compiler.h>
15#include <linux/linkage.h> 13#include <linux/linkage.h>
16#include <linux/types.h> 14#include <linux/types.h>
@@ -22,6 +20,4 @@ int sys_arc_gettls(void);
22 20
23#include <asm-generic/syscalls.h> 21#include <asm-generic/syscalls.h>
24 22
25#endif /* __KERNEL__ */
26
27#endif 23#endif
diff --git a/arch/arc/include/asm/thread_info.h b/arch/arc/include/asm/thread_info.h
index 45be21672011..02bc5ec0fb2e 100644
--- a/arch/arc/include/asm/thread_info.h
+++ b/arch/arc/include/asm/thread_info.h
@@ -16,8 +16,6 @@
16#ifndef _ASM_THREAD_INFO_H 16#ifndef _ASM_THREAD_INFO_H
17#define _ASM_THREAD_INFO_H 17#define _ASM_THREAD_INFO_H
18 18
19#ifdef __KERNEL__
20
21#include <asm/page.h> 19#include <asm/page.h>
22 20
23#ifdef CONFIG_16KSTACKS 21#ifdef CONFIG_16KSTACKS
@@ -114,6 +112,4 @@ static inline __attribute_const__ struct thread_info *current_thread_info(void)
114 * syscall, so all that reamins to be tested is _TIF_WORK_MASK 112 * syscall, so all that reamins to be tested is _TIF_WORK_MASK
115 */ 113 */
116 114
117#endif /* __KERNEL__ */
118
119#endif /* _ASM_THREAD_INFO_H */ 115#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/arc/include/asm/unaligned.h b/arch/arc/include/asm/unaligned.h
index 3e5f071bc00c..6da6b4edaeda 100644
--- a/arch/arc/include/asm/unaligned.h
+++ b/arch/arc/include/asm/unaligned.h
@@ -14,7 +14,7 @@
14#include <asm-generic/unaligned.h> 14#include <asm-generic/unaligned.h>
15#include <asm/ptrace.h> 15#include <asm/ptrace.h>
16 16
17#ifdef CONFIG_ARC_MISALIGN_ACCESS 17#ifdef CONFIG_ARC_EMUL_UNALIGNED
18int misaligned_fixup(unsigned long address, struct pt_regs *regs, 18int misaligned_fixup(unsigned long address, struct pt_regs *regs,
19 struct callee_regs *cregs); 19 struct callee_regs *cregs);
20#else 20#else
diff --git a/arch/arc/kernel/Makefile b/arch/arc/kernel/Makefile
index 8004b4fa6461..113f2033da9f 100644
--- a/arch/arc/kernel/Makefile
+++ b/arch/arc/kernel/Makefile
@@ -16,7 +16,7 @@ obj-$(CONFIG_MODULES) += arcksyms.o module.o
16obj-$(CONFIG_SMP) += smp.o 16obj-$(CONFIG_SMP) += smp.o
17obj-$(CONFIG_ARC_DW2_UNWIND) += unwind.o 17obj-$(CONFIG_ARC_DW2_UNWIND) += unwind.o
18obj-$(CONFIG_KPROBES) += kprobes.o 18obj-$(CONFIG_KPROBES) += kprobes.o
19obj-$(CONFIG_ARC_MISALIGN_ACCESS) += unaligned.o 19obj-$(CONFIG_ARC_EMUL_UNALIGNED) += unaligned.o
20obj-$(CONFIG_KGDB) += kgdb.o 20obj-$(CONFIG_KGDB) += kgdb.o
21obj-$(CONFIG_ARC_METAWARE_HLINK) += arc_hostlink.o 21obj-$(CONFIG_ARC_METAWARE_HLINK) += arc_hostlink.o
22obj-$(CONFIG_PERF_EVENTS) += perf_event.o 22obj-$(CONFIG_PERF_EVENTS) += perf_event.o
diff --git a/arch/arc/kernel/disasm.c b/arch/arc/kernel/disasm.c
index b8a549c4f540..3b7cd4864ba2 100644
--- a/arch/arc/kernel/disasm.c
+++ b/arch/arc/kernel/disasm.c
@@ -15,7 +15,7 @@
15#include <linux/uaccess.h> 15#include <linux/uaccess.h>
16#include <asm/disasm.h> 16#include <asm/disasm.h>
17 17
18#if defined(CONFIG_KGDB) || defined(CONFIG_ARC_MISALIGN_ACCESS) || \ 18#if defined(CONFIG_KGDB) || defined(CONFIG_ARC_EMUL_UNALIGNED) || \
19 defined(CONFIG_KPROBES) 19 defined(CONFIG_KPROBES)
20 20
21/* disasm_instr: Analyses instruction at addr, stores 21/* disasm_instr: Analyses instruction at addr, stores
@@ -535,4 +535,4 @@ int __kprobes disasm_next_pc(unsigned long pc, struct pt_regs *regs,
535 return instr.is_branch; 535 return instr.is_branch;
536} 536}
537 537
538#endif /* CONFIG_KGDB || CONFIG_ARC_MISALIGN_ACCESS || CONFIG_KPROBES */ 538#endif /* CONFIG_KGDB || CONFIG_ARC_EMUL_UNALIGNED || CONFIG_KPROBES */
diff --git a/arch/arc/kernel/head.S b/arch/arc/kernel/head.S
index 4d2481bd8b98..b0e8666fdccc 100644
--- a/arch/arc/kernel/head.S
+++ b/arch/arc/kernel/head.S
@@ -91,16 +91,6 @@ stext:
91 st r0, [@uboot_tag] 91 st r0, [@uboot_tag]
92 st r2, [@uboot_arg] 92 st r2, [@uboot_arg]
93 93
94 ; Identify if running on ISS vs Silicon
95 ; IDENTITY Reg [ 3 2 1 0 ]
96 ; (chip-id) ^^^^^ ==> 0xffff for ISS
97 lr r0, [identity]
98 lsr r3, r0, 16
99 cmp r3, 0xffff
100 mov.z r4, 0
101 mov.nz r4, 1
102 st r4, [@running_on_hw]
103
104 ; setup "current" tsk and optionally cache it in dedicated r25 94 ; setup "current" tsk and optionally cache it in dedicated r25
105 mov r9, @init_task 95 mov r9, @init_task
106 SET_CURR_TASK_ON_CPU r9, r0 ; r9 = tsk, r0 = scratch 96 SET_CURR_TASK_ON_CPU r9, r0 ; r9 = tsk, r0 = scratch
diff --git a/arch/arc/kernel/kgdb.c b/arch/arc/kernel/kgdb.c
index a2ff5c5d1450..ecf6a7869375 100644
--- a/arch/arc/kernel/kgdb.c
+++ b/arch/arc/kernel/kgdb.c
@@ -158,11 +158,6 @@ int kgdb_arch_handle_exception(int e_vector, int signo, int err_code,
158 return -1; 158 return -1;
159} 159}
160 160
161unsigned long kgdb_arch_pc(int exception, struct pt_regs *regs)
162{
163 return instruction_pointer(regs);
164}
165
166int kgdb_arch_init(void) 161int kgdb_arch_init(void)
167{ 162{
168 single_step_data.armed = 0; 163 single_step_data.armed = 0;
diff --git a/arch/arc/kernel/perf_event.c b/arch/arc/kernel/perf_event.c
index b9a5685a990e..ae1c485cbc68 100644
--- a/arch/arc/kernel/perf_event.c
+++ b/arch/arc/kernel/perf_event.c
@@ -244,25 +244,23 @@ static int arc_pmu_device_probe(struct platform_device *pdev)
244 pr_err("This core does not have performance counters!\n"); 244 pr_err("This core does not have performance counters!\n");
245 return -ENODEV; 245 return -ENODEV;
246 } 246 }
247 BUG_ON(pct_bcr.c > ARC_PMU_MAX_HWEVENTS);
247 248
248 arc_pmu = devm_kzalloc(&pdev->dev, sizeof(struct arc_pmu), 249 READ_BCR(ARC_REG_CC_BUILD, cc_bcr);
249 GFP_KERNEL); 250 if (!cc_bcr.v) {
251 pr_err("Performance counters exist, but no countable conditions?\n");
252 return -ENODEV;
253 }
254
255 arc_pmu = devm_kzalloc(&pdev->dev, sizeof(struct arc_pmu), GFP_KERNEL);
250 if (!arc_pmu) 256 if (!arc_pmu)
251 return -ENOMEM; 257 return -ENOMEM;
252 258
253 arc_pmu->n_counters = pct_bcr.c; 259 arc_pmu->n_counters = pct_bcr.c;
254 BUG_ON(arc_pmu->n_counters > ARC_PMU_MAX_HWEVENTS);
255
256 arc_pmu->counter_size = 32 + (pct_bcr.s << 4); 260 arc_pmu->counter_size = 32 + (pct_bcr.s << 4);
257 pr_info("ARC PMU found with %d counters of size %d bits\n",
258 arc_pmu->n_counters, arc_pmu->counter_size);
259
260 READ_BCR(ARC_REG_CC_BUILD, cc_bcr);
261
262 if (!cc_bcr.v)
263 pr_err("Strange! Performance counters exist, but no countable conditions?\n");
264 261
265 pr_info("ARC PMU has %d countable conditions\n", cc_bcr.c); 262 pr_info("ARC perf\t: %d counters (%d bits), %d countable conditions\n",
263 arc_pmu->n_counters, arc_pmu->counter_size, cc_bcr.c);
266 264
267 cc_name.str[8] = 0; 265 cc_name.str[8] = 0;
268 for (i = 0; i < PERF_COUNT_HW_MAX; i++) 266 for (i = 0; i < PERF_COUNT_HW_MAX; i++)
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 119dddb752b2..252bf603db9c 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -13,7 +13,9 @@
13#include <linux/console.h> 13#include <linux/console.h>
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/cpu.h> 15#include <linux/cpu.h>
16#include <linux/clk-provider.h>
16#include <linux/of_fdt.h> 17#include <linux/of_fdt.h>
18#include <linux/of_platform.h>
17#include <linux/cache.h> 19#include <linux/cache.h>
18#include <asm/sections.h> 20#include <asm/sections.h>
19#include <asm/arcregs.h> 21#include <asm/arcregs.h>
@@ -24,11 +26,10 @@
24#include <asm/unwind.h> 26#include <asm/unwind.h>
25#include <asm/clk.h> 27#include <asm/clk.h>
26#include <asm/mach_desc.h> 28#include <asm/mach_desc.h>
29#include <asm/smp.h>
27 30
28#define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x)) 31#define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x))
29 32
30int running_on_hw = 1; /* vs. on ISS */
31
32/* Part of U-boot ABI: see head.S */ 33/* Part of U-boot ABI: see head.S */
33int __initdata uboot_tag; 34int __initdata uboot_tag;
34char __initdata *uboot_arg; 35char __initdata *uboot_arg;
@@ -42,26 +43,26 @@ struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
42static void read_arc_build_cfg_regs(void) 43static void read_arc_build_cfg_regs(void)
43{ 44{
44 struct bcr_perip uncached_space; 45 struct bcr_perip uncached_space;
46 struct bcr_generic bcr;
45 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; 47 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
46 FIX_PTR(cpu); 48 FIX_PTR(cpu);
47 49
48 READ_BCR(AUX_IDENTITY, cpu->core); 50 READ_BCR(AUX_IDENTITY, cpu->core);
51 READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa);
49 52
50 cpu->timers = read_aux_reg(ARC_REG_TIMERS_BCR); 53 READ_BCR(ARC_REG_TIMERS_BCR, cpu->timers);
51 cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE); 54 cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
52 55
53 READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space); 56 READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space);
54 cpu->uncached_base = uncached_space.start << 24; 57 cpu->uncached_base = uncached_space.start << 24;
55 58
56 cpu->extn.mul = read_aux_reg(ARC_REG_MUL_BCR); 59 READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy);
57 cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR);
58 cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR);
59 cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR);
60 cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR);
61 READ_BCR(ARC_REG_MAC_BCR, cpu->extn_mac_mul);
62 60
63 cpu->extn.ext_arith = read_aux_reg(ARC_REG_EXTARITH_BCR); 61 cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */
64 cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR); 62 cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */
63 cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0; /* 1,3 */
64 cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0;
65 cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */
65 66
66 /* Note that we read the CCM BCRs independent of kernel config 67 /* Note that we read the CCM BCRs independent of kernel config
67 * This is to catch the cases where user doesn't know that 68 * This is to catch the cases where user doesn't know that
@@ -95,43 +96,76 @@ static void read_arc_build_cfg_regs(void)
95 read_decode_mmu_bcr(); 96 read_decode_mmu_bcr();
96 read_decode_cache_bcr(); 97 read_decode_cache_bcr();
97 98
98 READ_BCR(ARC_REG_FP_BCR, cpu->fp); 99 {
99 READ_BCR(ARC_REG_DPFP_BCR, cpu->dpfp); 100 struct bcr_fp_arcompact sp, dp;
101 struct bcr_bpu_arcompact bpu;
102
103 READ_BCR(ARC_REG_FP_BCR, sp);
104 READ_BCR(ARC_REG_DPFP_BCR, dp);
105 cpu->extn.fpu_sp = sp.ver ? 1 : 0;
106 cpu->extn.fpu_dp = dp.ver ? 1 : 0;
107
108 READ_BCR(ARC_REG_BPU_BCR, bpu);
109 cpu->bpu.ver = bpu.ver;
110 cpu->bpu.full = bpu.fam ? 1 : 0;
111 if (bpu.ent) {
112 cpu->bpu.num_cache = 256 << (bpu.ent - 1);
113 cpu->bpu.num_pred = 256 << (bpu.ent - 1);
114 }
115 }
116
117 READ_BCR(ARC_REG_AP_BCR, bcr);
118 cpu->extn.ap = bcr.ver ? 1 : 0;
119
120 READ_BCR(ARC_REG_SMART_BCR, bcr);
121 cpu->extn.smart = bcr.ver ? 1 : 0;
122
123 cpu->extn.debug = cpu->extn.ap | cpu->extn.smart;
100} 124}
101 125
102static const struct cpuinfo_data arc_cpu_tbl[] = { 126static const struct cpuinfo_data arc_cpu_tbl[] = {
103 { {0x10, "ARCTangent A5"}, 0x1F},
104 { {0x20, "ARC 600" }, 0x2F}, 127 { {0x20, "ARC 600" }, 0x2F},
105 { {0x30, "ARC 700" }, 0x33}, 128 { {0x30, "ARC 700" }, 0x33},
106 { {0x34, "ARC 700 R4.10"}, 0x34}, 129 { {0x34, "ARC 700 R4.10"}, 0x34},
130 { {0x35, "ARC 700 R4.11"}, 0x35},
107 { {0x00, NULL } } 131 { {0x00, NULL } }
108}; 132};
109 133
134#define IS_AVAIL1(v, str) ((v) ? str : "")
135#define IS_USED(cfg) (IS_ENABLED(cfg) ? "" : "(not used) ")
136#define IS_AVAIL2(v, str, cfg) IS_AVAIL1(v, str), IS_AVAIL1(v, IS_USED(cfg))
137
110static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) 138static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
111{ 139{
112 int n = 0;
113 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; 140 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
114 struct bcr_identity *core = &cpu->core; 141 struct bcr_identity *core = &cpu->core;
115 const struct cpuinfo_data *tbl; 142 const struct cpuinfo_data *tbl;
116 int be = 0; 143 char *isa_nm;
117#ifdef CONFIG_CPU_BIG_ENDIAN 144 int i, be, atomic;
118 be = 1; 145 int n = 0;
119#endif 146
120 FIX_PTR(cpu); 147 FIX_PTR(cpu);
121 148
149 {
150 isa_nm = "ARCompact";
151 be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
152
153 atomic = cpu->isa.atomic1;
154 if (!cpu->isa.ver) /* ISA BCR absent, use Kconfig info */
155 atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
156 }
157
122 n += scnprintf(buf + n, len - n, 158 n += scnprintf(buf + n, len - n,
123 "\nARC IDENTITY\t: Family [%#02x]" 159 "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
124 " Cpu-id [%#02x] Chip-id [%#4x]\n", 160 core->family, core->cpu_id, core->chip_id);
125 core->family, core->cpu_id,
126 core->chip_id);
127 161
128 for (tbl = &arc_cpu_tbl[0]; tbl->info.id != 0; tbl++) { 162 for (tbl = &arc_cpu_tbl[0]; tbl->info.id != 0; tbl++) {
129 if ((core->family >= tbl->info.id) && 163 if ((core->family >= tbl->info.id) &&
130 (core->family <= tbl->up_range)) { 164 (core->family <= tbl->up_range)) {
131 n += scnprintf(buf + n, len - n, 165 n += scnprintf(buf + n, len - n,
132 "processor\t: %s %s\n", 166 "processor [%d]\t: %s (%s ISA) %s\n",
133 tbl->info.str, 167 cpu_id, tbl->info.str, isa_nm,
134 be ? "[Big Endian]" : ""); 168 IS_AVAIL1(be, "[Big-Endian]"));
135 break; 169 break;
136 } 170 }
137 } 171 }
@@ -143,34 +177,35 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
143 (unsigned int)(arc_get_core_freq() / 1000000), 177 (unsigned int)(arc_get_core_freq() / 1000000),
144 (unsigned int)(arc_get_core_freq() / 10000) % 100); 178 (unsigned int)(arc_get_core_freq() / 10000) % 100);
145 179
146 n += scnprintf(buf + n, len - n, "Timers\t\t: %s %s\n", 180 n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ",
147 (cpu->timers & 0x200) ? "TIMER1" : "", 181 IS_AVAIL1(cpu->timers.t0, "Timer0 "),
148 (cpu->timers & 0x100) ? "TIMER0" : ""); 182 IS_AVAIL1(cpu->timers.t1, "Timer1 "),
183 IS_AVAIL2(cpu->timers.rtsc, "64-bit RTSC ", CONFIG_ARC_HAS_RTSC));
149 184
150 n += scnprintf(buf + n, len - n, "Vect Tbl Base\t: %#x\n", 185 n += i = scnprintf(buf + n, len - n, "%s%s",
151 cpu->vec_base); 186 IS_AVAIL2(atomic, "atomic ", CONFIG_ARC_HAS_LLSC));
152 187
153 n += scnprintf(buf + n, len - n, "UNCACHED Base\t: %#x\n", 188 if (i)
154 cpu->uncached_base); 189 n += scnprintf(buf + n, len - n, "\n\t\t: ");
155 190
156 return buf; 191 n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n",
157} 192 IS_AVAIL1(cpu->extn_mpy.ver, "mpy "),
193 IS_AVAIL1(cpu->extn.norm, "norm "),
194 IS_AVAIL1(cpu->extn.barrel, "barrel-shift "),
195 IS_AVAIL1(cpu->extn.swap, "swap "),
196 IS_AVAIL1(cpu->extn.minmax, "minmax "),
197 IS_AVAIL1(cpu->extn.crc, "crc "),
198 IS_AVAIL2(1, "swape", CONFIG_ARC_HAS_SWAPE));
158 199
159static const struct id_to_str mul_type_nm[] = { 200 if (cpu->bpu.ver)
160 { 0x0, "N/A"}, 201 n += scnprintf(buf + n, len - n,
161 { 0x1, "32x32 (spl Result Reg)" }, 202 "BPU\t\t: %s%s match, cache:%d, Predict Table:%d\n",
162 { 0x2, "32x32 (ANY Result Reg)" } 203 IS_AVAIL1(cpu->bpu.full, "full"),
163}; 204 IS_AVAIL1(!cpu->bpu.full, "partial"),
205 cpu->bpu.num_cache, cpu->bpu.num_pred);
164 206
165static const struct id_to_str mac_mul_nm[] = { 207 return buf;
166 {0x0, "N/A"}, 208}
167 {0x1, "N/A"},
168 {0x2, "Dual 16 x 16"},
169 {0x3, "N/A"},
170 {0x4, "32x16"},
171 {0x5, "N/A"},
172 {0x6, "Dual 16x16 and 32x16"}
173};
174 209
175static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len) 210static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
176{ 211{
@@ -178,67 +213,46 @@ static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
178 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; 213 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
179 214
180 FIX_PTR(cpu); 215 FIX_PTR(cpu);
181#define IS_AVAIL1(var, str) ((var) ? str : "")
182#define IS_AVAIL2(var, str) ((var == 0x2) ? str : "")
183#define IS_USED(cfg) (IS_ENABLED(cfg) ? "(in-use)" : "(not used)")
184 216
185 n += scnprintf(buf + n, len - n, 217 n += scnprintf(buf + n, len - n,
186 "Extn [700-Base]\t: %s %s %s %s %s %s\n", 218 "Vector Table\t: %#x\nUncached Base\t: %#x\n",
187 IS_AVAIL2(cpu->extn.norm, "norm,"), 219 cpu->vec_base, cpu->uncached_base);
188 IS_AVAIL2(cpu->extn.barrel, "barrel-shift,"), 220
189 IS_AVAIL1(cpu->extn.swap, "swap,"), 221 if (cpu->extn.fpu_sp || cpu->extn.fpu_dp)
190 IS_AVAIL2(cpu->extn.minmax, "minmax,"), 222 n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n",
191 IS_AVAIL1(cpu->extn.crc, "crc,"), 223 IS_AVAIL1(cpu->extn.fpu_sp, "SP "),
192 IS_AVAIL2(cpu->extn.ext_arith, "ext-arith")); 224 IS_AVAIL1(cpu->extn.fpu_dp, "DP "));
193 225
194 n += scnprintf(buf + n, len - n, "Extn [700-MPY]\t: %s", 226 if (cpu->extn.debug)
195 mul_type_nm[cpu->extn.mul].str); 227 n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s%s\n",
196 228 IS_AVAIL1(cpu->extn.ap, "ActionPoint "),
197 n += scnprintf(buf + n, len - n, " MAC MPY: %s\n", 229 IS_AVAIL1(cpu->extn.smart, "smaRT "),
198 mac_mul_nm[cpu->extn_mac_mul.type].str); 230 IS_AVAIL1(cpu->extn.rtt, "RTT "));
199 231
200 if (cpu->core.family == 0x34) { 232 if (cpu->dccm.sz || cpu->iccm.sz)
201 n += scnprintf(buf + n, len - n, 233 n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n",
202 "Extn [700-4.10]\t: LLOCK/SCOND %s, SWAPE %s, RTSC %s\n", 234 cpu->dccm.base_addr, TO_KB(cpu->dccm.sz),
203 IS_USED(CONFIG_ARC_HAS_LLSC),
204 IS_USED(CONFIG_ARC_HAS_SWAPE),
205 IS_USED(CONFIG_ARC_HAS_RTSC));
206 }
207
208 n += scnprintf(buf + n, len - n, "Extn [CCM]\t: %s",
209 !(cpu->dccm.sz || cpu->iccm.sz) ? "N/A" : "");
210
211 if (cpu->dccm.sz)
212 n += scnprintf(buf + n, len - n, "DCCM: @ %x, %d KB ",
213 cpu->dccm.base_addr, TO_KB(cpu->dccm.sz));
214
215 if (cpu->iccm.sz)
216 n += scnprintf(buf + n, len - n, "ICCM: @ %x, %d KB",
217 cpu->iccm.base_addr, TO_KB(cpu->iccm.sz)); 235 cpu->iccm.base_addr, TO_KB(cpu->iccm.sz));
218 236
219 n += scnprintf(buf + n, len - n, "\nExtn [FPU]\t: %s",
220 !(cpu->fp.ver || cpu->dpfp.ver) ? "N/A" : "");
221
222 if (cpu->fp.ver)
223 n += scnprintf(buf + n, len - n, "SP [v%d] %s",
224 cpu->fp.ver, cpu->fp.fast ? "(fast)" : "");
225
226 if (cpu->dpfp.ver)
227 n += scnprintf(buf + n, len - n, "DP [v%d] %s",
228 cpu->dpfp.ver, cpu->dpfp.fast ? "(fast)" : "");
229
230 n += scnprintf(buf + n, len - n, "\n");
231
232 n += scnprintf(buf + n, len - n, 237 n += scnprintf(buf + n, len - n,
233 "OS ABI [v3]\t: no-legacy-syscalls\n"); 238 "OS ABI [v3]\t: no-legacy-syscalls\n");
234 239
235 return buf; 240 return buf;
236} 241}
237 242
238static void arc_chk_ccms(void) 243static void arc_chk_core_config(void)
239{ 244{
240#if defined(CONFIG_ARC_HAS_DCCM) || defined(CONFIG_ARC_HAS_ICCM)
241 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; 245 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
246 int fpu_enabled;
247
248 if (!cpu->timers.t0)
249 panic("Timer0 is not present!\n");
250
251 if (!cpu->timers.t1)
252 panic("Timer1 is not present!\n");
253
254 if (IS_ENABLED(CONFIG_ARC_HAS_RTSC) && !cpu->timers.rtsc)
255 panic("RTSC is not present\n");
242 256
243#ifdef CONFIG_ARC_HAS_DCCM 257#ifdef CONFIG_ARC_HAS_DCCM
244 /* 258 /*
@@ -256,33 +270,20 @@ static void arc_chk_ccms(void)
256 if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz) 270 if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz)
257 panic("Linux built with incorrect ICCM Size\n"); 271 panic("Linux built with incorrect ICCM Size\n");
258#endif 272#endif
259#endif
260}
261 273
262/* 274 /*
263 * Ensure that FP hardware and kernel config match 275 * FP hardware/software config sanity
264 * -If hardware contains DPFP, kernel needs to save/restore FPU state 276 * -If hardware contains DPFP, kernel needs to save/restore FPU state
265 * across context switches 277 * -If not, it will crash trying to save/restore the non-existant regs
266 * -If hardware lacks DPFP, but kernel configured to save FPU state then 278 *
267 * kernel trying to access non-existant DPFP regs will crash 279 * (only DPDP checked since SP has no arch visible regs)
268 * 280 */
269 * We only check for Dbl precision Floating Point, because only DPFP 281 fpu_enabled = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE);
270 * hardware has dedicated regs which need to be saved/restored on ctx-sw
271 * (Single Precision uses core regs), thus kernel is kind of oblivious to it
272 */
273static void arc_chk_fpu(void)
274{
275 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
276 282
277 if (cpu->dpfp.ver) { 283 if (cpu->extn.fpu_dp && !fpu_enabled)
278#ifndef CONFIG_ARC_FPU_SAVE_RESTORE 284 pr_warn("CONFIG_ARC_FPU_SAVE_RESTORE needed for working apps\n");
279 pr_warn("DPFP support broken in this kernel...\n"); 285 else if (!cpu->extn.fpu_dp && fpu_enabled)
280#endif 286 panic("FPU non-existent, disable CONFIG_ARC_FPU_SAVE_RESTORE\n");
281 } else {
282#ifdef CONFIG_ARC_FPU_SAVE_RESTORE
283 panic("H/w lacks DPFP support, apps won't work\n");
284#endif
285 }
286} 287}
287 288
288/* 289/*
@@ -303,15 +304,11 @@ void setup_processor(void)
303 304
304 arc_mmu_init(); 305 arc_mmu_init();
305 arc_cache_init(); 306 arc_cache_init();
306 arc_chk_ccms();
307 307
308 printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str))); 308 printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
309
310#ifdef CONFIG_SMP
311 printk(arc_platform_smp_cpuinfo()); 309 printk(arc_platform_smp_cpuinfo());
312#endif
313 310
314 arc_chk_fpu(); 311 arc_chk_core_config();
315} 312}
316 313
317static inline int is_kernel(unsigned long addr) 314static inline int is_kernel(unsigned long addr)
@@ -360,11 +357,7 @@ void __init setup_arch(char **cmdline_p)
360 machine_desc->init_early(); 357 machine_desc->init_early();
361 358
362 setup_processor(); 359 setup_processor();
363
364#ifdef CONFIG_SMP
365 smp_init_cpus(); 360 smp_init_cpus();
366#endif
367
368 setup_arch_memory(); 361 setup_arch_memory();
369 362
370 /* copy flat DT out of .init and then unflatten it */ 363 /* copy flat DT out of .init and then unflatten it */
@@ -385,7 +378,13 @@ void __init setup_arch(char **cmdline_p)
385 378
386static int __init customize_machine(void) 379static int __init customize_machine(void)
387{ 380{
388 /* Add platform devices */ 381 of_clk_init(NULL);
382 /*
383 * Traverses flattened DeviceTree - registering platform devices
384 * (if any) complete with their resources
385 */
386 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
387
389 if (machine_desc->init_machine) 388 if (machine_desc->init_machine)
390 machine_desc->init_machine(); 389 machine_desc->init_machine();
391 390
@@ -419,19 +418,14 @@ static int show_cpuinfo(struct seq_file *m, void *v)
419 418
420 seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE)); 419 seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE));
421 420
422 seq_printf(m, "Bogo MIPS : \t%lu.%02lu\n", 421 seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n",
423 loops_per_jiffy / (500000 / HZ), 422 loops_per_jiffy / (500000 / HZ),
424 (loops_per_jiffy / (5000 / HZ)) % 100); 423 (loops_per_jiffy / (5000 / HZ)) % 100);
425 424
426 seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE)); 425 seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE));
427
428 seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE)); 426 seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE));
429
430 seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE)); 427 seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE));
431
432#ifdef CONFIG_SMP
433 seq_printf(m, arc_platform_smp_cpuinfo()); 428 seq_printf(m, arc_platform_smp_cpuinfo());
434#endif
435 429
436 free_page((unsigned long)str); 430 free_page((unsigned long)str);
437done: 431done:
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index dcd317c47d09..d01df0c517a2 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -101,7 +101,7 @@ void __weak arc_platform_smp_wait_to_boot(int cpu)
101 101
102const char *arc_platform_smp_cpuinfo(void) 102const char *arc_platform_smp_cpuinfo(void)
103{ 103{
104 return plat_smp_ops.info; 104 return plat_smp_ops.info ? : "";
105} 105}
106 106
107/* 107/*
diff --git a/arch/arc/mm/cache_arc700.c b/arch/arc/mm/cache_arc700.c
index 9e1142729fd1..8c3a3e02ba92 100644
--- a/arch/arc/mm/cache_arc700.c
+++ b/arch/arc/mm/cache_arc700.c
@@ -530,16 +530,9 @@ EXPORT_SYMBOL(dma_cache_wback);
530 */ 530 */
531void flush_icache_range(unsigned long kstart, unsigned long kend) 531void flush_icache_range(unsigned long kstart, unsigned long kend)
532{ 532{
533 unsigned int tot_sz, off, sz; 533 unsigned int tot_sz;
534 unsigned long phy, pfn;
535 534
536 /* printk("Kernel Cache Cohenercy: %lx to %lx\n",kstart, kend); */ 535 WARN(kstart < TASK_SIZE, "%s() can't handle user vaddr", __func__);
537
538 /* This is not the right API for user virtual address */
539 if (kstart < TASK_SIZE) {
540 BUG_ON("Flush icache range for user virtual addr space");
541 return;
542 }
543 536
544 /* Shortcut for bigger flush ranges. 537 /* Shortcut for bigger flush ranges.
545 * Here we don't care if this was kernel virtual or phy addr 538 * Here we don't care if this was kernel virtual or phy addr
@@ -572,6 +565,9 @@ void flush_icache_range(unsigned long kstart, unsigned long kend)
572 * straddles across 2 virtual pages and hence need for loop 565 * straddles across 2 virtual pages and hence need for loop
573 */ 566 */
574 while (tot_sz > 0) { 567 while (tot_sz > 0) {
568 unsigned int off, sz;
569 unsigned long phy, pfn;
570
575 off = kstart % PAGE_SIZE; 571 off = kstart % PAGE_SIZE;
576 pfn = vmalloc_to_pfn((void *)kstart); 572 pfn = vmalloc_to_pfn((void *)kstart);
577 phy = (pfn << PAGE_SHIFT) + off; 573 phy = (pfn << PAGE_SHIFT) + off;
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index e1acf0ce5647..7f47d2a56f44 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -609,14 +609,12 @@ char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
609 int n = 0; 609 int n = 0;
610 struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu; 610 struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu;
611 611
612 n += scnprintf(buf + n, len - n, "ARC700 MMU [v%x]\t: %dk PAGE, ",
613 p_mmu->ver, TO_KB(p_mmu->pg_sz));
614
615 n += scnprintf(buf + n, len - n, 612 n += scnprintf(buf + n, len - n,
616 "J-TLB %d (%dx%d), uDTLB %d, uITLB %d, %s\n", 613 "MMU [v%x]\t: %dk PAGE, JTLB %d (%dx%d), uDTLB %d, uITLB %d %s\n",
614 p_mmu->ver, TO_KB(p_mmu->pg_sz),
617 p_mmu->num_tlb, p_mmu->sets, p_mmu->ways, 615 p_mmu->num_tlb, p_mmu->sets, p_mmu->ways,
618 p_mmu->u_dtlb, p_mmu->u_itlb, 616 p_mmu->u_dtlb, p_mmu->u_itlb,
619 IS_ENABLED(CONFIG_ARC_MMU_SASID) ? "SASID" : ""); 617 IS_ENABLED(CONFIG_ARC_MMU_SASID) ? ",SASID" : "");
620 618
621 return buf; 619 return buf;
622} 620}
diff --git a/arch/arc/plat-arcfpga/Kconfig b/arch/arc/plat-arcfpga/Kconfig
index b9f34cf55acf..217593a70751 100644
--- a/arch/arc/plat-arcfpga/Kconfig
+++ b/arch/arc/plat-arcfpga/Kconfig
@@ -8,7 +8,7 @@
8 8
9menuconfig ARC_PLAT_FPGA_LEGACY 9menuconfig ARC_PLAT_FPGA_LEGACY
10 bool "\"Legacy\" ARC FPGA dev Boards" 10 bool "\"Legacy\" ARC FPGA dev Boards"
11 select ISS_SMP_EXTN if SMP 11 select ARC_HAS_COH_CACHES if SMP
12 help 12 help
13 Support for ARC development boards, provided by Synopsys. 13 Support for ARC development boards, provided by Synopsys.
14 These are based on FPGA or ISS. e.g. 14 These are based on FPGA or ISS. e.g.
@@ -18,17 +18,6 @@ menuconfig ARC_PLAT_FPGA_LEGACY
18 18
19if ARC_PLAT_FPGA_LEGACY 19if ARC_PLAT_FPGA_LEGACY
20 20
21config ARC_BOARD_ANGEL4
22 bool "ARC Angel4"
23 default y
24 help
25 ARC Angel4 FPGA Ref Platform (Xilinx Virtex Based)
26
27config ARC_BOARD_ML509
28 bool "ML509"
29 help
30 ARC ML509 FPGA Ref Platform (Xilinx Virtex-5 Based)
31
32config ISS_SMP_EXTN 21config ISS_SMP_EXTN
33 bool "ARC SMP Extensions (ISS Models only)" 22 bool "ARC SMP Extensions (ISS Models only)"
34 default n 23 default n
diff --git a/arch/arc/plat-arcfpga/include/plat/irq.h b/arch/arc/plat-arcfpga/include/plat/irq.h
deleted file mode 100644
index 2c9dea690ac4..000000000000
--- a/arch/arc/plat-arcfpga/include/plat/irq.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * vineetg: Feb 2009
9 * -For AA4 board, IRQ assignments to peripherals
10 */
11
12#ifndef __PLAT_IRQ_H
13#define __PLAT_IRQ_H
14
15#define UART0_IRQ 5
16#define UART1_IRQ 10
17#define UART2_IRQ 11
18
19#define IDE_IRQ 13
20#define PCI_IRQ 14
21#define PS2_IRQ 15
22
23#ifdef CONFIG_SMP
24#define IDU_INTERRUPT_0 16
25#endif
26
27#endif
diff --git a/arch/arc/plat-arcfpga/include/plat/memmap.h b/arch/arc/plat-arcfpga/include/plat/memmap.h
deleted file mode 100644
index 5c78e6135a1f..000000000000
--- a/arch/arc/plat-arcfpga/include/plat/memmap.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * vineetg: Feb 2009
9 * -For AA4 board, System Memory Map for Peripherals etc
10 */
11
12#ifndef __PLAT_MEMMAP_H
13#define __PLAT_MEMMAP_H
14
15#define UART0_BASE 0xC0FC1000
16#define UART1_BASE 0xC0FC1100
17
18#define IDE_CONTROLLER_BASE 0xC0FC9000
19
20#define AHB_PCI_HOST_BRG_BASE 0xC0FD0000
21
22#define PGU_BASEADDR 0xC0FC8000
23#define VLCK_ADDR 0xC0FCF028
24
25#define BVCI_LAT_UNIT_BASE 0xC0FED000
26
27#define PS2_BASE_ADDR 0xC0FCC000
28
29#endif
diff --git a/arch/arc/plat-arcfpga/platform.c b/arch/arc/plat-arcfpga/platform.c
index 1038949a99a1..afc88254acc1 100644
--- a/arch/arc/plat-arcfpga/platform.c
+++ b/arch/arc/plat-arcfpga/platform.c
@@ -8,37 +8,9 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#include <linux/types.h>
12#include <linux/init.h> 11#include <linux/init.h>
13#include <linux/device.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/console.h>
17#include <linux/of_platform.h>
18#include <asm/setup.h>
19#include <asm/clk.h>
20#include <asm/mach_desc.h> 12#include <asm/mach_desc.h>
21#include <plat/memmap.h>
22#include <plat/smp.h> 13#include <plat/smp.h>
23#include <plat/irq.h>
24
25static void __init plat_fpga_early_init(void)
26{
27 pr_info("[plat-arcfpga]: registering early dev resources\n");
28
29#ifdef CONFIG_ISS_SMP_EXTN
30 iss_model_init_early_smp();
31#endif
32}
33
34static void __init plat_fpga_populate_dev(void)
35{
36 /*
37 * Traverses flattened DeviceTree - registering platform devices
38 * (if any) complete with their resources
39 */
40 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
41}
42 14
43/*----------------------- Machine Descriptions ------------------------------ 15/*----------------------- Machine Descriptions ------------------------------
44 * 16 *
@@ -48,41 +20,26 @@ static void __init plat_fpga_populate_dev(void)
48 * callback set, by matching the DT compatible name. 20 * callback set, by matching the DT compatible name.
49 */ 21 */
50 22
51static const char *aa4_compat[] __initconst = { 23static const char *legacy_fpga_compat[] __initconst = {
52 "snps,arc-angel4", 24 "snps,arc-angel4",
53 NULL,
54};
55
56MACHINE_START(ANGEL4, "angel4")
57 .dt_compat = aa4_compat,
58 .init_early = plat_fpga_early_init,
59 .init_machine = plat_fpga_populate_dev,
60#ifdef CONFIG_ISS_SMP_EXTN
61 .init_smp = iss_model_init_smp,
62#endif
63MACHINE_END
64
65static const char *ml509_compat[] __initconst = {
66 "snps,arc-ml509", 25 "snps,arc-ml509",
67 NULL, 26 NULL,
68}; 27};
69 28
70MACHINE_START(ML509, "ml509") 29MACHINE_START(LEGACY_FPGA, "legacy_fpga")
71 .dt_compat = ml509_compat, 30 .dt_compat = legacy_fpga_compat,
72 .init_early = plat_fpga_early_init, 31#ifdef CONFIG_ISS_SMP_EXTN
73 .init_machine = plat_fpga_populate_dev, 32 .init_early = iss_model_init_early_smp,
74#ifdef CONFIG_SMP
75 .init_smp = iss_model_init_smp, 33 .init_smp = iss_model_init_smp,
76#endif 34#endif
77MACHINE_END 35MACHINE_END
78 36
79static const char *nsimosci_compat[] __initconst = { 37static const char *simulation_compat[] __initconst = {
38 "snps,nsim",
80 "snps,nsimosci", 39 "snps,nsimosci",
81 NULL, 40 NULL,
82}; 41};
83 42
84MACHINE_START(NSIMOSCI, "nsimosci") 43MACHINE_START(SIMULATION, "simulation")
85 .dt_compat = nsimosci_compat, 44 .dt_compat = simulation_compat,
86 .init_early = NULL,
87 .init_machine = plat_fpga_populate_dev,
88MACHINE_END 45MACHINE_END
diff --git a/arch/arc/plat-arcfpga/smp.c b/arch/arc/plat-arcfpga/smp.c
index 92bad9122077..64797ba3bbe3 100644
--- a/arch/arc/plat-arcfpga/smp.c
+++ b/arch/arc/plat-arcfpga/smp.c
@@ -13,9 +13,10 @@
13 13
14#include <linux/smp.h> 14#include <linux/smp.h>
15#include <linux/irq.h> 15#include <linux/irq.h>
16#include <plat/irq.h>
17#include <plat/smp.h> 16#include <plat/smp.h>
18 17
18#define IDU_INTERRUPT_0 16
19
19static char smp_cpuinfo_buf[128]; 20static char smp_cpuinfo_buf[128];
20 21
21/* 22/*
diff --git a/arch/arc/plat-tb10x/Kconfig b/arch/arc/plat-tb10x/Kconfig
index 6994c188dc88..d14b3d3c5dfd 100644
--- a/arch/arc/plat-tb10x/Kconfig
+++ b/arch/arc/plat-tb10x/Kconfig
@@ -18,7 +18,6 @@
18 18
19menuconfig ARC_PLAT_TB10X 19menuconfig ARC_PLAT_TB10X
20 bool "Abilis TB10x" 20 bool "Abilis TB10x"
21 select COMMON_CLK
22 select PINCTRL 21 select PINCTRL
23 select PINCTRL_TB10X 22 select PINCTRL_TB10X
24 select PINMUX 23 select PINMUX
diff --git a/arch/arc/plat-tb10x/tb10x.c b/arch/arc/plat-tb10x/tb10x.c
index 06cb30929460..da0ac0960a4b 100644
--- a/arch/arc/plat-tb10x/tb10x.c
+++ b/arch/arc/plat-tb10x/tb10x.c
@@ -19,21 +19,9 @@
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 20 */
21 21
22
23#include <linux/init.h> 22#include <linux/init.h>
24#include <linux/of_platform.h>
25#include <linux/clk-provider.h>
26#include <linux/pinctrl/consumer.h>
27
28#include <asm/mach_desc.h> 23#include <asm/mach_desc.h>
29 24
30
31static void __init tb10x_platform_init(void)
32{
33 of_clk_init(NULL);
34 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
35}
36
37static const char *tb10x_compat[] __initdata = { 25static const char *tb10x_compat[] __initdata = {
38 "abilis,arc-tb10x", 26 "abilis,arc-tb10x",
39 NULL, 27 NULL,
@@ -41,5 +29,4 @@ static const char *tb10x_compat[] __initdata = {
41 29
42MACHINE_START(TB10x, "tb10x") 30MACHINE_START(TB10x, "tb10x")
43 .dt_compat = tb10x_compat, 31 .dt_compat = tb10x_compat,
44 .init_machine = tb10x_platform_init,
45MACHINE_END 32MACHINE_END
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0e4839ea6cc1..b242f82637c5 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -54,8 +54,12 @@ dtb-$(CONFIG_ARCH_AT91) += at91-sama5d4ek.dtb
54dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb 54dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
55dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb 55dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
56dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb 56dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
57dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b-plus.dtb
57dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb 58dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
58dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb 59dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
60dtb-$(CONFIG_ARCH_BCM_CYGNUS) += bcm911360_entphn.dtb \
61 bcm911360k.dtb \
62 bcm958300k.dtb
59dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ 63dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
60 bcm21664-garnet.dtb 64 bcm21664-garnet.dtb
61dtb-$(CONFIG_ARCH_BERLIN) += \ 65dtb-$(CONFIG_ARCH_BERLIN) += \
@@ -107,6 +111,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
107 kirkwood-d2net.dtb \ 111 kirkwood-d2net.dtb \
108 kirkwood-db-88f6281.dtb \ 112 kirkwood-db-88f6281.dtb \
109 kirkwood-db-88f6282.dtb \ 113 kirkwood-db-88f6282.dtb \
114 kirkwood-dir665.dtb \
110 kirkwood-dns320.dtb \ 115 kirkwood-dns320.dtb \
111 kirkwood-dns325.dtb \ 116 kirkwood-dns325.dtb \
112 kirkwood-dockstar.dtb \ 117 kirkwood-dockstar.dtb \
@@ -277,7 +282,8 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
277 imx28-m28evk.dtb \ 282 imx28-m28evk.dtb \
278 imx28-sps1.dtb \ 283 imx28-sps1.dtb \
279 imx28-tx28.dtb 284 imx28-tx28.dtb
280dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb 285dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb \
286 ste-nomadik-nhk15.dtb
281dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \ 287dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \
282 nspire-tp.dtb \ 288 nspire-tp.dtb \
283 nspire-clp.dtb 289 nspire-clp.dtb
@@ -305,7 +311,9 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
305 omap3-ha.dtb \ 311 omap3-ha.dtb \
306 omap3-ha-lcd.dtb \ 312 omap3-ha-lcd.dtb \
307 omap3-igep0020.dtb \ 313 omap3-igep0020.dtb \
314 omap3-igep0020-rev-f.dtb \
308 omap3-igep0030.dtb \ 315 omap3-igep0030.dtb \
316 omap3-igep0030-rev-g.dtb \
309 omap3-ldp.dtb \ 317 omap3-ldp.dtb \
310 omap3-lilly-dbb056.dtb \ 318 omap3-lilly-dbb056.dtb \
311 omap3-n900.dtb \ 319 omap3-n900.dtb \
@@ -350,6 +358,7 @@ dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \
350 omap5-sbc-t54.dtb \ 358 omap5-sbc-t54.dtb \
351 omap5-uevm.dtb 359 omap5-uevm.dtb
352dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \ 360dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \
361 am57xx-beagle-x15.dtb \
353 dra72-evm.dtb 362 dra72-evm.dtb
354dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \ 363dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \
355 orion5x-lacie-ethernet-disk-mini-v2.dtb \ 364 orion5x-lacie-ethernet-disk-mini-v2.dtb \
@@ -366,8 +375,10 @@ dtb-$(CONFIG_ARCH_QCOM) += \
366 qcom-msm8660-surf.dtb \ 375 qcom-msm8660-surf.dtb \
367 qcom-msm8960-cdp.dtb \ 376 qcom-msm8960-cdp.dtb \
368 qcom-msm8974-sony-xperia-honami.dtb 377 qcom-msm8974-sony-xperia-honami.dtb
378dtb-$(CONFIG_ARCH_REALVIEW) += arm-realview-pb1176.dtb
369dtb-$(CONFIG_ARCH_ROCKCHIP) += \ 379dtb-$(CONFIG_ARCH_ROCKCHIP) += \
370 rk3066a-bqcurie2.dtb \ 380 rk3066a-bqcurie2.dtb \
381 rk3066a-marsboard.dtb \
371 rk3188-radxarock.dtb \ 382 rk3188-radxarock.dtb \
372 rk3288-evb-act8846.dtb \ 383 rk3288-evb-act8846.dtb \
373 rk3288-evb-rk808.dtb 384 rk3288-evb-rk808.dtb
@@ -379,27 +390,28 @@ dtb-$(CONFIG_ARCH_S5PV210) += s5pv210-aquila.dtb \
379 s5pv210-smdkc110.dtb \ 390 s5pv210-smdkc110.dtb \
380 s5pv210-smdkv210.dtb \ 391 s5pv210-smdkv210.dtb \
381 s5pv210-torbreck.dtb 392 s5pv210-torbreck.dtb
382dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \ 393dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
394 r8a73a4-ape6evm.dtb \
395 r8a73a4-ape6evm-reference.dtb \
383 r8a7740-armadillo800eva.dtb \ 396 r8a7740-armadillo800eva.dtb \
384 r8a7778-bockw.dtb \ 397 r8a7778-bockw.dtb \
385 r8a7778-bockw-reference.dtb \ 398 r8a7778-bockw-reference.dtb \
386 r8a7779-marzen.dtb \ 399 r8a7779-marzen.dtb \
387 r8a7791-koelsch.dtb \
388 r8a7790-lager.dtb \ 400 r8a7790-lager.dtb \
401 r8a7791-koelsch.dtb \
402 sh7372-mackerel.dtb \
389 sh73a0-kzm9g.dtb \ 403 sh73a0-kzm9g.dtb \
390 sh73a0-kzm9g-reference.dtb \ 404 sh73a0-kzm9g-reference.dtb
391 r8a73a4-ape6evm.dtb \
392 r8a73a4-ape6evm-reference.dtb \
393 sh7372-mackerel.dtb
394dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \ 405dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
395 r7s72100-genmai.dtb \ 406 r7s72100-genmai.dtb \
396 r8a7740-armadillo800eva.dtb \ 407 r8a7740-armadillo800eva.dtb \
408 r8a7779-marzen.dtb \
409 r8a7790-lager.dtb \
397 r8a7791-henninger.dtb \ 410 r8a7791-henninger.dtb \
398 r8a7791-koelsch.dtb \ 411 r8a7791-koelsch.dtb \
399 r8a7790-lager.dtb \
400 r8a7779-marzen.dtb \
401 r8a7794-alt.dtb 412 r8a7794-alt.dtb
402dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ 413dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
414 socfpga_arria10_socdk.dtb \
403 socfpga_cyclone5_socdk.dtb \ 415 socfpga_cyclone5_socdk.dtb \
404 socfpga_cyclone5_sockit.dtb \ 416 socfpga_cyclone5_sockit.dtb \
405 socfpga_cyclone5_socrates.dtb \ 417 socfpga_cyclone5_socrates.dtb \
@@ -412,6 +424,7 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
412 spear320-hmi.dtb 424 spear320-hmi.dtb
413dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb 425dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
414dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \ 426dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \
427 stih410-b2120.dtb \
415 stih415-b2000.dtb \ 428 stih415-b2000.dtb \
416 stih415-b2020.dtb \ 429 stih415-b2020.dtb \
417 stih416-b2000.dtb \ 430 stih416-b2000.dtb \
@@ -438,15 +451,20 @@ dtb-$(CONFIG_MACH_SUN6I) += \
438 sun6i-a31-hummingbird.dtb \ 451 sun6i-a31-hummingbird.dtb \
439 sun6i-a31-m9.dtb 452 sun6i-a31-m9.dtb
440dtb-$(CONFIG_MACH_SUN7I) += \ 453dtb-$(CONFIG_MACH_SUN7I) += \
454 sun7i-a20-bananapi.dtb \
441 sun7i-a20-cubieboard2.dtb \ 455 sun7i-a20-cubieboard2.dtb \
442 sun7i-a20-cubietruck.dtb \ 456 sun7i-a20-cubietruck.dtb \
443 sun7i-a20-hummingbird.dtb \ 457 sun7i-a20-hummingbird.dtb \
444 sun7i-a20-i12-tvbox.dtb \ 458 sun7i-a20-i12-tvbox.dtb \
459 sun7i-a20-m3.dtb \
445 sun7i-a20-olinuxino-lime.dtb \ 460 sun7i-a20-olinuxino-lime.dtb \
461 sun7i-a20-olinuxino-lime2.dtb \
446 sun7i-a20-olinuxino-micro.dtb \ 462 sun7i-a20-olinuxino-micro.dtb \
447 sun7i-a20-pcduino3.dtb 463 sun7i-a20-pcduino3.dtb
448dtb-$(CONFIG_MACH_SUN8I) += \ 464dtb-$(CONFIG_MACH_SUN8I) += \
449 sun8i-a23-ippo-q8h-v5.dtb 465 sun8i-a23-ippo-q8h-v5.dtb
466dtb-$(CONFIG_MACH_SUN9I) += \
467 sun9i-a80-optimus.dtb
450dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ 468dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
451 tegra20-iris-512.dtb \ 469 tegra20-iris-512.dtb \
452 tegra20-medcom-wide.dtb \ 470 tegra20-medcom-wide.dtb \
@@ -518,7 +536,10 @@ dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
518 dove-d2plug.dtb \ 536 dove-d2plug.dtb \
519 dove-d3plug.dtb \ 537 dove-d3plug.dtb \
520 dove-dove-db.dtb 538 dove-dove-db.dtb
521dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb 539dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb \
540 mt6592-evb.dtb \
541 mt8127-moose.dtb \
542 mt8135-evbp1.dtb
522 543
523targets += dtbs dtbs_install 544targets += dtbs dtbs_install
524targets += $(dtb-y) 545targets += $(dtb-y)
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index e2156a583de7..43a536c08c9f 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -437,9 +437,9 @@
437 status = "okay"; 437 status = "okay";
438 pinctrl-names = "default"; 438 pinctrl-names = "default";
439 pinctrl-0 = <&nandflash_pins_s0>; 439 pinctrl-0 = <&nandflash_pins_s0>;
440 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ 440 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
441 nand@0,0 { 441 nand@0,0 {
442 reg = <0 0 0>; /* CS0, offset 0 */ 442 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
443 ti,nand-ecc-opt = "bch8"; 443 ti,nand-ecc-opt = "bch8";
444 ti,elm-id = <&elm>; 444 ti,elm-id = <&elm>;
445 nand-bus-width = <8>; 445 nand-bus-width = <8>;
diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi
index a1a0cc5eb35c..c0e1135256cc 100644
--- a/arch/arm/boot/dts/am335x-igep0033.dtsi
+++ b/arch/arm/boot/dts/am335x-igep0033.dtsi
@@ -126,10 +126,10 @@
126 pinctrl-names = "default"; 126 pinctrl-names = "default";
127 pinctrl-0 = <&nandflash_pins>; 127 pinctrl-0 = <&nandflash_pins>;
128 128
129 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ 129 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
130 130
131 nand@0,0 { 131 nand@0,0 {
132 reg = <0 0 0>; /* CS0, offset 0 */ 132 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
133 nand-bus-width = <8>; 133 nand-bus-width = <8>;
134 ti,nand-ecc-opt = "bch8"; 134 ti,nand-ecc-opt = "bch8";
135 gpmc,device-width = <1>; 135 gpmc,device-width = <1>;
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 831810583823..62bf053d2cb8 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -204,6 +204,8 @@
204 reg = <0x44e09000 0x2000>; 204 reg = <0x44e09000 0x2000>;
205 interrupts = <72>; 205 interrupts = <72>;
206 status = "disabled"; 206 status = "disabled";
207 dmas = <&edma 26>, <&edma 27>;
208 dma-names = "tx", "rx";
207 }; 209 };
208 210
209 uart1: serial@48022000 { 211 uart1: serial@48022000 {
@@ -213,6 +215,8 @@
213 reg = <0x48022000 0x2000>; 215 reg = <0x48022000 0x2000>;
214 interrupts = <73>; 216 interrupts = <73>;
215 status = "disabled"; 217 status = "disabled";
218 dmas = <&edma 28>, <&edma 29>;
219 dma-names = "tx", "rx";
216 }; 220 };
217 221
218 uart2: serial@48024000 { 222 uart2: serial@48024000 {
@@ -222,6 +226,8 @@
222 reg = <0x48024000 0x2000>; 226 reg = <0x48024000 0x2000>;
223 interrupts = <74>; 227 interrupts = <74>;
224 status = "disabled"; 228 status = "disabled";
229 dmas = <&edma 30>, <&edma 31>;
230 dma-names = "tx", "rx";
225 }; 231 };
226 232
227 uart3: serial@481a6000 { 233 uart3: serial@481a6000 {
@@ -356,6 +362,7 @@
356 reg = <0x480C8000 0x200>; 362 reg = <0x480C8000 0x200>;
357 interrupts = <77>; 363 interrupts = <77>;
358 ti,hwmods = "mailbox"; 364 ti,hwmods = "mailbox";
365 #mbox-cells = <1>;
359 ti,mbox-num-users = <4>; 366 ti,mbox-num-users = <4>;
360 ti,mbox-num-fifos = <8>; 367 ti,mbox-num-fifos = <8>;
361 mbox_wkupm3: wkup_m3 { 368 mbox_wkupm3: wkup_m3 {
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 46660ffd2b65..4367f7550183 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -168,6 +168,7 @@
168 reg = <0x480C8000 0x200>; 168 reg = <0x480C8000 0x200>;
169 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 169 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
170 ti,hwmods = "mailbox"; 170 ti,hwmods = "mailbox";
171 #mbox-cells = <1>;
171 ti,mbox-num-users = <4>; 172 ti,mbox-num-users = <4>;
172 ti,mbox-num-fifos = <8>; 173 ti,mbox-num-fifos = <8>;
173 mbox_wkupm3: wkup_m3 { 174 mbox_wkupm3: wkup_m3 {
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index ac3e4859935f..bb4cb8554b4a 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -438,9 +438,9 @@
438 status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ 438 status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */
439 pinctrl-names = "default"; 439 pinctrl-names = "default";
440 pinctrl-0 = <&nand_flash_x8>; 440 pinctrl-0 = <&nand_flash_x8>;
441 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ 441 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
442 nand@0,0 { 442 nand@0,0 {
443 reg = <0 0 0>; /* CS0, offset 0 */ 443 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
444 ti,nand-ecc-opt = "bch16"; 444 ti,nand-ecc-opt = "bch16";
445 ti,elm-id = <&elm>; 445 ti,elm-id = <&elm>;
446 nand-bus-width = <8>; 446 nand-bus-width = <8>;
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
new file mode 100644
index 000000000000..49edbda68cd5
--- /dev/null
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -0,0 +1,405 @@
1/*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "dra74x.dtsi"
11#include <dt-bindings/clk/ti-dra7-atl.h>
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14
15/ {
16 model = "TI AM5728 BeagleBoard-X15";
17 compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
18
19 aliases {
20 rtc0 = &mcp_rtc;
21 rtc1 = &tps659038_rtc;
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0x80000000 0x80000000>;
27 };
28
29 vdd_3v3: fixedregulator-vdd_3v3 {
30 compatible = "regulator-fixed";
31 regulator-name = "vdd_3v3";
32 vin-supply = <&regen1>;
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 };
36
37 vtt_fixed: fixedregulator-vtt {
38 /* TPS51200 */
39 compatible = "regulator-fixed";
40 regulator-name = "vtt_fixed";
41 vin-supply = <&smps3_reg>;
42 regulator-min-microvolt = <3300000>;
43 regulator-max-microvolt = <3300000>;
44 regulator-always-on;
45 regulator-boot-on;
46 enable-active-high;
47 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
48 };
49
50 leds {
51 compatible = "gpio-leds";
52 pinctrl-names = "default";
53 pinctrl-0 = <&leds_pins_default>;
54
55 led@0 {
56 label = "beagle-x15:usr0";
57 gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
58 linux,default-trigger = "heartbeat";
59 default-state = "off";
60 };
61
62 led@1 {
63 label = "beagle-x15:usr1";
64 gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "cpu0";
66 default-state = "off";
67 };
68
69 led@2 {
70 label = "beagle-x15:usr2";
71 gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>;
72 linux,default-trigger = "mmc0";
73 default-state = "off";
74 };
75
76 led@3 {
77 label = "beagle-x15:usr3";
78 gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>;
79 linux,default-trigger = "ide-disk";
80 default-state = "off";
81 };
82 };
83};
84
85&dra7_pmx_core {
86 leds_pins_default: leds_pins_default {
87 pinctrl-single,pins = <
88 0x3a8 (PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */
89 0x3ac (PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */
90 0x3c0 (PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */
91 0x3c4 (PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */
92 >;
93 };
94
95 i2c1_pins_default: i2c1_pins_default {
96 pinctrl-single,pins = <
97 0x400 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */
98 0x404 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */
99 >;
100 };
101
102 i2c3_pins_default: i2c3_pins_default {
103 pinctrl-single,pins = <
104 0x2a4 (PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */
105 0x2a8 (PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */
106 >;
107 };
108
109 uart3_pins_default: uart3_pins_default {
110 pinctrl-single,pins = <
111 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd.rxd */
112 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd.txd */
113 >;
114 };
115
116 mmc1_pins_default: mmc1_pins_default {
117 pinctrl-single,pins = <
118 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
119 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
120 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
121 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
122 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
123 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
124 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
125 >;
126 };
127
128 mmc2_pins_default: mmc2_pins_default {
129 pinctrl-single,pins = <
130 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
131 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
132 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
133 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
134 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
135 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
136 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
137 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
138 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
139 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
140 >;
141 };
142
143 tps659038_pins_default: tps659038_pins_default {
144 pinctrl-single,pins = <
145 0x418 (PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */
146 >;
147 };
148
149 tmp102_pins_default: tmp102_pins_default {
150 pinctrl-single,pins = <
151 0x3C8 (PIN_INPUT_PULLUP | MUX_MODE14) /* spi2_d0.gpio7_16 */
152 >;
153 };
154
155 mcp79410_pins_default: mcp79410_pins_default {
156 pinctrl-single,pins = <
157 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
158 >;
159 };
160
161 usb1_pins: pinmux_usb1_pins {
162 pinctrl-single,pins = <
163 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
164 >;
165 };
166
167};
168
169&i2c1 {
170 status = "okay";
171 pinctrl-names = "default";
172 pinctrl-0 = <&i2c1_pins_default>;
173 clock-frequency = <400000>;
174
175 tps659038: tps659038@58 {
176 compatible = "ti,tps659038";
177 reg = <0x58>;
178 interrupt-parent = <&gpio1>;
179 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
180
181 pinctrl-names = "default";
182 pinctrl-0 = <&tps659038_pins_default>;
183
184 #interrupt-cells = <2>;
185 interrupt-controller;
186
187 ti,system-power-controller;
188
189 tps659038_pmic {
190 compatible = "ti,tps659038-pmic";
191
192 regulators {
193 smps12_reg: smps12 {
194 /* VDD_MPU */
195 regulator-name = "smps12";
196 regulator-min-microvolt = < 850000>;
197 regulator-max-microvolt = <1250000>;
198 regulator-always-on;
199 regulator-boot-on;
200 };
201
202 smps3_reg: smps3 {
203 /* VDD_DDR */
204 regulator-name = "smps3";
205 regulator-min-microvolt = <1350000>;
206 regulator-max-microvolt = <1350000>;
207 regulator-always-on;
208 regulator-boot-on;
209 };
210
211 smps45_reg: smps45 {
212 /* VDD_DSPEVE, VDD_IVA, VDD_GPU */
213 regulator-name = "smps45";
214 regulator-min-microvolt = < 850000>;
215 regulator-max-microvolt = <1150000>;
216 regulator-always-on;
217 regulator-boot-on;
218 };
219
220 smps6_reg: smps6 {
221 /* VDD_CORE */
222 regulator-name = "smps6";
223 regulator-min-microvolt = <850000>;
224 regulator-max-microvolt = <1030000>;
225 regulator-always-on;
226 regulator-boot-on;
227 };
228
229 /* SMPS7 unused */
230
231 smps8_reg: smps8 {
232 /* VDD_1V8 */
233 regulator-name = "smps8";
234 regulator-min-microvolt = <1800000>;
235 regulator-max-microvolt = <1800000>;
236 regulator-always-on;
237 regulator-boot-on;
238 };
239
240 /* SMPS9 unused */
241
242 ldo1_reg: ldo1 {
243 /* VDD_SD */
244 regulator-name = "ldo1";
245 regulator-min-microvolt = <1800000>;
246 regulator-max-microvolt = <3300000>;
247 regulator-boot-on;
248 };
249
250 ldo2_reg: ldo2 {
251 /* VDD_SHV5 */
252 regulator-name = "ldo2";
253 regulator-min-microvolt = <3300000>;
254 regulator-max-microvolt = <3300000>;
255 regulator-always-on;
256 regulator-boot-on;
257 };
258
259 ldo3_reg: ldo3 {
260 /* VDDA_1V8_PHY */
261 regulator-name = "ldo3";
262 regulator-min-microvolt = <1800000>;
263 regulator-max-microvolt = <1800000>;
264 regulator-always-on;
265 regulator-boot-on;
266 };
267
268 ldo9_reg: ldo9 {
269 /* VDD_RTC */
270 regulator-name = "ldo9";
271 regulator-min-microvolt = <1050000>;
272 regulator-max-microvolt = <1050000>;
273 regulator-always-on;
274 regulator-boot-on;
275 };
276
277 ldoln_reg: ldoln {
278 /* VDDA_1V8_PLL */
279 regulator-name = "ldoln";
280 regulator-min-microvolt = <1800000>;
281 regulator-max-microvolt = <1800000>;
282 regulator-always-on;
283 regulator-boot-on;
284 };
285
286 ldousb_reg: ldousb {
287 /* VDDA_3V_USB: VDDA_USBHS33 */
288 regulator-name = "ldousb";
289 regulator-min-microvolt = <3300000>;
290 regulator-max-microvolt = <3300000>;
291 regulator-boot-on;
292 };
293
294 regen1: regen1 {
295 /* VDD_3V3_ON */
296 regulator-name = "regen1";
297 regulator-boot-on;
298 regulator-always-on;
299 };
300 };
301 };
302
303 tps659038_rtc: tps659038_rtc {
304 compatible = "ti,palmas-rtc";
305 interrupt-parent = <&tps659038>;
306 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
307 wakeup-source;
308 };
309
310 tps659038_pwr_button: tps659038_pwr_button {
311 compatible = "ti,palmas-pwrbutton";
312 interrupt-parent = <&tps659038>;
313 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
314 wakeup-source;
315 ti,palmas-long-press-seconds = <12>;
316 };
317 };
318
319 tmp102: tmp102@48 {
320 compatible = "ti,tmp102";
321 reg = <0x48>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&tmp102_pins_default>;
324 interrupt-parent = <&gpio7>;
325 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
326 };
327};
328
329&i2c3 {
330 status = "okay";
331 pinctrl-names = "default";
332 pinctrl-0 = <&i2c3_pins_default>;
333 clock-frequency = <400000>;
334
335 mcp_rtc: rtc@6f {
336 compatible = "microchip,mcp7941x";
337 reg = <0x6f>;
338 interrupt-parent = <&gic>;
339 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>; /* IRQ_SYS_1N */
340
341 pinctrl-names = "default";
342 pinctrl-0 = <&mcp79410_pins_default>;
343
344 vcc-supply = <&vdd_3v3>;
345 wakeup-source;
346 };
347};
348
349&gpio7 {
350 ti,no-reset-on-init;
351 ti,no-idle-on-init;
352};
353
354&cpu0 {
355 cpu0-supply = <&smps12_reg>;
356 voltage-tolerance = <1>;
357};
358
359&uart3 {
360 status = "okay";
361 interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
362 <&dra7_pmx_core 0x248>;
363
364 pinctrl-names = "default";
365 pinctrl-0 = <&uart3_pins_default>;
366};
367
368&mmc1 {
369 status = "okay";
370
371 pinctrl-names = "default";
372 pinctrl-0 = <&mmc1_pins_default>;
373
374 vmmc-supply = <&ldo1_reg>;
375 vmmc_aux-supply = <&vdd_3v3>;
376 pbias-supply = <&pbias_mmc_reg>;
377 bus-width = <4>;
378 cd-gpios = <&gpio6 27 0>; /* gpio 219 */
379};
380
381&mmc2 {
382 status = "okay";
383
384 pinctrl-names = "default";
385 pinctrl-0 = <&mmc2_pins_default>;
386
387 vmmc-supply = <&vdd_3v3>;
388 bus-width = <8>;
389 ti,non-removable;
390 cap-mmc-dual-data-rate;
391};
392
393&sata {
394 status = "okay";
395};
396
397&usb2_phy1 {
398 phy-supply = <&ldousb_reg>;
399};
400
401&usb1 {
402 dr_mode = "host";
403 pinctrl-names = "default";
404 pinctrl-0 = <&usb1_pins>;
405};
diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts
new file mode 100644
index 000000000000..ff26c7ed8c41
--- /dev/null
+++ b/arch/arm/boot/dts/arm-realview-pb1176.dts
@@ -0,0 +1,412 @@
1/*
2 * Copyright 2014 Linaro Ltd
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23/dts-v1/;
24#include <dt-bindings/interrupt-controller/irq.h>
25#include <dt-bindings/gpio/gpio.h>
26#include "skeleton.dtsi"
27
28/ {
29 model = "ARM RealView PB1176";
30 compatible = "arm,realview-pb1176";
31
32 chosen { };
33
34 aliases {
35 serial0 = &pb1176_serial0;
36 serial1 = &pb1176_serial1;
37 serial2 = &pb1176_serial2;
38 serial3 = &pb1176_serial3;
39 serial4 = &fpga_serial;
40 };
41
42 memory {
43 /* 128 MiB memory @ 0x0 */
44 reg = <0x00000000 0x08000000>;
45 };
46
47 /* The voltage to the MMC card is hardwired at 3.3V */
48 vmmc: fixedregulator@0 {
49 compatible = "regulator-fixed";
50 regulator-name = "vmmc";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 regulator-boot-on;
54 };
55
56 xtal24mhz: xtal24mhz@24M {
57 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <24000000>;
60 };
61
62 timclk: timclk@1M {
63 #clock-cells = <0>;
64 compatible = "fixed-factor-clock";
65 clock-div = <24>;
66 clock-mult = <1>;
67 clocks = <&xtal24mhz>;
68 };
69
70 mclk: mclk@24M {
71 #clock-cells = <0>;
72 compatible = "fixed-factor-clock";
73 clock-div = <1>;
74 clock-mult = <1>;
75 clocks = <&xtal24mhz>;
76 };
77
78 kmiclk: kmiclk@24M {
79 #clock-cells = <0>;
80 compatible = "fixed-factor-clock";
81 clock-div = <1>;
82 clock-mult = <1>;
83 clocks = <&xtal24mhz>;
84 };
85
86 sspclk: sspclk@24M {
87 #clock-cells = <0>;
88 compatible = "fixed-factor-clock";
89 clock-div = <1>;
90 clock-mult = <1>;
91 clocks = <&xtal24mhz>;
92 };
93
94 uartclk: uartclk@24M {
95 #clock-cells = <0>;
96 compatible = "fixed-factor-clock";
97 clock-div = <1>;
98 clock-mult = <1>;
99 clocks = <&xtal24mhz>;
100 };
101
102 /* FIXME: this actually hangs off the PLL clocks */
103 pclk: pclk@0 {
104 #clock-cells = <0>;
105 compatible = "fixed-clock";
106 clock-frequency = <0>;
107 };
108
109 soc {
110 #address-cells = <1>;
111 #size-cells = <1>;
112 compatible = "arm,realview-pb1176-soc", "simple-bus";
113 regmap = <&syscon>;
114 ranges;
115
116 syscon: syscon@10000000 {
117 compatible = "arm,realview-pb1176-syscon", "syscon";
118 reg = <0x10000000 0x1000>;
119
120 led@08.0 {
121 compatible = "register-bit-led";
122 offset = <0x08>;
123 mask = <0x01>;
124 label = "versatile:0";
125 linux,default-trigger = "heartbeat";
126 default-state = "on";
127 };
128 led@08.1 {
129 compatible = "register-bit-led";
130 offset = <0x08>;
131 mask = <0x02>;
132 label = "versatile:1";
133 linux,default-trigger = "mmc0";
134 default-state = "off";
135 };
136 led@08.2 {
137 compatible = "register-bit-led";
138 offset = <0x08>;
139 mask = <0x04>;
140 label = "versatile:2";
141 linux,default-trigger = "cpu0";
142 default-state = "off";
143 };
144 led@08.3 {
145 compatible = "register-bit-led";
146 offset = <0x08>;
147 mask = <0x08>;
148 label = "versatile:3";
149 default-state = "off";
150 };
151 led@08.4 {
152 compatible = "register-bit-led";
153 offset = <0x08>;
154 mask = <0x10>;
155 label = "versatile:4";
156 default-state = "off";
157 };
158 led@08.5 {
159 compatible = "register-bit-led";
160 offset = <0x08>;
161 mask = <0x20>;
162 label = "versatile:5";
163 default-state = "off";
164 };
165 led@08.6 {
166 compatible = "register-bit-led";
167 offset = <0x08>;
168 mask = <0x40>;
169 label = "versatile:6";
170 default-state = "off";
171 };
172 led@08.7 {
173 compatible = "register-bit-led";
174 offset = <0x08>;
175 mask = <0x80>;
176 label = "versatile:7";
177 default-state = "off";
178 };
179 };
180
181 /* Primary DevChip GIC synthesized with the CPU */
182 intc_dc1176: interrupt-controller@10120000 {
183 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
184 #interrupt-cells = <3>;
185 #address-cells = <1>;
186 interrupt-controller;
187 reg = <0x10121000 0x1000>,
188 <0x10120000 0x100>;
189 };
190
191 L2: l2-cache {
192 compatible = "arm,l220-cache";
193 reg = <0x10110000 0x1000>;
194 interrupt-parent = <&intc_dc1176>;
195 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
196 cache-unified;
197 cache-level = <2>;
198 /*
199 * Override default cache size, sets and
200 * associativity as these may be erroneously set
201 * up by boot loader(s).
202 */
203 arm,override-auxreg;
204 cache-size = <131072>; // 128kB
205 cache-sets = <512>;
206 cache-line-size = <32>;
207 };
208
209 pmu {
210 compatible = "arm,arm1176-pmu";
211 interrupt-parent = <&intc_dc1176>;
212 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
213 };
214
215 timer01: timer@10104000 {
216 compatible = "arm,sp804", "arm,primecell";
217 reg = <0x10104000 0x1000>;
218 interrupt-parent = <&intc_dc1176>;
219 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&timclk>, <&timclk>, <&pclk>;
221 clock-names = "timer1", "timer2", "apb_pclk";
222 };
223
224 timer23: timer@10105000 {
225 compatible = "arm,sp804", "arm,primecell";
226 reg = <0x10105000 0x1000>;
227 interrupt-parent = <&intc_dc1176>;
228 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
229 arm,sp804-has-irq = <1>;
230 clocks = <&timclk>, <&timclk>, <&pclk>;
231 clock-names = "timer1", "timer2", "apb_pclk";
232 };
233
234 pb1176_rtc: rtc@10108000 {
235 compatible = "arm,pl031", "arm,primecell";
236 reg = <0x10108000 0x1000>;
237 interrupt-parent = <&intc_dc1176>;
238 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&pclk>;
240 clock-names = "apb_pclk";
241 };
242
243 pb1176_gpio0: gpio@1010a000 {
244 compatible = "arm,pl061", "arm,primecell";
245 reg = <0x1010a000 0x1000>;
246 gpio-controller;
247 interrupt-parent = <&intc_dc1176>;
248 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
249 #gpio-cells = <2>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
252 clocks = <&pclk>;
253 clock-names = "apb_pclk";
254 };
255
256 pb1176_ssp: ssp@1010b000 {
257 compatible = "arm,pl022", "arm,primecell";
258 reg = <0x1010b000 0x1000>;
259 interrupt-parent = <&intc_dc1176>;
260 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&sspclk>, <&pclk>;
262 clock-names = "SSPCLK", "apb_pclk";
263 };
264
265 pb1176_serial0: serial@1010c000 {
266 compatible = "arm,pl011", "arm,primecell";
267 reg = <0x1010c000 0x1000>;
268 interrupt-parent = <&intc_dc1176>;
269 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&uartclk>, <&pclk>;
271 clock-names = "uartclk", "apb_pclk";
272 };
273
274 pb1176_serial1: serial@1010d000 {
275 compatible = "arm,pl011", "arm,primecell";
276 reg = <0x1010d000 0x1000>;
277 interrupt-parent = <&intc_dc1176>;
278 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&uartclk>, <&pclk>;
280 clock-names = "uartclk", "apb_pclk";
281 };
282
283 pb1176_serial2: serial@1010e000 {
284 compatible = "arm,pl011", "arm,primecell";
285 reg = <0x1010e000 0x1000>;
286 interrupt-parent = <&intc_dc1176>;
287 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&uartclk>, <&pclk>;
289 clock-names = "uartclk", "apb_pclk";
290 };
291
292 pb1176_serial3: serial@1010f000 {
293 compatible = "arm,pl011", "arm,primecell";
294 reg = <0x1010f000 0x1000>;
295 interrupt-parent = <&intc_dc1176>;
296 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&uartclk>, <&pclk>;
298 clock-names = "uartclk", "apb_pclk";
299 };
300 };
301
302 /* These peripherals are inside the FPGA rather than the DevChip */
303 fpga {
304 #address-cells = <1>;
305 #size-cells = <1>;
306 compatible = "simple-bus";
307 ranges;
308
309 fpga_mci: mmcsd@10005000 {
310 compatible = "arm,pl18x", "arm,primecell";
311 reg = <0x10005000 0x1000>;
312 interrupt-parent = <&intc_fpga1176>;
313 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>,
314 <0 2 IRQ_TYPE_LEVEL_HIGH>;
315 /* Due to frequent FIFO overruns, use just 500 kHz */
316 max-frequency = <500000>;
317 bus-width = <4>;
318 cap-sd-highspeed;
319 cap-mmc-highspeed;
320 clocks = <&mclk>, <&pclk>;
321 clock-names = "mclk", "apb_pclk";
322 vmmc-supply = <&vmmc>;
323 cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>;
324 wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>;
325 };
326
327 fpga_kmi0: kmi@10006000 {
328 compatible = "arm,pl050", "arm,primecell";
329 reg = <0x10006000 0x1000>;
330 interrupt-parent = <&intc_fpga1176>;
331 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&kmiclk>, <&pclk>;
333 clock-names = "KMIREFCLK", "apb_pclk";
334 };
335
336 fpga_kmi1: kmi@10007000 {
337 compatible = "arm,pl050", "arm,primecell";
338 reg = <0x10007000 0x1000>;
339 interrupt-parent = <&intc_fpga1176>;
340 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&kmiclk>, <&pclk>;
342 clock-names = "KMIREFCLK", "apb_pclk";
343 };
344
345 fpga_charlcd: charlcd@10008000 {
346 compatible = "arm,versatile-lcd";
347 reg = <0x10008000 0x1000>;
348 interrupt-parent = <&intc_fpga1176>;
349 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&pclk>;
351 clock-names = "apb_pclk";
352 };
353
354 fpga_serial: serial@10009000 {
355 compatible = "arm,pl011", "arm,primecell";
356 reg = <0x10009000 0x1000>;
357 interrupt-parent = <&intc_fpga1176>;
358 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&uartclk>, <&pclk>;
360 clock-names = "uartclk", "apb_pclk";
361 };
362
363 /* This GIC on the board is cascaded off the DevChip GIC */
364 intc_fpga1176: interrupt-controller@10040000 {
365 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
366 #interrupt-cells = <3>;
367 #address-cells = <1>;
368 interrupt-controller;
369 reg = <0x10041000 0x1000>,
370 <0x10040000 0x100>;
371 interrupt-parent = <&intc_dc1176>;
372 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
373 };
374
375 fpga_gpio0: gpio@10014000 {
376 compatible = "arm,pl061", "arm,primecell";
377 reg = <0x10014000 0x1000>;
378 gpio-controller;
379 interrupt-parent = <&intc_fpga1176>;
380 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
381 #gpio-cells = <2>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 clocks = <&pclk>;
385 clock-names = "apb_pclk";
386 };
387
388 fpga_gpio1: gpio@10015000 {
389 compatible = "arm,pl061", "arm,primecell";
390 reg = <0x10015000 0x1000>;
391 gpio-controller;
392 interrupt-parent = <&intc_fpga1176>;
393 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
394 #gpio-cells = <2>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
397 clocks = <&pclk>;
398 clock-names = "apb_pclk";
399 };
400
401 fpga_rtc: rtc@10017000 {
402 compatible = "arm,pl031", "arm,primecell";
403 reg = <0x10017000 0x1000>;
404 interrupt-parent = <&intc_fpga1176>;
405 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&pclk>;
407 clock-names = "apb_pclk";
408 };
409
410
411 };
412};
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index 3aebd93cc33c..1e38628f4060 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -35,7 +35,7 @@
35 pcie-controller { 35 pcie-controller {
36 status = "okay"; 36 status = "okay";
37 37
38 /* Connected to Marvell SATA controller */ 38 /* Connected to Marvell 88SE9170 SATA controller */
39 pcie@1,0 { 39 pcie@1,0 {
40 /* Port 0, Lane 0 */ 40 /* Port 0, Lane 0 */
41 status = "okay"; 41 status = "okay";
@@ -53,8 +53,9 @@
53 status = "okay"; 53 status = "okay";
54 }; 54 };
55 55
56 /* eSATA interface */
56 sata@a0000 { 57 sata@a0000 {
57 nr-ports = <2>; 58 nr-ports = <1>;
58 status = "okay"; 59 status = "okay";
59 }; 60 };
60 61
@@ -204,20 +205,20 @@
204 default-state = "keep"; 205 default-state = "keep";
205 }; 206 };
206 207
207 green-sata1-led { 208 blue-sata1-led {
208 label = "rn102:green:sata1"; 209 label = "rn102:blue:sata1";
209 gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; 210 gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
210 default-state = "on"; 211 default-state = "on";
211 }; 212 };
212 213
213 green-sata2-led { 214 blue-sata2-led {
214 label = "rn102:green:sata2"; 215 label = "rn102:blue:sata2";
215 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; 216 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
216 default-state = "on"; 217 default-state = "on";
217 }; 218 };
218 219
219 green-backup-led { 220 blue-backup-led {
220 label = "rn102:green:backup"; 221 label = "rn102:blue:backup";
221 gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; 222 gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
222 default-state = "on"; 223 default-state = "on";
223 }; 224 };
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 6b3c23b1e138..7851942e244a 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -95,6 +95,7 @@
95 compatible = "marvell,aurora-outer-cache"; 95 compatible = "marvell,aurora-outer-cache";
96 reg = <0x08000 0x1000>; 96 reg = <0x08000 0x1000>;
97 cache-id-part = <0x100>; 97 cache-id-part = <0x100>;
98 cache-unified;
98 wt-override; 99 wt-override;
99 }; 100 };
100 101
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index de6571445cef..9721e55384ce 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -36,6 +36,12 @@
36 #clock-cells = <0>; 36 #clock-cells = <0>;
37 clock-frequency = <2000000000>; 37 clock-frequency = <2000000000>;
38 }; 38 };
39 /* 25 MHz reference crystal */
40 refclk: oscillator {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
44 };
39 }; 45 };
40 46
41 cpus { 47 cpus {
@@ -366,13 +372,15 @@
366 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 372 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
367 <&mpic 5>, 373 <&mpic 5>,
368 <&mpic 6>; 374 <&mpic 6>;
369 clocks = <&coreclk 0>; 375 clocks = <&coreclk 0>, <&refclk>;
376 clock-names = "nbclk", "fixed";
370 }; 377 };
371 378
372 watchdog@20300 { 379 watchdog@20300 {
373 compatible = "marvell,armada-375-wdt"; 380 compatible = "marvell,armada-375-wdt";
374 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>; 381 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
375 clocks = <&coreclk 0>; 382 clocks = <&coreclk 0>, <&refclk>;
383 clock-names = "nbclk", "fixed";
376 }; 384 };
377 385
378 cpurst@20800 { 386 cpurst@20800 {
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
index a55a97a70505..0e53fad111de 100644
--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -60,40 +60,6 @@
60 }; 60 };
61 61
62 internal-regs { 62 internal-regs {
63 pinctrl {
64 pinctrl-0 = <&pmx_phy_int>;
65 pinctrl-names = "default";
66
67 pmx_ge0: pmx-ge0 {
68 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
69 "mpp4", "mpp5", "mpp6", "mpp7",
70 "mpp8", "mpp9", "mpp10", "mpp11";
71 marvell,function = "ge0";
72 };
73
74 pmx_ge1: pmx-ge1 {
75 marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15",
76 "mpp16", "mpp17", "mpp18", "mpp19",
77 "mpp20", "mpp21", "mpp22", "mpp23";
78 marvell,function = "ge1";
79 };
80
81 pmx_keys: pmx-keys {
82 marvell,pins = "mpp33";
83 marvell,function = "gpio";
84 };
85
86 pmx_spi: pmx-spi {
87 marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39";
88 marvell,function = "spi";
89 };
90
91 pmx_phy_int: pmx-phy-int {
92 marvell,pins = "mpp32";
93 marvell,function = "gpio";
94 };
95 };
96
97 serial@12000 { 63 serial@12000 {
98 status = "okay"; 64 status = "okay";
99 }; 65 };
@@ -118,14 +84,14 @@
118 }; 84 };
119 85
120 ethernet@70000 { 86 ethernet@70000 {
121 pinctrl-0 = <&pmx_ge0>; 87 pinctrl-0 = <&pmx_ge0_rgmii>;
122 pinctrl-names = "default"; 88 pinctrl-names = "default";
123 status = "okay"; 89 status = "okay";
124 phy = <&phy0>; 90 phy = <&phy0>;
125 phy-mode = "rgmii-id"; 91 phy-mode = "rgmii-id";
126 }; 92 };
127 ethernet@74000 { 93 ethernet@74000 {
128 pinctrl-0 = <&pmx_ge1>; 94 pinctrl-0 = <&pmx_ge1_rgmii>;
129 pinctrl-names = "default"; 95 pinctrl-names = "default";
130 status = "okay"; 96 status = "okay";
131 phy = <&phy1>; 97 phy = <&phy1>;
@@ -162,3 +128,23 @@
162 }; 128 };
163 }; 129 };
164}; 130};
131
132&pinctrl {
133 pinctrl-0 = <&pmx_phy_int>;
134 pinctrl-names = "default";
135
136 pmx_keys: pmx-keys {
137 marvell,pins = "mpp33";
138 marvell,function = "gpio";
139 };
140
141 pmx_spi: pmx-spi {
142 marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39";
143 marvell,function = "spi";
144 };
145
146 pmx_phy_int: pmx-phy-int {
147 marvell,pins = "mpp32";
148 marvell,function = "gpio";
149 };
150};
diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
index 469cf7137595..aa5463c91924 100644
--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
+++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
@@ -51,37 +51,6 @@
51 }; 51 };
52 52
53 internal-regs { 53 internal-regs {
54 pinctrl {
55 poweroff_pin: poweroff-pin {
56 marvell,pins = "mpp24";
57 marvell,function = "gpio";
58 };
59
60 power_button_pin: power-button-pin {
61 marvell,pins = "mpp44";
62 marvell,function = "gpio";
63 };
64
65 reset_button_pin: reset-button-pin {
66 marvell,pins = "mpp45";
67 marvell,function = "gpio";
68 };
69 select_button_pin: select-button-pin {
70 marvell,pins = "mpp41";
71 marvell,function = "gpio";
72 };
73
74 scroll_button_pin: scroll-button-pin {
75 marvell,pins = "mpp42";
76 marvell,function = "gpio";
77 };
78
79 hdd_led_pin: hdd-led-pin {
80 marvell,pins = "mpp26";
81 marvell,function = "gpio";
82 };
83 };
84
85 serial@12000 { 54 serial@12000 {
86 status = "okay"; 55 status = "okay";
87 }; 56 };
@@ -97,12 +66,16 @@
97 }; 66 };
98 67
99 ethernet@70000 { 68 ethernet@70000 {
69 pinctrl-0 = <&pmx_ge0_rgmii>;
70 pinctrl-names = "default";
100 status = "okay"; 71 status = "okay";
101 phy = <&phy0>; 72 phy = <&phy0>;
102 phy-mode = "rgmii-id"; 73 phy-mode = "rgmii-id";
103 }; 74 };
104 75
105 ethernet@74000 { 76 ethernet@74000 {
77 pinctrl-0 = <&pmx_ge1_rgmii>;
78 pinctrl-names = "default";
106 status = "okay"; 79 status = "okay";
107 phy = <&phy1>; 80 phy = <&phy1>;
108 phy-mode = "rgmii-id"; 81 phy-mode = "rgmii-id";
@@ -125,6 +98,11 @@
125 reg = <0x2e>; 98 reg = <0x2e>;
126 }; 99 };
127 100
101 eeprom@50 {
102 compatible = "atmel,24c64";
103 reg = <0x50>;
104 };
105
128 pcf8563@51 { 106 pcf8563@51 {
129 compatible = "nxp,pcf8563"; 107 compatible = "nxp,pcf8563";
130 reg = <0x51>; 108 reg = <0x51>;
@@ -226,7 +204,7 @@
226 gpio-controller; 204 gpio-controller;
227 #gpio-cells = <2>; 205 #gpio-cells = <2>;
228 reg = <0>; 206 reg = <0>;
229 registers-number = <2>; 207 registers-number = <1>;
230 spi-max-frequency = <100000>; 208 spi-max-frequency = <100000>;
231 }; 209 };
232 }; 210 };
@@ -282,3 +260,34 @@
282 gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; 260 gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
283 }; 261 };
284}; 262};
263
264&pinctrl {
265 poweroff_pin: poweroff-pin {
266 marvell,pins = "mpp24";
267 marvell,function = "gpio";
268 };
269
270 power_button_pin: power-button-pin {
271 marvell,pins = "mpp44";
272 marvell,function = "gpio";
273 };
274
275 reset_button_pin: reset-button-pin {
276 marvell,pins = "mpp45";
277 marvell,function = "gpio";
278 };
279 select_button_pin: select-button-pin {
280 marvell,pins = "mpp41";
281 marvell,function = "gpio";
282 };
283
284 scroll_button_pin: scroll-button-pin {
285 marvell,pins = "mpp42";
286 marvell,function = "gpio";
287 };
288
289 hdd_led_pin: hdd-led-pin {
290 marvell,pins = "mpp26";
291 marvell,function = "gpio";
292 };
293};
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 2592e1c13560..281ccd24295c 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -167,17 +167,6 @@
167 }; 167 };
168 168
169 internal-regs { 169 internal-regs {
170 pinctrl {
171 compatible = "marvell,mv78230-pinctrl";
172 reg = <0x18000 0x38>;
173
174 sdio_pins: sdio-pins {
175 marvell,pins = "mpp30", "mpp31", "mpp32",
176 "mpp33", "mpp34", "mpp35";
177 marvell,function = "sd0";
178 };
179 };
180
181 gpio0: gpio@18100 { 170 gpio0: gpio@18100 {
182 compatible = "marvell,orion-gpio"; 171 compatible = "marvell,orion-gpio";
183 reg = <0x18100 0x40>; 172 reg = <0x18100 0x40>;
@@ -202,3 +191,7 @@
202 }; 191 };
203 }; 192 };
204}; 193};
194
195&pinctrl {
196 compatible = "marvell,mv78230-pinctrl";
197};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 480e237a870f..d7a8d0b0f385 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -251,17 +251,6 @@
251 }; 251 };
252 252
253 internal-regs { 253 internal-regs {
254 pinctrl {
255 compatible = "marvell,mv78260-pinctrl";
256 reg = <0x18000 0x38>;
257
258 sdio_pins: sdio-pins {
259 marvell,pins = "mpp30", "mpp31", "mpp32",
260 "mpp33", "mpp34", "mpp35";
261 marvell,function = "sd0";
262 };
263 };
264
265 gpio0: gpio@18100 { 254 gpio0: gpio@18100 {
266 compatible = "marvell,orion-gpio"; 255 compatible = "marvell,orion-gpio";
267 reg = <0x18100 0x40>; 256 reg = <0x18100 0x40>;
@@ -305,3 +294,7 @@
305 }; 294 };
306 }; 295 };
307}; 296};
297
298&pinctrl {
299 compatible = "marvell,mv78260-pinctrl";
300};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 2c7b1fef4703..9c40c130d11a 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -289,17 +289,6 @@
289 }; 289 };
290 290
291 internal-regs { 291 internal-regs {
292 pinctrl {
293 compatible = "marvell,mv78460-pinctrl";
294 reg = <0x18000 0x38>;
295
296 sdio_pins: sdio-pins {
297 marvell,pins = "mpp30", "mpp31", "mpp32",
298 "mpp33", "mpp34", "mpp35";
299 marvell,function = "sd0";
300 };
301 };
302
303 gpio0: gpio@18100 { 292 gpio0: gpio@18100 {
304 compatible = "marvell,orion-gpio"; 293 compatible = "marvell,orion-gpio";
305 reg = <0x18100 0x40>; 294 reg = <0x18100 0x40>;
@@ -343,3 +332,7 @@
343 }; 332 };
344 }; 333 };
345}; 334};
335
336&pinctrl {
337 compatible = "marvell,mv78460-pinctrl";
338};
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index 7d8f32873e82..d81430aa4ab3 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -55,86 +55,10 @@
55 }; 55 };
56 56
57 internal-regs { 57 internal-regs {
58 pinctrl { 58 /* Two rear eSATA ports */
59 poweroff: poweroff { 59 sata@a0000 {
60 marvell,pins = "mpp42"; 60 nr-ports = <2>;
61 marvell,function = "gpio"; 61 status = "okay";
62 };
63
64 power_button_pin: power-button-pin {
65 marvell,pins = "mpp27";
66 marvell,function = "gpio";
67 };
68
69 reset_button_pin: reset-button-pin {
70 marvell,pins = "mpp41";
71 marvell,function = "gpio";
72 };
73
74 sata1_led_pin: sata1-led-pin {
75 marvell,pins = "mpp31";
76 marvell,function = "gpio";
77 };
78
79 sata2_led_pin: sata2-led-pin {
80 marvell,pins = "mpp40";
81 marvell,function = "gpio";
82 };
83
84 sata3_led_pin: sata3-led-pin {
85 marvell,pins = "mpp44";
86 marvell,function = "gpio";
87 };
88
89 sata4_led_pin: sata4-led-pin {
90 marvell,pins = "mpp47";
91 marvell,function = "gpio";
92 };
93
94 sata1_power_pin: sata1-power-pin {
95 marvell,pins = "mpp24";
96 marvell,function = "gpio";
97 };
98
99 sata2_power_pin: sata2-power-pin {
100 marvell,pins = "mpp25";
101 marvell,function = "gpio";
102 };
103
104 sata3_power_pin: sata3-power-pin {
105 marvell,pins = "mpp26";
106 marvell,function = "gpio";
107 };
108
109 sata4_power_pin: sata4-power-pin {
110 marvell,pins = "mpp28";
111 marvell,function = "gpio";
112 };
113
114 sata1_pres_pin: sata1-pres-pin {
115 marvell,pins = "mpp32";
116 marvell,function = "gpio";
117 };
118
119 sata2_pres_pin: sata2-pres-pin {
120 marvell,pins = "mpp33";
121 marvell,function = "gpio";
122 };
123
124 sata3_pres_pin: sata3-pres-pin {
125 marvell,pins = "mpp34";
126 marvell,function = "gpio";
127 };
128
129 sata4_pres_pin: sata4-pres-pin {
130 marvell,pins = "mpp35";
131 marvell,function = "gpio";
132 };
133
134 err_led_pin: err-led-pin {
135 marvell,pins = "mpp45";
136 marvell,function = "gpio";
137 };
138 }; 62 };
139 63
140 serial@12000 { 64 serial@12000 {
@@ -328,3 +252,85 @@
328 gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 252 gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
329 }; 253 };
330}; 254};
255
256&pinctrl {
257 poweroff: poweroff {
258 marvell,pins = "mpp42";
259 marvell,function = "gpio";
260 };
261
262 power_button_pin: power-button-pin {
263 marvell,pins = "mpp27";
264 marvell,function = "gpio";
265 };
266
267 reset_button_pin: reset-button-pin {
268 marvell,pins = "mpp41";
269 marvell,function = "gpio";
270 };
271
272 sata1_led_pin: sata1-led-pin {
273 marvell,pins = "mpp31";
274 marvell,function = "gpio";
275 };
276
277 sata2_led_pin: sata2-led-pin {
278 marvell,pins = "mpp40";
279 marvell,function = "gpio";
280 };
281
282 sata3_led_pin: sata3-led-pin {
283 marvell,pins = "mpp44";
284 marvell,function = "gpio";
285 };
286
287 sata4_led_pin: sata4-led-pin {
288 marvell,pins = "mpp47";
289 marvell,function = "gpio";
290 };
291
292 sata1_power_pin: sata1-power-pin {
293 marvell,pins = "mpp24";
294 marvell,function = "gpio";
295 };
296
297 sata2_power_pin: sata2-power-pin {
298 marvell,pins = "mpp25";
299 marvell,function = "gpio";
300 };
301
302 sata3_power_pin: sata3-power-pin {
303 marvell,pins = "mpp26";
304 marvell,function = "gpio";
305 };
306
307 sata4_power_pin: sata4-power-pin {
308 marvell,pins = "mpp28";
309 marvell,function = "gpio";
310 };
311
312 sata1_pres_pin: sata1-pres-pin {
313 marvell,pins = "mpp32";
314 marvell,function = "gpio";
315 };
316
317 sata2_pres_pin: sata2-pres-pin {
318 marvell,pins = "mpp33";
319 marvell,function = "gpio";
320 };
321
322 sata3_pres_pin: sata3-pres-pin {
323 marvell,pins = "mpp34";
324 marvell,function = "gpio";
325 };
326
327 sata4_pres_pin: sata4-pres-pin {
328 marvell,pins = "mpp35";
329 marvell,function = "gpio";
330 };
331
332 err_led_pin: err-led-pin {
333 marvell,pins = "mpp45";
334 marvell,function = "gpio";
335 };
336};
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 4e5a59ee1501..6f6b0916df48 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -77,12 +77,7 @@
77 serial@12100 { 77 serial@12100 {
78 status = "okay"; 78 status = "okay";
79 }; 79 };
80 pinctrl { 80
81 led_pins: led-pins-0 {
82 marvell,pins = "mpp49", "mpp51", "mpp53";
83 marvell,function = "gpio";
84 };
85 };
86 leds { 81 leds {
87 compatible = "gpio-leds"; 82 compatible = "gpio-leds";
88 pinctrl-names = "default"; 83 pinctrl-names = "default";
@@ -187,3 +182,10 @@
187 }; 182 };
188 }; 183 };
189}; 184};
185
186&pinctrl {
187 led_pins: led-pins-0 {
188 marvell,pins = "mpp49", "mpp51", "mpp53";
189 marvell,function = "gpio";
190 };
191};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index bff9f6c18db1..a3919b644737 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -39,6 +39,7 @@
39 compatible = "marvell,aurora-system-cache"; 39 compatible = "marvell,aurora-system-cache";
40 reg = <0x08000 0x1000>; 40 reg = <0x08000 0x1000>;
41 cache-id-part = <0x100>; 41 cache-id-part = <0x100>;
42 cache-unified;
42 wt-override; 43 wt-override;
43 }; 44 };
44 45
@@ -71,6 +72,43 @@
71 status = "disabled"; 72 status = "disabled";
72 }; 73 };
73 74
75 pinctrl: pin-ctrl@18000 {
76 reg = <0x18000 0x38>;
77
78 pmx_ge0_gmii: pmx-ge0-gmii {
79 marvell,pins =
80 "mpp0", "mpp1", "mpp2", "mpp3",
81 "mpp4", "mpp5", "mpp6", "mpp7",
82 "mpp8", "mpp9", "mpp10", "mpp11",
83 "mpp12", "mpp13", "mpp14", "mpp15",
84 "mpp16", "mpp17", "mpp18", "mpp19",
85 "mpp20", "mpp21", "mpp22", "mpp23";
86 marvell,function = "ge0";
87 };
88
89 pmx_ge0_rgmii: pmx-ge0-rgmii {
90 marvell,pins =
91 "mpp0", "mpp1", "mpp2", "mpp3",
92 "mpp4", "mpp5", "mpp6", "mpp7",
93 "mpp8", "mpp9", "mpp10", "mpp11";
94 marvell,function = "ge0";
95 };
96
97 pmx_ge1_rgmii: pmx-ge1-rgmii {
98 marvell,pins =
99 "mpp12", "mpp13", "mpp14", "mpp15",
100 "mpp16", "mpp17", "mpp18", "mpp19",
101 "mpp20", "mpp21", "mpp22", "mpp23";
102 marvell,function = "ge1";
103 };
104
105 sdio_pins: sdio-pins {
106 marvell,pins = "mpp30", "mpp31", "mpp32",
107 "mpp33", "mpp34", "mpp35";
108 marvell,function = "sd0";
109 };
110 };
111
74 system-controller@18200 { 112 system-controller@18200 {
75 compatible = "marvell,armada-370-xp-system-controller"; 113 compatible = "marvell,armada-370-xp-system-controller";
76 reg = <0x18200 0x500>; 114 reg = <0x18200 0x500>;
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index d68b3c4862bc..653e4395b7cb 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -122,9 +122,10 @@
122 interrupts-extended = <&pmc AT91_PMC_LOCKB>; 122 interrupts-extended = <&pmc AT91_PMC_LOCKB>;
123 clocks = <&main>; 123 clocks = <&main>;
124 reg = <1>; 124 reg = <1>;
125 atmel,clk-input-range = <1000000 5000000>; 125 atmel,clk-input-range = <1000000 32000000>;
126 #atmel,pll-clk-output-range-cells = <4>; 126 #atmel,pll-clk-output-range-cells = <4>;
127 atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; 127 atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
128 <190000000 240000000 2 1>;
128 }; 129 };
129 130
130 mck: masterck { 131 mck: masterck {
@@ -676,6 +677,14 @@
676 }; 677 };
677 }; 678 };
678 679
680 can {
681 pinctrl_can_rx_tx: can_rx_tx {
682 atmel,pins =
683 <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* CANRX, conflicts with IRQ0 */
684 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* CANTX, conflicts with PCK0 */
685 };
686 };
687
679 pioA: gpio@fffff200 { 688 pioA: gpio@fffff200 {
680 compatible = "atmel,at91rm9200-gpio"; 689 compatible = "atmel,at91rm9200-gpio";
681 reg = <0xfffff200 0x200>; 690 reg = <0xfffff200 0x200>;
@@ -904,6 +913,17 @@
904 clock-names = "pwm_clk"; 913 clock-names = "pwm_clk";
905 status = "disabled"; 914 status = "disabled";
906 }; 915 };
916
917 can: can@fffac000 {
918 compatible = "atmel,at91sam9263-can";
919 reg = <0xfffac000 0x300>;
920 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
921 pinctrl-names = "default";
922 pinctrl-0 = <&pinctrl_can_rx_tx>;
923 clocks = <&can_clk>;
924 clock-names = "can_clk";
925 status = "disabled";
926 };
907 }; 927 };
908 928
909 fb0: fb@0x00700000 { 929 fb0: fb@0x00700000 {
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
index c2554219f7a4..3c5fa3388997 100644
--- a/arch/arm/boot/dts/at91sam9x25.dtsi
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -10,6 +10,7 @@
10#include "at91sam9x5_usart3.dtsi" 10#include "at91sam9x5_usart3.dtsi"
11#include "at91sam9x5_macb0.dtsi" 11#include "at91sam9x5_macb0.dtsi"
12#include "at91sam9x5_macb1.dtsi" 12#include "at91sam9x5_macb1.dtsi"
13#include "at91sam9x5_can.dtsi"
13 14
14/ { 15/ {
15 model = "Atmel AT91SAM9X25 SoC"; 16 model = "Atmel AT91SAM9X25 SoC";
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
index 8eac66ce0ab7..499cdc81f4c0 100644
--- a/arch/arm/boot/dts/at91sam9x35.dtsi
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -8,6 +8,7 @@
8 8
9#include "at91sam9x5.dtsi" 9#include "at91sam9x5.dtsi"
10#include "at91sam9x5_macb0.dtsi" 10#include "at91sam9x5_macb0.dtsi"
11#include "at91sam9x5_can.dtsi"
11 12
12/ { 13/ {
13 model = "Atmel AT91SAM9X35 SoC"; 14 model = "Atmel AT91SAM9X35 SoC";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 726274f7959b..bbb3ba65165f 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -860,6 +860,9 @@
860 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 860 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
861 pinctrl-names = "default"; 861 pinctrl-names = "default";
862 pinctrl-0 = <&pinctrl_dbgu>; 862 pinctrl-0 = <&pinctrl_dbgu>;
863 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>,
864 <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
865 dma-names = "tx", "rx";
863 clocks = <&mck>; 866 clocks = <&mck>;
864 clock-names = "usart"; 867 clock-names = "usart";
865 status = "disabled"; 868 status = "disabled";
@@ -871,6 +874,9 @@
871 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; 874 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
872 pinctrl-names = "default"; 875 pinctrl-names = "default";
873 pinctrl-0 = <&pinctrl_usart0>; 876 pinctrl-0 = <&pinctrl_usart0>;
877 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>,
878 <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
879 dma-names = "tx", "rx";
874 clocks = <&usart0_clk>; 880 clocks = <&usart0_clk>;
875 clock-names = "usart"; 881 clock-names = "usart";
876 status = "disabled"; 882 status = "disabled";
@@ -882,6 +888,9 @@
882 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; 888 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
883 pinctrl-names = "default"; 889 pinctrl-names = "default";
884 pinctrl-0 = <&pinctrl_usart1>; 890 pinctrl-0 = <&pinctrl_usart1>;
891 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>,
892 <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
893 dma-names = "tx", "rx";
885 clocks = <&usart1_clk>; 894 clocks = <&usart1_clk>;
886 clock-names = "usart"; 895 clock-names = "usart";
887 status = "disabled"; 896 status = "disabled";
@@ -893,6 +902,9 @@
893 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 902 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
894 pinctrl-names = "default"; 903 pinctrl-names = "default";
895 pinctrl-0 = <&pinctrl_usart2>; 904 pinctrl-0 = <&pinctrl_usart2>;
905 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>,
906 <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
907 dma-names = "tx", "rx";
896 clocks = <&usart2_clk>; 908 clocks = <&usart2_clk>;
897 clock-names = "usart"; 909 clock-names = "usart";
898 status = "disabled"; 910 status = "disabled";
diff --git a/arch/arm/boot/dts/at91sam9x5_can.dtsi b/arch/arm/boot/dts/at91sam9x5_can.dtsi
index f44ab7702a12..8eb2f9c1b978 100644
--- a/arch/arm/boot/dts/at91sam9x5_can.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_can.dtsi
@@ -1,5 +1,5 @@
1/* 1/*
2 * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 2 * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
3 * Ethernet interface. 3 * Ethernet interface.
4 * 4 *
5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
@@ -20,10 +20,50 @@
20 reg = <29>; 20 reg = <29>;
21 }; 21 };
22 22
23 can1_clk: can1_clk { 23 can1_clk: can1_clk {
24 #clock-cells = <0>; 24 #clock-cells = <0>;
25 reg = <30>; 25 reg = <30>;
26 }; 26 };
27 };
28 };
29
30 can0: can@f8000000 {
31 compatible = "atmel,at91sam9x5-can";
32 reg = <0xf8000000 0x300>;
33 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
34 pinctrl-names = "default";
35 pinctrl-0 = <&pinctrl_can0_rx_tx>;
36 clocks = <&can0_clk>;
37 clock-names = "can_clk";
38 status = "disabled";
39 };
40
41 can1: can@f8004000 {
42 compatible = "atmel,at91sam9x5-can";
43 reg = <0xf8004000 0x300>;
44 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_can1_rx_tx>;
47 clocks = <&can1_clk>;
48 clock-names = "can_clk";
49 status = "disabled";
50 };
51
52 pinctrl@fffff400 {
53 can0 {
54 pinctrl_can0_rx_tx: can0_rx_tx {
55 atmel,pins =
56 <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX0, conflicts with DRXD */
57 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* CANTX0, conflicts with DTXD */
58 };
59 };
60
61 can1 {
62 pinctrl_can1_rx_tx: can1_rx_tx {
63 atmel,pins =
64 <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX1, conflicts with RXD1 */
65 AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* CANTX1, conflicts with TXD1 */
66 };
27 }; 67 };
28 }; 68 };
29 }; 69 };
diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
index 140217a54384..43bb5b51caa6 100644
--- a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
@@ -57,6 +57,9 @@
57 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; 57 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
58 pinctrl-names = "default"; 58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_usart3>; 59 pinctrl-0 = <&pinctrl_usart3>;
60 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>,
61 <&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
62 dma-names = "tx", "rx";
60 clocks = <&usart3_clk>; 63 clocks = <&usart3_clk>;
61 clock-names = "usart"; 64 clock-names = "usart";
62 status = "disabled"; 65 status = "disabled";
diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
new file mode 100644
index 000000000000..60d8389fdb6c
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
@@ -0,0 +1,91 @@
1/*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2014 Broadcom Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33clocks {
34 #address-cells = <1>;
35 #size-cells = <1>;
36 ranges;
37
38 osc: oscillator {
39 compatible = "fixed-clock";
40 #clock-cells = <1>;
41 clock-frequency = <25000000>;
42 };
43
44 apb_clk: apb_clk {
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
47 clock-frequency = <1000000000>;
48 };
49
50 periph_clk: periph_clk {
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <500000000>;
54 };
55
56 sdio_clk: lcpll_ch2 {
57 compatible = "fixed-clock";
58 #clock-cells = <0>;
59 clock-frequency = <200000000>;
60 };
61
62 axi81_clk: axi81_clk {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <100000000>;
66 };
67
68 keypad_clk: keypad_clk {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <31806>;
72 };
73
74 adc_clk: adc_clk {
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <1562500>;
78 };
79
80 pwm_clk: pwm_clk {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <1000000>;
84 };
85
86 lcd_clk: mipipll_ch1 {
87 compatible = "fixed-clock";
88 #clock-cells = <0>;
89 clock-frequency = <100000000>;
90 };
91};
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
new file mode 100644
index 000000000000..5126f9e77a98
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -0,0 +1,140 @@
1/*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2014 Broadcom Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <dt-bindings/interrupt-controller/arm-gic.h>
34#include <dt-bindings/interrupt-controller/irq.h>
35
36#include "skeleton.dtsi"
37
38/ {
39 compatible = "brcm,cygnus";
40 model = "Broadcom Cygnus SoC";
41 interrupt-parent = <&gic>;
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
51 reg = <0x0>;
52 };
53 };
54
55 /include/ "bcm-cygnus-clock.dtsi"
56
57 amba {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "arm,amba-bus", "simple-bus";
61 interrupt-parent = <&gic>;
62 ranges;
63
64 wdt@18009000 {
65 compatible = "arm,sp805" , "arm,primecell";
66 reg = <0x18009000 0x1000>;
67 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
68 clocks = <&axi81_clk>;
69 clock-names = "apb_pclk";
70 };
71 };
72
73 uart0: serial@18020000 {
74 compatible = "snps,dw-apb-uart";
75 reg = <0x18020000 0x100>;
76 reg-shift = <2>;
77 reg-io-width = <4>;
78 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
79 clocks = <&axi81_clk>;
80 clock-frequency = <100000000>;
81 status = "disabled";
82 };
83
84 uart1: serial@18021000 {
85 compatible = "snps,dw-apb-uart";
86 reg = <0x18021000 0x100>;
87 reg-shift = <2>;
88 reg-io-width = <4>;
89 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&axi81_clk>;
91 clock-frequency = <100000000>;
92 status = "disabled";
93 };
94
95 uart2: serial@18022000 {
96 compatible = "snps,dw-apb-uart";
97 reg = <0x18020000 0x100>;
98 reg-shift = <2>;
99 reg-io-width = <4>;
100 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&axi81_clk>;
102 clock-frequency = <100000000>;
103 status = "disabled";
104 };
105
106 uart3: serial@18023000 {
107 compatible = "snps,dw-apb-uart";
108 reg = <0x18023000 0x100>;
109 reg-shift = <2>;
110 reg-io-width = <4>;
111 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&axi81_clk>;
113 clock-frequency = <100000000>;
114 status = "disabled";
115 };
116
117 gic: interrupt-controller@19021000 {
118 compatible = "arm,cortex-a9-gic";
119 #interrupt-cells = <3>;
120 #address-cells = <0>;
121 interrupt-controller;
122 reg = <0x19021000 0x1000>,
123 <0x19020100 0x100>;
124 };
125
126 L2: l2-cache {
127 compatible = "arm,pl310-cache";
128 reg = <0x19022000 0x1000>;
129 cache-unified;
130 cache-level = <2>;
131 };
132
133 timer@19020200 {
134 compatible = "arm,cortex-a9-global-timer";
135 reg = <0x19020200 0x100>;
136 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&periph_clk>;
138 };
139
140};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
new file mode 100644
index 000000000000..e479515099c3
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
@@ -0,0 +1,30 @@
1/dts-v1/;
2/include/ "bcm2835-rpi.dtsi"
3
4/ {
5 compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
6 model = "Raspberry Pi Model B+";
7
8 leds {
9 act {
10 gpios = <&gpio 47 0>;
11 };
12
13 pwr {
14 label = "PWR";
15 gpios = <&gpio 35 0>;
16 default-state = "keep";
17 linux,default-trigger = "default-on";
18 };
19 };
20};
21
22&gpio {
23 pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
24
25 /* I2S interface */
26 i2s_alt0: i2s_alt0 {
27 brcm,pins = <18 19 20 21>;
28 brcm,function = <4>; /* alt0 */
29 };
30};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 58a0d60b95f1..bafa46fc226a 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -1,63 +1,23 @@
1/dts-v1/; 1/dts-v1/;
2/include/ "bcm2835.dtsi" 2/include/ "bcm2835-rpi.dtsi"
3 3
4/ { 4/ {
5 compatible = "raspberrypi,model-b", "brcm,bcm2835"; 5 compatible = "raspberrypi,model-b", "brcm,bcm2835";
6 model = "Raspberry Pi Model B"; 6 model = "Raspberry Pi Model B";
7 7
8 memory {
9 reg = <0 0x10000000>;
10 };
11
12 leds { 8 leds {
13 compatible = "gpio-leds";
14
15 act { 9 act {
16 label = "ACT";
17 gpios = <&gpio 16 1>; 10 gpios = <&gpio 16 1>;
18 default-state = "keep";
19 linux,default-trigger = "heartbeat";
20 }; 11 };
21 }; 12 };
22}; 13};
23 14
24&gpio { 15&gpio {
25 pinctrl-names = "default"; 16 pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
26 pinctrl-0 = <&gpioout &alt0 &alt2 &alt3>;
27
28 gpioout: gpioout {
29 brcm,pins = <6>;
30 brcm,function = <1>; /* GPIO out */
31 };
32
33 alt0: alt0 {
34 brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>;
35 brcm,function = <4>; /* alt0 */
36 };
37
38 alt3: alt3 {
39 brcm,pins = <48 49 50 51 52 53>;
40 brcm,function = <7>; /* alt3 */
41 };
42 17
43 /* I2S interface */ 18 /* I2S interface */
44 alt2: alt2 { 19 i2s_alt2: i2s_alt2 {
45 brcm,pins = <28 29 30 31>; 20 brcm,pins = <28 29 30 31>;
46 brcm,function = <6>; /* alt2 */ 21 brcm,function = <6>; /* alt2 */
47 }; 22 };
48}; 23};
49
50&i2c0 {
51 status = "okay";
52 clock-frequency = <100000>;
53};
54
55&i2c1 {
56 status = "okay";
57 clock-frequency = <100000>;
58};
59
60&sdhci {
61 status = "okay";
62 bus-width = <4>;
63};
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
new file mode 100644
index 000000000000..c7064487017d
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -0,0 +1,51 @@
1/include/ "bcm2835.dtsi"
2
3/ {
4 memory {
5 reg = <0 0x10000000>;
6 };
7
8 leds {
9 compatible = "gpio-leds";
10
11 act {
12 label = "ACT";
13 default-state = "keep";
14 linux,default-trigger = "heartbeat";
15 };
16 };
17};
18
19&gpio {
20 pinctrl-names = "default";
21
22 gpioout: gpioout {
23 brcm,pins = <6>;
24 brcm,function = <1>; /* GPIO out */
25 };
26
27 alt0: alt0 {
28 brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>;
29 brcm,function = <4>; /* alt0 */
30 };
31
32 alt3: alt3 {
33 brcm,pins = <48 49 50 51 52 53>;
34 brcm,function = <7>; /* alt3 */
35 };
36};
37
38&i2c0 {
39 status = "okay";
40 clock-frequency = <100000>;
41};
42
43&i2c1 {
44 status = "okay";
45 clock-frequency = <100000>;
46};
47
48&sdhci {
49 status = "okay";
50 bus-width = <4>;
51};
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
new file mode 100644
index 000000000000..d2ee95280548
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -0,0 +1,53 @@
1/*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2014 Broadcom Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/dts-v1/;
34
35#include "bcm-cygnus.dtsi"
36
37/ {
38 model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
39 compatible = "brcm,bcm11360", "brcm,cygnus";
40
41 aliases {
42 serial0 = &uart3;
43 };
44
45 chosen {
46 stdout-path = &uart3;
47 bootargs = "console=ttyS0,115200";
48 };
49
50 uart3: serial@18023000 {
51 status = "okay";
52 };
53};
diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/bcm911360k.dts
new file mode 100644
index 000000000000..9658d4f62d59
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360k.dts
@@ -0,0 +1,53 @@
1/*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2014 Broadcom Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/dts-v1/;
34
35#include "bcm-cygnus.dtsi"
36
37/ {
38 model = "Cygnus SVK (BCM911360K)";
39 compatible = "brcm,bcm11360", "brcm,cygnus";
40
41 aliases {
42 serial0 = &uart3;
43 };
44
45 chosen {
46 stdout-path = &uart3;
47 bootargs = "console=ttyS0,115200";
48 };
49
50 uart3: serial@18023000 {
51 status = "okay";
52 };
53};
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
new file mode 100644
index 000000000000..f1bb36f3975c
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -0,0 +1,53 @@
1/*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2014 Broadcom Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/dts-v1/;
34
35#include "bcm-cygnus.dtsi"
36
37/ {
38 model = "Cygnus SVK (BCM958300K)";
39 compatible = "brcm,bcm58300", "brcm,cygnus";
40
41 aliases {
42 serial0 = &uart3;
43 };
44
45 chosen {
46 stdout-path = &uart3;
47 bootargs = "console=ttyS0,115200";
48 };
49
50 uart3: serial@18023000 {
51 status = "okay";
52 };
53};
diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
index c72bfd468d10..86d85d8896a3 100644
--- a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
+++ b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
@@ -26,4 +26,20 @@
26 }; 26 };
27}; 27};
28 28
29&ahci { status = "okay"; };
30
31&eth1 { status = "okay"; };
32
33/* Unpopulated SATA plug on solder side */
34&sata0 { status = "okay"; };
35
36&sata_phy { status = "okay"; };
37
38/* Samsung M8G2FA 8GB eMMC */
39&sdhci2 {
40 non-removable;
41 bus-width = <8>;
42 status = "okay";
43};
44
29&uart0 { status = "okay"; }; 45&uart0 { status = "okay"; };
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 9d7c810ebd0b..015a06c67c91 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -53,6 +53,35 @@
53 53
54 ranges = <0 0xf7000000 0x1000000>; 54 ranges = <0 0xf7000000 0x1000000>;
55 55
56 sdhci0: sdhci@ab0000 {
57 compatible = "mrvl,pxav3-mmc";
58 reg = <0xab0000 0x200>;
59 clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
60 clock-names = "io", "core";
61 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
62 status = "disabled";
63 };
64
65 sdhci1: sdhci@ab0800 {
66 compatible = "mrvl,pxav3-mmc";
67 reg = <0xab0800 0x200>;
68 clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
69 clock-names = "io", "core";
70 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
71 status = "disabled";
72 };
73
74 sdhci2: sdhci@ab1000 {
75 compatible = "mrvl,pxav3-mmc";
76 reg = <0xab1000 0x200>;
77 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
78 clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
79 clock-names = "io", "core";
80 pinctrl-0 = <&emmc_pmux>;
81 pinctrl-names = "default";
82 status = "disabled";
83 };
84
56 l2: l2-cache-controller@ac0000 { 85 l2: l2-cache-controller@ac0000 {
57 compatible = "marvell,tauros3-cache", "arm,pl310-cache"; 86 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
58 reg = <0xac0000 0x1000>; 87 reg = <0xac0000 0x1000>;
@@ -79,11 +108,47 @@
79 clocks = <&chip CLKID_TWD>; 108 clocks = <&chip CLKID_TWD>;
80 }; 109 };
81 110
111 eth1: ethernet@b90000 {
112 compatible = "marvell,pxa168-eth";
113 reg = <0xb90000 0x10000>;
114 clocks = <&chip CLKID_GETH1>;
115 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
116 /* set by bootloader */
117 local-mac-address = [00 00 00 00 00 00];
118 #address-cells = <1>;
119 #size-cells = <0>;
120 phy-connection-type = "mii";
121 phy-handle = <&ethphy1>;
122 status = "disabled";
123
124 ethphy1: ethernet-phy@0 {
125 reg = <0>;
126 };
127 };
128
82 cpu-ctrl@dd0000 { 129 cpu-ctrl@dd0000 {
83 compatible = "marvell,berlin-cpu-ctrl"; 130 compatible = "marvell,berlin-cpu-ctrl";
84 reg = <0xdd0000 0x10000>; 131 reg = <0xdd0000 0x10000>;
85 }; 132 };
86 133
134 eth0: ethernet@e50000 {
135 compatible = "marvell,pxa168-eth";
136 reg = <0xe50000 0x10000>;
137 clocks = <&chip CLKID_GETH0>;
138 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
139 /* set by bootloader */
140 local-mac-address = [00 00 00 00 00 00];
141 #address-cells = <1>;
142 #size-cells = <0>;
143 phy-connection-type = "mii";
144 phy-handle = <&ethphy0>;
145 status = "disabled";
146
147 ethphy0: ethernet-phy@0 {
148 reg = <0>;
149 };
150 };
151
87 apb@e80000 { 152 apb@e80000 {
88 compatible = "simple-bus"; 153 compatible = "simple-bus";
89 #address-cells = <1>; 154 #address-cells = <1>;
@@ -246,12 +311,57 @@
246 }; 311 };
247 }; 312 };
248 313
314 ahci: sata@e90000 {
315 compatible = "marvell,berlin2-ahci", "generic-ahci";
316 reg = <0xe90000 0x1000>;
317 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&chip CLKID_SATA>;
319 #address-cells = <1>;
320 #size-cells = <0>;
321
322 sata0: sata-port@0 {
323 reg = <0>;
324 phys = <&sata_phy 0>;
325 status = "disabled";
326 };
327
328 sata1: sata-port@1 {
329 reg = <1>;
330 phys = <&sata_phy 1>;
331 status = "disabled";
332 };
333 };
334
335 sata_phy: phy@e900a0 {
336 compatible = "marvell,berlin2-sata-phy";
337 reg = <0xe900a0 0x200>;
338 clocks = <&chip CLKID_SATA>;
339 #address-cells = <1>;
340 #size-cells = <0>;
341 #phy-cells = <1>;
342 status = "disabled";
343
344 sata-phy@0 {
345 reg = <0>;
346 };
347
348 sata-phy@1 {
349 reg = <1>;
350 };
351 };
352
249 chip: chip-control@ea0000 { 353 chip: chip-control@ea0000 {
250 compatible = "marvell,berlin2-chip-ctrl"; 354 compatible = "marvell,berlin2-chip-ctrl";
251 #clock-cells = <1>; 355 #clock-cells = <1>;
356 #reset-cells = <2>;
252 reg = <0xea0000 0x400>; 357 reg = <0xea0000 0x400>;
253 clocks = <&refclk>; 358 clocks = <&refclk>;
254 clock-names = "refclk"; 359 clock-names = "refclk";
360
361 emmc_pmux: emmc-pmux {
362 groups = "G26";
363 function = "emmc";
364 };
255 }; 365 };
256 366
257 apb@fc0000 { 367 apb@fc0000 {
diff --git a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
index bcd81ffc495d..30270be4d0c9 100644
--- a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
+++ b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
@@ -11,6 +11,7 @@
11/dts-v1/; 11/dts-v1/;
12 12
13#include "berlin2cd.dtsi" 13#include "berlin2cd.dtsi"
14#include <dt-bindings/gpio/gpio.h>
14 15
15/ { 16/ {
16 model = "Google Chromecast"; 17 model = "Google Chromecast";
@@ -24,6 +25,35 @@
24 device_type = "memory"; 25 device_type = "memory";
25 reg = <0x00000000 0x20000000>; /* 512 MB */ 26 reg = <0x00000000 0x20000000>; /* 512 MB */
26 }; 27 };
28
29 leds {
30 compatible = "gpio-leds";
31
32 white {
33 label = "white";
34 gpios = <&portc 1 GPIO_ACTIVE_HIGH>;
35 default-state = "keep";
36 };
37
38 red {
39 label = "red";
40 gpios = <&portc 2 GPIO_ACTIVE_HIGH>;
41 default-state = "keep";
42 };
43 };
44};
45
46/*
47 * AzureWave AW-NH387 (Marvell 88W8787)
48 * 802.11b/g/n + Bluetooth 2.1
49 */
50&sdhci0 {
51 non-removable;
52 status = "okay";
27}; 53};
28 54
29&uart0 { status = "okay"; }; 55&uart0 { status = "okay"; };
56
57&usb_phy1 { status = "okay"; };
58
59&usb1 { status = "okay"; };
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index cc1df65da504..230df3b1770e 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -45,6 +45,15 @@
45 45
46 ranges = <0 0xf7000000 0x1000000>; 46 ranges = <0 0xf7000000 0x1000000>;
47 47
48 sdhci0: sdhci@ab0000 {
49 compatible = "mrvl,pxav3-mmc";
50 reg = <0xab0000 0x200>;
51 clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
52 clock-names = "io", "core";
53 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
54 status = "disabled";
55 };
56
48 l2: l2-cache-controller@ac0000 { 57 l2: l2-cache-controller@ac0000 {
49 compatible = "arm,pl310-cache"; 58 compatible = "arm,pl310-cache";
50 reg = <0xac0000 0x1000>; 59 reg = <0xac0000 0x1000>;
@@ -66,6 +75,58 @@
66 clocks = <&chip CLKID_TWD>; 75 clocks = <&chip CLKID_TWD>;
67 }; 76 };
68 77
78 usb_phy0: usb-phy@b74000 {
79 compatible = "marvell,berlin2cd-usb-phy";
80 reg = <0xb74000 0x128>;
81 #phy-cells = <0>;
82 resets = <&chip 0x178 23>;
83 status = "disabled";
84 };
85
86 usb_phy1: usb-phy@b78000 {
87 compatible = "marvell,berlin2cd-usb-phy";
88 reg = <0xb78000 0x128>;
89 #phy-cells = <0>;
90 resets = <&chip 0x178 24>;
91 status = "disabled";
92 };
93
94 eth1: ethernet@b90000 {
95 compatible = "marvell,pxa168-eth";
96 reg = <0xb90000 0x10000>;
97 clocks = <&chip CLKID_GETH1>;
98 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
99 /* set by bootloader */
100 local-mac-address = [00 00 00 00 00 00];
101 #address-cells = <1>;
102 #size-cells = <0>;
103 phy-connection-type = "mii";
104 phy-handle = <&ethphy1>;
105 status = "disabled";
106
107 ethphy1: ethernet-phy@0 {
108 reg = <0>;
109 };
110 };
111
112 eth0: ethernet@e50000 {
113 compatible = "marvell,pxa168-eth";
114 reg = <0xe50000 0x10000>;
115 clocks = <&chip CLKID_GETH0>;
116 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
117 /* set by bootloader */
118 local-mac-address = [00 00 00 00 00 00];
119 #address-cells = <1>;
120 #size-cells = <0>;
121 phy-connection-type = "mii";
122 phy-handle = <&ethphy0>;
123 status = "disabled";
124
125 ethphy0: ethernet-phy@0 {
126 reg = <0>;
127 };
128 };
129
69 apb@e80000 { 130 apb@e80000 {
70 compatible = "simple-bus"; 131 compatible = "simple-bus";
71 #address-cells = <1>; 132 #address-cells = <1>;
@@ -231,6 +292,7 @@
231 chip: chip-control@ea0000 { 292 chip: chip-control@ea0000 {
232 compatible = "marvell,berlin2cd-chip-ctrl"; 293 compatible = "marvell,berlin2cd-chip-ctrl";
233 #clock-cells = <1>; 294 #clock-cells = <1>;
295 #reset-cells = <2>;
234 reg = <0xea0000 0x400>; 296 reg = <0xea0000 0x400>;
235 clocks = <&refclk>; 297 clocks = <&refclk>;
236 clock-names = "refclk"; 298 clock-names = "refclk";
@@ -241,6 +303,26 @@
241 }; 303 };
242 }; 304 };
243 305
306 usb0: usb@ed0000 {
307 compatible = "chipidea,usb2";
308 reg = <0xed0000 0x200>;
309 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&chip CLKID_USB0>;
311 phys = <&usb_phy0>;
312 phy-names = "usb-phy";
313 status = "disabled";
314 };
315
316 usb1: usb@ee0000 {
317 compatible = "chipidea,usb2";
318 reg = <0xee0000 0x200>;
319 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&chip CLKID_USB1>;
321 phys = <&usb_phy1>;
322 phy-names = "usb-phy";
323 status = "disabled";
324 };
325
244 apb@fc0000 { 326 apb@fc0000 {
245 compatible = "simple-bus"; 327 compatible = "simple-bus";
246 #address-cells = <1>; 328 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
index ea1f99b8eed6..28e7e2060c33 100644
--- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
+++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
@@ -7,6 +7,8 @@
7 */ 7 */
8 8
9/dts-v1/; 9/dts-v1/;
10
11#include <dt-bindings/gpio/gpio.h>
10#include "berlin2q.dtsi" 12#include "berlin2q.dtsi"
11 13
12/ { 14/ {
@@ -21,6 +23,39 @@
21 choosen { 23 choosen {
22 bootargs = "console=ttyS0,115200 earlyprintk"; 24 bootargs = "console=ttyS0,115200 earlyprintk";
23 }; 25 };
26
27 regulators {
28 compatible = "simple-bus";
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 reg_usb0_vbus: regulator@0 {
33 compatible = "regulator-fixed";
34 regulator-name = "usb0_vbus";
35 regulator-min-microvolt = <5000000>;
36 regulator-max-microvolt = <5000000>;
37 gpio = <&portb 8 GPIO_ACTIVE_HIGH>;
38 enable-active-high;
39 };
40
41 reg_usb1_vbus: regulator@1 {
42 compatible = "regulator-fixed";
43 regulator-name = "usb1_vbus";
44 regulator-min-microvolt = <5000000>;
45 regulator-max-microvolt = <5000000>;
46 gpio = <&portb 10 GPIO_ACTIVE_HIGH>;
47 enable-active-high;
48 };
49
50 reg_usb2_vbus: regulator@2 {
51 compatible = "regulator-fixed";
52 regulator-name = "usb2_vbus";
53 regulator-min-microvolt = <5000000>;
54 regulator-max-microvolt = <5000000>;
55 gpio = <&portb 12 GPIO_ACTIVE_HIGH>;
56 enable-active-high;
57 };
58 };
24}; 59};
25 60
26&sdhci1 { 61&sdhci1 {
@@ -46,6 +81,32 @@
46 status = "okay"; 81 status = "okay";
47}; 82};
48 83
84&usb_phy0 {
85 status = "okay";
86};
87
88&usb_phy2 {
89 status = "okay";
90};
91
92&usb0 {
93 vbus-supply = <&reg_usb0_vbus>;
94 status = "okay";
95};
96
97&usb2 {
98 vbus-supply = <&reg_usb2_vbus>;
99 status = "okay";
100};
101
49&eth0 { 102&eth0 {
50 status = "okay"; 103 status = "okay";
51}; 104};
105
106&sata0 {
107 status = "okay";
108};
109
110&sata_phy {
111 status = "okay";
112};
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 891d56b03922..35253c947a7c 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -114,6 +114,40 @@
114 #interrupt-cells = <3>; 114 #interrupt-cells = <3>;
115 }; 115 };
116 116
117 usb_phy2: phy@a2f400 {
118 compatible = "marvell,berlin2-usb-phy";
119 reg = <0xa2f400 0x128>;
120 #phy-cells = <0>;
121 resets = <&chip 0x104 14>;
122 status = "disabled";
123 };
124
125 usb2: usb@a30000 {
126 compatible = "chipidea,usb2";
127 reg = <0xa30000 0x10000>;
128 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&chip CLKID_USB2>;
130 phys = <&usb_phy2>;
131 phy-names = "usb-phy";
132 status = "disabled";
133 };
134
135 usb_phy0: phy@b74000 {
136 compatible = "marvell,berlin2-usb-phy";
137 reg = <0xb74000 0x128>;
138 #phy-cells = <0>;
139 resets = <&chip 0x104 12>;
140 status = "disabled";
141 };
142
143 usb_phy1: phy@b78000 {
144 compatible = "marvell,berlin2-usb-phy";
145 reg = <0xb78000 0x128>;
146 #phy-cells = <0>;
147 resets = <&chip 0x104 13>;
148 status = "disabled";
149 };
150
117 eth0: ethernet@b90000 { 151 eth0: ethernet@b90000 {
118 compatible = "marvell,pxa168-eth"; 152 compatible = "marvell,pxa168-eth";
119 reg = <0xb90000 0x10000>; 153 reg = <0xb90000 0x10000>;
@@ -123,6 +157,7 @@
123 local-mac-address = [00 00 00 00 00 00]; 157 local-mac-address = [00 00 00 00 00 00];
124 #address-cells = <1>; 158 #address-cells = <1>;
125 #size-cells = <0>; 159 #size-cells = <0>;
160 phy-connection-type = "mii";
126 phy-handle = <&ethphy0>; 161 phy-handle = <&ethphy0>;
127 status = "disabled"; 162 status = "disabled";
128 163
@@ -255,7 +290,6 @@
255 reg = <0x2c14 0x14>; 290 reg = <0x2c14 0x14>;
256 clocks = <&chip CLKID_CFG>; 291 clocks = <&chip CLKID_CFG>;
257 clock-names = "timer"; 292 clock-names = "timer";
258 status = "disabled";
259 }; 293 };
260 294
261 timer2: timer@2c28 { 295 timer2: timer@2c28 {
@@ -349,6 +383,7 @@
349 chip: chip-control@ea0000 { 383 chip: chip-control@ea0000 {
350 compatible = "marvell,berlin2q-chip-ctrl"; 384 compatible = "marvell,berlin2q-chip-ctrl";
351 #clock-cells = <1>; 385 #clock-cells = <1>;
386 #reset-cells = <2>;
352 reg = <0xea0000 0x400>, <0xdd0170 0x10>; 387 reg = <0xea0000 0x400>, <0xdd0170 0x10>;
353 clocks = <&refclk>; 388 clocks = <&refclk>;
354 clock-names = "refclk"; 389 clock-names = "refclk";
@@ -364,6 +399,65 @@
364 }; 399 };
365 }; 400 };
366 401
402 ahci: sata@e90000 {
403 compatible = "marvell,berlin2q-ahci", "generic-ahci";
404 reg = <0xe90000 0x1000>;
405 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&chip CLKID_SATA>;
407 #address-cells = <1>;
408 #size-cells = <0>;
409
410 sata0: sata-port@0 {
411 reg = <0>;
412 phys = <&sata_phy 0>;
413 status = "disabled";
414 };
415
416 sata1: sata-port@1 {
417 reg = <1>;
418 phys = <&sata_phy 1>;
419 status = "disabled";
420 };
421 };
422
423 sata_phy: phy@e900a0 {
424 compatible = "marvell,berlin2q-sata-phy";
425 reg = <0xe900a0 0x200>;
426 clocks = <&chip CLKID_SATA>;
427 #address-cells = <1>;
428 #size-cells = <0>;
429 #phy-cells = <1>;
430 status = "disabled";
431
432 sata-phy@0 {
433 reg = <0>;
434 };
435
436 sata-phy@1 {
437 reg = <1>;
438 };
439 };
440
441 usb0: usb@ed0000 {
442 compatible = "chipidea,usb2";
443 reg = <0xed0000 0x10000>;
444 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&chip CLKID_USB0>;
446 phys = <&usb_phy0>;
447 phy-names = "usb-phy";
448 status = "disabled";
449 };
450
451 usb1: usb@ee0000 {
452 compatible = "chipidea,usb2";
453 reg = <0xee0000 0x10000>;
454 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&chip CLKID_USB1>;
456 phys = <&usb_phy1>;
457 phy-names = "usb-phy";
458 status = "disabled";
459 };
460
367 apb@fc0000 { 461 apb@fc0000 {
368 compatible = "simple-bus"; 462 compatible = "simple-bus";
369 #address-cells = <1>; 463 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index c6ce6258434f..0d8a3bd0f00d 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -171,6 +171,86 @@
171 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ 171 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
172 >; 172 >;
173 }; 173 };
174
175 cpsw_default: cpsw_default {
176 pinctrl-single,pins = <
177 /* Slave 1 */
178 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
179 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
180 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
181 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
182 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
183 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
184 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
185 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
186 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
187 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
188 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
189 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
190
191 /* Slave 2 */
192 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
193 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
194 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
195 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
196 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
197 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
198 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
199 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
200 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
201 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
202 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
203 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
204 >;
205
206 };
207
208 cpsw_sleep: cpsw_sleep {
209 pinctrl-single,pins = <
210 /* Slave 1 */
211 0x250 (MUX_MODE15)
212 0x254 (MUX_MODE15)
213 0x258 (MUX_MODE15)
214 0x25c (MUX_MODE15)
215 0x260 (MUX_MODE15)
216 0x264 (MUX_MODE15)
217 0x268 (MUX_MODE15)
218 0x26c (MUX_MODE15)
219 0x270 (MUX_MODE15)
220 0x274 (MUX_MODE15)
221 0x278 (MUX_MODE15)
222 0x27c (MUX_MODE15)
223
224 /* Slave 2 */
225 0x198 (MUX_MODE15)
226 0x19c (MUX_MODE15)
227 0x1a0 (MUX_MODE15)
228 0x1a4 (MUX_MODE15)
229 0x1a8 (MUX_MODE15)
230 0x1ac (MUX_MODE15)
231 0x1b0 (MUX_MODE15)
232 0x1b4 (MUX_MODE15)
233 0x1b8 (MUX_MODE15)
234 0x1bc (MUX_MODE15)
235 0x1c0 (MUX_MODE15)
236 0x1c4 (MUX_MODE15)
237 >;
238 };
239
240 davinci_mdio_default: davinci_mdio_default {
241 pinctrl-single,pins = <
242 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
243 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
244 >;
245 };
246
247 davinci_mdio_sleep: davinci_mdio_sleep {
248 pinctrl-single,pins = <
249 0x23c (MUX_MODE15)
250 0x240 (MUX_MODE15)
251 >;
252 };
253
174}; 254};
175 255
176&i2c1 { 256&i2c1 {
@@ -201,6 +281,7 @@
201 regulator-name = "smps45"; 281 regulator-name = "smps45";
202 regulator-min-microvolt = < 850000>; 282 regulator-min-microvolt = < 850000>;
203 regulator-max-microvolt = <1150000>; 283 regulator-max-microvolt = <1150000>;
284 regulator-always-on;
204 regulator-boot-on; 285 regulator-boot-on;
205 }; 286 };
206 287
@@ -209,6 +290,7 @@
209 regulator-name = "smps6"; 290 regulator-name = "smps6";
210 regulator-min-microvolt = <850000>; 291 regulator-min-microvolt = <850000>;
211 regulator-max-microvolt = <12500000>; 292 regulator-max-microvolt = <12500000>;
293 regulator-always-on;
212 regulator-boot-on; 294 regulator-boot-on;
213 }; 295 };
214 296
@@ -226,6 +308,7 @@
226 regulator-name = "smps8"; 308 regulator-name = "smps8";
227 regulator-min-microvolt = < 850000>; 309 regulator-min-microvolt = < 850000>;
228 regulator-max-microvolt = <1250000>; 310 regulator-max-microvolt = <1250000>;
311 regulator-always-on;
229 regulator-boot-on; 312 regulator-boot-on;
230 }; 313 };
231 314
@@ -252,6 +335,7 @@
252 regulator-name = "ldo2"; 335 regulator-name = "ldo2";
253 regulator-min-microvolt = <3300000>; 336 regulator-min-microvolt = <3300000>;
254 regulator-max-microvolt = <3300000>; 337 regulator-max-microvolt = <3300000>;
338 regulator-always-on;
255 regulator-boot-on; 339 regulator-boot-on;
256 }; 340 };
257 341
@@ -269,6 +353,7 @@
269 regulator-name = "ldo9"; 353 regulator-name = "ldo9";
270 regulator-min-microvolt = <1050000>; 354 regulator-min-microvolt = <1050000>;
271 regulator-max-microvolt = <1050000>; 355 regulator-max-microvolt = <1050000>;
356 regulator-always-on;
272 regulator-boot-on; 357 regulator-boot-on;
273 }; 358 };
274 359
@@ -528,3 +613,29 @@
528 ti,no-reset-on-init; 613 ti,no-reset-on-init;
529 ti,no-idle-on-init; 614 ti,no-idle-on-init;
530}; 615};
616
617&mac {
618 status = "okay";
619 pinctrl-names = "default", "sleep";
620 pinctrl-0 = <&cpsw_default>;
621 pinctrl-1 = <&cpsw_sleep>;
622 dual_emac;
623};
624
625&cpsw_emac0 {
626 phy_id = <&davinci_mdio>, <2>;
627 phy-mode = "rgmii";
628 dual_emac_res_vlan = <1>;
629};
630
631&cpsw_emac1 {
632 phy_id = <&davinci_mdio>, <3>;
633 phy-mode = "rgmii";
634 dual_emac_res_vlan = <2>;
635};
636
637&davinci_mdio {
638 pinctrl-names = "default", "sleep";
639 pinctrl-0 = <&davinci_mdio_default>;
640 pinctrl-1 = <&davinci_mdio_sleep>;
641};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 9cc98436a982..9cd99b931302 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -34,6 +34,12 @@
34 serial3 = &uart4; 34 serial3 = &uart4;
35 serial4 = &uart5; 35 serial4 = &uart5;
36 serial5 = &uart6; 36 serial5 = &uart6;
37 serial6 = &uart7;
38 serial7 = &uart8;
39 serial8 = &uart9;
40 serial9 = &uart10;
41 ethernet0 = &cpsw_emac0;
42 ethernet1 = &cpsw_emac1;
37 }; 43 };
38 44
39 timer { 45 timer {
@@ -335,6 +341,8 @@
335 ti,hwmods = "uart1"; 341 ti,hwmods = "uart1";
336 clock-frequency = <48000000>; 342 clock-frequency = <48000000>;
337 status = "disabled"; 343 status = "disabled";
344 dmas = <&sdma 49>, <&sdma 50>;
345 dma-names = "tx", "rx";
338 }; 346 };
339 347
340 uart2: serial@4806c000 { 348 uart2: serial@4806c000 {
@@ -344,6 +352,8 @@
344 ti,hwmods = "uart2"; 352 ti,hwmods = "uart2";
345 clock-frequency = <48000000>; 353 clock-frequency = <48000000>;
346 status = "disabled"; 354 status = "disabled";
355 dmas = <&sdma 51>, <&sdma 52>;
356 dma-names = "tx", "rx";
347 }; 357 };
348 358
349 uart3: serial@48020000 { 359 uart3: serial@48020000 {
@@ -353,6 +363,8 @@
353 ti,hwmods = "uart3"; 363 ti,hwmods = "uart3";
354 clock-frequency = <48000000>; 364 clock-frequency = <48000000>;
355 status = "disabled"; 365 status = "disabled";
366 dmas = <&sdma 53>, <&sdma 54>;
367 dma-names = "tx", "rx";
356 }; 368 };
357 369
358 uart4: serial@4806e000 { 370 uart4: serial@4806e000 {
@@ -362,6 +374,8 @@
362 ti,hwmods = "uart4"; 374 ti,hwmods = "uart4";
363 clock-frequency = <48000000>; 375 clock-frequency = <48000000>;
364 status = "disabled"; 376 status = "disabled";
377 dmas = <&sdma 55>, <&sdma 56>;
378 dma-names = "tx", "rx";
365 }; 379 };
366 380
367 uart5: serial@48066000 { 381 uart5: serial@48066000 {
@@ -371,6 +385,8 @@
371 ti,hwmods = "uart5"; 385 ti,hwmods = "uart5";
372 clock-frequency = <48000000>; 386 clock-frequency = <48000000>;
373 status = "disabled"; 387 status = "disabled";
388 dmas = <&sdma 63>, <&sdma 64>;
389 dma-names = "tx", "rx";
374 }; 390 };
375 391
376 uart6: serial@48068000 { 392 uart6: serial@48068000 {
@@ -380,6 +396,8 @@
380 ti,hwmods = "uart6"; 396 ti,hwmods = "uart6";
381 clock-frequency = <48000000>; 397 clock-frequency = <48000000>;
382 status = "disabled"; 398 status = "disabled";
399 dmas = <&sdma 79>, <&sdma 80>;
400 dma-names = "tx", "rx";
383 }; 401 };
384 402
385 uart7: serial@48420000 { 403 uart7: serial@48420000 {
@@ -421,7 +439,11 @@
421 mailbox1: mailbox@4a0f4000 { 439 mailbox1: mailbox@4a0f4000 {
422 compatible = "ti,omap4-mailbox"; 440 compatible = "ti,omap4-mailbox";
423 reg = <0x4a0f4000 0x200>; 441 reg = <0x4a0f4000 0x200>;
442 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
424 ti,hwmods = "mailbox1"; 445 ti,hwmods = "mailbox1";
446 #mbox-cells = <1>;
425 ti,mbox-num-users = <3>; 447 ti,mbox-num-users = <3>;
426 ti,mbox-num-fifos = <8>; 448 ti,mbox-num-fifos = <8>;
427 status = "disabled"; 449 status = "disabled";
@@ -430,7 +452,12 @@
430 mailbox2: mailbox@4883a000 { 452 mailbox2: mailbox@4883a000 {
431 compatible = "ti,omap4-mailbox"; 453 compatible = "ti,omap4-mailbox";
432 reg = <0x4883a000 0x200>; 454 reg = <0x4883a000 0x200>;
455 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
433 ti,hwmods = "mailbox2"; 459 ti,hwmods = "mailbox2";
460 #mbox-cells = <1>;
434 ti,mbox-num-users = <4>; 461 ti,mbox-num-users = <4>;
435 ti,mbox-num-fifos = <12>; 462 ti,mbox-num-fifos = <12>;
436 status = "disabled"; 463 status = "disabled";
@@ -439,7 +466,12 @@
439 mailbox3: mailbox@4883c000 { 466 mailbox3: mailbox@4883c000 {
440 compatible = "ti,omap4-mailbox"; 467 compatible = "ti,omap4-mailbox";
441 reg = <0x4883c000 0x200>; 468 reg = <0x4883c000 0x200>;
469 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
442 ti,hwmods = "mailbox3"; 473 ti,hwmods = "mailbox3";
474 #mbox-cells = <1>;
443 ti,mbox-num-users = <4>; 475 ti,mbox-num-users = <4>;
444 ti,mbox-num-fifos = <12>; 476 ti,mbox-num-fifos = <12>;
445 status = "disabled"; 477 status = "disabled";
@@ -448,7 +480,12 @@
448 mailbox4: mailbox@4883e000 { 480 mailbox4: mailbox@4883e000 {
449 compatible = "ti,omap4-mailbox"; 481 compatible = "ti,omap4-mailbox";
450 reg = <0x4883e000 0x200>; 482 reg = <0x4883e000 0x200>;
483 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
485 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
451 ti,hwmods = "mailbox4"; 487 ti,hwmods = "mailbox4";
488 #mbox-cells = <1>;
452 ti,mbox-num-users = <4>; 489 ti,mbox-num-users = <4>;
453 ti,mbox-num-fifos = <12>; 490 ti,mbox-num-fifos = <12>;
454 status = "disabled"; 491 status = "disabled";
@@ -457,7 +494,12 @@
457 mailbox5: mailbox@48840000 { 494 mailbox5: mailbox@48840000 {
458 compatible = "ti,omap4-mailbox"; 495 compatible = "ti,omap4-mailbox";
459 reg = <0x48840000 0x200>; 496 reg = <0x48840000 0x200>;
497 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
460 ti,hwmods = "mailbox5"; 501 ti,hwmods = "mailbox5";
502 #mbox-cells = <1>;
461 ti,mbox-num-users = <4>; 503 ti,mbox-num-users = <4>;
462 ti,mbox-num-fifos = <12>; 504 ti,mbox-num-fifos = <12>;
463 status = "disabled"; 505 status = "disabled";
@@ -466,7 +508,12 @@
466 mailbox6: mailbox@48842000 { 508 mailbox6: mailbox@48842000 {
467 compatible = "ti,omap4-mailbox"; 509 compatible = "ti,omap4-mailbox";
468 reg = <0x48842000 0x200>; 510 reg = <0x48842000 0x200>;
511 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
469 ti,hwmods = "mailbox6"; 515 ti,hwmods = "mailbox6";
516 #mbox-cells = <1>;
470 ti,mbox-num-users = <4>; 517 ti,mbox-num-users = <4>;
471 ti,mbox-num-fifos = <12>; 518 ti,mbox-num-fifos = <12>;
472 status = "disabled"; 519 status = "disabled";
@@ -475,7 +522,12 @@
475 mailbox7: mailbox@48844000 { 522 mailbox7: mailbox@48844000 {
476 compatible = "ti,omap4-mailbox"; 523 compatible = "ti,omap4-mailbox";
477 reg = <0x48844000 0x200>; 524 reg = <0x48844000 0x200>;
525 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
478 ti,hwmods = "mailbox7"; 529 ti,hwmods = "mailbox7";
530 #mbox-cells = <1>;
479 ti,mbox-num-users = <4>; 531 ti,mbox-num-users = <4>;
480 ti,mbox-num-fifos = <12>; 532 ti,mbox-num-fifos = <12>;
481 status = "disabled"; 533 status = "disabled";
@@ -484,7 +536,12 @@
484 mailbox8: mailbox@48846000 { 536 mailbox8: mailbox@48846000 {
485 compatible = "ti,omap4-mailbox"; 537 compatible = "ti,omap4-mailbox";
486 reg = <0x48846000 0x200>; 538 reg = <0x48846000 0x200>;
539 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
487 ti,hwmods = "mailbox8"; 543 ti,hwmods = "mailbox8";
544 #mbox-cells = <1>;
488 ti,mbox-num-users = <4>; 545 ti,mbox-num-users = <4>;
489 ti,mbox-num-fifos = <12>; 546 ti,mbox-num-fifos = <12>;
490 status = "disabled"; 547 status = "disabled";
@@ -493,7 +550,12 @@
493 mailbox9: mailbox@4885e000 { 550 mailbox9: mailbox@4885e000 {
494 compatible = "ti,omap4-mailbox"; 551 compatible = "ti,omap4-mailbox";
495 reg = <0x4885e000 0x200>; 552 reg = <0x4885e000 0x200>;
553 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
496 ti,hwmods = "mailbox9"; 557 ti,hwmods = "mailbox9";
558 #mbox-cells = <1>;
497 ti,mbox-num-users = <4>; 559 ti,mbox-num-users = <4>;
498 ti,mbox-num-fifos = <12>; 560 ti,mbox-num-fifos = <12>;
499 status = "disabled"; 561 status = "disabled";
@@ -502,7 +564,12 @@
502 mailbox10: mailbox@48860000 { 564 mailbox10: mailbox@48860000 {
503 compatible = "ti,omap4-mailbox"; 565 compatible = "ti,omap4-mailbox";
504 reg = <0x48860000 0x200>; 566 reg = <0x48860000 0x200>;
567 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
505 ti,hwmods = "mailbox10"; 571 ti,hwmods = "mailbox10";
572 #mbox-cells = <1>;
506 ti,mbox-num-users = <4>; 573 ti,mbox-num-users = <4>;
507 ti,mbox-num-fifos = <12>; 574 ti,mbox-num-fifos = <12>;
508 status = "disabled"; 575 status = "disabled";
@@ -511,7 +578,12 @@
511 mailbox11: mailbox@48862000 { 578 mailbox11: mailbox@48862000 {
512 compatible = "ti,omap4-mailbox"; 579 compatible = "ti,omap4-mailbox";
513 reg = <0x48862000 0x200>; 580 reg = <0x48862000 0x200>;
581 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
514 ti,hwmods = "mailbox11"; 585 ti,hwmods = "mailbox11";
586 #mbox-cells = <1>;
515 ti,mbox-num-users = <4>; 587 ti,mbox-num-users = <4>;
516 ti,mbox-num-fifos = <12>; 588 ti,mbox-num-fifos = <12>;
517 status = "disabled"; 589 status = "disabled";
@@ -520,7 +592,12 @@
520 mailbox12: mailbox@48864000 { 592 mailbox12: mailbox@48864000 {
521 compatible = "ti,omap4-mailbox"; 593 compatible = "ti,omap4-mailbox";
522 reg = <0x48864000 0x200>; 594 reg = <0x48864000 0x200>;
595 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
523 ti,hwmods = "mailbox12"; 599 ti,hwmods = "mailbox12";
600 #mbox-cells = <1>;
524 ti,mbox-num-users = <4>; 601 ti,mbox-num-users = <4>;
525 ti,mbox-num-fifos = <12>; 602 ti,mbox-num-fifos = <12>;
526 status = "disabled"; 603 status = "disabled";
@@ -529,7 +606,12 @@
529 mailbox13: mailbox@48802000 { 606 mailbox13: mailbox@48802000 {
530 compatible = "ti,omap4-mailbox"; 607 compatible = "ti,omap4-mailbox";
531 reg = <0x48802000 0x200>; 608 reg = <0x48802000 0x200>;
609 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
532 ti,hwmods = "mailbox13"; 613 ti,hwmods = "mailbox13";
614 #mbox-cells = <1>;
533 ti,mbox-num-users = <4>; 615 ti,mbox-num-users = <4>;
534 ti,mbox-num-fifos = <12>; 616 ti,mbox-num-fifos = <12>;
535 status = "disabled"; 617 status = "disabled";
@@ -1141,7 +1223,7 @@
1141 }; 1223 };
1142 }; 1224 };
1143 1225
1144 omap_dwc3_1@48880000 { 1226 omap_dwc3_1: omap_dwc3_1@48880000 {
1145 compatible = "ti,dwc3"; 1227 compatible = "ti,dwc3";
1146 ti,hwmods = "usb_otg_ss1"; 1228 ti,hwmods = "usb_otg_ss1";
1147 reg = <0x48880000 0x10000>; 1229 reg = <0x48880000 0x10000>;
@@ -1162,7 +1244,7 @@
1162 }; 1244 };
1163 }; 1245 };
1164 1246
1165 omap_dwc3_2@488c0000 { 1247 omap_dwc3_2: omap_dwc3_2@488c0000 {
1166 compatible = "ti,dwc3"; 1248 compatible = "ti,dwc3";
1167 ti,hwmods = "usb_otg_ss2"; 1249 ti,hwmods = "usb_otg_ss2";
1168 reg = <0x488c0000 0x10000>; 1250 reg = <0x488c0000 0x10000>;
@@ -1184,7 +1266,7 @@
1184 }; 1266 };
1185 1267
1186 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ 1268 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1187 omap_dwc3_3@48900000 { 1269 omap_dwc3_3: omap_dwc3_3@48900000 {
1188 compatible = "ti,dwc3"; 1270 compatible = "ti,dwc3";
1189 ti,hwmods = "usb_otg_ss3"; 1271 ti,hwmods = "usb_otg_ss3";
1190 reg = <0x48900000 0x10000>; 1272 reg = <0x48900000 0x10000>;
@@ -1204,26 +1286,6 @@
1204 }; 1286 };
1205 }; 1287 };
1206 1288
1207 omap_dwc3_4@48940000 {
1208 compatible = "ti,dwc3";
1209 ti,hwmods = "usb_otg_ss4";
1210 reg = <0x48940000 0x10000>;
1211 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
1212 #address-cells = <1>;
1213 #size-cells = <1>;
1214 utmi-mode = <2>;
1215 ranges;
1216 status = "disabled";
1217 usb4: usb@48950000 {
1218 compatible = "snps,dwc3";
1219 reg = <0x48950000 0x17000>;
1220 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
1221 tx-fifo-resize;
1222 maximum-speed = "high-speed";
1223 dr_mode = "otg";
1224 };
1225 };
1226
1227 elm: elm@48078000 { 1289 elm: elm@48078000 {
1228 compatible = "ti,am3352-elm"; 1290 compatible = "ti,am3352-elm";
1229 reg = <0x48078000 0xfc0>; /* device IO registers */ 1291 reg = <0x48078000 0xfc0>; /* device IO registers */
@@ -1265,6 +1327,65 @@
1265 ti,irqs-skip = <10 133 139 140>; 1327 ti,irqs-skip = <10 133 139 140>;
1266 ti,irqs-safe-map = <0>; 1328 ti,irqs-safe-map = <0>;
1267 }; 1329 };
1330
1331 mac: ethernet@4a100000 {
1332 compatible = "ti,cpsw";
1333 ti,hwmods = "gmac";
1334 clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1335 clock-names = "fck", "cpts";
1336 cpdma_channels = <8>;
1337 ale_entries = <1024>;
1338 bd_ram_size = <0x2000>;
1339 no_bd_ram = <0>;
1340 rx_descs = <64>;
1341 mac_control = <0x20>;
1342 slaves = <2>;
1343 active_slave = <0>;
1344 cpts_clock_mult = <0x80000000>;
1345 cpts_clock_shift = <29>;
1346 reg = <0x48484000 0x1000
1347 0x48485200 0x2E00>;
1348 #address-cells = <1>;
1349 #size-cells = <1>;
1350 /*
1351 * rx_thresh_pend
1352 * rx_pend
1353 * tx_pend
1354 * misc_pend
1355 */
1356 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1357 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1359 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1360 ranges;
1361 status = "disabled";
1362
1363 davinci_mdio: mdio@48485000 {
1364 compatible = "ti,davinci_mdio";
1365 #address-cells = <1>;
1366 #size-cells = <0>;
1367 ti,hwmods = "davinci_mdio";
1368 bus_freq = <1000000>;
1369 reg = <0x48485000 0x100>;
1370 };
1371
1372 cpsw_emac0: slave@48480200 {
1373 /* Filled in by U-Boot */
1374 mac-address = [ 00 00 00 00 00 00 ];
1375 };
1376
1377 cpsw_emac1: slave@48480300 {
1378 /* Filled in by U-Boot */
1379 mac-address = [ 00 00 00 00 00 00 ];
1380 };
1381
1382 phy_sel: cpsw-phy-sel@4a002554 {
1383 compatible = "ti,dra7xx-cpsw-phy-sel";
1384 reg= <0x4a002554 0x4>;
1385 reg-names = "gmii-sel";
1386 };
1387 };
1388
1268 }; 1389 };
1269}; 1390};
1270 1391
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 41074288adfa..abbaaa782f88 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -17,6 +17,13 @@
17 device_type = "memory"; 17 device_type = "memory";
18 reg = <0x80000000 0x40000000>; /* 1024 MB */ 18 reg = <0x80000000 0x40000000>; /* 1024 MB */
19 }; 19 };
20
21 evm_3v3: fixedregulator-evm_3v3 {
22 compatible = "regulator-fixed";
23 regulator-name = "evm_3v3";
24 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>;
26 };
20}; 27};
21 28
22&dra7_pmx_core { 29&dra7_pmx_core {
@@ -26,6 +33,78 @@
26 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ 33 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
27 >; 34 >;
28 }; 35 };
36
37 nand_default: nand_default {
38 pinctrl-single,pins = <
39 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
40 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
41 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
42 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
43 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
44 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
45 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
46 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
47 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
48 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
49 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
50 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
51 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
52 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
53 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
54 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
55 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
56 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
57 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
58 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
59 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
60 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
61 >;
62 };
63
64 usb1_pins: pinmux_usb1_pins {
65 pinctrl-single,pins = <
66 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
67 >;
68 };
69
70 usb2_pins: pinmux_usb2_pins {
71 pinctrl-single,pins = <
72 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
73 >;
74 };
75
76 tps65917_pins_default: tps65917_pins_default {
77 pinctrl-single,pins = <
78 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
79 >;
80 };
81
82 mmc1_pins_default: mmc1_pins_default {
83 pinctrl-single,pins = <
84 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
85 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
86 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
87 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
88 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
89 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
90 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
91 >;
92 };
93
94 mmc2_pins_default: mmc2_pins_default {
95 pinctrl-single,pins = <
96 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
97 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
98 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
99 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
100 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
101 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
102 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
103 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
104 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
105 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
106 >;
107 };
29}; 108};
30 109
31&i2c1 { 110&i2c1 {
@@ -38,6 +117,9 @@
38 compatible = "ti,tps65917"; 117 compatible = "ti,tps65917";
39 reg = <0x58>; 118 reg = <0x58>;
40 119
120 pinctrl-names = "default";
121 pinctrl-0 = <&tps65917_pins_default>;
122
41 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ 123 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
42 interrupt-parent = <&gic>; 124 interrupt-parent = <&gic>;
43 interrupt-controller; 125 interrupt-controller;
@@ -136,9 +218,223 @@
136 }; 218 };
137 }; 219 };
138 }; 220 };
221
222 tps65917_power_button {
223 compatible = "ti,palmas-pwrbutton";
224 interrupt-parent = <&tps65917>;
225 interrupts = <1 IRQ_TYPE_NONE>;
226 wakeup-source;
227 ti,palmas-long-press-seconds = <6>;
228 };
139 }; 229 };
140}; 230};
141 231
142&uart1 { 232&uart1 {
143 status = "okay"; 233 status = "okay";
144}; 234};
235
236&elm {
237 status = "okay";
238};
239
240&gpmc {
241 status = "okay";
242 pinctrl-names = "default";
243 pinctrl-0 = <&nand_default>;
244 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
245 nand@0,0 {
246 /* To use NAND, DIP switch SW5 must be set like so:
247 * SW5.1 (NAND_SELn) = ON (LOW)
248 * SW5.9 (GPMC_WPN) = OFF (HIGH)
249 */
250 reg = <0 0 4>; /* device IO registers */
251 ti,nand-ecc-opt = "bch8";
252 ti,elm-id = <&elm>;
253 nand-bus-width = <16>;
254 gpmc,device-width = <2>;
255 gpmc,sync-clk-ps = <0>;
256 gpmc,cs-on-ns = <0>;
257 gpmc,cs-rd-off-ns = <80>;
258 gpmc,cs-wr-off-ns = <80>;
259 gpmc,adv-on-ns = <0>;
260 gpmc,adv-rd-off-ns = <60>;
261 gpmc,adv-wr-off-ns = <60>;
262 gpmc,we-on-ns = <10>;
263 gpmc,we-off-ns = <50>;
264 gpmc,oe-on-ns = <4>;
265 gpmc,oe-off-ns = <40>;
266 gpmc,access-ns = <40>;
267 gpmc,wr-access-ns = <80>;
268 gpmc,rd-cycle-ns = <80>;
269 gpmc,wr-cycle-ns = <80>;
270 gpmc,bus-turnaround-ns = <0>;
271 gpmc,cycle2cycle-delay-ns = <0>;
272 gpmc,clk-activation-ns = <0>;
273 gpmc,wait-monitoring-ns = <0>;
274 gpmc,wr-data-mux-bus-ns = <0>;
275 /* MTD partition table */
276 /* All SPL-* partitions are sized to minimal length
277 * which can be independently programmable. For
278 * NAND flash this is equal to size of erase-block */
279 #address-cells = <1>;
280 #size-cells = <1>;
281 partition@0 {
282 label = "NAND.SPL";
283 reg = <0x00000000 0x000020000>;
284 };
285 partition@1 {
286 label = "NAND.SPL.backup1";
287 reg = <0x00020000 0x00020000>;
288 };
289 partition@2 {
290 label = "NAND.SPL.backup2";
291 reg = <0x00040000 0x00020000>;
292 };
293 partition@3 {
294 label = "NAND.SPL.backup3";
295 reg = <0x00060000 0x00020000>;
296 };
297 partition@4 {
298 label = "NAND.u-boot-spl-os";
299 reg = <0x00080000 0x00040000>;
300 };
301 partition@5 {
302 label = "NAND.u-boot";
303 reg = <0x000c0000 0x00100000>;
304 };
305 partition@6 {
306 label = "NAND.u-boot-env";
307 reg = <0x001c0000 0x00020000>;
308 };
309 partition@7 {
310 label = "NAND.u-boot-env.backup1";
311 reg = <0x001e0000 0x00020000>;
312 };
313 partition@8 {
314 label = "NAND.kernel";
315 reg = <0x00200000 0x00800000>;
316 };
317 partition@9 {
318 label = "NAND.file-system";
319 reg = <0x00a00000 0x0f600000>;
320 };
321 };
322};
323
324&usb2_phy1 {
325 phy-supply = <&ldo4_reg>;
326};
327
328&usb2_phy2 {
329 phy-supply = <&ldo4_reg>;
330};
331
332&usb1 {
333 dr_mode = "peripheral";
334 pinctrl-names = "default";
335 pinctrl-0 = <&usb1_pins>;
336};
337
338&usb2 {
339 dr_mode = "host";
340 pinctrl-names = "default";
341 pinctrl-0 = <&usb2_pins>;
342};
343
344&mmc1 {
345 status = "okay";
346 pinctrl-names = "default";
347 pinctrl-0 = <&mmc1_pins_default>;
348
349 vmmc-supply = <&ldo1_reg>;
350 bus-width = <4>;
351 /*
352 * SDCD signal is not being used here - using the fact that GPIO mode
353 * is a viable alternative
354 */
355 cd-gpios = <&gpio6 27 0>;
356};
357
358&mmc2 {
359 /* SW5-3 in ON position */
360 status = "okay";
361 pinctrl-names = "default";
362 pinctrl-0 = <&mmc2_pins_default>;
363
364 vmmc-supply = <&evm_3v3>;
365 bus-width = <8>;
366 ti,non-removable;
367};
368
369&dra7_pmx_core {
370 cpsw_default: cpsw_default {
371 pinctrl-single,pins = <
372 /* Slave 2 */
373 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
374 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
375 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
376 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
377 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
378 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
379 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
380 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
381 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
382 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
383 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
384 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
385 >;
386
387 };
388
389 cpsw_sleep: cpsw_sleep {
390 pinctrl-single,pins = <
391 /* Slave 2 */
392 0x198 (MUX_MODE15)
393 0x19c (MUX_MODE15)
394 0x1a0 (MUX_MODE15)
395 0x1a4 (MUX_MODE15)
396 0x1a8 (MUX_MODE15)
397 0x1ac (MUX_MODE15)
398 0x1b0 (MUX_MODE15)
399 0x1b4 (MUX_MODE15)
400 0x1b8 (MUX_MODE15)
401 0x1bc (MUX_MODE15)
402 0x1c0 (MUX_MODE15)
403 0x1c4 (MUX_MODE15)
404 >;
405 };
406
407 davinci_mdio_default: davinci_mdio_default {
408 pinctrl-single,pins = <
409 /* MDIO */
410 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
411 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
412 >;
413 };
414
415 davinci_mdio_sleep: davinci_mdio_sleep {
416 pinctrl-single,pins = <
417 0x23c (MUX_MODE15)
418 0x240 (MUX_MODE15)
419 >;
420 };
421};
422
423&mac {
424 status = "okay";
425 pinctrl-names = "default", "sleep";
426 pinctrl-0 = <&cpsw_default>;
427 pinctrl-1 = <&cpsw_sleep>;
428};
429
430&cpsw_emac1 {
431 phy_id = <&davinci_mdio>, <3>;
432 phy-mode = "rgmii";
433};
434
435&davinci_mdio {
436 pinctrl-names = "default", "sleep";
437 pinctrl-0 = <&davinci_mdio_default>;
438 pinctrl-1 = <&davinci_mdio_sleep>;
439 active_slave = <1>;
440};
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 3be544c4891f..10173fab1a15 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -44,4 +44,26 @@
44 interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>, 44 interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>; 45 <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
46 }; 46 };
47
48 ocp {
49 omap_dwc3_4: omap_dwc3_4@48940000 {
50 compatible = "ti,dwc3";
51 ti,hwmods = "usb_otg_ss4";
52 reg = <0x48940000 0x10000>;
53 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
54 #address-cells = <1>;
55 #size-cells = <1>;
56 utmi-mode = <2>;
57 ranges;
58 status = "disabled";
59 usb4: usb@48950000 {
60 compatible = "snps,dwc3";
61 reg = <0x48950000 0x17000>;
62 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
63 tx-fifo-resize;
64 maximum-speed = "high-speed";
65 dr_mode = "otg";
66 };
67 };
68 };
47}; 69};
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index 50ccd151091e..667d323e80a3 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -25,37 +25,7 @@
25 25
26 chosen { 26 chosen {
27 bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp"; 27 bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp";
28 }; 28 stdout-path = &uart1;
29
30 reg_1p8v: regulator@0 {
31 compatible = "regulator-fixed";
32 regulator-name = "fixed-1.8V";
33 regulator-min-microvolt = <1800000>;
34 regulator-max-microvolt = <1800000>;
35 regulator-always-on;
36 regulator-boot-on;
37 };
38
39 reg_3p3v: regulator@1 {
40 compatible = "regulator-fixed";
41 regulator-name = "fixed-3.3V";
42 regulator-min-microvolt = <3300000>;
43 regulator-max-microvolt = <3300000>;
44 regulator-always-on;
45 regulator-boot-on;
46 };
47
48 lan9220@20000000 {
49 compatible = "smsc,lan9220", "smsc,lan9115";
50 reg = <0x20000000 0x10000>;
51 phy-mode = "mii";
52 interrupt-parent = <&gpio0>;
53 interrupts = <1 IRQ_TYPE_EDGE_RISING>;
54 reg-io-width = <4>;
55 smsc,irq-active-high;
56 smsc,irq-push-pull;
57 vddvario-supply = <&reg_1p8v>;
58 vdd33a-supply = <&reg_3p3v>;
59 }; 29 };
60 30
61 gpio_keys { 31 gpio_keys {
@@ -92,4 +62,35 @@
92 gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; 62 gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
93 }; 63 };
94 }; 64 };
65
66 reg_1p8v: regulator@0 {
67 compatible = "regulator-fixed";
68 regulator-name = "fixed-1.8V";
69 regulator-min-microvolt = <1800000>;
70 regulator-max-microvolt = <1800000>;
71 regulator-always-on;
72 regulator-boot-on;
73 };
74
75 reg_3p3v: regulator@1 {
76 compatible = "regulator-fixed";
77 regulator-name = "fixed-3.3V";
78 regulator-min-microvolt = <3300000>;
79 regulator-max-microvolt = <3300000>;
80 regulator-always-on;
81 regulator-boot-on;
82 };
83
84 lan9220@20000000 {
85 compatible = "smsc,lan9220", "smsc,lan9115";
86 reg = <0x20000000 0x10000>;
87 phy-mode = "mii";
88 interrupt-parent = <&gpio0>;
89 interrupts = <1 IRQ_TYPE_EDGE_RISING>;
90 reg-io-width = <4>;
91 smsc,irq-active-high;
92 smsc,irq-push-pull;
93 vddvario-supply = <&reg_1p8v>;
94 vdd33a-supply = <&reg_3p3v>;
95 };
95}; 96};
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index 00eeed3721b6..cc7bfe0ba40a 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -55,7 +55,7 @@
55 <0 121 IRQ_TYPE_LEVEL_HIGH>; 55 <0 121 IRQ_TYPE_LEVEL_HIGH>;
56 }; 56 };
57 57
58 smu@e0110000 { 58 clocks@e0110000 {
59 compatible = "renesas,emev2-smu"; 59 compatible = "renesas,emev2-smu";
60 reg = <0xe0110000 0x10000>; 60 reg = <0xe0110000 0x10000>;
61 #address-cells = <2>; 61 #address-cells = <2>;
@@ -129,7 +129,7 @@
129 }; 129 };
130 }; 130 };
131 131
132 sti@e0180000 { 132 timer@e0180000 {
133 compatible = "renesas,em-sti"; 133 compatible = "renesas,em-sti";
134 reg = <0xe0180000 0x54>; 134 reg = <0xe0180000 0x54>;
135 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; 135 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
@@ -137,7 +137,7 @@
137 clock-names = "sclk"; 137 clock-names = "sclk";
138 }; 138 };
139 139
140 uart@e1020000 { 140 uart0: serial@e1020000 {
141 compatible = "renesas,em-uart"; 141 compatible = "renesas,em-uart";
142 reg = <0xe1020000 0x38>; 142 reg = <0xe1020000 0x38>;
143 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 143 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
@@ -145,7 +145,7 @@
145 clock-names = "sclk"; 145 clock-names = "sclk";
146 }; 146 };
147 147
148 uart@e1030000 { 148 uart1: serial@e1030000 {
149 compatible = "renesas,em-uart"; 149 compatible = "renesas,em-uart";
150 reg = <0xe1030000 0x38>; 150 reg = <0xe1030000 0x38>;
151 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 151 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
@@ -153,7 +153,7 @@
153 clock-names = "sclk"; 153 clock-names = "sclk";
154 }; 154 };
155 155
156 uart@e1040000 { 156 uart2: serial@e1040000 {
157 compatible = "renesas,em-uart"; 157 compatible = "renesas,em-uart";
158 reg = <0xe1040000 0x38>; 158 reg = <0xe1040000 0x38>;
159 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 159 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
@@ -161,7 +161,7 @@
161 clock-names = "sclk"; 161 clock-names = "sclk";
162 }; 162 };
163 163
164 uart@e1050000 { 164 uart3: serial@e1050000 {
165 compatible = "renesas,em-uart"; 165 compatible = "renesas,em-uart";
166 reg = <0xe1050000 0x38>; 166 reg = <0xe1050000 0x38>;
167 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; 167 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
index 05b44c272c9a..721b09238f58 100644
--- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
+++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
@@ -51,3 +51,36 @@
51&uart0 { 51&uart0 {
52 status = "okay"; 52 status = "okay";
53}; 53};
54
55&gmac0 {
56 #address-cells = <1>;
57 #size-cells = <0>;
58 phy-handle = <&phy2>;
59 phy-mode = "mii";
60 /* Placeholder, overwritten by bootloader */
61 mac-address = [00 00 00 00 00 00];
62 status = "okay";
63
64 phy2: ethernet-phy@2 {
65 reg = <2>;
66 };
67};
68
69&gmac1 {
70 #address-cells = <1>;
71 #size-cells = <0>;
72 phy-handle = <&phy1>;
73 phy-mode = "rgmii";
74 /* Placeholder, overwritten by bootloader */
75 mac-address = [00 00 00 00 00 00];
76 status = "okay";
77
78 phy1: ethernet-phy@1 {
79 reg = <1>;
80 };
81};
82
83&ahci {
84 phys = <&sata_phy>;
85 phy-names = "sata-phy";
86};
diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index f85ba2924ff7..c52722b14e4a 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -131,6 +131,249 @@
131 clock-names = "apb_pclk"; 131 clock-names = "apb_pclk";
132 status = "disabled"; 132 status = "disabled";
133 }; 133 };
134
135 gpio0: gpio@b20000 {
136 compatible = "arm,pl061", "arm,primecell";
137 reg = <0xb20000 0x1000>;
138 interrupts = <0 108 0x4>;
139 gpio-controller;
140 #gpio-cells = <2>;
141 clocks = <&clock HIX5HD2_FIXED_100M>;
142 clock-names = "apb_pclk";
143 interrupt-controller;
144 #interrupt-cells = <2>;
145 status = "disabled";
146 };
147
148 gpio1: gpio@b21000 {
149 compatible = "arm,pl061", "arm,primecell";
150 reg = <0xb21000 0x1000>;
151 interrupts = <0 109 0x4>;
152 gpio-controller;
153 #gpio-cells = <2>;
154 clocks = <&clock HIX5HD2_FIXED_100M>;
155 clock-names = "apb_pclk";
156 interrupt-controller;
157 #interrupt-cells = <2>;
158 status = "disabled";
159 };
160
161 gpio2: gpio@b22000 {
162 compatible = "arm,pl061", "arm,primecell";
163 reg = <0xb22000 0x1000>;
164 interrupts = <0 110 0x4>;
165 gpio-controller;
166 #gpio-cells = <2>;
167 clocks = <&clock HIX5HD2_FIXED_100M>;
168 clock-names = "apb_pclk";
169 interrupt-controller;
170 #interrupt-cells = <2>;
171 status = "disabled";
172 };
173
174 gpio3: gpio@b23000 {
175 compatible = "arm,pl061", "arm,primecell";
176 reg = <0xb23000 0x1000>;
177 interrupts = <0 111 0x4>;
178 gpio-controller;
179 #gpio-cells = <2>;
180 clocks = <&clock HIX5HD2_FIXED_100M>;
181 clock-names = "apb_pclk";
182 interrupt-controller;
183 #interrupt-cells = <2>;
184 status = "disabled";
185 };
186
187 gpio4: gpio@b24000 {
188 compatible = "arm,pl061", "arm,primecell";
189 reg = <0xb24000 0x1000>;
190 interrupts = <0 112 0x4>;
191 gpio-controller;
192 #gpio-cells = <2>;
193 clocks = <&clock HIX5HD2_FIXED_100M>;
194 clock-names = "apb_pclk";
195 interrupt-controller;
196 #interrupt-cells = <2>;
197 status = "disabled";
198 };
199
200 gpio5: gpio@004000 {
201 compatible = "arm,pl061", "arm,primecell";
202 reg = <0x004000 0x1000>;
203 interrupts = <0 113 0x4>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 clocks = <&clock HIX5HD2_FIXED_100M>;
207 clock-names = "apb_pclk";
208 interrupt-controller;
209 #interrupt-cells = <2>;
210 status = "disabled";
211 };
212
213 gpio6: gpio@b26000 {
214 compatible = "arm,pl061", "arm,primecell";
215 reg = <0xb26000 0x1000>;
216 interrupts = <0 114 0x4>;
217 gpio-controller;
218 #gpio-cells = <2>;
219 clocks = <&clock HIX5HD2_FIXED_100M>;
220 clock-names = "apb_pclk";
221 interrupt-controller;
222 #interrupt-cells = <2>;
223 status = "disabled";
224 };
225
226 gpio7: gpio@b27000 {
227 compatible = "arm,pl061", "arm,primecell";
228 reg = <0xb27000 0x1000>;
229 interrupts = <0 115 0x4>;
230 gpio-controller;
231 #gpio-cells = <2>;
232 clocks = <&clock HIX5HD2_FIXED_100M>;
233 clock-names = "apb_pclk";
234 interrupt-controller;
235 #interrupt-cells = <2>;
236 status = "disabled";
237 };
238
239 gpio8: gpio@b28000 {
240 compatible = "arm,pl061", "arm,primecell";
241 reg = <0xb28000 0x1000>;
242 interrupts = <0 116 0x4>;
243 gpio-controller;
244 #gpio-cells = <2>;
245 clocks = <&clock HIX5HD2_FIXED_100M>;
246 clock-names = "apb_pclk";
247 interrupt-controller;
248 #interrupt-cells = <2>;
249 status = "disabled";
250 };
251
252 gpio9: gpio@b29000 {
253 compatible = "arm,pl061", "arm,primecell";
254 reg = <0xb29000 0x1000>;
255 interrupts = <0 117 0x4>;
256 gpio-controller;
257 #gpio-cells = <2>;
258 clocks = <&clock HIX5HD2_FIXED_100M>;
259 clock-names = "apb_pclk";
260 interrupt-controller;
261 #interrupt-cells = <2>;
262 status = "disabled";
263 };
264
265 gpio10: gpio@b2a000 {
266 compatible = "arm,pl061", "arm,primecell";
267 reg = <0xb2a000 0x1000>;
268 interrupts = <0 118 0x4>;
269 gpio-controller;
270 #gpio-cells = <2>;
271 clocks = <&clock HIX5HD2_FIXED_100M>;
272 clock-names = "apb_pclk";
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 status = "disabled";
276 };
277
278 gpio11: gpio@b2b000 {
279 compatible = "arm,pl061", "arm,primecell";
280 reg = <0xb2b000 0x1000>;
281 interrupts = <0 119 0x4>;
282 gpio-controller;
283 #gpio-cells = <2>;
284 clocks = <&clock HIX5HD2_FIXED_100M>;
285 clock-names = "apb_pclk";
286 interrupt-controller;
287 #interrupt-cells = <2>;
288 status = "disabled";
289 };
290
291 gpio12: gpio@b2c000 {
292 compatible = "arm,pl061", "arm,primecell";
293 reg = <0xb2c000 0x1000>;
294 interrupts = <0 120 0x4>;
295 gpio-controller;
296 #gpio-cells = <2>;
297 clocks = <&clock HIX5HD2_FIXED_100M>;
298 clock-names = "apb_pclk";
299 interrupt-controller;
300 #interrupt-cells = <2>;
301 status = "disabled";
302 };
303
304 gpio13: gpio@b2d000 {
305 compatible = "arm,pl061", "arm,primecell";
306 reg = <0xb2d000 0x1000>;
307 interrupts = <0 121 0x4>;
308 gpio-controller;
309 #gpio-cells = <2>;
310 clocks = <&clock HIX5HD2_FIXED_100M>;
311 clock-names = "apb_pclk";
312 interrupt-controller;
313 #interrupt-cells = <2>;
314 status = "disabled";
315 };
316
317 gpio14: gpio@b2e000 {
318 compatible = "arm,pl061", "arm,primecell";
319 reg = <0xb2e000 0x1000>;
320 interrupts = <0 122 0x4>;
321 gpio-controller;
322 #gpio-cells = <2>;
323 clocks = <&clock HIX5HD2_FIXED_100M>;
324 clock-names = "apb_pclk";
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 status = "disabled";
328 };
329
330 gpio15: gpio@b2f000 {
331 compatible = "arm,pl061", "arm,primecell";
332 reg = <0xb2f000 0x1000>;
333 interrupts = <0 123 0x4>;
334 gpio-controller;
335 #gpio-cells = <2>;
336 clocks = <&clock HIX5HD2_FIXED_100M>;
337 clock-names = "apb_pclk";
338 interrupt-controller;
339 #interrupt-cells = <2>;
340 status = "disabled";
341 };
342
343 gpio16: gpio@b30000 {
344 compatible = "arm,pl061", "arm,primecell";
345 reg = <0xb30000 0x1000>;
346 interrupts = <0 124 0x4>;
347 gpio-controller;
348 #gpio-cells = <2>;
349 clocks = <&clock HIX5HD2_FIXED_100M>;
350 clock-names = "apb_pclk";
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 status = "disabled";
354 };
355
356 gpio17: gpio@b31000 {
357 compatible = "arm,pl061", "arm,primecell";
358 reg = <0xb31000 0x1000>;
359 interrupts = <0 125 0x4>;
360 gpio-controller;
361 #gpio-cells = <2>;
362 clocks = <&clock HIX5HD2_FIXED_100M>;
363 clock-names = "apb_pclk";
364 interrupt-controller;
365 #interrupt-cells = <2>;
366 status = "disabled";
367 };
368
369 wdt0: watchdog@a2c000 {
370 compatible = "arm,sp805", "arm,primecell";
371 arm,primecell-periphid = <0x00141805>;
372 reg = <0xa2c000 0x1000>;
373 interrupts = <0 29 4>;
374 clocks = <&clock HIX5HD2_WDG0_RST>;
375 clock-names = "apb_pclk";
376 };
134 }; 377 };
135 378
136 local_timer@00a00600 { 379 local_timer@00a00600 {
@@ -148,9 +391,15 @@
148 }; 391 };
149 392
150 sysctrl: system-controller@00000000 { 393 sysctrl: system-controller@00000000 {
151 compatible = "hisilicon,sysctrl"; 394 compatible = "hisilicon,sysctrl", "syscon";
152 reg = <0x00000000 0x1000>; 395 reg = <0x00000000 0x1000>;
153 reboot-offset = <0x4>; 396 };
397
398 reboot {
399 compatible = "syscon-reboot";
400 regmap = <&sysctrl>;
401 offset = <0x4>;
402 mask = <0xdeadbeef>;
154 }; 403 };
155 404
156 cpuctrl@00a22000 { 405 cpuctrl@00a22000 {
@@ -166,5 +415,142 @@
166 #clock-cells = <1>; 415 #clock-cells = <1>;
167 }; 416 };
168 }; 417 };
418
419 /* unremovable emmc as mmcblk0 */
420 mmc: mmc@1830000 {
421 compatible = "snps,dw-mshc";
422 reg = <0x1830000 0x1000>;
423 interrupts = <0 35 4>;
424 clocks = <&clock HIX5HD2_MMC_CIU_RST>,
425 <&clock HIX5HD2_MMC_BIU_CLK>;
426 clock-names = "ciu", "biu";
427 };
428
429 sd: mmc@1820000 {
430 compatible = "snps,dw-mshc";
431 reg = <0x1820000 0x1000>;
432 interrupts = <0 34 4>;
433 clocks = <&clock HIX5HD2_SD_CIU_RST>,
434 <&clock HIX5HD2_SD_BIU_CLK>;
435 clock-names = "ciu","biu";
436 };
437
438 gmac0: ethernet@1840000 {
439 compatible = "hisilicon,hix5hd2-gmac";
440 reg = <0x1840000 0x1000>,<0x184300c 0x4>;
441 interrupts = <0 71 4>;
442 clocks = <&clock HIX5HD2_MAC0_CLK>;
443 status = "disabled";
444 };
445
446 gmac1: ethernet@1841000 {
447 compatible = "hisilicon,hix5hd2-gmac";
448 reg = <0x1841000 0x1000>,<0x1843010 0x4>;
449 interrupts = <0 72 4>;
450 clocks = <&clock HIX5HD2_MAC1_CLK>;
451 status = "disabled";
452 };
453
454 usb0: ehci@1890000 {
455 compatible = "generic-ehci";
456 reg = <0x1890000 0x1000>;
457 interrupts = <0 66 4>;
458 clocks = <&clock HIX5HD2_USB_CLK>;
459 };
460
461 usb1: ohci@1880000 {
462 compatible = "generic-ohci";
463 reg = <0x1880000 0x1000>;
464 interrupts = <0 67 4>;
465 clocks = <&clock HIX5HD2_USB_CLK>;
466 };
467
468 peripheral_ctrl: syscon@a20000 {
469 compatible = "syscon";
470 reg = <0xa20000 0x1000>;
471 };
472
473 sata_phy: phy@1900000 {
474 compatible = "hisilicon,hix5hd2-sata-phy";
475 reg = <0x1900000 0x10000>;
476 #phy-cells = <0>;
477 hisilicon,peripheral-syscon = <&peripheral_ctrl>;
478 hisilicon,power-reg = <0x8 10>;
479 };
480
481 ahci: sata@1900000 {
482 compatible = "hisilicon,hisi-ahci";
483 reg = <0x1900000 0x10000>;
484 interrupts = <0 70 4>;
485 clocks = <&clock HIX5HD2_SATA_CLK>;
486 };
487
488 ir: ir@001000 {
489 compatible = "hisilicon,hix5hd2-ir";
490 reg = <0x001000 0x1000>;
491 interrupts = <0 47 4>;
492 clocks = <&clock HIX5HD2_FIXED_24M>;
493 hisilicon,power-syscon = <&sysctrl>;
494 };
495
496 i2c0: i2c@b10000 {
497 compatible = "hisilicon,hix5hd2-i2c";
498 reg = <0xb10000 0x1000>;
499 interrupts = <0 38 4>;
500 clocks = <&clock HIX5HD2_I2C0_RST>;
501 #address-cells = <1>;
502 #size-cells = <0>;
503 status = "disabled";
504 };
505
506 i2c1: i2c@b11000 {
507 compatible = "hisilicon,hix5hd2-i2c";
508 reg = <0xb11000 0x1000>;
509 interrupts = <0 39 4>;
510 clocks = <&clock HIX5HD2_I2C1_RST>;
511 #address-cells = <1>;
512 #size-cells = <0>;
513 status = "disabled";
514 };
515
516 i2c2: i2c@b12000 {
517 compatible = "hisilicon,hix5hd2-i2c";
518 reg = <0xb12000 0x1000>;
519 interrupts = <0 40 4>;
520 clocks = <&clock HIX5HD2_I2C2_RST>;
521 #address-cells = <1>;
522 #size-cells = <0>;
523 status = "disabled";
524 };
525
526 i2c3: i2c@b13000 {
527 compatible = "hisilicon,hix5hd2-i2c";
528 reg = <0xb13000 0x1000>;
529 interrupts = <0 41 4>;
530 clocks = <&clock HIX5HD2_I2C3_RST>;
531 #address-cells = <1>;
532 #size-cells = <0>;
533 status = "disabled";
534 };
535
536 i2c4: i2c@b16000 {
537 compatible = "hisilicon,hix5hd2-i2c";
538 reg = <0xb16000 0x1000>;
539 interrupts = <0 43 4>;
540 clocks = <&clock HIX5HD2_I2C4_RST>;
541 #address-cells = <1>;
542 #size-cells = <0>;
543 status = "disabled";
544 };
545
546 i2c5: i2c@b17000 {
547 compatible = "hisilicon,hix5hd2-i2c";
548 reg = <0xb17000 0x1000>;
549 interrupts = <0 44 4>;
550 clocks = <&clock HIX5HD2_I2C5_RST>;
551 #address-cells = <1>;
552 #size-cells = <0>;
553 status = "disabled";
554 };
169 }; 555 };
170}; 556};
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 09664fcf5afb..0e13b4b10a92 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -193,7 +193,6 @@
193 i2c0: i2c@80058000 { 193 i2c0: i2c@80058000 {
194 pinctrl-names = "default"; 194 pinctrl-names = "default";
195 pinctrl-0 = <&i2c0_pins_a>; 195 pinctrl-0 = <&i2c0_pins_a>;
196 clock-frequency = <400000>;
197 status = "okay"; 196 status = "okay";
198 197
199 sgtl5000: codec@0a { 198 sgtl5000: codec@0a {
diff --git a/arch/arm/boot/dts/k2e-evm.dts b/arch/arm/boot/dts/k2e-evm.dts
index c568f067604d..560d62150ade 100644
--- a/arch/arm/boot/dts/k2e-evm.dts
+++ b/arch/arm/boot/dts/k2e-evm.dts
@@ -139,3 +139,15 @@
139 }; 139 };
140 }; 140 };
141}; 141};
142
143&mdio {
144 ethphy0: ethernet-phy@0 {
145 compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
146 reg = <0>;
147 };
148
149 ethphy1: ethernet-phy@1 {
150 compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
151 reg = <1>;
152 };
153};
diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi
index c358b4b9a073..5fc14683d6df 100644
--- a/arch/arm/boot/dts/k2e.dtsi
+++ b/arch/arm/boot/dts/k2e.dtsi
@@ -85,6 +85,51 @@
85 #gpio-cells = <2>; 85 #gpio-cells = <2>;
86 gpio,syscon-dev = <&devctrl 0x240>; 86 gpio,syscon-dev = <&devctrl 0x240>;
87 }; 87 };
88
89 pcie@21020000 {
90 compatible = "ti,keystone-pcie","snps,dw-pcie";
91 clocks = <&clkpcie1>;
92 clock-names = "pcie";
93 #address-cells = <3>;
94 #size-cells = <2>;
95 reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
96 ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
97 0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
98
99 device_type = "pci";
100 num-lanes = <2>;
101
102 #interrupt-cells = <1>;
103 interrupt-map-mask = <0 0 0 7>;
104 interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */
105 <0 0 0 2 &pcie_intc1 1>, /* INT B */
106 <0 0 0 3 &pcie_intc1 2>, /* INT C */
107 <0 0 0 4 &pcie_intc1 3>; /* INT D */
108
109 pcie_msi_intc1: msi-interrupt-controller {
110 interrupt-controller;
111 #interrupt-cells = <1>;
112 interrupt-parent = <&gic>;
113 interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
114 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
115 <GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
116 <GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
117 <GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
118 <GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
119 <GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
120 <GIC_SPI 384 IRQ_TYPE_EDGE_RISING>;
121 };
122
123 pcie_intc1: legacy-interrupt-controller {
124 interrupt-controller;
125 #interrupt-cells = <1>;
126 interrupt-parent = <&gic>;
127 interrupts = <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
128 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
129 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
130 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>;
131 };
132 };
88 }; 133 };
89}; 134};
90 135
diff --git a/arch/arm/boot/dts/k2l-evm.dts b/arch/arm/boot/dts/k2l-evm.dts
index fec43128a2e0..85cc7f2872d7 100644
--- a/arch/arm/boot/dts/k2l-evm.dts
+++ b/arch/arm/boot/dts/k2l-evm.dts
@@ -116,3 +116,15 @@
116 }; 116 };
117 }; 117 };
118}; 118};
119
120&mdio {
121 ethphy0: ethernet-phy@0 {
122 compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
123 reg = <0>;
124 };
125
126 ethphy1: ethernet-phy@1 {
127 compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
128 reg = <1>;
129 };
130};
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index 5d3e83fa2242..c06542b2c954 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -285,5 +285,50 @@
285 #interrupt-cells = <1>; 285 #interrupt-cells = <1>;
286 ti,syscon-dev = <&devctrl 0x2a0>; 286 ti,syscon-dev = <&devctrl 0x2a0>;
287 }; 287 };
288
289 pcie@21800000 {
290 compatible = "ti,keystone-pcie", "snps,dw-pcie";
291 clocks = <&clkpcie>;
292 clock-names = "pcie";
293 #address-cells = <3>;
294 #size-cells = <2>;
295 reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
296 ranges = <0x81000000 0 0 0x23250000 0 0x4000
297 0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
298
299 device_type = "pci";
300 num-lanes = <2>;
301
302 #interrupt-cells = <1>;
303 interrupt-map-mask = <0 0 0 7>;
304 interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
305 <0 0 0 2 &pcie_intc0 1>, /* INT B */
306 <0 0 0 3 &pcie_intc0 2>, /* INT C */
307 <0 0 0 4 &pcie_intc0 3>; /* INT D */
308
309 pcie_msi_intc0: msi-interrupt-controller {
310 interrupt-controller;
311 #interrupt-cells = <1>;
312 interrupt-parent = <&gic>;
313 interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
314 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
315 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
316 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
317 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
318 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
319 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
320 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
321 };
322
323 pcie_intc0: legacy-interrupt-controller {
324 interrupt-controller;
325 #interrupt-cells = <1>;
326 interrupt-parent = <&gic>;
327 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
328 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
329 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
330 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
331 };
332 };
288 }; 333 };
289}; 334};
diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/kirkwood-dir665.dts
new file mode 100644
index 000000000000..786959ee9cbe
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dir665.dts
@@ -0,0 +1,278 @@
1/*
2 * Copyright (C) 2014 Claudio Leite <leitec@staticky.com>
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9/dts-v1/;
10
11#include "kirkwood.dtsi"
12#include "kirkwood-6281.dtsi"
13
14/ {
15 model = "D-Link DIR-665";
16 compatible = "dlink,dir-665", "marvell,kirkwood-88f6281", "marvell,kirkwood";
17
18 memory {
19 device_type = "memory";
20 reg = <0x00000000 0x8000000>; /* 128 MB */
21 };
22
23 chosen {
24 bootargs = "console=ttyS0,115200n8 earlyprintk";
25 stdout-path = &uart0;
26 };
27
28 mbus {
29 pcie-controller {
30 status = "okay";
31
32 pcie@1,0 {
33 status = "okay";
34 };
35 };
36 };
37
38 ocp@f1000000 {
39 pinctrl: pin-controller@10000 {
40 pinctrl-0 =< &pmx_led_usb
41 &pmx_led_internet_blue
42 &pmx_led_internet_amber
43 &pmx_led_5g &pmx_led_status_blue
44 &pmx_led_wps &pmx_led_status_amber
45 &pmx_led_24g
46 &pmx_btn_restart &pmx_btn_wps>;
47 pinctrl-names = "default";
48
49 pmx_led_usb: pmx-led-usb {
50 marvell,pins = "mpp12";
51 marvell,function = "gpio";
52 };
53 pmx_led_internet_blue: pmx-led-internet-blue {
54 marvell,pins = "mpp42";
55 marvell,function = "gpio";
56 };
57 pmx_led_internet_amber: pmx-led-internet-amber {
58 marvell,pins = "mpp43";
59 marvell,function = "gpio";
60 };
61 pmx_led_5g: pmx-led-5g {
62 marvell,pins = "mpp44";
63 marvell,function = "gpio";
64 };
65 pmx_led_status_blue: pmx-led-status-blue {
66 marvell,pins = "mpp45";
67 marvell,function = "gpio";
68 };
69 pmx_led_wps: pmx-led-wps {
70 marvell,pins = "mpp47";
71 marvell,function = "gpio";
72 };
73 pmx_led_status_amber: pmx-led-status-amber {
74 marvell,pins = "mpp48";
75 marvell,function = "gpio";
76 };
77 pmx_led_24g: pmx-led-24g {
78 marvell,pins = "mpp49";
79 marvell,function = "gpio";
80 };
81 pmx_btn_restart: pmx-btn-restart {
82 marvell,pins = "mpp28";
83 marvell,function = "gpio";
84 };
85 pmx_btn_wps: pmx-btn-wps {
86 marvell,pins = "mpp46";
87 marvell,function = "gpio";
88 };
89 };
90
91 spi@10600 {
92 status = "okay";
93 m25p80@0 {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 compatible = "mxicy,mx25l12805d";
97 spi-max-frequency = <50000000>;
98 reg = <0>;
99
100 partition@0 {
101 label = "uboot";
102 reg = <0x0 0x30000>;
103 read-only;
104 };
105
106 partition@30000 {
107 label = "nvram";
108 reg = <0x30000 0x10000>;
109 read-only;
110 };
111
112 partition@40000 {
113 label = "kernel";
114 reg = <0x40000 0x180000>;
115 };
116
117 partition@1c0000 {
118 label = "rootfs";
119 reg = <0x1c0000 0xe00000>;
120 };
121
122 cal_data: partition@fc0000 {
123 label = "cal_data";
124 reg = <0xfc0000 0x10000>;
125 read-only;
126 };
127
128 partition@fd0000 {
129 label = "lang_pack";
130 reg = <0xfd0000 0x30000>;
131 read-only;
132 };
133 };
134 };
135
136 serial@12000 {
137 status = "okay";
138 };
139
140 i2c@11000 {
141 status = "okay";
142 };
143
144 ehci@50000 {
145 status = "okay";
146 };
147 };
148
149 gpio-leds {
150 compatible = "gpio-leds";
151
152 blue-usb {
153 label = "dir665:blue:usb";
154 gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
155 };
156 blue-internet {
157 /* Can only be turned on if the Internet
158 * Ethernet port has Link
159 */
160 label = "dir665:blue:internet";
161 gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
162 };
163 amber-internet {
164 label = "dir665:amber:internet";
165 gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
166 };
167 blue-wifi5g {
168 label = "dir665:blue:5g";
169 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
170 };
171 blue-status {
172 label = "dir665:blue:status";
173 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
174 };
175 blue-wps {
176 label = "dir665:blue:wps";
177 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
178 };
179 amber-status {
180 label = "dir665:amber:status";
181 gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
182 };
183 blue-24g {
184 label = "dir665:blue:24g";
185 gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
186 };
187 };
188
189 gpio-keys {
190 compatible = "gpio-keys";
191 #address-cells = <1>;
192 #size-cells = <0>;
193
194 reset {
195 label = "reset";
196 linux,code = <KEY_RESTART>;
197 gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
198 };
199 wps {
200 label = "wps";
201 linux,code = <KEY_WPS_BUTTON>;
202 gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
203 };
204 };
205
206 dsa@0 {
207 compatible = "marvell,dsa";
208 #address-cells = <2>;
209 #size-cells = <0>;
210
211 dsa,ethernet = <&eth0port>;
212 dsa,mii-bus = <&mdio>;
213
214 switch@0 {
215 #address-cells = <1>;
216 #size-cells = <0>;
217 reg = <0 0>; /* MDIO address 0, switch 0 in tree */
218
219 port@0 {
220 reg = <0>;
221 label = "lan4";
222 };
223
224 port@1 {
225 reg = <1>;
226 label = "lan3";
227 };
228
229 port@2 {
230 reg = <2>;
231 label = "lan2";
232 };
233
234 port@3 {
235 reg = <3>;
236 label = "lan1";
237 };
238
239 port@4 {
240 reg = <4>;
241 label = "wan";
242 };
243
244 port@6 {
245 reg = <6>;
246 label = "cpu";
247 };
248 };
249 };
250};
251
252&mdio {
253 status = "okay";
254};
255
256/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set
257 * fixed speed and duplex. */
258&eth0 {
259 status = "okay";
260
261 ethernet0-port@0 {
262 speed = <1000>;
263 duplex = <1>;
264 };
265};
266
267/* eth1 is connected to the switch as well. However DSA only supports a
268 * single CPU port. So leave this port disabled to avoid confusion. */
269
270&eth1 {
271 status = "disabled";
272};
273
274/* There is no battery on the boards, so the RTC does not keep time
275 * when there is no power, making it useless. */
276&rtc {
277 status = "disabled";
278};
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index e6539ea5a711..03bcff87bd27 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -50,6 +50,13 @@
50/ { 50/ {
51 interrupt-parent = <&gic>; 51 interrupt-parent = <&gic>;
52 52
53 L2: l2-cache-controller@c4200000 {
54 compatible = "arm,pl310-cache";
55 reg = <0xc4200000 0x1000>;
56 cache-unified;
57 cache-level = <2>;
58 };
59
53 gic: interrupt-controller@c4301000 { 60 gic: interrupt-controller@c4301000 {
54 compatible = "arm,cortex-a9-gic"; 61 compatible = "arm,cortex-a9-gic";
55 reg = <0xc4301000 0x1000>, 62 reg = <0xc4301000 0x1000>,
@@ -106,5 +113,35 @@
106 clocks = <&clk81>; 113 clocks = <&clk81>;
107 status = "disabled"; 114 status = "disabled";
108 }; 115 };
116
117 i2c_AO: i2c@c8100500 {
118 compatible = "amlogic,meson6-i2c";
119 reg = <0xc8100500 0x20>;
120 interrupts = <0 92 1>;
121 clocks = <&clk81>;
122 #address-cells = <1>;
123 #size-cells = <0>;
124 status = "disabled";
125 };
126
127 i2c_A: i2c@c1108500 {
128 compatible = "amlogic,meson6-i2c";
129 reg = <0xc1108500 0x20>;
130 interrupts = <0 21 1>;
131 clocks = <&clk81>;
132 #address-cells = <1>;
133 #size-cells = <0>;
134 status = "disabled";
135 };
136
137 i2c_B: i2c@c11087c0 {
138 compatible = "amlogic,meson6-i2c";
139 reg = <0xc11087c0 0x20>;
140 interrupts = <0 128 1>;
141 clocks = <&clk81>;
142 #address-cells = <1>;
143 #size-cells = <0>;
144 status = "disabled";
145 };
109 }; 146 };
110}; /* end of / */ 147}; /* end of / */
diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts
index dc2541faf1ec..d7d351a68944 100644
--- a/arch/arm/boot/dts/meson6-atv1200.dts
+++ b/arch/arm/boot/dts/meson6-atv1200.dts
@@ -50,7 +50,7 @@
50 50
51/ { 51/ {
52 model = "Geniatech ATV1200"; 52 model = "Geniatech ATV1200";
53 compatible = "geniatech,atv1200"; 53 compatible = "geniatech,atv1200", "amlogic,meson6";
54 54
55 aliases { 55 aliases {
56 serial0 = &uart_AO; 56 serial0 = &uart_AO;
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
index 4ba49127779f..8b33be15af94 100644
--- a/arch/arm/boot/dts/meson6.dtsi
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -60,12 +60,14 @@
60 cpu@200 { 60 cpu@200 {
61 device_type = "cpu"; 61 device_type = "cpu";
62 compatible = "arm,cortex-a9"; 62 compatible = "arm,cortex-a9";
63 next-level-cache = <&L2>;
63 reg = <0x200>; 64 reg = <0x200>;
64 }; 65 };
65 66
66 cpu@201 { 67 cpu@201 {
67 device_type = "cpu"; 68 device_type = "cpu";
68 compatible = "arm,cortex-a9"; 69 compatible = "arm,cortex-a9";
70 next-level-cache = <&L2>;
69 reg = <0x201>; 71 reg = <0x201>;
70 }; 72 };
71 }; 73 };
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
new file mode 100644
index 000000000000..1f442a7fe03b
--- /dev/null
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -0,0 +1,92 @@
1/*
2 * Copyright 2014 Carlo Caione <carlo@caione.org>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46/include/ "meson.dtsi"
47
48/ {
49 model = "Amlogic Meson8 SoC";
50 compatible = "amlogic,meson8";
51
52 interrupt-parent = <&gic>;
53
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 cpu@200 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a9";
61 next-level-cache = <&L2>;
62 reg = <0x200>;
63 };
64
65 cpu@201 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a9";
68 next-level-cache = <&L2>;
69 reg = <0x201>;
70 };
71
72 cpu@202 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a9";
75 next-level-cache = <&L2>;
76 reg = <0x202>;
77 };
78
79 cpu@203 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a9";
82 next-level-cache = <&L2>;
83 reg = <0x203>;
84 };
85 };
86
87 clk81: clk@0 {
88 #clock-cells = <0>;
89 compatible = "fixed-clock";
90 clock-frequency = <141666666>;
91 };
92}; /* end of / */
diff --git a/arch/arm/boot/dts/mt6592-evb.dts b/arch/arm/boot/dts/mt6592-evb.dts
new file mode 100644
index 000000000000..b57237e6394a
--- /dev/null
+++ b/arch/arm/boot/dts/mt6592-evb.dts
@@ -0,0 +1,26 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Howard Chen <ibanezchen@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15/dts-v1/;
16#include "mt6592.dtsi"
17
18/ {
19 model = "mt6592 evb";
20 compatible = "mediatek,mt6592-evb", "mediatek,mt6592";
21
22 memory {
23 reg = <0x80000000 0x40000000>;
24 };
25};
26
diff --git a/arch/arm/boot/dts/mt6592.dtsi b/arch/arm/boot/dts/mt6592.dtsi
new file mode 100644
index 000000000000..31e5a0979d78
--- /dev/null
+++ b/arch/arm/boot/dts/mt6592.dtsi
@@ -0,0 +1,98 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Howard Chen <ibanezchen@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include "skeleton.dtsi"
18
19/ {
20 compatible = "mediatek,mt6592";
21 interrupt-parent = <&gic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu@0 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a7";
30 reg = <0x0>;
31 };
32 cpu@1 {
33 device_type = "cpu";
34 compatible = "arm,cortex-a7";
35 reg = <0x1>;
36 };
37 cpu@2 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a7";
40 reg = <0x2>;
41 };
42 cpu@3 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a7";
45 reg = <0x3>;
46 };
47 cpu@4 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a7";
50 reg = <0x4>;
51 };
52 cpu@5 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a7";
55 reg = <0x5>;
56 };
57 cpu@6 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a7";
60 reg = <0x6>;
61 };
62 cpu@7 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a7";
65 reg = <0x7>;
66 };
67 };
68
69 system_clk: dummy13m {
70 compatible = "fixed-clock";
71 clock-frequency = <13000000>;
72 #clock-cells = <0>;
73 };
74
75 rtc_clk: dummy32k {
76 compatible = "fixed-clock";
77 clock-frequency = <32000>;
78 #clock-cells = <0>;
79 };
80
81 timer: timer@10008000 {
82 compatible = "mediatek,mt6577-timer";
83 reg = <0x10008000 0x80>;
84 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&system_clk>, <&rtc_clk>;
86 clock-names = "system-clk", "rtc-clk";
87 };
88
89 gic: interrupt-controller@10211000 {
90 compatible = "arm,cortex-a7-gic";
91 interrupt-controller;
92 #interrupt-cells = <3>;
93 reg = <0x10211000 0x1000>,
94 <0x10212000 0x1000>;
95 };
96
97};
98
diff --git a/arch/arm/boot/dts/mt8127-moose.dts b/arch/arm/boot/dts/mt8127-moose.dts
new file mode 100644
index 000000000000..13cba0e77e08
--- /dev/null
+++ b/arch/arm/boot/dts/mt8127-moose.dts
@@ -0,0 +1,25 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Joe.C <yingjoe.chen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15/dts-v1/;
16#include "mt8127.dtsi"
17
18/ {
19 model = "MediaTek MT8127 Moose Board";
20 compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
21
22 memory {
23 reg = <0 0x80000000 0 0x40000000>;
24 };
25};
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
new file mode 100644
index 000000000000..b24c0a2f3c44
--- /dev/null
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -0,0 +1,94 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Joe.C <yingjoe.chen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include "skeleton64.dtsi"
18
19/ {
20 compatible = "mediatek,mt8127";
21 interrupt-parent = <&gic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu@0 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a7";
30 reg = <0x0>;
31 };
32 cpu@1 {
33 device_type = "cpu";
34 compatible = "arm,cortex-a7";
35 reg = <0x1>;
36 };
37 cpu@2 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a7";
40 reg = <0x2>;
41 };
42 cpu@3 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a7";
45 reg = <0x3>;
46 };
47
48 };
49
50 clocks {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 ranges;
55
56 system_clk: dummy13m {
57 compatible = "fixed-clock";
58 clock-frequency = <13000000>;
59 #clock-cells = <0>;
60 };
61
62 rtc_clk: dummy32k {
63 compatible = "fixed-clock";
64 clock-frequency = <32000>;
65 #clock-cells = <0>;
66 };
67 };
68
69 soc {
70 #address-cells = <2>;
71 #size-cells = <2>;
72 compatible = "simple-bus";
73 ranges;
74
75 timer: timer@10008000 {
76 compatible = "mediatek,mt8127-timer",
77 "mediatek,mt6577-timer";
78 reg = <0 0x10008000 0 0x80>;
79 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
80 clocks = <&system_clk>, <&rtc_clk>;
81 clock-names = "system-clk", "rtc-clk";
82 };
83
84 gic: interrupt-controller@10211000 {
85 compatible = "arm,cortex-a7-gic";
86 interrupt-controller;
87 #interrupt-cells = <3>;
88 reg = <0 0x10211000 0 0x1000>,
89 <0 0x10212000 0 0x1000>,
90 <0 0x10214000 0 0x2000>,
91 <0 0x10216000 0 0x2000>;
92 };
93 };
94};
diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts b/arch/arm/boot/dts/mt8135-evbp1.dts
new file mode 100644
index 000000000000..a5adf9742308
--- /dev/null
+++ b/arch/arm/boot/dts/mt8135-evbp1.dts
@@ -0,0 +1,25 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Joe.C <yingjoe.chen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15/dts-v1/;
16#include "mt8135.dtsi"
17
18/ {
19 model = "MediaTek MT8135 evaluation board";
20 compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135";
21
22 memory {
23 reg = <0 0x80000000 0 0x40000000>;
24 };
25};
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
new file mode 100644
index 000000000000..7d56a986358e
--- /dev/null
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -0,0 +1,116 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Joe.C <yingjoe.chen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include "skeleton64.dtsi"
18
19/ {
20 compatible = "mediatek,mt8135";
21 interrupt-parent = <&gic>;
22
23 cpu-map {
24 cluster0 {
25 core0 {
26 cpu = <&cpu0>;
27 };
28 core1 {
29 cpu = <&cpu1>;
30 };
31 };
32
33 cluster1 {
34 core0 {
35 cpu = <&cpu2>;
36 };
37 core1 {
38 cpu = <&cpu3>;
39 };
40 };
41 };
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 cpu0: cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a7";
50 reg = <0x000>;
51 };
52
53 cpu1: cpu@1 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a7";
56 reg = <0x001>;
57 };
58
59 cpu2: cpu@100 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a15";
62 reg = <0x100>;
63 };
64
65 cpu3: cpu@101 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a15";
68 reg = <0x101>;
69 };
70 };
71
72 clocks {
73 #address-cells = <2>;
74 #size-cells = <2>;
75 compatible = "simple-bus";
76 ranges;
77
78 system_clk: dummy13m {
79 compatible = "fixed-clock";
80 clock-frequency = <13000000>;
81 #clock-cells = <0>;
82 };
83
84 rtc_clk: dummy32k {
85 compatible = "fixed-clock";
86 clock-frequency = <32000>;
87 #clock-cells = <0>;
88 };
89 };
90
91 soc {
92 #address-cells = <2>;
93 #size-cells = <2>;
94 compatible = "simple-bus";
95 ranges;
96
97 timer: timer@10008000 {
98 compatible = "mediatek,mt8135-timer",
99 "mediatek,mt6577-timer";
100 reg = <0 0x10008000 0 0x80>;
101 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
102 clocks = <&system_clk>, <&rtc_clk>;
103 clock-names = "system-clk", "rtc-clk";
104 };
105
106 gic: interrupt-controller@10211000 {
107 compatible = "arm,cortex-a15-gic";
108 interrupt-controller;
109 #interrupt-cells = <3>;
110 reg = <0 0x10211000 0 0x1000>,
111 <0 0x10212000 0 0x1000>,
112 <0 0x10214000 0 0x2000>,
113 <0 0x10216000 0 0x2000>;
114 };
115 };
116};
diff --git a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
index 521c587acaee..445fafc73254 100644
--- a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
+++ b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
@@ -23,24 +23,29 @@
23 ethernet@gpmc { 23 ethernet@gpmc {
24 compatible = "smsc,lan9221", "smsc,lan9115"; 24 compatible = "smsc,lan9221", "smsc,lan9115";
25 bank-width = <2>; 25 bank-width = <2>;
26 gpmc,mux-add-data; 26 gpmc,device-width = <1>;
27 gpmc,cs-on-ns = <1>; 27 gpmc,cycle2cycle-samecsen = <1>;
28 gpmc,cs-rd-off-ns = <180>; 28 gpmc,cycle2cycle-diffcsen = <1>;
29 gpmc,cs-wr-off-ns = <180>; 29 gpmc,cs-on-ns = <5>;
30 gpmc,adv-rd-off-ns = <18>; 30 gpmc,cs-rd-off-ns = <150>;
31 gpmc,adv-wr-off-ns = <48>; 31 gpmc,cs-wr-off-ns = <150>;
32 gpmc,oe-on-ns = <54>; 32 gpmc,adv-on-ns = <0>;
33 gpmc,oe-off-ns = <168>; 33 gpmc,adv-rd-off-ns = <15>;
34 gpmc,we-on-ns = <54>; 34 gpmc,adv-wr-off-ns = <40>;
35 gpmc,we-off-ns = <168>; 35 gpmc,oe-on-ns = <45>;
36 gpmc,rd-cycle-ns = <186>; 36 gpmc,oe-off-ns = <140>;
37 gpmc,wr-cycle-ns = <186>; 37 gpmc,we-on-ns = <45>;
38 gpmc,access-ns = <144>; 38 gpmc,we-off-ns = <140>;
39 gpmc,page-burst-access-ns = <24>; 39 gpmc,rd-cycle-ns = <155>;
40 gpmc,bus-turnaround-ns = <90>; 40 gpmc,wr-cycle-ns = <155>;
41 gpmc,cycle2cycle-delay-ns = <90>; 41 gpmc,access-ns = <120>;
42 gpmc,cycle2cycle-samecsen; 42 gpmc,page-burst-access-ns = <20>;
43 gpmc,cycle2cycle-diffcsen; 43 gpmc,bus-turnaround-ns = <75>;
44 gpmc,cycle2cycle-delay-ns = <75>;
45 gpmc,wait-monitoring-ns = <0>;
46 gpmc,clk-activation-ns = <0>;
47 gpmc,wr-data-mux-bus-ns = <0>;
48 gpmc,wr-access-ns = <0>;
44 vddvario-supply = <&vddvario>; 49 vddvario-supply = <&vddvario>;
45 vdd33a-supply = <&vdd33a>; 50 vdd33a-supply = <&vdd33a>;
46 reg-io-width = <4>; 51 reg-io-width = <4>;
diff --git a/arch/arm/boot/dts/omap-zoom-common.dtsi b/arch/arm/boot/dts/omap-zoom-common.dtsi
index 68221fab978d..46ef3e443861 100644
--- a/arch/arm/boot/dts/omap-zoom-common.dtsi
+++ b/arch/arm/boot/dts/omap-zoom-common.dtsi
@@ -5,7 +5,7 @@
5#include "omap-gpmc-smsc911x.dtsi" 5#include "omap-gpmc-smsc911x.dtsi"
6 6
7&gpmc { 7&gpmc {
8 ranges = <3 0 0x10000000 0x00000400>, 8 ranges = <3 0 0x10000000 0x1000000>, /* CS3: 16MB for UART */
9 <7 0 0x2c000000 0x01000000>; 9 <7 0 0x2c000000 0x01000000>;
10 10
11 /* 11 /*
@@ -15,7 +15,65 @@
15 */ 15 */
16 uart@3,0 { 16 uart@3,0 {
17 compatible = "ns16550a"; 17 compatible = "ns16550a";
18 reg = <3 0 0x100>; 18 reg = <3 0 8>; /* CS3, offset 0, IO size 8 */
19 bank-width = <2>;
20 reg-shift = <1>;
21 reg-io-width = <1>;
22 interrupt-parent = <&gpio4>;
23 interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */
24 clock-frequency = <1843200>;
25 current-speed = <115200>;
26 gpmc,mux-add-data = <0>;
27 gpmc,device-width = <1>;
28 gpmc,wait-pin = <1>;
29 gpmc,cycle2cycle-samecsen = <1>;
30 gpmc,cycle2cycle-diffcsen = <1>;
31 gpmc,cs-on-ns = <5>;
32 gpmc,cs-rd-off-ns = <155>;
33 gpmc,cs-wr-off-ns = <155>;
34 gpmc,adv-on-ns = <15>;
35 gpmc,adv-rd-off-ns = <40>;
36 gpmc,adv-wr-off-ns = <40>;
37 gpmc,oe-on-ns = <45>;
38 gpmc,oe-off-ns = <145>;
39 gpmc,we-on-ns = <45>;
40 gpmc,we-off-ns = <145>;
41 gpmc,rd-cycle-ns = <155>;
42 gpmc,wr-cycle-ns = <155>;
43 gpmc,access-ns = <145>;
44 gpmc,page-burst-access-ns = <20>;
45 gpmc,bus-turnaround-ns = <20>;
46 gpmc,cycle2cycle-delay-ns = <20>;
47 gpmc,wait-monitoring-ns = <0>;
48 gpmc,clk-activation-ns = <0>;
49 gpmc,wr-data-mux-bus-ns = <45>;
50 gpmc,wr-access-ns = <145>;
51 };
52 uart@3,1 {
53 compatible = "ns16550a";
54 reg = <3 0x100 8>; /* CS3, offset 0x100, IO size 8 */
55 bank-width = <2>;
56 reg-shift = <1>;
57 reg-io-width = <1>;
58 interrupt-parent = <&gpio4>;
59 interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */
60 clock-frequency = <1843200>;
61 current-speed = <115200>;
62 };
63 uart@3,2 {
64 compatible = "ns16550a";
65 reg = <3 0x200 8>; /* CS3, offset 0x200, IO size 8 */
66 bank-width = <2>;
67 reg-shift = <1>;
68 reg-io-width = <1>;
69 interrupt-parent = <&gpio4>;
70 interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */
71 clock-frequency = <1843200>;
72 current-speed = <115200>;
73 };
74 uart@3,3 {
75 compatible = "ns16550a";
76 reg = <3 0x300 8>; /* CS3, offset 0x300, IO size 8 */
19 bank-width = <2>; 77 bank-width = <2>;
20 reg-shift = <1>; 78 reg-shift = <1>;
21 reg-io-width = <1>; 79 reg-io-width = <1>;
diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
index 24c50db2a478..c9f1e93a95ae 100644
--- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
+++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
@@ -40,14 +40,14 @@
40}; 40};
41 41
42&gpmc { 42&gpmc {
43 ranges = <0 0 0x04000000 0x10000000>; 43 ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */
44 44
45 /* gpio-irq for dma: 26 */ 45 /* gpio-irq for dma: 26 */
46 46
47 onenand@0,0 { 47 onenand@0,0 {
48 #address-cells = <1>; 48 #address-cells = <1>;
49 #size-cells = <1>; 49 #size-cells = <1>;
50 reg = <0 0 0x10000000>; 50 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
51 51
52 gpmc,sync-read; 52 gpmc,sync-read;
53 gpmc,burst-length = <16>; 53 gpmc,burst-length = <16>;
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index ae89aad01595..e2b2e93d7b61 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -157,6 +157,7 @@
157 interrupts = <26>, <34>; 157 interrupts = <26>, <34>;
158 interrupt-names = "dsp", "iva"; 158 interrupt-names = "dsp", "iva";
159 ti,hwmods = "mailbox"; 159 ti,hwmods = "mailbox";
160 #mbox-cells = <1>;
160 ti,mbox-num-users = <4>; 161 ti,mbox-num-users = <4>;
161 ti,mbox-num-fifos = <6>; 162 ti,mbox-num-fifos = <6>;
162 mbox_dsp: dsp { 163 mbox_dsp: dsp {
diff --git a/arch/arm/boot/dts/omap2430-sdp.dts b/arch/arm/boot/dts/omap2430-sdp.dts
index 2c90d29b4cad..05eca2e4430f 100644
--- a/arch/arm/boot/dts/omap2430-sdp.dts
+++ b/arch/arm/boot/dts/omap2430-sdp.dts
@@ -43,7 +43,31 @@
43 interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */ 43 interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */
44 reg = <5 0x300 0xf>; 44 reg = <5 0x300 0xf>;
45 bank-width = <2>; 45 bank-width = <2>;
46 gpmc,mux-add-data; 46 gpmc,sync-clk-ps = <0>;
47 }; 47 gpmc,mux-add-data = <2>;
48 gpmc,device-width = <1>;
49 gpmc,cycle2cycle-samecsen = <1>;
50 gpmc,cycle2cycle-diffcsen = <1>;
51 gpmc,cs-on-ns = <7>;
52 gpmc,cs-rd-off-ns = <233>;
53 gpmc,cs-wr-off-ns = <233>;
54 gpmc,adv-on-ns = <22>;
55 gpmc,adv-rd-off-ns = <60>;
56 gpmc,adv-wr-off-ns = <60>;
57 gpmc,oe-on-ns = <67>;
58 gpmc,oe-off-ns = <210>;
59 gpmc,we-on-ns = <67>;
60 gpmc,we-off-ns = <210>;
61 gpmc,rd-cycle-ns = <233>;
62 gpmc,wr-cycle-ns = <233>;
63 gpmc,access-ns = <233>;
64 gpmc,page-burst-access-ns = <30>;
65 gpmc,bus-turnaround-ns = <30>;
66 gpmc,cycle2cycle-delay-ns = <30>;
67 gpmc,wait-monitoring-ns = <0>;
68 gpmc,clk-activation-ns = <0>;
69 gpmc,wr-data-mux-bus-ns = <0>;
70 gpmc,wr-access-ns = <0>;
71 };
48}; 72};
49 73
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index b56d71611026..0dc8de2782b1 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -247,6 +247,7 @@
247 reg = <0x48094000 0x200>; 247 reg = <0x48094000 0x200>;
248 interrupts = <26>; 248 interrupts = <26>;
249 ti,hwmods = "mailbox"; 249 ti,hwmods = "mailbox";
250 #mbox-cells = <1>;
250 ti,mbox-num-users = <4>; 251 ti,mbox-num-users = <4>;
251 ti,mbox-num-fifos = <6>; 252 ti,mbox-num-fifos = <6>;
252 mbox_dsp: dsp { 253 mbox_dsp: dsp {
diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts
index d00502f4fd9b..0ab748cf7749 100644
--- a/arch/arm/boot/dts/omap3-cm-t3517.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3517.dts
@@ -134,3 +134,14 @@
134 bus-width = <4>; 134 bus-width = <4>;
135 cap-power-off-card; 135 cap-power-off-card;
136}; 136};
137
138&dss {
139 status = "ok";
140
141 pinctrl-names = "default";
142 pinctrl-0 = <
143 &dss_dpi_pins_common
144 &dss_dpi_pins_cm_t35x
145 >;
146};
147
diff --git a/arch/arm/boot/dts/omap3-cm-t3530.dts b/arch/arm/boot/dts/omap3-cm-t3530.dts
index d1458496520e..8dd14fcf6825 100644
--- a/arch/arm/boot/dts/omap3-cm-t3530.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3530.dts
@@ -46,3 +46,14 @@
46 bus-width = <4>; 46 bus-width = <4>;
47 cap-power-off-card; 47 cap-power-off-card;
48}; 48};
49
50&dss {
51 status = "ok";
52
53 pinctrl-names = "default";
54 pinctrl-0 = <
55 &dss_dpi_pins_common
56 &dss_dpi_pins_cm_t35x
57 >;
58};
59
diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts
index b3f9a50b3bc8..46eadb21b5ef 100644
--- a/arch/arm/boot/dts/omap3-cm-t3730.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3730.dts
@@ -31,6 +31,19 @@
31 }; 31 };
32}; 32};
33 33
34&omap3_pmx_wkup {
35 dss_dpi_pins_cm_t3730: pinmux_dss_dpi_pins_cm_t3730 {
36 pinctrl-single,pins = <
37 OMAP3_WKUP_IOPAD(0x2a08, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */
38 OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */
39 OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */
40 OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */
41 OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */
42 OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */
43 >;
44 };
45};
46
34&omap3_pmx_core { 47&omap3_pmx_core {
35 48
36 mmc2_pins: pinmux_mmc2_pins { 49 mmc2_pins: pinmux_mmc2_pins {
@@ -61,3 +74,14 @@
61 bus-width = <4>; 74 bus-width = <4>;
62 cap-power-off-card; 75 cap-power-off-card;
63}; 76};
77
78&dss {
79 status = "ok";
80
81 pinctrl-names = "default";
82 pinctrl-0 = <
83 &dss_dpi_pins_common
84 &dss_dpi_pins_cm_t3730
85 >;
86};
87
diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
index c671a2299ea8..b074673703bf 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
@@ -76,6 +76,45 @@
76 OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */ 76 OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */
77 >; 77 >;
78 }; 78 };
79
80 dss_dpi_pins_common: pinmux_dss_dpi_pins_common {
81 pinctrl-single,pins = <
82 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
83 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
84 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
85 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
86
87 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
88 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
89 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
90 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
91 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
92 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
93 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
94 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
95 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
96 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
97 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
98 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
99 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
100 OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
101 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
102 OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
103 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
104 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
105 >;
106 };
107
108 dss_dpi_pins_cm_t35x: pinmux_dss_dpi_pins_cm_t35x {
109 pinctrl-single,pins = <
110 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
111 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
112 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
113 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
114 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
115 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
116 >;
117 };
79}; 118};
80 119
81&uart3 { 120&uart3 {
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index da402f0fdab4..169037e5ff53 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -106,10 +106,10 @@
106}; 106};
107 107
108&gpmc { 108&gpmc {
109 ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */ 109 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
110 110
111 nand@0,0 { 111 nand@0,0 {
112 reg = <0 0 0>; /* CS0, offset 0 */ 112 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
113 nand-bus-width = <16>; 113 nand-bus-width = <16>;
114 114
115 gpmc,sync-clk-ps = <0>; 115 gpmc,sync-clk-ps = <0>;
diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts
index a8bd4349c7d2..16e8ce350dda 100644
--- a/arch/arm/boot/dts/omap3-evm-37xx.dts
+++ b/arch/arm/boot/dts/omap3-evm-37xx.dts
@@ -154,13 +154,14 @@
154}; 154};
155 155
156&gpmc { 156&gpmc {
157 ranges = <0 0 0x00000000 0x20000000>, 157 ranges = <0 0 0x00000000 0x1000000>, /* CS0: 16MB for NAND */
158 <5 0 0x2c000000 0x01000000>; 158 <5 0 0x2c000000 0x01000000>;
159 159
160 nand@0,0 { 160 nand@0,0 {
161 linux,mtd-name= "hynix,h8kds0un0mer-4em"; 161 linux,mtd-name= "hynix,h8kds0un0mer-4em";
162 reg = <0 0 0>; 162 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
163 nand-bus-width = <16>; 163 nand-bus-width = <16>;
164 gpmc,device-width = <2>;
164 ti,nand-ecc-opt = "bch8"; 165 ti,nand-ecc-opt = "bch8";
165 166
166 gpmc,sync-clk-ps = <0>; 167 gpmc,sync-clk-ps = <0>;
diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi
index fd34f913ace3..655d6e920a86 100644
--- a/arch/arm/boot/dts/omap3-gta04.dtsi
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -104,67 +104,67 @@
104 104
105 uart1_pins: pinmux_uart1_pins { 105 uart1_pins: pinmux_uart1_pins {
106 pinctrl-single,pins = < 106 pinctrl-single,pins = <
107 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ 107 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
108 0x14c (PIN_OUTPUT |MUX_MODE0) /* uart1_tx.uart1_tx */ 108 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */
109 >; 109 >;
110 }; 110 };
111 111
112 uart2_pins: pinmux_uart2_pins { 112 uart2_pins: pinmux_uart2_pins {
113 pinctrl-single,pins = < 113 pinctrl-single,pins = <
114 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ 114 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
115 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ 115 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
116 >; 116 >;
117 }; 117 };
118 118
119 uart3_pins: pinmux_uart3_pins { 119 uart3_pins: pinmux_uart3_pins {
120 pinctrl-single,pins = < 120 pinctrl-single,pins = <
121 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ 121 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */
122 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ 122 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */
123 >; 123 >;
124 }; 124 };
125 125
126 mmc1_pins: pinmux_mmc1_pins { 126 mmc1_pins: pinmux_mmc1_pins {
127 pinctrl-single,pins = < 127 pinctrl-single,pins = <
128 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ 128 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
129 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ 129 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
130 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ 130 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
131 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ 131 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
132 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ 132 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
133 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ 133 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
134 >; 134 >;
135 }; 135 };
136 136
137 dss_dpi_pins: pinmux_dss_dpi_pins { 137 dss_dpi_pins: pinmux_dss_dpi_pins {
138 pinctrl-single,pins = < 138 pinctrl-single,pins = <
139 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 139 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
140 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 140 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
141 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 141 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
142 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 142 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
143 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ 143 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
144 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ 144 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
145 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ 145 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
146 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ 146 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
147 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ 147 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
148 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ 148 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
149 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ 149 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
150 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ 150 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
151 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ 151 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
152 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ 152 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
153 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ 153 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
154 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ 154 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
155 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ 155 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
156 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ 156 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
157 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ 157 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
158 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ 158 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
159 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ 159 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
160 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ 160 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
161 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ 161 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
162 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ 162 OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
163 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ 163 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
164 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ 164 OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
165 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ 165 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
166 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ 166 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
167 >; 167 >;
168 }; 168 };
169}; 169};
170 170
@@ -397,10 +397,10 @@
397}; 397};
398 398
399&gpmc { 399&gpmc {
400 ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */ 400 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
401 401
402 nand@0,0 { 402 nand@0,0 {
403 reg = <0 0 0>; /* CS0, offset 0 */ 403 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
404 nand-bus-width = <16>; 404 nand-bus-width = <16>;
405 ti,nand-ecc-opt = "bch8"; 405 ti,nand-ecc-opt = "bch8";
406 406
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index e2d163bf0619..8a63ad2286aa 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -31,18 +31,6 @@
31 regulator-always-on; 31 regulator-always-on;
32 }; 32 };
33 33
34 lbee1usjyc_vmmc: lbee1usjyc_vmmc {
35 pinctrl-names = "default";
36 pinctrl-0 = <&lbee1usjyc_pins>;
37 compatible = "regulator-fixed";
38 regulator-name = "regulator-lbee1usjyc";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
41 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 WIFI_PDN */
42 startup-delay-us = <10000>;
43 enable-active-high;
44 vin-supply = <&vdd33>;
45 };
46}; 34};
47 35
48&omap3_pmx_core { 36&omap3_pmx_core {
@@ -53,13 +41,6 @@
53 >; 41 >;
54 }; 42 };
55 43
56 uart2_pins: pinmux_uart2_pins {
57 pinctrl-single,pins = <
58 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
59 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
60 >;
61 };
62
63 uart3_pins: pinmux_uart3_pins { 44 uart3_pins: pinmux_uart3_pins {
64 pinctrl-single,pins = < 45 pinctrl-single,pins = <
65 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ 46 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */
@@ -67,15 +48,6 @@
67 >; 48 >;
68 }; 49 };
69 50
70 /* WiFi/BT combo */
71 lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
72 pinctrl-single,pins = <
73 0x136 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 */
74 0x138 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */
75 0x13a (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */
76 >;
77 };
78
79 mcbsp2_pins: pinmux_mcbsp2_pins { 51 mcbsp2_pins: pinmux_mcbsp2_pins {
80 pinctrl-single,pins = < 52 pinctrl-single,pins = <
81 0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ 53 0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
@@ -120,13 +92,6 @@
120 >; 92 >;
121 }; 93 };
122 94
123 i2c2_pins: pinmux_i2c2_pins {
124 pinctrl-single,pins = <
125 0x18e (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
126 0x190 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
127 >;
128 };
129
130 i2c3_pins: pinmux_i2c3_pins { 95 i2c3_pins: pinmux_i2c3_pins {
131 pinctrl-single,pins = < 96 pinctrl-single,pins = <
132 0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ 97 0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */
@@ -135,6 +100,55 @@
135 }; 100 };
136}; 101};
137 102
103&gpmc {
104 nand@0,0 {
105 linux,mtd-name= "micron,mt29c4g96maz";
106 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
107 nand-bus-width = <16>;
108 gpmc,device-width = <2>;
109 ti,nand-ecc-opt = "bch8";
110
111 gpmc,sync-clk-ps = <0>;
112 gpmc,cs-on-ns = <0>;
113 gpmc,cs-rd-off-ns = <44>;
114 gpmc,cs-wr-off-ns = <44>;
115 gpmc,adv-on-ns = <6>;
116 gpmc,adv-rd-off-ns = <34>;
117 gpmc,adv-wr-off-ns = <44>;
118 gpmc,we-off-ns = <40>;
119 gpmc,oe-off-ns = <54>;
120 gpmc,access-ns = <64>;
121 gpmc,rd-cycle-ns = <82>;
122 gpmc,wr-cycle-ns = <82>;
123 gpmc,wr-access-ns = <40>;
124 gpmc,wr-data-mux-bus-ns = <0>;
125
126 #address-cells = <1>;
127 #size-cells = <1>;
128
129 partition@0 {
130 label = "SPL";
131 reg = <0 0x100000>;
132 };
133 partition@80000 {
134 label = "U-Boot";
135 reg = <0x100000 0x180000>;
136 };
137 partition@1c0000 {
138 label = "Environment";
139 reg = <0x280000 0x100000>;
140 };
141 partition@280000 {
142 label = "Kernel";
143 reg = <0x380000 0x300000>;
144 };
145 partition@780000 {
146 label = "Filesystem";
147 reg = <0x680000 0x1f980000>;
148 };
149 };
150};
151
138&i2c1 { 152&i2c1 {
139 pinctrl-names = "default"; 153 pinctrl-names = "default";
140 pinctrl-0 = <&i2c1_pins>; 154 pinctrl-0 = <&i2c1_pins>;
@@ -156,12 +170,6 @@
156#include "twl4030.dtsi" 170#include "twl4030.dtsi"
157#include "twl4030_omap3.dtsi" 171#include "twl4030_omap3.dtsi"
158 172
159&i2c2 {
160 pinctrl-names = "default";
161 pinctrl-0 = <&i2c2_pins>;
162 clock-frequency = <400000>;
163};
164
165&i2c3 { 173&i2c3 {
166 pinctrl-names = "default"; 174 pinctrl-names = "default";
167 pinctrl-0 = <&i2c3_pins>; 175 pinctrl-0 = <&i2c3_pins>;
@@ -181,14 +189,6 @@
181 bus-width = <4>; 189 bus-width = <4>;
182}; 190};
183 191
184&mmc2 {
185 pinctrl-names = "default";
186 pinctrl-0 = <&mmc2_pins>;
187 vmmc-supply = <&lbee1usjyc_vmmc>;
188 bus-width = <4>;
189 non-removable;
190};
191
192&mmc3 { 192&mmc3 {
193 status = "disabled"; 193 status = "disabled";
194}; 194};
@@ -198,11 +198,6 @@
198 pinctrl-0 = <&uart1_pins>; 198 pinctrl-0 = <&uart1_pins>;
199}; 199};
200 200
201&uart2 {
202 pinctrl-names = "default";
203 pinctrl-0 = <&uart2_pins>;
204};
205
206&uart3 { 201&uart3 {
207 pinctrl-names = "default"; 202 pinctrl-names = "default";
208 pinctrl-0 = <&uart3_pins>; 203 pinctrl-0 = <&uart3_pins>;
diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/omap3-igep0020-common.dtsi
new file mode 100644
index 000000000000..e458c2185e3c
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0020-common.dtsi
@@ -0,0 +1,246 @@
1/*
2 * Common Device Tree Source for IGEPv2
3 *
4 * Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include "omap3-igep.dtsi"
13#include "omap-gpmc-smsc9221.dtsi"
14
15/ {
16
17 leds {
18 pinctrl-names = "default";
19 pinctrl-0 = <&leds_pins>;
20 compatible = "gpio-leds";
21
22 boot {
23 label = "omap3:green:boot";
24 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
25 default-state = "on";
26 };
27
28 user0 {
29 label = "omap3:red:user0";
30 gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
31 default-state = "off";
32 };
33
34 user1 {
35 label = "omap3:red:user1";
36 gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
37 default-state = "off";
38 };
39
40 user2 {
41 label = "omap3:green:user1";
42 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
43 };
44 };
45
46 /* HS USB Port 1 Power */
47 hsusb1_power: hsusb1_power_reg {
48 compatible = "regulator-fixed";
49 regulator-name = "hsusb1_vbus";
50 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <3300000>;
52 gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */
53 startup-delay-us = <70000>;
54 };
55
56 /* HS USB Host PHY on PORT 1 */
57 hsusb1_phy: hsusb1_phy {
58 compatible = "usb-nop-xceiv";
59 reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
60 vcc-supply = <&hsusb1_power>;
61 };
62
63 tfp410: encoder@0 {
64 compatible = "ti,tfp410";
65 powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
66
67 ports {
68 #address-cells = <1>;
69 #size-cells = <0>;
70
71 port@0 {
72 reg = <0>;
73
74 tfp410_in: endpoint@0 {
75 remote-endpoint = <&dpi_out>;
76 };
77 };
78
79 port@1 {
80 reg = <1>;
81
82 tfp410_out: endpoint@0 {
83 remote-endpoint = <&dvi_connector_in>;
84 };
85 };
86 };
87 };
88
89 dvi0: connector@0 {
90 compatible = "dvi-connector";
91 label = "dvi";
92
93 digital;
94
95 ddc-i2c-bus = <&i2c3>;
96
97 port {
98 dvi_connector_in: endpoint {
99 remote-endpoint = <&tfp410_out>;
100 };
101 };
102 };
103};
104
105&omap3_pmx_core {
106 pinctrl-names = "default";
107 pinctrl-0 = <
108 &tfp410_pins
109 &dss_dpi_pins
110 >;
111
112 tfp410_pins: pinmux_tfp410_pins {
113 pinctrl-single,pins = <
114 0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
115 >;
116 };
117
118 dss_dpi_pins: pinmux_dss_dpi_pins {
119 pinctrl-single,pins = <
120 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
121 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
122 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
123 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
124 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
125 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
126 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
127 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
128 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
129 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
130 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
131 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
132 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
133 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
134 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
135 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
136 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
137 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
138 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
139 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
140 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
141 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
142 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
143 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
144 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
145 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
146 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
147 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
148 >;
149 };
150
151 uart2_pins: pinmux_uart2_pins {
152 pinctrl-single,pins = <
153 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
154 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
155 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
156 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
157 >;
158 };
159};
160
161&omap3_pmx_core2 {
162 pinctrl-names = "default";
163 pinctrl-0 = <
164 &hsusbb1_pins
165 >;
166
167 hsusbb1_pins: pinmux_hsusbb1_pins {
168 pinctrl-single,pins = <
169 OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
170 OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
171 OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */
172 OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */
173 OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */
174 OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */
175 OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */
176 OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */
177 OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */
178 OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */
179 OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */
180 OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
181 >;
182 };
183
184 leds_pins: pinmux_leds_pins {
185 pinctrl-single,pins = <
186 OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
187 OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
188 OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
189 >;
190 };
191};
192
193&i2c3 {
194 clock-frequency = <100000>;
195
196 /*
197 * Display monitor features are burnt in the EEPROM
198 * as EDID data.
199 */
200 eeprom@50 {
201 compatible = "ti,eeprom";
202 reg = <0x50>;
203 };
204};
205
206&gpmc {
207 ranges = <0 0 0x00000000 0x20000000>,
208 <5 0 0x2c000000 0x01000000>;
209
210 ethernet@gpmc {
211 pinctrl-names = "default";
212 pinctrl-0 = <&smsc9221_pins>;
213 reg = <5 0 0xff>;
214 interrupt-parent = <&gpio6>;
215 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
216 };
217};
218
219&uart2 {
220 pinctrl-names = "default";
221 pinctrl-0 = <&uart2_pins>;
222};
223
224&usbhshost {
225 port1-mode = "ehci-phy";
226};
227
228&usbhsehci {
229 phys = <&hsusb1_phy>;
230};
231
232&vpll2 {
233 /* Needed for DSS */
234 regulator-name = "vdds_dsi";
235};
236
237&dss {
238 status = "ok";
239
240 port {
241 dpi_out: endpoint {
242 remote-endpoint = <&tfp410_in>;
243 data-lines = <24>;
244 };
245 };
246};
diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
new file mode 100644
index 000000000000..cc8bd0cd8cf8
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
@@ -0,0 +1,45 @@
1/*
2 * Device Tree Source for IGEPv2 Rev. F (TI OMAP AM/DM37x)
3 *
4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include "omap3-igep0020-common.dtsi"
13
14/ {
15 model = "IGEPv2 Rev. F (TI OMAP AM/DM37x)";
16 compatible = "isee,omap3-igep0020-rev-f", "ti,omap36xx", "ti,omap3";
17
18 /* Regulator to trigger the WL_EN signal of the Wifi module */
19 lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
20 compatible = "regulator-fixed";
21 regulator-name = "regulator-lbep5clwmc-wlen";
22 regulator-min-microvolt = <3300000>;
23 regulator-max-microvolt = <3300000>;
24 gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */
25 enable-active-high;
26 };
27};
28
29&omap3_pmx_core {
30 lbep5clwmc_pins: pinmux_lbep5clwmc_pins {
31 pinctrl-single,pins = <
32 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT | MUX_MODE4) /* mcspi1_cs3.gpio_177 - W_IRQ */
33 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */
34 OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */
35 >;
36 };
37};
38
39&mmc2 {
40 pinctrl-names = "default";
41 pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>;
42 vmmc-supply = <&lbep5clwmc_wlen>;
43 bus-width = <4>;
44 non-removable;
45};
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index b22caaaf774b..fea7f7edb45d 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Device Tree Source for IGEPv2 Rev. (TI OMAP AM/DM37x) 2 * Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x)
3 * 3 *
4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> 4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> 5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
@@ -9,272 +9,59 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#include "omap3-igep.dtsi" 12#include "omap3-igep0020-common.dtsi"
13#include "omap-gpmc-smsc9221.dtsi"
14 13
15/ { 14/ {
16 model = "IGEPv2 (TI OMAP AM/DM37x)"; 15 model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)";
17 compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3"; 16 compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3";
18 17
19 leds { 18 /* Regulator to trigger the WIFI_PDN signal of the Wifi module */
20 pinctrl-names = "default"; 19 lbee1usjyc_pdn: lbee1usjyc_pdn {
21 pinctrl-0 = <&leds_pins>; 20 compatible = "regulator-fixed";
22 compatible = "gpio-leds"; 21 regulator-name = "regulator-lbee1usjyc-pdn";
23 22 regulator-min-microvolt = <3300000>;
24 boot { 23 regulator-max-microvolt = <3300000>;
25 label = "omap3:green:boot"; 24 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 - WIFI_PDN */
26 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 25 startup-delay-us = <10000>;
27 default-state = "on"; 26 enable-active-high;
28 };
29
30 user0 {
31 label = "omap3:red:user0";
32 gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
33 default-state = "off";
34 };
35
36 user1 {
37 label = "omap3:red:user1";
38 gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
39 default-state = "off";
40 };
41
42 user2 {
43 label = "omap3:green:user1";
44 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
45 };
46 }; 27 };
47 28
48 /* HS USB Port 1 Power */ 29 /* Regulator to trigger the RESET_N_W signal of the Wifi module */
49 hsusb1_power: hsusb1_power_reg { 30 lbee1usjyc_reset_n_w: lbee1usjyc_reset_n_w {
50 compatible = "regulator-fixed"; 31 compatible = "regulator-fixed";
51 regulator-name = "hsusb1_vbus"; 32 regulator-name = "regulator-lbee1usjyc-reset-n-w";
52 regulator-min-microvolt = <3300000>; 33 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>; 34 regulator-max-microvolt = <3300000>;
54 gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */ 35 gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - RESET_N_W */
55 startup-delay-us = <70000>; 36 enable-active-high;
56 };
57
58 /* HS USB Host PHY on PORT 1 */
59 hsusb1_phy: hsusb1_phy {
60 compatible = "usb-nop-xceiv";
61 reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
62 vcc-supply = <&hsusb1_power>;
63 };
64
65 tfp410: encoder@0 {
66 compatible = "ti,tfp410";
67 powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
68
69 ports {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 port@0 {
74 reg = <0>;
75
76 tfp410_in: endpoint@0 {
77 remote-endpoint = <&dpi_out>;
78 };
79 };
80
81 port@1 {
82 reg = <1>;
83
84 tfp410_out: endpoint@0 {
85 remote-endpoint = <&dvi_connector_in>;
86 };
87 };
88 };
89 };
90
91 dvi0: connector@0 {
92 compatible = "dvi-connector";
93 label = "dvi";
94
95 digital;
96
97 ddc-i2c-bus = <&i2c3>;
98
99 port {
100 dvi_connector_in: endpoint {
101 remote-endpoint = <&tfp410_out>;
102 };
103 };
104 }; 37 };
105}; 38};
106 39
107&omap3_pmx_core { 40&omap3_pmx_core {
108 pinctrl-names = "default"; 41 lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
109 pinctrl-0 = <
110 &tfp410_pins
111 &dss_dpi_pins
112 >;
113
114 tfp410_pins: pinmux_tfp410_pins {
115 pinctrl-single,pins = < 42 pinctrl-single,pins = <
116 0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ 43 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */
44 OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */
45 OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */
117 >; 46 >;
118 }; 47 };
119 48
120 dss_dpi_pins: pinmux_dss_dpi_pins { 49 uart2_pins: pinmux_uart2_pins {
121 pinctrl-single,pins = < 50 pinctrl-single,pins = <
122 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 51 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
123 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 52 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
124 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 53 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
125 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 54 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
126 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
127 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
128 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
129 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
130 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
131 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
132 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
133 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
134 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
135 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
136 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
137 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
138 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
139 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
140 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
141 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
142 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
143 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
144 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
145 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
146 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
147 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
148 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
149 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
150 >; 55 >;
151 }; 56 };
152}; 57};
153 58
154&omap3_pmx_core2 { 59/* On board Wifi module */
60&mmc2 {
155 pinctrl-names = "default"; 61 pinctrl-names = "default";
156 pinctrl-0 = < 62 pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>;
157 &hsusbb1_pins 63 vmmc-supply = <&lbee1usjyc_pdn>;
158 >; 64 vmmc_aux-supply = <&lbee1usjyc_reset_n_w>;
159 65 bus-width = <4>;
160 hsusbb1_pins: pinmux_hsusbb1_pins { 66 non-removable;
161 pinctrl-single,pins = <
162 OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
163 OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
164 OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */
165 OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */
166 OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */
167 OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */
168 OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */
169 OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */
170 OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */
171 OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */
172 OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */
173 OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
174 >;
175 };
176
177 leds_pins: pinmux_leds_pins {
178 pinctrl-single,pins = <
179 OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
180 OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
181 OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
182 >;
183 };
184};
185
186&i2c3 {
187 clock-frequency = <100000>;
188
189 /*
190 * Display monitor features are burnt in the EEPROM
191 * as EDID data.
192 */
193 eeprom@50 {
194 compatible = "ti,eeprom";
195 reg = <0x50>;
196 };
197};
198
199&gpmc {
200 ranges = <0 0 0x00000000 0x20000000>,
201 <5 0 0x2c000000 0x01000000>;
202
203 nand@0,0 {
204 linux,mtd-name= "micron,mt29c4g96maz";
205 reg = <0 0 0>;
206 nand-bus-width = <16>;
207 ti,nand-ecc-opt = "bch8";
208
209 gpmc,sync-clk-ps = <0>;
210 gpmc,cs-on-ns = <0>;
211 gpmc,cs-rd-off-ns = <44>;
212 gpmc,cs-wr-off-ns = <44>;
213 gpmc,adv-on-ns = <6>;
214 gpmc,adv-rd-off-ns = <34>;
215 gpmc,adv-wr-off-ns = <44>;
216 gpmc,we-off-ns = <40>;
217 gpmc,oe-off-ns = <54>;
218 gpmc,access-ns = <64>;
219 gpmc,rd-cycle-ns = <82>;
220 gpmc,wr-cycle-ns = <82>;
221 gpmc,wr-access-ns = <40>;
222 gpmc,wr-data-mux-bus-ns = <0>;
223
224 #address-cells = <1>;
225 #size-cells = <1>;
226
227 partition@0 {
228 label = "SPL";
229 reg = <0 0x100000>;
230 };
231 partition@80000 {
232 label = "U-Boot";
233 reg = <0x100000 0x180000>;
234 };
235 partition@1c0000 {
236 label = "Environment";
237 reg = <0x280000 0x100000>;
238 };
239 partition@280000 {
240 label = "Kernel";
241 reg = <0x380000 0x300000>;
242 };
243 partition@780000 {
244 label = "Filesystem";
245 reg = <0x680000 0x1f980000>;
246 };
247 };
248
249 ethernet@gpmc {
250 pinctrl-names = "default";
251 pinctrl-0 = <&smsc9221_pins>;
252 reg = <5 0 0xff>;
253 interrupt-parent = <&gpio6>;
254 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
255 };
256};
257
258&usbhshost {
259 port1-mode = "ehci-phy";
260};
261
262&usbhsehci {
263 phys = <&hsusb1_phy>;
264};
265
266&vpll2 {
267 /* Needed for DSS */
268 regulator-name = "vdds_dsi";
269};
270
271&dss {
272 status = "ok";
273
274 port {
275 dpi_out: endpoint {
276 remote-endpoint = <&tfp410_in>;
277 data-lines = <24>;
278 };
279 };
280}; 67};
diff --git a/arch/arm/boot/dts/omap3-igep0030-common.dtsi b/arch/arm/boot/dts/omap3-igep0030-common.dtsi
new file mode 100644
index 000000000000..0cb1527c39d4
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0030-common.dtsi
@@ -0,0 +1,60 @@
1/*
2 * Common Device Tree Source for IGEP COM MODULE
3 *
4 * Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include "omap3-igep.dtsi"
13
14/ {
15 leds: gpio_leds {
16 compatible = "gpio-leds";
17
18 user0 {
19 label = "omap3:red:user0";
20 gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
21 default-state = "off";
22 };
23
24 user1 {
25 label = "omap3:green:user1";
26 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
27 default-state = "off";
28 };
29
30 user2 {
31 label = "omap3:red:user1";
32 gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* gpio_16 */
33 default-state = "off";
34 };
35 };
36};
37
38&omap3_pmx_core {
39 uart2_pins: pinmux_uart2_pins {
40 pinctrl-single,pins = <
41 OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */
42 OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */
43 OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */
44 OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */
45 >;
46 };
47};
48
49&omap3_pmx_core2 {
50 leds_core2_pins: pinmux_leds_core2_pins {
51 pinctrl-single,pins = <
52 OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
53 >;
54 };
55};
56
57&uart2 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&uart2_pins>;
60};
diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
new file mode 100644
index 000000000000..9326b282c94a
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
@@ -0,0 +1,67 @@
1/*
2 * Device Tree Source for IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)
3 *
4 * Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include "omap3-igep0030-common.dtsi"
13
14/ {
15 model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)";
16 compatible = "isee,omap3-igep0030-rev-g", "ti,omap36xx", "ti,omap3";
17
18 /* Regulator to trigger the WL_EN signal of the Wifi module */
19 lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
20 compatible = "regulator-fixed";
21 regulator-name = "regulator-lbep5clwmc-wlen";
22 regulator-min-microvolt = <3300000>;
23 regulator-max-microvolt = <3300000>;
24 gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */
25 enable-active-high;
26 };
27};
28
29&omap3_pmx_core {
30 lbep5clwmc_pins: pinmux_lbep5clwmc_pins {
31 pinctrl-single,pins = <
32 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 - W_IRQ */
33 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */
34 OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */
35 >;
36 };
37
38 leds_pins: pinmux_leds_pins {
39 pinctrl-single,pins = <
40 OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */
41 >;
42 };
43
44};
45
46&i2c2 {
47 status = "disabled";
48};
49
50&leds {
51 pinctrl-names = "default";
52 pinctrl-0 = <&leds_pins &leds_core2_pins>;
53
54 boot {
55 label = "omap3:green:boot";
56 gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
57 default-state = "on";
58 };
59};
60
61&mmc2 {
62 pinctrl-names = "default";
63 pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>;
64 vmmc-supply = <&lbep5clwmc_wlen>;
65 bus-width = <4>;
66 non-removable;
67};
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 2793749eb1ba..8150f47ccdf5 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Device Tree Source for IGEP COM MODULE (TI OMAP AM/DM37x) 2 * Device Tree Source for IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)
3 * 3 *
4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> 4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> 5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
@@ -9,97 +9,62 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#include "omap3-igep.dtsi" 12#include "omap3-igep0030-common.dtsi"
13 13
14/ { 14/ {
15 model = "IGEP COM MODULE (TI OMAP AM/DM37x)"; 15 model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)";
16 compatible = "isee,omap3-igep0030", "ti,omap36xx", "ti,omap3"; 16 compatible = "isee,omap3-igep0030", "ti,omap36xx", "ti,omap3";
17 17
18 leds { 18 /* Regulator to trigger the WIFI_PDN signal of the Wifi module */
19 pinctrl-names = "default"; 19 lbee1usjyc_pdn: lbee1usjyc_pdn {
20 pinctrl-0 = <&leds_pins>; 20 compatible = "regulator-fixed";
21 compatible = "gpio-leds"; 21 regulator-name = "regulator-lbee1usjyc-pdn";
22 22 regulator-min-microvolt = <3300000>;
23 boot { 23 regulator-max-microvolt = <3300000>;
24 label = "omap3:green:boot"; 24 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 - WIFI_PDN */
25 gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; 25 startup-delay-us = <10000>;
26 default-state = "on"; 26 enable-active-high;
27 }; 27 };
28
29 user0 {
30 label = "omap3:red:user0";
31 gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
32 default-state = "off";
33 };
34
35 user1 {
36 label = "omap3:green:user1";
37 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
38 default-state = "off";
39 };
40 28
41 user2 { 29 /* Regulator to trigger the RESET_N_W signal of the Wifi module */
42 label = "omap3:red:user1"; 30 lbee1usjyc_reset_n_w: lbee1usjyc_reset_n_w {
43 gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; 31 compatible = "regulator-fixed";
44 default-state = "off"; 32 regulator-name = "regulator-lbee1usjyc-reset-n-w";
45 }; 33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - RESET_N_W */
36 enable-active-high;
46 }; 37 };
47}; 38};
48 39
49&omap3_pmx_core2 { 40&omap3_pmx_core {
50 leds_pins: pinmux_leds_pins { 41 lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
51 pinctrl-single,pins = < 42 pinctrl-single,pins = <
52 OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ 43 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */
44 OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */
45 OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */
53 >; 46 >;
54 }; 47 };
55}; 48};
56 49
57&gpmc { 50&leds {
58 ranges = <0 0 0x00000000 0x20000000>; 51 pinctrl-names = "default";
59 52 pinctrl-0 = <&leds_core2_pins>;
60 nand@0,0 {
61 linux,mtd-name= "micron,mt29c4g96maz";
62 reg = <0 0 0>;
63 nand-bus-width = <16>;
64 ti,nand-ecc-opt = "bch8";
65 53
66 gpmc,sync-clk-ps = <0>; 54 boot {
67 gpmc,cs-on-ns = <0>; 55 label = "omap3:green:boot";
68 gpmc,cs-rd-off-ns = <44>; 56 gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; /* LEDSYNC */
69 gpmc,cs-wr-off-ns = <44>; 57 default-state = "on";
70 gpmc,adv-on-ns = <6>;
71 gpmc,adv-rd-off-ns = <34>;
72 gpmc,adv-wr-off-ns = <44>;
73 gpmc,we-off-ns = <40>;
74 gpmc,oe-off-ns = <54>;
75 gpmc,access-ns = <64>;
76 gpmc,rd-cycle-ns = <82>;
77 gpmc,wr-cycle-ns = <82>;
78 gpmc,wr-access-ns = <40>;
79 gpmc,wr-data-mux-bus-ns = <0>;
80
81 #address-cells = <1>;
82 #size-cells = <1>;
83
84 partition@0 {
85 label = "SPL";
86 reg = <0 0x100000>;
87 };
88 partition@80000 {
89 label = "U-Boot";
90 reg = <0x100000 0x180000>;
91 };
92 partition@1c0000 {
93 label = "Environment";
94 reg = <0x280000 0x100000>;
95 };
96 partition@280000 {
97 label = "Kernel";
98 reg = <0x380000 0x300000>;
99 };
100 partition@780000 {
101 label = "Filesystem";
102 reg = <0x680000 0x1f980000>;
103 };
104 }; 58 };
105}; 59};
60
61/* On board Wifi module */
62&mmc2 {
63 pinctrl-names = "default";
64 pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>;
65 vmmc-supply = <&lbee1usjyc_pdn>;
66 vmmc_aux-supply = <&lbee1usjyc_reset_n_w>;
67 bus-width = <4>;
68 non-removable;
69};
70
diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts
index 72dca0b7904d..202f95a5a383 100644
--- a/arch/arm/boot/dts/omap3-ldp.dts
+++ b/arch/arm/boot/dts/omap3-ldp.dts
@@ -101,8 +101,9 @@
101 101
102 nand@0,0 { 102 nand@0,0 {
103 linux,mtd-name= "micron,nand"; 103 linux,mtd-name= "micron,nand";
104 reg = <0 0 0>; 104 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
105 nand-bus-width = <16>; 105 nand-bus-width = <16>;
106 gpmc,device-width = <2>;
106 ti,nand-ecc-opt = "bch8"; 107 ti,nand-ecc-opt = "bch8";
107 108
108 gpmc,sync-clk-ps = <0>; 109 gpmc,sync-clk-ps = <0>;
diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
index d97308896f0c..e81fb651d5d0 100644
--- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
+++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
@@ -363,7 +363,7 @@
363 <7 0 0x15000000 0x01000000>; 363 <7 0 0x15000000 0x01000000>;
364 364
365 nand@0,0 { 365 nand@0,0 {
366 reg = <0 0 0x1000000>; 366 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
367 nand-bus-width = <16>; 367 nand-bus-width = <16>;
368 ti,nand-ecc-opt = "bch8"; 368 ti,nand-ecc-opt = "bch8";
369 /* no elm on omap3 */ 369 /* no elm on omap3 */
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 739fcf29c643..08ef71fe5273 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -142,6 +142,33 @@
142 >; 142 >;
143 }; 143 };
144 144
145 gpmc_pins: pinmux_gpmc_pins {
146 pinctrl-single,pins = <
147
148 /* address lines */
149 OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */
150 OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */
151 OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */
152
153 /* data lines, gpmc_d0..d7 not muxable according to TRM */
154 OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */
155 OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */
156 OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */
157 OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */
158 OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */
159 OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */
160 OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */
161 OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */
162
163 /*
164 * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
165 * according to TRM. OneNAND seems to require PIN_INPUT on clock.
166 */
167 OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */
168 OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
169 >;
170 };
171
145 i2c1_pins: pinmux_i2c1_pins { 172 i2c1_pins: pinmux_i2c1_pins {
146 pinctrl-single,pins = < 173 pinctrl-single,pins = <
147 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ 174 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
@@ -585,16 +612,16 @@
585}; 612};
586 613
587&gpmc { 614&gpmc {
588 ranges = <0 0 0x04000000 0x10000000>; /* 256MB */
589 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */ 615 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
590 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */ 616 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
617 pinctrl-names = "default";
618 pinctrl-0 = <&gpmc_pins>;
591 619
592 /* gpio-irq for dma: 65 */ 620 /* sys_ndmareq1 could be used by the driver, not as gpio65 though */
593
594 onenand@0,0 { 621 onenand@0,0 {
595 #address-cells = <1>; 622 #address-cells = <1>;
596 #size-cells = <1>; 623 #size-cells = <1>;
597 reg = <0 0 0x10000000>; 624 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
598 625
599 gpmc,sync-read; 626 gpmc,sync-read;
600 gpmc,sync-write; 627 gpmc,sync-write;
@@ -668,6 +695,8 @@
668 bank-width = <2>; 695 bank-width = <2>;
669 pinctrl-names = "default"; 696 pinctrl-names = "default";
670 pinctrl-0 = <&ethernet_pins>; 697 pinctrl-0 = <&ethernet_pins>;
698 power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* gpio86 */
699 reset-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio164 */
671 gpmc,device-width = <2>; 700 gpmc,device-width = <2>;
672 gpmc,sync-clk-ps = <0>; 701 gpmc,sync-clk-ps = <0>;
673 gpmc,cs-on-ns = <0>; 702 gpmc,cs-on-ns = <0>;
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index 70addcba37c5..1e49dfe7e212 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -115,12 +115,12 @@
115}; 115};
116 116
117&gpmc { 117&gpmc {
118 ranges = <0 0 0x04000000 0x20000000>; 118 ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */
119 119
120 onenand@0,0 { 120 onenand@0,0 {
121 #address-cells = <1>; 121 #address-cells = <1>;
122 #size-cells = <1>; 122 #size-cells = <1>;
123 reg = <0 0 0x20000000>; 123 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
124 124
125 gpmc,sync-read; 125 gpmc,sync-read;
126 gpmc,sync-write; 126 gpmc,sync-write;
diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi
index d59e3de1441e..b1cb5774f49a 100644
--- a/arch/arm/boot/dts/omap3-sb-t35.dtsi
+++ b/arch/arm/boot/dts/omap3-sb-t35.dtsi
@@ -2,6 +2,49 @@
2 * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730 2 * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730
3 */ 3 */
4 4
5/ {
6 tfp410: encoder@0 {
7 compatible = "ti,tfp410";
8
9 powerdown-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */
10
11 pinctrl-names = "default";
12 pinctrl-0 = <&tfp410_pins>;
13
14 ports {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 port@0 {
19 reg = <0>;
20
21 tfp410_in: endpoint@0 {
22 remote-endpoint = <&dpi_out>;
23 };
24 };
25
26 port@1 {
27 reg = <1>;
28
29 tfp410_out: endpoint@0 {
30 remote-endpoint = <&dvi_connector_in>;
31 };
32 };
33 };
34 };
35
36 dvi0: connector@0 {
37 compatible = "dvi-connector";
38 label = "dvi";
39
40 port {
41 dvi_connector_in: endpoint {
42 remote-endpoint = <&tfp410_out>;
43 };
44 };
45 };
46};
47
5&omap3_pmx_core { 48&omap3_pmx_core {
6 smsc2_pins: pinmux_smsc2_pins { 49 smsc2_pins: pinmux_smsc2_pins {
7 pinctrl-single,pins = < 50 pinctrl-single,pins = <
@@ -9,6 +52,12 @@
9 OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */ 52 OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */
10 >; 53 >;
11 }; 54 };
55
56 tfp410_pins: pinmux_tfp410_pins {
57 pinctrl-single,pins = <
58 OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
59 >;
60 };
12}; 61};
13 62
14&gpmc { 63&gpmc {
@@ -22,24 +71,29 @@
22 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 71 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
23 reg = <4 0 0xff>; 72 reg = <4 0 0xff>;
24 bank-width = <2>; 73 bank-width = <2>;
25 gpmc,mux-add-data; 74 gpmc,device-width = <1>;
26 gpmc,cs-on-ns = <1>; 75 gpmc,cycle2cycle-samecsen = <1>;
27 gpmc,cs-rd-off-ns = <180>; 76 gpmc,cycle2cycle-diffcsen = <1>;
28 gpmc,cs-wr-off-ns = <180>; 77 gpmc,cs-on-ns = <5>;
29 gpmc,adv-rd-off-ns = <18>; 78 gpmc,cs-rd-off-ns = <150>;
30 gpmc,adv-wr-off-ns = <48>; 79 gpmc,cs-wr-off-ns = <150>;
31 gpmc,oe-on-ns = <54>; 80 gpmc,adv-on-ns = <0>;
32 gpmc,oe-off-ns = <168>; 81 gpmc,adv-rd-off-ns = <15>;
33 gpmc,we-on-ns = <54>; 82 gpmc,adv-wr-off-ns = <40>;
34 gpmc,we-off-ns = <168>; 83 gpmc,oe-on-ns = <45>;
35 gpmc,rd-cycle-ns = <186>; 84 gpmc,oe-off-ns = <140>;
36 gpmc,wr-cycle-ns = <186>; 85 gpmc,we-on-ns = <45>;
37 gpmc,access-ns = <144>; 86 gpmc,we-off-ns = <140>;
38 gpmc,page-burst-access-ns = <24>; 87 gpmc,rd-cycle-ns = <155>;
39 gpmc,bus-turnaround-ns = <90>; 88 gpmc,wr-cycle-ns = <155>;
40 gpmc,cycle2cycle-delay-ns = <90>; 89 gpmc,access-ns = <120>;
41 gpmc,cycle2cycle-samecsen; 90 gpmc,page-burst-access-ns = <20>;
42 gpmc,cycle2cycle-diffcsen; 91 gpmc,bus-turnaround-ns = <75>;
92 gpmc,cycle2cycle-delay-ns = <75>;
93 gpmc,wait-monitoring-ns = <0>;
94 gpmc,clk-activation-ns = <0>;
95 gpmc,wr-data-mux-bus-ns = <0>;
96 gpmc,wr-access-ns = <0>;
43 vddvario-supply = <&vddvario>; 97 vddvario-supply = <&vddvario>;
44 vdd33a-supply = <&vdd33a>; 98 vdd33a-supply = <&vdd33a>;
45 reg-io-width = <4>; 99 reg-io-width = <4>;
diff --git a/arch/arm/boot/dts/omap3-sbc-t3517.dts b/arch/arm/boot/dts/omap3-sbc-t3517.dts
index 42189b65d393..4ec5d8684122 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3517.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3517.dts
@@ -9,6 +9,10 @@
9 model = "CompuLab SBC-T3517 with CM-T3517"; 9 model = "CompuLab SBC-T3517 with CM-T3517";
10 compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; 10 compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3";
11 11
12 aliases {
13 display0 = &dvi0;
14 };
15
12 /* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */ 16 /* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */
13 vddvario: regulator-vddvario-sb-t35 { 17 vddvario: regulator-vddvario-sb-t35 {
14 compatible = "regulator-fixed"; 18 compatible = "regulator-fixed";
@@ -54,3 +58,13 @@
54 wp-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59 */ 58 wp-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59 */
55 cd-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ 59 cd-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */
56}; 60};
61
62&dss {
63 port {
64 dpi_out: endpoint {
65 remote-endpoint = <&tfp410_in>;
66 data-lines = <24>;
67 };
68 };
69};
70
diff --git a/arch/arm/boot/dts/omap3-sbc-t3530.dts b/arch/arm/boot/dts/omap3-sbc-t3530.dts
index bbbeea6b1988..8dfc1df8cc17 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3530.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3530.dts
@@ -8,6 +8,10 @@
8/ { 8/ {
9 model = "CompuLab SBC-T3530 with CM-T3530"; 9 model = "CompuLab SBC-T3530 with CM-T3530";
10 compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3"; 10 compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3";
11
12 aliases {
13 display0 = &dvi0;
14 };
11}; 15};
12 16
13&omap3_pmx_core { 17&omap3_pmx_core {
@@ -34,3 +38,13 @@
34&mmc1 { 38&mmc1 {
35 cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>; 39 cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>;
36}; 40};
41
42&dss {
43 port {
44 dpi_out: endpoint {
45 remote-endpoint = <&tfp410_in>;
46 data-lines = <24>;
47 };
48 };
49};
50
diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts
index 08e4a7086f22..6b69864bd6ce 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3730.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3730.dts
@@ -8,6 +8,10 @@
8/ { 8/ {
9 model = "CompuLab SBC-T3730 with CM-T3730"; 9 model = "CompuLab SBC-T3730 with CM-T3730";
10 compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3"; 10 compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3";
11
12 aliases {
13 display0 = &dvi0;
14 };
11}; 15};
12 16
13&omap3_pmx_core { 17&omap3_pmx_core {
@@ -25,3 +29,13 @@
25 ranges = <5 0 0x2c000000 0x01000000>, 29 ranges = <5 0 0x2c000000 0x01000000>,
26 <4 0 0x2d000000 0x01000000>; 30 <4 0 0x2d000000 0x01000000>;
27}; 31};
32
33&dss {
34 port {
35 dpi_out: endpoint {
36 remote-endpoint = <&tfp410_in>;
37 data-lines = <24>;
38 };
39 };
40};
41
diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi
index b30f387d3a83..e89820a6776e 100644
--- a/arch/arm/boot/dts/omap3-tao3530.dtsi
+++ b/arch/arm/boot/dts/omap3-tao3530.dtsi
@@ -270,7 +270,7 @@
270 ranges = <0 0 0x00000000 0x01000000>; 270 ranges = <0 0 0x00000000 0x01000000>;
271 271
272 nand@0,0 { 272 nand@0,0 {
273 reg = <0 0 0>; /* CS0, offset 0 */ 273 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
274 nand-bus-width = <16>; 274 nand-bus-width = <16>;
275 gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ 275 gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
276 ti,nand-ecc-opt = "sw"; 276 ti,nand-ecc-opt = "sw";
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index d0e884d3a737..8db7def81c28 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -332,6 +332,7 @@
332 ti,hwmods = "mailbox"; 332 ti,hwmods = "mailbox";
333 reg = <0x48094000 0x200>; 333 reg = <0x48094000 0x200>;
334 interrupts = <26>; 334 interrupts = <26>;
335 #mbox-cells = <1>;
335 ti,mbox-num-users = <2>; 336 ti,mbox-num-users = <2>;
336 ti,mbox-num-fifos = <2>; 337 ti,mbox-num-fifos = <2>;
337 mbox_dsp: dsp { 338 mbox_dsp: dsp {
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 9bad94efe1c8..16b0cdfbee9c 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -51,8 +51,8 @@
51 51
52&gpmc { 52&gpmc {
53 ranges = <0 0 0x10000000 0x08000000>, 53 ranges = <0 0 0x10000000 0x08000000>,
54 <1 0 0x28000000 0x08000000>, 54 <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */
55 <2 0 0x20000000 0x10000000>; 55 <2 0 0x20000000 0x1000000>; /* CS2: 16MB for OneNAND */
56 56
57 nor@0,0 { 57 nor@0,0 {
58 compatible = "cfi-flash"; 58 compatible = "cfi-flash";
@@ -106,7 +106,7 @@
106 linux,mtd-name= "micron,mt29f1g08abb"; 106 linux,mtd-name= "micron,mt29f1g08abb";
107 #address-cells = <1>; 107 #address-cells = <1>;
108 #size-cells = <1>; 108 #size-cells = <1>;
109 reg = <1 0 0x08000000>; 109 reg = <1 0 4>; /* CS1, offset 0, IO size 4 */
110 ti,nand-ecc-opt = "sw"; 110 ti,nand-ecc-opt = "sw";
111 nand-bus-width = <8>; 111 nand-bus-width = <8>;
112 gpmc,cs-on-ns = <0>; 112 gpmc,cs-on-ns = <0>;
@@ -150,7 +150,7 @@
150 linux,mtd-name= "samsung,kfm2g16q2m-deb8"; 150 linux,mtd-name= "samsung,kfm2g16q2m-deb8";
151 #address-cells = <1>; 151 #address-cells = <1>;
152 #size-cells = <1>; 152 #size-cells = <1>;
153 reg = <2 0 0x10000000>; 153 reg = <2 0 0x20000>; /* CS2, offset 0, IO size 4 */
154 154
155 gpmc,device-width = <2>; 155 gpmc,device-width = <2>;
156 gpmc,mux-add-data = <2>; 156 gpmc,mux-add-data = <2>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 878c979203d0..a46eab82d2da 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -661,6 +661,7 @@
661 reg = <0x4a0f4000 0x200>; 661 reg = <0x4a0f4000 0x200>;
662 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 662 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
663 ti,hwmods = "mailbox"; 663 ti,hwmods = "mailbox";
664 #mbox-cells = <1>;
664 ti,mbox-num-users = <3>; 665 ti,mbox-num-users = <3>;
665 ti,mbox-num-fifos = <8>; 666 ti,mbox-num-fifos = <8>;
666 mbox_ipu: mbox_ipu { 667 mbox_ipu: mbox_ipu {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 256b7f69e45b..b321fdf42c9f 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -651,6 +651,7 @@
651 reg = <0x4a0f4000 0x200>; 651 reg = <0x4a0f4000 0x200>;
652 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 652 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
653 ti,hwmods = "mailbox"; 653 ti,hwmods = "mailbox";
654 #mbox-cells = <1>;
654 ti,mbox-num-users = <3>; 655 ti,mbox-num-users = <3>;
655 ti,mbox-num-fifos = <8>; 656 ti,mbox-num-fifos = <8>;
656 mbox_ipu: mbox_ipu { 657 mbox_ipu: mbox_ipu {
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index a3ed23c0a8f5..1518c5bcca33 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -21,7 +21,8 @@
21 }; 21 };
22 22
23 chosen { 23 chosen {
24 bootargs = "console=ttySC2,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; 24 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
25 stdout-path = &scif2;
25 }; 26 };
26 27
27 memory { 28 memory {
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 801a556e264b..277e73c110e5 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -52,16 +52,6 @@
52 clock-output-names = "usb_x1"; 52 clock-output-names = "usb_x1";
53 }; 53 };
54 54
55 /* Special CPG clocks */
56 cpg_clocks: cpg_clocks@fcfe0000 {
57 #clock-cells = <1>;
58 compatible = "renesas,r7s72100-cpg-clocks",
59 "renesas,rz-cpg-clocks";
60 reg = <0xfcfe0000 0x18>;
61 clocks = <&extal_clk>, <&usb_x1_clk>;
62 clock-output-names = "pll", "i", "g";
63 };
64
65 /* Fixed factor clocks */ 55 /* Fixed factor clocks */
66 b_clk: b_clk { 56 b_clk: b_clk {
67 #clock-cells = <0>; 57 #clock-cells = <0>;
@@ -88,6 +78,16 @@
88 clock-output-names = "p0"; 78 clock-output-names = "p0";
89 }; 79 };
90 80
81 /* Special CPG clocks */
82 cpg_clocks: cpg_clocks@fcfe0000 {
83 #clock-cells = <1>;
84 compatible = "renesas,r7s72100-cpg-clocks",
85 "renesas,rz-cpg-clocks";
86 reg = <0xfcfe0000 0x18>;
87 clocks = <&extal_clk>, <&usb_x1_clk>;
88 clock-output-names = "pll", "i", "g";
89 };
90
91 /* MSTP clocks */ 91 /* MSTP clocks */
92 mstp3_clks: mstp3_clks@fcfe0420 { 92 mstp3_clks: mstp3_clks@fcfe0420 {
93 #clock-cells = <1>; 93 #clock-cells = <1>;
@@ -148,97 +148,6 @@
148 }; 148 };
149 }; 149 };
150 150
151 gic: interrupt-controller@e8201000 {
152 compatible = "arm,cortex-a9-gic";
153 #interrupt-cells = <3>;
154 #address-cells = <0>;
155 interrupt-controller;
156 reg = <0xe8201000 0x1000>,
157 <0xe8202000 0x1000>;
158 };
159
160 i2c0: i2c@fcfee000 {
161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
164 reg = <0xfcfee000 0x44>;
165 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,
166 <0 158 IRQ_TYPE_EDGE_RISING>,
167 <0 159 IRQ_TYPE_EDGE_RISING>,
168 <0 160 IRQ_TYPE_LEVEL_HIGH>,
169 <0 161 IRQ_TYPE_LEVEL_HIGH>,
170 <0 162 IRQ_TYPE_LEVEL_HIGH>,
171 <0 163 IRQ_TYPE_LEVEL_HIGH>,
172 <0 164 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
174 clock-frequency = <100000>;
175 status = "disabled";
176 };
177
178 i2c1: i2c@fcfee400 {
179 #address-cells = <1>;
180 #size-cells = <0>;
181 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
182 reg = <0xfcfee400 0x44>;
183 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>,
184 <0 166 IRQ_TYPE_EDGE_RISING>,
185 <0 167 IRQ_TYPE_EDGE_RISING>,
186 <0 168 IRQ_TYPE_LEVEL_HIGH>,
187 <0 169 IRQ_TYPE_LEVEL_HIGH>,
188 <0 170 IRQ_TYPE_LEVEL_HIGH>,
189 <0 171 IRQ_TYPE_LEVEL_HIGH>,
190 <0 172 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
192 clock-frequency = <100000>;
193 status = "disabled";
194 };
195
196 i2c2: i2c@fcfee800 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
200 reg = <0xfcfee800 0x44>;
201 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>,
202 <0 174 IRQ_TYPE_EDGE_RISING>,
203 <0 175 IRQ_TYPE_EDGE_RISING>,
204 <0 176 IRQ_TYPE_LEVEL_HIGH>,
205 <0 177 IRQ_TYPE_LEVEL_HIGH>,
206 <0 178 IRQ_TYPE_LEVEL_HIGH>,
207 <0 179 IRQ_TYPE_LEVEL_HIGH>,
208 <0 180 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
210 clock-frequency = <100000>;
211 status = "disabled";
212 };
213
214 i2c3: i2c@fcfeec00 {
215 #address-cells = <1>;
216 #size-cells = <0>;
217 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
218 reg = <0xfcfeec00 0x44>;
219 interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>,
220 <0 182 IRQ_TYPE_EDGE_RISING>,
221 <0 183 IRQ_TYPE_EDGE_RISING>,
222 <0 184 IRQ_TYPE_LEVEL_HIGH>,
223 <0 185 IRQ_TYPE_LEVEL_HIGH>,
224 <0 186 IRQ_TYPE_LEVEL_HIGH>,
225 <0 187 IRQ_TYPE_LEVEL_HIGH>,
226 <0 188 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
228 clock-frequency = <100000>;
229 status = "disabled";
230 };
231
232 mtu2: timer@fcff0000 {
233 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
234 reg = <0xfcff0000 0x400>;
235 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
236 interrupt-names = "tgi0a";
237 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
238 clock-names = "fck";
239 status = "disabled";
240 };
241
242 scif0: serial@e8007000 { 151 scif0: serial@e8007000 {
243 compatible = "renesas,scif-r7s72100", "renesas,scif"; 152 compatible = "renesas,scif-r7s72100", "renesas,scif";
244 reg = <0xe8007000 64>; 153 reg = <0xe8007000 64>;
@@ -404,4 +313,95 @@
404 #size-cells = <0>; 313 #size-cells = <0>;
405 status = "disabled"; 314 status = "disabled";
406 }; 315 };
316
317 gic: interrupt-controller@e8201000 {
318 compatible = "arm,cortex-a9-gic";
319 #interrupt-cells = <3>;
320 #address-cells = <0>;
321 interrupt-controller;
322 reg = <0xe8201000 0x1000>,
323 <0xe8202000 0x1000>;
324 };
325
326 i2c0: i2c@fcfee000 {
327 #address-cells = <1>;
328 #size-cells = <0>;
329 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
330 reg = <0xfcfee000 0x44>;
331 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,
332 <0 158 IRQ_TYPE_EDGE_RISING>,
333 <0 159 IRQ_TYPE_EDGE_RISING>,
334 <0 160 IRQ_TYPE_LEVEL_HIGH>,
335 <0 161 IRQ_TYPE_LEVEL_HIGH>,
336 <0 162 IRQ_TYPE_LEVEL_HIGH>,
337 <0 163 IRQ_TYPE_LEVEL_HIGH>,
338 <0 164 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
340 clock-frequency = <100000>;
341 status = "disabled";
342 };
343
344 i2c1: i2c@fcfee400 {
345 #address-cells = <1>;
346 #size-cells = <0>;
347 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
348 reg = <0xfcfee400 0x44>;
349 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>,
350 <0 166 IRQ_TYPE_EDGE_RISING>,
351 <0 167 IRQ_TYPE_EDGE_RISING>,
352 <0 168 IRQ_TYPE_LEVEL_HIGH>,
353 <0 169 IRQ_TYPE_LEVEL_HIGH>,
354 <0 170 IRQ_TYPE_LEVEL_HIGH>,
355 <0 171 IRQ_TYPE_LEVEL_HIGH>,
356 <0 172 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
358 clock-frequency = <100000>;
359 status = "disabled";
360 };
361
362 i2c2: i2c@fcfee800 {
363 #address-cells = <1>;
364 #size-cells = <0>;
365 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
366 reg = <0xfcfee800 0x44>;
367 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>,
368 <0 174 IRQ_TYPE_EDGE_RISING>,
369 <0 175 IRQ_TYPE_EDGE_RISING>,
370 <0 176 IRQ_TYPE_LEVEL_HIGH>,
371 <0 177 IRQ_TYPE_LEVEL_HIGH>,
372 <0 178 IRQ_TYPE_LEVEL_HIGH>,
373 <0 179 IRQ_TYPE_LEVEL_HIGH>,
374 <0 180 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
376 clock-frequency = <100000>;
377 status = "disabled";
378 };
379
380 i2c3: i2c@fcfeec00 {
381 #address-cells = <1>;
382 #size-cells = <0>;
383 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
384 reg = <0xfcfeec00 0x44>;
385 interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>,
386 <0 182 IRQ_TYPE_EDGE_RISING>,
387 <0 183 IRQ_TYPE_EDGE_RISING>,
388 <0 184 IRQ_TYPE_LEVEL_HIGH>,
389 <0 185 IRQ_TYPE_LEVEL_HIGH>,
390 <0 186 IRQ_TYPE_LEVEL_HIGH>,
391 <0 187 IRQ_TYPE_LEVEL_HIGH>,
392 <0 188 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
394 clock-frequency = <100000>;
395 status = "disabled";
396 };
397
398 mtu2: timer@fcff0000 {
399 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
400 reg = <0xfcff0000 0x400>;
401 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-names = "tgi0a";
403 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
404 clock-names = "fck";
405 status = "disabled";
406 };
407}; 407};
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
index a860f32bca27..84e05f713c54 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
@@ -21,7 +21,8 @@
21 }; 21 };
22 22
23 chosen { 23 chosen {
24 bootargs = "console=ttySC0,115200 ignore_loglevel rw"; 24 bootargs = "ignore_loglevel rw";
25 stdout-path = &scifa0;
25 }; 26 };
26 27
27 memory@40000000 { 28 memory@40000000 {
@@ -93,6 +94,10 @@
93 voltage-tolerance = <1>; /* 1% */ 94 voltage-tolerance = <1>; /* 1% */
94}; 95};
95 96
97&cmt1 {
98 status = "okay";
99};
100
96&pfc { 101&pfc {
97 scifa0_pins: serial0 { 102 scifa0_pins: serial0 {
98 renesas,groups = "scifa0_data"; 103 renesas,groups = "scifa0_data";
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index ef152e384822..5ac57babc3b9 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -30,18 +30,6 @@
30 }; 30 };
31 }; 31 };
32 32
33 gic: interrupt-controller@f1001000 {
34 compatible = "arm,cortex-a15-gic";
35 #interrupt-cells = <3>;
36 #address-cells = <0>;
37 interrupt-controller;
38 reg = <0 0xf1001000 0 0x1000>,
39 <0 0xf1002000 0 0x1000>,
40 <0 0xf1004000 0 0x2000>,
41 <0 0xf1006000 0 0x2000>;
42 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
43 };
44
45 timer { 33 timer {
46 compatible = "arm,armv7-timer"; 34 compatible = "arm,armv7-timer";
47 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 35 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -50,6 +38,91 @@
50 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 38 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
51 }; 39 };
52 40
41 dmac: dma-multiplexer {
42 compatible = "renesas,shdma-mux";
43 #dma-cells = <1>;
44 dma-channels = <20>;
45 dma-requests = <256>;
46 #address-cells = <2>;
47 #size-cells = <2>;
48 ranges;
49
50 dma0: dma-controller@e6700020 {
51 compatible = "renesas,shdma-r8a73a4";
52 reg = <0 0xe6700020 0 0x89e0>;
53 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
54 0 200 IRQ_TYPE_LEVEL_HIGH
55 0 201 IRQ_TYPE_LEVEL_HIGH
56 0 202 IRQ_TYPE_LEVEL_HIGH
57 0 203 IRQ_TYPE_LEVEL_HIGH
58 0 204 IRQ_TYPE_LEVEL_HIGH
59 0 205 IRQ_TYPE_LEVEL_HIGH
60 0 206 IRQ_TYPE_LEVEL_HIGH
61 0 207 IRQ_TYPE_LEVEL_HIGH
62 0 208 IRQ_TYPE_LEVEL_HIGH
63 0 209 IRQ_TYPE_LEVEL_HIGH
64 0 210 IRQ_TYPE_LEVEL_HIGH
65 0 211 IRQ_TYPE_LEVEL_HIGH
66 0 212 IRQ_TYPE_LEVEL_HIGH
67 0 213 IRQ_TYPE_LEVEL_HIGH
68 0 214 IRQ_TYPE_LEVEL_HIGH
69 0 215 IRQ_TYPE_LEVEL_HIGH
70 0 216 IRQ_TYPE_LEVEL_HIGH
71 0 217 IRQ_TYPE_LEVEL_HIGH
72 0 218 IRQ_TYPE_LEVEL_HIGH
73 0 219 IRQ_TYPE_LEVEL_HIGH>;
74 interrupt-names = "error",
75 "ch0", "ch1", "ch2", "ch3",
76 "ch4", "ch5", "ch6", "ch7",
77 "ch8", "ch9", "ch10", "ch11",
78 "ch12", "ch13", "ch14", "ch15",
79 "ch16", "ch17", "ch18", "ch19";
80 };
81 };
82
83 pfc: pfc@e6050000 {
84 compatible = "renesas,pfc-r8a73a4";
85 reg = <0 0xe6050000 0 0x9000>;
86 gpio-controller;
87 #gpio-cells = <2>;
88 interrupts-extended =
89 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
90 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
91 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
92 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
93 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
94 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
95 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
96 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
97 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
98 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
99 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
100 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
101 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
102 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
103 <&irqc1 24 0>, <&irqc1 25 0>;
104 };
105
106 i2c5: i2c@e60b0000 {
107 #address-cells = <1>;
108 #size-cells = <0>;
109 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
110 reg = <0 0xe60b0000 0 0x428>;
111 interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>;
112
113 status = "disabled";
114 };
115
116 cmt1: timer@e6130000 {
117 compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
118 reg = <0 0xe6130000 0 0x1004>;
119 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
120
121 renesas,channels-mask = <0xff>;
122
123 status = "disabled";
124 };
125
53 irqc0: interrupt-controller@e61c0000 { 126 irqc0: interrupt-controller@e61c0000 {
54 compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; 127 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
55 #interrupt-cells = <2>; 128 #interrupt-cells = <2>;
@@ -122,48 +195,6 @@
122 <0 57 IRQ_TYPE_LEVEL_HIGH>; 195 <0 57 IRQ_TYPE_LEVEL_HIGH>;
123 }; 196 };
124 197
125 dmac: dma-multiplexer@0 {
126 compatible = "renesas,shdma-mux";
127 #dma-cells = <1>;
128 dma-channels = <20>;
129 dma-requests = <256>;
130 #address-cells = <2>;
131 #size-cells = <2>;
132 ranges;
133
134 dma0: dma-controller@e6700020 {
135 compatible = "renesas,shdma-r8a73a4";
136 reg = <0 0xe6700020 0 0x89e0>;
137 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
138 0 200 IRQ_TYPE_LEVEL_HIGH
139 0 201 IRQ_TYPE_LEVEL_HIGH
140 0 202 IRQ_TYPE_LEVEL_HIGH
141 0 203 IRQ_TYPE_LEVEL_HIGH
142 0 204 IRQ_TYPE_LEVEL_HIGH
143 0 205 IRQ_TYPE_LEVEL_HIGH
144 0 206 IRQ_TYPE_LEVEL_HIGH
145 0 207 IRQ_TYPE_LEVEL_HIGH
146 0 208 IRQ_TYPE_LEVEL_HIGH
147 0 209 IRQ_TYPE_LEVEL_HIGH
148 0 210 IRQ_TYPE_LEVEL_HIGH
149 0 211 IRQ_TYPE_LEVEL_HIGH
150 0 212 IRQ_TYPE_LEVEL_HIGH
151 0 213 IRQ_TYPE_LEVEL_HIGH
152 0 214 IRQ_TYPE_LEVEL_HIGH
153 0 215 IRQ_TYPE_LEVEL_HIGH
154 0 216 IRQ_TYPE_LEVEL_HIGH
155 0 217 IRQ_TYPE_LEVEL_HIGH
156 0 218 IRQ_TYPE_LEVEL_HIGH
157 0 219 IRQ_TYPE_LEVEL_HIGH>;
158 interrupt-names = "error",
159 "ch0", "ch1", "ch2", "ch3",
160 "ch4", "ch5", "ch6", "ch7",
161 "ch8", "ch9", "ch10", "ch11",
162 "ch12", "ch13", "ch14", "ch15",
163 "ch16", "ch17", "ch18", "ch19";
164 };
165 };
166
167 thermal@e61f0000 { 198 thermal@e61f0000 {
168 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; 199 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
169 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, 200 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
@@ -174,7 +205,7 @@
174 i2c0: i2c@e6500000 { 205 i2c0: i2c@e6500000 {
175 #address-cells = <1>; 206 #address-cells = <1>;
176 #size-cells = <0>; 207 #size-cells = <0>;
177 compatible = "renesas,rmobile-iic"; 208 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
178 reg = <0 0xe6500000 0 0x428>; 209 reg = <0 0xe6500000 0 0x428>;
179 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; 210 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
180 status = "disabled"; 211 status = "disabled";
@@ -183,7 +214,7 @@
183 i2c1: i2c@e6510000 { 214 i2c1: i2c@e6510000 {
184 #address-cells = <1>; 215 #address-cells = <1>;
185 #size-cells = <0>; 216 #size-cells = <0>;
186 compatible = "renesas,rmobile-iic"; 217 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
187 reg = <0 0xe6510000 0 0x428>; 218 reg = <0 0xe6510000 0 0x428>;
188 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; 219 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
189 status = "disabled"; 220 status = "disabled";
@@ -192,7 +223,7 @@
192 i2c2: i2c@e6520000 { 223 i2c2: i2c@e6520000 {
193 #address-cells = <1>; 224 #address-cells = <1>;
194 #size-cells = <0>; 225 #size-cells = <0>;
195 compatible = "renesas,rmobile-iic"; 226 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
196 reg = <0 0xe6520000 0 0x428>; 227 reg = <0 0xe6520000 0 0x428>;
197 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; 228 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
198 status = "disabled"; 229 status = "disabled";
@@ -201,7 +232,7 @@
201 i2c3: i2c@e6530000 { 232 i2c3: i2c@e6530000 {
202 #address-cells = <1>; 233 #address-cells = <1>;
203 #size-cells = <0>; 234 #size-cells = <0>;
204 compatible = "renesas,rmobile-iic"; 235 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
205 reg = <0 0xe6530000 0 0x428>; 236 reg = <0 0xe6530000 0 0x428>;
206 interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; 237 interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
207 status = "disabled"; 238 status = "disabled";
@@ -210,25 +241,16 @@
210 i2c4: i2c@e6540000 { 241 i2c4: i2c@e6540000 {
211 #address-cells = <1>; 242 #address-cells = <1>;
212 #size-cells = <0>; 243 #size-cells = <0>;
213 compatible = "renesas,rmobile-iic"; 244 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
214 reg = <0 0xe6540000 0 0x428>; 245 reg = <0 0xe6540000 0 0x428>;
215 interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>; 246 interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>;
216 status = "disabled"; 247 status = "disabled";
217 }; 248 };
218 249
219 i2c5: i2c@e60b0000 {
220 #address-cells = <1>;
221 #size-cells = <0>;
222 compatible = "renesas,rmobile-iic";
223 reg = <0 0xe60b0000 0 0x428>;
224 interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>;
225 status = "disabled";
226 };
227
228 i2c6: i2c@e6550000 { 250 i2c6: i2c@e6550000 {
229 #address-cells = <1>; 251 #address-cells = <1>;
230 #size-cells = <0>; 252 #size-cells = <0>;
231 compatible = "renesas,rmobile-iic"; 253 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
232 reg = <0 0xe6550000 0 0x428>; 254 reg = <0 0xe6550000 0 0x428>;
233 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; 255 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
234 status = "disabled"; 256 status = "disabled";
@@ -237,7 +259,7 @@
237 i2c7: i2c@e6560000 { 259 i2c7: i2c@e6560000 {
238 #address-cells = <1>; 260 #address-cells = <1>;
239 #size-cells = <0>; 261 #size-cells = <0>;
240 compatible = "renesas,rmobile-iic"; 262 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
241 reg = <0 0xe6560000 0 0x428>; 263 reg = <0 0xe6560000 0 0x428>;
242 interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; 264 interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
243 status = "disabled"; 265 status = "disabled";
@@ -246,12 +268,26 @@
246 i2c8: i2c@e6570000 { 268 i2c8: i2c@e6570000 {
247 #address-cells = <1>; 269 #address-cells = <1>;
248 #size-cells = <0>; 270 #size-cells = <0>;
249 compatible = "renesas,rmobile-iic"; 271 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
250 reg = <0 0xe6570000 0 0x428>; 272 reg = <0 0xe6570000 0 0x428>;
251 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; 273 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
252 status = "disabled"; 274 status = "disabled";
253 }; 275 };
254 276
277 scifb0: serial@e6c20000 {
278 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
279 reg = <0 0xe6c20000 0 0x100>;
280 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
281 status = "disabled";
282 };
283
284 scifb1: serial@e6c30000 {
285 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
286 reg = <0 0xe6c30000 0 0x100>;
287 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
288 status = "disabled";
289 };
290
255 scifa0: serial@e6c40000 { 291 scifa0: serial@e6c40000 {
256 compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; 292 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
257 reg = <0 0xe6c40000 0 0x100>; 293 reg = <0 0xe6c40000 0 0x100>;
@@ -266,73 +302,20 @@
266 status = "disabled"; 302 status = "disabled";
267 }; 303 };
268 304
269 scifb2: serial@e6c20000 { 305 scifb2: serial@e6ce0000 {
270 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
271 reg = <0 0xe6c20000 0 0x100>;
272 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
273 status = "disabled";
274 };
275
276 scifb3: serial@e6c30000 {
277 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
278 reg = <0 0xe6c30000 0 0x100>;
279 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
280 status = "disabled";
281 };
282
283 scifb4: serial@e6ce0000 {
284 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 306 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
285 reg = <0 0xe6ce0000 0 0x100>; 307 reg = <0 0xe6ce0000 0 0x100>;
286 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; 308 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
287 status = "disabled"; 309 status = "disabled";
288 }; 310 };
289 311
290 scifb5: serial@e6cf0000 { 312 scifb3: serial@e6cf0000 {
291 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 313 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
292 reg = <0 0xe6cf0000 0 0x100>; 314 reg = <0 0xe6cf0000 0 0x100>;
293 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; 315 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
294 status = "disabled"; 316 status = "disabled";
295 }; 317 };
296 318
297 mmcif0: mmc@ee200000 {
298 compatible = "renesas,sh-mmcif";
299 reg = <0 0xee200000 0 0x80>;
300 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
301 reg-io-width = <4>;
302 status = "disabled";
303 };
304
305 mmcif1: mmc@ee220000 {
306 compatible = "renesas,sh-mmcif";
307 reg = <0 0xee220000 0 0x80>;
308 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
309 reg-io-width = <4>;
310 status = "disabled";
311 };
312
313 pfc: pfc@e6050000 {
314 compatible = "renesas,pfc-r8a73a4";
315 reg = <0 0xe6050000 0 0x9000>;
316 gpio-controller;
317 #gpio-cells = <2>;
318 interrupts-extended =
319 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
320 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
321 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
322 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
323 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
324 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
325 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
326 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
327 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
328 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
329 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
330 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
331 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
332 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
333 <&irqc1 24 0>, <&irqc1 25 0>;
334 };
335
336 sdhi0: sd@ee100000 { 319 sdhi0: sd@ee100000 {
337 compatible = "renesas,sdhi-r8a73a4"; 320 compatible = "renesas,sdhi-r8a73a4";
338 reg = <0 0xee100000 0 0x100>; 321 reg = <0 0xee100000 0 0x100>;
@@ -356,4 +339,32 @@
356 cap-sd-highspeed; 339 cap-sd-highspeed;
357 status = "disabled"; 340 status = "disabled";
358 }; 341 };
342
343 mmcif0: mmc@ee200000 {
344 compatible = "renesas,sh-mmcif";
345 reg = <0 0xee200000 0 0x80>;
346 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
347 reg-io-width = <4>;
348 status = "disabled";
349 };
350
351 mmcif1: mmc@ee220000 {
352 compatible = "renesas,sh-mmcif";
353 reg = <0 0xee220000 0 0x80>;
354 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
355 reg-io-width = <4>;
356 status = "disabled";
357 };
358
359 gic: interrupt-controller@f1001000 {
360 compatible = "arm,cortex-a15-gic";
361 #interrupt-cells = <3>;
362 #address-cells = <0>;
363 interrupt-controller;
364 reg = <0 0xf1001000 0 0x1000>,
365 <0 0xf1002000 0 0x1000>,
366 <0 0xf1004000 0 0x2000>,
367 <0 0xf1006000 0 0x2000>;
368 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
369 };
359}; 370};
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index effb7b46f131..d4af4d86c6b0 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -25,6 +25,7 @@
25 25
26 chosen { 26 chosen {
27 bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; 27 bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
28 stdout-path = &scifa1;
28 }; 29 };
29 30
30 memory { 31 memory {
@@ -77,7 +78,7 @@
77 regulator-boot-on; 78 regulator-boot-on;
78 }; 79 };
79 80
80 gpio-keys { 81 keyboard {
81 compatible = "gpio-keys"; 82 compatible = "gpio-keys";
82 83
83 power-key { 84 power-key {
@@ -298,3 +299,7 @@
298 299
299 status = "okay"; 300 status = "okay";
300}; 301};
302
303&tmu0 {
304 status = "okay";
305};
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index d46c213a17ad..aec8da89ef9a 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -71,6 +71,7 @@
71 0 149 IRQ_TYPE_LEVEL_HIGH 71 0 149 IRQ_TYPE_LEVEL_HIGH
72 0 149 IRQ_TYPE_LEVEL_HIGH 72 0 149 IRQ_TYPE_LEVEL_HIGH
73 0 149 IRQ_TYPE_LEVEL_HIGH>; 73 0 149 IRQ_TYPE_LEVEL_HIGH>;
74 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
74 }; 75 };
75 76
76 /* irqpin1: IRQ8 - IRQ15 */ 77 /* irqpin1: IRQ8 - IRQ15 */
@@ -91,6 +92,7 @@
91 0 149 IRQ_TYPE_LEVEL_HIGH 92 0 149 IRQ_TYPE_LEVEL_HIGH
92 0 149 IRQ_TYPE_LEVEL_HIGH 93 0 149 IRQ_TYPE_LEVEL_HIGH
93 0 149 IRQ_TYPE_LEVEL_HIGH>; 94 0 149 IRQ_TYPE_LEVEL_HIGH>;
95 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
94 }; 96 };
95 97
96 /* irqpin2: IRQ16 - IRQ23 */ 98 /* irqpin2: IRQ16 - IRQ23 */
@@ -111,6 +113,7 @@
111 0 149 IRQ_TYPE_LEVEL_HIGH 113 0 149 IRQ_TYPE_LEVEL_HIGH
112 0 149 IRQ_TYPE_LEVEL_HIGH 114 0 149 IRQ_TYPE_LEVEL_HIGH
113 0 149 IRQ_TYPE_LEVEL_HIGH>; 115 0 149 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
114 }; 117 };
115 118
116 /* irqpin3: IRQ24 - IRQ31 */ 119 /* irqpin3: IRQ24 - IRQ31 */
@@ -131,6 +134,7 @@
131 0 149 IRQ_TYPE_LEVEL_HIGH 134 0 149 IRQ_TYPE_LEVEL_HIGH
132 0 149 IRQ_TYPE_LEVEL_HIGH 135 0 149 IRQ_TYPE_LEVEL_HIGH
133 0 149 IRQ_TYPE_LEVEL_HIGH>; 136 0 149 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
134 }; 138 };
135 139
136 ether: ethernet@e9a00000 { 140 ether: ethernet@e9a00000 {
@@ -193,7 +197,7 @@
193 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 197 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
194 reg = <0xe6c60000 0x100>; 198 reg = <0xe6c60000 0x100>;
195 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; 199 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; 200 clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
197 clock-names = "sci_ick"; 201 clock-names = "sci_ick";
198 status = "disabled"; 202 status = "disabled";
199 }; 203 };
@@ -331,6 +335,34 @@
331 status = "disabled"; 335 status = "disabled";
332 }; 336 };
333 337
338 tmu0: timer@fff80000 {
339 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
340 reg = <0xfff80000 0x2c>;
341 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
342 <0 199 IRQ_TYPE_LEVEL_HIGH>,
343 <0 200 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
345 clock-names = "fck";
346
347 #renesas,channels = <3>;
348
349 status = "disabled";
350 };
351
352 tmu1: timer@fff90000 {
353 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
354 reg = <0xfff90000 0x2c>;
355 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>,
356 <0 171 IRQ_TYPE_LEVEL_HIGH>,
357 <0 172 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
359 clock-names = "fck";
360
361 #renesas,channels = <3>;
362
363 status = "disabled";
364 };
365
334 clocks { 366 clocks {
335 #address-cells = <1>; 367 #address-cells = <1>;
336 #size-cells = <1>; 368 #size-cells = <1>;
@@ -448,8 +480,8 @@
448 mstp2_clks: mstp2_clks@e6150138 { 480 mstp2_clks: mstp2_clks@e6150138 {
449 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; 481 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
450 reg = <0xe6150138 4>, <0xe6150040 4>; 482 reg = <0xe6150138 4>, <0xe6150040 4>;
451 clocks = <&sub_clk>, <&sub_clk>, 483 clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
452 <&cpg_clocks R8A7740_CLK_HP>, 484 <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
453 <&cpg_clocks R8A7740_CLK_HP>, 485 <&cpg_clocks R8A7740_CLK_HP>,
454 <&cpg_clocks R8A7740_CLK_HP>, 486 <&cpg_clocks R8A7740_CLK_HP>,
455 <&cpg_clocks R8A7740_CLK_HP>, 487 <&cpg_clocks R8A7740_CLK_HP>,
@@ -458,7 +490,8 @@
458 <&sub_clk>; 490 <&sub_clk>;
459 #clock-cells = <1>; 491 #clock-cells = <1>;
460 renesas,clock-indices = < 492 renesas,clock-indices = <
461 R8A7740_CLK_SCIFA6 R8A7740_CLK_SCIFA7 493 R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
494 R8A7740_CLK_SCIFA7
462 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2 495 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
463 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC 496 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
464 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB 497 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
@@ -467,7 +500,8 @@
467 R8A7740_CLK_SCIFA4 500 R8A7740_CLK_SCIFA4
468 >; 501 >;
469 clock-output-names = 502 clock-output-names =
470 "scifa6", "scifa7", "dmac1", "dmac2", "dmac3", 503 "scifa6", "intca",
504 "scifa7", "dmac1", "dmac2", "dmac3",
471 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1", 505 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
472 "scifa2", "scifa3", "scifa4"; 506 "scifa2", "scifa3", "scifa4";
473 }; 507 };
diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
index 3342c74c5de8..04c0c37bb784 100644
--- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
@@ -28,7 +28,8 @@
28 }; 28 };
29 29
30 chosen { 30 chosen {
31 bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; 31 bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp rw";
32 stdout-path = &scif0;
32 }; 33 };
33 34
34 memory { 35 memory {
@@ -73,6 +74,10 @@
73 status = "okay"; 74 status = "okay";
74}; 75};
75 76
77&tmu0 {
78 status = "okay";
79};
80
76&pfc { 81&pfc {
77 scif0_pins: serial0 { 82 scif0_pins: serial0 {
78 renesas,groups = "scif0_data_a", "scif0_ctrl"; 83 renesas,groups = "scif0_data_a", "scif0_ctrl";
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 315ec62cb96b..ef8533910029 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -162,6 +162,42 @@
162 status = "disabled"; 162 status = "disabled";
163 }; 163 };
164 164
165 tmu0: timer@ffd80000 {
166 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
167 reg = <0xffd80000 0x30>;
168 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
169 <0 33 IRQ_TYPE_LEVEL_HIGH>,
170 <0 34 IRQ_TYPE_LEVEL_HIGH>;
171
172 #renesas,channels = <3>;
173
174 status = "disabled";
175 };
176
177 tmu1: timer@ffd81000 {
178 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
179 reg = <0xffd81000 0x30>;
180 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
181 <0 37 IRQ_TYPE_LEVEL_HIGH>,
182 <0 38 IRQ_TYPE_LEVEL_HIGH>;
183
184 #renesas,channels = <3>;
185
186 status = "disabled";
187 };
188
189 tmu2: timer@ffd82000 {
190 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
191 reg = <0xffd82000 0x30>;
192 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
193 <0 41 IRQ_TYPE_LEVEL_HIGH>,
194 <0 42 IRQ_TYPE_LEVEL_HIGH>;
195
196 #renesas,channels = <3>;
197
198 status = "disabled";
199 };
200
165 scif0: serial@ffe40000 { 201 scif0: serial@ffe40000 {
166 compatible = "renesas,scif-r8a7778", "renesas,scif"; 202 compatible = "renesas,scif-r8a7778", "renesas,scif";
167 reg = <0xffe40000 0x100>; 203 reg = <0xffe40000 0x100>;
@@ -215,8 +251,6 @@
215 compatible = "renesas,sdhi-r8a7778"; 251 compatible = "renesas,sdhi-r8a7778";
216 reg = <0xffe4c000 0x100>; 252 reg = <0xffe4c000 0x100>;
217 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; 253 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
218 cap-sd-highspeed;
219 cap-sdio-irq;
220 status = "disabled"; 254 status = "disabled";
221 }; 255 };
222 256
@@ -224,8 +258,6 @@
224 compatible = "renesas,sdhi-r8a7778"; 258 compatible = "renesas,sdhi-r8a7778";
225 reg = <0xffe4d000 0x100>; 259 reg = <0xffe4d000 0x100>;
226 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; 260 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
227 cap-sd-highspeed;
228 cap-sdio-irq;
229 status = "disabled"; 261 status = "disabled";
230 }; 262 };
231 263
@@ -233,8 +265,6 @@
233 compatible = "renesas,sdhi-r8a7778"; 265 compatible = "renesas,sdhi-r8a7778";
234 reg = <0xffe4f000 0x100>; 266 reg = <0xffe4f000 0x100>;
235 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 267 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
236 cap-sd-highspeed;
237 cap-sdio-irq;
238 status = "disabled"; 268 status = "disabled";
239 }; 269 };
240 270
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index c160404e4d40..e83d40e24bcd 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -25,6 +25,7 @@
25 25
26 chosen { 26 chosen {
27 bootargs = "console=ttySC2,115200 ignore_loglevel root=/dev/nfs ip=on"; 27 bootargs = "console=ttySC2,115200 ignore_loglevel root=/dev/nfs ip=on";
28 stdout-path = &scif2;
28 }; 29 };
29 30
30 memory { 31 memory {
@@ -68,6 +69,78 @@
68 gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; 69 gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
69 }; 70 };
70 }; 71 };
72
73 vga-encoder {
74 compatible = "adi,adv7123";
75
76 ports {
77 #address-cells = <1>;
78 #size-cells = <0>;
79
80 port@0 {
81 reg = <0>;
82 vga_enc_in: endpoint {
83 remote-endpoint = <&du_out_rgb0>;
84 };
85 };
86 port@1 {
87 reg = <1>;
88 vga_enc_out: endpoint {
89 remote-endpoint = <&vga_in>;
90 };
91 };
92 };
93 };
94
95 vga {
96 compatible = "vga-connector";
97
98 port {
99 vga_in: endpoint {
100 remote-endpoint = <&vga_enc_out>;
101 };
102 };
103 };
104
105 lvds-encoder {
106 compatible = "thine,thc63lvdm83d";
107
108 ports {
109 #address-cells = <1>;
110 #size-cells = <0>;
111
112 port@0 {
113 reg = <0>;
114 lvds_enc_in: endpoint {
115 remote-endpoint = <&du_out_rgb1>;
116 };
117 };
118 port@1 {
119 reg = <1>;
120 lvds_connector: endpoint {
121 };
122 };
123 };
124 };
125};
126
127&du {
128 pinctrl-0 = <&du_pins>;
129 pinctrl-names = "default";
130 status = "okay";
131
132 ports {
133 port@0 {
134 endpoint {
135 remote-endpoint = <&vga_enc_in>;
136 };
137 };
138 port@1 {
139 endpoint {
140 remote-endpoint = <&lvds_enc_in>;
141 };
142 };
143 };
71}; 144};
72 145
73&irqpin0 { 146&irqpin0 {
@@ -83,6 +156,17 @@
83}; 156};
84 157
85&pfc { 158&pfc {
159 du_pins: du {
160 du0 {
161 renesas,groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0";
162 renesas,function = "du0";
163 };
164 du1 {
165 renesas,groups = "du1_rgb666", "du1_sync_1", "du1_clk_out";
166 renesas,function = "du1";
167 };
168 };
169
86 lan0_pins: lan0 { 170 lan0_pins: lan0 {
87 intc { 171 intc {
88 renesas,groups = "intc_irq1_b"; 172 renesas,groups = "intc_irq1_b";
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 7cfba9aa1b41..ede9a29e4bc6 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -303,7 +303,7 @@
303 }; 303 };
304 304
305 sata: sata@fc600000 { 305 sata: sata@fc600000 {
306 compatible = "renesas,rcar-sata"; 306 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
307 reg = <0xfc600000 0x2000>; 307 reg = <0xfc600000 0x2000>;
308 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; 308 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&mstp1_clks R8A7779_CLK_SATA>; 309 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
@@ -314,8 +314,6 @@
314 reg = <0xffe4c000 0x100>; 314 reg = <0xffe4c000 0x100>;
315 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; 315 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; 316 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
317 cap-sd-highspeed;
318 cap-sdio-irq;
319 status = "disabled"; 317 status = "disabled";
320 }; 318 };
321 319
@@ -324,8 +322,6 @@
324 reg = <0xffe4d000 0x100>; 322 reg = <0xffe4d000 0x100>;
325 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 323 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; 324 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
327 cap-sd-highspeed;
328 cap-sdio-irq;
329 status = "disabled"; 325 status = "disabled";
330 }; 326 };
331 327
@@ -334,8 +330,6 @@
334 reg = <0xffe4e000 0x100>; 330 reg = <0xffe4e000 0x100>;
335 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 331 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; 332 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
337 cap-sd-highspeed;
338 cap-sdio-irq;
339 status = "disabled"; 333 status = "disabled";
340 }; 334 };
341 335
@@ -344,8 +338,6 @@
344 reg = <0xffe4f000 0x100>; 338 reg = <0xffe4f000 0x100>;
345 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 339 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; 340 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
347 cap-sd-highspeed;
348 cap-sdio-irq;
349 status = "disabled"; 341 status = "disabled";
350 }; 342 };
351 343
@@ -379,6 +371,30 @@
379 status = "disabled"; 371 status = "disabled";
380 }; 372 };
381 373
374 du: display@fff80000 {
375 compatible = "renesas,du-r8a7779";
376 reg = <0 0xfff80000 0 0x40000>;
377 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&mstp1_clks R8A7779_CLK_DU>;
379 status = "disabled";
380
381 ports {
382 #address-cells = <1>;
383 #size-cells = <0>;
384
385 port@0 {
386 reg = <0>;
387 du_out_rgb0: endpoint {
388 };
389 };
390 port@1 {
391 reg = <1>;
392 du_out_rgb1: endpoint {
393 };
394 };
395 };
396 };
397
382 clocks { 398 clocks {
383 #address-cells = <1>; 399 #address-cells = <1>;
384 #size-cells = <1>; 400 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 69098b906b39..636d53bb87a2 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -9,6 +9,34 @@
9 * kind, whether express or implied. 9 * kind, whether express or implied.
10 */ 10 */
11 11
12/*
13 * SSI-AK4643
14 *
15 * SW1: 1: AK4643
16 * 2: CN22
17 * 3: ADV7511
18 *
19 * This command is required when Playback/Capture
20 *
21 * amixer set "LINEOUT Mixer DACL" on
22 * amixer set "DVC Out" 100%
23 * amixer set "DVC In" 100%
24 *
25 * You can use Mute
26 *
27 * amixer set "DVC Out Mute" on
28 * amixer set "DVC In Mute" on
29 *
30 * You can use Volume Ramp
31 *
32 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
33 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
34 * amixer set "DVC Out Ramp" on
35 * aplay xxx.wav &
36 * amixer set "DVC Out" 80% // Volume Down
37 * amixer set "DVC Out" 100% // Volume Up
38 */
39
12/dts-v1/; 40/dts-v1/;
13#include "r8a7790.dtsi" 41#include "r8a7790.dtsi"
14#include <dt-bindings/gpio/gpio.h> 42#include <dt-bindings/gpio/gpio.h>
@@ -19,12 +47,13 @@
19 compatible = "renesas,lager", "renesas,r8a7790"; 47 compatible = "renesas,lager", "renesas,r8a7790";
20 48
21 aliases { 49 aliases {
22 serial6 = &scif0; 50 serial6 = &scifa0;
23 serial7 = &scif1; 51 serial7 = &scifa1;
24 }; 52 };
25 53
26 chosen { 54 chosen {
27 bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; 55 bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
56 stdout-path = &scifa0;
28 }; 57 };
29 58
30 memory@40000000 { 59 memory@40000000 {
@@ -42,7 +71,7 @@
42 #size-cells = <1>; 71 #size-cells = <1>;
43 }; 72 };
44 73
45 gpio_keys { 74 keyboard {
46 compatible = "gpio-keys"; 75 compatible = "gpio-keys";
47 76
48 button@1 { 77 button@1 {
@@ -144,6 +173,73 @@
144 states = <3300000 1 173 states = <3300000 1
145 1800000 0>; 174 1800000 0>;
146 }; 175 };
176
177 sound {
178 compatible = "simple-audio-card";
179
180 simple-audio-card,format = "left_j";
181 simple-audio-card,bitclock-master = <&sndcodec>;
182 simple-audio-card,frame-master = <&sndcodec>;
183
184 sndcpu: simple-audio-card,cpu {
185 sound-dai = <&rcar_sound>;
186 };
187
188 sndcodec: simple-audio-card,codec {
189 sound-dai = <&ak4643>;
190 system-clock-frequency = <11289600>;
191 };
192 };
193
194 vga-encoder {
195 compatible = "adi,adv7123";
196
197 ports {
198 #address-cells = <1>;
199 #size-cells = <0>;
200
201 port@0 {
202 reg = <0>;
203 adv7123_in: endpoint {
204 remote-endpoint = <&du_out_rgb>;
205 };
206 };
207 port@1 {
208 reg = <1>;
209 adv7123_out: endpoint {
210 remote-endpoint = <&vga_in>;
211 };
212 };
213 };
214 };
215
216 vga {
217 compatible = "vga-connector";
218
219 port {
220 vga_in: endpoint {
221 remote-endpoint = <&adv7123_out>;
222 };
223 };
224 };
225};
226
227&du {
228 pinctrl-0 = <&du_pins>;
229 pinctrl-names = "default";
230 status = "okay";
231
232 ports {
233 port@0 {
234 endpoint {
235 remote-endpoint = <&adv7123_in>;
236 };
237 };
238 port@2 {
239 lvds_connector: endpoint {
240 };
241 };
242 };
147}; 243};
148 244
149&extal_clk { 245&extal_clk {
@@ -151,17 +247,14 @@
151}; 247};
152 248
153&pfc { 249&pfc {
154 pinctrl-0 = <&du_pins>;
155 pinctrl-names = "default";
156
157 du_pins: du { 250 du_pins: du {
158 renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0"; 251 renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
159 renesas,function = "du"; 252 renesas,function = "du";
160 }; 253 };
161 254
162 scif0_pins: serial0 { 255 scifa0_pins: serial0 {
163 renesas,groups = "scif0_data"; 256 renesas,groups = "scifa0_data";
164 renesas,function = "scif0"; 257 renesas,function = "scifa0";
165 }; 258 };
166 259
167 ether_pins: ether { 260 ether_pins: ether {
@@ -174,9 +267,9 @@
174 renesas,function = "intc"; 267 renesas,function = "intc";
175 }; 268 };
176 269
177 scif1_pins: serial1 { 270 scifa1_pins: serial1 {
178 renesas,groups = "scif1_data"; 271 renesas,groups = "scifa1_data";
179 renesas,function = "scif1"; 272 renesas,function = "scifa1";
180 }; 273 };
181 274
182 sdhi0_pins: sd0 { 275 sdhi0_pins: sd0 {
@@ -220,6 +313,11 @@
220 renesas,function = "iic3"; 313 renesas,function = "iic3";
221 }; 314 };
222 315
316 hsusb_pins: hsusb {
317 renesas,groups = "usb0_ovc_vbus";
318 renesas,function = "usb0";
319 };
320
223 usb0_pins: usb0 { 321 usb0_pins: usb0 {
224 renesas,groups = "usb0"; 322 renesas,groups = "usb0";
225 renesas,function = "usb0"; 323 renesas,function = "usb0";
@@ -239,6 +337,16 @@
239 renesas,groups = "vin1_data8", "vin1_clk"; 337 renesas,groups = "vin1_data8", "vin1_clk";
240 renesas,function = "vin1"; 338 renesas,function = "vin1";
241 }; 339 };
340
341 sound_pins: sound {
342 renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
343 renesas,function = "ssi";
344 };
345
346 sound_clk_pins: sound_clk {
347 renesas,groups = "audio_clk_a";
348 renesas,function = "audio_clk";
349 };
242}; 350};
243 351
244&ether { 352&ether {
@@ -308,15 +416,15 @@
308 }; 416 };
309}; 417};
310 418
311&scif0 { 419&scifa0 {
312 pinctrl-0 = <&scif0_pins>; 420 pinctrl-0 = <&scifa0_pins>;
313 pinctrl-names = "default"; 421 pinctrl-names = "default";
314 422
315 status = "okay"; 423 status = "okay";
316}; 424};
317 425
318&scif1 { 426&scifa1 {
319 pinctrl-0 = <&scif1_pins>; 427 pinctrl-0 = <&scifa1_pins>;
320 pinctrl-names = "default"; 428 pinctrl-names = "default";
321 429
322 status = "okay"; 430 status = "okay";
@@ -376,6 +484,14 @@
376 pinctrl-0 = <&iic2_pins>; 484 pinctrl-0 = <&iic2_pins>;
377 pinctrl-names = "default"; 485 pinctrl-names = "default";
378 486
487 clock-frequency = <100000>;
488
489 ak4643: sound-codec@12 {
490 compatible = "asahi-kasei,ak4643";
491 #sound-dai-cells = <0>;
492 reg = <0x12>;
493 };
494
379 composite-in@20 { 495 composite-in@20 {
380 compatible = "adi,adv7180"; 496 compatible = "adi,adv7180";
381 reg = <0x20>; 497 reg = <0x20>;
@@ -418,12 +534,29 @@
418 pinctrl-names = "default"; 534 pinctrl-names = "default";
419}; 535};
420 536
537&xhci {
538 status = "okay";
539 pinctrl-0 = <&usb2_pins>;
540 pinctrl-names = "default";
541};
542
421&pci2 { 543&pci2 {
422 status = "okay"; 544 status = "okay";
423 pinctrl-0 = <&usb2_pins>; 545 pinctrl-0 = <&usb2_pins>;
424 pinctrl-names = "default"; 546 pinctrl-names = "default";
425}; 547};
426 548
549&hsusb {
550 status = "okay";
551 pinctrl-0 = <&hsusb_pins>;
552 pinctrl-names = "default";
553 renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>;
554};
555
556&usbphy {
557 status = "okay";
558};
559
427/* composite video input */ 560/* composite video input */
428&vin1 { 561&vin1 {
429 pinctrl-0 = <&vin1_pins>; 562 pinctrl-0 = <&vin1_pins>;
@@ -441,3 +574,23 @@
441 }; 574 };
442 }; 575 };
443}; 576};
577
578&rcar_sound {
579 pinctrl-0 = <&sound_pins &sound_clk_pins>;
580 pinctrl-names = "default";
581
582 #sound-dai-cells = <0>;
583
584 status = "okay";
585
586 rcar_sound,dai {
587 dai0 {
588 playback = <&ssi0 &src2 &dvc0>;
589 capture = <&ssi1 &src3 &dvc1>;
590 };
591 };
592};
593
594&ssi1 {
595 shared-pin;
596};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index d0e17733dc1a..c8f94a6eb136 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -312,6 +312,70 @@
312 #dma-cells = <1>; 312 #dma-cells = <1>;
313 dma-channels = <15>; 313 dma-channels = <15>;
314 }; 314 };
315
316 audma0: dma-controller@ec700000 {
317 compatible = "renesas,rcar-dmac";
318 reg = <0 0xec700000 0 0x10000>;
319 interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH
320 0 320 IRQ_TYPE_LEVEL_HIGH
321 0 321 IRQ_TYPE_LEVEL_HIGH
322 0 322 IRQ_TYPE_LEVEL_HIGH
323 0 323 IRQ_TYPE_LEVEL_HIGH
324 0 324 IRQ_TYPE_LEVEL_HIGH
325 0 325 IRQ_TYPE_LEVEL_HIGH
326 0 326 IRQ_TYPE_LEVEL_HIGH
327 0 327 IRQ_TYPE_LEVEL_HIGH
328 0 328 IRQ_TYPE_LEVEL_HIGH
329 0 329 IRQ_TYPE_LEVEL_HIGH
330 0 330 IRQ_TYPE_LEVEL_HIGH
331 0 331 IRQ_TYPE_LEVEL_HIGH
332 0 332 IRQ_TYPE_LEVEL_HIGH>;
333 interrupt-names = "error",
334 "ch0", "ch1", "ch2", "ch3",
335 "ch4", "ch5", "ch6", "ch7",
336 "ch8", "ch9", "ch10", "ch11",
337 "ch12";
338 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
339 clock-names = "fck";
340 #dma-cells = <1>;
341 dma-channels = <13>;
342 };
343
344 audma1: dma-controller@ec720000 {
345 compatible = "renesas,rcar-dmac";
346 reg = <0 0xec720000 0 0x10000>;
347 interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH
348 0 333 IRQ_TYPE_LEVEL_HIGH
349 0 334 IRQ_TYPE_LEVEL_HIGH
350 0 335 IRQ_TYPE_LEVEL_HIGH
351 0 336 IRQ_TYPE_LEVEL_HIGH
352 0 337 IRQ_TYPE_LEVEL_HIGH
353 0 338 IRQ_TYPE_LEVEL_HIGH
354 0 339 IRQ_TYPE_LEVEL_HIGH
355 0 340 IRQ_TYPE_LEVEL_HIGH
356 0 341 IRQ_TYPE_LEVEL_HIGH
357 0 342 IRQ_TYPE_LEVEL_HIGH
358 0 343 IRQ_TYPE_LEVEL_HIGH
359 0 344 IRQ_TYPE_LEVEL_HIGH
360 0 345 IRQ_TYPE_LEVEL_HIGH>;
361 interrupt-names = "error",
362 "ch0", "ch1", "ch2", "ch3",
363 "ch4", "ch5", "ch6", "ch7",
364 "ch8", "ch9", "ch10", "ch11",
365 "ch12";
366 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
367 clock-names = "fck";
368 #dma-cells = <1>;
369 dma-channels = <13>;
370 };
371
372 audmapp: dma-controller@ec740000 {
373 compatible = "renesas,rcar-audmapp";
374 #dma-cells = <1>;
375
376 reg = <0 0xec740000 0 0x200>;
377 };
378
315 i2c0: i2c@e6508000 { 379 i2c0: i2c@e6508000 {
316 #address-cells = <1>; 380 #address-cells = <1>;
317 #size-cells = <0>; 381 #size-cells = <0>;
@@ -359,6 +423,8 @@
359 reg = <0 0xe6500000 0 0x425>; 423 reg = <0 0xe6500000 0 0x425>;
360 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; 424 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&mstp3_clks R8A7790_CLK_IIC0>; 425 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
426 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
427 dma-names = "tx", "rx";
362 status = "disabled"; 428 status = "disabled";
363 }; 429 };
364 430
@@ -369,6 +435,8 @@
369 reg = <0 0xe6510000 0 0x425>; 435 reg = <0 0xe6510000 0 0x425>;
370 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; 436 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&mstp3_clks R8A7790_CLK_IIC1>; 437 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
438 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
439 dma-names = "tx", "rx";
372 status = "disabled"; 440 status = "disabled";
373 }; 441 };
374 442
@@ -379,6 +447,8 @@
379 reg = <0 0xe6520000 0 0x425>; 447 reg = <0 0xe6520000 0 0x425>;
380 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; 448 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&mstp3_clks R8A7790_CLK_IIC2>; 449 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
450 dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
451 dma-names = "tx", "rx";
382 status = "disabled"; 452 status = "disabled";
383 }; 453 };
384 454
@@ -389,14 +459,18 @@
389 reg = <0 0xe60b0000 0 0x425>; 459 reg = <0 0xe60b0000 0 0x425>;
390 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; 460 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; 461 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
462 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
463 dma-names = "tx", "rx";
392 status = "disabled"; 464 status = "disabled";
393 }; 465 };
394 466
395 mmcif0: mmcif@ee200000 { 467 mmcif0: mmc@ee200000 {
396 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; 468 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
397 reg = <0 0xee200000 0 0x80>; 469 reg = <0 0xee200000 0 0x80>;
398 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; 470 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; 471 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
472 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
473 dma-names = "tx", "rx";
400 reg-io-width = <4>; 474 reg-io-width = <4>;
401 status = "disabled"; 475 status = "disabled";
402 }; 476 };
@@ -406,6 +480,8 @@
406 reg = <0 0xee220000 0 0x80>; 480 reg = <0 0xee220000 0 0x80>;
407 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; 481 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; 482 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
483 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
484 dma-names = "tx", "rx";
409 reg-io-width = <4>; 485 reg-io-width = <4>;
410 status = "disabled"; 486 status = "disabled";
411 }; 487 };
@@ -420,7 +496,6 @@
420 reg = <0 0xee100000 0 0x200>; 496 reg = <0 0xee100000 0 0x200>;
421 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 497 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; 498 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
423 cap-sd-highspeed;
424 status = "disabled"; 499 status = "disabled";
425 }; 500 };
426 501
@@ -429,7 +504,6 @@
429 reg = <0 0xee120000 0 0x200>; 504 reg = <0 0xee120000 0 0x200>;
430 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; 505 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; 506 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
432 cap-sd-highspeed;
433 status = "disabled"; 507 status = "disabled";
434 }; 508 };
435 509
@@ -438,7 +512,6 @@
438 reg = <0 0xee140000 0 0x100>; 512 reg = <0 0xee140000 0 0x100>;
439 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; 513 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; 514 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
441 cap-sd-highspeed;
442 status = "disabled"; 515 status = "disabled";
443 }; 516 };
444 517
@@ -447,7 +520,6 @@
447 reg = <0 0xee160000 0 0x100>; 520 reg = <0 0xee160000 0 0x100>;
448 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; 521 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; 522 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
450 cap-sd-highspeed;
451 status = "disabled"; 523 status = "disabled";
452 }; 524 };
453 525
@@ -568,6 +640,36 @@
568 status = "disabled"; 640 status = "disabled";
569 }; 641 };
570 642
643 hsusb: usb@e6590000 {
644 compatible = "renesas,usbhs-r8a7790";
645 reg = <0 0xe6590000 0 0x100>;
646 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
648 renesas,buswait = <4>;
649 phys = <&usb0 1>;
650 phy-names = "usb";
651 status = "disabled";
652 };
653
654 usbphy: usb-phy@e6590100 {
655 compatible = "renesas,usb-phy-r8a7790";
656 reg = <0 0xe6590100 0 0x100>;
657 #address-cells = <1>;
658 #size-cells = <0>;
659 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
660 clock-names = "usbhs";
661 status = "disabled";
662
663 usb0: usb-channel@0 {
664 reg = <0>;
665 #phy-cells = <1>;
666 };
667 usb2: usb-channel@2 {
668 reg = <2>;
669 #phy-cells = <1>;
670 };
671 };
672
571 vin0: video@e6ef0000 { 673 vin0: video@e6ef0000 {
572 compatible = "renesas,vin-r8a7790"; 674 compatible = "renesas,vin-r8a7790";
573 clocks = <&mstp8_clks R8A7790_CLK_VIN0>; 675 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
@@ -600,6 +702,96 @@
600 status = "disabled"; 702 status = "disabled";
601 }; 703 };
602 704
705 vsp1@fe920000 {
706 compatible = "renesas,vsp1";
707 reg = <0 0xfe920000 0 0x8000>;
708 interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
710
711 renesas,has-sru;
712 renesas,#rpf = <5>;
713 renesas,#uds = <1>;
714 renesas,#wpf = <4>;
715 };
716
717 vsp1@fe928000 {
718 compatible = "renesas,vsp1";
719 reg = <0 0xfe928000 0 0x8000>;
720 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
722
723 renesas,has-lut;
724 renesas,has-sru;
725 renesas,#rpf = <5>;
726 renesas,#uds = <3>;
727 renesas,#wpf = <4>;
728 };
729
730 vsp1@fe930000 {
731 compatible = "renesas,vsp1";
732 reg = <0 0xfe930000 0 0x8000>;
733 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
735
736 renesas,has-lif;
737 renesas,has-lut;
738 renesas,#rpf = <4>;
739 renesas,#uds = <1>;
740 renesas,#wpf = <4>;
741 };
742
743 vsp1@fe938000 {
744 compatible = "renesas,vsp1";
745 reg = <0 0xfe938000 0 0x8000>;
746 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
748
749 renesas,has-lif;
750 renesas,has-lut;
751 renesas,#rpf = <4>;
752 renesas,#uds = <1>;
753 renesas,#wpf = <4>;
754 };
755
756 du: display@feb00000 {
757 compatible = "renesas,du-r8a7790";
758 reg = <0 0xfeb00000 0 0x70000>,
759 <0 0xfeb90000 0 0x1c>,
760 <0 0xfeb94000 0 0x1c>;
761 reg-names = "du", "lvds.0", "lvds.1";
762 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
763 <0 268 IRQ_TYPE_LEVEL_HIGH>,
764 <0 269 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
766 <&mstp7_clks R8A7790_CLK_DU1>,
767 <&mstp7_clks R8A7790_CLK_DU2>,
768 <&mstp7_clks R8A7790_CLK_LVDS0>,
769 <&mstp7_clks R8A7790_CLK_LVDS1>;
770 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
771 status = "disabled";
772
773 ports {
774 #address-cells = <1>;
775 #size-cells = <0>;
776
777 port@0 {
778 reg = <0>;
779 du_out_rgb: endpoint {
780 };
781 };
782 port@1 {
783 reg = <1>;
784 du_out_lvds0: endpoint {
785 };
786 };
787 port@2 {
788 reg = <2>;
789 du_out_lvds1: endpoint {
790 };
791 };
792 };
793 };
794
603 clocks { 795 clocks {
604 #address-cells = <2>; 796 #address-cells = <2>;
605 #size-cells = <2>; 797 #size-cells = <2>;
@@ -868,18 +1060,25 @@
868 mstp1_clks: mstp1_clks@e6150134 { 1060 mstp1_clks: mstp1_clks@e6150134 {
869 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1061 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
870 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 1062 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
871 clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, 1063 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
872 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, 1064 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
873 <&zs_clk>; 1065 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1066 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
874 #clock-cells = <1>; 1067 #clock-cells = <1>;
875 renesas,clock-indices = < 1068 renesas,clock-indices = <
876 R8A7790_CLK_JPU R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 1069 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
877 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 1070 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
878 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S 1071 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1072 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1073 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1074 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1075 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
879 >; 1076 >;
880 clock-output-names = 1077 clock-output-names =
881 "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", 1078 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
882 "vsp1-du0", "vsp1-rt", "vsp1-sy"; 1079 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1080 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
1081 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
883 }; 1082 };
884 mstp2_clks: mstp2_clks@e6150138 { 1083 mstp2_clks: mstp2_clks@e6150138 {
885 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1084 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -904,25 +1103,29 @@
904 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 1103 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
905 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, 1104 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
906 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, 1105 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
907 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; 1106 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1107 <&hp_clk>, <&hp_clk>;
908 #clock-cells = <1>; 1108 #clock-cells = <1>;
909 renesas,clock-indices = < 1109 renesas,clock-indices = <
910 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 1110 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
911 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 1111 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
912 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 1112 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1113 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
913 >; 1114 >;
914 clock-output-names = 1115 clock-output-names =
915 "iic2", "tpu0", "mmcif1", "sdhi3", 1116 "iic2", "tpu0", "mmcif1", "sdhi3",
916 "sdhi2", "sdhi1", "sdhi0", "mmcif0", 1117 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
917 "iic0", "pciec", "iic1", "ssusb", "cmt1"; 1118 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1119 "usbdmac0", "usbdmac1";
918 }; 1120 };
919 mstp5_clks: mstp5_clks@e6150144 { 1121 mstp5_clks: mstp5_clks@e6150144 {
920 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1122 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
921 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 1123 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
922 clocks = <&extal_clk>, <&p_clk>; 1124 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
923 #clock-cells = <1>; 1125 #clock-cells = <1>;
924 renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>; 1126 renesas,clock-indices = <R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
925 clock-output-names = "thermal", "pwm"; 1127 R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
1128 clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
926 }; 1129 };
927 mstp7_clks: mstp7_clks@e615014c { 1130 mstp7_clks: mstp7_clks@e615014c {
928 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1131 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1070,6 +1273,16 @@
1070 status = "disabled"; 1273 status = "disabled";
1071 }; 1274 };
1072 1275
1276 xhci: usb@ee000000 {
1277 compatible = "renesas,xhci-r8a7790";
1278 reg = <0 0xee000000 0 0xc00>;
1279 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1280 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1281 phys = <&usb2 1>;
1282 phy-names = "usb";
1283 status = "disabled";
1284 };
1285
1073 pci0: pci@ee090000 { 1286 pci0: pci@ee090000 {
1074 compatible = "renesas,pci-r8a7790"; 1287 compatible = "renesas,pci-r8a7790";
1075 device_type = "pci"; 1288 device_type = "pci";
@@ -1088,6 +1301,20 @@
1088 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 1301 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1089 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 1302 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1090 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; 1303 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1304
1305 usb@0,1 {
1306 reg = <0x800 0 0 0 0>;
1307 device_type = "pci";
1308 phys = <&usb0 0>;
1309 phy-names = "usb";
1310 };
1311
1312 usb@0,2 {
1313 reg = <0x1000 0 0 0 0>;
1314 device_type = "pci";
1315 phys = <&usb0 0>;
1316 phy-names = "usb";
1317 };
1091 }; 1318 };
1092 1319
1093 pci1: pci@ee0b0000 { 1320 pci1: pci@ee0b0000 {
@@ -1128,6 +1355,20 @@
1128 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 1355 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1129 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 1356 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1130 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; 1357 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1358
1359 usb@0,1 {
1360 reg = <0x800 0 0 0 0>;
1361 device_type = "pci";
1362 phys = <&usb2 0>;
1363 phy-names = "usb";
1364 };
1365
1366 usb@0,2 {
1367 reg = <0x1000 0 0 0 0>;
1368 device_type = "pci";
1369 phys = <&usb2 0>;
1370 phy-names = "usb";
1371 };
1131 }; 1372 };
1132 1373
1133 pciec: pcie@fe000000 { 1374 pciec: pcie@fe000000 {
@@ -1155,7 +1396,7 @@
1155 status = "disabled"; 1396 status = "disabled";
1156 }; 1397 };
1157 1398
1158 rcar_sound: rcar_sound@0xec500000 { 1399 rcar_sound: rcar_sound@ec500000 {
1159 #sound-dai-cells = <1>; 1400 #sound-dai-cells = <1>;
1160 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; 1401 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1161 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1402 reg = <0 0xec500000 0 0x1000>, /* SCU */
diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts
index f1b56de10205..740e38678032 100644
--- a/arch/arm/boot/dts/r8a7791-henninger.dts
+++ b/arch/arm/boot/dts/r8a7791-henninger.dts
@@ -23,6 +23,7 @@
23 23
24 chosen { 24 chosen {
25 bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp"; 25 bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp";
26 stdout-path = &scif0;
26 }; 27 };
27 28
28 memory@40000000 { 29 memory@40000000 {
@@ -271,6 +272,17 @@
271 pinctrl-names = "default"; 272 pinctrl-names = "default";
272}; 273};
273 274
275&hsusb {
276 status = "okay";
277 pinctrl-0 = <&usb0_pins>;
278 pinctrl-names = "default";
279 renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>;
280};
281
282&usbphy {
283 status = "okay";
284};
285
274&pcie_bus_clk { 286&pcie_bus_clk {
275 status = "okay"; 287 status = "okay";
276}; 288};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 07550e775e80..d6b5b8f23789 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -10,6 +10,34 @@
10 * kind, whether express or implied. 10 * kind, whether express or implied.
11 */ 11 */
12 12
13/*
14 * SSI-AK4643
15 *
16 * SW1: 1: AK4643
17 * 2: CN22
18 * 3: ADV7511
19 *
20 * This command is required when Playback/Capture
21 *
22 * amixer set "LINEOUT Mixer DACL" on
23 * amixer set "DVC Out" 100%
24 * amixer set "DVC In" 100%
25 *
26 * You can use Mute
27 *
28 * amixer set "DVC Out Mute" on
29 * amixer set "DVC In Mute" on
30 *
31 * You can use Volume Ramp
32 *
33 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
34 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
35 * amixer set "DVC Out Ramp" on
36 * aplay xxx.wav &
37 * amixer set "DVC Out" 80% // Volume Down
38 * amixer set "DVC Out" 100% // Volume Up
39 */
40
13/dts-v1/; 41/dts-v1/;
14#include "r8a7791.dtsi" 42#include "r8a7791.dtsi"
15#include <dt-bindings/gpio/gpio.h> 43#include <dt-bindings/gpio/gpio.h>
@@ -26,6 +54,7 @@
26 54
27 chosen { 55 chosen {
28 bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; 56 bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
57 stdout-path = &scif0;
29 }; 58 };
30 59
31 memory@40000000 { 60 memory@40000000 {
@@ -43,7 +72,7 @@
43 #size-cells = <1>; 72 #size-cells = <1>;
44 }; 73 };
45 74
46 gpio-keys { 75 keyboard {
47 compatible = "gpio-keys"; 76 compatible = "gpio-keys";
48 77
49 key-1 { 78 key-1 {
@@ -129,12 +158,15 @@
129 compatible = "gpio-leds"; 158 compatible = "gpio-leds";
130 led6 { 159 led6 {
131 gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; 160 gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
161 label = "LED6";
132 }; 162 };
133 led7 { 163 led7 {
134 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; 164 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
165 label = "LED7";
135 }; 166 };
136 led8 { 167 led8 {
137 gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; 168 gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
169 label = "LED8";
138 }; 170 };
139 }; 171 };
140 172
@@ -209,6 +241,36 @@
209 states = <3300000 1 241 states = <3300000 1
210 1800000 0>; 242 1800000 0>;
211 }; 243 };
244
245 sound {
246 compatible = "simple-audio-card";
247
248 simple-audio-card,format = "left_j";
249 simple-audio-card,bitclock-master = <&sndcodec>;
250 simple-audio-card,frame-master = <&sndcodec>;
251
252 sndcpu: simple-audio-card,cpu {
253 sound-dai = <&rcar_sound>;
254 };
255
256 sndcodec: simple-audio-card,codec {
257 sound-dai = <&ak4643>;
258 system-clock-frequency = <11289600>;
259 };
260 };
261};
262
263&du {
264 pinctrl-0 = <&du_pins>;
265 pinctrl-names = "default";
266 status = "okay";
267
268 ports {
269 port@1 {
270 lvds_connector: endpoint {
271 };
272 };
273 };
212}; 274};
213 275
214&extal_clk { 276&extal_clk {
@@ -216,9 +278,6 @@
216}; 278};
217 279
218&pfc { 280&pfc {
219 pinctrl-0 = <&du_pins>;
220 pinctrl-names = "default";
221
222 i2c2_pins: i2c2 { 281 i2c2_pins: i2c2 {
223 renesas,groups = "i2c2"; 282 renesas,groups = "i2c2";
224 renesas,function = "i2c2"; 283 renesas,function = "i2c2";
@@ -289,6 +348,16 @@
289 renesas,groups = "vin1_data8", "vin1_clk"; 348 renesas,groups = "vin1_data8", "vin1_clk";
290 renesas,function = "vin1"; 349 renesas,function = "vin1";
291 }; 350 };
351
352 sound_pins: sound {
353 renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
354 renesas,function = "ssi";
355 };
356
357 sound_clk_pins: sound_clk {
358 renesas,groups = "audio_clk_a";
359 renesas,function = "audio_clk";
360 };
292}; 361};
293 362
294&ether { 363&ether {
@@ -414,7 +483,13 @@
414 pinctrl-names = "default"; 483 pinctrl-names = "default";
415 484
416 status = "okay"; 485 status = "okay";
417 clock-frequency = <400000>; 486 clock-frequency = <100000>;
487
488 ak4643: sound-codec@12 {
489 compatible = "asahi-kasei,ak4643";
490 #sound-dai-cells = <0>;
491 reg = <0x12>;
492 };
418 493
419 composite-in@20 { 494 composite-in@20 {
420 compatible = "adi,adv7180"; 495 compatible = "adi,adv7180";
@@ -463,6 +538,17 @@
463 pinctrl-names = "default"; 538 pinctrl-names = "default";
464}; 539};
465 540
541&hsusb {
542 status = "okay";
543 pinctrl-0 = <&usb0_pins>;
544 pinctrl-names = "default";
545 renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>;
546};
547
548&usbphy {
549 status = "okay";
550};
551
466&pcie_bus_clk { 552&pcie_bus_clk {
467 status = "okay"; 553 status = "okay";
468}; 554};
@@ -491,3 +577,23 @@
491 }; 577 };
492 }; 578 };
493}; 579};
580
581&rcar_sound {
582 pinctrl-0 = <&sound_pins &sound_clk_pins>;
583 pinctrl-names = "default";
584
585 #sound-dai-cells = <0>;
586
587 status = "okay";
588
589 rcar_sound,dai {
590 dai0 {
591 playback = <&ssi0 &src2 &dvc0>;
592 capture = <&ssi1 &src3 &dvc1>;
593 };
594 };
595};
596
597&ssi1 {
598 shared-pin;
599};
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index e06c11fa8698..77c0beeb8d7c 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1,7 +1,7 @@
1/* 1/*
2 * Device Tree Source for the r8a7791 SoC 2 * Device Tree Source for the r8a7791 SoC
3 * 3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation 4 * Copyright (C) 2013-2014 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp. 5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc. 6 * Copyright (C) 2014 Cogent Embedded Inc.
7 * 7 *
@@ -301,6 +301,69 @@
301 dma-channels = <15>; 301 dma-channels = <15>;
302 }; 302 };
303 303
304 audma0: dma-controller@ec700000 {
305 compatible = "renesas,rcar-dmac";
306 reg = <0 0xec700000 0 0x10000>;
307 interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH
308 0 320 IRQ_TYPE_LEVEL_HIGH
309 0 321 IRQ_TYPE_LEVEL_HIGH
310 0 322 IRQ_TYPE_LEVEL_HIGH
311 0 323 IRQ_TYPE_LEVEL_HIGH
312 0 324 IRQ_TYPE_LEVEL_HIGH
313 0 325 IRQ_TYPE_LEVEL_HIGH
314 0 326 IRQ_TYPE_LEVEL_HIGH
315 0 327 IRQ_TYPE_LEVEL_HIGH
316 0 328 IRQ_TYPE_LEVEL_HIGH
317 0 329 IRQ_TYPE_LEVEL_HIGH
318 0 330 IRQ_TYPE_LEVEL_HIGH
319 0 331 IRQ_TYPE_LEVEL_HIGH
320 0 332 IRQ_TYPE_LEVEL_HIGH>;
321 interrupt-names = "error",
322 "ch0", "ch1", "ch2", "ch3",
323 "ch4", "ch5", "ch6", "ch7",
324 "ch8", "ch9", "ch10", "ch11",
325 "ch12";
326 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
327 clock-names = "fck";
328 #dma-cells = <1>;
329 dma-channels = <13>;
330 };
331
332 audma1: dma-controller@ec720000 {
333 compatible = "renesas,rcar-dmac";
334 reg = <0 0xec720000 0 0x10000>;
335 interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH
336 0 333 IRQ_TYPE_LEVEL_HIGH
337 0 334 IRQ_TYPE_LEVEL_HIGH
338 0 335 IRQ_TYPE_LEVEL_HIGH
339 0 336 IRQ_TYPE_LEVEL_HIGH
340 0 337 IRQ_TYPE_LEVEL_HIGH
341 0 338 IRQ_TYPE_LEVEL_HIGH
342 0 339 IRQ_TYPE_LEVEL_HIGH
343 0 340 IRQ_TYPE_LEVEL_HIGH
344 0 341 IRQ_TYPE_LEVEL_HIGH
345 0 342 IRQ_TYPE_LEVEL_HIGH
346 0 343 IRQ_TYPE_LEVEL_HIGH
347 0 344 IRQ_TYPE_LEVEL_HIGH
348 0 345 IRQ_TYPE_LEVEL_HIGH>;
349 interrupt-names = "error",
350 "ch0", "ch1", "ch2", "ch3",
351 "ch4", "ch5", "ch6", "ch7",
352 "ch8", "ch9", "ch10", "ch11",
353 "ch12";
354 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
355 clock-names = "fck";
356 #dma-cells = <1>;
357 dma-channels = <13>;
358 };
359
360 audmapp: dma-controller@ec740000 {
361 compatible = "renesas,rcar-audmapp";
362 #dma-cells = <1>;
363
364 reg = <0 0xec740000 0 0x200>;
365 };
366
304 /* The memory map in the User's Manual maps the cores to bus numbers */ 367 /* The memory map in the User's Manual maps the cores to bus numbers */
305 i2c0: i2c@e6508000 { 368 i2c0: i2c@e6508000 {
306 #address-cells = <1>; 369 #address-cells = <1>;
@@ -371,6 +434,8 @@
371 reg = <0 0xe60b0000 0 0x425>; 434 reg = <0 0xe60b0000 0 0x425>;
372 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; 435 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; 436 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
437 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
438 dma-names = "tx", "rx";
374 status = "disabled"; 439 status = "disabled";
375 }; 440 };
376 441
@@ -381,6 +446,8 @@
381 reg = <0 0xe6500000 0 0x425>; 446 reg = <0 0xe6500000 0 0x425>;
382 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; 447 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&mstp3_clks R8A7791_CLK_IIC0>; 448 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
449 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
450 dma-names = "tx", "rx";
384 status = "disabled"; 451 status = "disabled";
385 }; 452 };
386 453
@@ -391,6 +458,8 @@
391 reg = <0 0xe6510000 0 0x425>; 458 reg = <0 0xe6510000 0 0x425>;
392 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; 459 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&mstp3_clks R8A7791_CLK_IIC1>; 460 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
461 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
462 dma-names = "tx", "rx";
394 status = "disabled"; 463 status = "disabled";
395 }; 464 };
396 465
@@ -400,6 +469,17 @@
400 #gpio-range-cells = <3>; 469 #gpio-range-cells = <3>;
401 }; 470 };
402 471
472 mmcif0: mmc@ee200000 {
473 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
474 reg = <0 0xee200000 0 0x80>;
475 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
477 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
478 dma-names = "tx", "rx";
479 reg-io-width = <4>;
480 status = "disabled";
481 };
482
403 sdhi0: sd@ee100000 { 483 sdhi0: sd@ee100000 {
404 compatible = "renesas,sdhi-r8a7791"; 484 compatible = "renesas,sdhi-r8a7791";
405 reg = <0 0xee100000 0 0x200>; 485 reg = <0 0xee100000 0 0x200>;
@@ -613,6 +693,36 @@
613 status = "disabled"; 693 status = "disabled";
614 }; 694 };
615 695
696 hsusb: usb@e6590000 {
697 compatible = "renesas,usbhs-r8a7791";
698 reg = <0 0xe6590000 0 0x100>;
699 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
701 renesas,buswait = <4>;
702 phys = <&usb0 1>;
703 phy-names = "usb";
704 status = "disabled";
705 };
706
707 usbphy: usb-phy@e6590100 {
708 compatible = "renesas,usb-phy-r8a7791";
709 reg = <0 0xe6590100 0 0x100>;
710 #address-cells = <1>;
711 #size-cells = <0>;
712 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
713 clock-names = "usbhs";
714 status = "disabled";
715
716 usb0: usb-channel@0 {
717 reg = <0>;
718 #phy-cells = <1>;
719 };
720 usb2: usb-channel@2 {
721 reg = <2>;
722 #phy-cells = <1>;
723 };
724 };
725
616 vin0: video@e6ef0000 { 726 vin0: video@e6ef0000 {
617 compatible = "renesas,vin-r8a7791"; 727 compatible = "renesas,vin-r8a7791";
618 clocks = <&mstp8_clks R8A7791_CLK_VIN0>; 728 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
@@ -637,6 +747,75 @@
637 status = "disabled"; 747 status = "disabled";
638 }; 748 };
639 749
750 vsp1@fe928000 {
751 compatible = "renesas,vsp1";
752 reg = <0 0xfe928000 0 0x8000>;
753 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
755
756 renesas,has-lut;
757 renesas,has-sru;
758 renesas,#rpf = <5>;
759 renesas,#uds = <3>;
760 renesas,#wpf = <4>;
761 };
762
763 vsp1@fe930000 {
764 compatible = "renesas,vsp1";
765 reg = <0 0xfe930000 0 0x8000>;
766 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
767 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
768
769 renesas,has-lif;
770 renesas,has-lut;
771 renesas,#rpf = <4>;
772 renesas,#uds = <1>;
773 renesas,#wpf = <4>;
774 };
775
776 vsp1@fe938000 {
777 compatible = "renesas,vsp1";
778 reg = <0 0xfe938000 0 0x8000>;
779 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
781
782 renesas,has-lif;
783 renesas,has-lut;
784 renesas,#rpf = <4>;
785 renesas,#uds = <1>;
786 renesas,#wpf = <4>;
787 };
788
789 du: display@feb00000 {
790 compatible = "renesas,du-r8a7791";
791 reg = <0 0xfeb00000 0 0x40000>,
792 <0 0xfeb90000 0 0x1c>;
793 reg-names = "du", "lvds.0";
794 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
795 <0 268 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
797 <&mstp7_clks R8A7791_CLK_DU1>,
798 <&mstp7_clks R8A7791_CLK_LVDS0>;
799 clock-names = "du.0", "du.1", "lvds.0";
800 status = "disabled";
801
802 ports {
803 #address-cells = <1>;
804 #size-cells = <0>;
805
806 port@0 {
807 reg = <0>;
808 du_out_rgb: endpoint {
809 };
810 };
811 port@1 {
812 reg = <1>;
813 du_out_lvds0: endpoint {
814 };
815 };
816 };
817 };
818
640 clocks { 819 clocks {
641 #address-cells = <2>; 820 #address-cells = <2>;
642 #size-cells = <2>; 821 #size-cells = <2>;
@@ -889,17 +1068,23 @@
889 mstp1_clks: mstp1_clks@e6150134 { 1068 mstp1_clks: mstp1_clks@e6150134 {
890 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1069 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
891 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 1070 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
892 clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, 1071 clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
893 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; 1072 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1073 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1074 <&zs_clk>;
894 #clock-cells = <1>; 1075 #clock-cells = <1>;
895 renesas,clock-indices = < 1076 renesas,clock-indices = <
896 R8A7791_CLK_JPU R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 1077 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
897 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 1078 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
898 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S 1079 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1080 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1081 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1082 R8A7791_CLK_VSP1_S
899 >; 1083 >;
900 clock-output-names = 1084 clock-output-names =
901 "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", 1085 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
902 "vsp1-du0", "vsp1-sy"; 1086 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1087 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
903 }; 1088 };
904 mstp2_clks: mstp2_clks@e6150138 { 1089 mstp2_clks: mstp2_clks@e6150138 {
905 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1090 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -923,24 +1108,28 @@
923 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1108 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
924 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 1109 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
925 clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, 1110 clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
926 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; 1111 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1112 <&hp_clk>, <&hp_clk>;
927 #clock-cells = <1>; 1113 #clock-cells = <1>;
928 renesas,clock-indices = < 1114 renesas,clock-indices = <
929 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 1115 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
930 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 1116 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
931 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 1117 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
1118 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
932 >; 1119 >;
933 clock-output-names = 1120 clock-output-names =
934 "tpu0", "sdhi2", "sdhi1", "sdhi0", 1121 "tpu0", "sdhi2", "sdhi1", "sdhi0",
935 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1"; 1122 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1123 "usbdmac0", "usbdmac1";
936 }; 1124 };
937 mstp5_clks: mstp5_clks@e6150144 { 1125 mstp5_clks: mstp5_clks@e6150144 {
938 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1126 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
939 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 1127 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
940 clocks = <&extal_clk>, <&p_clk>; 1128 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
941 #clock-cells = <1>; 1129 #clock-cells = <1>;
942 renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>; 1130 renesas,clock-indices = <R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
943 clock-output-names = "thermal", "pwm"; 1131 R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
1132 clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
944 }; 1133 };
945 mstp7_clks: mstp7_clks@e615014c { 1134 mstp7_clks: mstp7_clks@e615014c {
946 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1135 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1088,6 +1277,16 @@
1088 status = "disabled"; 1277 status = "disabled";
1089 }; 1278 };
1090 1279
1280 xhci: usb@ee000000 {
1281 compatible = "renesas,xhci-r8a7791";
1282 reg = <0 0xee000000 0 0xc00>;
1283 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1284 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
1285 phys = <&usb2 1>;
1286 phy-names = "usb";
1287 status = "disabled";
1288 };
1289
1091 pci0: pci@ee090000 { 1290 pci0: pci@ee090000 {
1092 compatible = "renesas,pci-r8a7791"; 1291 compatible = "renesas,pci-r8a7791";
1093 device_type = "pci"; 1292 device_type = "pci";
@@ -1106,6 +1305,20 @@
1106 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 1305 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1107 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 1306 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1108 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; 1307 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1308
1309 usb@0,1 {
1310 reg = <0x800 0 0 0 0>;
1311 device_type = "pci";
1312 phys = <&usb0 0>;
1313 phy-names = "usb";
1314 };
1315
1316 usb@0,2 {
1317 reg = <0x1000 0 0 0 0>;
1318 device_type = "pci";
1319 phys = <&usb0 0>;
1320 phy-names = "usb";
1321 };
1109 }; 1322 };
1110 1323
1111 pci1: pci@ee0d0000 { 1324 pci1: pci@ee0d0000 {
@@ -1126,6 +1339,20 @@
1126 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 1339 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1127 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 1340 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1128 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; 1341 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1342
1343 usb@0,1 {
1344 reg = <0x800 0 0 0 0>;
1345 device_type = "pci";
1346 phys = <&usb2 0>;
1347 phy-names = "usb";
1348 };
1349
1350 usb@0,2 {
1351 reg = <0x1000 0 0 0 0>;
1352 device_type = "pci";
1353 phys = <&usb2 0>;
1354 phy-names = "usb";
1355 };
1129 }; 1356 };
1130 1357
1131 pciec: pcie@fe000000 { 1358 pciec: pcie@fe000000 {
@@ -1153,7 +1380,7 @@
1153 status = "disabled"; 1380 status = "disabled";
1154 }; 1381 };
1155 1382
1156 rcar_sound: rcar_sound@0xec500000 { 1383 rcar_sound: rcar_sound@ec500000 {
1157 #sound-dai-cells = <1>; 1384 #sound-dai-cells = <1>;
1158 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; 1385 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1159 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1386 reg = <0 0xec500000 0 0x1000>, /* SCU */
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 79d06ef017a0..f2cf7576bf3f 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -20,7 +20,8 @@
20 }; 20 };
21 21
22 chosen { 22 chosen {
23 bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp"; 23 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
24 stdout-path = &scif2;
24 }; 25 };
25 26
26 memory@40000000 { 27 memory@40000000 {
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index d4e8bce1e0b7..19c9de3f2a5a 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -82,6 +82,14 @@
82 status = "disabled"; 82 status = "disabled";
83 }; 83 };
84 84
85 timer {
86 compatible = "arm,armv7-timer";
87 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
88 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
89 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
91 };
92
85 irqc0: interrupt-controller@e61c0000 { 93 irqc0: interrupt-controller@e61c0000 {
86 compatible = "renesas,irqc-r8a7794", "renesas,irqc"; 94 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
87 #interrupt-cells = <2>; 95 #interrupt-cells = <2>;
@@ -453,16 +461,19 @@
453 mstp1_clks: mstp1_clks@e6150134 { 461 mstp1_clks: mstp1_clks@e6150134 {
454 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 462 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
455 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 463 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
456 clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, 464 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
457 <&cp_clk>, 465 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
458 <&zs_clk>, <&zs_clk>, <&zs_clk>; 466 <&zs_clk>, <&zs_clk>;
459 #clock-cells = <1>; 467 #clock-cells = <1>;
460 renesas,clock-indices = < 468 renesas,clock-indices = <
461 R8A7794_CLK_TMU1 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 469 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
462 R8A7794_CLK_CMT0 R8A7794_CLK_TMU0 470 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
471 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
472 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
463 >; 473 >;
464 clock-output-names = 474 clock-output-names =
465 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0"; 475 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
476 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
466 }; 477 };
467 mstp2_clks: mstp2_clks@e6150138 { 478 mstp2_clks: mstp2_clks@e6150138 {
468 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 479 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -509,13 +520,13 @@
509 mstp8_clks: mstp8_clks@e6150990 { 520 mstp8_clks: mstp8_clks@e6150990 {
510 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 521 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
511 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; 522 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
512 clocks = <&p_clk>; 523 clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
513 #clock-cells = <1>; 524 #clock-cells = <1>;
514 renesas,clock-indices = < 525 renesas,clock-indices = <
515 R8A7794_CLK_ETHER 526 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
516 >; 527 >;
517 clock-output-names = 528 clock-output-names =
518 "ether"; 529 "vin1", "vin0", "ether";
519 }; 530 };
520 mstp11_clks: mstp11_clks@e615099c { 531 mstp11_clks: mstp11_clks@e615099c {
521 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 532 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
diff --git a/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi b/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi
new file mode 100644
index 000000000000..65cb50f0c29f
--- /dev/null
+++ b/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi
@@ -0,0 +1,41 @@
1/*
2 * Common file for the AA104XD12 panel connected to Renesas R-Car boards
3 *
4 * Copyright (C) 2014 Renesas Electronics Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/ {
12 panel {
13 compatible = "mitsubishi,aa104xd12", "panel-dpi";
14
15 width-mm = <210>;
16 height-mm = <158>;
17
18 panel-timing {
19 /* 1024x768 @65Hz */
20 clock-frequency = <65000000>;
21 hactive = <1024>;
22 vactive = <768>;
23 hsync-len = <136>;
24 hfront-porch = <20>;
25 hback-porch = <160>;
26 vfront-porch = <3>;
27 vback-porch = <29>;
28 vsync-len = <6>;
29 };
30
31 port {
32 panel_in: endpoint {
33 remote-endpoint = <&lvds_connector>;
34 };
35 };
36 };
37};
38
39&lvds_connector {
40 remote-endpoint = <&panel_in>;
41};
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index d5344510c676..baf21ac6ce7f 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -60,6 +60,10 @@
60 }; 60 };
61}; 61};
62 62
63&cpu0 {
64 cpu0-supply = <&vdd_arm>;
65};
66
63&i2c1 { 67&i2c1 {
64 status = "okay"; 68 status = "okay";
65 clock-frequency = <400000>; 69 clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts
new file mode 100644
index 000000000000..57489ee54022
--- /dev/null
+++ b/arch/arm/boot/dts/rk3066a-marsboard.dts
@@ -0,0 +1,192 @@
1/*
2 * Copyright (c) 2014 Romain Perier <romain.perier@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44#include "rk3066a.dtsi"
45
46/ {
47 model = "MarsBoard RK3066";
48 compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a";
49
50 memory {
51 reg = <0x60000000 0x40000000>;
52 };
53
54 vcc_sd0: sdmmc-regulator {
55 compatible = "regulator-fixed";
56 regulator-name = "sdmmc-supply";
57 regulator-min-microvolt = <3000000>;
58 regulator-max-microvolt = <3000000>;
59 gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
60 startup-delay-us = <100000>;
61 vin-supply = <&vcc_io>;
62 };
63};
64
65&i2c1 {
66 status = "okay";
67 clock-frequency = <400000>;
68
69 tps: tps@2d {
70 reg = <0x2d>;
71
72 interrupt-parent = <&gpio6>;
73 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
74
75 vcc5-supply = <&vcc_io>;
76 vcc6-supply = <&vcc_io>;
77
78 regulators {
79 vcc_rtc: regulator@0 {
80 regulator-name = "vcc_rtc";
81 regulator-always-on;
82 };
83
84 vcc_io: regulator@1 {
85 regulator-name = "vcc_io";
86 regulator-always-on;
87 };
88
89 vdd_arm: regulator@2 {
90 regulator-name = "vdd_arm";
91 regulator-min-microvolt = <600000>;
92 regulator-max-microvolt = <1500000>;
93 regulator-boot-on;
94 regulator-always-on;
95 };
96
97 vcc_ddr: regulator@3 {
98 regulator-name = "vcc_ddr";
99 regulator-min-microvolt = <600000>;
100 regulator-max-microvolt = <1500000>;
101 regulator-boot-on;
102 regulator-always-on;
103 };
104
105 vcc18_cif: regulator@5 {
106 regulator-name = "vcc18_cif";
107 regulator-always-on;
108 };
109
110 vdd_11: regulator@6 {
111 regulator-name = "vdd_11";
112 regulator-always-on;
113 };
114
115 vcc_25: regulator@7 {
116 regulator-name = "vcc_25";
117 regulator-always-on;
118 };
119
120 vcc_18: regulator@8 {
121 regulator-name = "vcc_18";
122 regulator-always-on;
123 };
124
125 vcc25_hdmi: regulator@9 {
126 regulator-name = "vcc25_hdmi";
127 regulator-always-on;
128 };
129
130 vcca_33: regulator@10 {
131 regulator-name = "vcca_33";
132 regulator-always-on;
133 };
134
135 vcc_rmii: regulator@11 {
136 regulator-name = "vcc_rmii";
137 };
138
139 vcc28_cif: regulator@12 {
140 regulator-name = "vcc28_cif";
141 regulator-always-on;
142 };
143 };
144 };
145};
146
147/* must be included after &tps gets defined */
148#include "tps65910.dtsi"
149
150&emac {
151 status = "okay";
152
153 phy = <&phy0>;
154 phy-supply = <&vcc_rmii>;
155
156 pinctrl-names = "default";
157 pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
158
159 phy0: ethernet-phy@0 {
160 reg = <0>;
161 interrupt-parent = <&gpio1>;
162 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
163 };
164};
165
166&pinctrl {
167 lan8720a {
168 phy_int: phy-int {
169 rockchip,pins = <RK_GPIO1 26 RK_FUNC_GPIO &pcfg_pull_none>;
170 };
171 };
172};
173
174&uart0 {
175 status = "okay";
176};
177
178&uart1 {
179 status = "okay";
180};
181
182&uart2 {
183 status = "okay";
184};
185
186&uart3 {
187 status = "okay";
188};
189
190&wdt {
191 status = "okay";
192};
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index ad9c2db59670..41ffd4951ef3 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -26,11 +26,21 @@
26 #size-cells = <0>; 26 #size-cells = <0>;
27 enable-method = "rockchip,rk3066-smp"; 27 enable-method = "rockchip,rk3066-smp";
28 28
29 cpu@0 { 29 cpu0: cpu@0 {
30 device_type = "cpu"; 30 device_type = "cpu";
31 compatible = "arm,cortex-a9"; 31 compatible = "arm,cortex-a9";
32 next-level-cache = <&L2>; 32 next-level-cache = <&L2>;
33 reg = <0x0>; 33 reg = <0x0>;
34 operating-points = <
35 /* kHz uV */
36 1008000 1075000
37 816000 1025000
38 600000 1025000
39 504000 1000000
40 312000 975000
41 >;
42 clock-latency = <40000>;
43 clocks = <&cru ARMCLK>;
34 }; 44 };
35 cpu@1 { 45 cpu@1 {
36 device_type = "cpu"; 46 device_type = "cpu";
@@ -53,6 +63,51 @@
53 }; 63 };
54 }; 64 };
55 65
66 i2s0: i2s@10118000 {
67 compatible = "rockchip,rk3066-i2s";
68 reg = <0x10118000 0x2000>;
69 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
70 #address-cells = <1>;
71 #size-cells = <0>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&i2s0_bus>;
74 dmas = <&dmac1_s 4>, <&dmac1_s 5>;
75 dma-names = "tx", "rx";
76 clock-names = "i2s_hclk", "i2s_clk";
77 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
78 status = "disabled";
79 };
80
81 i2s1: i2s@1011a000 {
82 compatible = "rockchip,rk3066-i2s";
83 reg = <0x1011a000 0x2000>;
84 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
85 #address-cells = <1>;
86 #size-cells = <0>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&i2s1_bus>;
89 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
90 dma-names = "tx", "rx";
91 clock-names = "i2s_hclk", "i2s_clk";
92 clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
93 status = "disabled";
94 };
95
96 i2s2: i2s@1011c000 {
97 compatible = "rockchip,rk3066-i2s";
98 reg = <0x1011c000 0x2000>;
99 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
100 #address-cells = <1>;
101 #size-cells = <0>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&i2s2_bus>;
104 dmas = <&dmac1_s 9>, <&dmac1_s 10>;
105 dma-names = "tx", "rx";
106 clock-names = "i2s_hclk", "i2s_clk";
107 clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
108 status = "disabled";
109 };
110
56 cru: clock-controller@20000000 { 111 cru: clock-controller@20000000 {
57 compatible = "rockchip,rk3066a-cru"; 112 compatible = "rockchip,rk3066a-cru";
58 reg = <0x20000000 0x1000>; 113 reg = <0x20000000 0x1000>;
@@ -179,6 +234,24 @@
179 bias-disable; 234 bias-disable;
180 }; 235 };
181 236
237 emac {
238 emac_xfer: emac-xfer {
239 rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
240 <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
241 <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
242 <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
243 <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
244 <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
245 <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
246 <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
247 };
248
249 emac_mdio: emac-mdio {
250 rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
251 <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
252 };
253 };
254
182 emmc { 255 emmc {
183 emmc_clk: emmc-clk { 256 emmc_clk: emmc-clk {
184 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>; 257 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
@@ -405,6 +478,42 @@
405 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>; 478 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
406 }; 479 };
407 }; 480 };
481
482 i2s0 {
483 i2s0_bus: i2s0-bus {
484 rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
485 <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
486 <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
487 <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
488 <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
489 <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
490 <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
491 <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
492 <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
493 };
494 };
495
496 i2s1 {
497 i2s1_bus: i2s1-bus {
498 rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
499 <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
500 <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
501 <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
502 <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
503 <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
504 };
505 };
506
507 i2s2 {
508 i2s2_bus: i2s2-bus {
509 rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
510 <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
511 <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
512 <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
513 <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
514 <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
515 };
516 };
408 }; 517 };
409}; 518};
410 519
@@ -496,3 +605,7 @@
496&wdt { 605&wdt {
497 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; 606 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
498}; 607};
608
609&emac {
610 compatible = "rockchip,rk3066-emac";
611};
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 15910c9ddbc7..6eb62c053055 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -118,6 +118,10 @@
118 }; 118 };
119}; 119};
120 120
121&cpu0 {
122 cpu0-supply = <&vdd_arm>;
123};
124
121&i2c1 { 125&i2c1 {
122 status = "okay"; 126 status = "okay";
123 clock-frequency = <400000>; 127 clock-frequency = <400000>;
@@ -159,7 +163,7 @@
159 vdd_arm: REG3 { 163 vdd_arm: REG3 {
160 regulator-name = "VDD_ARM"; 164 regulator-name = "VDD_ARM";
161 regulator-min-microvolt = <875000>; 165 regulator-min-microvolt = <875000>;
162 regulator-max-microvolt = <1300000>; 166 regulator-max-microvolt = <1350000>;
163 regulator-always-on; 167 regulator-always-on;
164 }; 168 };
165 169
@@ -239,6 +243,18 @@
239 disable-wp; 243 disable-wp;
240}; 244};
241 245
246&pwm1 {
247 status = "okay";
248};
249
250&pwm2 {
251 status = "okay";
252};
253
254&pwm3 {
255 status = "okay";
256};
257
242&pinctrl { 258&pinctrl {
243 pcfg_output_low: pcfg-output-low { 259 pcfg_output_low: pcfg-output-low {
244 output-low; 260 output-low;
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index ddaada788b45..1d4d79c6688d 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -26,11 +26,24 @@
26 #size-cells = <0>; 26 #size-cells = <0>;
27 enable-method = "rockchip,rk3066-smp"; 27 enable-method = "rockchip,rk3066-smp";
28 28
29 cpu@0 { 29 cpu0: cpu@0 {
30 device_type = "cpu"; 30 device_type = "cpu";
31 compatible = "arm,cortex-a9"; 31 compatible = "arm,cortex-a9";
32 next-level-cache = <&L2>; 32 next-level-cache = <&L2>;
33 reg = <0x0>; 33 reg = <0x0>;
34 operating-points = <
35 /* kHz uV */
36 1608000 1350000
37 1416000 1250000
38 1200000 1150000
39 1008000 1075000
40 816000 975000
41 600000 950000
42 504000 925000
43 312000 875000
44 >;
45 clock-latency = <40000>;
46 clocks = <&cru ARMCLK>;
34 }; 47 };
35 cpu@1 { 48 cpu@1 {
36 device_type = "cpu"; 49 device_type = "cpu";
@@ -65,6 +78,21 @@
65 }; 78 };
66 }; 79 };
67 80
81 i2s0: i2s@1011a000 {
82 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
83 reg = <0x1011a000 0x2000>;
84 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
85 #address-cells = <1>;
86 #size-cells = <0>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&i2s0_bus>;
89 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
90 dma-names = "tx", "rx";
91 clock-names = "i2s_hclk", "i2s_clk";
92 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
93 status = "disabled";
94 };
95
68 cru: clock-controller@20000000 { 96 cru: clock-controller@20000000 {
69 compatible = "rockchip,rk3188-cru"; 97 compatible = "rockchip,rk3188-cru";
70 reg = <0x20000000 0x1000>; 98 reg = <0x20000000 0x1000>;
@@ -83,7 +111,7 @@
83 #size-cells = <1>; 111 #size-cells = <1>;
84 ranges; 112 ranges;
85 113
86 gpio0: gpio0@0x2000a000 { 114 gpio0: gpio0@2000a000 {
87 compatible = "rockchip,rk3188-gpio-bank0"; 115 compatible = "rockchip,rk3188-gpio-bank0";
88 reg = <0x2000a000 0x100>; 116 reg = <0x2000a000 0x100>;
89 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 117 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
@@ -96,7 +124,7 @@
96 #interrupt-cells = <2>; 124 #interrupt-cells = <2>;
97 }; 125 };
98 126
99 gpio1: gpio1@0x2003c000 { 127 gpio1: gpio1@2003c000 {
100 compatible = "rockchip,gpio-bank"; 128 compatible = "rockchip,gpio-bank";
101 reg = <0x2003c000 0x100>; 129 reg = <0x2003c000 0x100>;
102 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 130 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
@@ -395,6 +423,17 @@
395 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>; 423 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
396 }; 424 };
397 }; 425 };
426
427 i2s0 {
428 i2s0_bus: i2s0-bus {
429 rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
430 <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
431 <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
432 <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
433 <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
434 <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
435 };
436 };
398 }; 437 };
399}; 438};
400 439
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index ff522f8e3df4..d8c775e6d5fe 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -17,6 +17,10 @@
17 compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288"; 17 compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
18}; 18};
19 19
20&cpu0 {
21 cpu0-supply = <&vdd_cpu>;
22};
23
20&i2c0 { 24&i2c0 {
21 clock-frequency = <400000>; 25 clock-frequency = <400000>;
22 status = "okay"; 26 status = "okay";
@@ -44,7 +48,7 @@
44 regulator-always-on; 48 regulator-always-on;
45 regulator-boot-on; 49 regulator-boot-on;
46 regulator-min-microvolt = <750000>; 50 regulator-min-microvolt = <750000>;
47 regulator-max-microvolt = <1300000>; 51 regulator-max-microvolt = <1350000>;
48 regulator-name = "vdd_arm"; 52 regulator-name = "vdd_arm";
49 }; 53 };
50 54
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66dbb93b..ebcd2d2eef74 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -46,26 +46,48 @@
46 cpus { 46 cpus {
47 #address-cells = <1>; 47 #address-cells = <1>;
48 #size-cells = <0>; 48 #size-cells = <0>;
49 rockchip,pmu = <&pmu>;
49 50
50 cpu@500 { 51 cpu0: cpu@500 {
51 device_type = "cpu"; 52 device_type = "cpu";
52 compatible = "arm,cortex-a12"; 53 compatible = "arm,cortex-a12";
53 reg = <0x500>; 54 reg = <0x500>;
55 resets = <&cru SRST_CORE0>;
56 operating-points = <
57 /* KHz uV */
58 1608000 1350000
59 1512000 1300000
60 1416000 1200000
61 1200000 1100000
62 1008000 1050000
63 816000 1000000
64 696000 950000
65 600000 900000
66 408000 900000
67 312000 900000
68 216000 900000
69 126000 900000
70 >;
71 clock-latency = <40000>;
72 clocks = <&cru ARMCLK>;
54 }; 73 };
55 cpu@501 { 74 cpu@501 {
56 device_type = "cpu"; 75 device_type = "cpu";
57 compatible = "arm,cortex-a12"; 76 compatible = "arm,cortex-a12";
58 reg = <0x501>; 77 reg = <0x501>;
78 resets = <&cru SRST_CORE1>;
59 }; 79 };
60 cpu@502 { 80 cpu@502 {
61 device_type = "cpu"; 81 device_type = "cpu";
62 compatible = "arm,cortex-a12"; 82 compatible = "arm,cortex-a12";
63 reg = <0x502>; 83 reg = <0x502>;
84 resets = <&cru SRST_CORE2>;
64 }; 85 };
65 cpu@503 { 86 cpu@503 {
66 device_type = "cpu"; 87 device_type = "cpu";
67 compatible = "arm,cortex-a12"; 88 compatible = "arm,cortex-a12";
68 reg = <0x503>; 89 reg = <0x503>;
90 resets = <&cru SRST_CORE3>;
69 }; 91 };
70 }; 92 };
71 93
@@ -177,6 +199,8 @@
177 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 199 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
178 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 200 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
179 clock-names = "spiclk", "apb_pclk"; 201 clock-names = "spiclk", "apb_pclk";
202 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
203 dma-names = "tx", "rx";
180 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 204 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
181 pinctrl-names = "default"; 205 pinctrl-names = "default";
182 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 206 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
@@ -190,6 +214,8 @@
190 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 214 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
191 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 215 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
192 clock-names = "spiclk", "apb_pclk"; 216 clock-names = "spiclk", "apb_pclk";
217 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
218 dma-names = "tx", "rx";
193 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 219 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
194 pinctrl-names = "default"; 220 pinctrl-names = "default";
195 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 221 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
@@ -203,6 +229,8 @@
203 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 229 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
204 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 230 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
205 clock-names = "spiclk", "apb_pclk"; 231 clock-names = "spiclk", "apb_pclk";
232 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
233 dma-names = "tx", "rx";
206 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 234 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
207 pinctrl-names = "default"; 235 pinctrl-names = "default";
208 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 236 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
@@ -439,6 +467,18 @@
439 status = "disabled"; 467 status = "disabled";
440 }; 468 };
441 469
470 bus_intmem@ff700000 {
471 compatible = "mmio-sram";
472 reg = <0xff700000 0x18000>;
473 #address-cells = <1>;
474 #size-cells = <1>;
475 ranges = <0 0xff700000 0x18000>;
476 smp-sram@0 {
477 compatible = "rockchip,rk3066-smp-sram";
478 reg = <0x00 0x10>;
479 };
480 };
481
442 pmu: power-management@ff730000 { 482 pmu: power-management@ff730000 {
443 compatible = "rockchip,rk3288-pmu", "syscon"; 483 compatible = "rockchip,rk3288-pmu", "syscon";
444 reg = <0xff730000 0x100>; 484 reg = <0xff730000 0x100>;
@@ -455,6 +495,16 @@
455 rockchip,grf = <&grf>; 495 rockchip,grf = <&grf>;
456 #clock-cells = <1>; 496 #clock-cells = <1>;
457 #reset-cells = <1>; 497 #reset-cells = <1>;
498 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
499 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
500 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
501 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
502 <&cru PCLK_PERI>;
503 assigned-clock-rates = <594000000>, <400000000>,
504 <500000000>, <300000000>,
505 <150000000>, <75000000>,
506 <300000000>, <150000000>,
507 <75000000>;
458 }; 508 };
459 509
460 grf: syscon@ff770000 { 510 grf: syscon@ff770000 {
@@ -484,6 +534,24 @@
484 status = "disabled"; 534 status = "disabled";
485 }; 535 };
486 536
537 vopb_mmu: iommu@ff930300 {
538 compatible = "rockchip,iommu";
539 reg = <0xff930300 0x100>;
540 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
541 interrupt-names = "vopb_mmu";
542 #iommu-cells = <0>;
543 status = "disabled";
544 };
545
546 vopl_mmu: iommu@ff940300 {
547 compatible = "rockchip,iommu";
548 reg = <0xff940300 0x100>;
549 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
550 interrupt-names = "vopl_mmu";
551 #iommu-cells = <0>;
552 status = "disabled";
553 };
554
487 gic: interrupt-controller@ffc01000 { 555 gic: interrupt-controller@ffc01000 {
488 compatible = "arm,gic-400"; 556 compatible = "arm,gic-400";
489 interrupt-controller; 557 interrupt-controller;
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 499468d42ada..87df6a8955aa 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -29,6 +29,10 @@
29 mshc0 = &emmc; 29 mshc0 = &emmc;
30 mshc1 = &mmc0; 30 mshc1 = &mmc0;
31 mshc2 = &mmc1; 31 mshc2 = &mmc1;
32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
32 spi0 = &spi0; 36 spi0 = &spi0;
33 spi1 = &spi1; 37 spi1 = &spi1;
34 }; 38 };
@@ -367,6 +371,8 @@
367 reg = <0x20070000 0x1000>; 371 reg = <0x20070000 0x1000>;
368 #address-cells = <1>; 372 #address-cells = <1>;
369 #size-cells = <0>; 373 #size-cells = <0>;
374 dmas = <&dmac2 10>, <&dmac2 11>;
375 dma-names = "tx", "rx";
370 status = "disabled"; 376 status = "disabled";
371 }; 377 };
372 378
@@ -378,6 +384,8 @@
378 reg = <0x20074000 0x1000>; 384 reg = <0x20074000 0x1000>;
379 #address-cells = <1>; 385 #address-cells = <1>;
380 #size-cells = <0>; 386 #size-cells = <0>;
387 dmas = <&dmac2 12>, <&dmac2 13>;
388 dma-names = "tx", "rx";
381 status = "disabled"; 389 status = "disabled";
382 }; 390 };
383}; 391};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 30ef97e99dc5..939be1299ca6 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -40,6 +40,7 @@
40 40
41 chosen { 41 chosen {
42 bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw"; 42 bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw";
43 stdout-path = &scifa4;
43 }; 44 };
44 45
45 memory { 46 memory {
@@ -100,19 +101,23 @@
100 compatible = "gpio-leds"; 101 compatible = "gpio-leds";
101 led1 { 102 led1 {
102 gpios = <&pfc 20 GPIO_ACTIVE_LOW>; 103 gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
104 label = "LED1";
103 }; 105 };
104 led2 { 106 led2 {
105 gpios = <&pfc 21 GPIO_ACTIVE_LOW>; 107 gpios = <&pfc 21 GPIO_ACTIVE_LOW>;
108 label = "LED2";
106 }; 109 };
107 led3 { 110 led3 {
108 gpios = <&pfc 22 GPIO_ACTIVE_LOW>; 111 gpios = <&pfc 22 GPIO_ACTIVE_LOW>;
112 label = "LED3";
109 }; 113 };
110 led4 { 114 led4 {
111 gpios = <&pfc 23 GPIO_ACTIVE_LOW>; 115 gpios = <&pfc 23 GPIO_ACTIVE_LOW>;
116 label = "LED4";
112 }; 117 };
113 }; 118 };
114 119
115 gpio-keys { 120 keyboard {
116 compatible = "gpio-keys"; 121 compatible = "gpio-keys";
117 122
118 back-key { 123 back-key {
@@ -250,7 +255,7 @@
250 }; 255 };
251 }; 256 };
252 257
253 ak4648: ak4648@0x12 { 258 ak4648: ak4648@12 {
254 #sound-dai-cells = <0>; 259 #sound-dai-cells = <0>;
255 compatible = "asahi-kasei,ak4648"; 260 compatible = "asahi-kasei,ak4648";
256 reg = <0x12>; 261 reg = <0x12>;
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 030a5920312f..d8def5a529da 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -138,7 +138,7 @@
138 i2c0: i2c@e6820000 { 138 i2c0: i2c@e6820000 {
139 #address-cells = <1>; 139 #address-cells = <1>;
140 #size-cells = <0>; 140 #size-cells = <0>;
141 compatible = "renesas,rmobile-iic"; 141 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
142 reg = <0xe6820000 0x425>; 142 reg = <0xe6820000 0x425>;
143 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH 143 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
144 0 168 IRQ_TYPE_LEVEL_HIGH 144 0 168 IRQ_TYPE_LEVEL_HIGH
@@ -150,7 +150,7 @@
150 i2c1: i2c@e6822000 { 150 i2c1: i2c@e6822000 {
151 #address-cells = <1>; 151 #address-cells = <1>;
152 #size-cells = <0>; 152 #size-cells = <0>;
153 compatible = "renesas,rmobile-iic"; 153 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
154 reg = <0xe6822000 0x425>; 154 reg = <0xe6822000 0x425>;
155 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH 155 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
156 0 52 IRQ_TYPE_LEVEL_HIGH 156 0 52 IRQ_TYPE_LEVEL_HIGH
@@ -162,7 +162,7 @@
162 i2c2: i2c@e6824000 { 162 i2c2: i2c@e6824000 {
163 #address-cells = <1>; 163 #address-cells = <1>;
164 #size-cells = <0>; 164 #size-cells = <0>;
165 compatible = "renesas,rmobile-iic"; 165 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
166 reg = <0xe6824000 0x425>; 166 reg = <0xe6824000 0x425>;
167 interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH 167 interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
168 0 172 IRQ_TYPE_LEVEL_HIGH 168 0 172 IRQ_TYPE_LEVEL_HIGH
@@ -174,7 +174,7 @@
174 i2c3: i2c@e6826000 { 174 i2c3: i2c@e6826000 {
175 #address-cells = <1>; 175 #address-cells = <1>;
176 #size-cells = <0>; 176 #size-cells = <0>;
177 compatible = "renesas,rmobile-iic"; 177 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
178 reg = <0xe6826000 0x425>; 178 reg = <0xe6826000 0x425>;
179 interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH 179 interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
180 0 184 IRQ_TYPE_LEVEL_HIGH 180 0 184 IRQ_TYPE_LEVEL_HIGH
@@ -186,7 +186,7 @@
186 i2c4: i2c@e6828000 { 186 i2c4: i2c@e6828000 {
187 #address-cells = <1>; 187 #address-cells = <1>;
188 #size-cells = <0>; 188 #size-cells = <0>;
189 compatible = "renesas,rmobile-iic"; 189 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
190 reg = <0xe6828000 0x425>; 190 reg = <0xe6828000 0x425>;
191 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH 191 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
192 0 188 IRQ_TYPE_LEVEL_HIGH 192 0 188 IRQ_TYPE_LEVEL_HIGH
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 45fce2cf6fed..252c3d1bda50 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -547,7 +547,7 @@
547 status = "disabled"; 547 status = "disabled";
548 }; 548 };
549 549
550 gpio@ff708000 { 550 gpio0: gpio@ff708000 {
551 #address-cells = <1>; 551 #address-cells = <1>;
552 #size-cells = <0>; 552 #size-cells = <0>;
553 compatible = "snps,dw-apb-gpio"; 553 compatible = "snps,dw-apb-gpio";
@@ -555,7 +555,7 @@
555 clocks = <&per_base_clk>; 555 clocks = <&per_base_clk>;
556 status = "disabled"; 556 status = "disabled";
557 557
558 gpio0: gpio-controller@0 { 558 porta: gpio-controller@0 {
559 compatible = "snps,dw-apb-gpio-port"; 559 compatible = "snps,dw-apb-gpio-port";
560 gpio-controller; 560 gpio-controller;
561 #gpio-cells = <2>; 561 #gpio-cells = <2>;
@@ -567,7 +567,7 @@
567 }; 567 };
568 }; 568 };
569 569
570 gpio@ff709000 { 570 gpio1: gpio@ff709000 {
571 #address-cells = <1>; 571 #address-cells = <1>;
572 #size-cells = <0>; 572 #size-cells = <0>;
573 compatible = "snps,dw-apb-gpio"; 573 compatible = "snps,dw-apb-gpio";
@@ -575,7 +575,7 @@
575 clocks = <&per_base_clk>; 575 clocks = <&per_base_clk>;
576 status = "disabled"; 576 status = "disabled";
577 577
578 gpio1: gpio-controller@0 { 578 portb: gpio-controller@0 {
579 compatible = "snps,dw-apb-gpio-port"; 579 compatible = "snps,dw-apb-gpio-port";
580 gpio-controller; 580 gpio-controller;
581 #gpio-cells = <2>; 581 #gpio-cells = <2>;
@@ -587,7 +587,7 @@
587 }; 587 };
588 }; 588 };
589 589
590 gpio@ff70a000 { 590 gpio2: gpio@ff70a000 {
591 #address-cells = <1>; 591 #address-cells = <1>;
592 #size-cells = <0>; 592 #size-cells = <0>;
593 compatible = "snps,dw-apb-gpio"; 593 compatible = "snps,dw-apb-gpio";
@@ -595,7 +595,7 @@
595 clocks = <&per_base_clk>; 595 clocks = <&per_base_clk>;
596 status = "disabled"; 596 status = "disabled";
597 597
598 gpio2: gpio-controller@0 { 598 portc: gpio-controller@0 {
599 compatible = "snps,dw-apb-gpio-port"; 599 compatible = "snps,dw-apb-gpio-port";
600 gpio-controller; 600 gpio-controller;
601 #gpio-cells = <2>; 601 #gpio-cells = <2>;
@@ -639,6 +639,33 @@
639 clock-names = "biu", "ciu"; 639 clock-names = "biu", "ciu";
640 }; 640 };
641 641
642 ocram: sram@ffff0000 {
643 compatible = "mmio-sram";
644 reg = <0xffff0000 0x10000>;
645 };
646
647 spi0: spi@fff00000 {
648 compatible = "snps,dw-apb-ssi";
649 #address-cells = <1>;
650 #size-cells = <0>;
651 reg = <0xfff00000 0x1000>;
652 interrupts = <0 154 4>;
653 num-cs = <4>;
654 clocks = <&spi_m_clk>;
655 status = "disabled";
656 };
657
658 spi1: spi@fff01000 {
659 compatible = "snps,dw-apb-ssi";
660 #address-cells = <1>;
661 #size-cells = <0>;
662 reg = <0xfff01000 0x1000>;
663 interrupts = <0 156 4>;
664 num-cs = <4>;
665 clocks = <&spi_m_clk>;
666 status = "disabled";
667 };
668
642 /* Local timer */ 669 /* Local timer */
643 timer@fffec600 { 670 timer@fffec600 {
644 compatible = "arm,cortex-a9-twd-timer"; 671 compatible = "arm,cortex-a9-twd-timer";
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
new file mode 100644
index 000000000000..8a05c47fd57f
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -0,0 +1,374 @@
1/*
2 * Copyright Altera Corporation (C) 2014. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "skeleton.dtsi"
18#include <dt-bindings/interrupt-controller/arm-gic.h>
19
20/ {
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 aliases {
25 ethernet0 = &gmac0;
26 ethernet1 = &gmac1;
27 ethernet2 = &gmac2;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 timer0 = &timer0;
31 timer1 = &timer1;
32 timer2 = &timer2;
33 timer3 = &timer3;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu@0 {
41 compatible = "arm,cortex-a9";
42 device_type = "cpu";
43 reg = <0>;
44 next-level-cache = <&L2>;
45 };
46 cpu@1 {
47 compatible = "arm,cortex-a9";
48 device_type = "cpu";
49 reg = <1>;
50 next-level-cache = <&L2>;
51 };
52 };
53
54 intc: intc@ffffd000 {
55 compatible = "arm,cortex-a9-gic";
56 #interrupt-cells = <3>;
57 interrupt-controller;
58 reg = <0xffffd000 0x1000>,
59 <0xffffc100 0x100>;
60 };
61
62 soc {
63 #address-cells = <1>;
64 #size-cells = <1>;
65 compatible = "simple-bus";
66 device_type = "soc";
67 interrupt-parent = <&intc>;
68 ranges;
69
70 amba {
71 compatible = "arm,amba-bus";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 ranges;
75
76 pdma: pdma@ffda1000 {
77 compatible = "arm,pl330", "arm,primecell";
78 reg = <0xffda1000 0x1000>;
79 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
80 <0 84 IRQ_TYPE_LEVEL_HIGH>,
81 <0 85 IRQ_TYPE_LEVEL_HIGH>,
82 <0 86 IRQ_TYPE_LEVEL_HIGH>,
83 <0 87 IRQ_TYPE_LEVEL_HIGH>,
84 <0 88 IRQ_TYPE_LEVEL_HIGH>,
85 <0 89 IRQ_TYPE_LEVEL_HIGH>,
86 <0 90 IRQ_TYPE_LEVEL_HIGH>;
87 #dma-cells = <1>;
88 #dma-channels = <8>;
89 #dma-requests = <32>;
90 };
91 };
92
93 clkmgr@ffd04000 {
94 compatible = "altr,clk-mgr";
95 reg = <0xffd04000 0x1000>;
96
97 clocks {
98 #address-cells = <1>;
99 #size-cells = <0>;
100
101 osc1: osc1 {
102 #clock-cells = <0>;
103 compatible = "fixed-clock";
104 };
105
106 main_pll: main_pll {
107 #address-cells = <1>;
108 #size-cells = <0>;
109 #clock-cells = <0>;
110 compatible = "altr,socfpga-pll-clock";
111 clocks = <&osc1>;
112 };
113
114 periph_pll: periph_pll {
115 #address-cells = <1>;
116 #size-cells = <0>;
117 #clock-cells = <0>;
118 compatible = "altr,socfpga-pll-clock";
119 clocks = <&osc1>;
120 };
121 };
122 };
123
124 gmac0: ethernet@ff800000 {
125 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
126 reg = <0xff800000 0x2000>;
127 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
128 interrupt-names = "macirq";
129 /* Filled in by bootloader */
130 mac-address = [00 00 00 00 00 00];
131 status = "disabled";
132 };
133
134 gmac1: ethernet@ff802000 {
135 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
136 reg = <0xff802000 0x2000>;
137 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
138 interrupt-names = "macirq";
139 /* Filled in by bootloader */
140 mac-address = [00 00 00 00 00 00];
141 status = "disabled";
142 };
143
144 gmac2: ethernet@ff804000 {
145 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
146 reg = <0xff804000 0x2000>;
147 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
148 interrupt-names = "macirq";
149 /* Filled in by bootloader */
150 mac-address = [00 00 00 00 00 00];
151 status = "disabled";
152 };
153
154 gpio0: gpio@ffc02900 {
155 #address-cells = <1>;
156 #size-cells = <0>;
157 compatible = "snps,dw-apb-gpio";
158 reg = <0xffc02900 0x100>;
159 status = "disabled";
160
161 porta: gpio-controller@0 {
162 compatible = "snps,dw-apb-gpio-port";
163 gpio-controller;
164 #gpio-cells = <2>;
165 snps,nr-gpios = <29>;
166 reg = <0>;
167 interrupt-controller;
168 #interrupt-cells = <2>;
169 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
170 };
171 };
172
173 gpio1: gpio@ffc02a00 {
174 #address-cells = <1>;
175 #size-cells = <0>;
176 compatible = "snps,dw-apb-gpio";
177 reg = <0xffc02a00 0x100>;
178 status = "disabled";
179
180 portb: gpio-controller@0 {
181 compatible = "snps,dw-apb-gpio-port";
182 gpio-controller;
183 #gpio-cells = <2>;
184 snps,nr-gpios = <29>;
185 reg = <0>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
188 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
189 };
190 };
191
192 gpio2: gpio@ffc02b00 {
193 #address-cells = <1>;
194 #size-cells = <0>;
195 compatible = "snps,dw-apb-gpio";
196 reg = <0xffc02b00 0x100>;
197 status = "disabled";
198
199 portc: gpio-controller@0 {
200 compatible = "snps,dw-apb-gpio-port";
201 gpio-controller;
202 #gpio-cells = <2>;
203 snps,nr-gpios = <27>;
204 reg = <0>;
205 interrupt-controller;
206 #interrupt-cells = <2>;
207 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
208 };
209 };
210
211 i2c0: i2c@ffc02200 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "snps,designware-i2c";
215 reg = <0xffc02200 0x100>;
216 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
217 status = "disabled";
218 };
219
220 i2c1: i2c@ffc02300 {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "snps,designware-i2c";
224 reg = <0xffc02300 0x100>;
225 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
226 status = "disabled";
227 };
228
229 i2c2: i2c@ffc02400 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "snps,designware-i2c";
233 reg = <0xffc02400 0x100>;
234 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
235 status = "disabled";
236 };
237
238 i2c3: i2c@ffc02500 {
239 #address-cells = <1>;
240 #size-cells = <0>;
241 compatible = "snps,designware-i2c";
242 reg = <0xffc02500 0x100>;
243 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
244 status = "disabled";
245 };
246
247 i2c4: i2c@ffc02600 {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 compatible = "snps,designware-i2c";
251 reg = <0xffc02600 0x100>;
252 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
253 status = "disabled";
254 };
255
256 L2: l2-cache@fffff000 {
257 compatible = "arm,pl310-cache";
258 reg = <0xfffff000 0x1000>;
259 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
260 cache-unified;
261 cache-level = <2>;
262 };
263
264 mmc: dwmmc0@ff808000 {
265 #address-cells = <1>;
266 #size-cells = <0>;
267 compatible = "altr,socfpga-dw-mshc";
268 reg = <0xff808000 0x1000>;
269 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
270 fifo-depth = <0x400>;
271 };
272
273 ocram: sram@ffe00000 {
274 compatible = "mmio-sram";
275 reg = <0xffe00000 0x40000>;
276 };
277
278 rst: rstmgr@ffd05000 {
279 #reset-cells = <1>;
280 compatible = "altr,rst-mgr";
281 reg = <0xffd05000 0x100>;
282 };
283
284 sysmgr: sysmgr@ffd06000 {
285 compatible = "altr,sys-mgr", "syscon";
286 reg = <0xffd06000 0x300>;
287 };
288
289 /* Local timer */
290 timer@ffffc600 {
291 compatible = "arm,cortex-a9-twd-timer";
292 reg = <0xffffc600 0x100>;
293 interrupts = <1 13 0xf04>;
294 };
295
296 timer0: timer0@ffc02700 {
297 compatible = "snps,dw-apb-timer";
298 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
299 reg = <0xffc02700 0x100>;
300 };
301
302 timer1: timer1@ffc02800 {
303 compatible = "snps,dw-apb-timer";
304 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
305 reg = <0xffc02800 0x100>;
306 };
307
308 timer2: timer2@ffd00000 {
309 compatible = "snps,dw-apb-timer";
310 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
311 reg = <0xffd00000 0x100>;
312 };
313
314 timer3: timer3@ffd00100 {
315 compatible = "snps,dw-apb-timer";
316 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
317 reg = <0xffd01000 0x100>;
318 };
319
320 uart0: serial0@ffc02000 {
321 compatible = "snps,dw-apb-uart";
322 reg = <0xffc02000 0x100>;
323 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
324 reg-shift = <2>;
325 reg-io-width = <4>;
326 };
327
328 uart1: serial1@ffc02100 {
329 compatible = "snps,dw-apb-uart";
330 reg = <0xffc02100 0x100>;
331 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
332 reg-shift = <2>;
333 reg-io-width = <4>;
334 };
335
336 usbphy0: usbphy@0 {
337 #phy-cells = <0>;
338 compatible = "usb-nop-xceiv";
339 status = "okay";
340 };
341
342 usb0: usb@ffb00000 {
343 compatible = "snps,dwc2";
344 reg = <0xffb00000 0xffff>;
345 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
346 phys = <&usbphy0>;
347 phy-names = "usb2-phy";
348 status = "disabled";
349 };
350
351 usb1: usb@ffb40000 {
352 compatible = "snps,dwc2";
353 reg = <0xffb40000 0xffff>;
354 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
355 phys = <&usbphy0>;
356 phy-names = "usb2-phy";
357 status = "disabled";
358 };
359
360 watchdog0: watchdog@ffd00200 {
361 compatible = "snps,dw-wdt";
362 reg = <0xffd00200 0x100>;
363 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
364 status = "disabled";
365 };
366
367 watchdog1: watchdog@ffd00300 {
368 compatible = "snps,dw-wdt";
369 reg = <0xffd00300 0x100>;
370 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
371 status = "disabled";
372 };
373 };
374};
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dts b/arch/arm/boot/dts/socfpga_arria10_socdk.dts
new file mode 100755
index 000000000000..3015ce8d3057
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dts
@@ -0,0 +1,48 @@
1/*
2 * Copyright (C) 2014 Altera Corporation <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/dts-v1/;
19#include "socfpga_arria10.dtsi"
20
21/ {
22 model = "Altera SOCFPGA Arria 10";
23 compatible = "altr,socfpga-arria10", "altr,socfpga";
24
25 chosen {
26 bootargs = "console=ttyS0,115200 rootwait";
27 };
28
29 memory {
30 name = "memory";
31 device_type = "memory";
32 reg = <0x0 0x40000000>; /* 1GB */
33 };
34
35 soc {
36 clkmgr@ffd04000 {
37 clocks {
38 osc1 {
39 clock-frequency = <25000000>;
40 };
41 };
42 };
43
44 serial0@ffc02000 {
45 status = "okay";
46 };
47 };
48};
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 03e8268ae219..1907cc600452 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -29,7 +29,7 @@
29 }; 29 };
30 }; 30 };
31 31
32 dwmmc0@ff704000 { 32 mmc0: dwmmc0@ff704000 {
33 num-slots = <1>; 33 num-slots = <1>;
34 broken-cd; 34 broken-cd;
35 bus-width = <4>; 35 bus-width = <4>;
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index 27d551c384d0..ccaf41742fc3 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -37,6 +37,13 @@
37 */ 37 */
38 ethernet0 = &gmac1; 38 ethernet0 = &gmac1;
39 }; 39 };
40
41 regulator_3_3v: 3-3-v-regulator {
42 compatible = "regulator-fixed";
43 regulator-name = "3.3V";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 };
40}; 47};
41 48
42&gmac1 { 49&gmac1 {
@@ -68,6 +75,11 @@
68 }; 75 };
69}; 76};
70 77
78&mmc0 {
79 vmmc-supply = <&regulator_3_3v>;
80 vqmmc-supply = <&regulator_3_3v>;
81};
82
71&usb1 { 83&usb1 {
72 status = "okay"; 84 status = "okay";
73}; 85};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index 28c05e7a31c9..06db951e06f8 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -49,3 +49,7 @@
49 }; 49 };
50 }; 50 };
51}; 51};
52
53&watchdog0 {
54 status = "okay";
55};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index d7296a5f750c..258865da8f6a 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -37,6 +37,13 @@
37 */ 37 */
38 ethernet0 = &gmac1; 38 ethernet0 = &gmac1;
39 }; 39 };
40
41 regulator_3_3v: 3-3-v-regulator {
42 compatible = "regulator-fixed";
43 regulator-name = "3.3V";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 };
40}; 47};
41 48
42&gmac1 { 49&gmac1 {
@@ -53,6 +60,10 @@
53 rxc-skew-ps = <2000>; 60 rxc-skew-ps = <2000>;
54}; 61};
55 62
63&gpio1 {
64 status = "okay";
65};
66
56&i2c0 { 67&i2c0 {
57 status = "okay"; 68 status = "okay";
58 69
@@ -69,7 +80,9 @@
69}; 80};
70 81
71&mmc0 { 82&mmc0 {
72 cd-gpios = <&gpio1 18 0>; 83 cd-gpios = <&portb 18 0>;
84 vmmc-supply = <&regulator_3_3v>;
85 vqmmc-supply = <&regulator_3_3v>;
73}; 86};
74 87
75&usb1 { 88&usb1 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
index d26f155f5fd9..16ea6f5f2ab8 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -37,6 +37,13 @@
37 */ 37 */
38 ethernet0 = &gmac1; 38 ethernet0 = &gmac1;
39 }; 39 };
40
41 regulator_3_3v: vcc3p3-regulator {
42 compatible = "regulator-fixed";
43 regulator-name = "VCC3P3";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 };
40}; 47};
41 48
42&gmac1 { 49&gmac1 {
@@ -53,6 +60,11 @@
53 rxc-skew-ps = <2000>; 60 rxc-skew-ps = <2000>;
54}; 61};
55 62
63&mmc0 {
64 vmmc-supply = <&regulator_3_3v>;
65 vqmmc-supply = <&regulator_3_3v>;
66};
67
56&usb1 { 68&usb1 {
57 status = "okay"; 69 status = "okay";
58}; 70};
diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
new file mode 100644
index 000000000000..a8c00ee7522a
--- /dev/null
+++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
@@ -0,0 +1,151 @@
1/*
2 * Device Tree for the ST-Ericsson Nomadik S8815 board
3 * Produced by Calao Systems
4 */
5
6/dts-v1/;
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/gpio/gpio.h>
9#include "ste-nomadik-stn8815.dtsi"
10
11/ {
12 model = "Nomadik STN8815NHK";
13 compatible = "st,nomadik-nhk-15";
14
15 chosen {
16 bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk";
17 };
18
19 aliases {
20 stmpe-i2c0 = &stmpe0;
21 stmpe-i2c1 = &stmpe1;
22 };
23
24 pinctrl {
25 stmpe2401_1 {
26 stmpe2401_1_nhk_mode: stmpe2401_1_nhk {
27 nhk_cfg1 {
28 ste,pins = "GPIO76_B20"; // IRQ line
29 ste,input = <0>;
30 };
31 nhk_cfg2 {
32 ste,pins = "GPIO77_B8"; // reset line
33 ste,output = <1>;
34 };
35 };
36 };
37 stmpe2401_2 {
38 stmpe2401_2_nhk_mode: stmpe2401_2_nhk {
39 nhk_cfg1 {
40 ste,pins = "GPIO78_A8"; // IRQ line
41 ste,input = <0>;
42 };
43 nhk_cfg2 {
44 ste,pins = "GPIO79_C9"; // reset line
45 ste,output = <1>;
46 };
47 };
48 };
49 };
50
51 src@101e0000 {
52 /* These chrystal outputs are not used on this board */
53 disable-sxtalo;
54 disable-mxtalo;
55 };
56
57 /* This is where the interrupt is routed on the NHK-15 debug board */
58 external-bus@34000000 {
59 compatible = "simple-bus";
60 reg = <0x34000000 0x1000000>;
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges = <0 0x34000000 0x1000000>;
64 ethernet@300 {
65 compatible = "smsc,lan91c111";
66 reg = <0x300 0x0fd00>;
67 reg-io-width = <2>;
68 reset-gpios = <&stmpe_gpio44 10 GPIO_ACTIVE_HIGH>;
69 interrupt-parent = <&stmpe_gpio44>;
70 interrupts = <11 IRQ_TYPE_EDGE_RISING>;
71 };
72 };
73
74 i2c0 {
75 stmpe0: stmpe2401@43 {
76 compatible = "st,stmpe2401";
77 reg = <0x43>;
78 reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; // GPIO77
79 interrupts = <12 IRQ_TYPE_EDGE_FALLING>; // GPIO76
80 interrupt-parent = <&gpio2>;
81 interrupt-controller;
82 wakeup-source;
83 pinctrl-names = "default";
84 pinctrl-0 = <&stmpe2401_1_nhk_mode>;
85 stmpe_gpio43: stmpe_gpio {
86 compatible = "st,stmpe-gpio";
87 gpio-controller;
88 #gpio-cells = <2>;
89 interrupt-controller;
90 #interrupt-cells = <2>;
91 /* Some pins in alternate functions */
92 st,norequest-mask = <0xf0f002>;
93 };
94 stmpe_keypad {
95 compatible = "st,stmpe-keypad";
96 debounce-interval = <64>;
97 st,scan-count = <8>;
98 st,no-autorepeat;
99 keypad,num-rows = <8>;
100 keypad,num-columns = <8>;
101 linux,keymap = <0x00020072 // Vol down
102 0x00030073 // Vol up
103 0x0100009e // Back
104 0x010100e3 // TV out
105 0x01020098 // Lock
106 0x0103013b // Start
107 0x020000a3 // Next
108 0x020100a4 // Play
109 0x020200a5 // Prev
110 0x02030160 // OK
111 0x03000069 // Left
112 0x0301006a // Right
113 0x03020067 // Up
114 0x0303006c>; // Down
115 };
116 };
117 stmpe1: stmpe2401@44 {
118 compatible = "st,stmpe2401";
119 reg = <0x44>;
120 reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; // GPIO79
121 interrupts = <14 IRQ_TYPE_EDGE_FALLING>; // GPIO78
122 interrupt-parent = <&gpio2>;
123 interrupt-controller;
124 wakeup-source;
125 pinctrl-names = "default";
126 pinctrl-0 = <&stmpe2401_2_nhk_mode>;
127 stmpe_gpio44: stmpe_gpio {
128 compatible = "st,stmpe-gpio";
129 gpio-controller;
130 #gpio-cells = <2>;
131 interrupt-controller;
132 #interrupt-cells = <2>;
133 };
134 };
135 };
136
137 amba {
138 mmcsd: sdi@101f6000 {
139 cd-gpios = <&stmpe_gpio44 7 GPIO_ACTIVE_LOW>;
140 wp-gpios = <&stmpe_gpio44 18 GPIO_ACTIVE_HIGH>;
141 };
142 };
143
144 /* Custom board node with GPIO pins to active etc */
145 usb-s8815 {
146 /* This will turn off SATA so that MMC/SD can thrive */
147 mmcsd-gpio {
148 gpios = <&stmpe_gpio44 2 0x1>;
149 };
150 };
151};
diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts
index 90d8b6c7a205..e411ff7769fe 100644
--- a/arch/arm/boot/dts/ste-nomadik-s8815.dts
+++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts
@@ -4,6 +4,7 @@
4 */ 4 */
5 5
6/dts-v1/; 6/dts-v1/;
7#include <dt-bindings/interrupt-controller/irq.h>
7#include "ste-nomadik-stn8815.dtsi" 8#include "ste-nomadik-stn8815.dtsi"
8 9
9/ { 10/ {
@@ -14,14 +15,6 @@
14 bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk"; 15 bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk";
15 }; 16 };
16 17
17 /* This is where the interrupt is routed on the S8815 board */
18 external-bus@34000000 {
19 ethernet@300 {
20 interrupt-parent = <&gpio3>;
21 interrupts = <8 0x1>;
22 };
23 };
24
25 src@101e0000 { 18 src@101e0000 {
26 /* These chrystal drivers are not used on this board */ 19 /* These chrystal drivers are not used on this board */
27 disable-sxtalo; 20 disable-sxtalo;
@@ -47,6 +40,14 @@
47 }; 40 };
48 }; 41 };
49 }; 42 };
43 gpioi2c {
44 gpioi2c_default_mode: gpioi2c_default {
45 gpioi2c_default_cfg {
46 ste,pins = "GPIO73_C21", "GPIO74_C20";
47 ste,input = <0>;
48 };
49 };
50 };
50 user-led { 51 user-led {
51 user_led_default_mode: user_led_default { 52 user_led_default_mode: user_led_default {
52 user_led_default_cfg { 53 user_led_default_cfg {
@@ -65,6 +66,45 @@
65 }; 66 };
66 }; 67 };
67 68
69 /* Ethernet */
70 external-bus@34000000 {
71 compatible = "simple-bus";
72 reg = <0x34000000 0x1000000>;
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges = <0 0x34000000 0x1000000>;
76 ethernet@300 {
77 compatible = "smsc,lan91c111";
78 reg = <0x300 0x0fd00>;
79 interrupt-parent = <&gpio3>;
80 interrupts = <8 IRQ_TYPE_EDGE_RISING>;
81 };
82 };
83
84 /* GPIO I2C connected to the USB portions of the STw4811 only */
85 gpio-i2c {
86 compatible = "i2c-gpio";
87 gpios = <&gpio2 10 0>, /* sda */
88 <&gpio2 9 0>; /* scl */
89 #address-cells = <1>;
90 #size-cells = <0>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&gpioi2c_default_mode>;
93
94 stw4811@2d {
95 compatible = "st,stw4811-usb";
96 reg = <0x2d>;
97 };
98 };
99
100
101 /* Configure card detect for the uSD slot */
102 amba {
103 mmcsd: sdi@101f6000 {
104 cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
105 };
106 };
107
68 /* Custom board node with GPIO pins to active etc */ 108 /* Custom board node with GPIO pins to active etc */
69 usb-s8815 { 109 usb-s8815 {
70 /* This will bias the MMC/SD card detect line */ 110 /* This will bias the MMC/SD card detect line */
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index dbcf521b017f..f435ff20aefe 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -117,7 +117,7 @@
117 mmcsd_default_mux: mmcsd_mux { 117 mmcsd_default_mux: mmcsd_mux {
118 mmcsd_default_mux { 118 mmcsd_default_mux {
119 ste,function = "mmcsd"; 119 ste,function = "mmcsd";
120 ste,pins = "mmcsd_a_1"; 120 ste,pins = "mmcsd_a_1", "mmcsd_b_1";
121 }; 121 };
122 }; 122 };
123 mmcsd_default_mode: mmcsd_default { 123 mmcsd_default_mode: mmcsd_default {
@@ -127,9 +127,9 @@
127 ste,output = <0>; 127 ste,output = <0>;
128 }; 128 };
129 mmcsd_default_cfg2 { 129 mmcsd_default_cfg2 {
130 /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */ 130 /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 */
131 ste,pins = "GPIO10_C11", "GPIO15_A12", 131 ste,pins = "GPIO10_C11", "GPIO15_A12",
132 "GPIO16_C13"; 132 "GPIO16_C13", "GPIO23_D15";
133 ste,output = <1>; 133 ste,output = <1>;
134 }; 134 };
135 mmcsd_default_cfg3 { 135 mmcsd_default_cfg3 {
@@ -169,21 +169,11 @@
169 }; 169 };
170 }; 170 };
171 }; 171 };
172 i2c2 {
173 i2c2_default_mode: i2c2_default {
174 i2c2_default_cfg {
175 ste,pins = "GPIO73_C21", "GPIO74_C20";
176 ste,input = <0>;
177 };
178 };
179 };
180 }; 172 };
181 173
182 src: src@101e0000 { 174 src: src@101e0000 {
183 compatible = "stericsson,nomadik-src"; 175 compatible = "stericsson,nomadik-src";
184 reg = <0x101e0000 0x1000>; 176 reg = <0x101e0000 0x1000>;
185 disable-sxtalo;
186 disable-mxtalo;
187 177
188 /* 178 /*
189 * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz 179 * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz
@@ -683,18 +673,6 @@
683 }; 673 };
684 }; 674 };
685 675
686 external-bus@34000000 {
687 compatible = "simple-bus";
688 reg = <0x34000000 0x1000000>;
689 #address-cells = <1>;
690 #size-cells = <1>;
691 ranges = <0 0x34000000 0x1000000>;
692 ethernet@300 {
693 compatible = "smsc,lan91c111";
694 reg = <0x300 0x0fd00>;
695 };
696 };
697
698 /* I2C0 connected to the STw4811 power management chip */ 676 /* I2C0 connected to the STw4811 power management chip */
699 i2c0 { 677 i2c0 {
700 compatible = "st,nomadik-i2c", "arm,primecell"; 678 compatible = "st,nomadik-i2c", "arm,primecell";
@@ -749,22 +727,6 @@
749 }; 727 };
750 }; 728 };
751 729
752 /* I2C2 connected to the USB portions of the STw4811 only */
753 i2c2 {
754 compatible = "i2c-gpio";
755 gpios = <&gpio2 10 0>, /* sda */
756 <&gpio2 9 0>; /* scl */
757 #address-cells = <1>;
758 #size-cells = <0>;
759 pinctrl-names = "default";
760 pinctrl-0 = <&i2c2_default_mode>;
761
762 stw4811@2d {
763 compatible = "st,stw4811-usb";
764 reg = <0x2d>;
765 };
766 };
767
768 amba { 730 amba {
769 compatible = "arm,amba-bus"; 731 compatible = "arm,amba-bus";
770 #address-cells = <1>; 732 #address-cells = <1>;
@@ -844,7 +806,6 @@
844 bus-width = <4>; 806 bus-width = <4>;
845 cap-mmc-highspeed; 807 cap-mmc-highspeed;
846 cap-sd-highspeed; 808 cap-sd-highspeed;
847 cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
848 pinctrl-names = "default"; 809 pinctrl-names = "default";
849 pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; 810 pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>;
850 vmmc-supply = <&vmmc_regulator>; 811 vmmc-supply = <&vmmc_regulator>;
diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts
index fe69f92e5f82..261d5e2c48d2 100644
--- a/arch/arm/boot/dts/stih407-b2120.dts
+++ b/arch/arm/boot/dts/stih407-b2120.dts
@@ -7,13 +7,15 @@
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
8 */ 8 */
9/dts-v1/; 9/dts-v1/;
10#include "stih407.dtsi" 10#include "stih407-clock.dtsi"
11#include "stih407-family.dtsi"
12#include "stihxxx-b2120.dtsi"
11/ { 13/ {
12 model = "STiH407 B2120"; 14 model = "STiH407 B2120";
13 compatible = "st,stih407-b2120", "st,stih407"; 15 compatible = "st,stih407-b2120", "st,stih407";
14 16
15 chosen { 17 chosen {
16 bootargs = "console=ttyAS0,115200"; 18 bootargs = "console=ttyAS0,115200 clk_ignore_unused";
17 linux,stdout-path = &sbc_serial0; 19 linux,stdout-path = &sbc_serial0;
18 }; 20 };
19 21
@@ -26,53 +28,4 @@
26 ttyAS0 = &sbc_serial0; 28 ttyAS0 = &sbc_serial0;
27 }; 29 };
28 30
29 soc {
30 sbc_serial0: serial@9530000 {
31 status = "okay";
32 };
33
34 leds {
35 compatible = "gpio-leds";
36 red {
37 #gpio-cells = <2>;
38 label = "Front Panel LED";
39 gpios = <&pio4 1 0>;
40 linux,default-trigger = "heartbeat";
41 };
42 green {
43 #gpio-cells = <2>;
44 gpios = <&pio1 3 0>;
45 default-state = "off";
46 };
47 };
48
49 i2c@9842000 {
50 status = "okay";
51 };
52
53 i2c@9843000 {
54 status = "okay";
55 };
56
57 i2c@9844000 {
58 status = "okay";
59 };
60
61 i2c@9845000 {
62 status = "okay";
63 };
64
65 i2c@9540000 {
66 status = "okay";
67 };
68
69 /* SSC11 to HDMI */
70 i2c@9541000 {
71 status = "okay";
72 /* HDMI V1.3a supports Standard mode only */
73 clock-frequency = <100000>;
74 st,i2c-min-scl-pulse-width-us = <0>;
75 st,i2c-min-sda-pulse-width-us = <5>;
76 };
77 };
78}; 31};
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
index 800f46f009f3..e65744fc12ab 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -5,8 +5,13 @@
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8#include <dt-bindings/clock/stih407-clks.h>
8/ { 9/ {
9 clocks { 10 clocks {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 ranges;
14
10 /* 15 /*
11 * Fixed 30MHz oscillator inputs to SoC 16 * Fixed 30MHz oscillator inputs to SoC
12 */ 17 */
@@ -19,10 +24,59 @@
19 /* 24 /*
20 * ARM Peripheral clock for timers 25 * ARM Peripheral clock for timers
21 */ 26 */
22 arm_periph_clk: arm-periph-clk { 27 arm_periph_clk: clk-m-a9-periphs {
23 #clock-cells = <0>; 28 #clock-cells = <0>;
24 compatible = "fixed-clock"; 29 compatible = "fixed-factor-clock";
25 clock-frequency = <600000000>; 30
31 clocks = <&clk_m_a9>;
32 clock-div = <2>;
33 clock-mult = <1>;
34 };
35
36 /*
37 * A9 PLL.
38 */
39 clockgen-a9@92b0000 {
40 compatible = "st,clkgen-c32";
41 reg = <0x92b0000 0xffff>;
42
43 clockgen_a9_pll: clockgen-a9-pll {
44 #clock-cells = <1>;
45 compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
46
47 clocks = <&clk_sysin>;
48
49 clock-output-names = "clockgen-a9-pll-odf";
50 };
51 };
52
53 /*
54 * ARM CPU related clocks.
55 */
56 clk_m_a9: clk-m-a9@92b0000 {
57 #clock-cells = <0>;
58 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
59 reg = <0x92b0000 0x10000>;
60
61 clocks = <&clockgen_a9_pll 0>,
62 <&clockgen_a9_pll 0>,
63 <&clk_s_c0_flexgen 13>,
64 <&clk_m_a9_ext2f_div2>;
65 };
66
67 /*
68 * ARM Peripheral clock for timers
69 */
70 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
71 #clock-cells = <0>;
72 compatible = "fixed-factor-clock";
73
74 clocks = <&clk_s_c0_flexgen 13>;
75
76 clock-output-names = "clk-m-a9-ext2f-div2";
77
78 clock-div = <2>;
79 clock-mult = <1>;
26 }; 80 };
27 81
28 /* 82 /*
@@ -35,5 +89,238 @@
35 clock-frequency = <200000000>; 89 clock-frequency = <200000000>;
36 clock-output-names = "clk-s-icn-reg-0"; 90 clock-output-names = "clk-s-icn-reg-0";
37 }; 91 };
92
93 clockgen-a@090ff000 {
94 compatible = "st,clkgen-c32";
95 reg = <0x90ff000 0x1000>;
96
97 clk_s_a0_pll: clk-s-a0-pll {
98 #clock-cells = <1>;
99 compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
100
101 clocks = <&clk_sysin>;
102
103 clock-output-names = "clk-s-a0-pll-ofd-0";
104 };
105
106 clk_s_a0_flexgen: clk-s-a0-flexgen {
107 compatible = "st,flexgen";
108
109 #clock-cells = <1>;
110
111 clocks = <&clk_s_a0_pll 0>,
112 <&clk_sysin>;
113
114 clock-output-names = "clk-ic-lmi0";
115 };
116 };
117
118 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
119 #clock-cells = <1>;
120 compatible = "st,stih407-quadfs660-C", "st,quadfs";
121 reg = <0x9103000 0x1000>;
122
123 clocks = <&clk_sysin>;
124
125 clock-output-names = "clk-s-c0-fs0-ch0",
126 "clk-s-c0-fs0-ch1",
127 "clk-s-c0-fs0-ch2",
128 "clk-s-c0-fs0-ch3";
129 };
130
131 clk_s_c0: clockgen-c@09103000 {
132 compatible = "st,clkgen-c32";
133 reg = <0x9103000 0x1000>;
134
135 clk_s_c0_pll0: clk-s-c0-pll0 {
136 #clock-cells = <1>;
137 compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
138
139 clocks = <&clk_sysin>;
140
141 clock-output-names = "clk-s-c0-pll0-odf-0";
142 };
143
144 clk_s_c0_pll1: clk-s-c0-pll1 {
145 #clock-cells = <1>;
146 compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
147
148 clocks = <&clk_sysin>;
149
150 clock-output-names = "clk-s-c0-pll1-odf-0";
151 };
152
153 clk_s_c0_flexgen: clk-s-c0-flexgen {
154 #clock-cells = <1>;
155 compatible = "st,flexgen";
156
157 clocks = <&clk_s_c0_pll0 0>,
158 <&clk_s_c0_pll1 0>,
159 <&clk_s_c0_quadfs 0>,
160 <&clk_s_c0_quadfs 1>,
161 <&clk_s_c0_quadfs 2>,
162 <&clk_s_c0_quadfs 3>,
163 <&clk_sysin>;
164
165 clock-output-names = "clk-icn-gpu",
166 "clk-fdma",
167 "clk-nand",
168 "clk-hva",
169 "clk-proc-stfe",
170 "clk-proc-tp",
171 "clk-rx-icn-dmu",
172 "clk-rx-icn-hva",
173 "clk-icn-cpu",
174 "clk-tx-icn-dmu",
175 "clk-mmc-0",
176 "clk-mmc-1",
177 "clk-jpegdec",
178 "clk-ext2fa9",
179 "clk-ic-bdisp-0",
180 "clk-ic-bdisp-1",
181 "clk-pp-dmu",
182 "clk-vid-dmu",
183 "clk-dss-lpc",
184 "clk-st231-aud-0",
185 "clk-st231-gp-1",
186 "clk-st231-dmu",
187 "clk-icn-lmi",
188 "clk-tx-icn-disp-1",
189 "clk-icn-sbc",
190 "clk-stfe-frc2",
191 "clk-eth-phy",
192 "clk-eth-ref-phyclk",
193 "clk-flash-promip",
194 "clk-main-disp",
195 "clk-aux-disp",
196 "clk-compo-dvp";
197 };
198 };
199
200 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
201 #clock-cells = <1>;
202 compatible = "st,stih407-quadfs660-D", "st,quadfs";
203 reg = <0x9104000 0x1000>;
204
205 clocks = <&clk_sysin>;
206
207 clock-output-names = "clk-s-d0-fs0-ch0",
208 "clk-s-d0-fs0-ch1",
209 "clk-s-d0-fs0-ch2",
210 "clk-s-d0-fs0-ch3";
211 };
212
213 clockgen-d0@09104000 {
214 compatible = "st,clkgen-c32";
215 reg = <0x9104000 0x1000>;
216
217 clk_s_d0_flexgen: clk-s-d0-flexgen {
218 #clock-cells = <1>;
219 compatible = "st,flexgen";
220
221 clocks = <&clk_s_d0_quadfs 0>,
222 <&clk_s_d0_quadfs 1>,
223 <&clk_s_d0_quadfs 2>,
224 <&clk_s_d0_quadfs 3>,
225 <&clk_sysin>;
226
227 clock-output-names = "clk-pcm-0",
228 "clk-pcm-1",
229 "clk-pcm-2",
230 "clk-spdiff";
231 };
232 };
233
234 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
235 #clock-cells = <1>;
236 compatible = "st,stih407-quadfs660-D", "st,quadfs";
237 reg = <0x9106000 0x1000>;
238
239 clocks = <&clk_sysin>;
240
241 clock-output-names = "clk-s-d2-fs0-ch0",
242 "clk-s-d2-fs0-ch1",
243 "clk-s-d2-fs0-ch2",
244 "clk-s-d2-fs0-ch3";
245 };
246
247 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
248 #clock-cells = <0>;
249 compatible = "fixed-clock";
250 clock-frequency = <0>;
251 };
252
253 clockgen-d2@x9106000 {
254 compatible = "st,clkgen-c32";
255 reg = <0x9106000 0x1000>;
256
257 clk_s_d2_flexgen: clk-s-d2-flexgen {
258 #clock-cells = <1>;
259 compatible = "st,flexgen";
260
261 clocks = <&clk_s_d2_quadfs 0>,
262 <&clk_s_d2_quadfs 1>,
263 <&clk_s_d2_quadfs 2>,
264 <&clk_s_d2_quadfs 3>,
265 <&clk_sysin>,
266 <&clk_sysin>,
267 <&clk_tmdsout_hdmi>;
268
269 clock-output-names = "clk-pix-main-disp",
270 "clk-pix-pip",
271 "clk-pix-gdp1",
272 "clk-pix-gdp2",
273 "clk-pix-gdp3",
274 "clk-pix-gdp4",
275 "clk-pix-aux-disp",
276 "clk-denc",
277 "clk-pix-hddac",
278 "clk-hddac",
279 "clk-sddac",
280 "clk-pix-dvo",
281 "clk-dvo",
282 "clk-pix-hdmi",
283 "clk-tmds-hdmi",
284 "clk-ref-hdmiphy";
285 };
286 };
287
288 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
289 #clock-cells = <1>;
290 compatible = "st,stih407-quadfs660-D", "st,quadfs";
291 reg = <0x9107000 0x1000>;
292
293 clocks = <&clk_sysin>;
294
295 clock-output-names = "clk-s-d3-fs0-ch0",
296 "clk-s-d3-fs0-ch1",
297 "clk-s-d3-fs0-ch2",
298 "clk-s-d3-fs0-ch3";
299 };
300
301 clockgen-d3@9107000 {
302 compatible = "st,clkgen-c32";
303 reg = <0x9107000 0x1000>;
304
305 clk_s_d3_flexgen: clk-s-d3-flexgen {
306 #clock-cells = <1>;
307 compatible = "st,flexgen";
308
309 clocks = <&clk_s_d3_quadfs 0>,
310 <&clk_s_d3_quadfs 1>,
311 <&clk_s_d3_quadfs 2>,
312 <&clk_s_d3_quadfs 3>,
313 <&clk_sysin>;
314
315 clock-output-names = "clk-stfe-frc1",
316 "clk-tsout-0",
317 "clk-tsout-1",
318 "clk-mchi",
319 "clk-vsens-compo",
320 "clk-frc1-remote",
321 "clk-lpc-0",
322 "clk-lpc-1";
323 };
324 };
38 }; 325 };
39}; 326};
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 4f9024f19866..3e31d32133b8 100644
--- a/arch/arm/boot/dts/stih407.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -6,8 +6,8 @@
6 * it under the terms of the GNU General Public License version 2 as 6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation. 7 * publishhed by the Free Software Foundation.
8 */ 8 */
9#include "stih407-clock.dtsi"
10#include "stih407-pinctrl.dtsi" 9#include "stih407-pinctrl.dtsi"
10#include <dt-bindings/reset-controller/stih407-resets.h>
11/ { 11/ {
12 #address-cells = <1>; 12 #address-cells = <1>;
13 #size-cells = <1>; 13 #size-cells = <1>;
@@ -63,6 +63,21 @@
63 ranges; 63 ranges;
64 compatible = "simple-bus"; 64 compatible = "simple-bus";
65 65
66 powerdown: powerdown-controller {
67 compatible = "st,stih407-powerdown";
68 #reset-cells = <1>;
69 };
70
71 softreset: softreset-controller {
72 compatible = "st,stih407-softreset";
73 #reset-cells = <1>;
74 };
75
76 picophyreset: picophyreset-controller {
77 compatible = "st,stih407-picophyreset";
78 #reset-cells = <1>;
79 };
80
66 syscfg_sbc: sbc-syscfg@9620000 { 81 syscfg_sbc: sbc-syscfg@9620000 {
67 compatible = "st,stih407-sbc-syscfg", "syscon"; 82 compatible = "st,stih407-sbc-syscfg", "syscon";
68 reg = <0x9620000 0x1000>; 83 reg = <0x9620000 0x1000>;
@@ -104,7 +119,7 @@
104 interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>; 119 interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
105 pinctrl-names = "default"; 120 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_serial0>; 121 pinctrl-0 = <&pinctrl_serial0>;
107 clocks = <&clk_ext2f_a9>; 122 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
108 123
109 status = "disabled"; 124 status = "disabled";
110 }; 125 };
@@ -115,7 +130,7 @@
115 interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>; 130 interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
116 pinctrl-names = "default"; 131 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_serial1>; 132 pinctrl-0 = <&pinctrl_serial1>;
118 clocks = <&clk_ext2f_a9>; 133 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
119 134
120 status = "disabled"; 135 status = "disabled";
121 }; 136 };
@@ -126,7 +141,7 @@
126 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; 141 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
127 pinctrl-names = "default"; 142 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_serial2>; 143 pinctrl-0 = <&pinctrl_serial2>;
129 clocks = <&clk_ext2f_a9>; 144 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
130 145
131 status = "disabled"; 146 status = "disabled";
132 }; 147 };
@@ -158,7 +173,7 @@
158 compatible = "st,comms-ssc4-i2c"; 173 compatible = "st,comms-ssc4-i2c";
159 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 174 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
160 reg = <0x9840000 0x110>; 175 reg = <0x9840000 0x110>;
161 clocks = <&clk_ext2f_a9>; 176 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
162 clock-names = "ssc"; 177 clock-names = "ssc";
163 clock-frequency = <400000>; 178 clock-frequency = <400000>;
164 pinctrl-names = "default"; 179 pinctrl-names = "default";
@@ -171,7 +186,7 @@
171 compatible = "st,comms-ssc4-i2c"; 186 compatible = "st,comms-ssc4-i2c";
172 reg = <0x9841000 0x110>; 187 reg = <0x9841000 0x110>;
173 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 188 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&clk_ext2f_a9>; 189 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
175 clock-names = "ssc"; 190 clock-names = "ssc";
176 clock-frequency = <400000>; 191 clock-frequency = <400000>;
177 pinctrl-names = "default"; 192 pinctrl-names = "default";
@@ -184,7 +199,7 @@
184 compatible = "st,comms-ssc4-i2c"; 199 compatible = "st,comms-ssc4-i2c";
185 reg = <0x9842000 0x110>; 200 reg = <0x9842000 0x110>;
186 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 201 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&clk_ext2f_a9>; 202 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
188 clock-names = "ssc"; 203 clock-names = "ssc";
189 clock-frequency = <400000>; 204 clock-frequency = <400000>;
190 pinctrl-names = "default"; 205 pinctrl-names = "default";
@@ -197,7 +212,7 @@
197 compatible = "st,comms-ssc4-i2c"; 212 compatible = "st,comms-ssc4-i2c";
198 reg = <0x9843000 0x110>; 213 reg = <0x9843000 0x110>;
199 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 214 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&clk_ext2f_a9>; 215 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
201 clock-names = "ssc"; 216 clock-names = "ssc";
202 clock-frequency = <400000>; 217 clock-frequency = <400000>;
203 pinctrl-names = "default"; 218 pinctrl-names = "default";
@@ -210,7 +225,7 @@
210 compatible = "st,comms-ssc4-i2c"; 225 compatible = "st,comms-ssc4-i2c";
211 reg = <0x9844000 0x110>; 226 reg = <0x9844000 0x110>;
212 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 227 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&clk_ext2f_a9>; 228 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
214 clock-names = "ssc"; 229 clock-names = "ssc";
215 clock-frequency = <400000>; 230 clock-frequency = <400000>;
216 pinctrl-names = "default"; 231 pinctrl-names = "default";
@@ -223,7 +238,7 @@
223 compatible = "st,comms-ssc4-i2c"; 238 compatible = "st,comms-ssc4-i2c";
224 reg = <0x9845000 0x110>; 239 reg = <0x9845000 0x110>;
225 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 240 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&clk_ext2f_a9>; 241 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
227 clock-names = "ssc"; 242 clock-names = "ssc";
228 clock-frequency = <400000>; 243 clock-frequency = <400000>;
229 pinctrl-names = "default"; 244 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts
new file mode 100644
index 000000000000..2f61a9960dee
--- /dev/null
+++ b/arch/arm/boot/dts/stih410-b2120.dts
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) 2014 STMicroelectronics (R&D) Limited.
3 * Author: Peter Griffin <peter.griffin@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9/dts-v1/;
10#include "stih410.dtsi"
11#include "stihxxx-b2120.dtsi"
12/ {
13 model = "STiH410 B2120";
14 compatible = "st,stih410-b2120", "st,stih410";
15
16 chosen {
17 bootargs = "console=ttyAS0,115200 clk_ignore_unused";
18 linux,stdout-path = &sbc_serial0;
19 };
20
21 memory {
22 device_type = "memory";
23 reg = <0x40000000 0x80000000>;
24 };
25
26 aliases {
27 ttyAS0 = &sbc_serial0;
28 };
29};
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
new file mode 100644
index 000000000000..6b5803a30096
--- /dev/null
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -0,0 +1,338 @@
1/*
2 * Copyright (C) 2014 STMicroelectronics R&D Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8#include <dt-bindings/clock/stih410-clks.h>
9/ {
10 clocks {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 ranges;
14
15 compatible = "st,stih410-clk", "simple-bus";
16
17 /*
18 * Fixed 30MHz oscillator inputs to SoC
19 */
20 clk_sysin: clk-sysin {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <30000000>;
24 clock-output-names = "CLK_SYSIN";
25 };
26
27 /*
28 * ARM Peripheral clock for timers
29 */
30 arm_periph_clk: clk-m-a9-periphs {
31 #clock-cells = <0>;
32 compatible = "fixed-factor-clock";
33 clocks = <&clk_m_a9>;
34 clock-div = <2>;
35 clock-mult = <1>;
36 };
37
38 /*
39 * A9 PLL.
40 */
41 clockgen-a9@92b0000 {
42 compatible = "st,clkgen-c32";
43 reg = <0x92b0000 0xffff>;
44
45 clockgen_a9_pll: clockgen-a9-pll {
46 #clock-cells = <1>;
47 compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
48
49 clocks = <&clk_sysin>;
50
51 clock-output-names = "clockgen-a9-pll-odf";
52 };
53 };
54
55 /*
56 * ARM CPU related clocks.
57 */
58 clk_m_a9: clk-m-a9@92b0000 {
59 #clock-cells = <0>;
60 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
61 reg = <0x92b0000 0x10000>;
62
63 clocks = <&clockgen_a9_pll 0>,
64 <&clockgen_a9_pll 0>,
65 <&clk_s_c0_flexgen 13>,
66 <&clk_m_a9_ext2f_div2>;
67 };
68
69 /*
70 * ARM Peripheral clock for timers
71 */
72 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
73 #clock-cells = <0>;
74 compatible = "fixed-factor-clock";
75
76 clocks = <&clk_s_c0_flexgen 13>;
77
78 clock-output-names = "clk-m-a9-ext2f-div2";
79
80 clock-div = <2>;
81 clock-mult = <1>;
82 };
83
84 /*
85 * Bootloader initialized system infrastructure clock for
86 * serial devices.
87 */
88 clk_ext2f_a9: clockgen-c0@13 {
89 #clock-cells = <0>;
90 compatible = "fixed-clock";
91 clock-frequency = <200000000>;
92 clock-output-names = "clk-s-icn-reg-0";
93 };
94
95 clockgen-a@090ff000 {
96 compatible = "st,clkgen-c32";
97 reg = <0x90ff000 0x1000>;
98
99 clk_s_a0_pll: clk-s-a0-pll {
100 #clock-cells = <1>;
101 compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
102
103 clocks = <&clk_sysin>;
104
105 clock-output-names = "clk-s-a0-pll-ofd-0";
106 };
107
108 clk_s_a0_flexgen: clk-s-a0-flexgen {
109 compatible = "st,flexgen";
110
111 #clock-cells = <1>;
112
113 clocks = <&clk_s_a0_pll 0>,
114 <&clk_sysin>;
115
116 clock-output-names = "clk-ic-lmi0",
117 "clk-ic-lmi1";
118 };
119 };
120
121 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
122 #clock-cells = <1>;
123 compatible = "st,stih407-quadfs660-C", "st,quadfs";
124 reg = <0x9103000 0x1000>;
125
126 clocks = <&clk_sysin>;
127
128 clock-output-names = "clk-s-c0-fs0-ch0",
129 "clk-s-c0-fs0-ch1",
130 "clk-s-c0-fs0-ch2",
131 "clk-s-c0-fs0-ch3";
132 };
133
134 clk_s_c0: clockgen-c@09103000 {
135 compatible = "st,clkgen-c32";
136 reg = <0x9103000 0x1000>;
137
138 clk_s_c0_pll0: clk-s-c0-pll0 {
139 #clock-cells = <1>;
140 compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
141
142 clocks = <&clk_sysin>;
143
144 clock-output-names = "clk-s-c0-pll0-odf-0";
145 };
146
147 clk_s_c0_pll1: clk-s-c0-pll1 {
148 #clock-cells = <1>;
149 compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
150
151 clocks = <&clk_sysin>;
152
153 clock-output-names = "clk-s-c0-pll1-odf-0";
154 };
155
156 clk_s_c0_flexgen: clk-s-c0-flexgen {
157 #clock-cells = <1>;
158 compatible = "st,flexgen";
159
160 clocks = <&clk_s_c0_pll0 0>,
161 <&clk_s_c0_pll1 0>,
162 <&clk_s_c0_quadfs 0>,
163 <&clk_s_c0_quadfs 1>,
164 <&clk_s_c0_quadfs 2>,
165 <&clk_s_c0_quadfs 3>,
166 <&clk_sysin>;
167
168 clock-output-names = "clk-icn-gpu",
169 "clk-fdma",
170 "clk-nand",
171 "clk-hva",
172 "clk-proc-stfe",
173 "clk-proc-tp",
174 "clk-rx-icn-dmu",
175 "clk-rx-icn-hva",
176 "clk-icn-cpu",
177 "clk-tx-icn-dmu",
178 "clk-mmc-0",
179 "clk-mmc-1",
180 "clk-jpegdec",
181 "clk-ext2fa9",
182 "clk-ic-bdisp-0",
183 "clk-ic-bdisp-1",
184 "clk-pp-dmu",
185 "clk-vid-dmu",
186 "clk-dss-lpc",
187 "clk-st231-aud-0",
188 "clk-st231-gp-1",
189 "clk-st231-dmu",
190 "clk-icn-lmi",
191 "clk-tx-icn-disp-1",
192 "clk-icn-sbc",
193 "clk-stfe-frc2",
194 "clk-eth-phy",
195 "clk-eth-ref-phyclk",
196 "clk-flash-promip",
197 "clk-main-disp",
198 "clk-aux-disp",
199 "clk-compo-dvp",
200 "clk-tx-icn-hades",
201 "clk-rx-icn-hades",
202 "clk-icn-reg-16",
203 "clk-pp-hades",
204 "clk-clust-hades",
205 "clk-hwpe-hades",
206 "clk-fc-hades";
207 };
208 };
209
210 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
211 #clock-cells = <1>;
212 compatible = "st,stih407-quadfs660-D", "st,quadfs";
213 reg = <0x9104000 0x1000>;
214
215 clocks = <&clk_sysin>;
216
217 clock-output-names = "clk-s-d0-fs0-ch0",
218 "clk-s-d0-fs0-ch1",
219 "clk-s-d0-fs0-ch2",
220 "clk-s-d0-fs0-ch3";
221 };
222
223 clockgen-d0@09104000 {
224 compatible = "st,clkgen-c32";
225 reg = <0x9104000 0x1000>;
226
227 clk_s_d0_flexgen: clk-s-d0-flexgen {
228 #clock-cells = <1>;
229 compatible = "st,flexgen";
230
231 clocks = <&clk_s_d0_quadfs 0>,
232 <&clk_s_d0_quadfs 1>,
233 <&clk_s_d0_quadfs 2>,
234 <&clk_s_d0_quadfs 3>,
235 <&clk_sysin>;
236
237 clock-output-names = "clk-pcm-0",
238 "clk-pcm-1",
239 "clk-pcm-2",
240 "clk-spdiff",
241 "clk-pcmr10-master",
242 "clk-usb2-phy";
243 };
244 };
245
246 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
247 #clock-cells = <1>;
248 compatible = "st,stih407-quadfs660-D", "st,quadfs";
249 reg = <0x9106000 0x1000>;
250
251 clocks = <&clk_sysin>;
252
253 clock-output-names = "clk-s-d2-fs0-ch0",
254 "clk-s-d2-fs0-ch1",
255 "clk-s-d2-fs0-ch2",
256 "clk-s-d2-fs0-ch3";
257 };
258
259 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
260 #clock-cells = <0>;
261 compatible = "fixed-clock";
262 clock-frequency = <0>;
263 };
264
265 clockgen-d2@x9106000 {
266 compatible = "st,clkgen-c32";
267 reg = <0x9106000 0x1000>;
268
269 clk_s_d2_flexgen: clk-s-d2-flexgen {
270 #clock-cells = <1>;
271 compatible = "st,flexgen";
272
273 clocks = <&clk_s_d2_quadfs 0>,
274 <&clk_s_d2_quadfs 1>,
275 <&clk_s_d2_quadfs 2>,
276 <&clk_s_d2_quadfs 3>,
277 <&clk_sysin>,
278 <&clk_sysin>,
279 <&clk_tmdsout_hdmi>;
280
281 clock-output-names = "clk-pix-main-disp",
282 "clk-pix-pip",
283 "clk-pix-gdp1",
284 "clk-pix-gdp2",
285 "clk-pix-gdp3",
286 "clk-pix-gdp4",
287 "clk-pix-aux-disp",
288 "clk-denc",
289 "clk-pix-hddac",
290 "clk-hddac",
291 "clk-sddac",
292 "clk-pix-dvo",
293 "clk-dvo",
294 "clk-pix-hdmi",
295 "clk-tmds-hdmi",
296 "clk-ref-hdmiphy";
297 };
298 };
299
300 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
301 #clock-cells = <1>;
302 compatible = "st,stih407-quadfs660-D", "st,quadfs";
303 reg = <0x9107000 0x1000>;
304
305 clocks = <&clk_sysin>;
306
307 clock-output-names = "clk-s-d3-fs0-ch0",
308 "clk-s-d3-fs0-ch1",
309 "clk-s-d3-fs0-ch2",
310 "clk-s-d3-fs0-ch3";
311 };
312
313 clockgen-d3@9107000 {
314 compatible = "st,clkgen-c32";
315 reg = <0x9107000 0x1000>;
316
317 clk_s_d3_flexgen: clk-s-d3-flexgen {
318 #clock-cells = <1>;
319 compatible = "st,flexgen";
320
321 clocks = <&clk_s_d3_quadfs 0>,
322 <&clk_s_d3_quadfs 1>,
323 <&clk_s_d3_quadfs 2>,
324 <&clk_s_d3_quadfs 3>,
325 <&clk_sysin>;
326
327 clock-output-names = "clk-stfe-frc1",
328 "clk-tsout-0",
329 "clk-tsout-1",
330 "clk-mchi",
331 "clk-vsens-compo",
332 "clk-frc1-remote",
333 "clk-lpc-0",
334 "clk-lpc-1";
335 };
336 };
337 };
338};
diff --git a/arch/arm/boot/dts/stih410-pinctrl.dtsi b/arch/arm/boot/dts/stih410-pinctrl.dtsi
new file mode 100644
index 000000000000..b3e9dfc81c07
--- /dev/null
+++ b/arch/arm/boot/dts/stih410-pinctrl.dtsi
@@ -0,0 +1,34 @@
1/*
2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Peter Griffin <peter.griffin@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "st-pincfg.h"
10/ {
11
12 soc {
13 pin-controller-rear {
14
15 usb0 {
16 pinctrl_usb0: usb2-0 {
17 st,pins {
18 usb-oc-detect = <&pio35 0 ALT1 IN>;
19 usb-pwr-enable = <&pio35 1 ALT1 OUT>;
20 };
21 };
22 };
23
24 usb1 {
25 pinctrl_usb1: usb2-1 {
26 st,pins {
27 usb-oc-detect = <&pio35 2 ALT1 IN>;
28 usb-pwr-enable = <&pio35 3 ALT1 OUT>;
29 };
30 };
31 };
32 };
33 };
34};
diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
new file mode 100644
index 000000000000..c05627eb717d
--- /dev/null
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -0,0 +1,14 @@
1/*
2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Peter Griffin <peter.griffin@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih410-clock.dtsi"
10#include "stih407-family.dtsi"
11#include "stih410-pinctrl.dtsi"
12/ {
13
14};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
index 8509a037ae21..3791ad95dbaf 100644
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -11,33 +11,33 @@
11/ { 11/ {
12 12
13 aliases { 13 aliases {
14 gpio0 = &PIO0; 14 gpio0 = &pio0;
15 gpio1 = &PIO1; 15 gpio1 = &pio1;
16 gpio2 = &PIO2; 16 gpio2 = &pio2;
17 gpio3 = &PIO3; 17 gpio3 = &pio3;
18 gpio4 = &PIO4; 18 gpio4 = &pio4;
19 gpio5 = &PIO5; 19 gpio5 = &pio5;
20 gpio6 = &PIO6; 20 gpio6 = &pio6;
21 gpio7 = &PIO7; 21 gpio7 = &pio7;
22 gpio8 = &PIO8; 22 gpio8 = &pio8;
23 gpio9 = &PIO9; 23 gpio9 = &pio9;
24 gpio10 = &PIO10; 24 gpio10 = &pio10;
25 gpio11 = &PIO11; 25 gpio11 = &pio11;
26 gpio12 = &PIO12; 26 gpio12 = &pio12;
27 gpio13 = &PIO13; 27 gpio13 = &pio13;
28 gpio14 = &PIO14; 28 gpio14 = &pio14;
29 gpio15 = &PIO15; 29 gpio15 = &pio15;
30 gpio16 = &PIO16; 30 gpio16 = &pio16;
31 gpio17 = &PIO17; 31 gpio17 = &pio17;
32 gpio18 = &PIO18; 32 gpio18 = &pio18;
33 gpio19 = &PIO100; 33 gpio19 = &pio100;
34 gpio20 = &PIO101; 34 gpio20 = &pio101;
35 gpio21 = &PIO102; 35 gpio21 = &pio102;
36 gpio22 = &PIO103; 36 gpio22 = &pio103;
37 gpio23 = &PIO104; 37 gpio23 = &pio104;
38 gpio24 = &PIO105; 38 gpio24 = &pio105;
39 gpio25 = &PIO106; 39 gpio25 = &pio106;
40 gpio26 = &PIO107; 40 gpio26 = &pio107;
41 }; 41 };
42 42
43 soc { 43 soc {
@@ -52,7 +52,7 @@
52 interrupt-names = "irqmux"; 52 interrupt-names = "irqmux";
53 ranges = <0 0xfe610000 0x5000>; 53 ranges = <0 0xfe610000 0x5000>;
54 54
55 PIO0: gpio@fe610000 { 55 pio0: gpio@fe610000 {
56 gpio-controller; 56 gpio-controller;
57 #gpio-cells = <1>; 57 #gpio-cells = <1>;
58 interrupt-controller; 58 interrupt-controller;
@@ -60,7 +60,7 @@
60 reg = <0 0x100>; 60 reg = <0 0x100>;
61 st,bank-name = "PIO0"; 61 st,bank-name = "PIO0";
62 }; 62 };
63 PIO1: gpio@fe611000 { 63 pio1: gpio@fe611000 {
64 gpio-controller; 64 gpio-controller;
65 #gpio-cells = <1>; 65 #gpio-cells = <1>;
66 interrupt-controller; 66 interrupt-controller;
@@ -68,7 +68,7 @@
68 reg = <0x1000 0x100>; 68 reg = <0x1000 0x100>;
69 st,bank-name = "PIO1"; 69 st,bank-name = "PIO1";
70 }; 70 };
71 PIO2: gpio@fe612000 { 71 pio2: gpio@fe612000 {
72 gpio-controller; 72 gpio-controller;
73 #gpio-cells = <1>; 73 #gpio-cells = <1>;
74 interrupt-controller; 74 interrupt-controller;
@@ -76,7 +76,7 @@
76 reg = <0x2000 0x100>; 76 reg = <0x2000 0x100>;
77 st,bank-name = "PIO2"; 77 st,bank-name = "PIO2";
78 }; 78 };
79 PIO3: gpio@fe613000 { 79 pio3: gpio@fe613000 {
80 gpio-controller; 80 gpio-controller;
81 #gpio-cells = <1>; 81 #gpio-cells = <1>;
82 interrupt-controller; 82 interrupt-controller;
@@ -84,7 +84,7 @@
84 reg = <0x3000 0x100>; 84 reg = <0x3000 0x100>;
85 st,bank-name = "PIO3"; 85 st,bank-name = "PIO3";
86 }; 86 };
87 PIO4: gpio@fe614000 { 87 pio4: gpio@fe614000 {
88 gpio-controller; 88 gpio-controller;
89 #gpio-cells = <1>; 89 #gpio-cells = <1>;
90 interrupt-controller; 90 interrupt-controller;
@@ -96,8 +96,8 @@
96 sbc_serial1 { 96 sbc_serial1 {
97 pinctrl_sbc_serial1:sbc_serial1 { 97 pinctrl_sbc_serial1:sbc_serial1 {
98 st,pins { 98 st,pins {
99 tx = <&PIO2 6 ALT3 OUT>; 99 tx = <&pio2 6 ALT3 OUT>;
100 rx = <&PIO2 7 ALT3 IN>; 100 rx = <&pio2 7 ALT3 IN>;
101 }; 101 };
102 }; 102 };
103 }; 103 };
@@ -105,15 +105,15 @@
105 keyscan { 105 keyscan {
106 pinctrl_keyscan: keyscan { 106 pinctrl_keyscan: keyscan {
107 st,pins { 107 st,pins {
108 keyin0 = <&PIO0 2 ALT2 IN>; 108 keyin0 = <&pio0 2 ALT2 IN>;
109 keyin1 = <&PIO0 3 ALT2 IN>; 109 keyin1 = <&pio0 3 ALT2 IN>;
110 keyin2 = <&PIO0 4 ALT2 IN>; 110 keyin2 = <&pio0 4 ALT2 IN>;
111 keyin3 = <&PIO2 6 ALT2 IN>; 111 keyin3 = <&pio2 6 ALT2 IN>;
112 112
113 keyout0 = <&PIO1 6 ALT2 OUT>; 113 keyout0 = <&pio1 6 ALT2 OUT>;
114 keyout1 = <&PIO1 7 ALT2 OUT>; 114 keyout1 = <&pio1 7 ALT2 OUT>;
115 keyout2 = <&PIO0 6 ALT2 OUT>; 115 keyout2 = <&pio0 6 ALT2 OUT>;
116 keyout3 = <&PIO2 7 ALT2 OUT>; 116 keyout3 = <&pio2 7 ALT2 OUT>;
117 }; 117 };
118 }; 118 };
119 }; 119 };
@@ -121,8 +121,8 @@
121 sbc_i2c0 { 121 sbc_i2c0 {
122 pinctrl_sbc_i2c0_default: sbc_i2c0-default { 122 pinctrl_sbc_i2c0_default: sbc_i2c0-default {
123 st,pins { 123 st,pins {
124 sda = <&PIO4 6 ALT1 BIDIR>; 124 sda = <&pio4 6 ALT1 BIDIR>;
125 scl = <&PIO4 5 ALT1 BIDIR>; 125 scl = <&pio4 5 ALT1 BIDIR>;
126 }; 126 };
127 }; 127 };
128 }; 128 };
@@ -130,8 +130,8 @@
130 sbc_i2c1 { 130 sbc_i2c1 {
131 pinctrl_sbc_i2c1_default: sbc_i2c1-default { 131 pinctrl_sbc_i2c1_default: sbc_i2c1-default {
132 st,pins { 132 st,pins {
133 sda = <&PIO3 2 ALT2 BIDIR>; 133 sda = <&pio3 2 ALT2 BIDIR>;
134 scl = <&PIO3 1 ALT2 BIDIR>; 134 scl = <&pio3 1 ALT2 BIDIR>;
135 }; 135 };
136 }; 136 };
137 }; 137 };
@@ -139,7 +139,7 @@
139 rc{ 139 rc{
140 pinctrl_ir: ir0 { 140 pinctrl_ir: ir0 {
141 st,pins { 141 st,pins {
142 ir = <&PIO4 0 ALT2 IN>; 142 ir = <&pio4 0 ALT2 IN>;
143 }; 143 };
144 }; 144 };
145 }; 145 };
@@ -147,49 +147,49 @@
147 gmac1 { 147 gmac1 {
148 pinctrl_mii1: mii1 { 148 pinctrl_mii1: mii1 {
149 st,pins { 149 st,pins {
150 txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 150 txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
151 txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 151 txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
152 txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 152 txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
153 txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 153 txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
154 txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 154 txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
155 txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 155 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
156 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; 156 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
157 col = <&PIO0 7 ALT1 IN BYPASS 1000>; 157 col = <&pio0 7 ALT1 IN BYPASS 1000>;
158 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; 158 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
159 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; 159 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
160 crs = <&PIO1 2 ALT1 IN BYPASS 1000>; 160 crs = <&pio1 2 ALT1 IN BYPASS 1000>;
161 mdint = <&PIO1 3 ALT1 IN BYPASS 0>; 161 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
162 rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; 162 rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
163 rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; 163 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
164 rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; 164 rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
165 rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; 165 rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
166 rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; 166 rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
167 rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; 167 rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
168 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; 168 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
169 phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>; 169 phyclk = <&pio2 3 ALT1 IN NICLK 1000 CLK_A>;
170 }; 170 };
171 }; 171 };
172 172
173 pinctrl_rgmii1: rgmii1-0 { 173 pinctrl_rgmii1: rgmii1-0 {
174 st,pins { 174 st,pins {
175 txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>; 175 txd0 = <&pio0 0 ALT1 OUT DE_IO 1000 CLK_A>;
176 txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>; 176 txd1 = <&pio0 1 ALT1 OUT DE_IO 1000 CLK_A>;
177 txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>; 177 txd2 = <&pio0 2 ALT1 OUT DE_IO 1000 CLK_A>;
178 txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>; 178 txd3 = <&pio0 3 ALT1 OUT DE_IO 1000 CLK_A>;
179 txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>; 179 txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
180 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; 180 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
181 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; 181 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
182 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; 182 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
183 rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>; 183 rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
184 rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>; 184 rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
185 rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>; 185 rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
186 rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>; 186 rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
187 187
188 rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>; 188 rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>;
189 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; 189 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
190 phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>; 190 phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>;
191 191
192 clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>; 192 clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
193 }; 193 };
194 }; 194 };
195 }; 195 };
@@ -206,7 +206,7 @@
206 interrupt-names = "irqmux"; 206 interrupt-names = "irqmux";
207 ranges = <0 0xfee00000 0x8000>; 207 ranges = <0 0xfee00000 0x8000>;
208 208
209 PIO5: gpio@fee00000 { 209 pio5: gpio@fee00000 {
210 gpio-controller; 210 gpio-controller;
211 #gpio-cells = <1>; 211 #gpio-cells = <1>;
212 interrupt-controller; 212 interrupt-controller;
@@ -214,7 +214,7 @@
214 reg = <0 0x100>; 214 reg = <0 0x100>;
215 st,bank-name = "PIO5"; 215 st,bank-name = "PIO5";
216 }; 216 };
217 PIO6: gpio@fee01000 { 217 pio6: gpio@fee01000 {
218 gpio-controller; 218 gpio-controller;
219 #gpio-cells = <1>; 219 #gpio-cells = <1>;
220 interrupt-controller; 220 interrupt-controller;
@@ -222,7 +222,7 @@
222 reg = <0x1000 0x100>; 222 reg = <0x1000 0x100>;
223 st,bank-name = "PIO6"; 223 st,bank-name = "PIO6";
224 }; 224 };
225 PIO7: gpio@fee02000 { 225 pio7: gpio@fee02000 {
226 gpio-controller; 226 gpio-controller;
227 #gpio-cells = <1>; 227 #gpio-cells = <1>;
228 interrupt-controller; 228 interrupt-controller;
@@ -230,7 +230,7 @@
230 reg = <0x2000 0x100>; 230 reg = <0x2000 0x100>;
231 st,bank-name = "PIO7"; 231 st,bank-name = "PIO7";
232 }; 232 };
233 PIO8: gpio@fee03000 { 233 pio8: gpio@fee03000 {
234 gpio-controller; 234 gpio-controller;
235 #gpio-cells = <1>; 235 #gpio-cells = <1>;
236 interrupt-controller; 236 interrupt-controller;
@@ -238,7 +238,7 @@
238 reg = <0x3000 0x100>; 238 reg = <0x3000 0x100>;
239 st,bank-name = "PIO8"; 239 st,bank-name = "PIO8";
240 }; 240 };
241 PIO9: gpio@fee04000 { 241 pio9: gpio@fee04000 {
242 gpio-controller; 242 gpio-controller;
243 #gpio-cells = <1>; 243 #gpio-cells = <1>;
244 interrupt-controller; 244 interrupt-controller;
@@ -246,7 +246,7 @@
246 reg = <0x4000 0x100>; 246 reg = <0x4000 0x100>;
247 st,bank-name = "PIO9"; 247 st,bank-name = "PIO9";
248 }; 248 };
249 PIO10: gpio@fee05000 { 249 pio10: gpio@fee05000 {
250 gpio-controller; 250 gpio-controller;
251 #gpio-cells = <1>; 251 #gpio-cells = <1>;
252 interrupt-controller; 252 interrupt-controller;
@@ -254,7 +254,7 @@
254 reg = <0x5000 0x100>; 254 reg = <0x5000 0x100>;
255 st,bank-name = "PIO10"; 255 st,bank-name = "PIO10";
256 }; 256 };
257 PIO11: gpio@fee06000 { 257 pio11: gpio@fee06000 {
258 gpio-controller; 258 gpio-controller;
259 #gpio-cells = <1>; 259 #gpio-cells = <1>;
260 interrupt-controller; 260 interrupt-controller;
@@ -262,7 +262,7 @@
262 reg = <0x6000 0x100>; 262 reg = <0x6000 0x100>;
263 st,bank-name = "PIO11"; 263 st,bank-name = "PIO11";
264 }; 264 };
265 PIO12: gpio@fee07000 { 265 pio12: gpio@fee07000 {
266 gpio-controller; 266 gpio-controller;
267 #gpio-cells = <1>; 267 #gpio-cells = <1>;
268 interrupt-controller; 268 interrupt-controller;
@@ -274,8 +274,8 @@
274 i2c0 { 274 i2c0 {
275 pinctrl_i2c0_default: i2c0-default { 275 pinctrl_i2c0_default: i2c0-default {
276 st,pins { 276 st,pins {
277 sda = <&PIO9 3 ALT1 BIDIR>; 277 sda = <&pio9 3 ALT1 BIDIR>;
278 scl = <&PIO9 2 ALT1 BIDIR>; 278 scl = <&pio9 2 ALT1 BIDIR>;
279 }; 279 };
280 }; 280 };
281 }; 281 };
@@ -283,8 +283,8 @@
283 i2c1 { 283 i2c1 {
284 pinctrl_i2c1_default: i2c1-default { 284 pinctrl_i2c1_default: i2c1-default {
285 st,pins { 285 st,pins {
286 sda = <&PIO12 1 ALT1 BIDIR>; 286 sda = <&pio12 1 ALT1 BIDIR>;
287 scl = <&PIO12 0 ALT1 BIDIR>; 287 scl = <&pio12 0 ALT1 BIDIR>;
288 }; 288 };
289 }; 289 };
290 }; 290 };
@@ -301,7 +301,7 @@
301 interrupt-names = "irqmux"; 301 interrupt-names = "irqmux";
302 ranges = <0 0xfe820000 0x8000>; 302 ranges = <0 0xfe820000 0x8000>;
303 303
304 PIO13: gpio@fe820000 { 304 pio13: gpio@fe820000 {
305 gpio-controller; 305 gpio-controller;
306 #gpio-cells = <1>; 306 #gpio-cells = <1>;
307 interrupt-controller; 307 interrupt-controller;
@@ -309,7 +309,7 @@
309 reg = <0 0x100>; 309 reg = <0 0x100>;
310 st,bank-name = "PIO13"; 310 st,bank-name = "PIO13";
311 }; 311 };
312 PIO14: gpio@fe821000 { 312 pio14: gpio@fe821000 {
313 gpio-controller; 313 gpio-controller;
314 #gpio-cells = <1>; 314 #gpio-cells = <1>;
315 interrupt-controller; 315 interrupt-controller;
@@ -317,7 +317,7 @@
317 reg = <0x1000 0x100>; 317 reg = <0x1000 0x100>;
318 st,bank-name = "PIO14"; 318 st,bank-name = "PIO14";
319 }; 319 };
320 PIO15: gpio@fe822000 { 320 pio15: gpio@fe822000 {
321 gpio-controller; 321 gpio-controller;
322 #gpio-cells = <1>; 322 #gpio-cells = <1>;
323 interrupt-controller; 323 interrupt-controller;
@@ -325,7 +325,7 @@
325 reg = <0x2000 0x100>; 325 reg = <0x2000 0x100>;
326 st,bank-name = "PIO15"; 326 st,bank-name = "PIO15";
327 }; 327 };
328 PIO16: gpio@fe823000 { 328 pio16: gpio@fe823000 {
329 gpio-controller; 329 gpio-controller;
330 #gpio-cells = <1>; 330 #gpio-cells = <1>;
331 interrupt-controller; 331 interrupt-controller;
@@ -333,7 +333,7 @@
333 reg = <0x3000 0x100>; 333 reg = <0x3000 0x100>;
334 st,bank-name = "PIO16"; 334 st,bank-name = "PIO16";
335 }; 335 };
336 PIO17: gpio@fe824000 { 336 pio17: gpio@fe824000 {
337 gpio-controller; 337 gpio-controller;
338 #gpio-cells = <1>; 338 #gpio-cells = <1>;
339 interrupt-controller; 339 interrupt-controller;
@@ -341,7 +341,7 @@
341 reg = <0x4000 0x100>; 341 reg = <0x4000 0x100>;
342 st,bank-name = "PIO17"; 342 st,bank-name = "PIO17";
343 }; 343 };
344 PIO18: gpio@fe825000 { 344 pio18: gpio@fe825000 {
345 gpio-controller; 345 gpio-controller;
346 #gpio-cells = <1>; 346 #gpio-cells = <1>;
347 interrupt-controller; 347 interrupt-controller;
@@ -353,8 +353,8 @@
353 serial2 { 353 serial2 {
354 pinctrl_serial2: serial2-0 { 354 pinctrl_serial2: serial2-0 {
355 st,pins { 355 st,pins {
356 tx = <&PIO17 4 ALT2 OUT>; 356 tx = <&pio17 4 ALT2 OUT>;
357 rx = <&PIO17 5 ALT2 IN>; 357 rx = <&pio17 5 ALT2 IN>;
358 }; 358 };
359 }; 359 };
360 }; 360 };
@@ -362,73 +362,94 @@
362 gmac0{ 362 gmac0{
363 pinctrl_mii0: mii0 { 363 pinctrl_mii0: mii0 {
364 st,pins { 364 st,pins {
365 mdint = <&PIO13 6 ALT2 IN BYPASS 0>; 365 mdint = <&pio13 6 ALT2 IN BYPASS 0>;
366 txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 366 txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
367 367
368 txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 368 txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
369 txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 369 txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
370 txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; 370 txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
371 txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; 371 txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
372 372
373 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; 373 txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
374 txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 374 txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
375 crs = <&PIO15 2 ALT2 IN BYPASS 1000>; 375 crs = <&pio15 2 ALT2 IN BYPASS 1000>;
376 col = <&PIO15 3 ALT2 IN BYPASS 1000>; 376 col = <&pio15 3 ALT2 IN BYPASS 1000>;
377 mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>; 377 mdio = <&pio15 4 ALT2 OUT BYPASS 3000>;
378 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; 378 mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
379 379
380 rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; 380 rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
381 rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; 381 rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
382 rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; 382 rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
383 rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; 383 rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
384 rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; 384 rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
385 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; 385 rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
386 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; 386 rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
387 phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>; 387 phyclk = <&pio13 5 ALT2 OUT NICLK 1000 CLK_A>;
388 388
389 }; 389 };
390 }; 390 };
391 391
392 pinctrl_gmii0: gmii0 { 392 pinctrl_gmii0: gmii0 {
393 st,pins { 393 st,pins {
394 mdint = <&PIO13 6 ALT2 IN BYPASS 0>; 394 mdint = <&pio13 6 ALT2 IN BYPASS 0>;
395 mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>; 395 mdio = <&pio15 4 ALT2 OUT BYPASS 3000>;
396 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; 396 mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
397 txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; 397 txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
398 398
399 txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; 399 txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
400 txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; 400 txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
401 txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 401 txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
402 txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 402 txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
403 txd4 = <&PIO14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 403 txd4 = <&pio14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
404 txd5 = <&PIO14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 404 txd5 = <&pio14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
405 txd6 = <&PIO14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 405 txd6 = <&pio14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
406 txd7 = <&PIO14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 406 txd7 = <&pio14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
407 407
408 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; 408 txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
409 txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; 409 txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
410 crs = <&PIO15 2 ALT2 IN BYPASS 1000>; 410 crs = <&pio15 2 ALT2 IN BYPASS 1000>;
411 col = <&PIO15 3 ALT2 IN BYPASS 1000>; 411 col = <&pio15 3 ALT2 IN BYPASS 1000>;
412 rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 412 rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
413 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 413 rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
414 414
415 rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 415 rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
416 rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 416 rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
417 rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 417 rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
418 rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 418 rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
419 rxd4 = <&PIO16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 419 rxd4 = <&pio16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
420 rxd5 = <&PIO16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 420 rxd5 = <&pio16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
421 rxd6 = <&PIO16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 421 rxd6 = <&pio16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
422 rxd7 = <&PIO16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 422 rxd7 = <&pio16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
423 423
424 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; 424 rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
425 clk125 = <&PIO17 6 ALT1 IN NICLK 0 CLK_A>; 425 clk125 = <&pio17 6 ALT1 IN NICLK 0 CLK_A>;
426 phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>; 426 phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>;
427 427
428 428
429 }; 429 };
430 }; 430 };
431 }; 431 };
432
433 mmc0 {
434 pinctrl_mmc0: mmc0 {
435 st,pins {
436 mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
437 data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>;
438 data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>;
439 data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>;
440 data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>;
441 cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>;
442 wp = <&pio15 3 ALT4 IN>;
443 data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>;
444 data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>;
445 data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>;
446 data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>;
447 pwr = <&pio17 1 ALT4 OUT>;
448 cd = <&pio17 2 ALT4 IN>;
449 led = <&pio17 3 ALT4 OUT>;
450 };
451 };
452 };
432 }; 453 };
433 454
434 pin-controller-left { 455 pin-controller-left {
@@ -442,7 +463,7 @@
442 interrupt-names = "irqmux"; 463 interrupt-names = "irqmux";
443 ranges = <0 0xfd6b0000 0x3000>; 464 ranges = <0 0xfd6b0000 0x3000>;
444 465
445 PIO100: gpio@fd6b0000 { 466 pio100: gpio@fd6b0000 {
446 gpio-controller; 467 gpio-controller;
447 #gpio-cells = <1>; 468 #gpio-cells = <1>;
448 interrupt-controller; 469 interrupt-controller;
@@ -450,7 +471,7 @@
450 reg = <0 0x100>; 471 reg = <0 0x100>;
451 st,bank-name = "PIO100"; 472 st,bank-name = "PIO100";
452 }; 473 };
453 PIO101: gpio@fd6b1000 { 474 pio101: gpio@fd6b1000 {
454 gpio-controller; 475 gpio-controller;
455 #gpio-cells = <1>; 476 #gpio-cells = <1>;
456 interrupt-controller; 477 interrupt-controller;
@@ -458,7 +479,7 @@
458 reg = <0x1000 0x100>; 479 reg = <0x1000 0x100>;
459 st,bank-name = "PIO101"; 480 st,bank-name = "PIO101";
460 }; 481 };
461 PIO102: gpio@fd6b2000 { 482 pio102: gpio@fd6b2000 {
462 gpio-controller; 483 gpio-controller;
463 #gpio-cells = <1>; 484 #gpio-cells = <1>;
464 interrupt-controller; 485 interrupt-controller;
@@ -479,7 +500,7 @@
479 interrupt-names = "irqmux"; 500 interrupt-names = "irqmux";
480 ranges = <0 0xfd330000 0x5000>; 501 ranges = <0 0xfd330000 0x5000>;
481 502
482 PIO103: gpio@fd330000 { 503 pio103: gpio@fd330000 {
483 gpio-controller; 504 gpio-controller;
484 #gpio-cells = <1>; 505 #gpio-cells = <1>;
485 interrupt-controller; 506 interrupt-controller;
@@ -487,7 +508,7 @@
487 reg = <0 0x100>; 508 reg = <0 0x100>;
488 st,bank-name = "PIO103"; 509 st,bank-name = "PIO103";
489 }; 510 };
490 PIO104: gpio@fd331000 { 511 pio104: gpio@fd331000 {
491 gpio-controller; 512 gpio-controller;
492 #gpio-cells = <1>; 513 #gpio-cells = <1>;
493 interrupt-controller; 514 interrupt-controller;
@@ -495,7 +516,7 @@
495 reg = <0x1000 0x100>; 516 reg = <0x1000 0x100>;
496 st,bank-name = "PIO104"; 517 st,bank-name = "PIO104";
497 }; 518 };
498 PIO105: gpio@fd332000 { 519 pio105: gpio@fd332000 {
499 gpio-controller; 520 gpio-controller;
500 #gpio-cells = <1>; 521 #gpio-cells = <1>;
501 interrupt-controller; 522 interrupt-controller;
@@ -503,7 +524,7 @@
503 reg = <0x2000 0x100>; 524 reg = <0x2000 0x100>;
504 st,bank-name = "PIO105"; 525 st,bank-name = "PIO105";
505 }; 526 };
506 PIO106: gpio@fd333000 { 527 pio106: gpio@fd333000 {
507 gpio-controller; 528 gpio-controller;
508 #gpio-cells = <1>; 529 #gpio-cells = <1>;
509 interrupt-controller; 530 interrupt-controller;
@@ -511,7 +532,7 @@
511 reg = <0x3000 0x100>; 532 reg = <0x3000 0x100>;
512 st,bank-name = "PIO106"; 533 st,bank-name = "PIO106";
513 }; 534 };
514 PIO107: gpio@fd334000 { 535 pio107: gpio@fd334000 {
515 gpio-controller; 536 gpio-controller;
516 #gpio-cells = <1>; 537 #gpio-cells = <1>;
517 interrupt-controller; 538 interrupt-controller;
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index a0f6f75fe3b5..9198c12765ea 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -218,5 +218,17 @@
218 resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>, 218 resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>,
219 <&softreset STIH415_KEYSCAN_SOFTRESET>; 219 <&softreset STIH415_KEYSCAN_SOFTRESET>;
220 }; 220 };
221
222 mmc0: sdhci@fe81e000 {
223 compatible = "st,sdhci";
224 status = "disabled";
225 reg = <0xfe81e000 0x1000>;
226 interrupts = <GIC_SPI 145 IRQ_TYPE_NONE>;
227 interrupt-names = "mmcirq";
228 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_mmc0>;
230 clock-names = "mmc";
231 clocks = <&clk_s_a1_ls 1>;
232 };
221 }; 233 };
222}; 234};
diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts
index 4e2df66b99ea..200a81844765 100644
--- a/arch/arm/boot/dts/stih416-b2020.dts
+++ b/arch/arm/boot/dts/stih416-b2020.dts
@@ -12,4 +12,26 @@
12/ { 12/ {
13 model = "STiH416 B2020"; 13 model = "STiH416 B2020";
14 compatible = "st,stih416-b2020", "st,stih416"; 14 compatible = "st,stih416-b2020", "st,stih416";
15
16 soc {
17 mmc1: sdhci@fe81f000 {
18 status = "okay";
19 bus-width = <8>;
20 non-removable;
21 };
22
23 miphy365x_phy: phy@fe382000 {
24 phy_port0: port@fe382000 {
25 st,sata-gen = <3>;
26 };
27
28 phy_port1: port@fe38a000 {
29 st,pcie-tx-pol-inv;
30 };
31 };
32
33 sata0: sata@fe380000{
34 status = "okay";
35 };
36 };
15}; 37};
diff --git a/arch/arm/boot/dts/stih416-b2020e.dts b/arch/arm/boot/dts/stih416-b2020e.dts
index ba0fa2caaf18..961799e1dc51 100644
--- a/arch/arm/boot/dts/stih416-b2020e.dts
+++ b/arch/arm/boot/dts/stih416-b2020e.dts
@@ -19,17 +19,37 @@
19 red { 19 red {
20 #gpio-cells = <1>; 20 #gpio-cells = <1>;
21 label = "Front Panel LED"; 21 label = "Front Panel LED";
22 gpios = <&PIO4 1>; 22 gpios = <&pio4 1>;
23 linux,default-trigger = "heartbeat"; 23 linux,default-trigger = "heartbeat";
24 }; 24 };
25 green { 25 green {
26 gpios = <&PIO1 3>; 26 gpios = <&pio1 3>;
27 default-state = "off"; 27 default-state = "off";
28 }; 28 };
29 }; 29 };
30 30
31 ethernet1: dwmac@fef08000 { 31 ethernet1: dwmac@fef08000 {
32 snps,reset-gpio = <&PIO0 7>; 32 snps,reset-gpio = <&pio0 7>;
33 };
34
35 mmc1: sdhci@fe81f000 {
36 status = "okay";
37 bus-width = <8>;
38 non-removable;
39 };
40
41 miphy365x_phy: phy@fe382000 {
42 phy_port0: port@fe382000 {
43 st,sata-gen = <3>;
44 };
45
46 phy_port1: port@fe38a000 {
47 st,pcie-tx-pol-inv;
48 };
49 };
50
51 sata0: sata@fe380000{
52 status = "okay";
33 }; 53 };
34 }; 54 };
35}; 55};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index ee6c119e261e..9cccf2d6aa26 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -12,36 +12,36 @@
12/ { 12/ {
13 13
14 aliases { 14 aliases {
15 gpio0 = &PIO0; 15 gpio0 = &pio0;
16 gpio1 = &PIO1; 16 gpio1 = &pio1;
17 gpio2 = &PIO2; 17 gpio2 = &pio2;
18 gpio3 = &PIO3; 18 gpio3 = &pio3;
19 gpio4 = &PIO4; 19 gpio4 = &pio4;
20 gpio5 = &PIO40; 20 gpio5 = &pio40;
21 gpio6 = &PIO5; 21 gpio6 = &pio5;
22 gpio7 = &PIO6; 22 gpio7 = &pio6;
23 gpio8 = &PIO7; 23 gpio8 = &pio7;
24 gpio9 = &PIO8; 24 gpio9 = &pio8;
25 gpio10 = &PIO9; 25 gpio10 = &pio9;
26 gpio11 = &PIO10; 26 gpio11 = &pio10;
27 gpio12 = &PIO11; 27 gpio12 = &pio11;
28 gpio13 = &PIO12; 28 gpio13 = &pio12;
29 gpio14 = &PIO30; 29 gpio14 = &pio30;
30 gpio15 = &PIO31; 30 gpio15 = &pio31;
31 gpio16 = &PIO13; 31 gpio16 = &pio13;
32 gpio17 = &PIO14; 32 gpio17 = &pio14;
33 gpio18 = &PIO15; 33 gpio18 = &pio15;
34 gpio19 = &PIO16; 34 gpio19 = &pio16;
35 gpio20 = &PIO17; 35 gpio20 = &pio17;
36 gpio21 = &PIO18; 36 gpio21 = &pio18;
37 gpio22 = &PIO100; 37 gpio22 = &pio100;
38 gpio23 = &PIO101; 38 gpio23 = &pio101;
39 gpio24 = &PIO102; 39 gpio24 = &pio102;
40 gpio25 = &PIO103; 40 gpio25 = &pio103;
41 gpio26 = &PIO104; 41 gpio26 = &pio104;
42 gpio27 = &PIO105; 42 gpio27 = &pio105;
43 gpio28 = &PIO106; 43 gpio28 = &pio106;
44 gpio29 = &PIO107; 44 gpio29 = &pio107;
45 }; 45 };
46 46
47 soc { 47 soc {
@@ -56,7 +56,7 @@
56 interrupt-names = "irqmux"; 56 interrupt-names = "irqmux";
57 ranges = <0 0xfe610000 0x6000>; 57 ranges = <0 0xfe610000 0x6000>;
58 58
59 PIO0: gpio@fe610000 { 59 pio0: gpio@fe610000 {
60 gpio-controller; 60 gpio-controller;
61 #gpio-cells = <1>; 61 #gpio-cells = <1>;
62 interrupt-controller; 62 interrupt-controller;
@@ -64,7 +64,7 @@
64 reg = <0 0x100>; 64 reg = <0 0x100>;
65 st,bank-name = "PIO0"; 65 st,bank-name = "PIO0";
66 }; 66 };
67 PIO1: gpio@fe611000 { 67 pio1: gpio@fe611000 {
68 gpio-controller; 68 gpio-controller;
69 #gpio-cells = <1>; 69 #gpio-cells = <1>;
70 interrupt-controller; 70 interrupt-controller;
@@ -72,7 +72,7 @@
72 reg = <0x1000 0x100>; 72 reg = <0x1000 0x100>;
73 st,bank-name = "PIO1"; 73 st,bank-name = "PIO1";
74 }; 74 };
75 PIO2: gpio@fe612000 { 75 pio2: gpio@fe612000 {
76 gpio-controller; 76 gpio-controller;
77 #gpio-cells = <1>; 77 #gpio-cells = <1>;
78 interrupt-controller; 78 interrupt-controller;
@@ -80,7 +80,7 @@
80 reg = <0x2000 0x100>; 80 reg = <0x2000 0x100>;
81 st,bank-name = "PIO2"; 81 st,bank-name = "PIO2";
82 }; 82 };
83 PIO3: gpio@fe613000 { 83 pio3: gpio@fe613000 {
84 gpio-controller; 84 gpio-controller;
85 #gpio-cells = <1>; 85 #gpio-cells = <1>;
86 interrupt-controller; 86 interrupt-controller;
@@ -88,7 +88,7 @@
88 reg = <0x3000 0x100>; 88 reg = <0x3000 0x100>;
89 st,bank-name = "PIO3"; 89 st,bank-name = "PIO3";
90 }; 90 };
91 PIO4: gpio@fe614000 { 91 pio4: gpio@fe614000 {
92 gpio-controller; 92 gpio-controller;
93 #gpio-cells = <1>; 93 #gpio-cells = <1>;
94 interrupt-controller; 94 interrupt-controller;
@@ -96,7 +96,7 @@
96 reg = <0x4000 0x100>; 96 reg = <0x4000 0x100>;
97 st,bank-name = "PIO4"; 97 st,bank-name = "PIO4";
98 }; 98 };
99 PIO40: gpio@fe615000 { 99 pio40: gpio@fe615000 {
100 gpio-controller; 100 gpio-controller;
101 #gpio-cells = <1>; 101 #gpio-cells = <1>;
102 interrupt-controller; 102 interrupt-controller;
@@ -109,15 +109,15 @@
109 rc{ 109 rc{
110 pinctrl_ir: ir0 { 110 pinctrl_ir: ir0 {
111 st,pins { 111 st,pins {
112 ir = <&PIO4 0 ALT2 IN>; 112 ir = <&pio4 0 ALT2 IN>;
113 }; 113 };
114 }; 114 };
115 }; 115 };
116 sbc_serial1 { 116 sbc_serial1 {
117 pinctrl_sbc_serial1: sbc_serial1 { 117 pinctrl_sbc_serial1: sbc_serial1 {
118 st,pins { 118 st,pins {
119 tx = <&PIO2 6 ALT3 OUT>; 119 tx = <&pio2 6 ALT3 OUT>;
120 rx = <&PIO2 7 ALT3 IN>; 120 rx = <&pio2 7 ALT3 IN>;
121 }; 121 };
122 }; 122 };
123 }; 123 };
@@ -125,15 +125,15 @@
125 keyscan { 125 keyscan {
126 pinctrl_keyscan: keyscan { 126 pinctrl_keyscan: keyscan {
127 st,pins { 127 st,pins {
128 keyin0 = <&PIO0 2 ALT2 IN>; 128 keyin0 = <&pio0 2 ALT2 IN>;
129 keyin1 = <&PIO0 3 ALT2 IN>; 129 keyin1 = <&pio0 3 ALT2 IN>;
130 keyin2 = <&PIO0 4 ALT2 IN>; 130 keyin2 = <&pio0 4 ALT2 IN>;
131 keyin3 = <&PIO2 6 ALT2 IN>; 131 keyin3 = <&pio2 6 ALT2 IN>;
132 132
133 keyout0 = <&PIO1 6 ALT2 OUT>; 133 keyout0 = <&pio1 6 ALT2 OUT>;
134 keyout1 = <&PIO1 7 ALT2 OUT>; 134 keyout1 = <&pio1 7 ALT2 OUT>;
135 keyout2 = <&PIO0 6 ALT2 OUT>; 135 keyout2 = <&pio0 6 ALT2 OUT>;
136 keyout3 = <&PIO2 7 ALT2 OUT>; 136 keyout3 = <&pio2 7 ALT2 OUT>;
137 }; 137 };
138 }; 138 };
139 }; 139 };
@@ -141,8 +141,17 @@
141 sbc_i2c0 { 141 sbc_i2c0 {
142 pinctrl_sbc_i2c0_default: sbc_i2c0-default { 142 pinctrl_sbc_i2c0_default: sbc_i2c0-default {
143 st,pins { 143 st,pins {
144 sda = <&PIO4 6 ALT1 BIDIR>; 144 sda = <&pio4 6 ALT1 BIDIR>;
145 scl = <&PIO4 5 ALT1 BIDIR>; 145 scl = <&pio4 5 ALT1 BIDIR>;
146 };
147 };
148 };
149
150 usb {
151 pinctrl_usb3: usb3 {
152 st,pins {
153 oc-detect = <&pio40 0 ALT1 IN>;
154 pwr-enable = <&pio40 1 ALT1 OUT>;
146 }; 155 };
147 }; 156 };
148 }; 157 };
@@ -150,8 +159,8 @@
150 sbc_i2c1 { 159 sbc_i2c1 {
151 pinctrl_sbc_i2c1_default: sbc_i2c1-default { 160 pinctrl_sbc_i2c1_default: sbc_i2c1-default {
152 st,pins { 161 st,pins {
153 sda = <&PIO3 2 ALT2 BIDIR>; 162 sda = <&pio3 2 ALT2 BIDIR>;
154 scl = <&PIO3 1 ALT2 BIDIR>; 163 scl = <&pio3 1 ALT2 BIDIR>;
155 }; 164 };
156 }; 165 };
157 }; 166 };
@@ -159,51 +168,51 @@
159 gmac1 { 168 gmac1 {
160 pinctrl_mii1: mii1 { 169 pinctrl_mii1: mii1 {
161 st,pins { 170 st,pins {
162 txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 171 txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
163 txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 172 txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
164 txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 173 txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
165 txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 174 txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
166 txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 175 txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
167 txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 176 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
168 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; 177 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
169 col = <&PIO0 7 ALT1 IN BYPASS 1000>; 178 col = <&pio0 7 ALT1 IN BYPASS 1000>;
170 179
171 mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>; 180 mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
172 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; 181 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
173 crs = <&PIO1 2 ALT1 IN BYPASS 1000>; 182 crs = <&pio1 2 ALT1 IN BYPASS 1000>;
174 mdint = <&PIO1 3 ALT1 IN BYPASS 0>; 183 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
175 rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; 184 rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
176 rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; 185 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
177 rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; 186 rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
178 rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; 187 rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
179 188
180 rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; 189 rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
181 rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; 190 rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
182 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; 191 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
183 phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>; 192 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
184 }; 193 };
185 }; 194 };
186 pinctrl_rgmii1: rgmii1-0 { 195 pinctrl_rgmii1: rgmii1-0 {
187 st,pins { 196 st,pins {
188 txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>; 197 txd0 = <&pio0 0 ALT1 OUT DE_IO 500 CLK_A>;
189 txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>; 198 txd1 = <&pio0 1 ALT1 OUT DE_IO 500 CLK_A>;
190 txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>; 199 txd2 = <&pio0 2 ALT1 OUT DE_IO 500 CLK_A>;
191 txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>; 200 txd3 = <&pio0 3 ALT1 OUT DE_IO 500 CLK_A>;
192 txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>; 201 txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
193 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; 202 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
194 203
195 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; 204 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
196 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; 205 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
197 rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>; 206 rxd0 = <&pio1 4 ALT1 IN DE_IO 500 CLK_A>;
198 rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>; 207 rxd1 = <&pio1 5 ALT1 IN DE_IO 500 CLK_A>;
199 rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>; 208 rxd2 = <&pio1 6 ALT1 IN DE_IO 500 CLK_A>;
200 rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>; 209 rxd3 = <&pio1 7 ALT1 IN DE_IO 500 CLK_A>;
201 210
202 rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>; 211 rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>;
203 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; 212 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
204 phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>; 213 phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>;
205 214
206 clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>; 215 clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
207 }; 216 };
208 }; 217 };
209 }; 218 };
@@ -220,7 +229,7 @@
220 interrupt-names = "irqmux"; 229 interrupt-names = "irqmux";
221 ranges = <0 0xfee00000 0x10000>; 230 ranges = <0 0xfee00000 0x10000>;
222 231
223 PIO5: gpio@fee00000 { 232 pio5: gpio@fee00000 {
224 gpio-controller; 233 gpio-controller;
225 #gpio-cells = <1>; 234 #gpio-cells = <1>;
226 interrupt-controller; 235 interrupt-controller;
@@ -228,7 +237,7 @@
228 reg = <0 0x100>; 237 reg = <0 0x100>;
229 st,bank-name = "PIO5"; 238 st,bank-name = "PIO5";
230 }; 239 };
231 PIO6: gpio@fee01000 { 240 pio6: gpio@fee01000 {
232 gpio-controller; 241 gpio-controller;
233 #gpio-cells = <1>; 242 #gpio-cells = <1>;
234 interrupt-controller; 243 interrupt-controller;
@@ -236,7 +245,7 @@
236 reg = <0x1000 0x100>; 245 reg = <0x1000 0x100>;
237 st,bank-name = "PIO6"; 246 st,bank-name = "PIO6";
238 }; 247 };
239 PIO7: gpio@fee02000 { 248 pio7: gpio@fee02000 {
240 gpio-controller; 249 gpio-controller;
241 #gpio-cells = <1>; 250 #gpio-cells = <1>;
242 interrupt-controller; 251 interrupt-controller;
@@ -244,7 +253,7 @@
244 reg = <0x2000 0x100>; 253 reg = <0x2000 0x100>;
245 st,bank-name = "PIO7"; 254 st,bank-name = "PIO7";
246 }; 255 };
247 PIO8: gpio@fee03000 { 256 pio8: gpio@fee03000 {
248 gpio-controller; 257 gpio-controller;
249 #gpio-cells = <1>; 258 #gpio-cells = <1>;
250 interrupt-controller; 259 interrupt-controller;
@@ -252,7 +261,7 @@
252 reg = <0x3000 0x100>; 261 reg = <0x3000 0x100>;
253 st,bank-name = "PIO8"; 262 st,bank-name = "PIO8";
254 }; 263 };
255 PIO9: gpio@fee04000 { 264 pio9: gpio@fee04000 {
256 gpio-controller; 265 gpio-controller;
257 #gpio-cells = <1>; 266 #gpio-cells = <1>;
258 interrupt-controller; 267 interrupt-controller;
@@ -260,7 +269,7 @@
260 reg = <0x4000 0x100>; 269 reg = <0x4000 0x100>;
261 st,bank-name = "PIO9"; 270 st,bank-name = "PIO9";
262 }; 271 };
263 PIO10: gpio@fee05000 { 272 pio10: gpio@fee05000 {
264 gpio-controller; 273 gpio-controller;
265 #gpio-cells = <1>; 274 #gpio-cells = <1>;
266 interrupt-controller; 275 interrupt-controller;
@@ -268,7 +277,7 @@
268 reg = <0x5000 0x100>; 277 reg = <0x5000 0x100>;
269 st,bank-name = "PIO10"; 278 st,bank-name = "PIO10";
270 }; 279 };
271 PIO11: gpio@fee06000 { 280 pio11: gpio@fee06000 {
272 gpio-controller; 281 gpio-controller;
273 #gpio-cells = <1>; 282 #gpio-cells = <1>;
274 interrupt-controller; 283 interrupt-controller;
@@ -276,7 +285,7 @@
276 reg = <0x6000 0x100>; 285 reg = <0x6000 0x100>;
277 st,bank-name = "PIO11"; 286 st,bank-name = "PIO11";
278 }; 287 };
279 PIO12: gpio@fee07000 { 288 pio12: gpio@fee07000 {
280 gpio-controller; 289 gpio-controller;
281 #gpio-cells = <1>; 290 #gpio-cells = <1>;
282 interrupt-controller; 291 interrupt-controller;
@@ -284,7 +293,7 @@
284 reg = <0x7000 0x100>; 293 reg = <0x7000 0x100>;
285 st,bank-name = "PIO12"; 294 st,bank-name = "PIO12";
286 }; 295 };
287 PIO30: gpio@fee08000 { 296 pio30: gpio@fee08000 {
288 gpio-controller; 297 gpio-controller;
289 #gpio-cells = <1>; 298 #gpio-cells = <1>;
290 interrupt-controller; 299 interrupt-controller;
@@ -292,7 +301,7 @@
292 reg = <0x8000 0x100>; 301 reg = <0x8000 0x100>;
293 st,bank-name = "PIO30"; 302 st,bank-name = "PIO30";
294 }; 303 };
295 PIO31: gpio@fee09000 { 304 pio31: gpio@fee09000 {
296 gpio-controller; 305 gpio-controller;
297 #gpio-cells = <1>; 306 #gpio-cells = <1>;
298 interrupt-controller; 307 interrupt-controller;
@@ -304,7 +313,7 @@
304 serial2-oe { 313 serial2-oe {
305 pinctrl_serial2_oe: serial2-1 { 314 pinctrl_serial2_oe: serial2-1 {
306 st,pins { 315 st,pins {
307 output-enable = <&PIO11 3 ALT2 OUT>; 316 output-enable = <&pio11 3 ALT2 OUT>;
308 }; 317 };
309 }; 318 };
310 }; 319 };
@@ -312,17 +321,27 @@
312 i2c0 { 321 i2c0 {
313 pinctrl_i2c0_default: i2c0-default { 322 pinctrl_i2c0_default: i2c0-default {
314 st,pins { 323 st,pins {
315 sda = <&PIO9 3 ALT1 BIDIR>; 324 sda = <&pio9 3 ALT1 BIDIR>;
316 scl = <&PIO9 2 ALT1 BIDIR>; 325 scl = <&pio9 2 ALT1 BIDIR>;
326 };
327 };
328 };
329
330 usb {
331 pinctrl_usb0: usb0 {
332 st,pins {
333 oc-detect = <&pio9 4 ALT1 IN>;
334 pwr-enable = <&pio9 5 ALT1 OUT>;
317 }; 335 };
318 }; 336 };
319 }; 337 };
320 338
339
321 i2c1 { 340 i2c1 {
322 pinctrl_i2c1_default: i2c1-default { 341 pinctrl_i2c1_default: i2c1-default {
323 st,pins { 342 st,pins {
324 sda = <&PIO12 1 ALT1 BIDIR>; 343 sda = <&pio12 1 ALT1 BIDIR>;
325 scl = <&PIO12 0 ALT1 BIDIR>; 344 scl = <&pio12 0 ALT1 BIDIR>;
326 }; 345 };
327 }; 346 };
328 }; 347 };
@@ -330,12 +349,12 @@
330 fsm { 349 fsm {
331 pinctrl_fsm: fsm { 350 pinctrl_fsm: fsm {
332 st,pins { 351 st,pins {
333 spi-fsm-clk = <&PIO12 2 ALT1 OUT>; 352 spi-fsm-clk = <&pio12 2 ALT1 OUT>;
334 spi-fsm-cs = <&PIO12 3 ALT1 OUT>; 353 spi-fsm-cs = <&pio12 3 ALT1 OUT>;
335 spi-fsm-mosi = <&PIO12 4 ALT1 OUT>; 354 spi-fsm-mosi = <&pio12 4 ALT1 OUT>;
336 spi-fsm-miso = <&PIO12 5 ALT1 IN>; 355 spi-fsm-miso = <&pio12 5 ALT1 IN>;
337 spi-fsm-hol = <&PIO12 6 ALT1 OUT>; 356 spi-fsm-hol = <&pio12 6 ALT1 OUT>;
338 spi-fsm-wp = <&PIO12 7 ALT1 OUT>; 357 spi-fsm-wp = <&pio12 7 ALT1 OUT>;
339 }; 358 };
340 }; 359 };
341 }; 360 };
@@ -352,7 +371,7 @@
352 interrupt-names = "irqmux"; 371 interrupt-names = "irqmux";
353 ranges = <0 0xfe820000 0x6000>; 372 ranges = <0 0xfe820000 0x6000>;
354 373
355 PIO13: gpio@fe820000 { 374 pio13: gpio@fe820000 {
356 gpio-controller; 375 gpio-controller;
357 #gpio-cells = <1>; 376 #gpio-cells = <1>;
358 interrupt-controller; 377 interrupt-controller;
@@ -360,7 +379,7 @@
360 reg = <0 0x100>; 379 reg = <0 0x100>;
361 st,bank-name = "PIO13"; 380 st,bank-name = "PIO13";
362 }; 381 };
363 PIO14: gpio@fe821000 { 382 pio14: gpio@fe821000 {
364 gpio-controller; 383 gpio-controller;
365 #gpio-cells = <1>; 384 #gpio-cells = <1>;
366 interrupt-controller; 385 interrupt-controller;
@@ -368,7 +387,7 @@
368 reg = <0x1000 0x100>; 387 reg = <0x1000 0x100>;
369 st,bank-name = "PIO14"; 388 st,bank-name = "PIO14";
370 }; 389 };
371 PIO15: gpio@fe822000 { 390 pio15: gpio@fe822000 {
372 gpio-controller; 391 gpio-controller;
373 #gpio-cells = <1>; 392 #gpio-cells = <1>;
374 interrupt-controller; 393 interrupt-controller;
@@ -376,7 +395,7 @@
376 reg = <0x2000 0x100>; 395 reg = <0x2000 0x100>;
377 st,bank-name = "PIO15"; 396 st,bank-name = "PIO15";
378 }; 397 };
379 PIO16: gpio@fe823000 { 398 pio16: gpio@fe823000 {
380 gpio-controller; 399 gpio-controller;
381 #gpio-cells = <1>; 400 #gpio-cells = <1>;
382 interrupt-controller; 401 interrupt-controller;
@@ -384,7 +403,7 @@
384 reg = <0x3000 0x100>; 403 reg = <0x3000 0x100>;
385 st,bank-name = "PIO16"; 404 st,bank-name = "PIO16";
386 }; 405 };
387 PIO17: gpio@fe824000 { 406 pio17: gpio@fe824000 {
388 gpio-controller; 407 gpio-controller;
389 #gpio-cells = <1>; 408 #gpio-cells = <1>;
390 interrupt-controller; 409 interrupt-controller;
@@ -392,7 +411,7 @@
392 reg = <0x4000 0x100>; 411 reg = <0x4000 0x100>;
393 st,bank-name = "PIO17"; 412 st,bank-name = "PIO17";
394 }; 413 };
395 PIO18: gpio@fe825000 { 414 pio18: gpio@fe825000 {
396 gpio-controller; 415 gpio-controller;
397 #gpio-cells = <1>; 416 #gpio-cells = <1>;
398 interrupt-controller; 417 interrupt-controller;
@@ -405,8 +424,8 @@
405 serial2 { 424 serial2 {
406 pinctrl_serial2: serial2-0 { 425 pinctrl_serial2: serial2-0 {
407 st,pins { 426 st,pins {
408 tx = <&PIO17 4 ALT2 OUT>; 427 tx = <&pio17 4 ALT2 OUT>;
409 rx = <&PIO17 5 ALT2 IN>; 428 rx = <&pio17 5 ALT2 IN>;
410 }; 429 };
411 }; 430 };
412 }; 431 };
@@ -414,28 +433,28 @@
414 gmac0 { 433 gmac0 {
415 pinctrl_mii0: mii0 { 434 pinctrl_mii0: mii0 {
416 st,pins { 435 st,pins {
417 mdint = <&PIO13 6 ALT2 IN BYPASS 0>; 436 mdint = <&pio13 6 ALT2 IN BYPASS 0>;
418 txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 437 txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
419 txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 438 txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
420 txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 439 txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
421 txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; 440 txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
422 txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; 441 txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
423 442
424 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; 443 txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
425 txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 444 txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
426 crs = <&PIO15 2 ALT2 IN BYPASS 1000>; 445 crs = <&pio15 2 ALT2 IN BYPASS 1000>;
427 col = <&PIO15 3 ALT2 IN BYPASS 1000>; 446 col = <&pio15 3 ALT2 IN BYPASS 1000>;
428 mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>; 447 mdio= <&pio15 4 ALT2 OUT BYPASS 1500>;
429 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; 448 mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
430 449
431 rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; 450 rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
432 rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; 451 rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
433 rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; 452 rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
434 rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; 453 rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
435 rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; 454 rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
436 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; 455 rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
437 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; 456 rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
438 phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>; 457 phyclk = <&pio13 5 ALT2 OUT NICLK 0 CLK_B>;
439 }; 458 };
440 }; 459 };
441 460
@@ -445,25 +464,79 @@
445 }; 464 };
446 pinctrl_rgmii0: rgmii0 { 465 pinctrl_rgmii0: rgmii0 {
447 st,pins { 466 st,pins {
448 phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>; 467 phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>;
449 txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>; 468 txen = <&pio13 7 ALT2 OUT DE_IO 0 CLK_A>;
450 txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>; 469 txd0 = <&pio14 0 ALT2 OUT DE_IO 500 CLK_A>;
451 txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>; 470 txd1 = <&pio14 1 ALT2 OUT DE_IO 500 CLK_A>;
452 txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>; 471 txd2 = <&pio14 2 ALT2 OUT DE_IO 500 CLK_B>;
453 txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>; 472 txd3 = <&pio14 3 ALT2 OUT DE_IO 500 CLK_B>;
454 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; 473 txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
455 474
456 mdio = <&PIO15 4 ALT2 OUT BYPASS 0>; 475 mdio = <&pio15 4 ALT2 OUT BYPASS 0>;
457 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; 476 mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
458 477
459 rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>; 478 rxdv = <&pio15 6 ALT2 IN DE_IO 500 CLK_A>;
460 rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>; 479 rxd0 =<&pio16 0 ALT2 IN DE_IO 500 CLK_A>;
461 rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>; 480 rxd1 =<&pio16 1 ALT2 IN DE_IO 500 CLK_A>;
462 rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>; 481 rxd2 =<&pio16 2 ALT2 IN DE_IO 500 CLK_A>;
463 rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>; 482 rxd3 =<&pio16 3 ALT2 IN DE_IO 500 CLK_A>;
464 rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>; 483 rxclk =<&pio17 0 ALT2 IN NICLK 0 CLK_A>;
465 484
466 clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>; 485 clk125=<&pio17 6 ALT1 IN NICLK 0 CLK_A>;
486 };
487 };
488 };
489
490 mmc0 {
491 pinctrl_mmc0: mmc0 {
492 st,pins {
493 mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
494 data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>;
495 data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>;
496 data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>;
497 data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>;
498 cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>;
499 wp = <&pio15 3 ALT4 IN>;
500 data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>;
501 data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>;
502 data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>;
503 data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>;
504 pwr = <&pio17 1 ALT4 OUT>;
505 cd = <&pio17 2 ALT4 IN>;
506 led = <&pio17 3 ALT4 OUT>;
507 };
508 };
509 };
510 mmc1 {
511 pinctrl_mmc1: mmc1 {
512 st,pins {
513 mmcclk = <&pio15 0 ALT3 BIDIR_PU NICLK 0 CLK_B>;
514 data0 = <&pio13 7 ALT3 BIDIR_PU BYPASS 0>;
515 data1 = <&pio14 1 ALT3 BIDIR_PU BYPASS 0>;
516 data2 = <&pio14 2 ALT3 BIDIR_PU BYPASS 0>;
517 data3 = <&pio14 3 ALT3 BIDIR_PU BYPASS 0>;
518 cmd = <&pio15 4 ALT3 BIDIR_PU BYPASS 0>;
519 data4 = <&pio15 6 ALT3 BIDIR_PU BYPASS 0>;
520 data5 = <&pio15 7 ALT3 BIDIR_PU BYPASS 0>;
521 data6 = <&pio16 0 ALT3 BIDIR_PU BYPASS 0>;
522 data7 = <&pio16 1 ALT3 BIDIR_PU BYPASS 0>;
523 pwr = <&pio16 2 ALT3 OUT>;
524 nreset = <&pio13 6 ALT3 OUT>;
525 };
526 };
527 };
528
529 usb {
530 pinctrl_usb1: usb1 {
531 st,pins {
532 oc-detect = <&pio18 0 ALT1 IN>;
533 pwr-enable = <&pio18 1 ALT1 OUT>;
534 };
535 };
536 pinctrl_usb2: usb2 {
537 st,pins {
538 oc-detect = <&pio18 2 ALT1 IN>;
539 pwr-enable = <&pio18 3 ALT1 OUT>;
467 }; 540 };
468 }; 541 };
469 }; 542 };
@@ -480,7 +553,7 @@
480 interrupt-names = "irqmux"; 553 interrupt-names = "irqmux";
481 ranges = <0 0xfd6b0000 0x3000>; 554 ranges = <0 0xfd6b0000 0x3000>;
482 555
483 PIO100: gpio@fd6b0000 { 556 pio100: gpio@fd6b0000 {
484 gpio-controller; 557 gpio-controller;
485 #gpio-cells = <1>; 558 #gpio-cells = <1>;
486 interrupt-controller; 559 interrupt-controller;
@@ -488,7 +561,7 @@
488 reg = <0 0x100>; 561 reg = <0 0x100>;
489 st,bank-name = "PIO100"; 562 st,bank-name = "PIO100";
490 }; 563 };
491 PIO101: gpio@fd6b1000 { 564 pio101: gpio@fd6b1000 {
492 gpio-controller; 565 gpio-controller;
493 #gpio-cells = <1>; 566 #gpio-cells = <1>;
494 interrupt-controller; 567 interrupt-controller;
@@ -496,7 +569,7 @@
496 reg = <0x1000 0x100>; 569 reg = <0x1000 0x100>;
497 st,bank-name = "PIO101"; 570 st,bank-name = "PIO101";
498 }; 571 };
499 PIO102: gpio@fd6b2000 { 572 pio102: gpio@fd6b2000 {
500 gpio-controller; 573 gpio-controller;
501 #gpio-cells = <1>; 574 #gpio-cells = <1>;
502 interrupt-controller; 575 interrupt-controller;
@@ -517,7 +590,7 @@
517 interrupt-names = "irqmux"; 590 interrupt-names = "irqmux";
518 ranges = <0 0xfd330000 0x5000>; 591 ranges = <0 0xfd330000 0x5000>;
519 592
520 PIO103: gpio@fd330000 { 593 pio103: gpio@fd330000 {
521 gpio-controller; 594 gpio-controller;
522 #gpio-cells = <1>; 595 #gpio-cells = <1>;
523 interrupt-controller; 596 interrupt-controller;
@@ -525,7 +598,7 @@
525 reg = <0 0x100>; 598 reg = <0 0x100>;
526 st,bank-name = "PIO103"; 599 st,bank-name = "PIO103";
527 }; 600 };
528 PIO104: gpio@fd331000 { 601 pio104: gpio@fd331000 {
529 gpio-controller; 602 gpio-controller;
530 #gpio-cells = <1>; 603 #gpio-cells = <1>;
531 interrupt-controller; 604 interrupt-controller;
@@ -533,7 +606,7 @@
533 reg = <0x1000 0x100>; 606 reg = <0x1000 0x100>;
534 st,bank-name = "PIO104"; 607 st,bank-name = "PIO104";
535 }; 608 };
536 PIO105: gpio@fd332000 { 609 pio105: gpio@fd332000 {
537 gpio-controller; 610 gpio-controller;
538 #gpio-cells = <1>; 611 #gpio-cells = <1>;
539 interrupt-controller; 612 interrupt-controller;
@@ -541,7 +614,7 @@
541 reg = <0x2000 0x100>; 614 reg = <0x2000 0x100>;
542 st,bank-name = "PIO105"; 615 st,bank-name = "PIO105";
543 }; 616 };
544 PIO106: gpio@fd333000 { 617 pio106: gpio@fd333000 {
545 gpio-controller; 618 gpio-controller;
546 #gpio-cells = <1>; 619 #gpio-cells = <1>;
547 interrupt-controller; 620 interrupt-controller;
@@ -550,7 +623,7 @@
550 st,bank-name = "PIO106"; 623 st,bank-name = "PIO106";
551 }; 624 };
552 625
553 PIO107: gpio@fd334000 { 626 pio107: gpio@fd334000 {
554 gpio-controller; 627 gpio-controller;
555 #gpio-cells = <1>; 628 #gpio-cells = <1>;
556 interrupt-controller; 629 interrupt-controller;
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 84758d76d064..fad9073ddeed 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -9,6 +9,8 @@
9#include "stih41x.dtsi" 9#include "stih41x.dtsi"
10#include "stih416-clock.dtsi" 10#include "stih416-clock.dtsi"
11#include "stih416-pinctrl.dtsi" 11#include "stih416-pinctrl.dtsi"
12
13#include <dt-bindings/phy/phy-miphy365x.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/reset-controller/stih416-resets.h> 15#include <dt-bindings/reset-controller/stih416-resets.h>
14/ { 16/ {
@@ -236,5 +238,212 @@
236 resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>, 238 resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>,
237 <&softreset STIH416_KEYSCAN_SOFTRESET>; 239 <&softreset STIH416_KEYSCAN_SOFTRESET>;
238 }; 240 };
241
242 temp0 {
243 compatible = "st,stih416-sas-thermal";
244 clock-names = "thermal";
245 clocks = <&clockgen_c_vcc 14>;
246
247 status = "okay";
248 };
249
250 temp1@fdfe8000 {
251 compatible = "st,stih416-mpe-thermal";
252 reg = <0xfdfe8000 0x10>;
253 clocks = <&clockgen_e 3>;
254 clock-names = "thermal";
255 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
256
257 status = "okay";
258 };
259
260 mmc0: sdhci@fe81e000 {
261 compatible = "st,sdhci";
262 status = "disabled";
263 reg = <0xfe81e000 0x1000>;
264 interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>;
265 interrupt-names = "mmcirq";
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_mmc0>;
268 clock-names = "mmc";
269 clocks = <&clk_s_a1_ls 1>;
270 };
271
272 mmc1: sdhci@fe81f000 {
273 compatible = "st,sdhci";
274 status = "disabled";
275 reg = <0xfe81f000 0x1000>;
276 interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>;
277 interrupt-names = "mmcirq";
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_mmc1>;
280 clock-names = "mmc";
281 clocks = <&clk_s_a1_ls 8>;
282 };
283
284 miphy365x_phy: phy@fe382000 {
285 compatible = "st,miphy365x-phy";
286 st,syscfg = <&syscfg_rear>;
287 #address-cells = <1>;
288 #size-cells = <1>;
289 ranges;
290
291 phy_port0: port@fe382000 {
292 #phy-cells = <1>;
293 reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
294 reg-names = "sata", "pcie", "syscfg";
295 };
296
297 phy_port1: port@fe38a000 {
298 #phy-cells = <1>;
299 reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
300 reg-names = "sata", "pcie", "syscfg";
301 };
302 };
303
304 sata0: sata@fe380000 {
305 compatible = "st,sti-ahci";
306 reg = <0xfe380000 0x1000>;
307 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
308 interrupt-names = "hostc";
309 phys = <&phy_port0 MIPHY_TYPE_SATA>;
310 phy-names = "sata-phy";
311 resets = <&powerdown STIH416_SATA0_POWERDOWN>,
312 <&softreset STIH416_SATA0_SOFTRESET>;
313 reset-names = "pwr-dwn", "sw-rst";
314 clock-names = "ahci_clk";
315 clocks = <&clk_s_a0_ls CLK_ICN_REG>;
316
317 status = "disabled";
318 };
319
320 usb2_phy: phy@0 {
321 compatible = "st,stih416-usb-phy";
322 #phy-cells = <0>;
323 st,syscfg = <&syscfg_rear>;
324 clocks = <&clk_sysin>;
325 clock-names = "osc_phy";
326 };
327
328 ehci0: usb@fe1ffe00 {
329 compatible = "st,st-ehci-300x";
330 reg = <0xfe1ffe00 0x100>;
331 interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_usb0>;
334 clocks = <&clk_s_a1_ls 0>,
335 <&clockgen_b0 0>;
336 clock-names = "ic", "clk48";
337 phys = <&usb2_phy>;
338 phy-names = "usb";
339 resets = <&powerdown STIH416_USB0_POWERDOWN>,
340 <&softreset STIH416_USB0_SOFTRESET>;
341 reset-names = "power", "softreset";
342 };
343
344 ohci0: usb@fe1ffc00 {
345 compatible = "st,st-ohci-300x";
346 reg = <0xfe1ffc00 0x100>;
347 interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
348 clocks = <&clk_s_a1_ls 0>,
349 <&clockgen_b0 0>;
350 clock-names = "ic", "clk48";
351 phys = <&usb2_phy>;
352 phy-names = "usb";
353 status = "okay";
354 resets = <&powerdown STIH416_USB0_POWERDOWN>,
355 <&softreset STIH416_USB0_SOFTRESET>;
356 reset-names = "power", "softreset";
357 };
358
359 ehci1: usb@fe203e00 {
360 compatible = "st,st-ehci-300x";
361 reg = <0xfe203e00 0x100>;
362 interrupts = <GIC_SPI 150 IRQ_TYPE_NONE>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_usb1>;
365 clocks = <&clk_s_a1_ls 0>,
366 <&clockgen_b0 0>;
367 clock-names = "ic", "clk48";
368 phys = <&usb2_phy>;
369 phy-names = "usb";
370 resets = <&powerdown STIH416_USB1_POWERDOWN>,
371 <&softreset STIH416_USB1_SOFTRESET>;
372 reset-names = "power", "softreset";
373 };
374
375 ohci1: usb@fe203c00 {
376 compatible = "st,st-ohci-300x";
377 reg = <0xfe203c00 0x100>;
378 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
379 clocks = <&clk_s_a1_ls 0>,
380 <&clockgen_b0 0>;
381 clock-names = "ic", "clk48";
382 phys = <&usb2_phy>;
383 phy-names = "usb";
384 resets = <&powerdown STIH416_USB1_POWERDOWN>,
385 <&softreset STIH416_USB1_SOFTRESET>;
386 reset-names = "power", "softreset";
387 };
388
389 ehci2: usb@fe303e00 {
390 compatible = "st,st-ehci-300x";
391 reg = <0xfe303e00 0x100>;
392 interrupts = <GIC_SPI 152 IRQ_TYPE_NONE>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&pinctrl_usb2>;
395 clocks = <&clk_s_a1_ls 0>,
396 <&clockgen_b0 0>;
397 clock-names = "ic", "clk48";
398 phys = <&usb2_phy>;
399 phy-names = "usb";
400 resets = <&powerdown STIH416_USB2_POWERDOWN>,
401 <&softreset STIH416_USB2_SOFTRESET>;
402 reset-names = "power", "softreset";
403 };
404
405 ohci2: usb@fe303c00 {
406 compatible = "st,st-ohci-300x";
407 reg = <0xfe303c00 0x100>;
408 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
409 clocks = <&clk_s_a1_ls 0>,
410 <&clockgen_b0 0>;
411 clock-names = "ic", "clk48";
412 phys = <&usb2_phy>;
413 phy-names = "usb";
414 resets = <&powerdown STIH416_USB2_POWERDOWN>,
415 <&softreset STIH416_USB2_SOFTRESET>;
416 reset-names = "power", "softreset";
417 };
418
419 ehci3: usb@fe343e00 {
420 compatible = "st,st-ehci-300x";
421 reg = <0xfe343e00 0x100>;
422 interrupts = <GIC_SPI 154 IRQ_TYPE_NONE>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&pinctrl_usb3>;
425 clocks = <&clk_s_a1_ls 0>,
426 <&clockgen_b0 0>;
427 clock-names = "ic", "clk48";
428 phys = <&usb2_phy>;
429 phy-names = "usb";
430 resets = <&powerdown STIH416_USB3_POWERDOWN>,
431 <&softreset STIH416_USB3_SOFTRESET>;
432 reset-names = "power", "softreset";
433 };
434
435 ohci3: usb@fe343c00 {
436 compatible = "st,st-ohci-300x";
437 reg = <0xfe343c00 0x100>;
438 interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
439 clocks = <&clk_s_a1_ls 0>,
440 <&clockgen_b0 0>;
441 clock-names = "ic", "clk48";
442 phys = <&usb2_phy>;
443 phy-names = "usb";
444 resets = <&powerdown STIH416_USB3_POWERDOWN>,
445 <&softreset STIH416_USB3_SOFTRESET>;
446 reset-names = "power", "softreset";
447 };
239 }; 448 };
240}; 449};
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
index b3dd6ca5c2ae..5f91f455f05b 100644
--- a/arch/arm/boot/dts/stih41x-b2000.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -35,7 +35,7 @@
35 fp_led { 35 fp_led {
36 #gpio-cells = <1>; 36 #gpio-cells = <1>;
37 label = "Front Panel LED"; 37 label = "Front Panel LED";
38 gpios = <&PIO105 7>; 38 gpios = <&pio105 7>;
39 linux,default-trigger = "heartbeat"; 39 linux,default-trigger = "heartbeat";
40 }; 40 };
41 }; 41 };
@@ -55,7 +55,7 @@
55 phy-mode = "mii"; 55 phy-mode = "mii";
56 pinctrl-0 = <&pinctrl_mii0>; 56 pinctrl-0 = <&pinctrl_mii0>;
57 57
58 snps,reset-gpio = <&PIO106 2>; 58 snps,reset-gpio = <&pio106 2>;
59 snps,reset-active-low; 59 snps,reset-active-low;
60 snps,reset-delays-us = <0 10000 10000>; 60 snps,reset-delays-us = <0 10000 10000>;
61 }; 61 };
@@ -65,7 +65,7 @@
65 phy-mode = "mii"; 65 phy-mode = "mii";
66 st,tx-retime-src = "txclk"; 66 st,tx-retime-src = "txclk";
67 67
68 snps,reset-gpio = <&PIO4 7>; 68 snps,reset-gpio = <&pio4 7>;
69 snps,reset-active-low; 69 snps,reset-active-low;
70 snps,reset-delays-us = <0 10000 10000>; 70 snps,reset-delays-us = <0 10000 10000>;
71 }; 71 };
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
index d8a84295c328..487d7d87dbef 100644
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -32,11 +32,11 @@
32 red { 32 red {
33 #gpio-cells = <1>; 33 #gpio-cells = <1>;
34 label = "Front Panel LED"; 34 label = "Front Panel LED";
35 gpios = <&PIO4 1>; 35 gpios = <&pio4 1>;
36 linux,default-trigger = "heartbeat"; 36 linux,default-trigger = "heartbeat";
37 }; 37 };
38 green { 38 green {
39 gpios = <&PIO4 7>; 39 gpios = <&pio4 7>;
40 default-state = "off"; 40 default-state = "off";
41 }; 41 };
42 }; 42 };
@@ -68,11 +68,15 @@
68 phy-mode = "rgmii-id"; 68 phy-mode = "rgmii-id";
69 max-speed = <1000>; 69 max-speed = <1000>;
70 st,tx-retime-src = "clk_125"; 70 st,tx-retime-src = "clk_125";
71 snps,reset-gpio = <&PIO3 0>; 71 snps,reset-gpio = <&pio3 0>;
72 snps,reset-active-low; 72 snps,reset-active-low;
73 snps,reset-delays-us = <0 10000 10000>; 73 snps,reset-delays-us = <0 10000 10000>;
74 74
75 pinctrl-0 = <&pinctrl_rgmii1>; 75 pinctrl-0 = <&pinctrl_rgmii1>;
76 }; 76 };
77
78 mmc0: sdhci@fe81e000 {
79 bus-width = <8>;
80 };
77 }; 81 };
78}; 82};
diff --git a/arch/arm/boot/dts/stih41x-b2020x.dtsi b/arch/arm/boot/dts/stih41x-b2020x.dtsi
index df01c1211b32..f797a0607382 100644
--- a/arch/arm/boot/dts/stih41x-b2020x.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020x.dtsi
@@ -8,6 +8,10 @@
8 */ 8 */
9/ { 9/ {
10 soc { 10 soc {
11 mmc0: sdhci@fe81e000 {
12 status = "okay";
13 };
14
11 spifsm: spifsm@fe902000 { 15 spifsm: spifsm@fe902000 {
12 #address-cells = <1>; 16 #address-cells = <1>;
13 #size-cells = <1>; 17 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
new file mode 100644
index 000000000000..0074bd49797c
--- /dev/null
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -0,0 +1,59 @@
1/*
2 * Copyright (C) 2014 STMicroelectronics (R&D) Limited.
3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9/ {
10 soc {
11 sbc_serial0: serial@9530000 {
12 status = "okay";
13 };
14
15 leds {
16 compatible = "gpio-leds";
17 red {
18 #gpio-cells = <2>;
19 label = "Front Panel LED";
20 gpios = <&pio4 1 0>;
21 linux,default-trigger = "heartbeat";
22 };
23 green {
24 #gpio-cells = <2>;
25 gpios = <&pio1 3 0>;
26 default-state = "off";
27 };
28 };
29
30 i2c@9842000 {
31 status = "okay";
32 };
33
34 i2c@9843000 {
35 status = "okay";
36 };
37
38 i2c@9844000 {
39 status = "okay";
40 };
41
42 i2c@9845000 {
43 status = "okay";
44 };
45
46 i2c@9540000 {
47 status = "okay";
48 };
49
50 /* SSC11 to HDMI */
51 i2c@9541000 {
52 status = "okay";
53 /* HDMI V1.3a supports Standard mode only */
54 clock-frequency = <100000>;
55 st,i2c-min-scl-pulse-width-us = <0>;
56 st,i2c-min-sda-pulse-width-us = <5>;
57 };
58 };
59};
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index 9e99ade35e37..3bcfd81837f0 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * Emilio López <emilio@elopez.com.ar> 4 * Emilio López <emilio@elopez.com.ar>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
index 1763cc7ec023..f3f2974658e4 100644
--- a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
+++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
@@ -1,12 +1,48 @@
1/* 1/*
2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com> 2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
3 * 3 *
4 * The code contained herein is licensed under the GNU General Public 4 * This file is dual-licensed: you can use it either under the terms
5 * License. You may obtain a copy of the GNU General Public License 5 * of the GPL or the X11 license, at your option. Note that this dual
6 * Version 2 or later at the following locations: 6 * licensing only applies to this file, and not this project as a
7 * whole.
7 * 8 *
8 * http://www.opensource.org/licenses/gpl-license.html 9 * a) This file is free software; you can redistribute it and/or
9 * http://www.gnu.org/copyleft/gpl.html 10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
10 */ 46 */
11 47
12/dts-v1/; 48/dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 3ce56bfbc0b5..6a310da53f18 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -2,12 +2,48 @@
2 * Copyright 2012 Stefan Roese 2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de> 3 * Stefan Roese <sr@denx.de>
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * This file is dual-licensed: you can use it either under the terms
6 * License. You may obtain a copy of the GNU General Public License 6 * of the GPL or the X11 license, at your option. Note that this dual
7 * Version 2 or later at the following locations: 7 * licensing only applies to this file, and not this project as a
8 * whole.
8 * 9 *
9 * http://www.opensource.org/licenses/gpl-license.html 10 * a) This file is free software; you can redistribute it and/or
10 * http://www.gnu.org/copyleft/gpl.html 11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public
21 * License along with this file; if not, write to the Free
22 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 * MA 02110-1301 USA
24 *
25 * Or, alternatively,
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use,
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
11 */ 47 */
12 48
13/dts-v1/; 49/dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index 891ea446abae..efc116287e0f 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
index 6b0c37812ade..3e25ee4d3248 100644
--- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * David Lanzendörfer <david.lanzendoerfer@o2s.ch> 4 * David Lanzendörfer <david.lanzendoerfer@o2s.ch>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index b9ecce60f2e7..8b3f97470249 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
index d046d568f5a1..88cf1a531155 100644
--- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
@@ -1,12 +1,48 @@
1/* 1/*
2 * Copyright 2014 - Hans de Goede <hdegoede@redhat.com> 2 * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
3 * 3 *
4 * The code contained herein is licensed under the GNU General Public 4 * This file is dual-licensed: you can use it either under the terms
5 * License. You may obtain a copy of the GNU General Public License 5 * of the GPL or the X11 license, at your option. Note that this dual
6 * Version 2 or later at the following locations: 6 * licensing only applies to this file, and not this project as a
7 * whole.
7 * 8 *
8 * http://www.opensource.org/licenses/gpl-license.html 9 * a) This file is free software; you can redistribute it and/or
9 * http://www.gnu.org/copyleft/gpl.html 10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
10 */ 46 */
11 47
12/dts-v1/; 48/dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
index 6675bcd7860e..ce5994597407 100644
--- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
@@ -2,12 +2,48 @@
2 * Copyright 2014 Zoltan HERPAI 2 * Copyright 2014 Zoltan HERPAI
3 * Zoltan HERPAI <wigyori@uid0.hu> 3 * Zoltan HERPAI <wigyori@uid0.hu>
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * This file is dual-licensed: you can use it either under the terms
6 * License. You may obtain a copy of the GNU General Public License 6 * of the GPL or the X11 license, at your option. Note that this dual
7 * Version 2 or later at the following locations: 7 * licensing only applies to this file, and not this project as a
8 * whole.
8 * 9 *
9 * http://www.opensource.org/licenses/gpl-license.html 10 * a) This file is free software; you can redistribute it and/or
10 * http://www.gnu.org/copyleft/gpl.html 11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public
21 * License along with this file; if not, write to the Free
22 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 * MA 02110-1301 USA
24 *
25 * Or, alternatively,
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use,
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
11 */ 47 */
12 48
13/dts-v1/; 49/dts-v1/;
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index ea9519da5764..fe3c559ca6a8 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
index 43a93762d4f2..1fa2916eafc2 100644
--- a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
@@ -1,12 +1,48 @@
1/* 1/*
2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com> 2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
3 * 3 *
4 * The code contained herein is licensed under the GNU General Public 4 * This file is dual-licensed: you can use it either under the terms
5 * License. You may obtain a copy of the GNU General Public License 5 * of the GPL or the X11 license, at your option. Note that this dual
6 * Version 2 or later at the following locations: 6 * licensing only applies to this file, and not this project as a
7 * whole.
7 * 8 *
8 * http://www.opensource.org/licenses/gpl-license.html 9 * a) This file is free software; you can redistribute it and/or
9 * http://www.gnu.org/copyleft/gpl.html 10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
10 */ 46 */
11 47
12/dts-v1/; 48/dts-v1/;
diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
index 8b3cd0907b32..eeed1f236ee8 100644
--- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
+++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
@@ -6,18 +6,18 @@
6 * licensing only applies to this file, and not this project as a 6 * licensing only applies to this file, and not this project as a
7 * whole. 7 * whole.
8 * 8 *
9 * a) This library is free software; you can redistribute it and/or 9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as 10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the 11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version. 12 * License, or (at your option) any later version.
13 * 13 *
14 * This library is distributed in the hope that it will be useful, 14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public 19 * You should have received a copy of the GNU General Public
20 * License along with this library; if not, write to the Free 20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA 22 * MA 02110-1301 USA
23 * 23 *
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
index fa44b026483b..916ee8bb826f 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
@@ -1,15 +1,49 @@
1/* 1/*
2 * Copyright 2012 Maxime Ripard 2 * Copyright 2012 Maxime Ripard <maxime.ripard@free-electrons.com>
3 * Copyright 2013 Hans de Goede <hdegoede@redhat.com> 3 * Copyright 2013 Hans de Goede <hdegoede@redhat.com>
4 * 4 *
5 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
6 * 9 *
7 * The code contained herein is licensed under the GNU General Public 10 * a) This file is free software; you can redistribute it and/or
8 * License. You may obtain a copy of the GNU General Public License 11 * modify it under the terms of the GNU General Public License as
9 * Version 2 or later at the following locations: 12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
10 * 14 *
11 * http://www.opensource.org/licenses/gpl-license.html 15 * This file is distributed in the hope that it will be useful,
12 * http://www.gnu.org/copyleft/gpl.html 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public
21 * License along with this file; if not, write to the Free
22 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 * MA 02110-1301 USA
24 *
25 * Or, alternatively,
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use,
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
13 */ 47 */
14 48
15/dts-v1/; 49/dts-v1/;
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 429994e1943e..e31d291d14cb 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
index 2bbf8867362b..c74a63a39531 100644
--- a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
+++ b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * Boris Brezillon <boris.brezillon@free-electrons.com> 4 * Boris Brezillon <boris.brezillon@free-electrons.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
index 546cf6eff5c7..c36b4dc89c13 100644
--- a/arch/arm/boot/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
index f142065b3c1f..6e924d9d2912 100644
--- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts
index bc6115da5ae1..3ab544f3af4a 100644
--- a/arch/arm/boot/dts/sun6i-a31-m9.dts
+++ b/arch/arm/boot/dts/sun6i-a31-m9.dts
@@ -1,12 +1,48 @@
1/* 1/*
2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com> 2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
3 * 3 *
4 * The code contained herein is licensed under the GNU General Public 4 * This file is dual-licensed: you can use it either under the terms
5 * License. You may obtain a copy of the GNU General Public License 5 * of the GPL or the X11 license, at your option. Note that this dual
6 * Version 2 or later at the following locations: 6 * licensing only applies to this file, and not this project as a
7 * whole.
7 * 8 *
8 * http://www.opensource.org/licenses/gpl-license.html 9 * a) This file is free software; you can redistribute it and/or
9 * http://www.gnu.org/copyleft/gpl.html 10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
10 */ 46 */
11 47
12/dts-v1/; 48/dts-v1/;
@@ -32,13 +68,40 @@
32 status = "okay"; 68 status = "okay";
33 }; 69 };
34 70
71 usbphy: phy@01c19400 {
72 usb1_vbus-supply = <&reg_usb1_vbus>;
73 status = "okay";
74 };
75
76 ehci0: usb@01c1a000 {
77 status = "okay";
78 };
79
80 ehci1: usb@01c1b000 {
81 status = "okay";
82 };
83
35 pio: pinctrl@01c20800 { 84 pio: pinctrl@01c20800 {
85 led_pins_m9: led_pins@0 {
86 allwinner,pins = "PH13";
87 allwinner,function = "gpio_out";
88 allwinner,drive = <0>;
89 allwinner,pull = <0>;
90 };
91
36 mmc0_cd_pin_m9: mmc0_cd_pin@0 { 92 mmc0_cd_pin_m9: mmc0_cd_pin@0 {
37 allwinner,pins = "PH22"; 93 allwinner,pins = "PH22";
38 allwinner,function = "gpio_in"; 94 allwinner,function = "gpio_in";
39 allwinner,drive = <0>; 95 allwinner,drive = <0>;
40 allwinner,pull = <1>; 96 allwinner,pull = <1>;
41 }; 97 };
98
99 usb1_vbus_pin_m9: usb1_vbus_pin@0 {
100 allwinner,pins = "PC27";
101 allwinner,function = "gpio_out";
102 allwinner,drive = <0>;
103 allwinner,pull = <0>;
104 };
42 }; 105 };
43 106
44 uart0: serial@01c28000 { 107 uart0: serial@01c28000 {
@@ -46,5 +109,35 @@
46 pinctrl-0 = <&uart0_pins_a>; 109 pinctrl-0 = <&uart0_pins_a>;
47 status = "okay"; 110 status = "okay";
48 }; 111 };
112
113 gmac: ethernet@01c30000 {
114 pinctrl-names = "default";
115 pinctrl-0 = <&gmac_pins_mii_a>;
116 phy = <&phy1>;
117 phy-mode = "mii";
118 status = "okay";
119
120 phy1: ethernet-phy@1 {
121 reg = <1>;
122 };
123 };
124 };
125
126 leds {
127 compatible = "gpio-leds";
128 pinctrl-names = "default";
129 pinctrl-0 = <&led_pins_m9>;
130
131 blue {
132 label = "m9:blue:usr";
133 gpios = <&pio 7 13 0>;
134 };
135 };
136
137 reg_usb1_vbus: usb1-vbus {
138 pinctrl-names = "default";
139 pinctrl-0 = <&usb1_vbus_pin_m9>;
140 gpio = <&pio 2 27 0>;
141 status = "okay";
49 }; 142 };
50}; 143};
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 543f895d18d3..529c73803976 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -8,18 +8,18 @@
8 * licensing only applies to this file, and not this project as a 8 * licensing only applies to this file, and not this project as a
9 * whole. 9 * whole.
10 * 10 *
11 * a) This library is free software; you can redistribute it and/or 11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the 13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version. 14 * License, or (at your option) any later version.
15 * 15 *
16 * This library is distributed in the hope that it will be useful, 16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details. 19 * GNU General Public License for more details.
20 * 20 *
21 * You should have received a copy of the GNU General Public 21 * You should have received a copy of the GNU General Public
22 * License along with this library; if not, write to the Free 22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA 24 * MA 02110-1301 USA
25 * 25 *
@@ -132,11 +132,11 @@
132 }; 132 };
133 133
134 pll6: clk@01c20028 { 134 pll6: clk@01c20028 {
135 #clock-cells = <0>; 135 #clock-cells = <1>;
136 compatible = "allwinner,sun6i-a31-pll6-clk"; 136 compatible = "allwinner,sun6i-a31-pll6-clk";
137 reg = <0x01c20028 0x4>; 137 reg = <0x01c20028 0x4>;
138 clocks = <&osc24M>; 138 clocks = <&osc24M>;
139 clock-output-names = "pll6"; 139 clock-output-names = "pll6", "pll6x2";
140 }; 140 };
141 141
142 cpu: cpu@01c20050 { 142 cpu: cpu@01c20050 {
@@ -166,7 +166,7 @@
166 #clock-cells = <0>; 166 #clock-cells = <0>;
167 compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; 167 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
168 reg = <0x01c20054 0x4>; 168 reg = <0x01c20054 0x4>;
169 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; 169 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
170 clock-output-names = "ahb1_mux"; 170 clock-output-names = "ahb1_mux";
171 }; 171 };
172 172
@@ -221,7 +221,7 @@
221 #clock-cells = <0>; 221 #clock-cells = <0>;
222 compatible = "allwinner,sun4i-a10-apb1-mux-clk"; 222 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
223 reg = <0x01c20058 0x4>; 223 reg = <0x01c20058 0x4>;
224 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; 224 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
225 clock-output-names = "apb2_mux"; 225 clock-output-names = "apb2_mux";
226 }; 226 };
227 227
@@ -248,7 +248,7 @@
248 #clock-cells = <0>; 248 #clock-cells = <0>;
249 compatible = "allwinner,sun4i-a10-mod0-clk"; 249 compatible = "allwinner,sun4i-a10-mod0-clk";
250 reg = <0x01c20088 0x4>; 250 reg = <0x01c20088 0x4>;
251 clocks = <&osc24M>, <&pll6>; 251 clocks = <&osc24M>, <&pll6 0>;
252 clock-output-names = "mmc0"; 252 clock-output-names = "mmc0";
253 }; 253 };
254 254
@@ -256,7 +256,7 @@
256 #clock-cells = <0>; 256 #clock-cells = <0>;
257 compatible = "allwinner,sun4i-a10-mod0-clk"; 257 compatible = "allwinner,sun4i-a10-mod0-clk";
258 reg = <0x01c2008c 0x4>; 258 reg = <0x01c2008c 0x4>;
259 clocks = <&osc24M>, <&pll6>; 259 clocks = <&osc24M>, <&pll6 0>;
260 clock-output-names = "mmc1"; 260 clock-output-names = "mmc1";
261 }; 261 };
262 262
@@ -264,7 +264,7 @@
264 #clock-cells = <0>; 264 #clock-cells = <0>;
265 compatible = "allwinner,sun4i-a10-mod0-clk"; 265 compatible = "allwinner,sun4i-a10-mod0-clk";
266 reg = <0x01c20090 0x4>; 266 reg = <0x01c20090 0x4>;
267 clocks = <&osc24M>, <&pll6>; 267 clocks = <&osc24M>, <&pll6 0>;
268 clock-output-names = "mmc2"; 268 clock-output-names = "mmc2";
269 }; 269 };
270 270
@@ -272,7 +272,7 @@
272 #clock-cells = <0>; 272 #clock-cells = <0>;
273 compatible = "allwinner,sun4i-a10-mod0-clk"; 273 compatible = "allwinner,sun4i-a10-mod0-clk";
274 reg = <0x01c20094 0x4>; 274 reg = <0x01c20094 0x4>;
275 clocks = <&osc24M>, <&pll6>; 275 clocks = <&osc24M>, <&pll6 0>;
276 clock-output-names = "mmc3"; 276 clock-output-names = "mmc3";
277 }; 277 };
278 278
@@ -280,7 +280,7 @@
280 #clock-cells = <0>; 280 #clock-cells = <0>;
281 compatible = "allwinner,sun4i-a10-mod0-clk"; 281 compatible = "allwinner,sun4i-a10-mod0-clk";
282 reg = <0x01c200a0 0x4>; 282 reg = <0x01c200a0 0x4>;
283 clocks = <&osc24M>, <&pll6>; 283 clocks = <&osc24M>, <&pll6 0>;
284 clock-output-names = "spi0"; 284 clock-output-names = "spi0";
285 }; 285 };
286 286
@@ -288,7 +288,7 @@
288 #clock-cells = <0>; 288 #clock-cells = <0>;
289 compatible = "allwinner,sun4i-a10-mod0-clk"; 289 compatible = "allwinner,sun4i-a10-mod0-clk";
290 reg = <0x01c200a4 0x4>; 290 reg = <0x01c200a4 0x4>;
291 clocks = <&osc24M>, <&pll6>; 291 clocks = <&osc24M>, <&pll6 0>;
292 clock-output-names = "spi1"; 292 clock-output-names = "spi1";
293 }; 293 };
294 294
@@ -296,7 +296,7 @@
296 #clock-cells = <0>; 296 #clock-cells = <0>;
297 compatible = "allwinner,sun4i-a10-mod0-clk"; 297 compatible = "allwinner,sun4i-a10-mod0-clk";
298 reg = <0x01c200a8 0x4>; 298 reg = <0x01c200a8 0x4>;
299 clocks = <&osc24M>, <&pll6>; 299 clocks = <&osc24M>, <&pll6 0>;
300 clock-output-names = "spi2"; 300 clock-output-names = "spi2";
301 }; 301 };
302 302
@@ -304,7 +304,7 @@
304 #clock-cells = <0>; 304 #clock-cells = <0>;
305 compatible = "allwinner,sun4i-a10-mod0-clk"; 305 compatible = "allwinner,sun4i-a10-mod0-clk";
306 reg = <0x01c200ac 0x4>; 306 reg = <0x01c200ac 0x4>;
307 clocks = <&osc24M>, <&pll6>; 307 clocks = <&osc24M>, <&pll6 0>;
308 clock-output-names = "spi3"; 308 clock-output-names = "spi3";
309 }; 309 };
310 310
@@ -361,6 +361,10 @@
361 clocks = <&ahb1_gates 6>; 361 clocks = <&ahb1_gates 6>;
362 resets = <&ahb1_rst 6>; 362 resets = <&ahb1_rst 6>;
363 #dma-cells = <1>; 363 #dma-cells = <1>;
364
365 /* DMA controller requires AHB1 clocked from PLL6 */
366 assigned-clocks = <&ahb1_mux>;
367 assigned-clock-parents = <&pll6 0>;
364 }; 368 };
365 369
366 mmc0: mmc@01c0f000 { 370 mmc0: mmc@01c0f000 {
@@ -840,7 +844,7 @@
840 ar100: ar100_clk { 844 ar100: ar100_clk {
841 compatible = "allwinner,sun6i-a31-ar100-clk"; 845 compatible = "allwinner,sun6i-a31-ar100-clk";
842 #clock-cells = <0>; 846 #clock-cells = <0>;
843 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; 847 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
844 clock-output-names = "ar100"; 848 clock-output-names = "ar100";
845 }; 849 };
846 850
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
new file mode 100644
index 000000000000..1cf1214cc068
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
@@ -0,0 +1,214 @@
1/*
2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
3 *
4 * Hans de Goede <hdegoede@redhat.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50/dts-v1/;
51/include/ "sun7i-a20.dtsi"
52/include/ "sunxi-common-regulators.dtsi"
53
54/ {
55 model = "LeMaker Banana Pi";
56 compatible = "lemaker,bananapi", "allwinner,sun7i-a20";
57
58 soc@01c00000 {
59 spi0: spi@01c05000 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&spi0_pins_a>;
62 status = "okay";
63 };
64
65 mmc0: mmc@01c0f000 {
66 pinctrl-names = "default";
67 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>;
68 vmmc-supply = <&reg_vcc3v3>;
69 bus-width = <4>;
70 cd-gpios = <&pio 7 10 0>; /* PH10 */
71 cd-inverted;
72 status = "okay";
73 };
74
75 usbphy: phy@01c13400 {
76 usb1_vbus-supply = <&reg_usb1_vbus>;
77 usb2_vbus-supply = <&reg_usb2_vbus>;
78 status = "okay";
79 };
80
81 ehci0: usb@01c14000 {
82 status = "okay";
83 };
84
85 ohci0: usb@01c14400 {
86 status = "okay";
87 };
88
89 ahci: sata@01c18000 {
90 status = "okay";
91 };
92
93 ehci1: usb@01c1c000 {
94 status = "okay";
95 };
96
97 ohci1: usb@01c1c400 {
98 status = "okay";
99 };
100
101 pinctrl@01c20800 {
102 mmc0_cd_pin_bananapi: mmc0_cd_pin@0 {
103 allwinner,pins = "PH10";
104 allwinner,function = "gpio_in";
105 allwinner,drive = <0>;
106 allwinner,pull = <1>;
107 };
108
109 gmac_power_pin_bananapi: gmac_power_pin@0 {
110 allwinner,pins = "PH23";
111 allwinner,function = "gpio_out";
112 allwinner,drive = <0>;
113 allwinner,pull = <0>;
114 };
115
116 led_pins_bananapi: led_pins@0 {
117 allwinner,pins = "PH24";
118 allwinner,function = "gpio_out";
119 allwinner,drive = <0>;
120 allwinner,pull = <0>;
121 };
122 };
123
124 ir0: ir@01c21800 {
125 pinctrl-names = "default";
126 pinctrl-0 = <&ir0_pins_a>;
127 status = "okay";
128 };
129
130 uart0: serial@01c28000 {
131 pinctrl-names = "default";
132 pinctrl-0 = <&uart0_pins_a>;
133 status = "okay";
134 };
135
136 uart3: serial@01c28c00 {
137 pinctrl-names = "default";
138 pinctrl-0 = <&uart3_pins_b>;
139 status = "okay";
140 };
141
142 uart7: serial@01c29c00 {
143 pinctrl-names = "default";
144 pinctrl-0 = <&uart7_pins_a>;
145 status = "okay";
146 };
147
148 i2c0: i2c@01c2ac00 {
149 pinctrl-names = "default";
150 pinctrl-0 = <&i2c0_pins_a>;
151 status = "okay";
152
153 axp209: pmic@34 {
154 compatible = "x-powers,axp209";
155 reg = <0x34>;
156 interrupt-parent = <&nmi_intc>;
157 interrupts = <0 8>;
158
159 interrupt-controller;
160 #interrupt-cells = <1>;
161 };
162 };
163
164 i2c2: i2c@01c2b400 {
165 pinctrl-names = "default";
166 pinctrl-0 = <&i2c2_pins_a>;
167 status = "okay";
168 };
169
170 gmac: ethernet@01c50000 {
171 pinctrl-names = "default";
172 pinctrl-0 = <&gmac_pins_rgmii_a>;
173 phy = <&phy1>;
174 phy-mode = "rgmii";
175 phy-supply = <&reg_gmac_3v3>;
176 status = "okay";
177
178 phy1: ethernet-phy@1 {
179 reg = <1>;
180 };
181 };
182 };
183
184 leds {
185 compatible = "gpio-leds";
186 pinctrl-names = "default";
187 pinctrl-0 = <&led_pins_bananapi>;
188
189 green {
190 label = "bananapi:green:usr";
191 gpios = <&pio 7 24 0>;
192 };
193 };
194
195 reg_usb1_vbus: usb1-vbus {
196 status = "okay";
197 };
198
199 reg_usb2_vbus: usb2-vbus {
200 status = "okay";
201 };
202
203 reg_gmac_3v3: gmac-3v3 {
204 compatible = "regulator-fixed";
205 pinctrl-names = "default";
206 pinctrl-0 = <&gmac_power_pin_bananapi>;
207 regulator-name = "gmac-3v3";
208 regulator-min-microvolt = <3300000>;
209 regulator-max-microvolt = <3300000>;
210 startup-delay-us = <100000>;
211 enable-active-high;
212 gpio = <&pio 7 23 0>;
213 };
214};
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index a6c1a3c717bc..a281d259b9b8 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -40,6 +40,7 @@
40 }; 40 };
41 41
42 usbphy: phy@01c13400 { 42 usbphy: phy@01c13400 {
43 usb0_vbus-supply = <&reg_usb0_vbus>;
43 usb1_vbus-supply = <&reg_usb1_vbus>; 44 usb1_vbus-supply = <&reg_usb1_vbus>;
44 usb2_vbus-supply = <&reg_usb2_vbus>; 45 usb2_vbus-supply = <&reg_usb2_vbus>;
45 status = "okay"; 46 status = "okay";
@@ -92,6 +93,13 @@
92 allwinner,drive = <0>; 93 allwinner,drive = <0>;
93 allwinner,pull = <0>; 94 allwinner,pull = <0>;
94 }; 95 };
96
97 usb0_vbus_pin_a: usb0_vbus_pin@0 {
98 allwinner,pins = "PH17";
99 allwinner,function = "gpio_out";
100 allwinner,drive = <0>;
101 allwinner,pull = <0>;
102 };
95 }; 103 };
96 104
97 pwm: pwm@01c20e00 { 105 pwm: pwm@01c20e00 {
@@ -185,6 +193,12 @@
185 status = "okay"; 193 status = "okay";
186 }; 194 };
187 195
196 reg_usb0_vbus: usb0-vbus {
197 pinctrl-0 = <&usb0_vbus_pin_a>;
198 gpio = <&pio 7 17 0>;
199 status = "okay";
200 };
201
188 reg_usb1_vbus: usb1-vbus { 202 reg_usb1_vbus: usb1-vbus {
189 status = "okay"; 203 status = "okay";
190 }; 204 };
diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
index 6a67712d417a..f38bb1a6656c 100644
--- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
+++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
@@ -1,12 +1,48 @@
1/* 1/*
2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com> 2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
3 * 3 *
4 * The code contained herein is licensed under the GNU General Public 4 * This file is dual-licensed: you can use it either under the terms
5 * License. You may obtain a copy of the GNU General Public License 5 * of the GPL or the X11 license, at your option. Note that this dual
6 * Version 2 or later at the following locations: 6 * licensing only applies to this file, and not this project as a
7 * whole.
7 * 8 *
8 * http://www.opensource.org/licenses/gpl-license.html 9 * a) This file is free software; you can redistribute it and/or
9 * http://www.gnu.org/copyleft/gpl.html 10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
10 */ 46 */
11 47
12/dts-v1/; 48/dts-v1/;
diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts b/arch/arm/boot/dts/sun7i-a20-m3.dts
new file mode 100644
index 000000000000..b8e568c55271
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-m3.dts
@@ -0,0 +1,168 @@
1/*
2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
3 *
4 * Hans de Goede <hdegoede@redhat.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50/dts-v1/;
51/include/ "sun7i-a20.dtsi"
52/include/ "sunxi-common-regulators.dtsi"
53
54/ {
55 model = "Mele M3";
56 compatible = "mele,m3", "allwinner,sun7i-a20";
57
58 soc@01c00000 {
59 mmc0: mmc@01c0f000 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
62 vmmc-supply = <&reg_vcc3v3>;
63 bus-width = <4>;
64 cd-gpios = <&pio 7 1 0>; /* PH1 */
65 cd-inverted;
66 status = "okay";
67 };
68
69 mmc2: mmc@01c11000 {
70 pinctrl-names = "default";
71 pinctrl-0 = <&mmc2_pins_a>;
72 vmmc-supply = <&reg_vcc3v3>;
73 bus-width = <4>;
74 non-removable;
75 status = "okay";
76 };
77
78 usbphy: phy@01c13400 {
79 usb1_vbus-supply = <&reg_usb1_vbus>;
80 usb2_vbus-supply = <&reg_usb2_vbus>;
81 status = "okay";
82 };
83
84 ehci0: usb@01c14000 {
85 status = "okay";
86 };
87
88 ohci0: usb@01c14400 {
89 status = "okay";
90 };
91
92 ehci1: usb@01c1c000 {
93 status = "okay";
94 };
95
96 ohci1: usb@01c1c400 {
97 status = "okay";
98 };
99
100 pinctrl@01c20800 {
101 led_pins_m3: led_pins@0 {
102 allwinner,pins = "PH20";
103 allwinner,function = "gpio_out";
104 allwinner,drive = <0>;
105 allwinner,pull = <0>;
106 };
107 };
108
109 ir0: ir@01c21800 {
110 pinctrl-names = "default";
111 pinctrl-0 = <&ir0_pins_a>;
112 status = "okay";
113 };
114
115 uart0: serial@01c28000 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&uart0_pins_a>;
118 status = "okay";
119 };
120
121 i2c0: i2c@01c2ac00 {
122 pinctrl-names = "default";
123 pinctrl-0 = <&i2c0_pins_a>;
124 status = "okay";
125
126 axp209: pmic@34 {
127 compatible = "x-powers,axp209";
128 reg = <0x34>;
129 interrupt-parent = <&nmi_intc>;
130 interrupts = <0 8>;
131
132 interrupt-controller;
133 #interrupt-cells = <1>;
134 };
135 };
136
137 gmac: ethernet@01c50000 {
138 pinctrl-names = "default";
139 pinctrl-0 = <&gmac_pins_mii_a>;
140 phy = <&phy1>;
141 phy-mode = "mii";
142 status = "okay";
143
144 phy1: ethernet-phy@1 {
145 reg = <1>;
146 };
147 };
148 };
149
150 leds {
151 compatible = "gpio-leds";
152 pinctrl-names = "default";
153 pinctrl-0 = <&led_pins_m3>;
154
155 blue {
156 label = "m3:blue:usr";
157 gpios = <&pio 7 20 0>;
158 };
159 };
160
161 reg_usb1_vbus: usb1-vbus {
162 status = "okay";
163 };
164
165 reg_usb2_vbus: usb2-vbus {
166 status = "okay";
167 };
168};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
index 1eb8175959a6..3f3ff9693992 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
@@ -4,12 +4,48 @@
4 * Copyright 2014 - Hans de Goede <hdegoede@redhat.com> 4 * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
5 * Copyright (c) 2014 FUKAUMI Naoki <naobsd@gmail.com> 5 * Copyright (c) 2014 FUKAUMI Naoki <naobsd@gmail.com>
6 * 6 *
7 * The code contained herein is licensed under the GNU General Public 7 * This file is dual-licensed: you can use it either under the terms
8 * License. You may obtain a copy of the GNU General Public License 8 * of the GPL or the X11 license, at your option. Note that this dual
9 * Version 2 or later at the following locations: 9 * licensing only applies to this file, and not this project as a
10 * whole.
10 * 11 *
11 * http://www.opensource.org/licenses/gpl-license.html 12 * a) This file is free software; you can redistribute it and/or
12 * http://www.gnu.org/copyleft/gpl.html 13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public
23 * License along with this file; if not, write to the Free
24 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
25 * MA 02110-1301 USA
26 *
27 * Or, alternatively,
28 *
29 * b) Permission is hereby granted, free of charge, to any person
30 * obtaining a copy of this software and associated documentation
31 * files (the "Software"), to deal in the Software without
32 * restriction, including without limitation the rights to use,
33 * copy, modify, merge, publish, distribute, sublicense, and/or
34 * sell copies of the Software, and to permit persons to whom the
35 * Software is furnished to do so, subject to the following
36 * conditions:
37 *
38 * The above copyright notice and this permission notice shall be
39 * included in all copies or substantial portions of the Software.
40 *
41 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
42 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
43 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
44 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
45 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
47 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
48 * OTHER DEALINGS IN THE SOFTWARE.
13 */ 49 */
14 50
15/dts-v1/; 51/dts-v1/;
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
new file mode 100644
index 000000000000..ed364d5e755e
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
@@ -0,0 +1,228 @@
1/*
2 * Copyright 2014 - Iain Paton <ipaton0@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49/include/ "sun7i-a20.dtsi"
50/include/ "sunxi-common-regulators.dtsi"
51
52/ {
53 model = "Olimex A20-OLinuXino-LIME2";
54 compatible = "olimex,a20-olinuxino-lime2", "allwinner,sun7i-a20";
55
56 soc@01c00000 {
57 mmc0: mmc@01c0f000 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
60 vmmc-supply = <&reg_vcc3v3>;
61 bus-width = <4>;
62 cd-gpios = <&pio 7 1 0>; /* PH1 */
63 cd-inverted;
64 status = "okay";
65 };
66
67 usbphy: phy@01c13400 {
68 usb1_vbus-supply = <&reg_usb1_vbus>;
69 usb2_vbus-supply = <&reg_usb2_vbus>;
70 status = "okay";
71 };
72
73 ehci0: usb@01c14000 {
74 status = "okay";
75 };
76
77 ohci0: usb@01c14400 {
78 status = "okay";
79 };
80
81 ahci: sata@01c18000 {
82 target-supply = <&reg_ahci_5v>;
83 status = "okay";
84 };
85
86 ehci1: usb@01c1c000 {
87 status = "okay";
88 };
89
90 ohci1: usb@01c1c400 {
91 status = "okay";
92 };
93
94 pinctrl@01c20800 {
95 ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
96 allwinner,pins = "PC3";
97 allwinner,function = "gpio_out";
98 allwinner,drive = <0>;
99 allwinner,pull = <0>;
100 };
101
102 led_pins_olinuxinolime: led_pins@0 {
103 allwinner,pins = "PH2";
104 allwinner,function = "gpio_out";
105 allwinner,drive = <1>;
106 allwinner,pull = <0>;
107 };
108 };
109
110 uart0: serial@01c28000 {
111 pinctrl-names = "default";
112 pinctrl-0 = <&uart0_pins_a>;
113 status = "okay";
114 };
115
116 i2c0: i2c@01c2ac00 {
117 pinctrl-names = "default";
118 pinctrl-0 = <&i2c0_pins_a>;
119 status = "okay";
120
121 axp209: pmic@34 {
122 compatible = "x-powers,axp209";
123 reg = <0x34>;
124 interrupt-parent = <&nmi_intc>;
125 interrupts = <0 8>;
126
127 interrupt-controller;
128 #interrupt-cells = <1>;
129
130 acin-supply = <&reg_axp_ipsout>;
131 vin2-supply = <&reg_axp_ipsout>;
132 vin3-supply = <&reg_axp_ipsout>;
133 ldo24in-supply = <&reg_axp_ipsout>;
134 ldo3in-supply = <&reg_axp_ipsout>;
135
136 regulators {
137 vdd_rtc: ldo1 {
138 regulator-min-microvolt = <1300000>;
139 regulator-max-microvolt = <1300000>;
140 regulator-always-on;
141 };
142
143 avcc: ldo2 {
144 regulator-min-microvolt = <1800000>;
145 regulator-max-microvolt = <3300000>;
146 regulator-always-on;
147 };
148
149 vcc_csi0: ldo3 {
150 regulator-min-microvolt = <700000>;
151 regulator-max-microvolt = <3500000>;
152 regulator-always-on;
153 };
154
155 vcc_csi1: ldo4 {
156 regulator-min-microvolt = <1250000>;
157 regulator-max-microvolt = <3300000>;
158 regulator-always-on;
159 };
160
161 vdd_cpu: dcdc2 {
162 regulator-min-microvolt = <700000>;
163 regulator-max-microvolt = <2275000>;
164 regulator-always-on;
165 };
166
167 vdd_int: dcdc3 {
168 regulator-min-microvolt = <700000>;
169 regulator-max-microvolt = <3500000>;
170 regulator-always-on;
171 };
172 };
173 };
174 };
175
176 i2c1: i2c@01c2b000 {
177 pinctrl-names = "default";
178 pinctrl-0 = <&i2c1_pins_a>;
179 status = "okay";
180 };
181
182 gmac: ethernet@01c50000 {
183 pinctrl-names = "default";
184 pinctrl-0 = <&gmac_pins_rgmii_a>;
185 phy = <&phy1>;
186 phy-mode = "rgmii";
187 status = "okay";
188
189 phy1: ethernet-phy@1 {
190 reg = <1>;
191 };
192 };
193 };
194
195 leds {
196 compatible = "gpio-leds";
197 pinctrl-names = "default";
198 pinctrl-0 = <&led_pins_olinuxinolime>;
199
200 green {
201 label = "a20-olinuxino-lime2:green:usr";
202 gpios = <&pio 7 2 0>;
203 default-state = "on";
204 };
205 };
206
207 reg_ahci_5v: ahci-5v {
208 pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
209 gpio = <&pio 2 3 0>;
210 status = "okay";
211 };
212
213 reg_usb1_vbus: usb1-vbus {
214 status = "okay";
215 };
216
217 reg_usb2_vbus: usb2-vbus {
218 status = "okay";
219 };
220
221 reg_axp_ipsout: axp_ipsout {
222 compatible = "regulator-fixed";
223 regulator-name = "axp-ipsout";
224 regulator-min-microvolt = <5000000>;
225 regulator-max-microvolt = <5000000>;
226 regulator-always-on;
227 };
228};
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
index 046dfc0d45d8..8dca49b2477b 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
@@ -2,12 +2,48 @@
2 * Copyright 2014 Zoltan HERPAI 2 * Copyright 2014 Zoltan HERPAI
3 * Zoltan HERPAI <wigyori@uid0.hu> 3 * Zoltan HERPAI <wigyori@uid0.hu>
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * This file is dual-licensed: you can use it either under the terms
6 * License. You may obtain a copy of the GNU General Public License 6 * of the GPL or the X11 license, at your option. Note that this dual
7 * Version 2 or later at the following locations: 7 * licensing only applies to this file, and not this project as a
8 * whole.
8 * 9 *
9 * http://www.opensource.org/licenses/gpl-license.html 10 * a) This file is free software; you can redistribute it and/or
10 * http://www.gnu.org/copyleft/gpl.html 11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public
21 * License along with this file; if not, write to the Free
22 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 * MA 02110-1301 USA
24 *
25 * Or, alternatively,
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use,
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
11 */ 47 */
12 48
13/dts-v1/; 49/dts-v1/;
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 82097c905c48..d7135f5282bc 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -8,18 +8,18 @@
8 * licensing only applies to this file, and not this project as a 8 * licensing only applies to this file, and not this project as a
9 * whole. 9 * whole.
10 * 10 *
11 * a) This library is free software; you can redistribute it and/or 11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the 13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version. 14 * License, or (at your option) any later version.
15 * 15 *
16 * This library is distributed in the hope that it will be useful, 16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details. 19 * GNU General Public License for more details.
20 * 20 *
21 * You should have received a copy of the GNU General Public 21 * You should have received a copy of the GNU General Public
22 * License along with this library; if not, write to the Free 22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA 24 * MA 02110-1301 USA
25 * 25 *
@@ -552,8 +552,8 @@
552 reg-names = "phy_ctrl", "pmu1", "pmu2"; 552 reg-names = "phy_ctrl", "pmu1", "pmu2";
553 clocks = <&usb_clk 8>; 553 clocks = <&usb_clk 8>;
554 clock-names = "usb_phy"; 554 clock-names = "usb_phy";
555 resets = <&usb_clk 1>, <&usb_clk 2>; 555 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
556 reset-names = "usb1_reset", "usb2_reset"; 556 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
557 status = "disabled"; 557 status = "disabled";
558 }; 558 };
559 559
@@ -677,6 +677,13 @@
677 allwinner,pull = <0>; 677 allwinner,pull = <0>;
678 }; 678 };
679 679
680 uart3_pins_b: uart3@1 {
681 allwinner,pins = "PH0", "PH1";
682 allwinner,function = "uart3";
683 allwinner,drive = <0>;
684 allwinner,pull = <0>;
685 };
686
680 uart4_pins_a: uart4@0 { 687 uart4_pins_a: uart4@0 {
681 allwinner,pins = "PG10", "PG11"; 688 allwinner,pins = "PG10", "PG11";
682 allwinner,function = "uart4"; 689 allwinner,function = "uart4";
@@ -784,6 +791,13 @@
784 allwinner,pull = <0>; 791 allwinner,pull = <0>;
785 }; 792 };
786 793
794 spi0_pins_a: spi0@0 {
795 allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14";
796 allwinner,function = "spi0";
797 allwinner,drive = <0>;
798 allwinner,pull = <0>;
799 };
800
787 spi1_pins_a: spi1@0 { 801 spi1_pins_a: spi1@0 {
788 allwinner,pins = "PI16", "PI17", "PI18", "PI19"; 802 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
789 allwinner,function = "spi1"; 803 allwinner,function = "spi1";
@@ -819,6 +833,13 @@
819 allwinner,pull = <1>; 833 allwinner,pull = <1>;
820 }; 834 };
821 835
836 mmc2_pins_a: mmc2@0 {
837 allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11";
838 allwinner,function = "mmc2";
839 allwinner,drive = <2>;
840 allwinner,pull = <1>;
841 };
842
822 mmc3_pins_a: mmc3@0 { 843 mmc3_pins_a: mmc3@0 {
823 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; 844 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
824 allwinner,function = "mmc3"; 845 allwinner,function = "mmc3";
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
index e9b8cca8dcc1..7f2117ce6985 100644
--- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * Chen-Yu Tsai <wens@csie.org> 4 * Chen-Yu Tsai <wens@csie.org>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 6146ef15efbe..6086adbf9d74 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -8,18 +8,18 @@
8 * licensing only applies to this file, and not this project as a 8 * licensing only applies to this file, and not this project as a
9 * whole. 9 * whole.
10 * 10 *
11 * a) This library is free software; you can redistribute it and/or 11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the 13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version. 14 * License, or (at your option) any later version.
15 * 15 *
16 * This library is distributed in the hope that it will be useful, 16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details. 19 * GNU General Public License for more details.
20 * 20 *
21 * You should have received a copy of the GNU General Public 21 * You should have received a copy of the GNU General Public
22 * License along with this library; if not, write to the Free 22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA 24 * MA 02110-1301 USA
25 * 25 *
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
new file mode 100644
index 000000000000..506948f582ee
--- /dev/null
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -0,0 +1,119 @@
1/*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50/dts-v1/;
51/include/ "sun9i-a80.dtsi"
52
53/ {
54 model = "Merrii A80 Optimus Board";
55 compatible = "merrii,a80-optimus", "allwinner,sun9i-a80";
56
57 chosen {
58 bootargs = "earlyprintk console=ttyS0,115200";
59 };
60
61 soc {
62 pio: pinctrl@06000800 {
63 i2c3_pins_a: i2c3@0 {
64 /* Enable internal pull-up */
65 allwinner,pull = <1>;
66 };
67
68 led_pins_optimus: led-pins@0 {
69 allwinner,pins = "PH0", "PH1";
70 allwinner,function = "gpio_out";
71 allwinner,drive = <0>;
72 allwinner,pull = <0>;
73 };
74
75 uart4_pins_a: uart4@0 {
76 /* Enable internal pull-up */
77 allwinner,pull = <1>;
78 };
79 };
80
81 uart0: serial@07000000 {
82 pinctrl-names = "default";
83 pinctrl-0 = <&uart0_pins_a>;
84 status = "okay";
85 };
86
87 uart4: serial@07001000 {
88 pinctrl-names = "default";
89 pinctrl-0 = <&uart4_pins_a>;
90 status = "okay";
91 };
92
93 i2c3: i2c@07003400 {
94 pinctrl-names = "default";
95 pinctrl-0 = <&i2c3_pins_a>;
96 status = "okay";
97 };
98 };
99
100 leds {
101 compatible = "gpio-leds";
102 pinctrl-names = "default";
103 pinctrl-0 = <&led_pins_optimus>;
104
105 /* The LED names match those found on the board */
106
107 led2 {
108 label = "optimus:led2:usr";
109 gpios = <&pio 7 1 0>;
110 };
111
112 /* led3 is on PM15, in R_PIO */
113
114 led4 {
115 label = "optimus:led4:usr";
116 gpios = <&pio 7 0 0>;
117 };
118 };
119};
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
new file mode 100644
index 000000000000..494714f67b57
--- /dev/null
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -0,0 +1,514 @@
1/*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50/include/ "skeleton64.dtsi"
51
52/ {
53 interrupt-parent = <&gic>;
54
55 aliases {
56 serial0 = &uart0;
57 serial1 = &uart1;
58 serial2 = &uart2;
59 serial3 = &uart3;
60 serial4 = &uart4;
61 serial5 = &uart5;
62 serial6 = &r_uart;
63 };
64
65 cpus {
66 #address-cells = <1>;
67 #size-cells = <0>;
68
69 cpu0: cpu@0 {
70 compatible = "arm,cortex-a7";
71 device_type = "cpu";
72 reg = <0x0>;
73 };
74
75 cpu1: cpu@1 {
76 compatible = "arm,cortex-a7";
77 device_type = "cpu";
78 reg = <0x1>;
79 };
80
81 cpu2: cpu@2 {
82 compatible = "arm,cortex-a7";
83 device_type = "cpu";
84 reg = <0x2>;
85 };
86
87 cpu3: cpu@3 {
88 compatible = "arm,cortex-a7";
89 device_type = "cpu";
90 reg = <0x3>;
91 };
92
93 cpu4: cpu@100 {
94 compatible = "arm,cortex-a15";
95 device_type = "cpu";
96 reg = <0x100>;
97 };
98
99 cpu5: cpu@101 {
100 compatible = "arm,cortex-a15";
101 device_type = "cpu";
102 reg = <0x101>;
103 };
104
105 cpu6: cpu@102 {
106 compatible = "arm,cortex-a15";
107 device_type = "cpu";
108 reg = <0x102>;
109 };
110
111 cpu7: cpu@103 {
112 compatible = "arm,cortex-a15";
113 device_type = "cpu";
114 reg = <0x103>;
115 };
116 };
117
118 memory {
119 /* 8GB max. with LPAE */
120 reg = <0 0x20000000 0x02 0>;
121 };
122
123 clocks {
124 #address-cells = <1>;
125 #size-cells = <1>;
126 /*
127 * map 64 bit address range down to 32 bits,
128 * as the peripherals are all under 512MB.
129 */
130 ranges = <0 0 0 0x20000000>;
131
132 osc24M: osc24M_clk {
133 #clock-cells = <0>;
134 compatible = "fixed-clock";
135 clock-frequency = <24000000>;
136 clock-output-names = "osc24M";
137 };
138
139 osc32k: osc32k_clk {
140 #clock-cells = <0>;
141 compatible = "fixed-clock";
142 clock-frequency = <32768>;
143 clock-output-names = "osc32k";
144 };
145
146 pll4: clk@0600000c {
147 #clock-cells = <0>;
148 compatible = "allwinner,sun9i-a80-pll4-clk";
149 reg = <0x0600000c 0x4>;
150 clocks = <&osc24M>;
151 clock-output-names = "pll4";
152 };
153
154 pll12: clk@0600002c {
155 #clock-cells = <0>;
156 compatible = "allwinner,sun9i-a80-pll4-clk";
157 reg = <0x0600002c 0x4>;
158 clocks = <&osc24M>;
159 clock-output-names = "pll12";
160 };
161
162 gt_clk: clk@0600005c {
163 #clock-cells = <0>;
164 compatible = "allwinner,sun9i-a80-gt-clk";
165 reg = <0x0600005c 0x4>;
166 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
167 clock-output-names = "gt";
168 };
169
170 ahb0: clk@06000060 {
171 #clock-cells = <0>;
172 compatible = "allwinner,sun9i-a80-ahb-clk";
173 reg = <0x06000060 0x4>;
174 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
175 clock-output-names = "ahb0";
176 };
177
178 ahb1: clk@06000064 {
179 #clock-cells = <0>;
180 compatible = "allwinner,sun9i-a80-ahb-clk";
181 reg = <0x06000064 0x4>;
182 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
183 clock-output-names = "ahb1";
184 };
185
186 ahb2: clk@06000068 {
187 #clock-cells = <0>;
188 compatible = "allwinner,sun9i-a80-ahb-clk";
189 reg = <0x06000068 0x4>;
190 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
191 clock-output-names = "ahb2";
192 };
193
194 apb0: clk@06000070 {
195 #clock-cells = <0>;
196 compatible = "allwinner,sun9i-a80-apb0-clk";
197 reg = <0x06000070 0x4>;
198 clocks = <&osc24M>, <&pll4>;
199 clock-output-names = "apb0";
200 };
201
202 apb1: clk@06000074 {
203 #clock-cells = <0>;
204 compatible = "allwinner,sun9i-a80-apb1-clk";
205 reg = <0x06000074 0x4>;
206 clocks = <&osc24M>, <&pll4>;
207 clock-output-names = "apb1";
208 };
209
210 cci400_clk: clk@06000078 {
211 #clock-cells = <0>;
212 compatible = "allwinner,sun9i-a80-gt-clk";
213 reg = <0x06000078 0x4>;
214 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
215 clock-output-names = "cci400";
216 };
217
218 ahb0_gates: clk@06000580 {
219 #clock-cells = <1>;
220 compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
221 reg = <0x06000580 0x4>;
222 clocks = <&ahb0>;
223 clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
224 "ahb0_ss", "ahb0_sd", "ahb0_nand1",
225 "ahb0_nand0", "ahb0_sdram",
226 "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
227 "ahb0_spi0","ahb0_spi1", "ahb0_spi2",
228 "ahb0_spi3";
229 };
230
231 ahb1_gates: clk@06000584 {
232 #clock-cells = <1>;
233 compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
234 reg = <0x06000584 0x4>;
235 clocks = <&ahb1>;
236 clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
237 "ahb1_gmac", "ahb1_msgbox",
238 "ahb1_spinlock", "ahb1_hstimer",
239 "ahb1_dma";
240 };
241
242 ahb2_gates: clk@06000588 {
243 #clock-cells = <1>;
244 compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
245 reg = <0x06000588 0x4>;
246 clocks = <&ahb2>;
247 clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
248 "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
249 "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
250 };
251
252 apb0_gates: clk@06000590 {
253 #clock-cells = <1>;
254 compatible = "allwinner,sun9i-a80-apb0-gates-clk";
255 reg = <0x06000590 0x4>;
256 clocks = <&apb0>;
257 clock-output-names = "apb0_spdif", "apb0_pio",
258 "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
259 "apb0_lradc", "apb0_gpadc", "apb0_twd",
260 "apb0_cirtx";
261 };
262
263 apb1_gates: clk@06000594 {
264 #clock-cells = <1>;
265 compatible = "allwinner,sun9i-a80-apb1-gates-clk";
266 reg = <0x06000594 0x4>;
267 clocks = <&apb1>;
268 clock-output-names = "apb1_i2c0", "apb1_i2c1",
269 "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
270 "apb1_uart0", "apb1_uart1",
271 "apb1_uart2", "apb1_uart3",
272 "apb1_uart4", "apb1_uart5";
273 };
274 };
275
276 soc {
277 compatible = "simple-bus";
278 #address-cells = <1>;
279 #size-cells = <1>;
280 /*
281 * map 64 bit address range down to 32 bits,
282 * as the peripherals are all under 512MB.
283 */
284 ranges = <0 0 0 0x20000000>;
285
286 gic: interrupt-controller@01c41000 {
287 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
288 reg = <0x01c41000 0x1000>,
289 <0x01c42000 0x1000>,
290 <0x01c44000 0x2000>,
291 <0x01c46000 0x2000>;
292 interrupt-controller;
293 #interrupt-cells = <3>;
294 interrupts = <1 9 0xf04>;
295 };
296
297 ahb0_resets: reset@060005a0 {
298 #reset-cells = <1>;
299 compatible = "allwinner,sun6i-a31-clock-reset";
300 reg = <0x060005a0 0x4>;
301 };
302
303 ahb1_resets: reset@060005a4 {
304 #reset-cells = <1>;
305 compatible = "allwinner,sun6i-a31-clock-reset";
306 reg = <0x060005a4 0x4>;
307 };
308
309 ahb2_resets: reset@060005a8 {
310 #reset-cells = <1>;
311 compatible = "allwinner,sun6i-a31-clock-reset";
312 reg = <0x060005a8 0x4>;
313 };
314
315 apb0_resets: reset@060005b0 {
316 #reset-cells = <1>;
317 compatible = "allwinner,sun6i-a31-clock-reset";
318 reg = <0x060005b0 0x4>;
319 };
320
321 apb1_resets: reset@060005b4 {
322 #reset-cells = <1>;
323 compatible = "allwinner,sun6i-a31-clock-reset";
324 reg = <0x060005b4 0x4>;
325 };
326
327 timer@06000c00 {
328 compatible = "allwinner,sun4i-a10-timer";
329 reg = <0x06000c00 0xa0>;
330 interrupts = <0 18 4>,
331 <0 19 4>,
332 <0 20 4>,
333 <0 21 4>,
334 <0 22 4>,
335 <0 23 4>;
336
337 clocks = <&osc24M>;
338 };
339
340 pio: pinctrl@06000800 {
341 compatible = "allwinner,sun9i-a80-pinctrl";
342 reg = <0x06000800 0x400>;
343 interrupts = <0 11 4>,
344 <0 15 4>,
345 <0 16 4>,
346 <0 17 4>,
347 <0 120 4>;
348 clocks = <&apb0_gates 5>;
349 gpio-controller;
350 interrupt-controller;
351 #interrupt-cells = <2>;
352 #size-cells = <0>;
353 #gpio-cells = <3>;
354
355 i2c3_pins_a: i2c3@0 {
356 allwinner,pins = "PG10", "PG11";
357 allwinner,function = "i2c3";
358 allwinner,drive = <0>;
359 allwinner,pull = <0>;
360 };
361
362 uart0_pins_a: uart0@0 {
363 allwinner,pins = "PH12", "PH13";
364 allwinner,function = "uart0";
365 allwinner,drive = <0>;
366 allwinner,pull = <0>;
367 };
368
369 uart4_pins_a: uart4@0 {
370 allwinner,pins = "PG12", "PG13", "PG14", "PG15";
371 allwinner,function = "uart4";
372 allwinner,drive = <0>;
373 allwinner,pull = <0>;
374 };
375 };
376
377 uart0: serial@07000000 {
378 compatible = "snps,dw-apb-uart";
379 reg = <0x07000000 0x400>;
380 interrupts = <0 0 4>;
381 reg-shift = <2>;
382 reg-io-width = <4>;
383 clocks = <&apb1_gates 16>;
384 resets = <&apb1_resets 16>;
385 status = "disabled";
386 };
387
388 uart1: serial@07000400 {
389 compatible = "snps,dw-apb-uart";
390 reg = <0x07000400 0x400>;
391 interrupts = <0 1 4>;
392 reg-shift = <2>;
393 reg-io-width = <4>;
394 clocks = <&apb1_gates 17>;
395 resets = <&apb1_resets 17>;
396 status = "disabled";
397 };
398
399 uart2: serial@07000800 {
400 compatible = "snps,dw-apb-uart";
401 reg = <0x07000800 0x400>;
402 interrupts = <0 2 4>;
403 reg-shift = <2>;
404 reg-io-width = <4>;
405 clocks = <&apb1_gates 18>;
406 resets = <&apb1_resets 18>;
407 status = "disabled";
408 };
409
410 uart3: serial@07000c00 {
411 compatible = "snps,dw-apb-uart";
412 reg = <0x07000c00 0x400>;
413 interrupts = <0 3 4>;
414 reg-shift = <2>;
415 reg-io-width = <4>;
416 clocks = <&apb1_gates 19>;
417 resets = <&apb1_resets 19>;
418 status = "disabled";
419 };
420
421 uart4: serial@07001000 {
422 compatible = "snps,dw-apb-uart";
423 reg = <0x07001000 0x400>;
424 interrupts = <0 4 4>;
425 reg-shift = <2>;
426 reg-io-width = <4>;
427 clocks = <&apb1_gates 20>;
428 resets = <&apb1_resets 20>;
429 status = "disabled";
430 };
431
432 uart5: serial@07001400 {
433 compatible = "snps,dw-apb-uart";
434 reg = <0x07001400 0x400>;
435 interrupts = <0 5 4>;
436 reg-shift = <2>;
437 reg-io-width = <4>;
438 clocks = <&apb1_gates 21>;
439 resets = <&apb1_resets 21>;
440 status = "disabled";
441 };
442
443 i2c0: i2c@07002800 {
444 compatible = "allwinner,sun6i-a31-i2c";
445 reg = <0x07002800 0x400>;
446 interrupts = <0 6 4>;
447 clocks = <&apb1_gates 0>;
448 resets = <&apb1_resets 0>;
449 status = "disabled";
450 #address-cells = <1>;
451 #size-cells = <0>;
452 };
453
454 i2c1: i2c@07002c00 {
455 compatible = "allwinner,sun6i-a31-i2c";
456 reg = <0x07002c00 0x400>;
457 interrupts = <0 7 4>;
458 clocks = <&apb1_gates 1>;
459 resets = <&apb1_resets 1>;
460 status = "disabled";
461 #address-cells = <1>;
462 #size-cells = <0>;
463 };
464
465 i2c2: i2c@07003000 {
466 compatible = "allwinner,sun6i-a31-i2c";
467 reg = <0x07003000 0x400>;
468 interrupts = <0 8 4>;
469 clocks = <&apb1_gates 2>;
470 resets = <&apb1_resets 2>;
471 status = "disabled";
472 #address-cells = <1>;
473 #size-cells = <0>;
474 };
475
476 i2c3: i2c@07003400 {
477 compatible = "allwinner,sun6i-a31-i2c";
478 reg = <0x07003400 0x400>;
479 interrupts = <0 9 4>;
480 clocks = <&apb1_gates 3>;
481 resets = <&apb1_resets 3>;
482 status = "disabled";
483 #address-cells = <1>;
484 #size-cells = <0>;
485 };
486
487 i2c4: i2c@07003800 {
488 compatible = "allwinner,sun6i-a31-i2c";
489 reg = <0x07003800 0x400>;
490 interrupts = <0 10 4>;
491 clocks = <&apb1_gates 4>;
492 resets = <&apb1_resets 4>;
493 status = "disabled";
494 #address-cells = <1>;
495 #size-cells = <0>;
496 };
497
498 r_wdt: watchdog@08001000 {
499 compatible = "allwinner,sun6i-a31-wdt";
500 reg = <0x08001000 0x20>;
501 interrupts = <0 36 4>;
502 };
503
504 r_uart: serial@08002800 {
505 compatible = "snps,dw-apb-uart";
506 reg = <0x08002800 0x400>;
507 interrupts = <0 38 4>;
508 reg-shift = <2>;
509 reg-io-width = <4>;
510 clocks = <&osc24M>;
511 status = "disabled";
512 };
513 };
514};
diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
index c9c5b10e03eb..d8876634f965 100644
--- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi
+++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
@@ -3,12 +3,48 @@
3 * 3 *
4 * Copyright 2014 - Hans de Goede <hdegoede@redhat.com> 4 * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/ { 50/ {
@@ -21,6 +57,13 @@
21 allwinner,pull = <0>; 57 allwinner,pull = <0>;
22 }; 58 };
23 59
60 usb0_vbus_pin_a: usb0_vbus_pin@0 {
61 allwinner,pins = "PB9";
62 allwinner,function = "gpio_out";
63 allwinner,drive = <0>;
64 allwinner,pull = <0>;
65 };
66
24 usb1_vbus_pin_a: usb1_vbus_pin@0 { 67 usb1_vbus_pin_a: usb1_vbus_pin@0 {
25 allwinner,pins = "PH6"; 68 allwinner,pins = "PH6";
26 allwinner,function = "gpio_out"; 69 allwinner,function = "gpio_out";
@@ -44,11 +87,24 @@
44 regulator-name = "ahci-5v"; 87 regulator-name = "ahci-5v";
45 regulator-min-microvolt = <5000000>; 88 regulator-min-microvolt = <5000000>;
46 regulator-max-microvolt = <5000000>; 89 regulator-max-microvolt = <5000000>;
90 regulator-boot-on;
47 enable-active-high; 91 enable-active-high;
48 gpio = <&pio 1 8 0>; 92 gpio = <&pio 1 8 0>;
49 status = "disabled"; 93 status = "disabled";
50 }; 94 };
51 95
96 reg_usb0_vbus: usb0-vbus {
97 compatible = "regulator-fixed";
98 pinctrl-names = "default";
99 pinctrl-0 = <&usb0_vbus_pin_a>;
100 regulator-name = "usb0-vbus";
101 regulator-min-microvolt = <5000000>;
102 regulator-max-microvolt = <5000000>;
103 enable-active-high;
104 gpio = <&pio 1 9 0>;
105 status = "disabled";
106 };
107
52 reg_usb1_vbus: usb1-vbus { 108 reg_usb1_vbus: usb1-vbus {
53 compatible = "regulator-fixed"; 109 compatible = "regulator-fixed";
54 pinctrl-names = "default"; 110 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 206379546244..dcc6c75553a4 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -187,7 +187,7 @@
187 187
188 /* ALS and Proximity sensor */ 188 /* ALS and Proximity sensor */
189 isl29028@44 { 189 isl29028@44 {
190 compatible = "isil,isl29028"; 190 compatible = "isl,isl29028";
191 reg = <0x44>; 191 reg = <0x44>;
192 interrupt-parent = <&gpio>; 192 interrupt-parent = <&gpio>;
193 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>; 193 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 24036c440440..ce2ef5bec4f2 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -30,7 +30,6 @@
30 /* kHz uV */ 30 /* kHz uV */
31 666667 1000000 31 666667 1000000
32 333334 1000000 32 333334 1000000
33 222223 1000000
34 >; 33 >;
35 }; 34 };
36 35
@@ -65,7 +64,7 @@
65 interrupt-parent = <&intc>; 64 interrupt-parent = <&intc>;
66 ranges; 65 ranges;
67 66
68 adc@f8007100 { 67 adc: adc@f8007100 {
69 compatible = "xlnx,zynq-xadc-1.00.a"; 68 compatible = "xlnx,zynq-xadc-1.00.a";
70 reg = <0xf8007100 0x20>; 69 reg = <0xf8007100 0x20>;
71 interrupts = <0 7 4>; 70 interrupts = <0 7 4>;
@@ -137,7 +136,7 @@
137 <0xF8F00100 0x100>; 136 <0xF8F00100 0x100>;
138 }; 137 };
139 138
140 L2: cache-controller { 139 L2: cache-controller@f8f02000 {
141 compatible = "arm,pl310-cache"; 140 compatible = "arm,pl310-cache";
142 reg = <0xF8F02000 0x1000>; 141 reg = <0xF8F02000 0x1000>;
143 arm,data-latency = <3 2 2>; 142 arm,data-latency = <3 2 2>;
@@ -146,10 +145,10 @@
146 cache-level = <2>; 145 cache-level = <2>;
147 }; 146 };
148 147
149 memory-controller@f8006000 { 148 mc: memory-controller@f8006000 {
150 compatible = "xlnx,zynq-ddrc-a05"; 149 compatible = "xlnx,zynq-ddrc-a05";
151 reg = <0xf8006000 0x1000>; 150 reg = <0xf8006000 0x1000>;
152 } ; 151 };
153 152
154 uart0: serial@e0000000 { 153 uart0: serial@e0000000 {
155 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 154 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
@@ -195,7 +194,7 @@
195 194
196 gem0: ethernet@e000b000 { 195 gem0: ethernet@e000b000 {
197 compatible = "cdns,gem"; 196 compatible = "cdns,gem";
198 reg = <0xe000b000 0x4000>; 197 reg = <0xe000b000 0x1000>;
199 status = "disabled"; 198 status = "disabled";
200 interrupts = <0 22 4>; 199 interrupts = <0 22 4>;
201 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 200 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
@@ -206,7 +205,7 @@
206 205
207 gem1: ethernet@e000c000 { 206 gem1: ethernet@e000c000 {
208 compatible = "cdns,gem"; 207 compatible = "cdns,gem";
209 reg = <0xe000c000 0x4000>; 208 reg = <0xe000c000 0x1000>;
210 status = "disabled"; 209 status = "disabled";
211 interrupts = <0 45 4>; 210 interrupts = <0 45 4>;
212 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 211 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
@@ -315,5 +314,16 @@
315 reg = <0xf8f00600 0x20>; 314 reg = <0xf8f00600 0x20>;
316 clocks = <&clkc 4>; 315 clocks = <&clkc 4>;
317 }; 316 };
317
318 watchdog0: watchdog@f8005000 {
319 clocks = <&clkc 45>;
320 compatible = "xlnx,zynq-wdt-r1p2";
321 device_type = "watchdog";
322 interrupt-parent = <&intc>;
323 interrupts = <0 9 1>;
324 reg = <0xf8005000 0x1000>;
325 reset = <0>;
326 timeout-sec = <10>;
327 };
318 }; 328 };
319}; 329};
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 491b7d5523bf..f1dc7fc668f3 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -261,6 +261,7 @@ CONFIG_WATCHDOG=y
261CONFIG_XILINX_WATCHDOG=y 261CONFIG_XILINX_WATCHDOG=y
262CONFIG_ORION_WATCHDOG=y 262CONFIG_ORION_WATCHDOG=y
263CONFIG_SUNXI_WATCHDOG=y 263CONFIG_SUNXI_WATCHDOG=y
264CONFIG_MESON_WATCHDOG=y
264CONFIG_MFD_AS3722=y 265CONFIG_MFD_AS3722=y
265CONFIG_MFD_BCM590XX=y 266CONFIG_MFD_BCM590XX=y
266CONFIG_MFD_CROS_EC=y 267CONFIG_MFD_CROS_EC=y
@@ -353,6 +354,7 @@ CONFIG_MMC_MVSDIO=y
353CONFIG_MMC_SUNXI=y 354CONFIG_MMC_SUNXI=y
354CONFIG_MMC_DW=y 355CONFIG_MMC_DW=y
355CONFIG_MMC_DW_EXYNOS=y 356CONFIG_MMC_DW_EXYNOS=y
357CONFIG_MMC_DW_ROCKCHIP=y
356CONFIG_NEW_LEDS=y 358CONFIG_NEW_LEDS=y
357CONFIG_LEDS_CLASS=y 359CONFIG_LEDS_CLASS=y
358CONFIG_LEDS_GPIO=y 360CONFIG_LEDS_GPIO=y
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index 263ae3869e32..7d2ad30d9e70 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -20,7 +20,6 @@ CONFIG_PREEMPT=y
20CONFIG_AEABI=y 20CONFIG_AEABI=y
21CONFIG_ZBOOT_ROM_TEXT=0x0 21CONFIG_ZBOOT_ROM_TEXT=0x0
22CONFIG_ZBOOT_ROM_BSS=0x0 22CONFIG_ZBOOT_ROM_BSS=0x0
23CONFIG_FPE_NWFPE=y
24CONFIG_NET=y 23CONFIG_NET=y
25CONFIG_PACKET=y 24CONFIG_PACKET=y
26CONFIG_UNIX=y 25CONFIG_UNIX=y
@@ -57,14 +56,12 @@ CONFIG_MTD_NAND_FSMC=y
57CONFIG_MTD_ONENAND=y 56CONFIG_MTD_ONENAND=y
58CONFIG_MTD_ONENAND_VERIFY_WRITE=y 57CONFIG_MTD_ONENAND_VERIFY_WRITE=y
59CONFIG_MTD_ONENAND_GENERIC=y 58CONFIG_MTD_ONENAND_GENERIC=y
60CONFIG_PROC_DEVICETREE=y
61CONFIG_BLK_DEV_LOOP=y 59CONFIG_BLK_DEV_LOOP=y
62CONFIG_BLK_DEV_CRYPTOLOOP=y 60CONFIG_BLK_DEV_CRYPTOLOOP=y
63CONFIG_BLK_DEV_RAM=y 61CONFIG_BLK_DEV_RAM=y
64CONFIG_SCSI=y 62CONFIG_SCSI=y
65CONFIG_BLK_DEV_SD=y 63CONFIG_BLK_DEV_SD=y
66CONFIG_CHR_DEV_SG=y 64CONFIG_CHR_DEV_SG=y
67CONFIG_SCSI_MULTI_LUN=y
68CONFIG_SCSI_CONSTANTS=y 65CONFIG_SCSI_CONSTANTS=y
69CONFIG_SCSI_LOGGING=y 66CONFIG_SCSI_LOGGING=y
70CONFIG_SCSI_SCAN_ASYNC=y 67CONFIG_SCSI_SCAN_ASYNC=y
@@ -83,21 +80,21 @@ CONFIG_PPP_SYNC_TTY=m
83CONFIG_INPUT_EVDEV=y 80CONFIG_INPUT_EVDEV=y
84# CONFIG_KEYBOARD_ATKBD is not set 81# CONFIG_KEYBOARD_ATKBD is not set
85CONFIG_KEYBOARD_GPIO=y 82CONFIG_KEYBOARD_GPIO=y
83CONFIG_KEYBOARD_STMPE=y
86# CONFIG_MOUSE_PS2 is not set 84# CONFIG_MOUSE_PS2 is not set
87# CONFIG_SERIO is not set 85# CONFIG_SERIO is not set
88# CONFIG_LEGACY_PTYS is not set 86# CONFIG_LEGACY_PTYS is not set
89CONFIG_SERIAL_AMBA_PL011=y 87CONFIG_SERIAL_AMBA_PL011=y
90CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 88CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
91CONFIG_HW_RANDOM=y 89CONFIG_HW_RANDOM=y
92CONFIG_HW_RANDOM_NOMADIK=y
93CONFIG_I2C_CHARDEV=y 90CONFIG_I2C_CHARDEV=y
94CONFIG_I2C_GPIO=y 91CONFIG_I2C_GPIO=y
95CONFIG_I2C_NOMADIK=y
96CONFIG_DEBUG_GPIO=y 92CONFIG_DEBUG_GPIO=y
93CONFIG_GPIO_STMPE=y
97# CONFIG_HWMON is not set 94# CONFIG_HWMON is not set
95CONFIG_MFD_STMPE=y
98CONFIG_REGULATOR=y 96CONFIG_REGULATOR=y
99CONFIG_MMC=y 97CONFIG_MMC=y
100CONFIG_MMC_UNSAFE_RESUME=y
101# CONFIG_MMC_BLOCK_BOUNCE is not set 98# CONFIG_MMC_BLOCK_BOUNCE is not set
102CONFIG_MMC_ARMMMCI=y 99CONFIG_MMC_ARMMMCI=y
103CONFIG_NEW_LEDS=y 100CONFIG_NEW_LEDS=y
@@ -125,12 +122,12 @@ CONFIG_NLS_CODEPAGE_437=y
125CONFIG_NLS_ASCII=y 122CONFIG_NLS_ASCII=y
126CONFIG_NLS_ISO8859_1=y 123CONFIG_NLS_ISO8859_1=y
127CONFIG_NLS_ISO8859_15=y 124CONFIG_NLS_ISO8859_15=y
125CONFIG_DEBUG_INFO=y
128# CONFIG_ENABLE_MUST_CHECK is not set 126# CONFIG_ENABLE_MUST_CHECK is not set
129CONFIG_DEBUG_FS=y 127CONFIG_DEBUG_FS=y
130# CONFIG_SCHED_DEBUG is not set 128# CONFIG_SCHED_DEBUG is not set
131# CONFIG_DEBUG_PREEMPT is not set 129# CONFIG_DEBUG_PREEMPT is not set
132# CONFIG_DEBUG_BUGVERBOSE is not set 130# CONFIG_DEBUG_BUGVERBOSE is not set
133CONFIG_DEBUG_INFO=y
134CONFIG_CRYPTO_MD5=y 131CONFIG_CRYPTO_MD5=y
135CONFIG_CRYPTO_SHA1=y 132CONFIG_CRYPTO_SHA1=y
136CONFIG_CRYPTO_DES=y 133CONFIG_CRYPTO_DES=y
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 847045313101..f7ac0379850f 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -76,6 +76,7 @@ CONFIG_WATCHDOG=y
76CONFIG_SUNXI_WATCHDOG=y 76CONFIG_SUNXI_WATCHDOG=y
77CONFIG_MFD_AXP20X=y 77CONFIG_MFD_AXP20X=y
78CONFIG_REGULATOR=y 78CONFIG_REGULATOR=y
79CONFIG_REGULATOR_FIXED_VOLTAGE=y
79CONFIG_REGULATOR_GPIO=y 80CONFIG_REGULATOR_GPIO=y
80CONFIG_USB=y 81CONFIG_USB=y
81CONFIG_USB_EHCI_HCD=y 82CONFIG_USB_EHCI_HCD=y
diff --git a/arch/arm/include/uapi/asm/unistd.h b/arch/arm/include/uapi/asm/unistd.h
index 3aaa75cae90c..705bb7620673 100644
--- a/arch/arm/include/uapi/asm/unistd.h
+++ b/arch/arm/include/uapi/asm/unistd.h
@@ -412,6 +412,7 @@
412#define __NR_seccomp (__NR_SYSCALL_BASE+383) 412#define __NR_seccomp (__NR_SYSCALL_BASE+383)
413#define __NR_getrandom (__NR_SYSCALL_BASE+384) 413#define __NR_getrandom (__NR_SYSCALL_BASE+384)
414#define __NR_memfd_create (__NR_SYSCALL_BASE+385) 414#define __NR_memfd_create (__NR_SYSCALL_BASE+385)
415#define __NR_bpf (__NR_SYSCALL_BASE+386)
415 416
416/* 417/*
417 * The following SWIs are ARM private. 418 * The following SWIs are ARM private.
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 713e807621d2..2d2d6087b9b1 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -10,6 +10,7 @@
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13#include <linux/compiler.h>
13#include <linux/sched.h> 14#include <linux/sched.h>
14#include <linux/mm.h> 15#include <linux/mm.h>
15#include <linux/dma-mapping.h> 16#include <linux/dma-mapping.h>
@@ -39,10 +40,19 @@
39 * GCC 3.2.x: miscompiles NEW_AUX_ENT in fs/binfmt_elf.c 40 * GCC 3.2.x: miscompiles NEW_AUX_ENT in fs/binfmt_elf.c
40 * (http://gcc.gnu.org/PR8896) and incorrect structure 41 * (http://gcc.gnu.org/PR8896) and incorrect structure
41 * initialisation in fs/jffs2/erase.c 42 * initialisation in fs/jffs2/erase.c
43 * GCC 4.8.0-4.8.2: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58854
44 * miscompiles find_get_entry(), and can result in EXT3 and EXT4
45 * filesystem corruption (possibly other FS too).
42 */ 46 */
47#ifdef __GNUC__
43#if (__GNUC__ == 3 && __GNUC_MINOR__ < 3) 48#if (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
44#error Your compiler is too buggy; it is known to miscompile kernels. 49#error Your compiler is too buggy; it is known to miscompile kernels.
45#error Known good compilers: 3.3 50#error Known good compilers: 3.3, 4.x
51#endif
52#if GCC_VERSION >= 40800 && GCC_VERSION < 40803
53#error Your compiler is too buggy; it is known to miscompile kernels
54#error and result in filesystem corruption and oopses.
55#endif
46#endif 56#endif
47 57
48int main(void) 58int main(void)
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index 9f899d8fdcca..e51833f8cc38 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -395,6 +395,7 @@
395 CALL(sys_seccomp) 395 CALL(sys_seccomp)
396 CALL(sys_getrandom) 396 CALL(sys_getrandom)
397/* 385 */ CALL(sys_memfd_create) 397/* 385 */ CALL(sys_memfd_create)
398 CALL(sys_bpf)
398#ifndef syscalls_counted 399#ifndef syscalls_counted
399.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls 400.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
400#define syscalls_counted 401#define syscalls_counted
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 8c35ae4ff176..07a09570175d 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -20,7 +20,7 @@
20#include <linux/input.h> 20#include <linux/input.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/irqchip.h> 22#include <linux/irqchip.h>
23#include <linux/mailbox.h> 23#include <linux/pl320-ipc.h>
24#include <linux/of.h> 24#include <linux/of.h>
25#include <linux/of_irq.h> 25#include <linux/of_irq.h>
26#include <linux/of_platform.h> 26#include <linux/of_platform.h>
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 1412daf4a714..4e79da7c5e30 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -50,8 +50,8 @@ static const char *pcie_axi_sels[] = { "axi", "ahb", };
50static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; 50static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", };
51static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; 51static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
52static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; 52static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
53static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; 53static const char *eim_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
54static const char *emi_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 54static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
55static const char *vdo_axi_sels[] = { "axi", "ahb", }; 55static const char *vdo_axi_sels[] = { "axi", "ahb", };
56static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 56static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
57static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", 57static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
@@ -302,8 +302,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
302 clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 302 clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
303 clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 303 clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
304 clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); 304 clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
305 clk[IMX6QDL_CLK_EMI_SEL] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup); 305 clk[IMX6QDL_CLK_EIM_SEL] = imx_clk_fixup_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels), imx_cscmr1_fixup);
306 clk[IMX6QDL_CLK_EMI_SLOW_SEL] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup); 306 clk[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup);
307 clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); 307 clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
308 clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); 308 clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
309 clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); 309 clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
@@ -354,8 +354,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
354 clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); 354 clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
355 clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); 355 clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
356 clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); 356 clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
357 clk[IMX6QDL_CLK_EMI_PODF] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); 357 clk[IMX6QDL_CLK_EIM_PODF] = imx_clk_fixup_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
358 clk[IMX6QDL_CLK_EMI_SLOW_PODF] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); 358 clk[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_fixup_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
359 clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); 359 clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
360 clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); 360 clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
361 clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); 361 clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
@@ -456,7 +456,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
456 clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); 456 clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
457 clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); 457 clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
458 clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); 458 clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
459 clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10); 459 clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10);
460 clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); 460 clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
461 clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); 461 clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
462 clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); 462 clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
index f2acf075350d..a9549005097e 100644
--- a/arch/arm/mach-mediatek/mediatek.c
+++ b/arch/arm/mach-mediatek/mediatek.c
@@ -19,6 +19,9 @@
19 19
20static const char * const mediatek_board_dt_compat[] = { 20static const char * const mediatek_board_dt_compat[] = {
21 "mediatek,mt6589", 21 "mediatek,mt6589",
22 "mediatek,mt6592",
23 "mediatek,mt8127",
24 "mediatek,mt8135",
22 NULL, 25 NULL,
23}; 26};
24 27
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 9116ca476d7c..9bda46f1fab7 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -144,6 +144,7 @@ static int __init cpu8815_mmcsd_init(void)
144device_initcall(cpu8815_mmcsd_init); 144device_initcall(cpu8815_mmcsd_init);
145 145
146static const char * cpu8815_board_compat[] = { 146static const char * cpu8815_board_compat[] = {
147 "st,nomadik-nhk-15",
147 "calaosystems,usb-s8815", 148 "calaosystems,usb-s8815",
148 NULL, 149 NULL,
149}; 150};
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index c95346c94829..2156f69fc282 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -13,6 +13,7 @@
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/of_platform.h> 15#include <linux/of_platform.h>
16#include <linux/ti_wilink_st.h>
16#include <linux/wl12xx.h> 17#include <linux/wl12xx.h>
17 18
18#include <linux/platform_data/pinctrl-single.h> 19#include <linux/platform_data/pinctrl-single.h>
@@ -139,8 +140,38 @@ static void __init omap3_sbc_t3530_legacy_init(void)
139 omap_ads7846_init(1, 57, 0, NULL); 140 omap_ads7846_init(1, 57, 0, NULL);
140} 141}
141 142
142static void __init omap3_igep0020_legacy_init(void) 143struct ti_st_plat_data wilink_pdata = {
144 .nshutdown_gpio = 137,
145 .dev_name = "/dev/ttyO1",
146 .flow_cntrl = 1,
147 .baud_rate = 300000,
148};
149
150static struct platform_device wl18xx_device = {
151 .name = "kim",
152 .id = -1,
153 .dev = {
154 .platform_data = &wilink_pdata,
155 }
156};
157
158static struct platform_device btwilink_device = {
159 .name = "btwilink",
160 .id = -1,
161};
162
163static void __init omap3_igep0020_rev_f_legacy_init(void)
164{
165 legacy_init_wl12xx(0, 0, 177);
166 platform_device_register(&wl18xx_device);
167 platform_device_register(&btwilink_device);
168}
169
170static void __init omap3_igep0030_rev_g_legacy_init(void)
143{ 171{
172 legacy_init_wl12xx(0, 0, 136);
173 platform_device_register(&wl18xx_device);
174 platform_device_register(&btwilink_device);
144} 175}
145 176
146static void __init omap3_evm_legacy_init(void) 177static void __init omap3_evm_legacy_init(void)
@@ -252,9 +283,6 @@ static void __init nokia_n900_legacy_init(void)
252 platform_device_register(&omap3_rom_rng_device); 283 platform_device_register(&omap3_rom_rng_device);
253 284
254 } 285 }
255
256 /* Only on some development boards */
257 gpio_request_one(164, GPIOF_OUT_INIT_LOW, "smc91x reset");
258} 286}
259 287
260static void __init omap3_tao3530_legacy_init(void) 288static void __init omap3_tao3530_legacy_init(void)
@@ -393,7 +421,8 @@ static struct pdata_init pdata_quirks[] __initdata = {
393 { "nokia,omap3-n900", nokia_n900_legacy_init, }, 421 { "nokia,omap3-n900", nokia_n900_legacy_init, },
394 { "nokia,omap3-n9", hsmmc2_internal_input_clk, }, 422 { "nokia,omap3-n9", hsmmc2_internal_input_clk, },
395 { "nokia,omap3-n950", hsmmc2_internal_input_clk, }, 423 { "nokia,omap3-n950", hsmmc2_internal_input_clk, },
396 { "isee,omap3-igep0020", omap3_igep0020_legacy_init, }, 424 { "isee,omap3-igep0020-rev-f", omap3_igep0020_rev_f_legacy_init, },
425 { "isee,omap3-igep0030-rev-g", omap3_igep0030_rev_g_legacy_init, },
397 { "ti,omap3-evm-37xx", omap3_evm_legacy_init, }, 426 { "ti,omap3-evm-37xx", omap3_evm_legacy_init, },
398 { "ti,omap3-zoom3", omap3_zoom_legacy_init, }, 427 { "ti,omap3-zoom3", omap3_zoom_legacy_init, },
399 { "ti,am3517-evm", am3517_evm_legacy_init, }, 428 { "ti,am3517-evm", am3517_evm_legacy_init, },
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index 9db2029aa632..565925f37dc5 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -1,6 +1,19 @@
1menu "RealView platform type" 1menu "RealView platform type"
2 depends on ARCH_REALVIEW 2 depends on ARCH_REALVIEW
3 3
4config REALVIEW_DT
5 bool "Support RealView(R) Device Tree based boot"
6 select ARM_GIC
7 select MFD_SYSCON
8 select POWER_RESET
9 select POWER_RESET_VERSATILE
10 select POWER_SUPPLY
11 select SOC_REALVIEW
12 select USE_OF
13 help
14 Include support for booting the ARM(R) RealView(R) evaluation
15 boards using a device tree machine description.
16
4config MACH_REALVIEW_EB 17config MACH_REALVIEW_EB
5 bool "Support RealView(R) Emulation Baseboard" 18 bool "Support RealView(R) Emulation Baseboard"
6 select ARM_GIC 19 select ARM_GIC
diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile
index 541fa4c109ef..e07fdf7ae8a7 100644
--- a/arch/arm/mach-realview/Makefile
+++ b/arch/arm/mach-realview/Makefile
@@ -3,6 +3,7 @@
3# 3#
4 4
5obj-y := core.o 5obj-y := core.o
6obj-$(CONFIG_REALVIEW_DT) += realview-dt.o
6obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o 7obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o
7obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o 8obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o
8obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o 9obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o
diff --git a/arch/arm/mach-realview/realview-dt.c b/arch/arm/mach-realview/realview-dt.c
new file mode 100644
index 000000000000..cc28b89dd48f
--- /dev/null
+++ b/arch/arm/mach-realview/realview-dt.c
@@ -0,0 +1,32 @@
1/*
2 * Copyright (C) 2014 Linaro Ltd.
3 *
4 * Author: Linus Walleij <linus.walleij@linaro.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11#include <linux/of_platform.h>
12#include <asm/mach/arch.h>
13#include <asm/hardware/cache-l2x0.h>
14#include "core.h"
15
16static const char *realview_dt_platform_compat[] __initconst = {
17 "arm,realview-eb",
18 "arm,realview-pb1176",
19 "arm,realview-pb11mp",
20 "arm,realview-pba8",
21 "arm,realview-pbx",
22 NULL,
23};
24
25DT_MACHINE_START(REALVIEW_DT, "ARM RealView Machine (Device Tree Support)")
26#ifdef CONFIG_ZONE_DMA
27 .dma_zone_size = SZ_256M,
28#endif
29 .dt_compat = realview_dt_platform_compat,
30 .l2c_aux_val = 0x0,
31 .l2c_aux_mask = ~0x0,
32MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-ape6evm-reference.c b/arch/arm/mach-shmobile/board-ape6evm-reference.c
index a6503d8c77de..3b68370b03a0 100644
--- a/arch/arm/mach-shmobile/board-ape6evm-reference.c
+++ b/arch/arm/mach-shmobile/board-ape6evm-reference.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 15 */
20 16
21#include <linux/gpio.h> 17#include <linux/gpio.h>
@@ -48,7 +44,6 @@ static void __init ape6evm_add_standard_devices(void)
48 clk_put(parent); 44 clk_put(parent);
49 clk_put(mp); 45 clk_put(mp);
50 46
51 r8a73a4_add_dt_devices();
52 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 47 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
53} 48}
54 49
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
index b222f68d55b7..66f67816a844 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 15 */
20 16
21#include <linux/gpio.h> 17#include <linux/gpio.h>
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index e70983534403..0e912aff53de 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -12,11 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 */ 15 */
21 16
22#include <linux/clk.h> 17#include <linux/clk.h>
diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c
index 79c47847f200..d649ade4a202 100644
--- a/arch/arm/mach-shmobile/board-bockw-reference.c
+++ b/arch/arm/mach-shmobile/board-bockw-reference.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 15 */
20 16
21#include <linux/of_platform.h> 17#include <linux/of_platform.h>
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index 1cf2c75dacfb..f27b5a833bf0 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */ 16 */
21 17
22#include <linux/mfd/tmio.h> 18#include <linux/mfd/tmio.h>
diff --git a/arch/arm/mach-shmobile/board-koelsch-reference.c b/arch/arm/mach-shmobile/board-koelsch-reference.c
index 46aa540133d6..451ba624ce6e 100644
--- a/arch/arm/mach-shmobile/board-koelsch-reference.c
+++ b/arch/arm/mach-shmobile/board-koelsch-reference.c
@@ -13,93 +13,17 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */ 16 */
21 17
22#include <linux/dma-mapping.h>
23#include <linux/kernel.h> 18#include <linux/kernel.h>
24#include <linux/of_platform.h> 19#include <linux/of_platform.h>
25#include <linux/platform_data/rcar-du.h>
26 20
27#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
28 22
29#include "clock.h"
30#include "common.h" 23#include "common.h"
31#include "irqs.h"
32#include "r8a7791.h" 24#include "r8a7791.h"
33#include "rcar-gen2.h" 25#include "rcar-gen2.h"
34 26
35/* DU */
36static struct rcar_du_encoder_data koelsch_du_encoders[] = {
37 {
38 .type = RCAR_DU_ENCODER_NONE,
39 .output = RCAR_DU_OUTPUT_LVDS0,
40 .connector.lvds.panel = {
41 .width_mm = 210,
42 .height_mm = 158,
43 .mode = {
44 .pixelclock = 65000000,
45 .hactive = 1024,
46 .hfront_porch = 20,
47 .hback_porch = 160,
48 .hsync_len = 136,
49 .vactive = 768,
50 .vfront_porch = 3,
51 .vback_porch = 29,
52 .vsync_len = 6,
53 },
54 },
55 },
56};
57
58static struct rcar_du_platform_data koelsch_du_pdata = {
59 .encoders = koelsch_du_encoders,
60 .num_encoders = ARRAY_SIZE(koelsch_du_encoders),
61};
62
63static const struct resource du_resources[] __initconst = {
64 DEFINE_RES_MEM(0xfeb00000, 0x40000),
65 DEFINE_RES_MEM_NAMED(0xfeb90000, 0x1c, "lvds.0"),
66 DEFINE_RES_IRQ(gic_spi(256)),
67 DEFINE_RES_IRQ(gic_spi(268)),
68};
69
70static void __init koelsch_add_du_device(void)
71{
72 struct platform_device_info info = {
73 .name = "rcar-du-r8a7791",
74 .id = -1,
75 .res = du_resources,
76 .num_res = ARRAY_SIZE(du_resources),
77 .data = &koelsch_du_pdata,
78 .size_data = sizeof(koelsch_du_pdata),
79 .dma_mask = DMA_BIT_MASK(32),
80 };
81
82 platform_device_register_full(&info);
83}
84
85/*
86 * This is a really crude hack to provide clkdev support to platform
87 * devices until they get moved to DT.
88 */
89static const struct clk_name clk_names[] __initconst = {
90 { "du0", "du.0", "rcar-du-r8a7791" },
91 { "du1", "du.1", "rcar-du-r8a7791" },
92 { "lvds0", "lvds.0", "rcar-du-r8a7791" },
93};
94
95static void __init koelsch_add_standard_devices(void)
96{
97 shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false);
98 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
99
100 koelsch_add_du_device();
101}
102
103static const char * const koelsch_boards_compat_dt[] __initconst = { 27static const char * const koelsch_boards_compat_dt[] __initconst = {
104 "renesas,koelsch", 28 "renesas,koelsch",
105 "renesas,koelsch-reference", 29 "renesas,koelsch-reference",
@@ -110,7 +34,6 @@ DT_MACHINE_START(KOELSCH_DT, "koelsch")
110 .smp = smp_ops(r8a7791_smp_ops), 34 .smp = smp_ops(r8a7791_smp_ops),
111 .init_early = shmobile_init_delay, 35 .init_early = shmobile_init_delay,
112 .init_time = rcar_gen2_timer_init, 36 .init_time = rcar_gen2_timer_init,
113 .init_machine = koelsch_add_standard_devices,
114 .init_late = shmobile_init_late, 37 .init_late = shmobile_init_late,
115 .reserve = rcar_gen2_reserve, 38 .reserve = rcar_gen2_reserve,
116 .dt_compat = koelsch_boards_compat_dt, 39 .dt_compat = koelsch_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c
index 7111b5c1d67b..3a6a2766dc2b 100644
--- a/arch/arm/mach-shmobile/board-koelsch.c
+++ b/arch/arm/mach-shmobile/board-koelsch.c
@@ -14,10 +14,6 @@
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 */ 17 */
22 18
23#include <linux/dma-mapping.h> 19#include <linux/dma-mapping.h>
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index d9cdf9a97e23..f2ef759b6e96 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -14,10 +14,6 @@
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 */ 17 */
22 18
23#include <linux/delay.h> 19#include <linux/delay.h>
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 77e36fa0b142..7c9b63bdde9f 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */ 14 */
19 15
20#include <linux/delay.h> 16#include <linux/delay.h>
diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c
index bc4b48357dde..fa06bdba61df 100644
--- a/arch/arm/mach-shmobile/board-lager-reference.c
+++ b/arch/arm/mach-shmobile/board-lager-reference.c
@@ -12,100 +12,17 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 15 */
20 16
21#include <linux/dma-mapping.h>
22#include <linux/init.h> 17#include <linux/init.h>
23#include <linux/of_platform.h> 18#include <linux/of_platform.h>
24#include <linux/platform_data/rcar-du.h>
25 19
26#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
27 21
28#include "clock.h"
29#include "common.h" 22#include "common.h"
30#include "irqs.h"
31#include "r8a7790.h" 23#include "r8a7790.h"
32#include "rcar-gen2.h" 24#include "rcar-gen2.h"
33 25
34/* DU */
35static struct rcar_du_encoder_data lager_du_encoders[] = {
36 {
37 .type = RCAR_DU_ENCODER_VGA,
38 .output = RCAR_DU_OUTPUT_DPAD0,
39 }, {
40 .type = RCAR_DU_ENCODER_NONE,
41 .output = RCAR_DU_OUTPUT_LVDS1,
42 .connector.lvds.panel = {
43 .width_mm = 210,
44 .height_mm = 158,
45 .mode = {
46 .pixelclock = 65000000,
47 .hactive = 1024,
48 .hfront_porch = 20,
49 .hback_porch = 160,
50 .hsync_len = 136,
51 .vactive = 768,
52 .vfront_porch = 3,
53 .vback_porch = 29,
54 .vsync_len = 6,
55 },
56 },
57 },
58};
59
60static struct rcar_du_platform_data lager_du_pdata = {
61 .encoders = lager_du_encoders,
62 .num_encoders = ARRAY_SIZE(lager_du_encoders),
63};
64
65static const struct resource du_resources[] __initconst = {
66 DEFINE_RES_MEM(0xfeb00000, 0x70000),
67 DEFINE_RES_MEM_NAMED(0xfeb90000, 0x1c, "lvds.0"),
68 DEFINE_RES_MEM_NAMED(0xfeb94000, 0x1c, "lvds.1"),
69 DEFINE_RES_IRQ(gic_spi(256)),
70 DEFINE_RES_IRQ(gic_spi(268)),
71 DEFINE_RES_IRQ(gic_spi(269)),
72};
73
74static void __init lager_add_du_device(void)
75{
76 struct platform_device_info info = {
77 .name = "rcar-du-r8a7790",
78 .id = -1,
79 .res = du_resources,
80 .num_res = ARRAY_SIZE(du_resources),
81 .data = &lager_du_pdata,
82 .size_data = sizeof(lager_du_pdata),
83 .dma_mask = DMA_BIT_MASK(32),
84 };
85
86 platform_device_register_full(&info);
87}
88
89/*
90 * This is a really crude hack to provide clkdev support to platform
91 * devices until they get moved to DT.
92 */
93static const struct clk_name clk_names[] __initconst = {
94 { "du0", "du.0", "rcar-du-r8a7790" },
95 { "du1", "du.1", "rcar-du-r8a7790" },
96 { "du2", "du.2", "rcar-du-r8a7790" },
97 { "lvds0", "lvds.0", "rcar-du-r8a7790" },
98 { "lvds1", "lvds.1", "rcar-du-r8a7790" },
99};
100
101static void __init lager_add_standard_devices(void)
102{
103 shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false);
104 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
105
106 lager_add_du_device();
107}
108
109static const char *lager_boards_compat_dt[] __initdata = { 26static const char *lager_boards_compat_dt[] __initdata = {
110 "renesas,lager", 27 "renesas,lager",
111 "renesas,lager-reference", 28 "renesas,lager-reference",
@@ -116,7 +33,6 @@ DT_MACHINE_START(LAGER_DT, "lager")
116 .smp = smp_ops(r8a7790_smp_ops), 33 .smp = smp_ops(r8a7790_smp_ops),
117 .init_early = shmobile_init_delay, 34 .init_early = shmobile_init_delay,
118 .init_time = rcar_gen2_timer_init, 35 .init_time = rcar_gen2_timer_init,
119 .init_machine = lager_add_standard_devices,
120 .init_late = shmobile_init_late, 36 .init_late = shmobile_init_late,
121 .reserve = rcar_gen2_reserve, 37 .reserve = rcar_gen2_reserve,
122 .dt_compat = lager_boards_compat_dt, 38 .dt_compat = lager_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index 571327b1c942..b47262afb240 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */ 16 */
21 17
22#include <linux/gpio.h> 18#include <linux/gpio.h>
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index ca5d34b92aa7..ed1087031c5d 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -16,10 +16,6 @@
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details. 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 */ 19 */
24#include <linux/delay.h> 20#include <linux/delay.h>
25#include <linux/kernel.h> 21#include <linux/kernel.h>
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 38d9cdd26587..f0757bbaff87 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */ 16 */
21 17
22#include <linux/clk/shmobile.h> 18#include <linux/clk/shmobile.h>
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index ce33d7825c49..994dc7d86ae2 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */ 16 */
21 17
22#include <linux/kernel.h> 18#include <linux/kernel.h>
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index c2330ea1802c..1cf44dc6d718 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 15 */
20#include <linux/init.h> 16#include <linux/init.h>
21#include <linux/io.h> 17#include <linux/io.h>
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 0794f0426e70..969e85dad09b 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 15 */
20#include <linux/init.h> 16#include <linux/init.h>
21#include <linux/kernel.h> 17#include <linux/kernel.h>
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index 67980a08a601..e8510c35558c 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -17,10 +17,6 @@
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details. 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */ 20 */
25 21
26/* 22/*
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index c51f9db3f66f..fa8ab2cc9187 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 15 */
20#include <linux/bitops.h> 16#include <linux/bitops.h>
21#include <linux/init.h> 17#include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 126ddafad526..c395ff194254 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 15 */
20#include <linux/init.h> 16#include <linux/init.h>
21#include <linux/io.h> 17#include <linux/io.h>
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index 453b23129cfa..82143ca3bae9 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */ 16 */
21#include <linux/init.h> 17#include <linux/init.h>
22#include <linux/io.h> 18#include <linux/io.h>
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 7071676145c4..3bc92f46060e 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */ 14 */
19#include <linux/init.h> 15#include <linux/init.h>
20#include <linux/kernel.h> 16#include <linux/kernel.h>
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 02a6f45a0b9e..6b4c1f313cc9 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */ 14 */
19#include <linux/init.h> 15#include <linux/init.h>
20#include <linux/kernel.h> 16#include <linux/kernel.h>
diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c
index 806f94038cc4..1f81ad747153 100644
--- a/arch/arm/mach-shmobile/clock.c
+++ b/arch/arm/mach-shmobile/clock.c
@@ -14,10 +14,6 @@
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 * 16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 */ 17 */
22#include <linux/kernel.h> 18#include <linux/kernel.h>
23#include <linux/init.h> 19#include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/console.c b/arch/arm/mach-shmobile/console.c
index f2e79f2376e1..e329ccbd0a67 100644
--- a/arch/arm/mach-shmobile/console.c
+++ b/arch/arm/mach-shmobile/console.c
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */ 14 */
19#include <linux/kernel.h> 15#include <linux/kernel.h>
20#include <linux/init.h> 16#include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S
index f45dde701d7b..69df8bfac167 100644
--- a/arch/arm/mach-shmobile/headsmp-scu.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -12,11 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */ 15 */
21 16
22#include <linux/linkage.h> 17#include <linux/linkage.h>
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index e2af00b1bd9d..1ccf49cb485f 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */ 14 */
19#include <linux/kernel.h> 15#include <linux/kernel.h>
20#include <linux/init.h> 16#include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index 44457a94897b..9e3618028acc 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */ 14 */
19#include <linux/kernel.h> 15#include <linux/kernel.h>
20#include <linux/init.h> 16#include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/r8a73a4.h b/arch/arm/mach-shmobile/r8a73a4.h
index 5fafd6fcedf7..70dcd847a86e 100644
--- a/arch/arm/mach-shmobile/r8a73a4.h
+++ b/arch/arm/mach-shmobile/r8a73a4.h
@@ -11,7 +11,6 @@ enum {
11}; 11};
12 12
13void r8a73a4_add_standard_devices(void); 13void r8a73a4_add_standard_devices(void);
14void r8a73a4_add_dt_devices(void);
15void r8a73a4_clock_init(void); 14void r8a73a4_clock_init(void);
16void r8a73a4_pinmux_init(void); 15void r8a73a4_pinmux_init(void);
17 16
diff --git a/arch/arm/mach-shmobile/r8a7740.h b/arch/arm/mach-shmobile/r8a7740.h
index f369b4b0863d..ca7805ad7ea3 100644
--- a/arch/arm/mach-shmobile/r8a7740.h
+++ b/arch/arm/mach-shmobile/r8a7740.h
@@ -10,10 +10,6 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */ 13 */
18 14
19#ifndef __ASM_R8A7740_H__ 15#ifndef __ASM_R8A7740_H__
diff --git a/arch/arm/mach-shmobile/r8a7778.h b/arch/arm/mach-shmobile/r8a7778.h
index f4076a50e970..9086dfc6746a 100644
--- a/arch/arm/mach-shmobile/r8a7778.h
+++ b/arch/arm/mach-shmobile/r8a7778.h
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */ 14 */
19#ifndef __ASM_R8A7778_H__ 15#ifndef __ASM_R8A7778_H__
20#define __ASM_R8A7778_H__ 16#define __ASM_R8A7778_H__
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index b06a9e8f59a5..aad97be9cbe1 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -11,10 +11,6 @@
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */ 14 */
19#include <linux/kernel.h> 15#include <linux/kernel.h>
20#include <linux/init.h> 16#include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c
index 4122104359f9..171174777b6f 100644
--- a/arch/arm/mach-shmobile/setup-r7s72100.c
+++ b/arch/arm/mach-shmobile/setup-r7s72100.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 15 */
20 16
21#include <linux/kernel.h> 17#include <linux/kernel.h>
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index 53f40b70680d..c27682291cbf 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 15 */
20#include <linux/irq.h> 16#include <linux/irq.h>
21#include <linux/kernel.h> 17#include <linux/kernel.h>
@@ -180,18 +176,13 @@ static struct resource cmt1_resources[] = {
180 DEFINE_RES_IRQ(gic_spi(120)), 176 DEFINE_RES_IRQ(gic_spi(120)),
181}; 177};
182 178
183#define r8a7790_register_cmt(idx) \ 179#define r8a73a4_register_cmt(idx) \
184 platform_device_register_resndata(NULL, "sh-cmt-48-gen2", \ 180 platform_device_register_resndata(NULL, "sh-cmt-48-gen2", \
185 idx, cmt##idx##_resources, \ 181 idx, cmt##idx##_resources, \
186 ARRAY_SIZE(cmt##idx##_resources), \ 182 ARRAY_SIZE(cmt##idx##_resources), \
187 &cmt##idx##_platform_data, \ 183 &cmt##idx##_platform_data, \
188 sizeof(struct sh_timer_config)) 184 sizeof(struct sh_timer_config))
189 185
190void __init r8a73a4_add_dt_devices(void)
191{
192 r8a7790_register_cmt(1);
193}
194
195/* DMA */ 186/* DMA */
196static const struct sh_dmae_slave_config dma_slaves[] = { 187static const struct sh_dmae_slave_config dma_slaves[] = {
197 { 188 {
@@ -282,7 +273,7 @@ static struct resource dma_resources[] = {
282 273
283void __init r8a73a4_add_standard_devices(void) 274void __init r8a73a4_add_standard_devices(void)
284{ 275{
285 r8a73a4_add_dt_devices(); 276 r8a73a4_register_cmt(1);
286 r8a73a4_register_scif(0); 277 r8a73a4_register_scif(0);
287 r8a73a4_register_scif(1); 278 r8a73a4_register_scif(1);
288 r8a73a4_register_scif(2); 279 r8a73a4_register_scif(2);
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 8894e1b7ab0e..fe15dd26d15d 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 15 */
20#include <linux/delay.h> 16#include <linux/delay.h>
21#include <linux/dma-mapping.h> 17#include <linux/dma-mapping.h>
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 85fe016d6a87..7c7223de1e9c 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */ 16 */
21 17
22#include <linux/kernel.h> 18#include <linux/kernel.h>
@@ -292,8 +288,6 @@ void __init r8a7778_add_dt_devices(void)
292 l2x0_init(base, 0x00400000, 0xc20f0fff); 288 l2x0_init(base, 0x00400000, 0xc20f0fff);
293 } 289 }
294#endif 290#endif
295
296 r8a7778_register_tmu(0);
297} 291}
298 292
299/* HPB-DMA */ 293/* HPB-DMA */
@@ -501,6 +495,7 @@ static void __init r8a7778_register_hpb_dmae(void)
501void __init r8a7778_add_standard_devices(void) 495void __init r8a7778_add_standard_devices(void)
502{ 496{
503 r8a7778_add_dt_devices(); 497 r8a7778_add_dt_devices();
498 r8a7778_register_tmu(0);
504 r8a7778_register_scif(0); 499 r8a7778_register_scif(0);
505 r8a7778_register_scif(1); 500 r8a7778_register_scif(1);
506 r8a7778_register_scif(2); 501 r8a7778_register_scif(2);
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 136078ab9407..d08e75cceaab 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */ 16 */
21#include <linux/kernel.h> 17#include <linux/kernel.h>
22#include <linux/init.h> 18#include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 877fdeb985d0..ec7d97dca4de 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 15 */
20 16
21#include <linux/irq.h> 17#include <linux/irq.h>
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c
index 35d78639244f..d930925f8f1a 100644
--- a/arch/arm/mach-shmobile/setup-r8a7791.c
+++ b/arch/arm/mach-shmobile/setup-r8a7791.c
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */ 16 */
21 17
22#include <linux/irq.h> 18#include <linux/irq.h>
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 42d5b4308923..a669377aea57 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 15 */
20 16
21#include <linux/clk/shmobile.h> 17#include <linux/clk/shmobile.h>
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index d646c8d12423..e81c38538e13 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 15 */
20#include <linux/kernel.h> 16#include <linux/kernel.h>
21#include <linux/init.h> 17#include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index b7bd8e509668..1c8172dc2c6c 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -13,10 +13,6 @@
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */ 16 */
21#include <linux/kernel.h> 17#include <linux/kernel.h>
22#include <linux/init.h> 18#include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
index 9782862899e8..146b8de16432 100644
--- a/arch/arm/mach-shmobile/sleep-sh7372.S
+++ b/arch/arm/mach-shmobile/sleep-sh7372.S
@@ -22,11 +22,6 @@
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
24 * GNU General Public License for more details. 24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 */ 25 */
31 26
32#include <linux/linkage.h> 27#include <linux/linkage.h>
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 6ff1df1df9a7..baff3b5efed8 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 15 */
20#include <linux/kernel.h> 16#include <linux/kernel.h>
21#include <linux/init.h> 17#include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 3100e355c3fd..3f761f839043 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 15 */
20#include <linux/kernel.h> 16#include <linux/kernel.h>
21#include <linux/init.h> 17#include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 22d8f87b23e9..c16dbfe9836c 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -12,10 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 15 */
20#include <linux/kernel.h> 16#include <linux/kernel.h>
21#include <linux/init.h> 17#include <linux/init.h>
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
index 87c6be1e79bd..1081b763e0f3 100644
--- a/arch/arm/mach-shmobile/timer.c
+++ b/arch/arm/mach-shmobile/timer.c
@@ -12,11 +12,6 @@
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 */ 15 */
21#include <linux/platform_device.h> 16#include <linux/platform_device.h>
22#include <linux/clocksource.h> 17#include <linux/clocksource.h>
diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 572b8f719ffb..60c443dadb58 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -40,7 +40,7 @@ extern void __iomem *rst_manager_base_addr;
40extern struct smp_operations socfpga_smp_ops; 40extern struct smp_operations socfpga_smp_ops;
41extern char secondary_trampoline, secondary_trampoline_end; 41extern char secondary_trampoline, secondary_trampoline_end;
42 42
43extern unsigned long cpu1start_addr; 43extern unsigned long socfpga_cpu1start_addr;
44 44
45#define SOCFPGA_SCU_VIRT_BASE 0xfffec000 45#define SOCFPGA_SCU_VIRT_BASE 0xfffec000
46 46
diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
index 95c115d8b5ee..f65ea0af4af3 100644
--- a/arch/arm/mach-socfpga/headsmp.S
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -9,21 +9,26 @@
9 */ 9 */
10#include <linux/linkage.h> 10#include <linux/linkage.h>
11#include <linux/init.h> 11#include <linux/init.h>
12#include <asm/memory.h>
12 13
13 .arch armv7-a 14 .arch armv7-a
14 15
15ENTRY(secondary_trampoline) 16ENTRY(secondary_trampoline)
16 movw r2, #:lower16:cpu1start_addr 17 /* CPU1 will always fetch from 0x0 when it is brought out of reset.
17 movt r2, #:upper16:cpu1start_addr 18 * Thus, we can just subtract the PAGE_OFFSET to get the physical
18 19 * address of &cpu1start_addr. This would not work for platforms
19 /* The socfpga VT cannot handle a 0xC0000000 page offset when loading 20 * where the physical memory does not start at 0x0.
20 the cpu1start_addr, we bit clear it. Tested on HW and VT. */ 21 */
21 bic r2, r2, #0x40000000 22 adr r0, 1f
22 23 ldmia r0, {r1, r2}
23 ldr r0, [r2] 24 sub r2, r2, #PAGE_OFFSET
24 ldr r1, [r0] 25 ldr r3, [r2]
25 bx r1 26 ldr r4, [r3]
27 bx r4
26 28
29 .align
301: .long .
31 .long socfpga_cpu1start_addr
27ENTRY(secondary_trampoline_end) 32ENTRY(secondary_trampoline_end)
28 33
29ENTRY(socfpga_secondary_startup) 34ENTRY(socfpga_secondary_startup)
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 5356a72bc8ce..16ca97b039f9 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -33,11 +33,11 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
33{ 33{
34 int trampoline_size = &secondary_trampoline_end - &secondary_trampoline; 34 int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
35 35
36 if (cpu1start_addr) { 36 if (socfpga_cpu1start_addr) {
37 memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size); 37 memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
38 38
39 __raw_writel(virt_to_phys(socfpga_secondary_startup), 39 __raw_writel(virt_to_phys(socfpga_secondary_startup),
40 (sys_manager_base_addr + (cpu1start_addr & 0x000000ff))); 40 (sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff)));
41 41
42 flush_cache_all(); 42 flush_cache_all();
43 smp_wmb(); 43 smp_wmb();
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index adbf38314ca8..383d61e138af 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -29,7 +29,7 @@
29void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE)); 29void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
30void __iomem *sys_manager_base_addr; 30void __iomem *sys_manager_base_addr;
31void __iomem *rst_manager_base_addr; 31void __iomem *rst_manager_base_addr;
32unsigned long cpu1start_addr; 32unsigned long socfpga_cpu1start_addr;
33 33
34static struct map_desc scu_io_desc __initdata = { 34static struct map_desc scu_io_desc __initdata = {
35 .virtual = SOCFPGA_SCU_VIRT_BASE, 35 .virtual = SOCFPGA_SCU_VIRT_BASE,
@@ -70,7 +70,7 @@ void __init socfpga_sysmgr_init(void)
70 np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr"); 70 np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
71 71
72 if (of_property_read_u32(np, "cpu1-start-addr", 72 if (of_property_read_u32(np, "cpu1-start-addr",
73 (u32 *) &cpu1start_addr)) 73 (u32 *) &socfpga_cpu1start_addr))
74 pr_err("SMP: Need cpu1-start-addr in device tree.\n"); 74 pr_err("SMP: Need cpu1-start-addr in device tree.\n");
75 75
76 sys_manager_base_addr = of_iomap(np, 0); 76 sys_manager_base_addr = of_iomap(np, 0);
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
index 878e9ec97d0f..8825bc9e2553 100644
--- a/arch/arm/mach-sti/Kconfig
+++ b/arch/arm/mach-sti/Kconfig
@@ -42,4 +42,14 @@ config SOC_STIH416
42 and other digital audio/video applications using Flattened Device 42 and other digital audio/video applications using Flattened Device
43 Trees. 43 Trees.
44 44
45config SOC_STIH407
46 bool "STiH407 STMicroelectronics Consumer Electronics family"
47 default y
48 select STIH407_RESET
49 help
50 This enables support for STMicroelectronics Digital Consumer
51 Electronics family StiH407 parts, targetted at set-top-box
52 and other digital audio/video applications using Flattened Device
53 Trees.
54
45endif 55endif
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 55f9d6e0cc88..5e65ca8dea62 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -956,7 +956,7 @@ static u32 cache_id_part_number_from_dt;
956 * @associativity: variable to return the calculated associativity in 956 * @associativity: variable to return the calculated associativity in
957 * @max_way_size: the maximum size in bytes for the cache ways 957 * @max_way_size: the maximum size in bytes for the cache ways
958 */ 958 */
959static void __init l2x0_cache_size_of_parse(const struct device_node *np, 959static int __init l2x0_cache_size_of_parse(const struct device_node *np,
960 u32 *aux_val, u32 *aux_mask, 960 u32 *aux_val, u32 *aux_mask,
961 u32 *associativity, 961 u32 *associativity,
962 u32 max_way_size) 962 u32 max_way_size)
@@ -974,7 +974,7 @@ static void __init l2x0_cache_size_of_parse(const struct device_node *np,
974 of_property_read_u32(np, "cache-line-size", &line_size); 974 of_property_read_u32(np, "cache-line-size", &line_size);
975 975
976 if (!cache_size || !sets) 976 if (!cache_size || !sets)
977 return; 977 return -ENODEV;
978 978
979 /* All these l2 caches have the same line = block size actually */ 979 /* All these l2 caches have the same line = block size actually */
980 if (!line_size) { 980 if (!line_size) {
@@ -1009,7 +1009,7 @@ static void __init l2x0_cache_size_of_parse(const struct device_node *np,
1009 1009
1010 if (way_size > max_way_size) { 1010 if (way_size > max_way_size) {
1011 pr_err("L2C OF: set size %dKB is too large\n", way_size); 1011 pr_err("L2C OF: set size %dKB is too large\n", way_size);
1012 return; 1012 return -EINVAL;
1013 } 1013 }
1014 1014
1015 pr_info("L2C OF: override cache size: %d bytes (%dKB)\n", 1015 pr_info("L2C OF: override cache size: %d bytes (%dKB)\n",
@@ -1027,7 +1027,7 @@ static void __init l2x0_cache_size_of_parse(const struct device_node *np,
1027 if (way_size_bits < 1 || way_size_bits > 6) { 1027 if (way_size_bits < 1 || way_size_bits > 6) {
1028 pr_err("L2C OF: cache way size illegal: %dKB is not mapped\n", 1028 pr_err("L2C OF: cache way size illegal: %dKB is not mapped\n",
1029 way_size); 1029 way_size);
1030 return; 1030 return -EINVAL;
1031 } 1031 }
1032 1032
1033 mask |= L2C_AUX_CTRL_WAY_SIZE_MASK; 1033 mask |= L2C_AUX_CTRL_WAY_SIZE_MASK;
@@ -1036,6 +1036,8 @@ static void __init l2x0_cache_size_of_parse(const struct device_node *np,
1036 *aux_val &= ~mask; 1036 *aux_val &= ~mask;
1037 *aux_val |= val; 1037 *aux_val |= val;
1038 *aux_mask &= ~mask; 1038 *aux_mask &= ~mask;
1039
1040 return 0;
1039} 1041}
1040 1042
1041static void __init l2x0_of_parse(const struct device_node *np, 1043static void __init l2x0_of_parse(const struct device_node *np,
@@ -1046,6 +1048,7 @@ static void __init l2x0_of_parse(const struct device_node *np,
1046 u32 dirty = 0; 1048 u32 dirty = 0;
1047 u32 val = 0, mask = 0; 1049 u32 val = 0, mask = 0;
1048 u32 assoc; 1050 u32 assoc;
1051 int ret;
1049 1052
1050 of_property_read_u32(np, "arm,tag-latency", &tag); 1053 of_property_read_u32(np, "arm,tag-latency", &tag);
1051 if (tag) { 1054 if (tag) {
@@ -1068,7 +1071,10 @@ static void __init l2x0_of_parse(const struct device_node *np,
1068 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; 1071 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
1069 } 1072 }
1070 1073
1071 l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_256K); 1074 ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_256K);
1075 if (ret)
1076 return;
1077
1072 if (assoc > 8) { 1078 if (assoc > 8) {
1073 pr_err("l2x0 of: cache setting yield too high associativity\n"); 1079 pr_err("l2x0 of: cache setting yield too high associativity\n");
1074 pr_err("l2x0 of: %d calculated, max 8\n", assoc); 1080 pr_err("l2x0 of: %d calculated, max 8\n", assoc);
@@ -1125,6 +1131,7 @@ static void __init l2c310_of_parse(const struct device_node *np,
1125 u32 tag[3] = { 0, 0, 0 }; 1131 u32 tag[3] = { 0, 0, 0 };
1126 u32 filter[2] = { 0, 0 }; 1132 u32 filter[2] = { 0, 0 };
1127 u32 assoc; 1133 u32 assoc;
1134 int ret;
1128 1135
1129 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); 1136 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
1130 if (tag[0] && tag[1] && tag[2]) 1137 if (tag[0] && tag[1] && tag[2])
@@ -1152,7 +1159,10 @@ static void __init l2c310_of_parse(const struct device_node *np,
1152 l2x0_base + L310_ADDR_FILTER_START); 1159 l2x0_base + L310_ADDR_FILTER_START);
1153 } 1160 }
1154 1161
1155 l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K); 1162 ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K);
1163 if (ret)
1164 return;
1165
1156 switch (assoc) { 1166 switch (assoc) {
1157 case 16: 1167 case 16:
1158 *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK; 1168 *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK;
@@ -1164,8 +1174,8 @@ static void __init l2c310_of_parse(const struct device_node *np,
1164 *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK; 1174 *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK;
1165 break; 1175 break;
1166 default: 1176 default:
1167 pr_err("PL310 OF: cache setting yield illegal associativity\n"); 1177 pr_err("L2C-310 OF cache associativity %d invalid, only 8 or 16 permitted\n",
1168 pr_err("PL310 OF: %d calculated, only 8 and 16 legal\n", assoc); 1178 assoc);
1169 break; 1179 break;
1170 } 1180 }
1171} 1181}
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index c245d903927f..e8907117861e 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1198,7 +1198,6 @@ __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
1198{ 1198{
1199 return dma_common_pages_remap(pages, size, 1199 return dma_common_pages_remap(pages, size,
1200 VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller); 1200 VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller);
1201 return NULL;
1202} 1201}
1203 1202
1204/* 1203/*
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index 45aeaaca9052..e17ed00828d7 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -127,8 +127,11 @@ void *kmap_atomic_pfn(unsigned long pfn)
127{ 127{
128 unsigned long vaddr; 128 unsigned long vaddr;
129 int idx, type; 129 int idx, type;
130 struct page *page = pfn_to_page(pfn);
130 131
131 pagefault_disable(); 132 pagefault_disable();
133 if (!PageHighMem(page))
134 return page_address(page);
132 135
133 type = kmap_atomic_idx_push(); 136 type = kmap_atomic_idx_push();
134 idx = type + KM_TYPE_NR * smp_processor_id(); 137 idx = type + KM_TYPE_NR * smp_processor_id();
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 92bba32d9230..9481f85c56e6 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -559,10 +559,10 @@ void __init mem_init(void)
559#ifdef CONFIG_MODULES 559#ifdef CONFIG_MODULES
560 " modules : 0x%08lx - 0x%08lx (%4ld MB)\n" 560 " modules : 0x%08lx - 0x%08lx (%4ld MB)\n"
561#endif 561#endif
562 " .text : 0x%p" " - 0x%p" " (%4d kB)\n" 562 " .text : 0x%p" " - 0x%p" " (%4td kB)\n"
563 " .init : 0x%p" " - 0x%p" " (%4d kB)\n" 563 " .init : 0x%p" " - 0x%p" " (%4td kB)\n"
564 " .data : 0x%p" " - 0x%p" " (%4d kB)\n" 564 " .data : 0x%p" " - 0x%p" " (%4td kB)\n"
565 " .bss : 0x%p" " - 0x%p" " (%4d kB)\n", 565 " .bss : 0x%p" " - 0x%p" " (%4td kB)\n",
566 566
567 MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) + 567 MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) +
568 (PAGE_SIZE)), 568 (PAGE_SIZE)),
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index ac9afde76dea..9532f8d5857e 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1,5 +1,6 @@
1config ARM64 1config ARM64
2 def_bool y 2 def_bool y
3 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
3 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
4 select ARCH_HAS_SG_CHAIN 5 select ARCH_HAS_SG_CHAIN
5 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
@@ -232,7 +233,7 @@ config ARM64_VA_BITS_42
232 233
233config ARM64_VA_BITS_48 234config ARM64_VA_BITS_48
234 bool "48-bit" 235 bool "48-bit"
235 depends on BROKEN 236 depends on !ARM_SMMU
236 237
237endchoice 238endchoice
238 239
diff --git a/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi
index ac2cb2418025..c46cbb29f3c6 100644
--- a/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi
+++ b/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi
@@ -22,7 +22,7 @@
22 bank-width = <4>; 22 bank-width = <4>;
23 }; 23 };
24 24
25 vram@2,00000000 { 25 v2m_video_ram: vram@2,00000000 {
26 compatible = "arm,vexpress-vram"; 26 compatible = "arm,vexpress-vram";
27 reg = <2 0x00000000 0x00800000>; 27 reg = <2 0x00000000 0x00800000>;
28 }; 28 };
@@ -179,9 +179,42 @@
179 clcd@1f0000 { 179 clcd@1f0000 {
180 compatible = "arm,pl111", "arm,primecell"; 180 compatible = "arm,pl111", "arm,primecell";
181 reg = <0x1f0000 0x1000>; 181 reg = <0x1f0000 0x1000>;
182 interrupt-names = "combined";
182 interrupts = <14>; 183 interrupts = <14>;
183 clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; 184 clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
184 clock-names = "clcdclk", "apb_pclk"; 185 clock-names = "clcdclk", "apb_pclk";
186 arm,pl11x,framebuffer = <0x18000000 0x00180000>;
187 memory-region = <&v2m_video_ram>;
188 max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
189
190 port {
191 v2m_clcd_pads: endpoint {
192 remote-endpoint = <&v2m_clcd_panel>;
193 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
194 };
195 };
196
197 panel {
198 compatible = "panel-dpi";
199
200 port {
201 v2m_clcd_panel: endpoint {
202 remote-endpoint = <&v2m_clcd_pads>;
203 };
204 };
205
206 panel-timing {
207 clock-frequency = <63500127>;
208 hactive = <1024>;
209 hback-porch = <152>;
210 hfront-porch = <48>;
211 hsync-len = <104>;
212 vactive = <768>;
213 vback-porch = <23>;
214 vfront-porch = <3>;
215 vsync-len = <4>;
216 };
217 };
185 }; 218 };
186 219
187 virtio_block@0130000 { 220 virtio_block@0130000 {
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 9cd37de9aa8d..4ce602c2c6de 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -78,6 +78,7 @@ CONFIG_NET_XGENE=y
78# CONFIG_WLAN is not set 78# CONFIG_WLAN is not set
79CONFIG_INPUT_EVDEV=y 79CONFIG_INPUT_EVDEV=y
80# CONFIG_SERIO_SERPORT is not set 80# CONFIG_SERIO_SERPORT is not set
81CONFIG_SERIO_AMBAKMI=y
81CONFIG_LEGACY_PTY_COUNT=16 82CONFIG_LEGACY_PTY_COUNT=16
82CONFIG_SERIAL_8250=y 83CONFIG_SERIAL_8250=y
83CONFIG_SERIAL_8250_CONSOLE=y 84CONFIG_SERIAL_8250_CONSOLE=y
@@ -90,6 +91,7 @@ CONFIG_VIRTIO_CONSOLE=y
90CONFIG_REGULATOR=y 91CONFIG_REGULATOR=y
91CONFIG_REGULATOR_FIXED_VOLTAGE=y 92CONFIG_REGULATOR_FIXED_VOLTAGE=y
92CONFIG_FB=y 93CONFIG_FB=y
94CONFIG_FB_ARMCLCD=y
93CONFIG_FRAMEBUFFER_CONSOLE=y 95CONFIG_FRAMEBUFFER_CONSOLE=y
94CONFIG_LOGO=y 96CONFIG_LOGO=y
95# CONFIG_LOGO_LINUX_MONO is not set 97# CONFIG_LOGO_LINUX_MONO is not set
diff --git a/arch/arm64/include/asm/compat.h b/arch/arm64/include/asm/compat.h
index 253e33bc94fb..56de5aadede2 100644
--- a/arch/arm64/include/asm/compat.h
+++ b/arch/arm64/include/asm/compat.h
@@ -37,8 +37,8 @@ typedef s32 compat_ssize_t;
37typedef s32 compat_time_t; 37typedef s32 compat_time_t;
38typedef s32 compat_clock_t; 38typedef s32 compat_clock_t;
39typedef s32 compat_pid_t; 39typedef s32 compat_pid_t;
40typedef u32 __compat_uid_t; 40typedef u16 __compat_uid_t;
41typedef u32 __compat_gid_t; 41typedef u16 __compat_gid_t;
42typedef u16 __compat_uid16_t; 42typedef u16 __compat_uid16_t;
43typedef u16 __compat_gid16_t; 43typedef u16 __compat_gid16_t;
44typedef u32 __compat_uid32_t; 44typedef u32 __compat_uid32_t;
diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h
index 01d3aab64b79..1f65be393139 100644
--- a/arch/arm64/include/asm/elf.h
+++ b/arch/arm64/include/asm/elf.h
@@ -126,7 +126,7 @@ typedef struct user_fpsimd_state elf_fpregset_t;
126 * that it will "exec", and that there is sufficient room for the brk. 126 * that it will "exec", and that there is sufficient room for the brk.
127 */ 127 */
128extern unsigned long randomize_et_dyn(unsigned long base); 128extern unsigned long randomize_et_dyn(unsigned long base);
129#define ELF_ET_DYN_BASE (randomize_et_dyn(2 * TASK_SIZE_64 / 3)) 129#define ELF_ET_DYN_BASE (2 * TASK_SIZE_64 / 3)
130 130
131/* 131/*
132 * When the program starts, a1 contains a pointer to a function to be 132 * When the program starts, a1 contains a pointer to a function to be
@@ -169,7 +169,7 @@ extern unsigned long arch_randomize_brk(struct mm_struct *mm);
169#define COMPAT_ELF_PLATFORM ("v8l") 169#define COMPAT_ELF_PLATFORM ("v8l")
170#endif 170#endif
171 171
172#define COMPAT_ELF_ET_DYN_BASE (randomize_et_dyn(2 * TASK_SIZE_32 / 3)) 172#define COMPAT_ELF_ET_DYN_BASE (2 * TASK_SIZE_32 / 3)
173 173
174/* AArch32 registers. */ 174/* AArch32 registers. */
175#define COMPAT_ELF_NGREG 18 175#define COMPAT_ELF_NGREG 18
diff --git a/arch/arm64/include/asm/irq_work.h b/arch/arm64/include/asm/irq_work.h
index 8e24ef3f7c82..b4f6b19a8a68 100644
--- a/arch/arm64/include/asm/irq_work.h
+++ b/arch/arm64/include/asm/irq_work.h
@@ -1,6 +1,8 @@
1#ifndef __ASM_IRQ_WORK_H 1#ifndef __ASM_IRQ_WORK_H
2#define __ASM_IRQ_WORK_H 2#define __ASM_IRQ_WORK_H
3 3
4#ifdef CONFIG_SMP
5
4#include <asm/smp.h> 6#include <asm/smp.h>
5 7
6static inline bool arch_irq_work_has_interrupt(void) 8static inline bool arch_irq_work_has_interrupt(void)
@@ -8,4 +10,13 @@ static inline bool arch_irq_work_has_interrupt(void)
8 return !!__smp_cross_call; 10 return !!__smp_cross_call;
9} 11}
10 12
13#else
14
15static inline bool arch_irq_work_has_interrupt(void)
16{
17 return false;
18}
19
20#endif
21
11#endif /* __ASM_IRQ_WORK_H */ 22#endif /* __ASM_IRQ_WORK_H */
diff --git a/arch/arm64/kernel/efi.c b/arch/arm64/kernel/efi.c
index 03aaa99e1ea0..95c49ebc660d 100644
--- a/arch/arm64/kernel/efi.c
+++ b/arch/arm64/kernel/efi.c
@@ -89,7 +89,8 @@ static int __init uefi_init(void)
89 */ 89 */
90 if (efi.systab->hdr.signature != EFI_SYSTEM_TABLE_SIGNATURE) { 90 if (efi.systab->hdr.signature != EFI_SYSTEM_TABLE_SIGNATURE) {
91 pr_err("System table signature incorrect\n"); 91 pr_err("System table signature incorrect\n");
92 return -EINVAL; 92 retval = -EINVAL;
93 goto out;
93 } 94 }
94 if ((efi.systab->hdr.revision >> 16) < 2) 95 if ((efi.systab->hdr.revision >> 16) < 2)
95 pr_warn("Warning: EFI system table version %d.%02d, expected 2.00 or greater\n", 96 pr_warn("Warning: EFI system table version %d.%02d, expected 2.00 or greater\n",
@@ -103,6 +104,7 @@ static int __init uefi_init(void)
103 for (i = 0; i < (int) sizeof(vendor) - 1 && *c16; ++i) 104 for (i = 0; i < (int) sizeof(vendor) - 1 && *c16; ++i)
104 vendor[i] = c16[i]; 105 vendor[i] = c16[i];
105 vendor[i] = '\0'; 106 vendor[i] = '\0';
107 early_memunmap(c16, sizeof(vendor));
106 } 108 }
107 109
108 pr_info("EFI v%u.%.02u by %s\n", 110 pr_info("EFI v%u.%.02u by %s\n",
@@ -113,29 +115,11 @@ static int __init uefi_init(void)
113 if (retval == 0) 115 if (retval == 0)
114 set_bit(EFI_CONFIG_TABLES, &efi.flags); 116 set_bit(EFI_CONFIG_TABLES, &efi.flags);
115 117
116 early_memunmap(c16, sizeof(vendor)); 118out:
117 early_memunmap(efi.systab, sizeof(efi_system_table_t)); 119 early_memunmap(efi.systab, sizeof(efi_system_table_t));
118
119 return retval; 120 return retval;
120} 121}
121 122
122static __initdata char memory_type_name[][32] = {
123 {"Reserved"},
124 {"Loader Code"},
125 {"Loader Data"},
126 {"Boot Code"},
127 {"Boot Data"},
128 {"Runtime Code"},
129 {"Runtime Data"},
130 {"Conventional Memory"},
131 {"Unusable Memory"},
132 {"ACPI Reclaim Memory"},
133 {"ACPI Memory NVS"},
134 {"Memory Mapped I/O"},
135 {"MMIO Port Space"},
136 {"PAL Code"},
137};
138
139/* 123/*
140 * Return true for RAM regions we want to permanently reserve. 124 * Return true for RAM regions we want to permanently reserve.
141 */ 125 */
@@ -166,10 +150,13 @@ static __init void reserve_regions(void)
166 paddr = md->phys_addr; 150 paddr = md->phys_addr;
167 npages = md->num_pages; 151 npages = md->num_pages;
168 152
169 if (uefi_debug) 153 if (uefi_debug) {
170 pr_info(" 0x%012llx-0x%012llx [%s]", 154 char buf[64];
155
156 pr_info(" 0x%012llx-0x%012llx %s",
171 paddr, paddr + (npages << EFI_PAGE_SHIFT) - 1, 157 paddr, paddr + (npages << EFI_PAGE_SHIFT) - 1,
172 memory_type_name[md->type]); 158 efi_md_typeattr_format(buf, sizeof(buf), md));
159 }
173 160
174 memrange_efi_to_native(&paddr, &npages); 161 memrange_efi_to_native(&paddr, &npages);
175 size = npages << PAGE_SHIFT; 162 size = npages << PAGE_SHIFT;
@@ -393,11 +380,16 @@ static int __init arm64_enter_virtual_mode(void)
393 return -1; 380 return -1;
394 } 381 }
395 382
396 pr_info("Remapping and enabling EFI services.\n");
397
398 /* replace early memmap mapping with permanent mapping */
399 mapsize = memmap.map_end - memmap.map; 383 mapsize = memmap.map_end - memmap.map;
400 early_memunmap(memmap.map, mapsize); 384 early_memunmap(memmap.map, mapsize);
385
386 if (efi_runtime_disabled()) {
387 pr_info("EFI runtime services will be disabled.\n");
388 return -1;
389 }
390
391 pr_info("Remapping and enabling EFI services.\n");
392 /* replace early memmap mapping with permanent mapping */
401 memmap.map = (__force void *)ioremap_cache((phys_addr_t)memmap.phys_map, 393 memmap.map = (__force void *)ioremap_cache((phys_addr_t)memmap.phys_map,
402 mapsize); 394 mapsize);
403 memmap.map_end = memmap.map + mapsize; 395 memmap.map_end = memmap.map + mapsize;
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index c3065dbc4fa2..fde9923af859 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -378,8 +378,3 @@ unsigned long arch_randomize_brk(struct mm_struct *mm)
378{ 378{
379 return randomize_base(mm->brk); 379 return randomize_base(mm->brk);
380} 380}
381
382unsigned long randomize_et_dyn(unsigned long base)
383{
384 return randomize_base(base);
385}
diff --git a/arch/arm64/mm/ioremap.c b/arch/arm64/mm/ioremap.c
index fa324bd5a5c4..4a07630a6616 100644
--- a/arch/arm64/mm/ioremap.c
+++ b/arch/arm64/mm/ioremap.c
@@ -105,10 +105,10 @@ EXPORT_SYMBOL(ioremap_cache);
105 105
106static pte_t bm_pte[PTRS_PER_PTE] __page_aligned_bss; 106static pte_t bm_pte[PTRS_PER_PTE] __page_aligned_bss;
107#if CONFIG_ARM64_PGTABLE_LEVELS > 2 107#if CONFIG_ARM64_PGTABLE_LEVELS > 2
108static pte_t bm_pmd[PTRS_PER_PMD] __page_aligned_bss; 108static pmd_t bm_pmd[PTRS_PER_PMD] __page_aligned_bss;
109#endif 109#endif
110#if CONFIG_ARM64_PGTABLE_LEVELS > 3 110#if CONFIG_ARM64_PGTABLE_LEVELS > 3
111static pte_t bm_pud[PTRS_PER_PUD] __page_aligned_bss; 111static pud_t bm_pud[PTRS_PER_PUD] __page_aligned_bss;
112#endif 112#endif
113 113
114static inline pud_t * __init early_ioremap_pud(unsigned long addr) 114static inline pud_t * __init early_ioremap_pud(unsigned long addr)
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index 6894ef3e6234..0bf90d26e745 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -297,11 +297,15 @@ static void __init map_mem(void)
297 * create_mapping requires puds, pmds and ptes to be allocated from 297 * create_mapping requires puds, pmds and ptes to be allocated from
298 * memory addressable from the initial direct kernel mapping. 298 * memory addressable from the initial direct kernel mapping.
299 * 299 *
300 * The initial direct kernel mapping, located at swapper_pg_dir, 300 * The initial direct kernel mapping, located at swapper_pg_dir, gives
301 * gives us PUD_SIZE memory starting from PHYS_OFFSET (which must be 301 * us PUD_SIZE (4K pages) or PMD_SIZE (64K pages) memory starting from
302 * aligned to 2MB as per Documentation/arm64/booting.txt). 302 * PHYS_OFFSET (which must be aligned to 2MB as per
303 * Documentation/arm64/booting.txt).
303 */ 304 */
304 limit = PHYS_OFFSET + PUD_SIZE; 305 if (IS_ENABLED(CONFIG_ARM64_64K_PAGES))
306 limit = PHYS_OFFSET + PMD_SIZE;
307 else
308 limit = PHYS_OFFSET + PUD_SIZE;
305 memblock_set_current_limit(limit); 309 memblock_set_current_limit(limit);
306 310
307 /* map all the memory banks */ 311 /* map all the memory banks */
diff --git a/arch/arm64/mm/pgd.c b/arch/arm64/mm/pgd.c
index 62c6101df260..6682b361d3ac 100644
--- a/arch/arm64/mm/pgd.c
+++ b/arch/arm64/mm/pgd.c
@@ -30,12 +30,14 @@
30 30
31#define PGD_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) 31#define PGD_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
32 32
33static struct kmem_cache *pgd_cache;
34
33pgd_t *pgd_alloc(struct mm_struct *mm) 35pgd_t *pgd_alloc(struct mm_struct *mm)
34{ 36{
35 if (PGD_SIZE == PAGE_SIZE) 37 if (PGD_SIZE == PAGE_SIZE)
36 return (pgd_t *)get_zeroed_page(GFP_KERNEL); 38 return (pgd_t *)get_zeroed_page(GFP_KERNEL);
37 else 39 else
38 return kzalloc(PGD_SIZE, GFP_KERNEL); 40 return kmem_cache_zalloc(pgd_cache, GFP_KERNEL);
39} 41}
40 42
41void pgd_free(struct mm_struct *mm, pgd_t *pgd) 43void pgd_free(struct mm_struct *mm, pgd_t *pgd)
@@ -43,5 +45,17 @@ void pgd_free(struct mm_struct *mm, pgd_t *pgd)
43 if (PGD_SIZE == PAGE_SIZE) 45 if (PGD_SIZE == PAGE_SIZE)
44 free_page((unsigned long)pgd); 46 free_page((unsigned long)pgd);
45 else 47 else
46 kfree(pgd); 48 kmem_cache_free(pgd_cache, pgd);
49}
50
51static int __init pgd_cache_init(void)
52{
53 /*
54 * Naturally aligned pgds required by the architecture.
55 */
56 if (PGD_SIZE != PAGE_SIZE)
57 pgd_cache = kmem_cache_create("pgd_cache", PGD_SIZE, PGD_SIZE,
58 SLAB_PANIC, NULL);
59 return 0;
47} 60}
61core_initcall(pgd_cache_init);
diff --git a/arch/arm64/net/bpf_jit.h b/arch/arm64/net/bpf_jit.h
index 2134f7e6c288..de0a81a539a0 100644
--- a/arch/arm64/net/bpf_jit.h
+++ b/arch/arm64/net/bpf_jit.h
@@ -144,8 +144,12 @@
144 144
145/* Data-processing (2 source) */ 145/* Data-processing (2 source) */
146/* Rd = Rn OP Rm */ 146/* Rd = Rn OP Rm */
147#define A64_UDIV(sf, Rd, Rn, Rm) aarch64_insn_gen_data2(Rd, Rn, Rm, \ 147#define A64_DATA2(sf, Rd, Rn, Rm, type) aarch64_insn_gen_data2(Rd, Rn, Rm, \
148 A64_VARIANT(sf), AARCH64_INSN_DATA2_UDIV) 148 A64_VARIANT(sf), AARCH64_INSN_DATA2_##type)
149#define A64_UDIV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, UDIV)
150#define A64_LSLV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSLV)
151#define A64_LSRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSRV)
152#define A64_ASRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, ASRV)
149 153
150/* Data-processing (3 source) */ 154/* Data-processing (3 source) */
151/* Rd = Ra + Rn * Rm */ 155/* Rd = Ra + Rn * Rm */
diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
index 7ae33545535b..41f1e3e2ea24 100644
--- a/arch/arm64/net/bpf_jit_comp.c
+++ b/arch/arm64/net/bpf_jit_comp.c
@@ -19,12 +19,13 @@
19#define pr_fmt(fmt) "bpf_jit: " fmt 19#define pr_fmt(fmt) "bpf_jit: " fmt
20 20
21#include <linux/filter.h> 21#include <linux/filter.h>
22#include <linux/moduleloader.h>
23#include <linux/printk.h> 22#include <linux/printk.h>
24#include <linux/skbuff.h> 23#include <linux/skbuff.h>
25#include <linux/slab.h> 24#include <linux/slab.h>
25
26#include <asm/byteorder.h> 26#include <asm/byteorder.h>
27#include <asm/cacheflush.h> 27#include <asm/cacheflush.h>
28#include <asm/debug-monitors.h>
28 29
29#include "bpf_jit.h" 30#include "bpf_jit.h"
30 31
@@ -119,6 +120,14 @@ static inline int bpf2a64_offset(int bpf_to, int bpf_from,
119 return to - from; 120 return to - from;
120} 121}
121 122
123static void jit_fill_hole(void *area, unsigned int size)
124{
125 u32 *ptr;
126 /* We are guaranteed to have aligned memory. */
127 for (ptr = area; size >= sizeof(u32); size -= sizeof(u32))
128 *ptr++ = cpu_to_le32(AARCH64_BREAK_FAULT);
129}
130
122static inline int epilogue_offset(const struct jit_ctx *ctx) 131static inline int epilogue_offset(const struct jit_ctx *ctx)
123{ 132{
124 int to = ctx->offset[ctx->prog->len - 1]; 133 int to = ctx->offset[ctx->prog->len - 1];
@@ -196,6 +205,12 @@ static void build_epilogue(struct jit_ctx *ctx)
196 emit(A64_RET(A64_LR), ctx); 205 emit(A64_RET(A64_LR), ctx);
197} 206}
198 207
208/* JITs an eBPF instruction.
209 * Returns:
210 * 0 - successfully JITed an 8-byte eBPF instruction.
211 * >0 - successfully JITed a 16-byte eBPF instruction.
212 * <0 - failed to JIT.
213 */
199static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx) 214static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx)
200{ 215{
201 const u8 code = insn->code; 216 const u8 code = insn->code;
@@ -252,6 +267,18 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx)
252 emit(A64_MUL(is64, tmp, tmp, src), ctx); 267 emit(A64_MUL(is64, tmp, tmp, src), ctx);
253 emit(A64_SUB(is64, dst, dst, tmp), ctx); 268 emit(A64_SUB(is64, dst, dst, tmp), ctx);
254 break; 269 break;
270 case BPF_ALU | BPF_LSH | BPF_X:
271 case BPF_ALU64 | BPF_LSH | BPF_X:
272 emit(A64_LSLV(is64, dst, dst, src), ctx);
273 break;
274 case BPF_ALU | BPF_RSH | BPF_X:
275 case BPF_ALU64 | BPF_RSH | BPF_X:
276 emit(A64_LSRV(is64, dst, dst, src), ctx);
277 break;
278 case BPF_ALU | BPF_ARSH | BPF_X:
279 case BPF_ALU64 | BPF_ARSH | BPF_X:
280 emit(A64_ASRV(is64, dst, dst, src), ctx);
281 break;
255 /* dst = -dst */ 282 /* dst = -dst */
256 case BPF_ALU | BPF_NEG: 283 case BPF_ALU | BPF_NEG:
257 case BPF_ALU64 | BPF_NEG: 284 case BPF_ALU64 | BPF_NEG:
@@ -443,6 +470,27 @@ emit_cond_jmp:
443 emit(A64_B(jmp_offset), ctx); 470 emit(A64_B(jmp_offset), ctx);
444 break; 471 break;
445 472
473 /* dst = imm64 */
474 case BPF_LD | BPF_IMM | BPF_DW:
475 {
476 const struct bpf_insn insn1 = insn[1];
477 u64 imm64;
478
479 if (insn1.code != 0 || insn1.src_reg != 0 ||
480 insn1.dst_reg != 0 || insn1.off != 0) {
481 /* Note: verifier in BPF core must catch invalid
482 * instructions.
483 */
484 pr_err_once("Invalid BPF_LD_IMM64 instruction\n");
485 return -EINVAL;
486 }
487
488 imm64 = (u64)insn1.imm << 32 | imm;
489 emit_a64_mov_i64(dst, imm64, ctx);
490
491 return 1;
492 }
493
446 /* LDX: dst = *(size *)(src + off) */ 494 /* LDX: dst = *(size *)(src + off) */
447 case BPF_LDX | BPF_MEM | BPF_W: 495 case BPF_LDX | BPF_MEM | BPF_W:
448 case BPF_LDX | BPF_MEM | BPF_H: 496 case BPF_LDX | BPF_MEM | BPF_H:
@@ -594,6 +642,10 @@ static int build_body(struct jit_ctx *ctx)
594 ctx->offset[i] = ctx->idx; 642 ctx->offset[i] = ctx->idx;
595 643
596 ret = build_insn(insn, ctx); 644 ret = build_insn(insn, ctx);
645 if (ret > 0) {
646 i++;
647 continue;
648 }
597 if (ret) 649 if (ret)
598 return ret; 650 return ret;
599 } 651 }
@@ -613,8 +665,10 @@ void bpf_jit_compile(struct bpf_prog *prog)
613 665
614void bpf_int_jit_compile(struct bpf_prog *prog) 666void bpf_int_jit_compile(struct bpf_prog *prog)
615{ 667{
668 struct bpf_binary_header *header;
616 struct jit_ctx ctx; 669 struct jit_ctx ctx;
617 int image_size; 670 int image_size;
671 u8 *image_ptr;
618 672
619 if (!bpf_jit_enable) 673 if (!bpf_jit_enable)
620 return; 674 return;
@@ -636,23 +690,25 @@ void bpf_int_jit_compile(struct bpf_prog *prog)
636 goto out; 690 goto out;
637 691
638 build_prologue(&ctx); 692 build_prologue(&ctx);
639
640 build_epilogue(&ctx); 693 build_epilogue(&ctx);
641 694
642 /* Now we know the actual image size. */ 695 /* Now we know the actual image size. */
643 image_size = sizeof(u32) * ctx.idx; 696 image_size = sizeof(u32) * ctx.idx;
644 ctx.image = module_alloc(image_size); 697 header = bpf_jit_binary_alloc(image_size, &image_ptr,
645 if (unlikely(ctx.image == NULL)) 698 sizeof(u32), jit_fill_hole);
699 if (header == NULL)
646 goto out; 700 goto out;
647 701
648 /* 2. Now, the actual pass. */ 702 /* 2. Now, the actual pass. */
649 703
704 ctx.image = (u32 *)image_ptr;
650 ctx.idx = 0; 705 ctx.idx = 0;
706
651 build_prologue(&ctx); 707 build_prologue(&ctx);
652 708
653 ctx.body_offset = ctx.idx; 709 ctx.body_offset = ctx.idx;
654 if (build_body(&ctx)) { 710 if (build_body(&ctx)) {
655 module_free(NULL, ctx.image); 711 bpf_jit_binary_free(header);
656 goto out; 712 goto out;
657 } 713 }
658 714
@@ -663,17 +719,25 @@ void bpf_int_jit_compile(struct bpf_prog *prog)
663 bpf_jit_dump(prog->len, image_size, 2, ctx.image); 719 bpf_jit_dump(prog->len, image_size, 2, ctx.image);
664 720
665 bpf_flush_icache(ctx.image, ctx.image + ctx.idx); 721 bpf_flush_icache(ctx.image, ctx.image + ctx.idx);
666 prog->bpf_func = (void *)ctx.image;
667 prog->jited = 1;
668 722
723 set_memory_ro((unsigned long)header, header->pages);
724 prog->bpf_func = (void *)ctx.image;
725 prog->jited = true;
669out: 726out:
670 kfree(ctx.offset); 727 kfree(ctx.offset);
671} 728}
672 729
673void bpf_jit_free(struct bpf_prog *prog) 730void bpf_jit_free(struct bpf_prog *prog)
674{ 731{
675 if (prog->jited) 732 unsigned long addr = (unsigned long)prog->bpf_func & PAGE_MASK;
676 module_free(NULL, prog->bpf_func); 733 struct bpf_binary_header *header = (void *)addr;
734
735 if (!prog->jited)
736 goto free_filter;
737
738 set_memory_rw(addr, header->pages);
739 bpf_jit_binary_free(header);
677 740
678 kfree(prog); 741free_filter:
742 bpf_prog_unlock_free(prog);
679} 743}
diff --git a/arch/ia64/kernel/efi.c b/arch/ia64/kernel/efi.c
index 741b99c1a0b1..c52d7540dc05 100644
--- a/arch/ia64/kernel/efi.c
+++ b/arch/ia64/kernel/efi.c
@@ -568,6 +568,7 @@ efi_init (void)
568 { 568 {
569 const char *unit; 569 const char *unit;
570 unsigned long size; 570 unsigned long size;
571 char buf[64];
571 572
572 md = p; 573 md = p;
573 size = md->num_pages << EFI_PAGE_SHIFT; 574 size = md->num_pages << EFI_PAGE_SHIFT;
@@ -586,9 +587,10 @@ efi_init (void)
586 unit = "KB"; 587 unit = "KB";
587 } 588 }
588 589
589 printk("mem%02d: type=%2u, attr=0x%016lx, " 590 printk("mem%02d: %s "
590 "range=[0x%016lx-0x%016lx) (%4lu%s)\n", 591 "range=[0x%016lx-0x%016lx) (%4lu%s)\n",
591 i, md->type, md->attribute, md->phys_addr, 592 i, efi_md_typeattr_format(buf, sizeof(buf), md),
593 md->phys_addr,
592 md->phys_addr + efi_md_size(md), size, unit); 594 md->phys_addr + efi_md_size(md), size, unit);
593 } 595 }
594 } 596 }
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 6feded3b0c4c..a7736fa0580c 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -129,6 +129,10 @@ endmenu
129 129
130menu "Kernel features" 130menu "Kernel features"
131 131
132config NR_CPUS
133 int
134 default "1"
135
132config ADVANCED_OPTIONS 136config ADVANCED_OPTIONS
133 bool "Prompt for advanced kernel configuration options" 137 bool "Prompt for advanced kernel configuration options"
134 help 138 help
diff --git a/arch/microblaze/include/asm/unistd.h b/arch/microblaze/include/asm/unistd.h
index ea4b233647c1..0a53362d5548 100644
--- a/arch/microblaze/include/asm/unistd.h
+++ b/arch/microblaze/include/asm/unistd.h
@@ -38,6 +38,6 @@
38 38
39#endif /* __ASSEMBLY__ */ 39#endif /* __ASSEMBLY__ */
40 40
41#define __NR_syscalls 387 41#define __NR_syscalls 388
42 42
43#endif /* _ASM_MICROBLAZE_UNISTD_H */ 43#endif /* _ASM_MICROBLAZE_UNISTD_H */
diff --git a/arch/microblaze/include/uapi/asm/unistd.h b/arch/microblaze/include/uapi/asm/unistd.h
index 1c2380bf8fe6..c712677f8a2a 100644
--- a/arch/microblaze/include/uapi/asm/unistd.h
+++ b/arch/microblaze/include/uapi/asm/unistd.h
@@ -402,5 +402,6 @@
402#define __NR_seccomp 384 402#define __NR_seccomp 384
403#define __NR_getrandom 385 403#define __NR_getrandom 385
404#define __NR_memfd_create 386 404#define __NR_memfd_create 386
405#define __NR_bpf 387
405 406
406#endif /* _UAPI_ASM_MICROBLAZE_UNISTD_H */ 407#endif /* _UAPI_ASM_MICROBLAZE_UNISTD_H */
diff --git a/arch/microblaze/kernel/syscall_table.S b/arch/microblaze/kernel/syscall_table.S
index de59ee1d7010..0166e890486c 100644
--- a/arch/microblaze/kernel/syscall_table.S
+++ b/arch/microblaze/kernel/syscall_table.S
@@ -387,3 +387,4 @@ ENTRY(sys_call_table)
387 .long sys_seccomp 387 .long sys_seccomp
388 .long sys_getrandom /* 385 */ 388 .long sys_getrandom /* 385 */
389 .long sys_memfd_create 389 .long sys_memfd_create
390 .long sys_bpf
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index 9037914f6985..b30e41c0c033 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -660,8 +660,13 @@ void pci_process_bridge_OF_ranges(struct pci_controller *hose,
660 res = &hose->mem_resources[memno++]; 660 res = &hose->mem_resources[memno++];
661 break; 661 break;
662 } 662 }
663 if (res != NULL) 663 if (res != NULL) {
664 of_pci_range_to_resource(&range, dev, res); 664 res->name = dev->full_name;
665 res->flags = range.flags;
666 res->start = range.cpu_addr;
667 res->end = range.cpu_addr + range.size - 1;
668 res->parent = res->child = res->sibling = NULL;
669 }
665 } 670 }
666 671
667 /* If there's an ISA hole and the pci_mem_offset is -not- matching 672 /* If there's an ISA hole and the pci_mem_offset is -not- matching
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ad6badb6be71..f43aa536c517 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2066,6 +2066,7 @@ config MIPS_CPS
2066 support is unavailable. 2066 support is unavailable.
2067 2067
2068config MIPS_CPS_PM 2068config MIPS_CPS_PM
2069 depends on MIPS_CPS
2069 select MIPS_CPC 2070 select MIPS_CPC
2070 bool 2071 bool
2071 2072
diff --git a/arch/mips/ath79/mach-db120.c b/arch/mips/ath79/mach-db120.c
index 4d661a1d2dae..9423f5aed287 100644
--- a/arch/mips/ath79/mach-db120.c
+++ b/arch/mips/ath79/mach-db120.c
@@ -113,7 +113,7 @@ static void __init db120_pci_init(u8 *eeprom)
113 ath79_register_pci(); 113 ath79_register_pci();
114} 114}
115#else 115#else
116static inline void db120_pci_init(void) {} 116static inline void db120_pci_init(u8 *eeprom) {}
117#endif /* CONFIG_PCI */ 117#endif /* CONFIG_PCI */
118 118
119static void __init db120_setup(void) 119static void __init db120_setup(void)
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 38f4c32e2816..5ebdb32d9a2b 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -806,15 +806,6 @@ void __init prom_init(void)
806#endif 806#endif
807 } 807 }
808 808
809 if (octeon_is_simulation()) {
810 /*
811 * The simulator uses a mtdram device pre filled with
812 * the filesystem. Also specify the calibration delay
813 * to avoid calculating it every time.
814 */
815 strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824");
816 }
817
818 mips_hpt_frequency = octeon_get_clock_rate(); 809 mips_hpt_frequency = octeon_get_clock_rate();
819 810
820 octeon_init_cvmcount(); 811 octeon_init_cvmcount();
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
index 51f80bd36fcc..63b3468ede4c 100644
--- a/arch/mips/include/asm/cop2.h
+++ b/arch/mips/include/asm/cop2.h
@@ -37,15 +37,15 @@ extern void nlm_cop2_restore(struct nlm_cop2_state *);
37 37
38#define cop2_present 1 38#define cop2_present 1
39#define cop2_lazy_restore 1 39#define cop2_lazy_restore 1
40#define cop2_save(r) do { (r); } while (0) 40#define cop2_save(r) do { (void)(r); } while (0)
41#define cop2_restore(r) do { (r); } while (0) 41#define cop2_restore(r) do { (void)(r); } while (0)
42 42
43#else 43#else
44 44
45#define cop2_present 0 45#define cop2_present 0
46#define cop2_lazy_restore 0 46#define cop2_lazy_restore 0
47#define cop2_save(r) do { (r); } while (0) 47#define cop2_save(r) do { (void)(r); } while (0)
48#define cop2_restore(r) do { (r); } while (0) 48#define cop2_restore(r) do { (void)(r); } while (0)
49#endif 49#endif
50 50
51enum cu2_ops { 51enum cu2_ops {
diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h
index 992aaba603b5..b463f2aa5a61 100644
--- a/arch/mips/include/asm/ftrace.h
+++ b/arch/mips/include/asm/ftrace.h
@@ -24,7 +24,7 @@ do { \
24 asm volatile ( \ 24 asm volatile ( \
25 "1: " load " %[tmp_dst], 0(%[tmp_src])\n" \ 25 "1: " load " %[tmp_dst], 0(%[tmp_src])\n" \
26 " li %[tmp_err], 0\n" \ 26 " li %[tmp_err], 0\n" \
27 "2:\n" \ 27 "2: .insn\n" \
28 \ 28 \
29 ".section .fixup, \"ax\"\n" \ 29 ".section .fixup, \"ax\"\n" \
30 "3: li %[tmp_err], 1\n" \ 30 "3: li %[tmp_err], 1\n" \
@@ -46,7 +46,7 @@ do { \
46 asm volatile ( \ 46 asm volatile ( \
47 "1: " store " %[tmp_src], 0(%[tmp_dst])\n"\ 47 "1: " store " %[tmp_src], 0(%[tmp_dst])\n"\
48 " li %[tmp_err], 0\n" \ 48 " li %[tmp_err], 0\n" \
49 "2:\n" \ 49 "2: .insn\n" \
50 \ 50 \
51 ".section .fixup, \"ax\"\n" \ 51 ".section .fixup, \"ax\"\n" \
52 "3: li %[tmp_err], 1\n" \ 52 "3: li %[tmp_err], 1\n" \
diff --git a/arch/mips/include/asm/idle.h b/arch/mips/include/asm/idle.h
index d9f932de80e9..1c967abd545c 100644
--- a/arch/mips/include/asm/idle.h
+++ b/arch/mips/include/asm/idle.h
@@ -8,19 +8,12 @@ extern void (*cpu_wait)(void);
8extern void r4k_wait(void); 8extern void r4k_wait(void);
9extern asmlinkage void __r4k_wait(void); 9extern asmlinkage void __r4k_wait(void);
10extern void r4k_wait_irqoff(void); 10extern void r4k_wait_irqoff(void);
11extern void __pastwait(void);
12 11
13static inline int using_rollback_handler(void) 12static inline int using_rollback_handler(void)
14{ 13{
15 return cpu_wait == r4k_wait; 14 return cpu_wait == r4k_wait;
16} 15}
17 16
18static inline int address_is_in_r4k_wait_irqoff(unsigned long addr)
19{
20 return addr >= (unsigned long)r4k_wait_irqoff &&
21 addr < (unsigned long)__pastwait;
22}
23
24extern int mips_cpuidle_wait_enter(struct cpuidle_device *dev, 17extern int mips_cpuidle_wait_enter(struct cpuidle_device *dev,
25 struct cpuidle_driver *drv, int index); 18 struct cpuidle_driver *drv, int index);
26 19
diff --git a/arch/mips/include/uapi/asm/ptrace.h b/arch/mips/include/uapi/asm/ptrace.h
index bbcfb8ba8106..91a3d197ede3 100644
--- a/arch/mips/include/uapi/asm/ptrace.h
+++ b/arch/mips/include/uapi/asm/ptrace.h
@@ -9,6 +9,8 @@
9#ifndef _UAPI_ASM_PTRACE_H 9#ifndef _UAPI_ASM_PTRACE_H
10#define _UAPI_ASM_PTRACE_H 10#define _UAPI_ASM_PTRACE_H
11 11
12#include <linux/types.h>
13
12/* 0 - 31 are integer registers, 32 - 63 are fp registers. */ 14/* 0 - 31 are integer registers, 32 - 63 are fp registers. */
13#define FPR_BASE 32 15#define FPR_BASE 32
14#define PC 64 16#define PC 64
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 09ce45980758..0b9082b6b683 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -68,9 +68,6 @@ void r4k_wait_irqoff(void)
68 " wait \n" 68 " wait \n"
69 " .set pop \n"); 69 " .set pop \n");
70 local_irq_enable(); 70 local_irq_enable();
71 __asm__(
72 " .globl __pastwait \n"
73 "__pastwait: \n");
74} 71}
75 72
76/* 73/*
diff --git a/arch/mips/lasat/Kconfig b/arch/mips/lasat/Kconfig
index 1d2ee8a9be13..8776d0a34274 100644
--- a/arch/mips/lasat/Kconfig
+++ b/arch/mips/lasat/Kconfig
@@ -4,7 +4,7 @@ config PICVUE
4 4
5config PICVUE_PROC 5config PICVUE_PROC
6 tristate "PICVUE LCD display driver /proc interface" 6 tristate "PICVUE LCD display driver /proc interface"
7 depends on PICVUE 7 depends on PICVUE && PROC_FS
8 8
9config DS1603 9config DS1603
10 bool "DS1603 RTC driver" 10 bool "DS1603 RTC driver"
diff --git a/arch/mips/loongson/lemote-2f/clock.c b/arch/mips/loongson/lemote-2f/clock.c
index a217061beee3..462e34d46b4a 100644
--- a/arch/mips/loongson/lemote-2f/clock.c
+++ b/arch/mips/loongson/lemote-2f/clock.c
@@ -91,6 +91,7 @@ EXPORT_SYMBOL(clk_put);
91 91
92int clk_set_rate(struct clk *clk, unsigned long rate) 92int clk_set_rate(struct clk *clk, unsigned long rate)
93{ 93{
94 unsigned int rate_khz = rate / 1000;
94 struct cpufreq_frequency_table *pos; 95 struct cpufreq_frequency_table *pos;
95 int ret = 0; 96 int ret = 0;
96 int regval; 97 int regval;
@@ -107,9 +108,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
107 propagate_rate(clk); 108 propagate_rate(clk);
108 109
109 cpufreq_for_each_valid_entry(pos, loongson2_clockmod_table) 110 cpufreq_for_each_valid_entry(pos, loongson2_clockmod_table)
110 if (rate == pos->frequency) 111 if (rate_khz == pos->frequency)
111 break; 112 break;
112 if (rate != pos->frequency) 113 if (rate_khz != pos->frequency)
113 return -ENOTSUPP; 114 return -ENOTSUPP;
114 115
115 clk->rate = rate; 116 clk->rate = rate;
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 7a4727795a70..51a0fde4bec1 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -1023,7 +1023,7 @@ emul:
1023 goto emul; 1023 goto emul;
1024 1024
1025 case cop1x_op: 1025 case cop1x_op:
1026 if (cpu_has_mips_4_5 || cpu_has_mips64) 1026 if (cpu_has_mips_4_5 || cpu_has_mips64 || cpu_has_mips32r2)
1027 /* its one of ours */ 1027 /* its one of ours */
1028 goto emul; 1028 goto emul;
1029 1029
@@ -1068,7 +1068,7 @@ emul:
1068 break; 1068 break;
1069 1069
1070 case cop1x_op: 1070 case cop1x_op:
1071 if (!cpu_has_mips_4_5 && !cpu_has_mips64) 1071 if (!cpu_has_mips_4_5 && !cpu_has_mips64 && !cpu_has_mips32r2)
1072 return SIGILL; 1072 return SIGILL;
1073 1073
1074 sig = fpux_emu(xcp, ctx, ir, fault_addr); 1074 sig = fpux_emu(xcp, ctx, ir, fault_addr);
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index a08dd53a1cc5..b5f228e7eae6 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -1062,6 +1062,7 @@ static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
1062struct mips_huge_tlb_info { 1062struct mips_huge_tlb_info {
1063 int huge_pte; 1063 int huge_pte;
1064 int restore_scratch; 1064 int restore_scratch;
1065 bool need_reload_pte;
1065}; 1066};
1066 1067
1067static struct mips_huge_tlb_info 1068static struct mips_huge_tlb_info
@@ -1076,6 +1077,7 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1076 1077
1077 rv.huge_pte = scratch; 1078 rv.huge_pte = scratch;
1078 rv.restore_scratch = 0; 1079 rv.restore_scratch = 0;
1080 rv.need_reload_pte = false;
1079 1081
1080 if (check_for_high_segbits) { 1082 if (check_for_high_segbits) {
1081 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1083 UASM_i_MFC0(p, tmp, C0_BADVADDR);
@@ -1264,6 +1266,7 @@ static void build_r4000_tlb_refill_handler(void)
1264 } else { 1266 } else {
1265 htlb_info.huge_pte = K0; 1267 htlb_info.huge_pte = K0;
1266 htlb_info.restore_scratch = 0; 1268 htlb_info.restore_scratch = 0;
1269 htlb_info.need_reload_pte = true;
1267 vmalloc_mode = refill_noscratch; 1270 vmalloc_mode = refill_noscratch;
1268 /* 1271 /*
1269 * create the plain linear handler 1272 * create the plain linear handler
@@ -1300,7 +1303,8 @@ static void build_r4000_tlb_refill_handler(void)
1300 } 1303 }
1301#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1304#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1302 uasm_l_tlb_huge_update(&l, p); 1305 uasm_l_tlb_huge_update(&l, p);
1303 UASM_i_LW(&p, K0, 0, K1); 1306 if (htlb_info.need_reload_pte)
1307 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1);
1304 build_huge_update_entries(&p, htlb_info.huge_pte, K1); 1308 build_huge_update_entries(&p, htlb_info.huge_pte, K1);
1305 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, 1309 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
1306 htlb_info.restore_scratch); 1310 htlb_info.restore_scratch);
diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile
index b9510ea8db56..6510ace272d4 100644
--- a/arch/mips/mti-malta/Makefile
+++ b/arch/mips/mti-malta/Makefile
@@ -5,8 +5,9 @@
5# Copyright (C) 2008 Wind River Systems, Inc. 5# Copyright (C) 2008 Wind River Systems, Inc.
6# written by Ralf Baechle <ralf@linux-mips.org> 6# written by Ralf Baechle <ralf@linux-mips.org>
7# 7#
8obj-y := malta-amon.o malta-display.o malta-init.o \ 8obj-y := malta-display.o malta-init.o \
9 malta-int.o malta-memory.o malta-platform.o \ 9 malta-int.o malta-memory.o malta-platform.o \
10 malta-reset.o malta-setup.o malta-time.o 10 malta-reset.o malta-setup.o malta-time.o
11 11
12obj-$(CONFIG_MIPS_CMP) += malta-amon.o
12obj-$(CONFIG_MIPS_MALTA_PM) += malta-pm.o 13obj-$(CONFIG_MIPS_MALTA_PM) += malta-pm.o
diff --git a/arch/mips/mti-sead3/Makefile b/arch/mips/mti-sead3/Makefile
index febf4334545e..2ae49e99eb67 100644
--- a/arch/mips/mti-sead3/Makefile
+++ b/arch/mips/mti-sead3/Makefile
@@ -14,7 +14,6 @@ obj-y := sead3-lcd.o sead3-display.o sead3-init.o \
14 sead3-setup.o sead3-time.o 14 sead3-setup.o sead3-time.o
15 15
16obj-y += sead3-i2c-dev.o sead3-i2c.o \ 16obj-y += sead3-i2c-dev.o sead3-i2c.o \
17 sead3-pic32-i2c-drv.o sead3-pic32-bus.o \
18 leds-sead3.o sead3-leds.o 17 leds-sead3.o sead3-leds.o
19 18
20obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o 19obj-$(CONFIG_EARLY_PRINTK) += sead3-console.o
diff --git a/arch/mips/mti-sead3/sead3-i2c.c b/arch/mips/mti-sead3/sead3-i2c.c
index f70d5fc58ef5..795ae83894e0 100644
--- a/arch/mips/mti-sead3/sead3-i2c.c
+++ b/arch/mips/mti-sead3/sead3-i2c.c
@@ -5,10 +5,8 @@
5 * 5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */ 7 */
8#include <linux/module.h>
9#include <linux/init.h> 8#include <linux/init.h>
10#include <linux/platform_device.h> 9#include <linux/platform_device.h>
11#include <irq.h>
12 10
13struct resource sead3_i2c_resources[] = { 11struct resource sead3_i2c_resources[] = {
14 { 12 {
@@ -30,8 +28,4 @@ static int __init sead3_i2c_init(void)
30 return platform_device_register(&sead3_i2c_device); 28 return platform_device_register(&sead3_i2c_device);
31} 29}
32 30
33module_init(sead3_i2c_init); 31device_initcall(sead3_i2c_init);
34
35MODULE_AUTHOR("Chris Dearman <chris@mips.com>");
36MODULE_LICENSE("GPL");
37MODULE_DESCRIPTION("I2C probe driver for SEAD3");
diff --git a/arch/mips/mti-sead3/sead3-pic32-bus.c b/arch/mips/mti-sead3/sead3-pic32-bus.c
deleted file mode 100644
index 3b12aa5a7c88..000000000000
--- a/arch/mips/mti-sead3/sead3-pic32-bus.c
+++ /dev/null
@@ -1,102 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */
8#include <linux/delay.h>
9#include <linux/kernel.h>
10#include <linux/spinlock.h>
11#include <linux/io.h>
12#include <linux/errno.h>
13
14#define PIC32_NULL 0x00
15#define PIC32_RD 0x01
16#define PIC32_SYSRD 0x02
17#define PIC32_WR 0x10
18#define PIC32_SYSWR 0x20
19#define PIC32_IRQ_CLR 0x40
20#define PIC32_STATUS 0x80
21
22#define DELAY() udelay(100) /* FIXME: needed? */
23
24/* spinlock to ensure atomic access to PIC32 */
25static DEFINE_SPINLOCK(pic32_bus_lock);
26
27/* FIXME: io_remap these */
28static void __iomem *bus_xfer = (void __iomem *)0xbf000600;
29static void __iomem *bus_status = (void __iomem *)0xbf000060;
30
31static inline unsigned int ioready(void)
32{
33 return readl(bus_status) & 1;
34}
35
36static inline void wait_ioready(void)
37{
38 do { } while (!ioready());
39}
40
41static inline void wait_ioclear(void)
42{
43 do { } while (ioready());
44}
45
46static inline void check_ioclear(void)
47{
48 if (ioready()) {
49 pr_debug("ioclear: initially busy\n");
50 do {
51 (void) readl(bus_xfer);
52 DELAY();
53 } while (ioready());
54 pr_debug("ioclear: cleared busy\n");
55 }
56}
57
58u32 pic32_bus_readl(u32 reg)
59{
60 unsigned long flags;
61 u32 status, val;
62
63 spin_lock_irqsave(&pic32_bus_lock, flags);
64
65 check_ioclear();
66
67 writel((PIC32_RD << 24) | (reg & 0x00ffffff), bus_xfer);
68 DELAY();
69 wait_ioready();
70 status = readl(bus_xfer);
71 DELAY();
72 val = readl(bus_xfer);
73 wait_ioclear();
74
75 pr_debug("pic32_bus_readl: *%x -> %x (status=%x)\n", reg, val, status);
76
77 spin_unlock_irqrestore(&pic32_bus_lock, flags);
78
79 return val;
80}
81
82void pic32_bus_writel(u32 val, u32 reg)
83{
84 unsigned long flags;
85 u32 status;
86
87 spin_lock_irqsave(&pic32_bus_lock, flags);
88
89 check_ioclear();
90
91 writel((PIC32_WR << 24) | (reg & 0x00ffffff), bus_xfer);
92 DELAY();
93 writel(val, bus_xfer);
94 DELAY();
95 wait_ioready();
96 status = readl(bus_xfer);
97 wait_ioclear();
98
99 pr_debug("pic32_bus_writel: *%x <- %x (status=%x)\n", reg, val, status);
100
101 spin_unlock_irqrestore(&pic32_bus_lock, flags);
102}
diff --git a/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c b/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c
deleted file mode 100644
index 80fe194cfa53..000000000000
--- a/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c
+++ /dev/null
@@ -1,423 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */
8#include <linux/delay.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/spinlock.h>
12#include <linux/platform_device.h>
13#include <linux/init.h>
14#include <linux/errno.h>
15#include <linux/i2c.h>
16#include <linux/slab.h>
17
18#define PIC32_I2CxCON 0x0000
19#define PIC32_I2CxCONCLR 0x0004
20#define PIC32_I2CxCONSET 0x0008
21#define PIC32_I2CxCONINV 0x000C
22#define I2CCON_ON (1<<15)
23#define I2CCON_FRZ (1<<14)
24#define I2CCON_SIDL (1<<13)
25#define I2CCON_SCLREL (1<<12)
26#define I2CCON_STRICT (1<<11)
27#define I2CCON_A10M (1<<10)
28#define I2CCON_DISSLW (1<<9)
29#define I2CCON_SMEN (1<<8)
30#define I2CCON_GCEN (1<<7)
31#define I2CCON_STREN (1<<6)
32#define I2CCON_ACKDT (1<<5)
33#define I2CCON_ACKEN (1<<4)
34#define I2CCON_RCEN (1<<3)
35#define I2CCON_PEN (1<<2)
36#define I2CCON_RSEN (1<<1)
37#define I2CCON_SEN (1<<0)
38
39#define PIC32_I2CxSTAT 0x0010
40#define PIC32_I2CxSTATCLR 0x0014
41#define PIC32_I2CxSTATSET 0x0018
42#define PIC32_I2CxSTATINV 0x001C
43#define I2CSTAT_ACKSTAT (1<<15)
44#define I2CSTAT_TRSTAT (1<<14)
45#define I2CSTAT_BCL (1<<10)
46#define I2CSTAT_GCSTAT (1<<9)
47#define I2CSTAT_ADD10 (1<<8)
48#define I2CSTAT_IWCOL (1<<7)
49#define I2CSTAT_I2COV (1<<6)
50#define I2CSTAT_DA (1<<5)
51#define I2CSTAT_P (1<<4)
52#define I2CSTAT_S (1<<3)
53#define I2CSTAT_RW (1<<2)
54#define I2CSTAT_RBF (1<<1)
55#define I2CSTAT_TBF (1<<0)
56
57#define PIC32_I2CxADD 0x0020
58#define PIC32_I2CxADDCLR 0x0024
59#define PIC32_I2CxADDSET 0x0028
60#define PIC32_I2CxADDINV 0x002C
61#define PIC32_I2CxMSK 0x0030
62#define PIC32_I2CxMSKCLR 0x0034
63#define PIC32_I2CxMSKSET 0x0038
64#define PIC32_I2CxMSKINV 0x003C
65#define PIC32_I2CxBRG 0x0040
66#define PIC32_I2CxBRGCLR 0x0044
67#define PIC32_I2CxBRGSET 0x0048
68#define PIC32_I2CxBRGINV 0x004C
69#define PIC32_I2CxTRN 0x0050
70#define PIC32_I2CxTRNCLR 0x0054
71#define PIC32_I2CxTRNSET 0x0058
72#define PIC32_I2CxTRNINV 0x005C
73#define PIC32_I2CxRCV 0x0060
74
75struct i2c_platform_data {
76 u32 base;
77 struct i2c_adapter adap;
78 u32 xfer_timeout;
79 u32 ack_timeout;
80 u32 ctl_timeout;
81};
82
83extern u32 pic32_bus_readl(u32 reg);
84extern void pic32_bus_writel(u32 val, u32 reg);
85
86static inline void
87StartI2C(struct i2c_platform_data *adap)
88{
89 pr_debug("StartI2C\n");
90 pic32_bus_writel(I2CCON_SEN, adap->base + PIC32_I2CxCONSET);
91}
92
93static inline void
94StopI2C(struct i2c_platform_data *adap)
95{
96 pr_debug("StopI2C\n");
97 pic32_bus_writel(I2CCON_PEN, adap->base + PIC32_I2CxCONSET);
98}
99
100static inline void
101AckI2C(struct i2c_platform_data *adap)
102{
103 pr_debug("AckI2C\n");
104 pic32_bus_writel(I2CCON_ACKDT, adap->base + PIC32_I2CxCONCLR);
105 pic32_bus_writel(I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET);
106}
107
108static inline void
109NotAckI2C(struct i2c_platform_data *adap)
110{
111 pr_debug("NakI2C\n");
112 pic32_bus_writel(I2CCON_ACKDT, adap->base + PIC32_I2CxCONSET);
113 pic32_bus_writel(I2CCON_ACKEN, adap->base + PIC32_I2CxCONSET);
114}
115
116static inline int
117IdleI2C(struct i2c_platform_data *adap)
118{
119 int i;
120
121 pr_debug("IdleI2C\n");
122 for (i = 0; i < adap->ctl_timeout; i++) {
123 if (((pic32_bus_readl(adap->base + PIC32_I2CxCON) &
124 (I2CCON_ACKEN | I2CCON_RCEN | I2CCON_PEN | I2CCON_RSEN |
125 I2CCON_SEN)) == 0) &&
126 ((pic32_bus_readl(adap->base + PIC32_I2CxSTAT) &
127 (I2CSTAT_TRSTAT)) == 0))
128 return 0;
129 udelay(1);
130 }
131 return -ETIMEDOUT;
132}
133
134static inline u32
135MasterWriteI2C(struct i2c_platform_data *adap, u32 byte)
136{
137 pr_debug("MasterWriteI2C\n");
138
139 pic32_bus_writel(byte, adap->base + PIC32_I2CxTRN);
140
141 return pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & I2CSTAT_IWCOL;
142}
143
144static inline u32
145MasterReadI2C(struct i2c_platform_data *adap)
146{
147 pr_debug("MasterReadI2C\n");
148
149 pic32_bus_writel(I2CCON_RCEN, adap->base + PIC32_I2CxCONSET);
150
151 while (pic32_bus_readl(adap->base + PIC32_I2CxCON) & I2CCON_RCEN)
152 ;
153
154 pic32_bus_writel(I2CSTAT_I2COV, adap->base + PIC32_I2CxSTATCLR);
155
156 return pic32_bus_readl(adap->base + PIC32_I2CxRCV);
157}
158
159static int
160do_address(struct i2c_platform_data *adap, unsigned int addr, int rd)
161{
162 pr_debug("doaddress\n");
163
164 IdleI2C(adap);
165 StartI2C(adap);
166 IdleI2C(adap);
167
168 addr <<= 1;
169 if (rd)
170 addr |= 1;
171
172 if (MasterWriteI2C(adap, addr))
173 return -EIO;
174 IdleI2C(adap);
175 if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) & I2CSTAT_ACKSTAT)
176 return -EIO;
177 return 0;
178}
179
180static int
181i2c_read(struct i2c_platform_data *adap, unsigned char *buf,
182 unsigned int len)
183{
184 int i;
185 u32 data;
186
187 pr_debug("i2c_read\n");
188
189 i = 0;
190 while (i < len) {
191 data = MasterReadI2C(adap);
192 buf[i++] = data;
193 if (i < len)
194 AckI2C(adap);
195 else
196 NotAckI2C(adap);
197 }
198
199 StopI2C(adap);
200 IdleI2C(adap);
201 return 0;
202}
203
204static int
205i2c_write(struct i2c_platform_data *adap, unsigned char *buf,
206 unsigned int len)
207{
208 int i;
209 u32 data;
210
211 pr_debug("i2c_write\n");
212
213 i = 0;
214 while (i < len) {
215 data = buf[i];
216 if (MasterWriteI2C(adap, data))
217 return -EIO;
218 IdleI2C(adap);
219 if (pic32_bus_readl(adap->base + PIC32_I2CxSTAT) &
220 I2CSTAT_ACKSTAT)
221 return -EIO;
222 i++;
223 }
224
225 StopI2C(adap);
226 IdleI2C(adap);
227 return 0;
228}
229
230static int
231platform_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
232{
233 struct i2c_platform_data *adap = i2c_adap->algo_data;
234 struct i2c_msg *p;
235 int i, err = 0;
236
237 pr_debug("platform_xfer\n");
238 for (i = 0; i < num; i++) {
239#define __BUFSIZE 80
240 int ii;
241 static char buf[__BUFSIZE];
242 char *b = buf;
243
244 p = &msgs[i];
245 b += sprintf(buf, " [%d bytes]", p->len);
246 if ((p->flags & I2C_M_RD) == 0) {
247 for (ii = 0; ii < p->len; ii++) {
248 if (b < &buf[__BUFSIZE-4]) {
249 b += sprintf(b, " %02x", p->buf[ii]);
250 } else {
251 strcat(b, "...");
252 break;
253 }
254 }
255 }
256 pr_debug("xfer%d: DevAddr: %04x Op:%s Data:%s\n", i, p->addr,
257 (p->flags & I2C_M_RD) ? "Rd" : "Wr", buf);
258 }
259
260
261 for (i = 0; !err && i < num; i++) {
262 p = &msgs[i];
263 err = do_address(adap, p->addr, p->flags & I2C_M_RD);
264 if (err || !p->len)
265 continue;
266 if (p->flags & I2C_M_RD)
267 err = i2c_read(adap, p->buf, p->len);
268 else
269 err = i2c_write(adap, p->buf, p->len);
270 }
271
272 /* Return the number of messages processed, or the error code. */
273 if (err == 0)
274 err = num;
275
276 return err;
277}
278
279static u32
280platform_func(struct i2c_adapter *adap)
281{
282 pr_debug("platform_algo\n");
283 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
284}
285
286static const struct i2c_algorithm platform_algo = {
287 .master_xfer = platform_xfer,
288 .functionality = platform_func,
289};
290
291static void i2c_platform_setup(struct i2c_platform_data *priv)
292{
293 pr_debug("i2c_platform_setup\n");
294
295 pic32_bus_writel(500, priv->base + PIC32_I2CxBRG);
296 pic32_bus_writel(I2CCON_ON, priv->base + PIC32_I2CxCONCLR);
297 pic32_bus_writel(I2CCON_ON, priv->base + PIC32_I2CxCONSET);
298 pic32_bus_writel((I2CSTAT_BCL | I2CSTAT_IWCOL),
299 (priv->base + PIC32_I2CxSTATCLR));
300}
301
302static void i2c_platform_disable(struct i2c_platform_data *priv)
303{
304 pr_debug("i2c_platform_disable\n");
305}
306
307static int i2c_platform_probe(struct platform_device *pdev)
308{
309 struct i2c_platform_data *priv;
310 struct resource *r;
311 int ret;
312
313 pr_debug("i2c_platform_probe\n");
314 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
315 if (!r)
316 return -ENODEV;
317
318 priv = devm_kzalloc(&pdev->dev, sizeof(struct i2c_platform_data),
319 GFP_KERNEL);
320 if (!priv)
321 return -ENOMEM;
322
323 /* FIXME: need to allocate resource in PIC32 space */
324#if 0
325 priv->base = bus_request_region(r->start, resource_size(r),
326 pdev->name);
327#else
328 priv->base = r->start;
329#endif
330 if (!priv->base)
331 return -EBUSY;
332
333 priv->xfer_timeout = 200;
334 priv->ack_timeout = 200;
335 priv->ctl_timeout = 200;
336
337 priv->adap.nr = pdev->id;
338 priv->adap.algo = &platform_algo;
339 priv->adap.algo_data = priv;
340 priv->adap.dev.parent = &pdev->dev;
341 strlcpy(priv->adap.name, "PIC32 I2C", sizeof(priv->adap.name));
342
343 i2c_platform_setup(priv);
344
345 ret = i2c_add_numbered_adapter(&priv->adap);
346 if (ret) {
347 i2c_platform_disable(priv);
348 return ret;
349 }
350
351 platform_set_drvdata(pdev, priv);
352 return 0;
353}
354
355static int i2c_platform_remove(struct platform_device *pdev)
356{
357 struct i2c_platform_data *priv = platform_get_drvdata(pdev);
358
359 pr_debug("i2c_platform_remove\n");
360 platform_set_drvdata(pdev, NULL);
361 i2c_del_adapter(&priv->adap);
362 i2c_platform_disable(priv);
363 return 0;
364}
365
366#ifdef CONFIG_PM
367static int
368i2c_platform_suspend(struct platform_device *pdev, pm_message_t state)
369{
370 struct i2c_platform_data *priv = platform_get_drvdata(pdev);
371
372 dev_dbg(&pdev->dev, "i2c_platform_disable\n");
373 i2c_platform_disable(priv);
374
375 return 0;
376}
377
378static int
379i2c_platform_resume(struct platform_device *pdev)
380{
381 struct i2c_platform_data *priv = platform_get_drvdata(pdev);
382
383 dev_dbg(&pdev->dev, "i2c_platform_setup\n");
384 i2c_platform_setup(priv);
385
386 return 0;
387}
388#else
389#define i2c_platform_suspend NULL
390#define i2c_platform_resume NULL
391#endif
392
393static struct platform_driver i2c_platform_driver = {
394 .driver = {
395 .name = "i2c_pic32",
396 .owner = THIS_MODULE,
397 },
398 .probe = i2c_platform_probe,
399 .remove = i2c_platform_remove,
400 .suspend = i2c_platform_suspend,
401 .resume = i2c_platform_resume,
402};
403
404static int __init
405i2c_platform_init(void)
406{
407 pr_debug("i2c_platform_init\n");
408 return platform_driver_register(&i2c_platform_driver);
409}
410
411static void __exit
412i2c_platform_exit(void)
413{
414 pr_debug("i2c_platform_exit\n");
415 platform_driver_unregister(&i2c_platform_driver);
416}
417
418MODULE_AUTHOR("Chris Dearman, MIPS Technologies INC.");
419MODULE_DESCRIPTION("PIC32 I2C driver");
420MODULE_LICENSE("GPL");
421
422module_init(i2c_platform_init);
423module_exit(i2c_platform_exit);
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index 37fe8e7887e2..d3ed15b2b2d1 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -215,17 +215,12 @@ static int ltq_pci_probe(struct platform_device *pdev)
215 215
216 pci_clear_flags(PCI_PROBE_ONLY); 216 pci_clear_flags(PCI_PROBE_ONLY);
217 217
218 res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
219 res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1); 218 res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1);
220 if (!res_cfg || !res_bridge) {
221 dev_err(&pdev->dev, "missing memory resources\n");
222 return -EINVAL;
223 }
224
225 ltq_pci_membase = devm_ioremap_resource(&pdev->dev, res_bridge); 219 ltq_pci_membase = devm_ioremap_resource(&pdev->dev, res_bridge);
226 if (IS_ERR(ltq_pci_membase)) 220 if (IS_ERR(ltq_pci_membase))
227 return PTR_ERR(ltq_pci_membase); 221 return PTR_ERR(ltq_pci_membase);
228 222
223 res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
229 ltq_pci_mapped_cfg = devm_ioremap_resource(&pdev->dev, res_cfg); 224 ltq_pci_mapped_cfg = devm_ioremap_resource(&pdev->dev, res_cfg);
230 if (IS_ERR(ltq_pci_mapped_cfg)) 225 if (IS_ERR(ltq_pci_mapped_cfg))
231 return PTR_ERR(ltq_pci_mapped_cfg); 226 return PTR_ERR(ltq_pci_mapped_cfg);
diff --git a/arch/mips/pmcs-msp71xx/msp_irq.c b/arch/mips/pmcs-msp71xx/msp_irq.c
index f914c753de21..8d53d7a2ed45 100644
--- a/arch/mips/pmcs-msp71xx/msp_irq.c
+++ b/arch/mips/pmcs-msp71xx/msp_irq.c
@@ -16,6 +16,7 @@
16#include <linux/time.h> 16#include <linux/time.h>
17 17
18#include <asm/irq_cpu.h> 18#include <asm/irq_cpu.h>
19#include <asm/setup.h>
19 20
20#include <msp_int.h> 21#include <msp_int.h>
21 22
diff --git a/arch/mips/pmcs-msp71xx/msp_irq_cic.c b/arch/mips/pmcs-msp71xx/msp_irq_cic.c
index b8df2f7b3328..1207ec4dfb77 100644
--- a/arch/mips/pmcs-msp71xx/msp_irq_cic.c
+++ b/arch/mips/pmcs-msp71xx/msp_irq_cic.c
@@ -131,11 +131,11 @@ static int msp_cic_irq_set_affinity(struct irq_data *d,
131 int cpu; 131 int cpu;
132 unsigned long flags; 132 unsigned long flags;
133 unsigned int mtflags; 133 unsigned int mtflags;
134 unsigned long imask = (1 << (irq - MSP_CIC_INTBASE)); 134 unsigned long imask = (1 << (d->irq - MSP_CIC_INTBASE));
135 volatile u32 *cic_mask = (volatile u32 *)CIC_VPE0_MSK_REG; 135 volatile u32 *cic_mask = (volatile u32 *)CIC_VPE0_MSK_REG;
136 136
137 /* timer balancing should be disabled in kernel code */ 137 /* timer balancing should be disabled in kernel code */
138 BUG_ON(irq == MSP_INT_VPE0_TIMER || irq == MSP_INT_VPE1_TIMER); 138 BUG_ON(d->irq == MSP_INT_VPE0_TIMER || d->irq == MSP_INT_VPE1_TIMER);
139 139
140 LOCK_CORE(flags, mtflags); 140 LOCK_CORE(flags, mtflags);
141 /* enable if any of each VPE's TCs require this IRQ */ 141 /* enable if any of each VPE's TCs require this IRQ */
diff --git a/arch/mips/sibyte/Makefile b/arch/mips/sibyte/Makefile
index c8ed2c807e69..455c40d6d625 100644
--- a/arch/mips/sibyte/Makefile
+++ b/arch/mips/sibyte/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_SIBYTE_RHONE) += swarm/
25obj-$(CONFIG_SIBYTE_SENTOSA) += swarm/ 25obj-$(CONFIG_SIBYTE_SENTOSA) += swarm/
26obj-$(CONFIG_SIBYTE_SWARM) += swarm/ 26obj-$(CONFIG_SIBYTE_SWARM) += swarm/
27obj-$(CONFIG_SIBYTE_BIGSUR) += swarm/ 27obj-$(CONFIG_SIBYTE_BIGSUR) += swarm/
28obj-$(CONFIG_SIBYTE_LITTLESUR) += swarm/
diff --git a/arch/powerpc/configs/pseries_le_defconfig b/arch/powerpc/configs/pseries_le_defconfig
index 63392f4b29a4..d2008887eb8c 100644
--- a/arch/powerpc/configs/pseries_le_defconfig
+++ b/arch/powerpc/configs/pseries_le_defconfig
@@ -48,7 +48,6 @@ CONFIG_KEXEC=y
48CONFIG_IRQ_ALL_CPUS=y 48CONFIG_IRQ_ALL_CPUS=y
49CONFIG_MEMORY_HOTPLUG=y 49CONFIG_MEMORY_HOTPLUG=y
50CONFIG_MEMORY_HOTREMOVE=y 50CONFIG_MEMORY_HOTREMOVE=y
51CONFIG_CMA=y
52CONFIG_PPC_64K_PAGES=y 51CONFIG_PPC_64K_PAGES=y
53CONFIG_PPC_SUBPAGE_PROT=y 52CONFIG_PPC_SUBPAGE_PROT=y
54CONFIG_SCHED_SMT=y 53CONFIG_SCHED_SMT=y
@@ -138,6 +137,7 @@ CONFIG_NETCONSOLE=y
138CONFIG_NETPOLL_TRAP=y 137CONFIG_NETPOLL_TRAP=y
139CONFIG_TUN=m 138CONFIG_TUN=m
140CONFIG_VIRTIO_NET=m 139CONFIG_VIRTIO_NET=m
140CONFIG_VHOST_NET=m
141CONFIG_VORTEX=y 141CONFIG_VORTEX=y
142CONFIG_ACENIC=m 142CONFIG_ACENIC=m
143CONFIG_ACENIC_OMIT_TIGON_I=y 143CONFIG_ACENIC_OMIT_TIGON_I=y
@@ -303,4 +303,9 @@ CONFIG_CRYPTO_LZO=m
303# CONFIG_CRYPTO_ANSI_CPRNG is not set 303# CONFIG_CRYPTO_ANSI_CPRNG is not set
304CONFIG_CRYPTO_DEV_NX=y 304CONFIG_CRYPTO_DEV_NX=y
305CONFIG_CRYPTO_DEV_NX_ENCRYPT=m 305CONFIG_CRYPTO_DEV_NX_ENCRYPT=m
306CONFIG_VIRTUALIZATION=y
307CONFIG_KVM_BOOK3S_64=m
308CONFIG_KVM_BOOK3S_64_HV=y
309CONFIG_TRANSPARENT_HUGEPAGE=y
310CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
306CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y 311CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
index 3b260efbfbf9..ca07f9c27335 100644
--- a/arch/powerpc/include/asm/eeh.h
+++ b/arch/powerpc/include/asm/eeh.h
@@ -71,9 +71,10 @@ struct device_node;
71 71
72#define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */ 72#define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */
73#define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */ 73#define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */
74#define EEH_PE_RESET (1 << 2) /* PE reset in progress */ 74#define EEH_PE_CFG_BLOCKED (1 << 2) /* Block config access */
75 75
76#define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */ 76#define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */
77#define EEH_PE_CFG_RESTRICTED (1 << 9) /* Block config on error */
77 78
78struct eeh_pe { 79struct eeh_pe {
79 int type; /* PE type: PHB/Bus/Device */ 80 int type; /* PE type: PHB/Bus/Device */
diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index 623f2971ce0e..766b77d527ac 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -71,7 +71,7 @@ pte_t *huge_pte_offset_and_shift(struct mm_struct *mm,
71 71
72void flush_dcache_icache_hugepage(struct page *page); 72void flush_dcache_icache_hugepage(struct page *page);
73 73
74#if defined(CONFIG_PPC_MM_SLICES) || defined(CONFIG_PPC_SUBPAGE_PROT) 74#if defined(CONFIG_PPC_MM_SLICES)
75int is_hugepage_only_range(struct mm_struct *mm, unsigned long addr, 75int is_hugepage_only_range(struct mm_struct *mm, unsigned long addr,
76 unsigned long len); 76 unsigned long len);
77#else 77#else
diff --git a/arch/powerpc/include/asm/perf_event.h b/arch/powerpc/include/asm/perf_event.h
index 0bb23725b1e7..8bf1b6351716 100644
--- a/arch/powerpc/include/asm/perf_event.h
+++ b/arch/powerpc/include/asm/perf_event.h
@@ -34,7 +34,7 @@
34 do { \ 34 do { \
35 (regs)->result = 0; \ 35 (regs)->result = 0; \
36 (regs)->nip = __ip; \ 36 (regs)->nip = __ip; \
37 (regs)->gpr[1] = *(unsigned long *)__get_SP(); \ 37 (regs)->gpr[1] = current_stack_pointer(); \
38 asm volatile("mfmsr %0" : "=r" ((regs)->msr)); \ 38 asm volatile("mfmsr %0" : "=r" ((regs)->msr)); \
39 } while (0) 39 } while (0)
40#endif 40#endif
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index fe3f9488f321..c998279bd85b 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1265,8 +1265,7 @@ static inline unsigned long mfvtb (void)
1265 1265
1266#define proc_trap() asm volatile("trap") 1266#define proc_trap() asm volatile("trap")
1267 1267
1268#define __get_SP() ({unsigned long sp; \ 1268extern unsigned long current_stack_pointer(void);
1269 asm volatile("mr %0,1": "=r" (sp)); sp;})
1270 1269
1271extern unsigned long scom970_read(unsigned int address); 1270extern unsigned long scom970_read(unsigned int address);
1272extern void scom970_write(unsigned int address, unsigned long value); 1271extern void scom970_write(unsigned int address, unsigned long value);
diff --git a/arch/powerpc/include/asm/syscall.h b/arch/powerpc/include/asm/syscall.h
index 6fa2708da153..6240698fee9a 100644
--- a/arch/powerpc/include/asm/syscall.h
+++ b/arch/powerpc/include/asm/syscall.h
@@ -19,7 +19,7 @@
19 19
20/* ftrace syscalls requires exporting the sys_call_table */ 20/* ftrace syscalls requires exporting the sys_call_table */
21#ifdef CONFIG_FTRACE_SYSCALLS 21#ifdef CONFIG_FTRACE_SYSCALLS
22extern const unsigned long *sys_call_table; 22extern const unsigned long sys_call_table[];
23#endif /* CONFIG_FTRACE_SYSCALLS */ 23#endif /* CONFIG_FTRACE_SYSCALLS */
24 24
25static inline long syscall_get_nr(struct task_struct *task, 25static inline long syscall_get_nr(struct task_struct *task,
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index 7d8a60068805..ce9577d693be 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -365,3 +365,4 @@ SYSCALL_SPU(renameat2)
365SYSCALL_SPU(seccomp) 365SYSCALL_SPU(seccomp)
366SYSCALL_SPU(getrandom) 366SYSCALL_SPU(getrandom)
367SYSCALL_SPU(memfd_create) 367SYSCALL_SPU(memfd_create)
368SYSCALL_SPU(bpf)
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
index 4e9af3fd43e7..e0da021caa00 100644
--- a/arch/powerpc/include/asm/unistd.h
+++ b/arch/powerpc/include/asm/unistd.h
@@ -12,7 +12,7 @@
12#include <uapi/asm/unistd.h> 12#include <uapi/asm/unistd.h>
13 13
14 14
15#define __NR_syscalls 361 15#define __NR_syscalls 362
16 16
17#define __NR__exit __NR_exit 17#define __NR__exit __NR_exit
18#define NR_syscalls __NR_syscalls 18#define NR_syscalls __NR_syscalls
diff --git a/arch/powerpc/include/uapi/asm/unistd.h b/arch/powerpc/include/uapi/asm/unistd.h
index 0688fc06e183..f55351f2e66e 100644
--- a/arch/powerpc/include/uapi/asm/unistd.h
+++ b/arch/powerpc/include/uapi/asm/unistd.h
@@ -383,5 +383,6 @@
383#define __NR_seccomp 358 383#define __NR_seccomp 358
384#define __NR_getrandom 359 384#define __NR_getrandom 359
385#define __NR_memfd_create 360 385#define __NR_memfd_create 360
386#define __NR_bpf 361
386 387
387#endif /* _UAPI_ASM_POWERPC_UNISTD_H_ */ 388#endif /* _UAPI_ASM_POWERPC_UNISTD_H_ */
diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c
index adac9dc54aee..484b2d4462c1 100644
--- a/arch/powerpc/kernel/dma.c
+++ b/arch/powerpc/kernel/dma.c
@@ -53,9 +53,16 @@ void *dma_direct_alloc_coherent(struct device *dev, size_t size,
53#else 53#else
54 struct page *page; 54 struct page *page;
55 int node = dev_to_node(dev); 55 int node = dev_to_node(dev);
56#ifdef CONFIG_FSL_SOC
56 u64 pfn = get_pfn_limit(dev); 57 u64 pfn = get_pfn_limit(dev);
57 int zone; 58 int zone;
58 59
60 /*
61 * This code should be OK on other platforms, but we have drivers that
62 * don't set coherent_dma_mask. As a workaround we just ifdef it. This
63 * whole routine needs some serious cleanup.
64 */
65
59 zone = dma_pfn_limit_to_zone(pfn); 66 zone = dma_pfn_limit_to_zone(pfn);
60 if (zone < 0) { 67 if (zone < 0) {
61 dev_err(dev, "%s: No suitable zone for pfn %#llx\n", 68 dev_err(dev, "%s: No suitable zone for pfn %#llx\n",
@@ -73,6 +80,7 @@ void *dma_direct_alloc_coherent(struct device *dev, size_t size,
73 break; 80 break;
74#endif 81#endif
75 }; 82 };
83#endif /* CONFIG_FSL_SOC */
76 84
77 /* ignore region specifiers */ 85 /* ignore region specifiers */
78 flag &= ~(__GFP_HIGHMEM); 86 flag &= ~(__GFP_HIGHMEM);
diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index d543e4179c18..2248a1999c64 100644
--- a/arch/powerpc/kernel/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -257,6 +257,13 @@ static void *eeh_dump_pe_log(void *data, void *flag)
257 struct eeh_dev *edev, *tmp; 257 struct eeh_dev *edev, *tmp;
258 size_t *plen = flag; 258 size_t *plen = flag;
259 259
260 /* If the PE's config space is blocked, 0xFF's will be
261 * returned. It's pointless to collect the log in this
262 * case.
263 */
264 if (pe->state & EEH_PE_CFG_BLOCKED)
265 return NULL;
266
260 eeh_pe_for_each_dev(pe, edev, tmp) 267 eeh_pe_for_each_dev(pe, edev, tmp)
261 *plen += eeh_dump_dev_log(edev, pci_regs_buf + *plen, 268 *plen += eeh_dump_dev_log(edev, pci_regs_buf + *plen,
262 EEH_PCI_REGS_LOG_LEN - *plen); 269 EEH_PCI_REGS_LOG_LEN - *plen);
@@ -673,18 +680,18 @@ int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state stat
673 switch (state) { 680 switch (state) {
674 case pcie_deassert_reset: 681 case pcie_deassert_reset:
675 eeh_ops->reset(pe, EEH_RESET_DEACTIVATE); 682 eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
676 eeh_pe_state_clear(pe, EEH_PE_RESET); 683 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);
677 break; 684 break;
678 case pcie_hot_reset: 685 case pcie_hot_reset:
679 eeh_pe_state_mark(pe, EEH_PE_RESET); 686 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
680 eeh_ops->reset(pe, EEH_RESET_HOT); 687 eeh_ops->reset(pe, EEH_RESET_HOT);
681 break; 688 break;
682 case pcie_warm_reset: 689 case pcie_warm_reset:
683 eeh_pe_state_mark(pe, EEH_PE_RESET); 690 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
684 eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL); 691 eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
685 break; 692 break;
686 default: 693 default:
687 eeh_pe_state_clear(pe, EEH_PE_RESET); 694 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);
688 return -EINVAL; 695 return -EINVAL;
689 }; 696 };
690 697
@@ -1523,7 +1530,7 @@ int eeh_pe_reset(struct eeh_pe *pe, int option)
1523 switch (option) { 1530 switch (option) {
1524 case EEH_RESET_DEACTIVATE: 1531 case EEH_RESET_DEACTIVATE:
1525 ret = eeh_ops->reset(pe, option); 1532 ret = eeh_ops->reset(pe, option);
1526 eeh_pe_state_clear(pe, EEH_PE_RESET); 1533 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);
1527 if (ret) 1534 if (ret)
1528 break; 1535 break;
1529 1536
@@ -1538,7 +1545,7 @@ int eeh_pe_reset(struct eeh_pe *pe, int option)
1538 */ 1545 */
1539 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE); 1546 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
1540 1547
1541 eeh_pe_state_mark(pe, EEH_PE_RESET); 1548 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
1542 ret = eeh_ops->reset(pe, option); 1549 ret = eeh_ops->reset(pe, option);
1543 break; 1550 break;
1544 default: 1551 default:
diff --git a/arch/powerpc/kernel/eeh_driver.c b/arch/powerpc/kernel/eeh_driver.c
index 3fd514f8e4b2..6535936bdf27 100644
--- a/arch/powerpc/kernel/eeh_driver.c
+++ b/arch/powerpc/kernel/eeh_driver.c
@@ -528,13 +528,13 @@ int eeh_pe_reset_and_recover(struct eeh_pe *pe)
528 eeh_pe_dev_traverse(pe, eeh_report_error, &result); 528 eeh_pe_dev_traverse(pe, eeh_report_error, &result);
529 529
530 /* Issue reset */ 530 /* Issue reset */
531 eeh_pe_state_mark(pe, EEH_PE_RESET); 531 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
532 ret = eeh_reset_pe(pe); 532 ret = eeh_reset_pe(pe);
533 if (ret) { 533 if (ret) {
534 eeh_pe_state_clear(pe, EEH_PE_RECOVERING | EEH_PE_RESET); 534 eeh_pe_state_clear(pe, EEH_PE_RECOVERING | EEH_PE_CFG_BLOCKED);
535 return ret; 535 return ret;
536 } 536 }
537 eeh_pe_state_clear(pe, EEH_PE_RESET); 537 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);
538 538
539 /* Unfreeze the PE */ 539 /* Unfreeze the PE */
540 ret = eeh_clear_pe_frozen_state(pe, true); 540 ret = eeh_clear_pe_frozen_state(pe, true);
@@ -601,10 +601,10 @@ static int eeh_reset_device(struct eeh_pe *pe, struct pci_bus *bus)
601 * config accesses. So we prefer to block them. However, controlled 601 * config accesses. So we prefer to block them. However, controlled
602 * PCI config accesses initiated from EEH itself are allowed. 602 * PCI config accesses initiated from EEH itself are allowed.
603 */ 603 */
604 eeh_pe_state_mark(pe, EEH_PE_RESET); 604 eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
605 rc = eeh_reset_pe(pe); 605 rc = eeh_reset_pe(pe);
606 if (rc) { 606 if (rc) {
607 eeh_pe_state_clear(pe, EEH_PE_RESET); 607 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);
608 return rc; 608 return rc;
609 } 609 }
610 610
@@ -613,7 +613,7 @@ static int eeh_reset_device(struct eeh_pe *pe, struct pci_bus *bus)
613 /* Restore PE */ 613 /* Restore PE */
614 eeh_ops->configure_bridge(pe); 614 eeh_ops->configure_bridge(pe);
615 eeh_pe_restore_bars(pe); 615 eeh_pe_restore_bars(pe);
616 eeh_pe_state_clear(pe, EEH_PE_RESET); 616 eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);
617 617
618 /* Clear frozen state */ 618 /* Clear frozen state */
619 rc = eeh_clear_pe_frozen_state(pe, false); 619 rc = eeh_clear_pe_frozen_state(pe, false);
diff --git a/arch/powerpc/kernel/eeh_pe.c b/arch/powerpc/kernel/eeh_pe.c
index 53dd0915e690..5a63e2b0f65b 100644
--- a/arch/powerpc/kernel/eeh_pe.c
+++ b/arch/powerpc/kernel/eeh_pe.c
@@ -525,7 +525,7 @@ static void *__eeh_pe_state_mark(void *data, void *flag)
525 pe->state |= state; 525 pe->state |= state;
526 526
527 /* Offline PCI devices if applicable */ 527 /* Offline PCI devices if applicable */
528 if (state != EEH_PE_ISOLATED) 528 if (!(state & EEH_PE_ISOLATED))
529 return NULL; 529 return NULL;
530 530
531 eeh_pe_for_each_dev(pe, edev, tmp) { 531 eeh_pe_for_each_dev(pe, edev, tmp) {
@@ -534,6 +534,10 @@ static void *__eeh_pe_state_mark(void *data, void *flag)
534 pdev->error_state = pci_channel_io_frozen; 534 pdev->error_state = pci_channel_io_frozen;
535 } 535 }
536 536
537 /* Block PCI config access if required */
538 if (pe->state & EEH_PE_CFG_RESTRICTED)
539 pe->state |= EEH_PE_CFG_BLOCKED;
540
537 return NULL; 541 return NULL;
538} 542}
539 543
@@ -611,6 +615,10 @@ static void *__eeh_pe_state_clear(void *data, void *flag)
611 pdev->error_state = pci_channel_io_normal; 615 pdev->error_state = pci_channel_io_normal;
612 } 616 }
613 617
618 /* Unblock PCI config access if required */
619 if (pe->state & EEH_PE_CFG_RESTRICTED)
620 pe->state &= ~EEH_PE_CFG_BLOCKED;
621
614 return NULL; 622 return NULL;
615} 623}
616 624
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 050f79a4a168..72e783ea0681 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -1270,11 +1270,6 @@ hmi_exception_early:
1270 addi r3,r1,STACK_FRAME_OVERHEAD 1270 addi r3,r1,STACK_FRAME_OVERHEAD
1271 bl hmi_exception_realmode 1271 bl hmi_exception_realmode
1272 /* Windup the stack. */ 1272 /* Windup the stack. */
1273 /* Clear MSR_RI before setting SRR0 and SRR1. */
1274 li r0,MSR_RI
1275 mfmsr r9 /* get MSR value */
1276 andc r9,r9,r0
1277 mtmsrd r9,1 /* Clear MSR_RI */
1278 /* Move original HSRR0 and HSRR1 into the respective regs */ 1273 /* Move original HSRR0 and HSRR1 into the respective regs */
1279 ld r9,_MSR(r1) 1274 ld r9,_MSR(r1)
1280 mtspr SPRN_HSRR1,r9 1275 mtspr SPRN_HSRR1,r9
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 8eb857f216c1..c14383575fe8 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -466,7 +466,7 @@ static inline void check_stack_overflow(void)
466#ifdef CONFIG_DEBUG_STACKOVERFLOW 466#ifdef CONFIG_DEBUG_STACKOVERFLOW
467 long sp; 467 long sp;
468 468
469 sp = __get_SP() & (THREAD_SIZE-1); 469 sp = current_stack_pointer() & (THREAD_SIZE-1);
470 470
471 /* check for stack overflow: is there less than 2KB free? */ 471 /* check for stack overflow: is there less than 2KB free? */
472 if (unlikely(sp < (sizeof(struct thread_info) + 2048))) { 472 if (unlikely(sp < (sizeof(struct thread_info) + 2048))) {
diff --git a/arch/powerpc/kernel/misc.S b/arch/powerpc/kernel/misc.S
index 7ce26d45777e..0d432194c018 100644
--- a/arch/powerpc/kernel/misc.S
+++ b/arch/powerpc/kernel/misc.S
@@ -114,3 +114,7 @@ _GLOBAL(longjmp)
114 mtlr r0 114 mtlr r0
115 mr r3,r4 115 mr r3,r4
116 blr 116 blr
117
118_GLOBAL(current_stack_pointer)
119 PPC_LL r3,0(r1)
120 blr
diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c
index c4dfff6c2719..202963ee013a 100644
--- a/arch/powerpc/kernel/ppc_ksyms.c
+++ b/arch/powerpc/kernel/ppc_ksyms.c
@@ -41,3 +41,5 @@ EXPORT_SYMBOL(giveup_spe);
41#ifdef CONFIG_EPAPR_PARAVIRT 41#ifdef CONFIG_EPAPR_PARAVIRT
42EXPORT_SYMBOL(epapr_hypercall_start); 42EXPORT_SYMBOL(epapr_hypercall_start);
43#endif 43#endif
44
45EXPORT_SYMBOL(current_stack_pointer);
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index aa1df89c8b2a..923cd2daba89 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -1545,7 +1545,7 @@ void show_stack(struct task_struct *tsk, unsigned long *stack)
1545 tsk = current; 1545 tsk = current;
1546 if (sp == 0) { 1546 if (sp == 0) {
1547 if (tsk == current) 1547 if (tsk == current)
1548 asm("mr %0,1" : "=r" (sp)); 1548 sp = current_stack_pointer();
1549 else 1549 else
1550 sp = tsk->thread.ksp; 1550 sp = tsk->thread.ksp;
1551 } 1551 }
diff --git a/arch/powerpc/kernel/rtas_pci.c b/arch/powerpc/kernel/rtas_pci.c
index c168337aef9d..7c55b86206b3 100644
--- a/arch/powerpc/kernel/rtas_pci.c
+++ b/arch/powerpc/kernel/rtas_pci.c
@@ -66,6 +66,11 @@ int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
66 return PCIBIOS_DEVICE_NOT_FOUND; 66 return PCIBIOS_DEVICE_NOT_FOUND;
67 if (!config_access_valid(pdn, where)) 67 if (!config_access_valid(pdn, where))
68 return PCIBIOS_BAD_REGISTER_NUMBER; 68 return PCIBIOS_BAD_REGISTER_NUMBER;
69#ifdef CONFIG_EEH
70 if (pdn->edev && pdn->edev->pe &&
71 (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED))
72 return PCIBIOS_SET_FAILED;
73#endif
69 74
70 addr = rtas_config_addr(pdn->busno, pdn->devfn, where); 75 addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
71 buid = pdn->phb->buid; 76 buid = pdn->phb->buid;
@@ -90,9 +95,6 @@ static int rtas_pci_read_config(struct pci_bus *bus,
90 struct device_node *busdn, *dn; 95 struct device_node *busdn, *dn;
91 struct pci_dn *pdn; 96 struct pci_dn *pdn;
92 bool found = false; 97 bool found = false;
93#ifdef CONFIG_EEH
94 struct eeh_dev *edev;
95#endif
96 int ret; 98 int ret;
97 99
98 /* Search only direct children of the bus */ 100 /* Search only direct children of the bus */
@@ -109,11 +111,6 @@ static int rtas_pci_read_config(struct pci_bus *bus,
109 111
110 if (!found) 112 if (!found)
111 return PCIBIOS_DEVICE_NOT_FOUND; 113 return PCIBIOS_DEVICE_NOT_FOUND;
112#ifdef CONFIG_EEH
113 edev = of_node_to_eeh_dev(dn);
114 if (edev && edev->pe && edev->pe->state & EEH_PE_RESET)
115 return PCIBIOS_DEVICE_NOT_FOUND;
116#endif
117 114
118 ret = rtas_read_config(pdn, where, size, val); 115 ret = rtas_read_config(pdn, where, size, val);
119 if (*val == EEH_IO_ERROR_VALUE(size) && 116 if (*val == EEH_IO_ERROR_VALUE(size) &&
@@ -132,6 +129,11 @@ int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val)
132 return PCIBIOS_DEVICE_NOT_FOUND; 129 return PCIBIOS_DEVICE_NOT_FOUND;
133 if (!config_access_valid(pdn, where)) 130 if (!config_access_valid(pdn, where))
134 return PCIBIOS_BAD_REGISTER_NUMBER; 131 return PCIBIOS_BAD_REGISTER_NUMBER;
132#ifdef CONFIG_EEH
133 if (pdn->edev && pdn->edev->pe &&
134 (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED))
135 return PCIBIOS_SET_FAILED;
136#endif
135 137
136 addr = rtas_config_addr(pdn->busno, pdn->devfn, where); 138 addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
137 buid = pdn->phb->buid; 139 buid = pdn->phb->buid;
@@ -155,10 +157,6 @@ static int rtas_pci_write_config(struct pci_bus *bus,
155 struct device_node *busdn, *dn; 157 struct device_node *busdn, *dn;
156 struct pci_dn *pdn; 158 struct pci_dn *pdn;
157 bool found = false; 159 bool found = false;
158#ifdef CONFIG_EEH
159 struct eeh_dev *edev;
160#endif
161 int ret;
162 160
163 /* Search only direct children of the bus */ 161 /* Search only direct children of the bus */
164 busdn = pci_bus_to_OF_node(bus); 162 busdn = pci_bus_to_OF_node(bus);
@@ -173,14 +171,8 @@ static int rtas_pci_write_config(struct pci_bus *bus,
173 171
174 if (!found) 172 if (!found)
175 return PCIBIOS_DEVICE_NOT_FOUND; 173 return PCIBIOS_DEVICE_NOT_FOUND;
176#ifdef CONFIG_EEH
177 edev = of_node_to_eeh_dev(dn);
178 if (edev && edev->pe && (edev->pe->state & EEH_PE_RESET))
179 return PCIBIOS_DEVICE_NOT_FOUND;
180#endif
181 ret = rtas_write_config(pdn, where, size, val);
182 174
183 return ret; 175 return rtas_write_config(pdn, where, size, val);
184} 176}
185 177
186static struct pci_ops rtas_pci_ops = { 178static struct pci_ops rtas_pci_ops = {
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index cd07d79ad21c..4f3cfe1b6a33 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -522,36 +522,36 @@ void __init setup_system(void)
522 smp_release_cpus(); 522 smp_release_cpus();
523#endif 523#endif
524 524
525 printk("Starting Linux PPC64 %s\n", init_utsname()->version); 525 pr_info("Starting Linux PPC64 %s\n", init_utsname()->version);
526 526
527 printk("-----------------------------------------------------\n"); 527 pr_info("-----------------------------------------------------\n");
528 printk("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); 528 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
529 printk("phys_mem_size = 0x%llx\n", memblock_phys_mem_size()); 529 pr_info("phys_mem_size = 0x%llx\n", memblock_phys_mem_size());
530 530
531 if (ppc64_caches.dline_size != 0x80) 531 if (ppc64_caches.dline_size != 0x80)
532 printk("dcache_line_size = 0x%x\n", ppc64_caches.dline_size); 532 pr_info("dcache_line_size = 0x%x\n", ppc64_caches.dline_size);
533 if (ppc64_caches.iline_size != 0x80) 533 if (ppc64_caches.iline_size != 0x80)
534 printk("icache_line_size = 0x%x\n", ppc64_caches.iline_size); 534 pr_info("icache_line_size = 0x%x\n", ppc64_caches.iline_size);
535 535
536 printk("cpu_features = 0x%016lx\n", cur_cpu_spec->cpu_features); 536 pr_info("cpu_features = 0x%016lx\n", cur_cpu_spec->cpu_features);
537 printk(" possible = 0x%016lx\n", CPU_FTRS_POSSIBLE); 537 pr_info(" possible = 0x%016lx\n", CPU_FTRS_POSSIBLE);
538 printk(" always = 0x%016lx\n", CPU_FTRS_ALWAYS); 538 pr_info(" always = 0x%016lx\n", CPU_FTRS_ALWAYS);
539 printk("cpu_user_features = 0x%08x 0x%08x\n", cur_cpu_spec->cpu_user_features, 539 pr_info("cpu_user_features = 0x%08x 0x%08x\n", cur_cpu_spec->cpu_user_features,
540 cur_cpu_spec->cpu_user_features2); 540 cur_cpu_spec->cpu_user_features2);
541 printk("mmu_features = 0x%08x\n", cur_cpu_spec->mmu_features); 541 pr_info("mmu_features = 0x%08x\n", cur_cpu_spec->mmu_features);
542 printk("firmware_features = 0x%016lx\n", powerpc_firmware_features); 542 pr_info("firmware_features = 0x%016lx\n", powerpc_firmware_features);
543 543
544#ifdef CONFIG_PPC_STD_MMU_64 544#ifdef CONFIG_PPC_STD_MMU_64
545 if (htab_address) 545 if (htab_address)
546 printk("htab_address = 0x%p\n", htab_address); 546 pr_info("htab_address = 0x%p\n", htab_address);
547 547
548 printk("htab_hash_mask = 0x%lx\n", htab_hash_mask); 548 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask);
549#endif 549#endif
550 550
551 if (PHYSICAL_START > 0) 551 if (PHYSICAL_START > 0)
552 printk("physical_start = 0x%llx\n", 552 pr_info("physical_start = 0x%llx\n",
553 (unsigned long long)PHYSICAL_START); 553 (unsigned long long)PHYSICAL_START);
554 printk("-----------------------------------------------------\n"); 554 pr_info("-----------------------------------------------------\n");
555 555
556 DBG(" <- setup_system()\n"); 556 DBG(" <- setup_system()\n");
557} 557}
diff --git a/arch/powerpc/kernel/stacktrace.c b/arch/powerpc/kernel/stacktrace.c
index 3d30ef1038e5..ea43a347a104 100644
--- a/arch/powerpc/kernel/stacktrace.c
+++ b/arch/powerpc/kernel/stacktrace.c
@@ -50,7 +50,7 @@ void save_stack_trace(struct stack_trace *trace)
50{ 50{
51 unsigned long sp; 51 unsigned long sp;
52 52
53 asm("mr %0,1" : "=r" (sp)); 53 sp = current_stack_pointer();
54 54
55 save_context_stack(trace, sp, current, 1); 55 save_context_stack(trace, sp, current, 1);
56} 56}
diff --git a/arch/powerpc/mm/copro_fault.c b/arch/powerpc/mm/copro_fault.c
index 0f9939e693df..5a236f082c78 100644
--- a/arch/powerpc/mm/copro_fault.c
+++ b/arch/powerpc/mm/copro_fault.c
@@ -99,8 +99,6 @@ int copro_calculate_slb(struct mm_struct *mm, u64 ea, struct copro_slb *slb)
99 u64 vsid; 99 u64 vsid;
100 int psize, ssize; 100 int psize, ssize;
101 101
102 slb->esid = (ea & ESID_MASK) | SLB_ESID_V;
103
104 switch (REGION_ID(ea)) { 102 switch (REGION_ID(ea)) {
105 case USER_REGION_ID: 103 case USER_REGION_ID:
106 pr_devel("%s: 0x%llx -- USER_REGION_ID\n", __func__, ea); 104 pr_devel("%s: 0x%llx -- USER_REGION_ID\n", __func__, ea);
@@ -133,6 +131,7 @@ int copro_calculate_slb(struct mm_struct *mm, u64 ea, struct copro_slb *slb)
133 vsid |= mmu_psize_defs[psize].sllp | 131 vsid |= mmu_psize_defs[psize].sllp |
134 ((ssize == MMU_SEGSIZE_1T) ? SLB_VSID_B_1T : 0); 132 ((ssize == MMU_SEGSIZE_1T) ? SLB_VSID_B_1T : 0);
135 133
134 slb->esid = (ea & (ssize == MMU_SEGSIZE_1T ? ESID_MASK_1T : ESID_MASK)) | SLB_ESID_V;
136 slb->vsid = vsid; 135 slb->vsid = vsid;
137 136
138 return 0; 137 return 0;
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 649666d5d1c2..b9d1dfdbe5bb 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -8,6 +8,8 @@
8 * as published by the Free Software Foundation; either version 8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version. 9 * 2 of the License, or (at your option) any later version.
10 */ 10 */
11#define pr_fmt(fmt) "numa: " fmt
12
11#include <linux/threads.h> 13#include <linux/threads.h>
12#include <linux/bootmem.h> 14#include <linux/bootmem.h>
13#include <linux/init.h> 15#include <linux/init.h>
@@ -1153,6 +1155,22 @@ static int __init early_numa(char *p)
1153} 1155}
1154early_param("numa", early_numa); 1156early_param("numa", early_numa);
1155 1157
1158static bool topology_updates_enabled = true;
1159
1160static int __init early_topology_updates(char *p)
1161{
1162 if (!p)
1163 return 0;
1164
1165 if (!strcmp(p, "off")) {
1166 pr_info("Disabling topology updates\n");
1167 topology_updates_enabled = false;
1168 }
1169
1170 return 0;
1171}
1172early_param("topology_updates", early_topology_updates);
1173
1156#ifdef CONFIG_MEMORY_HOTPLUG 1174#ifdef CONFIG_MEMORY_HOTPLUG
1157/* 1175/*
1158 * Find the node associated with a hot added memory section for 1176 * Find the node associated with a hot added memory section for
@@ -1442,8 +1460,11 @@ static long hcall_vphn(unsigned long cpu, __be32 *associativity)
1442 long retbuf[PLPAR_HCALL9_BUFSIZE] = {0}; 1460 long retbuf[PLPAR_HCALL9_BUFSIZE] = {0};
1443 u64 flags = 1; 1461 u64 flags = 1;
1444 int hwcpu = get_hard_smp_processor_id(cpu); 1462 int hwcpu = get_hard_smp_processor_id(cpu);
1463 int i;
1445 1464
1446 rc = plpar_hcall9(H_HOME_NODE_ASSOCIATIVITY, retbuf, flags, hwcpu); 1465 rc = plpar_hcall9(H_HOME_NODE_ASSOCIATIVITY, retbuf, flags, hwcpu);
1466 for (i = 0; i < 6; i++)
1467 retbuf[i] = cpu_to_be64(retbuf[i]);
1447 vphn_unpack_associativity(retbuf, associativity); 1468 vphn_unpack_associativity(retbuf, associativity);
1448 1469
1449 return rc; 1470 return rc;
@@ -1488,11 +1509,14 @@ static int update_cpu_topology(void *data)
1488 cpu = smp_processor_id(); 1509 cpu = smp_processor_id();
1489 1510
1490 for (update = data; update; update = update->next) { 1511 for (update = data; update; update = update->next) {
1512 int new_nid = update->new_nid;
1491 if (cpu != update->cpu) 1513 if (cpu != update->cpu)
1492 continue; 1514 continue;
1493 1515
1494 unmap_cpu_from_node(update->cpu); 1516 unmap_cpu_from_node(cpu);
1495 map_cpu_to_node(update->cpu, update->new_nid); 1517 map_cpu_to_node(cpu, new_nid);
1518 set_cpu_numa_node(cpu, new_nid);
1519 set_cpu_numa_mem(cpu, local_memory_node(new_nid));
1496 vdso_getcpu_init(); 1520 vdso_getcpu_init();
1497 } 1521 }
1498 1522
@@ -1539,6 +1563,9 @@ int arch_update_cpu_topology(void)
1539 struct device *dev; 1563 struct device *dev;
1540 int weight, new_nid, i = 0; 1564 int weight, new_nid, i = 0;
1541 1565
1566 if (!prrn_enabled && !vphn_enabled)
1567 return 0;
1568
1542 weight = cpumask_weight(&cpu_associativity_changes_mask); 1569 weight = cpumask_weight(&cpu_associativity_changes_mask);
1543 if (!weight) 1570 if (!weight)
1544 return 0; 1571 return 0;
@@ -1592,6 +1619,15 @@ int arch_update_cpu_topology(void)
1592 cpu = cpu_last_thread_sibling(cpu); 1619 cpu = cpu_last_thread_sibling(cpu);
1593 } 1620 }
1594 1621
1622 pr_debug("Topology update for the following CPUs:\n");
1623 if (cpumask_weight(&updated_cpus)) {
1624 for (ud = &updates[0]; ud; ud = ud->next) {
1625 pr_debug("cpu %d moving from node %d "
1626 "to %d\n", ud->cpu,
1627 ud->old_nid, ud->new_nid);
1628 }
1629 }
1630
1595 /* 1631 /*
1596 * In cases where we have nothing to update (because the updates list 1632 * In cases where we have nothing to update (because the updates list
1597 * is too short or because the new topology is same as the old one), 1633 * is too short or because the new topology is same as the old one),
@@ -1800,8 +1836,12 @@ static const struct file_operations topology_ops = {
1800 1836
1801static int topology_update_init(void) 1837static int topology_update_init(void)
1802{ 1838{
1803 start_topology_update(); 1839 /* Do not poll for changes if disabled at boot */
1804 proc_create("powerpc/topology_updates", 0644, NULL, &topology_ops); 1840 if (topology_updates_enabled)
1841 start_topology_update();
1842
1843 if (!proc_create("powerpc/topology_updates", 0644, NULL, &topology_ops))
1844 return -ENOMEM;
1805 1845
1806 return 0; 1846 return 0;
1807} 1847}
diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
index 8d7bda94d196..ded0ea1afde4 100644
--- a/arch/powerpc/mm/slice.c
+++ b/arch/powerpc/mm/slice.c
@@ -682,6 +682,7 @@ void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
682 slice_convert(mm, mask, psize); 682 slice_convert(mm, mask, psize);
683} 683}
684 684
685#ifdef CONFIG_HUGETLB_PAGE
685/* 686/*
686 * is_hugepage_only_range() is used by generic code to verify whether 687 * is_hugepage_only_range() is used by generic code to verify whether
687 * a normal mmap mapping (non hugetlbfs) is valid on a given area. 688 * a normal mmap mapping (non hugetlbfs) is valid on a given area.
@@ -726,4 +727,4 @@ int is_hugepage_only_range(struct mm_struct *mm, unsigned long addr,
726#endif 727#endif
727 return !slice_check_fit(mask, available); 728 return !slice_check_fit(mask, available);
728} 729}
729 730#endif
diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/perf/hv-24x7.c
index 6c8710dd90c9..dba34088da28 100644
--- a/arch/powerpc/perf/hv-24x7.c
+++ b/arch/powerpc/perf/hv-24x7.c
@@ -417,11 +417,6 @@ static int h_24x7_event_add(struct perf_event *event, int flags)
417 return 0; 417 return 0;
418} 418}
419 419
420static int h_24x7_event_idx(struct perf_event *event)
421{
422 return 0;
423}
424
425static struct pmu h_24x7_pmu = { 420static struct pmu h_24x7_pmu = {
426 .task_ctx_nr = perf_invalid_context, 421 .task_ctx_nr = perf_invalid_context,
427 422
@@ -433,7 +428,6 @@ static struct pmu h_24x7_pmu = {
433 .start = h_24x7_event_start, 428 .start = h_24x7_event_start,
434 .stop = h_24x7_event_stop, 429 .stop = h_24x7_event_stop,
435 .read = h_24x7_event_update, 430 .read = h_24x7_event_update,
436 .event_idx = h_24x7_event_idx,
437}; 431};
438 432
439static int hv_24x7_init(void) 433static int hv_24x7_init(void)
diff --git a/arch/powerpc/perf/hv-gpci.c b/arch/powerpc/perf/hv-gpci.c
index 15fc76c93022..a051fe946c63 100644
--- a/arch/powerpc/perf/hv-gpci.c
+++ b/arch/powerpc/perf/hv-gpci.c
@@ -246,11 +246,6 @@ static int h_gpci_event_init(struct perf_event *event)
246 return 0; 246 return 0;
247} 247}
248 248
249static int h_gpci_event_idx(struct perf_event *event)
250{
251 return 0;
252}
253
254static struct pmu h_gpci_pmu = { 249static struct pmu h_gpci_pmu = {
255 .task_ctx_nr = perf_invalid_context, 250 .task_ctx_nr = perf_invalid_context,
256 251
@@ -262,7 +257,6 @@ static struct pmu h_gpci_pmu = {
262 .start = h_gpci_event_start, 257 .start = h_gpci_event_start,
263 .stop = h_gpci_event_stop, 258 .stop = h_gpci_event_stop,
264 .read = h_gpci_event_update, 259 .read = h_gpci_event_update,
265 .event_idx = h_gpci_event_idx,
266}; 260};
267 261
268static int hv_gpci_init(void) 262static int hv_gpci_init(void)
diff --git a/arch/powerpc/platforms/powernv/eeh-ioda.c b/arch/powerpc/platforms/powernv/eeh-ioda.c
index 426814a2ede3..eba9cb10619c 100644
--- a/arch/powerpc/platforms/powernv/eeh-ioda.c
+++ b/arch/powerpc/platforms/powernv/eeh-ioda.c
@@ -373,7 +373,7 @@ static int ioda_eeh_get_pe_state(struct eeh_pe *pe)
373 * moving forward, we have to return operational 373 * moving forward, we have to return operational
374 * state during PE reset. 374 * state during PE reset.
375 */ 375 */
376 if (pe->state & EEH_PE_RESET) { 376 if (pe->state & EEH_PE_CFG_BLOCKED) {
377 result = (EEH_STATE_MMIO_ACTIVE | 377 result = (EEH_STATE_MMIO_ACTIVE |
378 EEH_STATE_DMA_ACTIVE | 378 EEH_STATE_DMA_ACTIVE |
379 EEH_STATE_MMIO_ENABLED | 379 EEH_STATE_MMIO_ENABLED |
diff --git a/arch/powerpc/platforms/powernv/eeh-powernv.c b/arch/powerpc/platforms/powernv/eeh-powernv.c
index 3e89cbf55885..1d19e7917d7f 100644
--- a/arch/powerpc/platforms/powernv/eeh-powernv.c
+++ b/arch/powerpc/platforms/powernv/eeh-powernv.c
@@ -169,6 +169,26 @@ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag)
169 } 169 }
170 170
171 /* 171 /*
172 * If the PE contains any one of following adapters, the
173 * PCI config space can't be accessed when dumping EEH log.
174 * Otherwise, we will run into fenced PHB caused by shortage
175 * of outbound credits in the adapter. The PCI config access
176 * should be blocked until PE reset. MMIO access is dropped
177 * by hardware certainly. In order to drop PCI config requests,
178 * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which
179 * will be checked in the backend for PE state retrival. If
180 * the PE becomes frozen for the first time and the flag has
181 * been set for the PE, we will set EEH_PE_CFG_BLOCKED for
182 * that PE to block its config space.
183 *
184 * Broadcom Austin 4-ports NICs (14e4:1657)
185 * Broadcom Shiner 2-ports 10G NICs (14e4:168e)
186 */
187 if ((dev->vendor == PCI_VENDOR_ID_BROADCOM && dev->device == 0x1657) ||
188 (dev->vendor == PCI_VENDOR_ID_BROADCOM && dev->device == 0x168e))
189 edev->pe->state |= EEH_PE_CFG_RESTRICTED;
190
191 /*
172 * Cache the PE primary bus, which can't be fetched when 192 * Cache the PE primary bus, which can't be fetched when
173 * full hotplug is in progress. In that case, all child 193 * full hotplug is in progress. In that case, all child
174 * PCI devices of the PE are expected to be removed prior 194 * PCI devices of the PE are expected to be removed prior
@@ -383,6 +403,39 @@ static int powernv_eeh_err_inject(struct eeh_pe *pe, int type, int func,
383 return ret; 403 return ret;
384} 404}
385 405
406static inline bool powernv_eeh_cfg_blocked(struct device_node *dn)
407{
408 struct eeh_dev *edev = of_node_to_eeh_dev(dn);
409
410 if (!edev || !edev->pe)
411 return false;
412
413 if (edev->pe->state & EEH_PE_CFG_BLOCKED)
414 return true;
415
416 return false;
417}
418
419static int powernv_eeh_read_config(struct device_node *dn,
420 int where, int size, u32 *val)
421{
422 if (powernv_eeh_cfg_blocked(dn)) {
423 *val = 0xFFFFFFFF;
424 return PCIBIOS_SET_FAILED;
425 }
426
427 return pnv_pci_cfg_read(dn, where, size, val);
428}
429
430static int powernv_eeh_write_config(struct device_node *dn,
431 int where, int size, u32 val)
432{
433 if (powernv_eeh_cfg_blocked(dn))
434 return PCIBIOS_SET_FAILED;
435
436 return pnv_pci_cfg_write(dn, where, size, val);
437}
438
386/** 439/**
387 * powernv_eeh_next_error - Retrieve next EEH error to handle 440 * powernv_eeh_next_error - Retrieve next EEH error to handle
388 * @pe: Affected PE 441 * @pe: Affected PE
@@ -440,8 +493,8 @@ static struct eeh_ops powernv_eeh_ops = {
440 .get_log = powernv_eeh_get_log, 493 .get_log = powernv_eeh_get_log,
441 .configure_bridge = powernv_eeh_configure_bridge, 494 .configure_bridge = powernv_eeh_configure_bridge,
442 .err_inject = powernv_eeh_err_inject, 495 .err_inject = powernv_eeh_err_inject,
443 .read_config = pnv_pci_cfg_read, 496 .read_config = powernv_eeh_read_config,
444 .write_config = pnv_pci_cfg_write, 497 .write_config = powernv_eeh_write_config,
445 .next_error = powernv_eeh_next_error, 498 .next_error = powernv_eeh_next_error,
446 .restore_config = powernv_eeh_restore_config 499 .restore_config = powernv_eeh_restore_config
447}; 500};
diff --git a/arch/powerpc/platforms/powernv/opal-lpc.c b/arch/powerpc/platforms/powernv/opal-lpc.c
index dd2c285ad170..ad4b31df779a 100644
--- a/arch/powerpc/platforms/powernv/opal-lpc.c
+++ b/arch/powerpc/platforms/powernv/opal-lpc.c
@@ -191,7 +191,6 @@ static ssize_t lpc_debug_read(struct file *filp, char __user *ubuf,
191{ 191{
192 struct lpc_debugfs_entry *lpc = filp->private_data; 192 struct lpc_debugfs_entry *lpc = filp->private_data;
193 u32 data, pos, len, todo; 193 u32 data, pos, len, todo;
194 __be32 bedata;
195 int rc; 194 int rc;
196 195
197 if (!access_ok(VERIFY_WRITE, ubuf, count)) 196 if (!access_ok(VERIFY_WRITE, ubuf, count))
@@ -214,10 +213,9 @@ static ssize_t lpc_debug_read(struct file *filp, char __user *ubuf,
214 len = 2; 213 len = 2;
215 } 214 }
216 rc = opal_lpc_read(opal_lpc_chip_id, lpc->lpc_type, pos, 215 rc = opal_lpc_read(opal_lpc_chip_id, lpc->lpc_type, pos,
217 &bedata, len); 216 &data, len);
218 if (rc) 217 if (rc)
219 return -ENXIO; 218 return -ENXIO;
220 data = be32_to_cpu(bedata);
221 switch(len) { 219 switch(len) {
222 case 4: 220 case 4:
223 rc = __put_user((u32)data, (u32 __user *)ubuf); 221 rc = __put_user((u32)data, (u32 __user *)ubuf);
diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S
index e9e2450c1fdd..feb549aa3eea 100644
--- a/arch/powerpc/platforms/powernv/opal-wrappers.S
+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
@@ -58,7 +58,7 @@ END_FTR_SECTION(0, 1); \
58 */ 58 */
59 59
60#define OPAL_CALL(name, token) \ 60#define OPAL_CALL(name, token) \
61 _GLOBAL(name); \ 61 _GLOBAL_TOC(name); \
62 mflr r0; \ 62 mflr r0; \
63 std r0,16(r1); \ 63 std r0,16(r1); \
64 li r0,token; \ 64 li r0,token; \
diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
index b642b0562f5a..d019b081df9d 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -194,6 +194,27 @@ static int __init opal_register_exception_handlers(void)
194 * fwnmi area at 0x7000 to provide the glue space to OPAL 194 * fwnmi area at 0x7000 to provide the glue space to OPAL
195 */ 195 */
196 glue = 0x7000; 196 glue = 0x7000;
197
198 /*
199 * Check if we are running on newer firmware that exports
200 * OPAL_HANDLE_HMI token. If yes, then don't ask OPAL to patch
201 * the HMI interrupt and we catch it directly in Linux.
202 *
203 * For older firmware (i.e currently released POWER8 System Firmware
204 * as of today <= SV810_087), we fallback to old behavior and let OPAL
205 * patch the HMI vector and handle it inside OPAL firmware.
206 *
207 * For newer firmware (in development/yet to be released) we will
208 * start catching/handling HMI directly in Linux.
209 */
210 if (!opal_check_token(OPAL_HANDLE_HMI)) {
211 pr_info("opal: Old firmware detected, OPAL handles HMIs.\n");
212 opal_register_exception_handler(
213 OPAL_HYPERVISOR_MAINTENANCE_HANDLER,
214 0, glue);
215 glue += 128;
216 }
217
197 opal_register_exception_handler(OPAL_SOFTPATCH_HANDLER, 0, glue); 218 opal_register_exception_handler(OPAL_SOFTPATCH_HANDLER, 0, glue);
198#endif 219#endif
199 220
diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index b3ca77ddf36d..b2187d0068b8 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -505,7 +505,7 @@ static bool pnv_pci_cfg_check(struct pci_controller *hose,
505 edev = of_node_to_eeh_dev(dn); 505 edev = of_node_to_eeh_dev(dn);
506 if (edev) { 506 if (edev) {
507 if (edev->pe && 507 if (edev->pe &&
508 (edev->pe->state & EEH_PE_RESET)) 508 (edev->pe->state & EEH_PE_CFG_BLOCKED))
509 return false; 509 return false;
510 510
511 if (edev->mode & EEH_DEV_REMOVED) 511 if (edev->mode & EEH_DEV_REMOVED)
diff --git a/arch/powerpc/platforms/pseries/dlpar.c b/arch/powerpc/platforms/pseries/dlpar.c
index fdf01b660d59..6ad83bd11fe2 100644
--- a/arch/powerpc/platforms/pseries/dlpar.c
+++ b/arch/powerpc/platforms/pseries/dlpar.c
@@ -25,11 +25,11 @@
25#include <asm/rtas.h> 25#include <asm/rtas.h>
26 26
27struct cc_workarea { 27struct cc_workarea {
28 u32 drc_index; 28 __be32 drc_index;
29 u32 zero; 29 __be32 zero;
30 u32 name_offset; 30 __be32 name_offset;
31 u32 prop_length; 31 __be32 prop_length;
32 u32 prop_offset; 32 __be32 prop_offset;
33}; 33};
34 34
35void dlpar_free_cc_property(struct property *prop) 35void dlpar_free_cc_property(struct property *prop)
@@ -49,11 +49,11 @@ static struct property *dlpar_parse_cc_property(struct cc_workarea *ccwa)
49 if (!prop) 49 if (!prop)
50 return NULL; 50 return NULL;
51 51
52 name = (char *)ccwa + ccwa->name_offset; 52 name = (char *)ccwa + be32_to_cpu(ccwa->name_offset);
53 prop->name = kstrdup(name, GFP_KERNEL); 53 prop->name = kstrdup(name, GFP_KERNEL);
54 54
55 prop->length = ccwa->prop_length; 55 prop->length = be32_to_cpu(ccwa->prop_length);
56 value = (char *)ccwa + ccwa->prop_offset; 56 value = (char *)ccwa + be32_to_cpu(ccwa->prop_offset);
57 prop->value = kmemdup(value, prop->length, GFP_KERNEL); 57 prop->value = kmemdup(value, prop->length, GFP_KERNEL);
58 if (!prop->value) { 58 if (!prop->value) {
59 dlpar_free_cc_property(prop); 59 dlpar_free_cc_property(prop);
@@ -79,7 +79,7 @@ static struct device_node *dlpar_parse_cc_node(struct cc_workarea *ccwa,
79 if (!dn) 79 if (!dn)
80 return NULL; 80 return NULL;
81 81
82 name = (char *)ccwa + ccwa->name_offset; 82 name = (char *)ccwa + be32_to_cpu(ccwa->name_offset);
83 dn->full_name = kasprintf(GFP_KERNEL, "%s/%s", path, name); 83 dn->full_name = kasprintf(GFP_KERNEL, "%s/%s", path, name);
84 if (!dn->full_name) { 84 if (!dn->full_name) {
85 kfree(dn); 85 kfree(dn);
@@ -126,7 +126,7 @@ void dlpar_free_cc_nodes(struct device_node *dn)
126#define CALL_AGAIN -2 126#define CALL_AGAIN -2
127#define ERR_CFG_USE -9003 127#define ERR_CFG_USE -9003
128 128
129struct device_node *dlpar_configure_connector(u32 drc_index, 129struct device_node *dlpar_configure_connector(__be32 drc_index,
130 struct device_node *parent) 130 struct device_node *parent)
131{ 131{
132 struct device_node *dn; 132 struct device_node *dn;
@@ -414,7 +414,7 @@ static ssize_t dlpar_cpu_probe(const char *buf, size_t count)
414 if (!parent) 414 if (!parent)
415 return -ENODEV; 415 return -ENODEV;
416 416
417 dn = dlpar_configure_connector(drc_index, parent); 417 dn = dlpar_configure_connector(cpu_to_be32(drc_index), parent);
418 if (!dn) 418 if (!dn)
419 return -EINVAL; 419 return -EINVAL;
420 420
diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c b/arch/powerpc/platforms/pseries/hotplug-cpu.c
index b174fa751d26..5c375f93c669 100644
--- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
+++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
@@ -247,7 +247,7 @@ static int pseries_add_processor(struct device_node *np)
247 unsigned int cpu; 247 unsigned int cpu;
248 cpumask_var_t candidate_mask, tmp; 248 cpumask_var_t candidate_mask, tmp;
249 int err = -ENOSPC, len, nthreads, i; 249 int err = -ENOSPC, len, nthreads, i;
250 const u32 *intserv; 250 const __be32 *intserv;
251 251
252 intserv = of_get_property(np, "ibm,ppc-interrupt-server#s", &len); 252 intserv = of_get_property(np, "ibm,ppc-interrupt-server#s", &len);
253 if (!intserv) 253 if (!intserv)
@@ -293,7 +293,7 @@ static int pseries_add_processor(struct device_node *np)
293 for_each_cpu(cpu, tmp) { 293 for_each_cpu(cpu, tmp) {
294 BUG_ON(cpu_present(cpu)); 294 BUG_ON(cpu_present(cpu));
295 set_cpu_present(cpu, true); 295 set_cpu_present(cpu, true);
296 set_hard_smp_processor_id(cpu, *intserv++); 296 set_hard_smp_processor_id(cpu, be32_to_cpu(*intserv++));
297 } 297 }
298 err = 0; 298 err = 0;
299out_unlock: 299out_unlock:
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
index de1ec54a2a57..e32e00976a94 100644
--- a/arch/powerpc/platforms/pseries/iommu.c
+++ b/arch/powerpc/platforms/pseries/iommu.c
@@ -30,7 +30,6 @@
30#include <linux/mm.h> 30#include <linux/mm.h>
31#include <linux/memblock.h> 31#include <linux/memblock.h>
32#include <linux/spinlock.h> 32#include <linux/spinlock.h>
33#include <linux/sched.h> /* for show_stack */
34#include <linux/string.h> 33#include <linux/string.h>
35#include <linux/pci.h> 34#include <linux/pci.h>
36#include <linux/dma-mapping.h> 35#include <linux/dma-mapping.h>
@@ -168,7 +167,7 @@ static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
168 printk("\tindex = 0x%llx\n", (u64)tbl->it_index); 167 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
169 printk("\ttcenum = 0x%llx\n", (u64)tcenum); 168 printk("\ttcenum = 0x%llx\n", (u64)tcenum);
170 printk("\ttce val = 0x%llx\n", tce ); 169 printk("\ttce val = 0x%llx\n", tce );
171 show_stack(current, (unsigned long *)__get_SP()); 170 dump_stack();
172 } 171 }
173 172
174 tcenum++; 173 tcenum++;
@@ -257,7 +256,7 @@ static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
257 printk("\tindex = 0x%llx\n", (u64)tbl->it_index); 256 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
258 printk("\tnpages = 0x%llx\n", (u64)npages); 257 printk("\tnpages = 0x%llx\n", (u64)npages);
259 printk("\ttce[0] val = 0x%llx\n", tcep[0]); 258 printk("\ttce[0] val = 0x%llx\n", tcep[0]);
260 show_stack(current, (unsigned long *)__get_SP()); 259 dump_stack();
261 } 260 }
262 return ret; 261 return ret;
263} 262}
@@ -273,7 +272,7 @@ static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages
273 printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc); 272 printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
274 printk("\tindex = 0x%llx\n", (u64)tbl->it_index); 273 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
275 printk("\ttcenum = 0x%llx\n", (u64)tcenum); 274 printk("\ttcenum = 0x%llx\n", (u64)tcenum);
276 show_stack(current, (unsigned long *)__get_SP()); 275 dump_stack();
277 } 276 }
278 277
279 tcenum++; 278 tcenum++;
@@ -292,7 +291,7 @@ static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long n
292 printk("\trc = %lld\n", rc); 291 printk("\trc = %lld\n", rc);
293 printk("\tindex = 0x%llx\n", (u64)tbl->it_index); 292 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
294 printk("\tnpages = 0x%llx\n", (u64)npages); 293 printk("\tnpages = 0x%llx\n", (u64)npages);
295 show_stack(current, (unsigned long *)__get_SP()); 294 dump_stack();
296 } 295 }
297} 296}
298 297
@@ -307,7 +306,7 @@ static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum)
307 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc); 306 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc);
308 printk("\tindex = 0x%llx\n", (u64)tbl->it_index); 307 printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
309 printk("\ttcenum = 0x%llx\n", (u64)tcenum); 308 printk("\ttcenum = 0x%llx\n", (u64)tcenum);
310 show_stack(current, (unsigned long *)__get_SP()); 309 dump_stack();
311 } 310 }
312 311
313 return tce_ret; 312 return tce_ret;
diff --git a/arch/powerpc/platforms/pseries/pseries.h b/arch/powerpc/platforms/pseries/pseries.h
index 361add62abf1..1796c5438cc6 100644
--- a/arch/powerpc/platforms/pseries/pseries.h
+++ b/arch/powerpc/platforms/pseries/pseries.h
@@ -56,7 +56,8 @@ extern void hvc_vio_init_early(void);
56/* Dynamic logical Partitioning/Mobility */ 56/* Dynamic logical Partitioning/Mobility */
57extern void dlpar_free_cc_nodes(struct device_node *); 57extern void dlpar_free_cc_nodes(struct device_node *);
58extern void dlpar_free_cc_property(struct property *); 58extern void dlpar_free_cc_property(struct property *);
59extern struct device_node *dlpar_configure_connector(u32, struct device_node *); 59extern struct device_node *dlpar_configure_connector(__be32,
60 struct device_node *);
60extern int dlpar_attach_node(struct device_node *); 61extern int dlpar_attach_node(struct device_node *);
61extern int dlpar_detach_node(struct device_node *); 62extern int dlpar_detach_node(struct device_node *);
62 63
diff --git a/arch/powerpc/sysdev/msi_bitmap.c b/arch/powerpc/sysdev/msi_bitmap.c
index 0c75214b6f92..73b64c73505b 100644
--- a/arch/powerpc/sysdev/msi_bitmap.c
+++ b/arch/powerpc/sysdev/msi_bitmap.c
@@ -145,59 +145,64 @@ void msi_bitmap_free(struct msi_bitmap *bmp)
145 145
146#ifdef CONFIG_MSI_BITMAP_SELFTEST 146#ifdef CONFIG_MSI_BITMAP_SELFTEST
147 147
148#define check(x) \
149 if (!(x)) printk("msi_bitmap: test failed at line %d\n", __LINE__);
150
151static void __init test_basics(void) 148static void __init test_basics(void)
152{ 149{
153 struct msi_bitmap bmp; 150 struct msi_bitmap bmp;
154 int i, size = 512; 151 int rc, i, size = 512;
155 152
156 /* Can't allocate a bitmap of 0 irqs */ 153 /* Can't allocate a bitmap of 0 irqs */
157 check(msi_bitmap_alloc(&bmp, 0, NULL) != 0); 154 WARN_ON(msi_bitmap_alloc(&bmp, 0, NULL) == 0);
158 155
159 /* of_node may be NULL */ 156 /* of_node may be NULL */
160 check(0 == msi_bitmap_alloc(&bmp, size, NULL)); 157 WARN_ON(msi_bitmap_alloc(&bmp, size, NULL));
161 158
162 /* Should all be free by default */ 159 /* Should all be free by default */
163 check(0 == bitmap_find_free_region(bmp.bitmap, size, 160 WARN_ON(bitmap_find_free_region(bmp.bitmap, size, get_count_order(size)));
164 get_count_order(size)));
165 bitmap_release_region(bmp.bitmap, 0, get_count_order(size)); 161 bitmap_release_region(bmp.bitmap, 0, get_count_order(size));
166 162
167 /* With no node, there's no msi-available-ranges, so expect > 0 */ 163 /* With no node, there's no msi-available-ranges, so expect > 0 */
168 check(msi_bitmap_reserve_dt_hwirqs(&bmp) > 0); 164 WARN_ON(msi_bitmap_reserve_dt_hwirqs(&bmp) <= 0);
169 165
170 /* Should all still be free */ 166 /* Should all still be free */
171 check(0 == bitmap_find_free_region(bmp.bitmap, size, 167 WARN_ON(bitmap_find_free_region(bmp.bitmap, size, get_count_order(size)));
172 get_count_order(size)));
173 bitmap_release_region(bmp.bitmap, 0, get_count_order(size)); 168 bitmap_release_region(bmp.bitmap, 0, get_count_order(size));
174 169
175 /* Check we can fill it up and then no more */ 170 /* Check we can fill it up and then no more */
176 for (i = 0; i < size; i++) 171 for (i = 0; i < size; i++)
177 check(msi_bitmap_alloc_hwirqs(&bmp, 1) >= 0); 172 WARN_ON(msi_bitmap_alloc_hwirqs(&bmp, 1) < 0);
178 173
179 check(msi_bitmap_alloc_hwirqs(&bmp, 1) < 0); 174 WARN_ON(msi_bitmap_alloc_hwirqs(&bmp, 1) >= 0);
180 175
181 /* Should all be allocated */ 176 /* Should all be allocated */
182 check(bitmap_find_free_region(bmp.bitmap, size, 0) < 0); 177 WARN_ON(bitmap_find_free_region(bmp.bitmap, size, 0) >= 0);
183 178
184 /* And if we free one we can then allocate another */ 179 /* And if we free one we can then allocate another */
185 msi_bitmap_free_hwirqs(&bmp, size / 2, 1); 180 msi_bitmap_free_hwirqs(&bmp, size / 2, 1);
186 check(msi_bitmap_alloc_hwirqs(&bmp, 1) == size / 2); 181 WARN_ON(msi_bitmap_alloc_hwirqs(&bmp, 1) != size / 2);
182
183 /* Free most of them for the alignment tests */
184 msi_bitmap_free_hwirqs(&bmp, 3, size - 3);
187 185
188 /* Check we get a naturally aligned offset */ 186 /* Check we get a naturally aligned offset */
189 check(msi_bitmap_alloc_hwirqs(&bmp, 2) % 2 == 0); 187 rc = msi_bitmap_alloc_hwirqs(&bmp, 2);
190 check(msi_bitmap_alloc_hwirqs(&bmp, 4) % 4 == 0); 188 WARN_ON(rc < 0 && rc % 2 != 0);
191 check(msi_bitmap_alloc_hwirqs(&bmp, 8) % 8 == 0); 189 rc = msi_bitmap_alloc_hwirqs(&bmp, 4);
192 check(msi_bitmap_alloc_hwirqs(&bmp, 9) % 16 == 0); 190 WARN_ON(rc < 0 && rc % 4 != 0);
193 check(msi_bitmap_alloc_hwirqs(&bmp, 3) % 4 == 0); 191 rc = msi_bitmap_alloc_hwirqs(&bmp, 8);
194 check(msi_bitmap_alloc_hwirqs(&bmp, 7) % 8 == 0); 192 WARN_ON(rc < 0 && rc % 8 != 0);
195 check(msi_bitmap_alloc_hwirqs(&bmp, 121) % 128 == 0); 193 rc = msi_bitmap_alloc_hwirqs(&bmp, 9);
194 WARN_ON(rc < 0 && rc % 16 != 0);
195 rc = msi_bitmap_alloc_hwirqs(&bmp, 3);
196 WARN_ON(rc < 0 && rc % 4 != 0);
197 rc = msi_bitmap_alloc_hwirqs(&bmp, 7);
198 WARN_ON(rc < 0 && rc % 8 != 0);
199 rc = msi_bitmap_alloc_hwirqs(&bmp, 121);
200 WARN_ON(rc < 0 && rc % 128 != 0);
196 201
197 msi_bitmap_free(&bmp); 202 msi_bitmap_free(&bmp);
198 203
199 /* Clients may check bitmap == NULL for "not-allocated" */ 204 /* Clients may WARN_ON bitmap == NULL for "not-allocated" */
200 check(bmp.bitmap == NULL); 205 WARN_ON(bmp.bitmap != NULL);
201 206
202 kfree(bmp.bitmap); 207 kfree(bmp.bitmap);
203} 208}
@@ -219,14 +224,13 @@ static void __init test_of_node(void)
219 of_node_init(&of_node); 224 of_node_init(&of_node);
220 of_node.full_name = node_name; 225 of_node.full_name = node_name;
221 226
222 check(0 == msi_bitmap_alloc(&bmp, size, &of_node)); 227 WARN_ON(msi_bitmap_alloc(&bmp, size, &of_node));
223 228
224 /* No msi-available-ranges, so expect > 0 */ 229 /* No msi-available-ranges, so expect > 0 */
225 check(msi_bitmap_reserve_dt_hwirqs(&bmp) > 0); 230 WARN_ON(msi_bitmap_reserve_dt_hwirqs(&bmp) <= 0);
226 231
227 /* Should all still be free */ 232 /* Should all still be free */
228 check(0 == bitmap_find_free_region(bmp.bitmap, size, 233 WARN_ON(bitmap_find_free_region(bmp.bitmap, size, get_count_order(size)));
229 get_count_order(size)));
230 bitmap_release_region(bmp.bitmap, 0, get_count_order(size)); 234 bitmap_release_region(bmp.bitmap, 0, get_count_order(size));
231 235
232 /* Now create a fake msi-available-ranges property */ 236 /* Now create a fake msi-available-ranges property */
@@ -240,11 +244,11 @@ static void __init test_of_node(void)
240 of_node.properties = &prop; 244 of_node.properties = &prop;
241 245
242 /* msi-available-ranges, so expect == 0 */ 246 /* msi-available-ranges, so expect == 0 */
243 check(msi_bitmap_reserve_dt_hwirqs(&bmp) == 0); 247 WARN_ON(msi_bitmap_reserve_dt_hwirqs(&bmp));
244 248
245 /* Check we got the expected result */ 249 /* Check we got the expected result */
246 check(0 == bitmap_parselist(expected_str, expected, size)); 250 WARN_ON(bitmap_parselist(expected_str, expected, size));
247 check(bitmap_equal(expected, bmp.bitmap, size)); 251 WARN_ON(!bitmap_equal(expected, bmp.bitmap, size));
248 252
249 msi_bitmap_free(&bmp); 253 msi_bitmap_free(&bmp);
250 kfree(bmp.bitmap); 254 kfree(bmp.bitmap);
diff --git a/arch/s390/include/uapi/asm/unistd.h b/arch/s390/include/uapi/asm/unistd.h
index 940ac49198db..4197c89c52d4 100644
--- a/arch/s390/include/uapi/asm/unistd.h
+++ b/arch/s390/include/uapi/asm/unistd.h
@@ -286,7 +286,8 @@
286#define __NR_seccomp 348 286#define __NR_seccomp 348
287#define __NR_getrandom 349 287#define __NR_getrandom 349
288#define __NR_memfd_create 350 288#define __NR_memfd_create 350
289#define NR_syscalls 351 289#define __NR_bpf 351
290#define NR_syscalls 352
290 291
291/* 292/*
292 * There are some system calls that are not present on 64 bit, some 293 * There are some system calls that are not present on 64 bit, some
diff --git a/arch/s390/kernel/compat_wrapper.c b/arch/s390/kernel/compat_wrapper.c
index faf6caa510dc..c4f7a3d655b8 100644
--- a/arch/s390/kernel/compat_wrapper.c
+++ b/arch/s390/kernel/compat_wrapper.c
@@ -217,3 +217,4 @@ COMPAT_SYSCALL_WRAP5(renameat2, int, olddfd, const char __user *, oldname, int,
217COMPAT_SYSCALL_WRAP3(seccomp, unsigned int, op, unsigned int, flags, const char __user *, uargs) 217COMPAT_SYSCALL_WRAP3(seccomp, unsigned int, op, unsigned int, flags, const char __user *, uargs)
218COMPAT_SYSCALL_WRAP3(getrandom, char __user *, buf, size_t, count, unsigned int, flags) 218COMPAT_SYSCALL_WRAP3(getrandom, char __user *, buf, size_t, count, unsigned int, flags)
219COMPAT_SYSCALL_WRAP2(memfd_create, const char __user *, uname, unsigned int, flags) 219COMPAT_SYSCALL_WRAP2(memfd_create, const char __user *, uname, unsigned int, flags)
220COMPAT_SYSCALL_WRAP3(bpf, int, cmd, union bpf_attr *, attr, unsigned int, size);
diff --git a/arch/s390/kernel/perf_cpum_sf.c b/arch/s390/kernel/perf_cpum_sf.c
index 08e761318c17..b878f12a9597 100644
--- a/arch/s390/kernel/perf_cpum_sf.c
+++ b/arch/s390/kernel/perf_cpum_sf.c
@@ -1411,11 +1411,6 @@ static void cpumsf_pmu_del(struct perf_event *event, int flags)
1411 perf_pmu_enable(event->pmu); 1411 perf_pmu_enable(event->pmu);
1412} 1412}
1413 1413
1414static int cpumsf_pmu_event_idx(struct perf_event *event)
1415{
1416 return event->hw.idx;
1417}
1418
1419CPUMF_EVENT_ATTR(SF, SF_CYCLES_BASIC, PERF_EVENT_CPUM_SF); 1414CPUMF_EVENT_ATTR(SF, SF_CYCLES_BASIC, PERF_EVENT_CPUM_SF);
1420CPUMF_EVENT_ATTR(SF, SF_CYCLES_BASIC_DIAG, PERF_EVENT_CPUM_SF_DIAG); 1415CPUMF_EVENT_ATTR(SF, SF_CYCLES_BASIC_DIAG, PERF_EVENT_CPUM_SF_DIAG);
1421 1416
@@ -1458,7 +1453,6 @@ static struct pmu cpumf_sampling = {
1458 .stop = cpumsf_pmu_stop, 1453 .stop = cpumsf_pmu_stop,
1459 .read = cpumsf_pmu_read, 1454 .read = cpumsf_pmu_read,
1460 1455
1461 .event_idx = cpumsf_pmu_event_idx,
1462 .attr_groups = cpumsf_pmu_attr_groups, 1456 .attr_groups = cpumsf_pmu_attr_groups,
1463}; 1457};
1464 1458
diff --git a/arch/s390/kernel/syscalls.S b/arch/s390/kernel/syscalls.S
index 6fe886ac2db5..9f7087fd58de 100644
--- a/arch/s390/kernel/syscalls.S
+++ b/arch/s390/kernel/syscalls.S
@@ -359,3 +359,4 @@ SYSCALL(sys_renameat2,sys_renameat2,compat_sys_renameat2)
359SYSCALL(sys_seccomp,sys_seccomp,compat_sys_seccomp) 359SYSCALL(sys_seccomp,sys_seccomp,compat_sys_seccomp)
360SYSCALL(sys_getrandom,sys_getrandom,compat_sys_getrandom) 360SYSCALL(sys_getrandom,sys_getrandom,compat_sys_getrandom)
361SYSCALL(sys_memfd_create,sys_memfd_create,compat_sys_memfd_create) /* 350 */ 361SYSCALL(sys_memfd_create,sys_memfd_create,compat_sys_memfd_create) /* 350 */
362SYSCALL(sys_bpf,sys_bpf,compat_sys_bpf)
diff --git a/arch/s390/kernel/uprobes.c b/arch/s390/kernel/uprobes.c
index 956f4f7a591c..f6b3cd056ec2 100644
--- a/arch/s390/kernel/uprobes.c
+++ b/arch/s390/kernel/uprobes.c
@@ -5,13 +5,13 @@
5 * Author(s): Jan Willeke, 5 * Author(s): Jan Willeke,
6 */ 6 */
7 7
8#include <linux/kprobes.h>
9#include <linux/uaccess.h> 8#include <linux/uaccess.h>
10#include <linux/uprobes.h> 9#include <linux/uprobes.h>
11#include <linux/compat.h> 10#include <linux/compat.h>
12#include <linux/kdebug.h> 11#include <linux/kdebug.h>
13#include <asm/switch_to.h> 12#include <asm/switch_to.h>
14#include <asm/facility.h> 13#include <asm/facility.h>
14#include <asm/kprobes.h>
15#include <asm/dis.h> 15#include <asm/dis.h>
16#include "entry.h" 16#include "entry.h"
17 17
diff --git a/arch/s390/lib/probes.c b/arch/s390/lib/probes.c
index c5d64a099719..ae90e1ae3607 100644
--- a/arch/s390/lib/probes.c
+++ b/arch/s390/lib/probes.c
@@ -4,7 +4,7 @@
4 * Copyright IBM Corp. 2014 4 * Copyright IBM Corp. 2014
5 */ 5 */
6 6
7#include <linux/kprobes.h> 7#include <asm/kprobes.h>
8#include <asm/dis.h> 8#include <asm/dis.h>
9 9
10int probe_is_prohibited_opcode(u16 *insn) 10int probe_is_prohibited_opcode(u16 *insn)
diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c
index 296b61a4af59..1b79ca67392f 100644
--- a/arch/s390/mm/pgtable.c
+++ b/arch/s390/mm/pgtable.c
@@ -656,7 +656,7 @@ void __gmap_zap(struct gmap *gmap, unsigned long gaddr)
656 } 656 }
657 pgste_set_unlock(ptep, pgste); 657 pgste_set_unlock(ptep, pgste);
658out_pte: 658out_pte:
659 pte_unmap_unlock(*ptep, ptl); 659 pte_unmap_unlock(ptep, ptl);
660} 660}
661EXPORT_SYMBOL_GPL(__gmap_zap); 661EXPORT_SYMBOL_GPL(__gmap_zap);
662 662
@@ -943,7 +943,7 @@ retry:
943 } 943 }
944 if (!(pte_val(*ptep) & _PAGE_INVALID) && 944 if (!(pte_val(*ptep) & _PAGE_INVALID) &&
945 (pte_val(*ptep) & _PAGE_PROTECT)) { 945 (pte_val(*ptep) & _PAGE_PROTECT)) {
946 pte_unmap_unlock(*ptep, ptl); 946 pte_unmap_unlock(ptep, ptl);
947 if (fixup_user_fault(current, mm, addr, FAULT_FLAG_WRITE)) { 947 if (fixup_user_fault(current, mm, addr, FAULT_FLAG_WRITE)) {
948 up_read(&mm->mmap_sem); 948 up_read(&mm->mmap_sem);
949 return -EFAULT; 949 return -EFAULT;
@@ -974,7 +974,7 @@ retry:
974 pgste_val(new) |= PGSTE_UC_BIT; 974 pgste_val(new) |= PGSTE_UC_BIT;
975 975
976 pgste_set_unlock(ptep, new); 976 pgste_set_unlock(ptep, new);
977 pte_unmap_unlock(*ptep, ptl); 977 pte_unmap_unlock(ptep, ptl);
978 up_read(&mm->mmap_sem); 978 up_read(&mm->mmap_sem);
979 return 0; 979 return 0;
980} 980}
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index 9139d14b9c53..538c10db3537 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -118,7 +118,7 @@ static struct plat_sci_port scif0_platform_data = {
118}; 118};
119 119
120static struct resource scif0_resources[] = { 120static struct resource scif0_resources[] = {
121 DEFINE_RES_MEM(0xfffffe80, 0x100), 121 DEFINE_RES_MEM(0xfffffe80, 0x10),
122 DEFINE_RES_IRQ(evt2irq(0x4e0)), 122 DEFINE_RES_IRQ(evt2irq(0x4e0)),
123}; 123};
124 124
@@ -143,7 +143,7 @@ static struct plat_sci_port scif1_platform_data = {
143}; 143};
144 144
145static struct resource scif1_resources[] = { 145static struct resource scif1_resources[] = {
146 DEFINE_RES_MEM(0xa4000150, 0x100), 146 DEFINE_RES_MEM(0xa4000150, 0x10),
147 DEFINE_RES_IRQ(evt2irq(0x900)), 147 DEFINE_RES_IRQ(evt2irq(0x900)),
148}; 148};
149 149
@@ -169,7 +169,7 @@ static struct plat_sci_port scif2_platform_data = {
169}; 169};
170 170
171static struct resource scif2_resources[] = { 171static struct resource scif2_resources[] = {
172 DEFINE_RES_MEM(0xa4000140, 0x100), 172 DEFINE_RES_MEM(0xa4000140, 0x10),
173 DEFINE_RES_IRQ(evt2irq(0x880)), 173 DEFINE_RES_IRQ(evt2irq(0x880)),
174}; 174};
175 175
diff --git a/arch/sparc/include/asm/oplib_64.h b/arch/sparc/include/asm/oplib_64.h
index f34682430fcf..2e3a4add8591 100644
--- a/arch/sparc/include/asm/oplib_64.h
+++ b/arch/sparc/include/asm/oplib_64.h
@@ -62,7 +62,8 @@ struct linux_mem_p1275 {
62/* You must call prom_init() before using any of the library services, 62/* You must call prom_init() before using any of the library services,
63 * preferably as early as possible. Pass it the romvec pointer. 63 * preferably as early as possible. Pass it the romvec pointer.
64 */ 64 */
65void prom_init(void *cif_handler, void *cif_stack); 65void prom_init(void *cif_handler);
66void prom_init_report(void);
66 67
67/* Boot argument acquisition, returns the boot command line string. */ 68/* Boot argument acquisition, returns the boot command line string. */
68char *prom_getbootargs(void); 69char *prom_getbootargs(void);
diff --git a/arch/sparc/include/asm/setup.h b/arch/sparc/include/asm/setup.h
index f5fffd84d0dd..29d64b1758ed 100644
--- a/arch/sparc/include/asm/setup.h
+++ b/arch/sparc/include/asm/setup.h
@@ -48,6 +48,8 @@ unsigned long safe_compute_effective_address(struct pt_regs *, unsigned int);
48#endif 48#endif
49 49
50#ifdef CONFIG_SPARC64 50#ifdef CONFIG_SPARC64
51void __init start_early_boot(void);
52
51/* unaligned_64.c */ 53/* unaligned_64.c */
52int handle_ldf_stq(u32 insn, struct pt_regs *regs); 54int handle_ldf_stq(u32 insn, struct pt_regs *regs);
53void handle_ld_nf(u32 insn, struct pt_regs *regs); 55void handle_ld_nf(u32 insn, struct pt_regs *regs);
diff --git a/arch/sparc/include/uapi/asm/unistd.h b/arch/sparc/include/uapi/asm/unistd.h
index c842a89b1190..46d83842eddc 100644
--- a/arch/sparc/include/uapi/asm/unistd.h
+++ b/arch/sparc/include/uapi/asm/unistd.h
@@ -414,8 +414,9 @@
414#define __NR_seccomp 346 414#define __NR_seccomp 346
415#define __NR_getrandom 347 415#define __NR_getrandom 347
416#define __NR_memfd_create 348 416#define __NR_memfd_create 348
417#define __NR_bpf 349
417 418
418#define NR_syscalls 349 419#define NR_syscalls 350
419 420
420/* Bitmask values returned from kern_features system call. */ 421/* Bitmask values returned from kern_features system call. */
421#define KERN_FEATURE_MIXED_MODE_STACK 0x00000001 422#define KERN_FEATURE_MIXED_MODE_STACK 0x00000001
diff --git a/arch/sparc/kernel/entry.h b/arch/sparc/kernel/entry.h
index ebaba6167dd4..88d322b67fac 100644
--- a/arch/sparc/kernel/entry.h
+++ b/arch/sparc/kernel/entry.h
@@ -65,13 +65,10 @@ struct pause_patch_entry {
65extern struct pause_patch_entry __pause_3insn_patch, 65extern struct pause_patch_entry __pause_3insn_patch,
66 __pause_3insn_patch_end; 66 __pause_3insn_patch_end;
67 67
68void __init per_cpu_patch(void);
69void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *, 68void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *,
70 struct sun4v_1insn_patch_entry *); 69 struct sun4v_1insn_patch_entry *);
71void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *, 70void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *,
72 struct sun4v_2insn_patch_entry *); 71 struct sun4v_2insn_patch_entry *);
73void __init sun4v_patch(void);
74void __init boot_cpu_id_too_large(int cpu);
75extern unsigned int dcache_parity_tl1_occurred; 72extern unsigned int dcache_parity_tl1_occurred;
76extern unsigned int icache_parity_tl1_occurred; 73extern unsigned int icache_parity_tl1_occurred;
77 74
diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S
index 4fdeb8040d4d..3d61fcae7ee3 100644
--- a/arch/sparc/kernel/head_64.S
+++ b/arch/sparc/kernel/head_64.S
@@ -672,14 +672,12 @@ tlb_fixup_done:
672 sethi %hi(init_thread_union), %g6 672 sethi %hi(init_thread_union), %g6
673 or %g6, %lo(init_thread_union), %g6 673 or %g6, %lo(init_thread_union), %g6
674 ldx [%g6 + TI_TASK], %g4 674 ldx [%g6 + TI_TASK], %g4
675 mov %sp, %l6
676 675
677 wr %g0, ASI_P, %asi 676 wr %g0, ASI_P, %asi
678 mov 1, %g1 677 mov 1, %g1
679 sllx %g1, THREAD_SHIFT, %g1 678 sllx %g1, THREAD_SHIFT, %g1
680 sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1 679 sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
681 add %g6, %g1, %sp 680 add %g6, %g1, %sp
682 mov 0, %fp
683 681
684 /* Set per-cpu pointer initially to zero, this makes 682 /* Set per-cpu pointer initially to zero, this makes
685 * the boot-cpu use the in-kernel-image per-cpu areas 683 * the boot-cpu use the in-kernel-image per-cpu areas
@@ -706,44 +704,14 @@ tlb_fixup_done:
706 nop 704 nop
707#endif 705#endif
708 706
709 mov %l6, %o1 ! OpenPROM stack
710 call prom_init 707 call prom_init
711 mov %l7, %o0 ! OpenPROM cif handler 708 mov %l7, %o0 ! OpenPROM cif handler
712 709
713 /* Initialize current_thread_info()->cpu as early as possible. 710 /* To create a one-register-window buffer between the kernel's
714 * In order to do that accurately we have to patch up the get_cpuid() 711 * initial stack and the last stack frame we use from the firmware,
715 * assembler sequences. And that, in turn, requires that we know 712 * do the rest of the boot from a C helper function.
716 * if we are on a Starfire box or not. While we're here, patch up
717 * the sun4v sequences as well.
718 */ 713 */
719 call check_if_starfire 714 call start_early_boot
720 nop
721 call per_cpu_patch
722 nop
723 call sun4v_patch
724 nop
725
726#ifdef CONFIG_SMP
727 call hard_smp_processor_id
728 nop
729 cmp %o0, NR_CPUS
730 blu,pt %xcc, 1f
731 nop
732 call boot_cpu_id_too_large
733 nop
734 /* Not reached... */
735
7361:
737#else
738 mov 0, %o0
739#endif
740 sth %o0, [%g6 + TI_CPU]
741
742 call prom_init_report
743 nop
744
745 /* Off we go.... */
746 call start_kernel
747 nop 715 nop
748 /* Not reached... */ 716 /* Not reached... */
749 717
diff --git a/arch/sparc/kernel/hvtramp.S b/arch/sparc/kernel/hvtramp.S
index b7ddcdd1dea9..cdbfec299f2f 100644
--- a/arch/sparc/kernel/hvtramp.S
+++ b/arch/sparc/kernel/hvtramp.S
@@ -109,7 +109,6 @@ hv_cpu_startup:
109 sllx %g5, THREAD_SHIFT, %g5 109 sllx %g5, THREAD_SHIFT, %g5
110 sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5 110 sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
111 add %g6, %g5, %sp 111 add %g6, %g5, %sp
112 mov 0, %fp
113 112
114 call init_irqwork_curcpu 113 call init_irqwork_curcpu
115 nop 114 nop
diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c
index e629b8377587..c38d19fc27ba 100644
--- a/arch/sparc/kernel/setup_64.c
+++ b/arch/sparc/kernel/setup_64.c
@@ -30,6 +30,7 @@
30#include <linux/cpu.h> 30#include <linux/cpu.h>
31#include <linux/initrd.h> 31#include <linux/initrd.h>
32#include <linux/module.h> 32#include <linux/module.h>
33#include <linux/start_kernel.h>
33 34
34#include <asm/io.h> 35#include <asm/io.h>
35#include <asm/processor.h> 36#include <asm/processor.h>
@@ -162,7 +163,7 @@ char reboot_command[COMMAND_LINE_SIZE];
162 163
163static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 }; 164static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };
164 165
165void __init per_cpu_patch(void) 166static void __init per_cpu_patch(void)
166{ 167{
167 struct cpuid_patch_entry *p; 168 struct cpuid_patch_entry *p;
168 unsigned long ver; 169 unsigned long ver;
@@ -254,7 +255,7 @@ void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
254 } 255 }
255} 256}
256 257
257void __init sun4v_patch(void) 258static void __init sun4v_patch(void)
258{ 259{
259 extern void sun4v_hvapi_init(void); 260 extern void sun4v_hvapi_init(void);
260 261
@@ -323,14 +324,25 @@ static void __init pause_patch(void)
323 } 324 }
324} 325}
325 326
326#ifdef CONFIG_SMP 327void __init start_early_boot(void)
327void __init boot_cpu_id_too_large(int cpu)
328{ 328{
329 prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n", 329 int cpu;
330 cpu, NR_CPUS); 330
331 prom_halt(); 331 check_if_starfire();
332 per_cpu_patch();
333 sun4v_patch();
334
335 cpu = hard_smp_processor_id();
336 if (cpu >= NR_CPUS) {
337 prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
338 cpu, NR_CPUS);
339 prom_halt();
340 }
341 current_thread_info()->cpu = cpu;
342
343 prom_init_report();
344 start_kernel();
332} 345}
333#endif
334 346
335/* On Ultra, we support all of the v8 capabilities. */ 347/* On Ultra, we support all of the v8 capabilities. */
336unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | 348unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
diff --git a/arch/sparc/kernel/systbls_32.S b/arch/sparc/kernel/systbls_32.S
index 6a873c344bc0..ad0cdf497b78 100644
--- a/arch/sparc/kernel/systbls_32.S
+++ b/arch/sparc/kernel/systbls_32.S
@@ -86,4 +86,4 @@ sys_call_table:
86/*330*/ .long sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime 86/*330*/ .long sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime
87/*335*/ .long sys_syncfs, sys_sendmmsg, sys_setns, sys_process_vm_readv, sys_process_vm_writev 87/*335*/ .long sys_syncfs, sys_sendmmsg, sys_setns, sys_process_vm_readv, sys_process_vm_writev
88/*340*/ .long sys_ni_syscall, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr 88/*340*/ .long sys_ni_syscall, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr
89/*345*/ .long sys_renameat2, sys_seccomp, sys_getrandom, sys_memfd_create 89/*345*/ .long sys_renameat2, sys_seccomp, sys_getrandom, sys_memfd_create, sys_bpf
diff --git a/arch/sparc/kernel/systbls_64.S b/arch/sparc/kernel/systbls_64.S
index d9151b6490d8..580cde9370c9 100644
--- a/arch/sparc/kernel/systbls_64.S
+++ b/arch/sparc/kernel/systbls_64.S
@@ -87,7 +87,7 @@ sys_call_table32:
87/*330*/ .word compat_sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, compat_sys_open_by_handle_at, compat_sys_clock_adjtime 87/*330*/ .word compat_sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, compat_sys_open_by_handle_at, compat_sys_clock_adjtime
88 .word sys_syncfs, compat_sys_sendmmsg, sys_setns, compat_sys_process_vm_readv, compat_sys_process_vm_writev 88 .word sys_syncfs, compat_sys_sendmmsg, sys_setns, compat_sys_process_vm_readv, compat_sys_process_vm_writev
89/*340*/ .word sys_kern_features, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr 89/*340*/ .word sys_kern_features, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr
90 .word sys32_renameat2, sys_seccomp, sys_getrandom, sys_memfd_create 90 .word sys32_renameat2, sys_seccomp, sys_getrandom, sys_memfd_create, sys_bpf
91 91
92#endif /* CONFIG_COMPAT */ 92#endif /* CONFIG_COMPAT */
93 93
@@ -166,4 +166,4 @@ sys_call_table:
166/*330*/ .word sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime 166/*330*/ .word sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime
167 .word sys_syncfs, sys_sendmmsg, sys_setns, sys_process_vm_readv, sys_process_vm_writev 167 .word sys_syncfs, sys_sendmmsg, sys_setns, sys_process_vm_readv, sys_process_vm_writev
168/*340*/ .word sys_kern_features, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr 168/*340*/ .word sys_kern_features, sys_kcmp, sys_finit_module, sys_sched_setattr, sys_sched_getattr
169 .word sys_renameat2, sys_seccomp, sys_getrandom, sys_memfd_create 169 .word sys_renameat2, sys_seccomp, sys_getrandom, sys_memfd_create, sys_bpf
diff --git a/arch/sparc/kernel/trampoline_64.S b/arch/sparc/kernel/trampoline_64.S
index 737f8cbc7d56..88ede1d53b4c 100644
--- a/arch/sparc/kernel/trampoline_64.S
+++ b/arch/sparc/kernel/trampoline_64.S
@@ -109,10 +109,13 @@ startup_continue:
109 brnz,pn %g1, 1b 109 brnz,pn %g1, 1b
110 nop 110 nop
111 111
112 sethi %hi(p1275buf), %g2 112 /* Get onto temporary stack which will be in the locked
113 or %g2, %lo(p1275buf), %g2 113 * kernel image.
114 ldx [%g2 + 0x10], %l2 114 */
115 add %l2, -(192 + 128), %sp 115 sethi %hi(tramp_stack), %g1
116 or %g1, %lo(tramp_stack), %g1
117 add %g1, TRAMP_STACK_SIZE, %g1
118 sub %g1, STACKFRAME_SZ + STACK_BIAS + 256, %sp
116 flushw 119 flushw
117 120
118 /* Setup the loop variables: 121 /* Setup the loop variables:
@@ -394,7 +397,6 @@ after_lock_tlb:
394 sllx %g5, THREAD_SHIFT, %g5 397 sllx %g5, THREAD_SHIFT, %g5
395 sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5 398 sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
396 add %g6, %g5, %sp 399 add %g6, %g5, %sp
397 mov 0, %fp
398 400
399 rdpr %pstate, %o1 401 rdpr %pstate, %o1
400 or %o1, PSTATE_IE, %o1 402 or %o1, PSTATE_IE, %o1
diff --git a/arch/sparc/mm/gup.c b/arch/sparc/mm/gup.c
index 1aed0432c64b..ae6ce383d4df 100644
--- a/arch/sparc/mm/gup.c
+++ b/arch/sparc/mm/gup.c
@@ -160,6 +160,36 @@ static int gup_pud_range(pgd_t pgd, unsigned long addr, unsigned long end,
160 return 1; 160 return 1;
161} 161}
162 162
163int __get_user_pages_fast(unsigned long start, int nr_pages, int write,
164 struct page **pages)
165{
166 struct mm_struct *mm = current->mm;
167 unsigned long addr, len, end;
168 unsigned long next, flags;
169 pgd_t *pgdp;
170 int nr = 0;
171
172 start &= PAGE_MASK;
173 addr = start;
174 len = (unsigned long) nr_pages << PAGE_SHIFT;
175 end = start + len;
176
177 local_irq_save(flags);
178 pgdp = pgd_offset(mm, addr);
179 do {
180 pgd_t pgd = *pgdp;
181
182 next = pgd_addr_end(addr, end);
183 if (pgd_none(pgd))
184 break;
185 if (!gup_pud_range(pgd, addr, next, write, pages, &nr))
186 break;
187 } while (pgdp++, addr = next, addr != end);
188 local_irq_restore(flags);
189
190 return nr;
191}
192
163int get_user_pages_fast(unsigned long start, int nr_pages, int write, 193int get_user_pages_fast(unsigned long start, int nr_pages, int write,
164 struct page **pages) 194 struct page **pages)
165{ 195{
diff --git a/arch/sparc/prom/cif.S b/arch/sparc/prom/cif.S
index 9c86b4b7d429..8050f381f518 100644
--- a/arch/sparc/prom/cif.S
+++ b/arch/sparc/prom/cif.S
@@ -11,11 +11,10 @@
11 .text 11 .text
12 .globl prom_cif_direct 12 .globl prom_cif_direct
13prom_cif_direct: 13prom_cif_direct:
14 save %sp, -192, %sp
14 sethi %hi(p1275buf), %o1 15 sethi %hi(p1275buf), %o1
15 or %o1, %lo(p1275buf), %o1 16 or %o1, %lo(p1275buf), %o1
16 ldx [%o1 + 0x0010], %o2 ! prom_cif_stack 17 ldx [%o1 + 0x0008], %l2 ! prom_cif_handler
17 save %o2, -192, %sp
18 ldx [%i1 + 0x0008], %l2 ! prom_cif_handler
19 mov %g4, %l0 18 mov %g4, %l0
20 mov %g5, %l1 19 mov %g5, %l1
21 mov %g6, %l3 20 mov %g6, %l3
diff --git a/arch/sparc/prom/init_64.c b/arch/sparc/prom/init_64.c
index d95db755828f..110b0d78b864 100644
--- a/arch/sparc/prom/init_64.c
+++ b/arch/sparc/prom/init_64.c
@@ -26,13 +26,13 @@ phandle prom_chosen_node;
26 * It gets passed the pointer to the PROM vector. 26 * It gets passed the pointer to the PROM vector.
27 */ 27 */
28 28
29extern void prom_cif_init(void *, void *); 29extern void prom_cif_init(void *);
30 30
31void __init prom_init(void *cif_handler, void *cif_stack) 31void __init prom_init(void *cif_handler)
32{ 32{
33 phandle node; 33 phandle node;
34 34
35 prom_cif_init(cif_handler, cif_stack); 35 prom_cif_init(cif_handler);
36 36
37 prom_chosen_node = prom_finddevice(prom_chosen_path); 37 prom_chosen_node = prom_finddevice(prom_chosen_path);
38 if (!prom_chosen_node || (s32)prom_chosen_node == -1) 38 if (!prom_chosen_node || (s32)prom_chosen_node == -1)
diff --git a/arch/sparc/prom/p1275.c b/arch/sparc/prom/p1275.c
index b2340f008ae0..545d8bb79b65 100644
--- a/arch/sparc/prom/p1275.c
+++ b/arch/sparc/prom/p1275.c
@@ -20,7 +20,6 @@
20struct { 20struct {
21 long prom_callback; /* 0x00 */ 21 long prom_callback; /* 0x00 */
22 void (*prom_cif_handler)(long *); /* 0x08 */ 22 void (*prom_cif_handler)(long *); /* 0x08 */
23 unsigned long prom_cif_stack; /* 0x10 */
24} p1275buf; 23} p1275buf;
25 24
26extern void prom_world(int); 25extern void prom_world(int);
@@ -52,5 +51,4 @@ void p1275_cmd_direct(unsigned long *args)
52void prom_cif_init(void *cif_handler, void *cif_stack) 51void prom_cif_init(void *cif_handler, void *cif_stack)
53{ 52{
54 p1275buf.prom_cif_handler = (void (*)(long *))cif_handler; 53 p1275buf.prom_cif_handler = (void (*)(long *))cif_handler;
55 p1275buf.prom_cif_stack = (unsigned long)cif_stack;
56} 54}
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index f2327e88e07c..ded8a6774ac9 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -142,6 +142,10 @@ config INSTRUCTION_DECODER
142 def_bool y 142 def_bool y
143 depends on KPROBES || PERF_EVENTS || UPROBES 143 depends on KPROBES || PERF_EVENTS || UPROBES
144 144
145config PERF_EVENTS_INTEL_UNCORE
146 def_bool y
147 depends on PERF_EVENTS && SUP_SUP_INTEL && PCI
148
145config OUTPUT_FORMAT 149config OUTPUT_FORMAT
146 string 150 string
147 default "elf32-i386" if X86_32 151 default "elf32-i386" if X86_32
diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c
index de8eebd6f67c..1acf605a646d 100644
--- a/arch/x86/boot/compressed/eboot.c
+++ b/arch/x86/boot/compressed/eboot.c
@@ -330,8 +330,10 @@ __setup_efi_pci32(efi_pci_io_protocol_32 *pci, struct pci_setup_rom **__rom)
330 size = pci->romsize + sizeof(*rom); 330 size = pci->romsize + sizeof(*rom);
331 331
332 status = efi_call_early(allocate_pool, EFI_LOADER_DATA, size, &rom); 332 status = efi_call_early(allocate_pool, EFI_LOADER_DATA, size, &rom);
333 if (status != EFI_SUCCESS) 333 if (status != EFI_SUCCESS) {
334 efi_printk(sys_table, "Failed to alloc mem for rom\n");
334 return status; 335 return status;
336 }
335 337
336 memset(rom, 0, sizeof(*rom)); 338 memset(rom, 0, sizeof(*rom));
337 339
@@ -344,14 +346,18 @@ __setup_efi_pci32(efi_pci_io_protocol_32 *pci, struct pci_setup_rom **__rom)
344 status = efi_early->call(pci->pci.read, pci, EfiPciIoWidthUint16, 346 status = efi_early->call(pci->pci.read, pci, EfiPciIoWidthUint16,
345 PCI_VENDOR_ID, 1, &(rom->vendor)); 347 PCI_VENDOR_ID, 1, &(rom->vendor));
346 348
347 if (status != EFI_SUCCESS) 349 if (status != EFI_SUCCESS) {
350 efi_printk(sys_table, "Failed to read rom->vendor\n");
348 goto free_struct; 351 goto free_struct;
352 }
349 353
350 status = efi_early->call(pci->pci.read, pci, EfiPciIoWidthUint16, 354 status = efi_early->call(pci->pci.read, pci, EfiPciIoWidthUint16,
351 PCI_DEVICE_ID, 1, &(rom->devid)); 355 PCI_DEVICE_ID, 1, &(rom->devid));
352 356
353 if (status != EFI_SUCCESS) 357 if (status != EFI_SUCCESS) {
358 efi_printk(sys_table, "Failed to read rom->devid\n");
354 goto free_struct; 359 goto free_struct;
360 }
355 361
356 status = efi_early->call(pci->get_location, pci, &(rom->segment), 362 status = efi_early->call(pci->get_location, pci, &(rom->segment),
357 &(rom->bus), &(rom->device), &(rom->function)); 363 &(rom->bus), &(rom->device), &(rom->function));
@@ -432,8 +438,10 @@ __setup_efi_pci64(efi_pci_io_protocol_64 *pci, struct pci_setup_rom **__rom)
432 size = pci->romsize + sizeof(*rom); 438 size = pci->romsize + sizeof(*rom);
433 439
434 status = efi_call_early(allocate_pool, EFI_LOADER_DATA, size, &rom); 440 status = efi_call_early(allocate_pool, EFI_LOADER_DATA, size, &rom);
435 if (status != EFI_SUCCESS) 441 if (status != EFI_SUCCESS) {
442 efi_printk(sys_table, "Failed to alloc mem for rom\n");
436 return status; 443 return status;
444 }
437 445
438 rom->data.type = SETUP_PCI; 446 rom->data.type = SETUP_PCI;
439 rom->data.len = size - sizeof(struct setup_data); 447 rom->data.len = size - sizeof(struct setup_data);
@@ -444,14 +452,18 @@ __setup_efi_pci64(efi_pci_io_protocol_64 *pci, struct pci_setup_rom **__rom)
444 status = efi_early->call(pci->pci.read, pci, EfiPciIoWidthUint16, 452 status = efi_early->call(pci->pci.read, pci, EfiPciIoWidthUint16,
445 PCI_VENDOR_ID, 1, &(rom->vendor)); 453 PCI_VENDOR_ID, 1, &(rom->vendor));
446 454
447 if (status != EFI_SUCCESS) 455 if (status != EFI_SUCCESS) {
456 efi_printk(sys_table, "Failed to read rom->vendor\n");
448 goto free_struct; 457 goto free_struct;
458 }
449 459
450 status = efi_early->call(pci->pci.read, pci, EfiPciIoWidthUint16, 460 status = efi_early->call(pci->pci.read, pci, EfiPciIoWidthUint16,
451 PCI_DEVICE_ID, 1, &(rom->devid)); 461 PCI_DEVICE_ID, 1, &(rom->devid));
452 462
453 if (status != EFI_SUCCESS) 463 if (status != EFI_SUCCESS) {
464 efi_printk(sys_table, "Failed to read rom->devid\n");
454 goto free_struct; 465 goto free_struct;
466 }
455 467
456 status = efi_early->call(pci->get_location, pci, &(rom->segment), 468 status = efi_early->call(pci->get_location, pci, &(rom->segment),
457 &(rom->bus), &(rom->device), &(rom->function)); 469 &(rom->bus), &(rom->device), &(rom->function));
@@ -538,8 +550,10 @@ static void setup_efi_pci(struct boot_params *params)
538 EFI_LOADER_DATA, 550 EFI_LOADER_DATA,
539 size, (void **)&pci_handle); 551 size, (void **)&pci_handle);
540 552
541 if (status != EFI_SUCCESS) 553 if (status != EFI_SUCCESS) {
554 efi_printk(sys_table, "Failed to alloc mem for pci_handle\n");
542 return; 555 return;
556 }
543 557
544 status = efi_call_early(locate_handle, 558 status = efi_call_early(locate_handle,
545 EFI_LOCATE_BY_PROTOCOL, &pci_proto, 559 EFI_LOCATE_BY_PROTOCOL, &pci_proto,
@@ -1105,6 +1119,10 @@ struct boot_params *make_boot_params(struct efi_config *c)
1105 1119
1106 memset(sdt, 0, sizeof(*sdt)); 1120 memset(sdt, 0, sizeof(*sdt));
1107 1121
1122 status = efi_parse_options(cmdline_ptr);
1123 if (status != EFI_SUCCESS)
1124 goto fail2;
1125
1108 status = handle_cmdline_files(sys_table, image, 1126 status = handle_cmdline_files(sys_table, image,
1109 (char *)(unsigned long)hdr->cmd_line_ptr, 1127 (char *)(unsigned long)hdr->cmd_line_ptr,
1110 "initrd=", hdr->initrd_addr_max, 1128 "initrd=", hdr->initrd_addr_max,
diff --git a/arch/x86/ia32/ia32entry.S b/arch/x86/ia32/ia32entry.S
index 8ffba18395c8..ffe71228fc10 100644
--- a/arch/x86/ia32/ia32entry.S
+++ b/arch/x86/ia32/ia32entry.S
@@ -157,7 +157,7 @@ ENTRY(ia32_sysenter_target)
157 * ourselves. To save a few cycles, we can check whether 157 * ourselves. To save a few cycles, we can check whether
158 * NT was set instead of doing an unconditional popfq. 158 * NT was set instead of doing an unconditional popfq.
159 */ 159 */
160 testl $X86_EFLAGS_NT,EFLAGS(%rsp) /* saved EFLAGS match cpu */ 160 testl $X86_EFLAGS_NT,EFLAGS-ARGOFFSET(%rsp)
161 jnz sysenter_fix_flags 161 jnz sysenter_fix_flags
162sysenter_flags_fixed: 162sysenter_flags_fixed:
163 163
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
index 0ec241ede5a2..9b11757975d0 100644
--- a/arch/x86/include/asm/efi.h
+++ b/arch/x86/include/asm/efi.h
@@ -81,24 +81,23 @@ extern u64 asmlinkage efi_call(void *fp, ...);
81 */ 81 */
82#define __efi_call_virt(f, args...) efi_call_virt(f, args) 82#define __efi_call_virt(f, args...) efi_call_virt(f, args)
83 83
84extern void __iomem *efi_ioremap(unsigned long addr, unsigned long size, 84extern void __iomem *__init efi_ioremap(unsigned long addr, unsigned long size,
85 u32 type, u64 attribute); 85 u32 type, u64 attribute);
86 86
87#endif /* CONFIG_X86_32 */ 87#endif /* CONFIG_X86_32 */
88 88
89extern int add_efi_memmap;
90extern struct efi_scratch efi_scratch; 89extern struct efi_scratch efi_scratch;
91extern void efi_set_executable(efi_memory_desc_t *md, bool executable); 90extern void __init efi_set_executable(efi_memory_desc_t *md, bool executable);
92extern int efi_memblock_x86_reserve_range(void); 91extern int __init efi_memblock_x86_reserve_range(void);
93extern void efi_call_phys_prelog(void); 92extern void __init efi_call_phys_prolog(void);
94extern void efi_call_phys_epilog(void); 93extern void __init efi_call_phys_epilog(void);
95extern void efi_unmap_memmap(void); 94extern void __init efi_unmap_memmap(void);
96extern void efi_memory_uc(u64 addr, unsigned long size); 95extern void __init efi_memory_uc(u64 addr, unsigned long size);
97extern void __init efi_map_region(efi_memory_desc_t *md); 96extern void __init efi_map_region(efi_memory_desc_t *md);
98extern void __init efi_map_region_fixed(efi_memory_desc_t *md); 97extern void __init efi_map_region_fixed(efi_memory_desc_t *md);
99extern void efi_sync_low_kernel_mappings(void); 98extern void efi_sync_low_kernel_mappings(void);
100extern int efi_setup_page_tables(unsigned long pa_memmap, unsigned num_pages); 99extern int __init efi_setup_page_tables(unsigned long pa_memmap, unsigned num_pages);
101extern void efi_cleanup_page_tables(unsigned long pa_memmap, unsigned num_pages); 100extern void __init efi_cleanup_page_tables(unsigned long pa_memmap, unsigned num_pages);
102extern void __init old_map_region(efi_memory_desc_t *md); 101extern void __init old_map_region(efi_memory_desc_t *md);
103extern void __init runtime_code_page_mkexec(void); 102extern void __init runtime_code_page_mkexec(void);
104extern void __init efi_runtime_mkexec(void); 103extern void __init efi_runtime_mkexec(void);
@@ -162,16 +161,6 @@ static inline efi_status_t efi_thunk_set_virtual_address_map(
162extern bool efi_reboot_required(void); 161extern bool efi_reboot_required(void);
163 162
164#else 163#else
165/*
166 * IF EFI is not configured, have the EFI calls return -ENOSYS.
167 */
168#define efi_call0(_f) (-ENOSYS)
169#define efi_call1(_f, _a1) (-ENOSYS)
170#define efi_call2(_f, _a1, _a2) (-ENOSYS)
171#define efi_call3(_f, _a1, _a2, _a3) (-ENOSYS)
172#define efi_call4(_f, _a1, _a2, _a3, _a4) (-ENOSYS)
173#define efi_call5(_f, _a1, _a2, _a3, _a4, _a5) (-ENOSYS)
174#define efi_call6(_f, _a1, _a2, _a3, _a4, _a5, _a6) (-ENOSYS)
175static inline void parse_efi_setup(u64 phys_addr, u32 data_len) {} 164static inline void parse_efi_setup(u64 phys_addr, u32 data_len) {}
176static inline bool efi_reboot_required(void) 165static inline bool efi_reboot_required(void)
177{ 166{
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 7d603a71ab3a..6ed0c30d6a0c 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -989,6 +989,20 @@ static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code)
989 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 989 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
990} 990}
991 991
992static inline u64 get_canonical(u64 la)
993{
994 return ((int64_t)la << 16) >> 16;
995}
996
997static inline bool is_noncanonical_address(u64 la)
998{
999#ifdef CONFIG_X86_64
1000 return get_canonical(la) != la;
1001#else
1002 return false;
1003#endif
1004}
1005
992#define TSS_IOPB_BASE_OFFSET 0x66 1006#define TSS_IOPB_BASE_OFFSET 0x66
993#define TSS_BASE_SIZE 0x68 1007#define TSS_BASE_SIZE 0x68
994#define TSS_IOPB_SIZE (65536 / 8) 1008#define TSS_IOPB_SIZE (65536 / 8)
@@ -1050,7 +1064,7 @@ void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
1050 unsigned long address); 1064 unsigned long address);
1051 1065
1052void kvm_define_shared_msr(unsigned index, u32 msr); 1066void kvm_define_shared_msr(unsigned index, u32 msr);
1053void kvm_set_shared_msr(unsigned index, u64 val, u64 mask); 1067int kvm_set_shared_msr(unsigned index, u64 val, u64 mask);
1054 1068
1055bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); 1069bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip);
1056 1070
diff --git a/arch/x86/include/asm/preempt.h b/arch/x86/include/asm/preempt.h
index 7024c12f7bfe..400873450e33 100644
--- a/arch/x86/include/asm/preempt.h
+++ b/arch/x86/include/asm/preempt.h
@@ -105,6 +105,7 @@ static __always_inline bool should_resched(void)
105# ifdef CONFIG_CONTEXT_TRACKING 105# ifdef CONFIG_CONTEXT_TRACKING
106 extern asmlinkage void ___preempt_schedule_context(void); 106 extern asmlinkage void ___preempt_schedule_context(void);
107# define __preempt_schedule_context() asm ("call ___preempt_schedule_context") 107# define __preempt_schedule_context() asm ("call ___preempt_schedule_context")
108 extern asmlinkage void preempt_schedule_context(void);
108# endif 109# endif
109#endif 110#endif
110 111
diff --git a/arch/x86/include/uapi/asm/vmx.h b/arch/x86/include/uapi/asm/vmx.h
index 0e79420376eb..990a2fe1588d 100644
--- a/arch/x86/include/uapi/asm/vmx.h
+++ b/arch/x86/include/uapi/asm/vmx.h
@@ -67,6 +67,7 @@
67#define EXIT_REASON_EPT_MISCONFIG 49 67#define EXIT_REASON_EPT_MISCONFIG 49
68#define EXIT_REASON_INVEPT 50 68#define EXIT_REASON_INVEPT 50
69#define EXIT_REASON_PREEMPTION_TIMER 52 69#define EXIT_REASON_PREEMPTION_TIMER 52
70#define EXIT_REASON_INVVPID 53
70#define EXIT_REASON_WBINVD 54 71#define EXIT_REASON_WBINVD 54
71#define EXIT_REASON_XSETBV 55 72#define EXIT_REASON_XSETBV 55
72#define EXIT_REASON_APIC_WRITE 56 73#define EXIT_REASON_APIC_WRITE 56
@@ -114,6 +115,7 @@
114 { EXIT_REASON_EOI_INDUCED, "EOI_INDUCED" }, \ 115 { EXIT_REASON_EOI_INDUCED, "EOI_INDUCED" }, \
115 { EXIT_REASON_INVALID_STATE, "INVALID_STATE" }, \ 116 { EXIT_REASON_INVALID_STATE, "INVALID_STATE" }, \
116 { EXIT_REASON_INVD, "INVD" }, \ 117 { EXIT_REASON_INVD, "INVD" }, \
118 { EXIT_REASON_INVVPID, "INVVPID" }, \
117 { EXIT_REASON_INVPCID, "INVPCID" } 119 { EXIT_REASON_INVPCID, "INVPCID" }
118 120
119#endif /* _UAPIVMX_H */ 121#endif /* _UAPIVMX_H */
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index b436fc735aa4..a142e77693e1 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -397,7 +397,7 @@ static int mp_register_gsi(struct device *dev, u32 gsi, int trigger,
397 397
398 /* Don't set up the ACPI SCI because it's already set up */ 398 /* Don't set up the ACPI SCI because it's already set up */
399 if (acpi_gbl_FADT.sci_interrupt == gsi) 399 if (acpi_gbl_FADT.sci_interrupt == gsi)
400 return gsi; 400 return mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC);
401 401
402 trigger = trigger == ACPI_EDGE_SENSITIVE ? 0 : 1; 402 trigger = trigger == ACPI_EDGE_SENSITIVE ? 0 : 1;
403 polarity = polarity == ACPI_ACTIVE_HIGH ? 0 : 1; 403 polarity = polarity == ACPI_ACTIVE_HIGH ? 0 : 1;
@@ -604,14 +604,18 @@ void __init acpi_pic_sci_set_trigger(unsigned int irq, u16 trigger)
604 604
605int acpi_gsi_to_irq(u32 gsi, unsigned int *irqp) 605int acpi_gsi_to_irq(u32 gsi, unsigned int *irqp)
606{ 606{
607 int irq = mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC | IOAPIC_MAP_CHECK); 607 int irq;
608 608
609 if (irq >= 0) { 609 if (acpi_irq_model == ACPI_IRQ_MODEL_PIC) {
610 *irqp = gsi;
611 } else {
612 irq = mp_map_gsi_to_irq(gsi,
613 IOAPIC_MAP_ALLOC | IOAPIC_MAP_CHECK);
614 if (irq < 0)
615 return -1;
610 *irqp = irq; 616 *irqp = irq;
611 return 0;
612 } 617 }
613 618 return 0;
614 return -1;
615} 619}
616EXPORT_SYMBOL_GPL(acpi_gsi_to_irq); 620EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);
617 621
diff --git a/arch/x86/kernel/apb_timer.c b/arch/x86/kernel/apb_timer.c
index 5972b108f15a..b708738d016e 100644
--- a/arch/x86/kernel/apb_timer.c
+++ b/arch/x86/kernel/apb_timer.c
@@ -185,8 +185,6 @@ static void apbt_setup_irq(struct apbt_dev *adev)
185 185
186 irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT); 186 irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT);
187 irq_set_affinity(adev->irq, cpumask_of(adev->cpu)); 187 irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
188 /* APB timer irqs are set up as mp_irqs, timer is edge type */
189 __irq_set_handler(adev->irq, handle_edge_irq, 0, "edge");
190} 188}
191 189
192/* Should be called with per cpu */ 190/* Should be called with per cpu */
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 00853b254ab0..ba6cc041edb1 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1297,7 +1297,7 @@ void setup_local_APIC(void)
1297 unsigned int value, queued; 1297 unsigned int value, queued;
1298 int i, j, acked = 0; 1298 int i, j, acked = 0;
1299 unsigned long long tsc = 0, ntsc; 1299 unsigned long long tsc = 0, ntsc;
1300 long long max_loops = cpu_khz; 1300 long long max_loops = cpu_khz ? cpu_khz : 1000000;
1301 1301
1302 if (cpu_has_tsc) 1302 if (cpu_has_tsc)
1303 rdtscll(tsc); 1303 rdtscll(tsc);
@@ -1383,7 +1383,7 @@ void setup_local_APIC(void)
1383 break; 1383 break;
1384 } 1384 }
1385 if (queued) { 1385 if (queued) {
1386 if (cpu_has_tsc) { 1386 if (cpu_has_tsc && cpu_khz) {
1387 rdtscll(ntsc); 1387 rdtscll(ntsc);
1388 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1388 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1389 } else 1389 } else
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index 01d5453b5502..e27b49d7c922 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -39,9 +39,12 @@ obj-$(CONFIG_CPU_SUP_AMD) += perf_event_amd_iommu.o
39endif 39endif
40obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_p6.o perf_event_knc.o perf_event_p4.o 40obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_p6.o perf_event_knc.o perf_event_p4.o
41obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_lbr.o perf_event_intel_ds.o perf_event_intel.o 41obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_lbr.o perf_event_intel_ds.o perf_event_intel.o
42obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_uncore.o perf_event_intel_uncore_snb.o
43obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_uncore_snbep.o perf_event_intel_uncore_nhmex.o
44obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_rapl.o 42obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_rapl.o
43
44obj-$(CONFIG_PERF_EVENTS_INTEL_UNCORE) += perf_event_intel_uncore.o \
45 perf_event_intel_uncore_snb.o \
46 perf_event_intel_uncore_snbep.o \
47 perf_event_intel_uncore_nhmex.o
45endif 48endif
46 49
47 50
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 1ef456273172..9cc6b6f25f42 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -213,12 +213,13 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
213{ 213{
214#ifdef CONFIG_X86_F00F_BUG 214#ifdef CONFIG_X86_F00F_BUG
215 /* 215 /*
216 * All current models of Pentium and Pentium with MMX technology CPUs 216 * All models of Pentium and Pentium with MMX technology CPUs
217 * have the F0 0F bug, which lets nonprivileged users lock up the 217 * have the F0 0F bug, which lets nonprivileged users lock up the
218 * system. Announce that the fault handler will be checking for it. 218 * system. Announce that the fault handler will be checking for it.
219 * The Quark is also family 5, but does not have the same bug.
219 */ 220 */
220 clear_cpu_bug(c, X86_BUG_F00F); 221 clear_cpu_bug(c, X86_BUG_F00F);
221 if (!paravirt_enabled() && c->x86 == 5) { 222 if (!paravirt_enabled() && c->x86 == 5 && c->x86_model < 9) {
222 static int f00f_workaround_enabled; 223 static int f00f_workaround_enabled;
223 224
224 set_cpu_bug(c, X86_BUG_F00F); 225 set_cpu_bug(c, X86_BUG_F00F);
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 1b8299dd3d91..143e5f5dc855 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -243,8 +243,9 @@ static bool check_hw_exists(void)
243 243
244msr_fail: 244msr_fail:
245 printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); 245 printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
246 printk(boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR 246 printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
247 "Failed to access perfctr msr (MSR %x is %Lx)\n", reg, val_new); 247 boot_cpu_has(X86_FEATURE_HYPERVISOR) ? KERN_INFO : KERN_ERR,
248 reg, val_new);
248 249
249 return false; 250 return false;
250} 251}
@@ -444,12 +445,6 @@ int x86_pmu_hw_config(struct perf_event *event)
444 if (event->attr.type == PERF_TYPE_RAW) 445 if (event->attr.type == PERF_TYPE_RAW)
445 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; 446 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
446 447
447 if (event->attr.sample_period && x86_pmu.limit_period) {
448 if (x86_pmu.limit_period(event, event->attr.sample_period) >
449 event->attr.sample_period)
450 return -EINVAL;
451 }
452
453 return x86_setup_perfctr(event); 448 return x86_setup_perfctr(event);
454} 449}
455 450
@@ -987,9 +982,6 @@ int x86_perf_event_set_period(struct perf_event *event)
987 if (left > x86_pmu.max_period) 982 if (left > x86_pmu.max_period)
988 left = x86_pmu.max_period; 983 left = x86_pmu.max_period;
989 984
990 if (x86_pmu.limit_period)
991 left = x86_pmu.limit_period(event, left);
992
993 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; 985 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
994 986
995 /* 987 /*
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index d98a34d435d7..fc5eb390b368 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -445,7 +445,6 @@ struct x86_pmu {
445 struct x86_pmu_quirk *quirks; 445 struct x86_pmu_quirk *quirks;
446 int perfctr_second_write; 446 int perfctr_second_write;
447 bool late_ack; 447 bool late_ack;
448 unsigned (*limit_period)(struct perf_event *event, unsigned l);
449 448
450 /* 449 /*
451 * sysfs attrs 450 * sysfs attrs
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index a73947c53b65..944bf019b74f 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -220,15 +220,6 @@ static struct event_constraint intel_hsw_event_constraints[] = {
220 EVENT_CONSTRAINT_END 220 EVENT_CONSTRAINT_END
221}; 221};
222 222
223static struct event_constraint intel_bdw_event_constraints[] = {
224 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
225 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
226 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
227 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
228 INTEL_EVENT_CONSTRAINT(0xa3, 0x4), /* CYCLE_ACTIVITY.* */
229 EVENT_CONSTRAINT_END
230};
231
232static u64 intel_pmu_event_map(int hw_event) 223static u64 intel_pmu_event_map(int hw_event)
233{ 224{
234 return intel_perfmon_event_map[hw_event]; 225 return intel_perfmon_event_map[hw_event];
@@ -424,126 +415,6 @@ static __initconst const u64 snb_hw_cache_event_ids
424 415
425}; 416};
426 417
427static __initconst const u64 hsw_hw_cache_event_ids
428 [PERF_COUNT_HW_CACHE_MAX]
429 [PERF_COUNT_HW_CACHE_OP_MAX]
430 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
431{
432 [ C(L1D ) ] = {
433 [ C(OP_READ) ] = {
434 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
435 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
436 },
437 [ C(OP_WRITE) ] = {
438 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
439 [ C(RESULT_MISS) ] = 0x0,
440 },
441 [ C(OP_PREFETCH) ] = {
442 [ C(RESULT_ACCESS) ] = 0x0,
443 [ C(RESULT_MISS) ] = 0x0,
444 },
445 },
446 [ C(L1I ) ] = {
447 [ C(OP_READ) ] = {
448 [ C(RESULT_ACCESS) ] = 0x0,
449 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
450 },
451 [ C(OP_WRITE) ] = {
452 [ C(RESULT_ACCESS) ] = -1,
453 [ C(RESULT_MISS) ] = -1,
454 },
455 [ C(OP_PREFETCH) ] = {
456 [ C(RESULT_ACCESS) ] = 0x0,
457 [ C(RESULT_MISS) ] = 0x0,
458 },
459 },
460 [ C(LL ) ] = {
461 [ C(OP_READ) ] = {
462 /* OFFCORE_RESPONSE:ALL_DATA_RD|ALL_CODE_RD */
463 [ C(RESULT_ACCESS) ] = 0x1b7,
464 /* OFFCORE_RESPONSE:ALL_DATA_RD|ALL_CODE_RD|SUPPLIER_NONE|
465 L3_MISS|ANY_SNOOP */
466 [ C(RESULT_MISS) ] = 0x1b7,
467 },
468 [ C(OP_WRITE) ] = {
469 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE:ALL_RFO */
470 /* OFFCORE_RESPONSE:ALL_RFO|SUPPLIER_NONE|L3_MISS|ANY_SNOOP */
471 [ C(RESULT_MISS) ] = 0x1b7,
472 },
473 [ C(OP_PREFETCH) ] = {
474 [ C(RESULT_ACCESS) ] = 0x0,
475 [ C(RESULT_MISS) ] = 0x0,
476 },
477 },
478 [ C(DTLB) ] = {
479 [ C(OP_READ) ] = {
480 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
481 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
482 },
483 [ C(OP_WRITE) ] = {
484 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
485 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
486 },
487 [ C(OP_PREFETCH) ] = {
488 [ C(RESULT_ACCESS) ] = 0x0,
489 [ C(RESULT_MISS) ] = 0x0,
490 },
491 },
492 [ C(ITLB) ] = {
493 [ C(OP_READ) ] = {
494 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
495 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
496 },
497 [ C(OP_WRITE) ] = {
498 [ C(RESULT_ACCESS) ] = -1,
499 [ C(RESULT_MISS) ] = -1,
500 },
501 [ C(OP_PREFETCH) ] = {
502 [ C(RESULT_ACCESS) ] = -1,
503 [ C(RESULT_MISS) ] = -1,
504 },
505 },
506 [ C(BPU ) ] = {
507 [ C(OP_READ) ] = {
508 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
509 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
510 },
511 [ C(OP_WRITE) ] = {
512 [ C(RESULT_ACCESS) ] = -1,
513 [ C(RESULT_MISS) ] = -1,
514 },
515 [ C(OP_PREFETCH) ] = {
516 [ C(RESULT_ACCESS) ] = -1,
517 [ C(RESULT_MISS) ] = -1,
518 },
519 },
520};
521
522static __initconst const u64 hsw_hw_cache_extra_regs
523 [PERF_COUNT_HW_CACHE_MAX]
524 [PERF_COUNT_HW_CACHE_OP_MAX]
525 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
526{
527 [ C(LL ) ] = {
528 [ C(OP_READ) ] = {
529 /* OFFCORE_RESPONSE:ALL_DATA_RD|ALL_CODE_RD */
530 [ C(RESULT_ACCESS) ] = 0x2d5,
531 /* OFFCORE_RESPONSE:ALL_DATA_RD|ALL_CODE_RD|SUPPLIER_NONE|
532 L3_MISS|ANY_SNOOP */
533 [ C(RESULT_MISS) ] = 0x3fbc0202d5ull,
534 },
535 [ C(OP_WRITE) ] = {
536 [ C(RESULT_ACCESS) ] = 0x122, /* OFFCORE_RESPONSE:ALL_RFO */
537 /* OFFCORE_RESPONSE:ALL_RFO|SUPPLIER_NONE|L3_MISS|ANY_SNOOP */
538 [ C(RESULT_MISS) ] = 0x3fbc020122ull,
539 },
540 [ C(OP_PREFETCH) ] = {
541 [ C(RESULT_ACCESS) ] = 0x0,
542 [ C(RESULT_MISS) ] = 0x0,
543 },
544 },
545};
546
547static __initconst const u64 westmere_hw_cache_event_ids 418static __initconst const u64 westmere_hw_cache_event_ids
548 [PERF_COUNT_HW_CACHE_MAX] 419 [PERF_COUNT_HW_CACHE_MAX]
549 [PERF_COUNT_HW_CACHE_OP_MAX] 420 [PERF_COUNT_HW_CACHE_OP_MAX]
@@ -2034,24 +1905,6 @@ hsw_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
2034 return c; 1905 return c;
2035} 1906}
2036 1907
2037/*
2038 * Broadwell:
2039 * The INST_RETIRED.ALL period always needs to have lowest
2040 * 6bits cleared (BDM57). It shall not use a period smaller
2041 * than 100 (BDM11). We combine the two to enforce
2042 * a min-period of 128.
2043 */
2044static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
2045{
2046 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
2047 X86_CONFIG(.event=0xc0, .umask=0x01)) {
2048 if (left < 128)
2049 left = 128;
2050 left &= ~0x3fu;
2051 }
2052 return left;
2053}
2054
2055PMU_FORMAT_ATTR(event, "config:0-7" ); 1908PMU_FORMAT_ATTR(event, "config:0-7" );
2056PMU_FORMAT_ATTR(umask, "config:8-15" ); 1909PMU_FORMAT_ATTR(umask, "config:8-15" );
2057PMU_FORMAT_ATTR(edge, "config:18" ); 1910PMU_FORMAT_ATTR(edge, "config:18" );
@@ -2692,8 +2545,8 @@ __init int intel_pmu_init(void)
2692 case 69: /* 22nm Haswell ULT */ 2545 case 69: /* 22nm Haswell ULT */
2693 case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */ 2546 case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
2694 x86_pmu.late_ack = true; 2547 x86_pmu.late_ack = true;
2695 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 2548 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids));
2696 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); 2549 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
2697 2550
2698 intel_pmu_lbr_init_snb(); 2551 intel_pmu_lbr_init_snb();
2699 2552
@@ -2712,28 +2565,6 @@ __init int intel_pmu_init(void)
2712 pr_cont("Haswell events, "); 2565 pr_cont("Haswell events, ");
2713 break; 2566 break;
2714 2567
2715 case 61: /* 14nm Broadwell Core-M */
2716 x86_pmu.late_ack = true;
2717 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
2718 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
2719
2720 intel_pmu_lbr_init_snb();
2721
2722 x86_pmu.event_constraints = intel_bdw_event_constraints;
2723 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
2724 x86_pmu.extra_regs = intel_snbep_extra_regs;
2725 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2726 /* all extra regs are per-cpu when HT is on */
2727 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2728 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2729
2730 x86_pmu.hw_config = hsw_hw_config;
2731 x86_pmu.get_event_constraints = hsw_get_event_constraints;
2732 x86_pmu.cpu_events = hsw_events_attrs;
2733 x86_pmu.limit_period = bdw_limit_period;
2734 pr_cont("Broadwell events, ");
2735 break;
2736
2737 default: 2568 default:
2738 switch (x86_pmu.version) { 2569 switch (x86_pmu.version) {
2739 case 1: 2570 case 1:
diff --git a/arch/x86/kernel/entry_32.S b/arch/x86/kernel/entry_32.S
index b553ed89e5f5..344b63f18d14 100644
--- a/arch/x86/kernel/entry_32.S
+++ b/arch/x86/kernel/entry_32.S
@@ -447,15 +447,14 @@ sysenter_exit:
447sysenter_audit: 447sysenter_audit:
448 testl $(_TIF_WORK_SYSCALL_ENTRY & ~_TIF_SYSCALL_AUDIT),TI_flags(%ebp) 448 testl $(_TIF_WORK_SYSCALL_ENTRY & ~_TIF_SYSCALL_AUDIT),TI_flags(%ebp)
449 jnz syscall_trace_entry 449 jnz syscall_trace_entry
450 addl $4,%esp 450 /* movl PT_EAX(%esp), %eax already set, syscall number: 1st arg to audit */
451 CFI_ADJUST_CFA_OFFSET -4 451 movl PT_EBX(%esp), %edx /* ebx/a0: 2nd arg to audit */
452 movl %esi,4(%esp) /* 5th arg: 4th syscall arg */ 452 /* movl PT_ECX(%esp), %ecx already set, a1: 3nd arg to audit */
453 movl %edx,(%esp) /* 4th arg: 3rd syscall arg */ 453 pushl_cfi PT_ESI(%esp) /* a3: 5th arg */
454 /* %ecx already in %ecx 3rd arg: 2nd syscall arg */ 454 pushl_cfi PT_EDX+4(%esp) /* a2: 4th arg */
455 movl %ebx,%edx /* 2nd arg: 1st syscall arg */
456 /* %eax already in %eax 1st arg: syscall number */
457 call __audit_syscall_entry 455 call __audit_syscall_entry
458 pushl_cfi %ebx 456 popl_cfi %ecx /* get that remapped edx off the stack */
457 popl_cfi %ecx /* get that remapped esi off the stack */
459 movl PT_EAX(%esp),%eax /* reload syscall number */ 458 movl PT_EAX(%esp),%eax /* reload syscall number */
460 jmp sysenter_do_call 459 jmp sysenter_do_call
461 460
diff --git a/arch/x86/kernel/i8259.c b/arch/x86/kernel/i8259.c
index 8af817105e29..e7cc5370cd2f 100644
--- a/arch/x86/kernel/i8259.c
+++ b/arch/x86/kernel/i8259.c
@@ -111,8 +111,7 @@ static void make_8259A_irq(unsigned int irq)
111{ 111{
112 disable_irq_nosync(irq); 112 disable_irq_nosync(irq);
113 io_apic_irqs &= ~(1<<irq); 113 io_apic_irqs &= ~(1<<irq);
114 irq_set_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq, 114 irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
115 i8259A_chip.name);
116 enable_irq(irq); 115 enable_irq(irq);
117} 116}
118 117
diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c
index 44f1ed42fdf2..4de73ee78361 100644
--- a/arch/x86/kernel/irqinit.c
+++ b/arch/x86/kernel/irqinit.c
@@ -70,7 +70,6 @@ int vector_used_by_percpu_irq(unsigned int vector)
70void __init init_ISA_irqs(void) 70void __init init_ISA_irqs(void)
71{ 71{
72 struct irq_chip *chip = legacy_pic->chip; 72 struct irq_chip *chip = legacy_pic->chip;
73 const char *name = chip->name;
74 int i; 73 int i;
75 74
76#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC) 75#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
@@ -79,7 +78,7 @@ void __init init_ISA_irqs(void)
79 legacy_pic->init(0); 78 legacy_pic->init(0);
80 79
81 for (i = 0; i < nr_legacy_irqs(); i++) 80 for (i = 0; i < nr_legacy_irqs(); i++)
82 irq_set_chip_and_handler_name(i, chip, handle_level_irq, name); 81 irq_set_chip_and_handler(i, chip, handle_level_irq);
83} 82}
84 83
85void __init init_IRQ(void) 84void __init init_IRQ(void)
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 235cfd39e0d7..ab08aa2276fb 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -1128,7 +1128,6 @@ void __init setup_arch(char **cmdline_p)
1128 setup_real_mode(); 1128 setup_real_mode();
1129 1129
1130 memblock_set_current_limit(get_max_mapped()); 1130 memblock_set_current_limit(get_max_mapped());
1131 dma_contiguous_reserve(max_pfn_mapped << PAGE_SHIFT);
1132 1131
1133 /* 1132 /*
1134 * NOTE: On x86-32, only from this point on, fixmaps are ready for use. 1133 * NOTE: On x86-32, only from this point on, fixmaps are ready for use.
@@ -1159,6 +1158,7 @@ void __init setup_arch(char **cmdline_p)
1159 early_acpi_boot_init(); 1158 early_acpi_boot_init();
1160 1159
1161 initmem_init(); 1160 initmem_init();
1161 dma_contiguous_reserve(max_pfn_mapped << PAGE_SHIFT);
1162 1162
1163 /* 1163 /*
1164 * Reserve memory for crash kernel after SRAT is parsed so that it 1164 * Reserve memory for crash kernel after SRAT is parsed so that it
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 2d5200e56357..4d2128ac70bd 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -102,8 +102,6 @@ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
102DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 102DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
103EXPORT_PER_CPU_SYMBOL(cpu_info); 103EXPORT_PER_CPU_SYMBOL(cpu_info);
104 104
105static DEFINE_PER_CPU(struct completion, die_complete);
106
107atomic_t init_deasserted; 105atomic_t init_deasserted;
108 106
109/* 107/*
@@ -1318,6 +1316,8 @@ void cpu_disable_common(void)
1318 fixup_irqs(); 1316 fixup_irqs();
1319} 1317}
1320 1318
1319static DEFINE_PER_CPU(struct completion, die_complete);
1320
1321int native_cpu_disable(void) 1321int native_cpu_disable(void)
1322{ 1322{
1323 int ret; 1323 int ret;
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index b6025f9e36c6..b7e50bba3bbb 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -1166,14 +1166,17 @@ void __init tsc_init(void)
1166 1166
1167 x86_init.timers.tsc_pre_init(); 1167 x86_init.timers.tsc_pre_init();
1168 1168
1169 if (!cpu_has_tsc) 1169 if (!cpu_has_tsc) {
1170 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1170 return; 1171 return;
1172 }
1171 1173
1172 tsc_khz = x86_platform.calibrate_tsc(); 1174 tsc_khz = x86_platform.calibrate_tsc();
1173 cpu_khz = tsc_khz; 1175 cpu_khz = tsc_khz;
1174 1176
1175 if (!tsc_khz) { 1177 if (!tsc_khz) {
1176 mark_tsc_unstable("could not calculate TSC khz"); 1178 mark_tsc_unstable("could not calculate TSC khz");
1179 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1177 return; 1180 return;
1178 } 1181 }
1179 1182
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index a46207a05835..5edf088ca51e 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -504,11 +504,6 @@ static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
504 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc); 504 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
505} 505}
506 506
507static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
508{
509 register_address_increment(ctxt, &ctxt->_eip, rel);
510}
511
512static u32 desc_limit_scaled(struct desc_struct *desc) 507static u32 desc_limit_scaled(struct desc_struct *desc)
513{ 508{
514 u32 limit = get_desc_limit(desc); 509 u32 limit = get_desc_limit(desc);
@@ -569,6 +564,40 @@ static int emulate_nm(struct x86_emulate_ctxt *ctxt)
569 return emulate_exception(ctxt, NM_VECTOR, 0, false); 564 return emulate_exception(ctxt, NM_VECTOR, 0, false);
570} 565}
571 566
567static inline int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
568 int cs_l)
569{
570 switch (ctxt->op_bytes) {
571 case 2:
572 ctxt->_eip = (u16)dst;
573 break;
574 case 4:
575 ctxt->_eip = (u32)dst;
576 break;
577#ifdef CONFIG_X86_64
578 case 8:
579 if ((cs_l && is_noncanonical_address(dst)) ||
580 (!cs_l && (dst >> 32) != 0))
581 return emulate_gp(ctxt, 0);
582 ctxt->_eip = dst;
583 break;
584#endif
585 default:
586 WARN(1, "unsupported eip assignment size\n");
587 }
588 return X86EMUL_CONTINUE;
589}
590
591static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
592{
593 return assign_eip_far(ctxt, dst, ctxt->mode == X86EMUL_MODE_PROT64);
594}
595
596static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
597{
598 return assign_eip_near(ctxt, ctxt->_eip + rel);
599}
600
572static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) 601static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
573{ 602{
574 u16 selector; 603 u16 selector;
@@ -614,7 +643,8 @@ static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
614 643
615static int __linearize(struct x86_emulate_ctxt *ctxt, 644static int __linearize(struct x86_emulate_ctxt *ctxt,
616 struct segmented_address addr, 645 struct segmented_address addr,
617 unsigned size, bool write, bool fetch, 646 unsigned *max_size, unsigned size,
647 bool write, bool fetch,
618 ulong *linear) 648 ulong *linear)
619{ 649{
620 struct desc_struct desc; 650 struct desc_struct desc;
@@ -625,10 +655,15 @@ static int __linearize(struct x86_emulate_ctxt *ctxt,
625 unsigned cpl; 655 unsigned cpl;
626 656
627 la = seg_base(ctxt, addr.seg) + addr.ea; 657 la = seg_base(ctxt, addr.seg) + addr.ea;
658 *max_size = 0;
628 switch (ctxt->mode) { 659 switch (ctxt->mode) {
629 case X86EMUL_MODE_PROT64: 660 case X86EMUL_MODE_PROT64:
630 if (((signed long)la << 16) >> 16 != la) 661 if (((signed long)la << 16) >> 16 != la)
631 return emulate_gp(ctxt, 0); 662 return emulate_gp(ctxt, 0);
663
664 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
665 if (size > *max_size)
666 goto bad;
632 break; 667 break;
633 default: 668 default:
634 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, 669 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
@@ -646,20 +681,25 @@ static int __linearize(struct x86_emulate_ctxt *ctxt,
646 if ((ctxt->mode == X86EMUL_MODE_REAL) && !fetch && 681 if ((ctxt->mode == X86EMUL_MODE_REAL) && !fetch &&
647 (ctxt->d & NoBigReal)) { 682 (ctxt->d & NoBigReal)) {
648 /* la is between zero and 0xffff */ 683 /* la is between zero and 0xffff */
649 if (la > 0xffff || (u32)(la + size - 1) > 0xffff) 684 if (la > 0xffff)
650 goto bad; 685 goto bad;
686 *max_size = 0x10000 - la;
651 } else if ((desc.type & 8) || !(desc.type & 4)) { 687 } else if ((desc.type & 8) || !(desc.type & 4)) {
652 /* expand-up segment */ 688 /* expand-up segment */
653 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) 689 if (addr.ea > lim)
654 goto bad; 690 goto bad;
691 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
655 } else { 692 } else {
656 /* expand-down segment */ 693 /* expand-down segment */
657 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim) 694 if (addr.ea <= lim)
658 goto bad; 695 goto bad;
659 lim = desc.d ? 0xffffffff : 0xffff; 696 lim = desc.d ? 0xffffffff : 0xffff;
660 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) 697 if (addr.ea > lim)
661 goto bad; 698 goto bad;
699 *max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
662 } 700 }
701 if (size > *max_size)
702 goto bad;
663 cpl = ctxt->ops->cpl(ctxt); 703 cpl = ctxt->ops->cpl(ctxt);
664 if (!(desc.type & 8)) { 704 if (!(desc.type & 8)) {
665 /* data segment */ 705 /* data segment */
@@ -684,9 +724,9 @@ static int __linearize(struct x86_emulate_ctxt *ctxt,
684 return X86EMUL_CONTINUE; 724 return X86EMUL_CONTINUE;
685bad: 725bad:
686 if (addr.seg == VCPU_SREG_SS) 726 if (addr.seg == VCPU_SREG_SS)
687 return emulate_ss(ctxt, sel); 727 return emulate_ss(ctxt, 0);
688 else 728 else
689 return emulate_gp(ctxt, sel); 729 return emulate_gp(ctxt, 0);
690} 730}
691 731
692static int linearize(struct x86_emulate_ctxt *ctxt, 732static int linearize(struct x86_emulate_ctxt *ctxt,
@@ -694,7 +734,8 @@ static int linearize(struct x86_emulate_ctxt *ctxt,
694 unsigned size, bool write, 734 unsigned size, bool write,
695 ulong *linear) 735 ulong *linear)
696{ 736{
697 return __linearize(ctxt, addr, size, write, false, linear); 737 unsigned max_size;
738 return __linearize(ctxt, addr, &max_size, size, write, false, linear);
698} 739}
699 740
700 741
@@ -719,17 +760,27 @@ static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
719static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size) 760static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
720{ 761{
721 int rc; 762 int rc;
722 unsigned size; 763 unsigned size, max_size;
723 unsigned long linear; 764 unsigned long linear;
724 int cur_size = ctxt->fetch.end - ctxt->fetch.data; 765 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
725 struct segmented_address addr = { .seg = VCPU_SREG_CS, 766 struct segmented_address addr = { .seg = VCPU_SREG_CS,
726 .ea = ctxt->eip + cur_size }; 767 .ea = ctxt->eip + cur_size };
727 768
728 size = 15UL ^ cur_size; 769 /*
729 rc = __linearize(ctxt, addr, size, false, true, &linear); 770 * We do not know exactly how many bytes will be needed, and
771 * __linearize is expensive, so fetch as much as possible. We
772 * just have to avoid going beyond the 15 byte limit, the end
773 * of the segment, or the end of the page.
774 *
775 * __linearize is called with size 0 so that it does not do any
776 * boundary check itself. Instead, we use max_size to check
777 * against op_size.
778 */
779 rc = __linearize(ctxt, addr, &max_size, 0, false, true, &linear);
730 if (unlikely(rc != X86EMUL_CONTINUE)) 780 if (unlikely(rc != X86EMUL_CONTINUE))
731 return rc; 781 return rc;
732 782
783 size = min_t(unsigned, 15UL ^ cur_size, max_size);
733 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear)); 784 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
734 785
735 /* 786 /*
@@ -739,7 +790,8 @@ static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
739 * still, we must have hit the 15-byte boundary. 790 * still, we must have hit the 15-byte boundary.
740 */ 791 */
741 if (unlikely(size < op_size)) 792 if (unlikely(size < op_size))
742 return X86EMUL_UNHANDLEABLE; 793 return emulate_gp(ctxt, 0);
794
743 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end, 795 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
744 size, &ctxt->exception); 796 size, &ctxt->exception);
745 if (unlikely(rc != X86EMUL_CONTINUE)) 797 if (unlikely(rc != X86EMUL_CONTINUE))
@@ -751,8 +803,10 @@ static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
751static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, 803static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
752 unsigned size) 804 unsigned size)
753{ 805{
754 if (unlikely(ctxt->fetch.end - ctxt->fetch.ptr < size)) 806 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
755 return __do_insn_fetch_bytes(ctxt, size); 807
808 if (unlikely(done_size < size))
809 return __do_insn_fetch_bytes(ctxt, size - done_size);
756 else 810 else
757 return X86EMUL_CONTINUE; 811 return X86EMUL_CONTINUE;
758} 812}
@@ -1416,7 +1470,9 @@ static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1416 1470
1417/* Does not support long mode */ 1471/* Does not support long mode */
1418static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1472static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1419 u16 selector, int seg, u8 cpl, bool in_task_switch) 1473 u16 selector, int seg, u8 cpl,
1474 bool in_task_switch,
1475 struct desc_struct *desc)
1420{ 1476{
1421 struct desc_struct seg_desc, old_desc; 1477 struct desc_struct seg_desc, old_desc;
1422 u8 dpl, rpl; 1478 u8 dpl, rpl;
@@ -1557,6 +1613,8 @@ static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1557 } 1613 }
1558load: 1614load:
1559 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg); 1615 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
1616 if (desc)
1617 *desc = seg_desc;
1560 return X86EMUL_CONTINUE; 1618 return X86EMUL_CONTINUE;
1561exception: 1619exception:
1562 return emulate_exception(ctxt, err_vec, err_code, true); 1620 return emulate_exception(ctxt, err_vec, err_code, true);
@@ -1566,7 +1624,7 @@ static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1566 u16 selector, int seg) 1624 u16 selector, int seg)
1567{ 1625{
1568 u8 cpl = ctxt->ops->cpl(ctxt); 1626 u8 cpl = ctxt->ops->cpl(ctxt);
1569 return __load_segment_descriptor(ctxt, selector, seg, cpl, false); 1627 return __load_segment_descriptor(ctxt, selector, seg, cpl, false, NULL);
1570} 1628}
1571 1629
1572static void write_register_operand(struct operand *op) 1630static void write_register_operand(struct operand *op)
@@ -1960,17 +2018,31 @@ static int em_iret(struct x86_emulate_ctxt *ctxt)
1960static int em_jmp_far(struct x86_emulate_ctxt *ctxt) 2018static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
1961{ 2019{
1962 int rc; 2020 int rc;
1963 unsigned short sel; 2021 unsigned short sel, old_sel;
2022 struct desc_struct old_desc, new_desc;
2023 const struct x86_emulate_ops *ops = ctxt->ops;
2024 u8 cpl = ctxt->ops->cpl(ctxt);
2025
2026 /* Assignment of RIP may only fail in 64-bit mode */
2027 if (ctxt->mode == X86EMUL_MODE_PROT64)
2028 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2029 VCPU_SREG_CS);
1964 2030
1965 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2031 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
1966 2032
1967 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS); 2033 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
2034 &new_desc);
1968 if (rc != X86EMUL_CONTINUE) 2035 if (rc != X86EMUL_CONTINUE)
1969 return rc; 2036 return rc;
1970 2037
1971 ctxt->_eip = 0; 2038 rc = assign_eip_far(ctxt, ctxt->src.val, new_desc.l);
1972 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); 2039 if (rc != X86EMUL_CONTINUE) {
1973 return X86EMUL_CONTINUE; 2040 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
2041 /* assigning eip failed; restore the old cs */
2042 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2043 return rc;
2044 }
2045 return rc;
1974} 2046}
1975 2047
1976static int em_grp45(struct x86_emulate_ctxt *ctxt) 2048static int em_grp45(struct x86_emulate_ctxt *ctxt)
@@ -1981,13 +2053,15 @@ static int em_grp45(struct x86_emulate_ctxt *ctxt)
1981 case 2: /* call near abs */ { 2053 case 2: /* call near abs */ {
1982 long int old_eip; 2054 long int old_eip;
1983 old_eip = ctxt->_eip; 2055 old_eip = ctxt->_eip;
1984 ctxt->_eip = ctxt->src.val; 2056 rc = assign_eip_near(ctxt, ctxt->src.val);
2057 if (rc != X86EMUL_CONTINUE)
2058 break;
1985 ctxt->src.val = old_eip; 2059 ctxt->src.val = old_eip;
1986 rc = em_push(ctxt); 2060 rc = em_push(ctxt);
1987 break; 2061 break;
1988 } 2062 }
1989 case 4: /* jmp abs */ 2063 case 4: /* jmp abs */
1990 ctxt->_eip = ctxt->src.val; 2064 rc = assign_eip_near(ctxt, ctxt->src.val);
1991 break; 2065 break;
1992 case 5: /* jmp far */ 2066 case 5: /* jmp far */
1993 rc = em_jmp_far(ctxt); 2067 rc = em_jmp_far(ctxt);
@@ -2022,30 +2096,47 @@ static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
2022 2096
2023static int em_ret(struct x86_emulate_ctxt *ctxt) 2097static int em_ret(struct x86_emulate_ctxt *ctxt)
2024{ 2098{
2025 ctxt->dst.type = OP_REG; 2099 int rc;
2026 ctxt->dst.addr.reg = &ctxt->_eip; 2100 unsigned long eip;
2027 ctxt->dst.bytes = ctxt->op_bytes; 2101
2028 return em_pop(ctxt); 2102 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2103 if (rc != X86EMUL_CONTINUE)
2104 return rc;
2105
2106 return assign_eip_near(ctxt, eip);
2029} 2107}
2030 2108
2031static int em_ret_far(struct x86_emulate_ctxt *ctxt) 2109static int em_ret_far(struct x86_emulate_ctxt *ctxt)
2032{ 2110{
2033 int rc; 2111 int rc;
2034 unsigned long cs; 2112 unsigned long eip, cs;
2113 u16 old_cs;
2035 int cpl = ctxt->ops->cpl(ctxt); 2114 int cpl = ctxt->ops->cpl(ctxt);
2115 struct desc_struct old_desc, new_desc;
2116 const struct x86_emulate_ops *ops = ctxt->ops;
2036 2117
2037 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes); 2118 if (ctxt->mode == X86EMUL_MODE_PROT64)
2119 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2120 VCPU_SREG_CS);
2121
2122 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2038 if (rc != X86EMUL_CONTINUE) 2123 if (rc != X86EMUL_CONTINUE)
2039 return rc; 2124 return rc;
2040 if (ctxt->op_bytes == 4)
2041 ctxt->_eip = (u32)ctxt->_eip;
2042 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2125 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2043 if (rc != X86EMUL_CONTINUE) 2126 if (rc != X86EMUL_CONTINUE)
2044 return rc; 2127 return rc;
2045 /* Outer-privilege level return is not implemented */ 2128 /* Outer-privilege level return is not implemented */
2046 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl) 2129 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2047 return X86EMUL_UNHANDLEABLE; 2130 return X86EMUL_UNHANDLEABLE;
2048 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); 2131 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, 0, false,
2132 &new_desc);
2133 if (rc != X86EMUL_CONTINUE)
2134 return rc;
2135 rc = assign_eip_far(ctxt, eip, new_desc.l);
2136 if (rc != X86EMUL_CONTINUE) {
2137 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
2138 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2139 }
2049 return rc; 2140 return rc;
2050} 2141}
2051 2142
@@ -2306,7 +2397,7 @@ static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2306{ 2397{
2307 const struct x86_emulate_ops *ops = ctxt->ops; 2398 const struct x86_emulate_ops *ops = ctxt->ops;
2308 struct desc_struct cs, ss; 2399 struct desc_struct cs, ss;
2309 u64 msr_data; 2400 u64 msr_data, rcx, rdx;
2310 int usermode; 2401 int usermode;
2311 u16 cs_sel = 0, ss_sel = 0; 2402 u16 cs_sel = 0, ss_sel = 0;
2312 2403
@@ -2322,6 +2413,9 @@ static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2322 else 2413 else
2323 usermode = X86EMUL_MODE_PROT32; 2414 usermode = X86EMUL_MODE_PROT32;
2324 2415
2416 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2417 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2418
2325 cs.dpl = 3; 2419 cs.dpl = 3;
2326 ss.dpl = 3; 2420 ss.dpl = 3;
2327 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2421 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
@@ -2339,6 +2433,9 @@ static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2339 ss_sel = cs_sel + 8; 2433 ss_sel = cs_sel + 8;
2340 cs.d = 0; 2434 cs.d = 0;
2341 cs.l = 1; 2435 cs.l = 1;
2436 if (is_noncanonical_address(rcx) ||
2437 is_noncanonical_address(rdx))
2438 return emulate_gp(ctxt, 0);
2342 break; 2439 break;
2343 } 2440 }
2344 cs_sel |= SELECTOR_RPL_MASK; 2441 cs_sel |= SELECTOR_RPL_MASK;
@@ -2347,8 +2444,8 @@ static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2347 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2444 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2348 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2445 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2349 2446
2350 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX); 2447 ctxt->_eip = rdx;
2351 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX); 2448 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
2352 2449
2353 return X86EMUL_CONTINUE; 2450 return X86EMUL_CONTINUE;
2354} 2451}
@@ -2466,19 +2563,24 @@ static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2466 * Now load segment descriptors. If fault happens at this stage 2563 * Now load segment descriptors. If fault happens at this stage
2467 * it is handled in a context of new task 2564 * it is handled in a context of new task
2468 */ 2565 */
2469 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, true); 2566 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
2567 true, NULL);
2470 if (ret != X86EMUL_CONTINUE) 2568 if (ret != X86EMUL_CONTINUE)
2471 return ret; 2569 return ret;
2472 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true); 2570 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2571 true, NULL);
2473 if (ret != X86EMUL_CONTINUE) 2572 if (ret != X86EMUL_CONTINUE)
2474 return ret; 2573 return ret;
2475 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true); 2574 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2575 true, NULL);
2476 if (ret != X86EMUL_CONTINUE) 2576 if (ret != X86EMUL_CONTINUE)
2477 return ret; 2577 return ret;
2478 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true); 2578 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2579 true, NULL);
2479 if (ret != X86EMUL_CONTINUE) 2580 if (ret != X86EMUL_CONTINUE)
2480 return ret; 2581 return ret;
2481 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true); 2582 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2583 true, NULL);
2482 if (ret != X86EMUL_CONTINUE) 2584 if (ret != X86EMUL_CONTINUE)
2483 return ret; 2585 return ret;
2484 2586
@@ -2603,25 +2705,32 @@ static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2603 * Now load segment descriptors. If fault happenes at this stage 2705 * Now load segment descriptors. If fault happenes at this stage
2604 * it is handled in a context of new task 2706 * it is handled in a context of new task
2605 */ 2707 */
2606 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, cpl, true); 2708 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
2709 cpl, true, NULL);
2607 if (ret != X86EMUL_CONTINUE) 2710 if (ret != X86EMUL_CONTINUE)
2608 return ret; 2711 return ret;
2609 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true); 2712 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2713 true, NULL);
2610 if (ret != X86EMUL_CONTINUE) 2714 if (ret != X86EMUL_CONTINUE)
2611 return ret; 2715 return ret;
2612 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true); 2716 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2717 true, NULL);
2613 if (ret != X86EMUL_CONTINUE) 2718 if (ret != X86EMUL_CONTINUE)
2614 return ret; 2719 return ret;
2615 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true); 2720 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2721 true, NULL);
2616 if (ret != X86EMUL_CONTINUE) 2722 if (ret != X86EMUL_CONTINUE)
2617 return ret; 2723 return ret;
2618 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true); 2724 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2725 true, NULL);
2619 if (ret != X86EMUL_CONTINUE) 2726 if (ret != X86EMUL_CONTINUE)
2620 return ret; 2727 return ret;
2621 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, true); 2728 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
2729 true, NULL);
2622 if (ret != X86EMUL_CONTINUE) 2730 if (ret != X86EMUL_CONTINUE)
2623 return ret; 2731 return ret;
2624 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, true); 2732 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
2733 true, NULL);
2625 if (ret != X86EMUL_CONTINUE) 2734 if (ret != X86EMUL_CONTINUE)
2626 return ret; 2735 return ret;
2627 2736
@@ -2888,10 +2997,13 @@ static int em_aad(struct x86_emulate_ctxt *ctxt)
2888 2997
2889static int em_call(struct x86_emulate_ctxt *ctxt) 2998static int em_call(struct x86_emulate_ctxt *ctxt)
2890{ 2999{
3000 int rc;
2891 long rel = ctxt->src.val; 3001 long rel = ctxt->src.val;
2892 3002
2893 ctxt->src.val = (unsigned long)ctxt->_eip; 3003 ctxt->src.val = (unsigned long)ctxt->_eip;
2894 jmp_rel(ctxt, rel); 3004 rc = jmp_rel(ctxt, rel);
3005 if (rc != X86EMUL_CONTINUE)
3006 return rc;
2895 return em_push(ctxt); 3007 return em_push(ctxt);
2896} 3008}
2897 3009
@@ -2900,34 +3012,50 @@ static int em_call_far(struct x86_emulate_ctxt *ctxt)
2900 u16 sel, old_cs; 3012 u16 sel, old_cs;
2901 ulong old_eip; 3013 ulong old_eip;
2902 int rc; 3014 int rc;
3015 struct desc_struct old_desc, new_desc;
3016 const struct x86_emulate_ops *ops = ctxt->ops;
3017 int cpl = ctxt->ops->cpl(ctxt);
2903 3018
2904 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2905 old_eip = ctxt->_eip; 3019 old_eip = ctxt->_eip;
3020 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
2906 3021
2907 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 3022 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2908 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS)) 3023 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
3024 &new_desc);
3025 if (rc != X86EMUL_CONTINUE)
2909 return X86EMUL_CONTINUE; 3026 return X86EMUL_CONTINUE;
2910 3027
2911 ctxt->_eip = 0; 3028 rc = assign_eip_far(ctxt, ctxt->src.val, new_desc.l);
2912 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); 3029 if (rc != X86EMUL_CONTINUE)
3030 goto fail;
2913 3031
2914 ctxt->src.val = old_cs; 3032 ctxt->src.val = old_cs;
2915 rc = em_push(ctxt); 3033 rc = em_push(ctxt);
2916 if (rc != X86EMUL_CONTINUE) 3034 if (rc != X86EMUL_CONTINUE)
2917 return rc; 3035 goto fail;
2918 3036
2919 ctxt->src.val = old_eip; 3037 ctxt->src.val = old_eip;
2920 return em_push(ctxt); 3038 rc = em_push(ctxt);
3039 /* If we failed, we tainted the memory, but the very least we should
3040 restore cs */
3041 if (rc != X86EMUL_CONTINUE)
3042 goto fail;
3043 return rc;
3044fail:
3045 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3046 return rc;
3047
2921} 3048}
2922 3049
2923static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) 3050static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2924{ 3051{
2925 int rc; 3052 int rc;
3053 unsigned long eip;
2926 3054
2927 ctxt->dst.type = OP_REG; 3055 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2928 ctxt->dst.addr.reg = &ctxt->_eip; 3056 if (rc != X86EMUL_CONTINUE)
2929 ctxt->dst.bytes = ctxt->op_bytes; 3057 return rc;
2930 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); 3058 rc = assign_eip_near(ctxt, eip);
2931 if (rc != X86EMUL_CONTINUE) 3059 if (rc != X86EMUL_CONTINUE)
2932 return rc; 3060 return rc;
2933 rsp_increment(ctxt, ctxt->src.val); 3061 rsp_increment(ctxt, ctxt->src.val);
@@ -3254,20 +3382,24 @@ static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3254 3382
3255static int em_loop(struct x86_emulate_ctxt *ctxt) 3383static int em_loop(struct x86_emulate_ctxt *ctxt)
3256{ 3384{
3385 int rc = X86EMUL_CONTINUE;
3386
3257 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1); 3387 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3258 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) && 3388 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
3259 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) 3389 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3260 jmp_rel(ctxt, ctxt->src.val); 3390 rc = jmp_rel(ctxt, ctxt->src.val);
3261 3391
3262 return X86EMUL_CONTINUE; 3392 return rc;
3263} 3393}
3264 3394
3265static int em_jcxz(struct x86_emulate_ctxt *ctxt) 3395static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3266{ 3396{
3397 int rc = X86EMUL_CONTINUE;
3398
3267 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) 3399 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
3268 jmp_rel(ctxt, ctxt->src.val); 3400 rc = jmp_rel(ctxt, ctxt->src.val);
3269 3401
3270 return X86EMUL_CONTINUE; 3402 return rc;
3271} 3403}
3272 3404
3273static int em_in(struct x86_emulate_ctxt *ctxt) 3405static int em_in(struct x86_emulate_ctxt *ctxt)
@@ -3355,6 +3487,12 @@ static int em_bswap(struct x86_emulate_ctxt *ctxt)
3355 return X86EMUL_CONTINUE; 3487 return X86EMUL_CONTINUE;
3356} 3488}
3357 3489
3490static int em_clflush(struct x86_emulate_ctxt *ctxt)
3491{
3492 /* emulating clflush regardless of cpuid */
3493 return X86EMUL_CONTINUE;
3494}
3495
3358static bool valid_cr(int nr) 3496static bool valid_cr(int nr)
3359{ 3497{
3360 switch (nr) { 3498 switch (nr) {
@@ -3693,6 +3831,16 @@ static const struct opcode group11[] = {
3693 X7(D(Undefined)), 3831 X7(D(Undefined)),
3694}; 3832};
3695 3833
3834static const struct gprefix pfx_0f_ae_7 = {
3835 I(SrcMem | ByteOp, em_clflush), N, N, N,
3836};
3837
3838static const struct group_dual group15 = { {
3839 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
3840}, {
3841 N, N, N, N, N, N, N, N,
3842} };
3843
3696static const struct gprefix pfx_0f_6f_0f_7f = { 3844static const struct gprefix pfx_0f_6f_0f_7f = {
3697 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), 3845 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
3698}; 3846};
@@ -3901,10 +4049,11 @@ static const struct opcode twobyte_table[256] = {
3901 N, I(ImplicitOps | EmulateOnUD, em_syscall), 4049 N, I(ImplicitOps | EmulateOnUD, em_syscall),
3902 II(ImplicitOps | Priv, em_clts, clts), N, 4050 II(ImplicitOps | Priv, em_clts, clts), N,
3903 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, 4051 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3904 N, D(ImplicitOps | ModRM), N, N, 4052 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
3905 /* 0x10 - 0x1F */ 4053 /* 0x10 - 0x1F */
3906 N, N, N, N, N, N, N, N, 4054 N, N, N, N, N, N, N, N,
3907 D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM), 4055 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4056 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
3908 /* 0x20 - 0x2F */ 4057 /* 0x20 - 0x2F */
3909 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read), 4058 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
3910 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read), 4059 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
@@ -3956,7 +4105,7 @@ static const struct opcode twobyte_table[256] = {
3956 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), 4105 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
3957 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd), 4106 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
3958 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd), 4107 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
3959 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul), 4108 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
3960 /* 0xB0 - 0xB7 */ 4109 /* 0xB0 - 0xB7 */
3961 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg), 4110 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
3962 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), 4111 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
@@ -4473,10 +4622,10 @@ done_prefixes:
4473 /* Decode and fetch the destination operand: register or memory. */ 4622 /* Decode and fetch the destination operand: register or memory. */
4474 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); 4623 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
4475 4624
4476done:
4477 if (ctxt->rip_relative) 4625 if (ctxt->rip_relative)
4478 ctxt->memopp->addr.mem.ea += ctxt->_eip; 4626 ctxt->memopp->addr.mem.ea += ctxt->_eip;
4479 4627
4628done:
4480 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; 4629 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
4481} 4630}
4482 4631
@@ -4726,7 +4875,7 @@ special_insn:
4726 break; 4875 break;
4727 case 0x70 ... 0x7f: /* jcc (short) */ 4876 case 0x70 ... 0x7f: /* jcc (short) */
4728 if (test_cc(ctxt->b, ctxt->eflags)) 4877 if (test_cc(ctxt->b, ctxt->eflags))
4729 jmp_rel(ctxt, ctxt->src.val); 4878 rc = jmp_rel(ctxt, ctxt->src.val);
4730 break; 4879 break;
4731 case 0x8d: /* lea r16/r32, m */ 4880 case 0x8d: /* lea r16/r32, m */
4732 ctxt->dst.val = ctxt->src.addr.mem.ea; 4881 ctxt->dst.val = ctxt->src.addr.mem.ea;
@@ -4756,7 +4905,7 @@ special_insn:
4756 break; 4905 break;
4757 case 0xe9: /* jmp rel */ 4906 case 0xe9: /* jmp rel */
4758 case 0xeb: /* jmp rel short */ 4907 case 0xeb: /* jmp rel short */
4759 jmp_rel(ctxt, ctxt->src.val); 4908 rc = jmp_rel(ctxt, ctxt->src.val);
4760 ctxt->dst.type = OP_NONE; /* Disable writeback. */ 4909 ctxt->dst.type = OP_NONE; /* Disable writeback. */
4761 break; 4910 break;
4762 case 0xf4: /* hlt */ 4911 case 0xf4: /* hlt */
@@ -4881,13 +5030,11 @@ twobyte_insn:
4881 break; 5030 break;
4882 case 0x80 ... 0x8f: /* jnz rel, etc*/ 5031 case 0x80 ... 0x8f: /* jnz rel, etc*/
4883 if (test_cc(ctxt->b, ctxt->eflags)) 5032 if (test_cc(ctxt->b, ctxt->eflags))
4884 jmp_rel(ctxt, ctxt->src.val); 5033 rc = jmp_rel(ctxt, ctxt->src.val);
4885 break; 5034 break;
4886 case 0x90 ... 0x9f: /* setcc r/m8 */ 5035 case 0x90 ... 0x9f: /* setcc r/m8 */
4887 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); 5036 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
4888 break; 5037 break;
4889 case 0xae: /* clflush */
4890 break;
4891 case 0xb6 ... 0xb7: /* movzx */ 5038 case 0xb6 ... 0xb7: /* movzx */
4892 ctxt->dst.bytes = ctxt->op_bytes; 5039 ctxt->dst.bytes = ctxt->op_bytes;
4893 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val 5040 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
diff --git a/arch/x86/kvm/i8254.c b/arch/x86/kvm/i8254.c
index 518d86471b76..298781d4cfb4 100644
--- a/arch/x86/kvm/i8254.c
+++ b/arch/x86/kvm/i8254.c
@@ -262,8 +262,10 @@ void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu)
262 return; 262 return;
263 263
264 timer = &pit->pit_state.timer; 264 timer = &pit->pit_state.timer;
265 mutex_lock(&pit->pit_state.lock);
265 if (hrtimer_cancel(timer)) 266 if (hrtimer_cancel(timer))
266 hrtimer_start_expires(timer, HRTIMER_MODE_ABS); 267 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
268 mutex_unlock(&pit->pit_state.lock);
267} 269}
268 270
269static void destroy_pit_timer(struct kvm_pit *pit) 271static void destroy_pit_timer(struct kvm_pit *pit)
diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h
index 806d58e3c320..fd49c867b25a 100644
--- a/arch/x86/kvm/paging_tmpl.h
+++ b/arch/x86/kvm/paging_tmpl.h
@@ -298,7 +298,7 @@ retry_walk:
298 } 298 }
299#endif 299#endif
300 walker->max_level = walker->level; 300 walker->max_level = walker->level;
301 ASSERT(!is_long_mode(vcpu) && is_pae(vcpu)); 301 ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu)));
302 302
303 accessed_dirty = PT_GUEST_ACCESSED_MASK; 303 accessed_dirty = PT_GUEST_ACCESSED_MASK;
304 pt_access = pte_access = ACC_ALL; 304 pt_access = pte_access = ACC_ALL;
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 65510f624dfe..7527cefc5a43 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -3251,7 +3251,7 @@ static int wrmsr_interception(struct vcpu_svm *svm)
3251 msr.host_initiated = false; 3251 msr.host_initiated = false;
3252 3252
3253 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2; 3253 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3254 if (svm_set_msr(&svm->vcpu, &msr)) { 3254 if (kvm_set_msr(&svm->vcpu, &msr)) {
3255 trace_kvm_msr_write_ex(ecx, data); 3255 trace_kvm_msr_write_ex(ecx, data);
3256 kvm_inject_gp(&svm->vcpu, 0); 3256 kvm_inject_gp(&svm->vcpu, 0);
3257 } else { 3257 } else {
@@ -3551,9 +3551,9 @@ static int handle_exit(struct kvm_vcpu *vcpu)
3551 3551
3552 if (exit_code >= ARRAY_SIZE(svm_exit_handlers) 3552 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3553 || !svm_exit_handlers[exit_code]) { 3553 || !svm_exit_handlers[exit_code]) {
3554 kvm_run->exit_reason = KVM_EXIT_UNKNOWN; 3554 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_code);
3555 kvm_run->hw.hardware_exit_reason = exit_code; 3555 kvm_queue_exception(vcpu, UD_VECTOR);
3556 return 0; 3556 return 1;
3557 } 3557 }
3558 3558
3559 return svm_exit_handlers[exit_code](svm); 3559 return svm_exit_handlers[exit_code](svm);
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 0acac81f198b..3e556c68351b 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -2659,12 +2659,15 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2659 default: 2659 default:
2660 msr = find_msr_entry(vmx, msr_index); 2660 msr = find_msr_entry(vmx, msr_index);
2661 if (msr) { 2661 if (msr) {
2662 u64 old_msr_data = msr->data;
2662 msr->data = data; 2663 msr->data = data;
2663 if (msr - vmx->guest_msrs < vmx->save_nmsrs) { 2664 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2664 preempt_disable(); 2665 preempt_disable();
2665 kvm_set_shared_msr(msr->index, msr->data, 2666 ret = kvm_set_shared_msr(msr->index, msr->data,
2666 msr->mask); 2667 msr->mask);
2667 preempt_enable(); 2668 preempt_enable();
2669 if (ret)
2670 msr->data = old_msr_data;
2668 } 2671 }
2669 break; 2672 break;
2670 } 2673 }
@@ -4576,7 +4579,7 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
4576 vmcs_write32(TPR_THRESHOLD, 0); 4579 vmcs_write32(TPR_THRESHOLD, 0);
4577 } 4580 }
4578 4581
4579 kvm_vcpu_reload_apic_access_page(vcpu); 4582 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4580 4583
4581 if (vmx_vm_has_apicv(vcpu->kvm)) 4584 if (vmx_vm_has_apicv(vcpu->kvm))
4582 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc)); 4585 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
@@ -5291,7 +5294,7 @@ static int handle_wrmsr(struct kvm_vcpu *vcpu)
5291 msr.data = data; 5294 msr.data = data;
5292 msr.index = ecx; 5295 msr.index = ecx;
5293 msr.host_initiated = false; 5296 msr.host_initiated = false;
5294 if (vmx_set_msr(vcpu, &msr) != 0) { 5297 if (kvm_set_msr(vcpu, &msr) != 0) {
5295 trace_kvm_msr_write_ex(ecx, data); 5298 trace_kvm_msr_write_ex(ecx, data);
5296 kvm_inject_gp(vcpu, 0); 5299 kvm_inject_gp(vcpu, 0);
5297 return 1; 5300 return 1;
@@ -6423,6 +6426,8 @@ static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6423 const unsigned long *fields = shadow_read_write_fields; 6426 const unsigned long *fields = shadow_read_write_fields;
6424 const int num_fields = max_shadow_read_write_fields; 6427 const int num_fields = max_shadow_read_write_fields;
6425 6428
6429 preempt_disable();
6430
6426 vmcs_load(shadow_vmcs); 6431 vmcs_load(shadow_vmcs);
6427 6432
6428 for (i = 0; i < num_fields; i++) { 6433 for (i = 0; i < num_fields; i++) {
@@ -6446,6 +6451,8 @@ static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6446 6451
6447 vmcs_clear(shadow_vmcs); 6452 vmcs_clear(shadow_vmcs);
6448 vmcs_load(vmx->loaded_vmcs->vmcs); 6453 vmcs_load(vmx->loaded_vmcs->vmcs);
6454
6455 preempt_enable();
6449} 6456}
6450 6457
6451static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx) 6458static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
@@ -6743,6 +6750,12 @@ static int handle_invept(struct kvm_vcpu *vcpu)
6743 return 1; 6750 return 1;
6744} 6751}
6745 6752
6753static int handle_invvpid(struct kvm_vcpu *vcpu)
6754{
6755 kvm_queue_exception(vcpu, UD_VECTOR);
6756 return 1;
6757}
6758
6746/* 6759/*
6747 * The exit handlers return 1 if the exit was handled fully and guest execution 6760 * The exit handlers return 1 if the exit was handled fully and guest execution
6748 * may resume. Otherwise they set the kvm_run parameter to indicate what needs 6761 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
@@ -6788,6 +6801,7 @@ static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6788 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, 6801 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
6789 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, 6802 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
6790 [EXIT_REASON_INVEPT] = handle_invept, 6803 [EXIT_REASON_INVEPT] = handle_invept,
6804 [EXIT_REASON_INVVPID] = handle_invvpid,
6791}; 6805};
6792 6806
6793static const int kvm_vmx_max_exit_handlers = 6807static const int kvm_vmx_max_exit_handlers =
@@ -7023,7 +7037,7 @@ static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7023 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD: 7037 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7024 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE: 7038 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7025 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON: 7039 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7026 case EXIT_REASON_INVEPT: 7040 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7027 /* 7041 /*
7028 * VMX instructions trap unconditionally. This allows L1 to 7042 * VMX instructions trap unconditionally. This allows L1 to
7029 * emulate them for its L2 guest, i.e., allows 3-level nesting! 7043 * emulate them for its L2 guest, i.e., allows 3-level nesting!
@@ -7164,10 +7178,10 @@ static int vmx_handle_exit(struct kvm_vcpu *vcpu)
7164 && kvm_vmx_exit_handlers[exit_reason]) 7178 && kvm_vmx_exit_handlers[exit_reason])
7165 return kvm_vmx_exit_handlers[exit_reason](vcpu); 7179 return kvm_vmx_exit_handlers[exit_reason](vcpu);
7166 else { 7180 else {
7167 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN; 7181 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
7168 vcpu->run->hw.hardware_exit_reason = exit_reason; 7182 kvm_queue_exception(vcpu, UD_VECTOR);
7183 return 1;
7169 } 7184 }
7170 return 0;
7171} 7185}
7172 7186
7173static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) 7187static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 34c8f94331f8..0033df32a745 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -229,20 +229,25 @@ static void kvm_shared_msr_cpu_online(void)
229 shared_msr_update(i, shared_msrs_global.msrs[i]); 229 shared_msr_update(i, shared_msrs_global.msrs[i]);
230} 230}
231 231
232void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask) 232int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
233{ 233{
234 unsigned int cpu = smp_processor_id(); 234 unsigned int cpu = smp_processor_id();
235 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu); 235 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
236 int err;
236 237
237 if (((value ^ smsr->values[slot].curr) & mask) == 0) 238 if (((value ^ smsr->values[slot].curr) & mask) == 0)
238 return; 239 return 0;
239 smsr->values[slot].curr = value; 240 smsr->values[slot].curr = value;
240 wrmsrl(shared_msrs_global.msrs[slot], value); 241 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
242 if (err)
243 return 1;
244
241 if (!smsr->registered) { 245 if (!smsr->registered) {
242 smsr->urn.on_user_return = kvm_on_user_return; 246 smsr->urn.on_user_return = kvm_on_user_return;
243 user_return_notifier_register(&smsr->urn); 247 user_return_notifier_register(&smsr->urn);
244 smsr->registered = true; 248 smsr->registered = true;
245 } 249 }
250 return 0;
246} 251}
247EXPORT_SYMBOL_GPL(kvm_set_shared_msr); 252EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
248 253
@@ -987,7 +992,6 @@ void kvm_enable_efer_bits(u64 mask)
987} 992}
988EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); 993EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
989 994
990
991/* 995/*
992 * Writes msr value into into the appropriate "register". 996 * Writes msr value into into the appropriate "register".
993 * Returns 0 on success, non-0 otherwise. 997 * Returns 0 on success, non-0 otherwise.
@@ -995,8 +999,34 @@ EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
995 */ 999 */
996int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 1000int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
997{ 1001{
1002 switch (msr->index) {
1003 case MSR_FS_BASE:
1004 case MSR_GS_BASE:
1005 case MSR_KERNEL_GS_BASE:
1006 case MSR_CSTAR:
1007 case MSR_LSTAR:
1008 if (is_noncanonical_address(msr->data))
1009 return 1;
1010 break;
1011 case MSR_IA32_SYSENTER_EIP:
1012 case MSR_IA32_SYSENTER_ESP:
1013 /*
1014 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1015 * non-canonical address is written on Intel but not on
1016 * AMD (which ignores the top 32-bits, because it does
1017 * not implement 64-bit SYSENTER).
1018 *
1019 * 64-bit code should hence be able to write a non-canonical
1020 * value on AMD. Making the address canonical ensures that
1021 * vmentry does not fail on Intel after writing a non-canonical
1022 * value, and that something deterministic happens if the guest
1023 * invokes 64-bit SYSENTER.
1024 */
1025 msr->data = get_canonical(msr->data);
1026 }
998 return kvm_x86_ops->set_msr(vcpu, msr); 1027 return kvm_x86_ops->set_msr(vcpu, msr);
999} 1028}
1029EXPORT_SYMBOL_GPL(kvm_set_msr);
1000 1030
1001/* 1031/*
1002 * Adapt set_msr() to msr_io()'s calling convention 1032 * Adapt set_msr() to msr_io()'s calling convention
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index ae242a7c11c7..36de293caf25 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -409,7 +409,7 @@ phys_addr_t slow_virt_to_phys(void *__virt_addr)
409 psize = page_level_size(level); 409 psize = page_level_size(level);
410 pmask = page_level_mask(level); 410 pmask = page_level_mask(level);
411 offset = virt_addr & ~pmask; 411 offset = virt_addr & ~pmask;
412 phys_addr = pte_pfn(*pte) << PAGE_SHIFT; 412 phys_addr = (phys_addr_t)pte_pfn(*pte) << PAGE_SHIFT;
413 return (phys_addr | offset); 413 return (phys_addr | offset);
414} 414}
415EXPORT_SYMBOL_GPL(slow_virt_to_phys); 415EXPORT_SYMBOL_GPL(slow_virt_to_phys);
diff --git a/arch/x86/platform/efi/efi-bgrt.c b/arch/x86/platform/efi/efi-bgrt.c
index f15103dff4b4..d143d216d52b 100644
--- a/arch/x86/platform/efi/efi-bgrt.c
+++ b/arch/x86/platform/efi/efi-bgrt.c
@@ -40,20 +40,40 @@ void __init efi_bgrt_init(void)
40 if (ACPI_FAILURE(status)) 40 if (ACPI_FAILURE(status))
41 return; 41 return;
42 42
43 if (bgrt_tab->header.length < sizeof(*bgrt_tab)) 43 if (bgrt_tab->header.length < sizeof(*bgrt_tab)) {
44 pr_err("Ignoring BGRT: invalid length %u (expected %zu)\n",
45 bgrt_tab->header.length, sizeof(*bgrt_tab));
44 return; 46 return;
45 if (bgrt_tab->version != 1 || bgrt_tab->status != 1) 47 }
48 if (bgrt_tab->version != 1) {
49 pr_err("Ignoring BGRT: invalid version %u (expected 1)\n",
50 bgrt_tab->version);
51 return;
52 }
53 if (bgrt_tab->status != 1) {
54 pr_err("Ignoring BGRT: invalid status %u (expected 1)\n",
55 bgrt_tab->status);
56 return;
57 }
58 if (bgrt_tab->image_type != 0) {
59 pr_err("Ignoring BGRT: invalid image type %u (expected 0)\n",
60 bgrt_tab->image_type);
46 return; 61 return;
47 if (bgrt_tab->image_type != 0 || !bgrt_tab->image_address) 62 }
63 if (!bgrt_tab->image_address) {
64 pr_err("Ignoring BGRT: null image address\n");
48 return; 65 return;
66 }
49 67
50 image = efi_lookup_mapped_addr(bgrt_tab->image_address); 68 image = efi_lookup_mapped_addr(bgrt_tab->image_address);
51 if (!image) { 69 if (!image) {
52 image = early_memremap(bgrt_tab->image_address, 70 image = early_memremap(bgrt_tab->image_address,
53 sizeof(bmp_header)); 71 sizeof(bmp_header));
54 ioremapped = true; 72 ioremapped = true;
55 if (!image) 73 if (!image) {
74 pr_err("Ignoring BGRT: failed to map image header memory\n");
56 return; 75 return;
76 }
57 } 77 }
58 78
59 memcpy_fromio(&bmp_header, image, sizeof(bmp_header)); 79 memcpy_fromio(&bmp_header, image, sizeof(bmp_header));
@@ -61,14 +81,18 @@ void __init efi_bgrt_init(void)
61 early_iounmap(image, sizeof(bmp_header)); 81 early_iounmap(image, sizeof(bmp_header));
62 bgrt_image_size = bmp_header.size; 82 bgrt_image_size = bmp_header.size;
63 83
64 bgrt_image = kmalloc(bgrt_image_size, GFP_KERNEL); 84 bgrt_image = kmalloc(bgrt_image_size, GFP_KERNEL | __GFP_NOWARN);
65 if (!bgrt_image) 85 if (!bgrt_image) {
86 pr_err("Ignoring BGRT: failed to allocate memory for image (wanted %zu bytes)\n",
87 bgrt_image_size);
66 return; 88 return;
89 }
67 90
68 if (ioremapped) { 91 if (ioremapped) {
69 image = early_memremap(bgrt_tab->image_address, 92 image = early_memremap(bgrt_tab->image_address,
70 bmp_header.size); 93 bmp_header.size);
71 if (!image) { 94 if (!image) {
95 pr_err("Ignoring BGRT: failed to map image memory\n");
72 kfree(bgrt_image); 96 kfree(bgrt_image);
73 bgrt_image = NULL; 97 bgrt_image = NULL;
74 return; 98 return;
diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c
index 850da94fef30..dbc8627a5cdf 100644
--- a/arch/x86/platform/efi/efi.c
+++ b/arch/x86/platform/efi/efi.c
@@ -70,17 +70,7 @@ static efi_config_table_type_t arch_tables[] __initdata = {
70 70
71u64 efi_setup; /* efi setup_data physical address */ 71u64 efi_setup; /* efi setup_data physical address */
72 72
73static bool disable_runtime __initdata = false; 73static int add_efi_memmap __initdata;
74static int __init setup_noefi(char *arg)
75{
76 disable_runtime = true;
77 return 0;
78}
79early_param("noefi", setup_noefi);
80
81int add_efi_memmap;
82EXPORT_SYMBOL(add_efi_memmap);
83
84static int __init setup_add_efi_memmap(char *arg) 74static int __init setup_add_efi_memmap(char *arg)
85{ 75{
86 add_efi_memmap = 1; 76 add_efi_memmap = 1;
@@ -96,7 +86,7 @@ static efi_status_t __init phys_efi_set_virtual_address_map(
96{ 86{
97 efi_status_t status; 87 efi_status_t status;
98 88
99 efi_call_phys_prelog(); 89 efi_call_phys_prolog();
100 status = efi_call_phys(efi_phys.set_virtual_address_map, 90 status = efi_call_phys(efi_phys.set_virtual_address_map,
101 memory_map_size, descriptor_size, 91 memory_map_size, descriptor_size,
102 descriptor_version, virtual_map); 92 descriptor_version, virtual_map);
@@ -210,9 +200,12 @@ static void __init print_efi_memmap(void)
210 for (p = memmap.map, i = 0; 200 for (p = memmap.map, i = 0;
211 p < memmap.map_end; 201 p < memmap.map_end;
212 p += memmap.desc_size, i++) { 202 p += memmap.desc_size, i++) {
203 char buf[64];
204
213 md = p; 205 md = p;
214 pr_info("mem%02u: type=%u, attr=0x%llx, range=[0x%016llx-0x%016llx) (%lluMB)\n", 206 pr_info("mem%02u: %s range=[0x%016llx-0x%016llx) (%lluMB)\n",
215 i, md->type, md->attribute, md->phys_addr, 207 i, efi_md_typeattr_format(buf, sizeof(buf), md),
208 md->phys_addr,
216 md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT), 209 md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT),
217 (md->num_pages >> (20 - EFI_PAGE_SHIFT))); 210 (md->num_pages >> (20 - EFI_PAGE_SHIFT)));
218 } 211 }
@@ -344,9 +337,9 @@ static int __init efi_runtime_init32(void)
344 } 337 }
345 338
346 /* 339 /*
347 * We will only need *early* access to the following two 340 * We will only need *early* access to the SetVirtualAddressMap
348 * EFI runtime services before set_virtual_address_map 341 * EFI runtime service. All other runtime services will be called
349 * is invoked. 342 * via the virtual mapping.
350 */ 343 */
351 efi_phys.set_virtual_address_map = 344 efi_phys.set_virtual_address_map =
352 (efi_set_virtual_address_map_t *) 345 (efi_set_virtual_address_map_t *)
@@ -368,9 +361,9 @@ static int __init efi_runtime_init64(void)
368 } 361 }
369 362
370 /* 363 /*
371 * We will only need *early* access to the following two 364 * We will only need *early* access to the SetVirtualAddressMap
372 * EFI runtime services before set_virtual_address_map 365 * EFI runtime service. All other runtime services will be called
373 * is invoked. 366 * via the virtual mapping.
374 */ 367 */
375 efi_phys.set_virtual_address_map = 368 efi_phys.set_virtual_address_map =
376 (efi_set_virtual_address_map_t *) 369 (efi_set_virtual_address_map_t *)
@@ -492,7 +485,7 @@ void __init efi_init(void)
492 if (!efi_runtime_supported()) 485 if (!efi_runtime_supported())
493 pr_info("No EFI runtime due to 32/64-bit mismatch with kernel\n"); 486 pr_info("No EFI runtime due to 32/64-bit mismatch with kernel\n");
494 else { 487 else {
495 if (disable_runtime || efi_runtime_init()) 488 if (efi_runtime_disabled() || efi_runtime_init())
496 return; 489 return;
497 } 490 }
498 if (efi_memmap_init()) 491 if (efi_memmap_init())
@@ -537,7 +530,7 @@ void __init runtime_code_page_mkexec(void)
537 } 530 }
538} 531}
539 532
540void efi_memory_uc(u64 addr, unsigned long size) 533void __init efi_memory_uc(u64 addr, unsigned long size)
541{ 534{
542 unsigned long page_shift = 1UL << EFI_PAGE_SHIFT; 535 unsigned long page_shift = 1UL << EFI_PAGE_SHIFT;
543 u64 npages; 536 u64 npages;
@@ -732,6 +725,7 @@ static void __init kexec_enter_virtual_mode(void)
732 */ 725 */
733 if (!efi_is_native()) { 726 if (!efi_is_native()) {
734 efi_unmap_memmap(); 727 efi_unmap_memmap();
728 clear_bit(EFI_RUNTIME_SERVICES, &efi.flags);
735 return; 729 return;
736 } 730 }
737 731
@@ -805,6 +799,7 @@ static void __init __efi_enter_virtual_mode(void)
805 new_memmap = efi_map_regions(&count, &pg_shift); 799 new_memmap = efi_map_regions(&count, &pg_shift);
806 if (!new_memmap) { 800 if (!new_memmap) {
807 pr_err("Error reallocating memory, EFI runtime non-functional!\n"); 801 pr_err("Error reallocating memory, EFI runtime non-functional!\n");
802 clear_bit(EFI_RUNTIME_SERVICES, &efi.flags);
808 return; 803 return;
809 } 804 }
810 805
@@ -812,8 +807,10 @@ static void __init __efi_enter_virtual_mode(void)
812 807
813 BUG_ON(!efi.systab); 808 BUG_ON(!efi.systab);
814 809
815 if (efi_setup_page_tables(__pa(new_memmap), 1 << pg_shift)) 810 if (efi_setup_page_tables(__pa(new_memmap), 1 << pg_shift)) {
811 clear_bit(EFI_RUNTIME_SERVICES, &efi.flags);
816 return; 812 return;
813 }
817 814
818 efi_sync_low_kernel_mappings(); 815 efi_sync_low_kernel_mappings();
819 efi_dump_pagetable(); 816 efi_dump_pagetable();
@@ -938,14 +935,11 @@ u64 efi_mem_attributes(unsigned long phys_addr)
938 return 0; 935 return 0;
939} 936}
940 937
941static int __init parse_efi_cmdline(char *str) 938static int __init arch_parse_efi_cmdline(char *str)
942{ 939{
943 if (*str == '=') 940 if (parse_option_str(str, "old_map"))
944 str++;
945
946 if (!strncmp(str, "old_map", 7))
947 set_bit(EFI_OLD_MEMMAP, &efi.flags); 941 set_bit(EFI_OLD_MEMMAP, &efi.flags);
948 942
949 return 0; 943 return 0;
950} 944}
951early_param("efi", parse_efi_cmdline); 945early_param("efi", arch_parse_efi_cmdline);
diff --git a/arch/x86/platform/efi/efi_32.c b/arch/x86/platform/efi/efi_32.c
index 9ee3491e31fb..40e7cda52936 100644
--- a/arch/x86/platform/efi/efi_32.c
+++ b/arch/x86/platform/efi/efi_32.c
@@ -33,7 +33,7 @@
33 33
34/* 34/*
35 * To make EFI call EFI runtime service in physical addressing mode we need 35 * To make EFI call EFI runtime service in physical addressing mode we need
36 * prelog/epilog before/after the invocation to disable interrupt, to 36 * prolog/epilog before/after the invocation to disable interrupt, to
37 * claim EFI runtime service handler exclusively and to duplicate a memory in 37 * claim EFI runtime service handler exclusively and to duplicate a memory in
38 * low memory space say 0 - 3G. 38 * low memory space say 0 - 3G.
39 */ 39 */
@@ -41,11 +41,13 @@ static unsigned long efi_rt_eflags;
41 41
42void efi_sync_low_kernel_mappings(void) {} 42void efi_sync_low_kernel_mappings(void) {}
43void __init efi_dump_pagetable(void) {} 43void __init efi_dump_pagetable(void) {}
44int efi_setup_page_tables(unsigned long pa_memmap, unsigned num_pages) 44int __init efi_setup_page_tables(unsigned long pa_memmap, unsigned num_pages)
45{ 45{
46 return 0; 46 return 0;
47} 47}
48void efi_cleanup_page_tables(unsigned long pa_memmap, unsigned num_pages) {} 48void __init efi_cleanup_page_tables(unsigned long pa_memmap, unsigned num_pages)
49{
50}
49 51
50void __init efi_map_region(efi_memory_desc_t *md) 52void __init efi_map_region(efi_memory_desc_t *md)
51{ 53{
@@ -55,7 +57,7 @@ void __init efi_map_region(efi_memory_desc_t *md)
55void __init efi_map_region_fixed(efi_memory_desc_t *md) {} 57void __init efi_map_region_fixed(efi_memory_desc_t *md) {}
56void __init parse_efi_setup(u64 phys_addr, u32 data_len) {} 58void __init parse_efi_setup(u64 phys_addr, u32 data_len) {}
57 59
58void efi_call_phys_prelog(void) 60void __init efi_call_phys_prolog(void)
59{ 61{
60 struct desc_ptr gdt_descr; 62 struct desc_ptr gdt_descr;
61 63
@@ -69,7 +71,7 @@ void efi_call_phys_prelog(void)
69 load_gdt(&gdt_descr); 71 load_gdt(&gdt_descr);
70} 72}
71 73
72void efi_call_phys_epilog(void) 74void __init efi_call_phys_epilog(void)
73{ 75{
74 struct desc_ptr gdt_descr; 76 struct desc_ptr gdt_descr;
75 77
diff --git a/arch/x86/platform/efi/efi_64.c b/arch/x86/platform/efi/efi_64.c
index 290d397e1dd9..35aecb6042fb 100644
--- a/arch/x86/platform/efi/efi_64.c
+++ b/arch/x86/platform/efi/efi_64.c
@@ -79,7 +79,7 @@ static void __init early_code_mapping_set_exec(int executable)
79 } 79 }
80} 80}
81 81
82void __init efi_call_phys_prelog(void) 82void __init efi_call_phys_prolog(void)
83{ 83{
84 unsigned long vaddress; 84 unsigned long vaddress;
85 int pgd; 85 int pgd;
@@ -139,7 +139,7 @@ void efi_sync_low_kernel_mappings(void)
139 sizeof(pgd_t) * num_pgds); 139 sizeof(pgd_t) * num_pgds);
140} 140}
141 141
142int efi_setup_page_tables(unsigned long pa_memmap, unsigned num_pages) 142int __init efi_setup_page_tables(unsigned long pa_memmap, unsigned num_pages)
143{ 143{
144 unsigned long text; 144 unsigned long text;
145 struct page *page; 145 struct page *page;
@@ -192,7 +192,7 @@ int efi_setup_page_tables(unsigned long pa_memmap, unsigned num_pages)
192 return 0; 192 return 0;
193} 193}
194 194
195void efi_cleanup_page_tables(unsigned long pa_memmap, unsigned num_pages) 195void __init efi_cleanup_page_tables(unsigned long pa_memmap, unsigned num_pages)
196{ 196{
197 pgd_t *pgd = (pgd_t *)__va(real_mode_header->trampoline_pgd); 197 pgd_t *pgd = (pgd_t *)__va(real_mode_header->trampoline_pgd);
198 198
diff --git a/arch/x86/platform/efi/efi_stub_32.S b/arch/x86/platform/efi/efi_stub_32.S
index fbe66e626c09..040192b50d02 100644
--- a/arch/x86/platform/efi/efi_stub_32.S
+++ b/arch/x86/platform/efi/efi_stub_32.S
@@ -27,13 +27,13 @@ ENTRY(efi_call_phys)
27 * set to 0x0010, DS and SS have been set to 0x0018. In EFI, I found 27 * set to 0x0010, DS and SS have been set to 0x0018. In EFI, I found
28 * the values of these registers are the same. And, the corresponding 28 * the values of these registers are the same. And, the corresponding
29 * GDT entries are identical. So I will do nothing about segment reg 29 * GDT entries are identical. So I will do nothing about segment reg
30 * and GDT, but change GDT base register in prelog and epilog. 30 * and GDT, but change GDT base register in prolog and epilog.
31 */ 31 */
32 32
33 /* 33 /*
34 * 1. Now I am running with EIP = <physical address> + PAGE_OFFSET. 34 * 1. Now I am running with EIP = <physical address> + PAGE_OFFSET.
35 * But to make it smoothly switch from virtual mode to flat mode. 35 * But to make it smoothly switch from virtual mode to flat mode.
36 * The mapping of lower virtual memory has been created in prelog and 36 * The mapping of lower virtual memory has been created in prolog and
37 * epilog. 37 * epilog.
38 */ 38 */
39 movl $1f, %edx 39 movl $1f, %edx
diff --git a/arch/x86/platform/intel-mid/intel_mid_weak_decls.h b/arch/x86/platform/intel-mid/intel_mid_weak_decls.h
index 46aa25c8ce06..3c1c3866d82b 100644
--- a/arch/x86/platform/intel-mid/intel_mid_weak_decls.h
+++ b/arch/x86/platform/intel-mid/intel_mid_weak_decls.h
@@ -10,10 +10,9 @@
10 */ 10 */
11 11
12 12
13/* __attribute__((weak)) makes these declarations overridable */
14/* For every CPU addition a new get_<cpuname>_ops interface needs 13/* For every CPU addition a new get_<cpuname>_ops interface needs
15 * to be added. 14 * to be added.
16 */ 15 */
17extern void *get_penwell_ops(void) __attribute__((weak)); 16extern void *get_penwell_ops(void);
18extern void *get_cloverview_ops(void) __attribute__((weak)); 17extern void *get_cloverview_ops(void);
19extern void *get_tangier_ops(void) __attribute__((weak)); 18extern void *get_tangier_ops(void);
diff --git a/arch/x86/platform/intel-mid/sfi.c b/arch/x86/platform/intel-mid/sfi.c
index 3c53a90fdb18..c14ad34776c4 100644
--- a/arch/x86/platform/intel-mid/sfi.c
+++ b/arch/x86/platform/intel-mid/sfi.c
@@ -106,6 +106,7 @@ int __init sfi_parse_mtmr(struct sfi_table_header *table)
106 mp_irq.dstapic = MP_APIC_ALL; 106 mp_irq.dstapic = MP_APIC_ALL;
107 mp_irq.dstirq = pentry->irq; 107 mp_irq.dstirq = pentry->irq;
108 mp_save_irq(&mp_irq); 108 mp_save_irq(&mp_irq);
109 mp_map_gsi_to_irq(pentry->irq, IOAPIC_MAP_ALLOC);
109 } 110 }
110 111
111 return 0; 112 return 0;
@@ -176,6 +177,7 @@ int __init sfi_parse_mrtc(struct sfi_table_header *table)
176 mp_irq.dstapic = MP_APIC_ALL; 177 mp_irq.dstapic = MP_APIC_ALL;
177 mp_irq.dstirq = pentry->irq; 178 mp_irq.dstirq = pentry->irq;
178 mp_save_irq(&mp_irq); 179 mp_save_irq(&mp_irq);
180 mp_map_gsi_to_irq(pentry->irq, IOAPIC_MAP_ALLOC);
179 } 181 }
180 return 0; 182 return 0;
181} 183}
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 1a3f0445432a..fac5e4f9607c 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -1636,9 +1636,6 @@ asmlinkage __visible void __init xen_start_kernel(void)
1636 xen_raw_console_write("mapping kernel into physical memory\n"); 1636 xen_raw_console_write("mapping kernel into physical memory\n");
1637 xen_setup_kernel_pagetable((pgd_t *)xen_start_info->pt_base, xen_start_info->nr_pages); 1637 xen_setup_kernel_pagetable((pgd_t *)xen_start_info->pt_base, xen_start_info->nr_pages);
1638 1638
1639 /* Allocate and initialize top and mid mfn levels for p2m structure */
1640 xen_build_mfn_list_list();
1641
1642 /* keep using Xen gdt for now; no urgent need to change it */ 1639 /* keep using Xen gdt for now; no urgent need to change it */
1643 1640
1644#ifdef CONFIG_X86_32 1641#ifdef CONFIG_X86_32
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index f62af7647ec9..a8a1a3d08d4d 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -1217,10 +1217,13 @@ static void __init xen_pagetable_p2m_copy(void)
1217static void __init xen_pagetable_init(void) 1217static void __init xen_pagetable_init(void)
1218{ 1218{
1219 paging_init(); 1219 paging_init();
1220 xen_setup_shared_info();
1221#ifdef CONFIG_X86_64 1220#ifdef CONFIG_X86_64
1222 xen_pagetable_p2m_copy(); 1221 xen_pagetable_p2m_copy();
1223#endif 1222#endif
1223 /* Allocate and initialize top and mid mfn levels for p2m structure */
1224 xen_build_mfn_list_list();
1225
1226 xen_setup_shared_info();
1224 xen_post_allocator_init(); 1227 xen_post_allocator_init();
1225} 1228}
1226static void xen_write_cr2(unsigned long cr2) 1229static void xen_write_cr2(unsigned long cr2)
diff --git a/arch/x86/xen/p2m.c b/arch/x86/xen/p2m.c
index 9f5983b01ed9..b456b048eca9 100644
--- a/arch/x86/xen/p2m.c
+++ b/arch/x86/xen/p2m.c
@@ -163,6 +163,7 @@
163#include <linux/hash.h> 163#include <linux/hash.h>
164#include <linux/sched.h> 164#include <linux/sched.h>
165#include <linux/seq_file.h> 165#include <linux/seq_file.h>
166#include <linux/bootmem.h>
166 167
167#include <asm/cache.h> 168#include <asm/cache.h>
168#include <asm/setup.h> 169#include <asm/setup.h>
@@ -181,21 +182,20 @@ static void __init m2p_override_init(void);
181 182
182unsigned long xen_max_p2m_pfn __read_mostly; 183unsigned long xen_max_p2m_pfn __read_mostly;
183 184
185static unsigned long *p2m_mid_missing_mfn;
186static unsigned long *p2m_top_mfn;
187static unsigned long **p2m_top_mfn_p;
188
184/* Placeholders for holes in the address space */ 189/* Placeholders for holes in the address space */
185static RESERVE_BRK_ARRAY(unsigned long, p2m_missing, P2M_PER_PAGE); 190static RESERVE_BRK_ARRAY(unsigned long, p2m_missing, P2M_PER_PAGE);
186static RESERVE_BRK_ARRAY(unsigned long *, p2m_mid_missing, P2M_MID_PER_PAGE); 191static RESERVE_BRK_ARRAY(unsigned long *, p2m_mid_missing, P2M_MID_PER_PAGE);
187static RESERVE_BRK_ARRAY(unsigned long, p2m_mid_missing_mfn, P2M_MID_PER_PAGE);
188 192
189static RESERVE_BRK_ARRAY(unsigned long **, p2m_top, P2M_TOP_PER_PAGE); 193static RESERVE_BRK_ARRAY(unsigned long **, p2m_top, P2M_TOP_PER_PAGE);
190static RESERVE_BRK_ARRAY(unsigned long, p2m_top_mfn, P2M_TOP_PER_PAGE);
191static RESERVE_BRK_ARRAY(unsigned long *, p2m_top_mfn_p, P2M_TOP_PER_PAGE);
192 194
193static RESERVE_BRK_ARRAY(unsigned long, p2m_identity, P2M_PER_PAGE); 195static RESERVE_BRK_ARRAY(unsigned long, p2m_identity, P2M_PER_PAGE);
194static RESERVE_BRK_ARRAY(unsigned long *, p2m_mid_identity, P2M_MID_PER_PAGE); 196static RESERVE_BRK_ARRAY(unsigned long *, p2m_mid_identity, P2M_MID_PER_PAGE);
195static RESERVE_BRK_ARRAY(unsigned long, p2m_mid_identity_mfn, P2M_MID_PER_PAGE);
196 197
197RESERVE_BRK(p2m_mid, PAGE_SIZE * (MAX_DOMAIN_PAGES / (P2M_PER_PAGE * P2M_MID_PER_PAGE))); 198RESERVE_BRK(p2m_mid, PAGE_SIZE * (MAX_DOMAIN_PAGES / (P2M_PER_PAGE * P2M_MID_PER_PAGE)));
198RESERVE_BRK(p2m_mid_mfn, PAGE_SIZE * (MAX_DOMAIN_PAGES / (P2M_PER_PAGE * P2M_MID_PER_PAGE)));
199 199
200/* For each I/O range remapped we may lose up to two leaf pages for the boundary 200/* For each I/O range remapped we may lose up to two leaf pages for the boundary
201 * violations and three mid pages to cover up to 3GB. With 201 * violations and three mid pages to cover up to 3GB. With
@@ -272,11 +272,11 @@ static void p2m_init(unsigned long *p2m)
272 * Build the parallel p2m_top_mfn and p2m_mid_mfn structures 272 * Build the parallel p2m_top_mfn and p2m_mid_mfn structures
273 * 273 *
274 * This is called both at boot time, and after resuming from suspend: 274 * This is called both at boot time, and after resuming from suspend:
275 * - At boot time we're called very early, and must use extend_brk() 275 * - At boot time we're called rather early, and must use alloc_bootmem*()
276 * to allocate memory. 276 * to allocate memory.
277 * 277 *
278 * - After resume we're called from within stop_machine, but the mfn 278 * - After resume we're called from within stop_machine, but the mfn
279 * tree should alreay be completely allocated. 279 * tree should already be completely allocated.
280 */ 280 */
281void __ref xen_build_mfn_list_list(void) 281void __ref xen_build_mfn_list_list(void)
282{ 282{
@@ -287,20 +287,17 @@ void __ref xen_build_mfn_list_list(void)
287 287
288 /* Pre-initialize p2m_top_mfn to be completely missing */ 288 /* Pre-initialize p2m_top_mfn to be completely missing */
289 if (p2m_top_mfn == NULL) { 289 if (p2m_top_mfn == NULL) {
290 p2m_mid_missing_mfn = extend_brk(PAGE_SIZE, PAGE_SIZE); 290 p2m_mid_missing_mfn = alloc_bootmem_align(PAGE_SIZE, PAGE_SIZE);
291 p2m_mid_mfn_init(p2m_mid_missing_mfn, p2m_missing); 291 p2m_mid_mfn_init(p2m_mid_missing_mfn, p2m_missing);
292 p2m_mid_identity_mfn = extend_brk(PAGE_SIZE, PAGE_SIZE);
293 p2m_mid_mfn_init(p2m_mid_identity_mfn, p2m_identity);
294 292
295 p2m_top_mfn_p = extend_brk(PAGE_SIZE, PAGE_SIZE); 293 p2m_top_mfn_p = alloc_bootmem_align(PAGE_SIZE, PAGE_SIZE);
296 p2m_top_mfn_p_init(p2m_top_mfn_p); 294 p2m_top_mfn_p_init(p2m_top_mfn_p);
297 295
298 p2m_top_mfn = extend_brk(PAGE_SIZE, PAGE_SIZE); 296 p2m_top_mfn = alloc_bootmem_align(PAGE_SIZE, PAGE_SIZE);
299 p2m_top_mfn_init(p2m_top_mfn); 297 p2m_top_mfn_init(p2m_top_mfn);
300 } else { 298 } else {
301 /* Reinitialise, mfn's all change after migration */ 299 /* Reinitialise, mfn's all change after migration */
302 p2m_mid_mfn_init(p2m_mid_missing_mfn, p2m_missing); 300 p2m_mid_mfn_init(p2m_mid_missing_mfn, p2m_missing);
303 p2m_mid_mfn_init(p2m_mid_identity_mfn, p2m_identity);
304 } 301 }
305 302
306 for (pfn = 0; pfn < xen_max_p2m_pfn; pfn += P2M_PER_PAGE) { 303 for (pfn = 0; pfn < xen_max_p2m_pfn; pfn += P2M_PER_PAGE) {
@@ -328,10 +325,9 @@ void __ref xen_build_mfn_list_list(void)
328 /* 325 /*
329 * XXX boot-time only! We should never find 326 * XXX boot-time only! We should never find
330 * missing parts of the mfn tree after 327 * missing parts of the mfn tree after
331 * runtime. extend_brk() will BUG if we call 328 * runtime.
332 * it too late.
333 */ 329 */
334 mid_mfn_p = extend_brk(PAGE_SIZE, PAGE_SIZE); 330 mid_mfn_p = alloc_bootmem_align(PAGE_SIZE, PAGE_SIZE);
335 p2m_mid_mfn_init(mid_mfn_p, p2m_missing); 331 p2m_mid_mfn_init(mid_mfn_p, p2m_missing);
336 332
337 p2m_top_mfn_p[topidx] = mid_mfn_p; 333 p2m_top_mfn_p[topidx] = mid_mfn_p;
@@ -415,7 +411,6 @@ void __init xen_build_dynamic_phys_to_machine(void)
415 m2p_override_init(); 411 m2p_override_init();
416} 412}
417#ifdef CONFIG_X86_64 413#ifdef CONFIG_X86_64
418#include <linux/bootmem.h>
419unsigned long __init xen_revector_p2m_tree(void) 414unsigned long __init xen_revector_p2m_tree(void)
420{ 415{
421 unsigned long va_start; 416 unsigned long va_start;
@@ -477,7 +472,6 @@ unsigned long __init xen_revector_p2m_tree(void)
477 472
478 copy_page(new, mid_p); 473 copy_page(new, mid_p);
479 p2m_top[topidx][mididx] = &mfn_list[pfn_free]; 474 p2m_top[topidx][mididx] = &mfn_list[pfn_free];
480 p2m_top_mfn_p[topidx][mididx] = virt_to_mfn(&mfn_list[pfn_free]);
481 475
482 pfn_free += P2M_PER_PAGE; 476 pfn_free += P2M_PER_PAGE;
483 477
@@ -538,12 +532,13 @@ static bool alloc_p2m(unsigned long pfn)
538 unsigned topidx, mididx; 532 unsigned topidx, mididx;
539 unsigned long ***top_p, **mid; 533 unsigned long ***top_p, **mid;
540 unsigned long *top_mfn_p, *mid_mfn; 534 unsigned long *top_mfn_p, *mid_mfn;
535 unsigned long *p2m_orig;
541 536
542 topidx = p2m_top_index(pfn); 537 topidx = p2m_top_index(pfn);
543 mididx = p2m_mid_index(pfn); 538 mididx = p2m_mid_index(pfn);
544 539
545 top_p = &p2m_top[topidx]; 540 top_p = &p2m_top[topidx];
546 mid = *top_p; 541 mid = ACCESS_ONCE(*top_p);
547 542
548 if (mid == p2m_mid_missing) { 543 if (mid == p2m_mid_missing) {
549 /* Mid level is missing, allocate a new one */ 544 /* Mid level is missing, allocate a new one */
@@ -558,7 +553,7 @@ static bool alloc_p2m(unsigned long pfn)
558 } 553 }
559 554
560 top_mfn_p = &p2m_top_mfn[topidx]; 555 top_mfn_p = &p2m_top_mfn[topidx];
561 mid_mfn = p2m_top_mfn_p[topidx]; 556 mid_mfn = ACCESS_ONCE(p2m_top_mfn_p[topidx]);
562 557
563 BUG_ON(virt_to_mfn(mid_mfn) != *top_mfn_p); 558 BUG_ON(virt_to_mfn(mid_mfn) != *top_mfn_p);
564 559
@@ -566,6 +561,7 @@ static bool alloc_p2m(unsigned long pfn)
566 /* Separately check the mid mfn level */ 561 /* Separately check the mid mfn level */
567 unsigned long missing_mfn; 562 unsigned long missing_mfn;
568 unsigned long mid_mfn_mfn; 563 unsigned long mid_mfn_mfn;
564 unsigned long old_mfn;
569 565
570 mid_mfn = alloc_p2m_page(); 566 mid_mfn = alloc_p2m_page();
571 if (!mid_mfn) 567 if (!mid_mfn)
@@ -575,17 +571,19 @@ static bool alloc_p2m(unsigned long pfn)
575 571
576 missing_mfn = virt_to_mfn(p2m_mid_missing_mfn); 572 missing_mfn = virt_to_mfn(p2m_mid_missing_mfn);
577 mid_mfn_mfn = virt_to_mfn(mid_mfn); 573 mid_mfn_mfn = virt_to_mfn(mid_mfn);
578 if (cmpxchg(top_mfn_p, missing_mfn, mid_mfn_mfn) != missing_mfn) 574 old_mfn = cmpxchg(top_mfn_p, missing_mfn, mid_mfn_mfn);
575 if (old_mfn != missing_mfn) {
579 free_p2m_page(mid_mfn); 576 free_p2m_page(mid_mfn);
580 else 577 mid_mfn = mfn_to_virt(old_mfn);
578 } else {
581 p2m_top_mfn_p[topidx] = mid_mfn; 579 p2m_top_mfn_p[topidx] = mid_mfn;
580 }
582 } 581 }
583 582
584 if (p2m_top[topidx][mididx] == p2m_identity || 583 p2m_orig = ACCESS_ONCE(p2m_top[topidx][mididx]);
585 p2m_top[topidx][mididx] == p2m_missing) { 584 if (p2m_orig == p2m_identity || p2m_orig == p2m_missing) {
586 /* p2m leaf page is missing */ 585 /* p2m leaf page is missing */
587 unsigned long *p2m; 586 unsigned long *p2m;
588 unsigned long *p2m_orig = p2m_top[topidx][mididx];
589 587
590 p2m = alloc_p2m_page(); 588 p2m = alloc_p2m_page();
591 if (!p2m) 589 if (!p2m)
@@ -606,7 +604,6 @@ static bool __init early_alloc_p2m(unsigned long pfn, bool check_boundary)
606{ 604{
607 unsigned topidx, mididx, idx; 605 unsigned topidx, mididx, idx;
608 unsigned long *p2m; 606 unsigned long *p2m;
609 unsigned long *mid_mfn_p;
610 607
611 topidx = p2m_top_index(pfn); 608 topidx = p2m_top_index(pfn);
612 mididx = p2m_mid_index(pfn); 609 mididx = p2m_mid_index(pfn);
@@ -633,43 +630,21 @@ static bool __init early_alloc_p2m(unsigned long pfn, bool check_boundary)
633 630
634 p2m_top[topidx][mididx] = p2m; 631 p2m_top[topidx][mididx] = p2m;
635 632
636 /* For save/restore we need to MFN of the P2M saved */
637
638 mid_mfn_p = p2m_top_mfn_p[topidx];
639 WARN(mid_mfn_p[mididx] != virt_to_mfn(p2m_missing),
640 "P2M_TOP_P[%d][%d] != MFN of p2m_missing!\n",
641 topidx, mididx);
642 mid_mfn_p[mididx] = virt_to_mfn(p2m);
643
644 return true; 633 return true;
645} 634}
646 635
647static bool __init early_alloc_p2m_middle(unsigned long pfn) 636static bool __init early_alloc_p2m_middle(unsigned long pfn)
648{ 637{
649 unsigned topidx = p2m_top_index(pfn); 638 unsigned topidx = p2m_top_index(pfn);
650 unsigned long *mid_mfn_p;
651 unsigned long **mid; 639 unsigned long **mid;
652 640
653 mid = p2m_top[topidx]; 641 mid = p2m_top[topidx];
654 mid_mfn_p = p2m_top_mfn_p[topidx];
655 if (mid == p2m_mid_missing) { 642 if (mid == p2m_mid_missing) {
656 mid = extend_brk(PAGE_SIZE, PAGE_SIZE); 643 mid = extend_brk(PAGE_SIZE, PAGE_SIZE);
657 644
658 p2m_mid_init(mid, p2m_missing); 645 p2m_mid_init(mid, p2m_missing);
659 646
660 p2m_top[topidx] = mid; 647 p2m_top[topidx] = mid;
661
662 BUG_ON(mid_mfn_p != p2m_mid_missing_mfn);
663 }
664 /* And the save/restore P2M tables.. */
665 if (mid_mfn_p == p2m_mid_missing_mfn) {
666 mid_mfn_p = extend_brk(PAGE_SIZE, PAGE_SIZE);
667 p2m_mid_mfn_init(mid_mfn_p, p2m_missing);
668
669 p2m_top_mfn_p[topidx] = mid_mfn_p;
670 p2m_top_mfn[topidx] = virt_to_mfn(mid_mfn_p);
671 /* Note: we don't set mid_mfn_p[midix] here,
672 * look in early_alloc_p2m() */
673 } 648 }
674 return true; 649 return true;
675} 650}
@@ -680,14 +655,13 @@ static bool __init early_alloc_p2m_middle(unsigned long pfn)
680 * replace the P2M leaf with a p2m_missing or p2m_identity. 655 * replace the P2M leaf with a p2m_missing or p2m_identity.
681 * Stick the old page in the new P2M tree location. 656 * Stick the old page in the new P2M tree location.
682 */ 657 */
683bool __init early_can_reuse_p2m_middle(unsigned long set_pfn, unsigned long set_mfn) 658static bool __init early_can_reuse_p2m_middle(unsigned long set_pfn)
684{ 659{
685 unsigned topidx; 660 unsigned topidx;
686 unsigned mididx; 661 unsigned mididx;
687 unsigned ident_pfns; 662 unsigned ident_pfns;
688 unsigned inv_pfns; 663 unsigned inv_pfns;
689 unsigned long *p2m; 664 unsigned long *p2m;
690 unsigned long *mid_mfn_p;
691 unsigned idx; 665 unsigned idx;
692 unsigned long pfn; 666 unsigned long pfn;
693 667
@@ -733,11 +707,6 @@ bool __init early_can_reuse_p2m_middle(unsigned long set_pfn, unsigned long set_
733found: 707found:
734 /* Found one, replace old with p2m_identity or p2m_missing */ 708 /* Found one, replace old with p2m_identity or p2m_missing */
735 p2m_top[topidx][mididx] = (ident_pfns ? p2m_identity : p2m_missing); 709 p2m_top[topidx][mididx] = (ident_pfns ? p2m_identity : p2m_missing);
736 /* And the other for save/restore.. */
737 mid_mfn_p = p2m_top_mfn_p[topidx];
738 /* NOTE: Even if it is a p2m_identity it should still be point to
739 * a page filled with INVALID_P2M_ENTRY entries. */
740 mid_mfn_p[mididx] = virt_to_mfn(p2m_missing);
741 710
742 /* Reset where we want to stick the old page in. */ 711 /* Reset where we want to stick the old page in. */
743 topidx = p2m_top_index(set_pfn); 712 topidx = p2m_top_index(set_pfn);
@@ -752,8 +721,6 @@ found:
752 721
753 p2m_init(p2m); 722 p2m_init(p2m);
754 p2m_top[topidx][mididx] = p2m; 723 p2m_top[topidx][mididx] = p2m;
755 mid_mfn_p = p2m_top_mfn_p[topidx];
756 mid_mfn_p[mididx] = virt_to_mfn(p2m);
757 724
758 return true; 725 return true;
759} 726}
@@ -763,7 +730,7 @@ bool __init early_set_phys_to_machine(unsigned long pfn, unsigned long mfn)
763 if (!early_alloc_p2m_middle(pfn)) 730 if (!early_alloc_p2m_middle(pfn))
764 return false; 731 return false;
765 732
766 if (early_can_reuse_p2m_middle(pfn, mfn)) 733 if (early_can_reuse_p2m_middle(pfn))
767 return __set_phys_to_machine(pfn, mfn); 734 return __set_phys_to_machine(pfn, mfn);
768 735
769 if (!early_alloc_p2m(pfn, false /* boundary crossover OK!*/)) 736 if (!early_alloc_p2m(pfn, false /* boundary crossover OK!*/))
diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c
index af7216128d93..29834b3fd87f 100644
--- a/arch/x86/xen/setup.c
+++ b/arch/x86/xen/setup.c
@@ -595,6 +595,7 @@ char * __init xen_memory_setup(void)
595 rc = 0; 595 rc = 0;
596 } 596 }
597 BUG_ON(rc); 597 BUG_ON(rc);
598 BUG_ON(memmap.nr_entries == 0);
598 599
599 /* 600 /*
600 * Xen won't allow a 1:1 mapping to be created to UNUSABLE 601 * Xen won't allow a 1:1 mapping to be created to UNUSABLE
diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
index a1d430b112b3..f473d268d387 100644
--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
@@ -158,7 +158,7 @@ cycle_t xen_clocksource_read(void)
158 cycle_t ret; 158 cycle_t ret;
159 159
160 preempt_disable_notrace(); 160 preempt_disable_notrace();
161 src = this_cpu_ptr(&xen_vcpu->time); 161 src = &__this_cpu_read(xen_vcpu)->time;
162 ret = pvclock_clocksource_read(src); 162 ret = pvclock_clocksource_read(src);
163 preempt_enable_notrace(); 163 preempt_enable_notrace();
164 return ret; 164 return ret;
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-06 22:32:57 -0500