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-rw-r--r--arch/arm/include/asm/hardware/pl080.h138
-rw-r--r--arch/arm/mach-s3c2410/dma.c4
-rw-r--r--arch/arm/mach-s3c2410/include/mach/dma.h265
-rw-r--r--arch/arm/mach-s3c2412/dma.c3
-rw-r--r--arch/arm/mach-s3c2440/dma.c4
-rw-r--r--arch/arm/mach-s3c2443/dma.c3
-rw-r--r--arch/arm/mach-s3c6400/include/mach/dma.h59
-rw-r--r--arch/arm/plat-s3c/Kconfig7
-rw-r--r--arch/arm/plat-s3c/Makefile4
-rw-r--r--arch/arm/plat-s3c/dma.c86
-rw-r--r--arch/arm/plat-s3c/include/plat/dma-core.h22
-rw-r--r--arch/arm/plat-s3c/include/plat/dma.h127
-rw-r--r--arch/arm/plat-s3c24xx/Kconfig1
-rw-r--r--arch/arm/plat-s3c24xx/dma.c151
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/dma-plat.h (renamed from arch/arm/plat-s3c24xx/include/plat/dma.h)12
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/regs-dma.h145
-rw-r--r--arch/arm/plat-s3c64xx/Kconfig4
-rw-r--r--arch/arm/plat-s3c64xx/Makefile4
-rw-r--r--arch/arm/plat-s3c64xx/dma.c722
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/dma-plat.h70
20 files changed, 1468 insertions, 363 deletions
diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h
new file mode 100644
index 000000000000..6a6c66be7f65
--- /dev/null
+++ b/arch/arm/include/asm/hardware/pl080.h
@@ -0,0 +1,138 @@
1/* arch/arm/include/asm/hardware/pl080.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * ARM PrimeCell PL080 DMA controller
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* Note, there are some Samsung updates to this controller block which
16 * make it not entierly compatible with the PL080 specification from
17 * ARM. When in doubt, check the Samsung documentation first.
18 *
19 * The Samsung defines are PL080S, and add an extra controll register,
20 * the ability to move more than 2^11 counts of data and some extra
21 * OneNAND features.
22*/
23
24#define PL080_INT_STATUS (0x00)
25#define PL080_TC_STATUS (0x04)
26#define PL080_TC_CLEAR (0x08)
27#define PL080_ERR_STATUS (0x0C)
28#define PL080_ERR_CLEAR (0x10)
29#define PL080_RAW_TC_STATUS (0x14)
30#define PL080_RAW_ERR_STATUS (0x18)
31#define PL080_EN_CHAN (0x1c)
32#define PL080_SOFT_BREQ (0x20)
33#define PL080_SOFT_SREQ (0x24)
34#define PL080_SOFT_LBREQ (0x28)
35#define PL080_SOFT_LSREQ (0x2C)
36
37#define PL080_CONFIG (0x30)
38#define PL080_CONFIG_M2_BE (1 << 2)
39#define PL080_CONFIG_M1_BE (1 << 1)
40#define PL080_CONFIG_ENABLE (1 << 0)
41
42#define PL080_SYNC (0x34)
43
44/* Per channel configuration registers */
45
46#define PL008_Cx_STRIDE (0x20)
47#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20)))
48#define PL080_Cx_SRC_ADDR(x) ((0x100 + (x * 0x20)))
49#define PL080_Cx_DST_ADDR(x) ((0x104 + (x * 0x20)))
50#define PL080_Cx_LLI(x) ((0x108 + (x * 0x20)))
51#define PL080_Cx_CONTROL(x) ((0x10C + (x * 0x20)))
52#define PL080_Cx_CONFIG(x) ((0x110 + (x * 0x20)))
53#define PL080S_Cx_CONTROL2(x) ((0x110 + (x * 0x20)))
54#define PL080S_Cx_CONFIG(x) ((0x114 + (x * 0x20)))
55
56#define PL080_CH_SRC_ADDR (0x00)
57#define PL080_CH_DST_ADDR (0x04)
58#define PL080_CH_LLI (0x08)
59#define PL080_CH_CONTROL (0x0C)
60#define PL080_CH_CONFIG (0x10)
61#define PL080S_CH_CONTROL2 (0x10)
62#define PL080S_CH_CONFIG (0x14)
63
64#define PL080_LLI_ADDR_MASK (0x3fffffff << 2)
65#define PL080_LLI_ADDR_SHIFT (2)
66#define PL080_LLI_LM_AHB2 (1 << 0)
67
68#define PL080_CONTROL_TC_IRQ_EN (1 << 31)
69#define PL080_CONTROL_PROT_MASK (0x7 << 28)
70#define PL080_CONTROL_PROT_SHIFT (28)
71#define PL080_CONTROL_PROT_SYS (1 << 28)
72#define PL080_CONTROL_DST_INCR (1 << 27)
73#define PL080_CONTROL_SRC_INCR (1 << 26)
74#define PL080_CONTROL_DST_AHB2 (1 << 25)
75#define PL080_CONTROL_SRC_AHB2 (1 << 24)
76#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21)
77#define PL080_CONTROL_DWIDTH_SHIFT (21)
78#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18)
79#define PL080_CONTROL_SWIDTH_SHIFT (18)
80#define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15)
81#define PL080_CONTROL_DB_SIZE_SHIFT (15)
82#define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12)
83#define PL080_CONTROL_SB_SIZE_SHIFT (12)
84#define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0)
85#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0)
86
87#define PL080_BSIZE_1 (0x0)
88#define PL080_BSIZE_4 (0x1)
89#define PL080_BSIZE_8 (0x2)
90#define PL080_BSIZE_16 (0x3)
91#define PL080_BSIZE_32 (0x4)
92#define PL080_BSIZE_64 (0x5)
93#define PL080_BSIZE_128 (0x6)
94#define PL080_BSIZE_256 (0x7)
95
96#define PL080_WIDTH_8BIT (0x0)
97#define PL080_WIDTH_16BIT (0x1)
98#define PL080_WIDTH_32BIT (0x2)
99
100#define PL080_CONFIG_HALT (1 << 18)
101#define PL080_CONFIG_ACTIVE (1 << 17) /* RO */
102#define PL080_CONFIG_LOCK (1 << 16)
103#define PL080_CONFIG_TC_IRQ_MASK (1 << 15)
104#define PL080_CONFIG_ERR_IRQ_MASK (1 << 14)
105#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11)
106#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11)
107#define PL080_CONFIG_DST_SEL_MASK (0xf << 6)
108#define PL080_CONFIG_DST_SEL_SHIFT (6)
109#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1)
110#define PL080_CONFIG_SRC_SEL_SHIFT (1)
111#define PL080_CONFIG_ENABLE (1 << 0)
112
113#define PL080_FLOW_MEM2MEM (0x0)
114#define PL080_FLOW_MEM2PER (0x1)
115#define PL080_FLOW_PER2MEM (0x2)
116#define PL080_FLOW_SRC2DST (0x3)
117#define PL080_FLOW_SRC2DST_DST (0x4)
118#define PL080_FLOW_MEM2PER_PER (0x5)
119#define PL080_FLOW_PER2MEM_PER (0x6)
120#define PL080_FLOW_SRC2DST_SRC (0x7)
121
122/* DMA linked list chain structure */
123
124struct pl080_lli {
125 u32 src_addr;
126 u32 dst_addr;
127 u32 next_lli;
128 u32 control0;
129};
130
131struct pl080s_lli {
132 u32 src_addr;
133 u32 dst_addr;
134 u32 next_lli;
135 u32 control0;
136 u32 control1;
137};
138
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 440c014e24b3..dbf96e60d992 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -17,14 +17,16 @@
17#include <linux/sysdev.h> 17#include <linux/sysdev.h>
18#include <linux/serial_core.h> 18#include <linux/serial_core.h>
19 19
20#include <mach/map.h>
20#include <mach/dma.h> 21#include <mach/dma.h>
21 22
22#include <plat/cpu.h> 23#include <plat/cpu.h>
23#include <plat/dma.h> 24#include <plat/dma-plat.h>
24 25
25#include <plat/regs-serial.h> 26#include <plat/regs-serial.h>
26#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
27#include <plat/regs-ac97.h> 28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h>
28#include <mach/regs-mem.h> 30#include <mach/regs-mem.h>
29#include <mach/regs-lcd.h> 31#include <mach/regs-lcd.h>
30#include <mach/regs-sdi.h> 32#include <mach/regs-sdi.h>
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h
index 13358ce2128c..c3a2629e0ded 100644
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ b/arch/arm/mach-s3c2410/include/mach/dma.h
@@ -3,7 +3,7 @@
3 * Copyright (C) 2003,2004,2006 Simtec Electronics 3 * Copyright (C) 2003,2004,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
5 * 5 *
6 * Samsung S3C241XX DMA support 6 * Samsung S3C24XX DMA support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -13,8 +13,8 @@
13#ifndef __ASM_ARCH_DMA_H 13#ifndef __ASM_ARCH_DMA_H
14#define __ASM_ARCH_DMA_H __FILE__ 14#define __ASM_ARCH_DMA_H __FILE__
15 15
16#include <plat/dma.h>
16#include <linux/sysdev.h> 17#include <linux/sysdev.h>
17#include <mach/hardware.h>
18 18
19#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ 19#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
20 20
@@ -55,9 +55,9 @@ enum dma_ch {
55 55
56/* we have 4 dma channels */ 56/* we have 4 dma channels */
57#ifndef CONFIG_CPU_S3C2443 57#ifndef CONFIG_CPU_S3C2443
58#define S3C2410_DMA_CHANNELS (4) 58#define S3C_DMA_CHANNELS (4)
59#else 59#else
60#define S3C2410_DMA_CHANNELS (6) 60#define S3C_DMA_CHANNELS (6)
61#endif 61#endif
62 62
63/* types */ 63/* types */
@@ -68,7 +68,6 @@ enum s3c2410_dma_state {
68 S3C2410_DMA_PAUSED 68 S3C2410_DMA_PAUSED
69}; 69};
70 70
71
72/* enum s3c2410_dma_loadst 71/* enum s3c2410_dma_loadst
73 * 72 *
74 * This represents the state of the DMA engine, wrt to the loaded / running 73 * This represents the state of the DMA engine, wrt to the loaded / running
@@ -104,32 +103,6 @@ enum s3c2410_dma_loadst {
104 S3C2410_DMALOAD_1LOADED_1RUNNING, 103 S3C2410_DMALOAD_1LOADED_1RUNNING,
105}; 104};
106 105
107enum s3c2410_dma_buffresult {
108 S3C2410_RES_OK,
109 S3C2410_RES_ERR,
110 S3C2410_RES_ABORT
111};
112
113enum s3c2410_dmasrc {
114 S3C2410_DMASRC_HW, /* source is memory */
115 S3C2410_DMASRC_MEM /* source is hardware */
116};
117
118/* enum s3c2410_chan_op
119 *
120 * operation codes passed to the DMA code by the user, and also used
121 * to inform the current channel owner of any changes to the system state
122*/
123
124enum s3c2410_chan_op {
125 S3C2410_DMAOP_START,
126 S3C2410_DMAOP_STOP,
127 S3C2410_DMAOP_PAUSE,
128 S3C2410_DMAOP_RESUME,
129 S3C2410_DMAOP_FLUSH,
130 S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
131 S3C2410_DMAOP_STARTED, /* indicate channel started */
132};
133 106
134/* flags */ 107/* flags */
135 108
@@ -139,17 +112,14 @@ enum s3c2410_chan_op {
139 112
140/* dma buffer */ 113/* dma buffer */
141 114
142struct s3c2410_dma_client { 115struct s3c2410_dma_buf;
143 char *name;
144};
145 116
146/* s3c2410_dma_buf_s 117/* s3c2410_dma_buf
147 * 118 *
148 * internally used buffer structure to describe a queued or running 119 * internally used buffer structure to describe a queued or running
149 * buffer. 120 * buffer.
150*/ 121*/
151 122
152struct s3c2410_dma_buf;
153struct s3c2410_dma_buf { 123struct s3c2410_dma_buf {
154 struct s3c2410_dma_buf *next; 124 struct s3c2410_dma_buf *next;
155 int magic; /* magic */ 125 int magic; /* magic */
@@ -161,20 +131,6 @@ struct s3c2410_dma_buf {
161 131
162/* [1] is this updated for both recv/send modes? */ 132/* [1] is this updated for both recv/send modes? */
163 133
164struct s3c2410_dma_chan;
165
166/* s3c2410_dma_cbfn_t
167 *
168 * buffer callback routine type
169*/
170
171typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
172 void *buf, int size,
173 enum s3c2410_dma_buffresult result);
174
175typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
176 enum s3c2410_chan_op );
177
178struct s3c2410_dma_stats { 134struct s3c2410_dma_stats {
179 unsigned long loads; 135 unsigned long loads;
180 unsigned long timeout_longest; 136 unsigned long timeout_longest;
@@ -206,10 +162,10 @@ struct s3c2410_dma_chan {
206 162
207 /* channel configuration */ 163 /* channel configuration */
208 enum s3c2410_dmasrc source; 164 enum s3c2410_dmasrc source;
165 enum dma_ch req_ch;
209 unsigned long dev_addr; 166 unsigned long dev_addr;
210 unsigned long load_timeout; 167 unsigned long load_timeout;
211 unsigned int flags; /* channel flags */ 168 unsigned int flags; /* channel flags */
212 unsigned int hw_cfg; /* last hw config */
213 169
214 struct s3c24xx_dma_map *map; /* channel hw maps */ 170 struct s3c24xx_dma_map *map; /* channel hw maps */
215 171
@@ -236,213 +192,6 @@ struct s3c2410_dma_chan {
236 struct sys_device dev; 192 struct sys_device dev;
237}; 193};
238 194
239/* the currently allocated channel information */
240extern struct s3c2410_dma_chan s3c2410_chans[];
241
242/* note, we don't really use dma_device_t at the moment */
243typedef unsigned long dma_device_t; 195typedef unsigned long dma_device_t;
244 196
245/* functions --------------------------------------------------------------- */
246
247/* s3c2410_dma_request
248 *
249 * request a dma channel exclusivley
250*/
251
252extern int s3c2410_dma_request(unsigned int channel,
253 struct s3c2410_dma_client *, void *dev);
254
255
256/* s3c2410_dma_ctrl
257 *
258 * change the state of the dma channel
259*/
260
261extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
262
263/* s3c2410_dma_setflags
264 *
265 * set the channel's flags to a given state
266*/
267
268extern int s3c2410_dma_setflags(unsigned int channel,
269 unsigned int flags);
270
271/* s3c2410_dma_free
272 *
273 * free the dma channel (will also abort any outstanding operations)
274*/
275
276extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
277
278/* s3c2410_dma_enqueue
279 *
280 * place the given buffer onto the queue of operations for the channel.
281 * The buffer must be allocated from dma coherent memory, or the Dcache/WB
282 * drained before the buffer is given to the DMA system.
283*/
284
285extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
286 dma_addr_t data, int size);
287
288/* s3c2410_dma_config
289 *
290 * configure the dma channel
291*/
292
293extern int s3c2410_dma_config(unsigned int channel, int xferunit, int dcon);
294
295/* s3c2410_dma_devconfig
296 *
297 * configure the device we're talking to
298*/
299
300extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
301 int hwcfg, unsigned long devaddr);
302
303/* s3c2410_dma_getposition
304 *
305 * get the position that the dma transfer is currently at
306*/
307
308extern int s3c2410_dma_getposition(unsigned int channel,
309 dma_addr_t *src, dma_addr_t *dest);
310
311extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
312extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
313
314/* DMA Register definitions */
315
316#define S3C2410_DMA_DISRC (0x00)
317#define S3C2410_DMA_DISRCC (0x04)
318#define S3C2410_DMA_DIDST (0x08)
319#define S3C2410_DMA_DIDSTC (0x0C)
320#define S3C2410_DMA_DCON (0x10)
321#define S3C2410_DMA_DSTAT (0x14)
322#define S3C2410_DMA_DCSRC (0x18)
323#define S3C2410_DMA_DCDST (0x1C)
324#define S3C2410_DMA_DMASKTRIG (0x20)
325#define S3C2412_DMA_DMAREQSEL (0x24)
326#define S3C2443_DMA_DMAREQSEL (0x24)
327
328#define S3C2410_DISRCC_INC (1<<0)
329#define S3C2410_DISRCC_APB (1<<1)
330
331#define S3C2410_DMASKTRIG_STOP (1<<2)
332#define S3C2410_DMASKTRIG_ON (1<<1)
333#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
334
335#define S3C2410_DCON_DEMAND (0<<31)
336#define S3C2410_DCON_HANDSHAKE (1<<31)
337#define S3C2410_DCON_SYNC_PCLK (0<<30)
338#define S3C2410_DCON_SYNC_HCLK (1<<30)
339
340#define S3C2410_DCON_INTREQ (1<<29)
341
342#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
343#define S3C2410_DCON_CH0_UART0 (1<<24)
344#define S3C2410_DCON_CH0_SDI (2<<24)
345#define S3C2410_DCON_CH0_TIMER (3<<24)
346#define S3C2410_DCON_CH0_USBEP1 (4<<24)
347
348#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
349#define S3C2410_DCON_CH1_UART1 (1<<24)
350#define S3C2410_DCON_CH1_I2SSDI (2<<24)
351#define S3C2410_DCON_CH1_SPI (3<<24)
352#define S3C2410_DCON_CH1_USBEP2 (4<<24)
353
354#define S3C2410_DCON_CH2_I2SSDO (0<<24)
355#define S3C2410_DCON_CH2_I2SSDI (1<<24)
356#define S3C2410_DCON_CH2_SDI (2<<24)
357#define S3C2410_DCON_CH2_TIMER (3<<24)
358#define S3C2410_DCON_CH2_USBEP3 (4<<24)
359
360#define S3C2410_DCON_CH3_UART2 (0<<24)
361#define S3C2410_DCON_CH3_SDI (1<<24)
362#define S3C2410_DCON_CH3_SPI (2<<24)
363#define S3C2410_DCON_CH3_TIMER (3<<24)
364#define S3C2410_DCON_CH3_USBEP4 (4<<24)
365
366#define S3C2410_DCON_SRCSHIFT (24)
367#define S3C2410_DCON_SRCMASK (7<<24)
368
369#define S3C2410_DCON_BYTE (0<<20)
370#define S3C2410_DCON_HALFWORD (1<<20)
371#define S3C2410_DCON_WORD (2<<20)
372
373#define S3C2410_DCON_AUTORELOAD (0<<22)
374#define S3C2410_DCON_NORELOAD (1<<22)
375#define S3C2410_DCON_HWTRIG (1<<23)
376
377#ifdef CONFIG_CPU_S3C2440
378#define S3C2440_DIDSTC_CHKINT (1<<2)
379
380#define S3C2440_DCON_CH0_I2SSDO (5<<24)
381#define S3C2440_DCON_CH0_PCMIN (6<<24)
382
383#define S3C2440_DCON_CH1_PCMOUT (5<<24)
384#define S3C2440_DCON_CH1_SDI (6<<24)
385
386#define S3C2440_DCON_CH2_PCMIN (5<<24)
387#define S3C2440_DCON_CH2_MICIN (6<<24)
388
389#define S3C2440_DCON_CH3_MICIN (5<<24)
390#define S3C2440_DCON_CH3_PCMOUT (6<<24)
391#endif
392
393#ifdef CONFIG_CPU_S3C2412
394
395#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
396
397#define S3C2412_DMAREQSEL_HW (1)
398
399#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
400#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
401#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
402#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
403#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
404#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
405#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
406#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
407#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
408#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
409#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
410#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
411#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
412#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
413#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
414#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
415#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
416#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
417#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
418#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
419
420#endif
421
422#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1)
423
424#define S3C2443_DMAREQSEL_HW (1)
425
426#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
427#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
428#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
429#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
430#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
431#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
432#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
433#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
434#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
435#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
436#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
437#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
438#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
439#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
440#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
441#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
442#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
443#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
444#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
445#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
446#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
447
448#endif /* __ASM_ARCH_DMA_H */ 197#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index 9e3478506c6f..f8d16fc10bc6 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -20,12 +20,13 @@
20 20
21#include <mach/dma.h> 21#include <mach/dma.h>
22 22
23#include <plat/dma.h> 23#include <plat/dma-plat.h>
24#include <plat/cpu.h> 24#include <plat/cpu.h>
25 25
26#include <plat/regs-serial.h> 26#include <plat/regs-serial.h>
27#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
28#include <plat/regs-ac97.h> 28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h>
29#include <mach/regs-mem.h> 30#include <mach/regs-mem.h>
30#include <mach/regs-lcd.h> 31#include <mach/regs-lcd.h>
31#include <mach/regs-sdi.h> 32#include <mach/regs-sdi.h>
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index 69b6cf34df47..e08e081430f0 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -17,14 +17,16 @@
17#include <linux/sysdev.h> 17#include <linux/sysdev.h>
18#include <linux/serial_core.h> 18#include <linux/serial_core.h>
19 19
20#include <mach/map.h>
20#include <mach/dma.h> 21#include <mach/dma.h>
21 22
22#include <plat/dma.h> 23#include <plat/dma-plat.h>
23#include <plat/cpu.h> 24#include <plat/cpu.h>
24 25
25#include <plat/regs-serial.h> 26#include <plat/regs-serial.h>
26#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
27#include <plat/regs-ac97.h> 28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h>
28#include <mach/regs-mem.h> 30#include <mach/regs-mem.h>
29#include <mach/regs-lcd.h> 31#include <mach/regs-lcd.h>
30#include <mach/regs-sdi.h> 32#include <mach/regs-sdi.h>
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index 8430e5829186..397f3b5c0b47 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -20,12 +20,13 @@
20 20
21#include <mach/dma.h> 21#include <mach/dma.h>
22 22
23#include <plat/dma.h> 23#include <plat/dma-plat.h>
24#include <plat/cpu.h> 24#include <plat/cpu.h>
25 25
26#include <plat/regs-serial.h> 26#include <plat/regs-serial.h>
27#include <mach/regs-gpio.h> 27#include <mach/regs-gpio.h>
28#include <plat/regs-ac97.h> 28#include <plat/regs-ac97.h>
29#include <plat/regs-dma.h>
29#include <mach/regs-mem.h> 30#include <mach/regs-mem.h>
30#include <mach/regs-lcd.h> 31#include <mach/regs-lcd.h>
31#include <mach/regs-sdi.h> 32#include <mach/regs-sdi.h>
diff --git a/arch/arm/mach-s3c6400/include/mach/dma.h b/arch/arm/mach-s3c6400/include/mach/dma.h
index 9771ac2cb07e..1067619f0ba0 100644
--- a/arch/arm/mach-s3c6400/include/mach/dma.h
+++ b/arch/arm/mach-s3c6400/include/mach/dma.h
@@ -11,6 +11,63 @@
11#ifndef __ASM_ARCH_DMA_H 11#ifndef __ASM_ARCH_DMA_H
12#define __ASM_ARCH_DMA_H __FILE__ 12#define __ASM_ARCH_DMA_H __FILE__
13 13
14/* currently nothing here, placeholder */ 14#define S3C_DMA_CHANNELS (16)
15
16/* see mach-s3c2410/dma.h for notes on dma channel numbers */
17
18/* Note, for the S3C64XX architecture we keep the DMACH_
19 * defines in the order they are allocated to [S]DMA0/[S]DMA1
20 * so that is easy to do DHACH_ -> DMA controller conversion
21 */
22enum dma_ch {
23 /* DMA0/SDMA0 */
24 DMACH_UART0 = 0,
25 DMACH_UART0_SRC2,
26 DMACH_UART1,
27 DMACH_UART1_SRC2,
28 DMACH_UART2,
29 DMACH_UART2_SRC2,
30 DMACH_UART3,
31 DMACH_UART3_SRC2,
32 DMACH_PCM0_TX,
33 DMACH_PCM0_RX,
34 DMACH_I2S0_OUT,
35 DMACH_I2S0_IN,
36 DMACH_SPI0_TX,
37 DMACH_SPI0_RX,
38 DMACH_HSI_I2SV40_TX,
39 DMACH_HSI_I2SV40_RX,
40
41 /* DMA1/SDMA1 */
42 DMACH_PCM1_TX = 16,
43 DMACH_PCM1_RX,
44 DMACH_I2S1_OUT,
45 DMACH_I2S1_IN,
46 DMACH_SPI1_TX,
47 DMACH_SPI1_RX,
48 DMACH_AC97_PCMOUT,
49 DMACH_AC97_PCMIN,
50 DMACH_AC97_MICIN,
51 DMACH_PWM,
52 DMACH_IRDA,
53 DMACH_EXTERNAL,
54 DMACH_RES1,
55 DMACH_RES2,
56 DMACH_SECURITY_RX, /* SDMA1 only */
57 DMACH_SECURITY_TX, /* SDMA1 only */
58 DMACH_MAX /* the end */
59};
60
61static __inline__ int s3c_dma_has_circular(void)
62{
63 /* we will be supporting ciruclar buffers as soon as we have DMA
64 * engine support.
65 */
66 return 1;
67}
68
69#define S3C2410_DMAF_CIRCULAR (1 << 0)
70
71#include <plat/dma.h>
15 72
16#endif /* __ASM_ARCH_IRQ_H */ 73#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig
index 140391587c39..935c7558469b 100644
--- a/arch/arm/plat-s3c/Kconfig
+++ b/arch/arm/plat-s3c/Kconfig
@@ -159,6 +159,13 @@ config S3C_GPIO_CFG_S3C64XX
159 Internal configuration to enable S3C64XX style GPIO configuration 159 Internal configuration to enable S3C64XX style GPIO configuration
160 functions. 160 functions.
161 161
162# DMA
163
164config S3C_DMA
165 bool
166 help
167 Internal configuration for S3C DMA core
168
162# device definitions to compile in 169# device definitions to compile in
163 170
164config S3C_DEV_HSMMC 171config S3C_DEV_HSMMC
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile
index 061e20458e89..610651455a78 100644
--- a/arch/arm/plat-s3c/Makefile
+++ b/arch/arm/plat-s3c/Makefile
@@ -18,6 +18,10 @@ obj-y += pwm-clock.o
18obj-y += gpio.o 18obj-y += gpio.o
19obj-y += gpio-config.o 19obj-y += gpio-config.o
20 20
21# DMA support
22
23obj-$(CONFIG_S3C_DMA) += dma.o
24
21# PM support 25# PM support
22 26
23obj-$(CONFIG_PM) += pm.o 27obj-$(CONFIG_PM) += pm.o
diff --git a/arch/arm/plat-s3c/dma.c b/arch/arm/plat-s3c/dma.c
new file mode 100644
index 000000000000..c9db75c06af5
--- /dev/null
+++ b/arch/arm/plat-s3c/dma.c
@@ -0,0 +1,86 @@
1/* linux/arch/arm/plat-s3c/dma.c
2 *
3 * Copyright (c) 2003-2005,2006,2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C DMA core
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14struct s3c2410_dma_buf;
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/errno.h>
19
20#include <mach/dma.h>
21#include <mach/irqs.h>
22
23#include <plat/dma-plat.h>
24
25/* dma channel state information */
26struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
27struct s3c2410_dma_chan *s3c_dma_chan_map[DMACH_MAX];
28
29/* s3c_dma_lookup_channel
30 *
31 * change the dma channel number given into a real dma channel id
32*/
33
34struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel)
35{
36 if (channel & DMACH_LOW_LEVEL)
37 return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
38 else
39 return s3c_dma_chan_map[channel];
40}
41
42/* do we need to protect the settings of the fields from
43 * irq?
44*/
45
46int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
47{
48 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
49
50 if (chan == NULL)
51 return -EINVAL;
52
53 pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
54
55 chan->op_fn = rtn;
56
57 return 0;
58}
59EXPORT_SYMBOL(s3c2410_dma_set_opfn);
60
61int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
62{
63 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
64
65 if (chan == NULL)
66 return -EINVAL;
67
68 pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
69
70 chan->callback_fn = rtn;
71
72 return 0;
73}
74EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
75
76int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
77{
78 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
79
80 if (chan == NULL)
81 return -EINVAL;
82
83 chan->flags = flags;
84 return 0;
85}
86EXPORT_SYMBOL(s3c2410_dma_setflags);
diff --git a/arch/arm/plat-s3c/include/plat/dma-core.h b/arch/arm/plat-s3c/include/plat/dma-core.h
new file mode 100644
index 000000000000..32ff2a92cb3c
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/dma-core.h
@@ -0,0 +1,22 @@
1/* arch/arm/plat-s3c/include/plat/dma.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Samsung S3C DMA core support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15extern struct s3c2410_dma_chan *s3c_dma_lookup_channel(unsigned int channel);
16
17extern struct s3c2410_dma_chan *s3c_dma_chan_map[];
18
19/* the currently allocated channel information */
20extern struct s3c2410_dma_chan s3c2410_chans[];
21
22
diff --git a/arch/arm/plat-s3c/include/plat/dma.h b/arch/arm/plat-s3c/include/plat/dma.h
new file mode 100644
index 000000000000..34dba98f08e1
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/dma.h
@@ -0,0 +1,127 @@
1/* arch/arm/plat-s3c/include/plat/dma.h
2 *
3 * Copyright (C) 2003,2004,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13enum s3c2410_dma_buffresult {
14 S3C2410_RES_OK,
15 S3C2410_RES_ERR,
16 S3C2410_RES_ABORT
17};
18
19enum s3c2410_dmasrc {
20 S3C2410_DMASRC_HW, /* source is memory */
21 S3C2410_DMASRC_MEM /* source is hardware */
22};
23
24/* enum s3c2410_chan_op
25 *
26 * operation codes passed to the DMA code by the user, and also used
27 * to inform the current channel owner of any changes to the system state
28*/
29
30enum s3c2410_chan_op {
31 S3C2410_DMAOP_START,
32 S3C2410_DMAOP_STOP,
33 S3C2410_DMAOP_PAUSE,
34 S3C2410_DMAOP_RESUME,
35 S3C2410_DMAOP_FLUSH,
36 S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
37 S3C2410_DMAOP_STARTED, /* indicate channel started */
38};
39
40struct s3c2410_dma_client {
41 char *name;
42};
43
44struct s3c2410_dma_chan;
45
46/* s3c2410_dma_cbfn_t
47 *
48 * buffer callback routine type
49*/
50
51typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
52 void *buf, int size,
53 enum s3c2410_dma_buffresult result);
54
55typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
56 enum s3c2410_chan_op );
57
58
59
60/* s3c2410_dma_request
61 *
62 * request a dma channel exclusivley
63*/
64
65extern int s3c2410_dma_request(unsigned int channel,
66 struct s3c2410_dma_client *, void *dev);
67
68
69/* s3c2410_dma_ctrl
70 *
71 * change the state of the dma channel
72*/
73
74extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op);
75
76/* s3c2410_dma_setflags
77 *
78 * set the channel's flags to a given state
79*/
80
81extern int s3c2410_dma_setflags(unsigned int channel,
82 unsigned int flags);
83
84/* s3c2410_dma_free
85 *
86 * free the dma channel (will also abort any outstanding operations)
87*/
88
89extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *);
90
91/* s3c2410_dma_enqueue
92 *
93 * place the given buffer onto the queue of operations for the channel.
94 * The buffer must be allocated from dma coherent memory, or the Dcache/WB
95 * drained before the buffer is given to the DMA system.
96*/
97
98extern int s3c2410_dma_enqueue(unsigned int channel, void *id,
99 dma_addr_t data, int size);
100
101/* s3c2410_dma_config
102 *
103 * configure the dma channel
104*/
105
106extern int s3c2410_dma_config(unsigned int channel, int xferunit);
107
108/* s3c2410_dma_devconfig
109 *
110 * configure the device we're talking to
111*/
112
113extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
114 unsigned long devaddr);
115
116/* s3c2410_dma_getposition
117 *
118 * get the position that the dma transfer is currently at
119*/
120
121extern int s3c2410_dma_getposition(unsigned int channel,
122 dma_addr_t *src, dma_addr_t *dest);
123
124extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn);
125extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn);
126
127
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 2c8a2f5d75ff..5b0bc914f58e 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -71,6 +71,7 @@ config PM_SIMTEC
71config S3C2410_DMA 71config S3C2410_DMA
72 bool "S3C2410 DMA support" 72 bool "S3C2410 DMA support"
73 depends on ARCH_S3C2410 73 depends on ARCH_S3C2410
74 select S3C_DMA
74 help 75 help
75 S3C2410 DMA support. This is needed for drivers like sound which 76 S3C2410 DMA support. This is needed for drivers like sound which
76 use the S3C2410's DMA system to move data to and from the 77 use the S3C2410's DMA system to move data to and from the
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index aee2aeb46c60..b07fec01ab47 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -31,10 +31,10 @@
31#include <asm/irq.h> 31#include <asm/irq.h>
32#include <mach/hardware.h> 32#include <mach/hardware.h>
33#include <mach/dma.h> 33#include <mach/dma.h>
34
35#include <mach/map.h> 34#include <mach/map.h>
36 35
37#include <plat/dma.h> 36#include <plat/dma-plat.h>
37#include <plat/regs-dma.h>
38 38
39/* io map for dma */ 39/* io map for dma */
40static void __iomem *dma_base; 40static void __iomem *dma_base;
@@ -44,8 +44,6 @@ static int dma_channels;
44 44
45static struct s3c24xx_dma_selection dma_sel; 45static struct s3c24xx_dma_selection dma_sel;
46 46
47/* dma channel state information */
48struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
49 47
50/* debugging functions */ 48/* debugging functions */
51 49
@@ -135,21 +133,6 @@ dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
135#define dbg_showchan(chan) do { } while(0) 133#define dbg_showchan(chan) do { } while(0)
136#endif /* CONFIG_S3C2410_DMA_DEBUG */ 134#endif /* CONFIG_S3C2410_DMA_DEBUG */
137 135
138static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
139
140/* lookup_dma_channel
141 *
142 * change the dma channel number given into a real dma channel id
143*/
144
145static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
146{
147 if (channel & DMACH_LOW_LEVEL)
148 return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
149 else
150 return dma_chan_map[channel];
151}
152
153/* s3c2410_dma_stats_timeout 136/* s3c2410_dma_stats_timeout
154 * 137 *
155 * Update DMA stats from timeout info 138 * Update DMA stats from timeout info
@@ -214,8 +197,6 @@ s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
214 return 0; 197 return 0;
215} 198}
216 199
217
218
219/* s3c2410_dma_loadbuffer 200/* s3c2410_dma_loadbuffer
220 * 201 *
221 * load a buffer, and update the channel state 202 * load a buffer, and update the channel state
@@ -453,7 +434,7 @@ s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
453int s3c2410_dma_enqueue(unsigned int channel, void *id, 434int s3c2410_dma_enqueue(unsigned int channel, void *id,
454 dma_addr_t data, int size) 435 dma_addr_t data, int size)
455{ 436{
456 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 437 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
457 struct s3c2410_dma_buf *buf; 438 struct s3c2410_dma_buf *buf;
458 unsigned long flags; 439 unsigned long flags;
459 440
@@ -804,7 +785,7 @@ EXPORT_SYMBOL(s3c2410_dma_request);
804 785
805int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client) 786int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
806{ 787{
807 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 788 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
808 unsigned long flags; 789 unsigned long flags;
809 790
810 if (chan == NULL) 791 if (chan == NULL)
@@ -836,7 +817,7 @@ int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
836 chan->irq_claimed = 0; 817 chan->irq_claimed = 0;
837 818
838 if (!(channel & DMACH_LOW_LEVEL)) 819 if (!(channel & DMACH_LOW_LEVEL))
839 dma_chan_map[channel] = NULL; 820 s3c_dma_chan_map[channel] = NULL;
840 821
841 local_irq_restore(flags); 822 local_irq_restore(flags);
842 823
@@ -995,7 +976,7 @@ static int s3c2410_dma_started(struct s3c2410_dma_chan *chan)
995int 976int
996s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op) 977s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
997{ 978{
998 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 979 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
999 980
1000 if (chan == NULL) 981 if (chan == NULL)
1001 return -EINVAL; 982 return -EINVAL;
@@ -1038,14 +1019,13 @@ EXPORT_SYMBOL(s3c2410_dma_ctrl);
1038/* s3c2410_dma_config 1019/* s3c2410_dma_config
1039 * 1020 *
1040 * xfersize: size of unit in bytes (1,2,4) 1021 * xfersize: size of unit in bytes (1,2,4)
1041 * dcon: base value of the DCONx register
1042*/ 1022*/
1043 1023
1044int s3c2410_dma_config(unsigned int channel, 1024int s3c2410_dma_config(unsigned int channel,
1045 int xferunit, 1025 int xferunit)
1046 int dcon)
1047{ 1026{
1048 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 1027 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1028 unsigned int dcon;
1049 1029
1050 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n", 1030 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
1051 __func__, channel, xferunit, dcon); 1031 __func__, channel, xferunit, dcon);
@@ -1055,10 +1035,33 @@ int s3c2410_dma_config(unsigned int channel,
1055 1035
1056 pr_debug("%s: Initial dcon is %08x\n", __func__, dcon); 1036 pr_debug("%s: Initial dcon is %08x\n", __func__, dcon);
1057 1037
1058 dcon |= chan->dcon & dma_sel.dcon_mask; 1038 dcon = chan->dcon & dma_sel.dcon_mask;
1059 1039
1060 pr_debug("%s: New dcon is %08x\n", __func__, dcon); 1040 pr_debug("%s: New dcon is %08x\n", __func__, dcon);
1061 1041
1042 switch (chan->req_ch) {
1043 case DMACH_I2S_IN:
1044 case DMACH_I2S_OUT:
1045 case DMACH_PCM_IN:
1046 case DMACH_PCM_OUT:
1047 case DMACH_MIC_IN:
1048 default:
1049 dcon |= S3C2410_DCON_HANDSHAKE;
1050 dcon |= S3C2410_DCON_SYNC_PCLK;
1051 break;
1052
1053 case DMACH_SDI:
1054 /* note, ensure if need HANDSHAKE or not */
1055 dcon |= S3C2410_DCON_SYNC_PCLK;
1056 break;
1057
1058 case DMACH_XD0:
1059 case DMACH_XD1:
1060 dcon |= S3C2410_DCON_HANDSHAKE;
1061 dcon |= S3C2410_DCON_SYNC_HCLK;
1062 break;
1063 }
1064
1062 switch (xferunit) { 1065 switch (xferunit) {
1063 case 1: 1066 case 1:
1064 dcon |= S3C2410_DCON_BYTE; 1067 dcon |= S3C2410_DCON_BYTE;
@@ -1090,58 +1093,6 @@ int s3c2410_dma_config(unsigned int channel,
1090 1093
1091EXPORT_SYMBOL(s3c2410_dma_config); 1094EXPORT_SYMBOL(s3c2410_dma_config);
1092 1095
1093int s3c2410_dma_setflags(unsigned int channel, unsigned int flags)
1094{
1095 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1096
1097 if (chan == NULL)
1098 return -EINVAL;
1099
1100 pr_debug("%s: chan=%p, flags=%08x\n", __func__, chan, flags);
1101
1102 chan->flags = flags;
1103
1104 return 0;
1105}
1106
1107EXPORT_SYMBOL(s3c2410_dma_setflags);
1108
1109
1110/* do we need to protect the settings of the fields from
1111 * irq?
1112*/
1113
1114int s3c2410_dma_set_opfn(unsigned int channel, s3c2410_dma_opfn_t rtn)
1115{
1116 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1117
1118 if (chan == NULL)
1119 return -EINVAL;
1120
1121 pr_debug("%s: chan=%p, op rtn=%p\n", __func__, chan, rtn);
1122
1123 chan->op_fn = rtn;
1124
1125 return 0;
1126}
1127
1128EXPORT_SYMBOL(s3c2410_dma_set_opfn);
1129
1130int s3c2410_dma_set_buffdone_fn(unsigned int channel, s3c2410_dma_cbfn_t rtn)
1131{
1132 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1133
1134 if (chan == NULL)
1135 return -EINVAL;
1136
1137 pr_debug("%s: chan=%p, callback rtn=%p\n", __func__, chan, rtn);
1138
1139 chan->callback_fn = rtn;
1140
1141 return 0;
1142}
1143
1144EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
1145 1096
1146/* s3c2410_dma_devconfig 1097/* s3c2410_dma_devconfig
1147 * 1098 *
@@ -1150,29 +1101,38 @@ EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
1150 * source: S3C2410_DMASRC_HW: source is hardware 1101 * source: S3C2410_DMASRC_HW: source is hardware
1151 * S3C2410_DMASRC_MEM: source is memory 1102 * S3C2410_DMASRC_MEM: source is memory
1152 * 1103 *
1153 * hwcfg: the value for xxxSTCn register,
1154 * bit 0: 0=increment pointer, 1=leave pointer
1155 * bit 1: 0=source is AHB, 1=source is APB
1156 *
1157 * devaddr: physical address of the source 1104 * devaddr: physical address of the source
1158*/ 1105*/
1159 1106
1160int s3c2410_dma_devconfig(int channel, 1107int s3c2410_dma_devconfig(int channel,
1161 enum s3c2410_dmasrc source, 1108 enum s3c2410_dmasrc source,
1162 int hwcfg,
1163 unsigned long devaddr) 1109 unsigned long devaddr)
1164{ 1110{
1165 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 1111 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1112 unsigned int hwcfg;
1166 1113
1167 if (chan == NULL) 1114 if (chan == NULL)
1168 return -EINVAL; 1115 return -EINVAL;
1169 1116
1170 pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n", 1117 pr_debug("%s: source=%d, devaddr=%08lx\n",
1171 __func__, (int)source, hwcfg, devaddr); 1118 __func__, (int)source, devaddr);
1172 1119
1173 chan->source = source; 1120 chan->source = source;
1174 chan->dev_addr = devaddr; 1121 chan->dev_addr = devaddr;
1175 chan->hw_cfg = hwcfg; 1122
1123 switch (chan->req_ch) {
1124 case DMACH_XD0:
1125 case DMACH_XD1:
1126 hwcfg = 0; /* AHB */
1127 break;
1128
1129 default:
1130 hwcfg = S3C2410_DISRCC_APB;
1131 }
1132
1133 /* always assume our peripheral desintation is a fixed
1134 * address in memory. */
1135 hwcfg |= S3C2410_DISRCC_INC;
1176 1136
1177 switch (source) { 1137 switch (source) {
1178 case S3C2410_DMASRC_HW: 1138 case S3C2410_DMASRC_HW:
@@ -1219,7 +1179,7 @@ EXPORT_SYMBOL(s3c2410_dma_devconfig);
1219 1179
1220int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *dst) 1180int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *dst)
1221{ 1181{
1222 struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); 1182 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1223 1183
1224 if (chan == NULL) 1184 if (chan == NULL)
1225 return -EINVAL; 1185 return -EINVAL;
@@ -1278,8 +1238,8 @@ static int s3c2410_dma_resume(struct sys_device *dev)
1278 1238
1279 printk(KERN_INFO "dma%d: restoring configuration\n", cp->number); 1239 printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
1280 1240
1281 s3c2410_dma_config(no, cp->xfer_unit, cp->dcon); 1241 s3c2410_dma_config(no, cp->xfer_unit);
1282 s3c2410_dma_devconfig(no, cp->source, cp->hw_cfg, cp->dev_addr); 1242 s3c2410_dma_devconfig(no, cp->source, cp->dev_addr);
1283 1243
1284 /* re-select the dma source for this channel */ 1244 /* re-select the dma source for this channel */
1285 1245
@@ -1476,7 +1436,8 @@ static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
1476 found: 1436 found:
1477 dmach = &s3c2410_chans[ch]; 1437 dmach = &s3c2410_chans[ch];
1478 dmach->map = ch_map; 1438 dmach->map = ch_map;
1479 dma_chan_map[channel] = dmach; 1439 dmach->req_ch = channel;
1440 s3c_dma_chan_map[channel] = dmach;
1480 1441
1481 /* select the channel */ 1442 /* select the channel */
1482 1443
diff --git a/arch/arm/plat-s3c24xx/include/plat/dma.h b/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
index c78efe316fc8..9565ead1bc9b 100644
--- a/arch/arm/plat-s3c24xx/include/plat/dma.h
+++ b/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
@@ -1,4 +1,4 @@
1/* linux/include/asm-arm/plat-s3c24xx/dma.h 1/* linux/arch/arm/plat-s3c24xx/include/plat/dma-plat.h
2 * 2 *
3 * Copyright (C) 2006 Simtec Electronics 3 * Copyright (C) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
@@ -10,8 +10,10 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13#include <plat/dma-core.h>
14
13extern struct sysdev_class dma_sysclass; 15extern struct sysdev_class dma_sysclass;
14extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS]; 16extern struct s3c2410_dma_chan s3c2410_chans[S3C_DMA_CHANNELS];
15 17
16#define DMA_CH_VALID (1<<31) 18#define DMA_CH_VALID (1<<31)
17#define DMA_CH_NEVER (1<<30) 19#define DMA_CH_NEVER (1<<30)
@@ -31,8 +33,8 @@ struct s3c24xx_dma_map {
31 const char *name; 33 const char *name;
32 struct s3c24xx_dma_addr hw_addr; 34 struct s3c24xx_dma_addr hw_addr;
33 35
34 unsigned long channels[S3C2410_DMA_CHANNELS]; 36 unsigned long channels[S3C_DMA_CHANNELS];
35 unsigned long channels_rx[S3C2410_DMA_CHANNELS]; 37 unsigned long channels_rx[S3C_DMA_CHANNELS];
36}; 38};
37 39
38struct s3c24xx_dma_selection { 40struct s3c24xx_dma_selection {
@@ -58,7 +60,7 @@ extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
58*/ 60*/
59 61
60struct s3c24xx_dma_order_ch { 62struct s3c24xx_dma_order_ch {
61 unsigned int list[S3C2410_DMA_CHANNELS]; /* list of channels */ 63 unsigned int list[S3C_DMA_CHANNELS]; /* list of channels */
62 unsigned int flags; /* flags */ 64 unsigned int flags; /* flags */
63}; 65};
64 66
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
new file mode 100644
index 000000000000..3bc0a216df97
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
@@ -0,0 +1,145 @@
1/* arch/arm/mach-s3c2410/include/mach/dma.h
2 *
3 * Copyright (C) 2003,2004,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C24XX DMA support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* DMA Register definitions */
14
15#define S3C2410_DMA_DISRC (0x00)
16#define S3C2410_DMA_DISRCC (0x04)
17#define S3C2410_DMA_DIDST (0x08)
18#define S3C2410_DMA_DIDSTC (0x0C)
19#define S3C2410_DMA_DCON (0x10)
20#define S3C2410_DMA_DSTAT (0x14)
21#define S3C2410_DMA_DCSRC (0x18)
22#define S3C2410_DMA_DCDST (0x1C)
23#define S3C2410_DMA_DMASKTRIG (0x20)
24#define S3C2412_DMA_DMAREQSEL (0x24)
25#define S3C2443_DMA_DMAREQSEL (0x24)
26
27#define S3C2410_DISRCC_INC (1<<0)
28#define S3C2410_DISRCC_APB (1<<1)
29
30#define S3C2410_DMASKTRIG_STOP (1<<2)
31#define S3C2410_DMASKTRIG_ON (1<<1)
32#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
33
34#define S3C2410_DCON_DEMAND (0<<31)
35#define S3C2410_DCON_HANDSHAKE (1<<31)
36#define S3C2410_DCON_SYNC_PCLK (0<<30)
37#define S3C2410_DCON_SYNC_HCLK (1<<30)
38
39#define S3C2410_DCON_INTREQ (1<<29)
40
41#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
42#define S3C2410_DCON_CH0_UART0 (1<<24)
43#define S3C2410_DCON_CH0_SDI (2<<24)
44#define S3C2410_DCON_CH0_TIMER (3<<24)
45#define S3C2410_DCON_CH0_USBEP1 (4<<24)
46
47#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
48#define S3C2410_DCON_CH1_UART1 (1<<24)
49#define S3C2410_DCON_CH1_I2SSDI (2<<24)
50#define S3C2410_DCON_CH1_SPI (3<<24)
51#define S3C2410_DCON_CH1_USBEP2 (4<<24)
52
53#define S3C2410_DCON_CH2_I2SSDO (0<<24)
54#define S3C2410_DCON_CH2_I2SSDI (1<<24)
55#define S3C2410_DCON_CH2_SDI (2<<24)
56#define S3C2410_DCON_CH2_TIMER (3<<24)
57#define S3C2410_DCON_CH2_USBEP3 (4<<24)
58
59#define S3C2410_DCON_CH3_UART2 (0<<24)
60#define S3C2410_DCON_CH3_SDI (1<<24)
61#define S3C2410_DCON_CH3_SPI (2<<24)
62#define S3C2410_DCON_CH3_TIMER (3<<24)
63#define S3C2410_DCON_CH3_USBEP4 (4<<24)
64
65#define S3C2410_DCON_SRCSHIFT (24)
66#define S3C2410_DCON_SRCMASK (7<<24)
67
68#define S3C2410_DCON_BYTE (0<<20)
69#define S3C2410_DCON_HALFWORD (1<<20)
70#define S3C2410_DCON_WORD (2<<20)
71
72#define S3C2410_DCON_AUTORELOAD (0<<22)
73#define S3C2410_DCON_NORELOAD (1<<22)
74#define S3C2410_DCON_HWTRIG (1<<23)
75
76#ifdef CONFIG_CPU_S3C2440
77#define S3C2440_DIDSTC_CHKINT (1<<2)
78
79#define S3C2440_DCON_CH0_I2SSDO (5<<24)
80#define S3C2440_DCON_CH0_PCMIN (6<<24)
81
82#define S3C2440_DCON_CH1_PCMOUT (5<<24)
83#define S3C2440_DCON_CH1_SDI (6<<24)
84
85#define S3C2440_DCON_CH2_PCMIN (5<<24)
86#define S3C2440_DCON_CH2_MICIN (6<<24)
87
88#define S3C2440_DCON_CH3_MICIN (5<<24)
89#define S3C2440_DCON_CH3_PCMOUT (6<<24)
90#endif
91
92#ifdef CONFIG_CPU_S3C2412
93
94#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
95
96#define S3C2412_DMAREQSEL_HW (1)
97
98#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
99#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
100#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
101#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
102#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
103#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
104#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
105#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
106#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
107#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
108#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
109#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
110#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
111#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
112#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
113#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
114#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
115#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
116#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
117#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
118
119#endif
120
121#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1)
122
123#define S3C2443_DMAREQSEL_HW (1)
124
125#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0)
126#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1)
127#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2)
128#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3)
129#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4)
130#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5)
131#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9)
132#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10)
133#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17)
134#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18)
135#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19)
136#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20)
137#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21)
138#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22)
139#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23)
140#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24)
141#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
142#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
143#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
144#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
145#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig
index eb088db0e650..5ebd8b425a54 100644
--- a/arch/arm/plat-s3c64xx/Kconfig
+++ b/arch/arm/plat-s3c64xx/Kconfig
@@ -39,6 +39,10 @@ config CPU_S3C6400_CLOCK
39 Common clock support code for the S3C6400 that is shared 39 Common clock support code for the S3C6400 that is shared
40 by other CPUs in the series, such as the S3C6410. 40 by other CPUs in the series, such as the S3C6410.
41 41
42config S3C64XX_DMA
43 bool "S3C64XX DMA"
44 select S3C_DMA
45
42# platform specific device setup 46# platform specific device setup
43 47
44config S3C64XX_SETUP_I2C0 48config S3C64XX_SETUP_I2C0
diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile
index 030050f5c76d..2ed5df34f9ea 100644
--- a/arch/arm/plat-s3c64xx/Makefile
+++ b/arch/arm/plat-s3c64xx/Makefile
@@ -30,6 +30,10 @@ obj-$(CONFIG_PM) += pm.o
30obj-$(CONFIG_PM) += sleep.o 30obj-$(CONFIG_PM) += sleep.o
31obj-$(CONFIG_PM) += irq-pm.o 31obj-$(CONFIG_PM) += irq-pm.o
32 32
33# DMA support
34
35obj-$(CONFIG_S3C64XX_DMA) += dma.o
36
33# Device setup 37# Device setup
34 38
35obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o 39obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
diff --git a/arch/arm/plat-s3c64xx/dma.c b/arch/arm/plat-s3c64xx/dma.c
new file mode 100644
index 000000000000..67aa93dbb69e
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/dma.c
@@ -0,0 +1,722 @@
1/* linux/arch/arm/plat-s3c64xx/dma.c
2 *
3 * Copyright 2009 Openmoko, Inc.
4 * Copyright 2009 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX DMA core
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/dmapool.h>
19#include <linux/sysdev.h>
20#include <linux/errno.h>
21#include <linux/delay.h>
22#include <linux/clk.h>
23#include <linux/err.h>
24#include <linux/io.h>
25
26#include <mach/dma.h>
27#include <mach/map.h>
28#include <mach/irqs.h>
29
30#include <plat/dma-plat.h>
31#include <plat/regs-sys.h>
32
33#include <asm/hardware/pl080.h>
34
35/* dma channel state information */
36
37struct s3c64xx_dmac {
38 struct sys_device sysdev;
39 struct clk *clk;
40 void __iomem *regs;
41 struct s3c2410_dma_chan *channels;
42 enum dma_ch chanbase;
43};
44
45/* pool to provide LLI buffers */
46static struct dma_pool *dma_pool;
47
48/* Debug configuration and code */
49
50static unsigned char debug_show_buffs = 0;
51
52static void dbg_showchan(struct s3c2410_dma_chan *chan)
53{
54 pr_debug("DMA%d: %08x->%08x L %08x C %08x,%08x S %08x\n",
55 chan->number,
56 readl(chan->regs + PL080_CH_SRC_ADDR),
57 readl(chan->regs + PL080_CH_DST_ADDR),
58 readl(chan->regs + PL080_CH_LLI),
59 readl(chan->regs + PL080_CH_CONTROL),
60 readl(chan->regs + PL080S_CH_CONTROL2),
61 readl(chan->regs + PL080S_CH_CONFIG));
62}
63
64static void show_lli(struct pl080s_lli *lli)
65{
66 pr_debug("LLI[%p] %08x->%08x, NL %08x C %08x,%08x\n",
67 lli, lli->src_addr, lli->dst_addr, lli->next_lli,
68 lli->control0, lli->control1);
69}
70
71static void dbg_showbuffs(struct s3c2410_dma_chan *chan)
72{
73 struct s3c64xx_dma_buff *ptr;
74 struct s3c64xx_dma_buff *end;
75
76 pr_debug("DMA%d: buffs next %p, curr %p, end %p\n",
77 chan->number, chan->next, chan->curr, chan->end);
78
79 ptr = chan->next;
80 end = chan->end;
81
82 if (debug_show_buffs) {
83 for (; ptr != NULL; ptr = ptr->next) {
84 pr_debug("DMA%d: %08x ",
85 chan->number, ptr->lli_dma);
86 show_lli(ptr->lli);
87 }
88 }
89}
90
91/* End of Debug */
92
93static struct s3c2410_dma_chan *s3c64xx_dma_map_channel(unsigned int channel)
94{
95 struct s3c2410_dma_chan *chan;
96 unsigned int start, offs;
97
98 start = 0;
99
100 if (channel >= DMACH_PCM1_TX)
101 start = 8;
102
103 for (offs = 0; offs < 8; offs++) {
104 chan = &s3c2410_chans[start + offs];
105 if (!chan->in_use)
106 goto found;
107 }
108
109 return NULL;
110
111found:
112 s3c_dma_chan_map[channel] = chan;
113 return chan;
114}
115
116int s3c2410_dma_config(unsigned int channel, int xferunit)
117{
118 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
119
120 if (chan == NULL)
121 return -EINVAL;
122
123 switch (xferunit) {
124 case 1:
125 chan->hw_width = 0;
126 break;
127 case 2:
128 chan->hw_width = 1;
129 break;
130 case 4:
131 chan->hw_width = 2;
132 break;
133 default:
134 printk(KERN_ERR "%s: illegal width %d\n", __func__, xferunit);
135 return -EINVAL;
136 }
137
138 return 0;
139}
140EXPORT_SYMBOL(s3c2410_dma_config);
141
142static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan,
143 struct pl080s_lli *lli,
144 dma_addr_t data, int size)
145{
146 dma_addr_t src, dst;
147 u32 control0, control1;
148
149 switch (chan->source) {
150 case S3C2410_DMASRC_HW:
151 src = chan->dev_addr;
152 dst = data;
153 control0 = PL080_CONTROL_SRC_AHB2;
154 control0 |= (u32)chan->hw_width << PL080_CONTROL_SWIDTH_SHIFT;
155 control0 |= 2 << PL080_CONTROL_DWIDTH_SHIFT;
156 control0 |= PL080_CONTROL_DST_INCR;
157 break;
158
159 case S3C2410_DMASRC_MEM:
160 src = data;
161 dst = chan->dev_addr;
162 control0 = PL080_CONTROL_DST_AHB2;
163 control0 |= (u32)chan->hw_width << PL080_CONTROL_DWIDTH_SHIFT;
164 control0 |= 2 << PL080_CONTROL_SWIDTH_SHIFT;
165 control0 |= PL080_CONTROL_SRC_INCR;
166 break;
167 default:
168 BUG();
169 }
170
171 /* note, we do not currently setup any of the burst controls */
172
173 control1 = size >> chan->hw_width; /* size in no of xfers */
174 control0 |= PL080_CONTROL_PROT_SYS; /* always in priv. mode */
175 control0 |= PL080_CONTROL_TC_IRQ_EN; /* always fire IRQ */
176
177 lli->src_addr = src;
178 lli->dst_addr = dst;
179 lli->next_lli = 0;
180 lli->control0 = control0;
181 lli->control1 = control1;
182}
183
184static void s3c64xx_lli_to_regs(struct s3c2410_dma_chan *chan,
185 struct pl080s_lli *lli)
186{
187 void __iomem *regs = chan->regs;
188
189 pr_debug("%s: LLI %p => regs\n", __func__, lli);
190 show_lli(lli);
191
192 writel(lli->src_addr, regs + PL080_CH_SRC_ADDR);
193 writel(lli->dst_addr, regs + PL080_CH_DST_ADDR);
194 writel(lli->next_lli, regs + PL080_CH_LLI);
195 writel(lli->control0, regs + PL080_CH_CONTROL);
196 writel(lli->control1, regs + PL080S_CH_CONTROL2);
197}
198
199static int s3c64xx_dma_start(struct s3c2410_dma_chan *chan)
200{
201 struct s3c64xx_dmac *dmac = chan->dmac;
202 u32 config;
203 u32 bit = chan->bit;
204
205 dbg_showchan(chan);
206
207 pr_debug("%s: clearing interrupts\n", __func__);
208
209 /* clear interrupts */
210 writel(bit, dmac->regs + PL080_TC_CLEAR);
211 writel(bit, dmac->regs + PL080_ERR_CLEAR);
212
213 pr_debug("%s: starting channel\n", __func__);
214
215 config = readl(chan->regs + PL080S_CH_CONFIG);
216 config |= PL080_CONFIG_ENABLE;
217
218 pr_debug("%s: writing config %08x\n", __func__, config);
219 writel(config, chan->regs + PL080S_CH_CONFIG);
220
221 return 0;
222}
223
224static int s3c64xx_dma_stop(struct s3c2410_dma_chan *chan)
225{
226 u32 config;
227 int timeout;
228
229 pr_debug("%s: stopping channel\n", __func__);
230
231 dbg_showchan(chan);
232
233 config = readl(chan->regs + PL080S_CH_CONFIG);
234 config |= PL080_CONFIG_HALT;
235 writel(config, chan->regs + PL080S_CH_CONFIG);
236
237 timeout = 1000;
238 do {
239 config = readl(chan->regs + PL080S_CH_CONFIG);
240 pr_debug("%s: %d - config %08x\n", __func__, timeout, config);
241 if (config & PL080_CONFIG_ACTIVE)
242 udelay(10);
243 else
244 break;
245 } while (--timeout > 0);
246
247 if (config & PL080_CONFIG_ACTIVE) {
248 printk(KERN_ERR "%s: channel still active\n", __func__);
249 return -EFAULT;
250 }
251
252 config = readl(chan->regs + PL080S_CH_CONFIG);
253 config &= ~PL080_CONFIG_ENABLE;
254 writel(config, chan->regs + PL080S_CH_CONFIG);
255
256 return 0;
257}
258
259static inline void s3c64xx_dma_bufffdone(struct s3c2410_dma_chan *chan,
260 struct s3c64xx_dma_buff *buf,
261 enum s3c2410_dma_buffresult result)
262{
263 if (chan->callback_fn != NULL)
264 (chan->callback_fn)(chan, buf->pw, 0, result);
265}
266
267static void s3c64xx_dma_freebuff(struct s3c64xx_dma_buff *buff)
268{
269 dma_pool_free(dma_pool, buff->lli, buff->lli_dma);
270 kfree(buff);
271}
272
273static int s3c64xx_dma_flush(struct s3c2410_dma_chan *chan)
274{
275 struct s3c64xx_dma_buff *buff, *next;
276 u32 config;
277
278 dbg_showchan(chan);
279
280 pr_debug("%s: flushing channel\n", __func__);
281
282 config = readl(chan->regs + PL080S_CH_CONFIG);
283 config &= ~PL080_CONFIG_ENABLE;
284 writel(config, chan->regs + PL080S_CH_CONFIG);
285
286 /* dump all the buffers associated with this channel */
287
288 for (buff = chan->curr; buff != NULL; buff = next) {
289 next = buff->next;
290 pr_debug("%s: buff %p (next %p)\n", __func__, buff, buff->next);
291
292 s3c64xx_dma_bufffdone(chan, buff, S3C2410_RES_ABORT);
293 s3c64xx_dma_freebuff(buff);
294 }
295
296 chan->curr = chan->next = chan->end = NULL;
297
298 return 0;
299}
300
301int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op)
302{
303 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
304
305 WARN_ON(!chan);
306 if (!chan)
307 return -EINVAL;
308
309 switch (op) {
310 case S3C2410_DMAOP_START:
311 return s3c64xx_dma_start(chan);
312
313 case S3C2410_DMAOP_STOP:
314 return s3c64xx_dma_stop(chan);
315
316 case S3C2410_DMAOP_FLUSH:
317 return s3c64xx_dma_flush(chan);
318
319 /* belive PAUSE/RESUME are no-ops */
320 case S3C2410_DMAOP_PAUSE:
321 case S3C2410_DMAOP_RESUME:
322 case S3C2410_DMAOP_STARTED:
323 case S3C2410_DMAOP_TIMEOUT:
324 return 0;
325 }
326
327 return -ENOENT;
328}
329EXPORT_SYMBOL(s3c2410_dma_ctrl);
330
331/* s3c2410_dma_enque
332 *
333 */
334
335int s3c2410_dma_enqueue(unsigned int channel, void *id,
336 dma_addr_t data, int size)
337{
338 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
339 struct s3c64xx_dma_buff *next;
340 struct s3c64xx_dma_buff *buff;
341 struct pl080s_lli *lli;
342 int ret;
343
344 WARN_ON(!chan);
345 if (!chan)
346 return -EINVAL;
347
348 buff = kzalloc(sizeof(struct s3c64xx_dma_buff), GFP_KERNEL);
349 if (!buff) {
350 printk(KERN_ERR "%s: no memory for buffer\n", __func__);
351 return -ENOMEM;
352 }
353
354 lli = dma_pool_alloc(dma_pool, GFP_KERNEL, &buff->lli_dma);
355 if (!lli) {
356 printk(KERN_ERR "%s: no memory for lli\n", __func__);
357 ret = -ENOMEM;
358 goto err_buff;
359 }
360
361 pr_debug("%s: buff %p, dp %08x lli (%p, %08x) %d\n",
362 __func__, buff, data, lli, (u32)buff->lli_dma, size);
363
364 buff->lli = lli;
365 buff->pw = id;
366
367 s3c64xx_dma_fill_lli(chan, lli, data, size);
368
369 if ((next = chan->next) != NULL) {
370 struct s3c64xx_dma_buff *end = chan->end;
371 struct pl080s_lli *endlli = end->lli;
372
373 pr_debug("enquing onto channel\n");
374
375 end->next = buff;
376 endlli->next_lli = buff->lli_dma;
377
378 if (chan->flags & S3C2410_DMAF_CIRCULAR) {
379 struct s3c64xx_dma_buff *curr = chan->curr;
380 lli->next_lli = curr->lli_dma;
381 }
382
383 if (next == chan->curr) {
384 writel(buff->lli_dma, chan->regs + PL080_CH_LLI);
385 chan->next = buff;
386 }
387
388 show_lli(endlli);
389 chan->end = buff;
390 } else {
391 pr_debug("enquing onto empty channel\n");
392
393 chan->curr = buff;
394 chan->next = buff;
395 chan->end = buff;
396
397 s3c64xx_lli_to_regs(chan, lli);
398 }
399
400 show_lli(lli);
401
402 dbg_showchan(chan);
403 dbg_showbuffs(chan);
404 return 0;
405
406err_buff:
407 kfree(buff);
408 return ret;
409}
410
411EXPORT_SYMBOL(s3c2410_dma_enqueue);
412
413
414int s3c2410_dma_devconfig(int channel,
415 enum s3c2410_dmasrc source,
416 unsigned long devaddr)
417{
418 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
419 u32 peripheral;
420 u32 config = 0;
421
422 pr_debug("%s: channel %d, source %d, dev %08lx, chan %p\n",
423 __func__, channel, source, devaddr, chan);
424
425 WARN_ON(!chan);
426 if (!chan)
427 return -EINVAL;
428
429 peripheral = (chan->peripheral & 0xf);
430 chan->source = source;
431 chan->dev_addr = devaddr;
432
433 pr_debug("%s: peripheral %d\n", __func__, peripheral);
434
435 switch (source) {
436 case S3C2410_DMASRC_HW:
437 config = 2 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
438 config |= peripheral << PL080_CONFIG_SRC_SEL_SHIFT;
439 break;
440 case S3C2410_DMASRC_MEM:
441 config = 1 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
442 config |= peripheral << PL080_CONFIG_DST_SEL_SHIFT;
443 break;
444 default:
445 printk(KERN_ERR "%s: bad source\n", __func__);
446 return -EINVAL;
447 }
448
449 /* allow TC and ERR interrupts */
450 config |= PL080_CONFIG_TC_IRQ_MASK;
451 config |= PL080_CONFIG_ERR_IRQ_MASK;
452
453 pr_debug("%s: config %08x\n", __func__, config);
454
455 writel(config, chan->regs + PL080S_CH_CONFIG);
456
457 return 0;
458}
459EXPORT_SYMBOL(s3c2410_dma_devconfig);
460
461
462int s3c2410_dma_getposition(unsigned int channel,
463 dma_addr_t *src, dma_addr_t *dst)
464{
465 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
466
467 WARN_ON(!chan);
468 if (!chan)
469 return -EINVAL;
470
471 if (src != NULL)
472 *src = readl(chan->regs + PL080_CH_SRC_ADDR);
473
474 if (dst != NULL)
475 *dst = readl(chan->regs + PL080_CH_DST_ADDR);
476
477 return 0;
478}
479EXPORT_SYMBOL(s3c2410_dma_getposition);
480
481/* s3c2410_request_dma
482 *
483 * get control of an dma channel
484*/
485
486int s3c2410_dma_request(unsigned int channel,
487 struct s3c2410_dma_client *client,
488 void *dev)
489{
490 struct s3c2410_dma_chan *chan;
491 unsigned long flags;
492
493 pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
494 channel, client->name, dev);
495
496 local_irq_save(flags);
497
498 chan = s3c64xx_dma_map_channel(channel);
499 if (chan == NULL) {
500 local_irq_restore(flags);
501 return -EBUSY;
502 }
503
504 dbg_showchan(chan);
505
506 chan->client = client;
507 chan->in_use = 1;
508 chan->peripheral = channel;
509
510 local_irq_restore(flags);
511
512 /* need to setup */
513
514 pr_debug("%s: channel initialised, %p\n", __func__, chan);
515
516 return chan->number | DMACH_LOW_LEVEL;
517}
518
519EXPORT_SYMBOL(s3c2410_dma_request);
520
521/* s3c2410_dma_free
522 *
523 * release the given channel back to the system, will stop and flush
524 * any outstanding transfers, and ensure the channel is ready for the
525 * next claimant.
526 *
527 * Note, although a warning is currently printed if the freeing client
528 * info is not the same as the registrant's client info, the free is still
529 * allowed to go through.
530*/
531
532int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
533{
534 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
535 unsigned long flags;
536
537 if (chan == NULL)
538 return -EINVAL;
539
540 local_irq_save(flags);
541
542 if (chan->client != client) {
543 printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
544 channel, chan->client, client);
545 }
546
547 /* sort out stopping and freeing the channel */
548
549
550 chan->client = NULL;
551 chan->in_use = 0;
552
553 if (!(channel & DMACH_LOW_LEVEL))
554 s3c_dma_chan_map[channel] = NULL;
555
556 local_irq_restore(flags);
557
558 return 0;
559}
560
561EXPORT_SYMBOL(s3c2410_dma_free);
562
563
564static void s3c64xx_dma_tcirq(struct s3c64xx_dmac *dmac, int offs)
565{
566 struct s3c2410_dma_chan *chan = dmac->channels + offs;
567
568 /* note, we currently do not bother to work out which buffer
569 * or buffers have been completed since the last tc-irq. */
570
571 if (chan->callback_fn)
572 (chan->callback_fn)(chan, chan->curr->pw, 0, S3C2410_RES_OK);
573}
574
575static void s3c64xx_dma_errirq(struct s3c64xx_dmac *dmac, int offs)
576{
577 printk(KERN_DEBUG "%s: offs %d\n", __func__, offs);
578}
579
580static irqreturn_t s3c64xx_dma_irq(int irq, void *pw)
581{
582 struct s3c64xx_dmac *dmac = pw;
583 u32 tcstat, errstat;
584 u32 bit;
585 int offs;
586
587 tcstat = readl(dmac->regs + PL080_TC_STATUS);
588 errstat = readl(dmac->regs + PL080_ERR_STATUS);
589
590 for (offs = 0, bit = 1; offs < 8; offs++, bit <<= 1) {
591 if (tcstat & bit) {
592 writel(bit, dmac->regs + PL080_TC_CLEAR);
593 s3c64xx_dma_tcirq(dmac, offs);
594 }
595
596 if (errstat & bit) {
597 s3c64xx_dma_errirq(dmac, offs);
598 writel(bit, dmac->regs + PL080_ERR_CLEAR);
599 }
600 }
601
602 return IRQ_HANDLED;
603}
604
605static struct sysdev_class dma_sysclass = {
606 .name = "s3c64xx-dma",
607};
608
609static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
610 int irq, unsigned int base)
611{
612 struct s3c2410_dma_chan *chptr = &s3c2410_chans[chno];
613 struct s3c64xx_dmac *dmac;
614 char clkname[16];
615 void __iomem *regs;
616 void __iomem *regptr;
617 int err, ch;
618
619 dmac = kzalloc(sizeof(struct s3c64xx_dmac), GFP_KERNEL);
620 if (!dmac) {
621 printk(KERN_ERR "%s: failed to alloc mem\n", __func__);
622 return -ENOMEM;
623 }
624
625 dmac->sysdev.id = chno / 8;
626 dmac->sysdev.cls = &dma_sysclass;
627
628 err = sysdev_register(&dmac->sysdev);
629 if (err) {
630 printk(KERN_ERR "%s: failed to register sysdevice\n", __func__);
631 goto err_alloc;
632 }
633
634 regs = ioremap(base, 0x200);
635 if (!regs) {
636 printk(KERN_ERR "%s: failed to ioremap()\n", __func__);
637 err = -ENXIO;
638 goto err_dev;
639 }
640
641 snprintf(clkname, sizeof(clkname), "dma%d", dmac->sysdev.id);
642
643 dmac->clk = clk_get(NULL, clkname);
644 if (IS_ERR(dmac->clk)) {
645 printk(KERN_ERR "%s: failed to get clock %s\n", __func__, clkname);
646 err = PTR_ERR(dmac->clk);
647 goto err_map;
648 }
649
650 clk_enable(dmac->clk);
651
652 dmac->regs = regs;
653 dmac->chanbase = chbase;
654 dmac->channels = chptr;
655
656 err = request_irq(irq, s3c64xx_dma_irq, 0, "DMA", dmac);
657 if (err < 0) {
658 printk(KERN_ERR "%s: failed to get irq\n", __func__);
659 goto err_clk;
660 }
661
662 regptr = regs + PL080_Cx_BASE(0);
663
664 for (ch = 0; ch < 8; ch++, chno++, chptr++) {
665 printk(KERN_INFO "%s: registering DMA %d (%p)\n",
666 __func__, chno, regptr);
667
668 chptr->bit = 1 << ch;
669 chptr->number = chno;
670 chptr->dmac = dmac;
671 chptr->regs = regptr;
672 regptr += PL008_Cx_STRIDE;
673 }
674
675 /* for the moment, permanently enable the controller */
676 writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG);
677
678 printk(KERN_INFO "PL080: IRQ %d, at %p\n", irq, regs);
679
680 return 0;
681
682err_clk:
683 clk_disable(dmac->clk);
684 clk_put(dmac->clk);
685err_map:
686 iounmap(regs);
687err_dev:
688 sysdev_unregister(&dmac->sysdev);
689err_alloc:
690 kfree(dmac);
691 return err;
692}
693
694static int __init s3c64xx_dma_init(void)
695{
696 int ret;
697
698 printk(KERN_INFO "%s: Registering DMA channels\n", __func__);
699
700 dma_pool = dma_pool_create("DMA-LLI", NULL, 32, 16, 0);
701 if (!dma_pool) {
702 printk(KERN_ERR "%s: failed to create pool\n", __func__);
703 return -ENOMEM;
704 }
705
706 ret = sysdev_class_register(&dma_sysclass);
707 if (ret) {
708 printk(KERN_ERR "%s: failed to create sysclass\n", __func__);
709 return -ENOMEM;
710 }
711
712 /* Set all DMA configuration to be DMA, not SDMA */
713 writel(0xffffff, S3C_SYSREG(0x110));
714
715 /* Register standard DMA controlers */
716 s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000);
717 s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_DMA1, 0x75100000);
718
719 return 0;
720}
721
722arch_initcall(s3c64xx_dma_init);
diff --git a/arch/arm/plat-s3c64xx/include/plat/dma-plat.h b/arch/arm/plat-s3c64xx/include/plat/dma-plat.h
new file mode 100644
index 000000000000..0c30dd986725
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/dma-plat.h
@@ -0,0 +1,70 @@
1/* linux/arch/arm/plat-s3c64xx/include/plat/dma-plat.h
2 *
3 * Copyright 2009 Openmoko, Inc.
4 * Copyright 2009 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX DMA core
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
16
17struct s3c64xx_dma_buff;
18
19/** s3c64xx_dma_buff - S3C64XX DMA buffer descriptor
20 * @next: Pointer to next buffer in queue or ring.
21 * @pw: Client provided identifier
22 * @lli: Pointer to hardware descriptor this buffer is associated with.
23 * @lli_dma: Hardare address of the descriptor.
24 */
25struct s3c64xx_dma_buff {
26 struct s3c64xx_dma_buff *next;
27
28 void *pw;
29 struct pl080_lli *lli;
30 dma_addr_t lli_dma;
31};
32
33struct s3c64xx_dmac;
34
35struct s3c2410_dma_chan {
36 unsigned char number; /* number of this dma channel */
37 unsigned char in_use; /* channel allocated */
38 unsigned char bit; /* bit for enable/disable/etc */
39 unsigned char hw_width;
40 unsigned char peripheral;
41
42 unsigned int flags;
43 enum s3c2410_dmasrc source;
44
45
46 dma_addr_t dev_addr;
47
48 struct s3c2410_dma_client *client;
49 struct s3c64xx_dmac *dmac; /* pointer to controller */
50
51 void __iomem *regs;
52
53 /* cdriver callbacks */
54 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
55 s3c2410_dma_opfn_t op_fn; /* channel op callback */
56
57 /* buffer list and information */
58 struct s3c64xx_dma_buff *curr; /* current dma buffer */
59 struct s3c64xx_dma_buff *next; /* next buffer to load */
60 struct s3c64xx_dma_buff *end; /* end of queue */
61
62 /* note, when channel is running in circular mode, curr is the
63 * first buffer enqueued, end is the last and curr is where the
64 * last buffer-done event is set-at. The buffers are not freed
65 * and the last buffer hardware descriptor points back to the
66 * first.
67 */
68};
69
70#include <plat/dma-core.h>
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-08 11:07:43 -0400